commit d31d64eaf6e64896481e16a2be8e03cc9dbba792
Author: Xavier <magnum88@libertysurf.fr>
Date:   Wed Aug 24 08:14:49 2022 +0200

    first commit

diff --git a/NPR70_modem_v05_PCB/BOM_NPR70_v05_2021-09-17.csv b/NPR70_modem_v05_PCB/BOM_NPR70_v05_2021-09-17.csv
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diff --git a/NPR70_modem_v05_PCB/BOM_NPR70modem_v05.pdf b/NPR70_modem_v05_PCB/BOM_NPR70modem_v05.pdf
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index 0000000..d204bdf
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diff --git a/NPR70_modem_v05_PCB/H10015K_NPR-70_Modem_Kit_Assembly_Guide-Rev1.1.pdf b/NPR70_modem_v05_PCB/H10015K_NPR-70_Modem_Kit_Assembly_Guide-Rev1.1.pdf
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index 0000000..2eca00a
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diff --git a/NPR70_modem_v05_PCB/HSMM_Seminar2011-01-08.pdf b/NPR70_modem_v05_PCB/HSMM_Seminar2011-01-08.pdf
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index 0000000..c356fc1
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diff --git a/NPR70_modem_v05_PCB/IMG_20211127_101307.jpg b/NPR70_modem_v05_PCB/IMG_20211127_101307.jpg
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index 0000000..16489c2
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diff --git a/NPR70_modem_v05_PCB/IMG_20211127_101312.jpg b/NPR70_modem_v05_PCB/IMG_20211127_101312.jpg
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index 0000000..2c8aba2
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diff --git a/NPR70_modem_v05_PCB/License.txt b/NPR70_modem_v05_PCB/License.txt
new file mode 100755
index 0000000..a6af645
--- /dev/null
+++ b/NPR70_modem_v05_PCB/License.txt
@@ -0,0 +1,4 @@
+NPR 70 modem v05 PCB (New Packet Radio)
+(A GFSK data modem for ham radio 430-440MHz, at several hundreds of kbps)
+Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+Licensed under the TAPR Open Hardware License (www.tapr.org/OHL)
\ No newline at end of file
diff --git a/NPR70_modem_v05_PCB/NPR70_introduction_FR_v3.6.pdf b/NPR70_modem_v05_PCB/NPR70_introduction_FR_v3.6.pdf
new file mode 100755
index 0000000..339a0c4
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diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers.zip b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers.zip
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diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.cmp b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.cmp
new file mode 100755
index 0000000..bd4b601
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.cmp
@@ -0,0 +1,6870 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+%ADD10C,0.05543*%
+%ADD11R,0.10000X0.05000*%
+%ADD12R,0.10000X0.10000*%
+%ADD13C,0.05937*%
+%ADD14C,0.23000*%
+%ADD15C,0.09000*%
+%ADD16C,0.10500*%
+%ADD17C,0.09000*%
+%ADD18OC8,0.05000*%
+%ADD19C,0.05000*%
+%ADD20C,0.05600*%
+%ADD21OC8,0.05600*%
+%ADD22C,0.03569*%
+%ADD23C,0.01600*%
+%ADD24C,0.02400*%
+%ADD25C,0.05000*%
+%ADD26C,0.03200*%
+%ADD27C,0.04356*%
+%ADD28C,0.04000*%
+%ADD29C,0.00600*%
+%ADD30C,0.01200*%
+%ADD31C,0.00800*%
+%ADD32C,0.01000*%
+%ADD33C,0.06000*%
+D10*
+X0104028Y0047047D02*
+X0109572Y0047047D01*
+X0109572Y0057047D02*
+X0104028Y0057047D01*
+X0104028Y0067047D02*
+X0109572Y0067047D01*
+X0109572Y0077047D02*
+X0104028Y0077047D01*
+X0104028Y0087047D02*
+X0109572Y0087047D01*
+X0109572Y0097047D02*
+X0104028Y0097047D01*
+X0184028Y0097047D02*
+X0189572Y0097047D01*
+X0189572Y0087047D02*
+X0184028Y0087047D01*
+X0184028Y0077047D02*
+X0189572Y0077047D01*
+X0189572Y0067047D02*
+X0184028Y0067047D01*
+X0184028Y0057047D02*
+X0189572Y0057047D01*
+X0189572Y0047047D02*
+X0184028Y0047047D01*
+X0210550Y0049547D02*
+X0216093Y0049547D01*
+X0216093Y0059547D02*
+X0210550Y0059547D01*
+X0210550Y0069547D02*
+X0216093Y0069547D01*
+X0216093Y0079547D02*
+X0210550Y0079547D01*
+X0210550Y0089547D02*
+X0216093Y0089547D01*
+X0216093Y0099547D02*
+X0210550Y0099547D01*
+X0210550Y0109547D02*
+X0216093Y0109547D01*
+X0216093Y0119547D02*
+X0210550Y0119547D01*
+X0210550Y0129547D02*
+X0216093Y0129547D01*
+X0216093Y0139547D02*
+X0210550Y0139547D01*
+X0210550Y0149547D02*
+X0216093Y0149547D01*
+X0216093Y0159547D02*
+X0210550Y0159547D01*
+X0210550Y0169547D02*
+X0216093Y0169547D01*
+X0216093Y0179547D02*
+X0210550Y0179547D01*
+X0210550Y0189547D02*
+X0216093Y0189547D01*
+X0225278Y0219547D02*
+X0230822Y0219547D01*
+X0265007Y0189547D02*
+X0270550Y0189547D01*
+X0270550Y0179547D02*
+X0265007Y0179547D01*
+X0265007Y0169547D02*
+X0270550Y0169547D01*
+X0270550Y0159547D02*
+X0265007Y0159547D01*
+X0265007Y0149547D02*
+X0270550Y0149547D01*
+X0270550Y0139547D02*
+X0265007Y0139547D01*
+X0265007Y0129547D02*
+X0270550Y0129547D01*
+X0270550Y0119547D02*
+X0265007Y0119547D01*
+X0265007Y0109547D02*
+X0270550Y0109547D01*
+X0270550Y0099547D02*
+X0265007Y0099547D01*
+X0265007Y0089547D02*
+X0270550Y0089547D01*
+X0270550Y0079547D02*
+X0265007Y0079547D01*
+X0265007Y0069547D02*
+X0270550Y0069547D01*
+X0270550Y0059547D02*
+X0265007Y0059547D01*
+X0265007Y0049547D02*
+X0270550Y0049547D01*
+D11*
+X0283050Y0103287D03*
+X0283050Y0119035D03*
+X0283050Y0134783D03*
+X0283050Y0150531D03*
+X0283050Y0166279D03*
+X0283050Y0182027D03*
+X0283050Y0197775D03*
+X0283050Y0213523D03*
+X0361790Y0213523D03*
+X0361790Y0197775D03*
+X0361790Y0182027D03*
+X0361790Y0166279D03*
+X0361790Y0150531D03*
+X0361790Y0134783D03*
+X0361790Y0119035D03*
+X0361790Y0103287D03*
+D12*
+X0310609Y0083602D03*
+X0328326Y0233208D03*
+D13*
+X0343089Y0183027D02*
+X0343089Y0177090D01*
+X0343089Y0169247D02*
+X0343089Y0163310D01*
+X0101800Y0266578D02*
+X0101800Y0272515D01*
+X0091800Y0272515D02*
+X0091800Y0266578D01*
+X0081800Y0266578D02*
+X0081800Y0272515D01*
+X0081828Y0210787D02*
+X0087765Y0210787D01*
+X0026772Y0210787D02*
+X0020835Y0210787D01*
+X0020835Y0055275D02*
+X0026772Y0055275D01*
+X0056800Y0025015D02*
+X0056800Y0019078D01*
+X0066800Y0019078D02*
+X0066800Y0025015D01*
+X0076800Y0025015D02*
+X0076800Y0019078D01*
+X0081828Y0055275D02*
+X0087765Y0055275D01*
+D14*
+X0031800Y0029547D03*
+X0170550Y0139547D03*
+X0031800Y0262047D03*
+X0345550Y0262047D03*
+X0345550Y0029547D03*
+D15*
+X0275550Y0255797D03*
+D16*
+X0265511Y0265836D03*
+X0285589Y0265836D03*
+X0285589Y0245758D03*
+X0265511Y0245758D03*
+D17*
+X0072050Y0227047D02*
+X0063050Y0227047D01*
+X0045550Y0227047D02*
+X0036550Y0227047D01*
+D18*
+X0294300Y0044547D03*
+X0294300Y0035547D03*
+X0314300Y0035547D03*
+X0314300Y0044547D03*
+D19*
+X0304300Y0044547D03*
+X0304300Y0035547D03*
+X0324300Y0035547D03*
+X0324300Y0044547D03*
+D20*
+X0196800Y0243297D03*
+D21*
+X0196800Y0253297D03*
+X0206800Y0253297D03*
+X0216800Y0253297D03*
+X0226800Y0253297D03*
+X0236800Y0253297D03*
+X0236800Y0243297D03*
+X0226800Y0243297D03*
+X0216800Y0243297D03*
+X0206800Y0243297D03*
+D22*
+X0183050Y0257047D03*
+X0243050Y0232047D03*
+X0266800Y0233297D03*
+X0266800Y0223297D03*
+X0269300Y0212047D03*
+X0279300Y0205797D03*
+X0290550Y0205797D03*
+X0294300Y0213297D03*
+X0293050Y0220797D03*
+X0284300Y0222047D03*
+X0284300Y0233297D03*
+X0303050Y0254547D03*
+X0318050Y0264547D03*
+X0320550Y0240797D03*
+X0350550Y0233297D03*
+X0369300Y0238297D03*
+X0369300Y0272047D03*
+X0286800Y0190797D03*
+X0280550Y0172047D03*
+X0288050Y0158297D03*
+X0281800Y0155797D03*
+X0280550Y0129547D03*
+X0281800Y0113297D03*
+X0303050Y0122047D03*
+X0278050Y0094547D03*
+X0299300Y0089547D03*
+X0305550Y0092047D03*
+X0326800Y0089547D03*
+X0350550Y0089547D03*
+X0370550Y0094547D03*
+X0364300Y0112047D03*
+X0370550Y0125797D03*
+X0364300Y0128297D03*
+X0351800Y0125797D03*
+X0364300Y0143297D03*
+X0368050Y0158297D03*
+X0368050Y0174547D03*
+X0251800Y0204547D03*
+X0231800Y0204547D03*
+X0244300Y0179547D03*
+X0234300Y0153297D03*
+X0249300Y0147047D03*
+X0200550Y0112047D03*
+X0196800Y0164547D03*
+X0180550Y0173297D03*
+X0170550Y0173297D03*
+X0160550Y0173297D03*
+X0170550Y0189547D03*
+X0180550Y0186058D03*
+X0196800Y0198297D03*
+X0160550Y0197047D03*
+X0130550Y0125797D03*
+X0108050Y0124547D03*
+X0055550Y0164547D03*
+X0010550Y0173297D03*
+X0010550Y0099547D03*
+X0258050Y0033297D03*
+X0285550Y0054547D03*
+X0290550Y0062047D03*
+X0301800Y0065797D03*
+X0280550Y0077047D03*
+X0333050Y0059547D03*
+X0365550Y0067047D03*
+X0364300Y0019547D03*
+D23*
+X0301800Y0065797D02*
+X0299300Y0068297D01*
+X0299300Y0089547D01*
+X0291800Y0094547D02*
+X0291800Y0122047D01*
+X0303050Y0122047D01*
+X0291800Y0122047D02*
+X0291800Y0158297D01*
+X0291800Y0190797D01*
+X0286800Y0190797D01*
+X0291800Y0190797D02*
+X0291800Y0197775D01*
+X0266800Y0223297D02*
+X0240550Y0223297D01*
+X0243050Y0232047D01*
+X0285589Y0254547D02*
+X0303050Y0254547D01*
+X0220550Y0179547D02*
+X0210550Y0179547D01*
+X0220550Y0179547D02*
+X0234300Y0153297D01*
+X0243050Y0144547D02*
+X0203050Y0144547D01*
+X0198050Y0130797D02*
+X0205550Y0114547D01*
+X0241800Y0114547D01*
+X0243050Y0115797D01*
+X0243050Y0139547D01*
+X0243050Y0144547D01*
+X0243050Y0139547D02*
+X0243037Y0139716D01*
+X0243028Y0139885D01*
+X0243023Y0140054D01*
+X0243022Y0140224D01*
+X0243026Y0140393D01*
+X0243033Y0140563D01*
+X0243045Y0140732D01*
+X0243061Y0140900D01*
+X0243080Y0141068D01*
+X0243105Y0141236D01*
+X0243133Y0141403D01*
+X0243165Y0141570D01*
+X0243201Y0141735D01*
+X0243242Y0141900D01*
+X0243286Y0142063D01*
+X0243334Y0142225D01*
+X0243387Y0142387D01*
+X0243443Y0142546D01*
+X0243503Y0142705D01*
+X0243567Y0142862D01*
+X0243635Y0143017D01*
+X0243707Y0143170D01*
+X0243783Y0143322D01*
+X0243862Y0143472D01*
+X0243945Y0143620D01*
+X0244031Y0143765D01*
+X0244121Y0143909D01*
+X0244214Y0144050D01*
+X0244311Y0144189D01*
+X0244412Y0144326D01*
+X0244515Y0144460D01*
+X0244622Y0144591D01*
+X0244732Y0144720D01*
+X0244845Y0144846D01*
+X0244961Y0144969D01*
+X0245081Y0145090D01*
+X0245203Y0145207D01*
+X0245328Y0145321D01*
+X0245456Y0145433D01*
+X0245586Y0145541D01*
+X0245719Y0145646D01*
+X0245855Y0145747D01*
+X0245993Y0145845D01*
+X0246133Y0145940D01*
+X0246276Y0146032D01*
+X0246421Y0146119D01*
+X0246568Y0146204D01*
+X0246717Y0146284D01*
+X0246868Y0146361D01*
+X0247021Y0146434D01*
+X0247175Y0146504D01*
+X0247331Y0146569D01*
+X0247489Y0146631D01*
+X0247648Y0146689D01*
+X0247809Y0146743D01*
+X0247971Y0146793D01*
+X0248134Y0146839D01*
+X0248298Y0146881D01*
+X0248463Y0146918D01*
+X0248629Y0146952D01*
+X0248796Y0146982D01*
+X0248963Y0147008D01*
+X0249132Y0147029D01*
+X0249300Y0147047D01*
+X0280550Y0132283D02*
+X0280550Y0129547D01*
+X0280550Y0132283D02*
+X0283050Y0134783D01*
+X0283050Y0150531D02*
+X0281800Y0155797D01*
+X0283050Y0166279D02*
+X0280550Y0172047D01*
+X0283050Y0119035D02*
+X0283050Y0116166D01*
+X0281800Y0113297D01*
+X0283050Y0103287D02*
+X0283050Y0099547D01*
+X0278050Y0094547D01*
+X0270550Y0089547D02*
+X0273050Y0087047D01*
+X0283050Y0087047D01*
+X0290550Y0079547D01*
+X0290550Y0062047D01*
+X0285550Y0054547D02*
+X0281800Y0058297D01*
+X0280550Y0077047D01*
+X0291800Y0094547D02*
+X0310550Y0094547D01*
+X0310550Y0093297D01*
+X0310550Y0083661D01*
+X0310609Y0083602D01*
+X0320550Y0083602D01*
+X0350550Y0083602D02*
+X0355550Y0083602D01*
+X0364300Y0128297D02*
+X0361790Y0130807D01*
+X0361790Y0134783D01*
+X0364300Y0143297D02*
+X0361790Y0148307D01*
+X0361790Y0150531D01*
+X0243050Y0115797D02*
+X0243050Y0079547D01*
+X0200550Y0112047D02*
+X0181800Y0123297D01*
+X0130550Y0125797D01*
+X0108050Y0124547D02*
+X0108050Y0098297D01*
+X0106800Y0097047D01*
+X0170550Y0139547D02*
+X0186800Y0144547D01*
+X0185550Y0155797D02*
+X0185550Y0232047D01*
+X0163050Y0253297D01*
+X0124300Y0253297D02*
+X0096800Y0253297D01*
+X0093050Y0250797D01*
+X0092425Y0251422D01*
+X0091800Y0252047D01*
+X0160550Y0197047D02*
+X0160550Y0173297D01*
+X0170550Y0173297D02*
+X0170550Y0189547D01*
+X0180550Y0186058D02*
+X0180550Y0173297D01*
+X0196800Y0164547D02*
+X0196800Y0198297D01*
+D24*
+X0361790Y0119035D02*
+X0361790Y0112047D01*
+X0364300Y0112047D01*
+D25*
+X0361790Y0103287D02*
+X0350550Y0103287D01*
+X0350550Y0083602D01*
+X0310609Y0083602D01*
+X0333050Y0059547D02*
+X0333050Y0040797D01*
+X0344300Y0029547D01*
+X0345550Y0029547D01*
+X0364300Y0029547D01*
+X0364300Y0019547D01*
+X0345550Y0029547D02*
+X0349740Y0052197D01*
+X0355550Y0083602D01*
+X0350550Y0103287D02*
+X0350550Y0125797D01*
+X0350550Y0158297D01*
+X0350550Y0165797D01*
+X0350550Y0179547D01*
+X0350550Y0197047D01*
+X0361790Y0197047D01*
+X0361790Y0197775D01*
+X0350550Y0197047D02*
+X0350550Y0233208D01*
+X0328326Y0233208D01*
+X0343050Y0257933D01*
+X0345550Y0262047D01*
+X0318050Y0264547D01*
+X0285589Y0265836D01*
+X0285589Y0254547D01*
+X0285589Y0245758D01*
+X0295550Y0233297D02*
+X0317164Y0233297D01*
+X0328326Y0233208D01*
+X0295550Y0233297D02*
+X0295550Y0222047D01*
+X0295550Y0197775D01*
+X0291800Y0197775D01*
+X0283050Y0197775D01*
+X0279822Y0197775D01*
+X0279477Y0197779D01*
+X0279132Y0197792D01*
+X0278788Y0197812D01*
+X0278445Y0197842D01*
+X0278102Y0197879D01*
+X0277760Y0197925D01*
+X0277419Y0197979D01*
+X0277080Y0198041D01*
+X0276742Y0198111D01*
+X0276406Y0198190D01*
+X0276073Y0198276D01*
+X0275741Y0198371D01*
+X0275412Y0198474D01*
+X0275085Y0198584D01*
+X0274761Y0198702D01*
+X0274440Y0198829D01*
+X0274122Y0198963D01*
+X0273808Y0199104D01*
+X0273497Y0199253D01*
+X0273189Y0199410D01*
+X0272886Y0199574D01*
+X0272587Y0199745D01*
+X0272292Y0199923D01*
+X0272001Y0200109D01*
+X0271715Y0200301D01*
+X0271433Y0200501D01*
+X0271157Y0200707D01*
+X0270885Y0200919D01*
+X0270619Y0201139D01*
+X0270358Y0201364D01*
+X0270103Y0201596D01*
+X0269853Y0201834D01*
+X0269609Y0202078D01*
+X0269371Y0202328D01*
+X0269139Y0202583D01*
+X0268914Y0202844D01*
+X0268694Y0203110D01*
+X0268482Y0203382D01*
+X0268276Y0203658D01*
+X0268076Y0203940D01*
+X0267884Y0204226D01*
+X0267698Y0204517D01*
+X0267520Y0204812D01*
+X0267349Y0205111D01*
+X0267185Y0205414D01*
+X0267028Y0205722D01*
+X0266879Y0206033D01*
+X0266738Y0206347D01*
+X0266604Y0206665D01*
+X0266477Y0206986D01*
+X0266359Y0207310D01*
+X0266249Y0207637D01*
+X0266146Y0207966D01*
+X0266051Y0208298D01*
+X0265965Y0208631D01*
+X0265886Y0208967D01*
+X0265816Y0209305D01*
+X0265754Y0209644D01*
+X0265700Y0209985D01*
+X0265654Y0210327D01*
+X0265617Y0210670D01*
+X0265587Y0211013D01*
+X0265567Y0211357D01*
+X0265554Y0211702D01*
+X0265550Y0212047D01*
+X0265550Y0244469D01*
+X0265590Y0244514D01*
+X0265626Y0244561D01*
+X0265659Y0244610D01*
+X0265689Y0244662D01*
+X0265716Y0244716D01*
+X0265739Y0244771D01*
+X0265758Y0244827D01*
+X0265774Y0244885D01*
+X0265785Y0244943D01*
+X0265793Y0245002D01*
+X0265797Y0245062D01*
+X0265798Y0245122D01*
+X0265794Y0245181D01*
+X0265786Y0245240D01*
+X0265775Y0245299D01*
+X0265759Y0245357D01*
+X0265740Y0245413D01*
+X0265718Y0245468D01*
+X0265691Y0245522D01*
+X0265662Y0245574D01*
+X0265629Y0245623D01*
+X0265592Y0245671D01*
+X0265553Y0245716D01*
+X0265511Y0245758D01*
+X0265511Y0265836D01*
+X0238050Y0264586D01*
+X0238050Y0262047D01*
+X0243050Y0232047D02*
+X0231800Y0215797D01*
+X0231680Y0215799D01*
+X0231560Y0215805D01*
+X0231440Y0215814D01*
+X0231320Y0215828D01*
+X0231202Y0215845D01*
+X0231083Y0215866D01*
+X0230966Y0215891D01*
+X0230849Y0215920D01*
+X0230733Y0215952D01*
+X0230618Y0215988D01*
+X0230505Y0216028D01*
+X0230393Y0216071D01*
+X0230282Y0216118D01*
+X0230173Y0216168D01*
+X0230065Y0216222D01*
+X0229960Y0216280D01*
+X0229856Y0216340D01*
+X0229754Y0216404D01*
+X0229655Y0216471D01*
+X0229557Y0216542D01*
+X0229462Y0216615D01*
+X0229369Y0216692D01*
+X0229279Y0216771D01*
+X0229191Y0216853D01*
+X0229106Y0216938D01*
+X0229024Y0217026D01*
+X0228945Y0217116D01*
+X0228868Y0217209D01*
+X0228795Y0217304D01*
+X0228724Y0217402D01*
+X0228657Y0217501D01*
+X0228593Y0217603D01*
+X0228533Y0217707D01*
+X0228475Y0217812D01*
+X0228421Y0217920D01*
+X0228371Y0218029D01*
+X0228324Y0218140D01*
+X0228281Y0218252D01*
+X0228241Y0218365D01*
+X0228205Y0218480D01*
+X0228173Y0218596D01*
+X0228144Y0218713D01*
+X0228119Y0218830D01*
+X0228098Y0218949D01*
+X0228081Y0219067D01*
+X0228067Y0219187D01*
+X0228058Y0219307D01*
+X0228052Y0219427D01*
+X0228050Y0219547D01*
+X0183050Y0257047D02*
+X0186800Y0262047D01*
+X0175550Y0262047D01*
+X0170433Y0258464D01*
+X0163050Y0253297D01*
+X0124300Y0253297D01*
+X0146800Y0234547D02*
+X0101800Y0220797D01*
+X0048050Y0262047D02*
+X0031800Y0262047D01*
+X0031800Y0244547D01*
+X0045550Y0227047D01*
+X0020835Y0210787D02*
+X0014585Y0138297D01*
+X0018050Y0138297D01*
+X0014585Y0138297D02*
+X0014585Y0098297D01*
+X0053050Y0098297D01*
+X0014585Y0098297D02*
+X0020835Y0055275D01*
+X0021006Y0045679D01*
+X0031800Y0029547D01*
+X0046800Y0029547D01*
+X0050550Y0033297D01*
+X0061800Y0033297D01*
+X0066800Y0028297D01*
+X0066800Y0022047D01*
+X0066800Y0028297D02*
+X0066800Y0040797D01*
+X0041800Y0040797D01*
+X0030550Y0029547D01*
+X0031800Y0029547D01*
+X0108050Y0043297D02*
+X0109300Y0042047D01*
+X0119300Y0042047D01*
+X0120550Y0035797D01*
+X0123050Y0043297D01*
+X0186800Y0047047D01*
+X0198050Y0130797D02*
+X0170550Y0139547D01*
+X0185550Y0155797D01*
+X0186800Y0144547D02*
+X0203050Y0144547D01*
+X0284300Y0222047D02*
+X0295550Y0222047D01*
+X0361790Y0222047D02*
+X0361790Y0213523D01*
+X0361790Y0222047D02*
+X0364300Y0229547D01*
+X0364300Y0222047D01*
+X0284300Y0222047D02*
+X0285589Y0245758D01*
+D26*
+X0320550Y0240797D02*
+X0320737Y0240797D01*
+X0328326Y0233208D01*
+X0345550Y0262047D02*
+X0354300Y0262047D01*
+X0369300Y0272047D01*
+X0361790Y0197775D02*
+X0361790Y0192047D01*
+X0361800Y0192047D01*
+X0350550Y0179547D02*
+X0343601Y0179547D01*
+X0343089Y0180059D01*
+X0343089Y0166279D01*
+X0343572Y0165797D01*
+X0350550Y0165797D01*
+X0310550Y0093297D02*
+X0309300Y0092047D01*
+X0305550Y0092047D01*
+X0270550Y0079547D02*
+X0243050Y0079547D01*
+X0243050Y0059547D01*
+X0210550Y0059547D01*
+X0249300Y0147047D02*
+X0244300Y0179547D01*
+X0238050Y0262047D02*
+X0186800Y0262047D01*
+X0092425Y0251422D02*
+X0083675Y0253922D01*
+X0045550Y0227047D02*
+X0024595Y0228297D01*
+X0024340Y0228128D01*
+X0024089Y0227953D01*
+X0023842Y0227771D01*
+X0023600Y0227584D01*
+X0023363Y0227391D01*
+X0023130Y0227192D01*
+X0022902Y0226988D01*
+X0022680Y0226778D01*
+X0022462Y0226563D01*
+X0022249Y0226343D01*
+X0022042Y0226117D01*
+X0021841Y0225887D01*
+X0021645Y0225652D01*
+X0021455Y0225412D01*
+X0021270Y0225168D01*
+X0021092Y0224919D01*
+X0020919Y0224667D01*
+X0020753Y0224410D01*
+X0020593Y0224149D01*
+X0020440Y0223884D01*
+X0020293Y0223616D01*
+X0020152Y0223344D01*
+X0020018Y0223069D01*
+X0019891Y0222790D01*
+X0019770Y0222509D01*
+X0019657Y0222225D01*
+X0019550Y0221938D01*
+X0019450Y0221649D01*
+X0019357Y0221357D01*
+X0019271Y0221063D01*
+X0019193Y0220768D01*
+X0019121Y0220470D01*
+X0019057Y0220171D01*
+X0019000Y0219870D01*
+X0018950Y0219568D01*
+X0018908Y0219265D01*
+X0018873Y0218961D01*
+X0018845Y0218656D01*
+X0018825Y0218351D01*
+X0018812Y0218045D01*
+X0018806Y0217739D01*
+X0018808Y0217433D01*
+X0018817Y0217127D01*
+X0018834Y0216822D01*
+X0018858Y0216517D01*
+X0018889Y0216212D01*
+X0018928Y0215909D01*
+X0018974Y0215606D01*
+X0019027Y0215305D01*
+X0019088Y0215005D01*
+X0019156Y0214706D01*
+X0019231Y0214410D01*
+X0019313Y0214115D01*
+X0019402Y0213822D01*
+X0019498Y0213532D01*
+X0019602Y0213244D01*
+X0019712Y0212958D01*
+X0019829Y0212675D01*
+X0019953Y0212396D01*
+X0020084Y0212119D01*
+X0020221Y0211845D01*
+X0020365Y0211575D01*
+X0020515Y0211309D01*
+X0020672Y0211046D01*
+X0020835Y0210787D01*
+X0346800Y0087352D02*
+X0350550Y0083602D01*
+X0346800Y0087352D02*
+X0350550Y0089547D01*
+D27*
+X0239300Y0020797D03*
+X0186800Y0020797D03*
+X0120550Y0035797D03*
+X0053050Y0098297D03*
+X0018050Y0138297D03*
+X0119300Y0165797D03*
+X0131800Y0199547D03*
+X0101800Y0220797D03*
+X0133050Y0255797D03*
+X0146800Y0234547D03*
+X0166800Y0117047D03*
+X0361800Y0192047D03*
+X0364300Y0222047D03*
+X0364300Y0229547D03*
+D28*
+X0101800Y0220797D02*
+X0096800Y0253297D01*
+D29*
+X0279300Y0205797D02*
+X0279822Y0197775D01*
+X0291800Y0197775D02*
+X0290550Y0205797D01*
+X0291800Y0158297D02*
+X0288050Y0158297D01*
+X0350550Y0158297D02*
+X0368050Y0158297D01*
+D30*
+X0001800Y0275797D02*
+X0001800Y0017047D01*
+X0052047Y0017047D01*
+X0051631Y0018050D01*
+X0051631Y0026043D01*
+X0052418Y0027943D01*
+X0053872Y0029397D01*
+X0055772Y0030184D01*
+X0057828Y0030184D01*
+X0059728Y0029397D01*
+X0061182Y0027943D01*
+X0061968Y0026043D01*
+X0061968Y0018050D01*
+X0061553Y0017047D01*
+X0062708Y0017047D01*
+X0062566Y0017324D01*
+X0062344Y0018008D01*
+X0062231Y0018719D01*
+X0062231Y0021662D01*
+X0066416Y0021662D01*
+X0066416Y0022431D01*
+X0066416Y0029580D01*
+X0065730Y0029471D01*
+X0065046Y0029249D01*
+X0064406Y0028923D01*
+X0063824Y0028500D01*
+X0063315Y0027991D01*
+X0062893Y0027410D01*
+X0062566Y0026769D01*
+X0062344Y0026085D01*
+X0062231Y0025375D01*
+X0062231Y0022431D01*
+X0066416Y0022431D01*
+X0067184Y0022431D01*
+X0067184Y0029580D01*
+X0067870Y0029471D01*
+X0068554Y0029249D01*
+X0069194Y0028923D01*
+X0069776Y0028500D01*
+X0070285Y0027991D01*
+X0070707Y0027410D01*
+X0071034Y0026769D01*
+X0071256Y0026085D01*
+X0071368Y0025375D01*
+X0071368Y0022431D01*
+X0067184Y0022431D01*
+X0067184Y0021662D01*
+X0071368Y0021662D01*
+X0071368Y0018719D01*
+X0071256Y0018008D01*
+X0071034Y0017324D01*
+X0070892Y0017047D01*
+X0072047Y0017047D01*
+X0071631Y0018050D01*
+X0071631Y0026043D01*
+X0072418Y0027943D01*
+X0073872Y0029397D01*
+X0075772Y0030184D01*
+X0077828Y0030184D01*
+X0079728Y0029397D01*
+X0081182Y0027943D01*
+X0081968Y0026043D01*
+X0081968Y0018050D01*
+X0081553Y0017047D01*
+X0378050Y0017047D01*
+X0378050Y0275797D01*
+X0105828Y0275797D01*
+X0106182Y0275443D01*
+X0106968Y0273543D01*
+X0106968Y0265550D01*
+X0106182Y0263650D01*
+X0104728Y0262197D01*
+X0102828Y0261410D01*
+X0100772Y0261410D01*
+X0098872Y0262197D01*
+X0097418Y0263650D01*
+X0096631Y0265550D01*
+X0096631Y0273543D01*
+X0097418Y0275443D01*
+X0097772Y0275797D01*
+X0094979Y0275797D01*
+X0095285Y0275491D01*
+X0095707Y0274910D01*
+X0096034Y0274269D01*
+X0096256Y0273585D01*
+X0096368Y0272875D01*
+X0096368Y0269931D01*
+X0092184Y0269931D01*
+X0092184Y0269162D01*
+X0092184Y0262014D01*
+X0092870Y0262122D01*
+X0093554Y0262344D01*
+X0094194Y0262671D01*
+X0094776Y0263094D01*
+X0095285Y0263602D01*
+X0095707Y0264184D01*
+X0096034Y0264824D01*
+X0096256Y0265508D01*
+X0096368Y0266219D01*
+X0096368Y0269162D01*
+X0092184Y0269162D01*
+X0091416Y0269162D01*
+X0091416Y0262014D01*
+X0090730Y0262122D01*
+X0090046Y0262344D01*
+X0089406Y0262671D01*
+X0088824Y0263094D01*
+X0088315Y0263602D01*
+X0087893Y0264184D01*
+X0087566Y0264824D01*
+X0087344Y0265508D01*
+X0087231Y0266219D01*
+X0087231Y0269162D01*
+X0091416Y0269162D01*
+X0091416Y0269931D01*
+X0087231Y0269931D01*
+X0087231Y0272875D01*
+X0087344Y0273585D01*
+X0087566Y0274269D01*
+X0087893Y0274910D01*
+X0088315Y0275491D01*
+X0088621Y0275797D01*
+X0085828Y0275797D01*
+X0086182Y0275443D01*
+X0086968Y0273543D01*
+X0086968Y0265550D01*
+X0086182Y0263650D01*
+X0084728Y0262197D01*
+X0082828Y0261410D01*
+X0080772Y0261410D01*
+X0078872Y0262197D01*
+X0077418Y0263650D01*
+X0076631Y0265550D01*
+X0076631Y0273543D01*
+X0077418Y0275443D01*
+X0077772Y0275797D01*
+X0001800Y0275797D01*
+X0001800Y0275719D02*
+X0077695Y0275719D01*
+X0077036Y0274521D02*
+X0001800Y0274521D01*
+X0001800Y0273322D02*
+X0076631Y0273322D01*
+X0076631Y0272124D02*
+X0001800Y0272124D01*
+X0001800Y0270925D02*
+X0076631Y0270925D01*
+X0076631Y0269727D02*
+X0001800Y0269727D01*
+X0001800Y0268528D02*
+X0076631Y0268528D01*
+X0076631Y0267330D02*
+X0001800Y0267330D01*
+X0001800Y0266131D02*
+X0076631Y0266131D01*
+X0076887Y0264933D02*
+X0001800Y0264933D01*
+X0001800Y0263734D02*
+X0077384Y0263734D01*
+X0078533Y0262536D02*
+X0001800Y0262536D01*
+X0001800Y0261337D02*
+X0260329Y0261337D01*
+X0260350Y0261309D02*
+X0260985Y0260675D01*
+X0261697Y0260128D01*
+X0262475Y0259679D01*
+X0263304Y0259335D01*
+X0264172Y0259103D01*
+X0264911Y0259006D01*
+X0264911Y0265236D01*
+X0258681Y0265236D01*
+X0258778Y0264496D01*
+X0259011Y0263629D01*
+X0259354Y0262799D01*
+X0259803Y0262022D01*
+X0260350Y0261309D01*
+X0259507Y0262536D02*
+X0105067Y0262536D01*
+X0106216Y0263734D02*
+X0258982Y0263734D01*
+X0258721Y0264933D02*
+X0106713Y0264933D01*
+X0106968Y0266131D02*
+X0264911Y0266131D01*
+X0264911Y0266436D02*
+X0264911Y0265236D01*
+X0266111Y0265236D01*
+X0266111Y0266436D01*
+X0264911Y0266436D01*
+X0264911Y0272666D01*
+X0264172Y0272568D01*
+X0263304Y0272336D01*
+X0262475Y0271992D01*
+X0261697Y0271543D01*
+X0260985Y0270997D01*
+X0260350Y0270362D01*
+X0259803Y0269649D01*
+X0259354Y0268872D01*
+X0259011Y0268042D01*
+X0258778Y0267175D01*
+X0258681Y0266436D01*
+X0264911Y0266436D01*
+X0264911Y0267330D02*
+X0266111Y0267330D01*
+X0266111Y0266436D02*
+X0266111Y0272666D01*
+X0266850Y0272568D01*
+X0267718Y0272336D01*
+X0268547Y0271992D01*
+X0269325Y0271543D01*
+X0270037Y0270997D01*
+X0270672Y0270362D01*
+X0271219Y0269649D01*
+X0271668Y0268872D01*
+X0272011Y0268042D01*
+X0272244Y0267175D01*
+X0272341Y0266436D01*
+X0266111Y0266436D01*
+X0266111Y0266131D02*
+X0284989Y0266131D01*
+X0284989Y0266436D02*
+X0284989Y0265236D01*
+X0278759Y0265236D01*
+X0278856Y0264496D01*
+X0279089Y0263629D01*
+X0279432Y0262799D01*
+X0279881Y0262022D01*
+X0280428Y0261309D01*
+X0281063Y0260675D01*
+X0281775Y0260128D01*
+X0282553Y0259679D01*
+X0283382Y0259335D01*
+X0284250Y0259103D01*
+X0284989Y0259006D01*
+X0284989Y0265236D01*
+X0286189Y0265236D01*
+X0286189Y0266436D01*
+X0284989Y0266436D01*
+X0284989Y0272666D01*
+X0284250Y0272568D01*
+X0283382Y0272336D01*
+X0282553Y0271992D01*
+X0281775Y0271543D01*
+X0281063Y0270997D01*
+X0280428Y0270362D01*
+X0279881Y0269649D01*
+X0279432Y0268872D01*
+X0279089Y0268042D01*
+X0278856Y0267175D01*
+X0278759Y0266436D01*
+X0284989Y0266436D01*
+X0284989Y0267330D02*
+X0286189Y0267330D01*
+X0286189Y0266436D02*
+X0286189Y0272666D01*
+X0286928Y0272568D01*
+X0287796Y0272336D01*
+X0288625Y0271992D01*
+X0289403Y0271543D01*
+X0290115Y0270997D01*
+X0290750Y0270362D01*
+X0291297Y0269649D01*
+X0291746Y0268872D01*
+X0292089Y0268042D01*
+X0292322Y0267175D01*
+X0292419Y0266436D01*
+X0286189Y0266436D01*
+X0286189Y0266131D02*
+X0378050Y0266131D01*
+X0378050Y0264933D02*
+X0292379Y0264933D01*
+X0292419Y0265236D02*
+X0286189Y0265236D01*
+X0286189Y0259006D01*
+X0286928Y0259103D01*
+X0287796Y0259335D01*
+X0288625Y0259679D01*
+X0289403Y0260128D01*
+X0290115Y0260675D01*
+X0290750Y0261309D01*
+X0291297Y0262022D01*
+X0291746Y0262799D01*
+X0292089Y0263629D01*
+X0292322Y0264496D01*
+X0292419Y0265236D01*
+X0292117Y0263734D02*
+X0378050Y0263734D01*
+X0378050Y0262536D02*
+X0291593Y0262536D01*
+X0290771Y0261337D02*
+X0378050Y0261337D01*
+X0378050Y0260139D02*
+X0289417Y0260139D01*
+X0286189Y0260139D02*
+X0284989Y0260139D01*
+X0284989Y0261337D02*
+X0286189Y0261337D01*
+X0286189Y0262536D02*
+X0284989Y0262536D01*
+X0284989Y0263734D02*
+X0286189Y0263734D01*
+X0286189Y0264933D02*
+X0284989Y0264933D01*
+X0284989Y0268528D02*
+X0286189Y0268528D01*
+X0286189Y0269727D02*
+X0284989Y0269727D01*
+X0284989Y0270925D02*
+X0286189Y0270925D01*
+X0286189Y0272124D02*
+X0284989Y0272124D01*
+X0282870Y0272124D02*
+X0268230Y0272124D01*
+X0266111Y0272124D02*
+X0264911Y0272124D01*
+X0264911Y0270925D02*
+X0266111Y0270925D01*
+X0266111Y0269727D02*
+X0264911Y0269727D01*
+X0264911Y0268528D02*
+X0266111Y0268528D01*
+X0266111Y0265236D02*
+X0272341Y0265236D01*
+X0272244Y0264496D01*
+X0272011Y0263629D01*
+X0271668Y0262799D01*
+X0271219Y0262022D01*
+X0270672Y0261309D01*
+X0270037Y0260675D01*
+X0269325Y0260128D01*
+X0268547Y0259679D01*
+X0267718Y0259335D01*
+X0266850Y0259103D01*
+X0266111Y0259006D01*
+X0266111Y0265236D01*
+X0266111Y0264933D02*
+X0264911Y0264933D01*
+X0264911Y0263734D02*
+X0266111Y0263734D01*
+X0266111Y0262536D02*
+X0264911Y0262536D01*
+X0264911Y0261337D02*
+X0266111Y0261337D01*
+X0266111Y0260139D02*
+X0264911Y0260139D01*
+X0261683Y0260139D02*
+X0001800Y0260139D01*
+X0001800Y0258940D02*
+X0269600Y0258940D01*
+X0269870Y0259592D02*
+X0268850Y0257129D01*
+X0268850Y0254464D01*
+X0269870Y0252001D01*
+X0270350Y0251521D01*
+X0270350Y0250606D01*
+X0270037Y0250919D01*
+X0269325Y0251465D01*
+X0268547Y0251914D01*
+X0267718Y0252258D01*
+X0266850Y0252491D01*
+X0266111Y0252588D01*
+X0266111Y0246358D01*
+X0264911Y0246358D01*
+X0264911Y0252588D01*
+X0264172Y0252491D01*
+X0263304Y0252258D01*
+X0262475Y0251914D01*
+X0261697Y0251465D01*
+X0260985Y0250919D01*
+X0260350Y0250284D01*
+X0259803Y0249572D01*
+X0259354Y0248794D01*
+X0259011Y0247964D01*
+X0258778Y0247097D01*
+X0258681Y0246358D01*
+X0264911Y0246358D01*
+X0264911Y0245158D01*
+X0258681Y0245158D01*
+X0258778Y0244418D01*
+X0259011Y0243551D01*
+X0259354Y0242722D01*
+X0259803Y0241944D01*
+X0260350Y0241231D01*
+X0260985Y0240597D01*
+X0261697Y0240050D01*
+X0262475Y0239601D01*
+X0263304Y0239257D01*
+X0264172Y0239025D01*
+X0264911Y0238928D01*
+X0264911Y0245158D01*
+X0266111Y0245158D01*
+X0266111Y0238928D01*
+X0266850Y0239025D01*
+X0267718Y0239257D01*
+X0268547Y0239601D01*
+X0269325Y0240050D01*
+X0270037Y0240597D01*
+X0270350Y0240909D01*
+X0270350Y0217769D01*
+X0271449Y0214388D01*
+X0273538Y0211511D01*
+X0273538Y0211511D01*
+X0273538Y0211511D01*
+X0276415Y0209422D01*
+X0276600Y0209361D01*
+X0277139Y0208823D01*
+X0278257Y0208823D01*
+X0279796Y0208323D01*
+X0284084Y0208323D01*
+X0285291Y0208823D01*
+X0288961Y0208823D01*
+X0290250Y0210112D01*
+X0290250Y0216934D01*
+X0288961Y0218223D01*
+X0285291Y0218223D01*
+X0284084Y0218723D01*
+X0281574Y0218723D01*
+X0281445Y0218733D01*
+X0281200Y0218813D01*
+X0280991Y0218964D01*
+X0280840Y0219173D01*
+X0280760Y0219418D01*
+X0280750Y0219547D01*
+X0280750Y0240909D01*
+X0281063Y0240597D01*
+X0281775Y0240050D01*
+X0282553Y0239601D01*
+X0283382Y0239257D01*
+X0284250Y0239025D01*
+X0284989Y0238928D01*
+X0284989Y0245158D01*
+X0286189Y0245158D01*
+X0286189Y0246358D01*
+X0284989Y0246358D01*
+X0284989Y0252588D01*
+X0284250Y0252491D01*
+X0283382Y0252258D01*
+X0282553Y0251914D01*
+X0281775Y0251465D01*
+X0281063Y0250919D01*
+X0280750Y0250606D01*
+X0280750Y0251521D01*
+X0281230Y0252001D01*
+X0282250Y0254464D01*
+X0282250Y0257129D01*
+X0281230Y0259592D01*
+X0279345Y0261477D01*
+X0276883Y0262497D01*
+X0274217Y0262497D01*
+X0271755Y0261477D01*
+X0269870Y0259592D01*
+X0269339Y0260139D02*
+X0270417Y0260139D01*
+X0270693Y0261337D02*
+X0271615Y0261337D01*
+X0271515Y0262536D02*
+X0279585Y0262536D01*
+X0279485Y0261337D02*
+X0280407Y0261337D01*
+X0280683Y0260139D02*
+X0281761Y0260139D01*
+X0281500Y0258940D02*
+X0378050Y0258940D01*
+X0378050Y0257742D02*
+X0281996Y0257742D01*
+X0282250Y0256543D02*
+X0378050Y0256543D01*
+X0378050Y0255344D02*
+X0282250Y0255344D01*
+X0282118Y0254146D02*
+X0378050Y0254146D01*
+X0378050Y0252947D02*
+X0281622Y0252947D01*
+X0280977Y0251749D02*
+X0282266Y0251749D01*
+X0284989Y0251749D02*
+X0286189Y0251749D01*
+X0286189Y0252588D02*
+X0286189Y0246358D01*
+X0292419Y0246358D01*
+X0292322Y0247097D01*
+X0292089Y0247964D01*
+X0291746Y0248794D01*
+X0291297Y0249572D01*
+X0290750Y0250284D01*
+X0290115Y0250919D01*
+X0289403Y0251465D01*
+X0288625Y0251914D01*
+X0287796Y0252258D01*
+X0286928Y0252491D01*
+X0286189Y0252588D01*
+X0286189Y0250550D02*
+X0284989Y0250550D01*
+X0284989Y0249352D02*
+X0286189Y0249352D01*
+X0286189Y0248153D02*
+X0284989Y0248153D01*
+X0284989Y0246955D02*
+X0286189Y0246955D01*
+X0286189Y0245756D02*
+X0378050Y0245756D01*
+X0378050Y0244558D02*
+X0292340Y0244558D01*
+X0292322Y0244418D02*
+X0292419Y0245158D01*
+X0286189Y0245158D01*
+X0286189Y0238928D01*
+X0286928Y0239025D01*
+X0287796Y0239257D01*
+X0288625Y0239601D01*
+X0289403Y0240050D01*
+X0290115Y0240597D01*
+X0290750Y0241231D01*
+X0291297Y0241944D01*
+X0291746Y0242722D01*
+X0292089Y0243551D01*
+X0292322Y0244418D01*
+X0292010Y0243359D02*
+X0378050Y0243359D01*
+X0378050Y0242161D02*
+X0291422Y0242161D01*
+X0290481Y0240962D02*
+X0378050Y0240962D01*
+X0378050Y0239764D02*
+X0333701Y0239764D01*
+X0333536Y0239808D02*
+X0333943Y0239699D01*
+X0334308Y0239488D01*
+X0334606Y0239191D01*
+X0334817Y0238826D01*
+X0334926Y0238419D01*
+X0334926Y0233808D01*
+X0328926Y0233808D01*
+X0328926Y0232608D01*
+X0334926Y0232608D01*
+X0334926Y0228397D01*
+X0344817Y0228397D01*
+X0345773Y0228001D01*
+X0346504Y0227269D01*
+X0346900Y0226314D01*
+X0346900Y0191166D01*
+X0346941Y0191024D01*
+X0346900Y0190653D01*
+X0346900Y0190280D01*
+X0346843Y0190143D01*
+X0346827Y0189996D01*
+X0346647Y0189669D01*
+X0346504Y0189324D01*
+X0346399Y0189219D01*
+X0346328Y0189090D01*
+X0346037Y0188856D01*
+X0345773Y0188593D01*
+X0345636Y0188536D01*
+X0340650Y0184547D01*
+X0340650Y0162046D01*
+X0345636Y0158058D01*
+X0345773Y0158001D01*
+X0346037Y0157737D01*
+X0346328Y0157504D01*
+X0346399Y0157374D01*
+X0346504Y0157269D01*
+X0346647Y0156925D01*
+X0346827Y0156598D01*
+X0346843Y0156451D01*
+X0346900Y0156314D01*
+X0346900Y0155941D01*
+X0346941Y0155570D01*
+X0346900Y0155428D01*
+X0346900Y0097780D01*
+X0346504Y0096824D01*
+X0345773Y0096093D01*
+X0344817Y0095697D01*
+X0307533Y0095697D01*
+X0306577Y0096093D01*
+X0305846Y0096824D01*
+X0305450Y0097780D01*
+X0305450Y0126235D01*
+X0294796Y0141624D01*
+X0294596Y0141824D01*
+X0294504Y0142045D01*
+X0294368Y0142242D01*
+X0294308Y0142518D01*
+X0294200Y0142780D01*
+X0294200Y0143019D01*
+X0294149Y0143253D01*
+X0294200Y0143531D01*
+X0294200Y0192564D01*
+X0294596Y0193519D01*
+X0297950Y0196874D01*
+X0297950Y0226314D01*
+X0298346Y0227269D01*
+X0299077Y0228001D01*
+X0300033Y0228397D01*
+X0321726Y0228397D01*
+X0321726Y0232608D01*
+X0327726Y0232608D01*
+X0327726Y0233808D01*
+X0327726Y0239808D01*
+X0323115Y0239808D01*
+X0322708Y0239699D01*
+X0322343Y0239488D01*
+X0322045Y0239191D01*
+X0321835Y0238826D01*
+X0321726Y0238419D01*
+X0321726Y0233808D01*
+X0327726Y0233808D01*
+X0328926Y0233808D01*
+X0328926Y0239808D01*
+X0333536Y0239808D01*
+X0334886Y0238565D02*
+X0378050Y0238565D01*
+X0378050Y0237367D02*
+X0334926Y0237367D01*
+X0334926Y0236168D02*
+X0378050Y0236168D01*
+X0378050Y0234970D02*
+X0334926Y0234970D01*
+X0334926Y0232573D02*
+X0360679Y0232573D01*
+X0360861Y0232754D02*
+X0360316Y0232209D01*
+X0360251Y0232053D01*
+X0360140Y0231925D01*
+X0359895Y0231194D01*
+X0359600Y0230482D01*
+X0359600Y0230312D01*
+X0357385Y0223694D01*
+X0357090Y0222982D01*
+X0357090Y0222812D01*
+X0357036Y0222652D01*
+X0357090Y0221883D01*
+X0357090Y0218223D01*
+X0355879Y0218223D01*
+X0354590Y0216934D01*
+X0354590Y0210112D01*
+X0355879Y0208823D01*
+X0367701Y0208823D01*
+X0368990Y0210112D01*
+X0368990Y0216934D01*
+X0367701Y0218223D01*
+X0367123Y0218223D01*
+X0368284Y0219384D01*
+X0369000Y0221112D01*
+X0369000Y0228781D01*
+X0369054Y0228942D01*
+X0369000Y0229711D01*
+X0369000Y0230482D01*
+X0368935Y0230638D01*
+X0368923Y0230807D01*
+X0368579Y0231497D01*
+X0368284Y0232209D01*
+X0368165Y0232329D01*
+X0368089Y0232480D01*
+X0367507Y0232986D01*
+X0366962Y0233531D01*
+X0366806Y0233596D01*
+X0366678Y0233707D01*
+X0365947Y0233952D01*
+X0365235Y0234247D01*
+X0365066Y0234247D01*
+X0364905Y0234300D01*
+X0364136Y0234247D01*
+X0363365Y0234247D01*
+X0363209Y0234182D01*
+X0363040Y0234170D01*
+X0362350Y0233826D01*
+X0361638Y0233531D01*
+X0361518Y0233411D01*
+X0361366Y0233336D01*
+X0360861Y0232754D01*
+X0359955Y0231374D02*
+X0334926Y0231374D01*
+X0334926Y0230176D02*
+X0359554Y0230176D01*
+X0359153Y0228977D02*
+X0334926Y0228977D01*
+X0328926Y0233771D02*
+X0362217Y0233771D01*
+X0366486Y0233771D02*
+X0378050Y0233771D01*
+X0378050Y0232573D02*
+X0367983Y0232573D01*
+X0368641Y0231374D02*
+X0378050Y0231374D01*
+X0378050Y0230176D02*
+X0369000Y0230176D01*
+X0369051Y0228977D02*
+X0378050Y0228977D01*
+X0378050Y0227779D02*
+X0369000Y0227779D01*
+X0369000Y0226580D02*
+X0378050Y0226580D01*
+X0378050Y0225382D02*
+X0369000Y0225382D01*
+X0369000Y0224183D02*
+X0378050Y0224183D01*
+X0378050Y0222985D02*
+X0369000Y0222985D01*
+X0369000Y0221786D02*
+X0378050Y0221786D01*
+X0378050Y0220588D02*
+X0368783Y0220588D01*
+X0368286Y0219389D02*
+X0378050Y0219389D01*
+X0378050Y0218191D02*
+X0367734Y0218191D01*
+X0368932Y0216992D02*
+X0378050Y0216992D01*
+X0378050Y0215794D02*
+X0368990Y0215794D01*
+X0368990Y0214595D02*
+X0378050Y0214595D01*
+X0378050Y0213397D02*
+X0368990Y0213397D01*
+X0368990Y0212198D02*
+X0378050Y0212198D01*
+X0378050Y0211000D02*
+X0368990Y0211000D01*
+X0368679Y0209801D02*
+X0378050Y0209801D01*
+X0378050Y0208603D02*
+X0346900Y0208603D01*
+X0346900Y0209801D02*
+X0354901Y0209801D01*
+X0354590Y0211000D02*
+X0346900Y0211000D01*
+X0346900Y0212198D02*
+X0354590Y0212198D01*
+X0354590Y0213397D02*
+X0346900Y0213397D01*
+X0346900Y0214595D02*
+X0354590Y0214595D01*
+X0354590Y0215794D02*
+X0346900Y0215794D01*
+X0346900Y0216992D02*
+X0354648Y0216992D01*
+X0355846Y0218191D02*
+X0346900Y0218191D01*
+X0346900Y0219389D02*
+X0357090Y0219389D01*
+X0357090Y0220588D02*
+X0346900Y0220588D01*
+X0346900Y0221786D02*
+X0357090Y0221786D01*
+X0357091Y0222985D02*
+X0346900Y0222985D01*
+X0346900Y0224183D02*
+X0357549Y0224183D01*
+X0357950Y0225382D02*
+X0346900Y0225382D01*
+X0346790Y0226580D02*
+X0358351Y0226580D01*
+X0358752Y0227779D02*
+X0345995Y0227779D01*
+X0328926Y0234970D02*
+X0327726Y0234970D01*
+X0327726Y0236168D02*
+X0328926Y0236168D01*
+X0328926Y0237367D02*
+X0327726Y0237367D01*
+X0327726Y0238565D02*
+X0328926Y0238565D01*
+X0328926Y0239764D02*
+X0327726Y0239764D01*
+X0322950Y0239764D02*
+X0288907Y0239764D01*
+X0286189Y0239764D02*
+X0284989Y0239764D01*
+X0284989Y0240962D02*
+X0286189Y0240962D01*
+X0286189Y0242161D02*
+X0284989Y0242161D01*
+X0284989Y0243359D02*
+X0286189Y0243359D01*
+X0286189Y0244558D02*
+X0284989Y0244558D01*
+X0282271Y0239764D02*
+X0280750Y0239764D01*
+X0280750Y0238565D02*
+X0321765Y0238565D01*
+X0321726Y0237367D02*
+X0280750Y0237367D01*
+X0280750Y0236168D02*
+X0321726Y0236168D01*
+X0321726Y0234970D02*
+X0280750Y0234970D01*
+X0280750Y0233771D02*
+X0327726Y0233771D01*
+X0321726Y0232573D02*
+X0280750Y0232573D01*
+X0280750Y0231374D02*
+X0321726Y0231374D01*
+X0321726Y0230176D02*
+X0280750Y0230176D01*
+X0280750Y0228977D02*
+X0321726Y0228977D01*
+X0298855Y0227779D02*
+X0280750Y0227779D01*
+X0280750Y0226580D02*
+X0298060Y0226580D01*
+X0297950Y0225382D02*
+X0280750Y0225382D01*
+X0280750Y0224183D02*
+X0297950Y0224183D01*
+X0297950Y0222985D02*
+X0280750Y0222985D01*
+X0280750Y0221786D02*
+X0297950Y0221786D01*
+X0297950Y0220588D02*
+X0280750Y0220588D01*
+X0280769Y0219389D02*
+X0297950Y0219389D01*
+X0297950Y0218191D02*
+X0288994Y0218191D01*
+X0290192Y0216992D02*
+X0297950Y0216992D01*
+X0297950Y0215794D02*
+X0290250Y0215794D01*
+X0290250Y0214595D02*
+X0297950Y0214595D01*
+X0297950Y0213397D02*
+X0290250Y0213397D01*
+X0290250Y0212198D02*
+X0297950Y0212198D01*
+X0297950Y0211000D02*
+X0290250Y0211000D01*
+X0289939Y0209801D02*
+X0297950Y0209801D01*
+X0297950Y0208603D02*
+X0284759Y0208603D01*
+X0278936Y0208603D02*
+X0092454Y0208603D01*
+X0092146Y0207859D02*
+X0092933Y0209759D01*
+X0092933Y0211815D01*
+X0092146Y0213715D01*
+X0090692Y0215168D01*
+X0088793Y0215955D01*
+X0080799Y0215955D01*
+X0078900Y0215168D01*
+X0077446Y0213715D01*
+X0076659Y0211815D01*
+X0076659Y0209759D01*
+X0077446Y0207859D01*
+X0078900Y0206405D01*
+X0080799Y0205618D01*
+X0088793Y0205618D01*
+X0090692Y0206405D01*
+X0092146Y0207859D01*
+X0091691Y0207404D02*
+X0297950Y0207404D01*
+X0297950Y0206206D02*
+X0090210Y0206206D01*
+X0092933Y0209801D02*
+X0275893Y0209801D01*
+X0276415Y0209422D02*
+X0276415Y0209422D01*
+X0274243Y0211000D02*
+X0092933Y0211000D01*
+X0092774Y0212198D02*
+X0273040Y0212198D01*
+X0272169Y0213397D02*
+X0092278Y0213397D01*
+X0091266Y0214595D02*
+X0271381Y0214595D01*
+X0271449Y0214388D02*
+X0271449Y0214388D01*
+X0270992Y0215794D02*
+X0233085Y0215794D01*
+X0233113Y0215808D02*
+X0233670Y0216212D01*
+X0234156Y0216699D01*
+X0234561Y0217255D01*
+X0234873Y0217869D01*
+X0235086Y0218523D01*
+X0235193Y0219203D01*
+X0235193Y0219261D01*
+X0228336Y0219261D01*
+X0228336Y0219833D01*
+X0227764Y0219833D01*
+X0227764Y0223918D01*
+X0224934Y0223918D01*
+X0224255Y0223811D01*
+X0223600Y0223598D01*
+X0222987Y0223286D01*
+X0222430Y0222881D01*
+X0221944Y0222395D01*
+X0221539Y0221838D01*
+X0221227Y0221225D01*
+X0221014Y0220570D01*
+X0220907Y0219891D01*
+X0220907Y0219833D01*
+X0227764Y0219833D01*
+X0227764Y0219261D01*
+X0220907Y0219261D01*
+X0220907Y0219203D01*
+X0221014Y0218523D01*
+X0221227Y0217869D01*
+X0221539Y0217255D01*
+X0221944Y0216699D01*
+X0222430Y0216212D01*
+X0222987Y0215808D01*
+X0223600Y0215495D01*
+X0224255Y0215283D01*
+X0224934Y0215175D01*
+X0227764Y0215175D01*
+X0227764Y0219261D01*
+X0228336Y0219261D01*
+X0228336Y0215175D01*
+X0231166Y0215175D01*
+X0231845Y0215283D01*
+X0232500Y0215495D01*
+X0233113Y0215808D01*
+X0234369Y0216992D02*
+X0270602Y0216992D01*
+X0270350Y0218191D02*
+X0234978Y0218191D01*
+X0235193Y0219833D02*
+X0235193Y0219891D01*
+X0235086Y0220570D01*
+X0234873Y0221225D01*
+X0234561Y0221838D01*
+X0234156Y0222395D01*
+X0233670Y0222881D01*
+X0233113Y0223286D01*
+X0232500Y0223598D01*
+X0231845Y0223811D01*
+X0231166Y0223918D01*
+X0228336Y0223918D01*
+X0228336Y0219833D01*
+X0235193Y0219833D01*
+X0235080Y0220588D02*
+X0270350Y0220588D01*
+X0270350Y0221786D02*
+X0234587Y0221786D01*
+X0233527Y0222985D02*
+X0270350Y0222985D01*
+X0270350Y0224183D02*
+X0078116Y0224183D01*
+X0077730Y0223251D02*
+X0078750Y0225714D01*
+X0078750Y0228379D01*
+X0077730Y0230842D01*
+X0075845Y0232727D01*
+X0073383Y0233747D01*
+X0061717Y0233747D01*
+X0059255Y0232727D01*
+X0057370Y0230842D01*
+X0056350Y0228379D01*
+X0056350Y0225714D01*
+X0057370Y0223251D01*
+X0059255Y0221367D01*
+X0061717Y0220347D01*
+X0073383Y0220347D01*
+X0075845Y0221367D01*
+X0077730Y0223251D01*
+X0077463Y0222985D02*
+X0222573Y0222985D01*
+X0221513Y0221786D02*
+X0076265Y0221786D01*
+X0073964Y0220588D02*
+X0221020Y0220588D01*
+X0221122Y0218191D02*
+X0001800Y0218191D01*
+X0001800Y0219389D02*
+X0227764Y0219389D01*
+X0228336Y0219389D02*
+X0270350Y0219389D01*
+X0270350Y0225382D02*
+X0078612Y0225382D01*
+X0078750Y0226580D02*
+X0270350Y0226580D01*
+X0270350Y0227779D02*
+X0078750Y0227779D01*
+X0078502Y0228977D02*
+X0270350Y0228977D01*
+X0270350Y0230176D02*
+X0078006Y0230176D01*
+X0077198Y0231374D02*
+X0270350Y0231374D01*
+X0270350Y0232573D02*
+X0075999Y0232573D01*
+X0061136Y0220588D02*
+X0001800Y0220588D01*
+X0001800Y0221786D02*
+X0033438Y0221786D01*
+X0033353Y0221830D02*
+X0034208Y0221394D01*
+X0035122Y0221097D01*
+X0036070Y0220947D01*
+X0044950Y0220947D01*
+X0044950Y0226447D01*
+X0030469Y0226447D01*
+X0030600Y0225618D01*
+X0030897Y0224705D01*
+X0031333Y0223850D01*
+X0031897Y0223073D01*
+X0032576Y0222394D01*
+X0033353Y0221830D01*
+X0031985Y0222985D02*
+X0001800Y0222985D01*
+X0001800Y0224183D02*
+X0031163Y0224183D01*
+X0030677Y0225382D02*
+X0001800Y0225382D01*
+X0001800Y0226580D02*
+X0044950Y0226580D01*
+X0044950Y0226447D02*
+X0044950Y0227647D01*
+X0044950Y0233147D01*
+X0036070Y0233147D01*
+X0035122Y0232996D01*
+X0034208Y0232700D01*
+X0033353Y0232264D01*
+X0032576Y0231699D01*
+X0031897Y0231021D01*
+X0031333Y0230244D01*
+X0030897Y0229388D01*
+X0030600Y0228475D01*
+X0030469Y0227647D01*
+X0044950Y0227647D01*
+X0046150Y0227647D01*
+X0046150Y0233128D01*
+X0046978Y0232996D01*
+X0047892Y0232700D01*
+X0048747Y0232264D01*
+X0049524Y0231699D01*
+X0050203Y0231021D01*
+X0050767Y0230244D01*
+X0051203Y0229388D01*
+X0051500Y0228475D01*
+X0051631Y0227647D01*
+X0046150Y0227647D01*
+X0046150Y0226447D01*
+X0051631Y0226447D01*
+X0051500Y0225618D01*
+X0051203Y0224705D01*
+X0050767Y0223850D01*
+X0050203Y0223073D01*
+X0049524Y0222394D01*
+X0048747Y0221830D01*
+X0047892Y0221394D01*
+X0046978Y0221097D01*
+X0046150Y0220966D01*
+X0046150Y0226447D01*
+X0044950Y0226447D01*
+X0044950Y0225382D02*
+X0046150Y0225382D01*
+X0046150Y0226580D02*
+X0056350Y0226580D01*
+X0056350Y0227779D02*
+X0051610Y0227779D01*
+X0051337Y0228977D02*
+X0056598Y0228977D01*
+X0057094Y0230176D02*
+X0050802Y0230176D01*
+X0049849Y0231374D02*
+X0057902Y0231374D01*
+X0059101Y0232573D02*
+X0048141Y0232573D01*
+X0046150Y0232573D02*
+X0044950Y0232573D01*
+X0044950Y0231374D02*
+X0046150Y0231374D01*
+X0046150Y0230176D02*
+X0044950Y0230176D01*
+X0044950Y0228977D02*
+X0046150Y0228977D01*
+X0046150Y0227779D02*
+X0044950Y0227779D01*
+X0044950Y0224183D02*
+X0046150Y0224183D01*
+X0046150Y0222985D02*
+X0044950Y0222985D01*
+X0044950Y0221786D02*
+X0046150Y0221786D01*
+X0048662Y0221786D02*
+X0058835Y0221786D01*
+X0057637Y0222985D02*
+X0050115Y0222985D01*
+X0050937Y0224183D02*
+X0056984Y0224183D01*
+X0056488Y0225382D02*
+X0051423Y0225382D01*
+X0033959Y0232573D02*
+X0001800Y0232573D01*
+X0001800Y0233771D02*
+X0270350Y0233771D01*
+X0270350Y0234970D02*
+X0001800Y0234970D01*
+X0001800Y0236168D02*
+X0270350Y0236168D01*
+X0270350Y0237367D02*
+X0001800Y0237367D01*
+X0001800Y0238565D02*
+X0195157Y0238565D01*
+X0195805Y0238297D02*
+X0197795Y0238297D01*
+X0199632Y0239058D01*
+X0201039Y0240464D01*
+X0201800Y0242302D01*
+X0201800Y0244291D01*
+X0201039Y0246129D01*
+X0199632Y0247535D01*
+X0197795Y0248297D01*
+X0195805Y0248297D01*
+X0193968Y0247535D01*
+X0192561Y0246129D01*
+X0191800Y0244291D01*
+X0191800Y0242302D01*
+X0192561Y0240464D01*
+X0193968Y0239058D01*
+X0195805Y0238297D01*
+X0198443Y0238565D02*
+X0204460Y0238565D01*
+X0204729Y0238297D02*
+X0208871Y0238297D01*
+X0211800Y0241226D01*
+X0211800Y0245368D01*
+X0208871Y0248297D01*
+X0204729Y0248297D01*
+X0201800Y0245368D01*
+X0201800Y0241226D01*
+X0204729Y0238297D01*
+X0203262Y0239764D02*
+X0200338Y0239764D01*
+X0201245Y0240962D02*
+X0202063Y0240962D01*
+X0201800Y0242161D02*
+X0201741Y0242161D01*
+X0201800Y0243359D02*
+X0201800Y0243359D01*
+X0201800Y0244558D02*
+X0201690Y0244558D01*
+X0201193Y0245756D02*
+X0202189Y0245756D01*
+X0203387Y0246955D02*
+X0200213Y0246955D01*
+X0198871Y0248297D02*
+X0201800Y0251226D01*
+X0201800Y0255368D01*
+X0198871Y0258297D01*
+X0194729Y0258297D01*
+X0191800Y0255368D01*
+X0191800Y0251226D01*
+X0194729Y0248297D01*
+X0198871Y0248297D01*
+X0198140Y0248153D02*
+X0204586Y0248153D01*
+X0204977Y0248897D02*
+X0206500Y0248897D01*
+X0206500Y0252997D01*
+X0202400Y0252997D01*
+X0202400Y0251474D01*
+X0204977Y0248897D01*
+X0204522Y0249352D02*
+X0199926Y0249352D01*
+X0201125Y0250550D02*
+X0203324Y0250550D01*
+X0202400Y0251749D02*
+X0201800Y0251749D01*
+X0201800Y0252947D02*
+X0202400Y0252947D01*
+X0202400Y0253597D02*
+X0206500Y0253597D01*
+X0206500Y0257697D01*
+X0204977Y0257697D01*
+X0202400Y0255119D01*
+X0202400Y0253597D01*
+X0202400Y0254146D02*
+X0201800Y0254146D01*
+X0201800Y0255344D02*
+X0202625Y0255344D01*
+X0203824Y0256543D02*
+X0200625Y0256543D01*
+X0199426Y0257742D02*
+X0224174Y0257742D01*
+X0224729Y0258297D02*
+X0221800Y0255368D01*
+X0221800Y0251226D01*
+X0224729Y0248297D01*
+X0228871Y0248297D01*
+X0231800Y0251226D01*
+X0234729Y0248297D01*
+X0238871Y0248297D01*
+X0241800Y0251226D01*
+X0241800Y0255368D01*
+X0238871Y0258297D01*
+X0234729Y0258297D01*
+X0231800Y0255368D01*
+X0231800Y0251226D01*
+X0231800Y0255368D01*
+X0228871Y0258297D01*
+X0224729Y0258297D01*
+X0222975Y0256543D02*
+X0219776Y0256543D01*
+X0218623Y0257697D02*
+X0217100Y0257697D01*
+X0217100Y0253597D01*
+X0216500Y0253597D01*
+X0216500Y0257697D01*
+X0214977Y0257697D01*
+X0212400Y0255119D01*
+X0212400Y0253597D01*
+X0216500Y0253597D01*
+X0216500Y0252997D01*
+X0212400Y0252997D01*
+X0212400Y0251474D01*
+X0214977Y0248897D01*
+X0216500Y0248897D01*
+X0216500Y0252997D01*
+X0217100Y0252997D01*
+X0217100Y0253597D01*
+X0221200Y0253597D01*
+X0221200Y0255119D01*
+X0218623Y0257697D01*
+X0217100Y0256543D02*
+X0216500Y0256543D01*
+X0216500Y0255344D02*
+X0217100Y0255344D01*
+X0217100Y0254146D02*
+X0216500Y0254146D01*
+X0216500Y0252947D02*
+X0217100Y0252947D01*
+X0217100Y0252997D02*
+X0217100Y0248897D01*
+X0218623Y0248897D01*
+X0221200Y0251474D01*
+X0221200Y0252997D01*
+X0217100Y0252997D01*
+X0217100Y0251749D02*
+X0216500Y0251749D01*
+X0216500Y0250550D02*
+X0217100Y0250550D01*
+X0217100Y0249352D02*
+X0216500Y0249352D01*
+X0214522Y0249352D02*
+X0209078Y0249352D01*
+X0208623Y0248897D02*
+X0211200Y0251474D01*
+X0211200Y0252997D01*
+X0207100Y0252997D01*
+X0207100Y0253597D01*
+X0206500Y0253597D01*
+X0206500Y0252997D01*
+X0207100Y0252997D01*
+X0207100Y0248897D01*
+X0208623Y0248897D01*
+X0209014Y0248153D02*
+X0214586Y0248153D01*
+X0214729Y0248297D02*
+X0211800Y0245368D01*
+X0211800Y0241226D01*
+X0214729Y0238297D01*
+X0218871Y0238297D01*
+X0221800Y0241226D01*
+X0224729Y0238297D01*
+X0228871Y0238297D01*
+X0231800Y0241226D01*
+X0234729Y0238297D01*
+X0238871Y0238297D01*
+X0241800Y0241226D01*
+X0241800Y0245368D01*
+X0238871Y0248297D01*
+X0234729Y0248297D01*
+X0231800Y0245368D01*
+X0231800Y0241226D01*
+X0231800Y0245368D01*
+X0228871Y0248297D01*
+X0224729Y0248297D01*
+X0221800Y0245368D01*
+X0221800Y0241226D01*
+X0221800Y0245368D01*
+X0218871Y0248297D01*
+X0214729Y0248297D01*
+X0213387Y0246955D02*
+X0210213Y0246955D01*
+X0211411Y0245756D02*
+X0212189Y0245756D01*
+X0211800Y0244558D02*
+X0211800Y0244558D01*
+X0211800Y0243359D02*
+X0211800Y0243359D01*
+X0211800Y0242161D02*
+X0211800Y0242161D01*
+X0211537Y0240962D02*
+X0212063Y0240962D01*
+X0213262Y0239764D02*
+X0210338Y0239764D01*
+X0209140Y0238565D02*
+X0214460Y0238565D01*
+X0219140Y0238565D02*
+X0224460Y0238565D01*
+X0223262Y0239764D02*
+X0220338Y0239764D01*
+X0221537Y0240962D02*
+X0222063Y0240962D01*
+X0221800Y0242161D02*
+X0221800Y0242161D01*
+X0221800Y0243359D02*
+X0221800Y0243359D01*
+X0221800Y0244558D02*
+X0221800Y0244558D01*
+X0221411Y0245756D02*
+X0222189Y0245756D01*
+X0223387Y0246955D02*
+X0220213Y0246955D01*
+X0219014Y0248153D02*
+X0224586Y0248153D01*
+X0223674Y0249352D02*
+X0219078Y0249352D01*
+X0220276Y0250550D02*
+X0222475Y0250550D01*
+X0221800Y0251749D02*
+X0221200Y0251749D01*
+X0221200Y0252947D02*
+X0221800Y0252947D01*
+X0221800Y0254146D02*
+X0221200Y0254146D01*
+X0220975Y0255344D02*
+X0221800Y0255344D01*
+X0229426Y0257742D02*
+X0234174Y0257742D01*
+X0232975Y0256543D02*
+X0230625Y0256543D01*
+X0231800Y0255344D02*
+X0231800Y0255344D01*
+X0231800Y0254146D02*
+X0231800Y0254146D01*
+X0231800Y0252947D02*
+X0231800Y0252947D01*
+X0231800Y0251749D02*
+X0231800Y0251749D01*
+X0231125Y0250550D02*
+X0232475Y0250550D01*
+X0233674Y0249352D02*
+X0229926Y0249352D01*
+X0229014Y0248153D02*
+X0234586Y0248153D01*
+X0233387Y0246955D02*
+X0230213Y0246955D01*
+X0231411Y0245756D02*
+X0232189Y0245756D01*
+X0231800Y0244558D02*
+X0231800Y0244558D01*
+X0231800Y0243359D02*
+X0231800Y0243359D01*
+X0231800Y0242161D02*
+X0231800Y0242161D01*
+X0231537Y0240962D02*
+X0232063Y0240962D01*
+X0233262Y0239764D02*
+X0230338Y0239764D01*
+X0229140Y0238565D02*
+X0234460Y0238565D01*
+X0239140Y0238565D02*
+X0270350Y0238565D01*
+X0270350Y0239764D02*
+X0268829Y0239764D01*
+X0266111Y0239764D02*
+X0264911Y0239764D01*
+X0264911Y0240962D02*
+X0266111Y0240962D01*
+X0266111Y0242161D02*
+X0264911Y0242161D01*
+X0264911Y0243359D02*
+X0266111Y0243359D01*
+X0266111Y0244558D02*
+X0264911Y0244558D01*
+X0264911Y0245756D02*
+X0241411Y0245756D01*
+X0241800Y0244558D02*
+X0258760Y0244558D01*
+X0259090Y0243359D02*
+X0241800Y0243359D01*
+X0241800Y0242161D02*
+X0259678Y0242161D01*
+X0260619Y0240962D02*
+X0241537Y0240962D01*
+X0240338Y0239764D02*
+X0262193Y0239764D01*
+X0264911Y0246955D02*
+X0266111Y0246955D01*
+X0266111Y0248153D02*
+X0264911Y0248153D01*
+X0264911Y0249352D02*
+X0266111Y0249352D01*
+X0266111Y0250550D02*
+X0264911Y0250550D01*
+X0264911Y0251749D02*
+X0266111Y0251749D01*
+X0268834Y0251749D02*
+X0270123Y0251749D01*
+X0269478Y0252947D02*
+X0241800Y0252947D01*
+X0241800Y0251749D02*
+X0262188Y0251749D01*
+X0260616Y0250550D02*
+X0241125Y0250550D01*
+X0239926Y0249352D02*
+X0259676Y0249352D01*
+X0259089Y0248153D02*
+X0239014Y0248153D01*
+X0240213Y0246955D02*
+X0258760Y0246955D01*
+X0268982Y0254146D02*
+X0241800Y0254146D01*
+X0241800Y0255344D02*
+X0268850Y0255344D01*
+X0268850Y0256543D02*
+X0240625Y0256543D01*
+X0239426Y0257742D02*
+X0269104Y0257742D01*
+X0272040Y0263734D02*
+X0279060Y0263734D01*
+X0278799Y0264933D02*
+X0272301Y0264933D01*
+X0272202Y0267330D02*
+X0278898Y0267330D01*
+X0279290Y0268528D02*
+X0271810Y0268528D01*
+X0271160Y0269727D02*
+X0279940Y0269727D01*
+X0280991Y0270925D02*
+X0270109Y0270925D01*
+X0262792Y0272124D02*
+X0106968Y0272124D01*
+X0106968Y0273322D02*
+X0378050Y0273322D01*
+X0378050Y0272124D02*
+X0288308Y0272124D01*
+X0290187Y0270925D02*
+X0378050Y0270925D01*
+X0378050Y0269727D02*
+X0291238Y0269727D01*
+X0291888Y0268528D02*
+X0378050Y0268528D01*
+X0378050Y0267330D02*
+X0292280Y0267330D01*
+X0288912Y0251749D02*
+X0378050Y0251749D01*
+X0378050Y0250550D02*
+X0290484Y0250550D01*
+X0291424Y0249352D02*
+X0378050Y0249352D01*
+X0378050Y0248153D02*
+X0292011Y0248153D01*
+X0292340Y0246955D02*
+X0378050Y0246955D01*
+X0378050Y0274521D02*
+X0106564Y0274521D01*
+X0105905Y0275719D02*
+X0378050Y0275719D01*
+X0378050Y0207404D02*
+X0346900Y0207404D01*
+X0346900Y0206206D02*
+X0378050Y0206206D01*
+X0378050Y0205007D02*
+X0346900Y0205007D01*
+X0346900Y0203809D02*
+X0378050Y0203809D01*
+X0378050Y0202610D02*
+X0346900Y0202610D01*
+X0346900Y0201411D02*
+X0355664Y0201411D01*
+X0355808Y0201555D02*
+X0355510Y0201257D01*
+X0355299Y0200893D01*
+X0355190Y0200486D01*
+X0355190Y0198375D01*
+X0361190Y0198375D01*
+X0361190Y0197175D01*
+X0355190Y0197175D01*
+X0355190Y0195064D01*
+X0355299Y0194657D01*
+X0355510Y0194293D01*
+X0355808Y0193995D01*
+X0356173Y0193784D01*
+X0356580Y0193675D01*
+X0361190Y0193675D01*
+X0361190Y0197175D01*
+X0362390Y0197175D01*
+X0362390Y0193675D01*
+X0367001Y0193675D01*
+X0367408Y0193784D01*
+X0367773Y0193995D01*
+X0368070Y0194293D01*
+X0368281Y0194657D01*
+X0368390Y0195064D01*
+X0368390Y0197175D01*
+X0362390Y0197175D01*
+X0362390Y0198375D01*
+X0361190Y0198375D01*
+X0361190Y0201875D01*
+X0356580Y0201875D01*
+X0356173Y0201766D01*
+X0355808Y0201555D01*
+X0355190Y0200213D02*
+X0346900Y0200213D01*
+X0346900Y0199014D02*
+X0355190Y0199014D01*
+X0355190Y0196617D02*
+X0346900Y0196617D01*
+X0346900Y0195419D02*
+X0355190Y0195419D01*
+X0355582Y0194220D02*
+X0346900Y0194220D01*
+X0346900Y0193022D02*
+X0378050Y0193022D01*
+X0378050Y0194220D02*
+X0367998Y0194220D01*
+X0368390Y0195419D02*
+X0378050Y0195419D01*
+X0378050Y0196617D02*
+X0368390Y0196617D01*
+X0368390Y0198375D02*
+X0362390Y0198375D01*
+X0362390Y0201875D01*
+X0367001Y0201875D01*
+X0367408Y0201766D01*
+X0367773Y0201555D01*
+X0368070Y0201257D01*
+X0368281Y0200893D01*
+X0368390Y0200486D01*
+X0368390Y0198375D01*
+X0368390Y0199014D02*
+X0378050Y0199014D01*
+X0378050Y0197816D02*
+X0362390Y0197816D01*
+X0362390Y0199014D02*
+X0361190Y0199014D01*
+X0361190Y0197816D02*
+X0346900Y0197816D01*
+X0346900Y0191823D02*
+X0378050Y0191823D01*
+X0378050Y0190625D02*
+X0346900Y0190625D01*
+X0346547Y0189426D02*
+X0378050Y0189426D01*
+X0378050Y0188228D02*
+X0345251Y0188228D01*
+X0343753Y0187029D02*
+X0378050Y0187029D01*
+X0378050Y0185831D02*
+X0368598Y0185831D01*
+X0368990Y0185438D02*
+X0367701Y0186727D01*
+X0355879Y0186727D01*
+X0354590Y0185438D01*
+X0354590Y0178616D01*
+X0355879Y0177327D01*
+X0367701Y0177327D01*
+X0368990Y0178616D01*
+X0368990Y0185438D01*
+X0368990Y0184632D02*
+X0378050Y0184632D01*
+X0378050Y0183434D02*
+X0368990Y0183434D01*
+X0368990Y0182235D02*
+X0378050Y0182235D01*
+X0378050Y0181037D02*
+X0368990Y0181037D01*
+X0368990Y0179838D02*
+X0378050Y0179838D01*
+X0378050Y0178640D02*
+X0368990Y0178640D01*
+X0367816Y0177441D02*
+X0378050Y0177441D01*
+X0378050Y0176243D02*
+X0340650Y0176243D01*
+X0340650Y0177441D02*
+X0355765Y0177441D01*
+X0354590Y0178640D02*
+X0340650Y0178640D01*
+X0340650Y0179838D02*
+X0354590Y0179838D01*
+X0354590Y0181037D02*
+X0340650Y0181037D01*
+X0340650Y0182235D02*
+X0354590Y0182235D01*
+X0354590Y0183434D02*
+X0340650Y0183434D01*
+X0340757Y0184632D02*
+X0354590Y0184632D01*
+X0354983Y0185831D02*
+X0342255Y0185831D01*
+X0340650Y0175044D02*
+X0378050Y0175044D01*
+X0378050Y0173846D02*
+X0340650Y0173846D01*
+X0340650Y0172647D02*
+X0378050Y0172647D01*
+X0378050Y0171449D02*
+X0340650Y0171449D01*
+X0340650Y0170250D02*
+X0355150Y0170250D01*
+X0354590Y0169690D02*
+X0355879Y0170979D01*
+X0367701Y0170979D01*
+X0368990Y0169690D01*
+X0368990Y0162868D01*
+X0367701Y0161579D01*
+X0355879Y0161579D01*
+X0354590Y0162868D01*
+X0354590Y0169690D01*
+X0354590Y0169052D02*
+X0340650Y0169052D01*
+X0340650Y0167853D02*
+X0354590Y0167853D01*
+X0354590Y0166655D02*
+X0340650Y0166655D01*
+X0340650Y0165456D02*
+X0354590Y0165456D01*
+X0354590Y0164258D02*
+X0340650Y0164258D01*
+X0340650Y0163059D02*
+X0354590Y0163059D01*
+X0355597Y0161861D02*
+X0340882Y0161861D01*
+X0342380Y0160662D02*
+X0378050Y0160662D01*
+X0378050Y0159464D02*
+X0343878Y0159464D01*
+X0345377Y0158265D02*
+X0378050Y0158265D01*
+X0378050Y0157067D02*
+X0346588Y0157067D01*
+X0346908Y0155868D02*
+X0378050Y0155868D01*
+X0378050Y0154670D02*
+X0368263Y0154670D01*
+X0367701Y0155231D02*
+X0355879Y0155231D01*
+X0354590Y0153942D01*
+X0354590Y0147120D01*
+X0355879Y0145831D01*
+X0359675Y0145831D01*
+X0360421Y0144342D01*
+X0360316Y0144089D01*
+X0360316Y0142504D01*
+X0360922Y0141040D01*
+X0362043Y0139919D01*
+X0363096Y0139483D01*
+X0355879Y0139483D01*
+X0354590Y0138194D01*
+X0354590Y0131372D01*
+X0355879Y0130083D01*
+X0358843Y0130083D01*
+X0359247Y0129107D01*
+X0360316Y0128038D01*
+X0360316Y0127504D01*
+X0360922Y0126040D01*
+X0362043Y0124919D01*
+X0363507Y0124312D01*
+X0365093Y0124312D01*
+X0366557Y0124919D01*
+X0367678Y0126040D01*
+X0368284Y0127504D01*
+X0368284Y0129089D01*
+X0367822Y0130204D01*
+X0368990Y0131372D01*
+X0368990Y0138194D01*
+X0367701Y0139483D01*
+X0365504Y0139483D01*
+X0366557Y0139919D01*
+X0367678Y0141040D01*
+X0368284Y0142504D01*
+X0368284Y0144089D01*
+X0367678Y0145554D01*
+X0367400Y0145831D01*
+X0367701Y0145831D01*
+X0368990Y0147120D01*
+X0368990Y0153942D01*
+X0367701Y0155231D01*
+X0368990Y0153471D02*
+X0378050Y0153471D01*
+X0378050Y0152273D02*
+X0368990Y0152273D01*
+X0368990Y0151074D02*
+X0378050Y0151074D01*
+X0378050Y0149875D02*
+X0368990Y0149875D01*
+X0368990Y0148677D02*
+X0378050Y0148677D01*
+X0378050Y0147478D02*
+X0368990Y0147478D01*
+X0368150Y0146280D02*
+X0378050Y0146280D01*
+X0378050Y0145081D02*
+X0367873Y0145081D01*
+X0368284Y0143883D02*
+X0378050Y0143883D01*
+X0378050Y0142684D02*
+X0368284Y0142684D01*
+X0367862Y0141486D02*
+X0378050Y0141486D01*
+X0378050Y0140287D02*
+X0366925Y0140287D01*
+X0368095Y0139089D02*
+X0378050Y0139089D01*
+X0378050Y0137890D02*
+X0368990Y0137890D01*
+X0368990Y0136692D02*
+X0378050Y0136692D01*
+X0378050Y0135493D02*
+X0368990Y0135493D01*
+X0368990Y0134295D02*
+X0378050Y0134295D01*
+X0378050Y0133096D02*
+X0368990Y0133096D01*
+X0368990Y0131898D02*
+X0378050Y0131898D01*
+X0378050Y0130699D02*
+X0368318Y0130699D01*
+X0368114Y0129501D02*
+X0378050Y0129501D01*
+X0378050Y0128302D02*
+X0368284Y0128302D01*
+X0368118Y0127104D02*
+X0378050Y0127104D01*
+X0378050Y0125905D02*
+X0367543Y0125905D01*
+X0366044Y0124707D02*
+X0378050Y0124707D01*
+X0378050Y0123508D02*
+X0367928Y0123508D01*
+X0367701Y0123735D02*
+X0355879Y0123735D01*
+X0354590Y0122446D01*
+X0354590Y0115624D01*
+X0355879Y0114335D01*
+X0358390Y0114335D01*
+X0358390Y0111370D01*
+X0358908Y0110121D01*
+X0359864Y0109164D01*
+X0361114Y0108647D01*
+X0362097Y0108647D01*
+X0363507Y0108062D01*
+X0365093Y0108062D01*
+X0366557Y0108669D01*
+X0367678Y0109790D01*
+X0368284Y0111254D01*
+X0368284Y0112839D01*
+X0367678Y0114304D01*
+X0367646Y0114335D01*
+X0367701Y0114335D01*
+X0368990Y0115624D01*
+X0368990Y0122446D01*
+X0367701Y0123735D01*
+X0368990Y0122310D02*
+X0378050Y0122310D01*
+X0378050Y0121111D02*
+X0368990Y0121111D01*
+X0368990Y0119913D02*
+X0378050Y0119913D01*
+X0378050Y0118714D02*
+X0368990Y0118714D01*
+X0368990Y0117516D02*
+X0378050Y0117516D01*
+X0378050Y0116317D02*
+X0368990Y0116317D01*
+X0368485Y0115119D02*
+X0378050Y0115119D01*
+X0378050Y0113920D02*
+X0367837Y0113920D01*
+X0368284Y0112722D02*
+X0378050Y0112722D01*
+X0378050Y0111523D02*
+X0368284Y0111523D01*
+X0367899Y0110325D02*
+X0378050Y0110325D01*
+X0378050Y0109126D02*
+X0367014Y0109126D01*
+X0367001Y0107387D02*
+X0362390Y0107387D01*
+X0362390Y0103887D01*
+X0361190Y0103887D01*
+X0361190Y0107387D01*
+X0356580Y0107387D01*
+X0356173Y0107278D01*
+X0355808Y0107067D01*
+X0355510Y0106769D01*
+X0355299Y0106404D01*
+X0355190Y0105997D01*
+X0355190Y0103887D01*
+X0361190Y0103887D01*
+X0361190Y0102687D01*
+X0355190Y0102687D01*
+X0355190Y0100576D01*
+X0355299Y0100169D01*
+X0355510Y0099804D01*
+X0355808Y0099507D01*
+X0356173Y0099296D01*
+X0356580Y0099187D01*
+X0361190Y0099187D01*
+X0361190Y0102687D01*
+X0362390Y0102687D01*
+X0362390Y0099187D01*
+X0367001Y0099187D01*
+X0367408Y0099296D01*
+X0367773Y0099507D01*
+X0368070Y0099804D01*
+X0368281Y0100169D01*
+X0368390Y0100576D01*
+X0368390Y0102687D01*
+X0362390Y0102687D01*
+X0362390Y0103887D01*
+X0368390Y0103887D01*
+X0368390Y0105997D01*
+X0368281Y0106404D01*
+X0368070Y0106769D01*
+X0367773Y0107067D01*
+X0367408Y0107278D01*
+X0367001Y0107387D01*
+X0368094Y0106729D02*
+X0378050Y0106729D01*
+X0378050Y0105531D02*
+X0368390Y0105531D01*
+X0368390Y0104332D02*
+X0378050Y0104332D01*
+X0378050Y0103134D02*
+X0362390Y0103134D01*
+X0362390Y0104332D02*
+X0361190Y0104332D01*
+X0361190Y0103134D02*
+X0346900Y0103134D01*
+X0346900Y0104332D02*
+X0355190Y0104332D01*
+X0355190Y0105531D02*
+X0346900Y0105531D01*
+X0346900Y0106729D02*
+X0355487Y0106729D01*
+X0358823Y0110325D02*
+X0346900Y0110325D01*
+X0346900Y0111523D02*
+X0358390Y0111523D01*
+X0358390Y0112722D02*
+X0346900Y0112722D01*
+X0346900Y0113920D02*
+X0358390Y0113920D01*
+X0355095Y0115119D02*
+X0346900Y0115119D01*
+X0346900Y0116317D02*
+X0354590Y0116317D01*
+X0354590Y0117516D02*
+X0346900Y0117516D01*
+X0346900Y0118714D02*
+X0354590Y0118714D01*
+X0354590Y0119913D02*
+X0346900Y0119913D01*
+X0346900Y0121111D02*
+X0354590Y0121111D01*
+X0354590Y0122310D02*
+X0346900Y0122310D01*
+X0346900Y0123508D02*
+X0355652Y0123508D01*
+X0360482Y0127104D02*
+X0346900Y0127104D01*
+X0346900Y0128302D02*
+X0360052Y0128302D01*
+X0359084Y0129501D02*
+X0346900Y0129501D01*
+X0346900Y0130699D02*
+X0355262Y0130699D01*
+X0354590Y0131898D02*
+X0346900Y0131898D01*
+X0346900Y0133096D02*
+X0354590Y0133096D01*
+X0354590Y0134295D02*
+X0346900Y0134295D01*
+X0346900Y0135493D02*
+X0354590Y0135493D01*
+X0354590Y0136692D02*
+X0346900Y0136692D01*
+X0346900Y0137890D02*
+X0354590Y0137890D01*
+X0355485Y0139089D02*
+X0346900Y0139089D01*
+X0346900Y0140287D02*
+X0361675Y0140287D01*
+X0360738Y0141486D02*
+X0346900Y0141486D01*
+X0346900Y0142684D02*
+X0360316Y0142684D01*
+X0360316Y0143883D02*
+X0346900Y0143883D01*
+X0346900Y0145081D02*
+X0360050Y0145081D01*
+X0355430Y0146280D02*
+X0346900Y0146280D01*
+X0346900Y0147478D02*
+X0354590Y0147478D01*
+X0354590Y0148677D02*
+X0346900Y0148677D01*
+X0346900Y0149875D02*
+X0354590Y0149875D01*
+X0354590Y0151074D02*
+X0346900Y0151074D01*
+X0346900Y0152273D02*
+X0354590Y0152273D01*
+X0354590Y0153471D02*
+X0346900Y0153471D01*
+X0346900Y0154670D02*
+X0355317Y0154670D01*
+X0367983Y0161861D02*
+X0378050Y0161861D01*
+X0378050Y0163059D02*
+X0368990Y0163059D01*
+X0368990Y0164258D02*
+X0378050Y0164258D01*
+X0378050Y0165456D02*
+X0368990Y0165456D01*
+X0368990Y0166655D02*
+X0378050Y0166655D01*
+X0378050Y0167853D02*
+X0368990Y0167853D01*
+X0368990Y0169052D02*
+X0378050Y0169052D01*
+X0378050Y0170250D02*
+X0368430Y0170250D01*
+X0362390Y0194220D02*
+X0361190Y0194220D01*
+X0361190Y0195419D02*
+X0362390Y0195419D01*
+X0362390Y0196617D02*
+X0361190Y0196617D01*
+X0361190Y0200213D02*
+X0362390Y0200213D01*
+X0362390Y0201411D02*
+X0361190Y0201411D01*
+X0367916Y0201411D02*
+X0378050Y0201411D01*
+X0378050Y0200213D02*
+X0368390Y0200213D01*
+X0297950Y0200213D02*
+X0289650Y0200213D01*
+X0289650Y0200486D02*
+X0289541Y0200893D01*
+X0289330Y0201257D01*
+X0289032Y0201555D01*
+X0288668Y0201766D01*
+X0288261Y0201875D01*
+X0283650Y0201875D01*
+X0283650Y0198375D01*
+X0289650Y0198375D01*
+X0289650Y0200486D01*
+X0289176Y0201411D02*
+X0297950Y0201411D01*
+X0297950Y0202610D02*
+X0001800Y0202610D01*
+X0001800Y0203809D02*
+X0297950Y0203809D01*
+X0297950Y0205007D02*
+X0001800Y0205007D01*
+X0001800Y0206206D02*
+X0079382Y0206206D01*
+X0077901Y0207404D02*
+X0029850Y0207404D01*
+X0029749Y0207302D02*
+X0030257Y0207811D01*
+X0030680Y0208392D01*
+X0031006Y0209033D01*
+X0031228Y0209717D01*
+X0031337Y0210403D01*
+X0021220Y0210403D01*
+X0021220Y0211171D01*
+X0031337Y0211171D01*
+X0031228Y0211857D01*
+X0031006Y0212541D01*
+X0030680Y0213181D01*
+X0030257Y0213763D01*
+X0029749Y0214271D01*
+X0029167Y0214694D01*
+X0028526Y0215021D01*
+X0027842Y0215243D01*
+X0027132Y0215355D01*
+X0021220Y0215355D01*
+X0021220Y0211171D01*
+X0020451Y0211171D01*
+X0020451Y0210403D01*
+X0016271Y0210403D01*
+X0016379Y0209717D01*
+X0016602Y0209033D01*
+X0016928Y0208392D01*
+X0017351Y0207811D01*
+X0017859Y0207302D01*
+X0018441Y0206880D01*
+X0019082Y0206553D01*
+X0019766Y0206331D01*
+X0020451Y0206222D01*
+X0020451Y0210403D01*
+X0021220Y0210403D01*
+X0021220Y0206218D01*
+X0027132Y0206218D01*
+X0027842Y0206331D01*
+X0028526Y0206553D01*
+X0029167Y0206880D01*
+X0029749Y0207302D01*
+X0030787Y0208603D02*
+X0077138Y0208603D01*
+X0076659Y0209801D02*
+X0031242Y0209801D01*
+X0031118Y0212198D02*
+X0076818Y0212198D01*
+X0076659Y0211000D02*
+X0021220Y0211000D01*
+X0020451Y0211000D02*
+X0001800Y0211000D01*
+X0001800Y0212198D02*
+X0016490Y0212198D01*
+X0016379Y0211857D02*
+X0016602Y0212541D01*
+X0016928Y0213181D01*
+X0017351Y0213763D01*
+X0017859Y0214271D01*
+X0018441Y0214694D01*
+X0019082Y0215021D01*
+X0019766Y0215243D01*
+X0020451Y0215351D01*
+X0020451Y0211171D01*
+X0016271Y0211171D01*
+X0016379Y0211857D01*
+X0017085Y0213397D02*
+X0001800Y0213397D01*
+X0001800Y0214595D02*
+X0018305Y0214595D01*
+X0020451Y0214595D02*
+X0021220Y0214595D01*
+X0021220Y0213397D02*
+X0020451Y0213397D01*
+X0020451Y0212198D02*
+X0021220Y0212198D01*
+X0021220Y0209801D02*
+X0020451Y0209801D01*
+X0020451Y0208603D02*
+X0021220Y0208603D01*
+X0021220Y0207404D02*
+X0020451Y0207404D01*
+X0017757Y0207404D02*
+X0001800Y0207404D01*
+X0001800Y0208603D02*
+X0016821Y0208603D01*
+X0016366Y0209801D02*
+X0001800Y0209801D01*
+X0001800Y0215794D02*
+X0080409Y0215794D01*
+X0078326Y0214595D02*
+X0029303Y0214595D01*
+X0030523Y0213397D02*
+X0077314Y0213397D01*
+X0089183Y0215794D02*
+X0223015Y0215794D01*
+X0221731Y0216992D02*
+X0001800Y0216992D01*
+X0001800Y0227779D02*
+X0030490Y0227779D01*
+X0030763Y0228977D02*
+X0001800Y0228977D01*
+X0001800Y0230176D02*
+X0031298Y0230176D01*
+X0032251Y0231374D02*
+X0001800Y0231374D01*
+X0001800Y0239764D02*
+X0193262Y0239764D01*
+X0192355Y0240962D02*
+X0001800Y0240962D01*
+X0001800Y0242161D02*
+X0191859Y0242161D01*
+X0191800Y0243359D02*
+X0001800Y0243359D01*
+X0001800Y0244558D02*
+X0191910Y0244558D01*
+X0192407Y0245756D02*
+X0001800Y0245756D01*
+X0001800Y0246955D02*
+X0193387Y0246955D01*
+X0195460Y0248153D02*
+X0001800Y0248153D01*
+X0001800Y0249352D02*
+X0193674Y0249352D01*
+X0192475Y0250550D02*
+X0001800Y0250550D01*
+X0001800Y0251749D02*
+X0191800Y0251749D01*
+X0191800Y0252947D02*
+X0001800Y0252947D01*
+X0001800Y0254146D02*
+X0191800Y0254146D01*
+X0191800Y0255344D02*
+X0001800Y0255344D01*
+X0001800Y0256543D02*
+X0192975Y0256543D01*
+X0194174Y0257742D02*
+X0001800Y0257742D01*
+X0001800Y0201411D02*
+X0194280Y0201411D01*
+X0194543Y0201674D02*
+X0193422Y0200554D01*
+X0192816Y0199089D01*
+X0192816Y0197504D01*
+X0193422Y0196040D01*
+X0193800Y0195662D01*
+X0193800Y0167181D01*
+X0193422Y0166804D01*
+X0192816Y0165339D01*
+X0192816Y0163754D01*
+X0193422Y0162290D01*
+X0194543Y0161169D01*
+X0196007Y0160562D01*
+X0197593Y0160562D01*
+X0199057Y0161169D01*
+X0200178Y0162290D01*
+X0200784Y0163754D01*
+X0200784Y0165339D01*
+X0200178Y0166804D01*
+X0199800Y0167181D01*
+X0199800Y0195662D01*
+X0200178Y0196040D01*
+X0200784Y0197504D01*
+X0200784Y0199089D01*
+X0200178Y0200554D01*
+X0199057Y0201674D01*
+X0197593Y0202281D01*
+X0196007Y0202281D01*
+X0194543Y0201674D01*
+X0193281Y0200213D02*
+X0163018Y0200213D01*
+X0162807Y0200424D02*
+X0161343Y0201031D01*
+X0159757Y0201031D01*
+X0158293Y0200424D01*
+X0157172Y0199304D01*
+X0156566Y0197839D01*
+X0156566Y0196254D01*
+X0157172Y0194790D01*
+X0157550Y0194412D01*
+X0157550Y0175931D01*
+X0157172Y0175554D01*
+X0156566Y0174089D01*
+X0156566Y0172504D01*
+X0157172Y0171040D01*
+X0158293Y0169919D01*
+X0159757Y0169312D01*
+X0161343Y0169312D01*
+X0162807Y0169919D01*
+X0163928Y0171040D01*
+X0164534Y0172504D01*
+X0164534Y0174089D01*
+X0163928Y0175554D01*
+X0163550Y0175931D01*
+X0163550Y0194412D01*
+X0163928Y0194790D01*
+X0164534Y0196254D01*
+X0164534Y0197839D01*
+X0163928Y0199304D01*
+X0162807Y0200424D01*
+X0164047Y0199014D02*
+X0192816Y0199014D01*
+X0192816Y0197816D02*
+X0164534Y0197816D01*
+X0164534Y0196617D02*
+X0193183Y0196617D01*
+X0193800Y0195419D02*
+X0164188Y0195419D01*
+X0163550Y0194220D02*
+X0193800Y0194220D01*
+X0193800Y0193022D02*
+X0172571Y0193022D01*
+X0172807Y0192924D02*
+X0171343Y0193531D01*
+X0169757Y0193531D01*
+X0168293Y0192924D01*
+X0167172Y0191804D01*
+X0166566Y0190339D01*
+X0166566Y0188754D01*
+X0167172Y0187290D01*
+X0167550Y0186912D01*
+X0167550Y0175931D01*
+X0167172Y0175554D01*
+X0166566Y0174089D01*
+X0166566Y0172504D01*
+X0167172Y0171040D01*
+X0168293Y0169919D01*
+X0169757Y0169312D01*
+X0171343Y0169312D01*
+X0172807Y0169919D01*
+X0173928Y0171040D01*
+X0174534Y0172504D01*
+X0174534Y0174089D01*
+X0173928Y0175554D01*
+X0173550Y0175931D01*
+X0173550Y0186912D01*
+X0173928Y0187290D01*
+X0174534Y0188754D01*
+X0174534Y0190339D01*
+X0173928Y0191804D01*
+X0172807Y0192924D01*
+X0173908Y0191823D02*
+X0193800Y0191823D01*
+X0193800Y0190625D02*
+X0174416Y0190625D01*
+X0174534Y0189426D02*
+X0178284Y0189426D01*
+X0178293Y0189435D02*
+X0177172Y0188315D01*
+X0176566Y0186850D01*
+X0176566Y0185265D01*
+X0177172Y0183801D01*
+X0177550Y0183423D01*
+X0177550Y0175931D01*
+X0177172Y0175554D01*
+X0176566Y0174089D01*
+X0176566Y0172504D01*
+X0177172Y0171040D01*
+X0178293Y0169919D01*
+X0179757Y0169312D01*
+X0181343Y0169312D01*
+X0182807Y0169919D01*
+X0183928Y0171040D01*
+X0184534Y0172504D01*
+X0184534Y0174089D01*
+X0183928Y0175554D01*
+X0183550Y0175931D01*
+X0183550Y0183423D01*
+X0183928Y0183801D01*
+X0184534Y0185265D01*
+X0184534Y0186850D01*
+X0183928Y0188315D01*
+X0182807Y0189435D01*
+X0181343Y0190042D01*
+X0179757Y0190042D01*
+X0178293Y0189435D01*
+X0177136Y0188228D02*
+X0174316Y0188228D01*
+X0173667Y0187029D02*
+X0176640Y0187029D01*
+X0176566Y0185831D02*
+X0173550Y0185831D01*
+X0173550Y0184632D02*
+X0176828Y0184632D01*
+X0177539Y0183434D02*
+X0173550Y0183434D01*
+X0173550Y0182235D02*
+X0177550Y0182235D01*
+X0177550Y0181037D02*
+X0173550Y0181037D01*
+X0173550Y0179838D02*
+X0177550Y0179838D01*
+X0177550Y0178640D02*
+X0173550Y0178640D01*
+X0173550Y0177441D02*
+X0177550Y0177441D01*
+X0177550Y0176243D02*
+X0173550Y0176243D01*
+X0174139Y0175044D02*
+X0176961Y0175044D01*
+X0176566Y0173846D02*
+X0174534Y0173846D01*
+X0174534Y0172647D02*
+X0176566Y0172647D01*
+X0177003Y0171449D02*
+X0174097Y0171449D01*
+X0173138Y0170250D02*
+X0177962Y0170250D01*
+X0183138Y0170250D02*
+X0193800Y0170250D01*
+X0193800Y0169052D02*
+X0001800Y0169052D01*
+X0001800Y0170250D02*
+X0157962Y0170250D01*
+X0157003Y0171449D02*
+X0001800Y0171449D01*
+X0001800Y0172647D02*
+X0156566Y0172647D01*
+X0156566Y0173846D02*
+X0001800Y0173846D01*
+X0001800Y0175044D02*
+X0156961Y0175044D01*
+X0157550Y0176243D02*
+X0001800Y0176243D01*
+X0001800Y0177441D02*
+X0157550Y0177441D01*
+X0157550Y0178640D02*
+X0001800Y0178640D01*
+X0001800Y0179838D02*
+X0157550Y0179838D01*
+X0157550Y0181037D02*
+X0001800Y0181037D01*
+X0001800Y0182235D02*
+X0157550Y0182235D01*
+X0157550Y0183434D02*
+X0001800Y0183434D01*
+X0001800Y0184632D02*
+X0157550Y0184632D01*
+X0157550Y0185831D02*
+X0001800Y0185831D01*
+X0001800Y0187029D02*
+X0157550Y0187029D01*
+X0157550Y0188228D02*
+X0001800Y0188228D01*
+X0001800Y0189426D02*
+X0157550Y0189426D01*
+X0157550Y0190625D02*
+X0001800Y0190625D01*
+X0001800Y0191823D02*
+X0157550Y0191823D01*
+X0157550Y0193022D02*
+X0001800Y0193022D01*
+X0001800Y0194220D02*
+X0157550Y0194220D01*
+X0156912Y0195419D02*
+X0001800Y0195419D01*
+X0001800Y0196617D02*
+X0156566Y0196617D01*
+X0156566Y0197816D02*
+X0001800Y0197816D01*
+X0001800Y0199014D02*
+X0157053Y0199014D01*
+X0158082Y0200213D02*
+X0001800Y0200213D01*
+X0001800Y0167853D02*
+X0193800Y0167853D01*
+X0193361Y0166655D02*
+X0001800Y0166655D01*
+X0001800Y0165456D02*
+X0192864Y0165456D01*
+X0192816Y0164258D02*
+X0001800Y0164258D01*
+X0001800Y0163059D02*
+X0193104Y0163059D01*
+X0193852Y0161861D02*
+X0001800Y0161861D01*
+X0001800Y0160662D02*
+X0195767Y0160662D01*
+X0197833Y0160662D02*
+X0205631Y0160662D01*
+X0205578Y0160536D02*
+X0205578Y0158558D01*
+X0206335Y0156730D01*
+X0207734Y0155332D01*
+X0209561Y0154575D01*
+X0217082Y0154575D01*
+X0218910Y0155332D01*
+X0220308Y0156730D01*
+X0221065Y0158558D01*
+X0221065Y0160536D01*
+X0220308Y0162363D01*
+X0218910Y0163761D01*
+X0217082Y0164518D01*
+X0209561Y0164518D01*
+X0207734Y0163761D01*
+X0206335Y0162363D01*
+X0205578Y0160536D01*
+X0205578Y0159464D02*
+X0001800Y0159464D01*
+X0001800Y0158265D02*
+X0205700Y0158265D01*
+X0206196Y0157067D02*
+X0001800Y0157067D01*
+X0001800Y0155868D02*
+X0207198Y0155868D01*
+X0207734Y0153761D02*
+X0206335Y0152363D01*
+X0205578Y0150536D01*
+X0205578Y0148558D01*
+X0206335Y0146730D01*
+X0207734Y0145332D01*
+X0209561Y0144575D01*
+X0217082Y0144575D01*
+X0218910Y0145332D01*
+X0220308Y0146730D01*
+X0221065Y0148558D01*
+X0221065Y0150536D01*
+X0220308Y0152363D01*
+X0218910Y0153761D01*
+X0217082Y0154518D01*
+X0209561Y0154518D01*
+X0207734Y0153761D01*
+X0207443Y0153471D02*
+X0001800Y0153471D01*
+X0001800Y0152273D02*
+X0206298Y0152273D01*
+X0205801Y0151074D02*
+X0001800Y0151074D01*
+X0001800Y0149875D02*
+X0205578Y0149875D01*
+X0205578Y0148677D02*
+X0001800Y0148677D01*
+X0001800Y0147478D02*
+X0206025Y0147478D01*
+X0206786Y0146280D02*
+X0001800Y0146280D01*
+X0001800Y0145081D02*
+X0208338Y0145081D01*
+X0208027Y0143883D02*
+X0001800Y0143883D01*
+X0001800Y0142684D02*
+X0206657Y0142684D01*
+X0206335Y0142363D02*
+X0205578Y0140536D01*
+X0205578Y0138558D01*
+X0206335Y0136730D01*
+X0207734Y0135332D01*
+X0209561Y0134575D01*
+X0217082Y0134575D01*
+X0218910Y0135332D01*
+X0220308Y0136730D01*
+X0221065Y0138558D01*
+X0221065Y0140536D01*
+X0220308Y0142363D01*
+X0218910Y0143761D01*
+X0217082Y0144518D01*
+X0209561Y0144518D01*
+X0207734Y0143761D01*
+X0206335Y0142363D01*
+X0205972Y0141486D02*
+X0001800Y0141486D01*
+X0001800Y0140287D02*
+X0205578Y0140287D01*
+X0205578Y0139089D02*
+X0001800Y0139089D01*
+X0001800Y0137890D02*
+X0205855Y0137890D01*
+X0206374Y0136692D02*
+X0001800Y0136692D01*
+X0001800Y0135493D02*
+X0207572Y0135493D01*
+X0207734Y0133761D02*
+X0206335Y0132363D01*
+X0205578Y0130536D01*
+X0205578Y0128558D01*
+X0206335Y0126730D01*
+X0207734Y0125332D01*
+X0209561Y0124575D01*
+X0217082Y0124575D01*
+X0218910Y0125332D01*
+X0220308Y0126730D01*
+X0221065Y0128558D01*
+X0221065Y0130536D01*
+X0220308Y0132363D01*
+X0218910Y0133761D01*
+X0217082Y0134518D01*
+X0209561Y0134518D01*
+X0207734Y0133761D01*
+X0207069Y0133096D02*
+X0001800Y0133096D01*
+X0001800Y0131898D02*
+X0206143Y0131898D01*
+X0205646Y0130699D02*
+X0001800Y0130699D01*
+X0001800Y0129501D02*
+X0129081Y0129501D01*
+X0129757Y0129781D02*
+X0128293Y0129174D01*
+X0127172Y0128054D01*
+X0126566Y0126589D01*
+X0126566Y0125004D01*
+X0127172Y0123540D01*
+X0128293Y0122419D01*
+X0129757Y0121812D01*
+X0131343Y0121812D01*
+X0132807Y0122419D01*
+X0133059Y0122671D01*
+X0180902Y0120337D01*
+X0196740Y0110834D01*
+X0197172Y0109790D01*
+X0198293Y0108669D01*
+X0199757Y0108062D01*
+X0201343Y0108062D01*
+X0202807Y0108669D01*
+X0203928Y0109790D01*
+X0204534Y0111254D01*
+X0204534Y0112839D01*
+X0203928Y0114304D01*
+X0202807Y0115424D01*
+X0201343Y0116031D01*
+X0199757Y0116031D01*
+X0199747Y0116027D01*
+X0183724Y0125641D01*
+X0183621Y0125754D01*
+X0183216Y0125946D01*
+X0182832Y0126176D01*
+X0182680Y0126199D01*
+X0182542Y0126264D01*
+X0182095Y0126286D01*
+X0181651Y0126352D01*
+X0181503Y0126315D01*
+X0133316Y0128665D01*
+X0132807Y0129174D01*
+X0131343Y0129781D01*
+X0129757Y0129781D01*
+X0132019Y0129501D02*
+X0205578Y0129501D01*
+X0205684Y0128302D02*
+X0140758Y0128302D01*
+X0140460Y0122310D02*
+X0132543Y0122310D01*
+X0128557Y0122310D02*
+X0111436Y0122310D01*
+X0111428Y0122290D02*
+X0112034Y0123754D01*
+X0112034Y0125339D01*
+X0111428Y0126804D01*
+X0110307Y0127924D01*
+X0108843Y0128531D01*
+X0107257Y0128531D01*
+X0105793Y0127924D01*
+X0104672Y0126804D01*
+X0104066Y0125339D01*
+X0104066Y0123754D01*
+X0104672Y0122290D01*
+X0105050Y0121912D01*
+X0105050Y0102018D01*
+X0103039Y0102018D01*
+X0101212Y0101261D01*
+X0099814Y0099863D01*
+X0099057Y0098036D01*
+X0099057Y0096058D01*
+X0099814Y0094230D01*
+X0101212Y0092832D01*
+X0103039Y0092075D01*
+X0110561Y0092075D01*
+X0112388Y0092832D01*
+X0113786Y0094230D01*
+X0114543Y0096058D01*
+X0114543Y0098036D01*
+X0113786Y0099863D01*
+X0112388Y0101261D01*
+X0111050Y0101816D01*
+X0111050Y0121912D01*
+X0111428Y0122290D01*
+X0111050Y0121111D02*
+X0165029Y0121111D01*
+X0165328Y0127104D02*
+X0206181Y0127104D01*
+X0207160Y0125905D02*
+X0183301Y0125905D01*
+X0185281Y0124707D02*
+X0209243Y0124707D01*
+X0209561Y0124518D02*
+X0207734Y0123761D01*
+X0206335Y0122363D01*
+X0205578Y0120536D01*
+X0205578Y0118558D01*
+X0206335Y0116730D01*
+X0207734Y0115332D01*
+X0209561Y0114575D01*
+X0217082Y0114575D01*
+X0218910Y0115332D01*
+X0220308Y0116730D01*
+X0221065Y0118558D01*
+X0221065Y0120536D01*
+X0220308Y0122363D01*
+X0218910Y0123761D01*
+X0217082Y0124518D01*
+X0209561Y0124518D01*
+X0207481Y0123508D02*
+X0187278Y0123508D01*
+X0189276Y0122310D02*
+X0206313Y0122310D01*
+X0205817Y0121111D02*
+X0191273Y0121111D01*
+X0193271Y0119913D02*
+X0205578Y0119913D01*
+X0205578Y0118714D02*
+X0195268Y0118714D01*
+X0197266Y0117516D02*
+X0206010Y0117516D01*
+X0206749Y0116317D02*
+X0199263Y0116317D01*
+X0203113Y0115119D02*
+X0208249Y0115119D01*
+X0208117Y0113920D02*
+X0204087Y0113920D01*
+X0204534Y0112722D02*
+X0206694Y0112722D01*
+X0206335Y0112363D02*
+X0205578Y0110536D01*
+X0205578Y0108558D01*
+X0206335Y0106730D01*
+X0207734Y0105332D01*
+X0209561Y0104575D01*
+X0217082Y0104575D01*
+X0218910Y0105332D01*
+X0220308Y0106730D01*
+X0221065Y0108558D01*
+X0221065Y0110536D01*
+X0220308Y0112363D01*
+X0218910Y0113761D01*
+X0217082Y0114518D01*
+X0209561Y0114518D01*
+X0207734Y0113761D01*
+X0206335Y0112363D01*
+X0205987Y0111523D02*
+X0204534Y0111523D01*
+X0204149Y0110325D02*
+X0205578Y0110325D01*
+X0205578Y0109126D02*
+X0203264Y0109126D01*
+X0205839Y0107928D02*
+X0111050Y0107928D01*
+X0111050Y0109126D02*
+X0197836Y0109126D01*
+X0196951Y0110325D02*
+X0111050Y0110325D01*
+X0111050Y0111523D02*
+X0195592Y0111523D01*
+X0193594Y0112722D02*
+X0111050Y0112722D01*
+X0111050Y0113920D02*
+X0191597Y0113920D01*
+X0189599Y0115119D02*
+X0111050Y0115119D01*
+X0111050Y0116317D02*
+X0187602Y0116317D01*
+X0185604Y0117516D02*
+X0111050Y0117516D01*
+X0111050Y0118714D02*
+X0183607Y0118714D01*
+X0181609Y0119913D02*
+X0111050Y0119913D01*
+X0111932Y0123508D02*
+X0127204Y0123508D01*
+X0126689Y0124707D02*
+X0112034Y0124707D01*
+X0111800Y0125905D02*
+X0126566Y0125905D01*
+X0126779Y0127104D02*
+X0111127Y0127104D01*
+X0109395Y0128302D02*
+X0127421Y0128302D01*
+X0106705Y0128302D02*
+X0096156Y0128302D01*
+X0096500Y0127958D02*
+X0095211Y0129247D01*
+X0068389Y0129247D01*
+X0067100Y0127958D01*
+X0067100Y0066135D01*
+X0068389Y0064847D01*
+X0095211Y0064847D01*
+X0096500Y0066135D01*
+X0096500Y0127958D01*
+X0096500Y0127104D02*
+X0104973Y0127104D01*
+X0104300Y0125905D02*
+X0096500Y0125905D01*
+X0096500Y0124707D02*
+X0104066Y0124707D01*
+X0104168Y0123508D02*
+X0096500Y0123508D01*
+X0096500Y0122310D02*
+X0104664Y0122310D01*
+X0105050Y0121111D02*
+X0096500Y0121111D01*
+X0096500Y0119913D02*
+X0105050Y0119913D01*
+X0105050Y0118714D02*
+X0096500Y0118714D01*
+X0096500Y0117516D02*
+X0105050Y0117516D01*
+X0105050Y0116317D02*
+X0096500Y0116317D01*
+X0096500Y0115119D02*
+X0105050Y0115119D01*
+X0105050Y0113920D02*
+X0096500Y0113920D01*
+X0096500Y0112722D02*
+X0105050Y0112722D01*
+X0105050Y0111523D02*
+X0096500Y0111523D01*
+X0096500Y0110325D02*
+X0105050Y0110325D01*
+X0105050Y0109126D02*
+X0096500Y0109126D01*
+X0096500Y0107928D02*
+X0105050Y0107928D01*
+X0105050Y0106729D02*
+X0096500Y0106729D01*
+X0096500Y0105531D02*
+X0105050Y0105531D01*
+X0105050Y0104332D02*
+X0096500Y0104332D01*
+X0096500Y0103134D02*
+X0105050Y0103134D01*
+X0102838Y0101935D02*
+X0096500Y0101935D01*
+X0096500Y0100737D02*
+X0100687Y0100737D01*
+X0099679Y0099538D02*
+X0096500Y0099538D01*
+X0096500Y0098340D02*
+X0099183Y0098340D01*
+X0099057Y0097141D02*
+X0096500Y0097141D01*
+X0096500Y0095942D02*
+X0099104Y0095942D01*
+X0099601Y0094744D02*
+X0096500Y0094744D01*
+X0096500Y0093545D02*
+X0100499Y0093545D01*
+X0102383Y0092347D02*
+X0096500Y0092347D01*
+X0096500Y0091148D02*
+X0101099Y0091148D01*
+X0101212Y0091261D02*
+X0099814Y0089863D01*
+X0099057Y0088036D01*
+X0099057Y0086058D01*
+X0099814Y0084230D01*
+X0101212Y0082832D01*
+X0103039Y0082075D01*
+X0110561Y0082075D01*
+X0112388Y0082832D01*
+X0113786Y0084230D01*
+X0114543Y0086058D01*
+X0114543Y0088036D01*
+X0113786Y0089863D01*
+X0112388Y0091261D01*
+X0110561Y0092018D01*
+X0103039Y0092018D01*
+X0101212Y0091261D01*
+X0099901Y0089950D02*
+X0096500Y0089950D01*
+X0096500Y0088751D02*
+X0099353Y0088751D01*
+X0099057Y0087553D02*
+X0096500Y0087553D01*
+X0096500Y0086354D02*
+X0099057Y0086354D01*
+X0099430Y0085156D02*
+X0096500Y0085156D01*
+X0096500Y0083957D02*
+X0100087Y0083957D01*
+X0101389Y0082759D02*
+X0096500Y0082759D01*
+X0096500Y0081560D02*
+X0101934Y0081560D01*
+X0101212Y0081261D02*
+X0099814Y0079863D01*
+X0099057Y0078036D01*
+X0099057Y0076058D01*
+X0099814Y0074230D01*
+X0101212Y0072832D01*
+X0103039Y0072075D01*
+X0110561Y0072075D01*
+X0112388Y0072832D01*
+X0113786Y0074230D01*
+X0114543Y0076058D01*
+X0114543Y0078036D01*
+X0113786Y0079863D01*
+X0112388Y0081261D01*
+X0110561Y0082018D01*
+X0103039Y0082018D01*
+X0101212Y0081261D01*
+X0100313Y0080362D02*
+X0096500Y0080362D01*
+X0096500Y0079163D02*
+X0099524Y0079163D01*
+X0099057Y0077965D02*
+X0096500Y0077965D01*
+X0096500Y0076766D02*
+X0099057Y0076766D01*
+X0099260Y0075568D02*
+X0096500Y0075568D01*
+X0096500Y0074369D02*
+X0099756Y0074369D01*
+X0100873Y0073171D02*
+X0096500Y0073171D01*
+X0096500Y0071972D02*
+X0102928Y0071972D01*
+X0103039Y0072018D02*
+X0101212Y0071261D01*
+X0099814Y0069863D01*
+X0099057Y0068036D01*
+X0099057Y0066058D01*
+X0099814Y0064230D01*
+X0101212Y0062832D01*
+X0103039Y0062075D01*
+X0110561Y0062075D01*
+X0112388Y0062832D01*
+X0113786Y0064230D01*
+X0114543Y0066058D01*
+X0114543Y0068036D01*
+X0113786Y0069863D01*
+X0112388Y0071261D01*
+X0110561Y0072018D01*
+X0103039Y0072018D01*
+X0100724Y0070774D02*
+X0096500Y0070774D01*
+X0096500Y0069575D02*
+X0099694Y0069575D01*
+X0099198Y0068377D02*
+X0096500Y0068377D01*
+X0096500Y0067178D02*
+X0099057Y0067178D01*
+X0099089Y0065980D02*
+X0096344Y0065980D01*
+X0099585Y0064781D02*
+X0001800Y0064781D01*
+X0001800Y0063583D02*
+X0100461Y0063583D01*
+X0102293Y0062384D02*
+X0001800Y0062384D01*
+X0001800Y0061186D02*
+X0101136Y0061186D01*
+X0101212Y0061261D02*
+X0099814Y0059863D01*
+X0099057Y0058036D01*
+X0099057Y0056058D01*
+X0099814Y0054230D01*
+X0101212Y0052832D01*
+X0103039Y0052075D01*
+X0110561Y0052075D01*
+X0112388Y0052832D01*
+X0113786Y0054230D01*
+X0114543Y0056058D01*
+X0114543Y0058036D01*
+X0113786Y0059863D01*
+X0112388Y0061261D01*
+X0110561Y0062018D01*
+X0103039Y0062018D01*
+X0101212Y0061261D01*
+X0099938Y0059987D02*
+X0089894Y0059987D01*
+X0090692Y0059657D02*
+X0088793Y0060444D01*
+X0080799Y0060444D01*
+X0078900Y0059657D01*
+X0077446Y0058203D01*
+X0076659Y0056303D01*
+X0076659Y0054247D01*
+X0077446Y0052347D01*
+X0078900Y0050893D01*
+X0080799Y0050107D01*
+X0088793Y0050107D01*
+X0090692Y0050893D01*
+X0092146Y0052347D01*
+X0092933Y0054247D01*
+X0092933Y0056303D01*
+X0092146Y0058203D01*
+X0090692Y0059657D01*
+X0091560Y0058789D02*
+X0099369Y0058789D01*
+X0099057Y0057590D02*
+X0092400Y0057590D01*
+X0092896Y0056392D02*
+X0099057Y0056392D01*
+X0099415Y0055193D02*
+X0092933Y0055193D01*
+X0092829Y0053995D02*
+X0100049Y0053995D01*
+X0101299Y0052796D02*
+X0092332Y0052796D01*
+X0091396Y0051598D02*
+X0206018Y0051598D01*
+X0206335Y0052363D02*
+X0205578Y0050536D01*
+X0205578Y0048558D01*
+X0206335Y0046730D01*
+X0207734Y0045332D01*
+X0209561Y0044575D01*
+X0217082Y0044575D01*
+X0218910Y0045332D01*
+X0220308Y0046730D01*
+X0221065Y0048558D01*
+X0221065Y0050536D01*
+X0220308Y0052363D01*
+X0218910Y0053761D01*
+X0217082Y0054518D01*
+X0209561Y0054518D01*
+X0207734Y0053761D01*
+X0206335Y0052363D01*
+X0206768Y0052796D02*
+X0190637Y0052796D01*
+X0190595Y0052783D02*
+X0191250Y0052995D01*
+X0191863Y0053308D01*
+X0192420Y0053712D01*
+X0192906Y0054199D01*
+X0193311Y0054755D01*
+X0193623Y0055369D01*
+X0193836Y0056023D01*
+X0193943Y0056703D01*
+X0193943Y0056761D01*
+X0187086Y0056761D01*
+X0187086Y0057333D01*
+X0186514Y0057333D01*
+X0186514Y0061418D01*
+X0183684Y0061418D01*
+X0183005Y0061311D01*
+X0182350Y0061098D01*
+X0181737Y0060786D01*
+X0181180Y0060381D01*
+X0180694Y0059895D01*
+X0180289Y0059338D01*
+X0179977Y0058725D01*
+X0179764Y0058070D01*
+X0179657Y0057391D01*
+X0179657Y0057333D01*
+X0186514Y0057333D01*
+X0186514Y0056761D01*
+X0179657Y0056761D01*
+X0179657Y0056703D01*
+X0179764Y0056023D01*
+X0179977Y0055369D01*
+X0180289Y0054755D01*
+X0180694Y0054199D01*
+X0181180Y0053712D01*
+X0181737Y0053308D01*
+X0182350Y0052995D01*
+X0183005Y0052783D01*
+X0183684Y0052675D01*
+X0186514Y0052675D01*
+X0186514Y0056761D01*
+X0187086Y0056761D01*
+X0187086Y0052675D01*
+X0189916Y0052675D01*
+X0190595Y0052783D01*
+X0190595Y0051311D02*
+X0189916Y0051418D01*
+X0187086Y0051418D01*
+X0187086Y0047333D01*
+X0186514Y0047333D01*
+X0186514Y0051418D01*
+X0183684Y0051418D01*
+X0183005Y0051311D01*
+X0182350Y0051098D01*
+X0181737Y0050786D01*
+X0181180Y0050381D01*
+X0180694Y0049895D01*
+X0180289Y0049338D01*
+X0179977Y0048725D01*
+X0179764Y0048070D01*
+X0179657Y0047391D01*
+X0179657Y0047333D01*
+X0186514Y0047333D01*
+X0186514Y0046761D01*
+X0179657Y0046761D01*
+X0179657Y0046703D01*
+X0179764Y0046023D01*
+X0179977Y0045369D01*
+X0180289Y0044755D01*
+X0180694Y0044199D01*
+X0181180Y0043712D01*
+X0181737Y0043308D01*
+X0182350Y0042995D01*
+X0183005Y0042783D01*
+X0183684Y0042675D01*
+X0186514Y0042675D01*
+X0186514Y0046761D01*
+X0187086Y0046761D01*
+X0187086Y0047333D01*
+X0193943Y0047333D01*
+X0193943Y0047391D01*
+X0193836Y0048070D01*
+X0193623Y0048725D01*
+X0193311Y0049338D01*
+X0192906Y0049895D01*
+X0192420Y0050381D01*
+X0191863Y0050786D01*
+X0191250Y0051098D01*
+X0190595Y0051311D01*
+X0192395Y0050399D02*
+X0205578Y0050399D01*
+X0205578Y0049201D02*
+X0193381Y0049201D01*
+X0193846Y0048002D02*
+X0205809Y0048002D01*
+X0206305Y0046804D02*
+X0187086Y0046804D01*
+X0187086Y0046761D02*
+X0193943Y0046761D01*
+X0193943Y0046703D01*
+X0193836Y0046023D01*
+X0193623Y0045369D01*
+X0193311Y0044755D01*
+X0192906Y0044199D01*
+X0192420Y0043712D01*
+X0191863Y0043308D01*
+X0191250Y0042995D01*
+X0190595Y0042783D01*
+X0189916Y0042675D01*
+X0187086Y0042675D01*
+X0187086Y0046761D01*
+X0186514Y0046804D02*
+X0107086Y0046804D01*
+X0107086Y0046761D02*
+X0107086Y0047333D01*
+X0106514Y0047333D01*
+X0106514Y0051418D01*
+X0103684Y0051418D01*
+X0103005Y0051311D01*
+X0102350Y0051098D01*
+X0101737Y0050786D01*
+X0101180Y0050381D01*
+X0100694Y0049895D01*
+X0100289Y0049338D01*
+X0099977Y0048725D01*
+X0099764Y0048070D01*
+X0099657Y0047391D01*
+X0099657Y0047333D01*
+X0106514Y0047333D01*
+X0106514Y0046761D01*
+X0099657Y0046761D01*
+X0099657Y0046703D01*
+X0099764Y0046023D01*
+X0099977Y0045369D01*
+X0100289Y0044755D01*
+X0100694Y0044199D01*
+X0101180Y0043712D01*
+X0101737Y0043308D01*
+X0102350Y0042995D01*
+X0103005Y0042783D01*
+X0103684Y0042675D01*
+X0106514Y0042675D01*
+X0106514Y0046761D01*
+X0107086Y0046761D01*
+X0113943Y0046761D01*
+X0113943Y0046703D01*
+X0113836Y0046023D01*
+X0113623Y0045369D01*
+X0113311Y0044755D01*
+X0112906Y0044199D01*
+X0112420Y0043712D01*
+X0111863Y0043308D01*
+X0111250Y0042995D01*
+X0110595Y0042783D01*
+X0109916Y0042675D01*
+X0107086Y0042675D01*
+X0107086Y0046761D01*
+X0107086Y0047333D02*
+X0113943Y0047333D01*
+X0113943Y0047391D01*
+X0113836Y0048070D01*
+X0113623Y0048725D01*
+X0113311Y0049338D01*
+X0112906Y0049895D01*
+X0112420Y0050381D01*
+X0111863Y0050786D01*
+X0111250Y0051098D01*
+X0110595Y0051311D01*
+X0109916Y0051418D01*
+X0107086Y0051418D01*
+X0107086Y0047333D01*
+X0107086Y0048002D02*
+X0106514Y0048002D01*
+X0106514Y0046804D02*
+X0001800Y0046804D01*
+X0001800Y0048002D02*
+X0099754Y0048002D01*
+X0100219Y0049201D02*
+X0001800Y0049201D01*
+X0001800Y0050399D02*
+X0080093Y0050399D01*
+X0078196Y0051598D02*
+X0029483Y0051598D01*
+X0029749Y0051790D02*
+X0030257Y0052299D01*
+X0030680Y0052881D01*
+X0031006Y0053521D01*
+X0031228Y0054205D01*
+X0031337Y0054891D01*
+X0021220Y0054891D01*
+X0021220Y0055659D01*
+X0031337Y0055659D01*
+X0031228Y0056345D01*
+X0031006Y0057029D01*
+X0030680Y0057669D01*
+X0030257Y0058251D01*
+X0029749Y0058760D01*
+X0029167Y0059182D01*
+X0028526Y0059509D01*
+X0027842Y0059731D01*
+X0027132Y0059844D01*
+X0021220Y0059844D01*
+X0021220Y0055659D01*
+X0020451Y0055659D01*
+X0020451Y0054891D01*
+X0016271Y0054891D01*
+X0016379Y0054205D01*
+X0016602Y0053521D01*
+X0016928Y0052881D01*
+X0017351Y0052299D01*
+X0017859Y0051790D01*
+X0018441Y0051368D01*
+X0019082Y0051041D01*
+X0019766Y0050819D01*
+X0020451Y0050710D01*
+X0020451Y0054891D01*
+X0021220Y0054891D01*
+X0021220Y0050707D01*
+X0027132Y0050707D01*
+X0027842Y0050819D01*
+X0028526Y0051041D01*
+X0029167Y0051368D01*
+X0029749Y0051790D01*
+X0030618Y0052796D02*
+X0077260Y0052796D01*
+X0076764Y0053995D02*
+X0031160Y0053995D01*
+X0031213Y0056392D02*
+X0076696Y0056392D01*
+X0076659Y0055193D02*
+X0021220Y0055193D01*
+X0020451Y0055193D02*
+X0001800Y0055193D01*
+X0001800Y0053995D02*
+X0016448Y0053995D01*
+X0016990Y0052796D02*
+X0001800Y0052796D01*
+X0001800Y0051598D02*
+X0018125Y0051598D01*
+X0020451Y0051598D02*
+X0021220Y0051598D01*
+X0021220Y0052796D02*
+X0020451Y0052796D01*
+X0020451Y0053995D02*
+X0021220Y0053995D01*
+X0020451Y0055659D02*
+X0016271Y0055659D01*
+X0016379Y0056345D01*
+X0016602Y0057029D01*
+X0016928Y0057669D01*
+X0017351Y0058251D01*
+X0017859Y0058760D01*
+X0018441Y0059182D01*
+X0019082Y0059509D01*
+X0019766Y0059731D01*
+X0020451Y0059840D01*
+X0020451Y0055659D01*
+X0020451Y0056392D02*
+X0021220Y0056392D01*
+X0021220Y0057590D02*
+X0020451Y0057590D01*
+X0020451Y0058789D02*
+X0021220Y0058789D01*
+X0017899Y0058789D02*
+X0001800Y0058789D01*
+X0001800Y0059987D02*
+X0079698Y0059987D01*
+X0078032Y0058789D02*
+X0029709Y0058789D01*
+X0030720Y0057590D02*
+X0077192Y0057590D01*
+X0067256Y0065980D02*
+X0001800Y0065980D01*
+X0001800Y0067178D02*
+X0067100Y0067178D01*
+X0067100Y0068377D02*
+X0001800Y0068377D01*
+X0001800Y0069575D02*
+X0067100Y0069575D01*
+X0067100Y0070774D02*
+X0001800Y0070774D01*
+X0001800Y0071972D02*
+X0067100Y0071972D01*
+X0067100Y0073171D02*
+X0001800Y0073171D01*
+X0001800Y0074369D02*
+X0067100Y0074369D01*
+X0067100Y0075568D02*
+X0001800Y0075568D01*
+X0001800Y0076766D02*
+X0067100Y0076766D01*
+X0067100Y0077965D02*
+X0001800Y0077965D01*
+X0001800Y0079163D02*
+X0067100Y0079163D01*
+X0067100Y0080362D02*
+X0001800Y0080362D01*
+X0001800Y0081560D02*
+X0067100Y0081560D01*
+X0067100Y0082759D02*
+X0001800Y0082759D01*
+X0001800Y0083957D02*
+X0067100Y0083957D01*
+X0067100Y0085156D02*
+X0001800Y0085156D01*
+X0001800Y0086354D02*
+X0067100Y0086354D01*
+X0067100Y0087553D02*
+X0001800Y0087553D01*
+X0001800Y0088751D02*
+X0067100Y0088751D01*
+X0067100Y0089950D02*
+X0001800Y0089950D01*
+X0001800Y0091148D02*
+X0067100Y0091148D01*
+X0067100Y0092347D02*
+X0001800Y0092347D01*
+X0001800Y0093545D02*
+X0067100Y0093545D01*
+X0067100Y0094744D02*
+X0001800Y0094744D01*
+X0001800Y0095942D02*
+X0067100Y0095942D01*
+X0067100Y0097141D02*
+X0001800Y0097141D01*
+X0001800Y0098340D02*
+X0067100Y0098340D01*
+X0067100Y0099538D02*
+X0001800Y0099538D01*
+X0001800Y0100737D02*
+X0067100Y0100737D01*
+X0067100Y0101935D02*
+X0001800Y0101935D01*
+X0001800Y0103134D02*
+X0067100Y0103134D01*
+X0067100Y0104332D02*
+X0001800Y0104332D01*
+X0001800Y0105531D02*
+X0067100Y0105531D01*
+X0067100Y0106729D02*
+X0001800Y0106729D01*
+X0001800Y0107928D02*
+X0067100Y0107928D01*
+X0067100Y0109126D02*
+X0001800Y0109126D01*
+X0001800Y0110325D02*
+X0067100Y0110325D01*
+X0067100Y0111523D02*
+X0001800Y0111523D01*
+X0001800Y0112722D02*
+X0067100Y0112722D01*
+X0067100Y0113920D02*
+X0001800Y0113920D01*
+X0001800Y0115119D02*
+X0067100Y0115119D01*
+X0067100Y0116317D02*
+X0001800Y0116317D01*
+X0001800Y0117516D02*
+X0067100Y0117516D01*
+X0067100Y0118714D02*
+X0001800Y0118714D01*
+X0001800Y0119913D02*
+X0067100Y0119913D01*
+X0067100Y0121111D02*
+X0001800Y0121111D01*
+X0001800Y0122310D02*
+X0067100Y0122310D01*
+X0067100Y0123508D02*
+X0001800Y0123508D01*
+X0001800Y0124707D02*
+X0067100Y0124707D01*
+X0067100Y0125905D02*
+X0001800Y0125905D01*
+X0001800Y0127104D02*
+X0067100Y0127104D01*
+X0067444Y0128302D02*
+X0001800Y0128302D01*
+X0001800Y0134295D02*
+X0209022Y0134295D01*
+X0217622Y0134295D02*
+X0263478Y0134295D01*
+X0264018Y0134518D02*
+X0262190Y0133761D01*
+X0260792Y0132363D01*
+X0260035Y0130536D01*
+X0260035Y0128558D01*
+X0260792Y0126730D01*
+X0262190Y0125332D01*
+X0264018Y0124575D01*
+X0271539Y0124575D01*
+X0273366Y0125332D01*
+X0274765Y0126730D01*
+X0275522Y0128558D01*
+X0275522Y0130536D01*
+X0274765Y0132363D01*
+X0273366Y0133761D01*
+X0271539Y0134518D01*
+X0264018Y0134518D01*
+X0264018Y0134575D02*
+X0262190Y0135332D01*
+X0260792Y0136730D01*
+X0260035Y0138558D01*
+X0260035Y0140536D01*
+X0260792Y0142363D01*
+X0262190Y0143761D01*
+X0264018Y0144518D01*
+X0271539Y0144518D01*
+X0273366Y0143761D01*
+X0274765Y0142363D01*
+X0275522Y0140536D01*
+X0275522Y0138558D01*
+X0274765Y0136730D01*
+X0273366Y0135332D01*
+X0271539Y0134575D01*
+X0264018Y0134575D01*
+X0262029Y0135493D02*
+X0219071Y0135493D01*
+X0220269Y0136692D02*
+X0260831Y0136692D01*
+X0260311Y0137890D02*
+X0220788Y0137890D01*
+X0221065Y0139089D02*
+X0260035Y0139089D01*
+X0260035Y0140287D02*
+X0221065Y0140287D01*
+X0220671Y0141486D02*
+X0260429Y0141486D01*
+X0261113Y0142684D02*
+X0219987Y0142684D01*
+X0218616Y0143883D02*
+X0262484Y0143883D01*
+X0262795Y0145081D02*
+X0218305Y0145081D01*
+X0219858Y0146280D02*
+X0261242Y0146280D01*
+X0260792Y0146730D02*
+X0262190Y0145332D01*
+X0264018Y0144575D01*
+X0271539Y0144575D01*
+X0273366Y0145332D01*
+X0274765Y0146730D01*
+X0275522Y0148558D01*
+X0275522Y0150536D01*
+X0274765Y0152363D01*
+X0273366Y0153761D01*
+X0271539Y0154518D01*
+X0264018Y0154518D01*
+X0262190Y0153761D01*
+X0260792Y0152363D01*
+X0260035Y0150536D01*
+X0260035Y0148558D01*
+X0260792Y0146730D01*
+X0260482Y0147478D02*
+X0220618Y0147478D01*
+X0221065Y0148677D02*
+X0260035Y0148677D01*
+X0260035Y0149875D02*
+X0236452Y0149875D01*
+X0236557Y0149919D02*
+X0237678Y0151040D01*
+X0238284Y0152504D01*
+X0238284Y0154089D01*
+X0237678Y0155554D01*
+X0236557Y0156674D01*
+X0235740Y0157013D01*
+X0223270Y0180819D01*
+X0223093Y0181246D01*
+X0222995Y0181344D01*
+X0222931Y0181467D01*
+X0222576Y0181763D01*
+X0222249Y0182090D01*
+X0222121Y0182143D01*
+X0222014Y0182232D01*
+X0221574Y0182370D01*
+X0221147Y0182547D01*
+X0221008Y0182547D01*
+X0220875Y0182588D01*
+X0220415Y0182547D01*
+X0220124Y0182547D01*
+X0218910Y0183761D01*
+X0217082Y0184518D01*
+X0209561Y0184518D01*
+X0207734Y0183761D01*
+X0206335Y0182363D01*
+X0205578Y0180536D01*
+X0205578Y0178558D01*
+X0206335Y0176730D01*
+X0207734Y0175332D01*
+X0209561Y0174575D01*
+X0217082Y0174575D01*
+X0218910Y0175332D01*
+X0219212Y0175635D01*
+X0230396Y0154284D01*
+X0230316Y0154089D01*
+X0230316Y0152504D01*
+X0230922Y0151040D01*
+X0232043Y0149919D01*
+X0233507Y0149312D01*
+X0235093Y0149312D01*
+X0236557Y0149919D01*
+X0237692Y0151074D02*
+X0260258Y0151074D01*
+X0260755Y0152273D02*
+X0238188Y0152273D01*
+X0238284Y0153471D02*
+X0261900Y0153471D01*
+X0262190Y0155332D02*
+X0260792Y0156730D01*
+X0260035Y0158558D01*
+X0260035Y0160536D01*
+X0260792Y0162363D01*
+X0262190Y0163761D01*
+X0264018Y0164518D01*
+X0271539Y0164518D01*
+X0273366Y0163761D01*
+X0274765Y0162363D01*
+X0275522Y0160536D01*
+X0275522Y0158558D01*
+X0274765Y0156730D01*
+X0273366Y0155332D01*
+X0271539Y0154575D01*
+X0264018Y0154575D01*
+X0262190Y0155332D01*
+X0261654Y0155868D02*
+X0237363Y0155868D01*
+X0238044Y0154670D02*
+X0263790Y0154670D01*
+X0260653Y0157067D02*
+X0235712Y0157067D01*
+X0235084Y0158265D02*
+X0260156Y0158265D01*
+X0260035Y0159464D02*
+X0234456Y0159464D01*
+X0233829Y0160662D02*
+X0260087Y0160662D01*
+X0260584Y0161861D02*
+X0233201Y0161861D01*
+X0232573Y0163059D02*
+X0261488Y0163059D01*
+X0263388Y0164258D02*
+X0231945Y0164258D01*
+X0231317Y0165456D02*
+X0262066Y0165456D01*
+X0262190Y0165332D02*
+X0260792Y0166730D01*
+X0260035Y0168558D01*
+X0260035Y0170536D01*
+X0260792Y0172363D01*
+X0262190Y0173761D01*
+X0264018Y0174518D01*
+X0271539Y0174518D01*
+X0273366Y0173761D01*
+X0274765Y0172363D01*
+X0275522Y0170536D01*
+X0275522Y0168558D01*
+X0274765Y0166730D01*
+X0273366Y0165332D01*
+X0271539Y0164575D01*
+X0264018Y0164575D01*
+X0262190Y0165332D01*
+X0260868Y0166655D02*
+X0230690Y0166655D01*
+X0230062Y0167853D02*
+X0260327Y0167853D01*
+X0260035Y0169052D02*
+X0229434Y0169052D01*
+X0228806Y0170250D02*
+X0260035Y0170250D01*
+X0260413Y0171449D02*
+X0228178Y0171449D01*
+X0227551Y0172647D02*
+X0261076Y0172647D01*
+X0262394Y0173846D02*
+X0226923Y0173846D01*
+X0226295Y0175044D02*
+X0262885Y0175044D01*
+X0262190Y0175332D02*
+X0264018Y0174575D01*
+X0271539Y0174575D01*
+X0273366Y0175332D01*
+X0274765Y0176730D01*
+X0275522Y0178558D01*
+X0275522Y0180536D01*
+X0274765Y0182363D01*
+X0273366Y0183761D01*
+X0271539Y0184518D01*
+X0264018Y0184518D01*
+X0262190Y0183761D01*
+X0260792Y0182363D01*
+X0260035Y0180536D01*
+X0260035Y0178558D01*
+X0260792Y0176730D01*
+X0262190Y0175332D01*
+X0261280Y0176243D02*
+X0225667Y0176243D01*
+X0225039Y0177441D02*
+X0260498Y0177441D01*
+X0260035Y0178640D02*
+X0224412Y0178640D01*
+X0223784Y0179838D02*
+X0260035Y0179838D01*
+X0260243Y0181037D02*
+X0223180Y0181037D01*
+X0222004Y0182235D02*
+X0260739Y0182235D01*
+X0261863Y0183434D02*
+X0219237Y0183434D01*
+X0218910Y0185332D02*
+X0217082Y0184575D01*
+X0209561Y0184575D01*
+X0207734Y0185332D01*
+X0206335Y0186730D01*
+X0205578Y0188558D01*
+X0205578Y0190536D01*
+X0206335Y0192363D01*
+X0207734Y0193761D01*
+X0209561Y0194518D01*
+X0217082Y0194518D01*
+X0218910Y0193761D01*
+X0220308Y0192363D01*
+X0221065Y0190536D01*
+X0221065Y0188558D01*
+X0220308Y0186730D01*
+X0218910Y0185332D01*
+X0219408Y0185831D02*
+X0261692Y0185831D01*
+X0262190Y0185332D02*
+X0260792Y0186730D01*
+X0260035Y0188558D01*
+X0260035Y0190536D01*
+X0260792Y0192363D01*
+X0262190Y0193761D01*
+X0264018Y0194518D01*
+X0271539Y0194518D01*
+X0273366Y0193761D01*
+X0274765Y0192363D01*
+X0275522Y0190536D01*
+X0275522Y0188558D01*
+X0274765Y0186730D01*
+X0273366Y0185332D01*
+X0271539Y0184575D01*
+X0264018Y0184575D01*
+X0262190Y0185332D01*
+X0263879Y0184632D02*
+X0217221Y0184632D01*
+X0220432Y0187029D02*
+X0260668Y0187029D01*
+X0260172Y0188228D02*
+X0220928Y0188228D01*
+X0221065Y0189426D02*
+X0260035Y0189426D01*
+X0260072Y0190625D02*
+X0221028Y0190625D01*
+X0220532Y0191823D02*
+X0260568Y0191823D01*
+X0261451Y0193022D02*
+X0219649Y0193022D01*
+X0217801Y0194220D02*
+X0263299Y0194220D01*
+X0272258Y0194220D02*
+X0276842Y0194220D01*
+X0276770Y0194293D02*
+X0277068Y0193995D01*
+X0277432Y0193784D01*
+X0277839Y0193675D01*
+X0282450Y0193675D01*
+X0282450Y0197175D01*
+X0283650Y0197175D01*
+X0283650Y0193675D01*
+X0288261Y0193675D01*
+X0288668Y0193784D01*
+X0289032Y0193995D01*
+X0289330Y0194293D01*
+X0289541Y0194657D01*
+X0289650Y0195064D01*
+X0289650Y0197175D01*
+X0283650Y0197175D01*
+X0283650Y0198375D01*
+X0282450Y0198375D01*
+X0282450Y0197175D01*
+X0276450Y0197175D01*
+X0276450Y0195064D01*
+X0276559Y0194657D01*
+X0276770Y0194293D01*
+X0276450Y0195419D02*
+X0199800Y0195419D01*
+X0199800Y0194220D02*
+X0208842Y0194220D01*
+X0206994Y0193022D02*
+X0199800Y0193022D01*
+X0199800Y0191823D02*
+X0206112Y0191823D01*
+X0205615Y0190625D02*
+X0199800Y0190625D01*
+X0199800Y0189426D02*
+X0205578Y0189426D01*
+X0205715Y0188228D02*
+X0199800Y0188228D01*
+X0199800Y0187029D02*
+X0206211Y0187029D01*
+X0207235Y0185831D02*
+X0199800Y0185831D01*
+X0199800Y0184632D02*
+X0209423Y0184632D01*
+X0207406Y0183434D02*
+X0199800Y0183434D01*
+X0199800Y0182235D02*
+X0206282Y0182235D01*
+X0205786Y0181037D02*
+X0199800Y0181037D01*
+X0199800Y0179838D02*
+X0205578Y0179838D01*
+X0205578Y0178640D02*
+X0199800Y0178640D01*
+X0199800Y0177441D02*
+X0206041Y0177441D01*
+X0206823Y0176243D02*
+X0199800Y0176243D01*
+X0199800Y0175044D02*
+X0208428Y0175044D01*
+X0209561Y0174518D02*
+X0207734Y0173761D01*
+X0206335Y0172363D01*
+X0205578Y0170536D01*
+X0205578Y0168558D01*
+X0206335Y0166730D01*
+X0207734Y0165332D01*
+X0209561Y0164575D01*
+X0217082Y0164575D01*
+X0218910Y0165332D01*
+X0220308Y0166730D01*
+X0221065Y0168558D01*
+X0221065Y0170536D01*
+X0220308Y0172363D01*
+X0218910Y0173761D01*
+X0217082Y0174518D01*
+X0209561Y0174518D01*
+X0207937Y0173846D02*
+X0199800Y0173846D01*
+X0199800Y0172647D02*
+X0206620Y0172647D01*
+X0205957Y0171449D02*
+X0199800Y0171449D01*
+X0199800Y0170250D02*
+X0205578Y0170250D01*
+X0205578Y0169052D02*
+X0199800Y0169052D01*
+X0199800Y0167853D02*
+X0205870Y0167853D01*
+X0206411Y0166655D02*
+X0200239Y0166655D01*
+X0200736Y0165456D02*
+X0207610Y0165456D01*
+X0208932Y0164258D02*
+X0200784Y0164258D01*
+X0200496Y0163059D02*
+X0207031Y0163059D01*
+X0206127Y0161861D02*
+X0199748Y0161861D01*
+X0193800Y0171449D02*
+X0184097Y0171449D01*
+X0184534Y0172647D02*
+X0193800Y0172647D01*
+X0193800Y0173846D02*
+X0184534Y0173846D01*
+X0184139Y0175044D02*
+X0193800Y0175044D01*
+X0193800Y0176243D02*
+X0183550Y0176243D01*
+X0183550Y0177441D02*
+X0193800Y0177441D01*
+X0193800Y0178640D02*
+X0183550Y0178640D01*
+X0183550Y0179838D02*
+X0193800Y0179838D01*
+X0193800Y0181037D02*
+X0183550Y0181037D01*
+X0183550Y0182235D02*
+X0193800Y0182235D01*
+X0193800Y0183434D02*
+X0183561Y0183434D01*
+X0184272Y0184632D02*
+X0193800Y0184632D01*
+X0193800Y0185831D02*
+X0184534Y0185831D01*
+X0184460Y0187029D02*
+X0193800Y0187029D01*
+X0193800Y0188228D02*
+X0183964Y0188228D01*
+X0182816Y0189426D02*
+X0193800Y0189426D01*
+X0200417Y0196617D02*
+X0276450Y0196617D01*
+X0276450Y0198375D02*
+X0282450Y0198375D01*
+X0282450Y0201875D01*
+X0277839Y0201875D01*
+X0277432Y0201766D01*
+X0277068Y0201555D01*
+X0276770Y0201257D01*
+X0276559Y0200893D01*
+X0276450Y0200486D01*
+X0276450Y0198375D01*
+X0276450Y0199014D02*
+X0200784Y0199014D01*
+X0200784Y0197816D02*
+X0282450Y0197816D01*
+X0282450Y0199014D02*
+X0283650Y0199014D01*
+X0283650Y0197816D02*
+X0297950Y0197816D01*
+X0297950Y0199014D02*
+X0289650Y0199014D01*
+X0289650Y0196617D02*
+X0297694Y0196617D01*
+X0296495Y0195419D02*
+X0289650Y0195419D01*
+X0289258Y0194220D02*
+X0295297Y0194220D01*
+X0294390Y0193022D02*
+X0274106Y0193022D01*
+X0274988Y0191823D02*
+X0294200Y0191823D01*
+X0294200Y0190625D02*
+X0275485Y0190625D01*
+X0275522Y0189426D02*
+X0294200Y0189426D01*
+X0294200Y0188228D02*
+X0275385Y0188228D01*
+X0274889Y0187029D02*
+X0294200Y0187029D01*
+X0294200Y0185831D02*
+X0289857Y0185831D01*
+X0290250Y0185438D02*
+X0288961Y0186727D01*
+X0277139Y0186727D01*
+X0275850Y0185438D01*
+X0275850Y0178616D01*
+X0277139Y0177327D01*
+X0288961Y0177327D01*
+X0290250Y0178616D01*
+X0290250Y0185438D01*
+X0290250Y0184632D02*
+X0294200Y0184632D01*
+X0294200Y0183434D02*
+X0290250Y0183434D01*
+X0290250Y0182235D02*
+X0294200Y0182235D01*
+X0294200Y0181037D02*
+X0290250Y0181037D01*
+X0290250Y0179838D02*
+X0294200Y0179838D01*
+X0294200Y0178640D02*
+X0290250Y0178640D01*
+X0289076Y0177441D02*
+X0294200Y0177441D01*
+X0294200Y0176243D02*
+X0274277Y0176243D01*
+X0275059Y0177441D02*
+X0277024Y0177441D01*
+X0275850Y0178640D02*
+X0275522Y0178640D01*
+X0275522Y0179838D02*
+X0275850Y0179838D01*
+X0275850Y0181037D02*
+X0275314Y0181037D01*
+X0274818Y0182235D02*
+X0275850Y0182235D01*
+X0275850Y0183434D02*
+X0273694Y0183434D01*
+X0271677Y0184632D02*
+X0275850Y0184632D01*
+X0276243Y0185831D02*
+X0273865Y0185831D01*
+X0278293Y0175424D02*
+X0279757Y0176031D01*
+X0281343Y0176031D01*
+X0282807Y0175424D01*
+X0283928Y0174304D01*
+X0284534Y0172839D01*
+X0284534Y0171254D01*
+X0284420Y0170979D01*
+X0288961Y0170979D01*
+X0290250Y0169690D01*
+X0290250Y0162868D01*
+X0288961Y0161579D01*
+X0277139Y0161579D01*
+X0275850Y0162868D01*
+X0275850Y0169690D01*
+X0276814Y0170654D01*
+X0276566Y0171254D01*
+X0276566Y0172839D01*
+X0277172Y0174304D01*
+X0278293Y0175424D01*
+X0277913Y0175044D02*
+X0272672Y0175044D01*
+X0273163Y0173846D02*
+X0276983Y0173846D01*
+X0276566Y0172647D02*
+X0274480Y0172647D01*
+X0275143Y0171449D02*
+X0276566Y0171449D01*
+X0276410Y0170250D02*
+X0275522Y0170250D01*
+X0275522Y0169052D02*
+X0275850Y0169052D01*
+X0275850Y0167853D02*
+X0275230Y0167853D01*
+X0274689Y0166655D02*
+X0275850Y0166655D01*
+X0275850Y0165456D02*
+X0273490Y0165456D01*
+X0272168Y0164258D02*
+X0275850Y0164258D01*
+X0275850Y0163059D02*
+X0274069Y0163059D01*
+X0274973Y0161861D02*
+X0276857Y0161861D01*
+X0275469Y0160662D02*
+X0294200Y0160662D01*
+X0294200Y0159464D02*
+X0283359Y0159464D01*
+X0284057Y0159174D02*
+X0282593Y0159781D01*
+X0281007Y0159781D01*
+X0279543Y0159174D01*
+X0278422Y0158054D01*
+X0277816Y0156589D01*
+X0277816Y0155231D01*
+X0277139Y0155231D01*
+X0275850Y0153942D01*
+X0275850Y0147120D01*
+X0277139Y0145831D01*
+X0288961Y0145831D01*
+X0290250Y0147120D01*
+X0290250Y0153942D01*
+X0288961Y0155231D01*
+X0285784Y0155231D01*
+X0285784Y0156589D01*
+X0285178Y0158054D01*
+X0284057Y0159174D01*
+X0284966Y0158265D02*
+X0294200Y0158265D01*
+X0294200Y0157067D02*
+X0285587Y0157067D01*
+X0285784Y0155868D02*
+X0294200Y0155868D01*
+X0294200Y0154670D02*
+X0289523Y0154670D01*
+X0290250Y0153471D02*
+X0294200Y0153471D01*
+X0294200Y0152273D02*
+X0290250Y0152273D01*
+X0290250Y0151074D02*
+X0294200Y0151074D01*
+X0294200Y0149875D02*
+X0290250Y0149875D01*
+X0290250Y0148677D02*
+X0294200Y0148677D01*
+X0294200Y0147478D02*
+X0290250Y0147478D01*
+X0289410Y0146280D02*
+X0294200Y0146280D01*
+X0294200Y0145081D02*
+X0272761Y0145081D01*
+X0273073Y0143883D02*
+X0294200Y0143883D01*
+X0294239Y0142684D02*
+X0274443Y0142684D01*
+X0275128Y0141486D02*
+X0294891Y0141486D01*
+X0295721Y0140287D02*
+X0275522Y0140287D01*
+X0275522Y0139089D02*
+X0276745Y0139089D01*
+X0277139Y0139483D02*
+X0275850Y0138194D01*
+X0275850Y0131372D01*
+X0276659Y0130563D01*
+X0276566Y0130339D01*
+X0276566Y0128754D01*
+X0277172Y0127290D01*
+X0278293Y0126169D01*
+X0279757Y0125562D01*
+X0281343Y0125562D01*
+X0282807Y0126169D01*
+X0283928Y0127290D01*
+X0284534Y0128754D01*
+X0284534Y0130083D01*
+X0288961Y0130083D01*
+X0290250Y0131372D01*
+X0290250Y0138194D01*
+X0288961Y0139483D01*
+X0277139Y0139483D01*
+X0275850Y0137890D02*
+X0275245Y0137890D01*
+X0274726Y0136692D02*
+X0275850Y0136692D01*
+X0275850Y0135493D02*
+X0273528Y0135493D01*
+X0272078Y0134295D02*
+X0275850Y0134295D01*
+X0275850Y0133096D02*
+X0274031Y0133096D01*
+X0274957Y0131898D02*
+X0275850Y0131898D01*
+X0275454Y0130699D02*
+X0276522Y0130699D01*
+X0276566Y0129501D02*
+X0275522Y0129501D01*
+X0275416Y0128302D02*
+X0276753Y0128302D01*
+X0277358Y0127104D02*
+X0274919Y0127104D01*
+X0273940Y0125905D02*
+X0278930Y0125905D01*
+X0277139Y0123735D02*
+X0275850Y0122446D01*
+X0275850Y0115624D01*
+X0277139Y0114335D01*
+X0277918Y0114335D01*
+X0277816Y0114089D01*
+X0277816Y0112504D01*
+X0278422Y0111040D01*
+X0279543Y0109919D01*
+X0281007Y0109312D01*
+X0282593Y0109312D01*
+X0284057Y0109919D01*
+X0285178Y0111040D01*
+X0285784Y0112504D01*
+X0285784Y0114089D01*
+X0285682Y0114335D01*
+X0288961Y0114335D01*
+X0290250Y0115624D01*
+X0290250Y0122446D01*
+X0288961Y0123735D01*
+X0277139Y0123735D01*
+X0276912Y0123508D02*
+X0273619Y0123508D01*
+X0273366Y0123761D02*
+X0274765Y0122363D01*
+X0275522Y0120536D01*
+X0275522Y0118558D01*
+X0274765Y0116730D01*
+X0273366Y0115332D01*
+X0271539Y0114575D01*
+X0264018Y0114575D01*
+X0262190Y0115332D01*
+X0260792Y0116730D01*
+X0260035Y0118558D01*
+X0260035Y0120536D01*
+X0260792Y0122363D01*
+X0262190Y0123761D01*
+X0264018Y0124518D01*
+X0271539Y0124518D01*
+X0273366Y0123761D01*
+X0271857Y0124707D02*
+X0305450Y0124707D01*
+X0305450Y0125905D02*
+X0282170Y0125905D01*
+X0283742Y0127104D02*
+X0304848Y0127104D01*
+X0304018Y0128302D02*
+X0284347Y0128302D01*
+X0284534Y0129501D02*
+X0303189Y0129501D01*
+X0302359Y0130699D02*
+X0289578Y0130699D01*
+X0290250Y0131898D02*
+X0301529Y0131898D01*
+X0300700Y0133096D02*
+X0290250Y0133096D01*
+X0290250Y0134295D02*
+X0299870Y0134295D01*
+X0299040Y0135493D02*
+X0290250Y0135493D01*
+X0290250Y0136692D02*
+X0298210Y0136692D01*
+X0297381Y0137890D02*
+X0290250Y0137890D01*
+X0289355Y0139089D02*
+X0296551Y0139089D01*
+X0289188Y0123508D02*
+X0305450Y0123508D01*
+X0305450Y0122310D02*
+X0290250Y0122310D01*
+X0290250Y0121111D02*
+X0305450Y0121111D01*
+X0305450Y0119913D02*
+X0290250Y0119913D01*
+X0290250Y0118714D02*
+X0305450Y0118714D01*
+X0305450Y0117516D02*
+X0290250Y0117516D01*
+X0290250Y0116317D02*
+X0305450Y0116317D01*
+X0305450Y0115119D02*
+X0289745Y0115119D01*
+X0285784Y0113920D02*
+X0305450Y0113920D01*
+X0305450Y0112722D02*
+X0285784Y0112722D01*
+X0285378Y0111523D02*
+X0305450Y0111523D01*
+X0305450Y0110325D02*
+X0284463Y0110325D01*
+X0279137Y0110325D02*
+X0275522Y0110325D01*
+X0275522Y0110536D02*
+X0274765Y0112363D01*
+X0273366Y0113761D01*
+X0271539Y0114518D01*
+X0264018Y0114518D01*
+X0262190Y0113761D01*
+X0260792Y0112363D01*
+X0260035Y0110536D01*
+X0260035Y0108558D01*
+X0260792Y0106730D01*
+X0262190Y0105332D01*
+X0264018Y0104575D01*
+X0271539Y0104575D01*
+X0273366Y0105332D01*
+X0274765Y0106730D01*
+X0275522Y0108558D01*
+X0275522Y0110536D01*
+X0275113Y0111523D02*
+X0278222Y0111523D01*
+X0277816Y0112722D02*
+X0274406Y0112722D01*
+X0272983Y0113920D02*
+X0277816Y0113920D01*
+X0276355Y0115119D02*
+X0272851Y0115119D01*
+X0274351Y0116317D02*
+X0275850Y0116317D01*
+X0275850Y0117516D02*
+X0275090Y0117516D01*
+X0275522Y0118714D02*
+X0275850Y0118714D01*
+X0275850Y0119913D02*
+X0275522Y0119913D01*
+X0275283Y0121111D02*
+X0275850Y0121111D01*
+X0275850Y0122310D02*
+X0274787Y0122310D01*
+X0263700Y0124707D02*
+X0217400Y0124707D01*
+X0219163Y0123508D02*
+X0261937Y0123508D01*
+X0260770Y0122310D02*
+X0220330Y0122310D01*
+X0220827Y0121111D02*
+X0260273Y0121111D01*
+X0260035Y0119913D02*
+X0221065Y0119913D01*
+X0221065Y0118714D02*
+X0260035Y0118714D01*
+X0260467Y0117516D02*
+X0220633Y0117516D01*
+X0219895Y0116317D02*
+X0261205Y0116317D01*
+X0262705Y0115119D02*
+X0218395Y0115119D01*
+X0218526Y0113920D02*
+X0262574Y0113920D01*
+X0261151Y0112722D02*
+X0219949Y0112722D01*
+X0220656Y0111523D02*
+X0260444Y0111523D01*
+X0260035Y0110325D02*
+X0221065Y0110325D01*
+X0221065Y0109126D02*
+X0260035Y0109126D01*
+X0260296Y0107928D02*
+X0220804Y0107928D01*
+X0220307Y0106729D02*
+X0260793Y0106729D01*
+X0261992Y0105531D02*
+X0219108Y0105531D01*
+X0218910Y0103761D02*
+X0217082Y0104518D01*
+X0209561Y0104518D01*
+X0207734Y0103761D01*
+X0206335Y0102363D01*
+X0205578Y0100536D01*
+X0205578Y0098558D01*
+X0206335Y0096730D01*
+X0207734Y0095332D01*
+X0209561Y0094575D01*
+X0217082Y0094575D01*
+X0218910Y0095332D01*
+X0220308Y0096730D01*
+X0221065Y0098558D01*
+X0221065Y0100536D01*
+X0220308Y0102363D01*
+X0218910Y0103761D01*
+X0219537Y0103134D02*
+X0261563Y0103134D01*
+X0262190Y0103761D02*
+X0260792Y0102363D01*
+X0260035Y0100536D01*
+X0260035Y0098558D01*
+X0260792Y0096730D01*
+X0262190Y0095332D01*
+X0264018Y0094575D01*
+X0271539Y0094575D01*
+X0273366Y0095332D01*
+X0274555Y0096521D01*
+X0274066Y0095339D01*
+X0274066Y0093754D01*
+X0274555Y0092572D01*
+X0273366Y0093761D01*
+X0271539Y0094518D01*
+X0264018Y0094518D01*
+X0262190Y0093761D01*
+X0260792Y0092363D01*
+X0260035Y0090536D01*
+X0260035Y0088558D01*
+X0260792Y0086730D01*
+X0262190Y0085332D01*
+X0264018Y0084575D01*
+X0271279Y0084575D01*
+X0271351Y0084503D01*
+X0272453Y0084047D01*
+X0281807Y0084047D01*
+X0287550Y0078304D01*
+X0287550Y0064681D01*
+X0287172Y0064304D01*
+X0286566Y0062839D01*
+X0286566Y0061254D01*
+X0287172Y0059790D01*
+X0288293Y0058669D01*
+X0289757Y0058062D01*
+X0291343Y0058062D01*
+X0292807Y0058669D01*
+X0293928Y0059790D01*
+X0294534Y0061254D01*
+X0294534Y0062839D01*
+X0293928Y0064304D01*
+X0293550Y0064681D01*
+X0293550Y0080143D01*
+X0293093Y0081246D01*
+X0292249Y0082090D01*
+X0284749Y0089590D01*
+X0283647Y0090047D01*
+X0275522Y0090047D01*
+X0275522Y0090536D01*
+X0274882Y0092080D01*
+X0275793Y0091169D01*
+X0277257Y0090562D01*
+X0278843Y0090562D01*
+X0280307Y0091169D01*
+X0281428Y0092290D01*
+X0282034Y0093754D01*
+X0282034Y0094288D01*
+X0284749Y0097003D01*
+X0285593Y0097847D01*
+X0285900Y0098587D01*
+X0288961Y0098587D01*
+X0290250Y0099876D01*
+X0290250Y0106698D01*
+X0288961Y0107987D01*
+X0277139Y0107987D01*
+X0275850Y0106698D01*
+X0275850Y0099876D01*
+X0277139Y0098587D01*
+X0277848Y0098587D01*
+X0277792Y0098531D01*
+X0277257Y0098531D01*
+X0275793Y0097924D01*
+X0274882Y0097013D01*
+X0275522Y0098558D01*
+X0275522Y0100536D01*
+X0274765Y0102363D01*
+X0273366Y0103761D01*
+X0271539Y0104518D01*
+X0264018Y0104518D01*
+X0262190Y0103761D01*
+X0263568Y0104332D02*
+X0217532Y0104332D01*
+X0220485Y0101935D02*
+X0260615Y0101935D01*
+X0260118Y0100737D02*
+X0220982Y0100737D01*
+X0221065Y0099538D02*
+X0260035Y0099538D01*
+X0260125Y0098340D02*
+X0220975Y0098340D01*
+X0220478Y0097141D02*
+X0260622Y0097141D01*
+X0261580Y0095942D02*
+X0219520Y0095942D01*
+X0218910Y0093761D02*
+X0217082Y0094518D01*
+X0209561Y0094518D01*
+X0207734Y0093761D01*
+X0206335Y0092363D01*
+X0205578Y0090536D01*
+X0205578Y0088558D01*
+X0206335Y0086730D01*
+X0207734Y0085332D01*
+X0209561Y0084575D01*
+X0217082Y0084575D01*
+X0218910Y0085332D01*
+X0220308Y0086730D01*
+X0221065Y0088558D01*
+X0221065Y0090536D01*
+X0220308Y0092363D01*
+X0218910Y0093761D01*
+X0219125Y0093545D02*
+X0261974Y0093545D01*
+X0260785Y0092347D02*
+X0220315Y0092347D01*
+X0220811Y0091148D02*
+X0260289Y0091148D01*
+X0260035Y0089950D02*
+X0221065Y0089950D01*
+X0221065Y0088751D02*
+X0260035Y0088751D01*
+X0260451Y0087553D02*
+X0220649Y0087553D01*
+X0219932Y0086354D02*
+X0261168Y0086354D01*
+X0262615Y0085156D02*
+X0218484Y0085156D01*
+X0218437Y0083957D02*
+X0281897Y0083957D01*
+X0283095Y0082759D02*
+X0273520Y0082759D01*
+X0273398Y0082881D02*
+X0273884Y0082395D01*
+X0274289Y0081838D01*
+X0274601Y0081225D01*
+X0274814Y0080570D01*
+X0274922Y0079891D01*
+X0274922Y0079833D01*
+X0270836Y0079833D01*
+X0270264Y0079833D01*
+X0270264Y0083918D01*
+X0264663Y0083918D01*
+X0263983Y0083811D01*
+X0263329Y0083598D01*
+X0262715Y0083286D01*
+X0262159Y0082881D01*
+X0261672Y0082395D01*
+X0261268Y0081838D01*
+X0260955Y0081225D01*
+X0260743Y0080570D01*
+X0260635Y0079891D01*
+X0260635Y0079833D01*
+X0270264Y0079833D01*
+X0270264Y0079261D01*
+X0260635Y0079261D01*
+X0260635Y0079203D01*
+X0260743Y0078523D01*
+X0260955Y0077869D01*
+X0261268Y0077255D01*
+X0261672Y0076699D01*
+X0262159Y0076212D01*
+X0262715Y0075808D01*
+X0263329Y0075495D01*
+X0263983Y0075283D01*
+X0264663Y0075175D01*
+X0270264Y0075175D01*
+X0270264Y0079261D01*
+X0270836Y0079261D01*
+X0270836Y0079833D01*
+X0270836Y0083918D01*
+X0270894Y0083918D01*
+X0271574Y0083811D01*
+X0272228Y0083598D01*
+X0272841Y0083286D01*
+X0273398Y0082881D01*
+X0274430Y0081560D02*
+X0284294Y0081560D01*
+X0285492Y0080362D02*
+X0282869Y0080362D01*
+X0282807Y0080424D02*
+X0281343Y0081031D01*
+X0279757Y0081031D01*
+X0278293Y0080424D01*
+X0277172Y0079304D01*
+X0276566Y0077839D01*
+X0276566Y0076254D01*
+X0277172Y0074790D01*
+X0277731Y0074231D01*
+X0278800Y0058197D01*
+X0278800Y0057700D01*
+X0278839Y0057605D01*
+X0278846Y0057502D01*
+X0279067Y0057056D01*
+X0279257Y0056597D01*
+X0279330Y0056524D01*
+X0279375Y0056432D01*
+X0279749Y0056105D01*
+X0281566Y0054288D01*
+X0281566Y0053754D01*
+X0282172Y0052290D01*
+X0283293Y0051169D01*
+X0284757Y0050562D01*
+X0286343Y0050562D01*
+X0287807Y0051169D01*
+X0288928Y0052290D01*
+X0289534Y0053754D01*
+X0289534Y0055339D01*
+X0288928Y0056804D01*
+X0287807Y0057924D01*
+X0286343Y0058531D01*
+X0285808Y0058531D01*
+X0284718Y0059621D01*
+X0283721Y0074583D01*
+X0283928Y0074790D01*
+X0284534Y0076254D01*
+X0284534Y0077839D01*
+X0283928Y0079304D01*
+X0282807Y0080424D01*
+X0283986Y0079163D02*
+X0286691Y0079163D01*
+X0287550Y0077965D02*
+X0284482Y0077965D01*
+X0284534Y0076766D02*
+X0287550Y0076766D01*
+X0287550Y0075568D02*
+X0284250Y0075568D01*
+X0283735Y0074369D02*
+X0287550Y0074369D01*
+X0287550Y0073171D02*
+X0283815Y0073171D01*
+X0283895Y0071972D02*
+X0287550Y0071972D01*
+X0287550Y0070774D02*
+X0283975Y0070774D01*
+X0284055Y0069575D02*
+X0287550Y0069575D01*
+X0287550Y0068377D02*
+X0284135Y0068377D01*
+X0284215Y0067178D02*
+X0287550Y0067178D01*
+X0287550Y0065980D02*
+X0284294Y0065980D01*
+X0284374Y0064781D02*
+X0287550Y0064781D01*
+X0286874Y0063583D02*
+X0284454Y0063583D01*
+X0284534Y0062384D02*
+X0286566Y0062384D01*
+X0286594Y0061186D02*
+X0284614Y0061186D01*
+X0284694Y0059987D02*
+X0287091Y0059987D01*
+X0288173Y0058789D02*
+X0285551Y0058789D01*
+X0288141Y0057590D02*
+X0378050Y0057590D01*
+X0378050Y0056392D02*
+X0289098Y0056392D01*
+X0289534Y0055193D02*
+X0378050Y0055193D01*
+X0378050Y0053995D02*
+X0289534Y0053995D01*
+X0289137Y0052796D02*
+X0378050Y0052796D01*
+X0378050Y0051598D02*
+X0288235Y0051598D01*
+X0282865Y0051598D02*
+X0275082Y0051598D01*
+X0274765Y0052363D02*
+X0273366Y0053761D01*
+X0271539Y0054518D01*
+X0264018Y0054518D01*
+X0262190Y0053761D01*
+X0260792Y0052363D01*
+X0260035Y0050536D01*
+X0260035Y0048558D01*
+X0260792Y0046730D01*
+X0262190Y0045332D01*
+X0264018Y0044575D01*
+X0271539Y0044575D01*
+X0273366Y0045332D01*
+X0274765Y0046730D01*
+X0275522Y0048558D01*
+X0275522Y0050536D01*
+X0274765Y0052363D01*
+X0274332Y0052796D02*
+X0281963Y0052796D01*
+X0281566Y0053995D02*
+X0272803Y0053995D01*
+X0273031Y0055193D02*
+X0280661Y0055193D01*
+X0279421Y0056392D02*
+X0274426Y0056392D01*
+X0274765Y0056730D02*
+X0275522Y0058558D01*
+X0275522Y0060536D01*
+X0274765Y0062363D01*
+X0273366Y0063761D01*
+X0271539Y0064518D01*
+X0264018Y0064518D01*
+X0262190Y0063761D01*
+X0260792Y0062363D01*
+X0260035Y0060536D01*
+X0260035Y0058558D01*
+X0260792Y0056730D01*
+X0262190Y0055332D01*
+X0264018Y0054575D01*
+X0271539Y0054575D01*
+X0273366Y0055332D01*
+X0274765Y0056730D01*
+X0275121Y0057590D02*
+X0278840Y0057590D01*
+X0278761Y0058789D02*
+X0275522Y0058789D01*
+X0275522Y0059987D02*
+X0278681Y0059987D01*
+X0278601Y0061186D02*
+X0275252Y0061186D01*
+X0274743Y0062384D02*
+X0278521Y0062384D01*
+X0278441Y0063583D02*
+X0273545Y0063583D01*
+X0273366Y0065332D02*
+X0274765Y0066730D01*
+X0275522Y0068558D01*
+X0275522Y0070536D01*
+X0274765Y0072363D01*
+X0273366Y0073761D01*
+X0271539Y0074518D01*
+X0264018Y0074518D01*
+X0262190Y0073761D01*
+X0260792Y0072363D01*
+X0260035Y0070536D01*
+X0260035Y0068558D01*
+X0260792Y0066730D01*
+X0262190Y0065332D01*
+X0264018Y0064575D01*
+X0271539Y0064575D01*
+X0273366Y0065332D01*
+X0274014Y0065980D02*
+X0278281Y0065980D01*
+X0278201Y0067178D02*
+X0274950Y0067178D01*
+X0275447Y0068377D02*
+X0278121Y0068377D01*
+X0278041Y0069575D02*
+X0275522Y0069575D01*
+X0275423Y0070774D02*
+X0277962Y0070774D01*
+X0277882Y0071972D02*
+X0274927Y0071972D01*
+X0273957Y0073171D02*
+X0277802Y0073171D01*
+X0277593Y0074369D02*
+X0271899Y0074369D01*
+X0271574Y0075283D02*
+X0272228Y0075495D01*
+X0272841Y0075808D01*
+X0273398Y0076212D01*
+X0273884Y0076699D01*
+X0274289Y0077255D01*
+X0274601Y0077869D01*
+X0274814Y0078523D01*
+X0274922Y0079203D01*
+X0274922Y0079261D01*
+X0270836Y0079261D01*
+X0270836Y0075175D01*
+X0270894Y0075175D01*
+X0271574Y0075283D01*
+X0270836Y0075568D02*
+X0270264Y0075568D01*
+X0270264Y0076766D02*
+X0270836Y0076766D01*
+X0270836Y0077965D02*
+X0270264Y0077965D01*
+X0270264Y0079163D02*
+X0270836Y0079163D01*
+X0270836Y0080362D02*
+X0270264Y0080362D01*
+X0270264Y0081560D02*
+X0270836Y0081560D01*
+X0270836Y0082759D02*
+X0270264Y0082759D01*
+X0274847Y0080362D02*
+X0278231Y0080362D01*
+X0277114Y0079163D02*
+X0274915Y0079163D01*
+X0274633Y0077965D02*
+X0276618Y0077965D01*
+X0276566Y0076766D02*
+X0273934Y0076766D01*
+X0272370Y0075568D02*
+X0276850Y0075568D01*
+X0278361Y0064781D02*
+X0272037Y0064781D01*
+X0263520Y0064781D02*
+X0217580Y0064781D01*
+X0217082Y0064575D02*
+X0218910Y0065332D01*
+X0220308Y0066730D01*
+X0221065Y0068558D01*
+X0221065Y0070536D01*
+X0220308Y0072363D01*
+X0218910Y0073761D01*
+X0217082Y0074518D01*
+X0209561Y0074518D01*
+X0207734Y0073761D01*
+X0206335Y0072363D01*
+X0205578Y0070536D01*
+X0205578Y0068558D01*
+X0206335Y0066730D01*
+X0207734Y0065332D01*
+X0209561Y0064575D01*
+X0217082Y0064575D01*
+X0217117Y0063811D02*
+X0216437Y0063918D01*
+X0210836Y0063918D01*
+X0210836Y0059833D01*
+X0210264Y0059833D01*
+X0210264Y0063918D01*
+X0210206Y0063918D01*
+X0209526Y0063811D01*
+X0208872Y0063598D01*
+X0208259Y0063286D01*
+X0207702Y0062881D01*
+X0207215Y0062395D01*
+X0206811Y0061838D01*
+X0206499Y0061225D01*
+X0206286Y0060570D01*
+X0206178Y0059891D01*
+X0206178Y0059833D01*
+X0210264Y0059833D01*
+X0210264Y0059261D01*
+X0206178Y0059261D01*
+X0206178Y0059203D01*
+X0206286Y0058523D01*
+X0206499Y0057869D01*
+X0206811Y0057255D01*
+X0207215Y0056699D01*
+X0207702Y0056212D01*
+X0208259Y0055808D01*
+X0208872Y0055495D01*
+X0209526Y0055283D01*
+X0210206Y0055175D01*
+X0210264Y0055175D01*
+X0210264Y0059261D01*
+X0210836Y0059261D01*
+X0210836Y0059833D01*
+X0220465Y0059833D01*
+X0220465Y0059891D01*
+X0220357Y0060570D01*
+X0220145Y0061225D01*
+X0219832Y0061838D01*
+X0219428Y0062395D01*
+X0218941Y0062881D01*
+X0218385Y0063286D01*
+X0217771Y0063598D01*
+X0217117Y0063811D01*
+X0217802Y0063583D02*
+X0262012Y0063583D01*
+X0260813Y0062384D02*
+X0219435Y0062384D01*
+X0220157Y0061186D02*
+X0260304Y0061186D01*
+X0260035Y0059987D02*
+X0220450Y0059987D01*
+X0220465Y0059261D02*
+X0210836Y0059261D01*
+X0210836Y0055175D01*
+X0216437Y0055175D01*
+X0217117Y0055283D01*
+X0217771Y0055495D01*
+X0218385Y0055808D01*
+X0218941Y0056212D01*
+X0219428Y0056699D01*
+X0219832Y0057255D01*
+X0220145Y0057869D01*
+X0220357Y0058523D01*
+X0220465Y0059203D01*
+X0220465Y0059261D01*
+X0220399Y0058789D02*
+X0260035Y0058789D01*
+X0260436Y0057590D02*
+X0220003Y0057590D01*
+X0219121Y0056392D02*
+X0261131Y0056392D01*
+X0262526Y0055193D02*
+X0216551Y0055193D01*
+X0218347Y0053995D02*
+X0262753Y0053995D01*
+X0261225Y0052796D02*
+X0219875Y0052796D01*
+X0220625Y0051598D02*
+X0260475Y0051598D01*
+X0260035Y0050399D02*
+X0221065Y0050399D01*
+X0221065Y0049201D02*
+X0260035Y0049201D01*
+X0260265Y0048002D02*
+X0220835Y0048002D01*
+X0220338Y0046804D02*
+X0260762Y0046804D01*
+X0261917Y0045605D02*
+X0219183Y0045605D01*
+X0207461Y0045605D02*
+X0193700Y0045605D01*
+X0193057Y0044406D02*
+X0290200Y0044406D01*
+X0290200Y0044547D02*
+X0290200Y0042848D01*
+X0292602Y0040447D01*
+X0294300Y0040447D01*
+X0295998Y0040447D01*
+X0298400Y0042848D01*
+X0298400Y0044547D01*
+X0298400Y0046245D01*
+X0295998Y0048647D01*
+X0294300Y0048647D01*
+X0294300Y0044547D01*
+X0294300Y0044547D01*
+X0294300Y0048647D01*
+X0292602Y0048647D01*
+X0290200Y0046245D01*
+X0290200Y0044547D01*
+X0294300Y0044547D01*
+X0298400Y0044547D01*
+X0294300Y0044547D01*
+X0294300Y0044547D01*
+X0294300Y0044547D01*
+X0290200Y0044547D01*
+X0290200Y0045605D02*
+X0273639Y0045605D01*
+X0274795Y0046804D02*
+X0290759Y0046804D01*
+X0291957Y0048002D02*
+X0275291Y0048002D01*
+X0275522Y0049201D02*
+X0303254Y0049201D01*
+X0303365Y0049247D02*
+X0301638Y0048531D01*
+X0300316Y0047209D01*
+X0299600Y0045482D01*
+X0299600Y0043612D01*
+X0300316Y0041884D01*
+X0301638Y0040562D01*
+X0302882Y0040047D01*
+X0301638Y0039531D01*
+X0300316Y0038209D01*
+X0299600Y0036482D01*
+X0299600Y0034612D01*
+X0300316Y0032884D01*
+X0301638Y0031562D01*
+X0303365Y0030847D01*
+X0305235Y0030847D01*
+X0306962Y0031562D01*
+X0308284Y0032884D01*
+X0309000Y0034612D01*
+X0309000Y0036482D01*
+X0308284Y0038209D01*
+X0306962Y0039531D01*
+X0305718Y0040047D01*
+X0306962Y0040562D01*
+X0308284Y0041884D01*
+X0309000Y0043612D01*
+X0309000Y0045482D01*
+X0308284Y0047209D01*
+X0306962Y0048531D01*
+X0305235Y0049247D01*
+X0303365Y0049247D01*
+X0305346Y0049201D02*
+X0323254Y0049201D01*
+X0323365Y0049247D02*
+X0321638Y0048531D01*
+X0320316Y0047209D01*
+X0319600Y0045482D01*
+X0319600Y0043612D01*
+X0320316Y0041884D01*
+X0321638Y0040562D01*
+X0322882Y0040047D01*
+X0321638Y0039531D01*
+X0320316Y0038209D01*
+X0319600Y0036482D01*
+X0319600Y0034612D01*
+X0320316Y0032884D01*
+X0321638Y0031562D01*
+X0323365Y0030847D01*
+X0325235Y0030847D01*
+X0326962Y0031562D01*
+X0328284Y0032884D01*
+X0329000Y0034612D01*
+X0329000Y0036482D01*
+X0328284Y0038209D01*
+X0326962Y0039531D01*
+X0325718Y0040047D01*
+X0326962Y0040562D01*
+X0328284Y0041884D01*
+X0329000Y0043612D01*
+X0329000Y0045482D01*
+X0328284Y0047209D01*
+X0326962Y0048531D01*
+X0325235Y0049247D01*
+X0323365Y0049247D01*
+X0325346Y0049201D02*
+X0378050Y0049201D01*
+X0378050Y0050399D02*
+X0275522Y0050399D01*
+X0290200Y0043208D02*
+X0191667Y0043208D01*
+X0187086Y0043208D02*
+X0186514Y0043208D01*
+X0186514Y0044406D02*
+X0187086Y0044406D01*
+X0187086Y0045605D02*
+X0186514Y0045605D01*
+X0186514Y0048002D02*
+X0187086Y0048002D01*
+X0187086Y0049201D02*
+X0186514Y0049201D01*
+X0186514Y0050399D02*
+X0187086Y0050399D01*
+X0187086Y0052796D02*
+X0186514Y0052796D01*
+X0186514Y0053995D02*
+X0187086Y0053995D01*
+X0187086Y0055193D02*
+X0186514Y0055193D01*
+X0186514Y0056392D02*
+X0187086Y0056392D01*
+X0187086Y0057333D02*
+X0193943Y0057333D01*
+X0193943Y0057391D01*
+X0193836Y0058070D01*
+X0193623Y0058725D01*
+X0193311Y0059338D01*
+X0192906Y0059895D01*
+X0192420Y0060381D01*
+X0191863Y0060786D01*
+X0191250Y0061098D01*
+X0190595Y0061311D01*
+X0189916Y0061418D01*
+X0187086Y0061418D01*
+X0187086Y0057333D01*
+X0187086Y0057590D02*
+X0186514Y0057590D01*
+X0186514Y0058789D02*
+X0187086Y0058789D01*
+X0187086Y0059987D02*
+X0186514Y0059987D01*
+X0186514Y0061186D02*
+X0187086Y0061186D01*
+X0190561Y0062075D02*
+X0183039Y0062075D01*
+X0181212Y0062832D01*
+X0179814Y0064230D01*
+X0179057Y0066058D01*
+X0179057Y0068036D01*
+X0179814Y0069863D01*
+X0181212Y0071261D01*
+X0183039Y0072018D01*
+X0190561Y0072018D01*
+X0192388Y0071261D01*
+X0193786Y0069863D01*
+X0194543Y0068036D01*
+X0194543Y0066058D01*
+X0193786Y0064230D01*
+X0192388Y0062832D01*
+X0190561Y0062075D01*
+X0191307Y0062384D02*
+X0207208Y0062384D01*
+X0206486Y0061186D02*
+X0190980Y0061186D01*
+X0192814Y0059987D02*
+X0206194Y0059987D01*
+X0206244Y0058789D02*
+X0193591Y0058789D01*
+X0193912Y0057590D02*
+X0206640Y0057590D01*
+X0207523Y0056392D02*
+X0193894Y0056392D01*
+X0193534Y0055193D02*
+X0210092Y0055193D01*
+X0210264Y0055193D02*
+X0210836Y0055193D01*
+X0210836Y0056392D02*
+X0210264Y0056392D01*
+X0210264Y0057590D02*
+X0210836Y0057590D01*
+X0210836Y0058789D02*
+X0210264Y0058789D01*
+X0210264Y0059987D02*
+X0210836Y0059987D01*
+X0210836Y0061186D02*
+X0210264Y0061186D01*
+X0210264Y0062384D02*
+X0210836Y0062384D01*
+X0210836Y0063583D02*
+X0210264Y0063583D01*
+X0208842Y0063583D02*
+X0193139Y0063583D01*
+X0194015Y0064781D02*
+X0209063Y0064781D01*
+X0207086Y0065980D02*
+X0194511Y0065980D01*
+X0194543Y0067178D02*
+X0206150Y0067178D01*
+X0205653Y0068377D02*
+X0194402Y0068377D01*
+X0193906Y0069575D02*
+X0205578Y0069575D01*
+X0205677Y0070774D02*
+X0192876Y0070774D01*
+X0192388Y0072832D02*
+X0190561Y0072075D01*
+X0183039Y0072075D01*
+X0181212Y0072832D01*
+X0179814Y0074230D01*
+X0179057Y0076058D01*
+X0179057Y0078036D01*
+X0179814Y0079863D01*
+X0181212Y0081261D01*
+X0183039Y0082018D01*
+X0190561Y0082018D01*
+X0192388Y0081261D01*
+X0193786Y0079863D01*
+X0194543Y0078036D01*
+X0194543Y0076058D01*
+X0193786Y0074230D01*
+X0192388Y0072832D01*
+X0192727Y0073171D02*
+X0207143Y0073171D01*
+X0206173Y0071972D02*
+X0190672Y0071972D01*
+X0193844Y0074369D02*
+X0209201Y0074369D01*
+X0209561Y0074575D02*
+X0217082Y0074575D01*
+X0218910Y0075332D01*
+X0220308Y0076730D01*
+X0221065Y0078558D01*
+X0221065Y0080536D01*
+X0220308Y0082363D01*
+X0218910Y0083761D01*
+X0217082Y0084518D01*
+X0209561Y0084518D01*
+X0207734Y0083761D01*
+X0206335Y0082363D01*
+X0205578Y0080536D01*
+X0205578Y0078558D01*
+X0206335Y0076730D01*
+X0207734Y0075332D01*
+X0209561Y0074575D01*
+X0207498Y0075568D02*
+X0194340Y0075568D01*
+X0194543Y0076766D02*
+X0206320Y0076766D01*
+X0205824Y0077965D02*
+X0194543Y0077965D01*
+X0194076Y0079163D02*
+X0205578Y0079163D01*
+X0205578Y0080362D02*
+X0193287Y0080362D01*
+X0191666Y0081560D02*
+X0206003Y0081560D01*
+X0206731Y0082759D02*
+X0192211Y0082759D01*
+X0192388Y0082832D02*
+X0193786Y0084230D01*
+X0194543Y0086058D01*
+X0194543Y0088036D01*
+X0193786Y0089863D01*
+X0192388Y0091261D01*
+X0190561Y0092018D01*
+X0183039Y0092018D01*
+X0181212Y0091261D01*
+X0179814Y0089863D01*
+X0179057Y0088036D01*
+X0179057Y0086058D01*
+X0179814Y0084230D01*
+X0181212Y0082832D01*
+X0183039Y0082075D01*
+X0190561Y0082075D01*
+X0192388Y0082832D01*
+X0193513Y0083957D02*
+X0208207Y0083957D01*
+X0208159Y0085156D02*
+X0194170Y0085156D01*
+X0194543Y0086354D02*
+X0206711Y0086354D01*
+X0205995Y0087553D02*
+X0194543Y0087553D01*
+X0194247Y0088751D02*
+X0205578Y0088751D01*
+X0205578Y0089950D02*
+X0193699Y0089950D01*
+X0192501Y0091148D02*
+X0205832Y0091148D01*
+X0206329Y0092347D02*
+X0191217Y0092347D01*
+X0190561Y0092075D02*
+X0192388Y0092832D01*
+X0193786Y0094230D01*
+X0194543Y0096058D01*
+X0194543Y0098036D01*
+X0193786Y0099863D01*
+X0192388Y0101261D01*
+X0190561Y0102018D01*
+X0183039Y0102018D01*
+X0181212Y0101261D01*
+X0179814Y0099863D01*
+X0179057Y0098036D01*
+X0179057Y0096058D01*
+X0179814Y0094230D01*
+X0181212Y0092832D01*
+X0183039Y0092075D01*
+X0190561Y0092075D01*
+X0193101Y0093545D02*
+X0207518Y0093545D01*
+X0209153Y0094744D02*
+X0193999Y0094744D01*
+X0194496Y0095942D02*
+X0207123Y0095942D01*
+X0206165Y0097141D02*
+X0194543Y0097141D01*
+X0194417Y0098340D02*
+X0205669Y0098340D01*
+X0205578Y0099538D02*
+X0193921Y0099538D01*
+X0192913Y0100737D02*
+X0205662Y0100737D01*
+X0206158Y0101935D02*
+X0190762Y0101935D01*
+X0182838Y0101935D02*
+X0111050Y0101935D01*
+X0111050Y0103134D02*
+X0207106Y0103134D01*
+X0209111Y0104332D02*
+X0111050Y0104332D01*
+X0111050Y0105531D02*
+X0207535Y0105531D01*
+X0206337Y0106729D02*
+X0111050Y0106729D01*
+X0112913Y0100737D02*
+X0180687Y0100737D01*
+X0179679Y0099538D02*
+X0113921Y0099538D01*
+X0114417Y0098340D02*
+X0179183Y0098340D01*
+X0179057Y0097141D02*
+X0114543Y0097141D01*
+X0114496Y0095942D02*
+X0179104Y0095942D01*
+X0179601Y0094744D02*
+X0113999Y0094744D01*
+X0113101Y0093545D02*
+X0180499Y0093545D01*
+X0182383Y0092347D02*
+X0111217Y0092347D01*
+X0112501Y0091148D02*
+X0181099Y0091148D01*
+X0179901Y0089950D02*
+X0113699Y0089950D01*
+X0114247Y0088751D02*
+X0179353Y0088751D01*
+X0179057Y0087553D02*
+X0114543Y0087553D01*
+X0114543Y0086354D02*
+X0179057Y0086354D01*
+X0179430Y0085156D02*
+X0114170Y0085156D01*
+X0113513Y0083957D02*
+X0180087Y0083957D01*
+X0181389Y0082759D02*
+X0112211Y0082759D01*
+X0111666Y0081560D02*
+X0181934Y0081560D01*
+X0180313Y0080362D02*
+X0113287Y0080362D01*
+X0114076Y0079163D02*
+X0179524Y0079163D01*
+X0179057Y0077965D02*
+X0114543Y0077965D01*
+X0114543Y0076766D02*
+X0179057Y0076766D01*
+X0179260Y0075568D02*
+X0114340Y0075568D01*
+X0113844Y0074369D02*
+X0179756Y0074369D01*
+X0180873Y0073171D02*
+X0112727Y0073171D01*
+X0110672Y0071972D02*
+X0182928Y0071972D01*
+X0180724Y0070774D02*
+X0112876Y0070774D01*
+X0113906Y0069575D02*
+X0179694Y0069575D01*
+X0179198Y0068377D02*
+X0114402Y0068377D01*
+X0114543Y0067178D02*
+X0179057Y0067178D01*
+X0179089Y0065980D02*
+X0114511Y0065980D01*
+X0114015Y0064781D02*
+X0179585Y0064781D01*
+X0180461Y0063583D02*
+X0113139Y0063583D01*
+X0111307Y0062384D02*
+X0182293Y0062384D01*
+X0182620Y0061186D02*
+X0112464Y0061186D01*
+X0113662Y0059987D02*
+X0180786Y0059987D01*
+X0180009Y0058789D02*
+X0114231Y0058789D01*
+X0114543Y0057590D02*
+X0179688Y0057590D01*
+X0179706Y0056392D02*
+X0114543Y0056392D01*
+X0114185Y0055193D02*
+X0180066Y0055193D01*
+X0180898Y0053995D02*
+X0113551Y0053995D01*
+X0112301Y0052796D02*
+X0182963Y0052796D01*
+X0181205Y0050399D02*
+X0112395Y0050399D01*
+X0113381Y0049201D02*
+X0180219Y0049201D01*
+X0179754Y0048002D02*
+X0113846Y0048002D01*
+X0113700Y0045605D02*
+X0179900Y0045605D01*
+X0180543Y0044406D02*
+X0113057Y0044406D01*
+X0111667Y0043208D02*
+X0181933Y0043208D01*
+X0192702Y0053995D02*
+X0208297Y0053995D01*
+X0219557Y0065980D02*
+X0261543Y0065980D01*
+X0260606Y0067178D02*
+X0220494Y0067178D01*
+X0220990Y0068377D02*
+X0260110Y0068377D01*
+X0260035Y0069575D02*
+X0221065Y0069575D01*
+X0220966Y0070774D02*
+X0260134Y0070774D01*
+X0260630Y0071972D02*
+X0220470Y0071972D01*
+X0219500Y0073171D02*
+X0261600Y0073171D01*
+X0263658Y0074369D02*
+X0217442Y0074369D01*
+X0219145Y0075568D02*
+X0263186Y0075568D01*
+X0261623Y0076766D02*
+X0220323Y0076766D01*
+X0220819Y0077965D02*
+X0260924Y0077965D01*
+X0260641Y0079163D02*
+X0221065Y0079163D01*
+X0221065Y0080362D02*
+X0260710Y0080362D01*
+X0261126Y0081560D02*
+X0220640Y0081560D01*
+X0219912Y0082759D02*
+X0262036Y0082759D01*
+X0263610Y0094744D02*
+X0217490Y0094744D01*
+X0219483Y0125905D02*
+X0261617Y0125905D01*
+X0260637Y0127104D02*
+X0220463Y0127104D01*
+X0220959Y0128302D02*
+X0260141Y0128302D01*
+X0260035Y0129501D02*
+X0221065Y0129501D01*
+X0220997Y0130699D02*
+X0260103Y0130699D01*
+X0260599Y0131898D02*
+X0220501Y0131898D01*
+X0219575Y0133096D02*
+X0261525Y0133096D01*
+X0274314Y0146280D02*
+X0276690Y0146280D01*
+X0275850Y0147478D02*
+X0275075Y0147478D01*
+X0275522Y0148677D02*
+X0275850Y0148677D01*
+X0275850Y0149875D02*
+X0275522Y0149875D01*
+X0275299Y0151074D02*
+X0275850Y0151074D01*
+X0275850Y0152273D02*
+X0274802Y0152273D01*
+X0275850Y0153471D02*
+X0273657Y0153471D01*
+X0271767Y0154670D02*
+X0276577Y0154670D01*
+X0277816Y0155868D02*
+X0273902Y0155868D01*
+X0274904Y0157067D02*
+X0278013Y0157067D01*
+X0278634Y0158265D02*
+X0275400Y0158265D01*
+X0275522Y0159464D02*
+X0280241Y0159464D01*
+X0289243Y0161861D02*
+X0294200Y0161861D01*
+X0294200Y0163059D02*
+X0290250Y0163059D01*
+X0290250Y0164258D02*
+X0294200Y0164258D01*
+X0294200Y0165456D02*
+X0290250Y0165456D01*
+X0290250Y0166655D02*
+X0294200Y0166655D01*
+X0294200Y0167853D02*
+X0290250Y0167853D01*
+X0290250Y0169052D02*
+X0294200Y0169052D01*
+X0294200Y0170250D02*
+X0289690Y0170250D01*
+X0294200Y0171449D02*
+X0284534Y0171449D01*
+X0284534Y0172647D02*
+X0294200Y0172647D01*
+X0294200Y0173846D02*
+X0284117Y0173846D01*
+X0283187Y0175044D02*
+X0294200Y0175044D01*
+X0283650Y0194220D02*
+X0282450Y0194220D01*
+X0282450Y0195419D02*
+X0283650Y0195419D01*
+X0283650Y0196617D02*
+X0282450Y0196617D01*
+X0282450Y0200213D02*
+X0283650Y0200213D01*
+X0283650Y0201411D02*
+X0282450Y0201411D01*
+X0276924Y0201411D02*
+X0199320Y0201411D01*
+X0200319Y0200213D02*
+X0276450Y0200213D01*
+X0228336Y0215794D02*
+X0227764Y0215794D01*
+X0227764Y0216992D02*
+X0228336Y0216992D01*
+X0228336Y0218191D02*
+X0227764Y0218191D01*
+X0227764Y0220588D02*
+X0228336Y0220588D01*
+X0228336Y0221786D02*
+X0227764Y0221786D01*
+X0227764Y0222985D02*
+X0228336Y0222985D01*
+X0213324Y0250550D02*
+X0210276Y0250550D01*
+X0211200Y0251749D02*
+X0212400Y0251749D01*
+X0212400Y0252947D02*
+X0211200Y0252947D01*
+X0211200Y0253597D02*
+X0211200Y0255119D01*
+X0208623Y0257697D01*
+X0207100Y0257697D01*
+X0207100Y0253597D01*
+X0211200Y0253597D01*
+X0211200Y0254146D02*
+X0212400Y0254146D01*
+X0212625Y0255344D02*
+X0210975Y0255344D01*
+X0209776Y0256543D02*
+X0213824Y0256543D01*
+X0207100Y0256543D02*
+X0206500Y0256543D01*
+X0206500Y0255344D02*
+X0207100Y0255344D01*
+X0207100Y0254146D02*
+X0206500Y0254146D01*
+X0206500Y0252947D02*
+X0207100Y0252947D01*
+X0207100Y0251749D02*
+X0206500Y0251749D01*
+X0206500Y0250550D02*
+X0207100Y0250550D01*
+X0207100Y0249352D02*
+X0206500Y0249352D01*
+X0258820Y0267330D02*
+X0106968Y0267330D01*
+X0106968Y0268528D02*
+X0259212Y0268528D01*
+X0259862Y0269727D02*
+X0106968Y0269727D01*
+X0106968Y0270925D02*
+X0260913Y0270925D01*
+X0168529Y0193022D02*
+X0163550Y0193022D01*
+X0163550Y0191823D02*
+X0167192Y0191823D01*
+X0166684Y0190625D02*
+X0163550Y0190625D01*
+X0163550Y0189426D02*
+X0166566Y0189426D01*
+X0166784Y0188228D02*
+X0163550Y0188228D01*
+X0163550Y0187029D02*
+X0167433Y0187029D01*
+X0167550Y0185831D02*
+X0163550Y0185831D01*
+X0163550Y0184632D02*
+X0167550Y0184632D01*
+X0167550Y0183434D02*
+X0163550Y0183434D01*
+X0163550Y0182235D02*
+X0167550Y0182235D01*
+X0167550Y0181037D02*
+X0163550Y0181037D01*
+X0163550Y0179838D02*
+X0167550Y0179838D01*
+X0167550Y0178640D02*
+X0163550Y0178640D01*
+X0163550Y0177441D02*
+X0167550Y0177441D01*
+X0167550Y0176243D02*
+X0163550Y0176243D01*
+X0164139Y0175044D02*
+X0166961Y0175044D01*
+X0166566Y0173846D02*
+X0164534Y0173846D01*
+X0164534Y0172647D02*
+X0166566Y0172647D01*
+X0167003Y0171449D02*
+X0164097Y0171449D01*
+X0163138Y0170250D02*
+X0167962Y0170250D01*
+X0209333Y0154670D02*
+X0001800Y0154670D01*
+X0001800Y0057590D02*
+X0016888Y0057590D01*
+X0016395Y0056392D02*
+X0001800Y0056392D01*
+X0001800Y0045605D02*
+X0099900Y0045605D01*
+X0100543Y0044406D02*
+X0001800Y0044406D01*
+X0001800Y0043208D02*
+X0101933Y0043208D01*
+X0106514Y0043208D02*
+X0107086Y0043208D01*
+X0107086Y0044406D02*
+X0106514Y0044406D01*
+X0106514Y0045605D02*
+X0107086Y0045605D01*
+X0107086Y0049201D02*
+X0106514Y0049201D01*
+X0106514Y0050399D02*
+X0107086Y0050399D01*
+X0101205Y0050399D02*
+X0089499Y0050399D01*
+X0078213Y0030024D02*
+X0378050Y0030024D01*
+X0378050Y0028826D02*
+X0080299Y0028826D01*
+X0081312Y0027627D02*
+X0378050Y0027627D01*
+X0378050Y0026429D02*
+X0081809Y0026429D01*
+X0081968Y0025230D02*
+X0378050Y0025230D01*
+X0378050Y0024032D02*
+X0081968Y0024032D01*
+X0081968Y0022833D02*
+X0378050Y0022833D01*
+X0378050Y0021635D02*
+X0081968Y0021635D01*
+X0081968Y0020436D02*
+X0378050Y0020436D01*
+X0378050Y0019238D02*
+X0081968Y0019238D01*
+X0081964Y0018039D02*
+X0378050Y0018039D01*
+X0378050Y0031223D02*
+X0326143Y0031223D01*
+X0327821Y0032421D02*
+X0378050Y0032421D01*
+X0378050Y0033620D02*
+X0328589Y0033620D01*
+X0329000Y0034818D02*
+X0378050Y0034818D01*
+X0378050Y0036017D02*
+X0329000Y0036017D01*
+X0328696Y0037215D02*
+X0378050Y0037215D01*
+X0378050Y0038414D02*
+X0328080Y0038414D01*
+X0326766Y0039612D02*
+X0378050Y0039612D01*
+X0378050Y0040811D02*
+X0327211Y0040811D01*
+X0328336Y0042009D02*
+X0378050Y0042009D01*
+X0378050Y0043208D02*
+X0328833Y0043208D01*
+X0329000Y0044406D02*
+X0378050Y0044406D01*
+X0378050Y0045605D02*
+X0328949Y0045605D01*
+X0328452Y0046804D02*
+X0378050Y0046804D01*
+X0378050Y0048002D02*
+X0327491Y0048002D01*
+X0321109Y0048002D02*
+X0316643Y0048002D01*
+X0315998Y0048647D02*
+X0318400Y0046245D01*
+X0318400Y0044547D01*
+X0314300Y0044547D01*
+X0314300Y0044547D01*
+X0314300Y0048647D01*
+X0315998Y0048647D01*
+X0314300Y0048647D02*
+X0312602Y0048647D01*
+X0310200Y0046245D01*
+X0310200Y0044547D01*
+X0314300Y0044547D01*
+X0314300Y0048647D01*
+X0314300Y0048002D02*
+X0314300Y0048002D01*
+X0314300Y0046804D02*
+X0314300Y0046804D01*
+X0314300Y0045605D02*
+X0314300Y0045605D01*
+X0314300Y0044547D02*
+X0314300Y0044547D01*
+X0314300Y0044547D01*
+X0318400Y0044547D01*
+X0318400Y0042848D01*
+X0315998Y0040447D01*
+X0314300Y0040447D01*
+X0314300Y0044547D01*
+X0310200Y0044547D01*
+X0310200Y0042848D01*
+X0312602Y0040447D01*
+X0314300Y0040447D01*
+X0314300Y0044547D01*
+X0314300Y0044547D01*
+X0314300Y0044406D02*
+X0314300Y0044406D01*
+X0314300Y0043208D02*
+X0314300Y0043208D01*
+X0314300Y0042009D02*
+X0314300Y0042009D01*
+X0314300Y0040811D02*
+X0314300Y0040811D01*
+X0316247Y0040247D02*
+X0312353Y0040247D01*
+X0309600Y0037493D01*
+X0309600Y0033600D01*
+X0312353Y0030847D01*
+X0316247Y0030847D01*
+X0319000Y0033600D01*
+X0319000Y0037493D01*
+X0316247Y0040247D01*
+X0316363Y0040811D02*
+X0321389Y0040811D01*
+X0321834Y0039612D02*
+X0316881Y0039612D01*
+X0318080Y0038414D02*
+X0320520Y0038414D01*
+X0319904Y0037215D02*
+X0319000Y0037215D01*
+X0319000Y0036017D02*
+X0319600Y0036017D01*
+X0319600Y0034818D02*
+X0319000Y0034818D01*
+X0319000Y0033620D02*
+X0320011Y0033620D01*
+X0320778Y0032421D02*
+X0317821Y0032421D01*
+X0316623Y0031223D02*
+X0322457Y0031223D01*
+X0311977Y0031223D02*
+X0306143Y0031223D01*
+X0307821Y0032421D02*
+X0310779Y0032421D01*
+X0309600Y0033620D02*
+X0308589Y0033620D01*
+X0309000Y0034818D02*
+X0309600Y0034818D01*
+X0309600Y0036017D02*
+X0309000Y0036017D01*
+X0308696Y0037215D02*
+X0309600Y0037215D01*
+X0310520Y0038414D02*
+X0308080Y0038414D01*
+X0306766Y0039612D02*
+X0311719Y0039612D01*
+X0312237Y0040811D02*
+X0307211Y0040811D01*
+X0308336Y0042009D02*
+X0311039Y0042009D01*
+X0310200Y0043208D02*
+X0308833Y0043208D01*
+X0309000Y0044406D02*
+X0310200Y0044406D01*
+X0310200Y0045605D02*
+X0308949Y0045605D01*
+X0308452Y0046804D02*
+X0310759Y0046804D01*
+X0311957Y0048002D02*
+X0307491Y0048002D01*
+X0301109Y0048002D02*
+X0296643Y0048002D01*
+X0297841Y0046804D02*
+X0300148Y0046804D01*
+X0299651Y0045605D02*
+X0298400Y0045605D01*
+X0298400Y0044406D02*
+X0299600Y0044406D01*
+X0299767Y0043208D02*
+X0298400Y0043208D01*
+X0297561Y0042009D02*
+X0300264Y0042009D01*
+X0301389Y0040811D02*
+X0296363Y0040811D01*
+X0295998Y0039647D02*
+X0298400Y0037245D01*
+X0298400Y0035547D01*
+X0294300Y0035547D01*
+X0294300Y0035547D01*
+X0294300Y0039647D01*
+X0295998Y0039647D01*
+X0296032Y0039612D02*
+X0301834Y0039612D01*
+X0300520Y0038414D02*
+X0297231Y0038414D01*
+X0298400Y0037215D02*
+X0299904Y0037215D01*
+X0299600Y0036017D02*
+X0298400Y0036017D01*
+X0298400Y0035547D02*
+X0294300Y0035547D01*
+X0294300Y0039647D01*
+X0292602Y0039647D01*
+X0290200Y0037245D01*
+X0290200Y0035547D01*
+X0294300Y0035547D01*
+X0294300Y0035547D01*
+X0294300Y0035547D01*
+X0290200Y0035547D01*
+X0290200Y0033848D01*
+X0292602Y0031447D01*
+X0294300Y0031447D01*
+X0295998Y0031447D01*
+X0298400Y0033848D01*
+X0298400Y0035547D01*
+X0298400Y0034818D02*
+X0299600Y0034818D01*
+X0300011Y0033620D02*
+X0298171Y0033620D01*
+X0296973Y0032421D02*
+X0300778Y0032421D01*
+X0302457Y0031223D02*
+X0001800Y0031223D01*
+X0001800Y0032421D02*
+X0291627Y0032421D01*
+X0290429Y0033620D02*
+X0001800Y0033620D01*
+X0001800Y0034818D02*
+X0290200Y0034818D01*
+X0290200Y0036017D02*
+X0001800Y0036017D01*
+X0001800Y0037215D02*
+X0290200Y0037215D01*
+X0291369Y0038414D02*
+X0001800Y0038414D01*
+X0001800Y0039612D02*
+X0292567Y0039612D01*
+X0292237Y0040811D02*
+X0001800Y0040811D01*
+X0001800Y0042009D02*
+X0291039Y0042009D01*
+X0294300Y0042009D02*
+X0294300Y0042009D01*
+X0294300Y0040811D02*
+X0294300Y0040811D01*
+X0294300Y0040447D02*
+X0294300Y0044547D01*
+X0294300Y0044547D01*
+X0294300Y0040447D01*
+X0294300Y0039612D02*
+X0294300Y0039612D01*
+X0294300Y0038414D02*
+X0294300Y0038414D01*
+X0294300Y0037215D02*
+X0294300Y0037215D01*
+X0294300Y0036017D02*
+X0294300Y0036017D01*
+X0294300Y0035547D02*
+X0294300Y0031447D01*
+X0294300Y0035547D01*
+X0294300Y0035547D01*
+X0294300Y0034818D02*
+X0294300Y0034818D01*
+X0294300Y0033620D02*
+X0294300Y0033620D01*
+X0294300Y0032421D02*
+X0294300Y0032421D01*
+X0294300Y0043208D02*
+X0294300Y0043208D01*
+X0294300Y0044406D02*
+X0294300Y0044406D01*
+X0294300Y0045605D02*
+X0294300Y0045605D01*
+X0294300Y0046804D02*
+X0294300Y0046804D01*
+X0294300Y0048002D02*
+X0294300Y0048002D01*
+X0292927Y0058789D02*
+X0378050Y0058789D01*
+X0378050Y0059987D02*
+X0294009Y0059987D01*
+X0294506Y0061186D02*
+X0378050Y0061186D01*
+X0378050Y0062384D02*
+X0303973Y0062384D01*
+X0304057Y0062419D02*
+X0305178Y0063540D01*
+X0305784Y0065004D01*
+X0305784Y0066589D01*
+X0305178Y0068054D01*
+X0304057Y0069174D01*
+X0302593Y0069781D01*
+X0302300Y0069781D01*
+X0302300Y0086912D01*
+X0302678Y0087290D01*
+X0303284Y0088754D01*
+X0303284Y0090339D01*
+X0302678Y0091804D01*
+X0301557Y0092924D01*
+X0300093Y0093531D01*
+X0298507Y0093531D01*
+X0297043Y0092924D01*
+X0295922Y0091804D01*
+X0295316Y0090339D01*
+X0295316Y0088754D01*
+X0295922Y0087290D01*
+X0296300Y0086912D01*
+X0296300Y0067700D01*
+X0296757Y0066597D01*
+X0297601Y0065753D01*
+X0297816Y0065538D01*
+X0297816Y0065004D01*
+X0298422Y0063540D01*
+X0299543Y0062419D01*
+X0301007Y0061812D01*
+X0302593Y0061812D01*
+X0304057Y0062419D01*
+X0305195Y0063583D02*
+X0378050Y0063583D01*
+X0378050Y0064781D02*
+X0305692Y0064781D01*
+X0305784Y0065980D02*
+X0378050Y0065980D01*
+X0378050Y0067178D02*
+X0305540Y0067178D01*
+X0304855Y0068377D02*
+X0378050Y0068377D01*
+X0378050Y0069575D02*
+X0303089Y0069575D01*
+X0302300Y0070774D02*
+X0378050Y0070774D01*
+X0378050Y0071972D02*
+X0302300Y0071972D01*
+X0302300Y0073171D02*
+X0378050Y0073171D01*
+X0378050Y0074369D02*
+X0302300Y0074369D01*
+X0302300Y0075568D02*
+X0378050Y0075568D01*
+X0378050Y0076766D02*
+X0302300Y0076766D01*
+X0302300Y0077965D02*
+X0304129Y0077965D01*
+X0304118Y0077984D02*
+X0304329Y0077619D01*
+X0304627Y0077321D01*
+X0304991Y0077111D01*
+X0305398Y0077002D01*
+X0310009Y0077002D01*
+X0310009Y0083002D01*
+X0304009Y0083002D01*
+X0304009Y0078391D01*
+X0304118Y0077984D01*
+X0304009Y0079163D02*
+X0302300Y0079163D01*
+X0302300Y0080362D02*
+X0304009Y0080362D01*
+X0304009Y0081560D02*
+X0302300Y0081560D01*
+X0302300Y0082759D02*
+X0304009Y0082759D01*
+X0304009Y0084202D02*
+X0310009Y0084202D01*
+X0310009Y0090202D01*
+X0305398Y0090202D01*
+X0304991Y0090093D01*
+X0304627Y0089882D01*
+X0304329Y0089584D01*
+X0304118Y0089219D01*
+X0304009Y0088812D01*
+X0304009Y0084202D01*
+X0304009Y0085156D02*
+X0302300Y0085156D01*
+X0302300Y0086354D02*
+X0304009Y0086354D01*
+X0304009Y0087553D02*
+X0302787Y0087553D01*
+X0303283Y0088751D02*
+X0304009Y0088751D01*
+X0303284Y0089950D02*
+X0304744Y0089950D01*
+X0302949Y0091148D02*
+X0378050Y0091148D01*
+X0378050Y0089950D02*
+X0316474Y0089950D01*
+X0316591Y0089882D02*
+X0316227Y0090093D01*
+X0315820Y0090202D01*
+X0311209Y0090202D01*
+X0311209Y0084202D01*
+X0310009Y0084202D01*
+X0310009Y0083002D01*
+X0311209Y0083002D01*
+X0311209Y0084202D01*
+X0317209Y0084202D01*
+X0317209Y0088812D01*
+X0317100Y0089219D01*
+X0316889Y0089584D01*
+X0316591Y0089882D01*
+X0317209Y0088751D02*
+X0378050Y0088751D01*
+X0378050Y0087553D02*
+X0317209Y0087553D01*
+X0317209Y0086354D02*
+X0378050Y0086354D01*
+X0378050Y0085156D02*
+X0317209Y0085156D01*
+X0317209Y0083002D02*
+X0311209Y0083002D01*
+X0311209Y0077002D01*
+X0315820Y0077002D01*
+X0316227Y0077111D01*
+X0316591Y0077321D01*
+X0316889Y0077619D01*
+X0317100Y0077984D01*
+X0317209Y0078391D01*
+X0317209Y0083002D01*
+X0317209Y0082759D02*
+X0378050Y0082759D01*
+X0378050Y0083957D02*
+X0311209Y0083957D01*
+X0311209Y0082759D02*
+X0310009Y0082759D01*
+X0310009Y0083957D02*
+X0302300Y0083957D01*
+X0296300Y0083957D02*
+X0290382Y0083957D01*
+X0291580Y0082759D02*
+X0296300Y0082759D01*
+X0296300Y0081560D02*
+X0292779Y0081560D01*
+X0293460Y0080362D02*
+X0296300Y0080362D01*
+X0296300Y0079163D02*
+X0293550Y0079163D01*
+X0293550Y0077965D02*
+X0296300Y0077965D01*
+X0296300Y0076766D02*
+X0293550Y0076766D01*
+X0293550Y0075568D02*
+X0296300Y0075568D01*
+X0296300Y0074369D02*
+X0293550Y0074369D01*
+X0293550Y0073171D02*
+X0296300Y0073171D01*
+X0296300Y0071972D02*
+X0293550Y0071972D01*
+X0293550Y0070774D02*
+X0296300Y0070774D01*
+X0296300Y0069575D02*
+X0293550Y0069575D01*
+X0293550Y0068377D02*
+X0296300Y0068377D01*
+X0296516Y0067178D02*
+X0293550Y0067178D01*
+X0293550Y0065980D02*
+X0297374Y0065980D01*
+X0297908Y0064781D02*
+X0293550Y0064781D01*
+X0294226Y0063583D02*
+X0298405Y0063583D01*
+X0299627Y0062384D02*
+X0294534Y0062384D01*
+X0310009Y0077965D02*
+X0311209Y0077965D01*
+X0311209Y0079163D02*
+X0310009Y0079163D01*
+X0310009Y0080362D02*
+X0311209Y0080362D01*
+X0311209Y0081560D02*
+X0310009Y0081560D01*
+X0310009Y0085156D02*
+X0311209Y0085156D01*
+X0311209Y0086354D02*
+X0310009Y0086354D01*
+X0310009Y0087553D02*
+X0311209Y0087553D01*
+X0311209Y0088751D02*
+X0310009Y0088751D01*
+X0310009Y0089950D02*
+X0311209Y0089950D01*
+X0306939Y0095942D02*
+X0283688Y0095942D01*
+X0282490Y0094744D02*
+X0378050Y0094744D01*
+X0378050Y0095942D02*
+X0345411Y0095942D01*
+X0346635Y0097141D02*
+X0378050Y0097141D01*
+X0378050Y0098340D02*
+X0346900Y0098340D01*
+X0346900Y0099538D02*
+X0355776Y0099538D01*
+X0355190Y0100737D02*
+X0346900Y0100737D01*
+X0346900Y0101935D02*
+X0355190Y0101935D01*
+X0361190Y0101935D02*
+X0362390Y0101935D01*
+X0362390Y0100737D02*
+X0361190Y0100737D01*
+X0361190Y0099538D02*
+X0362390Y0099538D01*
+X0367804Y0099538D02*
+X0378050Y0099538D01*
+X0378050Y0100737D02*
+X0368390Y0100737D01*
+X0368390Y0101935D02*
+X0378050Y0101935D01*
+X0378050Y0107928D02*
+X0346900Y0107928D01*
+X0346900Y0109126D02*
+X0359956Y0109126D01*
+X0361190Y0106729D02*
+X0362390Y0106729D01*
+X0362390Y0105531D02*
+X0361190Y0105531D01*
+X0378050Y0093545D02*
+X0281948Y0093545D01*
+X0281451Y0092347D02*
+X0296466Y0092347D01*
+X0295651Y0091148D02*
+X0280257Y0091148D01*
+X0283880Y0089950D02*
+X0295316Y0089950D01*
+X0295317Y0088751D02*
+X0285588Y0088751D01*
+X0286786Y0087553D02*
+X0295813Y0087553D01*
+X0296300Y0086354D02*
+X0287985Y0086354D01*
+X0289183Y0085156D02*
+X0296300Y0085156D01*
+X0302134Y0092347D02*
+X0378050Y0092347D01*
+X0378050Y0081560D02*
+X0317209Y0081560D01*
+X0317209Y0080362D02*
+X0378050Y0080362D01*
+X0378050Y0079163D02*
+X0317209Y0079163D01*
+X0317089Y0077965D02*
+X0378050Y0077965D01*
+X0320148Y0046804D02*
+X0317841Y0046804D01*
+X0318400Y0045605D02*
+X0319651Y0045605D01*
+X0319600Y0044406D02*
+X0318400Y0044406D01*
+X0318400Y0043208D02*
+X0319767Y0043208D01*
+X0320264Y0042009D02*
+X0317561Y0042009D01*
+X0275843Y0091148D02*
+X0275268Y0091148D01*
+X0274152Y0093545D02*
+X0273582Y0093545D01*
+X0274066Y0094744D02*
+X0271947Y0094744D01*
+X0273977Y0095942D02*
+X0274316Y0095942D01*
+X0274935Y0097141D02*
+X0275010Y0097141D01*
+X0275431Y0098340D02*
+X0276795Y0098340D01*
+X0276188Y0099538D02*
+X0275522Y0099538D01*
+X0275438Y0100737D02*
+X0275850Y0100737D01*
+X0275850Y0101935D02*
+X0274942Y0101935D01*
+X0275850Y0103134D02*
+X0273994Y0103134D01*
+X0275850Y0104332D02*
+X0271989Y0104332D01*
+X0273565Y0105531D02*
+X0275850Y0105531D01*
+X0275881Y0106729D02*
+X0274763Y0106729D01*
+X0275261Y0107928D02*
+X0277079Y0107928D01*
+X0275522Y0109126D02*
+X0305450Y0109126D01*
+X0305450Y0107928D02*
+X0289021Y0107928D01*
+X0290219Y0106729D02*
+X0305450Y0106729D01*
+X0305450Y0105531D02*
+X0290250Y0105531D01*
+X0290250Y0104332D02*
+X0305450Y0104332D01*
+X0305450Y0103134D02*
+X0290250Y0103134D01*
+X0290250Y0101935D02*
+X0305450Y0101935D01*
+X0305450Y0100737D02*
+X0290250Y0100737D01*
+X0289912Y0099538D02*
+X0305450Y0099538D01*
+X0305450Y0098340D02*
+X0285797Y0098340D01*
+X0284887Y0097141D02*
+X0305714Y0097141D01*
+X0346900Y0124707D02*
+X0362556Y0124707D01*
+X0361057Y0125905D02*
+X0346900Y0125905D01*
+X0232148Y0149875D02*
+X0221065Y0149875D01*
+X0220842Y0151074D02*
+X0230908Y0151074D01*
+X0230412Y0152273D02*
+X0220345Y0152273D01*
+X0219200Y0153471D02*
+X0230316Y0153471D01*
+X0230194Y0154670D02*
+X0217310Y0154670D01*
+X0219446Y0155868D02*
+X0229566Y0155868D01*
+X0228939Y0157067D02*
+X0220447Y0157067D01*
+X0220944Y0158265D02*
+X0228311Y0158265D01*
+X0227683Y0159464D02*
+X0221065Y0159464D01*
+X0221013Y0160662D02*
+X0227055Y0160662D01*
+X0226427Y0161861D02*
+X0220516Y0161861D01*
+X0219612Y0163059D02*
+X0225800Y0163059D01*
+X0225172Y0164258D02*
+X0217712Y0164258D01*
+X0219034Y0165456D02*
+X0224544Y0165456D01*
+X0223916Y0166655D02*
+X0220232Y0166655D01*
+X0220773Y0167853D02*
+X0223289Y0167853D01*
+X0222661Y0169052D02*
+X0221065Y0169052D01*
+X0221065Y0170250D02*
+X0222033Y0170250D01*
+X0221405Y0171449D02*
+X0220687Y0171449D01*
+X0220777Y0172647D02*
+X0220024Y0172647D01*
+X0220150Y0173846D02*
+X0218706Y0173846D01*
+X0218215Y0175044D02*
+X0219522Y0175044D01*
+X0098533Y0262536D02*
+X0093929Y0262536D01*
+X0092184Y0262536D02*
+X0091416Y0262536D01*
+X0091416Y0263734D02*
+X0092184Y0263734D01*
+X0092184Y0264933D02*
+X0091416Y0264933D01*
+X0091416Y0266131D02*
+X0092184Y0266131D01*
+X0092184Y0267330D02*
+X0091416Y0267330D01*
+X0091416Y0268528D02*
+X0092184Y0268528D01*
+X0092184Y0269727D02*
+X0096631Y0269727D01*
+X0096631Y0270925D02*
+X0096368Y0270925D01*
+X0096368Y0272124D02*
+X0096631Y0272124D01*
+X0096631Y0273322D02*
+X0096298Y0273322D01*
+X0095905Y0274521D02*
+X0097036Y0274521D01*
+X0097695Y0275719D02*
+X0095057Y0275719D01*
+X0088543Y0275719D02*
+X0085905Y0275719D01*
+X0086564Y0274521D02*
+X0087695Y0274521D01*
+X0087302Y0273322D02*
+X0086968Y0273322D01*
+X0086968Y0272124D02*
+X0087231Y0272124D01*
+X0087231Y0270925D02*
+X0086968Y0270925D01*
+X0086968Y0269727D02*
+X0091416Y0269727D01*
+X0096368Y0268528D02*
+X0096631Y0268528D01*
+X0096631Y0267330D02*
+X0096368Y0267330D01*
+X0096355Y0266131D02*
+X0096631Y0266131D01*
+X0096887Y0264933D02*
+X0096069Y0264933D01*
+X0095381Y0263734D02*
+X0097384Y0263734D01*
+X0089671Y0262536D02*
+X0085067Y0262536D01*
+X0086216Y0263734D02*
+X0088219Y0263734D01*
+X0087531Y0264933D02*
+X0086713Y0264933D01*
+X0086968Y0266131D02*
+X0087245Y0266131D01*
+X0087231Y0267330D02*
+X0086968Y0267330D01*
+X0086968Y0268528D02*
+X0087231Y0268528D01*
+X0075387Y0030024D02*
+X0058213Y0030024D01*
+X0060299Y0028826D02*
+X0064273Y0028826D01*
+X0063051Y0027627D02*
+X0061312Y0027627D01*
+X0061809Y0026429D02*
+X0062456Y0026429D01*
+X0062231Y0025230D02*
+X0061968Y0025230D01*
+X0061968Y0024032D02*
+X0062231Y0024032D01*
+X0062231Y0022833D02*
+X0061968Y0022833D01*
+X0061968Y0021635D02*
+X0062231Y0021635D01*
+X0062231Y0020436D02*
+X0061968Y0020436D01*
+X0061968Y0019238D02*
+X0062231Y0019238D01*
+X0062339Y0018039D02*
+X0061964Y0018039D01*
+X0066416Y0022833D02*
+X0067184Y0022833D01*
+X0067184Y0024032D02*
+X0066416Y0024032D01*
+X0066416Y0025230D02*
+X0067184Y0025230D01*
+X0067184Y0026429D02*
+X0066416Y0026429D01*
+X0066416Y0027627D02*
+X0067184Y0027627D01*
+X0067184Y0028826D02*
+X0066416Y0028826D01*
+X0069327Y0028826D02*
+X0073301Y0028826D01*
+X0072288Y0027627D02*
+X0070549Y0027627D01*
+X0071144Y0026429D02*
+X0071791Y0026429D01*
+X0071631Y0025230D02*
+X0071368Y0025230D01*
+X0071368Y0024032D02*
+X0071631Y0024032D01*
+X0071631Y0022833D02*
+X0071368Y0022833D01*
+X0071368Y0021635D02*
+X0071631Y0021635D01*
+X0071631Y0020436D02*
+X0071368Y0020436D01*
+X0071368Y0019238D02*
+X0071631Y0019238D01*
+X0071636Y0018039D02*
+X0071261Y0018039D01*
+X0055387Y0030024D02*
+X0001800Y0030024D01*
+X0001800Y0028826D02*
+X0053301Y0028826D01*
+X0052288Y0027627D02*
+X0001800Y0027627D01*
+X0001800Y0026429D02*
+X0051791Y0026429D01*
+X0051631Y0025230D02*
+X0001800Y0025230D01*
+X0001800Y0024032D02*
+X0051631Y0024032D01*
+X0051631Y0022833D02*
+X0001800Y0022833D01*
+X0001800Y0021635D02*
+X0051631Y0021635D01*
+X0051631Y0020436D02*
+X0001800Y0020436D01*
+X0001800Y0019238D02*
+X0051631Y0019238D01*
+X0051636Y0018039D02*
+X0001800Y0018039D01*
+D31*
+X0350550Y0125797D02*
+X0351800Y0125797D01*
+D32*
+X0083675Y0253922D02*
+X0048675Y0253922D01*
+D33*
+X0275550Y0255797D02*
+X0275550Y0219547D01*
+X0275552Y0219394D01*
+X0275558Y0219242D01*
+X0275567Y0219090D01*
+X0275581Y0218938D01*
+X0275598Y0218786D01*
+X0275619Y0218635D01*
+X0275644Y0218484D01*
+X0275673Y0218334D01*
+X0275706Y0218185D01*
+X0275742Y0218037D01*
+X0275782Y0217890D01*
+X0275826Y0217744D01*
+X0275874Y0217599D01*
+X0275925Y0217455D01*
+X0275980Y0217312D01*
+X0276038Y0217171D01*
+X0276100Y0217032D01*
+X0276166Y0216894D01*
+X0276235Y0216758D01*
+X0276307Y0216624D01*
+X0276383Y0216491D01*
+X0276462Y0216361D01*
+X0276544Y0216232D01*
+X0276630Y0216106D01*
+X0276718Y0215982D01*
+X0276810Y0215860D01*
+X0276905Y0215740D01*
+X0277003Y0215623D01*
+X0277104Y0215509D01*
+X0277208Y0215397D01*
+X0277314Y0215287D01*
+X0277424Y0215181D01*
+X0277536Y0215077D01*
+X0277650Y0214976D01*
+X0277767Y0214878D01*
+X0277887Y0214783D01*
+X0278009Y0214691D01*
+X0278133Y0214603D01*
+X0278259Y0214517D01*
+X0278388Y0214435D01*
+X0278518Y0214356D01*
+X0278651Y0214280D01*
+X0278785Y0214208D01*
+X0278921Y0214139D01*
+X0279059Y0214073D01*
+X0279198Y0214011D01*
+X0279339Y0213953D01*
+X0279482Y0213898D01*
+X0279626Y0213847D01*
+X0279771Y0213799D01*
+X0279917Y0213755D01*
+X0280064Y0213715D01*
+X0280212Y0213679D01*
+X0280361Y0213646D01*
+X0280511Y0213617D01*
+X0280662Y0213592D01*
+X0280813Y0213571D01*
+X0280965Y0213554D01*
+X0281117Y0213540D01*
+X0281269Y0213531D01*
+X0281421Y0213525D01*
+X0281574Y0213523D01*
+X0283050Y0213523D01*
+M02*
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.drd b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.drd
new file mode 100755
index 0000000..d410676
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.drd
@@ -0,0 +1,186 @@
+%
+M48
+M72
+T01C0.01969
+T02C0.02362
+T03C0.02756
+T04C0.03543
+T05C0.03600
+T06C0.03937
+T07C0.06000
+T08C0.07000
+T09C0.14173
+%
+T01
+X10550Y99547
+X55550Y164547
+X10550Y173297
+X108050Y124547
+X130550Y125797
+X160550Y173297
+X170550Y173297
+X180550Y173297
+X180550Y186058
+X170550Y189547
+X160550Y197047
+X196800Y198297
+X231800Y204547
+X251800Y204547
+X269300Y212047
+X266800Y223297
+X266800Y233297
+X284300Y233297
+X284300Y222047
+X293050Y220797
+X294300Y213297
+X290550Y205797
+X279300Y205797
+X286800Y190797
+X280550Y172047
+X288050Y158297
+X281800Y155797
+X280550Y129547
+X281800Y113297
+X303050Y122047
+X278050Y94547
+X299300Y89547
+X305550Y92047
+X326800Y89547
+X350550Y89547
+X370550Y94547
+X364300Y112047
+X370550Y125797
+X364300Y128297
+X351800Y125797
+X364300Y143297
+X368050Y158297
+X368050Y174547
+X350550Y233297
+X369300Y238297
+X369300Y272047
+X320550Y240797
+X303050Y254547
+X318050Y264547
+X243050Y232047
+X183050Y257047
+X244300Y179547
+X234300Y153297
+X249300Y147047
+X200550Y112047
+X196800Y164547
+X280550Y77047
+X290550Y62047
+X285550Y54547
+X301800Y65797
+X333050Y59547
+X365550Y67047
+X364300Y19547
+X258050Y33297
+T02
+X294300Y35547
+X294300Y44547
+X304300Y44547
+X314300Y44547
+X314300Y35547
+X304300Y35547
+X324300Y35547
+X324300Y44547
+T03
+X239300Y20797
+X186800Y20797
+X120550Y35797
+X53050Y98297
+X18050Y138297
+X119300Y165797
+X131800Y199547
+X101800Y220797
+X133050Y255797
+X146800Y234547
+X166800Y117047
+X361800Y192047
+X364300Y222047
+X364300Y229547
+T04
+X270550Y189547
+X270550Y179547
+X270550Y169547
+X270550Y159547
+X270550Y149547
+X270550Y139547
+X270550Y129547
+X270550Y119547
+X270550Y109547
+X270550Y99547
+X270550Y89547
+X270550Y79547
+X270550Y69547
+X270550Y59547
+X270550Y49547
+X210550Y49547
+X210550Y59547
+X210550Y69547
+X210550Y79547
+X210550Y89547
+X210550Y99547
+X210550Y109547
+X210550Y119547
+X210550Y129547
+X210550Y139547
+X210550Y149547
+X210550Y159547
+X210550Y169547
+X210550Y179547
+X210550Y189547
+X228050Y219547
+X186800Y97047
+X186800Y87047
+X186800Y77047
+X186800Y67047
+X186800Y57047
+X186800Y47047
+X106800Y47047
+X106800Y57047
+X106800Y67047
+X106800Y77047
+X106800Y87047
+X106800Y97047
+T05
+X196800Y243297
+X196800Y253297
+X206800Y253297
+X216800Y253297
+X226800Y253297
+X236800Y253297
+X236800Y243297
+X226800Y243297
+X216800Y243297
+X206800Y243297
+T06
+X101800Y269547
+X91800Y269547
+X81800Y269547
+X87765Y210787
+X20835Y210787
+X20835Y55275
+X56800Y22047
+X66800Y22047
+X76800Y22047
+X87765Y55275
+X343089Y166279
+X343089Y180059
+T07
+X275550Y255797
+X63050Y227047
+X45550Y227047
+T08
+X265511Y245758
+X265511Y265836
+X285589Y265836
+X285589Y245758
+T09
+X31800Y29547
+X170550Y139547
+X31800Y262047
+X345550Y262047
+X345550Y29547
+M30
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.dri b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.dri
new file mode 100755
index 0000000..de1521b
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.dri
@@ -0,0 +1,44 @@
+Generated by EAGLE CAM Processor 8.5.1
+
+Drill Station Info File: C:/Users/pc/Documents/radio/NFPR/eagle/eagle_NPR70_v05/NPR70_v05.dri
+
+ Date              : 01/02/2020 14:35
+ Drills            : generated
+ Device            : Excellon drill station, coordinate format 2.5 inch
+
+Parameter settings:
+
+ Tolerance Drill + :  2.50 %
+ Tolerance Drill - :  2.50 %
+ Rotate            : no
+ Mirror            : no
+ Optimize          : yes
+ Auto fit          : yes
+ OffsetX           : 0inch
+ OffsetY           : 0inch
+ Layers            : Drills Holes
+
+Drill File Info:
+
+ Data Mode         : Absolute
+ Units             : 1/100000 Inch
+
+Drills used:
+
+ Code  Size       used
+
+ T01   0.0197inch    64
+ T02   0.0236inch     8
+ T03   0.0276inch    14
+ T04   0.0354inch    43
+ T05   0.0360inch    10
+ T06   0.0394inch    12
+ T07   0.0600inch     3
+ T08   0.0700inch     4
+ T09   0.1417inch     5
+
+Total number of drills: 163
+
+Plotfiles:
+
+ C:/Users/pc/Documents/radio/NFPR/eagle/eagle_NPR70_v05/NPR70_v05.drd
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.gko b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.gko
new file mode 100755
index 0000000..ef513e1
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.gko
@@ -0,0 +1,17 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+%ADD10C,0.00000*%
+D10*
+X0001800Y0012047D02*
+X0001800Y0279507D01*
+X0378001Y0279507D01*
+X0378001Y0012047D01*
+X0001800Y0012047D01*
+M02*
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.gpi b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.gpi
new file mode 100755
index 0000000..60dd974
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.gpi
@@ -0,0 +1,62 @@
+Generated by EAGLE CAM Processor 8.5.1
+
+Photoplotter Info File: C:/Users/pc/Documents/radio/NFPR/eagle/eagle_NPR70_v05/NPR70_v05.gpi
+
+ Date              : 01/02/2020 14:35
+ Plotfile          : C:/Users/pc/Documents/radio/NFPR/eagle/eagle_NPR70_v05/NPR70_v05.sts
+ Apertures         : generated: 
+ Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
+
+Parameter settings:
+
+ Emulate Apertures : no
+ Tolerance Draw  + :  0.00 %
+ Tolerance Draw  - :  0.00 %
+ Tolerance Flash + :  0.00 %
+ Tolerance Flash - :  0.00 %
+ Rotate            : no
+ Mirror            : no
+ Optimize          : yes
+ Auto fit          : yes
+ OffsetX           : 0inch
+ OffsetY           : 0inch
+
+Plotfile Info:
+
+ Coordinate Format : 2.5
+ Coordinate Units  : Inch
+ Data Mode         : Absolute
+ Zero Suppression  : None
+ End Of Block      : *
+
+Apertures used:
+
+ Code     Shape     Size                  used
+
+ D10      draw      0.0030inch            1802
+ D11      draw      0.0634inch              43
+ D12      draw      0.0674inch              12
+ D13      round     0.2380inch               5
+ D14      round     0.0980inch               1
+ D15      round     0.1130inch               4
+ D16      rectangle 0.0592inch x 0.0710inch    14
+ D17      rectangle 0.0710inch x 0.0592inch    18
+ D18      rectangle 0.0867inch x 0.0671inch    10
+ D19      rectangle 0.0671inch x 0.0867inch    12
+ D20      draw      0.0980inch               2
+ D21      rectangle 0.0680inch x 0.0552inch     1
+ D22      rectangle 0.0867inch x 0.0552inch     1
+ D23      rectangle 0.0789inch x 0.0730inch     1
+ D24      rectangle 0.0789inch x 0.0926inch     1
+ D25      rectangle 0.0946inch x 0.1104inch     2
+ D26      rectangle 0.1241inch x 0.1143inch     2
+ D27      rectangle 0.0631inch x 0.0474inch     3
+ D28      octagon   0.0580inch               4
+ D29      round     0.0580inch               4
+ D30      rectangle 0.0880inch x 0.0340inch     8
+ D31      round     0.0640inch               1
+ D32      octagon   0.0640inch               9
+ D33      rectangle 0.0789inch x 0.1025inch     2
+ D34      round     0.0437inch              37
+ D35      round     0.0516inch              13
+
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.plc b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.plc
new file mode 100755
index 0000000..306ae4d
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.plc
@@ -0,0 +1,11353 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+%ADD10C,0.00000*%
+%ADD11C,0.00600*%
+%ADD12C,0.00800*%
+%ADD13C,0.00500*%
+%ADD14C,0.00400*%
+%ADD15C,0.00300*%
+%ADD16C,0.02000*%
+%ADD17R,0.07500X0.05000*%
+%ADD18R,0.07000X0.03000*%
+%ADD19R,0.03000X0.05000*%
+%ADD20C,0.00700*%
+%ADD21R,0.02000X0.01000*%
+%ADD22R,0.01500X0.00500*%
+%ADD23R,0.01000X0.01000*%
+D10*
+X0001800Y0012047D02*
+X0001800Y0279507D01*
+X0378001Y0279507D01*
+X0378001Y0012047D01*
+X0001800Y0012047D01*
+D11*
+X0018300Y0029547D02*
+X0018304Y0029878D01*
+X0018316Y0030209D01*
+X0018337Y0030540D01*
+X0018365Y0030870D01*
+X0018402Y0031200D01*
+X0018446Y0031528D01*
+X0018499Y0031855D01*
+X0018559Y0032181D01*
+X0018628Y0032505D01*
+X0018705Y0032827D01*
+X0018789Y0033148D01*
+X0018881Y0033466D01*
+X0018981Y0033782D01*
+X0019089Y0034095D01*
+X0019205Y0034406D01*
+X0019328Y0034713D01*
+X0019458Y0035018D01*
+X0019596Y0035319D01*
+X0019741Y0035617D01*
+X0019894Y0035911D01*
+X0020054Y0036201D01*
+X0020221Y0036487D01*
+X0020394Y0036769D01*
+X0020575Y0037047D01*
+X0020763Y0037320D01*
+X0020957Y0037589D01*
+X0021157Y0037853D01*
+X0021364Y0038111D01*
+X0021578Y0038365D01*
+X0021797Y0038613D01*
+X0022023Y0038856D01*
+X0022254Y0039093D01*
+X0022491Y0039324D01*
+X0022734Y0039550D01*
+X0022982Y0039769D01*
+X0023236Y0039983D01*
+X0023494Y0040190D01*
+X0023758Y0040390D01*
+X0024027Y0040584D01*
+X0024300Y0040772D01*
+X0024578Y0040953D01*
+X0024860Y0041126D01*
+X0025146Y0041293D01*
+X0025436Y0041453D01*
+X0025730Y0041606D01*
+X0026028Y0041751D01*
+X0026329Y0041889D01*
+X0026634Y0042019D01*
+X0026941Y0042142D01*
+X0027252Y0042258D01*
+X0027565Y0042366D01*
+X0027881Y0042466D01*
+X0028199Y0042558D01*
+X0028520Y0042642D01*
+X0028842Y0042719D01*
+X0029166Y0042788D01*
+X0029492Y0042848D01*
+X0029819Y0042901D01*
+X0030147Y0042945D01*
+X0030477Y0042982D01*
+X0030807Y0043010D01*
+X0031138Y0043031D01*
+X0031469Y0043043D01*
+X0031800Y0043047D01*
+X0032131Y0043043D01*
+X0032462Y0043031D01*
+X0032793Y0043010D01*
+X0033123Y0042982D01*
+X0033453Y0042945D01*
+X0033781Y0042901D01*
+X0034108Y0042848D01*
+X0034434Y0042788D01*
+X0034758Y0042719D01*
+X0035080Y0042642D01*
+X0035401Y0042558D01*
+X0035719Y0042466D01*
+X0036035Y0042366D01*
+X0036348Y0042258D01*
+X0036659Y0042142D01*
+X0036966Y0042019D01*
+X0037271Y0041889D01*
+X0037572Y0041751D01*
+X0037870Y0041606D01*
+X0038164Y0041453D01*
+X0038454Y0041293D01*
+X0038740Y0041126D01*
+X0039022Y0040953D01*
+X0039300Y0040772D01*
+X0039573Y0040584D01*
+X0039842Y0040390D01*
+X0040106Y0040190D01*
+X0040364Y0039983D01*
+X0040618Y0039769D01*
+X0040866Y0039550D01*
+X0041109Y0039324D01*
+X0041346Y0039093D01*
+X0041577Y0038856D01*
+X0041803Y0038613D01*
+X0042022Y0038365D01*
+X0042236Y0038111D01*
+X0042443Y0037853D01*
+X0042643Y0037589D01*
+X0042837Y0037320D01*
+X0043025Y0037047D01*
+X0043206Y0036769D01*
+X0043379Y0036487D01*
+X0043546Y0036201D01*
+X0043706Y0035911D01*
+X0043859Y0035617D01*
+X0044004Y0035319D01*
+X0044142Y0035018D01*
+X0044272Y0034713D01*
+X0044395Y0034406D01*
+X0044511Y0034095D01*
+X0044619Y0033782D01*
+X0044719Y0033466D01*
+X0044811Y0033148D01*
+X0044895Y0032827D01*
+X0044972Y0032505D01*
+X0045041Y0032181D01*
+X0045101Y0031855D01*
+X0045154Y0031528D01*
+X0045198Y0031200D01*
+X0045235Y0030870D01*
+X0045263Y0030540D01*
+X0045284Y0030209D01*
+X0045296Y0029878D01*
+X0045300Y0029547D01*
+X0045296Y0029216D01*
+X0045284Y0028885D01*
+X0045263Y0028554D01*
+X0045235Y0028224D01*
+X0045198Y0027894D01*
+X0045154Y0027566D01*
+X0045101Y0027239D01*
+X0045041Y0026913D01*
+X0044972Y0026589D01*
+X0044895Y0026267D01*
+X0044811Y0025946D01*
+X0044719Y0025628D01*
+X0044619Y0025312D01*
+X0044511Y0024999D01*
+X0044395Y0024688D01*
+X0044272Y0024381D01*
+X0044142Y0024076D01*
+X0044004Y0023775D01*
+X0043859Y0023477D01*
+X0043706Y0023183D01*
+X0043546Y0022893D01*
+X0043379Y0022607D01*
+X0043206Y0022325D01*
+X0043025Y0022047D01*
+X0042837Y0021774D01*
+X0042643Y0021505D01*
+X0042443Y0021241D01*
+X0042236Y0020983D01*
+X0042022Y0020729D01*
+X0041803Y0020481D01*
+X0041577Y0020238D01*
+X0041346Y0020001D01*
+X0041109Y0019770D01*
+X0040866Y0019544D01*
+X0040618Y0019325D01*
+X0040364Y0019111D01*
+X0040106Y0018904D01*
+X0039842Y0018704D01*
+X0039573Y0018510D01*
+X0039300Y0018322D01*
+X0039022Y0018141D01*
+X0038740Y0017968D01*
+X0038454Y0017801D01*
+X0038164Y0017641D01*
+X0037870Y0017488D01*
+X0037572Y0017343D01*
+X0037271Y0017205D01*
+X0036966Y0017075D01*
+X0036659Y0016952D01*
+X0036348Y0016836D01*
+X0036035Y0016728D01*
+X0035719Y0016628D01*
+X0035401Y0016536D01*
+X0035080Y0016452D01*
+X0034758Y0016375D01*
+X0034434Y0016306D01*
+X0034108Y0016246D01*
+X0033781Y0016193D01*
+X0033453Y0016149D01*
+X0033123Y0016112D01*
+X0032793Y0016084D01*
+X0032462Y0016063D01*
+X0032131Y0016051D01*
+X0031800Y0016047D01*
+X0031469Y0016051D01*
+X0031138Y0016063D01*
+X0030807Y0016084D01*
+X0030477Y0016112D01*
+X0030147Y0016149D01*
+X0029819Y0016193D01*
+X0029492Y0016246D01*
+X0029166Y0016306D01*
+X0028842Y0016375D01*
+X0028520Y0016452D01*
+X0028199Y0016536D01*
+X0027881Y0016628D01*
+X0027565Y0016728D01*
+X0027252Y0016836D01*
+X0026941Y0016952D01*
+X0026634Y0017075D01*
+X0026329Y0017205D01*
+X0026028Y0017343D01*
+X0025730Y0017488D01*
+X0025436Y0017641D01*
+X0025146Y0017801D01*
+X0024860Y0017968D01*
+X0024578Y0018141D01*
+X0024300Y0018322D01*
+X0024027Y0018510D01*
+X0023758Y0018704D01*
+X0023494Y0018904D01*
+X0023236Y0019111D01*
+X0022982Y0019325D01*
+X0022734Y0019544D01*
+X0022491Y0019770D01*
+X0022254Y0020001D01*
+X0022023Y0020238D01*
+X0021797Y0020481D01*
+X0021578Y0020729D01*
+X0021364Y0020983D01*
+X0021157Y0021241D01*
+X0020957Y0021505D01*
+X0020763Y0021774D01*
+X0020575Y0022047D01*
+X0020394Y0022325D01*
+X0020221Y0022607D01*
+X0020054Y0022893D01*
+X0019894Y0023183D01*
+X0019741Y0023477D01*
+X0019596Y0023775D01*
+X0019458Y0024076D01*
+X0019328Y0024381D01*
+X0019205Y0024688D01*
+X0019089Y0024999D01*
+X0018981Y0025312D01*
+X0018881Y0025628D01*
+X0018789Y0025946D01*
+X0018705Y0026267D01*
+X0018628Y0026589D01*
+X0018559Y0026913D01*
+X0018499Y0027239D01*
+X0018446Y0027566D01*
+X0018402Y0027894D01*
+X0018365Y0028224D01*
+X0018337Y0028554D01*
+X0018316Y0028885D01*
+X0018304Y0029216D01*
+X0018300Y0029547D01*
+X0012961Y0047401D02*
+X0095639Y0047401D01*
+X0095639Y0218661D01*
+X0012961Y0218661D01*
+X0012961Y0047401D01*
+X0023787Y0065418D02*
+X0026632Y0065418D01*
+X0026632Y0065417D02*
+X0026715Y0065419D01*
+X0026798Y0065425D01*
+X0026881Y0065435D01*
+X0026964Y0065448D01*
+X0027045Y0065466D01*
+X0027126Y0065487D01*
+X0027205Y0065512D01*
+X0027283Y0065541D01*
+X0027360Y0065573D01*
+X0027435Y0065609D01*
+X0027509Y0065648D01*
+X0027580Y0065691D01*
+X0027650Y0065737D01*
+X0027717Y0065787D01*
+X0027782Y0065839D01*
+X0027844Y0065894D01*
+X0027904Y0065953D01*
+X0027961Y0066014D01*
+X0028015Y0066077D01*
+X0028066Y0066143D01*
+X0028113Y0066212D01*
+X0028158Y0066282D01*
+X0028199Y0066355D01*
+X0028236Y0066429D01*
+X0028271Y0066505D01*
+X0028301Y0066583D01*
+X0028328Y0066661D01*
+X0028351Y0066742D01*
+X0028371Y0066823D01*
+X0028386Y0066905D01*
+X0028398Y0066987D01*
+X0028406Y0067070D01*
+X0028410Y0067153D01*
+X0028410Y0067237D01*
+X0028406Y0067320D01*
+X0028398Y0067403D01*
+X0028386Y0067485D01*
+X0028371Y0067567D01*
+X0028351Y0067648D01*
+X0028328Y0067729D01*
+X0028301Y0067807D01*
+X0028271Y0067885D01*
+X0028236Y0067961D01*
+X0028199Y0068035D01*
+X0028158Y0068108D01*
+X0028113Y0068178D01*
+X0028066Y0068247D01*
+X0028015Y0068313D01*
+X0027961Y0068376D01*
+X0027904Y0068437D01*
+X0027844Y0068496D01*
+X0027782Y0068551D01*
+X0027717Y0068603D01*
+X0027650Y0068653D01*
+X0027580Y0068699D01*
+X0027509Y0068742D01*
+X0027435Y0068781D01*
+X0027360Y0068817D01*
+X0027283Y0068849D01*
+X0027205Y0068878D01*
+X0027126Y0068903D01*
+X0027045Y0068924D01*
+X0026964Y0068942D01*
+X0026881Y0068955D01*
+X0026798Y0068965D01*
+X0026715Y0068971D01*
+X0026632Y0068973D01*
+X0023787Y0068973D01*
+X0023704Y0068971D01*
+X0023621Y0068965D01*
+X0023538Y0068955D01*
+X0023455Y0068942D01*
+X0023374Y0068924D01*
+X0023293Y0068903D01*
+X0023214Y0068878D01*
+X0023136Y0068849D01*
+X0023059Y0068817D01*
+X0022984Y0068781D01*
+X0022910Y0068742D01*
+X0022839Y0068699D01*
+X0022769Y0068653D01*
+X0022702Y0068603D01*
+X0022637Y0068551D01*
+X0022575Y0068496D01*
+X0022515Y0068437D01*
+X0022458Y0068376D01*
+X0022404Y0068313D01*
+X0022353Y0068247D01*
+X0022306Y0068178D01*
+X0022261Y0068108D01*
+X0022220Y0068035D01*
+X0022183Y0067961D01*
+X0022148Y0067885D01*
+X0022118Y0067807D01*
+X0022091Y0067729D01*
+X0022068Y0067648D01*
+X0022048Y0067567D01*
+X0022033Y0067485D01*
+X0022021Y0067403D01*
+X0022013Y0067320D01*
+X0022009Y0067237D01*
+X0022009Y0067153D01*
+X0022013Y0067070D01*
+X0022021Y0066987D01*
+X0022033Y0066905D01*
+X0022048Y0066823D01*
+X0022068Y0066742D01*
+X0022091Y0066661D01*
+X0022118Y0066583D01*
+X0022148Y0066505D01*
+X0022183Y0066429D01*
+X0022220Y0066355D01*
+X0022261Y0066282D01*
+X0022306Y0066212D01*
+X0022353Y0066143D01*
+X0022404Y0066077D01*
+X0022458Y0066014D01*
+X0022515Y0065953D01*
+X0022575Y0065894D01*
+X0022637Y0065839D01*
+X0022702Y0065787D01*
+X0022769Y0065737D01*
+X0022839Y0065691D01*
+X0022910Y0065648D01*
+X0022984Y0065609D01*
+X0023059Y0065573D01*
+X0023136Y0065541D01*
+X0023214Y0065512D01*
+X0023293Y0065487D01*
+X0023374Y0065466D01*
+X0023455Y0065448D01*
+X0023538Y0065435D01*
+X0023621Y0065425D01*
+X0023704Y0065419D01*
+X0023787Y0065417D01*
+X0022009Y0071777D02*
+X0026632Y0071777D01*
+X0026632Y0071776D02*
+X0026715Y0071778D01*
+X0026798Y0071784D01*
+X0026881Y0071794D01*
+X0026964Y0071807D01*
+X0027045Y0071825D01*
+X0027126Y0071846D01*
+X0027205Y0071871D01*
+X0027283Y0071900D01*
+X0027360Y0071932D01*
+X0027435Y0071968D01*
+X0027509Y0072007D01*
+X0027580Y0072050D01*
+X0027650Y0072096D01*
+X0027717Y0072146D01*
+X0027782Y0072198D01*
+X0027844Y0072253D01*
+X0027904Y0072312D01*
+X0027961Y0072373D01*
+X0028015Y0072436D01*
+X0028066Y0072502D01*
+X0028113Y0072571D01*
+X0028158Y0072641D01*
+X0028199Y0072714D01*
+X0028236Y0072788D01*
+X0028271Y0072864D01*
+X0028301Y0072942D01*
+X0028328Y0073020D01*
+X0028351Y0073101D01*
+X0028371Y0073182D01*
+X0028386Y0073264D01*
+X0028398Y0073346D01*
+X0028406Y0073429D01*
+X0028410Y0073512D01*
+X0028410Y0073596D01*
+X0028406Y0073679D01*
+X0028398Y0073762D01*
+X0028386Y0073844D01*
+X0028371Y0073926D01*
+X0028351Y0074007D01*
+X0028328Y0074088D01*
+X0028301Y0074166D01*
+X0028271Y0074244D01*
+X0028236Y0074320D01*
+X0028199Y0074394D01*
+X0028158Y0074467D01*
+X0028113Y0074537D01*
+X0028066Y0074606D01*
+X0028015Y0074672D01*
+X0027961Y0074735D01*
+X0027904Y0074796D01*
+X0027844Y0074855D01*
+X0027782Y0074910D01*
+X0027717Y0074962D01*
+X0027650Y0075012D01*
+X0027580Y0075058D01*
+X0027509Y0075101D01*
+X0027435Y0075140D01*
+X0027360Y0075176D01*
+X0027283Y0075208D01*
+X0027205Y0075237D01*
+X0027126Y0075262D01*
+X0027045Y0075283D01*
+X0026964Y0075301D01*
+X0026881Y0075314D01*
+X0026798Y0075324D01*
+X0026715Y0075330D01*
+X0026632Y0075332D01*
+X0022009Y0075332D01*
+X0022009Y0077726D02*
+X0022009Y0081281D01*
+X0022009Y0079503D02*
+X0028409Y0079503D01*
+X0025921Y0086806D02*
+X0025921Y0091073D01*
+X0044974Y0104788D02*
+X0051374Y0106921D01*
+X0044974Y0109054D01*
+X0046752Y0111297D02*
+X0049596Y0111297D01*
+X0049679Y0111299D01*
+X0049762Y0111305D01*
+X0049845Y0111315D01*
+X0049928Y0111328D01*
+X0050009Y0111346D01*
+X0050090Y0111367D01*
+X0050169Y0111392D01*
+X0050247Y0111421D01*
+X0050324Y0111453D01*
+X0050399Y0111489D01*
+X0050473Y0111528D01*
+X0050544Y0111571D01*
+X0050614Y0111617D01*
+X0050681Y0111667D01*
+X0050746Y0111719D01*
+X0050808Y0111774D01*
+X0050868Y0111833D01*
+X0050925Y0111894D01*
+X0050979Y0111957D01*
+X0051030Y0112023D01*
+X0051077Y0112092D01*
+X0051122Y0112162D01*
+X0051163Y0112235D01*
+X0051200Y0112309D01*
+X0051235Y0112385D01*
+X0051265Y0112463D01*
+X0051292Y0112541D01*
+X0051315Y0112622D01*
+X0051335Y0112703D01*
+X0051350Y0112785D01*
+X0051362Y0112867D01*
+X0051370Y0112950D01*
+X0051374Y0113033D01*
+X0051374Y0113117D01*
+X0051370Y0113200D01*
+X0051362Y0113283D01*
+X0051350Y0113365D01*
+X0051335Y0113447D01*
+X0051315Y0113528D01*
+X0051292Y0113609D01*
+X0051265Y0113687D01*
+X0051235Y0113765D01*
+X0051200Y0113841D01*
+X0051163Y0113915D01*
+X0051122Y0113988D01*
+X0051077Y0114058D01*
+X0051030Y0114127D01*
+X0050979Y0114193D01*
+X0050925Y0114256D01*
+X0050868Y0114317D01*
+X0050808Y0114376D01*
+X0050746Y0114431D01*
+X0050681Y0114483D01*
+X0050614Y0114533D01*
+X0050544Y0114579D01*
+X0050473Y0114622D01*
+X0050399Y0114661D01*
+X0050324Y0114697D01*
+X0050247Y0114729D01*
+X0050169Y0114758D01*
+X0050090Y0114783D01*
+X0050009Y0114804D01*
+X0049928Y0114822D01*
+X0049845Y0114835D01*
+X0049762Y0114845D01*
+X0049679Y0114851D01*
+X0049596Y0114853D01*
+X0046752Y0114853D01*
+X0046669Y0114851D01*
+X0046586Y0114845D01*
+X0046503Y0114835D01*
+X0046420Y0114822D01*
+X0046339Y0114804D01*
+X0046258Y0114783D01*
+X0046179Y0114758D01*
+X0046101Y0114729D01*
+X0046024Y0114697D01*
+X0045949Y0114661D01*
+X0045875Y0114622D01*
+X0045804Y0114579D01*
+X0045734Y0114533D01*
+X0045667Y0114483D01*
+X0045602Y0114431D01*
+X0045540Y0114376D01*
+X0045480Y0114317D01*
+X0045423Y0114256D01*
+X0045369Y0114193D01*
+X0045318Y0114127D01*
+X0045271Y0114058D01*
+X0045226Y0113988D01*
+X0045185Y0113915D01*
+X0045148Y0113841D01*
+X0045113Y0113765D01*
+X0045083Y0113687D01*
+X0045056Y0113609D01*
+X0045033Y0113528D01*
+X0045013Y0113447D01*
+X0044998Y0113365D01*
+X0044986Y0113283D01*
+X0044978Y0113200D01*
+X0044974Y0113117D01*
+X0044974Y0113033D01*
+X0044978Y0112950D01*
+X0044986Y0112867D01*
+X0044998Y0112785D01*
+X0045013Y0112703D01*
+X0045033Y0112622D01*
+X0045056Y0112541D01*
+X0045083Y0112463D01*
+X0045113Y0112385D01*
+X0045148Y0112309D01*
+X0045185Y0112235D01*
+X0045226Y0112162D01*
+X0045271Y0112092D01*
+X0045318Y0112023D01*
+X0045369Y0111957D01*
+X0045423Y0111894D01*
+X0045480Y0111833D01*
+X0045540Y0111774D01*
+X0045602Y0111719D01*
+X0045667Y0111667D01*
+X0045734Y0111617D01*
+X0045804Y0111571D01*
+X0045875Y0111528D01*
+X0045949Y0111489D01*
+X0046024Y0111453D01*
+X0046101Y0111421D01*
+X0046179Y0111392D01*
+X0046258Y0111367D01*
+X0046339Y0111346D01*
+X0046420Y0111328D01*
+X0046503Y0111315D01*
+X0046586Y0111305D01*
+X0046669Y0111299D01*
+X0046752Y0111297D01*
+X0044974Y0117668D02*
+X0051374Y0117668D01*
+X0051374Y0120513D01*
+X0051374Y0124152D02*
+X0044974Y0124152D01*
+X0044974Y0122374D02*
+X0044974Y0125930D01*
+X0044974Y0129896D02*
+X0051374Y0132029D01*
+X0049774Y0131496D02*
+X0049774Y0128296D01*
+X0051374Y0127763D02*
+X0044974Y0129896D01*
+X0046396Y0134477D02*
+X0049952Y0134477D01*
+X0049952Y0134478D02*
+X0050026Y0134480D01*
+X0050101Y0134486D01*
+X0050174Y0134496D01*
+X0050248Y0134509D01*
+X0050320Y0134526D01*
+X0050391Y0134548D01*
+X0050462Y0134572D01*
+X0050530Y0134601D01*
+X0050598Y0134633D01*
+X0050663Y0134669D01*
+X0050726Y0134707D01*
+X0050788Y0134750D01*
+X0050847Y0134795D01*
+X0050904Y0134843D01*
+X0050958Y0134894D01*
+X0051009Y0134948D01*
+X0051057Y0135005D01*
+X0051102Y0135064D01*
+X0051145Y0135126D01*
+X0051183Y0135189D01*
+X0051219Y0135254D01*
+X0051251Y0135322D01*
+X0051280Y0135390D01*
+X0051304Y0135461D01*
+X0051326Y0135532D01*
+X0051343Y0135604D01*
+X0051356Y0135678D01*
+X0051366Y0135751D01*
+X0051372Y0135826D01*
+X0051374Y0135900D01*
+X0051374Y0138033D01*
+X0047818Y0138033D01*
+X0047818Y0136966D01*
+X0046396Y0134478D02*
+X0046322Y0134480D01*
+X0046247Y0134486D01*
+X0046174Y0134496D01*
+X0046100Y0134509D01*
+X0046028Y0134526D01*
+X0045957Y0134548D01*
+X0045886Y0134572D01*
+X0045818Y0134601D01*
+X0045750Y0134633D01*
+X0045685Y0134669D01*
+X0045622Y0134707D01*
+X0045560Y0134750D01*
+X0045501Y0134795D01*
+X0045445Y0134843D01*
+X0045391Y0134894D01*
+X0045339Y0134948D01*
+X0045291Y0135005D01*
+X0045246Y0135064D01*
+X0045203Y0135126D01*
+X0045165Y0135189D01*
+X0045129Y0135254D01*
+X0045097Y0135322D01*
+X0045068Y0135390D01*
+X0045044Y0135461D01*
+X0045022Y0135532D01*
+X0045005Y0135604D01*
+X0044992Y0135678D01*
+X0044982Y0135751D01*
+X0044976Y0135826D01*
+X0044974Y0135900D01*
+X0044974Y0138033D01*
+X0044974Y0141053D02*
+X0044974Y0143898D01*
+X0044974Y0141053D02*
+X0051374Y0141053D01*
+X0051374Y0143898D01*
+X0047818Y0143187D02*
+X0047818Y0141053D01*
+X0055474Y0140445D02*
+X0055474Y0144001D01*
+X0055474Y0142223D02*
+X0061874Y0142223D01*
+X0061874Y0138612D02*
+X0055474Y0136479D01*
+X0061874Y0134346D01*
+X0060274Y0134879D02*
+X0060274Y0138079D01*
+X0061874Y0132429D02*
+X0061874Y0129585D01*
+X0055474Y0129585D01*
+X0055474Y0126564D02*
+X0060096Y0126564D01*
+X0060179Y0126562D01*
+X0060262Y0126556D01*
+X0060345Y0126546D01*
+X0060428Y0126533D01*
+X0060509Y0126515D01*
+X0060590Y0126494D01*
+X0060669Y0126469D01*
+X0060747Y0126440D01*
+X0060824Y0126408D01*
+X0060899Y0126372D01*
+X0060973Y0126333D01*
+X0061044Y0126290D01*
+X0061114Y0126244D01*
+X0061181Y0126194D01*
+X0061246Y0126142D01*
+X0061308Y0126087D01*
+X0061368Y0126028D01*
+X0061425Y0125967D01*
+X0061479Y0125904D01*
+X0061530Y0125838D01*
+X0061577Y0125769D01*
+X0061622Y0125699D01*
+X0061663Y0125626D01*
+X0061700Y0125552D01*
+X0061735Y0125476D01*
+X0061765Y0125398D01*
+X0061792Y0125320D01*
+X0061815Y0125239D01*
+X0061835Y0125158D01*
+X0061850Y0125076D01*
+X0061862Y0124994D01*
+X0061870Y0124911D01*
+X0061874Y0124828D01*
+X0061874Y0124744D01*
+X0061870Y0124661D01*
+X0061862Y0124578D01*
+X0061850Y0124496D01*
+X0061835Y0124414D01*
+X0061815Y0124333D01*
+X0061792Y0124252D01*
+X0061765Y0124174D01*
+X0061735Y0124096D01*
+X0061700Y0124020D01*
+X0061663Y0123946D01*
+X0061622Y0123873D01*
+X0061577Y0123803D01*
+X0061530Y0123734D01*
+X0061479Y0123668D01*
+X0061425Y0123605D01*
+X0061368Y0123544D01*
+X0061308Y0123485D01*
+X0061246Y0123430D01*
+X0061181Y0123378D01*
+X0061114Y0123328D01*
+X0061044Y0123282D01*
+X0060973Y0123239D01*
+X0060899Y0123200D01*
+X0060824Y0123164D01*
+X0060747Y0123132D01*
+X0060669Y0123103D01*
+X0060590Y0123078D01*
+X0060509Y0123057D01*
+X0060428Y0123039D01*
+X0060345Y0123026D01*
+X0060262Y0123016D01*
+X0060179Y0123010D01*
+X0060096Y0123008D01*
+X0060096Y0123009D02*
+X0055474Y0123009D01*
+X0055474Y0120000D02*
+X0055474Y0117866D01*
+X0055476Y0117792D01*
+X0055482Y0117717D01*
+X0055492Y0117644D01*
+X0055505Y0117570D01*
+X0055522Y0117498D01*
+X0055544Y0117427D01*
+X0055568Y0117356D01*
+X0055597Y0117288D01*
+X0055629Y0117220D01*
+X0055665Y0117155D01*
+X0055703Y0117092D01*
+X0055746Y0117030D01*
+X0055791Y0116971D01*
+X0055839Y0116914D01*
+X0055891Y0116860D01*
+X0055945Y0116809D01*
+X0056001Y0116761D01*
+X0056060Y0116716D01*
+X0056122Y0116673D01*
+X0056185Y0116635D01*
+X0056250Y0116599D01*
+X0056318Y0116567D01*
+X0056386Y0116538D01*
+X0056457Y0116514D01*
+X0056528Y0116492D01*
+X0056600Y0116475D01*
+X0056674Y0116462D01*
+X0056747Y0116452D01*
+X0056822Y0116446D01*
+X0056896Y0116444D01*
+X0060452Y0116444D01*
+X0060526Y0116446D01*
+X0060601Y0116452D01*
+X0060674Y0116462D01*
+X0060748Y0116475D01*
+X0060820Y0116492D01*
+X0060891Y0116514D01*
+X0060962Y0116538D01*
+X0061030Y0116567D01*
+X0061098Y0116599D01*
+X0061163Y0116635D01*
+X0061226Y0116673D01*
+X0061288Y0116716D01*
+X0061347Y0116761D01*
+X0061404Y0116809D01*
+X0061458Y0116860D01*
+X0061509Y0116914D01*
+X0061557Y0116971D01*
+X0061602Y0117030D01*
+X0061645Y0117092D01*
+X0061683Y0117155D01*
+X0061719Y0117220D01*
+X0061751Y0117288D01*
+X0061780Y0117356D01*
+X0061804Y0117427D01*
+X0061826Y0117498D01*
+X0061843Y0117570D01*
+X0061856Y0117644D01*
+X0061866Y0117717D01*
+X0061872Y0117792D01*
+X0061874Y0117866D01*
+X0061874Y0120000D01*
+X0058318Y0120000D01*
+X0058318Y0118933D01*
+X0058318Y0113256D02*
+X0058318Y0111122D01*
+X0055474Y0111122D02*
+X0055474Y0113967D01*
+X0055474Y0111122D02*
+X0061874Y0111122D01*
+X0061874Y0113967D01*
+X0061874Y0108343D02*
+X0059030Y0106921D01*
+X0059030Y0106565D02*
+X0059030Y0104788D01*
+X0059030Y0106565D02*
+X0059028Y0106648D01*
+X0059022Y0106731D01*
+X0059012Y0106814D01*
+X0058999Y0106897D01*
+X0058981Y0106978D01*
+X0058960Y0107059D01*
+X0058935Y0107138D01*
+X0058906Y0107216D01*
+X0058874Y0107293D01*
+X0058838Y0107368D01*
+X0058799Y0107442D01*
+X0058756Y0107513D01*
+X0058710Y0107583D01*
+X0058660Y0107650D01*
+X0058608Y0107715D01*
+X0058553Y0107777D01*
+X0058494Y0107837D01*
+X0058433Y0107894D01*
+X0058370Y0107948D01*
+X0058304Y0107999D01*
+X0058235Y0108046D01*
+X0058165Y0108091D01*
+X0058092Y0108132D01*
+X0058018Y0108169D01*
+X0057942Y0108204D01*
+X0057864Y0108234D01*
+X0057786Y0108261D01*
+X0057705Y0108284D01*
+X0057624Y0108304D01*
+X0057542Y0108319D01*
+X0057460Y0108331D01*
+X0057377Y0108339D01*
+X0057294Y0108343D01*
+X0057210Y0108343D01*
+X0057127Y0108339D01*
+X0057044Y0108331D01*
+X0056962Y0108319D01*
+X0056880Y0108304D01*
+X0056799Y0108284D01*
+X0056718Y0108261D01*
+X0056640Y0108234D01*
+X0056562Y0108204D01*
+X0056486Y0108169D01*
+X0056412Y0108132D01*
+X0056339Y0108091D01*
+X0056269Y0108046D01*
+X0056200Y0107999D01*
+X0056134Y0107948D01*
+X0056071Y0107894D01*
+X0056010Y0107837D01*
+X0055951Y0107777D01*
+X0055896Y0107715D01*
+X0055844Y0107650D01*
+X0055794Y0107583D01*
+X0055748Y0107513D01*
+X0055705Y0107442D01*
+X0055666Y0107368D01*
+X0055630Y0107293D01*
+X0055598Y0107216D01*
+X0055569Y0107138D01*
+X0055544Y0107059D01*
+X0055523Y0106978D01*
+X0055505Y0106897D01*
+X0055492Y0106814D01*
+X0055482Y0106731D01*
+X0055476Y0106648D01*
+X0055474Y0106565D01*
+X0055474Y0104788D01*
+X0061874Y0104788D01*
+X0080874Y0090908D02*
+X0085141Y0090908D01*
+X0083007Y0088775D02*
+X0083007Y0093041D01*
+X0079096Y0083250D02*
+X0079096Y0079694D01*
+X0079096Y0081472D02*
+X0085496Y0081472D01*
+X0083718Y0077301D02*
+X0079096Y0077301D01*
+X0079096Y0073745D02*
+X0083718Y0073745D01*
+X0083801Y0073747D01*
+X0083884Y0073753D01*
+X0083967Y0073763D01*
+X0084050Y0073776D01*
+X0084131Y0073794D01*
+X0084212Y0073815D01*
+X0084291Y0073840D01*
+X0084369Y0073869D01*
+X0084446Y0073901D01*
+X0084521Y0073937D01*
+X0084595Y0073976D01*
+X0084666Y0074019D01*
+X0084736Y0074065D01*
+X0084803Y0074115D01*
+X0084868Y0074167D01*
+X0084930Y0074222D01*
+X0084990Y0074281D01*
+X0085047Y0074342D01*
+X0085101Y0074405D01*
+X0085152Y0074471D01*
+X0085199Y0074540D01*
+X0085244Y0074610D01*
+X0085285Y0074683D01*
+X0085322Y0074757D01*
+X0085357Y0074833D01*
+X0085387Y0074911D01*
+X0085414Y0074989D01*
+X0085437Y0075070D01*
+X0085457Y0075151D01*
+X0085472Y0075233D01*
+X0085484Y0075315D01*
+X0085492Y0075398D01*
+X0085496Y0075481D01*
+X0085496Y0075565D01*
+X0085492Y0075648D01*
+X0085484Y0075731D01*
+X0085472Y0075813D01*
+X0085457Y0075895D01*
+X0085437Y0075976D01*
+X0085414Y0076057D01*
+X0085387Y0076135D01*
+X0085357Y0076213D01*
+X0085322Y0076289D01*
+X0085285Y0076363D01*
+X0085244Y0076436D01*
+X0085199Y0076506D01*
+X0085152Y0076575D01*
+X0085101Y0076641D01*
+X0085047Y0076704D01*
+X0084990Y0076765D01*
+X0084930Y0076824D01*
+X0084868Y0076879D01*
+X0084803Y0076931D01*
+X0084736Y0076981D01*
+X0084666Y0077027D01*
+X0084595Y0077070D01*
+X0084521Y0077109D01*
+X0084446Y0077145D01*
+X0084369Y0077177D01*
+X0084291Y0077206D01*
+X0084212Y0077231D01*
+X0084131Y0077252D01*
+X0084050Y0077270D01*
+X0083967Y0077283D01*
+X0083884Y0077293D01*
+X0083801Y0077299D01*
+X0083718Y0077301D01*
+X0083718Y0070942D02*
+X0080874Y0070942D01*
+X0080791Y0070940D01*
+X0080708Y0070934D01*
+X0080625Y0070924D01*
+X0080542Y0070911D01*
+X0080461Y0070893D01*
+X0080380Y0070872D01*
+X0080301Y0070847D01*
+X0080223Y0070818D01*
+X0080146Y0070786D01*
+X0080071Y0070750D01*
+X0079997Y0070711D01*
+X0079926Y0070668D01*
+X0079856Y0070622D01*
+X0079789Y0070572D01*
+X0079724Y0070520D01*
+X0079662Y0070465D01*
+X0079602Y0070406D01*
+X0079545Y0070345D01*
+X0079491Y0070282D01*
+X0079440Y0070216D01*
+X0079393Y0070147D01*
+X0079348Y0070077D01*
+X0079307Y0070004D01*
+X0079270Y0069930D01*
+X0079235Y0069854D01*
+X0079205Y0069776D01*
+X0079178Y0069698D01*
+X0079155Y0069617D01*
+X0079135Y0069536D01*
+X0079120Y0069454D01*
+X0079108Y0069372D01*
+X0079100Y0069289D01*
+X0079096Y0069206D01*
+X0079096Y0069122D01*
+X0079100Y0069039D01*
+X0079108Y0068956D01*
+X0079120Y0068874D01*
+X0079135Y0068792D01*
+X0079155Y0068711D01*
+X0079178Y0068630D01*
+X0079205Y0068552D01*
+X0079235Y0068474D01*
+X0079270Y0068398D01*
+X0079307Y0068324D01*
+X0079348Y0068251D01*
+X0079393Y0068181D01*
+X0079440Y0068112D01*
+X0079491Y0068046D01*
+X0079545Y0067983D01*
+X0079602Y0067922D01*
+X0079662Y0067863D01*
+X0079724Y0067808D01*
+X0079789Y0067756D01*
+X0079856Y0067706D01*
+X0079926Y0067660D01*
+X0079997Y0067617D01*
+X0080071Y0067578D01*
+X0080146Y0067542D01*
+X0080223Y0067510D01*
+X0080301Y0067481D01*
+X0080380Y0067456D01*
+X0080461Y0067435D01*
+X0080542Y0067417D01*
+X0080625Y0067404D01*
+X0080708Y0067394D01*
+X0080791Y0067388D01*
+X0080874Y0067386D01*
+X0083718Y0067386D01*
+X0083801Y0067388D01*
+X0083884Y0067394D01*
+X0083967Y0067404D01*
+X0084050Y0067417D01*
+X0084131Y0067435D01*
+X0084212Y0067456D01*
+X0084291Y0067481D01*
+X0084369Y0067510D01*
+X0084446Y0067542D01*
+X0084521Y0067578D01*
+X0084595Y0067617D01*
+X0084666Y0067660D01*
+X0084736Y0067706D01*
+X0084803Y0067756D01*
+X0084868Y0067808D01*
+X0084930Y0067863D01*
+X0084990Y0067922D01*
+X0085047Y0067983D01*
+X0085101Y0068046D01*
+X0085152Y0068112D01*
+X0085199Y0068181D01*
+X0085244Y0068251D01*
+X0085285Y0068324D01*
+X0085322Y0068398D01*
+X0085357Y0068474D01*
+X0085387Y0068552D01*
+X0085414Y0068630D01*
+X0085437Y0068711D01*
+X0085457Y0068792D01*
+X0085472Y0068874D01*
+X0085484Y0068956D01*
+X0085492Y0069039D01*
+X0085496Y0069122D01*
+X0085496Y0069206D01*
+X0085492Y0069289D01*
+X0085484Y0069372D01*
+X0085472Y0069454D01*
+X0085457Y0069536D01*
+X0085437Y0069617D01*
+X0085414Y0069698D01*
+X0085387Y0069776D01*
+X0085357Y0069854D01*
+X0085322Y0069930D01*
+X0085285Y0070004D01*
+X0085244Y0070077D01*
+X0085199Y0070147D01*
+X0085152Y0070216D01*
+X0085101Y0070282D01*
+X0085047Y0070345D01*
+X0084990Y0070406D01*
+X0084930Y0070465D01*
+X0084868Y0070520D01*
+X0084803Y0070572D01*
+X0084736Y0070622D01*
+X0084666Y0070668D01*
+X0084595Y0070711D01*
+X0084521Y0070750D01*
+X0084446Y0070786D01*
+X0084369Y0070818D01*
+X0084291Y0070847D01*
+X0084212Y0070872D01*
+X0084131Y0070893D01*
+X0084050Y0070911D01*
+X0083967Y0070924D01*
+X0083884Y0070934D01*
+X0083801Y0070940D01*
+X0083718Y0070942D01*
+X0117100Y0038747D02*
+X0118522Y0032347D01*
+X0119944Y0036613D01*
+X0121367Y0032347D01*
+X0122789Y0038747D01*
+X0125114Y0037324D02*
+X0125116Y0037398D01*
+X0125122Y0037473D01*
+X0125132Y0037546D01*
+X0125145Y0037620D01*
+X0125162Y0037692D01*
+X0125184Y0037763D01*
+X0125208Y0037834D01*
+X0125237Y0037902D01*
+X0125269Y0037970D01*
+X0125305Y0038035D01*
+X0125343Y0038098D01*
+X0125386Y0038160D01*
+X0125431Y0038219D01*
+X0125479Y0038276D01*
+X0125530Y0038330D01*
+X0125585Y0038381D01*
+X0125641Y0038429D01*
+X0125700Y0038474D01*
+X0125762Y0038517D01*
+X0125825Y0038555D01*
+X0125890Y0038591D01*
+X0125958Y0038623D01*
+X0126026Y0038652D01*
+X0126097Y0038676D01*
+X0126168Y0038698D01*
+X0126240Y0038715D01*
+X0126314Y0038728D01*
+X0126387Y0038738D01*
+X0126462Y0038744D01*
+X0126536Y0038746D01*
+X0125114Y0037324D02*
+X0125116Y0037249D01*
+X0125122Y0037174D01*
+X0125131Y0037100D01*
+X0125145Y0037026D01*
+X0125162Y0036953D01*
+X0125183Y0036881D01*
+X0125208Y0036811D01*
+X0125237Y0036741D01*
+X0125269Y0036674D01*
+X0125304Y0036608D01*
+X0125343Y0036543D01*
+X0125385Y0036481D01*
+X0125431Y0036422D01*
+X0125479Y0036364D01*
+X0125530Y0036310D01*
+X0125584Y0036258D01*
+X0125641Y0036209D01*
+X0125700Y0036163D01*
+X0125761Y0036120D01*
+X0125825Y0036080D01*
+X0127781Y0035013D01*
+X0127069Y0032347D02*
+X0126961Y0032349D01*
+X0126854Y0032355D01*
+X0126746Y0032364D01*
+X0126639Y0032378D01*
+X0126533Y0032395D01*
+X0126427Y0032416D01*
+X0126322Y0032441D01*
+X0126218Y0032470D01*
+X0126115Y0032502D01*
+X0126014Y0032538D01*
+X0125914Y0032578D01*
+X0125815Y0032621D01*
+X0125718Y0032668D01*
+X0125622Y0032718D01*
+X0125529Y0032772D01*
+X0125437Y0032829D01*
+X0125348Y0032889D01*
+X0125261Y0032952D01*
+X0125176Y0033019D01*
+X0125093Y0033088D01*
+X0125013Y0033161D01*
+X0124936Y0033236D01*
+X0127780Y0035013D02*
+X0127844Y0034973D01*
+X0127905Y0034930D01*
+X0127964Y0034884D01*
+X0128021Y0034835D01*
+X0128075Y0034783D01*
+X0128126Y0034729D01*
+X0128174Y0034671D01*
+X0128220Y0034612D01*
+X0128262Y0034550D01*
+X0128301Y0034485D01*
+X0128336Y0034419D01*
+X0128368Y0034352D01*
+X0128397Y0034282D01*
+X0128422Y0034212D01*
+X0128443Y0034140D01*
+X0128460Y0034067D01*
+X0128474Y0033993D01*
+X0128483Y0033919D01*
+X0128489Y0033844D01*
+X0128491Y0033769D01*
+X0128489Y0033695D01*
+X0128483Y0033620D01*
+X0128473Y0033547D01*
+X0128460Y0033473D01*
+X0128443Y0033401D01*
+X0128421Y0033330D01*
+X0128397Y0033259D01*
+X0128368Y0033191D01*
+X0128336Y0033123D01*
+X0128300Y0033058D01*
+X0128262Y0032995D01*
+X0128219Y0032933D01*
+X0128174Y0032874D01*
+X0128126Y0032817D01*
+X0128075Y0032763D01*
+X0128021Y0032712D01*
+X0127964Y0032664D01*
+X0127905Y0032619D01*
+X0127843Y0032576D01*
+X0127780Y0032538D01*
+X0127715Y0032502D01*
+X0127647Y0032470D01*
+X0127579Y0032441D01*
+X0127508Y0032417D01*
+X0127437Y0032395D01*
+X0127365Y0032378D01*
+X0127291Y0032365D01*
+X0127218Y0032355D01*
+X0127143Y0032349D01*
+X0127069Y0032347D01*
+X0128136Y0038214D02*
+X0128054Y0038273D01*
+X0127970Y0038329D01*
+X0127884Y0038381D01*
+X0127796Y0038431D01*
+X0127706Y0038477D01*
+X0127615Y0038519D01*
+X0127522Y0038558D01*
+X0127427Y0038594D01*
+X0127331Y0038626D01*
+X0127234Y0038654D01*
+X0127137Y0038679D01*
+X0127038Y0038699D01*
+X0126938Y0038716D01*
+X0126838Y0038730D01*
+X0126738Y0038739D01*
+X0126637Y0038745D01*
+X0126536Y0038747D01*
+X0130885Y0038747D02*
+X0130885Y0035902D01*
+X0133018Y0035902D01*
+X0133092Y0035900D01*
+X0133167Y0035894D01*
+X0133240Y0035884D01*
+X0133314Y0035871D01*
+X0133386Y0035854D01*
+X0133457Y0035832D01*
+X0133528Y0035808D01*
+X0133596Y0035779D01*
+X0133664Y0035747D01*
+X0133729Y0035711D01*
+X0133792Y0035673D01*
+X0133854Y0035630D01*
+X0133913Y0035585D01*
+X0133970Y0035537D01*
+X0134024Y0035486D01*
+X0134075Y0035432D01*
+X0134123Y0035375D01*
+X0134168Y0035316D01*
+X0134211Y0035254D01*
+X0134249Y0035191D01*
+X0134285Y0035126D01*
+X0134317Y0035058D01*
+X0134346Y0034990D01*
+X0134370Y0034919D01*
+X0134392Y0034848D01*
+X0134409Y0034776D01*
+X0134422Y0034702D01*
+X0134432Y0034629D01*
+X0134438Y0034554D01*
+X0134440Y0034480D01*
+X0134441Y0034480D02*
+X0134441Y0033769D01*
+X0134440Y0033769D02*
+X0134438Y0033695D01*
+X0134432Y0033620D01*
+X0134422Y0033547D01*
+X0134409Y0033473D01*
+X0134392Y0033401D01*
+X0134370Y0033330D01*
+X0134346Y0033259D01*
+X0134317Y0033191D01*
+X0134285Y0033123D01*
+X0134249Y0033058D01*
+X0134211Y0032995D01*
+X0134168Y0032933D01*
+X0134123Y0032874D01*
+X0134075Y0032817D01*
+X0134024Y0032763D01*
+X0133970Y0032712D01*
+X0133913Y0032664D01*
+X0133854Y0032619D01*
+X0133792Y0032576D01*
+X0133729Y0032538D01*
+X0133664Y0032502D01*
+X0133596Y0032470D01*
+X0133528Y0032441D01*
+X0133457Y0032417D01*
+X0133386Y0032395D01*
+X0133314Y0032378D01*
+X0133240Y0032365D01*
+X0133167Y0032355D01*
+X0133092Y0032349D01*
+X0133018Y0032347D01*
+X0130885Y0032347D01*
+X0137039Y0032347D02*
+X0139172Y0032347D01*
+X0139246Y0032349D01*
+X0139321Y0032355D01*
+X0139394Y0032365D01*
+X0139468Y0032378D01*
+X0139540Y0032395D01*
+X0139611Y0032417D01*
+X0139682Y0032441D01*
+X0139750Y0032470D01*
+X0139818Y0032502D01*
+X0139883Y0032538D01*
+X0139946Y0032576D01*
+X0140008Y0032619D01*
+X0140067Y0032664D01*
+X0140124Y0032712D01*
+X0140178Y0032763D01*
+X0140229Y0032817D01*
+X0140277Y0032874D01*
+X0140322Y0032933D01*
+X0140365Y0032995D01*
+X0140403Y0033058D01*
+X0140439Y0033123D01*
+X0140471Y0033191D01*
+X0140500Y0033259D01*
+X0140524Y0033330D01*
+X0140546Y0033401D01*
+X0140563Y0033473D01*
+X0140576Y0033547D01*
+X0140586Y0033620D01*
+X0140592Y0033695D01*
+X0140594Y0033769D01*
+X0140595Y0033769D02*
+X0140595Y0034480D01*
+X0146215Y0033236D02*
+X0146275Y0033363D01*
+X0146331Y0033492D01*
+X0146384Y0033622D01*
+X0146434Y0033754D01*
+X0146480Y0033887D01*
+X0146522Y0034021D01*
+X0146561Y0034156D01*
+X0146597Y0034293D01*
+X0146628Y0034430D01*
+X0146656Y0034568D01*
+X0146681Y0034706D01*
+X0146701Y0034845D01*
+X0146718Y0034985D01*
+X0146731Y0035125D01*
+X0146740Y0035266D01*
+X0146746Y0035406D01*
+X0146748Y0035547D01*
+X0152369Y0033236D02*
+X0152429Y0033363D01*
+X0152485Y0033492D01*
+X0152538Y0033622D01*
+X0152588Y0033754D01*
+X0152634Y0033887D01*
+X0152676Y0034021D01*
+X0152715Y0034156D01*
+X0152751Y0034293D01*
+X0152782Y0034430D01*
+X0152810Y0034568D01*
+X0152835Y0034706D01*
+X0152855Y0034845D01*
+X0152872Y0034985D01*
+X0152885Y0035125D01*
+X0152894Y0035266D01*
+X0152900Y0035406D01*
+X0152902Y0035547D01*
+X0149347Y0035547D02*
+X0149349Y0035688D01*
+X0149355Y0035828D01*
+X0149364Y0035969D01*
+X0149377Y0036109D01*
+X0149394Y0036249D01*
+X0149414Y0036388D01*
+X0149439Y0036526D01*
+X0149467Y0036664D01*
+X0149498Y0036801D01*
+X0149534Y0036938D01*
+X0149573Y0037073D01*
+X0149615Y0037207D01*
+X0149661Y0037340D01*
+X0149711Y0037472D01*
+X0149764Y0037602D01*
+X0149820Y0037731D01*
+X0149880Y0037858D01*
+X0151125Y0038747D02*
+X0151196Y0038745D01*
+X0151267Y0038739D01*
+X0151337Y0038730D01*
+X0151407Y0038716D01*
+X0151476Y0038699D01*
+X0151543Y0038679D01*
+X0151610Y0038654D01*
+X0151675Y0038626D01*
+X0151739Y0038595D01*
+X0151801Y0038560D01*
+X0151861Y0038522D01*
+X0151919Y0038481D01*
+X0151974Y0038437D01*
+X0152027Y0038389D01*
+X0152077Y0038339D01*
+X0152125Y0038287D01*
+X0152170Y0038232D01*
+X0152211Y0038174D01*
+X0152250Y0038114D01*
+X0152285Y0038053D01*
+X0152317Y0037989D01*
+X0152345Y0037924D01*
+X0152370Y0037858D01*
+X0152547Y0037324D02*
+X0149703Y0033769D01*
+X0151125Y0032346D02*
+X0151196Y0032348D01*
+X0151267Y0032354D01*
+X0151337Y0032363D01*
+X0151407Y0032377D01*
+X0151476Y0032394D01*
+X0151543Y0032414D01*
+X0151610Y0032439D01*
+X0151675Y0032467D01*
+X0151739Y0032498D01*
+X0151801Y0032533D01*
+X0151861Y0032571D01*
+X0151918Y0032612D01*
+X0151974Y0032656D01*
+X0152027Y0032704D01*
+X0152077Y0032754D01*
+X0152125Y0032806D01*
+X0152170Y0032861D01*
+X0152211Y0032919D01*
+X0152250Y0032979D01*
+X0152285Y0033040D01*
+X0152317Y0033104D01*
+X0152345Y0033169D01*
+X0152370Y0033235D01*
+X0151125Y0032346D02*
+X0151054Y0032348D01*
+X0150983Y0032354D01*
+X0150913Y0032363D01*
+X0150843Y0032377D01*
+X0150774Y0032394D01*
+X0150707Y0032414D01*
+X0150640Y0032439D01*
+X0150575Y0032467D01*
+X0150511Y0032498D01*
+X0150449Y0032533D01*
+X0150389Y0032571D01*
+X0150331Y0032612D01*
+X0150276Y0032656D01*
+X0150223Y0032704D01*
+X0150173Y0032754D01*
+X0150125Y0032806D01*
+X0150080Y0032861D01*
+X0150039Y0032919D01*
+X0150000Y0032979D01*
+X0149965Y0033040D01*
+X0149933Y0033104D01*
+X0149905Y0033169D01*
+X0149880Y0033235D01*
+X0143726Y0033236D02*
+X0143666Y0033363D01*
+X0143610Y0033492D01*
+X0143557Y0033622D01*
+X0143507Y0033754D01*
+X0143461Y0033887D01*
+X0143419Y0034021D01*
+X0143380Y0034156D01*
+X0143344Y0034293D01*
+X0143313Y0034430D01*
+X0143285Y0034568D01*
+X0143260Y0034706D01*
+X0143240Y0034845D01*
+X0143223Y0034985D01*
+X0143210Y0035125D01*
+X0143201Y0035266D01*
+X0143195Y0035406D01*
+X0143193Y0035547D01*
+X0146748Y0035547D02*
+X0146746Y0035688D01*
+X0146740Y0035828D01*
+X0146731Y0035969D01*
+X0146718Y0036109D01*
+X0146701Y0036249D01*
+X0146681Y0036388D01*
+X0146656Y0036526D01*
+X0146628Y0036664D01*
+X0146597Y0036801D01*
+X0146561Y0036938D01*
+X0146522Y0037073D01*
+X0146480Y0037207D01*
+X0146434Y0037340D01*
+X0146384Y0037472D01*
+X0146331Y0037602D01*
+X0146275Y0037731D01*
+X0146215Y0037858D01*
+X0146393Y0037324D02*
+X0143549Y0033769D01*
+X0144971Y0032346D02*
+X0145042Y0032348D01*
+X0145113Y0032354D01*
+X0145183Y0032363D01*
+X0145253Y0032377D01*
+X0145322Y0032394D01*
+X0145389Y0032414D01*
+X0145456Y0032439D01*
+X0145521Y0032467D01*
+X0145585Y0032498D01*
+X0145647Y0032533D01*
+X0145707Y0032571D01*
+X0145764Y0032612D01*
+X0145820Y0032656D01*
+X0145873Y0032704D01*
+X0145923Y0032754D01*
+X0145971Y0032806D01*
+X0146016Y0032861D01*
+X0146057Y0032919D01*
+X0146096Y0032979D01*
+X0146131Y0033040D01*
+X0146163Y0033104D01*
+X0146191Y0033169D01*
+X0146216Y0033235D01*
+X0144971Y0032346D02*
+X0144900Y0032348D01*
+X0144829Y0032354D01*
+X0144759Y0032363D01*
+X0144689Y0032377D01*
+X0144620Y0032394D01*
+X0144553Y0032414D01*
+X0144486Y0032439D01*
+X0144421Y0032467D01*
+X0144357Y0032498D01*
+X0144295Y0032533D01*
+X0144235Y0032571D01*
+X0144177Y0032612D01*
+X0144122Y0032656D01*
+X0144069Y0032704D01*
+X0144019Y0032754D01*
+X0143971Y0032806D01*
+X0143926Y0032861D01*
+X0143885Y0032919D01*
+X0143846Y0032979D01*
+X0143811Y0033040D01*
+X0143779Y0033104D01*
+X0143751Y0033169D01*
+X0143726Y0033235D01*
+X0152903Y0035547D02*
+X0152901Y0035688D01*
+X0152895Y0035828D01*
+X0152886Y0035969D01*
+X0152873Y0036109D01*
+X0152856Y0036249D01*
+X0152836Y0036388D01*
+X0152811Y0036526D01*
+X0152783Y0036664D01*
+X0152752Y0036801D01*
+X0152716Y0036938D01*
+X0152677Y0037073D01*
+X0152635Y0037207D01*
+X0152589Y0037340D01*
+X0152539Y0037472D01*
+X0152486Y0037602D01*
+X0152430Y0037731D01*
+X0152370Y0037858D01*
+X0151125Y0038747D02*
+X0151054Y0038745D01*
+X0150983Y0038739D01*
+X0150913Y0038730D01*
+X0150843Y0038716D01*
+X0150774Y0038699D01*
+X0150707Y0038679D01*
+X0150640Y0038654D01*
+X0150575Y0038626D01*
+X0150511Y0038595D01*
+X0150449Y0038560D01*
+X0150389Y0038522D01*
+X0150331Y0038481D01*
+X0150276Y0038437D01*
+X0150223Y0038389D01*
+X0150173Y0038339D01*
+X0150125Y0038287D01*
+X0150080Y0038232D01*
+X0150039Y0038174D01*
+X0150000Y0038114D01*
+X0149965Y0038053D01*
+X0149933Y0037989D01*
+X0149905Y0037924D01*
+X0149880Y0037858D01*
+X0143726Y0037858D02*
+X0143666Y0037731D01*
+X0143610Y0037602D01*
+X0143557Y0037472D01*
+X0143507Y0037340D01*
+X0143461Y0037207D01*
+X0143419Y0037073D01*
+X0143380Y0036938D01*
+X0143344Y0036801D01*
+X0143313Y0036664D01*
+X0143285Y0036526D01*
+X0143260Y0036388D01*
+X0143240Y0036249D01*
+X0143223Y0036109D01*
+X0143210Y0035969D01*
+X0143201Y0035828D01*
+X0143195Y0035688D01*
+X0143193Y0035547D01*
+X0144971Y0038747D02*
+X0145042Y0038745D01*
+X0145113Y0038739D01*
+X0145183Y0038730D01*
+X0145253Y0038716D01*
+X0145322Y0038699D01*
+X0145389Y0038679D01*
+X0145456Y0038654D01*
+X0145521Y0038626D01*
+X0145585Y0038595D01*
+X0145647Y0038560D01*
+X0145707Y0038522D01*
+X0145765Y0038481D01*
+X0145820Y0038437D01*
+X0145873Y0038389D01*
+X0145923Y0038339D01*
+X0145971Y0038287D01*
+X0146016Y0038232D01*
+X0146057Y0038174D01*
+X0146096Y0038114D01*
+X0146131Y0038053D01*
+X0146163Y0037989D01*
+X0146191Y0037924D01*
+X0146216Y0037858D01*
+X0144971Y0038747D02*
+X0144900Y0038745D01*
+X0144829Y0038739D01*
+X0144759Y0038730D01*
+X0144689Y0038716D01*
+X0144620Y0038699D01*
+X0144553Y0038679D01*
+X0144486Y0038654D01*
+X0144421Y0038626D01*
+X0144357Y0038595D01*
+X0144295Y0038560D01*
+X0144235Y0038522D01*
+X0144177Y0038481D01*
+X0144122Y0038437D01*
+X0144069Y0038389D01*
+X0144019Y0038339D01*
+X0143971Y0038287D01*
+X0143926Y0038232D01*
+X0143885Y0038174D01*
+X0143846Y0038114D01*
+X0143811Y0038053D01*
+X0143779Y0037989D01*
+X0143751Y0037924D01*
+X0143726Y0037858D01*
+X0140595Y0038747D02*
+X0137039Y0038747D01*
+X0137039Y0035902D01*
+X0139172Y0035902D01*
+X0139246Y0035900D01*
+X0139321Y0035894D01*
+X0139394Y0035884D01*
+X0139468Y0035871D01*
+X0139540Y0035854D01*
+X0139611Y0035832D01*
+X0139682Y0035808D01*
+X0139750Y0035779D01*
+X0139818Y0035747D01*
+X0139883Y0035711D01*
+X0139946Y0035673D01*
+X0140008Y0035630D01*
+X0140067Y0035585D01*
+X0140124Y0035537D01*
+X0140178Y0035486D01*
+X0140229Y0035432D01*
+X0140277Y0035375D01*
+X0140322Y0035316D01*
+X0140365Y0035254D01*
+X0140403Y0035191D01*
+X0140439Y0035126D01*
+X0140471Y0035058D01*
+X0140500Y0034990D01*
+X0140524Y0034919D01*
+X0140546Y0034848D01*
+X0140563Y0034776D01*
+X0140576Y0034702D01*
+X0140586Y0034629D01*
+X0140592Y0034554D01*
+X0140594Y0034480D01*
+X0134441Y0038747D02*
+X0130885Y0038747D01*
+X0149347Y0035547D02*
+X0149349Y0035406D01*
+X0149355Y0035266D01*
+X0149364Y0035125D01*
+X0149377Y0034985D01*
+X0149394Y0034845D01*
+X0149414Y0034706D01*
+X0149439Y0034568D01*
+X0149467Y0034430D01*
+X0149498Y0034293D01*
+X0149534Y0034156D01*
+X0149573Y0034021D01*
+X0149615Y0033887D01*
+X0149661Y0033754D01*
+X0149711Y0033622D01*
+X0149764Y0033492D01*
+X0149820Y0033363D01*
+X0149880Y0033236D01*
+X0159000Y0032347D02*
+X0159000Y0038747D01*
+X0163953Y0038747D02*
+X0165375Y0038747D01*
+X0164664Y0038747D02*
+X0164664Y0032347D01*
+X0163953Y0032347D02*
+X0165375Y0032347D01*
+X0161845Y0032347D02*
+X0159000Y0032347D01*
+X0169177Y0032347D02*
+X0169177Y0038747D01*
+X0170954Y0038747D02*
+X0167399Y0038747D01*
+X0173359Y0038747D02*
+X0176204Y0038747D01*
+X0173359Y0038747D02*
+X0173359Y0032347D01*
+X0176204Y0032347D01*
+X0175493Y0035902D02*
+X0173359Y0035902D01*
+X0191800Y0022047D02*
+X0101800Y0022047D01*
+X0101800Y0122047D01*
+X0191800Y0122047D01*
+X0191800Y0022047D01*
+X0203050Y0019547D02*
+X0203050Y0012047D01*
+X0210550Y0012047D01*
+X0215921Y0030347D02*
+X0218054Y0036747D01*
+X0220133Y0036747D02*
+X0221555Y0036747D01*
+X0220844Y0036747D02*
+X0220844Y0030347D01*
+X0220133Y0030347D02*
+X0221555Y0030347D01*
+X0224194Y0030347D02*
+X0224194Y0036747D01*
+X0227750Y0030347D01*
+X0227750Y0036747D01*
+X0215921Y0030347D02*
+X0213787Y0036747D01*
+X0255335Y0036747D02*
+X0255335Y0030347D01*
+X0257113Y0030347D01*
+X0257113Y0030346D02*
+X0257195Y0030348D01*
+X0257277Y0030354D01*
+X0257359Y0030363D01*
+X0257440Y0030376D01*
+X0257520Y0030393D01*
+X0257600Y0030414D01*
+X0257678Y0030438D01*
+X0257755Y0030466D01*
+X0257831Y0030497D01*
+X0257906Y0030532D01*
+X0257978Y0030571D01*
+X0258049Y0030612D01*
+X0258118Y0030657D01*
+X0258184Y0030705D01*
+X0258249Y0030756D01*
+X0258311Y0030810D01*
+X0258370Y0030867D01*
+X0258427Y0030926D01*
+X0258481Y0030988D01*
+X0258532Y0031053D01*
+X0258580Y0031119D01*
+X0258625Y0031188D01*
+X0258666Y0031259D01*
+X0258705Y0031331D01*
+X0258740Y0031406D01*
+X0258771Y0031482D01*
+X0258799Y0031559D01*
+X0258823Y0031637D01*
+X0258844Y0031717D01*
+X0258861Y0031797D01*
+X0258874Y0031878D01*
+X0258883Y0031960D01*
+X0258889Y0032042D01*
+X0258891Y0032124D01*
+X0258891Y0034969D01*
+X0258889Y0035051D01*
+X0258883Y0035133D01*
+X0258874Y0035215D01*
+X0258861Y0035296D01*
+X0258844Y0035376D01*
+X0258823Y0035456D01*
+X0258799Y0035534D01*
+X0258771Y0035611D01*
+X0258740Y0035687D01*
+X0258705Y0035762D01*
+X0258666Y0035834D01*
+X0258625Y0035905D01*
+X0258580Y0035974D01*
+X0258532Y0036040D01*
+X0258481Y0036105D01*
+X0258427Y0036167D01*
+X0258370Y0036226D01*
+X0258311Y0036283D01*
+X0258249Y0036337D01*
+X0258184Y0036388D01*
+X0258118Y0036436D01*
+X0258049Y0036481D01*
+X0257978Y0036522D01*
+X0257906Y0036561D01*
+X0257831Y0036596D01*
+X0257755Y0036627D01*
+X0257678Y0036655D01*
+X0257600Y0036679D01*
+X0257520Y0036700D01*
+X0257440Y0036717D01*
+X0257359Y0036730D01*
+X0257277Y0036739D01*
+X0257195Y0036745D01*
+X0257113Y0036747D01*
+X0255335Y0036747D01*
+X0261694Y0035324D02*
+X0263472Y0036747D01*
+X0263472Y0030347D01*
+X0261694Y0030347D02*
+X0265250Y0030347D01*
+X0278050Y0019547D02*
+X0278050Y0012047D01*
+X0270550Y0012047D01*
+X0332050Y0029547D02*
+X0332054Y0029878D01*
+X0332066Y0030209D01*
+X0332087Y0030540D01*
+X0332115Y0030870D01*
+X0332152Y0031200D01*
+X0332196Y0031528D01*
+X0332249Y0031855D01*
+X0332309Y0032181D01*
+X0332378Y0032505D01*
+X0332455Y0032827D01*
+X0332539Y0033148D01*
+X0332631Y0033466D01*
+X0332731Y0033782D01*
+X0332839Y0034095D01*
+X0332955Y0034406D01*
+X0333078Y0034713D01*
+X0333208Y0035018D01*
+X0333346Y0035319D01*
+X0333491Y0035617D01*
+X0333644Y0035911D01*
+X0333804Y0036201D01*
+X0333971Y0036487D01*
+X0334144Y0036769D01*
+X0334325Y0037047D01*
+X0334513Y0037320D01*
+X0334707Y0037589D01*
+X0334907Y0037853D01*
+X0335114Y0038111D01*
+X0335328Y0038365D01*
+X0335547Y0038613D01*
+X0335773Y0038856D01*
+X0336004Y0039093D01*
+X0336241Y0039324D01*
+X0336484Y0039550D01*
+X0336732Y0039769D01*
+X0336986Y0039983D01*
+X0337244Y0040190D01*
+X0337508Y0040390D01*
+X0337777Y0040584D01*
+X0338050Y0040772D01*
+X0338328Y0040953D01*
+X0338610Y0041126D01*
+X0338896Y0041293D01*
+X0339186Y0041453D01*
+X0339480Y0041606D01*
+X0339778Y0041751D01*
+X0340079Y0041889D01*
+X0340384Y0042019D01*
+X0340691Y0042142D01*
+X0341002Y0042258D01*
+X0341315Y0042366D01*
+X0341631Y0042466D01*
+X0341949Y0042558D01*
+X0342270Y0042642D01*
+X0342592Y0042719D01*
+X0342916Y0042788D01*
+X0343242Y0042848D01*
+X0343569Y0042901D01*
+X0343897Y0042945D01*
+X0344227Y0042982D01*
+X0344557Y0043010D01*
+X0344888Y0043031D01*
+X0345219Y0043043D01*
+X0345550Y0043047D01*
+X0345881Y0043043D01*
+X0346212Y0043031D01*
+X0346543Y0043010D01*
+X0346873Y0042982D01*
+X0347203Y0042945D01*
+X0347531Y0042901D01*
+X0347858Y0042848D01*
+X0348184Y0042788D01*
+X0348508Y0042719D01*
+X0348830Y0042642D01*
+X0349151Y0042558D01*
+X0349469Y0042466D01*
+X0349785Y0042366D01*
+X0350098Y0042258D01*
+X0350409Y0042142D01*
+X0350716Y0042019D01*
+X0351021Y0041889D01*
+X0351322Y0041751D01*
+X0351620Y0041606D01*
+X0351914Y0041453D01*
+X0352204Y0041293D01*
+X0352490Y0041126D01*
+X0352772Y0040953D01*
+X0353050Y0040772D01*
+X0353323Y0040584D01*
+X0353592Y0040390D01*
+X0353856Y0040190D01*
+X0354114Y0039983D01*
+X0354368Y0039769D01*
+X0354616Y0039550D01*
+X0354859Y0039324D01*
+X0355096Y0039093D01*
+X0355327Y0038856D01*
+X0355553Y0038613D01*
+X0355772Y0038365D01*
+X0355986Y0038111D01*
+X0356193Y0037853D01*
+X0356393Y0037589D01*
+X0356587Y0037320D01*
+X0356775Y0037047D01*
+X0356956Y0036769D01*
+X0357129Y0036487D01*
+X0357296Y0036201D01*
+X0357456Y0035911D01*
+X0357609Y0035617D01*
+X0357754Y0035319D01*
+X0357892Y0035018D01*
+X0358022Y0034713D01*
+X0358145Y0034406D01*
+X0358261Y0034095D01*
+X0358369Y0033782D01*
+X0358469Y0033466D01*
+X0358561Y0033148D01*
+X0358645Y0032827D01*
+X0358722Y0032505D01*
+X0358791Y0032181D01*
+X0358851Y0031855D01*
+X0358904Y0031528D01*
+X0358948Y0031200D01*
+X0358985Y0030870D01*
+X0359013Y0030540D01*
+X0359034Y0030209D01*
+X0359046Y0029878D01*
+X0359050Y0029547D01*
+X0359046Y0029216D01*
+X0359034Y0028885D01*
+X0359013Y0028554D01*
+X0358985Y0028224D01*
+X0358948Y0027894D01*
+X0358904Y0027566D01*
+X0358851Y0027239D01*
+X0358791Y0026913D01*
+X0358722Y0026589D01*
+X0358645Y0026267D01*
+X0358561Y0025946D01*
+X0358469Y0025628D01*
+X0358369Y0025312D01*
+X0358261Y0024999D01*
+X0358145Y0024688D01*
+X0358022Y0024381D01*
+X0357892Y0024076D01*
+X0357754Y0023775D01*
+X0357609Y0023477D01*
+X0357456Y0023183D01*
+X0357296Y0022893D01*
+X0357129Y0022607D01*
+X0356956Y0022325D01*
+X0356775Y0022047D01*
+X0356587Y0021774D01*
+X0356393Y0021505D01*
+X0356193Y0021241D01*
+X0355986Y0020983D01*
+X0355772Y0020729D01*
+X0355553Y0020481D01*
+X0355327Y0020238D01*
+X0355096Y0020001D01*
+X0354859Y0019770D01*
+X0354616Y0019544D01*
+X0354368Y0019325D01*
+X0354114Y0019111D01*
+X0353856Y0018904D01*
+X0353592Y0018704D01*
+X0353323Y0018510D01*
+X0353050Y0018322D01*
+X0352772Y0018141D01*
+X0352490Y0017968D01*
+X0352204Y0017801D01*
+X0351914Y0017641D01*
+X0351620Y0017488D01*
+X0351322Y0017343D01*
+X0351021Y0017205D01*
+X0350716Y0017075D01*
+X0350409Y0016952D01*
+X0350098Y0016836D01*
+X0349785Y0016728D01*
+X0349469Y0016628D01*
+X0349151Y0016536D01*
+X0348830Y0016452D01*
+X0348508Y0016375D01*
+X0348184Y0016306D01*
+X0347858Y0016246D01*
+X0347531Y0016193D01*
+X0347203Y0016149D01*
+X0346873Y0016112D01*
+X0346543Y0016084D01*
+X0346212Y0016063D01*
+X0345881Y0016051D01*
+X0345550Y0016047D01*
+X0345219Y0016051D01*
+X0344888Y0016063D01*
+X0344557Y0016084D01*
+X0344227Y0016112D01*
+X0343897Y0016149D01*
+X0343569Y0016193D01*
+X0343242Y0016246D01*
+X0342916Y0016306D01*
+X0342592Y0016375D01*
+X0342270Y0016452D01*
+X0341949Y0016536D01*
+X0341631Y0016628D01*
+X0341315Y0016728D01*
+X0341002Y0016836D01*
+X0340691Y0016952D01*
+X0340384Y0017075D01*
+X0340079Y0017205D01*
+X0339778Y0017343D01*
+X0339480Y0017488D01*
+X0339186Y0017641D01*
+X0338896Y0017801D01*
+X0338610Y0017968D01*
+X0338328Y0018141D01*
+X0338050Y0018322D01*
+X0337777Y0018510D01*
+X0337508Y0018704D01*
+X0337244Y0018904D01*
+X0336986Y0019111D01*
+X0336732Y0019325D01*
+X0336484Y0019544D01*
+X0336241Y0019770D01*
+X0336004Y0020001D01*
+X0335773Y0020238D01*
+X0335547Y0020481D01*
+X0335328Y0020729D01*
+X0335114Y0020983D01*
+X0334907Y0021241D01*
+X0334707Y0021505D01*
+X0334513Y0021774D01*
+X0334325Y0022047D01*
+X0334144Y0022325D01*
+X0333971Y0022607D01*
+X0333804Y0022893D01*
+X0333644Y0023183D01*
+X0333491Y0023477D01*
+X0333346Y0023775D01*
+X0333208Y0024076D01*
+X0333078Y0024381D01*
+X0332955Y0024688D01*
+X0332839Y0024999D01*
+X0332731Y0025312D01*
+X0332631Y0025628D01*
+X0332539Y0025946D01*
+X0332455Y0026267D01*
+X0332378Y0026589D01*
+X0332309Y0026913D01*
+X0332249Y0027239D01*
+X0332196Y0027566D01*
+X0332152Y0027894D01*
+X0332115Y0028224D01*
+X0332087Y0028554D01*
+X0332066Y0028885D01*
+X0332054Y0029216D01*
+X0332050Y0029547D01*
+X0322420Y0083602D02*
+X0361790Y0083602D01*
+X0361790Y0095413D01*
+X0361790Y0109192D02*
+X0361790Y0113129D01*
+X0361790Y0124940D02*
+X0361790Y0128877D01*
+X0361790Y0140688D02*
+X0361790Y0144625D01*
+X0361790Y0156436D02*
+X0361790Y0160373D01*
+X0361790Y0172184D02*
+X0361790Y0176121D01*
+X0361790Y0187933D02*
+X0361790Y0191870D01*
+X0361790Y0203681D02*
+X0361790Y0207618D01*
+X0361790Y0221397D02*
+X0361790Y0233208D01*
+X0338168Y0233208D01*
+X0318483Y0233208D02*
+X0283050Y0233208D01*
+X0283050Y0221397D01*
+X0278050Y0214547D02*
+X0270550Y0214547D01*
+X0278050Y0214547D02*
+X0278050Y0204547D01*
+X0283050Y0203681D02*
+X0283050Y0207618D01*
+X0283050Y0191870D02*
+X0283050Y0187933D01*
+X0283050Y0176121D02*
+X0283050Y0172184D01*
+X0283050Y0160373D02*
+X0283050Y0156436D01*
+X0283050Y0144625D02*
+X0283050Y0140688D01*
+X0283050Y0128877D02*
+X0283050Y0124940D01*
+X0283050Y0113129D02*
+X0283050Y0109192D01*
+X0283050Y0095413D02*
+X0283050Y0083602D01*
+X0298798Y0083602D01*
+X0317405Y0137939D02*
+X0317405Y0139717D01*
+X0317405Y0137939D02*
+X0323805Y0137939D01*
+X0320961Y0137939D02*
+X0320961Y0139717D01*
+X0320961Y0140073D02*
+X0323805Y0141495D01*
+X0323805Y0144274D02*
+X0317405Y0144274D01*
+X0317405Y0147119D01*
+X0320250Y0147119D02*
+X0320250Y0144274D01*
+X0320961Y0139717D02*
+X0320959Y0139800D01*
+X0320953Y0139883D01*
+X0320943Y0139966D01*
+X0320930Y0140049D01*
+X0320912Y0140130D01*
+X0320891Y0140211D01*
+X0320866Y0140290D01*
+X0320837Y0140368D01*
+X0320805Y0140445D01*
+X0320769Y0140520D01*
+X0320730Y0140594D01*
+X0320687Y0140665D01*
+X0320641Y0140735D01*
+X0320591Y0140802D01*
+X0320539Y0140867D01*
+X0320484Y0140929D01*
+X0320425Y0140989D01*
+X0320364Y0141046D01*
+X0320301Y0141100D01*
+X0320235Y0141151D01*
+X0320166Y0141198D01*
+X0320096Y0141243D01*
+X0320023Y0141284D01*
+X0319949Y0141321D01*
+X0319873Y0141356D01*
+X0319795Y0141386D01*
+X0319717Y0141413D01*
+X0319636Y0141436D01*
+X0319555Y0141456D01*
+X0319473Y0141471D01*
+X0319391Y0141483D01*
+X0319308Y0141491D01*
+X0319225Y0141495D01*
+X0319141Y0141495D01*
+X0319058Y0141491D01*
+X0318975Y0141483D01*
+X0318893Y0141471D01*
+X0318811Y0141456D01*
+X0318730Y0141436D01*
+X0318649Y0141413D01*
+X0318571Y0141386D01*
+X0318493Y0141356D01*
+X0318417Y0141321D01*
+X0318343Y0141284D01*
+X0318270Y0141243D01*
+X0318200Y0141198D01*
+X0318131Y0141151D01*
+X0318065Y0141100D01*
+X0318002Y0141046D01*
+X0317941Y0140989D01*
+X0317882Y0140929D01*
+X0317827Y0140867D01*
+X0317775Y0140802D01*
+X0317725Y0140735D01*
+X0317679Y0140665D01*
+X0317636Y0140594D01*
+X0317597Y0140520D01*
+X0317561Y0140445D01*
+X0317529Y0140368D01*
+X0317500Y0140290D01*
+X0317475Y0140211D01*
+X0317454Y0140130D01*
+X0317436Y0140049D01*
+X0317423Y0139966D01*
+X0317413Y0139883D01*
+X0317407Y0139800D01*
+X0317405Y0139717D01*
+X0322383Y0149391D02*
+X0317405Y0150813D01*
+X0320961Y0151880D02*
+X0323805Y0151880D01*
+X0322383Y0152946D02*
+X0322383Y0149391D01*
+X0322383Y0155545D02*
+X0317405Y0156967D01*
+X0320961Y0158034D02*
+X0323805Y0158034D01*
+X0322383Y0159100D02*
+X0322383Y0155545D01*
+X0322027Y0161699D02*
+X0320250Y0161699D01*
+X0320250Y0163832D01*
+X0320250Y0161699D02*
+X0320144Y0161701D01*
+X0320037Y0161707D01*
+X0319932Y0161717D01*
+X0319826Y0161731D01*
+X0319721Y0161749D01*
+X0319617Y0161770D01*
+X0319514Y0161796D01*
+X0319412Y0161825D01*
+X0319311Y0161859D01*
+X0319211Y0161896D01*
+X0319113Y0161936D01*
+X0319016Y0161981D01*
+X0318921Y0162029D01*
+X0318828Y0162080D01*
+X0318737Y0162135D01*
+X0318648Y0162193D01*
+X0318561Y0162255D01*
+X0318477Y0162319D01*
+X0318395Y0162387D01*
+X0318316Y0162458D01*
+X0318239Y0162532D01*
+X0318165Y0162609D01*
+X0318094Y0162688D01*
+X0318026Y0162770D01*
+X0317962Y0162854D01*
+X0317900Y0162941D01*
+X0317842Y0163030D01*
+X0317787Y0163121D01*
+X0317736Y0163214D01*
+X0317688Y0163309D01*
+X0317643Y0163406D01*
+X0317603Y0163504D01*
+X0317566Y0163604D01*
+X0317532Y0163705D01*
+X0317503Y0163807D01*
+X0317477Y0163910D01*
+X0317456Y0164014D01*
+X0317438Y0164119D01*
+X0317424Y0164225D01*
+X0317414Y0164330D01*
+X0317408Y0164437D01*
+X0317406Y0164543D01*
+X0317405Y0167853D02*
+X0317405Y0169986D01*
+X0317407Y0170060D01*
+X0317413Y0170135D01*
+X0317423Y0170208D01*
+X0317436Y0170282D01*
+X0317453Y0170354D01*
+X0317475Y0170425D01*
+X0317499Y0170496D01*
+X0317528Y0170564D01*
+X0317560Y0170632D01*
+X0317596Y0170697D01*
+X0317634Y0170760D01*
+X0317677Y0170822D01*
+X0317722Y0170881D01*
+X0317770Y0170938D01*
+X0317821Y0170992D01*
+X0317875Y0171043D01*
+X0317932Y0171091D01*
+X0317991Y0171136D01*
+X0318053Y0171179D01*
+X0318116Y0171217D01*
+X0318181Y0171253D01*
+X0318249Y0171285D01*
+X0318317Y0171314D01*
+X0318388Y0171338D01*
+X0318459Y0171360D01*
+X0318531Y0171377D01*
+X0318605Y0171390D01*
+X0318678Y0171400D01*
+X0318753Y0171406D01*
+X0318827Y0171408D01*
+X0318901Y0171406D01*
+X0318976Y0171400D01*
+X0319049Y0171390D01*
+X0319123Y0171377D01*
+X0319195Y0171360D01*
+X0319266Y0171338D01*
+X0319337Y0171314D01*
+X0319405Y0171285D01*
+X0319473Y0171253D01*
+X0319538Y0171217D01*
+X0319601Y0171179D01*
+X0319663Y0171136D01*
+X0319722Y0171091D01*
+X0319779Y0171043D01*
+X0319833Y0170992D01*
+X0319884Y0170938D01*
+X0319932Y0170881D01*
+X0319977Y0170822D01*
+X0320020Y0170760D01*
+X0320058Y0170697D01*
+X0320094Y0170632D01*
+X0320126Y0170564D01*
+X0320155Y0170496D01*
+X0320179Y0170425D01*
+X0320201Y0170354D01*
+X0320218Y0170282D01*
+X0320231Y0170208D01*
+X0320241Y0170135D01*
+X0320247Y0170060D01*
+X0320249Y0169986D01*
+X0320250Y0169986D02*
+X0320250Y0168564D01*
+X0320249Y0169631D02*
+X0320251Y0169714D01*
+X0320257Y0169797D01*
+X0320267Y0169880D01*
+X0320280Y0169963D01*
+X0320298Y0170044D01*
+X0320319Y0170125D01*
+X0320344Y0170204D01*
+X0320373Y0170282D01*
+X0320405Y0170359D01*
+X0320441Y0170434D01*
+X0320480Y0170508D01*
+X0320523Y0170579D01*
+X0320569Y0170649D01*
+X0320619Y0170716D01*
+X0320671Y0170781D01*
+X0320726Y0170843D01*
+X0320785Y0170903D01*
+X0320846Y0170960D01*
+X0320909Y0171014D01*
+X0320975Y0171065D01*
+X0321044Y0171112D01*
+X0321114Y0171157D01*
+X0321187Y0171198D01*
+X0321261Y0171235D01*
+X0321337Y0171270D01*
+X0321415Y0171300D01*
+X0321493Y0171327D01*
+X0321574Y0171350D01*
+X0321655Y0171370D01*
+X0321737Y0171385D01*
+X0321819Y0171397D01*
+X0321902Y0171405D01*
+X0321985Y0171409D01*
+X0322069Y0171409D01*
+X0322152Y0171405D01*
+X0322235Y0171397D01*
+X0322317Y0171385D01*
+X0322399Y0171370D01*
+X0322480Y0171350D01*
+X0322561Y0171327D01*
+X0322639Y0171300D01*
+X0322717Y0171270D01*
+X0322793Y0171235D01*
+X0322867Y0171198D01*
+X0322940Y0171157D01*
+X0323010Y0171112D01*
+X0323079Y0171065D01*
+X0323145Y0171014D01*
+X0323208Y0170960D01*
+X0323269Y0170903D01*
+X0323328Y0170843D01*
+X0323383Y0170781D01*
+X0323435Y0170716D01*
+X0323485Y0170649D01*
+X0323531Y0170579D01*
+X0323574Y0170508D01*
+X0323613Y0170434D01*
+X0323649Y0170359D01*
+X0323681Y0170282D01*
+X0323710Y0170204D01*
+X0323735Y0170125D01*
+X0323756Y0170044D01*
+X0323774Y0169963D01*
+X0323787Y0169880D01*
+X0323797Y0169797D01*
+X0323803Y0169714D01*
+X0323805Y0169631D01*
+X0323805Y0167853D01*
+X0322027Y0165254D02*
+X0321672Y0165254D01*
+X0321598Y0165252D01*
+X0321523Y0165246D01*
+X0321450Y0165236D01*
+X0321376Y0165223D01*
+X0321304Y0165206D01*
+X0321233Y0165184D01*
+X0321162Y0165160D01*
+X0321094Y0165131D01*
+X0321026Y0165099D01*
+X0320961Y0165063D01*
+X0320898Y0165025D01*
+X0320836Y0164982D01*
+X0320777Y0164937D01*
+X0320720Y0164889D01*
+X0320666Y0164838D01*
+X0320615Y0164784D01*
+X0320567Y0164727D01*
+X0320522Y0164668D01*
+X0320479Y0164606D01*
+X0320441Y0164543D01*
+X0320405Y0164478D01*
+X0320373Y0164410D01*
+X0320344Y0164342D01*
+X0320320Y0164271D01*
+X0320298Y0164200D01*
+X0320281Y0164128D01*
+X0320268Y0164054D01*
+X0320258Y0163981D01*
+X0320252Y0163906D01*
+X0320250Y0163832D01*
+X0322027Y0165255D02*
+X0322110Y0165253D01*
+X0322193Y0165247D01*
+X0322276Y0165237D01*
+X0322359Y0165224D01*
+X0322440Y0165206D01*
+X0322521Y0165185D01*
+X0322600Y0165160D01*
+X0322678Y0165131D01*
+X0322755Y0165099D01*
+X0322830Y0165063D01*
+X0322904Y0165024D01*
+X0322975Y0164981D01*
+X0323045Y0164935D01*
+X0323112Y0164885D01*
+X0323177Y0164833D01*
+X0323239Y0164778D01*
+X0323299Y0164719D01*
+X0323356Y0164658D01*
+X0323410Y0164595D01*
+X0323461Y0164529D01*
+X0323508Y0164460D01*
+X0323553Y0164390D01*
+X0323594Y0164317D01*
+X0323631Y0164243D01*
+X0323666Y0164167D01*
+X0323696Y0164089D01*
+X0323723Y0164011D01*
+X0323746Y0163930D01*
+X0323766Y0163849D01*
+X0323781Y0163767D01*
+X0323793Y0163685D01*
+X0323801Y0163602D01*
+X0323805Y0163519D01*
+X0323805Y0163435D01*
+X0323801Y0163352D01*
+X0323793Y0163269D01*
+X0323781Y0163187D01*
+X0323766Y0163105D01*
+X0323746Y0163024D01*
+X0323723Y0162943D01*
+X0323696Y0162865D01*
+X0323666Y0162787D01*
+X0323631Y0162711D01*
+X0323594Y0162637D01*
+X0323553Y0162564D01*
+X0323508Y0162494D01*
+X0323461Y0162425D01*
+X0323410Y0162359D01*
+X0323356Y0162296D01*
+X0323299Y0162235D01*
+X0323239Y0162176D01*
+X0323177Y0162121D01*
+X0323112Y0162069D01*
+X0323045Y0162019D01*
+X0322975Y0161973D01*
+X0322904Y0161930D01*
+X0322830Y0161891D01*
+X0322755Y0161855D01*
+X0322678Y0161823D01*
+X0322600Y0161794D01*
+X0322521Y0161769D01*
+X0322440Y0161748D01*
+X0322359Y0161730D01*
+X0322276Y0161717D01*
+X0322193Y0161707D01*
+X0322110Y0161701D01*
+X0322027Y0161699D01*
+X0320250Y0174224D02*
+X0320250Y0177068D01*
+X0317405Y0177068D02*
+X0317405Y0174224D01*
+X0323805Y0174224D01*
+X0323805Y0179340D02*
+X0323805Y0181118D01*
+X0323803Y0181201D01*
+X0323797Y0181284D01*
+X0323787Y0181367D01*
+X0323774Y0181450D01*
+X0323756Y0181531D01*
+X0323735Y0181612D01*
+X0323710Y0181691D01*
+X0323681Y0181769D01*
+X0323649Y0181846D01*
+X0323613Y0181921D01*
+X0323574Y0181995D01*
+X0323531Y0182066D01*
+X0323485Y0182136D01*
+X0323435Y0182203D01*
+X0323383Y0182268D01*
+X0323328Y0182330D01*
+X0323269Y0182390D01*
+X0323208Y0182447D01*
+X0323145Y0182501D01*
+X0323079Y0182552D01*
+X0323010Y0182599D01*
+X0322940Y0182644D01*
+X0322867Y0182685D01*
+X0322793Y0182722D01*
+X0322717Y0182757D01*
+X0322639Y0182787D01*
+X0322561Y0182814D01*
+X0322480Y0182837D01*
+X0322399Y0182857D01*
+X0322317Y0182872D01*
+X0322235Y0182884D01*
+X0322152Y0182892D01*
+X0322069Y0182896D01*
+X0321985Y0182896D01*
+X0321902Y0182892D01*
+X0321819Y0182884D01*
+X0321737Y0182872D01*
+X0321655Y0182857D01*
+X0321574Y0182837D01*
+X0321493Y0182814D01*
+X0321415Y0182787D01*
+X0321337Y0182757D01*
+X0321261Y0182722D01*
+X0321187Y0182685D01*
+X0321114Y0182644D01*
+X0321044Y0182599D01*
+X0320975Y0182552D01*
+X0320909Y0182501D01*
+X0320846Y0182447D01*
+X0320785Y0182390D01*
+X0320726Y0182330D01*
+X0320671Y0182268D01*
+X0320619Y0182203D01*
+X0320569Y0182136D01*
+X0320523Y0182066D01*
+X0320480Y0181995D01*
+X0320441Y0181921D01*
+X0320405Y0181846D01*
+X0320373Y0181769D01*
+X0320344Y0181691D01*
+X0320319Y0181612D01*
+X0320298Y0181531D01*
+X0320280Y0181450D01*
+X0320267Y0181367D01*
+X0320257Y0181284D01*
+X0320251Y0181201D01*
+X0320249Y0181118D01*
+X0320250Y0181474D02*
+X0320250Y0180051D01*
+X0320249Y0181474D02*
+X0320247Y0181548D01*
+X0320241Y0181623D01*
+X0320231Y0181696D01*
+X0320218Y0181770D01*
+X0320201Y0181842D01*
+X0320179Y0181913D01*
+X0320155Y0181984D01*
+X0320126Y0182052D01*
+X0320094Y0182120D01*
+X0320058Y0182185D01*
+X0320020Y0182248D01*
+X0319977Y0182310D01*
+X0319932Y0182369D01*
+X0319884Y0182426D01*
+X0319833Y0182480D01*
+X0319779Y0182531D01*
+X0319722Y0182579D01*
+X0319663Y0182624D01*
+X0319601Y0182667D01*
+X0319538Y0182705D01*
+X0319473Y0182741D01*
+X0319405Y0182773D01*
+X0319337Y0182802D01*
+X0319266Y0182826D01*
+X0319195Y0182848D01*
+X0319123Y0182865D01*
+X0319049Y0182878D01*
+X0318976Y0182888D01*
+X0318901Y0182894D01*
+X0318827Y0182896D01*
+X0318753Y0182894D01*
+X0318678Y0182888D01*
+X0318605Y0182878D01*
+X0318531Y0182865D01*
+X0318459Y0182848D01*
+X0318388Y0182826D01*
+X0318317Y0182802D01*
+X0318249Y0182773D01*
+X0318181Y0182741D01*
+X0318116Y0182705D01*
+X0318053Y0182667D01*
+X0317991Y0182624D01*
+X0317932Y0182579D01*
+X0317875Y0182531D01*
+X0317821Y0182480D01*
+X0317770Y0182426D01*
+X0317722Y0182369D01*
+X0317677Y0182310D01*
+X0317634Y0182248D01*
+X0317596Y0182185D01*
+X0317560Y0182120D01*
+X0317528Y0182052D01*
+X0317499Y0181984D01*
+X0317475Y0181913D01*
+X0317453Y0181842D01*
+X0317436Y0181770D01*
+X0317423Y0181696D01*
+X0317413Y0181623D01*
+X0317407Y0181548D01*
+X0317405Y0181474D01*
+X0317405Y0179340D01*
+X0320605Y0189050D02*
+X0320746Y0189048D01*
+X0320886Y0189042D01*
+X0321027Y0189033D01*
+X0321167Y0189020D01*
+X0321307Y0189003D01*
+X0321446Y0188983D01*
+X0321584Y0188958D01*
+X0321722Y0188930D01*
+X0321859Y0188899D01*
+X0321996Y0188863D01*
+X0322131Y0188824D01*
+X0322265Y0188782D01*
+X0322398Y0188736D01*
+X0322530Y0188686D01*
+X0322660Y0188633D01*
+X0322789Y0188577D01*
+X0322916Y0188517D01*
+X0322917Y0188517D02*
+X0322983Y0188492D01*
+X0323048Y0188464D01*
+X0323112Y0188432D01*
+X0323173Y0188397D01*
+X0323233Y0188358D01*
+X0323291Y0188317D01*
+X0323346Y0188272D01*
+X0323398Y0188224D01*
+X0323448Y0188174D01*
+X0323496Y0188121D01*
+X0323540Y0188065D01*
+X0323581Y0188008D01*
+X0323619Y0187948D01*
+X0323654Y0187886D01*
+X0323685Y0187822D01*
+X0323713Y0187757D01*
+X0323738Y0187690D01*
+X0323758Y0187623D01*
+X0323775Y0187554D01*
+X0323789Y0187484D01*
+X0323798Y0187414D01*
+X0323804Y0187343D01*
+X0323806Y0187272D01*
+X0323804Y0187201D01*
+X0323798Y0187130D01*
+X0323789Y0187060D01*
+X0323775Y0186990D01*
+X0323758Y0186921D01*
+X0323738Y0186854D01*
+X0323713Y0186787D01*
+X0323685Y0186722D01*
+X0323654Y0186658D01*
+X0323619Y0186596D01*
+X0323581Y0186536D01*
+X0323540Y0186478D01*
+X0323496Y0186423D01*
+X0323448Y0186370D01*
+X0323398Y0186320D01*
+X0323346Y0186272D01*
+X0323291Y0186227D01*
+X0323233Y0186186D01*
+X0323173Y0186147D01*
+X0323112Y0186112D01*
+X0323048Y0186080D01*
+X0322983Y0186052D01*
+X0322917Y0186027D01*
+X0322383Y0185850D02*
+X0318827Y0188694D01*
+X0318294Y0188517D02*
+X0318228Y0188492D01*
+X0318163Y0188464D01*
+X0318099Y0188432D01*
+X0318038Y0188397D01*
+X0317978Y0188358D01*
+X0317920Y0188317D01*
+X0317865Y0188272D01*
+X0317813Y0188224D01*
+X0317763Y0188174D01*
+X0317715Y0188121D01*
+X0317671Y0188066D01*
+X0317630Y0188008D01*
+X0317592Y0187948D01*
+X0317557Y0187886D01*
+X0317526Y0187822D01*
+X0317498Y0187757D01*
+X0317473Y0187690D01*
+X0317453Y0187623D01*
+X0317436Y0187554D01*
+X0317422Y0187484D01*
+X0317413Y0187414D01*
+X0317407Y0187343D01*
+X0317405Y0187272D01*
+X0317407Y0187201D01*
+X0317413Y0187130D01*
+X0317422Y0187060D01*
+X0317436Y0186990D01*
+X0317453Y0186921D01*
+X0317473Y0186854D01*
+X0317498Y0186787D01*
+X0317526Y0186722D01*
+X0317557Y0186658D01*
+X0317592Y0186596D01*
+X0317630Y0186536D01*
+X0317671Y0186478D01*
+X0317715Y0186423D01*
+X0317763Y0186370D01*
+X0317813Y0186320D01*
+X0317865Y0186272D01*
+X0317920Y0186227D01*
+X0317978Y0186186D01*
+X0318038Y0186147D01*
+X0318099Y0186112D01*
+X0318163Y0186080D01*
+X0318228Y0186052D01*
+X0318294Y0186027D01*
+X0318294Y0188517D02*
+X0318421Y0188577D01*
+X0318550Y0188633D01*
+X0318680Y0188686D01*
+X0318812Y0188736D01*
+X0318945Y0188782D01*
+X0319079Y0188824D01*
+X0319214Y0188863D01*
+X0319351Y0188899D01*
+X0319488Y0188930D01*
+X0319626Y0188958D01*
+X0319764Y0188983D01*
+X0319903Y0189003D01*
+X0320043Y0189020D01*
+X0320183Y0189033D01*
+X0320324Y0189042D01*
+X0320464Y0189048D01*
+X0320605Y0189050D01*
+X0320605Y0185494D02*
+X0320464Y0185496D01*
+X0320324Y0185502D01*
+X0320183Y0185511D01*
+X0320043Y0185524D01*
+X0319903Y0185541D01*
+X0319764Y0185561D01*
+X0319626Y0185586D01*
+X0319488Y0185614D01*
+X0319351Y0185645D01*
+X0319214Y0185681D01*
+X0319079Y0185720D01*
+X0318945Y0185762D01*
+X0318812Y0185808D01*
+X0318680Y0185858D01*
+X0318550Y0185911D01*
+X0318421Y0185967D01*
+X0318294Y0186027D01*
+X0320605Y0185494D02*
+X0320746Y0185496D01*
+X0320886Y0185502D01*
+X0321027Y0185511D01*
+X0321167Y0185524D01*
+X0321307Y0185541D01*
+X0321446Y0185561D01*
+X0321584Y0185586D01*
+X0321722Y0185614D01*
+X0321859Y0185645D01*
+X0321996Y0185681D01*
+X0322131Y0185720D01*
+X0322265Y0185762D01*
+X0322398Y0185808D01*
+X0322530Y0185858D01*
+X0322660Y0185911D01*
+X0322789Y0185967D01*
+X0322916Y0186027D01*
+X0262750Y0200347D02*
+X0259194Y0200347D01*
+X0262217Y0203902D01*
+X0261150Y0206747D02*
+X0261061Y0206745D01*
+X0260972Y0206739D01*
+X0260883Y0206730D01*
+X0260795Y0206716D01*
+X0260708Y0206699D01*
+X0260621Y0206678D01*
+X0260535Y0206653D01*
+X0260451Y0206625D01*
+X0260368Y0206592D01*
+X0260286Y0206557D01*
+X0260206Y0206517D01*
+X0260128Y0206475D01*
+X0260051Y0206429D01*
+X0259977Y0206380D01*
+X0259905Y0206327D01*
+X0259835Y0206272D01*
+X0259768Y0206213D01*
+X0259703Y0206152D01*
+X0259641Y0206088D01*
+X0259582Y0206021D01*
+X0259526Y0205952D01*
+X0259473Y0205880D01*
+X0259423Y0205806D01*
+X0259376Y0205730D01*
+X0259333Y0205653D01*
+X0259293Y0205573D01*
+X0259256Y0205492D01*
+X0259223Y0205409D01*
+X0259194Y0205324D01*
+X0262217Y0203902D02*
+X0262274Y0203960D01*
+X0262330Y0204021D01*
+X0262382Y0204084D01*
+X0262431Y0204149D01*
+X0262477Y0204217D01*
+X0262519Y0204287D01*
+X0262559Y0204359D01*
+X0262594Y0204432D01*
+X0262627Y0204508D01*
+X0262655Y0204584D01*
+X0262680Y0204662D01*
+X0262701Y0204741D01*
+X0262719Y0204821D01*
+X0262732Y0204902D01*
+X0262742Y0204983D01*
+X0262748Y0205065D01*
+X0262750Y0205147D01*
+X0262748Y0205226D01*
+X0262742Y0205304D01*
+X0262733Y0205382D01*
+X0262719Y0205459D01*
+X0262702Y0205536D01*
+X0262681Y0205611D01*
+X0262656Y0205686D01*
+X0262628Y0205759D01*
+X0262596Y0205831D01*
+X0262561Y0205901D01*
+X0262522Y0205970D01*
+X0262480Y0206036D01*
+X0262435Y0206100D01*
+X0262387Y0206162D01*
+X0262336Y0206221D01*
+X0262281Y0206278D01*
+X0262224Y0206333D01*
+X0262165Y0206384D01*
+X0262103Y0206432D01*
+X0262039Y0206477D01*
+X0261973Y0206519D01*
+X0261904Y0206558D01*
+X0261834Y0206593D01*
+X0261762Y0206625D01*
+X0261689Y0206653D01*
+X0261614Y0206678D01*
+X0261539Y0206699D01*
+X0261462Y0206716D01*
+X0261385Y0206730D01*
+X0261307Y0206739D01*
+X0261229Y0206745D01*
+X0261150Y0206747D01*
+X0254818Y0206747D02*
+X0254818Y0200347D01*
+X0253040Y0200347D02*
+X0256596Y0200347D01*
+X0253040Y0205324D02*
+X0254818Y0206747D01*
+X0250237Y0204969D02*
+X0250237Y0202124D01*
+X0250235Y0202042D01*
+X0250229Y0201960D01*
+X0250220Y0201878D01*
+X0250207Y0201797D01*
+X0250190Y0201717D01*
+X0250169Y0201637D01*
+X0250145Y0201559D01*
+X0250117Y0201482D01*
+X0250086Y0201406D01*
+X0250051Y0201331D01*
+X0250012Y0201259D01*
+X0249971Y0201188D01*
+X0249926Y0201119D01*
+X0249878Y0201053D01*
+X0249827Y0200988D01*
+X0249773Y0200926D01*
+X0249716Y0200867D01*
+X0249657Y0200810D01*
+X0249595Y0200756D01*
+X0249530Y0200705D01*
+X0249464Y0200657D01*
+X0249395Y0200612D01*
+X0249324Y0200571D01*
+X0249252Y0200532D01*
+X0249177Y0200497D01*
+X0249101Y0200466D01*
+X0249024Y0200438D01*
+X0248946Y0200414D01*
+X0248866Y0200393D01*
+X0248786Y0200376D01*
+X0248705Y0200363D01*
+X0248623Y0200354D01*
+X0248541Y0200348D01*
+X0248459Y0200346D01*
+X0248459Y0200347D02*
+X0246681Y0200347D01*
+X0246681Y0206747D01*
+X0248459Y0206747D01*
+X0248541Y0206745D01*
+X0248623Y0206739D01*
+X0248705Y0206730D01*
+X0248786Y0206717D01*
+X0248866Y0206700D01*
+X0248946Y0206679D01*
+X0249024Y0206655D01*
+X0249101Y0206627D01*
+X0249177Y0206596D01*
+X0249252Y0206561D01*
+X0249324Y0206522D01*
+X0249395Y0206481D01*
+X0249464Y0206436D01*
+X0249530Y0206388D01*
+X0249595Y0206337D01*
+X0249657Y0206283D01*
+X0249716Y0206226D01*
+X0249773Y0206167D01*
+X0249827Y0206105D01*
+X0249878Y0206040D01*
+X0249926Y0205974D01*
+X0249971Y0205905D01*
+X0250012Y0205834D01*
+X0250051Y0205762D01*
+X0250086Y0205687D01*
+X0250117Y0205611D01*
+X0250145Y0205534D01*
+X0250169Y0205456D01*
+X0250190Y0205376D01*
+X0250207Y0205296D01*
+X0250220Y0205215D01*
+X0250229Y0205133D01*
+X0250235Y0205051D01*
+X0250237Y0204969D01*
+X0231328Y0203902D02*
+X0231402Y0203904D01*
+X0231477Y0203910D01*
+X0231550Y0203920D01*
+X0231624Y0203933D01*
+X0231696Y0203950D01*
+X0231767Y0203972D01*
+X0231838Y0203996D01*
+X0231906Y0204025D01*
+X0231974Y0204057D01*
+X0232039Y0204093D01*
+X0232102Y0204131D01*
+X0232164Y0204174D01*
+X0232223Y0204219D01*
+X0232280Y0204267D01*
+X0232334Y0204318D01*
+X0232385Y0204372D01*
+X0232433Y0204429D01*
+X0232478Y0204488D01*
+X0232521Y0204550D01*
+X0232559Y0204613D01*
+X0232595Y0204678D01*
+X0232627Y0204746D01*
+X0232656Y0204814D01*
+X0232680Y0204885D01*
+X0232702Y0204956D01*
+X0232719Y0205028D01*
+X0232732Y0205102D01*
+X0232742Y0205175D01*
+X0232748Y0205250D01*
+X0232750Y0205324D01*
+X0232748Y0205398D01*
+X0232742Y0205473D01*
+X0232732Y0205546D01*
+X0232719Y0205620D01*
+X0232702Y0205692D01*
+X0232680Y0205763D01*
+X0232656Y0205834D01*
+X0232627Y0205902D01*
+X0232595Y0205970D01*
+X0232559Y0206035D01*
+X0232521Y0206098D01*
+X0232478Y0206160D01*
+X0232433Y0206219D01*
+X0232385Y0206276D01*
+X0232334Y0206330D01*
+X0232280Y0206381D01*
+X0232223Y0206429D01*
+X0232164Y0206474D01*
+X0232102Y0206517D01*
+X0232039Y0206555D01*
+X0231974Y0206591D01*
+X0231906Y0206623D01*
+X0231838Y0206652D01*
+X0231767Y0206676D01*
+X0231696Y0206698D01*
+X0231624Y0206715D01*
+X0231550Y0206728D01*
+X0231477Y0206738D01*
+X0231402Y0206744D01*
+X0231328Y0206746D01*
+X0231328Y0206747D02*
+X0229194Y0206747D01*
+X0229906Y0203902D02*
+X0231328Y0203902D01*
+X0230972Y0203902D02*
+X0231055Y0203900D01*
+X0231138Y0203894D01*
+X0231221Y0203884D01*
+X0231304Y0203871D01*
+X0231385Y0203853D01*
+X0231466Y0203832D01*
+X0231545Y0203807D01*
+X0231623Y0203778D01*
+X0231700Y0203746D01*
+X0231775Y0203710D01*
+X0231849Y0203671D01*
+X0231920Y0203628D01*
+X0231990Y0203582D01*
+X0232057Y0203532D01*
+X0232122Y0203480D01*
+X0232184Y0203425D01*
+X0232244Y0203366D01*
+X0232301Y0203305D01*
+X0232355Y0203242D01*
+X0232406Y0203176D01*
+X0232453Y0203107D01*
+X0232498Y0203037D01*
+X0232539Y0202964D01*
+X0232576Y0202890D01*
+X0232611Y0202814D01*
+X0232641Y0202736D01*
+X0232668Y0202658D01*
+X0232691Y0202577D01*
+X0232711Y0202496D01*
+X0232726Y0202414D01*
+X0232738Y0202332D01*
+X0232746Y0202249D01*
+X0232750Y0202166D01*
+X0232750Y0202082D01*
+X0232746Y0201999D01*
+X0232738Y0201916D01*
+X0232726Y0201834D01*
+X0232711Y0201752D01*
+X0232691Y0201671D01*
+X0232668Y0201590D01*
+X0232641Y0201512D01*
+X0232611Y0201434D01*
+X0232576Y0201358D01*
+X0232539Y0201284D01*
+X0232498Y0201211D01*
+X0232453Y0201141D01*
+X0232406Y0201072D01*
+X0232355Y0201006D01*
+X0232301Y0200943D01*
+X0232244Y0200882D01*
+X0232184Y0200823D01*
+X0232122Y0200768D01*
+X0232057Y0200716D01*
+X0231990Y0200666D01*
+X0231920Y0200620D01*
+X0231849Y0200577D01*
+X0231775Y0200538D01*
+X0231700Y0200502D01*
+X0231623Y0200470D01*
+X0231545Y0200441D01*
+X0231466Y0200416D01*
+X0231385Y0200395D01*
+X0231304Y0200377D01*
+X0231221Y0200364D01*
+X0231138Y0200354D01*
+X0231055Y0200348D01*
+X0230972Y0200346D01*
+X0230972Y0200347D02*
+X0229194Y0200347D01*
+X0226596Y0200347D02*
+X0223040Y0200347D01*
+X0224818Y0200347D02*
+X0224818Y0206747D01*
+X0223040Y0205324D01*
+X0220237Y0204969D02*
+X0220237Y0202124D01*
+X0220235Y0202042D01*
+X0220229Y0201960D01*
+X0220220Y0201878D01*
+X0220207Y0201797D01*
+X0220190Y0201717D01*
+X0220169Y0201637D01*
+X0220145Y0201559D01*
+X0220117Y0201482D01*
+X0220086Y0201406D01*
+X0220051Y0201331D01*
+X0220012Y0201259D01*
+X0219971Y0201188D01*
+X0219926Y0201119D01*
+X0219878Y0201053D01*
+X0219827Y0200988D01*
+X0219773Y0200926D01*
+X0219716Y0200867D01*
+X0219657Y0200810D01*
+X0219595Y0200756D01*
+X0219530Y0200705D01*
+X0219464Y0200657D01*
+X0219395Y0200612D01*
+X0219324Y0200571D01*
+X0219252Y0200532D01*
+X0219177Y0200497D01*
+X0219101Y0200466D01*
+X0219024Y0200438D01*
+X0218946Y0200414D01*
+X0218866Y0200393D01*
+X0218786Y0200376D01*
+X0218705Y0200363D01*
+X0218623Y0200354D01*
+X0218541Y0200348D01*
+X0218459Y0200346D01*
+X0218459Y0200347D02*
+X0216681Y0200347D01*
+X0216681Y0206747D01*
+X0218459Y0206747D01*
+X0218541Y0206745D01*
+X0218623Y0206739D01*
+X0218705Y0206730D01*
+X0218786Y0206717D01*
+X0218866Y0206700D01*
+X0218946Y0206679D01*
+X0219024Y0206655D01*
+X0219101Y0206627D01*
+X0219177Y0206596D01*
+X0219252Y0206561D01*
+X0219324Y0206522D01*
+X0219395Y0206481D01*
+X0219464Y0206436D01*
+X0219530Y0206388D01*
+X0219595Y0206337D01*
+X0219657Y0206283D01*
+X0219716Y0206226D01*
+X0219773Y0206167D01*
+X0219827Y0206105D01*
+X0219878Y0206040D01*
+X0219926Y0205974D01*
+X0219971Y0205905D01*
+X0220012Y0205834D01*
+X0220051Y0205762D01*
+X0220086Y0205687D01*
+X0220117Y0205611D01*
+X0220145Y0205534D01*
+X0220169Y0205456D01*
+X0220190Y0205376D01*
+X0220207Y0205296D01*
+X0220220Y0205215D01*
+X0220229Y0205133D01*
+X0220235Y0205051D01*
+X0220237Y0204969D01*
+X0210550Y0214547D02*
+X0203050Y0214547D01*
+X0203050Y0207047D01*
+X0196500Y0209597D02*
+X0194167Y0213874D01*
+X0192611Y0212319D02*
+X0196500Y0216597D01*
+X0192611Y0216597D02*
+X0192611Y0209597D01*
+X0189388Y0211541D02*
+X0189388Y0214652D01*
+X0189386Y0214739D01*
+X0189380Y0214826D01*
+X0189370Y0214913D01*
+X0189357Y0214999D01*
+X0189339Y0215085D01*
+X0189318Y0215169D01*
+X0189293Y0215253D01*
+X0189264Y0215335D01*
+X0189232Y0215416D01*
+X0189195Y0215495D01*
+X0189156Y0215573D01*
+X0189113Y0215649D01*
+X0189066Y0215723D01*
+X0189017Y0215795D01*
+X0188964Y0215864D01*
+X0188908Y0215931D01*
+X0188849Y0215995D01*
+X0188787Y0216057D01*
+X0188723Y0216116D01*
+X0188656Y0216172D01*
+X0188587Y0216225D01*
+X0188515Y0216274D01*
+X0188441Y0216321D01*
+X0188365Y0216364D01*
+X0188287Y0216403D01*
+X0188208Y0216440D01*
+X0188127Y0216472D01*
+X0188045Y0216501D01*
+X0187961Y0216526D01*
+X0187877Y0216547D01*
+X0187791Y0216565D01*
+X0187705Y0216578D01*
+X0187618Y0216588D01*
+X0187531Y0216594D01*
+X0187444Y0216596D01*
+X0187444Y0216597D02*
+X0185499Y0216597D01*
+X0185499Y0209597D01*
+X0187444Y0209597D01*
+X0187531Y0209599D01*
+X0187618Y0209605D01*
+X0187705Y0209615D01*
+X0187791Y0209628D01*
+X0187877Y0209646D01*
+X0187961Y0209667D01*
+X0188045Y0209692D01*
+X0188127Y0209721D01*
+X0188208Y0209753D01*
+X0188287Y0209790D01*
+X0188365Y0209829D01*
+X0188441Y0209872D01*
+X0188515Y0209919D01*
+X0188587Y0209968D01*
+X0188656Y0210021D01*
+X0188723Y0210077D01*
+X0188787Y0210136D01*
+X0188849Y0210198D01*
+X0188908Y0210262D01*
+X0188964Y0210329D01*
+X0189017Y0210398D01*
+X0189066Y0210470D01*
+X0189113Y0210544D01*
+X0189156Y0210620D01*
+X0189195Y0210698D01*
+X0189232Y0210777D01*
+X0189264Y0210858D01*
+X0189293Y0210940D01*
+X0189318Y0211024D01*
+X0189339Y0211108D01*
+X0189357Y0211194D01*
+X0189370Y0211280D01*
+X0189380Y0211367D01*
+X0189386Y0211454D01*
+X0189388Y0211541D01*
+X0182354Y0209597D02*
+X0182354Y0216597D01*
+X0182354Y0213486D02*
+X0178465Y0213486D01*
+X0178465Y0216597D02*
+X0178465Y0209597D01*
+X0175539Y0211152D02*
+X0171650Y0211152D01*
+X0173206Y0216597D01*
+X0169277Y0216597D02*
+X0166166Y0216597D01*
+X0166166Y0209597D01*
+X0166166Y0213486D02*
+X0169277Y0213486D01*
+X0174373Y0212708D02*
+X0174373Y0209597D01*
+X0171014Y0220997D02*
+X0171014Y0224497D01*
+X0171015Y0224497D02*
+X0171013Y0224562D01*
+X0171008Y0224628D01*
+X0170999Y0224692D01*
+X0170986Y0224757D01*
+X0170969Y0224820D01*
+X0170950Y0224882D01*
+X0170926Y0224944D01*
+X0170899Y0225003D01*
+X0170869Y0225061D01*
+X0170836Y0225118D01*
+X0170800Y0225172D01*
+X0170760Y0225225D01*
+X0170718Y0225275D01*
+X0170673Y0225322D01*
+X0170626Y0225367D01*
+X0170576Y0225409D01*
+X0170523Y0225449D01*
+X0170469Y0225485D01*
+X0170412Y0225518D01*
+X0170354Y0225548D01*
+X0170295Y0225575D01*
+X0170233Y0225599D01*
+X0170171Y0225618D01*
+X0170108Y0225635D01*
+X0170043Y0225648D01*
+X0169979Y0225657D01*
+X0169913Y0225662D01*
+X0169848Y0225664D01*
+X0169848Y0225663D02*
+X0166348Y0225663D01*
+X0166348Y0220997D01*
+X0168681Y0220997D02*
+X0168681Y0225663D01*
+X0163422Y0224108D02*
+X0163422Y0223330D01*
+X0160311Y0223330D01*
+X0160311Y0224108D02*
+X0160311Y0222163D01*
+X0160313Y0222098D01*
+X0160318Y0222032D01*
+X0160327Y0221968D01*
+X0160340Y0221903D01*
+X0160357Y0221840D01*
+X0160376Y0221778D01*
+X0160400Y0221716D01*
+X0160427Y0221657D01*
+X0160457Y0221599D01*
+X0160490Y0221542D01*
+X0160526Y0221488D01*
+X0160566Y0221435D01*
+X0160608Y0221385D01*
+X0160653Y0221338D01*
+X0160700Y0221293D01*
+X0160750Y0221251D01*
+X0160803Y0221211D01*
+X0160857Y0221175D01*
+X0160914Y0221142D01*
+X0160972Y0221112D01*
+X0161031Y0221085D01*
+X0161093Y0221061D01*
+X0161155Y0221042D01*
+X0161218Y0221025D01*
+X0161283Y0221012D01*
+X0161347Y0221003D01*
+X0161413Y0220998D01*
+X0161478Y0220996D01*
+X0161478Y0220997D02*
+X0163422Y0220997D01*
+X0163423Y0224108D02*
+X0163421Y0224186D01*
+X0163415Y0224263D01*
+X0163406Y0224340D01*
+X0163392Y0224416D01*
+X0163375Y0224492D01*
+X0163354Y0224567D01*
+X0163329Y0224640D01*
+X0163301Y0224712D01*
+X0163269Y0224783D01*
+X0163234Y0224852D01*
+X0163195Y0224919D01*
+X0163153Y0224985D01*
+X0163107Y0225048D01*
+X0163059Y0225108D01*
+X0163008Y0225166D01*
+X0162953Y0225222D01*
+X0162897Y0225275D01*
+X0162837Y0225325D01*
+X0162775Y0225371D01*
+X0162711Y0225415D01*
+X0162645Y0225456D01*
+X0162577Y0225493D01*
+X0162507Y0225526D01*
+X0162435Y0225556D01*
+X0162363Y0225583D01*
+X0162288Y0225606D01*
+X0162213Y0225625D01*
+X0162137Y0225640D01*
+X0162060Y0225652D01*
+X0161983Y0225660D01*
+X0161906Y0225664D01*
+X0161828Y0225664D01*
+X0161751Y0225660D01*
+X0161674Y0225652D01*
+X0161597Y0225640D01*
+X0161521Y0225625D01*
+X0161446Y0225606D01*
+X0161371Y0225583D01*
+X0161299Y0225556D01*
+X0161227Y0225526D01*
+X0161157Y0225493D01*
+X0161089Y0225456D01*
+X0161023Y0225415D01*
+X0160959Y0225371D01*
+X0160897Y0225325D01*
+X0160837Y0225275D01*
+X0160781Y0225222D01*
+X0160726Y0225166D01*
+X0160675Y0225108D01*
+X0160627Y0225048D01*
+X0160581Y0224985D01*
+X0160539Y0224919D01*
+X0160500Y0224852D01*
+X0160465Y0224783D01*
+X0160433Y0224712D01*
+X0160405Y0224640D01*
+X0160380Y0224567D01*
+X0160359Y0224492D01*
+X0160342Y0224416D01*
+X0160328Y0224340D01*
+X0160319Y0224263D01*
+X0160313Y0224186D01*
+X0160311Y0224108D01*
+X0157460Y0225663D02*
+X0155516Y0225663D01*
+X0155516Y0225664D02*
+X0155451Y0225662D01*
+X0155385Y0225657D01*
+X0155321Y0225648D01*
+X0155256Y0225635D01*
+X0155193Y0225618D01*
+X0155131Y0225599D01*
+X0155069Y0225575D01*
+X0155010Y0225548D01*
+X0154952Y0225518D01*
+X0154895Y0225485D01*
+X0154841Y0225449D01*
+X0154788Y0225409D01*
+X0154738Y0225367D01*
+X0154691Y0225322D01*
+X0154646Y0225275D01*
+X0154604Y0225225D01*
+X0154564Y0225172D01*
+X0154528Y0225118D01*
+X0154495Y0225061D01*
+X0154465Y0225003D01*
+X0154438Y0224944D01*
+X0154414Y0224882D01*
+X0154395Y0224820D01*
+X0154378Y0224757D01*
+X0154365Y0224692D01*
+X0154356Y0224628D01*
+X0154351Y0224562D01*
+X0154349Y0224497D01*
+X0154349Y0222163D01*
+X0154351Y0222098D01*
+X0154356Y0222032D01*
+X0154365Y0221968D01*
+X0154378Y0221903D01*
+X0154395Y0221840D01*
+X0154414Y0221778D01*
+X0154438Y0221716D01*
+X0154465Y0221657D01*
+X0154495Y0221599D01*
+X0154528Y0221542D01*
+X0154564Y0221488D01*
+X0154604Y0221435D01*
+X0154646Y0221385D01*
+X0154691Y0221338D01*
+X0154738Y0221293D01*
+X0154788Y0221251D01*
+X0154841Y0221211D01*
+X0154895Y0221175D01*
+X0154952Y0221142D01*
+X0155010Y0221112D01*
+X0155069Y0221085D01*
+X0155131Y0221061D01*
+X0155193Y0221042D01*
+X0155256Y0221025D01*
+X0155321Y0221012D01*
+X0155385Y0221003D01*
+X0155451Y0220998D01*
+X0155516Y0220996D01*
+X0155516Y0220997D02*
+X0157460Y0220997D01*
+X0157460Y0227997D01*
+X0151772Y0224108D02*
+X0151772Y0222552D01*
+X0151770Y0222474D01*
+X0151764Y0222397D01*
+X0151755Y0222320D01*
+X0151741Y0222244D01*
+X0151724Y0222168D01*
+X0151703Y0222093D01*
+X0151678Y0222020D01*
+X0151650Y0221948D01*
+X0151618Y0221877D01*
+X0151583Y0221808D01*
+X0151544Y0221741D01*
+X0151502Y0221675D01*
+X0151456Y0221612D01*
+X0151408Y0221552D01*
+X0151357Y0221494D01*
+X0151302Y0221438D01*
+X0151246Y0221385D01*
+X0151186Y0221335D01*
+X0151124Y0221289D01*
+X0151060Y0221245D01*
+X0150994Y0221204D01*
+X0150926Y0221167D01*
+X0150856Y0221134D01*
+X0150784Y0221104D01*
+X0150712Y0221077D01*
+X0150637Y0221054D01*
+X0150562Y0221035D01*
+X0150486Y0221020D01*
+X0150409Y0221008D01*
+X0150332Y0221000D01*
+X0150255Y0220996D01*
+X0150177Y0220996D01*
+X0150100Y0221000D01*
+X0150023Y0221008D01*
+X0149946Y0221020D01*
+X0149870Y0221035D01*
+X0149795Y0221054D01*
+X0149720Y0221077D01*
+X0149648Y0221104D01*
+X0149576Y0221134D01*
+X0149506Y0221167D01*
+X0149438Y0221204D01*
+X0149372Y0221245D01*
+X0149308Y0221289D01*
+X0149246Y0221335D01*
+X0149186Y0221385D01*
+X0149130Y0221438D01*
+X0149075Y0221494D01*
+X0149024Y0221552D01*
+X0148976Y0221612D01*
+X0148930Y0221675D01*
+X0148888Y0221741D01*
+X0148849Y0221808D01*
+X0148814Y0221877D01*
+X0148782Y0221948D01*
+X0148754Y0222020D01*
+X0148729Y0222093D01*
+X0148708Y0222168D01*
+X0148691Y0222244D01*
+X0148677Y0222320D01*
+X0148668Y0222397D01*
+X0148662Y0222474D01*
+X0148660Y0222552D01*
+X0148660Y0224108D01*
+X0148662Y0224186D01*
+X0148668Y0224263D01*
+X0148677Y0224340D01*
+X0148691Y0224416D01*
+X0148708Y0224492D01*
+X0148729Y0224567D01*
+X0148754Y0224640D01*
+X0148782Y0224712D01*
+X0148814Y0224783D01*
+X0148849Y0224852D01*
+X0148888Y0224919D01*
+X0148930Y0224985D01*
+X0148976Y0225048D01*
+X0149024Y0225108D01*
+X0149075Y0225166D01*
+X0149130Y0225222D01*
+X0149186Y0225275D01*
+X0149246Y0225325D01*
+X0149308Y0225371D01*
+X0149372Y0225415D01*
+X0149438Y0225456D01*
+X0149506Y0225493D01*
+X0149576Y0225526D01*
+X0149648Y0225556D01*
+X0149720Y0225583D01*
+X0149795Y0225606D01*
+X0149870Y0225625D01*
+X0149946Y0225640D01*
+X0150023Y0225652D01*
+X0150100Y0225660D01*
+X0150177Y0225664D01*
+X0150255Y0225664D01*
+X0150332Y0225660D01*
+X0150409Y0225652D01*
+X0150486Y0225640D01*
+X0150562Y0225625D01*
+X0150637Y0225606D01*
+X0150712Y0225583D01*
+X0150784Y0225556D01*
+X0150856Y0225526D01*
+X0150926Y0225493D01*
+X0150994Y0225456D01*
+X0151060Y0225415D01*
+X0151124Y0225371D01*
+X0151186Y0225325D01*
+X0151246Y0225275D01*
+X0151302Y0225222D01*
+X0151357Y0225166D01*
+X0151408Y0225108D01*
+X0151456Y0225048D01*
+X0151502Y0224985D01*
+X0151544Y0224919D01*
+X0151583Y0224852D01*
+X0151618Y0224783D01*
+X0151650Y0224712D01*
+X0151678Y0224640D01*
+X0151703Y0224567D01*
+X0151724Y0224492D01*
+X0151741Y0224416D01*
+X0151755Y0224340D01*
+X0151764Y0224263D01*
+X0151770Y0224186D01*
+X0151772Y0224108D01*
+X0145735Y0224497D02*
+X0145735Y0220997D01*
+X0143402Y0220997D02*
+X0143402Y0225663D01*
+X0144568Y0225663D02*
+X0141068Y0225663D01*
+X0141068Y0220997D01*
+X0144788Y0216597D02*
+X0144788Y0209597D01*
+X0142844Y0209597D01*
+X0142844Y0209596D02*
+X0142779Y0209598D01*
+X0142713Y0209603D01*
+X0142649Y0209612D01*
+X0142584Y0209625D01*
+X0142521Y0209642D01*
+X0142459Y0209661D01*
+X0142397Y0209685D01*
+X0142338Y0209712D01*
+X0142280Y0209742D01*
+X0142223Y0209775D01*
+X0142169Y0209811D01*
+X0142116Y0209851D01*
+X0142066Y0209893D01*
+X0142019Y0209938D01*
+X0141974Y0209985D01*
+X0141932Y0210035D01*
+X0141892Y0210088D01*
+X0141856Y0210142D01*
+X0141823Y0210199D01*
+X0141793Y0210257D01*
+X0141766Y0210316D01*
+X0141742Y0210378D01*
+X0141723Y0210440D01*
+X0141706Y0210503D01*
+X0141693Y0210568D01*
+X0141684Y0210632D01*
+X0141679Y0210698D01*
+X0141677Y0210763D01*
+X0141677Y0213097D01*
+X0141679Y0213162D01*
+X0141684Y0213228D01*
+X0141693Y0213292D01*
+X0141706Y0213357D01*
+X0141723Y0213420D01*
+X0141742Y0213482D01*
+X0141766Y0213544D01*
+X0141793Y0213603D01*
+X0141823Y0213661D01*
+X0141856Y0213718D01*
+X0141892Y0213772D01*
+X0141932Y0213825D01*
+X0141974Y0213875D01*
+X0142019Y0213922D01*
+X0142066Y0213967D01*
+X0142116Y0214009D01*
+X0142169Y0214049D01*
+X0142223Y0214085D01*
+X0142280Y0214118D01*
+X0142338Y0214148D01*
+X0142397Y0214175D01*
+X0142459Y0214199D01*
+X0142521Y0214218D01*
+X0142584Y0214235D01*
+X0142649Y0214248D01*
+X0142713Y0214257D01*
+X0142779Y0214262D01*
+X0142844Y0214264D01*
+X0142844Y0214263D02*
+X0144788Y0214263D01*
+X0151403Y0214263D02*
+X0153347Y0214263D01*
+X0153347Y0214264D02*
+X0153412Y0214262D01*
+X0153478Y0214257D01*
+X0153542Y0214248D01*
+X0153607Y0214235D01*
+X0153670Y0214218D01*
+X0153732Y0214199D01*
+X0153794Y0214175D01*
+X0153853Y0214148D01*
+X0153911Y0214118D01*
+X0153968Y0214085D01*
+X0154022Y0214049D01*
+X0154075Y0214009D01*
+X0154125Y0213967D01*
+X0154172Y0213922D01*
+X0154217Y0213875D01*
+X0154259Y0213825D01*
+X0154299Y0213772D01*
+X0154335Y0213718D01*
+X0154368Y0213661D01*
+X0154398Y0213603D01*
+X0154425Y0213544D01*
+X0154449Y0213482D01*
+X0154468Y0213420D01*
+X0154485Y0213357D01*
+X0154498Y0213292D01*
+X0154507Y0213228D01*
+X0154512Y0213162D01*
+X0154514Y0213097D01*
+X0154514Y0210763D01*
+X0154512Y0210695D01*
+X0154506Y0210628D01*
+X0154496Y0210560D01*
+X0154483Y0210494D01*
+X0154465Y0210428D01*
+X0154444Y0210364D01*
+X0154419Y0210301D01*
+X0154390Y0210239D01*
+X0154358Y0210179D01*
+X0154322Y0210122D01*
+X0154283Y0210066D01*
+X0154241Y0210013D01*
+X0154196Y0209962D01*
+X0154148Y0209914D01*
+X0154097Y0209869D01*
+X0154044Y0209827D01*
+X0153988Y0209788D01*
+X0153930Y0209752D01*
+X0153871Y0209720D01*
+X0153809Y0209691D01*
+X0153746Y0209666D01*
+X0153682Y0209645D01*
+X0153616Y0209627D01*
+X0153550Y0209614D01*
+X0153482Y0209604D01*
+X0153415Y0209598D01*
+X0153347Y0209596D01*
+X0153347Y0209597D02*
+X0151403Y0209597D01*
+X0151403Y0216597D01*
+X0156872Y0214263D02*
+X0158427Y0209597D01*
+X0157649Y0207263D02*
+X0159983Y0214263D01*
+X0157649Y0207263D02*
+X0156872Y0207263D01*
+X0139100Y0209597D02*
+X0137155Y0209597D01*
+X0137155Y0209596D02*
+X0137090Y0209598D01*
+X0137024Y0209603D01*
+X0136960Y0209612D01*
+X0136895Y0209625D01*
+X0136832Y0209642D01*
+X0136770Y0209661D01*
+X0136708Y0209685D01*
+X0136649Y0209712D01*
+X0136591Y0209742D01*
+X0136534Y0209775D01*
+X0136480Y0209811D01*
+X0136427Y0209851D01*
+X0136377Y0209893D01*
+X0136330Y0209938D01*
+X0136285Y0209985D01*
+X0136243Y0210035D01*
+X0136203Y0210088D01*
+X0136167Y0210142D01*
+X0136134Y0210199D01*
+X0136104Y0210257D01*
+X0136077Y0210316D01*
+X0136053Y0210378D01*
+X0136034Y0210440D01*
+X0136017Y0210503D01*
+X0136004Y0210568D01*
+X0135995Y0210632D01*
+X0135990Y0210698D01*
+X0135988Y0210763D01*
+X0135988Y0212708D01*
+X0135988Y0211930D02*
+X0139100Y0211930D01*
+X0139100Y0212708D01*
+X0139098Y0212786D01*
+X0139092Y0212863D01*
+X0139083Y0212940D01*
+X0139069Y0213016D01*
+X0139052Y0213092D01*
+X0139031Y0213167D01*
+X0139006Y0213240D01*
+X0138978Y0213312D01*
+X0138946Y0213383D01*
+X0138911Y0213452D01*
+X0138872Y0213519D01*
+X0138830Y0213585D01*
+X0138784Y0213648D01*
+X0138736Y0213708D01*
+X0138685Y0213766D01*
+X0138630Y0213822D01*
+X0138574Y0213875D01*
+X0138514Y0213925D01*
+X0138452Y0213971D01*
+X0138388Y0214015D01*
+X0138322Y0214056D01*
+X0138254Y0214093D01*
+X0138184Y0214126D01*
+X0138112Y0214156D01*
+X0138040Y0214183D01*
+X0137965Y0214206D01*
+X0137890Y0214225D01*
+X0137814Y0214240D01*
+X0137737Y0214252D01*
+X0137660Y0214260D01*
+X0137583Y0214264D01*
+X0137505Y0214264D01*
+X0137428Y0214260D01*
+X0137351Y0214252D01*
+X0137274Y0214240D01*
+X0137198Y0214225D01*
+X0137123Y0214206D01*
+X0137048Y0214183D01*
+X0136976Y0214156D01*
+X0136904Y0214126D01*
+X0136834Y0214093D01*
+X0136766Y0214056D01*
+X0136700Y0214015D01*
+X0136636Y0213971D01*
+X0136574Y0213925D01*
+X0136514Y0213875D01*
+X0136458Y0213822D01*
+X0136403Y0213766D01*
+X0136352Y0213708D01*
+X0136304Y0213648D01*
+X0136258Y0213585D01*
+X0136216Y0213519D01*
+X0136177Y0213452D01*
+X0136142Y0213383D01*
+X0136110Y0213312D01*
+X0136082Y0213240D01*
+X0136057Y0213167D01*
+X0136036Y0213092D01*
+X0136019Y0213016D01*
+X0136005Y0212940D01*
+X0135996Y0212863D01*
+X0135990Y0212786D01*
+X0135988Y0212708D01*
+X0133164Y0213097D02*
+X0133164Y0209597D01*
+X0130053Y0209597D02*
+X0130053Y0214263D01*
+X0131998Y0214263D01*
+X0131998Y0214264D02*
+X0132066Y0214262D01*
+X0132133Y0214256D01*
+X0132201Y0214246D01*
+X0132267Y0214233D01*
+X0132333Y0214215D01*
+X0132397Y0214194D01*
+X0132460Y0214169D01*
+X0132522Y0214140D01*
+X0132581Y0214108D01*
+X0132639Y0214072D01*
+X0132695Y0214033D01*
+X0132748Y0213991D01*
+X0132799Y0213946D01*
+X0132847Y0213898D01*
+X0132892Y0213847D01*
+X0132934Y0213794D01*
+X0132973Y0213738D01*
+X0133009Y0213681D01*
+X0133041Y0213621D01*
+X0133070Y0213559D01*
+X0133095Y0213496D01*
+X0133116Y0213432D01*
+X0133134Y0213366D01*
+X0133147Y0213300D01*
+X0133157Y0213232D01*
+X0133163Y0213165D01*
+X0133165Y0213097D01*
+X0126982Y0214263D02*
+X0126982Y0208430D01*
+X0126983Y0208430D02*
+X0126981Y0208362D01*
+X0126975Y0208295D01*
+X0126965Y0208227D01*
+X0126952Y0208161D01*
+X0126934Y0208095D01*
+X0126913Y0208031D01*
+X0126888Y0207968D01*
+X0126859Y0207906D01*
+X0126827Y0207847D01*
+X0126791Y0207789D01*
+X0126752Y0207733D01*
+X0126710Y0207680D01*
+X0126665Y0207629D01*
+X0126617Y0207581D01*
+X0126566Y0207536D01*
+X0126513Y0207494D01*
+X0126457Y0207455D01*
+X0126400Y0207419D01*
+X0126340Y0207387D01*
+X0126278Y0207358D01*
+X0126215Y0207333D01*
+X0126151Y0207312D01*
+X0126085Y0207294D01*
+X0126019Y0207281D01*
+X0125951Y0207271D01*
+X0125884Y0207265D01*
+X0125816Y0207263D01*
+X0124260Y0207263D01*
+X0125038Y0209597D02*
+X0126982Y0209597D01*
+X0125038Y0209596D02*
+X0124973Y0209598D01*
+X0124907Y0209603D01*
+X0124843Y0209612D01*
+X0124778Y0209625D01*
+X0124715Y0209642D01*
+X0124653Y0209661D01*
+X0124591Y0209685D01*
+X0124532Y0209712D01*
+X0124474Y0209742D01*
+X0124417Y0209775D01*
+X0124363Y0209811D01*
+X0124310Y0209851D01*
+X0124260Y0209893D01*
+X0124213Y0209938D01*
+X0124168Y0209985D01*
+X0124126Y0210035D01*
+X0124086Y0210088D01*
+X0124050Y0210142D01*
+X0124017Y0210199D01*
+X0123987Y0210257D01*
+X0123960Y0210316D01*
+X0123936Y0210378D01*
+X0123917Y0210440D01*
+X0123900Y0210503D01*
+X0123887Y0210568D01*
+X0123878Y0210632D01*
+X0123873Y0210698D01*
+X0123871Y0210763D01*
+X0123871Y0213097D01*
+X0123873Y0213162D01*
+X0123878Y0213228D01*
+X0123887Y0213292D01*
+X0123900Y0213357D01*
+X0123917Y0213420D01*
+X0123936Y0213482D01*
+X0123960Y0213544D01*
+X0123987Y0213603D01*
+X0124017Y0213661D01*
+X0124050Y0213718D01*
+X0124086Y0213772D01*
+X0124126Y0213825D01*
+X0124168Y0213875D01*
+X0124213Y0213922D01*
+X0124260Y0213967D01*
+X0124310Y0214009D01*
+X0124363Y0214049D01*
+X0124417Y0214085D01*
+X0124474Y0214118D01*
+X0124532Y0214148D01*
+X0124591Y0214175D01*
+X0124653Y0214199D01*
+X0124715Y0214218D01*
+X0124778Y0214235D01*
+X0124843Y0214248D01*
+X0124907Y0214257D01*
+X0124973Y0214262D01*
+X0125038Y0214264D01*
+X0125038Y0214263D02*
+X0126982Y0214263D01*
+X0121277Y0214263D02*
+X0121277Y0209597D01*
+X0117684Y0209597D02*
+X0117746Y0209598D01*
+X0117808Y0209603D01*
+X0117869Y0209612D01*
+X0117930Y0209624D01*
+X0117990Y0209640D01*
+X0118049Y0209660D01*
+X0118107Y0209684D01*
+X0118163Y0209710D01*
+X0118217Y0209741D01*
+X0118269Y0209774D01*
+X0118319Y0209811D01*
+X0118367Y0209851D01*
+X0118412Y0209894D01*
+X0118455Y0209939D01*
+X0118494Y0209987D01*
+X0118531Y0210037D01*
+X0118564Y0210090D01*
+X0118594Y0210144D01*
+X0118621Y0210200D01*
+X0118644Y0210258D01*
+X0118664Y0210317D01*
+X0118680Y0210377D01*
+X0118692Y0210438D01*
+X0118700Y0210499D01*
+X0118705Y0210561D01*
+X0118706Y0210624D01*
+X0118703Y0210686D01*
+X0118696Y0210747D01*
+X0118685Y0210809D01*
+X0118671Y0210869D01*
+X0118653Y0210929D01*
+X0118631Y0210987D01*
+X0118606Y0211044D01*
+X0118577Y0211099D01*
+X0118545Y0211152D01*
+X0118509Y0211203D01*
+X0118471Y0211252D01*
+X0118430Y0211298D01*
+X0118386Y0211342D01*
+X0118339Y0211383D01*
+X0118290Y0211421D01*
+X0118238Y0211456D01*
+X0118185Y0211488D01*
+X0118129Y0211516D01*
+X0118072Y0211541D01*
+X0118073Y0211541D02*
+X0116128Y0212319D01*
+X0116129Y0212319D02*
+X0116072Y0212344D01*
+X0116016Y0212372D01*
+X0115963Y0212404D01*
+X0115911Y0212439D01*
+X0115862Y0212477D01*
+X0115815Y0212518D01*
+X0115771Y0212562D01*
+X0115730Y0212608D01*
+X0115692Y0212657D01*
+X0115656Y0212708D01*
+X0115624Y0212761D01*
+X0115595Y0212816D01*
+X0115570Y0212873D01*
+X0115548Y0212931D01*
+X0115530Y0212991D01*
+X0115516Y0213051D01*
+X0115505Y0213113D01*
+X0115498Y0213174D01*
+X0115495Y0213236D01*
+X0115496Y0213299D01*
+X0115501Y0213361D01*
+X0115509Y0213422D01*
+X0115521Y0213483D01*
+X0115537Y0213543D01*
+X0115557Y0213602D01*
+X0115580Y0213660D01*
+X0115607Y0213716D01*
+X0115637Y0213770D01*
+X0115670Y0213823D01*
+X0115707Y0213873D01*
+X0115746Y0213921D01*
+X0115789Y0213966D01*
+X0115834Y0214009D01*
+X0115882Y0214049D01*
+X0115932Y0214086D01*
+X0115984Y0214119D01*
+X0116038Y0214150D01*
+X0116094Y0214176D01*
+X0116152Y0214200D01*
+X0116211Y0214220D01*
+X0116271Y0214236D01*
+X0116332Y0214248D01*
+X0116393Y0214257D01*
+X0116455Y0214262D01*
+X0116517Y0214263D01*
+X0115545Y0209986D02*
+X0115692Y0209934D01*
+X0115841Y0209887D01*
+X0115990Y0209843D01*
+X0116141Y0209802D01*
+X0116293Y0209765D01*
+X0116445Y0209732D01*
+X0116598Y0209702D01*
+X0116752Y0209676D01*
+X0116906Y0209654D01*
+X0117061Y0209635D01*
+X0117216Y0209620D01*
+X0117372Y0209609D01*
+X0117528Y0209601D01*
+X0117684Y0209597D01*
+X0118267Y0213874D02*
+X0118149Y0213925D01*
+X0118029Y0213973D01*
+X0117908Y0214017D01*
+X0117785Y0214058D01*
+X0117662Y0214095D01*
+X0117537Y0214128D01*
+X0117412Y0214158D01*
+X0117286Y0214184D01*
+X0117159Y0214206D01*
+X0117031Y0214225D01*
+X0116903Y0214240D01*
+X0116775Y0214251D01*
+X0116646Y0214259D01*
+X0116517Y0214263D01*
+X0112941Y0212708D02*
+X0112941Y0211930D01*
+X0109830Y0211930D01*
+X0109830Y0212708D02*
+X0109830Y0210763D01*
+X0109829Y0210763D02*
+X0109831Y0210698D01*
+X0109836Y0210632D01*
+X0109845Y0210568D01*
+X0109858Y0210503D01*
+X0109875Y0210440D01*
+X0109894Y0210378D01*
+X0109918Y0210316D01*
+X0109945Y0210257D01*
+X0109975Y0210199D01*
+X0110008Y0210142D01*
+X0110044Y0210088D01*
+X0110084Y0210035D01*
+X0110126Y0209985D01*
+X0110171Y0209938D01*
+X0110218Y0209893D01*
+X0110268Y0209851D01*
+X0110321Y0209811D01*
+X0110375Y0209775D01*
+X0110432Y0209742D01*
+X0110490Y0209712D01*
+X0110549Y0209685D01*
+X0110611Y0209661D01*
+X0110673Y0209642D01*
+X0110736Y0209625D01*
+X0110801Y0209612D01*
+X0110865Y0209603D01*
+X0110931Y0209598D01*
+X0110996Y0209596D01*
+X0110996Y0209597D02*
+X0112941Y0209597D01*
+X0112941Y0212708D02*
+X0112939Y0212786D01*
+X0112933Y0212863D01*
+X0112924Y0212940D01*
+X0112910Y0213016D01*
+X0112893Y0213092D01*
+X0112872Y0213167D01*
+X0112847Y0213240D01*
+X0112819Y0213312D01*
+X0112787Y0213383D01*
+X0112752Y0213452D01*
+X0112713Y0213519D01*
+X0112671Y0213585D01*
+X0112625Y0213648D01*
+X0112577Y0213708D01*
+X0112526Y0213766D01*
+X0112471Y0213822D01*
+X0112415Y0213875D01*
+X0112355Y0213925D01*
+X0112293Y0213971D01*
+X0112229Y0214015D01*
+X0112163Y0214056D01*
+X0112095Y0214093D01*
+X0112025Y0214126D01*
+X0111953Y0214156D01*
+X0111881Y0214183D01*
+X0111806Y0214206D01*
+X0111731Y0214225D01*
+X0111655Y0214240D01*
+X0111578Y0214252D01*
+X0111501Y0214260D01*
+X0111424Y0214264D01*
+X0111346Y0214264D01*
+X0111269Y0214260D01*
+X0111192Y0214252D01*
+X0111115Y0214240D01*
+X0111039Y0214225D01*
+X0110964Y0214206D01*
+X0110889Y0214183D01*
+X0110817Y0214156D01*
+X0110745Y0214126D01*
+X0110675Y0214093D01*
+X0110607Y0214056D01*
+X0110541Y0214015D01*
+X0110477Y0213971D01*
+X0110415Y0213925D01*
+X0110355Y0213875D01*
+X0110299Y0213822D01*
+X0110244Y0213766D01*
+X0110193Y0213708D01*
+X0110145Y0213648D01*
+X0110099Y0213585D01*
+X0110057Y0213519D01*
+X0110018Y0213452D01*
+X0109983Y0213383D01*
+X0109951Y0213312D01*
+X0109923Y0213240D01*
+X0109898Y0213167D01*
+X0109877Y0213092D01*
+X0109860Y0213016D01*
+X0109846Y0212940D01*
+X0109837Y0212863D01*
+X0109831Y0212786D01*
+X0109829Y0212708D01*
+X0106979Y0214263D02*
+X0105034Y0214263D01*
+X0105034Y0214264D02*
+X0104969Y0214262D01*
+X0104903Y0214257D01*
+X0104839Y0214248D01*
+X0104774Y0214235D01*
+X0104711Y0214218D01*
+X0104649Y0214199D01*
+X0104587Y0214175D01*
+X0104528Y0214148D01*
+X0104470Y0214118D01*
+X0104413Y0214085D01*
+X0104359Y0214049D01*
+X0104306Y0214009D01*
+X0104256Y0213967D01*
+X0104209Y0213922D01*
+X0104164Y0213875D01*
+X0104122Y0213825D01*
+X0104082Y0213772D01*
+X0104046Y0213718D01*
+X0104013Y0213661D01*
+X0103983Y0213603D01*
+X0103956Y0213544D01*
+X0103932Y0213482D01*
+X0103913Y0213420D01*
+X0103896Y0213357D01*
+X0103883Y0213292D01*
+X0103874Y0213228D01*
+X0103869Y0213162D01*
+X0103867Y0213097D01*
+X0103868Y0213097D02*
+X0103868Y0210763D01*
+X0103867Y0210763D02*
+X0103869Y0210698D01*
+X0103874Y0210632D01*
+X0103883Y0210568D01*
+X0103896Y0210503D01*
+X0103913Y0210440D01*
+X0103932Y0210378D01*
+X0103956Y0210316D01*
+X0103983Y0210257D01*
+X0104013Y0210199D01*
+X0104046Y0210142D01*
+X0104082Y0210088D01*
+X0104122Y0210035D01*
+X0104164Y0209985D01*
+X0104209Y0209938D01*
+X0104256Y0209893D01*
+X0104306Y0209851D01*
+X0104359Y0209811D01*
+X0104413Y0209775D01*
+X0104470Y0209742D01*
+X0104528Y0209712D01*
+X0104587Y0209685D01*
+X0104649Y0209661D01*
+X0104711Y0209642D01*
+X0104774Y0209625D01*
+X0104839Y0209612D01*
+X0104903Y0209603D01*
+X0104969Y0209598D01*
+X0105034Y0209596D01*
+X0105034Y0209597D02*
+X0106979Y0209597D01*
+X0106979Y0216597D01*
+X0107756Y0220997D02*
+X0107756Y0227997D01*
+X0110979Y0227997D02*
+X0112924Y0227997D01*
+X0110979Y0227997D02*
+X0110979Y0220997D01*
+X0110979Y0224108D02*
+X0112924Y0224108D01*
+X0113011Y0224110D01*
+X0113098Y0224116D01*
+X0113185Y0224126D01*
+X0113271Y0224139D01*
+X0113357Y0224157D01*
+X0113441Y0224178D01*
+X0113525Y0224203D01*
+X0113607Y0224232D01*
+X0113688Y0224264D01*
+X0113767Y0224301D01*
+X0113845Y0224340D01*
+X0113921Y0224383D01*
+X0113995Y0224430D01*
+X0114067Y0224479D01*
+X0114136Y0224532D01*
+X0114203Y0224588D01*
+X0114267Y0224647D01*
+X0114329Y0224709D01*
+X0114388Y0224773D01*
+X0114444Y0224840D01*
+X0114497Y0224909D01*
+X0114546Y0224981D01*
+X0114593Y0225055D01*
+X0114636Y0225131D01*
+X0114675Y0225209D01*
+X0114712Y0225288D01*
+X0114744Y0225369D01*
+X0114773Y0225451D01*
+X0114798Y0225535D01*
+X0114819Y0225619D01*
+X0114837Y0225705D01*
+X0114850Y0225791D01*
+X0114860Y0225878D01*
+X0114866Y0225965D01*
+X0114868Y0226052D01*
+X0114866Y0226139D01*
+X0114860Y0226226D01*
+X0114850Y0226313D01*
+X0114837Y0226399D01*
+X0114819Y0226485D01*
+X0114798Y0226569D01*
+X0114773Y0226653D01*
+X0114744Y0226735D01*
+X0114712Y0226816D01*
+X0114675Y0226895D01*
+X0114636Y0226973D01*
+X0114593Y0227049D01*
+X0114546Y0227123D01*
+X0114497Y0227195D01*
+X0114444Y0227264D01*
+X0114388Y0227331D01*
+X0114329Y0227395D01*
+X0114267Y0227457D01*
+X0114203Y0227516D01*
+X0114136Y0227572D01*
+X0114067Y0227625D01*
+X0113995Y0227674D01*
+X0113921Y0227721D01*
+X0113845Y0227764D01*
+X0113767Y0227803D01*
+X0113688Y0227840D01*
+X0113607Y0227872D01*
+X0113525Y0227901D01*
+X0113441Y0227926D01*
+X0113357Y0227947D01*
+X0113271Y0227965D01*
+X0113185Y0227978D01*
+X0113098Y0227988D01*
+X0113011Y0227994D01*
+X0112924Y0227996D01*
+X0117530Y0227997D02*
+X0119475Y0227997D01*
+X0119475Y0227996D02*
+X0119562Y0227994D01*
+X0119649Y0227988D01*
+X0119736Y0227978D01*
+X0119822Y0227965D01*
+X0119908Y0227947D01*
+X0119992Y0227926D01*
+X0120076Y0227901D01*
+X0120158Y0227872D01*
+X0120239Y0227840D01*
+X0120318Y0227803D01*
+X0120396Y0227764D01*
+X0120472Y0227721D01*
+X0120546Y0227674D01*
+X0120618Y0227625D01*
+X0120687Y0227572D01*
+X0120754Y0227516D01*
+X0120818Y0227457D01*
+X0120880Y0227395D01*
+X0120939Y0227331D01*
+X0120995Y0227264D01*
+X0121048Y0227195D01*
+X0121097Y0227123D01*
+X0121144Y0227049D01*
+X0121187Y0226973D01*
+X0121226Y0226895D01*
+X0121263Y0226816D01*
+X0121295Y0226735D01*
+X0121324Y0226653D01*
+X0121349Y0226569D01*
+X0121370Y0226485D01*
+X0121388Y0226399D01*
+X0121401Y0226313D01*
+X0121411Y0226226D01*
+X0121417Y0226139D01*
+X0121419Y0226052D01*
+X0121417Y0225965D01*
+X0121411Y0225878D01*
+X0121401Y0225791D01*
+X0121388Y0225705D01*
+X0121370Y0225619D01*
+X0121349Y0225535D01*
+X0121324Y0225451D01*
+X0121295Y0225369D01*
+X0121263Y0225288D01*
+X0121226Y0225209D01*
+X0121187Y0225131D01*
+X0121144Y0225055D01*
+X0121097Y0224981D01*
+X0121048Y0224909D01*
+X0120995Y0224840D01*
+X0120939Y0224773D01*
+X0120880Y0224709D01*
+X0120818Y0224647D01*
+X0120754Y0224588D01*
+X0120687Y0224532D01*
+X0120618Y0224479D01*
+X0120546Y0224430D01*
+X0120472Y0224383D01*
+X0120396Y0224340D01*
+X0120318Y0224301D01*
+X0120239Y0224264D01*
+X0120158Y0224232D01*
+X0120076Y0224203D01*
+X0119992Y0224178D01*
+X0119908Y0224157D01*
+X0119822Y0224139D01*
+X0119736Y0224126D01*
+X0119649Y0224116D01*
+X0119562Y0224110D01*
+X0119475Y0224108D01*
+X0117530Y0224108D01*
+X0119863Y0224108D02*
+X0121419Y0220997D01*
+X0117530Y0220997D02*
+X0117530Y0227997D01*
+X0124091Y0227997D02*
+X0127980Y0227997D01*
+X0126036Y0220997D01*
+X0131075Y0222552D02*
+X0134186Y0226441D01*
+X0133991Y0227025D02*
+X0133965Y0227094D01*
+X0133936Y0227163D01*
+X0133903Y0227229D01*
+X0133866Y0227294D01*
+X0133827Y0227357D01*
+X0133784Y0227418D01*
+X0133738Y0227476D01*
+X0133689Y0227532D01*
+X0133637Y0227586D01*
+X0133583Y0227636D01*
+X0133526Y0227684D01*
+X0133466Y0227729D01*
+X0133405Y0227771D01*
+X0133341Y0227809D01*
+X0133276Y0227844D01*
+X0133208Y0227876D01*
+X0133139Y0227904D01*
+X0133069Y0227928D01*
+X0132998Y0227949D01*
+X0132925Y0227966D01*
+X0132852Y0227980D01*
+X0132778Y0227989D01*
+X0132704Y0227995D01*
+X0132630Y0227997D01*
+X0132556Y0227995D01*
+X0132482Y0227989D01*
+X0132408Y0227980D01*
+X0132335Y0227966D01*
+X0132262Y0227949D01*
+X0132191Y0227928D01*
+X0132121Y0227904D01*
+X0132052Y0227876D01*
+X0131984Y0227844D01*
+X0131919Y0227809D01*
+X0131855Y0227771D01*
+X0131794Y0227729D01*
+X0131734Y0227684D01*
+X0131677Y0227636D01*
+X0131623Y0227586D01*
+X0131571Y0227532D01*
+X0131522Y0227476D01*
+X0131476Y0227418D01*
+X0131433Y0227357D01*
+X0131394Y0227294D01*
+X0131357Y0227229D01*
+X0131324Y0227163D01*
+X0131295Y0227094D01*
+X0131269Y0227025D01*
+X0133991Y0227025D02*
+X0134053Y0226893D01*
+X0134111Y0226760D01*
+X0134167Y0226626D01*
+X0134219Y0226490D01*
+X0134267Y0226353D01*
+X0134312Y0226215D01*
+X0134354Y0226075D01*
+X0134392Y0225935D01*
+X0134426Y0225794D01*
+X0134457Y0225652D01*
+X0134484Y0225509D01*
+X0134508Y0225366D01*
+X0134528Y0225222D01*
+X0134545Y0225077D01*
+X0134558Y0224933D01*
+X0134567Y0224788D01*
+X0134572Y0224642D01*
+X0134574Y0224497D01*
+X0130686Y0224497D02*
+X0130688Y0224642D01*
+X0130693Y0224788D01*
+X0130702Y0224933D01*
+X0130715Y0225077D01*
+X0130732Y0225222D01*
+X0130752Y0225366D01*
+X0130776Y0225509D01*
+X0130803Y0225652D01*
+X0130834Y0225794D01*
+X0130868Y0225935D01*
+X0130906Y0226075D01*
+X0130948Y0226215D01*
+X0130993Y0226353D01*
+X0131041Y0226490D01*
+X0131093Y0226626D01*
+X0131149Y0226760D01*
+X0131207Y0226893D01*
+X0131269Y0227025D01*
+X0134575Y0224497D02*
+X0134573Y0224352D01*
+X0134568Y0224206D01*
+X0134559Y0224061D01*
+X0134546Y0223916D01*
+X0134529Y0223772D01*
+X0134509Y0223628D01*
+X0134485Y0223485D01*
+X0134458Y0223342D01*
+X0134427Y0223200D01*
+X0134393Y0223059D01*
+X0134355Y0222918D01*
+X0134313Y0222779D01*
+X0134268Y0222641D01*
+X0134220Y0222504D01*
+X0134168Y0222368D01*
+X0134112Y0222233D01*
+X0134054Y0222100D01*
+X0133992Y0221969D01*
+X0133991Y0221969D02*
+X0133965Y0221900D01*
+X0133936Y0221831D01*
+X0133903Y0221765D01*
+X0133866Y0221700D01*
+X0133827Y0221637D01*
+X0133784Y0221576D01*
+X0133738Y0221518D01*
+X0133689Y0221462D01*
+X0133637Y0221408D01*
+X0133583Y0221358D01*
+X0133526Y0221310D01*
+X0133466Y0221265D01*
+X0133405Y0221223D01*
+X0133341Y0221185D01*
+X0133276Y0221150D01*
+X0133208Y0221118D01*
+X0133139Y0221090D01*
+X0133069Y0221066D01*
+X0132998Y0221045D01*
+X0132925Y0221028D01*
+X0132852Y0221014D01*
+X0132778Y0221005D01*
+X0132704Y0220999D01*
+X0132630Y0220997D01*
+X0132556Y0220999D01*
+X0132482Y0221005D01*
+X0132408Y0221014D01*
+X0132335Y0221028D01*
+X0132262Y0221045D01*
+X0132191Y0221066D01*
+X0132121Y0221090D01*
+X0132052Y0221118D01*
+X0131984Y0221150D01*
+X0131919Y0221185D01*
+X0131855Y0221223D01*
+X0131794Y0221265D01*
+X0131734Y0221310D01*
+X0131677Y0221358D01*
+X0131623Y0221408D01*
+X0131571Y0221462D01*
+X0131522Y0221518D01*
+X0131476Y0221576D01*
+X0131433Y0221637D01*
+X0131394Y0221700D01*
+X0131357Y0221765D01*
+X0131324Y0221831D01*
+X0131295Y0221900D01*
+X0131269Y0221969D01*
+X0131268Y0221969D02*
+X0131206Y0222100D01*
+X0131148Y0222233D01*
+X0131092Y0222368D01*
+X0131040Y0222504D01*
+X0130992Y0222641D01*
+X0130947Y0222779D01*
+X0130905Y0222918D01*
+X0130867Y0223059D01*
+X0130833Y0223200D01*
+X0130802Y0223342D01*
+X0130775Y0223485D01*
+X0130751Y0223628D01*
+X0130731Y0223772D01*
+X0130714Y0223916D01*
+X0130701Y0224061D01*
+X0130692Y0224206D01*
+X0130687Y0224352D01*
+X0130685Y0224497D01*
+X0124091Y0227219D02*
+X0124091Y0227997D01*
+X0121472Y0216597D02*
+X0121472Y0216208D01*
+X0121083Y0216208D01*
+X0121083Y0216597D01*
+X0121472Y0216597D01*
+X0107756Y0220997D02*
+X0103868Y0227997D01*
+X0103868Y0220997D01*
+X0086239Y0199961D02*
+X0086239Y0195694D01*
+X0084106Y0197828D02*
+X0088372Y0197828D01*
+X0077965Y0195339D02*
+X0077965Y0201739D01*
+X0074410Y0201739D02*
+X0077965Y0195339D01*
+X0074410Y0195339D02*
+X0074410Y0201739D01*
+X0071770Y0201739D02*
+X0070348Y0201739D01*
+X0071059Y0201739D02*
+X0071059Y0195339D01*
+X0070348Y0195339D02*
+X0071770Y0195339D01*
+X0039160Y0197828D02*
+X0034893Y0197828D01*
+X0028753Y0195339D02*
+X0028753Y0201739D01*
+X0025197Y0201739D02*
+X0028753Y0195339D01*
+X0025197Y0195339D02*
+X0025197Y0201739D01*
+X0022558Y0201739D02*
+X0021135Y0201739D01*
+X0021847Y0201739D02*
+X0021847Y0195339D01*
+X0022558Y0195339D02*
+X0021135Y0195339D01*
+X0038350Y0236086D02*
+X0042617Y0236086D01*
+X0064600Y0236086D02*
+X0068867Y0236086D01*
+X0066733Y0233952D02*
+X0066733Y0238219D01*
+X0072800Y0262547D02*
+X0071800Y0263547D01*
+X0071800Y0275047D01*
+X0072800Y0262547D02*
+X0110800Y0262547D01*
+X0111800Y0263547D01*
+X0111800Y0275047D01*
+X0144568Y0225664D02*
+X0144633Y0225662D01*
+X0144699Y0225657D01*
+X0144763Y0225648D01*
+X0144828Y0225635D01*
+X0144891Y0225618D01*
+X0144953Y0225599D01*
+X0145015Y0225575D01*
+X0145074Y0225548D01*
+X0145132Y0225518D01*
+X0145189Y0225485D01*
+X0145243Y0225449D01*
+X0145296Y0225409D01*
+X0145346Y0225367D01*
+X0145393Y0225322D01*
+X0145438Y0225275D01*
+X0145480Y0225225D01*
+X0145520Y0225172D01*
+X0145556Y0225118D01*
+X0145589Y0225061D01*
+X0145619Y0225003D01*
+X0145646Y0224944D01*
+X0145670Y0224882D01*
+X0145689Y0224820D01*
+X0145706Y0224757D01*
+X0145719Y0224692D01*
+X0145728Y0224628D01*
+X0145733Y0224562D01*
+X0145735Y0224497D01*
+X0177237Y0225663D02*
+X0178793Y0220997D01*
+X0180348Y0225663D01*
+X0186673Y0224497D02*
+X0186671Y0224352D01*
+X0186666Y0224206D01*
+X0186657Y0224061D01*
+X0186644Y0223916D01*
+X0186627Y0223772D01*
+X0186607Y0223628D01*
+X0186583Y0223485D01*
+X0186556Y0223342D01*
+X0186525Y0223200D01*
+X0186491Y0223059D01*
+X0186453Y0222918D01*
+X0186411Y0222779D01*
+X0186366Y0222641D01*
+X0186318Y0222504D01*
+X0186266Y0222368D01*
+X0186210Y0222233D01*
+X0186152Y0222100D01*
+X0186090Y0221969D01*
+X0186089Y0221969D02*
+X0186063Y0221900D01*
+X0186034Y0221831D01*
+X0186001Y0221765D01*
+X0185964Y0221700D01*
+X0185925Y0221637D01*
+X0185882Y0221576D01*
+X0185836Y0221518D01*
+X0185787Y0221462D01*
+X0185735Y0221408D01*
+X0185681Y0221358D01*
+X0185624Y0221310D01*
+X0185564Y0221265D01*
+X0185503Y0221223D01*
+X0185439Y0221185D01*
+X0185374Y0221150D01*
+X0185306Y0221118D01*
+X0185237Y0221090D01*
+X0185167Y0221066D01*
+X0185096Y0221045D01*
+X0185023Y0221028D01*
+X0184950Y0221014D01*
+X0184876Y0221005D01*
+X0184802Y0220999D01*
+X0184728Y0220997D01*
+X0184654Y0220999D01*
+X0184580Y0221005D01*
+X0184506Y0221014D01*
+X0184433Y0221028D01*
+X0184360Y0221045D01*
+X0184289Y0221066D01*
+X0184219Y0221090D01*
+X0184150Y0221118D01*
+X0184082Y0221150D01*
+X0184017Y0221185D01*
+X0183953Y0221223D01*
+X0183892Y0221265D01*
+X0183832Y0221310D01*
+X0183775Y0221358D01*
+X0183721Y0221408D01*
+X0183669Y0221462D01*
+X0183620Y0221518D01*
+X0183574Y0221576D01*
+X0183531Y0221637D01*
+X0183492Y0221700D01*
+X0183455Y0221765D01*
+X0183422Y0221831D01*
+X0183393Y0221900D01*
+X0183367Y0221969D01*
+X0183173Y0222552D02*
+X0186284Y0226441D01*
+X0186089Y0227025D02*
+X0186063Y0227094D01*
+X0186034Y0227163D01*
+X0186001Y0227229D01*
+X0185964Y0227294D01*
+X0185925Y0227357D01*
+X0185882Y0227418D01*
+X0185836Y0227476D01*
+X0185787Y0227532D01*
+X0185735Y0227586D01*
+X0185681Y0227636D01*
+X0185624Y0227684D01*
+X0185564Y0227729D01*
+X0185503Y0227771D01*
+X0185439Y0227809D01*
+X0185374Y0227844D01*
+X0185306Y0227876D01*
+X0185237Y0227904D01*
+X0185167Y0227928D01*
+X0185096Y0227949D01*
+X0185023Y0227966D01*
+X0184950Y0227980D01*
+X0184876Y0227989D01*
+X0184802Y0227995D01*
+X0184728Y0227997D01*
+X0184654Y0227995D01*
+X0184580Y0227989D01*
+X0184506Y0227980D01*
+X0184433Y0227966D01*
+X0184360Y0227949D01*
+X0184289Y0227928D01*
+X0184219Y0227904D01*
+X0184150Y0227876D01*
+X0184082Y0227844D01*
+X0184017Y0227809D01*
+X0183953Y0227771D01*
+X0183892Y0227729D01*
+X0183832Y0227684D01*
+X0183775Y0227636D01*
+X0183721Y0227586D01*
+X0183669Y0227532D01*
+X0183620Y0227476D01*
+X0183574Y0227418D01*
+X0183531Y0227357D01*
+X0183492Y0227294D01*
+X0183455Y0227229D01*
+X0183422Y0227163D01*
+X0183393Y0227094D01*
+X0183367Y0227025D01*
+X0186089Y0227025D02*
+X0186151Y0226893D01*
+X0186209Y0226760D01*
+X0186265Y0226626D01*
+X0186317Y0226490D01*
+X0186365Y0226353D01*
+X0186410Y0226215D01*
+X0186452Y0226075D01*
+X0186490Y0225935D01*
+X0186524Y0225794D01*
+X0186555Y0225652D01*
+X0186582Y0225509D01*
+X0186606Y0225366D01*
+X0186626Y0225222D01*
+X0186643Y0225077D01*
+X0186656Y0224933D01*
+X0186665Y0224788D01*
+X0186670Y0224642D01*
+X0186672Y0224497D01*
+X0182784Y0224497D02*
+X0182786Y0224642D01*
+X0182791Y0224788D01*
+X0182800Y0224933D01*
+X0182813Y0225077D01*
+X0182830Y0225222D01*
+X0182850Y0225366D01*
+X0182874Y0225509D01*
+X0182901Y0225652D01*
+X0182932Y0225794D01*
+X0182966Y0225935D01*
+X0183004Y0226075D01*
+X0183046Y0226215D01*
+X0183091Y0226353D01*
+X0183139Y0226490D01*
+X0183191Y0226626D01*
+X0183247Y0226760D01*
+X0183305Y0226893D01*
+X0183367Y0227025D01*
+X0182783Y0224497D02*
+X0182785Y0224352D01*
+X0182790Y0224206D01*
+X0182799Y0224061D01*
+X0182812Y0223916D01*
+X0182829Y0223772D01*
+X0182849Y0223628D01*
+X0182873Y0223485D01*
+X0182900Y0223342D01*
+X0182931Y0223200D01*
+X0182965Y0223059D01*
+X0183003Y0222918D01*
+X0183045Y0222779D01*
+X0183090Y0222641D01*
+X0183138Y0222504D01*
+X0183190Y0222368D01*
+X0183246Y0222233D01*
+X0183304Y0222100D01*
+X0183366Y0221969D01*
+X0189378Y0220997D02*
+X0191712Y0220997D01*
+X0191712Y0220996D02*
+X0191788Y0220998D01*
+X0191865Y0221003D01*
+X0191940Y0221013D01*
+X0192016Y0221026D01*
+X0192090Y0221043D01*
+X0192164Y0221063D01*
+X0192236Y0221087D01*
+X0192307Y0221114D01*
+X0192377Y0221145D01*
+X0192445Y0221180D01*
+X0192512Y0221217D01*
+X0192576Y0221258D01*
+X0192639Y0221302D01*
+X0192699Y0221349D01*
+X0192757Y0221399D01*
+X0192812Y0221452D01*
+X0192865Y0221507D01*
+X0192915Y0221565D01*
+X0192962Y0221625D01*
+X0193006Y0221688D01*
+X0193047Y0221752D01*
+X0193084Y0221819D01*
+X0193119Y0221887D01*
+X0193150Y0221957D01*
+X0193177Y0222028D01*
+X0193201Y0222100D01*
+X0193221Y0222174D01*
+X0193238Y0222248D01*
+X0193251Y0222324D01*
+X0193261Y0222399D01*
+X0193266Y0222476D01*
+X0193268Y0222552D01*
+X0193267Y0222552D02*
+X0193267Y0223330D01*
+X0193268Y0223330D02*
+X0193266Y0223406D01*
+X0193261Y0223483D01*
+X0193251Y0223558D01*
+X0193238Y0223634D01*
+X0193221Y0223708D01*
+X0193201Y0223782D01*
+X0193177Y0223854D01*
+X0193150Y0223925D01*
+X0193119Y0223995D01*
+X0193084Y0224063D01*
+X0193047Y0224130D01*
+X0193006Y0224194D01*
+X0192962Y0224257D01*
+X0192915Y0224317D01*
+X0192865Y0224375D01*
+X0192812Y0224430D01*
+X0192757Y0224483D01*
+X0192699Y0224533D01*
+X0192639Y0224580D01*
+X0192576Y0224624D01*
+X0192512Y0224665D01*
+X0192445Y0224702D01*
+X0192377Y0224737D01*
+X0192307Y0224768D01*
+X0192236Y0224795D01*
+X0192164Y0224819D01*
+X0192090Y0224839D01*
+X0192016Y0224856D01*
+X0191940Y0224869D01*
+X0191865Y0224879D01*
+X0191788Y0224884D01*
+X0191712Y0224886D01*
+X0189378Y0224886D01*
+X0189378Y0227997D01*
+X0193267Y0227997D01*
+X0191800Y0231897D02*
+X0191800Y0234597D01*
+X0185300Y0234597D01*
+X0185300Y0239797D01*
+X0181800Y0239797D01*
+X0181800Y0234597D01*
+X0185300Y0234597D01*
+X0181800Y0239797D02*
+X0181800Y0245797D01*
+X0181800Y0250797D01*
+X0181800Y0256797D01*
+X0185300Y0256797D01*
+X0185300Y0262097D01*
+X0181800Y0262097D01*
+X0181800Y0256797D01*
+X0181800Y0250797D02*
+X0185300Y0250797D01*
+X0185300Y0245797D01*
+X0181800Y0245797D01*
+X0187600Y0245297D02*
+X0189100Y0246497D01*
+X0189100Y0241097D01*
+X0187600Y0241097D02*
+X0190600Y0241097D01*
+X0195100Y0239097D02*
+X0196800Y0235797D01*
+X0196800Y0236797D01*
+X0196800Y0235797D02*
+X0198500Y0239097D01*
+X0195100Y0239097D01*
+X0191800Y0234597D02*
+X0241800Y0234597D01*
+X0248300Y0234597D01*
+X0251700Y0234597D01*
+X0251700Y0239797D01*
+X0251700Y0245797D01*
+X0251700Y0250797D01*
+X0251700Y0256797D01*
+X0251700Y0262097D01*
+X0248300Y0262097D01*
+X0241800Y0262097D01*
+X0191800Y0262097D01*
+X0185300Y0262097D01*
+X0191800Y0262097D02*
+X0191800Y0285797D01*
+X0206800Y0280797D01*
+X0216800Y0285797D01*
+X0231800Y0280797D01*
+X0241800Y0285797D01*
+X0241800Y0262097D01*
+X0248300Y0262097D02*
+X0248300Y0256797D01*
+X0251700Y0256797D01*
+X0251700Y0250797D02*
+X0248300Y0250797D01*
+X0248300Y0245797D01*
+X0251700Y0245797D01*
+X0251700Y0239797D02*
+X0248300Y0239797D01*
+X0248300Y0234597D01*
+X0241800Y0234597D02*
+X0241800Y0231897D01*
+X0191800Y0231897D01*
+X0157050Y0139547D02*
+X0157054Y0139878D01*
+X0157066Y0140209D01*
+X0157087Y0140540D01*
+X0157115Y0140870D01*
+X0157152Y0141200D01*
+X0157196Y0141528D01*
+X0157249Y0141855D01*
+X0157309Y0142181D01*
+X0157378Y0142505D01*
+X0157455Y0142827D01*
+X0157539Y0143148D01*
+X0157631Y0143466D01*
+X0157731Y0143782D01*
+X0157839Y0144095D01*
+X0157955Y0144406D01*
+X0158078Y0144713D01*
+X0158208Y0145018D01*
+X0158346Y0145319D01*
+X0158491Y0145617D01*
+X0158644Y0145911D01*
+X0158804Y0146201D01*
+X0158971Y0146487D01*
+X0159144Y0146769D01*
+X0159325Y0147047D01*
+X0159513Y0147320D01*
+X0159707Y0147589D01*
+X0159907Y0147853D01*
+X0160114Y0148111D01*
+X0160328Y0148365D01*
+X0160547Y0148613D01*
+X0160773Y0148856D01*
+X0161004Y0149093D01*
+X0161241Y0149324D01*
+X0161484Y0149550D01*
+X0161732Y0149769D01*
+X0161986Y0149983D01*
+X0162244Y0150190D01*
+X0162508Y0150390D01*
+X0162777Y0150584D01*
+X0163050Y0150772D01*
+X0163328Y0150953D01*
+X0163610Y0151126D01*
+X0163896Y0151293D01*
+X0164186Y0151453D01*
+X0164480Y0151606D01*
+X0164778Y0151751D01*
+X0165079Y0151889D01*
+X0165384Y0152019D01*
+X0165691Y0152142D01*
+X0166002Y0152258D01*
+X0166315Y0152366D01*
+X0166631Y0152466D01*
+X0166949Y0152558D01*
+X0167270Y0152642D01*
+X0167592Y0152719D01*
+X0167916Y0152788D01*
+X0168242Y0152848D01*
+X0168569Y0152901D01*
+X0168897Y0152945D01*
+X0169227Y0152982D01*
+X0169557Y0153010D01*
+X0169888Y0153031D01*
+X0170219Y0153043D01*
+X0170550Y0153047D01*
+X0170881Y0153043D01*
+X0171212Y0153031D01*
+X0171543Y0153010D01*
+X0171873Y0152982D01*
+X0172203Y0152945D01*
+X0172531Y0152901D01*
+X0172858Y0152848D01*
+X0173184Y0152788D01*
+X0173508Y0152719D01*
+X0173830Y0152642D01*
+X0174151Y0152558D01*
+X0174469Y0152466D01*
+X0174785Y0152366D01*
+X0175098Y0152258D01*
+X0175409Y0152142D01*
+X0175716Y0152019D01*
+X0176021Y0151889D01*
+X0176322Y0151751D01*
+X0176620Y0151606D01*
+X0176914Y0151453D01*
+X0177204Y0151293D01*
+X0177490Y0151126D01*
+X0177772Y0150953D01*
+X0178050Y0150772D01*
+X0178323Y0150584D01*
+X0178592Y0150390D01*
+X0178856Y0150190D01*
+X0179114Y0149983D01*
+X0179368Y0149769D01*
+X0179616Y0149550D01*
+X0179859Y0149324D01*
+X0180096Y0149093D01*
+X0180327Y0148856D01*
+X0180553Y0148613D01*
+X0180772Y0148365D01*
+X0180986Y0148111D01*
+X0181193Y0147853D01*
+X0181393Y0147589D01*
+X0181587Y0147320D01*
+X0181775Y0147047D01*
+X0181956Y0146769D01*
+X0182129Y0146487D01*
+X0182296Y0146201D01*
+X0182456Y0145911D01*
+X0182609Y0145617D01*
+X0182754Y0145319D01*
+X0182892Y0145018D01*
+X0183022Y0144713D01*
+X0183145Y0144406D01*
+X0183261Y0144095D01*
+X0183369Y0143782D01*
+X0183469Y0143466D01*
+X0183561Y0143148D01*
+X0183645Y0142827D01*
+X0183722Y0142505D01*
+X0183791Y0142181D01*
+X0183851Y0141855D01*
+X0183904Y0141528D01*
+X0183948Y0141200D01*
+X0183985Y0140870D01*
+X0184013Y0140540D01*
+X0184034Y0140209D01*
+X0184046Y0139878D01*
+X0184050Y0139547D01*
+X0184046Y0139216D01*
+X0184034Y0138885D01*
+X0184013Y0138554D01*
+X0183985Y0138224D01*
+X0183948Y0137894D01*
+X0183904Y0137566D01*
+X0183851Y0137239D01*
+X0183791Y0136913D01*
+X0183722Y0136589D01*
+X0183645Y0136267D01*
+X0183561Y0135946D01*
+X0183469Y0135628D01*
+X0183369Y0135312D01*
+X0183261Y0134999D01*
+X0183145Y0134688D01*
+X0183022Y0134381D01*
+X0182892Y0134076D01*
+X0182754Y0133775D01*
+X0182609Y0133477D01*
+X0182456Y0133183D01*
+X0182296Y0132893D01*
+X0182129Y0132607D01*
+X0181956Y0132325D01*
+X0181775Y0132047D01*
+X0181587Y0131774D01*
+X0181393Y0131505D01*
+X0181193Y0131241D01*
+X0180986Y0130983D01*
+X0180772Y0130729D01*
+X0180553Y0130481D01*
+X0180327Y0130238D01*
+X0180096Y0130001D01*
+X0179859Y0129770D01*
+X0179616Y0129544D01*
+X0179368Y0129325D01*
+X0179114Y0129111D01*
+X0178856Y0128904D01*
+X0178592Y0128704D01*
+X0178323Y0128510D01*
+X0178050Y0128322D01*
+X0177772Y0128141D01*
+X0177490Y0127968D01*
+X0177204Y0127801D01*
+X0176914Y0127641D01*
+X0176620Y0127488D01*
+X0176322Y0127343D01*
+X0176021Y0127205D01*
+X0175716Y0127075D01*
+X0175409Y0126952D01*
+X0175098Y0126836D01*
+X0174785Y0126728D01*
+X0174469Y0126628D01*
+X0174151Y0126536D01*
+X0173830Y0126452D01*
+X0173508Y0126375D01*
+X0173184Y0126306D01*
+X0172858Y0126246D01*
+X0172531Y0126193D01*
+X0172203Y0126149D01*
+X0171873Y0126112D01*
+X0171543Y0126084D01*
+X0171212Y0126063D01*
+X0170881Y0126051D01*
+X0170550Y0126047D01*
+X0170219Y0126051D01*
+X0169888Y0126063D01*
+X0169557Y0126084D01*
+X0169227Y0126112D01*
+X0168897Y0126149D01*
+X0168569Y0126193D01*
+X0168242Y0126246D01*
+X0167916Y0126306D01*
+X0167592Y0126375D01*
+X0167270Y0126452D01*
+X0166949Y0126536D01*
+X0166631Y0126628D01*
+X0166315Y0126728D01*
+X0166002Y0126836D01*
+X0165691Y0126952D01*
+X0165384Y0127075D01*
+X0165079Y0127205D01*
+X0164778Y0127343D01*
+X0164480Y0127488D01*
+X0164186Y0127641D01*
+X0163896Y0127801D01*
+X0163610Y0127968D01*
+X0163328Y0128141D01*
+X0163050Y0128322D01*
+X0162777Y0128510D01*
+X0162508Y0128704D01*
+X0162244Y0128904D01*
+X0161986Y0129111D01*
+X0161732Y0129325D01*
+X0161484Y0129544D01*
+X0161241Y0129770D01*
+X0161004Y0130001D01*
+X0160773Y0130238D01*
+X0160547Y0130481D01*
+X0160328Y0130729D01*
+X0160114Y0130983D01*
+X0159907Y0131241D01*
+X0159707Y0131505D01*
+X0159513Y0131774D01*
+X0159325Y0132047D01*
+X0159144Y0132325D01*
+X0158971Y0132607D01*
+X0158804Y0132893D01*
+X0158644Y0133183D01*
+X0158491Y0133477D01*
+X0158346Y0133775D01*
+X0158208Y0134076D01*
+X0158078Y0134381D01*
+X0157955Y0134688D01*
+X0157839Y0134999D01*
+X0157731Y0135312D01*
+X0157631Y0135628D01*
+X0157539Y0135946D01*
+X0157455Y0136267D01*
+X0157378Y0136589D01*
+X0157309Y0136913D01*
+X0157249Y0137239D01*
+X0157196Y0137566D01*
+X0157152Y0137894D01*
+X0157115Y0138224D01*
+X0157087Y0138554D01*
+X0157066Y0138885D01*
+X0157054Y0139216D01*
+X0157050Y0139547D01*
+X0155598Y0113747D02*
+X0152754Y0113747D01*
+X0152754Y0107347D01*
+X0155598Y0107347D01*
+X0154887Y0110902D02*
+X0152754Y0110902D01*
+X0149883Y0109836D02*
+X0145617Y0109836D01*
+X0143000Y0107347D02*
+X0141577Y0110191D01*
+X0141222Y0110191D02*
+X0139444Y0110191D01*
+X0141222Y0110191D02*
+X0141305Y0110193D01*
+X0141388Y0110199D01*
+X0141471Y0110209D01*
+X0141554Y0110222D01*
+X0141635Y0110240D01*
+X0141716Y0110261D01*
+X0141795Y0110286D01*
+X0141873Y0110315D01*
+X0141950Y0110347D01*
+X0142025Y0110383D01*
+X0142099Y0110422D01*
+X0142170Y0110465D01*
+X0142240Y0110511D01*
+X0142307Y0110561D01*
+X0142372Y0110613D01*
+X0142434Y0110668D01*
+X0142494Y0110727D01*
+X0142551Y0110788D01*
+X0142605Y0110851D01*
+X0142656Y0110917D01*
+X0142703Y0110986D01*
+X0142748Y0111056D01*
+X0142789Y0111129D01*
+X0142826Y0111203D01*
+X0142861Y0111279D01*
+X0142891Y0111357D01*
+X0142918Y0111435D01*
+X0142941Y0111516D01*
+X0142961Y0111597D01*
+X0142976Y0111679D01*
+X0142988Y0111761D01*
+X0142996Y0111844D01*
+X0143000Y0111927D01*
+X0143000Y0112011D01*
+X0142996Y0112094D01*
+X0142988Y0112177D01*
+X0142976Y0112259D01*
+X0142961Y0112341D01*
+X0142941Y0112422D01*
+X0142918Y0112503D01*
+X0142891Y0112581D01*
+X0142861Y0112659D01*
+X0142826Y0112735D01*
+X0142789Y0112809D01*
+X0142748Y0112882D01*
+X0142703Y0112952D01*
+X0142656Y0113021D01*
+X0142605Y0113087D01*
+X0142551Y0113150D01*
+X0142494Y0113211D01*
+X0142434Y0113270D01*
+X0142372Y0113325D01*
+X0142307Y0113377D01*
+X0142240Y0113427D01*
+X0142170Y0113473D01*
+X0142099Y0113516D01*
+X0142025Y0113555D01*
+X0141950Y0113591D01*
+X0141873Y0113623D01*
+X0141795Y0113652D01*
+X0141716Y0113677D01*
+X0141635Y0113698D01*
+X0141554Y0113716D01*
+X0141471Y0113729D01*
+X0141388Y0113739D01*
+X0141305Y0113745D01*
+X0141222Y0113747D01*
+X0139444Y0113747D01*
+X0139444Y0107347D01*
+X0136098Y0110013D02*
+X0134143Y0111080D01*
+X0134854Y0113747D02*
+X0134955Y0113745D01*
+X0135056Y0113739D01*
+X0135156Y0113730D01*
+X0135256Y0113716D01*
+X0135356Y0113699D01*
+X0135455Y0113679D01*
+X0135552Y0113654D01*
+X0135649Y0113626D01*
+X0135745Y0113594D01*
+X0135840Y0113558D01*
+X0135933Y0113519D01*
+X0136024Y0113477D01*
+X0136114Y0113431D01*
+X0136202Y0113381D01*
+X0136288Y0113329D01*
+X0136372Y0113273D01*
+X0136454Y0113214D01*
+X0134143Y0111080D02*
+X0134079Y0111120D01*
+X0134018Y0111163D01*
+X0133959Y0111209D01*
+X0133902Y0111258D01*
+X0133848Y0111310D01*
+X0133797Y0111364D01*
+X0133749Y0111422D01*
+X0133703Y0111481D01*
+X0133661Y0111543D01*
+X0133622Y0111608D01*
+X0133587Y0111674D01*
+X0133555Y0111741D01*
+X0133526Y0111811D01*
+X0133501Y0111881D01*
+X0133480Y0111953D01*
+X0133463Y0112026D01*
+X0133449Y0112100D01*
+X0133440Y0112174D01*
+X0133434Y0112249D01*
+X0133432Y0112324D01*
+X0133434Y0112398D01*
+X0133440Y0112473D01*
+X0133450Y0112546D01*
+X0133463Y0112620D01*
+X0133480Y0112692D01*
+X0133502Y0112763D01*
+X0133526Y0112834D01*
+X0133555Y0112902D01*
+X0133587Y0112970D01*
+X0133623Y0113035D01*
+X0133661Y0113098D01*
+X0133704Y0113160D01*
+X0133749Y0113219D01*
+X0133797Y0113276D01*
+X0133848Y0113330D01*
+X0133903Y0113381D01*
+X0133959Y0113429D01*
+X0134018Y0113474D01*
+X0134080Y0113517D01*
+X0134143Y0113555D01*
+X0134208Y0113591D01*
+X0134276Y0113623D01*
+X0134344Y0113652D01*
+X0134415Y0113676D01*
+X0134486Y0113698D01*
+X0134558Y0113715D01*
+X0134632Y0113728D01*
+X0134705Y0113738D01*
+X0134780Y0113744D01*
+X0134854Y0113746D01*
+X0133254Y0108236D02*
+X0133331Y0108161D01*
+X0133411Y0108088D01*
+X0133494Y0108019D01*
+X0133579Y0107952D01*
+X0133666Y0107889D01*
+X0133755Y0107829D01*
+X0133847Y0107772D01*
+X0133940Y0107718D01*
+X0134036Y0107668D01*
+X0134133Y0107621D01*
+X0134232Y0107578D01*
+X0134332Y0107538D01*
+X0134433Y0107502D01*
+X0134536Y0107470D01*
+X0134640Y0107441D01*
+X0134745Y0107416D01*
+X0134851Y0107395D01*
+X0134957Y0107378D01*
+X0135064Y0107364D01*
+X0135172Y0107355D01*
+X0135279Y0107349D01*
+X0135387Y0107347D01*
+X0135461Y0107349D01*
+X0135536Y0107355D01*
+X0135609Y0107365D01*
+X0135683Y0107378D01*
+X0135755Y0107395D01*
+X0135826Y0107417D01*
+X0135897Y0107441D01*
+X0135965Y0107470D01*
+X0136033Y0107502D01*
+X0136098Y0107538D01*
+X0136161Y0107576D01*
+X0136223Y0107619D01*
+X0136282Y0107664D01*
+X0136339Y0107712D01*
+X0136393Y0107763D01*
+X0136444Y0107817D01*
+X0136492Y0107874D01*
+X0136537Y0107933D01*
+X0136580Y0107995D01*
+X0136618Y0108058D01*
+X0136654Y0108123D01*
+X0136686Y0108191D01*
+X0136715Y0108259D01*
+X0136739Y0108330D01*
+X0136761Y0108401D01*
+X0136778Y0108473D01*
+X0136791Y0108547D01*
+X0136801Y0108620D01*
+X0136807Y0108695D01*
+X0136809Y0108769D01*
+X0136807Y0108844D01*
+X0136801Y0108919D01*
+X0136792Y0108993D01*
+X0136778Y0109067D01*
+X0136761Y0109140D01*
+X0136740Y0109212D01*
+X0136715Y0109282D01*
+X0136686Y0109352D01*
+X0136654Y0109419D01*
+X0136619Y0109485D01*
+X0136580Y0109550D01*
+X0136538Y0109612D01*
+X0136492Y0109671D01*
+X0136444Y0109729D01*
+X0136393Y0109783D01*
+X0136339Y0109835D01*
+X0136282Y0109884D01*
+X0136223Y0109930D01*
+X0136162Y0109973D01*
+X0136098Y0110013D01*
+X0130656Y0109124D02*
+X0130656Y0113747D01*
+X0127100Y0113747D02*
+X0127100Y0109124D01*
+X0127102Y0109041D01*
+X0127108Y0108958D01*
+X0127118Y0108875D01*
+X0127131Y0108792D01*
+X0127149Y0108711D01*
+X0127170Y0108630D01*
+X0127195Y0108551D01*
+X0127224Y0108473D01*
+X0127256Y0108396D01*
+X0127292Y0108321D01*
+X0127331Y0108247D01*
+X0127374Y0108176D01*
+X0127420Y0108106D01*
+X0127470Y0108039D01*
+X0127522Y0107974D01*
+X0127577Y0107912D01*
+X0127636Y0107852D01*
+X0127697Y0107795D01*
+X0127760Y0107741D01*
+X0127826Y0107690D01*
+X0127895Y0107643D01*
+X0127965Y0107598D01*
+X0128038Y0107557D01*
+X0128112Y0107520D01*
+X0128188Y0107485D01*
+X0128266Y0107455D01*
+X0128344Y0107428D01*
+X0128425Y0107405D01*
+X0128506Y0107385D01*
+X0128588Y0107370D01*
+X0128670Y0107358D01*
+X0128753Y0107350D01*
+X0128836Y0107346D01*
+X0128920Y0107346D01*
+X0129003Y0107350D01*
+X0129086Y0107358D01*
+X0129168Y0107370D01*
+X0129250Y0107385D01*
+X0129331Y0107405D01*
+X0129412Y0107428D01*
+X0129490Y0107455D01*
+X0129568Y0107485D01*
+X0129644Y0107520D01*
+X0129718Y0107557D01*
+X0129791Y0107598D01*
+X0129861Y0107643D01*
+X0129930Y0107690D01*
+X0129996Y0107741D01*
+X0130059Y0107795D01*
+X0130120Y0107852D01*
+X0130179Y0107912D01*
+X0130234Y0107974D01*
+X0130286Y0108039D01*
+X0130336Y0108106D01*
+X0130382Y0108176D01*
+X0130425Y0108247D01*
+X0130464Y0108321D01*
+X0130500Y0108396D01*
+X0130532Y0108473D01*
+X0130561Y0108551D01*
+X0130586Y0108630D01*
+X0130607Y0108711D01*
+X0130625Y0108792D01*
+X0130638Y0108875D01*
+X0130648Y0108958D01*
+X0130654Y0109041D01*
+X0130656Y0109124D01*
+X0158554Y0111080D02*
+X0160509Y0110013D01*
+X0159798Y0107347D02*
+X0159690Y0107349D01*
+X0159583Y0107355D01*
+X0159475Y0107364D01*
+X0159368Y0107378D01*
+X0159262Y0107395D01*
+X0159156Y0107416D01*
+X0159051Y0107441D01*
+X0158947Y0107470D01*
+X0158844Y0107502D01*
+X0158743Y0107538D01*
+X0158643Y0107578D01*
+X0158544Y0107621D01*
+X0158447Y0107668D01*
+X0158351Y0107718D01*
+X0158258Y0107772D01*
+X0158166Y0107829D01*
+X0158077Y0107889D01*
+X0157990Y0107952D01*
+X0157905Y0108019D01*
+X0157822Y0108088D01*
+X0157742Y0108161D01*
+X0157665Y0108236D01*
+X0160509Y0110013D02*
+X0160573Y0109973D01*
+X0160634Y0109930D01*
+X0160693Y0109884D01*
+X0160750Y0109835D01*
+X0160804Y0109783D01*
+X0160855Y0109729D01*
+X0160903Y0109671D01*
+X0160949Y0109612D01*
+X0160991Y0109550D01*
+X0161030Y0109485D01*
+X0161065Y0109419D01*
+X0161097Y0109352D01*
+X0161126Y0109282D01*
+X0161151Y0109212D01*
+X0161172Y0109140D01*
+X0161189Y0109067D01*
+X0161203Y0108993D01*
+X0161212Y0108919D01*
+X0161218Y0108844D01*
+X0161220Y0108769D01*
+X0161218Y0108695D01*
+X0161212Y0108620D01*
+X0161202Y0108547D01*
+X0161189Y0108473D01*
+X0161172Y0108401D01*
+X0161150Y0108330D01*
+X0161126Y0108259D01*
+X0161097Y0108191D01*
+X0161065Y0108123D01*
+X0161029Y0108058D01*
+X0160991Y0107995D01*
+X0160948Y0107933D01*
+X0160903Y0107874D01*
+X0160855Y0107817D01*
+X0160804Y0107763D01*
+X0160750Y0107712D01*
+X0160693Y0107664D01*
+X0160634Y0107619D01*
+X0160572Y0107576D01*
+X0160509Y0107538D01*
+X0160444Y0107502D01*
+X0160376Y0107470D01*
+X0160308Y0107441D01*
+X0160237Y0107417D01*
+X0160166Y0107395D01*
+X0160094Y0107378D01*
+X0160020Y0107365D01*
+X0159947Y0107355D01*
+X0159872Y0107349D01*
+X0159798Y0107347D01*
+X0160865Y0113214D02*
+X0160783Y0113273D01*
+X0160699Y0113329D01*
+X0160613Y0113381D01*
+X0160525Y0113431D01*
+X0160435Y0113477D01*
+X0160344Y0113519D01*
+X0160251Y0113558D01*
+X0160156Y0113594D01*
+X0160060Y0113626D01*
+X0159963Y0113654D01*
+X0159866Y0113679D01*
+X0159767Y0113699D01*
+X0159667Y0113716D01*
+X0159567Y0113730D01*
+X0159467Y0113739D01*
+X0159366Y0113745D01*
+X0159265Y0113747D01*
+X0159265Y0113746D02*
+X0159191Y0113744D01*
+X0159116Y0113738D01*
+X0159043Y0113728D01*
+X0158969Y0113715D01*
+X0158897Y0113698D01*
+X0158826Y0113676D01*
+X0158755Y0113652D01*
+X0158687Y0113623D01*
+X0158619Y0113591D01*
+X0158554Y0113555D01*
+X0158491Y0113517D01*
+X0158429Y0113474D01*
+X0158370Y0113429D01*
+X0158314Y0113381D01*
+X0158259Y0113330D01*
+X0158208Y0113276D01*
+X0158160Y0113219D01*
+X0158115Y0113160D01*
+X0158072Y0113098D01*
+X0158034Y0113035D01*
+X0157998Y0112970D01*
+X0157966Y0112902D01*
+X0157937Y0112834D01*
+X0157913Y0112763D01*
+X0157891Y0112692D01*
+X0157874Y0112620D01*
+X0157861Y0112546D01*
+X0157851Y0112473D01*
+X0157845Y0112398D01*
+X0157843Y0112324D01*
+X0157845Y0112249D01*
+X0157851Y0112174D01*
+X0157860Y0112100D01*
+X0157874Y0112026D01*
+X0157891Y0111953D01*
+X0157912Y0111881D01*
+X0157937Y0111811D01*
+X0157966Y0111741D01*
+X0157998Y0111674D01*
+X0158033Y0111608D01*
+X0158072Y0111543D01*
+X0158114Y0111481D01*
+X0158160Y0111422D01*
+X0158208Y0111364D01*
+X0158259Y0111310D01*
+X0158313Y0111258D01*
+X0158370Y0111209D01*
+X0158429Y0111163D01*
+X0158490Y0111120D01*
+X0158554Y0111080D01*
+X0163614Y0112324D02*
+X0165392Y0113747D01*
+X0165392Y0107347D01*
+X0167169Y0107347D02*
+X0163614Y0107347D01*
+X0085800Y0029047D02*
+X0086800Y0028047D01*
+X0086800Y0016547D01*
+X0085800Y0029047D02*
+X0047800Y0029047D01*
+X0046800Y0028047D01*
+X0046800Y0016547D01*
+X0057252Y0146189D02*
+X0060096Y0146189D01*
+X0060179Y0146191D01*
+X0060262Y0146197D01*
+X0060345Y0146207D01*
+X0060428Y0146220D01*
+X0060509Y0146238D01*
+X0060590Y0146259D01*
+X0060669Y0146284D01*
+X0060747Y0146313D01*
+X0060824Y0146345D01*
+X0060899Y0146381D01*
+X0060973Y0146420D01*
+X0061044Y0146463D01*
+X0061114Y0146509D01*
+X0061181Y0146559D01*
+X0061246Y0146611D01*
+X0061308Y0146666D01*
+X0061368Y0146725D01*
+X0061425Y0146786D01*
+X0061479Y0146849D01*
+X0061530Y0146915D01*
+X0061577Y0146984D01*
+X0061622Y0147054D01*
+X0061663Y0147127D01*
+X0061700Y0147201D01*
+X0061735Y0147277D01*
+X0061765Y0147355D01*
+X0061792Y0147433D01*
+X0061815Y0147514D01*
+X0061835Y0147595D01*
+X0061850Y0147677D01*
+X0061862Y0147759D01*
+X0061870Y0147842D01*
+X0061874Y0147925D01*
+X0061874Y0148009D01*
+X0061870Y0148092D01*
+X0061862Y0148175D01*
+X0061850Y0148257D01*
+X0061835Y0148339D01*
+X0061815Y0148420D01*
+X0061792Y0148501D01*
+X0061765Y0148579D01*
+X0061735Y0148657D01*
+X0061700Y0148733D01*
+X0061663Y0148807D01*
+X0061622Y0148880D01*
+X0061577Y0148950D01*
+X0061530Y0149019D01*
+X0061479Y0149085D01*
+X0061425Y0149148D01*
+X0061368Y0149209D01*
+X0061308Y0149268D01*
+X0061246Y0149323D01*
+X0061181Y0149375D01*
+X0061114Y0149425D01*
+X0061044Y0149471D01*
+X0060973Y0149514D01*
+X0060899Y0149553D01*
+X0060824Y0149589D01*
+X0060747Y0149621D01*
+X0060669Y0149650D01*
+X0060590Y0149675D01*
+X0060509Y0149696D01*
+X0060428Y0149714D01*
+X0060345Y0149727D01*
+X0060262Y0149737D01*
+X0060179Y0149743D01*
+X0060096Y0149745D01*
+X0060096Y0149744D02*
+X0057252Y0149744D01*
+X0057252Y0149745D02*
+X0057169Y0149743D01*
+X0057086Y0149737D01*
+X0057003Y0149727D01*
+X0056920Y0149714D01*
+X0056839Y0149696D01*
+X0056758Y0149675D01*
+X0056679Y0149650D01*
+X0056601Y0149621D01*
+X0056524Y0149589D01*
+X0056449Y0149553D01*
+X0056375Y0149514D01*
+X0056304Y0149471D01*
+X0056234Y0149425D01*
+X0056167Y0149375D01*
+X0056102Y0149323D01*
+X0056040Y0149268D01*
+X0055980Y0149209D01*
+X0055923Y0149148D01*
+X0055869Y0149085D01*
+X0055818Y0149019D01*
+X0055771Y0148950D01*
+X0055726Y0148880D01*
+X0055685Y0148807D01*
+X0055648Y0148733D01*
+X0055613Y0148657D01*
+X0055583Y0148579D01*
+X0055556Y0148501D01*
+X0055533Y0148420D01*
+X0055513Y0148339D01*
+X0055498Y0148257D01*
+X0055486Y0148175D01*
+X0055478Y0148092D01*
+X0055474Y0148009D01*
+X0055474Y0147925D01*
+X0055478Y0147842D01*
+X0055486Y0147759D01*
+X0055498Y0147677D01*
+X0055513Y0147595D01*
+X0055533Y0147514D01*
+X0055556Y0147433D01*
+X0055583Y0147355D01*
+X0055613Y0147277D01*
+X0055648Y0147201D01*
+X0055685Y0147127D01*
+X0055726Y0147054D01*
+X0055771Y0146984D01*
+X0055818Y0146915D01*
+X0055869Y0146849D01*
+X0055923Y0146786D01*
+X0055980Y0146725D01*
+X0056040Y0146666D01*
+X0056102Y0146611D01*
+X0056167Y0146559D01*
+X0056234Y0146509D01*
+X0056304Y0146463D01*
+X0056375Y0146420D01*
+X0056449Y0146381D01*
+X0056524Y0146345D01*
+X0056601Y0146313D01*
+X0056679Y0146284D01*
+X0056758Y0146259D01*
+X0056839Y0146238D01*
+X0056920Y0146220D01*
+X0057003Y0146207D01*
+X0057086Y0146197D01*
+X0057169Y0146191D01*
+X0057252Y0146189D01*
+X0059030Y0152584D02*
+X0059030Y0154362D01*
+X0059030Y0154717D02*
+X0061874Y0156140D01*
+X0061874Y0152584D02*
+X0055474Y0152584D01*
+X0055474Y0154362D01*
+X0055476Y0154445D01*
+X0055482Y0154528D01*
+X0055492Y0154611D01*
+X0055505Y0154694D01*
+X0055523Y0154775D01*
+X0055544Y0154856D01*
+X0055569Y0154935D01*
+X0055598Y0155013D01*
+X0055630Y0155090D01*
+X0055666Y0155165D01*
+X0055705Y0155239D01*
+X0055748Y0155310D01*
+X0055794Y0155380D01*
+X0055844Y0155447D01*
+X0055896Y0155512D01*
+X0055951Y0155574D01*
+X0056010Y0155634D01*
+X0056071Y0155691D01*
+X0056134Y0155745D01*
+X0056200Y0155796D01*
+X0056269Y0155843D01*
+X0056339Y0155888D01*
+X0056412Y0155929D01*
+X0056486Y0155966D01*
+X0056562Y0156001D01*
+X0056640Y0156031D01*
+X0056718Y0156058D01*
+X0056799Y0156081D01*
+X0056880Y0156101D01*
+X0056962Y0156116D01*
+X0057044Y0156128D01*
+X0057127Y0156136D01*
+X0057210Y0156140D01*
+X0057294Y0156140D01*
+X0057377Y0156136D01*
+X0057460Y0156128D01*
+X0057542Y0156116D01*
+X0057624Y0156101D01*
+X0057705Y0156081D01*
+X0057786Y0156058D01*
+X0057864Y0156031D01*
+X0057942Y0156001D01*
+X0058018Y0155966D01*
+X0058092Y0155929D01*
+X0058165Y0155888D01*
+X0058235Y0155843D01*
+X0058304Y0155796D01*
+X0058370Y0155745D01*
+X0058433Y0155691D01*
+X0058494Y0155634D01*
+X0058553Y0155574D01*
+X0058608Y0155512D01*
+X0058660Y0155447D01*
+X0058710Y0155380D01*
+X0058756Y0155310D01*
+X0058799Y0155239D01*
+X0058838Y0155165D01*
+X0058874Y0155090D01*
+X0058906Y0155013D01*
+X0058935Y0154935D01*
+X0058960Y0154856D01*
+X0058981Y0154775D01*
+X0058999Y0154694D01*
+X0059012Y0154611D01*
+X0059022Y0154528D01*
+X0059028Y0154445D01*
+X0059030Y0154362D01*
+X0018300Y0262047D02*
+X0018304Y0262378D01*
+X0018316Y0262709D01*
+X0018337Y0263040D01*
+X0018365Y0263370D01*
+X0018402Y0263700D01*
+X0018446Y0264028D01*
+X0018499Y0264355D01*
+X0018559Y0264681D01*
+X0018628Y0265005D01*
+X0018705Y0265327D01*
+X0018789Y0265648D01*
+X0018881Y0265966D01*
+X0018981Y0266282D01*
+X0019089Y0266595D01*
+X0019205Y0266906D01*
+X0019328Y0267213D01*
+X0019458Y0267518D01*
+X0019596Y0267819D01*
+X0019741Y0268117D01*
+X0019894Y0268411D01*
+X0020054Y0268701D01*
+X0020221Y0268987D01*
+X0020394Y0269269D01*
+X0020575Y0269547D01*
+X0020763Y0269820D01*
+X0020957Y0270089D01*
+X0021157Y0270353D01*
+X0021364Y0270611D01*
+X0021578Y0270865D01*
+X0021797Y0271113D01*
+X0022023Y0271356D01*
+X0022254Y0271593D01*
+X0022491Y0271824D01*
+X0022734Y0272050D01*
+X0022982Y0272269D01*
+X0023236Y0272483D01*
+X0023494Y0272690D01*
+X0023758Y0272890D01*
+X0024027Y0273084D01*
+X0024300Y0273272D01*
+X0024578Y0273453D01*
+X0024860Y0273626D01*
+X0025146Y0273793D01*
+X0025436Y0273953D01*
+X0025730Y0274106D01*
+X0026028Y0274251D01*
+X0026329Y0274389D01*
+X0026634Y0274519D01*
+X0026941Y0274642D01*
+X0027252Y0274758D01*
+X0027565Y0274866D01*
+X0027881Y0274966D01*
+X0028199Y0275058D01*
+X0028520Y0275142D01*
+X0028842Y0275219D01*
+X0029166Y0275288D01*
+X0029492Y0275348D01*
+X0029819Y0275401D01*
+X0030147Y0275445D01*
+X0030477Y0275482D01*
+X0030807Y0275510D01*
+X0031138Y0275531D01*
+X0031469Y0275543D01*
+X0031800Y0275547D01*
+X0032131Y0275543D01*
+X0032462Y0275531D01*
+X0032793Y0275510D01*
+X0033123Y0275482D01*
+X0033453Y0275445D01*
+X0033781Y0275401D01*
+X0034108Y0275348D01*
+X0034434Y0275288D01*
+X0034758Y0275219D01*
+X0035080Y0275142D01*
+X0035401Y0275058D01*
+X0035719Y0274966D01*
+X0036035Y0274866D01*
+X0036348Y0274758D01*
+X0036659Y0274642D01*
+X0036966Y0274519D01*
+X0037271Y0274389D01*
+X0037572Y0274251D01*
+X0037870Y0274106D01*
+X0038164Y0273953D01*
+X0038454Y0273793D01*
+X0038740Y0273626D01*
+X0039022Y0273453D01*
+X0039300Y0273272D01*
+X0039573Y0273084D01*
+X0039842Y0272890D01*
+X0040106Y0272690D01*
+X0040364Y0272483D01*
+X0040618Y0272269D01*
+X0040866Y0272050D01*
+X0041109Y0271824D01*
+X0041346Y0271593D01*
+X0041577Y0271356D01*
+X0041803Y0271113D01*
+X0042022Y0270865D01*
+X0042236Y0270611D01*
+X0042443Y0270353D01*
+X0042643Y0270089D01*
+X0042837Y0269820D01*
+X0043025Y0269547D01*
+X0043206Y0269269D01*
+X0043379Y0268987D01*
+X0043546Y0268701D01*
+X0043706Y0268411D01*
+X0043859Y0268117D01*
+X0044004Y0267819D01*
+X0044142Y0267518D01*
+X0044272Y0267213D01*
+X0044395Y0266906D01*
+X0044511Y0266595D01*
+X0044619Y0266282D01*
+X0044719Y0265966D01*
+X0044811Y0265648D01*
+X0044895Y0265327D01*
+X0044972Y0265005D01*
+X0045041Y0264681D01*
+X0045101Y0264355D01*
+X0045154Y0264028D01*
+X0045198Y0263700D01*
+X0045235Y0263370D01*
+X0045263Y0263040D01*
+X0045284Y0262709D01*
+X0045296Y0262378D01*
+X0045300Y0262047D01*
+X0045296Y0261716D01*
+X0045284Y0261385D01*
+X0045263Y0261054D01*
+X0045235Y0260724D01*
+X0045198Y0260394D01*
+X0045154Y0260066D01*
+X0045101Y0259739D01*
+X0045041Y0259413D01*
+X0044972Y0259089D01*
+X0044895Y0258767D01*
+X0044811Y0258446D01*
+X0044719Y0258128D01*
+X0044619Y0257812D01*
+X0044511Y0257499D01*
+X0044395Y0257188D01*
+X0044272Y0256881D01*
+X0044142Y0256576D01*
+X0044004Y0256275D01*
+X0043859Y0255977D01*
+X0043706Y0255683D01*
+X0043546Y0255393D01*
+X0043379Y0255107D01*
+X0043206Y0254825D01*
+X0043025Y0254547D01*
+X0042837Y0254274D01*
+X0042643Y0254005D01*
+X0042443Y0253741D01*
+X0042236Y0253483D01*
+X0042022Y0253229D01*
+X0041803Y0252981D01*
+X0041577Y0252738D01*
+X0041346Y0252501D01*
+X0041109Y0252270D01*
+X0040866Y0252044D01*
+X0040618Y0251825D01*
+X0040364Y0251611D01*
+X0040106Y0251404D01*
+X0039842Y0251204D01*
+X0039573Y0251010D01*
+X0039300Y0250822D01*
+X0039022Y0250641D01*
+X0038740Y0250468D01*
+X0038454Y0250301D01*
+X0038164Y0250141D01*
+X0037870Y0249988D01*
+X0037572Y0249843D01*
+X0037271Y0249705D01*
+X0036966Y0249575D01*
+X0036659Y0249452D01*
+X0036348Y0249336D01*
+X0036035Y0249228D01*
+X0035719Y0249128D01*
+X0035401Y0249036D01*
+X0035080Y0248952D01*
+X0034758Y0248875D01*
+X0034434Y0248806D01*
+X0034108Y0248746D01*
+X0033781Y0248693D01*
+X0033453Y0248649D01*
+X0033123Y0248612D01*
+X0032793Y0248584D01*
+X0032462Y0248563D01*
+X0032131Y0248551D01*
+X0031800Y0248547D01*
+X0031469Y0248551D01*
+X0031138Y0248563D01*
+X0030807Y0248584D01*
+X0030477Y0248612D01*
+X0030147Y0248649D01*
+X0029819Y0248693D01*
+X0029492Y0248746D01*
+X0029166Y0248806D01*
+X0028842Y0248875D01*
+X0028520Y0248952D01*
+X0028199Y0249036D01*
+X0027881Y0249128D01*
+X0027565Y0249228D01*
+X0027252Y0249336D01*
+X0026941Y0249452D01*
+X0026634Y0249575D01*
+X0026329Y0249705D01*
+X0026028Y0249843D01*
+X0025730Y0249988D01*
+X0025436Y0250141D01*
+X0025146Y0250301D01*
+X0024860Y0250468D01*
+X0024578Y0250641D01*
+X0024300Y0250822D01*
+X0024027Y0251010D01*
+X0023758Y0251204D01*
+X0023494Y0251404D01*
+X0023236Y0251611D01*
+X0022982Y0251825D01*
+X0022734Y0252044D01*
+X0022491Y0252270D01*
+X0022254Y0252501D01*
+X0022023Y0252738D01*
+X0021797Y0252981D01*
+X0021578Y0253229D01*
+X0021364Y0253483D01*
+X0021157Y0253741D01*
+X0020957Y0254005D01*
+X0020763Y0254274D01*
+X0020575Y0254547D01*
+X0020394Y0254825D01*
+X0020221Y0255107D01*
+X0020054Y0255393D01*
+X0019894Y0255683D01*
+X0019741Y0255977D01*
+X0019596Y0256275D01*
+X0019458Y0256576D01*
+X0019328Y0256881D01*
+X0019205Y0257188D01*
+X0019089Y0257499D01*
+X0018981Y0257812D01*
+X0018881Y0258128D01*
+X0018789Y0258446D01*
+X0018705Y0258767D01*
+X0018628Y0259089D01*
+X0018559Y0259413D01*
+X0018499Y0259739D01*
+X0018446Y0260066D01*
+X0018402Y0260394D01*
+X0018365Y0260724D01*
+X0018337Y0261054D01*
+X0018316Y0261385D01*
+X0018304Y0261716D01*
+X0018300Y0262047D01*
+X0332050Y0262047D02*
+X0332054Y0262378D01*
+X0332066Y0262709D01*
+X0332087Y0263040D01*
+X0332115Y0263370D01*
+X0332152Y0263700D01*
+X0332196Y0264028D01*
+X0332249Y0264355D01*
+X0332309Y0264681D01*
+X0332378Y0265005D01*
+X0332455Y0265327D01*
+X0332539Y0265648D01*
+X0332631Y0265966D01*
+X0332731Y0266282D01*
+X0332839Y0266595D01*
+X0332955Y0266906D01*
+X0333078Y0267213D01*
+X0333208Y0267518D01*
+X0333346Y0267819D01*
+X0333491Y0268117D01*
+X0333644Y0268411D01*
+X0333804Y0268701D01*
+X0333971Y0268987D01*
+X0334144Y0269269D01*
+X0334325Y0269547D01*
+X0334513Y0269820D01*
+X0334707Y0270089D01*
+X0334907Y0270353D01*
+X0335114Y0270611D01*
+X0335328Y0270865D01*
+X0335547Y0271113D01*
+X0335773Y0271356D01*
+X0336004Y0271593D01*
+X0336241Y0271824D01*
+X0336484Y0272050D01*
+X0336732Y0272269D01*
+X0336986Y0272483D01*
+X0337244Y0272690D01*
+X0337508Y0272890D01*
+X0337777Y0273084D01*
+X0338050Y0273272D01*
+X0338328Y0273453D01*
+X0338610Y0273626D01*
+X0338896Y0273793D01*
+X0339186Y0273953D01*
+X0339480Y0274106D01*
+X0339778Y0274251D01*
+X0340079Y0274389D01*
+X0340384Y0274519D01*
+X0340691Y0274642D01*
+X0341002Y0274758D01*
+X0341315Y0274866D01*
+X0341631Y0274966D01*
+X0341949Y0275058D01*
+X0342270Y0275142D01*
+X0342592Y0275219D01*
+X0342916Y0275288D01*
+X0343242Y0275348D01*
+X0343569Y0275401D01*
+X0343897Y0275445D01*
+X0344227Y0275482D01*
+X0344557Y0275510D01*
+X0344888Y0275531D01*
+X0345219Y0275543D01*
+X0345550Y0275547D01*
+X0345881Y0275543D01*
+X0346212Y0275531D01*
+X0346543Y0275510D01*
+X0346873Y0275482D01*
+X0347203Y0275445D01*
+X0347531Y0275401D01*
+X0347858Y0275348D01*
+X0348184Y0275288D01*
+X0348508Y0275219D01*
+X0348830Y0275142D01*
+X0349151Y0275058D01*
+X0349469Y0274966D01*
+X0349785Y0274866D01*
+X0350098Y0274758D01*
+X0350409Y0274642D01*
+X0350716Y0274519D01*
+X0351021Y0274389D01*
+X0351322Y0274251D01*
+X0351620Y0274106D01*
+X0351914Y0273953D01*
+X0352204Y0273793D01*
+X0352490Y0273626D01*
+X0352772Y0273453D01*
+X0353050Y0273272D01*
+X0353323Y0273084D01*
+X0353592Y0272890D01*
+X0353856Y0272690D01*
+X0354114Y0272483D01*
+X0354368Y0272269D01*
+X0354616Y0272050D01*
+X0354859Y0271824D01*
+X0355096Y0271593D01*
+X0355327Y0271356D01*
+X0355553Y0271113D01*
+X0355772Y0270865D01*
+X0355986Y0270611D01*
+X0356193Y0270353D01*
+X0356393Y0270089D01*
+X0356587Y0269820D01*
+X0356775Y0269547D01*
+X0356956Y0269269D01*
+X0357129Y0268987D01*
+X0357296Y0268701D01*
+X0357456Y0268411D01*
+X0357609Y0268117D01*
+X0357754Y0267819D01*
+X0357892Y0267518D01*
+X0358022Y0267213D01*
+X0358145Y0266906D01*
+X0358261Y0266595D01*
+X0358369Y0266282D01*
+X0358469Y0265966D01*
+X0358561Y0265648D01*
+X0358645Y0265327D01*
+X0358722Y0265005D01*
+X0358791Y0264681D01*
+X0358851Y0264355D01*
+X0358904Y0264028D01*
+X0358948Y0263700D01*
+X0358985Y0263370D01*
+X0359013Y0263040D01*
+X0359034Y0262709D01*
+X0359046Y0262378D01*
+X0359050Y0262047D01*
+X0359046Y0261716D01*
+X0359034Y0261385D01*
+X0359013Y0261054D01*
+X0358985Y0260724D01*
+X0358948Y0260394D01*
+X0358904Y0260066D01*
+X0358851Y0259739D01*
+X0358791Y0259413D01*
+X0358722Y0259089D01*
+X0358645Y0258767D01*
+X0358561Y0258446D01*
+X0358469Y0258128D01*
+X0358369Y0257812D01*
+X0358261Y0257499D01*
+X0358145Y0257188D01*
+X0358022Y0256881D01*
+X0357892Y0256576D01*
+X0357754Y0256275D01*
+X0357609Y0255977D01*
+X0357456Y0255683D01*
+X0357296Y0255393D01*
+X0357129Y0255107D01*
+X0356956Y0254825D01*
+X0356775Y0254547D01*
+X0356587Y0254274D01*
+X0356393Y0254005D01*
+X0356193Y0253741D01*
+X0355986Y0253483D01*
+X0355772Y0253229D01*
+X0355553Y0252981D01*
+X0355327Y0252738D01*
+X0355096Y0252501D01*
+X0354859Y0252270D01*
+X0354616Y0252044D01*
+X0354368Y0251825D01*
+X0354114Y0251611D01*
+X0353856Y0251404D01*
+X0353592Y0251204D01*
+X0353323Y0251010D01*
+X0353050Y0250822D01*
+X0352772Y0250641D01*
+X0352490Y0250468D01*
+X0352204Y0250301D01*
+X0351914Y0250141D01*
+X0351620Y0249988D01*
+X0351322Y0249843D01*
+X0351021Y0249705D01*
+X0350716Y0249575D01*
+X0350409Y0249452D01*
+X0350098Y0249336D01*
+X0349785Y0249228D01*
+X0349469Y0249128D01*
+X0349151Y0249036D01*
+X0348830Y0248952D01*
+X0348508Y0248875D01*
+X0348184Y0248806D01*
+X0347858Y0248746D01*
+X0347531Y0248693D01*
+X0347203Y0248649D01*
+X0346873Y0248612D01*
+X0346543Y0248584D01*
+X0346212Y0248563D01*
+X0345881Y0248551D01*
+X0345550Y0248547D01*
+X0345219Y0248551D01*
+X0344888Y0248563D01*
+X0344557Y0248584D01*
+X0344227Y0248612D01*
+X0343897Y0248649D01*
+X0343569Y0248693D01*
+X0343242Y0248746D01*
+X0342916Y0248806D01*
+X0342592Y0248875D01*
+X0342270Y0248952D01*
+X0341949Y0249036D01*
+X0341631Y0249128D01*
+X0341315Y0249228D01*
+X0341002Y0249336D01*
+X0340691Y0249452D01*
+X0340384Y0249575D01*
+X0340079Y0249705D01*
+X0339778Y0249843D01*
+X0339480Y0249988D01*
+X0339186Y0250141D01*
+X0338896Y0250301D01*
+X0338610Y0250468D01*
+X0338328Y0250641D01*
+X0338050Y0250822D01*
+X0337777Y0251010D01*
+X0337508Y0251204D01*
+X0337244Y0251404D01*
+X0336986Y0251611D01*
+X0336732Y0251825D01*
+X0336484Y0252044D01*
+X0336241Y0252270D01*
+X0336004Y0252501D01*
+X0335773Y0252738D01*
+X0335547Y0252981D01*
+X0335328Y0253229D01*
+X0335114Y0253483D01*
+X0334907Y0253741D01*
+X0334707Y0254005D01*
+X0334513Y0254274D01*
+X0334325Y0254547D01*
+X0334144Y0254825D01*
+X0333971Y0255107D01*
+X0333804Y0255393D01*
+X0333644Y0255683D01*
+X0333491Y0255977D01*
+X0333346Y0256275D01*
+X0333208Y0256576D01*
+X0333078Y0256881D01*
+X0332955Y0257188D01*
+X0332839Y0257499D01*
+X0332731Y0257812D01*
+X0332631Y0258128D01*
+X0332539Y0258446D01*
+X0332455Y0258767D01*
+X0332378Y0259089D01*
+X0332309Y0259413D01*
+X0332249Y0259739D01*
+X0332196Y0260066D01*
+X0332152Y0260394D01*
+X0332115Y0260724D01*
+X0332087Y0261054D01*
+X0332066Y0261385D01*
+X0332054Y0261716D01*
+X0332050Y0262047D01*
+D12*
+X0338070Y0262047D02*
+X0338072Y0262231D01*
+X0338079Y0262414D01*
+X0338090Y0262597D01*
+X0338106Y0262780D01*
+X0338126Y0262963D01*
+X0338151Y0263145D01*
+X0338180Y0263326D01*
+X0338214Y0263506D01*
+X0338252Y0263686D01*
+X0338294Y0263864D01*
+X0338341Y0264042D01*
+X0338392Y0264218D01*
+X0338448Y0264393D01*
+X0338507Y0264567D01*
+X0338571Y0264739D01*
+X0338639Y0264909D01*
+X0338712Y0265078D01*
+X0338788Y0265245D01*
+X0338869Y0265410D01*
+X0338953Y0265573D01*
+X0339042Y0265734D01*
+X0339134Y0265892D01*
+X0339230Y0266049D01*
+X0339331Y0266203D01*
+X0339434Y0266354D01*
+X0339542Y0266503D01*
+X0339653Y0266649D01*
+X0339768Y0266792D01*
+X0339886Y0266933D01*
+X0340008Y0267070D01*
+X0340133Y0267205D01*
+X0340261Y0267336D01*
+X0340392Y0267464D01*
+X0340527Y0267589D01*
+X0340664Y0267711D01*
+X0340805Y0267829D01*
+X0340948Y0267944D01*
+X0341094Y0268055D01*
+X0341243Y0268163D01*
+X0341394Y0268266D01*
+X0341548Y0268367D01*
+X0341705Y0268463D01*
+X0341863Y0268555D01*
+X0342024Y0268644D01*
+X0342187Y0268728D01*
+X0342352Y0268809D01*
+X0342519Y0268885D01*
+X0342688Y0268958D01*
+X0342858Y0269026D01*
+X0343030Y0269090D01*
+X0343204Y0269149D01*
+X0343379Y0269205D01*
+X0343555Y0269256D01*
+X0343733Y0269303D01*
+X0343911Y0269345D01*
+X0344091Y0269383D01*
+X0344271Y0269417D01*
+X0344452Y0269446D01*
+X0344634Y0269471D01*
+X0344817Y0269491D01*
+X0345000Y0269507D01*
+X0345183Y0269518D01*
+X0345366Y0269525D01*
+X0345550Y0269527D01*
+X0345734Y0269525D01*
+X0345917Y0269518D01*
+X0346100Y0269507D01*
+X0346283Y0269491D01*
+X0346466Y0269471D01*
+X0346648Y0269446D01*
+X0346829Y0269417D01*
+X0347009Y0269383D01*
+X0347189Y0269345D01*
+X0347367Y0269303D01*
+X0347545Y0269256D01*
+X0347721Y0269205D01*
+X0347896Y0269149D01*
+X0348070Y0269090D01*
+X0348242Y0269026D01*
+X0348412Y0268958D01*
+X0348581Y0268885D01*
+X0348748Y0268809D01*
+X0348913Y0268728D01*
+X0349076Y0268644D01*
+X0349237Y0268555D01*
+X0349395Y0268463D01*
+X0349552Y0268367D01*
+X0349706Y0268266D01*
+X0349857Y0268163D01*
+X0350006Y0268055D01*
+X0350152Y0267944D01*
+X0350295Y0267829D01*
+X0350436Y0267711D01*
+X0350573Y0267589D01*
+X0350708Y0267464D01*
+X0350839Y0267336D01*
+X0350967Y0267205D01*
+X0351092Y0267070D01*
+X0351214Y0266933D01*
+X0351332Y0266792D01*
+X0351447Y0266649D01*
+X0351558Y0266503D01*
+X0351666Y0266354D01*
+X0351769Y0266203D01*
+X0351870Y0266049D01*
+X0351966Y0265892D01*
+X0352058Y0265734D01*
+X0352147Y0265573D01*
+X0352231Y0265410D01*
+X0352312Y0265245D01*
+X0352388Y0265078D01*
+X0352461Y0264909D01*
+X0352529Y0264739D01*
+X0352593Y0264567D01*
+X0352652Y0264393D01*
+X0352708Y0264218D01*
+X0352759Y0264042D01*
+X0352806Y0263864D01*
+X0352848Y0263686D01*
+X0352886Y0263506D01*
+X0352920Y0263326D01*
+X0352949Y0263145D01*
+X0352974Y0262963D01*
+X0352994Y0262780D01*
+X0353010Y0262597D01*
+X0353021Y0262414D01*
+X0353028Y0262231D01*
+X0353030Y0262047D01*
+X0353028Y0261863D01*
+X0353021Y0261680D01*
+X0353010Y0261497D01*
+X0352994Y0261314D01*
+X0352974Y0261131D01*
+X0352949Y0260949D01*
+X0352920Y0260768D01*
+X0352886Y0260588D01*
+X0352848Y0260408D01*
+X0352806Y0260230D01*
+X0352759Y0260052D01*
+X0352708Y0259876D01*
+X0352652Y0259701D01*
+X0352593Y0259527D01*
+X0352529Y0259355D01*
+X0352461Y0259185D01*
+X0352388Y0259016D01*
+X0352312Y0258849D01*
+X0352231Y0258684D01*
+X0352147Y0258521D01*
+X0352058Y0258360D01*
+X0351966Y0258202D01*
+X0351870Y0258045D01*
+X0351769Y0257891D01*
+X0351666Y0257740D01*
+X0351558Y0257591D01*
+X0351447Y0257445D01*
+X0351332Y0257302D01*
+X0351214Y0257161D01*
+X0351092Y0257024D01*
+X0350967Y0256889D01*
+X0350839Y0256758D01*
+X0350708Y0256630D01*
+X0350573Y0256505D01*
+X0350436Y0256383D01*
+X0350295Y0256265D01*
+X0350152Y0256150D01*
+X0350006Y0256039D01*
+X0349857Y0255931D01*
+X0349706Y0255828D01*
+X0349552Y0255727D01*
+X0349395Y0255631D01*
+X0349237Y0255539D01*
+X0349076Y0255450D01*
+X0348913Y0255366D01*
+X0348748Y0255285D01*
+X0348581Y0255209D01*
+X0348412Y0255136D01*
+X0348242Y0255068D01*
+X0348070Y0255004D01*
+X0347896Y0254945D01*
+X0347721Y0254889D01*
+X0347545Y0254838D01*
+X0347367Y0254791D01*
+X0347189Y0254749D01*
+X0347009Y0254711D01*
+X0346829Y0254677D01*
+X0346648Y0254648D01*
+X0346466Y0254623D01*
+X0346283Y0254603D01*
+X0346100Y0254587D01*
+X0345917Y0254576D01*
+X0345734Y0254569D01*
+X0345550Y0254567D01*
+X0345366Y0254569D01*
+X0345183Y0254576D01*
+X0345000Y0254587D01*
+X0344817Y0254603D01*
+X0344634Y0254623D01*
+X0344452Y0254648D01*
+X0344271Y0254677D01*
+X0344091Y0254711D01*
+X0343911Y0254749D01*
+X0343733Y0254791D01*
+X0343555Y0254838D01*
+X0343379Y0254889D01*
+X0343204Y0254945D01*
+X0343030Y0255004D01*
+X0342858Y0255068D01*
+X0342688Y0255136D01*
+X0342519Y0255209D01*
+X0342352Y0255285D01*
+X0342187Y0255366D01*
+X0342024Y0255450D01*
+X0341863Y0255539D01*
+X0341705Y0255631D01*
+X0341548Y0255727D01*
+X0341394Y0255828D01*
+X0341243Y0255931D01*
+X0341094Y0256039D01*
+X0340948Y0256150D01*
+X0340805Y0256265D01*
+X0340664Y0256383D01*
+X0340527Y0256505D01*
+X0340392Y0256630D01*
+X0340261Y0256758D01*
+X0340133Y0256889D01*
+X0340008Y0257024D01*
+X0339886Y0257161D01*
+X0339768Y0257302D01*
+X0339653Y0257445D01*
+X0339542Y0257591D01*
+X0339434Y0257740D01*
+X0339331Y0257891D01*
+X0339230Y0258045D01*
+X0339134Y0258202D01*
+X0339042Y0258360D01*
+X0338953Y0258521D01*
+X0338869Y0258684D01*
+X0338788Y0258849D01*
+X0338712Y0259016D01*
+X0338639Y0259185D01*
+X0338571Y0259355D01*
+X0338507Y0259527D01*
+X0338448Y0259701D01*
+X0338392Y0259876D01*
+X0338341Y0260052D01*
+X0338294Y0260230D01*
+X0338252Y0260408D01*
+X0338214Y0260588D01*
+X0338180Y0260768D01*
+X0338151Y0260949D01*
+X0338126Y0261131D01*
+X0338106Y0261314D01*
+X0338090Y0261497D01*
+X0338079Y0261680D01*
+X0338072Y0261863D01*
+X0338070Y0262047D01*
+X0288936Y0289655D02*
+X0288936Y0297923D01*
+X0286967Y0299104D01*
+X0264133Y0299104D01*
+X0264133Y0301466D01*
+X0286967Y0301466D01*
+X0286967Y0299104D01*
+X0288936Y0289655D02*
+X0286967Y0288474D01*
+X0264133Y0288474D01*
+X0262164Y0289655D01*
+X0262164Y0297923D01*
+X0264133Y0299104D01*
+X0264133Y0288474D02*
+X0264133Y0272726D01*
+X0271219Y0268395D02*
+X0279881Y0268395D01*
+X0286967Y0272726D02*
+X0286967Y0288474D01*
+X0288148Y0260127D02*
+X0288148Y0251466D01*
+X0279881Y0243198D02*
+X0271219Y0243198D01*
+X0262952Y0251466D02*
+X0262952Y0260127D01*
+X0268857Y0255797D02*
+X0268859Y0255961D01*
+X0268865Y0256125D01*
+X0268875Y0256289D01*
+X0268889Y0256453D01*
+X0268907Y0256616D01*
+X0268929Y0256779D01*
+X0268956Y0256941D01*
+X0268986Y0257103D01*
+X0269020Y0257263D01*
+X0269058Y0257423D01*
+X0269099Y0257582D01*
+X0269145Y0257740D01*
+X0269195Y0257896D01*
+X0269248Y0258052D01*
+X0269305Y0258206D01*
+X0269366Y0258358D01*
+X0269431Y0258509D01*
+X0269500Y0258659D01*
+X0269572Y0258806D01*
+X0269647Y0258952D01*
+X0269727Y0259096D01*
+X0269809Y0259238D01*
+X0269895Y0259378D01*
+X0269985Y0259515D01*
+X0270078Y0259651D01*
+X0270174Y0259784D01*
+X0270274Y0259915D01*
+X0270376Y0260043D01*
+X0270482Y0260169D01*
+X0270591Y0260292D01*
+X0270703Y0260412D01*
+X0270817Y0260530D01*
+X0270935Y0260644D01*
+X0271055Y0260756D01*
+X0271178Y0260865D01*
+X0271304Y0260971D01*
+X0271432Y0261073D01*
+X0271563Y0261173D01*
+X0271696Y0261269D01*
+X0271832Y0261362D01*
+X0271969Y0261452D01*
+X0272109Y0261538D01*
+X0272251Y0261620D01*
+X0272395Y0261700D01*
+X0272541Y0261775D01*
+X0272688Y0261847D01*
+X0272838Y0261916D01*
+X0272989Y0261981D01*
+X0273141Y0262042D01*
+X0273295Y0262099D01*
+X0273451Y0262152D01*
+X0273607Y0262202D01*
+X0273765Y0262248D01*
+X0273924Y0262289D01*
+X0274084Y0262327D01*
+X0274244Y0262361D01*
+X0274406Y0262391D01*
+X0274568Y0262418D01*
+X0274731Y0262440D01*
+X0274894Y0262458D01*
+X0275058Y0262472D01*
+X0275222Y0262482D01*
+X0275386Y0262488D01*
+X0275550Y0262490D01*
+X0275714Y0262488D01*
+X0275878Y0262482D01*
+X0276042Y0262472D01*
+X0276206Y0262458D01*
+X0276369Y0262440D01*
+X0276532Y0262418D01*
+X0276694Y0262391D01*
+X0276856Y0262361D01*
+X0277016Y0262327D01*
+X0277176Y0262289D01*
+X0277335Y0262248D01*
+X0277493Y0262202D01*
+X0277649Y0262152D01*
+X0277805Y0262099D01*
+X0277959Y0262042D01*
+X0278111Y0261981D01*
+X0278262Y0261916D01*
+X0278412Y0261847D01*
+X0278559Y0261775D01*
+X0278705Y0261700D01*
+X0278849Y0261620D01*
+X0278991Y0261538D01*
+X0279131Y0261452D01*
+X0279268Y0261362D01*
+X0279404Y0261269D01*
+X0279537Y0261173D01*
+X0279668Y0261073D01*
+X0279796Y0260971D01*
+X0279922Y0260865D01*
+X0280045Y0260756D01*
+X0280165Y0260644D01*
+X0280283Y0260530D01*
+X0280397Y0260412D01*
+X0280509Y0260292D01*
+X0280618Y0260169D01*
+X0280724Y0260043D01*
+X0280826Y0259915D01*
+X0280926Y0259784D01*
+X0281022Y0259651D01*
+X0281115Y0259515D01*
+X0281205Y0259378D01*
+X0281291Y0259238D01*
+X0281373Y0259096D01*
+X0281453Y0258952D01*
+X0281528Y0258806D01*
+X0281600Y0258659D01*
+X0281669Y0258509D01*
+X0281734Y0258358D01*
+X0281795Y0258206D01*
+X0281852Y0258052D01*
+X0281905Y0257896D01*
+X0281955Y0257740D01*
+X0282001Y0257582D01*
+X0282042Y0257423D01*
+X0282080Y0257263D01*
+X0282114Y0257103D01*
+X0282144Y0256941D01*
+X0282171Y0256779D01*
+X0282193Y0256616D01*
+X0282211Y0256453D01*
+X0282225Y0256289D01*
+X0282235Y0256125D01*
+X0282241Y0255961D01*
+X0282243Y0255797D01*
+X0282241Y0255633D01*
+X0282235Y0255469D01*
+X0282225Y0255305D01*
+X0282211Y0255141D01*
+X0282193Y0254978D01*
+X0282171Y0254815D01*
+X0282144Y0254653D01*
+X0282114Y0254491D01*
+X0282080Y0254331D01*
+X0282042Y0254171D01*
+X0282001Y0254012D01*
+X0281955Y0253854D01*
+X0281905Y0253698D01*
+X0281852Y0253542D01*
+X0281795Y0253388D01*
+X0281734Y0253236D01*
+X0281669Y0253085D01*
+X0281600Y0252935D01*
+X0281528Y0252788D01*
+X0281453Y0252642D01*
+X0281373Y0252498D01*
+X0281291Y0252356D01*
+X0281205Y0252216D01*
+X0281115Y0252079D01*
+X0281022Y0251943D01*
+X0280926Y0251810D01*
+X0280826Y0251679D01*
+X0280724Y0251551D01*
+X0280618Y0251425D01*
+X0280509Y0251302D01*
+X0280397Y0251182D01*
+X0280283Y0251064D01*
+X0280165Y0250950D01*
+X0280045Y0250838D01*
+X0279922Y0250729D01*
+X0279796Y0250623D01*
+X0279668Y0250521D01*
+X0279537Y0250421D01*
+X0279404Y0250325D01*
+X0279268Y0250232D01*
+X0279131Y0250142D01*
+X0278991Y0250056D01*
+X0278849Y0249974D01*
+X0278705Y0249894D01*
+X0278559Y0249819D01*
+X0278412Y0249747D01*
+X0278262Y0249678D01*
+X0278111Y0249613D01*
+X0277959Y0249552D01*
+X0277805Y0249495D01*
+X0277649Y0249442D01*
+X0277493Y0249392D01*
+X0277335Y0249346D01*
+X0277176Y0249305D01*
+X0277016Y0249267D01*
+X0276856Y0249233D01*
+X0276694Y0249203D01*
+X0276532Y0249176D01*
+X0276369Y0249154D01*
+X0276206Y0249136D01*
+X0276042Y0249122D01*
+X0275878Y0249112D01*
+X0275714Y0249106D01*
+X0275550Y0249104D01*
+X0275386Y0249106D01*
+X0275222Y0249112D01*
+X0275058Y0249122D01*
+X0274894Y0249136D01*
+X0274731Y0249154D01*
+X0274568Y0249176D01*
+X0274406Y0249203D01*
+X0274244Y0249233D01*
+X0274084Y0249267D01*
+X0273924Y0249305D01*
+X0273765Y0249346D01*
+X0273607Y0249392D01*
+X0273451Y0249442D01*
+X0273295Y0249495D01*
+X0273141Y0249552D01*
+X0272989Y0249613D01*
+X0272838Y0249678D01*
+X0272688Y0249747D01*
+X0272541Y0249819D01*
+X0272395Y0249894D01*
+X0272251Y0249974D01*
+X0272109Y0250056D01*
+X0271969Y0250142D01*
+X0271832Y0250232D01*
+X0271696Y0250325D01*
+X0271563Y0250421D01*
+X0271432Y0250521D01*
+X0271304Y0250623D01*
+X0271178Y0250729D01*
+X0271055Y0250838D01*
+X0270935Y0250950D01*
+X0270817Y0251064D01*
+X0270703Y0251182D01*
+X0270591Y0251302D01*
+X0270482Y0251425D01*
+X0270376Y0251551D01*
+X0270274Y0251679D01*
+X0270174Y0251810D01*
+X0270078Y0251943D01*
+X0269985Y0252079D01*
+X0269895Y0252216D01*
+X0269809Y0252356D01*
+X0269727Y0252498D01*
+X0269647Y0252642D01*
+X0269572Y0252788D01*
+X0269500Y0252935D01*
+X0269431Y0253085D01*
+X0269366Y0253236D01*
+X0269305Y0253388D01*
+X0269248Y0253542D01*
+X0269195Y0253698D01*
+X0269145Y0253854D01*
+X0269099Y0254012D01*
+X0269058Y0254171D01*
+X0269020Y0254331D01*
+X0268986Y0254491D01*
+X0268956Y0254653D01*
+X0268929Y0254815D01*
+X0268907Y0254978D01*
+X0268889Y0255141D01*
+X0268875Y0255305D01*
+X0268865Y0255469D01*
+X0268859Y0255633D01*
+X0268857Y0255797D01*
+X0163070Y0139547D02*
+X0163072Y0139731D01*
+X0163079Y0139914D01*
+X0163090Y0140097D01*
+X0163106Y0140280D01*
+X0163126Y0140463D01*
+X0163151Y0140645D01*
+X0163180Y0140826D01*
+X0163214Y0141006D01*
+X0163252Y0141186D01*
+X0163294Y0141364D01*
+X0163341Y0141542D01*
+X0163392Y0141718D01*
+X0163448Y0141893D01*
+X0163507Y0142067D01*
+X0163571Y0142239D01*
+X0163639Y0142409D01*
+X0163712Y0142578D01*
+X0163788Y0142745D01*
+X0163869Y0142910D01*
+X0163953Y0143073D01*
+X0164042Y0143234D01*
+X0164134Y0143392D01*
+X0164230Y0143549D01*
+X0164331Y0143703D01*
+X0164434Y0143854D01*
+X0164542Y0144003D01*
+X0164653Y0144149D01*
+X0164768Y0144292D01*
+X0164886Y0144433D01*
+X0165008Y0144570D01*
+X0165133Y0144705D01*
+X0165261Y0144836D01*
+X0165392Y0144964D01*
+X0165527Y0145089D01*
+X0165664Y0145211D01*
+X0165805Y0145329D01*
+X0165948Y0145444D01*
+X0166094Y0145555D01*
+X0166243Y0145663D01*
+X0166394Y0145766D01*
+X0166548Y0145867D01*
+X0166705Y0145963D01*
+X0166863Y0146055D01*
+X0167024Y0146144D01*
+X0167187Y0146228D01*
+X0167352Y0146309D01*
+X0167519Y0146385D01*
+X0167688Y0146458D01*
+X0167858Y0146526D01*
+X0168030Y0146590D01*
+X0168204Y0146649D01*
+X0168379Y0146705D01*
+X0168555Y0146756D01*
+X0168733Y0146803D01*
+X0168911Y0146845D01*
+X0169091Y0146883D01*
+X0169271Y0146917D01*
+X0169452Y0146946D01*
+X0169634Y0146971D01*
+X0169817Y0146991D01*
+X0170000Y0147007D01*
+X0170183Y0147018D01*
+X0170366Y0147025D01*
+X0170550Y0147027D01*
+X0170734Y0147025D01*
+X0170917Y0147018D01*
+X0171100Y0147007D01*
+X0171283Y0146991D01*
+X0171466Y0146971D01*
+X0171648Y0146946D01*
+X0171829Y0146917D01*
+X0172009Y0146883D01*
+X0172189Y0146845D01*
+X0172367Y0146803D01*
+X0172545Y0146756D01*
+X0172721Y0146705D01*
+X0172896Y0146649D01*
+X0173070Y0146590D01*
+X0173242Y0146526D01*
+X0173412Y0146458D01*
+X0173581Y0146385D01*
+X0173748Y0146309D01*
+X0173913Y0146228D01*
+X0174076Y0146144D01*
+X0174237Y0146055D01*
+X0174395Y0145963D01*
+X0174552Y0145867D01*
+X0174706Y0145766D01*
+X0174857Y0145663D01*
+X0175006Y0145555D01*
+X0175152Y0145444D01*
+X0175295Y0145329D01*
+X0175436Y0145211D01*
+X0175573Y0145089D01*
+X0175708Y0144964D01*
+X0175839Y0144836D01*
+X0175967Y0144705D01*
+X0176092Y0144570D01*
+X0176214Y0144433D01*
+X0176332Y0144292D01*
+X0176447Y0144149D01*
+X0176558Y0144003D01*
+X0176666Y0143854D01*
+X0176769Y0143703D01*
+X0176870Y0143549D01*
+X0176966Y0143392D01*
+X0177058Y0143234D01*
+X0177147Y0143073D01*
+X0177231Y0142910D01*
+X0177312Y0142745D01*
+X0177388Y0142578D01*
+X0177461Y0142409D01*
+X0177529Y0142239D01*
+X0177593Y0142067D01*
+X0177652Y0141893D01*
+X0177708Y0141718D01*
+X0177759Y0141542D01*
+X0177806Y0141364D01*
+X0177848Y0141186D01*
+X0177886Y0141006D01*
+X0177920Y0140826D01*
+X0177949Y0140645D01*
+X0177974Y0140463D01*
+X0177994Y0140280D01*
+X0178010Y0140097D01*
+X0178021Y0139914D01*
+X0178028Y0139731D01*
+X0178030Y0139547D01*
+X0178028Y0139363D01*
+X0178021Y0139180D01*
+X0178010Y0138997D01*
+X0177994Y0138814D01*
+X0177974Y0138631D01*
+X0177949Y0138449D01*
+X0177920Y0138268D01*
+X0177886Y0138088D01*
+X0177848Y0137908D01*
+X0177806Y0137730D01*
+X0177759Y0137552D01*
+X0177708Y0137376D01*
+X0177652Y0137201D01*
+X0177593Y0137027D01*
+X0177529Y0136855D01*
+X0177461Y0136685D01*
+X0177388Y0136516D01*
+X0177312Y0136349D01*
+X0177231Y0136184D01*
+X0177147Y0136021D01*
+X0177058Y0135860D01*
+X0176966Y0135702D01*
+X0176870Y0135545D01*
+X0176769Y0135391D01*
+X0176666Y0135240D01*
+X0176558Y0135091D01*
+X0176447Y0134945D01*
+X0176332Y0134802D01*
+X0176214Y0134661D01*
+X0176092Y0134524D01*
+X0175967Y0134389D01*
+X0175839Y0134258D01*
+X0175708Y0134130D01*
+X0175573Y0134005D01*
+X0175436Y0133883D01*
+X0175295Y0133765D01*
+X0175152Y0133650D01*
+X0175006Y0133539D01*
+X0174857Y0133431D01*
+X0174706Y0133328D01*
+X0174552Y0133227D01*
+X0174395Y0133131D01*
+X0174237Y0133039D01*
+X0174076Y0132950D01*
+X0173913Y0132866D01*
+X0173748Y0132785D01*
+X0173581Y0132709D01*
+X0173412Y0132636D01*
+X0173242Y0132568D01*
+X0173070Y0132504D01*
+X0172896Y0132445D01*
+X0172721Y0132389D01*
+X0172545Y0132338D01*
+X0172367Y0132291D01*
+X0172189Y0132249D01*
+X0172009Y0132211D01*
+X0171829Y0132177D01*
+X0171648Y0132148D01*
+X0171466Y0132123D01*
+X0171283Y0132103D01*
+X0171100Y0132087D01*
+X0170917Y0132076D01*
+X0170734Y0132069D01*
+X0170550Y0132067D01*
+X0170366Y0132069D01*
+X0170183Y0132076D01*
+X0170000Y0132087D01*
+X0169817Y0132103D01*
+X0169634Y0132123D01*
+X0169452Y0132148D01*
+X0169271Y0132177D01*
+X0169091Y0132211D01*
+X0168911Y0132249D01*
+X0168733Y0132291D01*
+X0168555Y0132338D01*
+X0168379Y0132389D01*
+X0168204Y0132445D01*
+X0168030Y0132504D01*
+X0167858Y0132568D01*
+X0167688Y0132636D01*
+X0167519Y0132709D01*
+X0167352Y0132785D01*
+X0167187Y0132866D01*
+X0167024Y0132950D01*
+X0166863Y0133039D01*
+X0166705Y0133131D01*
+X0166548Y0133227D01*
+X0166394Y0133328D01*
+X0166243Y0133431D01*
+X0166094Y0133539D01*
+X0165948Y0133650D01*
+X0165805Y0133765D01*
+X0165664Y0133883D01*
+X0165527Y0134005D01*
+X0165392Y0134130D01*
+X0165261Y0134258D01*
+X0165133Y0134389D01*
+X0165008Y0134524D01*
+X0164886Y0134661D01*
+X0164768Y0134802D01*
+X0164653Y0134945D01*
+X0164542Y0135091D01*
+X0164434Y0135240D01*
+X0164331Y0135391D01*
+X0164230Y0135545D01*
+X0164134Y0135702D01*
+X0164042Y0135860D01*
+X0163953Y0136021D01*
+X0163869Y0136184D01*
+X0163788Y0136349D01*
+X0163712Y0136516D01*
+X0163639Y0136685D01*
+X0163571Y0136855D01*
+X0163507Y0137027D01*
+X0163448Y0137201D01*
+X0163392Y0137376D01*
+X0163341Y0137552D01*
+X0163294Y0137730D01*
+X0163252Y0137908D01*
+X0163214Y0138088D01*
+X0163180Y0138268D01*
+X0163151Y0138449D01*
+X0163126Y0138631D01*
+X0163106Y0138814D01*
+X0163090Y0138997D01*
+X0163079Y0139180D01*
+X0163072Y0139363D01*
+X0163070Y0139547D01*
+X0228450Y0128455D02*
+X0228450Y0124366D01*
+X0237650Y0124366D01*
+X0237650Y0128455D01*
+X0235094Y0131207D02*
+X0231006Y0131207D01*
+X0231006Y0131206D02*
+X0230906Y0131208D01*
+X0230805Y0131214D01*
+X0230706Y0131224D01*
+X0230606Y0131237D01*
+X0230507Y0131255D01*
+X0230409Y0131277D01*
+X0230312Y0131302D01*
+X0230216Y0131331D01*
+X0230121Y0131364D01*
+X0230028Y0131401D01*
+X0229936Y0131441D01*
+X0229846Y0131485D01*
+X0229757Y0131532D01*
+X0229670Y0131583D01*
+X0229586Y0131637D01*
+X0229504Y0131694D01*
+X0229424Y0131755D01*
+X0229346Y0131818D01*
+X0229271Y0131885D01*
+X0229199Y0131955D01*
+X0229129Y0132027D01*
+X0229062Y0132102D01*
+X0228999Y0132180D01*
+X0228938Y0132260D01*
+X0228881Y0132342D01*
+X0228827Y0132426D01*
+X0228776Y0132513D01*
+X0228729Y0132602D01*
+X0228685Y0132692D01*
+X0228645Y0132784D01*
+X0228608Y0132877D01*
+X0228575Y0132972D01*
+X0228546Y0133068D01*
+X0228521Y0133165D01*
+X0228499Y0133263D01*
+X0228481Y0133362D01*
+X0228468Y0133462D01*
+X0228458Y0133561D01*
+X0228452Y0133662D01*
+X0228450Y0133762D01*
+X0228452Y0133862D01*
+X0228458Y0133963D01*
+X0228468Y0134062D01*
+X0228481Y0134162D01*
+X0228499Y0134261D01*
+X0228521Y0134359D01*
+X0228546Y0134456D01*
+X0228575Y0134552D01*
+X0228608Y0134647D01*
+X0228645Y0134740D01*
+X0228685Y0134832D01*
+X0228729Y0134922D01*
+X0228776Y0135011D01*
+X0228827Y0135098D01*
+X0228881Y0135182D01*
+X0228938Y0135264D01*
+X0228999Y0135344D01*
+X0229062Y0135422D01*
+X0229129Y0135497D01*
+X0229199Y0135569D01*
+X0229271Y0135639D01*
+X0229346Y0135706D01*
+X0229424Y0135769D01*
+X0229504Y0135830D01*
+X0229586Y0135887D01*
+X0229670Y0135941D01*
+X0229757Y0135992D01*
+X0229846Y0136039D01*
+X0229936Y0136083D01*
+X0230028Y0136123D01*
+X0230121Y0136160D01*
+X0230216Y0136193D01*
+X0230312Y0136222D01*
+X0230409Y0136247D01*
+X0230507Y0136269D01*
+X0230606Y0136287D01*
+X0230706Y0136300D01*
+X0230805Y0136310D01*
+X0230906Y0136316D01*
+X0231006Y0136318D01*
+X0235094Y0136318D01*
+X0235194Y0136316D01*
+X0235295Y0136310D01*
+X0235394Y0136300D01*
+X0235494Y0136287D01*
+X0235593Y0136269D01*
+X0235691Y0136247D01*
+X0235788Y0136222D01*
+X0235884Y0136193D01*
+X0235979Y0136160D01*
+X0236072Y0136123D01*
+X0236164Y0136083D01*
+X0236254Y0136039D01*
+X0236343Y0135992D01*
+X0236430Y0135941D01*
+X0236514Y0135887D01*
+X0236596Y0135830D01*
+X0236676Y0135769D01*
+X0236754Y0135706D01*
+X0236829Y0135639D01*
+X0236901Y0135569D01*
+X0236971Y0135497D01*
+X0237038Y0135422D01*
+X0237101Y0135344D01*
+X0237162Y0135264D01*
+X0237219Y0135182D01*
+X0237273Y0135098D01*
+X0237324Y0135011D01*
+X0237371Y0134922D01*
+X0237415Y0134832D01*
+X0237455Y0134740D01*
+X0237492Y0134647D01*
+X0237525Y0134552D01*
+X0237554Y0134456D01*
+X0237579Y0134359D01*
+X0237601Y0134261D01*
+X0237619Y0134162D01*
+X0237632Y0134062D01*
+X0237642Y0133963D01*
+X0237648Y0133862D01*
+X0237650Y0133762D01*
+X0237648Y0133662D01*
+X0237642Y0133561D01*
+X0237632Y0133462D01*
+X0237619Y0133362D01*
+X0237601Y0133263D01*
+X0237579Y0133165D01*
+X0237554Y0133068D01*
+X0237525Y0132972D01*
+X0237492Y0132877D01*
+X0237455Y0132784D01*
+X0237415Y0132692D01*
+X0237371Y0132602D01*
+X0237324Y0132513D01*
+X0237273Y0132426D01*
+X0237219Y0132342D01*
+X0237162Y0132260D01*
+X0237101Y0132180D01*
+X0237038Y0132102D01*
+X0236971Y0132027D01*
+X0236901Y0131955D01*
+X0236829Y0131885D01*
+X0236754Y0131818D01*
+X0236676Y0131755D01*
+X0236596Y0131694D01*
+X0236514Y0131637D01*
+X0236430Y0131583D01*
+X0236343Y0131532D01*
+X0236254Y0131485D01*
+X0236164Y0131441D01*
+X0236072Y0131401D01*
+X0235979Y0131364D01*
+X0235884Y0131331D01*
+X0235788Y0131302D01*
+X0235691Y0131277D01*
+X0235593Y0131255D01*
+X0235494Y0131237D01*
+X0235394Y0131224D01*
+X0235295Y0131214D01*
+X0235194Y0131208D01*
+X0235094Y0131206D01*
+X0232539Y0127433D02*
+X0232539Y0124366D01*
+X0237650Y0121331D02*
+X0237650Y0117242D01*
+X0228450Y0117242D01*
+X0228450Y0114188D02*
+X0228450Y0112144D01*
+X0228452Y0112055D01*
+X0228458Y0111966D01*
+X0228467Y0111877D01*
+X0228481Y0111789D01*
+X0228498Y0111702D01*
+X0228520Y0111615D01*
+X0228545Y0111529D01*
+X0228573Y0111445D01*
+X0228606Y0111362D01*
+X0228642Y0111280D01*
+X0228681Y0111200D01*
+X0228724Y0111122D01*
+X0228770Y0111046D01*
+X0228820Y0110972D01*
+X0228872Y0110900D01*
+X0228928Y0110830D01*
+X0228987Y0110763D01*
+X0229049Y0110699D01*
+X0229113Y0110637D01*
+X0229180Y0110578D01*
+X0229250Y0110522D01*
+X0229322Y0110470D01*
+X0229396Y0110420D01*
+X0229472Y0110374D01*
+X0229550Y0110331D01*
+X0229630Y0110292D01*
+X0229712Y0110256D01*
+X0229795Y0110223D01*
+X0229879Y0110195D01*
+X0229965Y0110170D01*
+X0230052Y0110148D01*
+X0230139Y0110131D01*
+X0230227Y0110117D01*
+X0230316Y0110108D01*
+X0230405Y0110102D01*
+X0230494Y0110100D01*
+X0230494Y0110099D02*
+X0235606Y0110099D01*
+X0235606Y0110100D02*
+X0235695Y0110102D01*
+X0235784Y0110108D01*
+X0235873Y0110117D01*
+X0235961Y0110131D01*
+X0236048Y0110148D01*
+X0236135Y0110170D01*
+X0236221Y0110195D01*
+X0236305Y0110223D01*
+X0236388Y0110256D01*
+X0236470Y0110292D01*
+X0236550Y0110331D01*
+X0236628Y0110374D01*
+X0236704Y0110420D01*
+X0236778Y0110470D01*
+X0236850Y0110522D01*
+X0236920Y0110578D01*
+X0236987Y0110637D01*
+X0237051Y0110699D01*
+X0237113Y0110763D01*
+X0237172Y0110830D01*
+X0237228Y0110900D01*
+X0237280Y0110972D01*
+X0237330Y0111046D01*
+X0237376Y0111122D01*
+X0237419Y0111200D01*
+X0237458Y0111280D01*
+X0237494Y0111362D01*
+X0237527Y0111445D01*
+X0237555Y0111529D01*
+X0237580Y0111615D01*
+X0237602Y0111702D01*
+X0237619Y0111789D01*
+X0237633Y0111877D01*
+X0237642Y0111966D01*
+X0237648Y0112055D01*
+X0237650Y0112144D01*
+X0237650Y0114188D01*
+X0243450Y0110974D02*
+X0243450Y0107907D01*
+X0243450Y0110974D02*
+X0243452Y0111063D01*
+X0243458Y0111152D01*
+X0243467Y0111241D01*
+X0243481Y0111329D01*
+X0243498Y0111416D01*
+X0243520Y0111503D01*
+X0243545Y0111589D01*
+X0243573Y0111673D01*
+X0243606Y0111756D01*
+X0243642Y0111838D01*
+X0243681Y0111918D01*
+X0243724Y0111996D01*
+X0243770Y0112072D01*
+X0243820Y0112146D01*
+X0243872Y0112218D01*
+X0243928Y0112288D01*
+X0243987Y0112355D01*
+X0244049Y0112419D01*
+X0244113Y0112481D01*
+X0244180Y0112540D01*
+X0244250Y0112596D01*
+X0244322Y0112648D01*
+X0244396Y0112698D01*
+X0244472Y0112744D01*
+X0244550Y0112787D01*
+X0244630Y0112826D01*
+X0244712Y0112862D01*
+X0244795Y0112895D01*
+X0244879Y0112923D01*
+X0244965Y0112948D01*
+X0245052Y0112970D01*
+X0245139Y0112987D01*
+X0245227Y0113001D01*
+X0245316Y0113010D01*
+X0245405Y0113016D01*
+X0245494Y0113018D01*
+X0245583Y0113016D01*
+X0245672Y0113010D01*
+X0245761Y0113001D01*
+X0245849Y0112987D01*
+X0245936Y0112970D01*
+X0246023Y0112948D01*
+X0246109Y0112923D01*
+X0246193Y0112895D01*
+X0246276Y0112862D01*
+X0246358Y0112826D01*
+X0246438Y0112787D01*
+X0246516Y0112744D01*
+X0246592Y0112698D01*
+X0246666Y0112648D01*
+X0246738Y0112596D01*
+X0246808Y0112540D01*
+X0246875Y0112481D01*
+X0246939Y0112419D01*
+X0247001Y0112355D01*
+X0247060Y0112288D01*
+X0247116Y0112218D01*
+X0247168Y0112146D01*
+X0247218Y0112072D01*
+X0247264Y0111996D01*
+X0247307Y0111918D01*
+X0247346Y0111838D01*
+X0247382Y0111756D01*
+X0247415Y0111673D01*
+X0247443Y0111589D01*
+X0247468Y0111503D01*
+X0247490Y0111416D01*
+X0247507Y0111329D01*
+X0247521Y0111241D01*
+X0247530Y0111152D01*
+X0247536Y0111063D01*
+X0247538Y0110974D01*
+X0247539Y0110974D02*
+X0247539Y0108929D01*
+X0247538Y0110463D02*
+X0247540Y0110563D01*
+X0247546Y0110664D01*
+X0247556Y0110763D01*
+X0247569Y0110863D01*
+X0247587Y0110962D01*
+X0247609Y0111060D01*
+X0247634Y0111157D01*
+X0247663Y0111253D01*
+X0247696Y0111348D01*
+X0247733Y0111441D01*
+X0247773Y0111533D01*
+X0247817Y0111623D01*
+X0247864Y0111712D01*
+X0247915Y0111799D01*
+X0247969Y0111883D01*
+X0248026Y0111965D01*
+X0248087Y0112045D01*
+X0248150Y0112123D01*
+X0248217Y0112198D01*
+X0248287Y0112270D01*
+X0248359Y0112340D01*
+X0248434Y0112407D01*
+X0248512Y0112470D01*
+X0248592Y0112531D01*
+X0248674Y0112588D01*
+X0248758Y0112642D01*
+X0248845Y0112693D01*
+X0248934Y0112740D01*
+X0249024Y0112784D01*
+X0249116Y0112824D01*
+X0249209Y0112861D01*
+X0249304Y0112894D01*
+X0249400Y0112923D01*
+X0249497Y0112948D01*
+X0249595Y0112970D01*
+X0249694Y0112988D01*
+X0249794Y0113001D01*
+X0249893Y0113011D01*
+X0249994Y0113017D01*
+X0250094Y0113019D01*
+X0250194Y0113017D01*
+X0250295Y0113011D01*
+X0250394Y0113001D01*
+X0250494Y0112988D01*
+X0250593Y0112970D01*
+X0250691Y0112948D01*
+X0250788Y0112923D01*
+X0250884Y0112894D01*
+X0250979Y0112861D01*
+X0251072Y0112824D01*
+X0251164Y0112784D01*
+X0251254Y0112740D01*
+X0251343Y0112693D01*
+X0251430Y0112642D01*
+X0251514Y0112588D01*
+X0251596Y0112531D01*
+X0251676Y0112470D01*
+X0251754Y0112407D01*
+X0251829Y0112340D01*
+X0251901Y0112270D01*
+X0251971Y0112198D01*
+X0252038Y0112123D01*
+X0252101Y0112045D01*
+X0252162Y0111965D01*
+X0252219Y0111883D01*
+X0252273Y0111799D01*
+X0252324Y0111712D01*
+X0252371Y0111623D01*
+X0252415Y0111533D01*
+X0252455Y0111441D01*
+X0252492Y0111348D01*
+X0252525Y0111253D01*
+X0252554Y0111157D01*
+X0252579Y0111060D01*
+X0252601Y0110962D01*
+X0252619Y0110863D01*
+X0252632Y0110763D01*
+X0252642Y0110664D01*
+X0252648Y0110563D01*
+X0252650Y0110463D01*
+X0252650Y0107907D01*
+X0250606Y0104798D02*
+X0250606Y0099687D01*
+X0243450Y0101732D01*
+X0248561Y0103265D02*
+X0252650Y0103265D01*
+X0252650Y0096936D02*
+X0252650Y0092847D01*
+X0243450Y0092847D01*
+X0237650Y0092847D02*
+X0228450Y0092847D01*
+X0237650Y0097958D01*
+X0228450Y0097958D01*
+X0228450Y0101615D02*
+X0235094Y0101615D01*
+X0235094Y0101614D02*
+X0235194Y0101616D01*
+X0235295Y0101622D01*
+X0235394Y0101632D01*
+X0235494Y0101645D01*
+X0235593Y0101663D01*
+X0235691Y0101685D01*
+X0235788Y0101710D01*
+X0235884Y0101739D01*
+X0235979Y0101772D01*
+X0236072Y0101809D01*
+X0236164Y0101849D01*
+X0236254Y0101893D01*
+X0236343Y0101940D01*
+X0236430Y0101991D01*
+X0236514Y0102045D01*
+X0236596Y0102102D01*
+X0236676Y0102163D01*
+X0236754Y0102226D01*
+X0236829Y0102293D01*
+X0236901Y0102363D01*
+X0236971Y0102435D01*
+X0237038Y0102510D01*
+X0237101Y0102588D01*
+X0237162Y0102668D01*
+X0237219Y0102750D01*
+X0237273Y0102834D01*
+X0237324Y0102921D01*
+X0237371Y0103010D01*
+X0237415Y0103100D01*
+X0237455Y0103192D01*
+X0237492Y0103285D01*
+X0237525Y0103380D01*
+X0237554Y0103476D01*
+X0237579Y0103573D01*
+X0237601Y0103671D01*
+X0237619Y0103770D01*
+X0237632Y0103870D01*
+X0237642Y0103969D01*
+X0237648Y0104070D01*
+X0237650Y0104170D01*
+X0237648Y0104270D01*
+X0237642Y0104371D01*
+X0237632Y0104470D01*
+X0237619Y0104570D01*
+X0237601Y0104669D01*
+X0237579Y0104767D01*
+X0237554Y0104864D01*
+X0237525Y0104960D01*
+X0237492Y0105055D01*
+X0237455Y0105148D01*
+X0237415Y0105240D01*
+X0237371Y0105330D01*
+X0237324Y0105419D01*
+X0237273Y0105506D01*
+X0237219Y0105590D01*
+X0237162Y0105672D01*
+X0237101Y0105752D01*
+X0237038Y0105830D01*
+X0236971Y0105905D01*
+X0236901Y0105977D01*
+X0236829Y0106047D01*
+X0236754Y0106114D01*
+X0236676Y0106177D01*
+X0236596Y0106238D01*
+X0236514Y0106295D01*
+X0236430Y0106349D01*
+X0236343Y0106400D01*
+X0236254Y0106447D01*
+X0236164Y0106491D01*
+X0236072Y0106531D01*
+X0235979Y0106568D01*
+X0235884Y0106601D01*
+X0235788Y0106630D01*
+X0235691Y0106655D01*
+X0235593Y0106677D01*
+X0235494Y0106695D01*
+X0235394Y0106708D01*
+X0235295Y0106718D01*
+X0235194Y0106724D01*
+X0235094Y0106726D01*
+X0228450Y0106726D01*
+X0245750Y0121238D02*
+X0245845Y0121236D01*
+X0245940Y0121231D01*
+X0246035Y0121221D01*
+X0246129Y0121209D01*
+X0246223Y0121192D01*
+X0246316Y0121172D01*
+X0246409Y0121149D01*
+X0246500Y0121121D01*
+X0246590Y0121091D01*
+X0246679Y0121057D01*
+X0246767Y0121019D01*
+X0246853Y0120978D01*
+X0246937Y0120934D01*
+X0247020Y0120887D01*
+X0247100Y0120836D01*
+X0247179Y0120783D01*
+X0247256Y0120726D01*
+X0247330Y0120667D01*
+X0247402Y0120604D01*
+X0247472Y0120539D01*
+X0247539Y0120471D01*
+X0247539Y0120472D02*
+X0252650Y0116127D01*
+X0252650Y0121238D01*
+X0252650Y0124679D02*
+X0243450Y0124679D01*
+X0247028Y0126724D02*
+X0252650Y0129790D01*
+X0250606Y0132558D02*
+X0245494Y0132558D01*
+X0245405Y0132560D01*
+X0245316Y0132566D01*
+X0245227Y0132575D01*
+X0245139Y0132589D01*
+X0245052Y0132606D01*
+X0244965Y0132628D01*
+X0244879Y0132653D01*
+X0244795Y0132681D01*
+X0244712Y0132714D01*
+X0244630Y0132750D01*
+X0244550Y0132789D01*
+X0244472Y0132832D01*
+X0244396Y0132878D01*
+X0244322Y0132928D01*
+X0244250Y0132980D01*
+X0244180Y0133036D01*
+X0244113Y0133095D01*
+X0244049Y0133157D01*
+X0243987Y0133221D01*
+X0243928Y0133288D01*
+X0243872Y0133358D01*
+X0243820Y0133430D01*
+X0243770Y0133504D01*
+X0243724Y0133580D01*
+X0243681Y0133658D01*
+X0243642Y0133738D01*
+X0243606Y0133820D01*
+X0243573Y0133903D01*
+X0243545Y0133987D01*
+X0243520Y0134073D01*
+X0243498Y0134160D01*
+X0243481Y0134247D01*
+X0243467Y0134335D01*
+X0243458Y0134424D01*
+X0243452Y0134513D01*
+X0243450Y0134602D01*
+X0243450Y0136647D01*
+X0250606Y0132558D02*
+X0250695Y0132560D01*
+X0250784Y0132566D01*
+X0250873Y0132575D01*
+X0250961Y0132589D01*
+X0251048Y0132606D01*
+X0251135Y0132628D01*
+X0251221Y0132653D01*
+X0251305Y0132681D01*
+X0251388Y0132714D01*
+X0251470Y0132750D01*
+X0251550Y0132789D01*
+X0251628Y0132832D01*
+X0251704Y0132878D01*
+X0251778Y0132928D01*
+X0251850Y0132980D01*
+X0251920Y0133036D01*
+X0251987Y0133095D01*
+X0252051Y0133157D01*
+X0252113Y0133221D01*
+X0252172Y0133288D01*
+X0252228Y0133358D01*
+X0252280Y0133430D01*
+X0252330Y0133504D01*
+X0252376Y0133580D01*
+X0252419Y0133658D01*
+X0252458Y0133738D01*
+X0252494Y0133820D01*
+X0252527Y0133903D01*
+X0252555Y0133987D01*
+X0252580Y0134073D01*
+X0252602Y0134160D01*
+X0252619Y0134247D01*
+X0252633Y0134335D01*
+X0252642Y0134424D01*
+X0252648Y0134513D01*
+X0252650Y0134602D01*
+X0252650Y0136647D01*
+X0243450Y0129790D02*
+X0249072Y0124679D01*
+X0243450Y0118938D02*
+X0243452Y0118832D01*
+X0243458Y0118726D01*
+X0243467Y0118620D01*
+X0243480Y0118515D01*
+X0243498Y0118410D01*
+X0243518Y0118306D01*
+X0243543Y0118203D01*
+X0243571Y0118100D01*
+X0243603Y0117999D01*
+X0243639Y0117899D01*
+X0243678Y0117800D01*
+X0243720Y0117703D01*
+X0243767Y0117607D01*
+X0243816Y0117513D01*
+X0243869Y0117421D01*
+X0243925Y0117331D01*
+X0243984Y0117243D01*
+X0244047Y0117157D01*
+X0244112Y0117074D01*
+X0244181Y0116993D01*
+X0244252Y0116914D01*
+X0244326Y0116838D01*
+X0244403Y0116765D01*
+X0244482Y0116694D01*
+X0244564Y0116626D01*
+X0244648Y0116562D01*
+X0244735Y0116500D01*
+X0244824Y0116442D01*
+X0244914Y0116387D01*
+X0245007Y0116335D01*
+X0245101Y0116286D01*
+X0245197Y0116241D01*
+X0245295Y0116199D01*
+X0245394Y0116161D01*
+X0245495Y0116127D01*
+X0243450Y0118938D02*
+X0243452Y0119033D01*
+X0243458Y0119128D01*
+X0243468Y0119222D01*
+X0243481Y0119317D01*
+X0243499Y0119410D01*
+X0243520Y0119503D01*
+X0243546Y0119594D01*
+X0243575Y0119685D01*
+X0243607Y0119774D01*
+X0243644Y0119862D01*
+X0243684Y0119948D01*
+X0243727Y0120033D01*
+X0243774Y0120115D01*
+X0243825Y0120196D01*
+X0243878Y0120274D01*
+X0243935Y0120351D01*
+X0243995Y0120424D01*
+X0244058Y0120496D01*
+X0244124Y0120564D01*
+X0244192Y0120630D01*
+X0244264Y0120693D01*
+X0244337Y0120753D01*
+X0244414Y0120810D01*
+X0244492Y0120863D01*
+X0244573Y0120914D01*
+X0244655Y0120961D01*
+X0244740Y0121004D01*
+X0244826Y0121044D01*
+X0244914Y0121081D01*
+X0245003Y0121113D01*
+X0245094Y0121142D01*
+X0245185Y0121168D01*
+X0245278Y0121189D01*
+X0245371Y0121207D01*
+X0245466Y0121220D01*
+X0245560Y0121230D01*
+X0245655Y0121236D01*
+X0245750Y0121238D01*
+X0338070Y0029547D02*
+X0338072Y0029731D01*
+X0338079Y0029914D01*
+X0338090Y0030097D01*
+X0338106Y0030280D01*
+X0338126Y0030463D01*
+X0338151Y0030645D01*
+X0338180Y0030826D01*
+X0338214Y0031006D01*
+X0338252Y0031186D01*
+X0338294Y0031364D01*
+X0338341Y0031542D01*
+X0338392Y0031718D01*
+X0338448Y0031893D01*
+X0338507Y0032067D01*
+X0338571Y0032239D01*
+X0338639Y0032409D01*
+X0338712Y0032578D01*
+X0338788Y0032745D01*
+X0338869Y0032910D01*
+X0338953Y0033073D01*
+X0339042Y0033234D01*
+X0339134Y0033392D01*
+X0339230Y0033549D01*
+X0339331Y0033703D01*
+X0339434Y0033854D01*
+X0339542Y0034003D01*
+X0339653Y0034149D01*
+X0339768Y0034292D01*
+X0339886Y0034433D01*
+X0340008Y0034570D01*
+X0340133Y0034705D01*
+X0340261Y0034836D01*
+X0340392Y0034964D01*
+X0340527Y0035089D01*
+X0340664Y0035211D01*
+X0340805Y0035329D01*
+X0340948Y0035444D01*
+X0341094Y0035555D01*
+X0341243Y0035663D01*
+X0341394Y0035766D01*
+X0341548Y0035867D01*
+X0341705Y0035963D01*
+X0341863Y0036055D01*
+X0342024Y0036144D01*
+X0342187Y0036228D01*
+X0342352Y0036309D01*
+X0342519Y0036385D01*
+X0342688Y0036458D01*
+X0342858Y0036526D01*
+X0343030Y0036590D01*
+X0343204Y0036649D01*
+X0343379Y0036705D01*
+X0343555Y0036756D01*
+X0343733Y0036803D01*
+X0343911Y0036845D01*
+X0344091Y0036883D01*
+X0344271Y0036917D01*
+X0344452Y0036946D01*
+X0344634Y0036971D01*
+X0344817Y0036991D01*
+X0345000Y0037007D01*
+X0345183Y0037018D01*
+X0345366Y0037025D01*
+X0345550Y0037027D01*
+X0345734Y0037025D01*
+X0345917Y0037018D01*
+X0346100Y0037007D01*
+X0346283Y0036991D01*
+X0346466Y0036971D01*
+X0346648Y0036946D01*
+X0346829Y0036917D01*
+X0347009Y0036883D01*
+X0347189Y0036845D01*
+X0347367Y0036803D01*
+X0347545Y0036756D01*
+X0347721Y0036705D01*
+X0347896Y0036649D01*
+X0348070Y0036590D01*
+X0348242Y0036526D01*
+X0348412Y0036458D01*
+X0348581Y0036385D01*
+X0348748Y0036309D01*
+X0348913Y0036228D01*
+X0349076Y0036144D01*
+X0349237Y0036055D01*
+X0349395Y0035963D01*
+X0349552Y0035867D01*
+X0349706Y0035766D01*
+X0349857Y0035663D01*
+X0350006Y0035555D01*
+X0350152Y0035444D01*
+X0350295Y0035329D01*
+X0350436Y0035211D01*
+X0350573Y0035089D01*
+X0350708Y0034964D01*
+X0350839Y0034836D01*
+X0350967Y0034705D01*
+X0351092Y0034570D01*
+X0351214Y0034433D01*
+X0351332Y0034292D01*
+X0351447Y0034149D01*
+X0351558Y0034003D01*
+X0351666Y0033854D01*
+X0351769Y0033703D01*
+X0351870Y0033549D01*
+X0351966Y0033392D01*
+X0352058Y0033234D01*
+X0352147Y0033073D01*
+X0352231Y0032910D01*
+X0352312Y0032745D01*
+X0352388Y0032578D01*
+X0352461Y0032409D01*
+X0352529Y0032239D01*
+X0352593Y0032067D01*
+X0352652Y0031893D01*
+X0352708Y0031718D01*
+X0352759Y0031542D01*
+X0352806Y0031364D01*
+X0352848Y0031186D01*
+X0352886Y0031006D01*
+X0352920Y0030826D01*
+X0352949Y0030645D01*
+X0352974Y0030463D01*
+X0352994Y0030280D01*
+X0353010Y0030097D01*
+X0353021Y0029914D01*
+X0353028Y0029731D01*
+X0353030Y0029547D01*
+X0353028Y0029363D01*
+X0353021Y0029180D01*
+X0353010Y0028997D01*
+X0352994Y0028814D01*
+X0352974Y0028631D01*
+X0352949Y0028449D01*
+X0352920Y0028268D01*
+X0352886Y0028088D01*
+X0352848Y0027908D01*
+X0352806Y0027730D01*
+X0352759Y0027552D01*
+X0352708Y0027376D01*
+X0352652Y0027201D01*
+X0352593Y0027027D01*
+X0352529Y0026855D01*
+X0352461Y0026685D01*
+X0352388Y0026516D01*
+X0352312Y0026349D01*
+X0352231Y0026184D01*
+X0352147Y0026021D01*
+X0352058Y0025860D01*
+X0351966Y0025702D01*
+X0351870Y0025545D01*
+X0351769Y0025391D01*
+X0351666Y0025240D01*
+X0351558Y0025091D01*
+X0351447Y0024945D01*
+X0351332Y0024802D01*
+X0351214Y0024661D01*
+X0351092Y0024524D01*
+X0350967Y0024389D01*
+X0350839Y0024258D01*
+X0350708Y0024130D01*
+X0350573Y0024005D01*
+X0350436Y0023883D01*
+X0350295Y0023765D01*
+X0350152Y0023650D01*
+X0350006Y0023539D01*
+X0349857Y0023431D01*
+X0349706Y0023328D01*
+X0349552Y0023227D01*
+X0349395Y0023131D01*
+X0349237Y0023039D01*
+X0349076Y0022950D01*
+X0348913Y0022866D01*
+X0348748Y0022785D01*
+X0348581Y0022709D01*
+X0348412Y0022636D01*
+X0348242Y0022568D01*
+X0348070Y0022504D01*
+X0347896Y0022445D01*
+X0347721Y0022389D01*
+X0347545Y0022338D01*
+X0347367Y0022291D01*
+X0347189Y0022249D01*
+X0347009Y0022211D01*
+X0346829Y0022177D01*
+X0346648Y0022148D01*
+X0346466Y0022123D01*
+X0346283Y0022103D01*
+X0346100Y0022087D01*
+X0345917Y0022076D01*
+X0345734Y0022069D01*
+X0345550Y0022067D01*
+X0345366Y0022069D01*
+X0345183Y0022076D01*
+X0345000Y0022087D01*
+X0344817Y0022103D01*
+X0344634Y0022123D01*
+X0344452Y0022148D01*
+X0344271Y0022177D01*
+X0344091Y0022211D01*
+X0343911Y0022249D01*
+X0343733Y0022291D01*
+X0343555Y0022338D01*
+X0343379Y0022389D01*
+X0343204Y0022445D01*
+X0343030Y0022504D01*
+X0342858Y0022568D01*
+X0342688Y0022636D01*
+X0342519Y0022709D01*
+X0342352Y0022785D01*
+X0342187Y0022866D01*
+X0342024Y0022950D01*
+X0341863Y0023039D01*
+X0341705Y0023131D01*
+X0341548Y0023227D01*
+X0341394Y0023328D01*
+X0341243Y0023431D01*
+X0341094Y0023539D01*
+X0340948Y0023650D01*
+X0340805Y0023765D01*
+X0340664Y0023883D01*
+X0340527Y0024005D01*
+X0340392Y0024130D01*
+X0340261Y0024258D01*
+X0340133Y0024389D01*
+X0340008Y0024524D01*
+X0339886Y0024661D01*
+X0339768Y0024802D01*
+X0339653Y0024945D01*
+X0339542Y0025091D01*
+X0339434Y0025240D01*
+X0339331Y0025391D01*
+X0339230Y0025545D01*
+X0339134Y0025702D01*
+X0339042Y0025860D01*
+X0338953Y0026021D01*
+X0338869Y0026184D01*
+X0338788Y0026349D01*
+X0338712Y0026516D01*
+X0338639Y0026685D01*
+X0338571Y0026855D01*
+X0338507Y0027027D01*
+X0338448Y0027201D01*
+X0338392Y0027376D01*
+X0338341Y0027552D01*
+X0338294Y0027730D01*
+X0338252Y0027908D01*
+X0338214Y0028088D01*
+X0338180Y0028268D01*
+X0338151Y0028449D01*
+X0338126Y0028631D01*
+X0338106Y0028814D01*
+X0338090Y0028997D01*
+X0338079Y0029180D01*
+X0338072Y0029363D01*
+X0338070Y0029547D01*
+X0024320Y0029547D02*
+X0024322Y0029731D01*
+X0024329Y0029914D01*
+X0024340Y0030097D01*
+X0024356Y0030280D01*
+X0024376Y0030463D01*
+X0024401Y0030645D01*
+X0024430Y0030826D01*
+X0024464Y0031006D01*
+X0024502Y0031186D01*
+X0024544Y0031364D01*
+X0024591Y0031542D01*
+X0024642Y0031718D01*
+X0024698Y0031893D01*
+X0024757Y0032067D01*
+X0024821Y0032239D01*
+X0024889Y0032409D01*
+X0024962Y0032578D01*
+X0025038Y0032745D01*
+X0025119Y0032910D01*
+X0025203Y0033073D01*
+X0025292Y0033234D01*
+X0025384Y0033392D01*
+X0025480Y0033549D01*
+X0025581Y0033703D01*
+X0025684Y0033854D01*
+X0025792Y0034003D01*
+X0025903Y0034149D01*
+X0026018Y0034292D01*
+X0026136Y0034433D01*
+X0026258Y0034570D01*
+X0026383Y0034705D01*
+X0026511Y0034836D01*
+X0026642Y0034964D01*
+X0026777Y0035089D01*
+X0026914Y0035211D01*
+X0027055Y0035329D01*
+X0027198Y0035444D01*
+X0027344Y0035555D01*
+X0027493Y0035663D01*
+X0027644Y0035766D01*
+X0027798Y0035867D01*
+X0027955Y0035963D01*
+X0028113Y0036055D01*
+X0028274Y0036144D01*
+X0028437Y0036228D01*
+X0028602Y0036309D01*
+X0028769Y0036385D01*
+X0028938Y0036458D01*
+X0029108Y0036526D01*
+X0029280Y0036590D01*
+X0029454Y0036649D01*
+X0029629Y0036705D01*
+X0029805Y0036756D01*
+X0029983Y0036803D01*
+X0030161Y0036845D01*
+X0030341Y0036883D01*
+X0030521Y0036917D01*
+X0030702Y0036946D01*
+X0030884Y0036971D01*
+X0031067Y0036991D01*
+X0031250Y0037007D01*
+X0031433Y0037018D01*
+X0031616Y0037025D01*
+X0031800Y0037027D01*
+X0031984Y0037025D01*
+X0032167Y0037018D01*
+X0032350Y0037007D01*
+X0032533Y0036991D01*
+X0032716Y0036971D01*
+X0032898Y0036946D01*
+X0033079Y0036917D01*
+X0033259Y0036883D01*
+X0033439Y0036845D01*
+X0033617Y0036803D01*
+X0033795Y0036756D01*
+X0033971Y0036705D01*
+X0034146Y0036649D01*
+X0034320Y0036590D01*
+X0034492Y0036526D01*
+X0034662Y0036458D01*
+X0034831Y0036385D01*
+X0034998Y0036309D01*
+X0035163Y0036228D01*
+X0035326Y0036144D01*
+X0035487Y0036055D01*
+X0035645Y0035963D01*
+X0035802Y0035867D01*
+X0035956Y0035766D01*
+X0036107Y0035663D01*
+X0036256Y0035555D01*
+X0036402Y0035444D01*
+X0036545Y0035329D01*
+X0036686Y0035211D01*
+X0036823Y0035089D01*
+X0036958Y0034964D01*
+X0037089Y0034836D01*
+X0037217Y0034705D01*
+X0037342Y0034570D01*
+X0037464Y0034433D01*
+X0037582Y0034292D01*
+X0037697Y0034149D01*
+X0037808Y0034003D01*
+X0037916Y0033854D01*
+X0038019Y0033703D01*
+X0038120Y0033549D01*
+X0038216Y0033392D01*
+X0038308Y0033234D01*
+X0038397Y0033073D01*
+X0038481Y0032910D01*
+X0038562Y0032745D01*
+X0038638Y0032578D01*
+X0038711Y0032409D01*
+X0038779Y0032239D01*
+X0038843Y0032067D01*
+X0038902Y0031893D01*
+X0038958Y0031718D01*
+X0039009Y0031542D01*
+X0039056Y0031364D01*
+X0039098Y0031186D01*
+X0039136Y0031006D01*
+X0039170Y0030826D01*
+X0039199Y0030645D01*
+X0039224Y0030463D01*
+X0039244Y0030280D01*
+X0039260Y0030097D01*
+X0039271Y0029914D01*
+X0039278Y0029731D01*
+X0039280Y0029547D01*
+X0039278Y0029363D01*
+X0039271Y0029180D01*
+X0039260Y0028997D01*
+X0039244Y0028814D01*
+X0039224Y0028631D01*
+X0039199Y0028449D01*
+X0039170Y0028268D01*
+X0039136Y0028088D01*
+X0039098Y0027908D01*
+X0039056Y0027730D01*
+X0039009Y0027552D01*
+X0038958Y0027376D01*
+X0038902Y0027201D01*
+X0038843Y0027027D01*
+X0038779Y0026855D01*
+X0038711Y0026685D01*
+X0038638Y0026516D01*
+X0038562Y0026349D01*
+X0038481Y0026184D01*
+X0038397Y0026021D01*
+X0038308Y0025860D01*
+X0038216Y0025702D01*
+X0038120Y0025545D01*
+X0038019Y0025391D01*
+X0037916Y0025240D01*
+X0037808Y0025091D01*
+X0037697Y0024945D01*
+X0037582Y0024802D01*
+X0037464Y0024661D01*
+X0037342Y0024524D01*
+X0037217Y0024389D01*
+X0037089Y0024258D01*
+X0036958Y0024130D01*
+X0036823Y0024005D01*
+X0036686Y0023883D01*
+X0036545Y0023765D01*
+X0036402Y0023650D01*
+X0036256Y0023539D01*
+X0036107Y0023431D01*
+X0035956Y0023328D01*
+X0035802Y0023227D01*
+X0035645Y0023131D01*
+X0035487Y0023039D01*
+X0035326Y0022950D01*
+X0035163Y0022866D01*
+X0034998Y0022785D01*
+X0034831Y0022709D01*
+X0034662Y0022636D01*
+X0034492Y0022568D01*
+X0034320Y0022504D01*
+X0034146Y0022445D01*
+X0033971Y0022389D01*
+X0033795Y0022338D01*
+X0033617Y0022291D01*
+X0033439Y0022249D01*
+X0033259Y0022211D01*
+X0033079Y0022177D01*
+X0032898Y0022148D01*
+X0032716Y0022123D01*
+X0032533Y0022103D01*
+X0032350Y0022087D01*
+X0032167Y0022076D01*
+X0031984Y0022069D01*
+X0031800Y0022067D01*
+X0031616Y0022069D01*
+X0031433Y0022076D01*
+X0031250Y0022087D01*
+X0031067Y0022103D01*
+X0030884Y0022123D01*
+X0030702Y0022148D01*
+X0030521Y0022177D01*
+X0030341Y0022211D01*
+X0030161Y0022249D01*
+X0029983Y0022291D01*
+X0029805Y0022338D01*
+X0029629Y0022389D01*
+X0029454Y0022445D01*
+X0029280Y0022504D01*
+X0029108Y0022568D01*
+X0028938Y0022636D01*
+X0028769Y0022709D01*
+X0028602Y0022785D01*
+X0028437Y0022866D01*
+X0028274Y0022950D01*
+X0028113Y0023039D01*
+X0027955Y0023131D01*
+X0027798Y0023227D01*
+X0027644Y0023328D01*
+X0027493Y0023431D01*
+X0027344Y0023539D01*
+X0027198Y0023650D01*
+X0027055Y0023765D01*
+X0026914Y0023883D01*
+X0026777Y0024005D01*
+X0026642Y0024130D01*
+X0026511Y0024258D01*
+X0026383Y0024389D01*
+X0026258Y0024524D01*
+X0026136Y0024661D01*
+X0026018Y0024802D01*
+X0025903Y0024945D01*
+X0025792Y0025091D01*
+X0025684Y0025240D01*
+X0025581Y0025391D01*
+X0025480Y0025545D01*
+X0025384Y0025702D01*
+X0025292Y0025860D01*
+X0025203Y0026021D01*
+X0025119Y0026184D01*
+X0025038Y0026349D01*
+X0024962Y0026516D01*
+X0024889Y0026685D01*
+X0024821Y0026855D01*
+X0024757Y0027027D01*
+X0024698Y0027201D01*
+X0024642Y0027376D01*
+X0024591Y0027552D01*
+X0024544Y0027730D01*
+X0024502Y0027908D01*
+X0024464Y0028088D01*
+X0024430Y0028268D01*
+X0024401Y0028449D01*
+X0024376Y0028631D01*
+X0024356Y0028814D01*
+X0024340Y0028997D01*
+X0024329Y0029180D01*
+X0024322Y0029363D01*
+X0024320Y0029547D01*
+X0024320Y0262047D02*
+X0024322Y0262231D01*
+X0024329Y0262414D01*
+X0024340Y0262597D01*
+X0024356Y0262780D01*
+X0024376Y0262963D01*
+X0024401Y0263145D01*
+X0024430Y0263326D01*
+X0024464Y0263506D01*
+X0024502Y0263686D01*
+X0024544Y0263864D01*
+X0024591Y0264042D01*
+X0024642Y0264218D01*
+X0024698Y0264393D01*
+X0024757Y0264567D01*
+X0024821Y0264739D01*
+X0024889Y0264909D01*
+X0024962Y0265078D01*
+X0025038Y0265245D01*
+X0025119Y0265410D01*
+X0025203Y0265573D01*
+X0025292Y0265734D01*
+X0025384Y0265892D01*
+X0025480Y0266049D01*
+X0025581Y0266203D01*
+X0025684Y0266354D01*
+X0025792Y0266503D01*
+X0025903Y0266649D01*
+X0026018Y0266792D01*
+X0026136Y0266933D01*
+X0026258Y0267070D01*
+X0026383Y0267205D01*
+X0026511Y0267336D01*
+X0026642Y0267464D01*
+X0026777Y0267589D01*
+X0026914Y0267711D01*
+X0027055Y0267829D01*
+X0027198Y0267944D01*
+X0027344Y0268055D01*
+X0027493Y0268163D01*
+X0027644Y0268266D01*
+X0027798Y0268367D01*
+X0027955Y0268463D01*
+X0028113Y0268555D01*
+X0028274Y0268644D01*
+X0028437Y0268728D01*
+X0028602Y0268809D01*
+X0028769Y0268885D01*
+X0028938Y0268958D01*
+X0029108Y0269026D01*
+X0029280Y0269090D01*
+X0029454Y0269149D01*
+X0029629Y0269205D01*
+X0029805Y0269256D01*
+X0029983Y0269303D01*
+X0030161Y0269345D01*
+X0030341Y0269383D01*
+X0030521Y0269417D01*
+X0030702Y0269446D01*
+X0030884Y0269471D01*
+X0031067Y0269491D01*
+X0031250Y0269507D01*
+X0031433Y0269518D01*
+X0031616Y0269525D01*
+X0031800Y0269527D01*
+X0031984Y0269525D01*
+X0032167Y0269518D01*
+X0032350Y0269507D01*
+X0032533Y0269491D01*
+X0032716Y0269471D01*
+X0032898Y0269446D01*
+X0033079Y0269417D01*
+X0033259Y0269383D01*
+X0033439Y0269345D01*
+X0033617Y0269303D01*
+X0033795Y0269256D01*
+X0033971Y0269205D01*
+X0034146Y0269149D01*
+X0034320Y0269090D01*
+X0034492Y0269026D01*
+X0034662Y0268958D01*
+X0034831Y0268885D01*
+X0034998Y0268809D01*
+X0035163Y0268728D01*
+X0035326Y0268644D01*
+X0035487Y0268555D01*
+X0035645Y0268463D01*
+X0035802Y0268367D01*
+X0035956Y0268266D01*
+X0036107Y0268163D01*
+X0036256Y0268055D01*
+X0036402Y0267944D01*
+X0036545Y0267829D01*
+X0036686Y0267711D01*
+X0036823Y0267589D01*
+X0036958Y0267464D01*
+X0037089Y0267336D01*
+X0037217Y0267205D01*
+X0037342Y0267070D01*
+X0037464Y0266933D01*
+X0037582Y0266792D01*
+X0037697Y0266649D01*
+X0037808Y0266503D01*
+X0037916Y0266354D01*
+X0038019Y0266203D01*
+X0038120Y0266049D01*
+X0038216Y0265892D01*
+X0038308Y0265734D01*
+X0038397Y0265573D01*
+X0038481Y0265410D01*
+X0038562Y0265245D01*
+X0038638Y0265078D01*
+X0038711Y0264909D01*
+X0038779Y0264739D01*
+X0038843Y0264567D01*
+X0038902Y0264393D01*
+X0038958Y0264218D01*
+X0039009Y0264042D01*
+X0039056Y0263864D01*
+X0039098Y0263686D01*
+X0039136Y0263506D01*
+X0039170Y0263326D01*
+X0039199Y0263145D01*
+X0039224Y0262963D01*
+X0039244Y0262780D01*
+X0039260Y0262597D01*
+X0039271Y0262414D01*
+X0039278Y0262231D01*
+X0039280Y0262047D01*
+X0039278Y0261863D01*
+X0039271Y0261680D01*
+X0039260Y0261497D01*
+X0039244Y0261314D01*
+X0039224Y0261131D01*
+X0039199Y0260949D01*
+X0039170Y0260768D01*
+X0039136Y0260588D01*
+X0039098Y0260408D01*
+X0039056Y0260230D01*
+X0039009Y0260052D01*
+X0038958Y0259876D01*
+X0038902Y0259701D01*
+X0038843Y0259527D01*
+X0038779Y0259355D01*
+X0038711Y0259185D01*
+X0038638Y0259016D01*
+X0038562Y0258849D01*
+X0038481Y0258684D01*
+X0038397Y0258521D01*
+X0038308Y0258360D01*
+X0038216Y0258202D01*
+X0038120Y0258045D01*
+X0038019Y0257891D01*
+X0037916Y0257740D01*
+X0037808Y0257591D01*
+X0037697Y0257445D01*
+X0037582Y0257302D01*
+X0037464Y0257161D01*
+X0037342Y0257024D01*
+X0037217Y0256889D01*
+X0037089Y0256758D01*
+X0036958Y0256630D01*
+X0036823Y0256505D01*
+X0036686Y0256383D01*
+X0036545Y0256265D01*
+X0036402Y0256150D01*
+X0036256Y0256039D01*
+X0036107Y0255931D01*
+X0035956Y0255828D01*
+X0035802Y0255727D01*
+X0035645Y0255631D01*
+X0035487Y0255539D01*
+X0035326Y0255450D01*
+X0035163Y0255366D01*
+X0034998Y0255285D01*
+X0034831Y0255209D01*
+X0034662Y0255136D01*
+X0034492Y0255068D01*
+X0034320Y0255004D01*
+X0034146Y0254945D01*
+X0033971Y0254889D01*
+X0033795Y0254838D01*
+X0033617Y0254791D01*
+X0033439Y0254749D01*
+X0033259Y0254711D01*
+X0033079Y0254677D01*
+X0032898Y0254648D01*
+X0032716Y0254623D01*
+X0032533Y0254603D01*
+X0032350Y0254587D01*
+X0032167Y0254576D01*
+X0031984Y0254569D01*
+X0031800Y0254567D01*
+X0031616Y0254569D01*
+X0031433Y0254576D01*
+X0031250Y0254587D01*
+X0031067Y0254603D01*
+X0030884Y0254623D01*
+X0030702Y0254648D01*
+X0030521Y0254677D01*
+X0030341Y0254711D01*
+X0030161Y0254749D01*
+X0029983Y0254791D01*
+X0029805Y0254838D01*
+X0029629Y0254889D01*
+X0029454Y0254945D01*
+X0029280Y0255004D01*
+X0029108Y0255068D01*
+X0028938Y0255136D01*
+X0028769Y0255209D01*
+X0028602Y0255285D01*
+X0028437Y0255366D01*
+X0028274Y0255450D01*
+X0028113Y0255539D01*
+X0027955Y0255631D01*
+X0027798Y0255727D01*
+X0027644Y0255828D01*
+X0027493Y0255931D01*
+X0027344Y0256039D01*
+X0027198Y0256150D01*
+X0027055Y0256265D01*
+X0026914Y0256383D01*
+X0026777Y0256505D01*
+X0026642Y0256630D01*
+X0026511Y0256758D01*
+X0026383Y0256889D01*
+X0026258Y0257024D01*
+X0026136Y0257161D01*
+X0026018Y0257302D01*
+X0025903Y0257445D01*
+X0025792Y0257591D01*
+X0025684Y0257740D01*
+X0025581Y0257891D01*
+X0025480Y0258045D01*
+X0025384Y0258202D01*
+X0025292Y0258360D01*
+X0025203Y0258521D01*
+X0025119Y0258684D01*
+X0025038Y0258849D01*
+X0024962Y0259016D01*
+X0024889Y0259185D01*
+X0024821Y0259355D01*
+X0024757Y0259527D01*
+X0024698Y0259701D01*
+X0024642Y0259876D01*
+X0024591Y0260052D01*
+X0024544Y0260230D01*
+X0024502Y0260408D01*
+X0024464Y0260588D01*
+X0024430Y0260768D01*
+X0024401Y0260949D01*
+X0024376Y0261131D01*
+X0024356Y0261314D01*
+X0024340Y0261497D01*
+X0024329Y0261680D01*
+X0024322Y0261863D01*
+X0024320Y0262047D01*
+D13*
+X0072050Y0260497D02*
+X0072050Y0255997D01*
+X0074050Y0255997D01*
+X0075790Y0256997D02*
+X0078290Y0256997D01*
+X0077540Y0257997D02*
+X0077540Y0255997D01*
+X0075790Y0256997D02*
+X0076790Y0260497D01*
+X0080290Y0259247D02*
+X0080290Y0258997D01*
+X0080292Y0258937D01*
+X0080297Y0258876D01*
+X0080306Y0258817D01*
+X0080319Y0258758D01*
+X0080335Y0258699D01*
+X0080355Y0258642D01*
+X0080378Y0258587D01*
+X0080405Y0258532D01*
+X0080434Y0258480D01*
+X0080467Y0258429D01*
+X0080503Y0258380D01*
+X0080541Y0258334D01*
+X0080583Y0258290D01*
+X0080627Y0258248D01*
+X0080673Y0258210D01*
+X0080722Y0258174D01*
+X0080773Y0258141D01*
+X0080825Y0258112D01*
+X0080880Y0258085D01*
+X0080935Y0258062D01*
+X0080992Y0258042D01*
+X0081051Y0258026D01*
+X0081110Y0258013D01*
+X0081169Y0258004D01*
+X0081230Y0257999D01*
+X0081290Y0257997D01*
+X0082790Y0257997D01*
+X0082790Y0259247D01*
+X0082788Y0259316D01*
+X0082782Y0259385D01*
+X0082773Y0259453D01*
+X0082760Y0259520D01*
+X0082743Y0259587D01*
+X0082722Y0259653D01*
+X0082698Y0259717D01*
+X0082670Y0259780D01*
+X0082639Y0259842D01*
+X0082605Y0259902D01*
+X0082567Y0259959D01*
+X0082526Y0260015D01*
+X0082483Y0260068D01*
+X0082436Y0260119D01*
+X0082387Y0260167D01*
+X0082335Y0260212D01*
+X0082280Y0260254D01*
+X0082224Y0260293D01*
+X0082165Y0260330D01*
+X0082104Y0260362D01*
+X0082042Y0260392D01*
+X0081978Y0260418D01*
+X0081913Y0260440D01*
+X0081847Y0260459D01*
+X0081780Y0260474D01*
+X0081712Y0260485D01*
+X0081643Y0260493D01*
+X0081574Y0260497D01*
+X0081506Y0260497D01*
+X0081437Y0260493D01*
+X0081368Y0260485D01*
+X0081300Y0260474D01*
+X0081233Y0260459D01*
+X0081167Y0260440D01*
+X0081102Y0260418D01*
+X0081038Y0260392D01*
+X0080976Y0260362D01*
+X0080915Y0260330D01*
+X0080856Y0260293D01*
+X0080800Y0260254D01*
+X0080745Y0260212D01*
+X0080693Y0260167D01*
+X0080644Y0260119D01*
+X0080597Y0260068D01*
+X0080554Y0260015D01*
+X0080513Y0259959D01*
+X0080475Y0259902D01*
+X0080441Y0259842D01*
+X0080410Y0259780D01*
+X0080382Y0259717D01*
+X0080358Y0259653D01*
+X0080337Y0259587D01*
+X0080320Y0259520D01*
+X0080307Y0259453D01*
+X0080298Y0259385D01*
+X0080292Y0259316D01*
+X0080290Y0259247D01*
+X0082790Y0257997D02*
+X0082788Y0257910D01*
+X0082782Y0257823D01*
+X0082773Y0257736D01*
+X0082760Y0257650D01*
+X0082743Y0257564D01*
+X0082722Y0257479D01*
+X0082697Y0257396D01*
+X0082669Y0257313D01*
+X0082638Y0257232D01*
+X0082603Y0257152D01*
+X0082564Y0257074D01*
+X0082522Y0256997D01*
+X0082477Y0256922D01*
+X0082428Y0256850D01*
+X0082377Y0256779D01*
+X0082322Y0256711D01*
+X0082265Y0256646D01*
+X0082204Y0256583D01*
+X0082141Y0256522D01*
+X0082076Y0256465D01*
+X0082008Y0256410D01*
+X0081937Y0256359D01*
+X0081865Y0256310D01*
+X0081790Y0256265D01*
+X0081713Y0256223D01*
+X0081635Y0256184D01*
+X0081555Y0256149D01*
+X0081474Y0256118D01*
+X0081391Y0256090D01*
+X0081308Y0256065D01*
+X0081223Y0256044D01*
+X0081137Y0256027D01*
+X0081051Y0256014D01*
+X0080964Y0256005D01*
+X0080877Y0255999D01*
+X0080790Y0255997D01*
+X0084790Y0256997D02*
+X0087290Y0256997D01*
+X0086540Y0257997D02*
+X0086540Y0255997D01*
+X0084790Y0256997D02*
+X0085790Y0260497D01*
+X0091790Y0258247D02*
+X0091788Y0258127D01*
+X0091782Y0258007D01*
+X0091772Y0257887D01*
+X0091759Y0257768D01*
+X0091741Y0257649D01*
+X0091720Y0257531D01*
+X0091695Y0257413D01*
+X0091666Y0257297D01*
+X0091633Y0257181D01*
+X0091597Y0257067D01*
+X0091557Y0256953D01*
+X0091513Y0256841D01*
+X0091466Y0256731D01*
+X0091415Y0256622D01*
+X0091394Y0256566D01*
+X0091368Y0256511D01*
+X0091340Y0256457D01*
+X0091308Y0256406D01*
+X0091273Y0256357D01*
+X0091234Y0256311D01*
+X0091193Y0256267D01*
+X0091149Y0256225D01*
+X0091102Y0256187D01*
+X0091053Y0256152D01*
+X0091001Y0256120D01*
+X0090948Y0256092D01*
+X0090893Y0256067D01*
+X0090837Y0256046D01*
+X0090779Y0256028D01*
+X0090720Y0256015D01*
+X0090660Y0256005D01*
+X0090600Y0255999D01*
+X0090540Y0255997D01*
+X0090480Y0255999D01*
+X0090420Y0256005D01*
+X0090360Y0256015D01*
+X0090301Y0256028D01*
+X0090243Y0256046D01*
+X0090187Y0256067D01*
+X0090132Y0256092D01*
+X0090079Y0256120D01*
+X0090027Y0256152D01*
+X0089978Y0256187D01*
+X0089931Y0256225D01*
+X0089887Y0256267D01*
+X0089846Y0256311D01*
+X0089807Y0256357D01*
+X0089772Y0256406D01*
+X0089740Y0256457D01*
+X0089712Y0256511D01*
+X0089686Y0256566D01*
+X0089665Y0256622D01*
+X0089540Y0256997D02*
+X0091540Y0259497D01*
+X0091415Y0259872D02*
+X0091394Y0259928D01*
+X0091368Y0259983D01*
+X0091340Y0260037D01*
+X0091308Y0260088D01*
+X0091273Y0260137D01*
+X0091234Y0260183D01*
+X0091193Y0260227D01*
+X0091149Y0260269D01*
+X0091102Y0260307D01*
+X0091053Y0260342D01*
+X0091001Y0260374D01*
+X0090948Y0260402D01*
+X0090893Y0260427D01*
+X0090837Y0260448D01*
+X0090779Y0260466D01*
+X0090720Y0260479D01*
+X0090660Y0260489D01*
+X0090600Y0260495D01*
+X0090540Y0260497D01*
+X0090480Y0260495D01*
+X0090420Y0260489D01*
+X0090360Y0260479D01*
+X0090301Y0260466D01*
+X0090243Y0260448D01*
+X0090187Y0260427D01*
+X0090132Y0260402D01*
+X0090079Y0260374D01*
+X0090027Y0260342D01*
+X0089978Y0260307D01*
+X0089931Y0260269D01*
+X0089887Y0260227D01*
+X0089846Y0260183D01*
+X0089807Y0260137D01*
+X0089772Y0260088D01*
+X0089740Y0260037D01*
+X0089712Y0259983D01*
+X0089686Y0259928D01*
+X0089665Y0259872D01*
+X0091415Y0259872D02*
+X0091466Y0259763D01*
+X0091513Y0259653D01*
+X0091557Y0259541D01*
+X0091597Y0259427D01*
+X0091633Y0259313D01*
+X0091666Y0259197D01*
+X0091695Y0259081D01*
+X0091720Y0258963D01*
+X0091741Y0258845D01*
+X0091759Y0258726D01*
+X0091772Y0258607D01*
+X0091782Y0258487D01*
+X0091788Y0258367D01*
+X0091790Y0258247D01*
+X0089290Y0258247D02*
+X0089292Y0258127D01*
+X0089298Y0258007D01*
+X0089308Y0257887D01*
+X0089321Y0257768D01*
+X0089339Y0257649D01*
+X0089360Y0257531D01*
+X0089385Y0257413D01*
+X0089414Y0257297D01*
+X0089447Y0257181D01*
+X0089483Y0257067D01*
+X0089523Y0256953D01*
+X0089567Y0256841D01*
+X0089614Y0256731D01*
+X0089665Y0256622D01*
+X0089290Y0258247D02*
+X0089292Y0258367D01*
+X0089298Y0258487D01*
+X0089308Y0258607D01*
+X0089321Y0258726D01*
+X0089339Y0258845D01*
+X0089360Y0258963D01*
+X0089385Y0259081D01*
+X0089414Y0259197D01*
+X0089447Y0259313D01*
+X0089483Y0259427D01*
+X0089523Y0259541D01*
+X0089567Y0259653D01*
+X0089614Y0259763D01*
+X0089665Y0259872D01*
+X0093590Y0255497D02*
+X0095590Y0255497D01*
+X0097390Y0255997D02*
+X0098890Y0255997D01*
+X0098950Y0255999D01*
+X0099011Y0256004D01*
+X0099070Y0256013D01*
+X0099129Y0256026D01*
+X0099188Y0256042D01*
+X0099245Y0256062D01*
+X0099300Y0256085D01*
+X0099355Y0256112D01*
+X0099407Y0256141D01*
+X0099458Y0256174D01*
+X0099507Y0256210D01*
+X0099553Y0256248D01*
+X0099597Y0256290D01*
+X0099639Y0256334D01*
+X0099677Y0256380D01*
+X0099713Y0256429D01*
+X0099746Y0256480D01*
+X0099775Y0256532D01*
+X0099802Y0256587D01*
+X0099825Y0256642D01*
+X0099845Y0256699D01*
+X0099861Y0256758D01*
+X0099874Y0256817D01*
+X0099883Y0256876D01*
+X0099888Y0256937D01*
+X0099890Y0256997D01*
+X0099890Y0257497D01*
+X0099888Y0257557D01*
+X0099883Y0257618D01*
+X0099874Y0257677D01*
+X0099861Y0257736D01*
+X0099845Y0257795D01*
+X0099825Y0257852D01*
+X0099802Y0257907D01*
+X0099775Y0257962D01*
+X0099746Y0258014D01*
+X0099713Y0258065D01*
+X0099677Y0258114D01*
+X0099639Y0258160D01*
+X0099597Y0258204D01*
+X0099553Y0258246D01*
+X0099507Y0258284D01*
+X0099458Y0258320D01*
+X0099407Y0258353D01*
+X0099355Y0258382D01*
+X0099300Y0258409D01*
+X0099245Y0258432D01*
+X0099188Y0258452D01*
+X0099129Y0258468D01*
+X0099070Y0258481D01*
+X0099011Y0258490D01*
+X0098950Y0258495D01*
+X0098890Y0258497D01*
+X0097390Y0258497D01*
+X0097390Y0260497D01*
+X0099890Y0260497D01*
+X0101640Y0260497D02*
+X0103140Y0255997D01*
+X0104640Y0260497D01*
+X0194550Y0265047D02*
+X0194550Y0269547D01*
+X0195800Y0269547D01*
+X0195869Y0269545D01*
+X0195938Y0269539D01*
+X0196006Y0269530D01*
+X0196073Y0269517D01*
+X0196140Y0269500D01*
+X0196206Y0269479D01*
+X0196270Y0269455D01*
+X0196333Y0269427D01*
+X0196395Y0269396D01*
+X0196455Y0269362D01*
+X0196512Y0269324D01*
+X0196568Y0269283D01*
+X0196621Y0269240D01*
+X0196672Y0269193D01*
+X0196720Y0269144D01*
+X0196765Y0269092D01*
+X0196807Y0269037D01*
+X0196846Y0268981D01*
+X0196883Y0268922D01*
+X0196915Y0268861D01*
+X0196945Y0268799D01*
+X0196971Y0268735D01*
+X0196993Y0268670D01*
+X0197012Y0268604D01*
+X0197027Y0268537D01*
+X0197038Y0268469D01*
+X0197046Y0268400D01*
+X0197050Y0268331D01*
+X0197050Y0268263D01*
+X0197046Y0268194D01*
+X0197038Y0268125D01*
+X0197027Y0268057D01*
+X0197012Y0267990D01*
+X0196993Y0267924D01*
+X0196971Y0267859D01*
+X0196945Y0267795D01*
+X0196915Y0267733D01*
+X0196883Y0267672D01*
+X0196846Y0267613D01*
+X0196807Y0267557D01*
+X0196765Y0267502D01*
+X0196720Y0267450D01*
+X0196672Y0267401D01*
+X0196621Y0267354D01*
+X0196568Y0267311D01*
+X0196512Y0267270D01*
+X0196455Y0267232D01*
+X0196395Y0267198D01*
+X0196333Y0267167D01*
+X0196270Y0267139D01*
+X0196206Y0267115D01*
+X0196140Y0267094D01*
+X0196073Y0267077D01*
+X0196006Y0267064D01*
+X0195938Y0267055D01*
+X0195869Y0267049D01*
+X0195800Y0267047D01*
+X0194550Y0267047D01*
+X0196050Y0267047D02*
+X0197050Y0265047D01*
+X0199067Y0266797D02*
+X0202067Y0266797D01*
+X0204103Y0266047D02*
+X0204103Y0268547D01*
+X0204105Y0268607D01*
+X0204110Y0268668D01*
+X0204119Y0268727D01*
+X0204132Y0268786D01*
+X0204148Y0268845D01*
+X0204168Y0268902D01*
+X0204191Y0268957D01*
+X0204218Y0269012D01*
+X0204247Y0269064D01*
+X0204280Y0269115D01*
+X0204316Y0269164D01*
+X0204354Y0269210D01*
+X0204396Y0269254D01*
+X0204440Y0269296D01*
+X0204486Y0269334D01*
+X0204535Y0269370D01*
+X0204586Y0269403D01*
+X0204638Y0269432D01*
+X0204693Y0269459D01*
+X0204748Y0269482D01*
+X0204805Y0269502D01*
+X0204864Y0269518D01*
+X0204923Y0269531D01*
+X0204982Y0269540D01*
+X0205043Y0269545D01*
+X0205103Y0269547D01*
+X0206103Y0269547D01*
+X0208041Y0268047D02*
+X0209041Y0268047D01*
+X0209095Y0268045D01*
+X0209148Y0268039D01*
+X0209200Y0268030D01*
+X0209252Y0268017D01*
+X0209303Y0268000D01*
+X0209353Y0267979D01*
+X0209400Y0267955D01*
+X0209446Y0267928D01*
+X0209490Y0267897D01*
+X0209532Y0267864D01*
+X0209571Y0267827D01*
+X0209608Y0267788D01*
+X0209641Y0267746D01*
+X0209672Y0267702D01*
+X0209699Y0267656D01*
+X0209723Y0267609D01*
+X0209744Y0267559D01*
+X0209761Y0267508D01*
+X0209774Y0267456D01*
+X0209783Y0267404D01*
+X0209789Y0267351D01*
+X0209791Y0267297D01*
+X0209791Y0265047D01*
+X0208666Y0265047D01*
+X0208608Y0265049D01*
+X0208549Y0265055D01*
+X0208492Y0265065D01*
+X0208435Y0265078D01*
+X0208379Y0265095D01*
+X0208324Y0265116D01*
+X0208271Y0265141D01*
+X0208220Y0265169D01*
+X0208171Y0265201D01*
+X0208124Y0265235D01*
+X0208079Y0265273D01*
+X0208037Y0265314D01*
+X0207998Y0265357D01*
+X0207962Y0265403D01*
+X0207928Y0265451D01*
+X0207899Y0265501D01*
+X0207872Y0265554D01*
+X0207849Y0265608D01*
+X0207830Y0265663D01*
+X0207815Y0265719D01*
+X0207803Y0265776D01*
+X0207795Y0265834D01*
+X0207791Y0265893D01*
+X0207791Y0265951D01*
+X0207795Y0266010D01*
+X0207803Y0266068D01*
+X0207815Y0266125D01*
+X0207830Y0266181D01*
+X0207849Y0266236D01*
+X0207872Y0266290D01*
+X0207899Y0266343D01*
+X0207928Y0266393D01*
+X0207962Y0266441D01*
+X0207998Y0266487D01*
+X0208037Y0266530D01*
+X0208079Y0266571D01*
+X0208124Y0266609D01*
+X0208171Y0266643D01*
+X0208220Y0266675D01*
+X0208271Y0266703D01*
+X0208324Y0266728D01*
+X0208379Y0266749D01*
+X0208435Y0266766D01*
+X0208492Y0266779D01*
+X0208549Y0266789D01*
+X0208608Y0266795D01*
+X0208666Y0266797D01*
+X0209791Y0266797D01*
+X0212043Y0268047D02*
+X0213293Y0268047D01*
+X0213347Y0268045D01*
+X0213400Y0268039D01*
+X0213452Y0268030D01*
+X0213504Y0268017D01*
+X0213555Y0268000D01*
+X0213605Y0267979D01*
+X0213652Y0267955D01*
+X0213698Y0267928D01*
+X0213742Y0267897D01*
+X0213784Y0267864D01*
+X0213823Y0267827D01*
+X0213860Y0267788D01*
+X0213893Y0267746D01*
+X0213924Y0267702D01*
+X0213951Y0267656D01*
+X0213975Y0267609D01*
+X0213996Y0267559D01*
+X0214013Y0267508D01*
+X0214026Y0267456D01*
+X0214035Y0267404D01*
+X0214041Y0267351D01*
+X0214043Y0267297D01*
+X0214043Y0265797D01*
+X0214041Y0265743D01*
+X0214035Y0265690D01*
+X0214026Y0265638D01*
+X0214013Y0265586D01*
+X0213996Y0265535D01*
+X0213975Y0265485D01*
+X0213951Y0265438D01*
+X0213924Y0265392D01*
+X0213893Y0265348D01*
+X0213860Y0265306D01*
+X0213823Y0265267D01*
+X0213784Y0265230D01*
+X0213742Y0265197D01*
+X0213698Y0265166D01*
+X0213652Y0265139D01*
+X0213605Y0265115D01*
+X0213555Y0265094D01*
+X0213504Y0265077D01*
+X0213452Y0265064D01*
+X0213400Y0265055D01*
+X0213347Y0265049D01*
+X0213293Y0265047D01*
+X0212043Y0265047D01*
+X0212043Y0269547D01*
+X0215965Y0269547D02*
+X0215965Y0265797D01*
+X0215967Y0265743D01*
+X0215973Y0265690D01*
+X0215982Y0265638D01*
+X0215995Y0265586D01*
+X0216012Y0265535D01*
+X0216033Y0265485D01*
+X0216057Y0265438D01*
+X0216084Y0265392D01*
+X0216115Y0265348D01*
+X0216148Y0265306D01*
+X0216185Y0265267D01*
+X0216224Y0265230D01*
+X0216266Y0265197D01*
+X0216310Y0265166D01*
+X0216356Y0265139D01*
+X0216403Y0265115D01*
+X0216453Y0265094D01*
+X0216504Y0265077D01*
+X0216556Y0265064D01*
+X0216608Y0265055D01*
+X0216661Y0265049D01*
+X0216715Y0265047D01*
+X0218317Y0265797D02*
+X0218317Y0267047D01*
+X0218317Y0266547D02*
+X0220317Y0266547D01*
+X0220317Y0267047D01*
+X0220315Y0267109D01*
+X0220309Y0267170D01*
+X0220300Y0267231D01*
+X0220287Y0267291D01*
+X0220270Y0267350D01*
+X0220249Y0267408D01*
+X0220225Y0267465D01*
+X0220198Y0267520D01*
+X0220167Y0267573D01*
+X0220133Y0267625D01*
+X0220096Y0267674D01*
+X0220056Y0267721D01*
+X0220013Y0267765D01*
+X0219968Y0267806D01*
+X0219920Y0267845D01*
+X0219869Y0267881D01*
+X0219817Y0267913D01*
+X0219763Y0267942D01*
+X0219707Y0267968D01*
+X0219649Y0267990D01*
+X0219591Y0268009D01*
+X0219531Y0268024D01*
+X0219470Y0268035D01*
+X0219409Y0268043D01*
+X0219348Y0268047D01*
+X0219286Y0268047D01*
+X0219225Y0268043D01*
+X0219164Y0268035D01*
+X0219103Y0268024D01*
+X0219043Y0268009D01*
+X0218985Y0267990D01*
+X0218927Y0267968D01*
+X0218871Y0267942D01*
+X0218817Y0267913D01*
+X0218765Y0267881D01*
+X0218714Y0267845D01*
+X0218666Y0267806D01*
+X0218621Y0267765D01*
+X0218578Y0267721D01*
+X0218538Y0267674D01*
+X0218501Y0267625D01*
+X0218467Y0267573D01*
+X0218436Y0267520D01*
+X0218409Y0267465D01*
+X0218385Y0267408D01*
+X0218364Y0267350D01*
+X0218347Y0267291D01*
+X0218334Y0267231D01*
+X0218325Y0267170D01*
+X0218319Y0267109D01*
+X0218317Y0267047D01*
+X0218317Y0265797D02*
+X0218319Y0265743D01*
+X0218325Y0265690D01*
+X0218334Y0265638D01*
+X0218347Y0265586D01*
+X0218364Y0265535D01*
+X0218385Y0265485D01*
+X0218409Y0265438D01*
+X0218436Y0265392D01*
+X0218467Y0265348D01*
+X0218500Y0265306D01*
+X0218537Y0265267D01*
+X0218576Y0265230D01*
+X0218618Y0265197D01*
+X0218662Y0265166D01*
+X0218708Y0265139D01*
+X0218755Y0265115D01*
+X0218805Y0265094D01*
+X0218856Y0265077D01*
+X0218908Y0265064D01*
+X0218960Y0265055D01*
+X0219013Y0265049D01*
+X0219067Y0265047D01*
+X0220317Y0265047D01*
+X0222267Y0265047D02*
+X0224767Y0265047D01*
+X0223517Y0265047D02*
+X0223517Y0269547D01*
+X0222267Y0268547D01*
+X0229267Y0267297D02*
+X0229265Y0267177D01*
+X0229259Y0267057D01*
+X0229249Y0266937D01*
+X0229236Y0266818D01*
+X0229218Y0266699D01*
+X0229197Y0266581D01*
+X0229172Y0266463D01*
+X0229143Y0266347D01*
+X0229110Y0266231D01*
+X0229074Y0266117D01*
+X0229034Y0266003D01*
+X0228990Y0265891D01*
+X0228943Y0265781D01*
+X0228892Y0265672D01*
+X0228871Y0265616D01*
+X0228845Y0265561D01*
+X0228817Y0265507D01*
+X0228785Y0265456D01*
+X0228750Y0265407D01*
+X0228711Y0265361D01*
+X0228670Y0265317D01*
+X0228626Y0265275D01*
+X0228579Y0265237D01*
+X0228530Y0265202D01*
+X0228478Y0265170D01*
+X0228425Y0265142D01*
+X0228370Y0265117D01*
+X0228314Y0265096D01*
+X0228256Y0265078D01*
+X0228197Y0265065D01*
+X0228137Y0265055D01*
+X0228077Y0265049D01*
+X0228017Y0265047D01*
+X0227957Y0265049D01*
+X0227897Y0265055D01*
+X0227837Y0265065D01*
+X0227778Y0265078D01*
+X0227720Y0265096D01*
+X0227664Y0265117D01*
+X0227609Y0265142D01*
+X0227556Y0265170D01*
+X0227504Y0265202D01*
+X0227455Y0265237D01*
+X0227408Y0265275D01*
+X0227364Y0265317D01*
+X0227323Y0265361D01*
+X0227284Y0265407D01*
+X0227249Y0265456D01*
+X0227217Y0265507D01*
+X0227189Y0265561D01*
+X0227163Y0265616D01*
+X0227142Y0265672D01*
+X0227017Y0266047D02*
+X0229017Y0268547D01*
+X0228892Y0268922D02*
+X0228871Y0268978D01*
+X0228845Y0269033D01*
+X0228817Y0269087D01*
+X0228785Y0269138D01*
+X0228750Y0269187D01*
+X0228711Y0269233D01*
+X0228670Y0269277D01*
+X0228626Y0269319D01*
+X0228579Y0269357D01*
+X0228530Y0269392D01*
+X0228478Y0269424D01*
+X0228425Y0269452D01*
+X0228370Y0269477D01*
+X0228314Y0269498D01*
+X0228256Y0269516D01*
+X0228197Y0269529D01*
+X0228137Y0269539D01*
+X0228077Y0269545D01*
+X0228017Y0269547D01*
+X0227957Y0269545D01*
+X0227897Y0269539D01*
+X0227837Y0269529D01*
+X0227778Y0269516D01*
+X0227720Y0269498D01*
+X0227664Y0269477D01*
+X0227609Y0269452D01*
+X0227556Y0269424D01*
+X0227504Y0269392D01*
+X0227455Y0269357D01*
+X0227408Y0269319D01*
+X0227364Y0269277D01*
+X0227323Y0269233D01*
+X0227284Y0269187D01*
+X0227249Y0269138D01*
+X0227217Y0269087D01*
+X0227189Y0269033D01*
+X0227163Y0268978D01*
+X0227142Y0268922D01*
+X0228892Y0268922D02*
+X0228943Y0268813D01*
+X0228990Y0268703D01*
+X0229034Y0268591D01*
+X0229074Y0268477D01*
+X0229110Y0268363D01*
+X0229143Y0268247D01*
+X0229172Y0268131D01*
+X0229197Y0268013D01*
+X0229218Y0267895D01*
+X0229236Y0267776D01*
+X0229249Y0267657D01*
+X0229259Y0267537D01*
+X0229265Y0267417D01*
+X0229267Y0267297D01*
+X0226768Y0267297D02*
+X0226770Y0267177D01*
+X0226776Y0267057D01*
+X0226786Y0266937D01*
+X0226799Y0266818D01*
+X0226817Y0266699D01*
+X0226838Y0266581D01*
+X0226863Y0266463D01*
+X0226892Y0266347D01*
+X0226925Y0266231D01*
+X0226961Y0266117D01*
+X0227001Y0266003D01*
+X0227045Y0265891D01*
+X0227092Y0265781D01*
+X0227143Y0265672D01*
+X0226768Y0267297D02*
+X0226770Y0267417D01*
+X0226776Y0267537D01*
+X0226786Y0267657D01*
+X0226799Y0267776D01*
+X0226817Y0267895D01*
+X0226838Y0268013D01*
+X0226863Y0268131D01*
+X0226892Y0268247D01*
+X0226925Y0268363D01*
+X0226961Y0268477D01*
+X0227001Y0268591D01*
+X0227045Y0268703D01*
+X0227092Y0268813D01*
+X0227143Y0268922D01*
+X0231492Y0269547D02*
+X0231492Y0265047D01*
+X0231492Y0267047D02*
+X0232742Y0267047D01*
+X0232811Y0267049D01*
+X0232880Y0267055D01*
+X0232948Y0267064D01*
+X0233015Y0267077D01*
+X0233082Y0267094D01*
+X0233148Y0267115D01*
+X0233212Y0267139D01*
+X0233275Y0267167D01*
+X0233337Y0267198D01*
+X0233397Y0267232D01*
+X0233454Y0267270D01*
+X0233510Y0267311D01*
+X0233563Y0267354D01*
+X0233614Y0267401D01*
+X0233662Y0267450D01*
+X0233707Y0267502D01*
+X0233749Y0267557D01*
+X0233788Y0267613D01*
+X0233825Y0267672D01*
+X0233857Y0267733D01*
+X0233887Y0267795D01*
+X0233913Y0267859D01*
+X0233935Y0267924D01*
+X0233954Y0267990D01*
+X0233969Y0268057D01*
+X0233980Y0268125D01*
+X0233988Y0268194D01*
+X0233992Y0268263D01*
+X0233992Y0268331D01*
+X0233988Y0268400D01*
+X0233980Y0268469D01*
+X0233969Y0268537D01*
+X0233954Y0268604D01*
+X0233935Y0268670D01*
+X0233913Y0268735D01*
+X0233887Y0268799D01*
+X0233857Y0268861D01*
+X0233825Y0268922D01*
+X0233788Y0268981D01*
+X0233749Y0269037D01*
+X0233707Y0269092D01*
+X0233662Y0269144D01*
+X0233614Y0269193D01*
+X0233563Y0269240D01*
+X0233510Y0269283D01*
+X0233454Y0269324D01*
+X0233397Y0269362D01*
+X0233337Y0269396D01*
+X0233275Y0269427D01*
+X0233212Y0269455D01*
+X0233148Y0269479D01*
+X0233082Y0269500D01*
+X0233015Y0269517D01*
+X0232948Y0269530D01*
+X0232880Y0269539D01*
+X0232811Y0269545D01*
+X0232742Y0269547D01*
+X0231492Y0269547D01*
+X0206103Y0265047D02*
+X0205103Y0265047D01*
+X0205043Y0265049D01*
+X0204982Y0265054D01*
+X0204923Y0265063D01*
+X0204864Y0265076D01*
+X0204805Y0265092D01*
+X0204748Y0265112D01*
+X0204693Y0265135D01*
+X0204638Y0265162D01*
+X0204586Y0265191D01*
+X0204535Y0265224D01*
+X0204486Y0265260D01*
+X0204440Y0265298D01*
+X0204396Y0265340D01*
+X0204354Y0265384D01*
+X0204316Y0265430D01*
+X0204280Y0265479D01*
+X0204247Y0265530D01*
+X0204218Y0265582D01*
+X0204191Y0265637D01*
+X0204168Y0265692D01*
+X0204148Y0265749D01*
+X0204132Y0265808D01*
+X0204119Y0265867D01*
+X0204110Y0265926D01*
+X0204105Y0265987D01*
+X0204103Y0266047D01*
+X0346042Y0221397D02*
+X0346044Y0221522D01*
+X0346050Y0221647D01*
+X0346060Y0221771D01*
+X0346074Y0221895D01*
+X0346091Y0222019D01*
+X0346113Y0222142D01*
+X0346139Y0222264D01*
+X0346168Y0222386D01*
+X0346201Y0222506D01*
+X0346239Y0222625D01*
+X0346279Y0222744D01*
+X0346324Y0222860D01*
+X0346372Y0222975D01*
+X0346424Y0223089D01*
+X0346480Y0223201D01*
+X0346539Y0223311D01*
+X0346601Y0223419D01*
+X0346667Y0223526D01*
+X0346736Y0223630D01*
+X0346809Y0223731D01*
+X0346884Y0223831D01*
+X0346963Y0223928D01*
+X0347045Y0224022D01*
+X0347130Y0224114D01*
+X0347217Y0224203D01*
+X0347308Y0224289D01*
+X0347401Y0224372D01*
+X0347497Y0224453D01*
+X0347595Y0224530D01*
+X0347695Y0224604D01*
+X0347798Y0224675D01*
+X0347903Y0224742D01*
+X0348011Y0224807D01*
+X0348120Y0224867D01*
+X0348231Y0224925D01*
+X0348344Y0224978D01*
+X0348458Y0225028D01*
+X0348574Y0225075D01*
+X0348691Y0225117D01*
+X0348810Y0225156D01*
+X0348930Y0225192D01*
+X0349051Y0225223D01*
+X0349173Y0225251D01*
+X0349295Y0225274D01*
+X0349419Y0225294D01*
+X0349543Y0225310D01*
+X0349667Y0225322D01*
+X0349792Y0225330D01*
+X0349917Y0225334D01*
+X0350041Y0225334D01*
+X0350166Y0225330D01*
+X0350291Y0225322D01*
+X0350415Y0225310D01*
+X0350539Y0225294D01*
+X0350663Y0225274D01*
+X0350785Y0225251D01*
+X0350907Y0225223D01*
+X0351028Y0225192D01*
+X0351148Y0225156D01*
+X0351267Y0225117D01*
+X0351384Y0225075D01*
+X0351500Y0225028D01*
+X0351614Y0224978D01*
+X0351727Y0224925D01*
+X0351838Y0224867D01*
+X0351948Y0224807D01*
+X0352055Y0224742D01*
+X0352160Y0224675D01*
+X0352263Y0224604D01*
+X0352363Y0224530D01*
+X0352461Y0224453D01*
+X0352557Y0224372D01*
+X0352650Y0224289D01*
+X0352741Y0224203D01*
+X0352828Y0224114D01*
+X0352913Y0224022D01*
+X0352995Y0223928D01*
+X0353074Y0223831D01*
+X0353149Y0223731D01*
+X0353222Y0223630D01*
+X0353291Y0223526D01*
+X0353357Y0223419D01*
+X0353419Y0223311D01*
+X0353478Y0223201D01*
+X0353534Y0223089D01*
+X0353586Y0222975D01*
+X0353634Y0222860D01*
+X0353679Y0222744D01*
+X0353719Y0222625D01*
+X0353757Y0222506D01*
+X0353790Y0222386D01*
+X0353819Y0222264D01*
+X0353845Y0222142D01*
+X0353867Y0222019D01*
+X0353884Y0221895D01*
+X0353898Y0221771D01*
+X0353908Y0221647D01*
+X0353914Y0221522D01*
+X0353916Y0221397D01*
+X0353914Y0221272D01*
+X0353908Y0221147D01*
+X0353898Y0221023D01*
+X0353884Y0220899D01*
+X0353867Y0220775D01*
+X0353845Y0220652D01*
+X0353819Y0220530D01*
+X0353790Y0220408D01*
+X0353757Y0220288D01*
+X0353719Y0220169D01*
+X0353679Y0220050D01*
+X0353634Y0219934D01*
+X0353586Y0219819D01*
+X0353534Y0219705D01*
+X0353478Y0219593D01*
+X0353419Y0219483D01*
+X0353357Y0219375D01*
+X0353291Y0219268D01*
+X0353222Y0219164D01*
+X0353149Y0219063D01*
+X0353074Y0218963D01*
+X0352995Y0218866D01*
+X0352913Y0218772D01*
+X0352828Y0218680D01*
+X0352741Y0218591D01*
+X0352650Y0218505D01*
+X0352557Y0218422D01*
+X0352461Y0218341D01*
+X0352363Y0218264D01*
+X0352263Y0218190D01*
+X0352160Y0218119D01*
+X0352055Y0218052D01*
+X0351947Y0217987D01*
+X0351838Y0217927D01*
+X0351727Y0217869D01*
+X0351614Y0217816D01*
+X0351500Y0217766D01*
+X0351384Y0217719D01*
+X0351267Y0217677D01*
+X0351148Y0217638D01*
+X0351028Y0217602D01*
+X0350907Y0217571D01*
+X0350785Y0217543D01*
+X0350663Y0217520D01*
+X0350539Y0217500D01*
+X0350415Y0217484D01*
+X0350291Y0217472D01*
+X0350166Y0217464D01*
+X0350041Y0217460D01*
+X0349917Y0217460D01*
+X0349792Y0217464D01*
+X0349667Y0217472D01*
+X0349543Y0217484D01*
+X0349419Y0217500D01*
+X0349295Y0217520D01*
+X0349173Y0217543D01*
+X0349051Y0217571D01*
+X0348930Y0217602D01*
+X0348810Y0217638D01*
+X0348691Y0217677D01*
+X0348574Y0217719D01*
+X0348458Y0217766D01*
+X0348344Y0217816D01*
+X0348231Y0217869D01*
+X0348120Y0217927D01*
+X0348010Y0217987D01*
+X0347903Y0218052D01*
+X0347798Y0218119D01*
+X0347695Y0218190D01*
+X0347595Y0218264D01*
+X0347497Y0218341D01*
+X0347401Y0218422D01*
+X0347308Y0218505D01*
+X0347217Y0218591D01*
+X0347130Y0218680D01*
+X0347045Y0218772D01*
+X0346963Y0218866D01*
+X0346884Y0218963D01*
+X0346809Y0219063D01*
+X0346736Y0219164D01*
+X0346667Y0219268D01*
+X0346601Y0219375D01*
+X0346539Y0219483D01*
+X0346480Y0219593D01*
+X0346424Y0219705D01*
+X0346372Y0219819D01*
+X0346324Y0219934D01*
+X0346279Y0220050D01*
+X0346239Y0220169D01*
+X0346201Y0220288D01*
+X0346168Y0220408D01*
+X0346139Y0220530D01*
+X0346113Y0220652D01*
+X0346091Y0220775D01*
+X0346074Y0220899D01*
+X0346060Y0221023D01*
+X0346050Y0221147D01*
+X0346044Y0221272D01*
+X0346042Y0221397D01*
+X0328800Y0048547D02*
+X0309800Y0048547D01*
+X0309800Y0013047D01*
+X0313300Y0013047D01*
+X0313300Y0006547D01*
+X0313800Y0006047D02*
+X0313800Y0007547D01*
+X0313800Y0006047D02*
+X0309300Y0009547D01*
+X0308800Y0013047D02*
+X0305300Y0013047D01*
+X0305300Y0006547D01*
+X0307300Y0006547D02*
+X0311800Y0003047D01*
+X0310300Y0003047D01*
+X0311800Y0003047D02*
+X0311800Y0004547D01*
+X0312300Y0006047D02*
+X0313800Y0006047D01*
+X0313300Y0006547D02*
+X0313321Y0006394D01*
+X0313346Y0006241D01*
+X0313375Y0006089D01*
+X0313408Y0005938D01*
+X0313445Y0005787D01*
+X0313485Y0005638D01*
+X0313529Y0005489D01*
+X0313578Y0005342D01*
+X0313630Y0005196D01*
+X0313685Y0005052D01*
+X0313744Y0004909D01*
+X0313807Y0004768D01*
+X0313874Y0004628D01*
+X0313944Y0004490D01*
+X0314018Y0004354D01*
+X0314095Y0004219D01*
+X0314175Y0004087D01*
+X0314259Y0003957D01*
+X0314346Y0003829D01*
+X0314437Y0003703D01*
+X0314530Y0003580D01*
+X0314627Y0003459D01*
+X0314727Y0003341D01*
+X0314829Y0003225D01*
+X0314935Y0003112D01*
+X0315044Y0003002D01*
+X0315155Y0002894D01*
+X0315269Y0002789D01*
+X0315386Y0002688D01*
+X0315505Y0002589D01*
+X0315627Y0002493D01*
+X0315751Y0002401D01*
+X0315878Y0002312D01*
+X0316006Y0002226D01*
+X0316137Y0002143D01*
+X0316270Y0002064D01*
+X0316405Y0001988D01*
+X0316542Y0001916D01*
+X0316681Y0001847D01*
+X0316821Y0001782D01*
+X0316963Y0001720D01*
+X0317106Y0001662D01*
+X0317251Y0001608D01*
+X0317398Y0001557D01*
+X0317545Y0001510D01*
+X0317694Y0001467D01*
+X0317844Y0001428D01*
+X0317994Y0001393D01*
+X0318146Y0001361D01*
+X0318298Y0001334D01*
+X0318451Y0001310D01*
+X0318605Y0001290D01*
+X0318759Y0001274D01*
+X0318913Y0001262D01*
+X0319068Y0001254D01*
+X0319223Y0001250D01*
+X0319377Y0001250D01*
+X0319532Y0001254D01*
+X0319687Y0001262D01*
+X0319841Y0001274D01*
+X0319995Y0001290D01*
+X0320149Y0001310D01*
+X0320302Y0001334D01*
+X0320454Y0001361D01*
+X0320606Y0001393D01*
+X0320756Y0001428D01*
+X0320906Y0001467D01*
+X0321055Y0001510D01*
+X0321202Y0001557D01*
+X0321349Y0001608D01*
+X0321494Y0001662D01*
+X0321637Y0001720D01*
+X0321779Y0001782D01*
+X0321919Y0001847D01*
+X0322058Y0001916D01*
+X0322195Y0001988D01*
+X0322330Y0002064D01*
+X0322463Y0002143D01*
+X0322594Y0002226D01*
+X0322722Y0002312D01*
+X0322849Y0002401D01*
+X0322973Y0002493D01*
+X0323095Y0002589D01*
+X0323214Y0002688D01*
+X0323331Y0002789D01*
+X0323445Y0002894D01*
+X0323556Y0003002D01*
+X0323665Y0003112D01*
+X0323771Y0003225D01*
+X0323873Y0003341D01*
+X0323973Y0003459D01*
+X0324070Y0003580D01*
+X0324163Y0003703D01*
+X0324254Y0003829D01*
+X0324341Y0003957D01*
+X0324425Y0004087D01*
+X0324505Y0004219D01*
+X0324582Y0004354D01*
+X0324656Y0004490D01*
+X0324726Y0004628D01*
+X0324793Y0004768D01*
+X0324856Y0004909D01*
+X0324915Y0005052D01*
+X0324970Y0005196D01*
+X0325022Y0005342D01*
+X0325071Y0005489D01*
+X0325115Y0005638D01*
+X0325155Y0005787D01*
+X0325192Y0005938D01*
+X0325225Y0006089D01*
+X0325254Y0006241D01*
+X0325279Y0006394D01*
+X0325300Y0006547D01*
+X0325300Y0013047D01*
+X0313300Y0013047D01*
+X0308800Y0013047D02*
+X0308800Y0048547D01*
+X0289800Y0048547D01*
+X0289800Y0013047D01*
+X0293300Y0013047D01*
+X0293300Y0006547D01*
+X0293321Y0006394D01*
+X0293346Y0006241D01*
+X0293375Y0006089D01*
+X0293408Y0005938D01*
+X0293445Y0005787D01*
+X0293485Y0005638D01*
+X0293529Y0005489D01*
+X0293578Y0005342D01*
+X0293630Y0005196D01*
+X0293685Y0005052D01*
+X0293744Y0004909D01*
+X0293807Y0004768D01*
+X0293874Y0004628D01*
+X0293944Y0004490D01*
+X0294018Y0004354D01*
+X0294095Y0004219D01*
+X0294175Y0004087D01*
+X0294259Y0003957D01*
+X0294346Y0003829D01*
+X0294437Y0003703D01*
+X0294530Y0003580D01*
+X0294627Y0003459D01*
+X0294727Y0003341D01*
+X0294829Y0003225D01*
+X0294935Y0003112D01*
+X0295044Y0003002D01*
+X0295155Y0002894D01*
+X0295269Y0002789D01*
+X0295386Y0002688D01*
+X0295505Y0002589D01*
+X0295627Y0002493D01*
+X0295751Y0002401D01*
+X0295878Y0002312D01*
+X0296006Y0002226D01*
+X0296137Y0002143D01*
+X0296270Y0002064D01*
+X0296405Y0001988D01*
+X0296542Y0001916D01*
+X0296681Y0001847D01*
+X0296821Y0001782D01*
+X0296963Y0001720D01*
+X0297106Y0001662D01*
+X0297251Y0001608D01*
+X0297398Y0001557D01*
+X0297545Y0001510D01*
+X0297694Y0001467D01*
+X0297844Y0001428D01*
+X0297994Y0001393D01*
+X0298146Y0001361D01*
+X0298298Y0001334D01*
+X0298451Y0001310D01*
+X0298605Y0001290D01*
+X0298759Y0001274D01*
+X0298913Y0001262D01*
+X0299068Y0001254D01*
+X0299223Y0001250D01*
+X0299377Y0001250D01*
+X0299532Y0001254D01*
+X0299687Y0001262D01*
+X0299841Y0001274D01*
+X0299995Y0001290D01*
+X0300149Y0001310D01*
+X0300302Y0001334D01*
+X0300454Y0001361D01*
+X0300606Y0001393D01*
+X0300756Y0001428D01*
+X0300906Y0001467D01*
+X0301055Y0001510D01*
+X0301202Y0001557D01*
+X0301349Y0001608D01*
+X0301494Y0001662D01*
+X0301637Y0001720D01*
+X0301779Y0001782D01*
+X0301919Y0001847D01*
+X0302058Y0001916D01*
+X0302195Y0001988D01*
+X0302330Y0002064D01*
+X0302463Y0002143D01*
+X0302594Y0002226D01*
+X0302722Y0002312D01*
+X0302849Y0002401D01*
+X0302973Y0002493D01*
+X0303095Y0002589D01*
+X0303214Y0002688D01*
+X0303331Y0002789D01*
+X0303445Y0002894D01*
+X0303556Y0003002D01*
+X0303665Y0003112D01*
+X0303771Y0003225D01*
+X0303873Y0003341D01*
+X0303973Y0003459D01*
+X0304070Y0003580D01*
+X0304163Y0003703D01*
+X0304254Y0003829D01*
+X0304341Y0003957D01*
+X0304425Y0004087D01*
+X0304505Y0004219D01*
+X0304582Y0004354D01*
+X0304656Y0004490D01*
+X0304726Y0004628D01*
+X0304793Y0004768D01*
+X0304856Y0004909D01*
+X0304915Y0005052D01*
+X0304970Y0005196D01*
+X0305022Y0005342D01*
+X0305071Y0005489D01*
+X0305115Y0005638D01*
+X0305155Y0005787D01*
+X0305192Y0005938D01*
+X0305225Y0006089D01*
+X0305254Y0006241D01*
+X0305279Y0006394D01*
+X0305300Y0006547D01*
+X0305300Y0013047D02*
+X0293300Y0013047D01*
+X0325300Y0013047D02*
+X0328800Y0013047D01*
+X0328800Y0048547D01*
+X0329300Y0009547D02*
+X0333800Y0006047D01*
+X0332300Y0006047D01*
+X0333800Y0006047D02*
+X0333800Y0007547D01*
+X0331800Y0004547D02*
+X0331800Y0003047D01*
+X0330300Y0003047D01*
+X0331800Y0003047D02*
+X0327300Y0006547D01*
+X0085300Y0031097D02*
+X0084050Y0031097D01*
+X0085300Y0031097D02*
+X0085369Y0031099D01*
+X0085438Y0031105D01*
+X0085506Y0031114D01*
+X0085573Y0031127D01*
+X0085640Y0031144D01*
+X0085706Y0031165D01*
+X0085770Y0031189D01*
+X0085833Y0031217D01*
+X0085895Y0031248D01*
+X0085955Y0031282D01*
+X0086012Y0031320D01*
+X0086068Y0031361D01*
+X0086121Y0031404D01*
+X0086172Y0031451D01*
+X0086220Y0031500D01*
+X0086265Y0031552D01*
+X0086307Y0031607D01*
+X0086346Y0031663D01*
+X0086383Y0031722D01*
+X0086415Y0031783D01*
+X0086445Y0031845D01*
+X0086471Y0031909D01*
+X0086493Y0031974D01*
+X0086512Y0032040D01*
+X0086527Y0032107D01*
+X0086538Y0032175D01*
+X0086546Y0032244D01*
+X0086550Y0032313D01*
+X0086550Y0032381D01*
+X0086546Y0032450D01*
+X0086538Y0032519D01*
+X0086527Y0032587D01*
+X0086512Y0032654D01*
+X0086493Y0032720D01*
+X0086471Y0032785D01*
+X0086445Y0032849D01*
+X0086415Y0032911D01*
+X0086383Y0032972D01*
+X0086346Y0033031D01*
+X0086307Y0033087D01*
+X0086265Y0033142D01*
+X0086220Y0033194D01*
+X0086172Y0033243D01*
+X0086121Y0033290D01*
+X0086068Y0033333D01*
+X0086012Y0033374D01*
+X0085955Y0033412D01*
+X0085895Y0033446D01*
+X0085833Y0033477D01*
+X0085770Y0033505D01*
+X0085706Y0033529D01*
+X0085640Y0033550D01*
+X0085573Y0033567D01*
+X0085506Y0033580D01*
+X0085438Y0033589D01*
+X0085369Y0033595D01*
+X0085300Y0033597D01*
+X0085550Y0033597D02*
+X0084550Y0033597D01*
+X0085550Y0033597D02*
+X0085612Y0033599D01*
+X0085673Y0033605D01*
+X0085734Y0033614D01*
+X0085794Y0033627D01*
+X0085853Y0033644D01*
+X0085911Y0033665D01*
+X0085968Y0033689D01*
+X0086023Y0033716D01*
+X0086076Y0033747D01*
+X0086128Y0033781D01*
+X0086177Y0033818D01*
+X0086224Y0033858D01*
+X0086268Y0033901D01*
+X0086309Y0033946D01*
+X0086348Y0033994D01*
+X0086384Y0034045D01*
+X0086416Y0034097D01*
+X0086445Y0034151D01*
+X0086471Y0034207D01*
+X0086493Y0034265D01*
+X0086512Y0034323D01*
+X0086527Y0034383D01*
+X0086538Y0034444D01*
+X0086546Y0034505D01*
+X0086550Y0034566D01*
+X0086550Y0034628D01*
+X0086546Y0034689D01*
+X0086538Y0034750D01*
+X0086527Y0034811D01*
+X0086512Y0034871D01*
+X0086493Y0034929D01*
+X0086471Y0034987D01*
+X0086445Y0035043D01*
+X0086416Y0035097D01*
+X0086384Y0035149D01*
+X0086348Y0035200D01*
+X0086309Y0035248D01*
+X0086268Y0035293D01*
+X0086224Y0035336D01*
+X0086177Y0035376D01*
+X0086128Y0035413D01*
+X0086076Y0035447D01*
+X0086023Y0035478D01*
+X0085968Y0035505D01*
+X0085911Y0035529D01*
+X0085853Y0035550D01*
+X0085794Y0035567D01*
+X0085734Y0035580D01*
+X0085673Y0035589D01*
+X0085612Y0035595D01*
+X0085550Y0035597D01*
+X0084050Y0035597D01*
+X0082300Y0035597D02*
+X0080800Y0031097D01*
+X0079300Y0035597D01*
+X0076550Y0035597D02*
+X0075050Y0035597D01*
+X0076550Y0035597D02*
+X0076612Y0035595D01*
+X0076673Y0035589D01*
+X0076734Y0035580D01*
+X0076794Y0035567D01*
+X0076853Y0035550D01*
+X0076911Y0035529D01*
+X0076968Y0035505D01*
+X0077023Y0035478D01*
+X0077076Y0035447D01*
+X0077128Y0035413D01*
+X0077177Y0035376D01*
+X0077224Y0035336D01*
+X0077268Y0035293D01*
+X0077309Y0035248D01*
+X0077348Y0035200D01*
+X0077384Y0035149D01*
+X0077416Y0035097D01*
+X0077445Y0035043D01*
+X0077471Y0034987D01*
+X0077493Y0034929D01*
+X0077512Y0034871D01*
+X0077527Y0034811D01*
+X0077538Y0034750D01*
+X0077546Y0034689D01*
+X0077550Y0034628D01*
+X0077550Y0034566D01*
+X0077546Y0034505D01*
+X0077538Y0034444D01*
+X0077527Y0034383D01*
+X0077512Y0034323D01*
+X0077493Y0034265D01*
+X0077471Y0034207D01*
+X0077445Y0034151D01*
+X0077416Y0034097D01*
+X0077384Y0034045D01*
+X0077348Y0033994D01*
+X0077309Y0033946D01*
+X0077268Y0033901D01*
+X0077224Y0033858D01*
+X0077177Y0033818D01*
+X0077128Y0033781D01*
+X0077076Y0033747D01*
+X0077023Y0033716D01*
+X0076968Y0033689D01*
+X0076911Y0033665D01*
+X0076853Y0033644D01*
+X0076794Y0033627D01*
+X0076734Y0033614D01*
+X0076673Y0033605D01*
+X0076612Y0033599D01*
+X0076550Y0033597D01*
+X0075550Y0033597D01*
+X0076300Y0033597D02*
+X0076369Y0033595D01*
+X0076438Y0033589D01*
+X0076506Y0033580D01*
+X0076573Y0033567D01*
+X0076640Y0033550D01*
+X0076706Y0033529D01*
+X0076770Y0033505D01*
+X0076833Y0033477D01*
+X0076895Y0033446D01*
+X0076955Y0033412D01*
+X0077012Y0033374D01*
+X0077068Y0033333D01*
+X0077121Y0033290D01*
+X0077172Y0033243D01*
+X0077220Y0033194D01*
+X0077265Y0033142D01*
+X0077307Y0033087D01*
+X0077346Y0033031D01*
+X0077383Y0032972D01*
+X0077415Y0032911D01*
+X0077445Y0032849D01*
+X0077471Y0032785D01*
+X0077493Y0032720D01*
+X0077512Y0032654D01*
+X0077527Y0032587D01*
+X0077538Y0032519D01*
+X0077546Y0032450D01*
+X0077550Y0032381D01*
+X0077550Y0032313D01*
+X0077546Y0032244D01*
+X0077538Y0032175D01*
+X0077527Y0032107D01*
+X0077512Y0032040D01*
+X0077493Y0031974D01*
+X0077471Y0031909D01*
+X0077445Y0031845D01*
+X0077415Y0031783D01*
+X0077383Y0031722D01*
+X0077346Y0031663D01*
+X0077307Y0031607D01*
+X0077265Y0031552D01*
+X0077220Y0031500D01*
+X0077172Y0031451D01*
+X0077121Y0031404D01*
+X0077068Y0031361D01*
+X0077012Y0031320D01*
+X0076955Y0031282D01*
+X0076895Y0031248D01*
+X0076833Y0031217D01*
+X0076770Y0031189D01*
+X0076706Y0031165D01*
+X0076640Y0031144D01*
+X0076573Y0031127D01*
+X0076506Y0031114D01*
+X0076438Y0031105D01*
+X0076369Y0031099D01*
+X0076300Y0031097D01*
+X0075050Y0031097D01*
+X0073250Y0030597D02*
+X0071250Y0030597D01*
+X0068200Y0031097D02*
+X0069450Y0035597D01*
+X0066950Y0035597D01*
+X0066950Y0035097D01*
+X0063950Y0035597D02*
+X0062450Y0035597D01*
+X0063950Y0035597D02*
+X0064012Y0035595D01*
+X0064073Y0035589D01*
+X0064134Y0035580D01*
+X0064194Y0035567D01*
+X0064253Y0035550D01*
+X0064311Y0035529D01*
+X0064368Y0035505D01*
+X0064423Y0035478D01*
+X0064476Y0035447D01*
+X0064528Y0035413D01*
+X0064577Y0035376D01*
+X0064624Y0035336D01*
+X0064668Y0035293D01*
+X0064709Y0035248D01*
+X0064748Y0035200D01*
+X0064784Y0035149D01*
+X0064816Y0035097D01*
+X0064845Y0035043D01*
+X0064871Y0034987D01*
+X0064893Y0034929D01*
+X0064912Y0034871D01*
+X0064927Y0034811D01*
+X0064938Y0034750D01*
+X0064946Y0034689D01*
+X0064950Y0034628D01*
+X0064950Y0034566D01*
+X0064946Y0034505D01*
+X0064938Y0034444D01*
+X0064927Y0034383D01*
+X0064912Y0034323D01*
+X0064893Y0034265D01*
+X0064871Y0034207D01*
+X0064845Y0034151D01*
+X0064816Y0034097D01*
+X0064784Y0034045D01*
+X0064748Y0033994D01*
+X0064709Y0033946D01*
+X0064668Y0033901D01*
+X0064624Y0033858D01*
+X0064577Y0033818D01*
+X0064528Y0033781D01*
+X0064476Y0033747D01*
+X0064423Y0033716D01*
+X0064368Y0033689D01*
+X0064311Y0033665D01*
+X0064253Y0033644D01*
+X0064194Y0033627D01*
+X0064134Y0033614D01*
+X0064073Y0033605D01*
+X0064012Y0033599D01*
+X0063950Y0033597D01*
+X0062950Y0033597D01*
+X0063700Y0033597D02*
+X0063769Y0033595D01*
+X0063838Y0033589D01*
+X0063906Y0033580D01*
+X0063973Y0033567D01*
+X0064040Y0033550D01*
+X0064106Y0033529D01*
+X0064170Y0033505D01*
+X0064233Y0033477D01*
+X0064295Y0033446D01*
+X0064355Y0033412D01*
+X0064412Y0033374D01*
+X0064468Y0033333D01*
+X0064521Y0033290D01*
+X0064572Y0033243D01*
+X0064620Y0033194D01*
+X0064665Y0033142D01*
+X0064707Y0033087D01*
+X0064746Y0033031D01*
+X0064783Y0032972D01*
+X0064815Y0032911D01*
+X0064845Y0032849D01*
+X0064871Y0032785D01*
+X0064893Y0032720D01*
+X0064912Y0032654D01*
+X0064927Y0032587D01*
+X0064938Y0032519D01*
+X0064946Y0032450D01*
+X0064950Y0032381D01*
+X0064950Y0032313D01*
+X0064946Y0032244D01*
+X0064938Y0032175D01*
+X0064927Y0032107D01*
+X0064912Y0032040D01*
+X0064893Y0031974D01*
+X0064871Y0031909D01*
+X0064845Y0031845D01*
+X0064815Y0031783D01*
+X0064783Y0031722D01*
+X0064746Y0031663D01*
+X0064707Y0031607D01*
+X0064665Y0031552D01*
+X0064620Y0031500D01*
+X0064572Y0031451D01*
+X0064521Y0031404D01*
+X0064468Y0031361D01*
+X0064412Y0031320D01*
+X0064355Y0031282D01*
+X0064295Y0031248D01*
+X0064233Y0031217D01*
+X0064170Y0031189D01*
+X0064106Y0031165D01*
+X0064040Y0031144D01*
+X0063973Y0031127D01*
+X0063906Y0031114D01*
+X0063838Y0031105D01*
+X0063769Y0031099D01*
+X0063700Y0031097D01*
+X0062450Y0031097D01*
+X0060450Y0033097D02*
+X0060450Y0034347D01*
+X0060448Y0034416D01*
+X0060442Y0034485D01*
+X0060433Y0034553D01*
+X0060420Y0034620D01*
+X0060403Y0034687D01*
+X0060382Y0034753D01*
+X0060358Y0034817D01*
+X0060330Y0034880D01*
+X0060299Y0034942D01*
+X0060265Y0035002D01*
+X0060227Y0035059D01*
+X0060186Y0035115D01*
+X0060143Y0035168D01*
+X0060096Y0035219D01*
+X0060047Y0035267D01*
+X0059995Y0035312D01*
+X0059940Y0035354D01*
+X0059884Y0035393D01*
+X0059825Y0035430D01*
+X0059764Y0035462D01*
+X0059702Y0035492D01*
+X0059638Y0035518D01*
+X0059573Y0035540D01*
+X0059507Y0035559D01*
+X0059440Y0035574D01*
+X0059372Y0035585D01*
+X0059303Y0035593D01*
+X0059234Y0035597D01*
+X0059166Y0035597D01*
+X0059097Y0035593D01*
+X0059028Y0035585D01*
+X0058960Y0035574D01*
+X0058893Y0035559D01*
+X0058827Y0035540D01*
+X0058762Y0035518D01*
+X0058698Y0035492D01*
+X0058636Y0035462D01*
+X0058575Y0035430D01*
+X0058516Y0035393D01*
+X0058460Y0035354D01*
+X0058405Y0035312D01*
+X0058353Y0035267D01*
+X0058304Y0035219D01*
+X0058257Y0035168D01*
+X0058214Y0035115D01*
+X0058173Y0035059D01*
+X0058135Y0035002D01*
+X0058101Y0034942D01*
+X0058070Y0034880D01*
+X0058042Y0034817D01*
+X0058018Y0034753D01*
+X0057997Y0034687D01*
+X0057980Y0034620D01*
+X0057967Y0034553D01*
+X0057958Y0034485D01*
+X0057952Y0034416D01*
+X0057950Y0034347D01*
+X0057950Y0034097D01*
+X0057952Y0034037D01*
+X0057957Y0033976D01*
+X0057966Y0033917D01*
+X0057979Y0033858D01*
+X0057995Y0033799D01*
+X0058015Y0033742D01*
+X0058038Y0033687D01*
+X0058065Y0033632D01*
+X0058094Y0033580D01*
+X0058127Y0033529D01*
+X0058163Y0033480D01*
+X0058201Y0033434D01*
+X0058243Y0033390D01*
+X0058287Y0033348D01*
+X0058333Y0033310D01*
+X0058382Y0033274D01*
+X0058433Y0033241D01*
+X0058485Y0033212D01*
+X0058540Y0033185D01*
+X0058595Y0033162D01*
+X0058652Y0033142D01*
+X0058711Y0033126D01*
+X0058770Y0033113D01*
+X0058829Y0033104D01*
+X0058890Y0033099D01*
+X0058950Y0033097D01*
+X0060450Y0033097D01*
+X0060448Y0033010D01*
+X0060442Y0032923D01*
+X0060433Y0032836D01*
+X0060420Y0032750D01*
+X0060403Y0032664D01*
+X0060382Y0032579D01*
+X0060357Y0032496D01*
+X0060329Y0032413D01*
+X0060298Y0032332D01*
+X0060263Y0032252D01*
+X0060224Y0032174D01*
+X0060182Y0032097D01*
+X0060137Y0032022D01*
+X0060088Y0031950D01*
+X0060037Y0031879D01*
+X0059982Y0031811D01*
+X0059925Y0031746D01*
+X0059864Y0031683D01*
+X0059801Y0031622D01*
+X0059736Y0031565D01*
+X0059668Y0031510D01*
+X0059597Y0031459D01*
+X0059525Y0031410D01*
+X0059450Y0031365D01*
+X0059373Y0031323D01*
+X0059295Y0031284D01*
+X0059215Y0031249D01*
+X0059134Y0031218D01*
+X0059051Y0031190D01*
+X0058968Y0031165D01*
+X0058883Y0031144D01*
+X0058797Y0031127D01*
+X0058711Y0031114D01*
+X0058624Y0031105D01*
+X0058537Y0031099D01*
+X0058450Y0031097D01*
+X0055950Y0031097D02*
+X0053450Y0031097D01*
+X0055575Y0033597D01*
+X0054825Y0035596D02*
+X0054752Y0035594D01*
+X0054680Y0035589D01*
+X0054608Y0035580D01*
+X0054536Y0035567D01*
+X0054465Y0035551D01*
+X0054395Y0035531D01*
+X0054327Y0035507D01*
+X0054259Y0035481D01*
+X0054193Y0035450D01*
+X0054128Y0035417D01*
+X0054066Y0035380D01*
+X0054005Y0035341D01*
+X0053946Y0035298D01*
+X0053889Y0035252D01*
+X0053835Y0035204D01*
+X0053784Y0035153D01*
+X0053734Y0035099D01*
+X0053688Y0035043D01*
+X0053645Y0034985D01*
+X0053604Y0034924D01*
+X0053567Y0034862D01*
+X0053533Y0034798D01*
+X0053502Y0034732D01*
+X0053474Y0034665D01*
+X0053450Y0034596D01*
+X0055575Y0033597D02*
+X0055621Y0033643D01*
+X0055665Y0033692D01*
+X0055705Y0033743D01*
+X0055743Y0033796D01*
+X0055778Y0033851D01*
+X0055810Y0033908D01*
+X0055839Y0033966D01*
+X0055865Y0034026D01*
+X0055887Y0034088D01*
+X0055906Y0034150D01*
+X0055922Y0034213D01*
+X0055934Y0034277D01*
+X0055943Y0034342D01*
+X0055948Y0034407D01*
+X0055950Y0034472D01*
+X0055948Y0034537D01*
+X0055942Y0034603D01*
+X0055933Y0034667D01*
+X0055920Y0034731D01*
+X0055903Y0034795D01*
+X0055882Y0034857D01*
+X0055858Y0034918D01*
+X0055830Y0034977D01*
+X0055799Y0035035D01*
+X0055765Y0035090D01*
+X0055727Y0035144D01*
+X0055687Y0035195D01*
+X0055643Y0035244D01*
+X0055597Y0035290D01*
+X0055548Y0035334D01*
+X0055497Y0035374D01*
+X0055443Y0035412D01*
+X0055388Y0035446D01*
+X0055330Y0035477D01*
+X0055271Y0035505D01*
+X0055210Y0035529D01*
+X0055148Y0035550D01*
+X0055084Y0035567D01*
+X0055020Y0035580D01*
+X0054956Y0035589D01*
+X0054890Y0035595D01*
+X0054825Y0035597D01*
+X0051250Y0035597D02*
+X0051250Y0031097D01*
+X0049750Y0033097D02*
+X0051250Y0035597D01*
+X0049750Y0033097D02*
+X0048250Y0035597D01*
+X0048250Y0031097D01*
+X0046310Y0031097D02*
+X0044310Y0031097D01*
+X0044310Y0035597D01*
+D14*
+X0045350Y0219036D02*
+X0042283Y0219036D01*
+X0029072Y0224747D02*
+X0029072Y0229347D01*
+X0027794Y0229347D02*
+X0030350Y0229347D01*
+X0026406Y0229347D02*
+X0023339Y0224747D01*
+X0021898Y0224747D02*
+X0019853Y0224747D01*
+X0019853Y0229347D01*
+X0021898Y0229347D01*
+X0023339Y0229347D02*
+X0026406Y0224747D01*
+X0021387Y0227302D02*
+X0019853Y0227302D01*
+X0017600Y0226024D02*
+X0017600Y0229347D01*
+X0015044Y0229347D02*
+X0015044Y0226024D01*
+X0015046Y0225954D01*
+X0015052Y0225883D01*
+X0015061Y0225814D01*
+X0015075Y0225745D01*
+X0015092Y0225676D01*
+X0015113Y0225609D01*
+X0015138Y0225543D01*
+X0015166Y0225479D01*
+X0015198Y0225416D01*
+X0015233Y0225355D01*
+X0015272Y0225296D01*
+X0015313Y0225239D01*
+X0015358Y0225185D01*
+X0015406Y0225133D01*
+X0015456Y0225084D01*
+X0015510Y0225037D01*
+X0015565Y0224994D01*
+X0015623Y0224954D01*
+X0015683Y0224917D01*
+X0015745Y0224884D01*
+X0015809Y0224854D01*
+X0015874Y0224827D01*
+X0015940Y0224804D01*
+X0016008Y0224785D01*
+X0016077Y0224770D01*
+X0016146Y0224758D01*
+X0016216Y0224750D01*
+X0016287Y0224746D01*
+X0016357Y0224746D01*
+X0016428Y0224750D01*
+X0016498Y0224758D01*
+X0016567Y0224770D01*
+X0016636Y0224785D01*
+X0016704Y0224804D01*
+X0016770Y0224827D01*
+X0016835Y0224854D01*
+X0016899Y0224884D01*
+X0016961Y0224917D01*
+X0017021Y0224954D01*
+X0017079Y0224994D01*
+X0017134Y0225037D01*
+X0017188Y0225084D01*
+X0017238Y0225133D01*
+X0017286Y0225185D01*
+X0017331Y0225239D01*
+X0017372Y0225296D01*
+X0017411Y0225355D01*
+X0017446Y0225416D01*
+X0017478Y0225479D01*
+X0017506Y0225543D01*
+X0017531Y0225609D01*
+X0017552Y0225676D01*
+X0017569Y0225745D01*
+X0017583Y0225814D01*
+X0017592Y0225883D01*
+X0017598Y0225954D01*
+X0017600Y0226024D01*
+X0253250Y0245997D02*
+X0257850Y0249063D01*
+X0257850Y0250752D02*
+X0257850Y0253308D01*
+X0257850Y0252030D02*
+X0253250Y0252030D01*
+X0254272Y0250752D01*
+X0253250Y0249063D02*
+X0257850Y0245997D01*
+X0290000Y0054847D02*
+X0290000Y0050247D01*
+X0292044Y0050247D01*
+X0293900Y0050247D02*
+X0293900Y0054847D01*
+X0295944Y0054847D01*
+X0297791Y0054847D02*
+X0299069Y0054847D01*
+X0297791Y0054847D02*
+X0297791Y0050247D01*
+X0299069Y0050247D01*
+X0299069Y0050246D02*
+X0299138Y0050248D01*
+X0299207Y0050253D01*
+X0299276Y0050263D01*
+X0299344Y0050276D01*
+X0299411Y0050293D01*
+X0299477Y0050313D01*
+X0299542Y0050337D01*
+X0299606Y0050364D01*
+X0299668Y0050395D01*
+X0299728Y0050429D01*
+X0299786Y0050466D01*
+X0299842Y0050507D01*
+X0299896Y0050550D01*
+X0299948Y0050596D01*
+X0299997Y0050645D01*
+X0300043Y0050697D01*
+X0300086Y0050751D01*
+X0300127Y0050807D01*
+X0300164Y0050865D01*
+X0300198Y0050925D01*
+X0300229Y0050987D01*
+X0300256Y0051051D01*
+X0300280Y0051116D01*
+X0300300Y0051182D01*
+X0300317Y0051249D01*
+X0300330Y0051317D01*
+X0300340Y0051386D01*
+X0300345Y0051455D01*
+X0300347Y0051524D01*
+X0300347Y0053569D01*
+X0300345Y0053638D01*
+X0300340Y0053707D01*
+X0300330Y0053776D01*
+X0300317Y0053844D01*
+X0300300Y0053911D01*
+X0300280Y0053977D01*
+X0300256Y0054042D01*
+X0300229Y0054106D01*
+X0300198Y0054168D01*
+X0300164Y0054228D01*
+X0300127Y0054286D01*
+X0300086Y0054342D01*
+X0300043Y0054396D01*
+X0299997Y0054448D01*
+X0299948Y0054497D01*
+X0299896Y0054543D01*
+X0299842Y0054586D01*
+X0299786Y0054627D01*
+X0299728Y0054664D01*
+X0299668Y0054698D01*
+X0299606Y0054729D01*
+X0299542Y0054756D01*
+X0299477Y0054780D01*
+X0299411Y0054800D01*
+X0299344Y0054817D01*
+X0299276Y0054830D01*
+X0299207Y0054840D01*
+X0299138Y0054845D01*
+X0299069Y0054847D01*
+X0302441Y0053824D02*
+X0303719Y0054847D01*
+X0303719Y0050247D01*
+X0302441Y0050247D02*
+X0304997Y0050247D01*
+X0310500Y0050247D02*
+X0312544Y0050247D01*
+X0314400Y0050247D02*
+X0314400Y0054847D01*
+X0316444Y0054847D01*
+X0318291Y0054847D02*
+X0319569Y0054847D01*
+X0318291Y0054847D02*
+X0318291Y0050247D01*
+X0319569Y0050247D01*
+X0319569Y0050246D02*
+X0319638Y0050248D01*
+X0319707Y0050253D01*
+X0319776Y0050263D01*
+X0319844Y0050276D01*
+X0319911Y0050293D01*
+X0319977Y0050313D01*
+X0320042Y0050337D01*
+X0320106Y0050364D01*
+X0320168Y0050395D01*
+X0320228Y0050429D01*
+X0320286Y0050466D01*
+X0320342Y0050507D01*
+X0320396Y0050550D01*
+X0320448Y0050596D01*
+X0320497Y0050645D01*
+X0320543Y0050697D01*
+X0320586Y0050751D01*
+X0320627Y0050807D01*
+X0320664Y0050865D01*
+X0320698Y0050925D01*
+X0320729Y0050987D01*
+X0320756Y0051051D01*
+X0320780Y0051116D01*
+X0320800Y0051182D01*
+X0320817Y0051249D01*
+X0320830Y0051317D01*
+X0320840Y0051386D01*
+X0320845Y0051455D01*
+X0320847Y0051524D01*
+X0320847Y0053569D01*
+X0320845Y0053638D01*
+X0320840Y0053707D01*
+X0320830Y0053776D01*
+X0320817Y0053844D01*
+X0320800Y0053911D01*
+X0320780Y0053977D01*
+X0320756Y0054042D01*
+X0320729Y0054106D01*
+X0320698Y0054168D01*
+X0320664Y0054228D01*
+X0320627Y0054286D01*
+X0320586Y0054342D01*
+X0320543Y0054396D01*
+X0320497Y0054448D01*
+X0320448Y0054497D01*
+X0320396Y0054543D01*
+X0320342Y0054586D01*
+X0320286Y0054627D01*
+X0320228Y0054664D01*
+X0320168Y0054698D01*
+X0320106Y0054729D01*
+X0320042Y0054756D01*
+X0319977Y0054780D01*
+X0319911Y0054800D01*
+X0319844Y0054817D01*
+X0319776Y0054830D01*
+X0319707Y0054840D01*
+X0319638Y0054845D01*
+X0319569Y0054847D01*
+X0315933Y0052802D02*
+X0314400Y0052802D01*
+X0314400Y0050247D02*
+X0316444Y0050247D01*
+X0310500Y0050247D02*
+X0310500Y0054847D01*
+X0322941Y0050247D02*
+X0325497Y0050247D01*
+X0322941Y0050247D02*
+X0325113Y0052802D01*
+X0324347Y0054846D02*
+X0324273Y0054844D01*
+X0324199Y0054839D01*
+X0324125Y0054829D01*
+X0324052Y0054816D01*
+X0323979Y0054800D01*
+X0323908Y0054779D01*
+X0323838Y0054755D01*
+X0323769Y0054728D01*
+X0323701Y0054697D01*
+X0323635Y0054663D01*
+X0323571Y0054626D01*
+X0323509Y0054585D01*
+X0323449Y0054541D01*
+X0323391Y0054495D01*
+X0323335Y0054445D01*
+X0323282Y0054393D01*
+X0323232Y0054338D01*
+X0323185Y0054281D01*
+X0323141Y0054221D01*
+X0323099Y0054159D01*
+X0323061Y0054096D01*
+X0323026Y0054030D01*
+X0322995Y0053963D01*
+X0322967Y0053894D01*
+X0322942Y0053824D01*
+X0325113Y0052803D02*
+X0325160Y0052850D01*
+X0325204Y0052900D01*
+X0325246Y0052952D01*
+X0325285Y0053006D01*
+X0325320Y0053062D01*
+X0325353Y0053120D01*
+X0325383Y0053180D01*
+X0325409Y0053241D01*
+X0325432Y0053304D01*
+X0325451Y0053368D01*
+X0325467Y0053432D01*
+X0325480Y0053498D01*
+X0325489Y0053564D01*
+X0325494Y0053630D01*
+X0325496Y0053697D01*
+X0325497Y0053697D02*
+X0325495Y0053764D01*
+X0325489Y0053831D01*
+X0325480Y0053897D01*
+X0325466Y0053962D01*
+X0325449Y0054027D01*
+X0325428Y0054090D01*
+X0325403Y0054152D01*
+X0325375Y0054213D01*
+X0325343Y0054272D01*
+X0325308Y0054329D01*
+X0325269Y0054384D01*
+X0325228Y0054436D01*
+X0325183Y0054486D01*
+X0325136Y0054533D01*
+X0325086Y0054578D01*
+X0325034Y0054619D01*
+X0324979Y0054658D01*
+X0324922Y0054693D01*
+X0324863Y0054725D01*
+X0324802Y0054753D01*
+X0324740Y0054778D01*
+X0324677Y0054799D01*
+X0324612Y0054816D01*
+X0324547Y0054830D01*
+X0324481Y0054839D01*
+X0324414Y0054845D01*
+X0324347Y0054847D01*
+X0295944Y0050247D02*
+X0293900Y0050247D01*
+X0293900Y0052802D02*
+X0295433Y0052802D01*
+D15*
+X0067900Y0219636D02*
+X0065433Y0219636D01*
+X0066667Y0220869D02*
+X0066667Y0218402D01*
+D16*
+X0073600Y0264947D03*
+X0085000Y0026647D03*
+D17*
+X0084050Y0014547D03*
+X0049550Y0014547D03*
+X0074550Y0277047D03*
+X0109050Y0277047D03*
+D18*
+X0101800Y0278047D03*
+X0091800Y0278047D03*
+X0081800Y0278047D03*
+X0076800Y0013547D03*
+X0066800Y0013547D03*
+X0056800Y0013547D03*
+D19*
+X0061800Y0014547D03*
+X0071800Y0014547D03*
+X0086800Y0277047D03*
+X0096800Y0277047D03*
+D20*
+X0194650Y0277247D02*
+X0194650Y0273747D01*
+X0194652Y0273674D01*
+X0194658Y0273601D01*
+X0194667Y0273528D01*
+X0194681Y0273456D01*
+X0194698Y0273385D01*
+X0194719Y0273314D01*
+X0194743Y0273245D01*
+X0194771Y0273178D01*
+X0194803Y0273111D01*
+X0194838Y0273047D01*
+X0194876Y0272985D01*
+X0194917Y0272924D01*
+X0194962Y0272866D01*
+X0195010Y0272810D01*
+X0195060Y0272757D01*
+X0195113Y0272707D01*
+X0195169Y0272659D01*
+X0195227Y0272614D01*
+X0195288Y0272573D01*
+X0195350Y0272535D01*
+X0195414Y0272500D01*
+X0195481Y0272468D01*
+X0195548Y0272440D01*
+X0195617Y0272416D01*
+X0195688Y0272395D01*
+X0195759Y0272378D01*
+X0195831Y0272364D01*
+X0195904Y0272355D01*
+X0195977Y0272349D01*
+X0196050Y0272347D01*
+X0198150Y0272347D01*
+X0198150Y0275847D01*
+X0197100Y0275847D01*
+X0194650Y0277247D02*
+X0194652Y0277320D01*
+X0194658Y0277393D01*
+X0194667Y0277466D01*
+X0194681Y0277538D01*
+X0194698Y0277609D01*
+X0194719Y0277680D01*
+X0194743Y0277749D01*
+X0194771Y0277816D01*
+X0194803Y0277883D01*
+X0194838Y0277947D01*
+X0194876Y0278009D01*
+X0194917Y0278070D01*
+X0194962Y0278128D01*
+X0195010Y0278184D01*
+X0195060Y0278237D01*
+X0195113Y0278287D01*
+X0195169Y0278335D01*
+X0195227Y0278380D01*
+X0195288Y0278421D01*
+X0195350Y0278459D01*
+X0195414Y0278494D01*
+X0195481Y0278526D01*
+X0195548Y0278554D01*
+X0195617Y0278578D01*
+X0195688Y0278599D01*
+X0195759Y0278616D01*
+X0195831Y0278630D01*
+X0195904Y0278639D01*
+X0195977Y0278645D01*
+X0196050Y0278647D01*
+X0198150Y0278647D01*
+X0201306Y0278647D02*
+X0203056Y0278647D01*
+X0201306Y0278647D02*
+X0201306Y0272347D01*
+X0201306Y0275147D02*
+X0203056Y0275147D01*
+X0203138Y0275149D01*
+X0203220Y0275155D01*
+X0203301Y0275164D01*
+X0203382Y0275178D01*
+X0203463Y0275195D01*
+X0203542Y0275216D01*
+X0203620Y0275240D01*
+X0203697Y0275269D01*
+X0203773Y0275301D01*
+X0203847Y0275336D01*
+X0203919Y0275375D01*
+X0203990Y0275417D01*
+X0204058Y0275462D01*
+X0204124Y0275511D01*
+X0204188Y0275562D01*
+X0204249Y0275617D01*
+X0204308Y0275674D01*
+X0204364Y0275734D01*
+X0204417Y0275797D01*
+X0204467Y0275862D01*
+X0204514Y0275929D01*
+X0204558Y0275998D01*
+X0204598Y0276070D01*
+X0204635Y0276143D01*
+X0204669Y0276218D01*
+X0204699Y0276294D01*
+X0204725Y0276372D01*
+X0204748Y0276451D01*
+X0204767Y0276530D01*
+X0204782Y0276611D01*
+X0204794Y0276692D01*
+X0204802Y0276774D01*
+X0204806Y0276856D01*
+X0204806Y0276938D01*
+X0204802Y0277020D01*
+X0204794Y0277102D01*
+X0204782Y0277183D01*
+X0204767Y0277264D01*
+X0204748Y0277343D01*
+X0204725Y0277422D01*
+X0204699Y0277500D01*
+X0204669Y0277576D01*
+X0204635Y0277651D01*
+X0204598Y0277724D01*
+X0204558Y0277796D01*
+X0204514Y0277865D01*
+X0204467Y0277932D01*
+X0204417Y0277997D01*
+X0204364Y0278060D01*
+X0204308Y0278120D01*
+X0204249Y0278177D01*
+X0204188Y0278232D01*
+X0204124Y0278283D01*
+X0204058Y0278332D01*
+X0203990Y0278377D01*
+X0203919Y0278419D01*
+X0203847Y0278458D01*
+X0203773Y0278493D01*
+X0203697Y0278525D01*
+X0203620Y0278554D01*
+X0203542Y0278578D01*
+X0203463Y0278599D01*
+X0203382Y0278616D01*
+X0203301Y0278630D01*
+X0203220Y0278639D01*
+X0203138Y0278645D01*
+X0203056Y0278647D01*
+X0206982Y0278647D02*
+X0208382Y0278647D01*
+X0207682Y0278647D02*
+X0207682Y0272347D01*
+X0206982Y0272347D02*
+X0208382Y0272347D01*
+X0210856Y0274097D02*
+X0210856Y0276897D01*
+X0210858Y0276979D01*
+X0210864Y0277061D01*
+X0210873Y0277142D01*
+X0210887Y0277223D01*
+X0210904Y0277304D01*
+X0210925Y0277383D01*
+X0210949Y0277461D01*
+X0210978Y0277538D01*
+X0211010Y0277614D01*
+X0211045Y0277688D01*
+X0211084Y0277760D01*
+X0211126Y0277831D01*
+X0211171Y0277899D01*
+X0211220Y0277965D01*
+X0211271Y0278029D01*
+X0211326Y0278090D01*
+X0211383Y0278149D01*
+X0211443Y0278205D01*
+X0211506Y0278258D01*
+X0211571Y0278308D01*
+X0211638Y0278355D01*
+X0211707Y0278399D01*
+X0211779Y0278439D01*
+X0211852Y0278476D01*
+X0211927Y0278510D01*
+X0212003Y0278540D01*
+X0212081Y0278566D01*
+X0212160Y0278589D01*
+X0212239Y0278608D01*
+X0212320Y0278623D01*
+X0212401Y0278635D01*
+X0212483Y0278643D01*
+X0212565Y0278647D01*
+X0212647Y0278647D01*
+X0212729Y0278643D01*
+X0212811Y0278635D01*
+X0212892Y0278623D01*
+X0212973Y0278608D01*
+X0213052Y0278589D01*
+X0213131Y0278566D01*
+X0213209Y0278540D01*
+X0213285Y0278510D01*
+X0213360Y0278476D01*
+X0213433Y0278439D01*
+X0213505Y0278399D01*
+X0213574Y0278355D01*
+X0213641Y0278308D01*
+X0213706Y0278258D01*
+X0213769Y0278205D01*
+X0213829Y0278149D01*
+X0213886Y0278090D01*
+X0213941Y0278029D01*
+X0213992Y0277965D01*
+X0214041Y0277899D01*
+X0214086Y0277831D01*
+X0214128Y0277760D01*
+X0214167Y0277688D01*
+X0214202Y0277614D01*
+X0214234Y0277538D01*
+X0214263Y0277461D01*
+X0214287Y0277383D01*
+X0214308Y0277304D01*
+X0214325Y0277223D01*
+X0214339Y0277142D01*
+X0214348Y0277061D01*
+X0214354Y0276979D01*
+X0214356Y0276897D01*
+X0214356Y0274097D01*
+X0214354Y0274015D01*
+X0214348Y0273933D01*
+X0214339Y0273852D01*
+X0214325Y0273771D01*
+X0214308Y0273690D01*
+X0214287Y0273611D01*
+X0214263Y0273533D01*
+X0214234Y0273456D01*
+X0214202Y0273380D01*
+X0214167Y0273306D01*
+X0214128Y0273234D01*
+X0214086Y0273163D01*
+X0214041Y0273095D01*
+X0213992Y0273029D01*
+X0213941Y0272965D01*
+X0213886Y0272904D01*
+X0213829Y0272845D01*
+X0213769Y0272789D01*
+X0213706Y0272736D01*
+X0213641Y0272686D01*
+X0213574Y0272639D01*
+X0213505Y0272595D01*
+X0213433Y0272555D01*
+X0213360Y0272518D01*
+X0213285Y0272484D01*
+X0213209Y0272454D01*
+X0213131Y0272428D01*
+X0213052Y0272405D01*
+X0212973Y0272386D01*
+X0212892Y0272371D01*
+X0212811Y0272359D01*
+X0212729Y0272351D01*
+X0212647Y0272347D01*
+X0212565Y0272347D01*
+X0212483Y0272351D01*
+X0212401Y0272359D01*
+X0212320Y0272371D01*
+X0212239Y0272386D01*
+X0212160Y0272405D01*
+X0212081Y0272428D01*
+X0212003Y0272454D01*
+X0211927Y0272484D01*
+X0211852Y0272518D01*
+X0211779Y0272555D01*
+X0211707Y0272595D01*
+X0211638Y0272639D01*
+X0211571Y0272686D01*
+X0211506Y0272736D01*
+X0211443Y0272789D01*
+X0211383Y0272845D01*
+X0211326Y0272904D01*
+X0211271Y0272965D01*
+X0211220Y0273029D01*
+X0211171Y0273095D01*
+X0211126Y0273163D01*
+X0211084Y0273234D01*
+X0211045Y0273306D01*
+X0211010Y0273380D01*
+X0210978Y0273456D01*
+X0210949Y0273533D01*
+X0210925Y0273611D01*
+X0210904Y0273690D01*
+X0210887Y0273771D01*
+X0210873Y0273852D01*
+X0210864Y0273933D01*
+X0210858Y0274015D01*
+X0210856Y0274097D01*
+D21*
+X0196800Y0237897D03*
+D22*
+X0196050Y0238647D03*
+X0197550Y0238647D03*
+D23*
+X0196800Y0237097D03*
+M02*
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.pls b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.pls
new file mode 100755
index 0000000..16596c0
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.pls
@@ -0,0 +1,5239 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+%ADD10C,0.00000*%
+%ADD11C,0.00600*%
+%ADD12C,0.00400*%
+%ADD13C,0.00300*%
+%ADD14C,0.01000*%
+%ADD15C,0.01200*%
+%ADD16C,0.00200*%
+%ADD17C,0.00800*%
+%ADD18R,0.02657X0.09646*%
+D10*
+X0001800Y0012047D02*
+X0001800Y0279507D01*
+X0378001Y0279507D01*
+X0378001Y0012047D01*
+X0001800Y0012047D01*
+D11*
+X0041800Y0049547D02*
+X0041800Y0050797D01*
+X0041800Y0049547D02*
+X0050550Y0049547D01*
+X0054300Y0049547D01*
+X0054300Y0050797D01*
+X0054300Y0055797D02*
+X0054300Y0057047D01*
+X0050550Y0057047D01*
+X0041800Y0057047D01*
+X0041800Y0055797D01*
+X0101800Y0034547D02*
+X0101800Y0024547D01*
+X0101800Y0022047D01*
+X0103050Y0022047D01*
+X0110550Y0022047D02*
+X0111800Y0022047D01*
+X0111800Y0024547D01*
+X0111800Y0034547D01*
+X0110550Y0034547D01*
+X0103050Y0034547D02*
+X0101800Y0034547D01*
+X0129350Y0173297D02*
+X0133550Y0173297D01*
+X0137550Y0173297D01*
+X0141750Y0173297D01*
+X0141826Y0173299D01*
+X0141902Y0173305D01*
+X0141977Y0173314D01*
+X0142052Y0173328D01*
+X0142126Y0173345D01*
+X0142199Y0173366D01*
+X0142271Y0173390D01*
+X0142342Y0173419D01*
+X0142411Y0173450D01*
+X0142478Y0173485D01*
+X0142543Y0173524D01*
+X0142607Y0173566D01*
+X0142668Y0173611D01*
+X0142727Y0173659D01*
+X0142783Y0173710D01*
+X0142837Y0173764D01*
+X0142888Y0173820D01*
+X0142936Y0173879D01*
+X0142981Y0173940D01*
+X0143023Y0174004D01*
+X0143062Y0174069D01*
+X0143097Y0174136D01*
+X0143128Y0174205D01*
+X0143157Y0174276D01*
+X0143181Y0174348D01*
+X0143202Y0174421D01*
+X0143219Y0174495D01*
+X0143233Y0174570D01*
+X0143242Y0174645D01*
+X0143248Y0174721D01*
+X0143250Y0174797D01*
+X0143250Y0191797D01*
+X0143248Y0191873D01*
+X0143242Y0191949D01*
+X0143233Y0192024D01*
+X0143219Y0192099D01*
+X0143202Y0192173D01*
+X0143181Y0192246D01*
+X0143157Y0192318D01*
+X0143128Y0192389D01*
+X0143097Y0192458D01*
+X0143062Y0192525D01*
+X0143023Y0192590D01*
+X0142981Y0192654D01*
+X0142936Y0192715D01*
+X0142888Y0192774D01*
+X0142837Y0192830D01*
+X0142783Y0192884D01*
+X0142727Y0192935D01*
+X0142668Y0192983D01*
+X0142607Y0193028D01*
+X0142543Y0193070D01*
+X0142478Y0193109D01*
+X0142411Y0193144D01*
+X0142342Y0193175D01*
+X0142271Y0193204D01*
+X0142199Y0193228D01*
+X0142126Y0193249D01*
+X0142052Y0193266D01*
+X0141977Y0193280D01*
+X0141902Y0193289D01*
+X0141826Y0193295D01*
+X0141750Y0193297D01*
+X0129350Y0193297D01*
+X0129274Y0193295D01*
+X0129198Y0193289D01*
+X0129123Y0193280D01*
+X0129048Y0193266D01*
+X0128974Y0193249D01*
+X0128901Y0193228D01*
+X0128829Y0193204D01*
+X0128758Y0193175D01*
+X0128689Y0193144D01*
+X0128622Y0193109D01*
+X0128557Y0193070D01*
+X0128493Y0193028D01*
+X0128432Y0192983D01*
+X0128373Y0192935D01*
+X0128317Y0192884D01*
+X0128263Y0192830D01*
+X0128212Y0192774D01*
+X0128164Y0192715D01*
+X0128119Y0192654D01*
+X0128077Y0192590D01*
+X0128038Y0192525D01*
+X0128003Y0192458D01*
+X0127972Y0192389D01*
+X0127943Y0192318D01*
+X0127919Y0192246D01*
+X0127898Y0192173D01*
+X0127881Y0192099D01*
+X0127867Y0192024D01*
+X0127858Y0191949D01*
+X0127852Y0191873D01*
+X0127850Y0191797D01*
+X0127850Y0174797D01*
+X0127852Y0174721D01*
+X0127858Y0174645D01*
+X0127867Y0174570D01*
+X0127881Y0174495D01*
+X0127898Y0174421D01*
+X0127919Y0174348D01*
+X0127943Y0174276D01*
+X0127972Y0174205D01*
+X0128003Y0174136D01*
+X0128038Y0174069D01*
+X0128077Y0174004D01*
+X0128119Y0173940D01*
+X0128164Y0173879D01*
+X0128212Y0173820D01*
+X0128263Y0173764D01*
+X0128317Y0173710D01*
+X0128373Y0173659D01*
+X0128432Y0173611D01*
+X0128493Y0173566D01*
+X0128557Y0173524D01*
+X0128622Y0173485D01*
+X0128689Y0173450D01*
+X0128758Y0173419D01*
+X0128829Y0173390D01*
+X0128901Y0173366D01*
+X0128974Y0173345D01*
+X0129048Y0173328D01*
+X0129123Y0173314D01*
+X0129198Y0173305D01*
+X0129274Y0173299D01*
+X0129350Y0173297D01*
+X0133550Y0173297D02*
+X0133552Y0173385D01*
+X0133558Y0173474D01*
+X0133568Y0173562D01*
+X0133581Y0173649D01*
+X0133599Y0173736D01*
+X0133620Y0173822D01*
+X0133645Y0173907D01*
+X0133674Y0173990D01*
+X0133707Y0174073D01*
+X0133743Y0174153D01*
+X0133782Y0174232D01*
+X0133825Y0174310D01*
+X0133872Y0174385D01*
+X0133922Y0174458D01*
+X0133975Y0174529D01*
+X0134031Y0174598D01*
+X0134090Y0174664D01*
+X0134152Y0174727D01*
+X0134216Y0174787D01*
+X0134283Y0174845D01*
+X0134353Y0174899D01*
+X0134425Y0174951D01*
+X0134499Y0174999D01*
+X0134576Y0175044D01*
+X0134654Y0175085D01*
+X0134734Y0175123D01*
+X0134815Y0175157D01*
+X0134898Y0175188D01*
+X0134983Y0175215D01*
+X0135068Y0175238D01*
+X0135154Y0175257D01*
+X0135242Y0175273D01*
+X0135329Y0175285D01*
+X0135417Y0175293D01*
+X0135506Y0175297D01*
+X0135594Y0175297D01*
+X0135683Y0175293D01*
+X0135771Y0175285D01*
+X0135858Y0175273D01*
+X0135946Y0175257D01*
+X0136032Y0175238D01*
+X0136117Y0175215D01*
+X0136202Y0175188D01*
+X0136285Y0175157D01*
+X0136366Y0175123D01*
+X0136446Y0175085D01*
+X0136524Y0175044D01*
+X0136601Y0174999D01*
+X0136675Y0174951D01*
+X0136747Y0174899D01*
+X0136817Y0174845D01*
+X0136884Y0174787D01*
+X0136948Y0174727D01*
+X0137010Y0174664D01*
+X0137069Y0174598D01*
+X0137125Y0174529D01*
+X0137178Y0174458D01*
+X0137228Y0174385D01*
+X0137275Y0174310D01*
+X0137318Y0174232D01*
+X0137357Y0174153D01*
+X0137393Y0174073D01*
+X0137426Y0173990D01*
+X0137455Y0173907D01*
+X0137480Y0173822D01*
+X0137501Y0173736D01*
+X0137519Y0173649D01*
+X0137532Y0173562D01*
+X0137542Y0173474D01*
+X0137548Y0173385D01*
+X0137550Y0173297D01*
+X0068867Y0216586D02*
+X0064600Y0216586D01*
+X0066733Y0218719D02*
+X0066733Y0214452D01*
+X0041367Y0216586D02*
+X0037100Y0216586D01*
+X0104300Y0232047D02*
+X0104300Y0234547D01*
+X0104300Y0232047D02*
+X0111800Y0232047D01*
+X0131800Y0232047D01*
+X0131800Y0234547D01*
+X0131800Y0247047D02*
+X0131800Y0249547D01*
+X0111800Y0249547D01*
+X0104300Y0249547D01*
+X0104300Y0247047D01*
+X0141800Y0245797D02*
+X0143050Y0245797D01*
+X0141800Y0245797D02*
+X0141800Y0260797D01*
+X0141800Y0268297D01*
+X0143050Y0268297D01*
+X0153050Y0268297D02*
+X0154300Y0268297D01*
+X0154300Y0260797D01*
+X0154300Y0245797D01*
+X0153050Y0245797D01*
+D12*
+X0156821Y0252070D02*
+X0159377Y0252070D01*
+X0159439Y0252072D01*
+X0159500Y0252077D01*
+X0159561Y0252087D01*
+X0159622Y0252100D01*
+X0159681Y0252116D01*
+X0159739Y0252136D01*
+X0159796Y0252160D01*
+X0159852Y0252187D01*
+X0159906Y0252217D01*
+X0159958Y0252251D01*
+X0160007Y0252287D01*
+X0160055Y0252327D01*
+X0160100Y0252369D01*
+X0160142Y0252414D01*
+X0160181Y0252462D01*
+X0160218Y0252511D01*
+X0160252Y0252563D01*
+X0160282Y0252617D01*
+X0160309Y0252673D01*
+X0160333Y0252730D01*
+X0160353Y0252788D01*
+X0160369Y0252847D01*
+X0160382Y0252908D01*
+X0160392Y0252969D01*
+X0160397Y0253030D01*
+X0160399Y0253092D01*
+X0160399Y0254114D01*
+X0159377Y0255833D02*
+X0160399Y0257110D01*
+X0155799Y0257110D01*
+X0155799Y0255833D02*
+X0155799Y0258388D01*
+X0155799Y0260333D02*
+X0155799Y0262888D01*
+X0155799Y0261610D02*
+X0160399Y0261610D01*
+X0159377Y0260333D01*
+X0155799Y0254114D02*
+X0155799Y0253092D01*
+X0155801Y0253030D01*
+X0155806Y0252969D01*
+X0155816Y0252908D01*
+X0155829Y0252847D01*
+X0155845Y0252788D01*
+X0155865Y0252730D01*
+X0155889Y0252673D01*
+X0155916Y0252617D01*
+X0155946Y0252563D01*
+X0155980Y0252511D01*
+X0156016Y0252462D01*
+X0156056Y0252414D01*
+X0156098Y0252369D01*
+X0156143Y0252327D01*
+X0156191Y0252287D01*
+X0156240Y0252251D01*
+X0156292Y0252217D01*
+X0156346Y0252187D01*
+X0156402Y0252160D01*
+X0156459Y0252136D01*
+X0156517Y0252116D01*
+X0156576Y0252100D01*
+X0156637Y0252087D01*
+X0156698Y0252077D01*
+X0156759Y0252072D01*
+X0156821Y0252070D01*
+X0175750Y0249136D02*
+X0177794Y0249136D01*
+X0176772Y0249902D02*
+X0176772Y0247347D01*
+X0180350Y0248369D01*
+X0180350Y0244341D02*
+X0180350Y0243063D01*
+X0175750Y0243063D01*
+X0175750Y0244341D01*
+X0175752Y0244411D01*
+X0175758Y0244482D01*
+X0175767Y0244551D01*
+X0175781Y0244620D01*
+X0175798Y0244689D01*
+X0175819Y0244756D01*
+X0175844Y0244822D01*
+X0175872Y0244886D01*
+X0175904Y0244949D01*
+X0175939Y0245010D01*
+X0175978Y0245069D01*
+X0176019Y0245126D01*
+X0176064Y0245180D01*
+X0176112Y0245232D01*
+X0176162Y0245281D01*
+X0176216Y0245328D01*
+X0176271Y0245371D01*
+X0176329Y0245411D01*
+X0176389Y0245448D01*
+X0176451Y0245481D01*
+X0176515Y0245511D01*
+X0176580Y0245538D01*
+X0176646Y0245561D01*
+X0176714Y0245580D01*
+X0176783Y0245595D01*
+X0176852Y0245607D01*
+X0176922Y0245615D01*
+X0176993Y0245619D01*
+X0177063Y0245619D01*
+X0177134Y0245615D01*
+X0177204Y0245607D01*
+X0177273Y0245595D01*
+X0177342Y0245580D01*
+X0177410Y0245561D01*
+X0177476Y0245538D01*
+X0177541Y0245511D01*
+X0177605Y0245481D01*
+X0177667Y0245448D01*
+X0177727Y0245411D01*
+X0177785Y0245371D01*
+X0177840Y0245328D01*
+X0177894Y0245281D01*
+X0177944Y0245232D01*
+X0177992Y0245180D01*
+X0178037Y0245126D01*
+X0178078Y0245069D01*
+X0178117Y0245010D01*
+X0178152Y0244949D01*
+X0178184Y0244886D01*
+X0178212Y0244822D01*
+X0178237Y0244756D01*
+X0178258Y0244689D01*
+X0178275Y0244620D01*
+X0178289Y0244551D01*
+X0178298Y0244482D01*
+X0178304Y0244411D01*
+X0178306Y0244341D01*
+X0178306Y0243063D01*
+X0178306Y0244341D02*
+X0178308Y0244404D01*
+X0178314Y0244467D01*
+X0178323Y0244529D01*
+X0178337Y0244590D01*
+X0178354Y0244651D01*
+X0178375Y0244710D01*
+X0178400Y0244768D01*
+X0178428Y0244825D01*
+X0178459Y0244879D01*
+X0178494Y0244931D01*
+X0178532Y0244982D01*
+X0178573Y0245030D01*
+X0178617Y0245075D01*
+X0178663Y0245117D01*
+X0178712Y0245157D01*
+X0178763Y0245193D01*
+X0178817Y0245226D01*
+X0178872Y0245256D01*
+X0178930Y0245282D01*
+X0178988Y0245305D01*
+X0179048Y0245324D01*
+X0179109Y0245339D01*
+X0179171Y0245351D01*
+X0179234Y0245359D01*
+X0179297Y0245363D01*
+X0179359Y0245363D01*
+X0179422Y0245359D01*
+X0179485Y0245351D01*
+X0179547Y0245339D01*
+X0179608Y0245324D01*
+X0179668Y0245305D01*
+X0179726Y0245282D01*
+X0179784Y0245256D01*
+X0179839Y0245226D01*
+X0179893Y0245193D01*
+X0179944Y0245157D01*
+X0179993Y0245117D01*
+X0180039Y0245075D01*
+X0180083Y0245030D01*
+X0180124Y0244982D01*
+X0180162Y0244931D01*
+X0180197Y0244879D01*
+X0180228Y0244825D01*
+X0180256Y0244768D01*
+X0180281Y0244710D01*
+X0180302Y0244651D01*
+X0180319Y0244590D01*
+X0180333Y0244529D01*
+X0180342Y0244467D01*
+X0180348Y0244404D01*
+X0180350Y0244341D01*
+X0177667Y0240541D02*
+X0178433Y0239136D01*
+X0180350Y0239647D02*
+X0180348Y0239729D01*
+X0180343Y0239811D01*
+X0180334Y0239893D01*
+X0180322Y0239974D01*
+X0180306Y0240055D01*
+X0180287Y0240135D01*
+X0180264Y0240214D01*
+X0180238Y0240292D01*
+X0180209Y0240369D01*
+X0180176Y0240444D01*
+X0180140Y0240518D01*
+X0180102Y0240591D01*
+X0180060Y0240662D01*
+X0180015Y0240730D01*
+X0179967Y0240797D01*
+X0178434Y0239136D02*
+X0178468Y0239082D01*
+X0178505Y0239031D01*
+X0178545Y0238982D01*
+X0178588Y0238935D01*
+X0178634Y0238892D01*
+X0178682Y0238851D01*
+X0178733Y0238813D01*
+X0178786Y0238778D01*
+X0178841Y0238746D01*
+X0178898Y0238718D01*
+X0178956Y0238694D01*
+X0179016Y0238673D01*
+X0179077Y0238656D01*
+X0179139Y0238642D01*
+X0179202Y0238633D01*
+X0179265Y0238627D01*
+X0179328Y0238625D01*
+X0179390Y0238627D01*
+X0179451Y0238632D01*
+X0179512Y0238642D01*
+X0179573Y0238655D01*
+X0179632Y0238671D01*
+X0179690Y0238691D01*
+X0179747Y0238715D01*
+X0179803Y0238742D01*
+X0179857Y0238772D01*
+X0179909Y0238806D01*
+X0179958Y0238843D01*
+X0180006Y0238882D01*
+X0180051Y0238924D01*
+X0180093Y0238969D01*
+X0180133Y0239017D01*
+X0180169Y0239066D01*
+X0180203Y0239118D01*
+X0180233Y0239172D01*
+X0180260Y0239228D01*
+X0180284Y0239285D01*
+X0180304Y0239343D01*
+X0180320Y0239402D01*
+X0180333Y0239463D01*
+X0180343Y0239524D01*
+X0180348Y0239585D01*
+X0180350Y0239647D01*
+X0176389Y0238497D02*
+X0176326Y0238561D01*
+X0176267Y0238629D01*
+X0176210Y0238698D01*
+X0176156Y0238770D01*
+X0176105Y0238844D01*
+X0176057Y0238920D01*
+X0176013Y0238997D01*
+X0175972Y0239077D01*
+X0175934Y0239158D01*
+X0175899Y0239241D01*
+X0175868Y0239325D01*
+X0175841Y0239411D01*
+X0175817Y0239497D01*
+X0175796Y0239585D01*
+X0175780Y0239673D01*
+X0175767Y0239762D01*
+X0175757Y0239851D01*
+X0175752Y0239940D01*
+X0175750Y0240030D01*
+X0175752Y0240092D01*
+X0175757Y0240153D01*
+X0175767Y0240214D01*
+X0175780Y0240275D01*
+X0175796Y0240334D01*
+X0175816Y0240392D01*
+X0175840Y0240449D01*
+X0175867Y0240505D01*
+X0175897Y0240559D01*
+X0175931Y0240611D01*
+X0175967Y0240660D01*
+X0176007Y0240708D01*
+X0176049Y0240753D01*
+X0176094Y0240795D01*
+X0176142Y0240835D01*
+X0176191Y0240871D01*
+X0176243Y0240905D01*
+X0176297Y0240935D01*
+X0176353Y0240962D01*
+X0176410Y0240986D01*
+X0176468Y0241006D01*
+X0176527Y0241022D01*
+X0176588Y0241035D01*
+X0176649Y0241045D01*
+X0176710Y0241050D01*
+X0176772Y0241052D01*
+X0176835Y0241050D01*
+X0176898Y0241044D01*
+X0176961Y0241035D01*
+X0177023Y0241021D01*
+X0177084Y0241004D01*
+X0177144Y0240983D01*
+X0177202Y0240959D01*
+X0177259Y0240931D01*
+X0177314Y0240899D01*
+X0177367Y0240864D01*
+X0177418Y0240826D01*
+X0177466Y0240785D01*
+X0177512Y0240742D01*
+X0177555Y0240695D01*
+X0177595Y0240646D01*
+X0177632Y0240595D01*
+X0177666Y0240541D01*
+X0126008Y0228639D02*
+X0126008Y0226084D01*
+X0126007Y0226084D02*
+X0126005Y0226022D01*
+X0126000Y0225961D01*
+X0125990Y0225900D01*
+X0125977Y0225839D01*
+X0125961Y0225780D01*
+X0125941Y0225722D01*
+X0125917Y0225665D01*
+X0125890Y0225609D01*
+X0125860Y0225555D01*
+X0125826Y0225503D01*
+X0125790Y0225454D01*
+X0125750Y0225406D01*
+X0125708Y0225361D01*
+X0125663Y0225319D01*
+X0125615Y0225279D01*
+X0125566Y0225243D01*
+X0125514Y0225209D01*
+X0125460Y0225179D01*
+X0125404Y0225152D01*
+X0125347Y0225128D01*
+X0125289Y0225108D01*
+X0125230Y0225092D01*
+X0125169Y0225079D01*
+X0125108Y0225069D01*
+X0125047Y0225064D01*
+X0124985Y0225062D01*
+X0123963Y0225062D01*
+X0122245Y0225062D02*
+X0119689Y0225062D01*
+X0120967Y0225062D02*
+X0120967Y0229662D01*
+X0122245Y0228639D01*
+X0123963Y0229662D02*
+X0124985Y0229662D01*
+X0124985Y0229661D02*
+X0125047Y0229659D01*
+X0125108Y0229654D01*
+X0125169Y0229644D01*
+X0125230Y0229631D01*
+X0125289Y0229615D01*
+X0125347Y0229595D01*
+X0125404Y0229571D01*
+X0125460Y0229544D01*
+X0125514Y0229514D01*
+X0125566Y0229480D01*
+X0125615Y0229444D01*
+X0125663Y0229404D01*
+X0125708Y0229362D01*
+X0125750Y0229317D01*
+X0125790Y0229269D01*
+X0125826Y0229220D01*
+X0125860Y0229168D01*
+X0125890Y0229114D01*
+X0125917Y0229058D01*
+X0125941Y0229001D01*
+X0125961Y0228943D01*
+X0125977Y0228884D01*
+X0125990Y0228823D01*
+X0126000Y0228762D01*
+X0126005Y0228701D01*
+X0126007Y0228639D01*
+X0117745Y0225062D02*
+X0115189Y0225062D01*
+X0117745Y0225062D02*
+X0115572Y0227617D01*
+X0116339Y0229661D02*
+X0116413Y0229659D01*
+X0116487Y0229654D01*
+X0116561Y0229644D01*
+X0116634Y0229631D01*
+X0116707Y0229615D01*
+X0116778Y0229594D01*
+X0116848Y0229570D01*
+X0116917Y0229543D01*
+X0116985Y0229512D01*
+X0117051Y0229478D01*
+X0117115Y0229441D01*
+X0117177Y0229400D01*
+X0117238Y0229356D01*
+X0117295Y0229310D01*
+X0117351Y0229260D01*
+X0117404Y0229208D01*
+X0117454Y0229153D01*
+X0117501Y0229096D01*
+X0117545Y0229036D01*
+X0117587Y0228974D01*
+X0117625Y0228911D01*
+X0117660Y0228845D01*
+X0117691Y0228778D01*
+X0117719Y0228709D01*
+X0117744Y0228639D01*
+X0115572Y0227618D02*
+X0115525Y0227665D01*
+X0115481Y0227715D01*
+X0115439Y0227767D01*
+X0115400Y0227821D01*
+X0115365Y0227877D01*
+X0115332Y0227935D01*
+X0115302Y0227995D01*
+X0115276Y0228056D01*
+X0115253Y0228119D01*
+X0115234Y0228183D01*
+X0115218Y0228247D01*
+X0115205Y0228313D01*
+X0115196Y0228379D01*
+X0115191Y0228445D01*
+X0115189Y0228512D01*
+X0115191Y0228579D01*
+X0115197Y0228646D01*
+X0115206Y0228712D01*
+X0115220Y0228777D01*
+X0115237Y0228842D01*
+X0115258Y0228905D01*
+X0115283Y0228967D01*
+X0115311Y0229028D01*
+X0115343Y0229087D01*
+X0115378Y0229144D01*
+X0115417Y0229199D01*
+X0115458Y0229251D01*
+X0115503Y0229301D01*
+X0115550Y0229348D01*
+X0115600Y0229393D01*
+X0115652Y0229434D01*
+X0115707Y0229473D01*
+X0115764Y0229508D01*
+X0115823Y0229540D01*
+X0115884Y0229568D01*
+X0115946Y0229593D01*
+X0116009Y0229614D01*
+X0116074Y0229631D01*
+X0116139Y0229645D01*
+X0116205Y0229654D01*
+X0116272Y0229660D01*
+X0116339Y0229662D01*
+X0081006Y0191846D02*
+X0081068Y0191844D01*
+X0081129Y0191839D01*
+X0081190Y0191829D01*
+X0081251Y0191816D01*
+X0081310Y0191800D01*
+X0081368Y0191780D01*
+X0081425Y0191756D01*
+X0081481Y0191729D01*
+X0081535Y0191699D01*
+X0081587Y0191665D01*
+X0081636Y0191629D01*
+X0081684Y0191589D01*
+X0081729Y0191547D01*
+X0081771Y0191502D01*
+X0081811Y0191454D01*
+X0081847Y0191405D01*
+X0081881Y0191353D01*
+X0081911Y0191299D01*
+X0081938Y0191243D01*
+X0081962Y0191186D01*
+X0081982Y0191128D01*
+X0081998Y0191069D01*
+X0082011Y0191008D01*
+X0082021Y0190947D01*
+X0082026Y0190886D01*
+X0082028Y0190824D01*
+X0081517Y0189930D02*
+X0080111Y0189163D01*
+X0080622Y0187247D02*
+X0080712Y0187249D01*
+X0080801Y0187254D01*
+X0080890Y0187264D01*
+X0080979Y0187277D01*
+X0081067Y0187293D01*
+X0081155Y0187314D01*
+X0081241Y0187338D01*
+X0081327Y0187365D01*
+X0081411Y0187396D01*
+X0081494Y0187431D01*
+X0081575Y0187469D01*
+X0081655Y0187510D01*
+X0081732Y0187554D01*
+X0081808Y0187602D01*
+X0081882Y0187653D01*
+X0081954Y0187707D01*
+X0082024Y0187764D01*
+X0082091Y0187823D01*
+X0082155Y0187886D01*
+X0080111Y0189163D02*
+X0080057Y0189129D01*
+X0080006Y0189092D01*
+X0079957Y0189052D01*
+X0079910Y0189009D01*
+X0079867Y0188963D01*
+X0079826Y0188915D01*
+X0079788Y0188864D01*
+X0079753Y0188811D01*
+X0079721Y0188756D01*
+X0079693Y0188699D01*
+X0079669Y0188641D01*
+X0079648Y0188581D01*
+X0079631Y0188520D01*
+X0079617Y0188458D01*
+X0079608Y0188395D01*
+X0079602Y0188332D01*
+X0079600Y0188269D01*
+X0079602Y0188207D01*
+X0079607Y0188146D01*
+X0079617Y0188085D01*
+X0079630Y0188024D01*
+X0079646Y0187965D01*
+X0079666Y0187907D01*
+X0079690Y0187850D01*
+X0079717Y0187794D01*
+X0079747Y0187740D01*
+X0079781Y0187688D01*
+X0079817Y0187639D01*
+X0079857Y0187591D01*
+X0079899Y0187546D01*
+X0079944Y0187504D01*
+X0079992Y0187464D01*
+X0080041Y0187428D01*
+X0080093Y0187394D01*
+X0080147Y0187364D01*
+X0080203Y0187337D01*
+X0080260Y0187313D01*
+X0080318Y0187293D01*
+X0080377Y0187277D01*
+X0080438Y0187264D01*
+X0080499Y0187254D01*
+X0080560Y0187249D01*
+X0080622Y0187247D01*
+X0079856Y0191464D02*
+X0079923Y0191512D01*
+X0079991Y0191557D01*
+X0080062Y0191599D01*
+X0080135Y0191637D01*
+X0080209Y0191673D01*
+X0080284Y0191706D01*
+X0080361Y0191735D01*
+X0080439Y0191761D01*
+X0080518Y0191784D01*
+X0080598Y0191803D01*
+X0080679Y0191819D01*
+X0080760Y0191831D01*
+X0080842Y0191840D01*
+X0080924Y0191845D01*
+X0081006Y0191847D01*
+X0082028Y0190824D02*
+X0082026Y0190761D01*
+X0082020Y0190698D01*
+X0082011Y0190635D01*
+X0081997Y0190573D01*
+X0081980Y0190512D01*
+X0081959Y0190452D01*
+X0081935Y0190394D01*
+X0081907Y0190337D01*
+X0081875Y0190282D01*
+X0081840Y0190229D01*
+X0081802Y0190178D01*
+X0081761Y0190130D01*
+X0081718Y0190084D01*
+X0081671Y0190041D01*
+X0081622Y0190001D01*
+X0081571Y0189964D01*
+X0081517Y0189930D01*
+X0077589Y0189802D02*
+X0076311Y0189802D01*
+X0076248Y0189804D01*
+X0076185Y0189810D01*
+X0076123Y0189819D01*
+X0076062Y0189833D01*
+X0076001Y0189850D01*
+X0075942Y0189871D01*
+X0075884Y0189896D01*
+X0075827Y0189924D01*
+X0075773Y0189955D01*
+X0075721Y0189990D01*
+X0075670Y0190028D01*
+X0075622Y0190069D01*
+X0075577Y0190113D01*
+X0075535Y0190159D01*
+X0075495Y0190208D01*
+X0075459Y0190259D01*
+X0075426Y0190313D01*
+X0075396Y0190368D01*
+X0075370Y0190426D01*
+X0075347Y0190484D01*
+X0075328Y0190544D01*
+X0075313Y0190605D01*
+X0075301Y0190667D01*
+X0075293Y0190730D01*
+X0075289Y0190793D01*
+X0075289Y0190855D01*
+X0075293Y0190918D01*
+X0075301Y0190981D01*
+X0075313Y0191043D01*
+X0075328Y0191104D01*
+X0075347Y0191164D01*
+X0075370Y0191222D01*
+X0075396Y0191280D01*
+X0075426Y0191335D01*
+X0075459Y0191389D01*
+X0075495Y0191440D01*
+X0075535Y0191489D01*
+X0075577Y0191535D01*
+X0075622Y0191579D01*
+X0075670Y0191620D01*
+X0075721Y0191658D01*
+X0075773Y0191693D01*
+X0075827Y0191724D01*
+X0075884Y0191752D01*
+X0075942Y0191777D01*
+X0076001Y0191798D01*
+X0076062Y0191815D01*
+X0076123Y0191829D01*
+X0076185Y0191838D01*
+X0076248Y0191844D01*
+X0076311Y0191846D01*
+X0076311Y0191847D02*
+X0077589Y0191847D01*
+X0077589Y0187247D01*
+X0076311Y0187247D01*
+X0076311Y0187246D02*
+X0076241Y0187248D01*
+X0076170Y0187254D01*
+X0076101Y0187263D01*
+X0076032Y0187277D01*
+X0075963Y0187294D01*
+X0075896Y0187315D01*
+X0075830Y0187340D01*
+X0075766Y0187368D01*
+X0075703Y0187400D01*
+X0075642Y0187435D01*
+X0075583Y0187474D01*
+X0075526Y0187515D01*
+X0075472Y0187560D01*
+X0075420Y0187608D01*
+X0075371Y0187658D01*
+X0075324Y0187712D01*
+X0075281Y0187767D01*
+X0075241Y0187825D01*
+X0075204Y0187885D01*
+X0075171Y0187947D01*
+X0075141Y0188011D01*
+X0075114Y0188076D01*
+X0075091Y0188142D01*
+X0075072Y0188210D01*
+X0075057Y0188279D01*
+X0075045Y0188348D01*
+X0075037Y0188418D01*
+X0075033Y0188489D01*
+X0075033Y0188559D01*
+X0075037Y0188630D01*
+X0075045Y0188700D01*
+X0075057Y0188769D01*
+X0075072Y0188838D01*
+X0075091Y0188906D01*
+X0075114Y0188972D01*
+X0075141Y0189037D01*
+X0075171Y0189101D01*
+X0075204Y0189163D01*
+X0075241Y0189223D01*
+X0075281Y0189281D01*
+X0075324Y0189336D01*
+X0075371Y0189390D01*
+X0075420Y0189440D01*
+X0075472Y0189488D01*
+X0075526Y0189533D01*
+X0075583Y0189574D01*
+X0075642Y0189613D01*
+X0075703Y0189648D01*
+X0075766Y0189680D01*
+X0075830Y0189708D01*
+X0075896Y0189733D01*
+X0075963Y0189754D01*
+X0076032Y0189771D01*
+X0076101Y0189785D01*
+X0076170Y0189794D01*
+X0076241Y0189800D01*
+X0076311Y0189802D01*
+X0073306Y0190824D02*
+X0072028Y0191847D01*
+X0072028Y0187247D01*
+X0073306Y0187247D02*
+X0070750Y0187247D01*
+X0120522Y0141847D02*
+X0122056Y0141847D01*
+X0120522Y0141846D02*
+X0120459Y0141844D01*
+X0120396Y0141838D01*
+X0120334Y0141829D01*
+X0120273Y0141815D01*
+X0120212Y0141798D01*
+X0120153Y0141777D01*
+X0120095Y0141752D01*
+X0120038Y0141724D01*
+X0119984Y0141693D01*
+X0119932Y0141658D01*
+X0119881Y0141620D01*
+X0119833Y0141579D01*
+X0119788Y0141535D01*
+X0119746Y0141489D01*
+X0119706Y0141440D01*
+X0119670Y0141389D01*
+X0119637Y0141335D01*
+X0119607Y0141280D01*
+X0119581Y0141222D01*
+X0119558Y0141164D01*
+X0119539Y0141104D01*
+X0119524Y0141043D01*
+X0119512Y0140981D01*
+X0119504Y0140918D01*
+X0119500Y0140855D01*
+X0119500Y0140793D01*
+X0119504Y0140730D01*
+X0119512Y0140667D01*
+X0119524Y0140605D01*
+X0119539Y0140544D01*
+X0119558Y0140484D01*
+X0119581Y0140426D01*
+X0119607Y0140368D01*
+X0119637Y0140313D01*
+X0119670Y0140259D01*
+X0119706Y0140208D01*
+X0119746Y0140159D01*
+X0119788Y0140113D01*
+X0119833Y0140069D01*
+X0119881Y0140028D01*
+X0119932Y0139990D01*
+X0119984Y0139955D01*
+X0120038Y0139924D01*
+X0120095Y0139896D01*
+X0120153Y0139871D01*
+X0120212Y0139850D01*
+X0120273Y0139833D01*
+X0120334Y0139819D01*
+X0120396Y0139810D01*
+X0120459Y0139804D01*
+X0120522Y0139802D01*
+X0121544Y0139802D01*
+X0120778Y0139802D02*
+X0120708Y0139800D01*
+X0120637Y0139794D01*
+X0120568Y0139785D01*
+X0120499Y0139771D01*
+X0120430Y0139754D01*
+X0120363Y0139733D01*
+X0120297Y0139708D01*
+X0120233Y0139680D01*
+X0120170Y0139648D01*
+X0120109Y0139613D01*
+X0120050Y0139574D01*
+X0119993Y0139533D01*
+X0119939Y0139488D01*
+X0119887Y0139440D01*
+X0119838Y0139390D01*
+X0119791Y0139336D01*
+X0119748Y0139281D01*
+X0119708Y0139223D01*
+X0119671Y0139163D01*
+X0119638Y0139101D01*
+X0119608Y0139037D01*
+X0119581Y0138972D01*
+X0119558Y0138906D01*
+X0119539Y0138838D01*
+X0119524Y0138769D01*
+X0119512Y0138700D01*
+X0119504Y0138630D01*
+X0119500Y0138559D01*
+X0119500Y0138489D01*
+X0119504Y0138418D01*
+X0119512Y0138348D01*
+X0119524Y0138279D01*
+X0119539Y0138210D01*
+X0119558Y0138142D01*
+X0119581Y0138076D01*
+X0119608Y0138011D01*
+X0119638Y0137947D01*
+X0119671Y0137885D01*
+X0119708Y0137825D01*
+X0119748Y0137767D01*
+X0119791Y0137712D01*
+X0119838Y0137658D01*
+X0119887Y0137608D01*
+X0119939Y0137560D01*
+X0119993Y0137515D01*
+X0120050Y0137474D01*
+X0120109Y0137435D01*
+X0120170Y0137400D01*
+X0120233Y0137368D01*
+X0120297Y0137340D01*
+X0120363Y0137315D01*
+X0120430Y0137294D01*
+X0120499Y0137277D01*
+X0120568Y0137263D01*
+X0120637Y0137254D01*
+X0120708Y0137248D01*
+X0120778Y0137246D01*
+X0120778Y0137247D02*
+X0122056Y0137247D01*
+X0123971Y0137247D02*
+X0124993Y0139291D01*
+X0125249Y0139291D02*
+X0126527Y0139291D01*
+X0125249Y0139291D02*
+X0125179Y0139293D01*
+X0125108Y0139299D01*
+X0125039Y0139308D01*
+X0124970Y0139322D01*
+X0124901Y0139339D01*
+X0124834Y0139360D01*
+X0124768Y0139385D01*
+X0124704Y0139413D01*
+X0124641Y0139445D01*
+X0124580Y0139480D01*
+X0124521Y0139519D01*
+X0124464Y0139560D01*
+X0124410Y0139605D01*
+X0124358Y0139653D01*
+X0124309Y0139703D01*
+X0124262Y0139757D01*
+X0124219Y0139812D01*
+X0124179Y0139870D01*
+X0124142Y0139930D01*
+X0124109Y0139992D01*
+X0124079Y0140056D01*
+X0124052Y0140121D01*
+X0124029Y0140187D01*
+X0124010Y0140255D01*
+X0123995Y0140324D01*
+X0123983Y0140393D01*
+X0123975Y0140463D01*
+X0123971Y0140534D01*
+X0123971Y0140604D01*
+X0123975Y0140675D01*
+X0123983Y0140745D01*
+X0123995Y0140814D01*
+X0124010Y0140883D01*
+X0124029Y0140951D01*
+X0124052Y0141017D01*
+X0124079Y0141082D01*
+X0124109Y0141146D01*
+X0124142Y0141208D01*
+X0124179Y0141268D01*
+X0124219Y0141326D01*
+X0124262Y0141381D01*
+X0124309Y0141435D01*
+X0124358Y0141485D01*
+X0124410Y0141533D01*
+X0124464Y0141578D01*
+X0124521Y0141619D01*
+X0124580Y0141658D01*
+X0124641Y0141693D01*
+X0124704Y0141725D01*
+X0124768Y0141753D01*
+X0124834Y0141778D01*
+X0124901Y0141799D01*
+X0124970Y0141816D01*
+X0125039Y0141830D01*
+X0125108Y0141839D01*
+X0125179Y0141845D01*
+X0125249Y0141847D01*
+X0126527Y0141847D01*
+X0126527Y0137247D01*
+X0096600Y0120597D02*
+X0096600Y0115997D01*
+X0095322Y0115997D01*
+X0095322Y0115996D02*
+X0095253Y0115998D01*
+X0095184Y0116003D01*
+X0095115Y0116013D01*
+X0095047Y0116026D01*
+X0094980Y0116043D01*
+X0094914Y0116063D01*
+X0094849Y0116087D01*
+X0094785Y0116114D01*
+X0094723Y0116145D01*
+X0094663Y0116179D01*
+X0094605Y0116216D01*
+X0094549Y0116257D01*
+X0094495Y0116300D01*
+X0094443Y0116346D01*
+X0094394Y0116395D01*
+X0094348Y0116447D01*
+X0094305Y0116501D01*
+X0094264Y0116557D01*
+X0094227Y0116615D01*
+X0094193Y0116675D01*
+X0094162Y0116737D01*
+X0094135Y0116801D01*
+X0094111Y0116866D01*
+X0094091Y0116932D01*
+X0094074Y0116999D01*
+X0094061Y0117067D01*
+X0094051Y0117136D01*
+X0094046Y0117205D01*
+X0094044Y0117274D01*
+X0094044Y0119319D01*
+X0094046Y0119388D01*
+X0094051Y0119457D01*
+X0094061Y0119526D01*
+X0094074Y0119594D01*
+X0094091Y0119661D01*
+X0094111Y0119727D01*
+X0094135Y0119792D01*
+X0094162Y0119856D01*
+X0094193Y0119918D01*
+X0094227Y0119978D01*
+X0094264Y0120036D01*
+X0094305Y0120092D01*
+X0094348Y0120146D01*
+X0094394Y0120198D01*
+X0094443Y0120247D01*
+X0094495Y0120293D01*
+X0094549Y0120336D01*
+X0094605Y0120377D01*
+X0094663Y0120414D01*
+X0094723Y0120448D01*
+X0094785Y0120479D01*
+X0094849Y0120506D01*
+X0094914Y0120530D01*
+X0094980Y0120550D01*
+X0095047Y0120567D01*
+X0095115Y0120580D01*
+X0095184Y0120590D01*
+X0095253Y0120595D01*
+X0095322Y0120597D01*
+X0096600Y0120597D01*
+X0091950Y0119574D02*
+X0090672Y0120597D01*
+X0090672Y0115997D01*
+X0091950Y0115997D02*
+X0089394Y0115997D01*
+X0047005Y0063146D02*
+X0045983Y0063146D01*
+X0047005Y0063146D02*
+X0047067Y0063144D01*
+X0047128Y0063139D01*
+X0047189Y0063129D01*
+X0047250Y0063116D01*
+X0047309Y0063100D01*
+X0047367Y0063080D01*
+X0047424Y0063056D01*
+X0047480Y0063029D01*
+X0047534Y0062999D01*
+X0047586Y0062965D01*
+X0047635Y0062929D01*
+X0047683Y0062889D01*
+X0047728Y0062847D01*
+X0047770Y0062802D01*
+X0047810Y0062754D01*
+X0047846Y0062705D01*
+X0047880Y0062653D01*
+X0047910Y0062599D01*
+X0047937Y0062543D01*
+X0047961Y0062486D01*
+X0047981Y0062428D01*
+X0047997Y0062369D01*
+X0048010Y0062308D01*
+X0048020Y0062247D01*
+X0048025Y0062186D01*
+X0048027Y0062124D01*
+X0048027Y0059568D01*
+X0048025Y0059506D01*
+X0048020Y0059445D01*
+X0048010Y0059384D01*
+X0047997Y0059323D01*
+X0047981Y0059264D01*
+X0047961Y0059206D01*
+X0047937Y0059149D01*
+X0047910Y0059093D01*
+X0047880Y0059039D01*
+X0047846Y0058987D01*
+X0047810Y0058938D01*
+X0047770Y0058890D01*
+X0047728Y0058845D01*
+X0047683Y0058803D01*
+X0047635Y0058763D01*
+X0047586Y0058727D01*
+X0047534Y0058693D01*
+X0047480Y0058663D01*
+X0047424Y0058636D01*
+X0047367Y0058612D01*
+X0047309Y0058592D01*
+X0047250Y0058576D01*
+X0047189Y0058563D01*
+X0047128Y0058553D01*
+X0047067Y0058548D01*
+X0047005Y0058546D01*
+X0045983Y0058546D01*
+X0044264Y0058546D02*
+X0041709Y0058546D01*
+X0042986Y0058546D02*
+X0042986Y0063146D01*
+X0044264Y0062124D01*
+X0114549Y0029110D02*
+X0114551Y0029169D01*
+X0114556Y0029227D01*
+X0114565Y0029285D01*
+X0114578Y0029342D01*
+X0114594Y0029399D01*
+X0114614Y0029454D01*
+X0114637Y0029508D01*
+X0114663Y0029560D01*
+X0114693Y0029611D01*
+X0114725Y0029660D01*
+X0114761Y0029707D01*
+X0114799Y0029751D01*
+X0114840Y0029793D01*
+X0114884Y0029832D01*
+X0114930Y0029869D01*
+X0114978Y0029902D01*
+X0115028Y0029933D01*
+X0115080Y0029960D01*
+X0115133Y0029984D01*
+X0115188Y0030005D01*
+X0114549Y0029110D02*
+X0114551Y0029051D01*
+X0114556Y0028993D01*
+X0114565Y0028935D01*
+X0114578Y0028878D01*
+X0114594Y0028821D01*
+X0114614Y0028766D01*
+X0114637Y0028712D01*
+X0114663Y0028660D01*
+X0114693Y0028609D01*
+X0114725Y0028560D01*
+X0114761Y0028513D01*
+X0114799Y0028469D01*
+X0114840Y0028427D01*
+X0114884Y0028388D01*
+X0114930Y0028351D01*
+X0114978Y0028318D01*
+X0115028Y0028287D01*
+X0115080Y0028260D01*
+X0115133Y0028236D01*
+X0115188Y0028215D01*
+X0115571Y0028088D02*
+X0118127Y0030133D01*
+X0118511Y0030005D02*
+X0118566Y0029984D01*
+X0118619Y0029960D01*
+X0118671Y0029933D01*
+X0118721Y0029902D01*
+X0118769Y0029869D01*
+X0118815Y0029832D01*
+X0118859Y0029793D01*
+X0118900Y0029751D01*
+X0118938Y0029707D01*
+X0118974Y0029660D01*
+X0119006Y0029611D01*
+X0119036Y0029560D01*
+X0119062Y0029508D01*
+X0119085Y0029454D01*
+X0119105Y0029399D01*
+X0119121Y0029342D01*
+X0119134Y0029285D01*
+X0119143Y0029227D01*
+X0119148Y0029169D01*
+X0119150Y0029110D01*
+X0119148Y0029051D01*
+X0119143Y0028993D01*
+X0119134Y0028935D01*
+X0119121Y0028878D01*
+X0119105Y0028821D01*
+X0119085Y0028766D01*
+X0119062Y0028712D01*
+X0119036Y0028660D01*
+X0119006Y0028609D01*
+X0118974Y0028560D01*
+X0118938Y0028513D01*
+X0118900Y0028469D01*
+X0118859Y0028427D01*
+X0118815Y0028388D01*
+X0118769Y0028351D01*
+X0118721Y0028318D01*
+X0118671Y0028287D01*
+X0118619Y0028260D01*
+X0118566Y0028236D01*
+X0118511Y0028215D01*
+X0118510Y0030005D02*
+X0118406Y0030053D01*
+X0118301Y0030099D01*
+X0118195Y0030141D01*
+X0118087Y0030180D01*
+X0117978Y0030216D01*
+X0117868Y0030248D01*
+X0117757Y0030278D01*
+X0117645Y0030303D01*
+X0117533Y0030326D01*
+X0117420Y0030345D01*
+X0117306Y0030360D01*
+X0117192Y0030372D01*
+X0117078Y0030381D01*
+X0116964Y0030386D01*
+X0116849Y0030388D01*
+X0116849Y0027832D02*
+X0116964Y0027834D01*
+X0117078Y0027839D01*
+X0117192Y0027848D01*
+X0117306Y0027860D01*
+X0117420Y0027875D01*
+X0117533Y0027894D01*
+X0117645Y0027917D01*
+X0117757Y0027942D01*
+X0117868Y0027972D01*
+X0117978Y0028004D01*
+X0118087Y0028040D01*
+X0118195Y0028079D01*
+X0118301Y0028121D01*
+X0118406Y0028167D01*
+X0118510Y0028215D01*
+X0116849Y0030388D02*
+X0116734Y0030386D01*
+X0116620Y0030381D01*
+X0116506Y0030372D01*
+X0116392Y0030360D01*
+X0116278Y0030345D01*
+X0116165Y0030326D01*
+X0116053Y0030303D01*
+X0115941Y0030278D01*
+X0115830Y0030248D01*
+X0115720Y0030216D01*
+X0115611Y0030180D01*
+X0115503Y0030141D01*
+X0115397Y0030099D01*
+X0115292Y0030053D01*
+X0115188Y0030005D01*
+X0115188Y0028215D02*
+X0115292Y0028167D01*
+X0115397Y0028121D01*
+X0115503Y0028079D01*
+X0115611Y0028040D01*
+X0115720Y0028004D01*
+X0115830Y0027972D01*
+X0115941Y0027942D01*
+X0116053Y0027917D01*
+X0116165Y0027894D01*
+X0116278Y0027875D01*
+X0116392Y0027860D01*
+X0116506Y0027848D01*
+X0116620Y0027839D01*
+X0116734Y0027834D01*
+X0116849Y0027832D01*
+X0114549Y0025888D02*
+X0114549Y0023333D01*
+X0114549Y0024610D02*
+X0119149Y0024610D01*
+X0118127Y0023333D01*
+X0119149Y0021614D02*
+X0119149Y0020592D01*
+X0119147Y0020530D01*
+X0119142Y0020469D01*
+X0119132Y0020408D01*
+X0119119Y0020347D01*
+X0119103Y0020288D01*
+X0119083Y0020230D01*
+X0119059Y0020173D01*
+X0119032Y0020117D01*
+X0119002Y0020063D01*
+X0118968Y0020011D01*
+X0118931Y0019962D01*
+X0118892Y0019914D01*
+X0118850Y0019869D01*
+X0118805Y0019827D01*
+X0118757Y0019787D01*
+X0118708Y0019751D01*
+X0118656Y0019717D01*
+X0118602Y0019687D01*
+X0118546Y0019660D01*
+X0118489Y0019636D01*
+X0118431Y0019616D01*
+X0118372Y0019600D01*
+X0118311Y0019587D01*
+X0118250Y0019577D01*
+X0118189Y0019572D01*
+X0118127Y0019570D01*
+X0115571Y0019570D01*
+X0115509Y0019572D01*
+X0115448Y0019577D01*
+X0115387Y0019587D01*
+X0115326Y0019600D01*
+X0115267Y0019616D01*
+X0115209Y0019636D01*
+X0115152Y0019660D01*
+X0115096Y0019687D01*
+X0115042Y0019717D01*
+X0114990Y0019751D01*
+X0114941Y0019787D01*
+X0114893Y0019827D01*
+X0114848Y0019869D01*
+X0114806Y0019914D01*
+X0114766Y0019962D01*
+X0114730Y0020011D01*
+X0114696Y0020063D01*
+X0114666Y0020117D01*
+X0114639Y0020173D01*
+X0114615Y0020230D01*
+X0114595Y0020288D01*
+X0114579Y0020347D01*
+X0114566Y0020408D01*
+X0114556Y0020469D01*
+X0114551Y0020530D01*
+X0114549Y0020592D01*
+X0114549Y0021614D01*
+X0239500Y0025320D02*
+X0244100Y0025320D01*
+X0244100Y0026598D01*
+X0244098Y0026668D01*
+X0244092Y0026739D01*
+X0244083Y0026808D01*
+X0244069Y0026877D01*
+X0244052Y0026946D01*
+X0244031Y0027013D01*
+X0244006Y0027079D01*
+X0243978Y0027143D01*
+X0243946Y0027206D01*
+X0243911Y0027267D01*
+X0243872Y0027326D01*
+X0243831Y0027383D01*
+X0243786Y0027437D01*
+X0243738Y0027489D01*
+X0243688Y0027538D01*
+X0243634Y0027585D01*
+X0243579Y0027628D01*
+X0243521Y0027668D01*
+X0243461Y0027705D01*
+X0243399Y0027738D01*
+X0243335Y0027768D01*
+X0243270Y0027795D01*
+X0243204Y0027818D01*
+X0243136Y0027837D01*
+X0243067Y0027852D01*
+X0242998Y0027864D01*
+X0242928Y0027872D01*
+X0242857Y0027876D01*
+X0242787Y0027876D01*
+X0242716Y0027872D01*
+X0242646Y0027864D01*
+X0242577Y0027852D01*
+X0242508Y0027837D01*
+X0242440Y0027818D01*
+X0242374Y0027795D01*
+X0242309Y0027768D01*
+X0242245Y0027738D01*
+X0242183Y0027705D01*
+X0242123Y0027668D01*
+X0242065Y0027628D01*
+X0242010Y0027585D01*
+X0241956Y0027538D01*
+X0241906Y0027489D01*
+X0241858Y0027437D01*
+X0241813Y0027383D01*
+X0241772Y0027326D01*
+X0241733Y0027267D01*
+X0241698Y0027206D01*
+X0241666Y0027143D01*
+X0241638Y0027079D01*
+X0241613Y0027013D01*
+X0241592Y0026946D01*
+X0241575Y0026877D01*
+X0241561Y0026808D01*
+X0241552Y0026739D01*
+X0241546Y0026668D01*
+X0241544Y0026598D01*
+X0241544Y0025320D01*
+X0241544Y0026853D02*
+X0239500Y0027876D01*
+X0239500Y0029791D02*
+X0239500Y0032347D01*
+X0239500Y0031069D02*
+X0244100Y0031069D01*
+X0243078Y0029791D01*
+X0239500Y0034291D02*
+X0239500Y0036847D01*
+X0239500Y0034291D02*
+X0242056Y0036463D01*
+X0244100Y0035697D02*
+X0244098Y0035623D01*
+X0244093Y0035549D01*
+X0244083Y0035475D01*
+X0244070Y0035402D01*
+X0244054Y0035329D01*
+X0244033Y0035258D01*
+X0244009Y0035188D01*
+X0243982Y0035119D01*
+X0243951Y0035051D01*
+X0243917Y0034985D01*
+X0243880Y0034921D01*
+X0243839Y0034859D01*
+X0243795Y0034799D01*
+X0243749Y0034741D01*
+X0243699Y0034685D01*
+X0243647Y0034632D01*
+X0243592Y0034582D01*
+X0243535Y0034535D01*
+X0243475Y0034491D01*
+X0243413Y0034449D01*
+X0243350Y0034411D01*
+X0243284Y0034376D01*
+X0243217Y0034345D01*
+X0243148Y0034317D01*
+X0243078Y0034292D01*
+X0242056Y0036463D02*
+X0242103Y0036510D01*
+X0242153Y0036554D01*
+X0242205Y0036596D01*
+X0242259Y0036635D01*
+X0242315Y0036670D01*
+X0242373Y0036703D01*
+X0242433Y0036733D01*
+X0242494Y0036759D01*
+X0242557Y0036782D01*
+X0242621Y0036801D01*
+X0242685Y0036817D01*
+X0242751Y0036830D01*
+X0242817Y0036839D01*
+X0242883Y0036844D01*
+X0242950Y0036846D01*
+X0242950Y0036847D02*
+X0243017Y0036845D01*
+X0243084Y0036839D01*
+X0243150Y0036830D01*
+X0243215Y0036816D01*
+X0243280Y0036799D01*
+X0243343Y0036778D01*
+X0243405Y0036753D01*
+X0243466Y0036725D01*
+X0243525Y0036693D01*
+X0243582Y0036658D01*
+X0243637Y0036619D01*
+X0243689Y0036578D01*
+X0243739Y0036533D01*
+X0243786Y0036486D01*
+X0243831Y0036436D01*
+X0243872Y0036384D01*
+X0243911Y0036329D01*
+X0243946Y0036272D01*
+X0243978Y0036213D01*
+X0244006Y0036152D01*
+X0244031Y0036090D01*
+X0244052Y0036027D01*
+X0244069Y0035962D01*
+X0244083Y0035897D01*
+X0244092Y0035831D01*
+X0244098Y0035764D01*
+X0244100Y0035697D01*
+X0277000Y0035570D02*
+X0281600Y0035570D01*
+X0281600Y0036848D01*
+X0281598Y0036918D01*
+X0281592Y0036989D01*
+X0281583Y0037058D01*
+X0281569Y0037127D01*
+X0281552Y0037196D01*
+X0281531Y0037263D01*
+X0281506Y0037329D01*
+X0281478Y0037393D01*
+X0281446Y0037456D01*
+X0281411Y0037517D01*
+X0281372Y0037576D01*
+X0281331Y0037633D01*
+X0281286Y0037687D01*
+X0281238Y0037739D01*
+X0281188Y0037788D01*
+X0281134Y0037835D01*
+X0281079Y0037878D01*
+X0281021Y0037918D01*
+X0280961Y0037955D01*
+X0280899Y0037988D01*
+X0280835Y0038018D01*
+X0280770Y0038045D01*
+X0280704Y0038068D01*
+X0280636Y0038087D01*
+X0280567Y0038102D01*
+X0280498Y0038114D01*
+X0280428Y0038122D01*
+X0280357Y0038126D01*
+X0280287Y0038126D01*
+X0280216Y0038122D01*
+X0280146Y0038114D01*
+X0280077Y0038102D01*
+X0280008Y0038087D01*
+X0279940Y0038068D01*
+X0279874Y0038045D01*
+X0279809Y0038018D01*
+X0279745Y0037988D01*
+X0279683Y0037955D01*
+X0279623Y0037918D01*
+X0279565Y0037878D01*
+X0279510Y0037835D01*
+X0279456Y0037788D01*
+X0279406Y0037739D01*
+X0279358Y0037687D01*
+X0279313Y0037633D01*
+X0279272Y0037576D01*
+X0279233Y0037517D01*
+X0279198Y0037456D01*
+X0279166Y0037393D01*
+X0279138Y0037329D01*
+X0279113Y0037263D01*
+X0279092Y0037196D01*
+X0279075Y0037127D01*
+X0279061Y0037058D01*
+X0279052Y0036989D01*
+X0279046Y0036918D01*
+X0279044Y0036848D01*
+X0279044Y0035570D01*
+X0279044Y0037103D02*
+X0277000Y0038126D01*
+X0277000Y0040041D02*
+X0277000Y0042597D01*
+X0277000Y0041319D02*
+X0281600Y0041319D01*
+X0280578Y0040041D01*
+X0279300Y0047097D02*
+X0279185Y0047095D01*
+X0279071Y0047090D01*
+X0278957Y0047081D01*
+X0278843Y0047069D01*
+X0278729Y0047054D01*
+X0278616Y0047035D01*
+X0278504Y0047012D01*
+X0278392Y0046987D01*
+X0278281Y0046957D01*
+X0278171Y0046925D01*
+X0278062Y0046889D01*
+X0277954Y0046850D01*
+X0277848Y0046808D01*
+X0277743Y0046762D01*
+X0277639Y0046714D01*
+X0277584Y0046693D01*
+X0277531Y0046669D01*
+X0277479Y0046642D01*
+X0277429Y0046611D01*
+X0277381Y0046578D01*
+X0277335Y0046541D01*
+X0277291Y0046502D01*
+X0277250Y0046460D01*
+X0277212Y0046416D01*
+X0277176Y0046369D01*
+X0277144Y0046320D01*
+X0277114Y0046269D01*
+X0277088Y0046217D01*
+X0277065Y0046163D01*
+X0277045Y0046108D01*
+X0277029Y0046051D01*
+X0277016Y0045994D01*
+X0277007Y0045936D01*
+X0277002Y0045878D01*
+X0277000Y0045819D01*
+X0277002Y0045760D01*
+X0277007Y0045702D01*
+X0277016Y0045644D01*
+X0277029Y0045587D01*
+X0277045Y0045530D01*
+X0277065Y0045475D01*
+X0277088Y0045421D01*
+X0277114Y0045369D01*
+X0277144Y0045318D01*
+X0277176Y0045269D01*
+X0277212Y0045222D01*
+X0277250Y0045178D01*
+X0277291Y0045136D01*
+X0277335Y0045097D01*
+X0277381Y0045060D01*
+X0277429Y0045027D01*
+X0277479Y0044996D01*
+X0277531Y0044969D01*
+X0277584Y0044945D01*
+X0277639Y0044924D01*
+X0278022Y0044797D02*
+X0280578Y0046841D01*
+X0280961Y0046714D02*
+X0281016Y0046693D01*
+X0281069Y0046669D01*
+X0281121Y0046642D01*
+X0281171Y0046611D01*
+X0281219Y0046578D01*
+X0281265Y0046541D01*
+X0281309Y0046502D01*
+X0281350Y0046460D01*
+X0281388Y0046416D01*
+X0281424Y0046369D01*
+X0281456Y0046320D01*
+X0281486Y0046269D01*
+X0281512Y0046217D01*
+X0281535Y0046163D01*
+X0281555Y0046108D01*
+X0281571Y0046051D01*
+X0281584Y0045994D01*
+X0281593Y0045936D01*
+X0281598Y0045878D01*
+X0281600Y0045819D01*
+X0281598Y0045760D01*
+X0281593Y0045702D01*
+X0281584Y0045644D01*
+X0281571Y0045587D01*
+X0281555Y0045530D01*
+X0281535Y0045475D01*
+X0281512Y0045421D01*
+X0281486Y0045369D01*
+X0281456Y0045318D01*
+X0281424Y0045269D01*
+X0281388Y0045222D01*
+X0281350Y0045178D01*
+X0281309Y0045136D01*
+X0281265Y0045097D01*
+X0281219Y0045060D01*
+X0281171Y0045027D01*
+X0281121Y0044996D01*
+X0281069Y0044969D01*
+X0281016Y0044945D01*
+X0280961Y0044924D01*
+X0280961Y0046714D02*
+X0280857Y0046762D01*
+X0280752Y0046808D01*
+X0280646Y0046850D01*
+X0280538Y0046889D01*
+X0280429Y0046925D01*
+X0280319Y0046957D01*
+X0280208Y0046987D01*
+X0280096Y0047012D01*
+X0279984Y0047035D01*
+X0279871Y0047054D01*
+X0279757Y0047069D01*
+X0279643Y0047081D01*
+X0279529Y0047090D01*
+X0279415Y0047095D01*
+X0279300Y0047097D01*
+X0279300Y0044541D02*
+X0279415Y0044543D01*
+X0279529Y0044548D01*
+X0279643Y0044557D01*
+X0279757Y0044569D01*
+X0279871Y0044584D01*
+X0279984Y0044603D01*
+X0280096Y0044626D01*
+X0280208Y0044651D01*
+X0280319Y0044681D01*
+X0280429Y0044713D01*
+X0280538Y0044749D01*
+X0280646Y0044788D01*
+X0280752Y0044830D01*
+X0280857Y0044876D01*
+X0280961Y0044924D01*
+X0279300Y0044541D02*
+X0279185Y0044543D01*
+X0279071Y0044548D01*
+X0278957Y0044557D01*
+X0278843Y0044569D01*
+X0278729Y0044584D01*
+X0278616Y0044603D01*
+X0278504Y0044626D01*
+X0278392Y0044651D01*
+X0278281Y0044681D01*
+X0278171Y0044713D01*
+X0278062Y0044749D01*
+X0277954Y0044788D01*
+X0277848Y0044830D01*
+X0277743Y0044876D01*
+X0277639Y0044924D01*
+X0279044Y0025597D02*
+X0281600Y0025597D01*
+X0280322Y0025597D02*
+X0280322Y0020997D01*
+X0277400Y0020997D02*
+X0274844Y0020997D01*
+X0276122Y0020997D02*
+X0276122Y0025597D01*
+X0277400Y0024574D01*
+X0303323Y0025291D02*
+X0303323Y0026569D01*
+X0303323Y0025291D02*
+X0304857Y0025291D01*
+X0303324Y0025291D02*
+X0303326Y0025202D01*
+X0303332Y0025113D01*
+X0303341Y0025024D01*
+X0303355Y0024936D01*
+X0303372Y0024849D01*
+X0303394Y0024762D01*
+X0303419Y0024676D01*
+X0303447Y0024592D01*
+X0303480Y0024509D01*
+X0303516Y0024427D01*
+X0303555Y0024347D01*
+X0303598Y0024269D01*
+X0303644Y0024193D01*
+X0303694Y0024119D01*
+X0303746Y0024047D01*
+X0303802Y0023977D01*
+X0303861Y0023910D01*
+X0303923Y0023846D01*
+X0303987Y0023784D01*
+X0304054Y0023725D01*
+X0304124Y0023669D01*
+X0304196Y0023617D01*
+X0304270Y0023567D01*
+X0304346Y0023521D01*
+X0304424Y0023478D01*
+X0304504Y0023439D01*
+X0304586Y0023403D01*
+X0304669Y0023370D01*
+X0304753Y0023342D01*
+X0304839Y0023317D01*
+X0304926Y0023295D01*
+X0305013Y0023278D01*
+X0305101Y0023264D01*
+X0305190Y0023255D01*
+X0305279Y0023249D01*
+X0305368Y0023247D01*
+X0307794Y0023247D02*
+X0308817Y0025291D01*
+X0309072Y0025291D02*
+X0310350Y0025291D01*
+X0309072Y0025291D02*
+X0309002Y0025293D01*
+X0308931Y0025299D01*
+X0308862Y0025308D01*
+X0308793Y0025322D01*
+X0308724Y0025339D01*
+X0308657Y0025360D01*
+X0308591Y0025385D01*
+X0308527Y0025413D01*
+X0308464Y0025445D01*
+X0308403Y0025480D01*
+X0308344Y0025519D01*
+X0308287Y0025560D01*
+X0308233Y0025605D01*
+X0308181Y0025653D01*
+X0308132Y0025703D01*
+X0308085Y0025757D01*
+X0308042Y0025812D01*
+X0308002Y0025870D01*
+X0307965Y0025930D01*
+X0307932Y0025992D01*
+X0307902Y0026056D01*
+X0307875Y0026121D01*
+X0307852Y0026187D01*
+X0307833Y0026255D01*
+X0307818Y0026324D01*
+X0307806Y0026393D01*
+X0307798Y0026463D01*
+X0307794Y0026534D01*
+X0307794Y0026604D01*
+X0307798Y0026675D01*
+X0307806Y0026745D01*
+X0307818Y0026814D01*
+X0307833Y0026883D01*
+X0307852Y0026951D01*
+X0307875Y0027017D01*
+X0307902Y0027082D01*
+X0307932Y0027146D01*
+X0307965Y0027208D01*
+X0308002Y0027268D01*
+X0308042Y0027326D01*
+X0308085Y0027381D01*
+X0308132Y0027435D01*
+X0308181Y0027485D01*
+X0308233Y0027533D01*
+X0308287Y0027578D01*
+X0308344Y0027619D01*
+X0308403Y0027658D01*
+X0308464Y0027693D01*
+X0308527Y0027725D01*
+X0308591Y0027753D01*
+X0308657Y0027778D01*
+X0308724Y0027799D01*
+X0308793Y0027816D01*
+X0308862Y0027830D01*
+X0308931Y0027839D01*
+X0309002Y0027845D01*
+X0309072Y0027847D01*
+X0310350Y0027847D01*
+X0310350Y0023247D01*
+X0305879Y0026313D02*
+X0305879Y0026569D01*
+X0305879Y0026313D02*
+X0305877Y0026251D01*
+X0305872Y0026190D01*
+X0305862Y0026129D01*
+X0305849Y0026068D01*
+X0305833Y0026009D01*
+X0305813Y0025951D01*
+X0305789Y0025894D01*
+X0305762Y0025838D01*
+X0305732Y0025784D01*
+X0305698Y0025732D01*
+X0305662Y0025683D01*
+X0305622Y0025635D01*
+X0305580Y0025590D01*
+X0305535Y0025548D01*
+X0305487Y0025508D01*
+X0305438Y0025472D01*
+X0305386Y0025438D01*
+X0305332Y0025408D01*
+X0305276Y0025381D01*
+X0305219Y0025357D01*
+X0305161Y0025337D01*
+X0305102Y0025321D01*
+X0305041Y0025308D01*
+X0304980Y0025298D01*
+X0304919Y0025293D01*
+X0304857Y0025291D01*
+X0305879Y0026569D02*
+X0305877Y0026639D01*
+X0305871Y0026710D01*
+X0305862Y0026779D01*
+X0305848Y0026848D01*
+X0305831Y0026917D01*
+X0305810Y0026984D01*
+X0305785Y0027050D01*
+X0305757Y0027114D01*
+X0305725Y0027177D01*
+X0305690Y0027238D01*
+X0305651Y0027297D01*
+X0305610Y0027354D01*
+X0305565Y0027408D01*
+X0305517Y0027460D01*
+X0305467Y0027509D01*
+X0305413Y0027556D01*
+X0305358Y0027599D01*
+X0305300Y0027639D01*
+X0305240Y0027676D01*
+X0305178Y0027709D01*
+X0305114Y0027739D01*
+X0305049Y0027766D01*
+X0304983Y0027789D01*
+X0304915Y0027808D01*
+X0304846Y0027823D01*
+X0304777Y0027835D01*
+X0304707Y0027843D01*
+X0304636Y0027847D01*
+X0304566Y0027847D01*
+X0304495Y0027843D01*
+X0304425Y0027835D01*
+X0304356Y0027823D01*
+X0304287Y0027808D01*
+X0304219Y0027789D01*
+X0304153Y0027766D01*
+X0304088Y0027739D01*
+X0304024Y0027709D01*
+X0303962Y0027676D01*
+X0303902Y0027639D01*
+X0303844Y0027599D01*
+X0303789Y0027556D01*
+X0303735Y0027509D01*
+X0303685Y0027460D01*
+X0303637Y0027408D01*
+X0303592Y0027354D01*
+X0303551Y0027297D01*
+X0303512Y0027238D01*
+X0303477Y0027177D01*
+X0303445Y0027114D01*
+X0303417Y0027050D01*
+X0303392Y0026984D01*
+X0303371Y0026917D01*
+X0303354Y0026848D01*
+X0303340Y0026779D01*
+X0303331Y0026710D01*
+X0303325Y0026639D01*
+X0303323Y0026569D01*
+X0299100Y0065997D02*
+X0299100Y0070597D01*
+X0297822Y0070597D01*
+X0297752Y0070595D01*
+X0297681Y0070589D01*
+X0297612Y0070580D01*
+X0297543Y0070566D01*
+X0297474Y0070549D01*
+X0297407Y0070528D01*
+X0297341Y0070503D01*
+X0297277Y0070475D01*
+X0297214Y0070443D01*
+X0297153Y0070408D01*
+X0297094Y0070369D01*
+X0297037Y0070328D01*
+X0296983Y0070283D01*
+X0296931Y0070235D01*
+X0296882Y0070185D01*
+X0296835Y0070131D01*
+X0296792Y0070076D01*
+X0296752Y0070018D01*
+X0296715Y0069958D01*
+X0296682Y0069896D01*
+X0296652Y0069832D01*
+X0296625Y0069767D01*
+X0296602Y0069701D01*
+X0296583Y0069633D01*
+X0296568Y0069564D01*
+X0296556Y0069495D01*
+X0296548Y0069425D01*
+X0296544Y0069354D01*
+X0296544Y0069284D01*
+X0296548Y0069213D01*
+X0296556Y0069143D01*
+X0296568Y0069074D01*
+X0296583Y0069005D01*
+X0296602Y0068937D01*
+X0296625Y0068871D01*
+X0296652Y0068806D01*
+X0296682Y0068742D01*
+X0296715Y0068680D01*
+X0296752Y0068620D01*
+X0296792Y0068562D01*
+X0296835Y0068507D01*
+X0296882Y0068453D01*
+X0296931Y0068403D01*
+X0296983Y0068355D01*
+X0297037Y0068310D01*
+X0297094Y0068269D01*
+X0297153Y0068230D01*
+X0297214Y0068195D01*
+X0297277Y0068163D01*
+X0297341Y0068135D01*
+X0297407Y0068110D01*
+X0297474Y0068089D01*
+X0297543Y0068072D01*
+X0297612Y0068058D01*
+X0297681Y0068049D01*
+X0297752Y0068043D01*
+X0297822Y0068041D01*
+X0299100Y0068041D01*
+X0297567Y0068041D02*
+X0296544Y0065997D01*
+X0294629Y0065997D02*
+X0292073Y0065997D01*
+X0293351Y0065997D02*
+X0293351Y0070597D01*
+X0294629Y0069574D01*
+X0290129Y0069574D02*
+X0288851Y0070597D01*
+X0288851Y0065997D01*
+X0290129Y0065997D02*
+X0287573Y0065997D01*
+X0314500Y0068774D02*
+X0314502Y0068704D01*
+X0314508Y0068633D01*
+X0314517Y0068564D01*
+X0314531Y0068495D01*
+X0314548Y0068426D01*
+X0314569Y0068359D01*
+X0314594Y0068293D01*
+X0314622Y0068229D01*
+X0314654Y0068166D01*
+X0314689Y0068105D01*
+X0314728Y0068046D01*
+X0314769Y0067989D01*
+X0314814Y0067935D01*
+X0314862Y0067883D01*
+X0314912Y0067834D01*
+X0314966Y0067787D01*
+X0315021Y0067744D01*
+X0315079Y0067704D01*
+X0315139Y0067667D01*
+X0315201Y0067634D01*
+X0315265Y0067604D01*
+X0315330Y0067577D01*
+X0315396Y0067554D01*
+X0315464Y0067535D01*
+X0315533Y0067520D01*
+X0315602Y0067508D01*
+X0315672Y0067500D01*
+X0315743Y0067496D01*
+X0315813Y0067496D01*
+X0315884Y0067500D01*
+X0315954Y0067508D01*
+X0316023Y0067520D01*
+X0316092Y0067535D01*
+X0316160Y0067554D01*
+X0316226Y0067577D01*
+X0316291Y0067604D01*
+X0316355Y0067634D01*
+X0316417Y0067667D01*
+X0316477Y0067704D01*
+X0316535Y0067744D01*
+X0316590Y0067787D01*
+X0316644Y0067834D01*
+X0316694Y0067883D01*
+X0316742Y0067935D01*
+X0316787Y0067989D01*
+X0316828Y0068046D01*
+X0316867Y0068105D01*
+X0316902Y0068166D01*
+X0316934Y0068229D01*
+X0316962Y0068293D01*
+X0316987Y0068359D01*
+X0317008Y0068426D01*
+X0317025Y0068495D01*
+X0317039Y0068564D01*
+X0317048Y0068633D01*
+X0317054Y0068704D01*
+X0317056Y0068774D01*
+X0317054Y0068844D01*
+X0317048Y0068915D01*
+X0317039Y0068984D01*
+X0317025Y0069053D01*
+X0317008Y0069122D01*
+X0316987Y0069189D01*
+X0316962Y0069255D01*
+X0316934Y0069319D01*
+X0316902Y0069382D01*
+X0316867Y0069443D01*
+X0316828Y0069502D01*
+X0316787Y0069559D01*
+X0316742Y0069613D01*
+X0316694Y0069665D01*
+X0316644Y0069714D01*
+X0316590Y0069761D01*
+X0316535Y0069804D01*
+X0316477Y0069844D01*
+X0316417Y0069881D01*
+X0316355Y0069914D01*
+X0316291Y0069944D01*
+X0316226Y0069971D01*
+X0316160Y0069994D01*
+X0316092Y0070013D01*
+X0316023Y0070028D01*
+X0315954Y0070040D01*
+X0315884Y0070048D01*
+X0315813Y0070052D01*
+X0315743Y0070052D01*
+X0315672Y0070048D01*
+X0315602Y0070040D01*
+X0315533Y0070028D01*
+X0315464Y0070013D01*
+X0315396Y0069994D01*
+X0315330Y0069971D01*
+X0315265Y0069944D01*
+X0315201Y0069914D01*
+X0315139Y0069881D01*
+X0315079Y0069844D01*
+X0315021Y0069804D01*
+X0314966Y0069761D01*
+X0314912Y0069714D01*
+X0314862Y0069665D01*
+X0314814Y0069613D01*
+X0314769Y0069559D01*
+X0314728Y0069502D01*
+X0314689Y0069443D01*
+X0314654Y0069382D01*
+X0314622Y0069319D01*
+X0314594Y0069255D01*
+X0314569Y0069189D01*
+X0314548Y0069122D01*
+X0314531Y0069053D01*
+X0314517Y0068984D01*
+X0314508Y0068915D01*
+X0314502Y0068844D01*
+X0314500Y0068774D01*
+X0314756Y0071074D02*
+X0314758Y0071011D01*
+X0314764Y0070948D01*
+X0314773Y0070886D01*
+X0314787Y0070825D01*
+X0314804Y0070764D01*
+X0314825Y0070705D01*
+X0314850Y0070647D01*
+X0314878Y0070590D01*
+X0314909Y0070536D01*
+X0314944Y0070484D01*
+X0314982Y0070433D01*
+X0315023Y0070385D01*
+X0315067Y0070340D01*
+X0315113Y0070298D01*
+X0315162Y0070258D01*
+X0315213Y0070222D01*
+X0315267Y0070189D01*
+X0315322Y0070159D01*
+X0315380Y0070133D01*
+X0315438Y0070110D01*
+X0315498Y0070091D01*
+X0315559Y0070076D01*
+X0315621Y0070064D01*
+X0315684Y0070056D01*
+X0315747Y0070052D01*
+X0315809Y0070052D01*
+X0315872Y0070056D01*
+X0315935Y0070064D01*
+X0315997Y0070076D01*
+X0316058Y0070091D01*
+X0316118Y0070110D01*
+X0316176Y0070133D01*
+X0316234Y0070159D01*
+X0316289Y0070189D01*
+X0316343Y0070222D01*
+X0316394Y0070258D01*
+X0316443Y0070298D01*
+X0316489Y0070340D01*
+X0316533Y0070385D01*
+X0316574Y0070433D01*
+X0316612Y0070484D01*
+X0316647Y0070536D01*
+X0316678Y0070590D01*
+X0316706Y0070647D01*
+X0316731Y0070705D01*
+X0316752Y0070764D01*
+X0316769Y0070825D01*
+X0316783Y0070886D01*
+X0316792Y0070948D01*
+X0316798Y0071011D01*
+X0316800Y0071074D01*
+X0316798Y0071137D01*
+X0316792Y0071200D01*
+X0316783Y0071262D01*
+X0316769Y0071323D01*
+X0316752Y0071384D01*
+X0316731Y0071443D01*
+X0316706Y0071501D01*
+X0316678Y0071558D01*
+X0316647Y0071612D01*
+X0316612Y0071664D01*
+X0316574Y0071715D01*
+X0316533Y0071763D01*
+X0316489Y0071808D01*
+X0316443Y0071850D01*
+X0316394Y0071890D01*
+X0316343Y0071926D01*
+X0316289Y0071959D01*
+X0316234Y0071989D01*
+X0316176Y0072015D01*
+X0316118Y0072038D01*
+X0316058Y0072057D01*
+X0315997Y0072072D01*
+X0315935Y0072084D01*
+X0315872Y0072092D01*
+X0315809Y0072096D01*
+X0315747Y0072096D01*
+X0315684Y0072092D01*
+X0315621Y0072084D01*
+X0315559Y0072072D01*
+X0315498Y0072057D01*
+X0315438Y0072038D01*
+X0315380Y0072015D01*
+X0315322Y0071989D01*
+X0315267Y0071959D01*
+X0315213Y0071926D01*
+X0315162Y0071890D01*
+X0315113Y0071850D01*
+X0315067Y0071808D01*
+X0315023Y0071763D01*
+X0314982Y0071715D01*
+X0314944Y0071664D01*
+X0314909Y0071612D01*
+X0314878Y0071558D01*
+X0314850Y0071501D01*
+X0314825Y0071443D01*
+X0314804Y0071384D01*
+X0314787Y0071323D01*
+X0314773Y0071262D01*
+X0314764Y0071200D01*
+X0314758Y0071137D01*
+X0314756Y0071074D01*
+X0319993Y0069541D02*
+X0318971Y0067497D01*
+X0320249Y0069541D02*
+X0321527Y0069541D01*
+X0320249Y0069541D02*
+X0320179Y0069543D01*
+X0320108Y0069549D01*
+X0320039Y0069558D01*
+X0319970Y0069572D01*
+X0319901Y0069589D01*
+X0319834Y0069610D01*
+X0319768Y0069635D01*
+X0319704Y0069663D01*
+X0319641Y0069695D01*
+X0319580Y0069730D01*
+X0319521Y0069769D01*
+X0319464Y0069810D01*
+X0319410Y0069855D01*
+X0319358Y0069903D01*
+X0319309Y0069953D01*
+X0319262Y0070007D01*
+X0319219Y0070062D01*
+X0319179Y0070120D01*
+X0319142Y0070180D01*
+X0319109Y0070242D01*
+X0319079Y0070306D01*
+X0319052Y0070371D01*
+X0319029Y0070437D01*
+X0319010Y0070505D01*
+X0318995Y0070574D01*
+X0318983Y0070643D01*
+X0318975Y0070713D01*
+X0318971Y0070784D01*
+X0318971Y0070854D01*
+X0318975Y0070925D01*
+X0318983Y0070995D01*
+X0318995Y0071064D01*
+X0319010Y0071133D01*
+X0319029Y0071201D01*
+X0319052Y0071267D01*
+X0319079Y0071332D01*
+X0319109Y0071396D01*
+X0319142Y0071458D01*
+X0319179Y0071518D01*
+X0319219Y0071576D01*
+X0319262Y0071631D01*
+X0319309Y0071685D01*
+X0319358Y0071735D01*
+X0319410Y0071783D01*
+X0319464Y0071828D01*
+X0319521Y0071869D01*
+X0319580Y0071908D01*
+X0319641Y0071943D01*
+X0319704Y0071975D01*
+X0319768Y0072003D01*
+X0319834Y0072028D01*
+X0319901Y0072049D01*
+X0319970Y0072066D01*
+X0320039Y0072080D01*
+X0320108Y0072089D01*
+X0320179Y0072095D01*
+X0320249Y0072097D01*
+X0321527Y0072097D01*
+X0321527Y0067497D01*
+X0352073Y0077247D02*
+X0354629Y0077247D01*
+X0352457Y0079802D01*
+X0353223Y0081846D02*
+X0353297Y0081844D01*
+X0353371Y0081839D01*
+X0353445Y0081829D01*
+X0353518Y0081816D01*
+X0353591Y0081800D01*
+X0353662Y0081779D01*
+X0353732Y0081755D01*
+X0353801Y0081728D01*
+X0353869Y0081697D01*
+X0353935Y0081663D01*
+X0353999Y0081626D01*
+X0354061Y0081585D01*
+X0354122Y0081541D01*
+X0354179Y0081495D01*
+X0354235Y0081445D01*
+X0354288Y0081393D01*
+X0354338Y0081338D01*
+X0354385Y0081281D01*
+X0354429Y0081221D01*
+X0354471Y0081159D01*
+X0354509Y0081096D01*
+X0354544Y0081030D01*
+X0354575Y0080963D01*
+X0354603Y0080894D01*
+X0354628Y0080824D01*
+X0352457Y0079803D02*
+X0352410Y0079850D01*
+X0352366Y0079900D01*
+X0352324Y0079952D01*
+X0352285Y0080006D01*
+X0352250Y0080062D01*
+X0352217Y0080120D01*
+X0352187Y0080180D01*
+X0352161Y0080241D01*
+X0352138Y0080304D01*
+X0352119Y0080368D01*
+X0352103Y0080432D01*
+X0352090Y0080498D01*
+X0352081Y0080564D01*
+X0352076Y0080630D01*
+X0352074Y0080697D01*
+X0352073Y0080697D02*
+X0352075Y0080764D01*
+X0352081Y0080831D01*
+X0352090Y0080897D01*
+X0352104Y0080962D01*
+X0352121Y0081027D01*
+X0352142Y0081090D01*
+X0352167Y0081152D01*
+X0352195Y0081213D01*
+X0352227Y0081272D01*
+X0352262Y0081329D01*
+X0352301Y0081384D01*
+X0352342Y0081436D01*
+X0352387Y0081486D01*
+X0352434Y0081533D01*
+X0352484Y0081578D01*
+X0352536Y0081619D01*
+X0352591Y0081658D01*
+X0352648Y0081693D01*
+X0352707Y0081725D01*
+X0352768Y0081753D01*
+X0352830Y0081778D01*
+X0352893Y0081799D01*
+X0352958Y0081816D01*
+X0353023Y0081830D01*
+X0353089Y0081839D01*
+X0353156Y0081845D01*
+X0353223Y0081847D01*
+X0357822Y0081847D02*
+X0359100Y0081847D01*
+X0359100Y0077247D01*
+X0359100Y0079291D02*
+X0357822Y0079291D01*
+X0357567Y0079291D02*
+X0356544Y0077247D01*
+X0357822Y0079291D02*
+X0357752Y0079293D01*
+X0357681Y0079299D01*
+X0357612Y0079308D01*
+X0357543Y0079322D01*
+X0357474Y0079339D01*
+X0357407Y0079360D01*
+X0357341Y0079385D01*
+X0357277Y0079413D01*
+X0357214Y0079445D01*
+X0357153Y0079480D01*
+X0357094Y0079519D01*
+X0357037Y0079560D01*
+X0356983Y0079605D01*
+X0356931Y0079653D01*
+X0356882Y0079703D01*
+X0356835Y0079757D01*
+X0356792Y0079812D01*
+X0356752Y0079870D01*
+X0356715Y0079930D01*
+X0356682Y0079992D01*
+X0356652Y0080056D01*
+X0356625Y0080121D01*
+X0356602Y0080187D01*
+X0356583Y0080255D01*
+X0356568Y0080324D01*
+X0356556Y0080393D01*
+X0356548Y0080463D01*
+X0356544Y0080534D01*
+X0356544Y0080604D01*
+X0356548Y0080675D01*
+X0356556Y0080745D01*
+X0356568Y0080814D01*
+X0356583Y0080883D01*
+X0356602Y0080951D01*
+X0356625Y0081017D01*
+X0356652Y0081082D01*
+X0356682Y0081146D01*
+X0356715Y0081208D01*
+X0356752Y0081268D01*
+X0356792Y0081326D01*
+X0356835Y0081381D01*
+X0356882Y0081435D01*
+X0356931Y0081485D01*
+X0356983Y0081533D01*
+X0357037Y0081578D01*
+X0357094Y0081619D01*
+X0357153Y0081658D01*
+X0357214Y0081693D01*
+X0357277Y0081725D01*
+X0357341Y0081753D01*
+X0357407Y0081778D01*
+X0357474Y0081799D01*
+X0357543Y0081816D01*
+X0357612Y0081830D01*
+X0357681Y0081839D01*
+X0357752Y0081845D01*
+X0357822Y0081847D01*
+X0259100Y0139747D02*
+X0259100Y0144347D01*
+X0257822Y0144347D01*
+X0257752Y0144345D01*
+X0257681Y0144339D01*
+X0257612Y0144330D01*
+X0257543Y0144316D01*
+X0257474Y0144299D01*
+X0257407Y0144278D01*
+X0257341Y0144253D01*
+X0257277Y0144225D01*
+X0257214Y0144193D01*
+X0257153Y0144158D01*
+X0257094Y0144119D01*
+X0257037Y0144078D01*
+X0256983Y0144033D01*
+X0256931Y0143985D01*
+X0256882Y0143935D01*
+X0256835Y0143881D01*
+X0256792Y0143826D01*
+X0256752Y0143768D01*
+X0256715Y0143708D01*
+X0256682Y0143646D01*
+X0256652Y0143582D01*
+X0256625Y0143517D01*
+X0256602Y0143451D01*
+X0256583Y0143383D01*
+X0256568Y0143314D01*
+X0256556Y0143245D01*
+X0256548Y0143175D01*
+X0256544Y0143104D01*
+X0256544Y0143034D01*
+X0256548Y0142963D01*
+X0256556Y0142893D01*
+X0256568Y0142824D01*
+X0256583Y0142755D01*
+X0256602Y0142687D01*
+X0256625Y0142621D01*
+X0256652Y0142556D01*
+X0256682Y0142492D01*
+X0256715Y0142430D01*
+X0256752Y0142370D01*
+X0256792Y0142312D01*
+X0256835Y0142257D01*
+X0256882Y0142203D01*
+X0256931Y0142153D01*
+X0256983Y0142105D01*
+X0257037Y0142060D01*
+X0257094Y0142019D01*
+X0257153Y0141980D01*
+X0257214Y0141945D01*
+X0257277Y0141913D01*
+X0257341Y0141885D01*
+X0257407Y0141860D01*
+X0257474Y0141839D01*
+X0257543Y0141822D01*
+X0257612Y0141808D01*
+X0257681Y0141799D01*
+X0257752Y0141793D01*
+X0257822Y0141791D01*
+X0259100Y0141791D01*
+X0257567Y0141791D02*
+X0256544Y0139747D01*
+X0253351Y0139747D02*
+X0252073Y0144347D01*
+X0254629Y0144347D01*
+X0254629Y0143836D01*
+X0244027Y0143041D02*
+X0242749Y0143041D01*
+X0242493Y0143041D02*
+X0241471Y0140997D01*
+X0239556Y0142274D02*
+X0239556Y0143552D01*
+X0238022Y0143552D01*
+X0239555Y0143552D02*
+X0239553Y0143641D01*
+X0239547Y0143730D01*
+X0239538Y0143819D01*
+X0239524Y0143907D01*
+X0239507Y0143994D01*
+X0239485Y0144081D01*
+X0239460Y0144167D01*
+X0239432Y0144251D01*
+X0239399Y0144334D01*
+X0239363Y0144416D01*
+X0239324Y0144496D01*
+X0239281Y0144574D01*
+X0239235Y0144650D01*
+X0239185Y0144724D01*
+X0239133Y0144796D01*
+X0239077Y0144866D01*
+X0239018Y0144933D01*
+X0238956Y0144997D01*
+X0238892Y0145059D01*
+X0238825Y0145118D01*
+X0238755Y0145174D01*
+X0238683Y0145226D01*
+X0238609Y0145276D01*
+X0238533Y0145322D01*
+X0238455Y0145365D01*
+X0238375Y0145404D01*
+X0238293Y0145440D01*
+X0238210Y0145473D01*
+X0238126Y0145501D01*
+X0238040Y0145526D01*
+X0237953Y0145548D01*
+X0237866Y0145565D01*
+X0237778Y0145579D01*
+X0237689Y0145588D01*
+X0237600Y0145594D01*
+X0237511Y0145596D01*
+X0237000Y0142530D02*
+X0237000Y0142274D01*
+X0237000Y0142530D02*
+X0237002Y0142592D01*
+X0237007Y0142653D01*
+X0237017Y0142714D01*
+X0237030Y0142775D01*
+X0237046Y0142834D01*
+X0237066Y0142892D01*
+X0237090Y0142949D01*
+X0237117Y0143005D01*
+X0237147Y0143059D01*
+X0237181Y0143111D01*
+X0237217Y0143160D01*
+X0237257Y0143208D01*
+X0237299Y0143253D01*
+X0237344Y0143295D01*
+X0237392Y0143335D01*
+X0237441Y0143371D01*
+X0237493Y0143405D01*
+X0237547Y0143435D01*
+X0237603Y0143462D01*
+X0237660Y0143486D01*
+X0237718Y0143506D01*
+X0237777Y0143522D01*
+X0237838Y0143535D01*
+X0237899Y0143545D01*
+X0237960Y0143550D01*
+X0238022Y0143552D01*
+X0237000Y0142274D02*
+X0237002Y0142204D01*
+X0237008Y0142133D01*
+X0237017Y0142064D01*
+X0237031Y0141995D01*
+X0237048Y0141926D01*
+X0237069Y0141859D01*
+X0237094Y0141793D01*
+X0237122Y0141729D01*
+X0237154Y0141666D01*
+X0237189Y0141605D01*
+X0237228Y0141546D01*
+X0237269Y0141489D01*
+X0237314Y0141435D01*
+X0237362Y0141383D01*
+X0237412Y0141334D01*
+X0237466Y0141287D01*
+X0237521Y0141244D01*
+X0237579Y0141204D01*
+X0237639Y0141167D01*
+X0237701Y0141134D01*
+X0237765Y0141104D01*
+X0237830Y0141077D01*
+X0237896Y0141054D01*
+X0237964Y0141035D01*
+X0238033Y0141020D01*
+X0238102Y0141008D01*
+X0238172Y0141000D01*
+X0238243Y0140996D01*
+X0238313Y0140996D01*
+X0238384Y0141000D01*
+X0238454Y0141008D01*
+X0238523Y0141020D01*
+X0238592Y0141035D01*
+X0238660Y0141054D01*
+X0238726Y0141077D01*
+X0238791Y0141104D01*
+X0238855Y0141134D01*
+X0238917Y0141167D01*
+X0238977Y0141204D01*
+X0239035Y0141244D01*
+X0239090Y0141287D01*
+X0239144Y0141334D01*
+X0239194Y0141383D01*
+X0239242Y0141435D01*
+X0239287Y0141489D01*
+X0239328Y0141546D01*
+X0239367Y0141605D01*
+X0239402Y0141666D01*
+X0239434Y0141729D01*
+X0239462Y0141793D01*
+X0239487Y0141859D01*
+X0239508Y0141926D01*
+X0239525Y0141995D01*
+X0239539Y0142064D01*
+X0239548Y0142133D01*
+X0239554Y0142204D01*
+X0239556Y0142274D01*
+X0242749Y0143041D02*
+X0242679Y0143043D01*
+X0242608Y0143049D01*
+X0242539Y0143058D01*
+X0242470Y0143072D01*
+X0242401Y0143089D01*
+X0242334Y0143110D01*
+X0242268Y0143135D01*
+X0242204Y0143163D01*
+X0242141Y0143195D01*
+X0242080Y0143230D01*
+X0242021Y0143269D01*
+X0241964Y0143310D01*
+X0241910Y0143355D01*
+X0241858Y0143403D01*
+X0241809Y0143453D01*
+X0241762Y0143507D01*
+X0241719Y0143562D01*
+X0241679Y0143620D01*
+X0241642Y0143680D01*
+X0241609Y0143742D01*
+X0241579Y0143806D01*
+X0241552Y0143871D01*
+X0241529Y0143937D01*
+X0241510Y0144005D01*
+X0241495Y0144074D01*
+X0241483Y0144143D01*
+X0241475Y0144213D01*
+X0241471Y0144284D01*
+X0241471Y0144354D01*
+X0241475Y0144425D01*
+X0241483Y0144495D01*
+X0241495Y0144564D01*
+X0241510Y0144633D01*
+X0241529Y0144701D01*
+X0241552Y0144767D01*
+X0241579Y0144832D01*
+X0241609Y0144896D01*
+X0241642Y0144958D01*
+X0241679Y0145018D01*
+X0241719Y0145076D01*
+X0241762Y0145131D01*
+X0241809Y0145185D01*
+X0241858Y0145235D01*
+X0241910Y0145283D01*
+X0241964Y0145328D01*
+X0242021Y0145369D01*
+X0242080Y0145408D01*
+X0242141Y0145443D01*
+X0242204Y0145475D01*
+X0242268Y0145503D01*
+X0242334Y0145528D01*
+X0242401Y0145549D01*
+X0242470Y0145566D01*
+X0242539Y0145580D01*
+X0242608Y0145589D01*
+X0242679Y0145595D01*
+X0242749Y0145597D01*
+X0244027Y0145597D01*
+X0244027Y0140997D01*
+X0230277Y0135597D02*
+X0230277Y0130997D01*
+X0230277Y0133041D02*
+X0228999Y0133041D01*
+X0228743Y0133041D02*
+X0227721Y0130997D01*
+X0225806Y0130997D02*
+X0224272Y0130997D01*
+X0224210Y0130999D01*
+X0224149Y0131004D01*
+X0224088Y0131014D01*
+X0224027Y0131027D01*
+X0223968Y0131043D01*
+X0223910Y0131063D01*
+X0223853Y0131087D01*
+X0223797Y0131114D01*
+X0223743Y0131144D01*
+X0223691Y0131178D01*
+X0223642Y0131214D01*
+X0223594Y0131254D01*
+X0223549Y0131296D01*
+X0223507Y0131341D01*
+X0223467Y0131389D01*
+X0223431Y0131438D01*
+X0223397Y0131490D01*
+X0223367Y0131544D01*
+X0223340Y0131600D01*
+X0223316Y0131657D01*
+X0223296Y0131715D01*
+X0223280Y0131774D01*
+X0223267Y0131835D01*
+X0223257Y0131896D01*
+X0223252Y0131957D01*
+X0223250Y0132019D01*
+X0223250Y0132530D01*
+X0223252Y0132592D01*
+X0223257Y0132653D01*
+X0223267Y0132714D01*
+X0223280Y0132775D01*
+X0223296Y0132834D01*
+X0223316Y0132892D01*
+X0223340Y0132949D01*
+X0223367Y0133005D01*
+X0223397Y0133059D01*
+X0223431Y0133111D01*
+X0223467Y0133160D01*
+X0223507Y0133208D01*
+X0223549Y0133253D01*
+X0223594Y0133295D01*
+X0223642Y0133335D01*
+X0223691Y0133371D01*
+X0223743Y0133405D01*
+X0223797Y0133435D01*
+X0223853Y0133462D01*
+X0223910Y0133486D01*
+X0223968Y0133506D01*
+X0224027Y0133522D01*
+X0224088Y0133535D01*
+X0224149Y0133545D01*
+X0224210Y0133550D01*
+X0224272Y0133552D01*
+X0225806Y0133552D01*
+X0225806Y0135597D01*
+X0223250Y0135597D01*
+X0228999Y0135597D02*
+X0230277Y0135597D01*
+X0228999Y0135597D02*
+X0228929Y0135595D01*
+X0228858Y0135589D01*
+X0228789Y0135580D01*
+X0228720Y0135566D01*
+X0228651Y0135549D01*
+X0228584Y0135528D01*
+X0228518Y0135503D01*
+X0228454Y0135475D01*
+X0228391Y0135443D01*
+X0228330Y0135408D01*
+X0228271Y0135369D01*
+X0228214Y0135328D01*
+X0228160Y0135283D01*
+X0228108Y0135235D01*
+X0228059Y0135185D01*
+X0228012Y0135131D01*
+X0227969Y0135076D01*
+X0227929Y0135018D01*
+X0227892Y0134958D01*
+X0227859Y0134896D01*
+X0227829Y0134832D01*
+X0227802Y0134767D01*
+X0227779Y0134701D01*
+X0227760Y0134633D01*
+X0227745Y0134564D01*
+X0227733Y0134495D01*
+X0227725Y0134425D01*
+X0227721Y0134354D01*
+X0227721Y0134284D01*
+X0227725Y0134213D01*
+X0227733Y0134143D01*
+X0227745Y0134074D01*
+X0227760Y0134005D01*
+X0227779Y0133937D01*
+X0227802Y0133871D01*
+X0227829Y0133806D01*
+X0227859Y0133742D01*
+X0227892Y0133680D01*
+X0227929Y0133620D01*
+X0227969Y0133562D01*
+X0228012Y0133507D01*
+X0228059Y0133453D01*
+X0228108Y0133403D01*
+X0228160Y0133355D01*
+X0228214Y0133310D01*
+X0228271Y0133269D01*
+X0228330Y0133230D01*
+X0228391Y0133195D01*
+X0228454Y0133163D01*
+X0228518Y0133135D01*
+X0228584Y0133110D01*
+X0228651Y0133089D01*
+X0228720Y0133072D01*
+X0228789Y0133058D01*
+X0228858Y0133049D01*
+X0228929Y0133043D01*
+X0228999Y0133041D01*
+X0200350Y0184747D02*
+X0200350Y0189347D01*
+X0199072Y0189347D01*
+X0199002Y0189345D01*
+X0198931Y0189339D01*
+X0198862Y0189330D01*
+X0198793Y0189316D01*
+X0198724Y0189299D01*
+X0198657Y0189278D01*
+X0198591Y0189253D01*
+X0198527Y0189225D01*
+X0198464Y0189193D01*
+X0198403Y0189158D01*
+X0198344Y0189119D01*
+X0198287Y0189078D01*
+X0198233Y0189033D01*
+X0198181Y0188985D01*
+X0198132Y0188935D01*
+X0198085Y0188881D01*
+X0198042Y0188826D01*
+X0198002Y0188768D01*
+X0197965Y0188708D01*
+X0197932Y0188646D01*
+X0197902Y0188582D01*
+X0197875Y0188517D01*
+X0197852Y0188451D01*
+X0197833Y0188383D01*
+X0197818Y0188314D01*
+X0197806Y0188245D01*
+X0197798Y0188175D01*
+X0197794Y0188104D01*
+X0197794Y0188034D01*
+X0197798Y0187963D01*
+X0197806Y0187893D01*
+X0197818Y0187824D01*
+X0197833Y0187755D01*
+X0197852Y0187687D01*
+X0197875Y0187621D01*
+X0197902Y0187556D01*
+X0197932Y0187492D01*
+X0197965Y0187430D01*
+X0198002Y0187370D01*
+X0198042Y0187312D01*
+X0198085Y0187257D01*
+X0198132Y0187203D01*
+X0198181Y0187153D01*
+X0198233Y0187105D01*
+X0198287Y0187060D01*
+X0198344Y0187019D01*
+X0198403Y0186980D01*
+X0198464Y0186945D01*
+X0198527Y0186913D01*
+X0198591Y0186885D01*
+X0198657Y0186860D01*
+X0198724Y0186839D01*
+X0198793Y0186822D01*
+X0198862Y0186808D01*
+X0198931Y0186799D01*
+X0199002Y0186793D01*
+X0199072Y0186791D01*
+X0200350Y0186791D01*
+X0198817Y0186791D02*
+X0197794Y0184747D01*
+X0195879Y0184747D02*
+X0193323Y0184747D01*
+X0194601Y0184747D02*
+X0194601Y0189347D01*
+X0195879Y0188324D01*
+X0249500Y0189519D02*
+X0252056Y0189519D01*
+X0251033Y0193097D01*
+X0250267Y0190541D02*
+X0250267Y0188497D01*
+X0253971Y0188497D02*
+X0254993Y0190541D01*
+X0255249Y0190541D02*
+X0256527Y0190541D01*
+X0255249Y0190541D02*
+X0255179Y0190543D01*
+X0255108Y0190549D01*
+X0255039Y0190558D01*
+X0254970Y0190572D01*
+X0254901Y0190589D01*
+X0254834Y0190610D01*
+X0254768Y0190635D01*
+X0254704Y0190663D01*
+X0254641Y0190695D01*
+X0254580Y0190730D01*
+X0254521Y0190769D01*
+X0254464Y0190810D01*
+X0254410Y0190855D01*
+X0254358Y0190903D01*
+X0254309Y0190953D01*
+X0254262Y0191007D01*
+X0254219Y0191062D01*
+X0254179Y0191120D01*
+X0254142Y0191180D01*
+X0254109Y0191242D01*
+X0254079Y0191306D01*
+X0254052Y0191371D01*
+X0254029Y0191437D01*
+X0254010Y0191505D01*
+X0253995Y0191574D01*
+X0253983Y0191643D01*
+X0253975Y0191713D01*
+X0253971Y0191784D01*
+X0253971Y0191854D01*
+X0253975Y0191925D01*
+X0253983Y0191995D01*
+X0253995Y0192064D01*
+X0254010Y0192133D01*
+X0254029Y0192201D01*
+X0254052Y0192267D01*
+X0254079Y0192332D01*
+X0254109Y0192396D01*
+X0254142Y0192458D01*
+X0254179Y0192518D01*
+X0254219Y0192576D01*
+X0254262Y0192631D01*
+X0254309Y0192685D01*
+X0254358Y0192735D01*
+X0254410Y0192783D01*
+X0254464Y0192828D01*
+X0254521Y0192869D01*
+X0254580Y0192908D01*
+X0254641Y0192943D01*
+X0254704Y0192975D01*
+X0254768Y0193003D01*
+X0254834Y0193028D01*
+X0254901Y0193049D01*
+X0254970Y0193066D01*
+X0255039Y0193080D01*
+X0255108Y0193089D01*
+X0255179Y0193095D01*
+X0255249Y0193097D01*
+X0256527Y0193097D01*
+X0256527Y0188497D01*
+X0060350Y0245008D02*
+X0060350Y0246286D01*
+X0060348Y0246349D01*
+X0060342Y0246412D01*
+X0060333Y0246474D01*
+X0060319Y0246535D01*
+X0060302Y0246596D01*
+X0060281Y0246655D01*
+X0060256Y0246713D01*
+X0060228Y0246770D01*
+X0060197Y0246824D01*
+X0060162Y0246876D01*
+X0060124Y0246927D01*
+X0060083Y0246975D01*
+X0060039Y0247020D01*
+X0059993Y0247062D01*
+X0059944Y0247102D01*
+X0059893Y0247138D01*
+X0059839Y0247171D01*
+X0059784Y0247201D01*
+X0059726Y0247227D01*
+X0059668Y0247250D01*
+X0059608Y0247269D01*
+X0059547Y0247284D01*
+X0059485Y0247296D01*
+X0059422Y0247304D01*
+X0059359Y0247308D01*
+X0059297Y0247308D01*
+X0059234Y0247304D01*
+X0059171Y0247296D01*
+X0059109Y0247284D01*
+X0059048Y0247269D01*
+X0058988Y0247250D01*
+X0058930Y0247227D01*
+X0058872Y0247201D01*
+X0058817Y0247171D01*
+X0058763Y0247138D01*
+X0058712Y0247102D01*
+X0058663Y0247062D01*
+X0058617Y0247020D01*
+X0058573Y0246975D01*
+X0058532Y0246927D01*
+X0058494Y0246876D01*
+X0058459Y0246824D01*
+X0058428Y0246770D01*
+X0058400Y0246713D01*
+X0058375Y0246655D01*
+X0058354Y0246596D01*
+X0058337Y0246535D01*
+X0058323Y0246474D01*
+X0058314Y0246412D01*
+X0058308Y0246349D01*
+X0058306Y0246286D01*
+X0058306Y0245008D01*
+X0058306Y0246286D02*
+X0058304Y0246356D01*
+X0058298Y0246427D01*
+X0058289Y0246496D01*
+X0058275Y0246565D01*
+X0058258Y0246634D01*
+X0058237Y0246701D01*
+X0058212Y0246767D01*
+X0058184Y0246831D01*
+X0058152Y0246894D01*
+X0058117Y0246955D01*
+X0058078Y0247014D01*
+X0058037Y0247071D01*
+X0057992Y0247125D01*
+X0057944Y0247177D01*
+X0057894Y0247226D01*
+X0057840Y0247273D01*
+X0057785Y0247316D01*
+X0057727Y0247356D01*
+X0057667Y0247393D01*
+X0057605Y0247426D01*
+X0057541Y0247456D01*
+X0057476Y0247483D01*
+X0057410Y0247506D01*
+X0057342Y0247525D01*
+X0057273Y0247540D01*
+X0057204Y0247552D01*
+X0057134Y0247560D01*
+X0057063Y0247564D01*
+X0056993Y0247564D01*
+X0056922Y0247560D01*
+X0056852Y0247552D01*
+X0056783Y0247540D01*
+X0056714Y0247525D01*
+X0056646Y0247506D01*
+X0056580Y0247483D01*
+X0056515Y0247456D01*
+X0056451Y0247426D01*
+X0056389Y0247393D01*
+X0056329Y0247356D01*
+X0056271Y0247316D01*
+X0056216Y0247273D01*
+X0056162Y0247226D01*
+X0056112Y0247177D01*
+X0056064Y0247125D01*
+X0056019Y0247071D01*
+X0055978Y0247014D01*
+X0055939Y0246955D01*
+X0055904Y0246894D01*
+X0055872Y0246831D01*
+X0055844Y0246767D01*
+X0055819Y0246701D01*
+X0055798Y0246634D01*
+X0055781Y0246565D01*
+X0055767Y0246496D01*
+X0055758Y0246427D01*
+X0055752Y0246356D01*
+X0055750Y0246286D01*
+X0055750Y0245008D01*
+X0060350Y0245008D01*
+X0058434Y0241080D02*
+X0058468Y0241026D01*
+X0058505Y0240975D01*
+X0058545Y0240926D01*
+X0058588Y0240879D01*
+X0058634Y0240836D01*
+X0058682Y0240795D01*
+X0058733Y0240757D01*
+X0058786Y0240722D01*
+X0058841Y0240690D01*
+X0058898Y0240662D01*
+X0058956Y0240638D01*
+X0059016Y0240617D01*
+X0059077Y0240600D01*
+X0059139Y0240586D01*
+X0059202Y0240577D01*
+X0059265Y0240571D01*
+X0059328Y0240569D01*
+X0059390Y0240571D01*
+X0059451Y0240576D01*
+X0059512Y0240586D01*
+X0059573Y0240599D01*
+X0059632Y0240615D01*
+X0059690Y0240635D01*
+X0059747Y0240659D01*
+X0059803Y0240686D01*
+X0059857Y0240716D01*
+X0059909Y0240750D01*
+X0059958Y0240787D01*
+X0060006Y0240826D01*
+X0060051Y0240868D01*
+X0060093Y0240913D01*
+X0060133Y0240961D01*
+X0060169Y0241010D01*
+X0060203Y0241062D01*
+X0060233Y0241116D01*
+X0060260Y0241172D01*
+X0060284Y0241229D01*
+X0060304Y0241287D01*
+X0060320Y0241346D01*
+X0060333Y0241407D01*
+X0060343Y0241468D01*
+X0060348Y0241529D01*
+X0060350Y0241591D01*
+X0060348Y0241673D01*
+X0060343Y0241755D01*
+X0060334Y0241837D01*
+X0060322Y0241918D01*
+X0060306Y0241999D01*
+X0060287Y0242079D01*
+X0060264Y0242158D01*
+X0060238Y0242236D01*
+X0060209Y0242313D01*
+X0060176Y0242388D01*
+X0060140Y0242462D01*
+X0060102Y0242535D01*
+X0060060Y0242606D01*
+X0060015Y0242674D01*
+X0059967Y0242741D01*
+X0056389Y0240441D02*
+X0056326Y0240505D01*
+X0056267Y0240573D01*
+X0056210Y0240642D01*
+X0056156Y0240714D01*
+X0056105Y0240788D01*
+X0056057Y0240864D01*
+X0056013Y0240941D01*
+X0055972Y0241021D01*
+X0055934Y0241102D01*
+X0055899Y0241185D01*
+X0055868Y0241269D01*
+X0055841Y0241355D01*
+X0055817Y0241441D01*
+X0055796Y0241529D01*
+X0055780Y0241617D01*
+X0055767Y0241706D01*
+X0055757Y0241795D01*
+X0055752Y0241884D01*
+X0055750Y0241974D01*
+X0055752Y0242036D01*
+X0055757Y0242097D01*
+X0055767Y0242158D01*
+X0055780Y0242219D01*
+X0055796Y0242278D01*
+X0055816Y0242336D01*
+X0055840Y0242393D01*
+X0055867Y0242449D01*
+X0055897Y0242503D01*
+X0055931Y0242555D01*
+X0055967Y0242604D01*
+X0056007Y0242652D01*
+X0056049Y0242697D01*
+X0056094Y0242739D01*
+X0056142Y0242779D01*
+X0056191Y0242815D01*
+X0056243Y0242849D01*
+X0056297Y0242879D01*
+X0056353Y0242906D01*
+X0056410Y0242930D01*
+X0056468Y0242950D01*
+X0056527Y0242966D01*
+X0056588Y0242979D01*
+X0056649Y0242989D01*
+X0056710Y0242994D01*
+X0056772Y0242996D01*
+X0057667Y0242486D02*
+X0058433Y0241080D01*
+X0057666Y0242486D02*
+X0057632Y0242540D01*
+X0057595Y0242591D01*
+X0057555Y0242640D01*
+X0057512Y0242687D01*
+X0057466Y0242730D01*
+X0057418Y0242771D01*
+X0057367Y0242809D01*
+X0057314Y0242844D01*
+X0057259Y0242876D01*
+X0057202Y0242904D01*
+X0057144Y0242928D01*
+X0057084Y0242949D01*
+X0057023Y0242966D01*
+X0056961Y0242980D01*
+X0056898Y0242989D01*
+X0056835Y0242995D01*
+X0056772Y0242997D01*
+X0055750Y0249291D02*
+X0055750Y0251847D01*
+X0055750Y0249291D02*
+X0058306Y0251463D01*
+X0060350Y0250697D02*
+X0060348Y0250623D01*
+X0060343Y0250549D01*
+X0060333Y0250475D01*
+X0060320Y0250402D01*
+X0060304Y0250329D01*
+X0060283Y0250258D01*
+X0060259Y0250188D01*
+X0060232Y0250119D01*
+X0060201Y0250051D01*
+X0060167Y0249985D01*
+X0060130Y0249921D01*
+X0060089Y0249859D01*
+X0060045Y0249799D01*
+X0059999Y0249741D01*
+X0059949Y0249685D01*
+X0059897Y0249632D01*
+X0059842Y0249582D01*
+X0059785Y0249535D01*
+X0059725Y0249491D01*
+X0059663Y0249449D01*
+X0059600Y0249411D01*
+X0059534Y0249376D01*
+X0059467Y0249345D01*
+X0059398Y0249317D01*
+X0059328Y0249292D01*
+X0058306Y0251463D02*
+X0058353Y0251510D01*
+X0058403Y0251554D01*
+X0058455Y0251596D01*
+X0058509Y0251635D01*
+X0058565Y0251670D01*
+X0058623Y0251703D01*
+X0058683Y0251733D01*
+X0058744Y0251759D01*
+X0058807Y0251782D01*
+X0058871Y0251801D01*
+X0058935Y0251817D01*
+X0059001Y0251830D01*
+X0059067Y0251839D01*
+X0059133Y0251844D01*
+X0059200Y0251846D01*
+X0059200Y0251847D02*
+X0059267Y0251845D01*
+X0059334Y0251839D01*
+X0059400Y0251830D01*
+X0059465Y0251816D01*
+X0059530Y0251799D01*
+X0059593Y0251778D01*
+X0059655Y0251753D01*
+X0059716Y0251725D01*
+X0059775Y0251693D01*
+X0059832Y0251658D01*
+X0059887Y0251619D01*
+X0059939Y0251578D01*
+X0059989Y0251533D01*
+X0060036Y0251486D01*
+X0060081Y0251436D01*
+X0060122Y0251384D01*
+X0060161Y0251329D01*
+X0060196Y0251272D01*
+X0060228Y0251213D01*
+X0060256Y0251152D01*
+X0060281Y0251090D01*
+X0060302Y0251027D01*
+X0060319Y0250962D01*
+X0060333Y0250897D01*
+X0060342Y0250831D01*
+X0060348Y0250764D01*
+X0060350Y0250697D01*
+D13*
+X0076119Y0252702D02*
+X0076119Y0253525D01*
+X0076120Y0252702D02*
+X0076122Y0252646D01*
+X0076128Y0252590D01*
+X0076137Y0252535D01*
+X0076150Y0252480D01*
+X0076167Y0252427D01*
+X0076188Y0252375D01*
+X0076212Y0252324D01*
+X0076240Y0252275D01*
+X0076270Y0252228D01*
+X0076304Y0252183D01*
+X0076341Y0252141D01*
+X0076381Y0252101D01*
+X0076423Y0252064D01*
+X0076468Y0252030D01*
+X0076515Y0252000D01*
+X0076564Y0251972D01*
+X0076615Y0251948D01*
+X0076667Y0251927D01*
+X0076720Y0251910D01*
+X0076775Y0251897D01*
+X0076830Y0251888D01*
+X0076886Y0251882D01*
+X0076942Y0251880D01*
+X0078997Y0251880D01*
+X0079053Y0251882D01*
+X0079109Y0251888D01*
+X0079164Y0251897D01*
+X0079219Y0251910D01*
+X0079272Y0251927D01*
+X0079324Y0251948D01*
+X0079375Y0251972D01*
+X0079424Y0252000D01*
+X0079471Y0252030D01*
+X0079516Y0252064D01*
+X0079558Y0252101D01*
+X0079598Y0252141D01*
+X0079635Y0252183D01*
+X0079669Y0252228D01*
+X0079699Y0252275D01*
+X0079727Y0252324D01*
+X0079751Y0252375D01*
+X0079772Y0252427D01*
+X0079789Y0252480D01*
+X0079802Y0252535D01*
+X0079811Y0252590D01*
+X0079817Y0252646D01*
+X0079819Y0252702D01*
+X0079819Y0253525D01*
+X0078175Y0254890D02*
+X0077147Y0254890D01*
+X0078175Y0254890D02*
+X0078175Y0256124D01*
+X0078175Y0254891D02*
+X0078256Y0254893D01*
+X0078336Y0254899D01*
+X0078416Y0254909D01*
+X0078496Y0254923D01*
+X0078574Y0254940D01*
+X0078652Y0254962D01*
+X0078729Y0254987D01*
+X0078804Y0255016D01*
+X0078878Y0255049D01*
+X0078950Y0255085D01*
+X0079020Y0255125D01*
+X0079088Y0255168D01*
+X0079154Y0255215D01*
+X0079218Y0255264D01*
+X0079279Y0255317D01*
+X0079337Y0255373D01*
+X0079393Y0255431D01*
+X0079446Y0255492D01*
+X0079495Y0255556D01*
+X0079542Y0255622D01*
+X0079585Y0255690D01*
+X0079625Y0255760D01*
+X0079661Y0255832D01*
+X0079694Y0255906D01*
+X0079723Y0255981D01*
+X0079748Y0256058D01*
+X0079770Y0256136D01*
+X0079787Y0256214D01*
+X0079801Y0256294D01*
+X0079811Y0256374D01*
+X0079817Y0256454D01*
+X0079819Y0256535D01*
+X0077353Y0256946D02*
+X0077147Y0256946D01*
+X0077353Y0256946D02*
+X0077409Y0256944D01*
+X0077465Y0256938D01*
+X0077520Y0256929D01*
+X0077575Y0256916D01*
+X0077628Y0256899D01*
+X0077680Y0256878D01*
+X0077731Y0256854D01*
+X0077780Y0256826D01*
+X0077827Y0256796D01*
+X0077872Y0256762D01*
+X0077914Y0256725D01*
+X0077954Y0256685D01*
+X0077991Y0256643D01*
+X0078025Y0256598D01*
+X0078055Y0256551D01*
+X0078083Y0256502D01*
+X0078107Y0256451D01*
+X0078128Y0256399D01*
+X0078145Y0256346D01*
+X0078158Y0256291D01*
+X0078167Y0256236D01*
+X0078173Y0256180D01*
+X0078175Y0256124D01*
+X0077147Y0256946D02*
+X0077084Y0256944D01*
+X0077021Y0256938D01*
+X0076958Y0256928D01*
+X0076896Y0256915D01*
+X0076835Y0256898D01*
+X0076776Y0256877D01*
+X0076717Y0256852D01*
+X0076661Y0256824D01*
+X0076606Y0256792D01*
+X0076553Y0256757D01*
+X0076503Y0256719D01*
+X0076454Y0256678D01*
+X0076409Y0256634D01*
+X0076366Y0256587D01*
+X0076327Y0256538D01*
+X0076290Y0256486D01*
+X0076257Y0256432D01*
+X0076227Y0256376D01*
+X0076200Y0256319D01*
+X0076177Y0256260D01*
+X0076158Y0256199D01*
+X0076143Y0256138D01*
+X0076131Y0256076D01*
+X0076123Y0256013D01*
+X0076119Y0255950D01*
+X0076119Y0255886D01*
+X0076123Y0255823D01*
+X0076131Y0255760D01*
+X0076143Y0255698D01*
+X0076158Y0255637D01*
+X0076177Y0255576D01*
+X0076200Y0255517D01*
+X0076227Y0255460D01*
+X0076257Y0255404D01*
+X0076290Y0255350D01*
+X0076327Y0255298D01*
+X0076366Y0255249D01*
+X0076409Y0255202D01*
+X0076454Y0255158D01*
+X0076503Y0255117D01*
+X0076553Y0255079D01*
+X0076606Y0255044D01*
+X0076661Y0255012D01*
+X0076717Y0254984D01*
+X0076776Y0254959D01*
+X0076835Y0254938D01*
+X0076896Y0254921D01*
+X0076958Y0254908D01*
+X0077021Y0254898D01*
+X0077084Y0254892D01*
+X0077147Y0254890D01*
+X0083973Y0221316D02*
+X0085206Y0221316D01*
+X0083973Y0221316D02*
+X0083917Y0221314D01*
+X0083861Y0221308D01*
+X0083806Y0221299D01*
+X0083751Y0221286D01*
+X0083698Y0221269D01*
+X0083646Y0221248D01*
+X0083595Y0221224D01*
+X0083546Y0221196D01*
+X0083499Y0221166D01*
+X0083454Y0221132D01*
+X0083412Y0221095D01*
+X0083372Y0221055D01*
+X0083335Y0221013D01*
+X0083301Y0220968D01*
+X0083271Y0220921D01*
+X0083243Y0220872D01*
+X0083219Y0220821D01*
+X0083198Y0220769D01*
+X0083181Y0220716D01*
+X0083168Y0220661D01*
+X0083159Y0220606D01*
+X0083153Y0220550D01*
+X0083151Y0220494D01*
+X0083153Y0220438D01*
+X0083159Y0220382D01*
+X0083168Y0220327D01*
+X0083181Y0220272D01*
+X0083198Y0220219D01*
+X0083219Y0220167D01*
+X0083243Y0220116D01*
+X0083271Y0220067D01*
+X0083301Y0220020D01*
+X0083335Y0219975D01*
+X0083372Y0219933D01*
+X0083412Y0219893D01*
+X0083454Y0219856D01*
+X0083499Y0219822D01*
+X0083546Y0219792D01*
+X0083595Y0219764D01*
+X0083646Y0219740D01*
+X0083698Y0219719D01*
+X0083751Y0219702D01*
+X0083806Y0219689D01*
+X0083861Y0219680D01*
+X0083917Y0219674D01*
+X0083973Y0219672D01*
+X0084795Y0219672D01*
+X0084179Y0219672D02*
+X0084116Y0219670D01*
+X0084053Y0219664D01*
+X0083990Y0219654D01*
+X0083928Y0219641D01*
+X0083867Y0219624D01*
+X0083808Y0219603D01*
+X0083749Y0219578D01*
+X0083693Y0219550D01*
+X0083638Y0219518D01*
+X0083585Y0219483D01*
+X0083535Y0219445D01*
+X0083486Y0219404D01*
+X0083441Y0219360D01*
+X0083398Y0219313D01*
+X0083359Y0219264D01*
+X0083322Y0219212D01*
+X0083289Y0219158D01*
+X0083259Y0219102D01*
+X0083232Y0219045D01*
+X0083209Y0218986D01*
+X0083190Y0218925D01*
+X0083175Y0218864D01*
+X0083163Y0218802D01*
+X0083155Y0218739D01*
+X0083151Y0218676D01*
+X0083151Y0218612D01*
+X0083155Y0218549D01*
+X0083163Y0218486D01*
+X0083175Y0218424D01*
+X0083190Y0218363D01*
+X0083209Y0218302D01*
+X0083232Y0218243D01*
+X0083259Y0218186D01*
+X0083289Y0218130D01*
+X0083322Y0218076D01*
+X0083359Y0218024D01*
+X0083398Y0217975D01*
+X0083441Y0217928D01*
+X0083486Y0217884D01*
+X0083535Y0217843D01*
+X0083585Y0217805D01*
+X0083638Y0217770D01*
+X0083693Y0217738D01*
+X0083749Y0217710D01*
+X0083808Y0217685D01*
+X0083867Y0217664D01*
+X0083928Y0217647D01*
+X0083990Y0217634D01*
+X0084053Y0217624D01*
+X0084116Y0217618D01*
+X0084179Y0217616D01*
+X0085206Y0217616D01*
+X0086751Y0217616D02*
+X0088806Y0217616D01*
+X0087779Y0217616D02*
+X0087779Y0221316D01*
+X0088806Y0220494D01*
+X0090172Y0221316D02*
+X0090994Y0221316D01*
+X0091050Y0221314D01*
+X0091106Y0221308D01*
+X0091161Y0221299D01*
+X0091216Y0221286D01*
+X0091269Y0221269D01*
+X0091321Y0221248D01*
+X0091372Y0221224D01*
+X0091421Y0221196D01*
+X0091468Y0221166D01*
+X0091513Y0221132D01*
+X0091555Y0221095D01*
+X0091595Y0221055D01*
+X0091632Y0221013D01*
+X0091666Y0220968D01*
+X0091696Y0220921D01*
+X0091724Y0220872D01*
+X0091748Y0220821D01*
+X0091769Y0220769D01*
+X0091786Y0220716D01*
+X0091799Y0220661D01*
+X0091808Y0220606D01*
+X0091814Y0220550D01*
+X0091816Y0220494D01*
+X0091816Y0218438D01*
+X0091814Y0218382D01*
+X0091808Y0218326D01*
+X0091799Y0218271D01*
+X0091786Y0218216D01*
+X0091769Y0218163D01*
+X0091748Y0218111D01*
+X0091724Y0218060D01*
+X0091696Y0218011D01*
+X0091666Y0217964D01*
+X0091632Y0217919D01*
+X0091595Y0217877D01*
+X0091555Y0217837D01*
+X0091513Y0217800D01*
+X0091468Y0217766D01*
+X0091421Y0217736D01*
+X0091372Y0217708D01*
+X0091321Y0217684D01*
+X0091269Y0217663D01*
+X0091216Y0217646D01*
+X0091161Y0217633D01*
+X0091106Y0217624D01*
+X0091050Y0217618D01*
+X0090994Y0217616D01*
+X0090172Y0217616D01*
+X0120853Y0254647D02*
+X0122908Y0254647D01*
+X0122908Y0254648D02*
+X0122964Y0254650D01*
+X0123020Y0254656D01*
+X0123075Y0254665D01*
+X0123130Y0254678D01*
+X0123183Y0254695D01*
+X0123235Y0254716D01*
+X0123286Y0254740D01*
+X0123335Y0254768D01*
+X0123382Y0254798D01*
+X0123427Y0254832D01*
+X0123469Y0254869D01*
+X0123509Y0254909D01*
+X0123546Y0254951D01*
+X0123580Y0254996D01*
+X0123610Y0255043D01*
+X0123638Y0255092D01*
+X0123662Y0255143D01*
+X0123683Y0255195D01*
+X0123700Y0255248D01*
+X0123713Y0255303D01*
+X0123722Y0255358D01*
+X0123728Y0255414D01*
+X0123730Y0255470D01*
+X0123731Y0255470D02*
+X0123731Y0256292D01*
+X0123731Y0257658D02*
+X0123731Y0259713D01*
+X0120031Y0258685D01*
+X0120031Y0256292D02*
+X0120031Y0255470D01*
+X0120033Y0255414D01*
+X0120039Y0255358D01*
+X0120048Y0255303D01*
+X0120061Y0255248D01*
+X0120078Y0255195D01*
+X0120099Y0255143D01*
+X0120123Y0255092D01*
+X0120151Y0255043D01*
+X0120181Y0254996D01*
+X0120215Y0254951D01*
+X0120252Y0254909D01*
+X0120292Y0254869D01*
+X0120334Y0254832D01*
+X0120379Y0254798D01*
+X0120426Y0254768D01*
+X0120475Y0254740D01*
+X0120526Y0254716D01*
+X0120578Y0254695D01*
+X0120631Y0254678D01*
+X0120686Y0254665D01*
+X0120741Y0254656D01*
+X0120797Y0254650D01*
+X0120853Y0254648D01*
+X0123320Y0257658D02*
+X0123731Y0257658D01*
+X0126728Y0259447D02*
+X0127756Y0259447D01*
+X0126728Y0259446D02*
+X0126665Y0259448D01*
+X0126602Y0259454D01*
+X0126539Y0259464D01*
+X0126477Y0259477D01*
+X0126416Y0259494D01*
+X0126357Y0259515D01*
+X0126298Y0259540D01*
+X0126242Y0259568D01*
+X0126187Y0259600D01*
+X0126134Y0259635D01*
+X0126084Y0259673D01*
+X0126035Y0259714D01*
+X0125990Y0259758D01*
+X0125947Y0259805D01*
+X0125908Y0259854D01*
+X0125871Y0259906D01*
+X0125838Y0259960D01*
+X0125808Y0260016D01*
+X0125781Y0260073D01*
+X0125758Y0260132D01*
+X0125739Y0260193D01*
+X0125724Y0260254D01*
+X0125712Y0260316D01*
+X0125704Y0260379D01*
+X0125700Y0260442D01*
+X0125700Y0260506D01*
+X0125704Y0260569D01*
+X0125712Y0260632D01*
+X0125724Y0260694D01*
+X0125739Y0260755D01*
+X0125758Y0260816D01*
+X0125781Y0260875D01*
+X0125808Y0260932D01*
+X0125838Y0260988D01*
+X0125871Y0261042D01*
+X0125908Y0261094D01*
+X0125947Y0261143D01*
+X0125990Y0261190D01*
+X0126035Y0261234D01*
+X0126084Y0261275D01*
+X0126134Y0261313D01*
+X0126187Y0261348D01*
+X0126242Y0261380D01*
+X0126298Y0261408D01*
+X0126357Y0261433D01*
+X0126416Y0261454D01*
+X0126477Y0261471D01*
+X0126539Y0261484D01*
+X0126602Y0261494D01*
+X0126665Y0261500D01*
+X0126728Y0261502D01*
+X0126522Y0261502D02*
+X0127344Y0261502D01*
+X0126522Y0261502D02*
+X0126466Y0261504D01*
+X0126410Y0261510D01*
+X0126355Y0261519D01*
+X0126300Y0261532D01*
+X0126247Y0261549D01*
+X0126195Y0261570D01*
+X0126144Y0261594D01*
+X0126095Y0261622D01*
+X0126048Y0261652D01*
+X0126003Y0261686D01*
+X0125961Y0261723D01*
+X0125921Y0261763D01*
+X0125884Y0261805D01*
+X0125850Y0261850D01*
+X0125820Y0261897D01*
+X0125792Y0261946D01*
+X0125768Y0261997D01*
+X0125747Y0262049D01*
+X0125730Y0262102D01*
+X0125717Y0262157D01*
+X0125708Y0262212D01*
+X0125702Y0262268D01*
+X0125700Y0262324D01*
+X0125702Y0262380D01*
+X0125708Y0262436D01*
+X0125717Y0262491D01*
+X0125730Y0262546D01*
+X0125747Y0262599D01*
+X0125768Y0262651D01*
+X0125792Y0262702D01*
+X0125820Y0262751D01*
+X0125850Y0262798D01*
+X0125884Y0262843D01*
+X0125921Y0262885D01*
+X0125961Y0262925D01*
+X0126003Y0262962D01*
+X0126048Y0262996D01*
+X0126095Y0263026D01*
+X0126144Y0263054D01*
+X0126195Y0263078D01*
+X0126247Y0263099D01*
+X0126300Y0263116D01*
+X0126355Y0263129D01*
+X0126410Y0263138D01*
+X0126466Y0263144D01*
+X0126522Y0263146D01*
+X0126522Y0263147D02*
+X0127756Y0263147D01*
+X0130156Y0263147D02*
+X0131184Y0263147D01*
+X0131184Y0259447D01*
+X0130156Y0259447D01*
+X0130156Y0259446D02*
+X0130093Y0259448D01*
+X0130030Y0259454D01*
+X0129967Y0259464D01*
+X0129905Y0259477D01*
+X0129844Y0259494D01*
+X0129785Y0259515D01*
+X0129726Y0259540D01*
+X0129670Y0259568D01*
+X0129615Y0259600D01*
+X0129562Y0259635D01*
+X0129512Y0259673D01*
+X0129463Y0259714D01*
+X0129418Y0259758D01*
+X0129375Y0259805D01*
+X0129336Y0259854D01*
+X0129299Y0259906D01*
+X0129266Y0259960D01*
+X0129236Y0260016D01*
+X0129209Y0260073D01*
+X0129186Y0260132D01*
+X0129167Y0260193D01*
+X0129152Y0260254D01*
+X0129140Y0260316D01*
+X0129132Y0260379D01*
+X0129128Y0260442D01*
+X0129128Y0260506D01*
+X0129132Y0260569D01*
+X0129140Y0260632D01*
+X0129152Y0260694D01*
+X0129167Y0260755D01*
+X0129186Y0260816D01*
+X0129209Y0260875D01*
+X0129236Y0260932D01*
+X0129266Y0260988D01*
+X0129299Y0261042D01*
+X0129336Y0261094D01*
+X0129375Y0261143D01*
+X0129418Y0261190D01*
+X0129463Y0261234D01*
+X0129512Y0261275D01*
+X0129562Y0261313D01*
+X0129615Y0261348D01*
+X0129670Y0261380D01*
+X0129726Y0261408D01*
+X0129785Y0261433D01*
+X0129844Y0261454D01*
+X0129905Y0261471D01*
+X0129967Y0261484D01*
+X0130030Y0261494D01*
+X0130093Y0261500D01*
+X0130156Y0261502D01*
+X0131184Y0261502D01*
+X0130156Y0261502D02*
+X0130100Y0261504D01*
+X0130044Y0261510D01*
+X0129989Y0261519D01*
+X0129934Y0261532D01*
+X0129881Y0261549D01*
+X0129829Y0261570D01*
+X0129778Y0261594D01*
+X0129729Y0261622D01*
+X0129682Y0261652D01*
+X0129637Y0261686D01*
+X0129595Y0261723D01*
+X0129555Y0261763D01*
+X0129518Y0261805D01*
+X0129484Y0261850D01*
+X0129454Y0261897D01*
+X0129426Y0261946D01*
+X0129402Y0261997D01*
+X0129381Y0262049D01*
+X0129364Y0262102D01*
+X0129351Y0262157D01*
+X0129342Y0262212D01*
+X0129336Y0262268D01*
+X0129334Y0262324D01*
+X0129336Y0262380D01*
+X0129342Y0262436D01*
+X0129351Y0262491D01*
+X0129364Y0262546D01*
+X0129381Y0262599D01*
+X0129402Y0262651D01*
+X0129426Y0262702D01*
+X0129454Y0262751D01*
+X0129484Y0262798D01*
+X0129518Y0262843D01*
+X0129555Y0262885D01*
+X0129595Y0262925D01*
+X0129637Y0262962D01*
+X0129682Y0262996D01*
+X0129729Y0263026D01*
+X0129778Y0263054D01*
+X0129829Y0263078D01*
+X0129881Y0263099D01*
+X0129934Y0263116D01*
+X0129989Y0263129D01*
+X0130044Y0263138D01*
+X0130100Y0263144D01*
+X0130156Y0263146D01*
+X0133191Y0260988D02*
+X0134322Y0261605D01*
+X0133911Y0263147D02*
+X0133835Y0263145D01*
+X0133759Y0263139D01*
+X0133683Y0263130D01*
+X0133608Y0263117D01*
+X0133533Y0263100D01*
+X0133460Y0263079D01*
+X0133387Y0263055D01*
+X0133316Y0263028D01*
+X0133247Y0262996D01*
+X0133178Y0262962D01*
+X0133112Y0262924D01*
+X0133048Y0262883D01*
+X0132986Y0262839D01*
+X0134322Y0261605D02*
+X0134368Y0261634D01*
+X0134411Y0261666D01*
+X0134453Y0261700D01*
+X0134492Y0261738D01*
+X0134529Y0261777D01*
+X0134563Y0261819D01*
+X0134595Y0261864D01*
+X0134623Y0261910D01*
+X0134648Y0261958D01*
+X0134671Y0262007D01*
+X0134689Y0262058D01*
+X0134705Y0262110D01*
+X0134717Y0262162D01*
+X0134726Y0262216D01*
+X0134731Y0262270D01*
+X0134733Y0262324D01*
+X0134731Y0262380D01*
+X0134725Y0262436D01*
+X0134716Y0262491D01*
+X0134703Y0262546D01*
+X0134686Y0262599D01*
+X0134665Y0262651D01*
+X0134641Y0262702D01*
+X0134613Y0262751D01*
+X0134583Y0262798D01*
+X0134549Y0262843D01*
+X0134512Y0262885D01*
+X0134472Y0262925D01*
+X0134430Y0262962D01*
+X0134385Y0262996D01*
+X0134338Y0263026D01*
+X0134289Y0263054D01*
+X0134238Y0263078D01*
+X0134186Y0263099D01*
+X0134133Y0263116D01*
+X0134078Y0263129D01*
+X0134023Y0263138D01*
+X0133967Y0263144D01*
+X0133911Y0263146D01*
+X0134835Y0259961D02*
+X0134777Y0259905D01*
+X0134717Y0259852D01*
+X0134654Y0259801D01*
+X0134588Y0259754D01*
+X0134521Y0259710D01*
+X0134451Y0259669D01*
+X0134380Y0259631D01*
+X0134307Y0259597D01*
+X0134233Y0259566D01*
+X0134157Y0259538D01*
+X0134080Y0259514D01*
+X0134002Y0259494D01*
+X0133923Y0259477D01*
+X0133843Y0259464D01*
+X0133763Y0259454D01*
+X0133683Y0259449D01*
+X0133602Y0259447D01*
+X0133546Y0259449D01*
+X0133490Y0259455D01*
+X0133435Y0259464D01*
+X0133380Y0259477D01*
+X0133327Y0259494D01*
+X0133275Y0259515D01*
+X0133224Y0259539D01*
+X0133175Y0259567D01*
+X0133128Y0259597D01*
+X0133083Y0259631D01*
+X0133041Y0259668D01*
+X0133001Y0259708D01*
+X0132964Y0259750D01*
+X0132930Y0259795D01*
+X0132900Y0259842D01*
+X0132872Y0259891D01*
+X0132848Y0259942D01*
+X0132827Y0259994D01*
+X0132810Y0260047D01*
+X0132797Y0260102D01*
+X0132788Y0260157D01*
+X0132782Y0260213D01*
+X0132780Y0260269D01*
+X0132782Y0260323D01*
+X0132787Y0260377D01*
+X0132796Y0260431D01*
+X0132808Y0260483D01*
+X0132824Y0260535D01*
+X0132842Y0260586D01*
+X0132865Y0260635D01*
+X0132890Y0260683D01*
+X0132918Y0260729D01*
+X0132950Y0260774D01*
+X0132984Y0260816D01*
+X0133021Y0260855D01*
+X0133060Y0260893D01*
+X0133102Y0260927D01*
+X0133145Y0260959D01*
+X0133191Y0260988D01*
+X0231206Y0188977D02*
+X0232439Y0188977D01*
+X0233805Y0188977D02*
+X0234627Y0188977D01*
+X0234683Y0188975D01*
+X0234739Y0188969D01*
+X0234794Y0188960D01*
+X0234849Y0188947D01*
+X0234902Y0188930D01*
+X0234954Y0188909D01*
+X0235005Y0188885D01*
+X0235054Y0188857D01*
+X0235101Y0188827D01*
+X0235146Y0188793D01*
+X0235188Y0188756D01*
+X0235228Y0188716D01*
+X0235265Y0188674D01*
+X0235299Y0188629D01*
+X0235329Y0188582D01*
+X0235357Y0188533D01*
+X0235381Y0188482D01*
+X0235402Y0188430D01*
+X0235419Y0188377D01*
+X0235432Y0188322D01*
+X0235441Y0188267D01*
+X0235447Y0188211D01*
+X0235449Y0188155D01*
+X0235449Y0186100D01*
+X0235447Y0186044D01*
+X0235441Y0185988D01*
+X0235432Y0185933D01*
+X0235419Y0185878D01*
+X0235402Y0185825D01*
+X0235381Y0185773D01*
+X0235357Y0185722D01*
+X0235329Y0185673D01*
+X0235299Y0185626D01*
+X0235265Y0185581D01*
+X0235228Y0185539D01*
+X0235188Y0185499D01*
+X0235146Y0185462D01*
+X0235101Y0185428D01*
+X0235054Y0185398D01*
+X0235005Y0185370D01*
+X0234954Y0185346D01*
+X0234902Y0185325D01*
+X0234849Y0185308D01*
+X0234794Y0185295D01*
+X0234739Y0185286D01*
+X0234683Y0185280D01*
+X0234627Y0185278D01*
+X0234627Y0185277D02*
+X0233805Y0185277D01*
+X0232439Y0185277D02*
+X0231411Y0185277D01*
+X0231348Y0185279D01*
+X0231285Y0185285D01*
+X0231222Y0185295D01*
+X0231160Y0185308D01*
+X0231099Y0185325D01*
+X0231040Y0185346D01*
+X0230981Y0185371D01*
+X0230925Y0185399D01*
+X0230870Y0185431D01*
+X0230817Y0185466D01*
+X0230767Y0185504D01*
+X0230718Y0185545D01*
+X0230673Y0185589D01*
+X0230630Y0185636D01*
+X0230591Y0185685D01*
+X0230554Y0185737D01*
+X0230521Y0185791D01*
+X0230491Y0185847D01*
+X0230464Y0185904D01*
+X0230441Y0185963D01*
+X0230422Y0186024D01*
+X0230407Y0186085D01*
+X0230395Y0186147D01*
+X0230387Y0186210D01*
+X0230383Y0186273D01*
+X0230383Y0186337D01*
+X0230387Y0186400D01*
+X0230395Y0186463D01*
+X0230407Y0186525D01*
+X0230422Y0186586D01*
+X0230441Y0186647D01*
+X0230464Y0186706D01*
+X0230491Y0186763D01*
+X0230521Y0186819D01*
+X0230554Y0186873D01*
+X0230591Y0186925D01*
+X0230630Y0186974D01*
+X0230673Y0187021D01*
+X0230718Y0187065D01*
+X0230767Y0187106D01*
+X0230817Y0187144D01*
+X0230870Y0187179D01*
+X0230925Y0187211D01*
+X0230981Y0187239D01*
+X0231040Y0187264D01*
+X0231099Y0187285D01*
+X0231160Y0187302D01*
+X0231222Y0187315D01*
+X0231285Y0187325D01*
+X0231348Y0187331D01*
+X0231411Y0187333D01*
+X0231206Y0187333D02*
+X0232028Y0187333D01*
+X0231206Y0187333D02*
+X0231150Y0187335D01*
+X0231094Y0187341D01*
+X0231039Y0187350D01*
+X0230984Y0187363D01*
+X0230931Y0187380D01*
+X0230879Y0187401D01*
+X0230828Y0187425D01*
+X0230779Y0187453D01*
+X0230732Y0187483D01*
+X0230687Y0187517D01*
+X0230645Y0187554D01*
+X0230605Y0187594D01*
+X0230568Y0187636D01*
+X0230534Y0187681D01*
+X0230504Y0187728D01*
+X0230476Y0187777D01*
+X0230452Y0187828D01*
+X0230431Y0187880D01*
+X0230414Y0187933D01*
+X0230401Y0187988D01*
+X0230392Y0188043D01*
+X0230386Y0188099D01*
+X0230384Y0188155D01*
+X0230386Y0188211D01*
+X0230392Y0188267D01*
+X0230401Y0188322D01*
+X0230414Y0188377D01*
+X0230431Y0188430D01*
+X0230452Y0188482D01*
+X0230476Y0188533D01*
+X0230504Y0188582D01*
+X0230534Y0188629D01*
+X0230568Y0188674D01*
+X0230605Y0188716D01*
+X0230645Y0188756D01*
+X0230687Y0188793D01*
+X0230732Y0188827D01*
+X0230779Y0188857D01*
+X0230828Y0188885D01*
+X0230879Y0188909D01*
+X0230931Y0188930D01*
+X0230984Y0188947D01*
+X0231039Y0188960D01*
+X0231094Y0188969D01*
+X0231150Y0188975D01*
+X0231206Y0188977D01*
+X0136816Y0157994D02*
+X0136816Y0155938D01*
+X0136814Y0155882D01*
+X0136808Y0155826D01*
+X0136799Y0155771D01*
+X0136786Y0155716D01*
+X0136769Y0155663D01*
+X0136748Y0155611D01*
+X0136724Y0155560D01*
+X0136696Y0155511D01*
+X0136666Y0155464D01*
+X0136632Y0155419D01*
+X0136595Y0155377D01*
+X0136555Y0155337D01*
+X0136513Y0155300D01*
+X0136468Y0155266D01*
+X0136421Y0155236D01*
+X0136372Y0155208D01*
+X0136321Y0155184D01*
+X0136269Y0155163D01*
+X0136216Y0155146D01*
+X0136161Y0155133D01*
+X0136106Y0155124D01*
+X0136050Y0155118D01*
+X0135994Y0155116D01*
+X0135172Y0155116D01*
+X0133806Y0155116D02*
+X0131751Y0155116D01*
+X0132779Y0155116D02*
+X0132779Y0158816D01*
+X0133806Y0157994D01*
+X0135172Y0158816D02*
+X0135994Y0158816D01*
+X0136050Y0158814D01*
+X0136106Y0158808D01*
+X0136161Y0158799D01*
+X0136216Y0158786D01*
+X0136269Y0158769D01*
+X0136321Y0158748D01*
+X0136372Y0158724D01*
+X0136421Y0158696D01*
+X0136468Y0158666D01*
+X0136513Y0158632D01*
+X0136555Y0158595D01*
+X0136595Y0158555D01*
+X0136632Y0158513D01*
+X0136666Y0158468D01*
+X0136696Y0158421D01*
+X0136724Y0158372D01*
+X0136748Y0158321D01*
+X0136769Y0158269D01*
+X0136786Y0158216D01*
+X0136799Y0158161D01*
+X0136808Y0158106D01*
+X0136814Y0158050D01*
+X0136816Y0157994D01*
+X0130206Y0157172D02*
+X0130206Y0156144D01*
+X0130207Y0156144D02*
+X0130205Y0156081D01*
+X0130199Y0156018D01*
+X0130189Y0155955D01*
+X0130176Y0155893D01*
+X0130159Y0155832D01*
+X0130138Y0155773D01*
+X0130113Y0155714D01*
+X0130085Y0155658D01*
+X0130053Y0155603D01*
+X0130018Y0155550D01*
+X0129980Y0155500D01*
+X0129939Y0155451D01*
+X0129895Y0155406D01*
+X0129848Y0155363D01*
+X0129799Y0155324D01*
+X0129747Y0155287D01*
+X0129693Y0155254D01*
+X0129637Y0155224D01*
+X0129580Y0155197D01*
+X0129521Y0155174D01*
+X0129460Y0155155D01*
+X0129399Y0155140D01*
+X0129337Y0155128D01*
+X0129274Y0155120D01*
+X0129211Y0155116D01*
+X0129147Y0155116D01*
+X0129084Y0155120D01*
+X0129021Y0155128D01*
+X0128959Y0155140D01*
+X0128898Y0155155D01*
+X0128837Y0155174D01*
+X0128778Y0155197D01*
+X0128721Y0155224D01*
+X0128665Y0155254D01*
+X0128611Y0155287D01*
+X0128559Y0155324D01*
+X0128510Y0155363D01*
+X0128463Y0155406D01*
+X0128419Y0155451D01*
+X0128378Y0155500D01*
+X0128340Y0155550D01*
+X0128305Y0155603D01*
+X0128273Y0155658D01*
+X0128245Y0155714D01*
+X0128220Y0155773D01*
+X0128199Y0155832D01*
+X0128182Y0155893D01*
+X0128169Y0155955D01*
+X0128159Y0156018D01*
+X0128153Y0156081D01*
+X0128151Y0156144D01*
+X0128151Y0156349D01*
+X0128153Y0156405D01*
+X0128159Y0156461D01*
+X0128168Y0156516D01*
+X0128181Y0156571D01*
+X0128198Y0156624D01*
+X0128219Y0156676D01*
+X0128243Y0156727D01*
+X0128271Y0156776D01*
+X0128301Y0156823D01*
+X0128335Y0156868D01*
+X0128372Y0156910D01*
+X0128412Y0156950D01*
+X0128454Y0156987D01*
+X0128499Y0157021D01*
+X0128546Y0157051D01*
+X0128595Y0157079D01*
+X0128646Y0157103D01*
+X0128698Y0157124D01*
+X0128751Y0157141D01*
+X0128806Y0157154D01*
+X0128861Y0157163D01*
+X0128917Y0157169D01*
+X0128973Y0157171D01*
+X0128973Y0157172D02*
+X0130206Y0157172D01*
+X0130204Y0157250D01*
+X0130199Y0157328D01*
+X0130189Y0157406D01*
+X0130176Y0157483D01*
+X0130160Y0157560D01*
+X0130139Y0157635D01*
+X0130116Y0157710D01*
+X0130088Y0157783D01*
+X0130057Y0157855D01*
+X0130023Y0157925D01*
+X0129986Y0157994D01*
+X0129945Y0158061D01*
+X0129901Y0158126D01*
+X0129854Y0158188D01*
+X0129804Y0158249D01*
+X0129752Y0158306D01*
+X0129696Y0158362D01*
+X0129639Y0158414D01*
+X0129578Y0158464D01*
+X0129516Y0158511D01*
+X0129451Y0158555D01*
+X0129384Y0158596D01*
+X0129315Y0158633D01*
+X0129245Y0158667D01*
+X0129173Y0158698D01*
+X0129100Y0158726D01*
+X0129025Y0158749D01*
+X0128950Y0158770D01*
+X0128873Y0158786D01*
+X0128796Y0158799D01*
+X0128718Y0158809D01*
+X0128640Y0158814D01*
+X0128562Y0158816D01*
+X0064627Y0087727D02*
+X0063805Y0087727D01*
+X0064627Y0087727D02*
+X0064683Y0087725D01*
+X0064739Y0087719D01*
+X0064794Y0087710D01*
+X0064849Y0087697D01*
+X0064902Y0087680D01*
+X0064954Y0087659D01*
+X0065005Y0087635D01*
+X0065054Y0087607D01*
+X0065101Y0087577D01*
+X0065146Y0087543D01*
+X0065188Y0087506D01*
+X0065228Y0087466D01*
+X0065265Y0087424D01*
+X0065299Y0087379D01*
+X0065329Y0087332D01*
+X0065357Y0087283D01*
+X0065381Y0087232D01*
+X0065402Y0087180D01*
+X0065419Y0087127D01*
+X0065432Y0087072D01*
+X0065441Y0087017D01*
+X0065447Y0086961D01*
+X0065449Y0086905D01*
+X0065449Y0084850D01*
+X0065447Y0084794D01*
+X0065441Y0084738D01*
+X0065432Y0084683D01*
+X0065419Y0084628D01*
+X0065402Y0084575D01*
+X0065381Y0084523D01*
+X0065357Y0084472D01*
+X0065329Y0084423D01*
+X0065299Y0084376D01*
+X0065265Y0084331D01*
+X0065228Y0084289D01*
+X0065188Y0084249D01*
+X0065146Y0084212D01*
+X0065101Y0084178D01*
+X0065054Y0084148D01*
+X0065005Y0084120D01*
+X0064954Y0084096D01*
+X0064902Y0084075D01*
+X0064849Y0084058D01*
+X0064794Y0084045D01*
+X0064739Y0084036D01*
+X0064683Y0084030D01*
+X0064627Y0084028D01*
+X0064627Y0084027D02*
+X0063805Y0084027D01*
+X0062439Y0084027D02*
+X0060384Y0084027D01*
+X0061411Y0084027D02*
+X0061411Y0087727D01*
+X0062439Y0086905D01*
+X0058839Y0084850D02*
+X0056784Y0084850D01*
+X0057400Y0085672D02*
+X0057400Y0084027D01*
+X0058839Y0084850D02*
+X0058017Y0087727D01*
+X0062555Y0046477D02*
+X0063377Y0046477D01*
+X0063433Y0046475D01*
+X0063489Y0046469D01*
+X0063544Y0046460D01*
+X0063599Y0046447D01*
+X0063652Y0046430D01*
+X0063704Y0046409D01*
+X0063755Y0046385D01*
+X0063804Y0046357D01*
+X0063851Y0046327D01*
+X0063896Y0046293D01*
+X0063938Y0046256D01*
+X0063978Y0046216D01*
+X0064015Y0046174D01*
+X0064049Y0046129D01*
+X0064079Y0046082D01*
+X0064107Y0046033D01*
+X0064131Y0045982D01*
+X0064152Y0045930D01*
+X0064169Y0045877D01*
+X0064182Y0045822D01*
+X0064191Y0045767D01*
+X0064197Y0045711D01*
+X0064199Y0045655D01*
+X0064199Y0043600D01*
+X0064197Y0043544D01*
+X0064191Y0043488D01*
+X0064182Y0043433D01*
+X0064169Y0043378D01*
+X0064152Y0043325D01*
+X0064131Y0043273D01*
+X0064107Y0043222D01*
+X0064079Y0043173D01*
+X0064049Y0043126D01*
+X0064015Y0043081D01*
+X0063978Y0043039D01*
+X0063938Y0042999D01*
+X0063896Y0042962D01*
+X0063851Y0042928D01*
+X0063804Y0042898D01*
+X0063755Y0042870D01*
+X0063704Y0042846D01*
+X0063652Y0042825D01*
+X0063599Y0042808D01*
+X0063544Y0042795D01*
+X0063489Y0042786D01*
+X0063433Y0042780D01*
+X0063377Y0042778D01*
+X0063377Y0042777D02*
+X0062555Y0042777D01*
+X0061189Y0043805D02*
+X0061187Y0043742D01*
+X0061181Y0043679D01*
+X0061171Y0043616D01*
+X0061158Y0043554D01*
+X0061141Y0043493D01*
+X0061120Y0043434D01*
+X0061095Y0043375D01*
+X0061067Y0043319D01*
+X0061035Y0043264D01*
+X0061000Y0043211D01*
+X0060962Y0043161D01*
+X0060921Y0043112D01*
+X0060877Y0043067D01*
+X0060830Y0043024D01*
+X0060781Y0042985D01*
+X0060729Y0042948D01*
+X0060675Y0042915D01*
+X0060619Y0042885D01*
+X0060562Y0042858D01*
+X0060503Y0042835D01*
+X0060442Y0042816D01*
+X0060381Y0042801D01*
+X0060319Y0042789D01*
+X0060256Y0042781D01*
+X0060193Y0042777D01*
+X0060129Y0042777D01*
+X0060066Y0042781D01*
+X0060003Y0042789D01*
+X0059941Y0042801D01*
+X0059880Y0042816D01*
+X0059819Y0042835D01*
+X0059760Y0042858D01*
+X0059703Y0042885D01*
+X0059647Y0042915D01*
+X0059593Y0042948D01*
+X0059541Y0042985D01*
+X0059492Y0043024D01*
+X0059445Y0043067D01*
+X0059401Y0043112D01*
+X0059360Y0043161D01*
+X0059322Y0043211D01*
+X0059287Y0043264D01*
+X0059255Y0043319D01*
+X0059227Y0043375D01*
+X0059202Y0043434D01*
+X0059181Y0043493D01*
+X0059164Y0043554D01*
+X0059151Y0043616D01*
+X0059141Y0043679D01*
+X0059135Y0043742D01*
+X0059133Y0043805D01*
+X0059135Y0043868D01*
+X0059141Y0043931D01*
+X0059151Y0043994D01*
+X0059164Y0044056D01*
+X0059181Y0044117D01*
+X0059202Y0044176D01*
+X0059227Y0044235D01*
+X0059255Y0044291D01*
+X0059287Y0044346D01*
+X0059322Y0044399D01*
+X0059360Y0044449D01*
+X0059401Y0044498D01*
+X0059445Y0044543D01*
+X0059492Y0044586D01*
+X0059541Y0044625D01*
+X0059593Y0044662D01*
+X0059647Y0044695D01*
+X0059703Y0044725D01*
+X0059760Y0044752D01*
+X0059819Y0044775D01*
+X0059880Y0044794D01*
+X0059941Y0044809D01*
+X0060003Y0044821D01*
+X0060066Y0044829D01*
+X0060129Y0044833D01*
+X0060193Y0044833D01*
+X0060256Y0044829D01*
+X0060319Y0044821D01*
+X0060381Y0044809D01*
+X0060442Y0044794D01*
+X0060503Y0044775D01*
+X0060562Y0044752D01*
+X0060619Y0044725D01*
+X0060675Y0044695D01*
+X0060729Y0044662D01*
+X0060781Y0044625D01*
+X0060830Y0044586D01*
+X0060877Y0044543D01*
+X0060921Y0044498D01*
+X0060962Y0044449D01*
+X0061000Y0044399D01*
+X0061035Y0044346D01*
+X0061067Y0044291D01*
+X0061095Y0044235D01*
+X0061120Y0044176D01*
+X0061141Y0044117D01*
+X0061158Y0044056D01*
+X0061171Y0043994D01*
+X0061181Y0043931D01*
+X0061187Y0043868D01*
+X0061189Y0043805D01*
+X0060983Y0045655D02*
+X0060981Y0045599D01*
+X0060975Y0045543D01*
+X0060966Y0045488D01*
+X0060953Y0045433D01*
+X0060936Y0045380D01*
+X0060915Y0045328D01*
+X0060891Y0045277D01*
+X0060863Y0045228D01*
+X0060833Y0045181D01*
+X0060799Y0045136D01*
+X0060762Y0045094D01*
+X0060722Y0045054D01*
+X0060680Y0045017D01*
+X0060635Y0044983D01*
+X0060588Y0044953D01*
+X0060539Y0044925D01*
+X0060488Y0044901D01*
+X0060436Y0044880D01*
+X0060383Y0044863D01*
+X0060328Y0044850D01*
+X0060273Y0044841D01*
+X0060217Y0044835D01*
+X0060161Y0044833D01*
+X0060105Y0044835D01*
+X0060049Y0044841D01*
+X0059994Y0044850D01*
+X0059939Y0044863D01*
+X0059886Y0044880D01*
+X0059834Y0044901D01*
+X0059783Y0044925D01*
+X0059734Y0044953D01*
+X0059687Y0044983D01*
+X0059642Y0045017D01*
+X0059600Y0045054D01*
+X0059560Y0045094D01*
+X0059523Y0045136D01*
+X0059489Y0045181D01*
+X0059459Y0045228D01*
+X0059431Y0045277D01*
+X0059407Y0045328D01*
+X0059386Y0045380D01*
+X0059369Y0045433D01*
+X0059356Y0045488D01*
+X0059347Y0045543D01*
+X0059341Y0045599D01*
+X0059339Y0045655D01*
+X0059341Y0045711D01*
+X0059347Y0045767D01*
+X0059356Y0045822D01*
+X0059369Y0045877D01*
+X0059386Y0045930D01*
+X0059407Y0045982D01*
+X0059431Y0046033D01*
+X0059459Y0046082D01*
+X0059489Y0046129D01*
+X0059523Y0046174D01*
+X0059560Y0046216D01*
+X0059600Y0046256D01*
+X0059642Y0046293D01*
+X0059687Y0046327D01*
+X0059734Y0046357D01*
+X0059783Y0046385D01*
+X0059834Y0046409D01*
+X0059886Y0046430D01*
+X0059939Y0046447D01*
+X0059994Y0046460D01*
+X0060049Y0046469D01*
+X0060105Y0046475D01*
+X0060161Y0046477D01*
+X0060217Y0046475D01*
+X0060273Y0046469D01*
+X0060328Y0046460D01*
+X0060383Y0046447D01*
+X0060436Y0046430D01*
+X0060488Y0046409D01*
+X0060539Y0046385D01*
+X0060588Y0046357D01*
+X0060635Y0046327D01*
+X0060680Y0046293D01*
+X0060722Y0046256D01*
+X0060762Y0046216D01*
+X0060799Y0046174D01*
+X0060833Y0046129D01*
+X0060863Y0046082D01*
+X0060891Y0046033D01*
+X0060915Y0045982D01*
+X0060936Y0045930D01*
+X0060953Y0045877D01*
+X0060966Y0045822D01*
+X0060975Y0045767D01*
+X0060981Y0045711D01*
+X0060983Y0045655D01*
+X0086634Y0042950D02*
+X0086634Y0041922D01*
+X0087867Y0041922D01*
+X0086634Y0041922D02*
+X0086636Y0041844D01*
+X0086641Y0041766D01*
+X0086651Y0041688D01*
+X0086664Y0041611D01*
+X0086680Y0041534D01*
+X0086701Y0041459D01*
+X0086724Y0041384D01*
+X0086752Y0041311D01*
+X0086783Y0041239D01*
+X0086817Y0041169D01*
+X0086854Y0041100D01*
+X0086895Y0041033D01*
+X0086939Y0040968D01*
+X0086986Y0040906D01*
+X0087036Y0040845D01*
+X0087088Y0040788D01*
+X0087144Y0040732D01*
+X0087201Y0040680D01*
+X0087262Y0040630D01*
+X0087324Y0040583D01*
+X0087389Y0040539D01*
+X0087456Y0040498D01*
+X0087525Y0040461D01*
+X0087595Y0040427D01*
+X0087667Y0040396D01*
+X0087740Y0040368D01*
+X0087815Y0040345D01*
+X0087890Y0040324D01*
+X0087967Y0040308D01*
+X0088044Y0040295D01*
+X0088122Y0040285D01*
+X0088200Y0040280D01*
+X0088278Y0040278D01*
+X0090055Y0040277D02*
+X0090877Y0040277D01*
+X0090877Y0040278D02*
+X0090933Y0040280D01*
+X0090989Y0040286D01*
+X0091044Y0040295D01*
+X0091099Y0040308D01*
+X0091152Y0040325D01*
+X0091204Y0040346D01*
+X0091255Y0040370D01*
+X0091304Y0040398D01*
+X0091351Y0040428D01*
+X0091396Y0040462D01*
+X0091438Y0040499D01*
+X0091478Y0040539D01*
+X0091515Y0040581D01*
+X0091549Y0040626D01*
+X0091579Y0040673D01*
+X0091607Y0040722D01*
+X0091631Y0040773D01*
+X0091652Y0040825D01*
+X0091669Y0040878D01*
+X0091682Y0040933D01*
+X0091691Y0040988D01*
+X0091697Y0041044D01*
+X0091699Y0041100D01*
+X0091699Y0043155D01*
+X0091697Y0043211D01*
+X0091691Y0043267D01*
+X0091682Y0043322D01*
+X0091669Y0043377D01*
+X0091652Y0043430D01*
+X0091631Y0043482D01*
+X0091607Y0043533D01*
+X0091579Y0043582D01*
+X0091549Y0043629D01*
+X0091515Y0043674D01*
+X0091478Y0043716D01*
+X0091438Y0043756D01*
+X0091396Y0043793D01*
+X0091351Y0043827D01*
+X0091304Y0043857D01*
+X0091255Y0043885D01*
+X0091204Y0043909D01*
+X0091152Y0043930D01*
+X0091099Y0043947D01*
+X0091044Y0043960D01*
+X0090989Y0043969D01*
+X0090933Y0043975D01*
+X0090877Y0043977D01*
+X0090055Y0043977D01*
+X0088689Y0042950D02*
+X0088689Y0042744D01*
+X0088687Y0042688D01*
+X0088681Y0042632D01*
+X0088672Y0042577D01*
+X0088659Y0042522D01*
+X0088642Y0042469D01*
+X0088621Y0042417D01*
+X0088597Y0042366D01*
+X0088569Y0042317D01*
+X0088539Y0042270D01*
+X0088505Y0042225D01*
+X0088468Y0042183D01*
+X0088428Y0042143D01*
+X0088386Y0042106D01*
+X0088341Y0042072D01*
+X0088294Y0042042D01*
+X0088245Y0042014D01*
+X0088194Y0041990D01*
+X0088142Y0041969D01*
+X0088089Y0041952D01*
+X0088034Y0041939D01*
+X0087979Y0041930D01*
+X0087923Y0041924D01*
+X0087867Y0041922D01*
+X0088689Y0042950D02*
+X0088687Y0043013D01*
+X0088681Y0043076D01*
+X0088671Y0043139D01*
+X0088658Y0043201D01*
+X0088641Y0043262D01*
+X0088620Y0043321D01*
+X0088595Y0043380D01*
+X0088567Y0043436D01*
+X0088535Y0043491D01*
+X0088500Y0043544D01*
+X0088462Y0043594D01*
+X0088421Y0043643D01*
+X0088377Y0043688D01*
+X0088330Y0043731D01*
+X0088281Y0043770D01*
+X0088229Y0043807D01*
+X0088175Y0043840D01*
+X0088119Y0043870D01*
+X0088062Y0043897D01*
+X0088003Y0043920D01*
+X0087942Y0043939D01*
+X0087881Y0043954D01*
+X0087819Y0043966D01*
+X0087756Y0043974D01*
+X0087693Y0043978D01*
+X0087629Y0043978D01*
+X0087566Y0043974D01*
+X0087503Y0043966D01*
+X0087441Y0043954D01*
+X0087380Y0043939D01*
+X0087319Y0043920D01*
+X0087260Y0043897D01*
+X0087203Y0043870D01*
+X0087147Y0043840D01*
+X0087093Y0043807D01*
+X0087041Y0043770D01*
+X0086992Y0043731D01*
+X0086945Y0043688D01*
+X0086901Y0043643D01*
+X0086860Y0043594D01*
+X0086822Y0043544D01*
+X0086787Y0043491D01*
+X0086755Y0043436D01*
+X0086727Y0043380D01*
+X0086702Y0043321D01*
+X0086681Y0043262D01*
+X0086664Y0043201D01*
+X0086651Y0043139D01*
+X0086641Y0043076D01*
+X0086635Y0043013D01*
+X0086633Y0042950D01*
+X0126281Y0050470D02*
+X0126281Y0051292D01*
+X0126281Y0050470D02*
+X0126283Y0050414D01*
+X0126289Y0050358D01*
+X0126298Y0050303D01*
+X0126311Y0050248D01*
+X0126328Y0050195D01*
+X0126349Y0050143D01*
+X0126373Y0050092D01*
+X0126401Y0050043D01*
+X0126431Y0049996D01*
+X0126465Y0049951D01*
+X0126502Y0049909D01*
+X0126542Y0049869D01*
+X0126584Y0049832D01*
+X0126629Y0049798D01*
+X0126676Y0049768D01*
+X0126725Y0049740D01*
+X0126776Y0049716D01*
+X0126828Y0049695D01*
+X0126881Y0049678D01*
+X0126936Y0049665D01*
+X0126991Y0049656D01*
+X0127047Y0049650D01*
+X0127103Y0049648D01*
+X0127103Y0049647D02*
+X0129158Y0049647D01*
+X0129158Y0049648D02*
+X0129214Y0049650D01*
+X0129270Y0049656D01*
+X0129325Y0049665D01*
+X0129380Y0049678D01*
+X0129433Y0049695D01*
+X0129485Y0049716D01*
+X0129536Y0049740D01*
+X0129585Y0049768D01*
+X0129632Y0049798D01*
+X0129677Y0049832D01*
+X0129719Y0049869D01*
+X0129759Y0049909D01*
+X0129796Y0049951D01*
+X0129830Y0049996D01*
+X0129860Y0050043D01*
+X0129888Y0050092D01*
+X0129912Y0050143D01*
+X0129933Y0050195D01*
+X0129950Y0050248D01*
+X0129963Y0050303D01*
+X0129972Y0050358D01*
+X0129978Y0050414D01*
+X0129980Y0050470D01*
+X0129981Y0050470D02*
+X0129981Y0051292D01*
+X0128336Y0054406D02*
+X0128380Y0054449D01*
+X0128427Y0054490D01*
+X0128476Y0054527D01*
+X0128527Y0054562D01*
+X0128581Y0054593D01*
+X0128636Y0054621D01*
+X0128693Y0054645D01*
+X0128751Y0054666D01*
+X0128811Y0054683D01*
+X0128871Y0054697D01*
+X0128932Y0054706D01*
+X0128994Y0054712D01*
+X0129056Y0054714D01*
+X0128336Y0054405D02*
+X0126281Y0052658D01*
+X0126281Y0054713D01*
+X0129158Y0052658D02*
+X0129222Y0052681D01*
+X0129285Y0052707D01*
+X0129346Y0052737D01*
+X0129405Y0052770D01*
+X0129462Y0052807D01*
+X0129517Y0052847D01*
+X0129569Y0052890D01*
+X0129619Y0052936D01*
+X0129667Y0052984D01*
+X0129711Y0053036D01*
+X0129753Y0053089D01*
+X0129791Y0053145D01*
+X0129826Y0053203D01*
+X0129858Y0053263D01*
+X0129886Y0053325D01*
+X0129911Y0053388D01*
+X0129932Y0053453D01*
+X0129949Y0053519D01*
+X0129963Y0053585D01*
+X0129972Y0053652D01*
+X0129978Y0053720D01*
+X0129980Y0053788D01*
+X0129981Y0053788D02*
+X0129979Y0053846D01*
+X0129974Y0053904D01*
+X0129965Y0053961D01*
+X0129952Y0054018D01*
+X0129936Y0054074D01*
+X0129916Y0054129D01*
+X0129893Y0054182D01*
+X0129867Y0054234D01*
+X0129837Y0054284D01*
+X0129804Y0054332D01*
+X0129769Y0054378D01*
+X0129730Y0054421D01*
+X0129689Y0054462D01*
+X0129646Y0054501D01*
+X0129600Y0054536D01*
+X0129552Y0054569D01*
+X0129502Y0054599D01*
+X0129450Y0054625D01*
+X0129397Y0054648D01*
+X0129342Y0054668D01*
+X0129286Y0054684D01*
+X0129229Y0054697D01*
+X0129172Y0054706D01*
+X0129114Y0054711D01*
+X0129056Y0054713D01*
+X0334284Y0076100D02*
+X0334284Y0076511D01*
+X0334286Y0076567D01*
+X0334292Y0076623D01*
+X0334301Y0076678D01*
+X0334314Y0076733D01*
+X0334331Y0076786D01*
+X0334352Y0076838D01*
+X0334376Y0076889D01*
+X0334404Y0076938D01*
+X0334434Y0076985D01*
+X0334468Y0077030D01*
+X0334505Y0077072D01*
+X0334545Y0077112D01*
+X0334587Y0077149D01*
+X0334632Y0077183D01*
+X0334679Y0077213D01*
+X0334728Y0077241D01*
+X0334779Y0077265D01*
+X0334831Y0077286D01*
+X0334884Y0077303D01*
+X0334939Y0077316D01*
+X0334994Y0077325D01*
+X0335050Y0077331D01*
+X0335106Y0077333D01*
+X0336339Y0077333D01*
+X0336339Y0078977D01*
+X0334284Y0078977D01*
+X0334284Y0076100D02*
+X0334286Y0076044D01*
+X0334292Y0075988D01*
+X0334301Y0075933D01*
+X0334314Y0075878D01*
+X0334331Y0075825D01*
+X0334352Y0075773D01*
+X0334376Y0075722D01*
+X0334404Y0075673D01*
+X0334434Y0075626D01*
+X0334468Y0075581D01*
+X0334505Y0075539D01*
+X0334545Y0075499D01*
+X0334587Y0075462D01*
+X0334632Y0075428D01*
+X0334679Y0075398D01*
+X0334728Y0075370D01*
+X0334779Y0075346D01*
+X0334831Y0075325D01*
+X0334884Y0075308D01*
+X0334939Y0075295D01*
+X0334994Y0075286D01*
+X0335050Y0075280D01*
+X0335106Y0075278D01*
+X0335106Y0075277D02*
+X0336339Y0075277D01*
+X0337884Y0075277D02*
+X0339939Y0075277D01*
+X0338911Y0075277D02*
+X0338911Y0078977D01*
+X0339939Y0078155D01*
+X0341305Y0078977D02*
+X0342127Y0078977D01*
+X0342183Y0078975D01*
+X0342239Y0078969D01*
+X0342294Y0078960D01*
+X0342349Y0078947D01*
+X0342402Y0078930D01*
+X0342454Y0078909D01*
+X0342505Y0078885D01*
+X0342554Y0078857D01*
+X0342601Y0078827D01*
+X0342646Y0078793D01*
+X0342688Y0078756D01*
+X0342728Y0078716D01*
+X0342765Y0078674D01*
+X0342799Y0078629D01*
+X0342829Y0078582D01*
+X0342857Y0078533D01*
+X0342881Y0078482D01*
+X0342902Y0078430D01*
+X0342919Y0078377D01*
+X0342932Y0078322D01*
+X0342941Y0078267D01*
+X0342947Y0078211D01*
+X0342949Y0078155D01*
+X0342949Y0076100D01*
+X0342947Y0076044D01*
+X0342941Y0075988D01*
+X0342932Y0075933D01*
+X0342919Y0075878D01*
+X0342902Y0075825D01*
+X0342881Y0075773D01*
+X0342857Y0075722D01*
+X0342829Y0075673D01*
+X0342799Y0075626D01*
+X0342765Y0075581D01*
+X0342728Y0075539D01*
+X0342688Y0075499D01*
+X0342646Y0075462D01*
+X0342601Y0075428D01*
+X0342554Y0075398D01*
+X0342505Y0075370D01*
+X0342454Y0075346D01*
+X0342402Y0075325D01*
+X0342349Y0075308D01*
+X0342294Y0075295D01*
+X0342239Y0075286D01*
+X0342183Y0075280D01*
+X0342127Y0075278D01*
+X0342127Y0075277D02*
+X0341305Y0075277D01*
+X0351942Y0201880D02*
+X0353997Y0201880D01*
+X0354053Y0201882D01*
+X0354109Y0201888D01*
+X0354164Y0201897D01*
+X0354219Y0201910D01*
+X0354272Y0201927D01*
+X0354324Y0201948D01*
+X0354375Y0201972D01*
+X0354424Y0202000D01*
+X0354471Y0202030D01*
+X0354516Y0202064D01*
+X0354558Y0202101D01*
+X0354598Y0202141D01*
+X0354635Y0202183D01*
+X0354669Y0202228D01*
+X0354699Y0202275D01*
+X0354727Y0202324D01*
+X0354751Y0202375D01*
+X0354772Y0202427D01*
+X0354789Y0202480D01*
+X0354802Y0202535D01*
+X0354811Y0202590D01*
+X0354817Y0202646D01*
+X0354819Y0202702D01*
+X0354819Y0203525D01*
+X0354819Y0204890D02*
+X0354819Y0206946D01*
+X0353175Y0206124D02*
+X0353175Y0204890D01*
+X0354819Y0204890D01*
+X0353175Y0206124D02*
+X0353173Y0206180D01*
+X0353167Y0206236D01*
+X0353158Y0206291D01*
+X0353145Y0206346D01*
+X0353128Y0206399D01*
+X0353107Y0206451D01*
+X0353083Y0206502D01*
+X0353055Y0206551D01*
+X0353025Y0206598D01*
+X0352991Y0206643D01*
+X0352954Y0206685D01*
+X0352914Y0206725D01*
+X0352872Y0206762D01*
+X0352827Y0206796D01*
+X0352780Y0206826D01*
+X0352731Y0206854D01*
+X0352680Y0206878D01*
+X0352628Y0206899D01*
+X0352575Y0206916D01*
+X0352520Y0206929D01*
+X0352465Y0206938D01*
+X0352409Y0206944D01*
+X0352353Y0206946D01*
+X0351942Y0206946D01*
+X0351886Y0206944D01*
+X0351830Y0206938D01*
+X0351775Y0206929D01*
+X0351720Y0206916D01*
+X0351667Y0206899D01*
+X0351615Y0206878D01*
+X0351564Y0206854D01*
+X0351515Y0206826D01*
+X0351468Y0206796D01*
+X0351423Y0206762D01*
+X0351381Y0206725D01*
+X0351341Y0206685D01*
+X0351304Y0206643D01*
+X0351270Y0206598D01*
+X0351240Y0206551D01*
+X0351212Y0206502D01*
+X0351188Y0206451D01*
+X0351167Y0206399D01*
+X0351150Y0206346D01*
+X0351137Y0206291D01*
+X0351128Y0206236D01*
+X0351122Y0206180D01*
+X0351120Y0206124D01*
+X0351119Y0206124D02*
+X0351119Y0204890D01*
+X0351119Y0203525D02*
+X0351119Y0202702D01*
+X0351120Y0202702D02*
+X0351122Y0202646D01*
+X0351128Y0202590D01*
+X0351137Y0202535D01*
+X0351150Y0202480D01*
+X0351167Y0202427D01*
+X0351188Y0202375D01*
+X0351212Y0202324D01*
+X0351240Y0202275D01*
+X0351270Y0202228D01*
+X0351304Y0202183D01*
+X0351341Y0202141D01*
+X0351381Y0202101D01*
+X0351423Y0202064D01*
+X0351468Y0202030D01*
+X0351515Y0202000D01*
+X0351564Y0201972D01*
+X0351615Y0201948D01*
+X0351667Y0201927D01*
+X0351720Y0201910D01*
+X0351775Y0201897D01*
+X0351830Y0201888D01*
+X0351886Y0201882D01*
+X0351942Y0201880D01*
+D14*
+X0154300Y0260797D02*
+X0141800Y0260797D01*
+X0050550Y0057047D02*
+X0050550Y0049547D01*
+X0101800Y0024547D02*
+X0111800Y0024547D01*
+D15*
+X0111800Y0232047D02*
+X0111800Y0249547D01*
+D16*
+X0129250Y0193297D02*
+X0129250Y0173297D01*
+D17*
+X0098375Y0113415D02*
+X0090265Y0113415D01*
+X0090265Y0103179D02*
+X0098375Y0103179D01*
+D18*
+X0097164Y0108297D03*
+M02*
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.sol b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.sol
new file mode 100755
index 0000000..4efb3b2
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.sol
@@ -0,0 +1,5244 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+%ADD10C,0.05543*%
+%ADD11C,0.05937*%
+%ADD12C,0.23000*%
+%ADD13C,0.09000*%
+%ADD14C,0.10500*%
+%ADD15R,0.05118X0.06299*%
+%ADD16R,0.06299X0.05118*%
+%ADD17R,0.07874X0.05906*%
+%ADD18R,0.05906X0.07874*%
+%ADD19C,0.09000*%
+%ADD20R,0.06000X0.04724*%
+%ADD21R,0.07874X0.04724*%
+%ADD22R,0.07087X0.06500*%
+%ADD23R,0.07087X0.08465*%
+%ADD24R,0.08661X0.10236*%
+%ADD25R,0.11614X0.10630*%
+%ADD26R,0.05512X0.03937*%
+%ADD27OC8,0.05000*%
+%ADD28C,0.05000*%
+%ADD29R,0.08000X0.02600*%
+%ADD30C,0.05600*%
+%ADD31OC8,0.05600*%
+%ADD32R,0.07087X0.09449*%
+%ADD33C,0.01600*%
+%ADD34C,0.03569*%
+%ADD35C,0.05000*%
+%ADD36C,0.06000*%
+%ADD37C,0.02400*%
+%ADD38C,0.03200*%
+%ADD39C,0.02000*%
+%ADD40C,0.04356*%
+%ADD41C,0.00800*%
+%ADD42C,0.04000*%
+%ADD43C,0.10000*%
+%ADD44C,0.00600*%
+%ADD45C,0.07000*%
+%ADD46C,0.08000*%
+D10*
+X0104028Y0047047D02*
+X0109572Y0047047D01*
+X0109572Y0057047D02*
+X0104028Y0057047D01*
+X0104028Y0067047D02*
+X0109572Y0067047D01*
+X0109572Y0077047D02*
+X0104028Y0077047D01*
+X0104028Y0087047D02*
+X0109572Y0087047D01*
+X0109572Y0097047D02*
+X0104028Y0097047D01*
+X0184028Y0097047D02*
+X0189572Y0097047D01*
+X0189572Y0087047D02*
+X0184028Y0087047D01*
+X0184028Y0077047D02*
+X0189572Y0077047D01*
+X0189572Y0067047D02*
+X0184028Y0067047D01*
+X0184028Y0057047D02*
+X0189572Y0057047D01*
+X0189572Y0047047D02*
+X0184028Y0047047D01*
+X0210550Y0049547D02*
+X0216093Y0049547D01*
+X0216093Y0059547D02*
+X0210550Y0059547D01*
+X0210550Y0069547D02*
+X0216093Y0069547D01*
+X0216093Y0079547D02*
+X0210550Y0079547D01*
+X0210550Y0089547D02*
+X0216093Y0089547D01*
+X0216093Y0099547D02*
+X0210550Y0099547D01*
+X0210550Y0109547D02*
+X0216093Y0109547D01*
+X0216093Y0119547D02*
+X0210550Y0119547D01*
+X0210550Y0129547D02*
+X0216093Y0129547D01*
+X0216093Y0139547D02*
+X0210550Y0139547D01*
+X0210550Y0149547D02*
+X0216093Y0149547D01*
+X0216093Y0159547D02*
+X0210550Y0159547D01*
+X0210550Y0169547D02*
+X0216093Y0169547D01*
+X0216093Y0179547D02*
+X0210550Y0179547D01*
+X0210550Y0189547D02*
+X0216093Y0189547D01*
+X0225278Y0219547D02*
+X0230822Y0219547D01*
+X0265007Y0189547D02*
+X0270550Y0189547D01*
+X0270550Y0179547D02*
+X0265007Y0179547D01*
+X0265007Y0169547D02*
+X0270550Y0169547D01*
+X0270550Y0159547D02*
+X0265007Y0159547D01*
+X0265007Y0149547D02*
+X0270550Y0149547D01*
+X0270550Y0139547D02*
+X0265007Y0139547D01*
+X0265007Y0129547D02*
+X0270550Y0129547D01*
+X0270550Y0119547D02*
+X0265007Y0119547D01*
+X0265007Y0109547D02*
+X0270550Y0109547D01*
+X0270550Y0099547D02*
+X0265007Y0099547D01*
+X0265007Y0089547D02*
+X0270550Y0089547D01*
+X0270550Y0079547D02*
+X0265007Y0079547D01*
+X0265007Y0069547D02*
+X0270550Y0069547D01*
+X0270550Y0059547D02*
+X0265007Y0059547D01*
+X0265007Y0049547D02*
+X0270550Y0049547D01*
+D11*
+X0343089Y0163310D02*
+X0343089Y0169247D01*
+X0343089Y0177090D02*
+X0343089Y0183027D01*
+X0101800Y0266578D02*
+X0101800Y0272515D01*
+X0091800Y0272515D02*
+X0091800Y0266578D01*
+X0081800Y0266578D02*
+X0081800Y0272515D01*
+X0081828Y0210787D02*
+X0087765Y0210787D01*
+X0026772Y0210787D02*
+X0020835Y0210787D01*
+X0020835Y0055275D02*
+X0026772Y0055275D01*
+X0056800Y0025015D02*
+X0056800Y0019078D01*
+X0066800Y0019078D02*
+X0066800Y0025015D01*
+X0076800Y0025015D02*
+X0076800Y0019078D01*
+X0081828Y0055275D02*
+X0087765Y0055275D01*
+D12*
+X0031800Y0029547D03*
+X0170550Y0139547D03*
+X0031800Y0262047D03*
+X0345550Y0262047D03*
+X0345550Y0029547D03*
+D13*
+X0275550Y0255797D03*
+D14*
+X0265511Y0265836D03*
+X0285589Y0265836D03*
+X0285589Y0245758D03*
+X0265511Y0245758D03*
+D15*
+X0199290Y0179547D03*
+X0191810Y0179547D03*
+X0126790Y0147047D03*
+X0119310Y0147047D03*
+X0079290Y0198297D03*
+X0071810Y0198297D03*
+X0126810Y0268297D03*
+X0134290Y0268297D03*
+X0315560Y0061047D03*
+X0323040Y0061047D03*
+X0303040Y0057047D03*
+X0295560Y0057047D03*
+X0315560Y0026047D03*
+X0323040Y0026047D03*
+D16*
+X0286300Y0036307D03*
+X0286300Y0043787D03*
+X0249300Y0035787D03*
+X0249300Y0028307D03*
+X0354300Y0064557D03*
+X0354300Y0072037D03*
+X0255550Y0150807D03*
+X0255550Y0158287D03*
+X0241800Y0158287D03*
+X0241800Y0150807D03*
+X0226800Y0149537D03*
+X0226800Y0142057D03*
+X0253050Y0175807D03*
+X0253050Y0183287D03*
+X0170550Y0239557D03*
+X0170550Y0247037D03*
+X0065550Y0243307D03*
+X0065550Y0250787D03*
+D17*
+X0114300Y0257391D03*
+X0114300Y0269202D03*
+X0361800Y0211702D03*
+X0361800Y0199891D03*
+X0341800Y0069202D03*
+X0341800Y0057391D03*
+X0120550Y0057952D03*
+X0120550Y0046141D03*
+X0090550Y0035452D03*
+X0090550Y0023641D03*
+D18*
+X0067706Y0037047D03*
+X0055894Y0037047D03*
+X0054644Y0078297D03*
+X0066456Y0078297D03*
+X0127144Y0164547D03*
+X0138956Y0164547D03*
+X0092706Y0227047D03*
+X0080894Y0227047D03*
+X0084644Y0254547D03*
+X0096456Y0254547D03*
+X0225894Y0179547D03*
+X0237706Y0179547D03*
+D19*
+X0072050Y0227047D02*
+X0063050Y0227047D01*
+X0045550Y0227047D02*
+X0036550Y0227047D01*
+D20*
+X0054812Y0053297D03*
+D21*
+X0042538Y0053297D03*
+D22*
+X0106800Y0020649D03*
+D23*
+X0106800Y0034694D03*
+D24*
+X0148050Y0247204D03*
+X0148050Y0266889D03*
+D25*
+X0131337Y0240797D03*
+X0104763Y0240797D03*
+D26*
+X0266219Y0033287D03*
+X0266219Y0025807D03*
+X0274881Y0029547D03*
+D27*
+X0294300Y0035547D03*
+X0294300Y0044547D03*
+X0314300Y0044547D03*
+X0314300Y0035547D03*
+D28*
+X0304300Y0035547D03*
+X0304300Y0044547D03*
+X0324300Y0044547D03*
+X0324300Y0035547D03*
+D29*
+X0147650Y0175797D03*
+X0147650Y0180797D03*
+X0147650Y0185797D03*
+X0147650Y0190797D03*
+X0123450Y0190797D03*
+X0123450Y0185797D03*
+X0123450Y0180797D03*
+X0123450Y0175797D03*
+D30*
+X0196800Y0243297D03*
+D31*
+X0196800Y0253297D03*
+X0206800Y0253297D03*
+X0216800Y0253297D03*
+X0226800Y0253297D03*
+X0236800Y0253297D03*
+X0236800Y0243297D03*
+X0226800Y0243297D03*
+X0216800Y0243297D03*
+X0206800Y0243297D03*
+D32*
+X0102272Y0108297D03*
+X0086328Y0108297D03*
+D33*
+X0001800Y0015797D02*
+X0001800Y0277047D01*
+X0061800Y0277047D01*
+X0061800Y0260047D01*
+X0054456Y0260047D01*
+X0052434Y0259209D01*
+X0050887Y0257662D01*
+X0050050Y0255641D01*
+X0050050Y0243776D01*
+X0046800Y0240797D01*
+X0046800Y0233227D01*
+X0046250Y0233314D01*
+X0046250Y0227747D01*
+X0044850Y0227747D01*
+X0044850Y0233347D01*
+X0036054Y0233347D01*
+X0035075Y0233192D01*
+X0034132Y0232885D01*
+X0033248Y0232435D01*
+X0032446Y0231852D01*
+X0031745Y0231151D01*
+X0031162Y0230349D01*
+X0030712Y0229465D01*
+X0030405Y0228522D01*
+X0030282Y0227747D01*
+X0044850Y0227747D01*
+X0044850Y0226347D01*
+X0030282Y0226347D01*
+X0030405Y0225571D01*
+X0030712Y0224628D01*
+X0031162Y0223745D01*
+X0031745Y0222943D01*
+X0032446Y0222241D01*
+X0033248Y0221658D01*
+X0034132Y0221208D01*
+X0035075Y0220902D01*
+X0036054Y0220747D01*
+X0044850Y0220747D01*
+X0044850Y0226347D01*
+X0046250Y0226347D01*
+X0046250Y0220779D01*
+X0046800Y0220866D01*
+X0046800Y0218297D01*
+X0043050Y0213297D01*
+X0043050Y0180797D01*
+X0058050Y0165797D01*
+X0058050Y0083976D01*
+X0057834Y0084034D01*
+X0055321Y0084034D01*
+X0055321Y0078973D01*
+X0053968Y0078973D01*
+X0053968Y0077620D01*
+X0055321Y0077620D01*
+X0055321Y0072560D01*
+X0057834Y0072560D01*
+X0058050Y0072618D01*
+X0058050Y0072047D01*
+X0044300Y0062047D01*
+X0044300Y0057459D01*
+X0042919Y0057459D01*
+X0042919Y0053678D01*
+X0042157Y0053678D01*
+X0042157Y0057459D01*
+X0038364Y0057459D01*
+X0037906Y0057336D01*
+X0037496Y0057099D01*
+X0037161Y0056764D01*
+X0036924Y0056354D01*
+X0036801Y0055896D01*
+X0036801Y0053678D01*
+X0042157Y0053678D01*
+X0042157Y0052916D01*
+X0036801Y0052916D01*
+X0036801Y0050698D01*
+X0036924Y0050240D01*
+X0037161Y0049829D01*
+X0037496Y0049494D01*
+X0037906Y0049257D01*
+X0038364Y0049134D01*
+X0042157Y0049134D01*
+X0042157Y0052916D01*
+X0042919Y0052916D01*
+X0042919Y0049134D01*
+X0044412Y0049134D01*
+X0048050Y0035797D01*
+X0048050Y0015797D01*
+X0001800Y0015797D01*
+X0001800Y0016842D02*
+X0048050Y0016842D01*
+X0048050Y0018441D02*
+X0001800Y0018441D01*
+X0001800Y0020039D02*
+X0048050Y0020039D01*
+X0048050Y0021638D02*
+X0001800Y0021638D01*
+X0001800Y0023236D02*
+X0048050Y0023236D01*
+X0048050Y0024835D02*
+X0001800Y0024835D01*
+X0001800Y0026433D02*
+X0048050Y0026433D01*
+X0048050Y0028032D02*
+X0001800Y0028032D01*
+X0001800Y0029630D02*
+X0048050Y0029630D01*
+X0048050Y0031229D02*
+X0001800Y0031229D01*
+X0001800Y0032827D02*
+X0048050Y0032827D01*
+X0048050Y0034426D02*
+X0001800Y0034426D01*
+X0001800Y0036024D02*
+X0047988Y0036024D01*
+X0047552Y0037623D02*
+X0001800Y0037623D01*
+X0001800Y0039221D02*
+X0047116Y0039221D01*
+X0046680Y0040820D02*
+X0001800Y0040820D01*
+X0001800Y0042418D02*
+X0046244Y0042418D01*
+X0045808Y0044017D02*
+X0001800Y0044017D01*
+X0001800Y0045615D02*
+X0045372Y0045615D01*
+X0044936Y0047214D02*
+X0001800Y0047214D01*
+X0001800Y0048812D02*
+X0044500Y0048812D01*
+X0042919Y0050411D02*
+X0042157Y0050411D01*
+X0042157Y0052009D02*
+X0042919Y0052009D01*
+X0042157Y0053608D02*
+X0031245Y0053608D01*
+X0031192Y0053445D02*
+X0031424Y0054158D01*
+X0031541Y0054900D01*
+X0031541Y0055091D01*
+X0021020Y0055091D01*
+X0021020Y0055459D01*
+X0031541Y0055459D01*
+X0031541Y0055650D01*
+X0031424Y0056392D01*
+X0031192Y0057105D01*
+X0030851Y0057774D01*
+X0030410Y0058381D01*
+X0029879Y0058912D01*
+X0029272Y0059353D01*
+X0028603Y0059694D01*
+X0027889Y0059926D01*
+X0027148Y0060044D01*
+X0021020Y0060044D01*
+X0021020Y0055459D01*
+X0020651Y0055459D01*
+X0020651Y0055091D01*
+X0016067Y0055091D01*
+X0016067Y0054900D01*
+X0016184Y0054158D01*
+X0016416Y0053445D01*
+X0016757Y0052776D01*
+X0017198Y0052169D01*
+X0017729Y0051638D01*
+X0018336Y0051197D01*
+X0019005Y0050856D01*
+X0019719Y0050624D01*
+X0020460Y0050507D01*
+X0020651Y0050507D01*
+X0020651Y0055091D01*
+X0021020Y0055091D01*
+X0021020Y0050507D01*
+X0027148Y0050507D01*
+X0027889Y0050624D01*
+X0028603Y0050856D01*
+X0029272Y0051197D01*
+X0029879Y0051638D01*
+X0030410Y0052169D01*
+X0030851Y0052776D01*
+X0031192Y0053445D01*
+X0030251Y0052009D02*
+X0036801Y0052009D01*
+X0036878Y0050411D02*
+X0001800Y0050411D01*
+X0001800Y0052009D02*
+X0017357Y0052009D01*
+X0016363Y0053608D02*
+X0001800Y0053608D01*
+X0001800Y0055206D02*
+X0020651Y0055206D01*
+X0020651Y0055459D02*
+X0016067Y0055459D01*
+X0016067Y0055650D01*
+X0016184Y0056392D01*
+X0016416Y0057105D01*
+X0016757Y0057774D01*
+X0017198Y0058381D01*
+X0017729Y0058912D01*
+X0018336Y0059353D01*
+X0019005Y0059694D01*
+X0019719Y0059926D01*
+X0020460Y0060044D01*
+X0020651Y0060044D01*
+X0020651Y0055459D01*
+X0021020Y0055206D02*
+X0036801Y0055206D01*
+X0037202Y0056805D02*
+X0031289Y0056805D01*
+X0030388Y0058404D02*
+X0044300Y0058404D01*
+X0044300Y0060002D02*
+X0027410Y0060002D01*
+X0021020Y0060002D02*
+X0020651Y0060002D01*
+X0020198Y0060002D02*
+X0001800Y0060002D01*
+X0001800Y0058404D02*
+X0017220Y0058404D01*
+X0016319Y0056805D02*
+X0001800Y0056805D01*
+X0001800Y0061601D02*
+X0044300Y0061601D01*
+X0045884Y0063199D02*
+X0001800Y0063199D01*
+X0001800Y0064798D02*
+X0048082Y0064798D01*
+X0050280Y0066396D02*
+X0001800Y0066396D01*
+X0001800Y0067995D02*
+X0052478Y0067995D01*
+X0054676Y0069593D02*
+X0001800Y0069593D01*
+X0001800Y0071192D02*
+X0056874Y0071192D01*
+X0055321Y0072790D02*
+X0053968Y0072790D01*
+X0053968Y0072560D02*
+X0051455Y0072560D01*
+X0050997Y0072682D01*
+X0050587Y0072919D01*
+X0050251Y0073254D01*
+X0050014Y0073665D01*
+X0049892Y0074123D01*
+X0049892Y0077620D01*
+X0053968Y0077620D01*
+X0053968Y0072560D01*
+X0053968Y0074389D02*
+X0055321Y0074389D01*
+X0055321Y0075987D02*
+X0053968Y0075987D01*
+X0053968Y0077586D02*
+X0055321Y0077586D01*
+X0055321Y0079184D02*
+X0053968Y0079184D01*
+X0053968Y0078973D02*
+X0053968Y0084034D01*
+X0051455Y0084034D01*
+X0050997Y0083911D01*
+X0050587Y0083674D01*
+X0050251Y0083339D01*
+X0050014Y0082928D01*
+X0049892Y0082471D01*
+X0049892Y0078973D01*
+X0053968Y0078973D01*
+X0053968Y0080783D02*
+X0055321Y0080783D01*
+X0055321Y0082381D02*
+X0053968Y0082381D01*
+X0053968Y0083980D02*
+X0055321Y0083980D01*
+X0058036Y0083980D02*
+X0058050Y0083980D01*
+X0058050Y0085578D02*
+X0001800Y0085578D01*
+X0001800Y0083980D02*
+X0051253Y0083980D01*
+X0049892Y0082381D02*
+X0001800Y0082381D01*
+X0001800Y0080783D02*
+X0049892Y0080783D01*
+X0049892Y0079184D02*
+X0001800Y0079184D01*
+X0001800Y0077586D02*
+X0049892Y0077586D01*
+X0049892Y0075987D02*
+X0001800Y0075987D01*
+X0001800Y0074389D02*
+X0049892Y0074389D01*
+X0050810Y0072790D02*
+X0001800Y0072790D01*
+X0001800Y0087177D02*
+X0058050Y0087177D01*
+X0058050Y0088775D02*
+X0001800Y0088775D01*
+X0001800Y0090374D02*
+X0058050Y0090374D01*
+X0058050Y0091972D02*
+X0001800Y0091972D01*
+X0001800Y0093571D02*
+X0058050Y0093571D01*
+X0058050Y0095169D02*
+X0001800Y0095169D01*
+X0001800Y0096768D02*
+X0058050Y0096768D01*
+X0058050Y0098366D02*
+X0001800Y0098366D01*
+X0001800Y0099965D02*
+X0058050Y0099965D01*
+X0058050Y0101563D02*
+X0001800Y0101563D01*
+X0001800Y0103162D02*
+X0058050Y0103162D01*
+X0058050Y0104760D02*
+X0001800Y0104760D01*
+X0001800Y0106359D02*
+X0058050Y0106359D01*
+X0058050Y0107957D02*
+X0001800Y0107957D01*
+X0001800Y0109556D02*
+X0058050Y0109556D01*
+X0058050Y0111154D02*
+X0001800Y0111154D01*
+X0001800Y0112753D02*
+X0058050Y0112753D01*
+X0058050Y0114351D02*
+X0001800Y0114351D01*
+X0001800Y0115950D02*
+X0058050Y0115950D01*
+X0058050Y0117548D02*
+X0001800Y0117548D01*
+X0001800Y0119147D02*
+X0058050Y0119147D01*
+X0058050Y0120745D02*
+X0001800Y0120745D01*
+X0001800Y0122344D02*
+X0058050Y0122344D01*
+X0058050Y0123942D02*
+X0001800Y0123942D01*
+X0001800Y0125541D02*
+X0058050Y0125541D01*
+X0058050Y0127140D02*
+X0001800Y0127140D01*
+X0001800Y0128738D02*
+X0058050Y0128738D01*
+X0058050Y0130337D02*
+X0001800Y0130337D01*
+X0001800Y0131935D02*
+X0058050Y0131935D01*
+X0058050Y0133534D02*
+X0001800Y0133534D01*
+X0001800Y0135132D02*
+X0058050Y0135132D01*
+X0058050Y0136731D02*
+X0001800Y0136731D01*
+X0001800Y0138329D02*
+X0058050Y0138329D01*
+X0058050Y0139928D02*
+X0001800Y0139928D01*
+X0001800Y0141526D02*
+X0058050Y0141526D01*
+X0058050Y0143125D02*
+X0001800Y0143125D01*
+X0001800Y0144723D02*
+X0058050Y0144723D01*
+X0058050Y0146322D02*
+X0001800Y0146322D01*
+X0001800Y0147920D02*
+X0058050Y0147920D01*
+X0058050Y0149519D02*
+X0001800Y0149519D01*
+X0001800Y0151117D02*
+X0058050Y0151117D01*
+X0058050Y0152716D02*
+X0001800Y0152716D01*
+X0001800Y0154314D02*
+X0058050Y0154314D01*
+X0058050Y0155913D02*
+X0001800Y0155913D01*
+X0001800Y0157511D02*
+X0058050Y0157511D01*
+X0058050Y0159110D02*
+X0001800Y0159110D01*
+X0001800Y0160708D02*
+X0058050Y0160708D01*
+X0058050Y0162307D02*
+X0001800Y0162307D01*
+X0001800Y0163905D02*
+X0058050Y0163905D01*
+X0058050Y0165504D02*
+X0001800Y0165504D01*
+X0001800Y0167102D02*
+X0056744Y0167102D01*
+X0055146Y0168701D02*
+X0001800Y0168701D01*
+X0001800Y0170299D02*
+X0053547Y0170299D01*
+X0051949Y0171898D02*
+X0001800Y0171898D01*
+X0001800Y0173496D02*
+X0050350Y0173496D01*
+X0048752Y0175095D02*
+X0001800Y0175095D01*
+X0001800Y0176693D02*
+X0047153Y0176693D01*
+X0045555Y0178292D02*
+X0001800Y0178292D01*
+X0001800Y0179890D02*
+X0043956Y0179890D01*
+X0043050Y0181489D02*
+X0001800Y0181489D01*
+X0001800Y0183087D02*
+X0043050Y0183087D01*
+X0043050Y0184686D02*
+X0001800Y0184686D01*
+X0001800Y0186284D02*
+X0043050Y0186284D01*
+X0043050Y0187883D02*
+X0001800Y0187883D01*
+X0001800Y0189481D02*
+X0043050Y0189481D01*
+X0043050Y0191080D02*
+X0001800Y0191080D01*
+X0001800Y0192678D02*
+X0043050Y0192678D01*
+X0043050Y0194277D02*
+X0001800Y0194277D01*
+X0001800Y0195875D02*
+X0043050Y0195875D01*
+X0043050Y0197474D02*
+X0001800Y0197474D01*
+X0001800Y0199073D02*
+X0043050Y0199073D01*
+X0043050Y0200671D02*
+X0001800Y0200671D01*
+X0001800Y0202270D02*
+X0043050Y0202270D01*
+X0043050Y0203868D02*
+X0001800Y0203868D01*
+X0001800Y0205467D02*
+X0043050Y0205467D01*
+X0043050Y0207065D02*
+X0029763Y0207065D01*
+X0029879Y0207150D02*
+X0030410Y0207680D01*
+X0030851Y0208288D01*
+X0031192Y0208956D01*
+X0031424Y0209670D01*
+X0031541Y0210412D01*
+X0031541Y0210603D01*
+X0021020Y0210603D01*
+X0021020Y0210971D01*
+X0031541Y0210971D01*
+X0031541Y0211162D01*
+X0031424Y0211903D01*
+X0031192Y0212617D01*
+X0030851Y0213286D01*
+X0030410Y0213893D01*
+X0029879Y0214424D01*
+X0029272Y0214865D01*
+X0028603Y0215206D01*
+X0027889Y0215438D01*
+X0027148Y0215555D01*
+X0021020Y0215555D01*
+X0021020Y0210971D01*
+X0020651Y0210971D01*
+X0020651Y0210603D01*
+X0016067Y0210603D01*
+X0016067Y0210412D01*
+X0016184Y0209670D01*
+X0016416Y0208956D01*
+X0016757Y0208288D01*
+X0017198Y0207680D01*
+X0017729Y0207150D01*
+X0018336Y0206708D01*
+X0019005Y0206368D01*
+X0019719Y0206136D01*
+X0020460Y0206018D01*
+X0020651Y0206018D01*
+X0020651Y0210603D01*
+X0021020Y0210603D01*
+X0021020Y0206018D01*
+X0027148Y0206018D01*
+X0027889Y0206136D01*
+X0028603Y0206368D01*
+X0029272Y0206708D01*
+X0029879Y0207150D01*
+X0031042Y0208664D02*
+X0043050Y0208664D01*
+X0043050Y0210262D02*
+X0031517Y0210262D01*
+X0031430Y0211861D02*
+X0043050Y0211861D01*
+X0043172Y0213459D02*
+X0030725Y0213459D01*
+X0028894Y0215058D02*
+X0044371Y0215058D01*
+X0045570Y0216656D02*
+X0001800Y0216656D01*
+X0001800Y0215058D02*
+X0018714Y0215058D01*
+X0019005Y0215206D02*
+X0018336Y0214865D01*
+X0017729Y0214424D01*
+X0017198Y0213893D01*
+X0016757Y0213286D01*
+X0016416Y0212617D01*
+X0016184Y0211903D01*
+X0016067Y0211162D01*
+X0016067Y0210971D01*
+X0020651Y0210971D01*
+X0020651Y0215555D01*
+X0020460Y0215555D01*
+X0019719Y0215438D01*
+X0019005Y0215206D01*
+X0020651Y0215058D02*
+X0021020Y0215058D01*
+X0021020Y0213459D02*
+X0020651Y0213459D01*
+X0020651Y0211861D02*
+X0021020Y0211861D01*
+X0021020Y0210262D02*
+X0020651Y0210262D01*
+X0020651Y0208664D02*
+X0021020Y0208664D01*
+X0021020Y0207065D02*
+X0020651Y0207065D01*
+X0017845Y0207065D02*
+X0001800Y0207065D01*
+X0001800Y0208664D02*
+X0016565Y0208664D01*
+X0016091Y0210262D02*
+X0001800Y0210262D01*
+X0001800Y0211861D02*
+X0016178Y0211861D01*
+X0016883Y0213459D02*
+X0001800Y0213459D01*
+X0001800Y0218255D02*
+X0046768Y0218255D01*
+X0046800Y0219853D02*
+X0001800Y0219853D01*
+X0001800Y0221452D02*
+X0033654Y0221452D01*
+X0031666Y0223050D02*
+X0001800Y0223050D01*
+X0001800Y0224649D02*
+X0030705Y0224649D01*
+X0030298Y0226247D02*
+X0001800Y0226247D01*
+X0001800Y0227846D02*
+X0030298Y0227846D01*
+X0030705Y0229444D02*
+X0001800Y0229444D01*
+X0001800Y0231043D02*
+X0031666Y0231043D01*
+X0033653Y0232641D02*
+X0001800Y0232641D01*
+X0001800Y0234240D02*
+X0046800Y0234240D01*
+X0046800Y0235838D02*
+X0001800Y0235838D01*
+X0001800Y0237437D02*
+X0046800Y0237437D01*
+X0046800Y0239035D02*
+X0001800Y0239035D01*
+X0001800Y0240634D02*
+X0046800Y0240634D01*
+X0048366Y0242232D02*
+X0001800Y0242232D01*
+X0001800Y0243831D02*
+X0050050Y0243831D01*
+X0050050Y0245429D02*
+X0001800Y0245429D01*
+X0001800Y0247028D02*
+X0050050Y0247028D01*
+X0050050Y0248626D02*
+X0001800Y0248626D01*
+X0001800Y0250225D02*
+X0050050Y0250225D01*
+X0050050Y0251823D02*
+X0001800Y0251823D01*
+X0001800Y0253422D02*
+X0050050Y0253422D01*
+X0050050Y0255020D02*
+X0001800Y0255020D01*
+X0001800Y0256619D02*
+X0050455Y0256619D01*
+X0051443Y0258217D02*
+X0001800Y0258217D01*
+X0001800Y0259816D02*
+X0053899Y0259816D01*
+X0061800Y0261414D02*
+X0001800Y0261414D01*
+X0001800Y0263013D02*
+X0061800Y0263013D01*
+X0061800Y0264611D02*
+X0001800Y0264611D01*
+X0001800Y0266210D02*
+X0061800Y0266210D01*
+X0061800Y0267809D02*
+X0001800Y0267809D01*
+X0001800Y0269407D02*
+X0061800Y0269407D01*
+X0061800Y0271006D02*
+X0001800Y0271006D01*
+X0001800Y0272604D02*
+X0061800Y0272604D01*
+X0061800Y0274203D02*
+X0001800Y0274203D01*
+X0001800Y0275801D02*
+X0061800Y0275801D01*
+X0091643Y0269362D02*
+X0091984Y0269362D01*
+X0091984Y0261810D01*
+X0092175Y0261810D01*
+X0092917Y0261927D01*
+X0093630Y0262159D01*
+X0094299Y0262500D01*
+X0094906Y0262941D01*
+X0095437Y0263472D01*
+X0095878Y0264079D01*
+X0096033Y0264382D01*
+X0096571Y0263084D01*
+X0096800Y0262855D01*
+X0096800Y0257047D01*
+X0097132Y0257047D01*
+X0097132Y0255223D01*
+X0101208Y0255223D01*
+X0101208Y0257047D01*
+X0113624Y0257047D01*
+X0113624Y0256715D01*
+X0114976Y0256715D01*
+X0114976Y0252638D01*
+X0118474Y0252638D01*
+X0118932Y0252761D01*
+X0119342Y0252998D01*
+X0119677Y0253333D01*
+X0119914Y0253744D01*
+X0120037Y0254201D01*
+X0120037Y0256715D01*
+X0114976Y0256715D01*
+X0114976Y0257047D01*
+X0150550Y0257047D01*
+X0150550Y0254122D01*
+X0148850Y0254122D01*
+X0148850Y0248004D01*
+X0147250Y0248004D01*
+X0147250Y0246404D01*
+X0148850Y0246404D01*
+X0148850Y0240286D01*
+X0150550Y0240286D01*
+X0150550Y0230797D01*
+X0119300Y0225797D01*
+X0106800Y0215797D01*
+X0091478Y0215797D01*
+X0091259Y0216016D01*
+X0090560Y0216306D01*
+X0090662Y0221310D01*
+X0092029Y0221310D01*
+X0092029Y0226370D01*
+X0093382Y0226370D01*
+X0093382Y0221310D01*
+X0095895Y0221310D01*
+X0096353Y0221432D01*
+X0096763Y0221669D01*
+X0097099Y0222004D01*
+X0097336Y0222415D01*
+X0097458Y0222873D01*
+X0097458Y0226370D01*
+X0093382Y0226370D01*
+X0093382Y0227723D01*
+X0097458Y0227723D01*
+X0097458Y0231221D01*
+X0097336Y0231678D01*
+X0097099Y0232089D01*
+X0096763Y0232424D01*
+X0096353Y0232661D01*
+X0095895Y0232784D01*
+X0093382Y0232784D01*
+X0093382Y0227723D01*
+X0092029Y0227723D01*
+X0092029Y0232784D01*
+X0090897Y0232784D01*
+X0090959Y0235847D01*
+X0095857Y0234601D01*
+X0096243Y0233669D01*
+X0097143Y0232769D01*
+X0098319Y0232282D01*
+X0111206Y0232282D01*
+X0112382Y0232769D01*
+X0113283Y0233669D01*
+X0113770Y0234845D01*
+X0113770Y0246748D01*
+X0113283Y0247924D01*
+X0112382Y0248824D01*
+X0111206Y0249312D01*
+X0104551Y0249312D01*
+X0101155Y0250176D01*
+X0101208Y0250373D01*
+X0101208Y0253870D01*
+X0097132Y0253870D01*
+X0097132Y0255223D01*
+X0095779Y0255223D01*
+X0095779Y0260284D01*
+X0093266Y0260284D01*
+X0092808Y0260161D01*
+X0092398Y0259924D01*
+X0092062Y0259589D01*
+X0091825Y0259178D01*
+X0091737Y0258850D01*
+X0091596Y0259192D01*
+X0091439Y0259349D01*
+X0091489Y0261810D01*
+X0091616Y0261810D01*
+X0091616Y0268017D01*
+X0091643Y0269362D01*
+X0091616Y0267809D02*
+X0091984Y0267809D01*
+X0091984Y0266210D02*
+X0091616Y0266210D01*
+X0091616Y0264611D02*
+X0091984Y0264611D01*
+X0091984Y0263013D02*
+X0091616Y0263013D01*
+X0091481Y0261414D02*
+X0096800Y0261414D01*
+X0096800Y0259816D02*
+X0095779Y0259816D01*
+X0095779Y0258217D02*
+X0096800Y0258217D01*
+X0097132Y0256619D02*
+X0095779Y0256619D01*
+X0097132Y0255020D02*
+X0108563Y0255020D01*
+X0108563Y0254201D02*
+X0108563Y0256715D01*
+X0113624Y0256715D01*
+X0113624Y0252638D01*
+X0110126Y0252638D01*
+X0109668Y0252761D01*
+X0109258Y0252998D01*
+X0108923Y0253333D01*
+X0108686Y0253744D01*
+X0108563Y0254201D01*
+X0108871Y0253422D02*
+X0101208Y0253422D01*
+X0101208Y0251823D02*
+X0141919Y0251823D01*
+X0141919Y0252559D02*
+X0141919Y0248004D01*
+X0147250Y0248004D01*
+X0147250Y0254122D01*
+X0143482Y0254122D01*
+X0143025Y0254000D01*
+X0142614Y0253763D01*
+X0142279Y0253427D01*
+X0142042Y0253017D01*
+X0141919Y0252559D01*
+X0142276Y0253422D02*
+X0119729Y0253422D01*
+X0120037Y0255020D02*
+X0150550Y0255020D01*
+X0150550Y0256619D02*
+X0120037Y0256619D01*
+X0114976Y0256619D02*
+X0113624Y0256619D01*
+X0113624Y0255020D02*
+X0114976Y0255020D01*
+X0114976Y0253422D02*
+X0113624Y0253422D01*
+X0112580Y0248626D02*
+X0141919Y0248626D01*
+X0141919Y0250225D02*
+X0101169Y0250225D01*
+X0101208Y0256619D02*
+X0108563Y0256619D01*
+X0113654Y0247028D02*
+X0123981Y0247028D01*
+X0124090Y0247217D02*
+X0123853Y0246806D01*
+X0123730Y0246349D01*
+X0123730Y0241597D01*
+X0130537Y0241597D01*
+X0130537Y0239997D01*
+X0123730Y0239997D01*
+X0123730Y0235245D01*
+X0123853Y0234787D01*
+X0124090Y0234377D01*
+X0124425Y0234041D01*
+X0124836Y0233804D01*
+X0125293Y0233682D01*
+X0130537Y0233682D01*
+X0130537Y0239997D01*
+X0132137Y0239997D01*
+X0132137Y0233682D01*
+X0137381Y0233682D01*
+X0137839Y0233804D01*
+X0138250Y0234041D01*
+X0138585Y0234377D01*
+X0138822Y0234787D01*
+X0138944Y0235245D01*
+X0138944Y0239997D01*
+X0132137Y0239997D01*
+X0132137Y0241597D01*
+X0130537Y0241597D01*
+X0130537Y0247912D01*
+X0125293Y0247912D01*
+X0124836Y0247789D01*
+X0124425Y0247552D01*
+X0124090Y0247217D01*
+X0123730Y0245429D02*
+X0113770Y0245429D01*
+X0113770Y0243831D02*
+X0123730Y0243831D01*
+X0123730Y0242232D02*
+X0113770Y0242232D01*
+X0113770Y0240634D02*
+X0130537Y0240634D01*
+X0130537Y0242232D02*
+X0132137Y0242232D01*
+X0132137Y0241597D02*
+X0132137Y0247912D01*
+X0137381Y0247912D01*
+X0137839Y0247789D01*
+X0138250Y0247552D01*
+X0138585Y0247217D01*
+X0138822Y0246806D01*
+X0138944Y0246349D01*
+X0138944Y0241597D01*
+X0132137Y0241597D01*
+X0132137Y0240634D02*
+X0142635Y0240634D01*
+X0142614Y0240646D02*
+X0143025Y0240409D01*
+X0143482Y0240286D01*
+X0147250Y0240286D01*
+X0147250Y0246404D01*
+X0141919Y0246404D01*
+X0141919Y0241849D01*
+X0142042Y0241391D01*
+X0142279Y0240981D01*
+X0142614Y0240646D01*
+X0141919Y0242232D02*
+X0138944Y0242232D01*
+X0138944Y0243831D02*
+X0141919Y0243831D01*
+X0141919Y0245429D02*
+X0138944Y0245429D01*
+X0138694Y0247028D02*
+X0147250Y0247028D01*
+X0147250Y0248626D02*
+X0148850Y0248626D01*
+X0148850Y0250225D02*
+X0147250Y0250225D01*
+X0147250Y0251823D02*
+X0148850Y0251823D01*
+X0148850Y0253422D02*
+X0147250Y0253422D01*
+X0147250Y0245429D02*
+X0148850Y0245429D01*
+X0148850Y0243831D02*
+X0147250Y0243831D01*
+X0147250Y0242232D02*
+X0148850Y0242232D01*
+X0148850Y0240634D02*
+X0147250Y0240634D01*
+X0150550Y0239035D02*
+X0138944Y0239035D01*
+X0138944Y0237437D02*
+X0150550Y0237437D01*
+X0150550Y0235838D02*
+X0138944Y0235838D01*
+X0138448Y0234240D02*
+X0150550Y0234240D01*
+X0150550Y0232641D02*
+X0112074Y0232641D01*
+X0113519Y0234240D02*
+X0124227Y0234240D01*
+X0123730Y0235838D02*
+X0113770Y0235838D01*
+X0113770Y0237437D02*
+X0123730Y0237437D01*
+X0123730Y0239035D02*
+X0113770Y0239035D01*
+X0117865Y0224649D02*
+X0097458Y0224649D01*
+X0097458Y0226247D02*
+X0122116Y0226247D01*
+X0115867Y0223050D02*
+X0097458Y0223050D01*
+X0096387Y0221452D02*
+X0113869Y0221452D01*
+X0111871Y0219853D02*
+X0090633Y0219853D01*
+X0090600Y0218255D02*
+X0109872Y0218255D01*
+X0107874Y0216656D02*
+X0090568Y0216656D01*
+X0092029Y0221452D02*
+X0093382Y0221452D01*
+X0093382Y0223050D02*
+X0092029Y0223050D01*
+X0092029Y0224649D02*
+X0093382Y0224649D01*
+X0093382Y0226247D02*
+X0092029Y0226247D01*
+X0092029Y0227846D02*
+X0093382Y0227846D01*
+X0093382Y0229444D02*
+X0092029Y0229444D01*
+X0092029Y0231043D02*
+X0093382Y0231043D01*
+X0093382Y0232641D02*
+X0092029Y0232641D01*
+X0090926Y0234240D02*
+X0096006Y0234240D01*
+X0096387Y0232641D02*
+X0097451Y0232641D01*
+X0097458Y0231043D02*
+X0150550Y0231043D01*
+X0142097Y0229444D02*
+X0097458Y0229444D01*
+X0097458Y0227846D02*
+X0132106Y0227846D01*
+X0132137Y0234240D02*
+X0130537Y0234240D01*
+X0130537Y0235838D02*
+X0132137Y0235838D01*
+X0132137Y0237437D02*
+X0130537Y0237437D01*
+X0130537Y0239035D02*
+X0132137Y0239035D01*
+X0132137Y0243831D02*
+X0130537Y0243831D01*
+X0130537Y0245429D02*
+X0132137Y0245429D01*
+X0132137Y0247028D02*
+X0130537Y0247028D01*
+X0144457Y0267047D02*
+X0153050Y0267047D01*
+X0148050Y0266889D02*
+X0144457Y0267047D01*
+X0164300Y0267046D02*
+X0164369Y0266980D01*
+X0164441Y0266916D01*
+X0164516Y0266856D01*
+X0164592Y0266799D01*
+X0164672Y0266745D01*
+X0164753Y0266694D01*
+X0164836Y0266646D01*
+X0164922Y0266603D01*
+X0165008Y0266562D01*
+X0165097Y0266526D01*
+X0165187Y0266493D01*
+X0165278Y0266463D01*
+X0165371Y0266438D01*
+X0165464Y0266416D01*
+X0165558Y0266399D01*
+X0165653Y0266385D01*
+X0165749Y0266375D01*
+X0165844Y0266369D01*
+X0165940Y0266367D01*
+X0190550Y0248297D02*
+X0223050Y0248297D01*
+X0226800Y0253297D01*
+X0226800Y0243297D02*
+X0226800Y0235797D01*
+X0219300Y0225797D01*
+X0219300Y0207047D01*
+X0229300Y0198297D01*
+X0279300Y0198297D01*
+X0280550Y0197047D01*
+X0280550Y0172047D01*
+X0270550Y0169547D02*
+X0253050Y0169547D01*
+X0225550Y0169547D01*
+X0220550Y0174547D01*
+X0205550Y0174547D01*
+X0204300Y0173297D01*
+X0191800Y0173297D01*
+X0188050Y0169547D01*
+X0188050Y0153297D01*
+X0191800Y0149547D01*
+X0191800Y0133297D01*
+X0184300Y0124547D01*
+X0184300Y0104547D01*
+X0178050Y0100797D01*
+X0178050Y0090797D01*
+X0180550Y0087047D01*
+X0186800Y0087047D01*
+X0186800Y0077047D02*
+X0179300Y0077047D01*
+X0151800Y0109547D01*
+X0151800Y0149547D01*
+X0180550Y0173297D01*
+X0170550Y0173297D02*
+X0148050Y0152047D01*
+X0148050Y0104547D01*
+X0178050Y0067047D01*
+X0186800Y0067047D01*
+X0196800Y0062047D02*
+X0174300Y0062047D01*
+X0144300Y0099547D01*
+X0144300Y0154547D01*
+X0160550Y0173297D01*
+X0153050Y0184547D02*
+X0151800Y0185797D01*
+X0147650Y0185797D01*
+X0147650Y0190797D02*
+X0151800Y0190797D01*
+X0155550Y0188297D01*
+X0166800Y0188297D01*
+X0170550Y0190797D01*
+X0170550Y0189547D01*
+X0170550Y0190797D02*
+X0184300Y0190797D01*
+X0186800Y0189547D01*
+X0204300Y0189547D01*
+X0206800Y0195797D01*
+X0218050Y0195797D01*
+X0223050Y0190797D01*
+X0255550Y0190797D01*
+X0266800Y0179547D01*
+X0270550Y0179547D01*
+X0270550Y0189547D02*
+X0265550Y0194547D01*
+X0225550Y0194547D01*
+X0220550Y0199547D01*
+X0204300Y0199547D01*
+X0201800Y0193297D01*
+X0189300Y0193297D01*
+X0186800Y0194547D01*
+X0168050Y0194547D01*
+X0164300Y0192047D01*
+X0156800Y0192047D01*
+X0144300Y0207047D01*
+X0128050Y0207047D01*
+X0108050Y0187047D01*
+X0108050Y0180797D01*
+X0108050Y0124547D01*
+X0122361Y0117047D02*
+X0122489Y0117047D01*
+X0129300Y0125797D02*
+X0130550Y0125797D01*
+X0129300Y0125797D02*
+X0113050Y0142047D01*
+X0113050Y0147047D01*
+X0119310Y0147047D01*
+X0113050Y0147047D02*
+X0113050Y0170797D01*
+X0118050Y0175797D01*
+X0123450Y0175797D01*
+X0123450Y0180797D02*
+X0108050Y0180797D01*
+X0153050Y0184547D02*
+X0179300Y0184547D01*
+X0180550Y0186058D01*
+X0179300Y0184547D02*
+X0185550Y0184547D01*
+X0186800Y0185797D01*
+X0206800Y0185797D01*
+X0210550Y0189547D01*
+X0225894Y0184547D02*
+X0225894Y0179547D01*
+X0225894Y0184547D02*
+X0228394Y0187047D01*
+X0251800Y0187047D01*
+X0255550Y0183297D01*
+X0253050Y0183287D01*
+X0253050Y0175807D02*
+X0253050Y0169547D01*
+X0259300Y0164547D02*
+X0204300Y0164547D01*
+X0199300Y0169547D01*
+X0194300Y0169547D01*
+X0191800Y0167047D01*
+X0191800Y0157047D01*
+X0195550Y0153297D01*
+X0195550Y0130797D01*
+X0188050Y0122047D01*
+X0188050Y0098297D01*
+X0186800Y0097047D01*
+X0191800Y0103297D02*
+X0191800Y0119547D01*
+X0199300Y0128297D01*
+X0199300Y0157047D01*
+X0196800Y0159547D01*
+X0196800Y0164547D01*
+X0210550Y0159547D02*
+X0210552Y0159479D01*
+X0210557Y0159411D01*
+X0210567Y0159343D01*
+X0210579Y0159276D01*
+X0210596Y0159210D01*
+X0210616Y0159145D01*
+X0210639Y0159081D01*
+X0210666Y0159018D01*
+X0210697Y0158957D01*
+X0210730Y0158897D01*
+X0210767Y0158840D01*
+X0210807Y0158784D01*
+X0210850Y0158731D01*
+X0210895Y0158680D01*
+X0210943Y0158632D01*
+X0210994Y0158587D01*
+X0211047Y0158544D01*
+X0211103Y0158504D01*
+X0211160Y0158467D01*
+X0211220Y0158434D01*
+X0211281Y0158403D01*
+X0211344Y0158376D01*
+X0211408Y0158353D01*
+X0211473Y0158333D01*
+X0211539Y0158316D01*
+X0211606Y0158304D01*
+X0211674Y0158294D01*
+X0211742Y0158289D01*
+X0211810Y0158287D01*
+X0241800Y0158287D01*
+X0259300Y0164547D02*
+X0264300Y0159547D01*
+X0270550Y0159547D01*
+X0281800Y0155797D02*
+X0281800Y0149547D01*
+X0298050Y0133297D01*
+X0298050Y0089547D01*
+X0299300Y0089547D01*
+X0294300Y0087047D02*
+X0299300Y0082047D01*
+X0351800Y0082047D01*
+X0356800Y0087047D01*
+X0356800Y0105797D01*
+X0355550Y0107047D01*
+X0355550Y0118297D01*
+X0359300Y0122047D01*
+X0359300Y0129547D01*
+X0364300Y0134547D01*
+X0364300Y0143297D01*
+X0364300Y0128297D02*
+X0364300Y0120797D01*
+X0359300Y0115797D01*
+X0359300Y0109547D01*
+X0360550Y0108297D01*
+X0360550Y0084547D01*
+X0354300Y0078297D01*
+X0296800Y0078297D01*
+X0290550Y0084547D01*
+X0290550Y0130797D01*
+X0284300Y0137047D01*
+X0275550Y0137047D01*
+X0273050Y0134547D01*
+X0219300Y0134547D01*
+X0213050Y0139547D01*
+X0210550Y0139547D01*
+X0210550Y0129547D02*
+X0207425Y0129547D01*
+X0195550Y0117047D01*
+X0195550Y0105975D01*
+X0207737Y0094547D01*
+X0226800Y0094547D01*
+X0255550Y0074547D01*
+X0275550Y0074547D01*
+X0278050Y0072047D01*
+X0283050Y0072047D01*
+X0285550Y0074547D01*
+X0354300Y0074547D01*
+X0356800Y0074547D01*
+X0364300Y0082047D01*
+X0364300Y0112047D01*
+X0378050Y0082047D02*
+X0378050Y0014547D01*
+X0330550Y0014547D01*
+X0330550Y0063297D01*
+X0336369Y0061357D01*
+X0336186Y0061039D01*
+X0336063Y0060581D01*
+X0336063Y0058068D01*
+X0341124Y0058068D01*
+X0341124Y0056715D01*
+X0342476Y0056715D01*
+X0342476Y0052638D01*
+X0345974Y0052638D01*
+X0346432Y0052761D01*
+X0346842Y0052998D01*
+X0347177Y0053333D01*
+X0347414Y0053744D01*
+X0347537Y0054201D01*
+X0347537Y0056715D01*
+X0342476Y0056715D01*
+X0342476Y0058068D01*
+X0347537Y0058068D01*
+X0347537Y0058297D01*
+X0355550Y0058297D01*
+X0355550Y0058797D01*
+X0358086Y0058797D01*
+X0359262Y0059285D01*
+X0360162Y0060185D01*
+X0360650Y0061361D01*
+X0360650Y0067752D01*
+X0360424Y0068297D01*
+X0360650Y0068841D01*
+X0360650Y0072380D01*
+X0378050Y0082047D01*
+X0378050Y0080783D02*
+X0375775Y0080783D01*
+X0378050Y0079184D02*
+X0372897Y0079184D01*
+X0370020Y0077586D02*
+X0378050Y0077586D01*
+X0378050Y0075987D02*
+X0367143Y0075987D01*
+X0364265Y0074389D02*
+X0378050Y0074389D01*
+X0378050Y0072790D02*
+X0361388Y0072790D01*
+X0360650Y0071192D02*
+X0378050Y0071192D01*
+X0378050Y0069593D02*
+X0360650Y0069593D01*
+X0360549Y0067995D02*
+X0378050Y0067995D01*
+X0378050Y0066396D02*
+X0360650Y0066396D01*
+X0360650Y0064798D02*
+X0378050Y0064798D01*
+X0378050Y0063199D02*
+X0360650Y0063199D01*
+X0360650Y0061601D02*
+X0378050Y0061601D01*
+X0378050Y0060002D02*
+X0359980Y0060002D01*
+X0355550Y0058404D02*
+X0378050Y0058404D01*
+X0378050Y0056805D02*
+X0342476Y0056805D01*
+X0341124Y0056805D02*
+X0330550Y0056805D01*
+X0330550Y0055206D02*
+X0336063Y0055206D01*
+X0336063Y0054201D02*
+X0336063Y0056715D01*
+X0341124Y0056715D01*
+X0341124Y0052638D01*
+X0337626Y0052638D01*
+X0337168Y0052761D01*
+X0336758Y0052998D01*
+X0336423Y0053333D01*
+X0336186Y0053744D01*
+X0336063Y0054201D01*
+X0336264Y0053608D02*
+X0330550Y0053608D01*
+X0330550Y0052009D02*
+X0378050Y0052009D01*
+X0378050Y0050411D02*
+X0330550Y0050411D01*
+X0330550Y0048812D02*
+X0378050Y0048812D01*
+X0378050Y0047214D02*
+X0330550Y0047214D01*
+X0330550Y0045615D02*
+X0378050Y0045615D01*
+X0378050Y0044017D02*
+X0330550Y0044017D01*
+X0330550Y0042418D02*
+X0378050Y0042418D01*
+X0378050Y0040820D02*
+X0330550Y0040820D01*
+X0330550Y0039221D02*
+X0378050Y0039221D01*
+X0378050Y0037623D02*
+X0330550Y0037623D01*
+X0330550Y0036024D02*
+X0378050Y0036024D01*
+X0378050Y0034426D02*
+X0330550Y0034426D01*
+X0330550Y0032827D02*
+X0378050Y0032827D01*
+X0378050Y0031229D02*
+X0330550Y0031229D01*
+X0330550Y0029630D02*
+X0378050Y0029630D01*
+X0378050Y0028032D02*
+X0330550Y0028032D01*
+X0330550Y0026433D02*
+X0378050Y0026433D01*
+X0378050Y0024835D02*
+X0330550Y0024835D01*
+X0330550Y0023236D02*
+X0378050Y0023236D01*
+X0378050Y0021638D02*
+X0330550Y0021638D01*
+X0330550Y0020039D02*
+X0378050Y0020039D01*
+X0378050Y0018441D02*
+X0330550Y0018441D01*
+X0330550Y0016842D02*
+X0378050Y0016842D01*
+X0378050Y0015244D02*
+X0330550Y0015244D01*
+X0323040Y0026047D02*
+X0323040Y0034287D01*
+X0324300Y0035547D01*
+X0319300Y0032047D02*
+X0315550Y0028297D01*
+X0315550Y0026057D01*
+X0315560Y0026047D01*
+X0319300Y0032047D02*
+X0319300Y0050797D01*
+X0315560Y0054537D01*
+X0315560Y0061047D01*
+X0314550Y0061047D01*
+X0309300Y0068297D02*
+X0306800Y0070797D01*
+X0286800Y0070797D01*
+X0276800Y0060797D01*
+X0276800Y0045797D01*
+X0274300Y0043297D01*
+X0276800Y0038297D02*
+X0280550Y0043297D01*
+X0280550Y0059547D01*
+X0288050Y0067047D01*
+X0301800Y0067047D01*
+X0301800Y0065797D01*
+X0303040Y0057047D02*
+X0304300Y0055787D01*
+X0304300Y0044547D01*
+X0304300Y0035547D02*
+X0297050Y0028297D01*
+X0288050Y0028297D01*
+X0286300Y0030047D01*
+X0286300Y0036307D01*
+X0286300Y0043787D02*
+X0285550Y0044537D01*
+X0285550Y0054547D01*
+X0290550Y0062047D02*
+X0295550Y0057047D01*
+X0295560Y0057047D01*
+X0270550Y0059547D02*
+X0255550Y0059547D01*
+X0223050Y0084547D01*
+X0205550Y0084547D01*
+X0200550Y0094547D01*
+X0191800Y0103297D01*
+X0200550Y0112047D02*
+X0205550Y0104547D01*
+X0244300Y0104547D01*
+X0256800Y0099547D01*
+X0270550Y0099547D01*
+X0278050Y0094547D02*
+X0278050Y0109547D01*
+X0273050Y0114547D01*
+X0255550Y0114547D01*
+X0239300Y0119547D01*
+X0210550Y0119547D01*
+X0208050Y0124547D02*
+X0205550Y0122047D01*
+X0205550Y0114547D01*
+X0210550Y0109547D01*
+X0210550Y0099547D02*
+X0239300Y0099547D01*
+X0261800Y0084547D01*
+X0278050Y0084547D01*
+X0283050Y0089547D01*
+X0283050Y0112047D01*
+X0281800Y0113297D01*
+X0275550Y0124547D02*
+X0208050Y0124547D01*
+X0186800Y0135797D02*
+X0176800Y0125797D01*
+X0176800Y0114547D01*
+X0173050Y0110797D01*
+X0160550Y0110797D01*
+X0156800Y0114547D01*
+X0156800Y0145797D01*
+X0165550Y0153297D01*
+X0180550Y0153297D01*
+X0186800Y0147047D01*
+X0186800Y0135797D01*
+X0186800Y0136731D02*
+X0156800Y0136731D01*
+X0156800Y0138329D02*
+X0186800Y0138329D01*
+X0186800Y0139928D02*
+X0156800Y0139928D01*
+X0156800Y0141526D02*
+X0186800Y0141526D01*
+X0186800Y0143125D02*
+X0156800Y0143125D01*
+X0156800Y0144723D02*
+X0186800Y0144723D01*
+X0186800Y0146322D02*
+X0157412Y0146322D01*
+X0159277Y0147920D02*
+X0185927Y0147920D01*
+X0184328Y0149519D02*
+X0161142Y0149519D01*
+X0163007Y0151117D02*
+X0182730Y0151117D01*
+X0181131Y0152716D02*
+X0164872Y0152716D01*
+X0156800Y0135132D02*
+X0186135Y0135132D01*
+X0184537Y0133534D02*
+X0156800Y0133534D01*
+X0156800Y0131935D02*
+X0182938Y0131935D01*
+X0181340Y0130337D02*
+X0156800Y0130337D01*
+X0156800Y0128738D02*
+X0179741Y0128738D01*
+X0178143Y0127140D02*
+X0156800Y0127140D01*
+X0156800Y0125541D02*
+X0176800Y0125541D01*
+X0176800Y0123942D02*
+X0156800Y0123942D01*
+X0156800Y0122344D02*
+X0176800Y0122344D01*
+X0176800Y0120745D02*
+X0156800Y0120745D01*
+X0156800Y0119147D02*
+X0176800Y0119147D01*
+X0176800Y0117548D02*
+X0156800Y0117548D01*
+X0156800Y0115950D02*
+X0176800Y0115950D01*
+X0176605Y0114351D02*
+X0156995Y0114351D01*
+X0158594Y0112753D02*
+X0175006Y0112753D01*
+X0173408Y0111154D02*
+X0160192Y0111154D01*
+X0196800Y0062047D02*
+X0204300Y0054547D01*
+X0226800Y0054547D01*
+X0245550Y0049547D01*
+X0270550Y0049547D01*
+X0276800Y0038297D02*
+X0249310Y0038297D01*
+X0249300Y0035787D01*
+X0249300Y0028307D02*
+X0249300Y0025807D01*
+X0266219Y0025807D01*
+X0266219Y0033287D02*
+X0266209Y0033297D01*
+X0258050Y0033297D01*
+X0248050Y0021995D02*
+X0248050Y0017047D01*
+X0183050Y0017047D01*
+X0179300Y0020797D01*
+X0176800Y0020797D01*
+X0176800Y0047847D01*
+X0179526Y0047847D01*
+X0179457Y0047406D01*
+X0179457Y0047133D01*
+X0186714Y0047133D01*
+X0186714Y0046961D01*
+X0179457Y0046961D01*
+X0179457Y0046687D01*
+X0179569Y0045976D01*
+X0179792Y0045292D01*
+X0180118Y0044651D01*
+X0180541Y0044068D01*
+X0181050Y0043560D01*
+X0181632Y0043137D01*
+X0182273Y0042810D01*
+X0182958Y0042588D01*
+X0183669Y0042475D01*
+X0186714Y0042475D01*
+X0186714Y0046961D01*
+X0186886Y0046961D01*
+X0186886Y0047133D01*
+X0194143Y0047133D01*
+X0194143Y0047406D01*
+X0194132Y0047475D01*
+X0210150Y0034297D01*
+X0242950Y0029104D01*
+X0242950Y0025111D01*
+X0243438Y0023935D01*
+X0244338Y0023035D01*
+X0245514Y0022547D01*
+X0246902Y0022547D01*
+X0247034Y0022415D01*
+X0248050Y0021995D01*
+X0248050Y0021638D02*
+X0176800Y0021638D01*
+X0176800Y0023236D02*
+X0244136Y0023236D01*
+X0243065Y0024835D02*
+X0176800Y0024835D01*
+X0176800Y0026433D02*
+X0242950Y0026433D01*
+X0242950Y0028032D02*
+X0176800Y0028032D01*
+X0176800Y0029630D02*
+X0239626Y0029630D01*
+X0229529Y0031229D02*
+X0176800Y0031229D01*
+X0176800Y0032827D02*
+X0219431Y0032827D01*
+X0209993Y0034426D02*
+X0176800Y0034426D01*
+X0176800Y0036024D02*
+X0208050Y0036024D01*
+X0206107Y0037623D02*
+X0176800Y0037623D01*
+X0176800Y0039221D02*
+X0204164Y0039221D01*
+X0202221Y0040820D02*
+X0176800Y0040820D01*
+X0176800Y0042418D02*
+X0200278Y0042418D01*
+X0198335Y0044017D02*
+X0193007Y0044017D01*
+X0193059Y0044068D02*
+X0193482Y0044651D01*
+X0193808Y0045292D01*
+X0194031Y0045976D01*
+X0194143Y0046687D01*
+X0194143Y0046961D01*
+X0186886Y0046961D01*
+X0186886Y0042475D01*
+X0189931Y0042475D01*
+X0190642Y0042588D01*
+X0191327Y0042810D01*
+X0191968Y0043137D01*
+X0192550Y0043560D01*
+X0193059Y0044068D01*
+X0193914Y0045615D02*
+X0196392Y0045615D01*
+X0194449Y0047214D02*
+X0194143Y0047214D01*
+X0186886Y0045615D02*
+X0186714Y0045615D01*
+X0186714Y0044017D02*
+X0186886Y0044017D01*
+X0180593Y0044017D02*
+X0176800Y0044017D01*
+X0176800Y0045615D02*
+X0179686Y0045615D01*
+X0179457Y0047214D02*
+X0176800Y0047214D01*
+X0180057Y0020039D02*
+X0248050Y0020039D01*
+X0248050Y0018441D02*
+X0181656Y0018441D01*
+X0124300Y0032047D02*
+X0123050Y0030797D01*
+X0112143Y0030797D01*
+X0112143Y0033894D01*
+X0107600Y0033894D01*
+X0107600Y0035494D01*
+X0112143Y0035494D01*
+X0112143Y0039164D01*
+X0112021Y0039621D01*
+X0111784Y0040032D01*
+X0111449Y0040367D01*
+X0111038Y0040604D01*
+X0110580Y0040727D01*
+X0107600Y0040727D01*
+X0107600Y0035494D01*
+X0106000Y0035494D01*
+X0106000Y0033894D01*
+X0101457Y0033894D01*
+X0101457Y0030797D01*
+X0095087Y0030797D01*
+X0095182Y0030822D01*
+X0095592Y0031059D01*
+X0095927Y0031394D01*
+X0096164Y0031805D01*
+X0096287Y0032262D01*
+X0096287Y0034776D01*
+X0091226Y0034776D01*
+X0091226Y0036129D01*
+X0089874Y0036129D01*
+X0089874Y0040205D01*
+X0086376Y0040205D01*
+X0085918Y0040082D01*
+X0085508Y0039845D01*
+X0085173Y0039510D01*
+X0084936Y0039100D01*
+X0084813Y0038642D01*
+X0084813Y0036129D01*
+X0089874Y0036129D01*
+X0089874Y0034776D01*
+X0084813Y0034776D01*
+X0084813Y0032262D01*
+X0084936Y0031805D01*
+X0085173Y0031394D01*
+X0085508Y0031059D01*
+X0085918Y0030822D01*
+X0086013Y0030797D01*
+X0078961Y0030797D01*
+X0078027Y0031184D01*
+X0075573Y0031184D01*
+X0074639Y0030797D01*
+X0063050Y0030797D01*
+X0063050Y0032510D01*
+X0063075Y0032415D01*
+X0063312Y0032004D01*
+X0063648Y0031669D01*
+X0064058Y0031432D01*
+X0064516Y0031310D01*
+X0067029Y0031310D01*
+X0067029Y0036370D01*
+X0068382Y0036370D01*
+X0068382Y0031310D01*
+X0070895Y0031310D01*
+X0071353Y0031432D01*
+X0071763Y0031669D01*
+X0072099Y0032004D01*
+X0072336Y0032415D01*
+X0072458Y0032873D01*
+X0072458Y0036370D01*
+X0068382Y0036370D01*
+X0068382Y0037723D01*
+X0072458Y0037723D01*
+X0072458Y0040774D01*
+X0072824Y0040847D01*
+X0092713Y0040847D01*
+X0092904Y0040781D01*
+X0093940Y0040847D01*
+X0094978Y0040847D01*
+X0095164Y0040924D01*
+X0095365Y0040937D01*
+X0096297Y0041393D01*
+X0097256Y0041791D01*
+X0097399Y0041933D01*
+X0097580Y0042022D01*
+X0098267Y0042801D01*
+X0099001Y0043535D01*
+X0099078Y0043721D01*
+X0099211Y0043872D01*
+X0099547Y0044854D01*
+X0099764Y0045377D01*
+X0099792Y0045292D01*
+X0100118Y0044651D01*
+X0100541Y0044068D01*
+X0101050Y0043560D01*
+X0101632Y0043137D01*
+X0102273Y0042810D01*
+X0102958Y0042588D01*
+X0103669Y0042475D01*
+X0106714Y0042475D01*
+X0106714Y0046961D01*
+X0106886Y0046961D01*
+X0106886Y0047133D01*
+X0114143Y0047133D01*
+X0114143Y0047406D01*
+X0114031Y0048117D01*
+X0113808Y0048802D01*
+X0113482Y0049443D01*
+X0113059Y0050025D01*
+X0112550Y0050534D01*
+X0111968Y0050957D01*
+X0111327Y0051283D01*
+X0111291Y0051295D01*
+X0112954Y0051984D01*
+X0113017Y0052047D01*
+X0113050Y0052047D01*
+X0115432Y0050459D01*
+X0115173Y0050199D01*
+X0114936Y0049789D01*
+X0114813Y0049331D01*
+X0114813Y0046818D01*
+X0118316Y0046818D01*
+X0119068Y0045465D01*
+X0114813Y0045465D01*
+X0114813Y0042951D01*
+X0114936Y0042494D01*
+X0115173Y0042083D01*
+X0115508Y0041748D01*
+X0115918Y0041511D01*
+X0116376Y0041388D01*
+X0119874Y0041388D01*
+X0119874Y0044014D01*
+X0121226Y0041579D01*
+X0121226Y0041388D01*
+X0121332Y0041388D01*
+X0123050Y0038297D01*
+X0124612Y0035797D01*
+X0124300Y0032047D01*
+X0124365Y0032827D02*
+X0112143Y0032827D01*
+X0112143Y0031229D02*
+X0123482Y0031229D01*
+X0124498Y0034426D02*
+X0107600Y0034426D01*
+X0107600Y0036024D02*
+X0106000Y0036024D01*
+X0106000Y0035494D02*
+X0106000Y0040727D01*
+X0103020Y0040727D01*
+X0102562Y0040604D01*
+X0102151Y0040367D01*
+X0101816Y0040032D01*
+X0101579Y0039621D01*
+X0101457Y0039164D01*
+X0101457Y0035494D01*
+X0106000Y0035494D01*
+X0106000Y0034426D02*
+X0096287Y0034426D01*
+X0096287Y0032827D02*
+X0101457Y0032827D01*
+X0101457Y0031229D02*
+X0095762Y0031229D01*
+X0096287Y0036129D02*
+X0091226Y0036129D01*
+X0091226Y0040205D01*
+X0094724Y0040205D01*
+X0095182Y0040082D01*
+X0095592Y0039845D01*
+X0095927Y0039510D01*
+X0096164Y0039100D01*
+X0096287Y0038642D01*
+X0096287Y0036129D01*
+X0096287Y0037623D02*
+X0101457Y0037623D01*
+X0101472Y0039221D02*
+X0096094Y0039221D01*
+X0093515Y0040820D02*
+X0121648Y0040820D01*
+X0120760Y0042418D02*
+X0119874Y0042418D01*
+X0118984Y0045615D02*
+X0113914Y0045615D01*
+X0113808Y0045292D02*
+X0114031Y0045976D01*
+X0114143Y0046687D01*
+X0114143Y0046961D01*
+X0106886Y0046961D01*
+X0106886Y0042475D01*
+X0109931Y0042475D01*
+X0110642Y0042588D01*
+X0111327Y0042810D01*
+X0111968Y0043137D01*
+X0112550Y0043560D01*
+X0113059Y0044068D01*
+X0113482Y0044651D01*
+X0113808Y0045292D01*
+X0113007Y0044017D02*
+X0114813Y0044017D01*
+X0114979Y0042418D02*
+X0097930Y0042418D01*
+X0099261Y0044017D02*
+X0100593Y0044017D01*
+X0106714Y0044017D02*
+X0106886Y0044017D01*
+X0106886Y0045615D02*
+X0106714Y0045615D01*
+X0112673Y0050411D02*
+X0115384Y0050411D01*
+X0114813Y0048812D02*
+X0113803Y0048812D01*
+X0114143Y0047214D02*
+X0114813Y0047214D01*
+X0113106Y0052009D02*
+X0112980Y0052009D01*
+X0120550Y0057952D02*
+X0120894Y0058297D01*
+X0122536Y0039221D02*
+X0112128Y0039221D01*
+X0112143Y0037623D02*
+X0123471Y0037623D01*
+X0124470Y0036024D02*
+X0112143Y0036024D01*
+X0107600Y0037623D02*
+X0106000Y0037623D01*
+X0106000Y0039221D02*
+X0107600Y0039221D01*
+X0101457Y0036024D02*
+X0091226Y0036024D01*
+X0089874Y0036024D02*
+X0072458Y0036024D01*
+X0072458Y0034426D02*
+X0084813Y0034426D01*
+X0084813Y0032827D02*
+X0072446Y0032827D01*
+X0068382Y0032827D02*
+X0067029Y0032827D01*
+X0067029Y0034426D02*
+X0068382Y0034426D01*
+X0068382Y0036024D02*
+X0067029Y0036024D01*
+X0067029Y0037723D02*
+X0067029Y0042784D01*
+X0064516Y0042784D01*
+X0064058Y0042661D01*
+X0063648Y0042424D01*
+X0063312Y0042089D01*
+X0063075Y0041678D01*
+X0063050Y0041584D01*
+X0063050Y0043297D01*
+X0067199Y0043297D01*
+X0067398Y0043097D01*
+X0067742Y0042581D01*
+X0068262Y0042233D01*
+X0068382Y0042113D01*
+X0068382Y0037723D01*
+X0067029Y0037723D01*
+X0068382Y0037623D02*
+X0084813Y0037623D01*
+X0085006Y0039221D02*
+X0072458Y0039221D01*
+X0072689Y0040820D02*
+X0092791Y0040820D01*
+X0091226Y0039221D02*
+X0089874Y0039221D01*
+X0089874Y0037623D02*
+X0091226Y0037623D01*
+X0085338Y0031229D02*
+X0063050Y0031229D01*
+X0067029Y0039221D02*
+X0068382Y0039221D01*
+X0068382Y0040820D02*
+X0067029Y0040820D01*
+X0067029Y0042418D02*
+X0067985Y0042418D01*
+X0063642Y0042418D02*
+X0063050Y0042418D01*
+X0042919Y0055206D02*
+X0042157Y0055206D01*
+X0042157Y0056805D02*
+X0042919Y0056805D01*
+X0021020Y0056805D02*
+X0020651Y0056805D01*
+X0020651Y0058404D02*
+X0021020Y0058404D01*
+X0021020Y0053608D02*
+X0020651Y0053608D01*
+X0020651Y0052009D02*
+X0021020Y0052009D01*
+X0160550Y0197047D02*
+X0206800Y0243297D01*
+X0216800Y0243297D02*
+X0216800Y0238297D01*
+X0196800Y0198297D01*
+X0259300Y0142047D02*
+X0261800Y0144547D01*
+X0282010Y0144547D01*
+X0294300Y0132257D01*
+X0294300Y0087047D01*
+X0286800Y0084547D02*
+X0280550Y0077047D01*
+X0286800Y0084547D02*
+X0286800Y0129547D01*
+X0282913Y0133434D01*
+X0276937Y0133434D01*
+X0273050Y0129547D01*
+X0270550Y0129547D01*
+X0275550Y0124547D02*
+X0280550Y0129547D01*
+X0259300Y0142047D02*
+X0235550Y0142047D01*
+X0226800Y0142057D01*
+X0323040Y0061047D02*
+X0324300Y0059787D01*
+X0324300Y0044547D01*
+X0314300Y0035547D02*
+X0303300Y0024547D01*
+X0284881Y0024547D01*
+X0274881Y0029547D01*
+X0323040Y0026047D02*
+X0324300Y0027307D01*
+X0341124Y0053608D02*
+X0342476Y0053608D01*
+X0342476Y0055206D02*
+X0341124Y0055206D01*
+X0336063Y0058404D02*
+X0330550Y0058404D01*
+X0330550Y0060002D02*
+X0336063Y0060002D01*
+X0335638Y0061601D02*
+X0330550Y0061601D01*
+X0330550Y0063199D02*
+X0330843Y0063199D01*
+X0341800Y0069202D02*
+X0343394Y0068297D01*
+X0346800Y0068297D01*
+X0350550Y0064547D01*
+X0354300Y0064557D01*
+X0347537Y0055206D02*
+X0378050Y0055206D01*
+X0378050Y0053608D02*
+X0347336Y0053608D01*
+X0299300Y0244508D02*
+X0303050Y0254547D01*
+X0096642Y0263013D02*
+X0094978Y0263013D01*
+X0092289Y0259816D02*
+X0091448Y0259816D01*
+X0090959Y0235838D02*
+X0090994Y0235838D01*
+X0046250Y0232641D02*
+X0044850Y0232641D01*
+X0044850Y0231043D02*
+X0046250Y0231043D01*
+X0046250Y0229444D02*
+X0044850Y0229444D01*
+X0044850Y0227846D02*
+X0046250Y0227846D01*
+X0046250Y0226247D02*
+X0044850Y0226247D01*
+X0044850Y0224649D02*
+X0046250Y0224649D01*
+X0046250Y0223050D02*
+X0044850Y0223050D01*
+X0044850Y0221452D02*
+X0046250Y0221452D01*
+D34*
+X0010550Y0173297D03*
+X0055550Y0164547D03*
+X0108050Y0124547D03*
+X0130550Y0125797D03*
+X0160550Y0173297D03*
+X0170550Y0173297D03*
+X0180550Y0173297D03*
+X0180550Y0186058D03*
+X0170550Y0189547D03*
+X0160550Y0197047D03*
+X0196800Y0198297D03*
+X0231800Y0204547D03*
+X0251800Y0204547D03*
+X0269300Y0212047D03*
+X0266800Y0223297D03*
+X0266800Y0233297D03*
+X0284300Y0233297D03*
+X0284300Y0222047D03*
+X0293050Y0220797D03*
+X0294300Y0213297D03*
+X0290550Y0205797D03*
+X0279300Y0205797D03*
+X0286800Y0190797D03*
+X0280550Y0172047D03*
+X0288050Y0158297D03*
+X0281800Y0155797D03*
+X0280550Y0129547D03*
+X0281800Y0113297D03*
+X0303050Y0122047D03*
+X0278050Y0094547D03*
+X0299300Y0089547D03*
+X0305550Y0092047D03*
+X0326800Y0089547D03*
+X0350550Y0089547D03*
+X0370550Y0094547D03*
+X0364300Y0112047D03*
+X0370550Y0125797D03*
+X0364300Y0128297D03*
+X0351800Y0125797D03*
+X0364300Y0143297D03*
+X0368050Y0158297D03*
+X0368050Y0174547D03*
+X0350550Y0233297D03*
+X0369300Y0238297D03*
+X0369300Y0272047D03*
+X0320550Y0240797D03*
+X0303050Y0254547D03*
+X0318050Y0264547D03*
+X0243050Y0232047D03*
+X0183050Y0257047D03*
+X0244300Y0179547D03*
+X0234300Y0153297D03*
+X0249300Y0147047D03*
+X0200550Y0112047D03*
+X0196800Y0164547D03*
+X0280550Y0077047D03*
+X0290550Y0062047D03*
+X0285550Y0054547D03*
+X0301800Y0065797D03*
+X0333050Y0059547D03*
+X0365550Y0067047D03*
+X0364300Y0019547D03*
+X0258050Y0033297D03*
+X0010550Y0099547D03*
+D35*
+X0014585Y0100797D02*
+X0014585Y0092047D01*
+X0023050Y0092047D01*
+X0037263Y0092047D01*
+X0042538Y0053297D01*
+X0053050Y0092834D01*
+X0053050Y0098297D01*
+X0053050Y0082391D01*
+X0053007Y0082289D01*
+X0052968Y0082185D01*
+X0052932Y0082080D01*
+X0052901Y0081973D01*
+X0052873Y0081866D01*
+X0052849Y0081758D01*
+X0052829Y0081649D01*
+X0052813Y0081539D01*
+X0052800Y0081429D01*
+X0052792Y0081318D01*
+X0052788Y0081207D01*
+X0052787Y0081096D01*
+X0052791Y0080986D01*
+X0052798Y0080875D01*
+X0052810Y0080765D01*
+X0052825Y0080655D01*
+X0052845Y0080546D01*
+X0052868Y0080437D01*
+X0052895Y0080329D01*
+X0052926Y0080223D01*
+X0052960Y0080118D01*
+X0052999Y0080014D01*
+X0053041Y0079911D01*
+X0053087Y0079810D01*
+X0053136Y0079711D01*
+X0053189Y0079613D01*
+X0053245Y0079517D01*
+X0053305Y0079424D01*
+X0053368Y0079333D01*
+X0053434Y0079244D01*
+X0053503Y0079157D01*
+X0053575Y0079073D01*
+X0053651Y0078991D01*
+X0053729Y0078913D01*
+X0053810Y0078837D01*
+X0053893Y0078764D01*
+X0053979Y0078694D01*
+X0054068Y0078627D01*
+X0054159Y0078564D01*
+X0054252Y0078503D01*
+X0054347Y0078446D01*
+X0054444Y0078393D01*
+X0054543Y0078343D01*
+X0054644Y0078297D01*
+X0053050Y0098297D02*
+X0026800Y0098297D01*
+X0026800Y0093297D01*
+X0026751Y0093204D01*
+X0026700Y0093114D01*
+X0026644Y0093025D01*
+X0026586Y0092938D01*
+X0026524Y0092854D01*
+X0026459Y0092772D01*
+X0026391Y0092693D01*
+X0026320Y0092616D01*
+X0026247Y0092542D01*
+X0026170Y0092470D01*
+X0026091Y0092402D01*
+X0026010Y0092336D01*
+X0025926Y0092274D01*
+X0025840Y0092215D01*
+X0025752Y0092159D01*
+X0025661Y0092106D01*
+X0025569Y0092057D01*
+X0025475Y0092011D01*
+X0025380Y0091969D01*
+X0025282Y0091930D01*
+X0025184Y0091895D01*
+X0025084Y0091864D01*
+X0024983Y0091837D01*
+X0024881Y0091813D01*
+X0024779Y0091793D01*
+X0024675Y0091777D01*
+X0024572Y0091765D01*
+X0024467Y0091757D01*
+X0024363Y0091753D01*
+X0024258Y0091752D01*
+X0024154Y0091756D01*
+X0024050Y0091763D01*
+X0023946Y0091775D01*
+X0023842Y0091790D01*
+X0023740Y0091809D01*
+X0023638Y0091832D01*
+X0023537Y0091858D01*
+X0023437Y0091889D01*
+X0023338Y0091923D01*
+X0023240Y0091961D01*
+X0023144Y0092002D01*
+X0023050Y0092047D01*
+X0026800Y0098297D02*
+X0017085Y0098297D01*
+X0016987Y0098299D01*
+X0016889Y0098305D01*
+X0016791Y0098314D01*
+X0016694Y0098328D01*
+X0016597Y0098345D01*
+X0016501Y0098366D01*
+X0016406Y0098391D01*
+X0016312Y0098419D01*
+X0016220Y0098452D01*
+X0016128Y0098487D01*
+X0016038Y0098527D01*
+X0015950Y0098569D01*
+X0015863Y0098616D01*
+X0015779Y0098665D01*
+X0015696Y0098718D01*
+X0015616Y0098774D01*
+X0015537Y0098834D01*
+X0015461Y0098896D01*
+X0015388Y0098961D01*
+X0015317Y0099029D01*
+X0015249Y0099100D01*
+X0015184Y0099173D01*
+X0015122Y0099249D01*
+X0015062Y0099328D01*
+X0015006Y0099408D01*
+X0014953Y0099491D01*
+X0014904Y0099575D01*
+X0014857Y0099662D01*
+X0014815Y0099750D01*
+X0014775Y0099840D01*
+X0014740Y0099932D01*
+X0014707Y0100024D01*
+X0014679Y0100118D01*
+X0014654Y0100213D01*
+X0014633Y0100309D01*
+X0014616Y0100406D01*
+X0014602Y0100503D01*
+X0014593Y0100601D01*
+X0014587Y0100699D01*
+X0014585Y0100797D01*
+X0014585Y0118297D01*
+X0026800Y0118297D01*
+X0026800Y0098297D01*
+X0014585Y0092047D02*
+X0020835Y0055275D01*
+X0023703Y0041648D01*
+X0023050Y0043494D01*
+X0023703Y0041648D02*
+X0031800Y0029547D01*
+X0055206Y0028641D02*
+X0056800Y0022047D01*
+X0055206Y0028641D02*
+X0055894Y0037047D01*
+X0066800Y0034547D02*
+X0067706Y0035452D01*
+X0068956Y0035452D01*
+X0067706Y0037047D01*
+X0068956Y0035452D02*
+X0090550Y0035452D01*
+X0114644Y0035452D01*
+X0116175Y0033922D01*
+X0117587Y0035334D01*
+X0121800Y0035334D01*
+X0104300Y0045334D01*
+X0106800Y0034694D01*
+X0113994Y0036102D01*
+X0120550Y0035797D01*
+X0106800Y0057047D02*
+X0106800Y0067047D01*
+X0103956Y0057952D02*
+X0103999Y0057874D01*
+X0104045Y0057797D01*
+X0104094Y0057722D01*
+X0104147Y0057649D01*
+X0104202Y0057579D01*
+X0104261Y0057511D01*
+X0104322Y0057446D01*
+X0104386Y0057383D01*
+X0104453Y0057323D01*
+X0104522Y0057266D01*
+X0104593Y0057212D01*
+X0104667Y0057161D01*
+X0104743Y0057113D01*
+X0104820Y0057069D01*
+X0104900Y0057027D01*
+X0104981Y0056990D01*
+X0105064Y0056955D01*
+X0105148Y0056925D01*
+X0105233Y0056897D01*
+X0105320Y0056874D01*
+X0105407Y0056854D01*
+X0105495Y0056838D01*
+X0105584Y0056825D01*
+X0105673Y0056817D01*
+X0105763Y0056812D01*
+X0105853Y0056811D01*
+X0105942Y0056814D01*
+X0106031Y0056821D01*
+X0106120Y0056831D01*
+X0106209Y0056845D01*
+X0106297Y0056863D01*
+X0106384Y0056885D01*
+X0106470Y0056910D01*
+X0106555Y0056939D01*
+X0106638Y0056971D01*
+X0106720Y0057007D01*
+X0106801Y0057047D01*
+X0103956Y0057952D02*
+X0120550Y0057952D01*
+X0096979Y0057047D02*
+X0094300Y0067047D01*
+X0094300Y0117047D01*
+X0122361Y0117047D01*
+X0138050Y0117047D01*
+X0138050Y0147047D01*
+X0138050Y0154547D01*
+X0139300Y0160797D01*
+X0139300Y0165452D01*
+X0138956Y0164547D01*
+X0142706Y0172102D01*
+X0147650Y0175797D01*
+X0149300Y0178297D01*
+X0155550Y0179547D01*
+X0191810Y0179547D01*
+X0199290Y0179547D02*
+X0210550Y0179547D01*
+X0225894Y0179547D01*
+X0237706Y0179547D02*
+X0244300Y0179547D01*
+X0231800Y0215797D02*
+X0243050Y0232047D01*
+X0228050Y0219547D02*
+X0228052Y0219427D01*
+X0228058Y0219307D01*
+X0228067Y0219187D01*
+X0228081Y0219067D01*
+X0228098Y0218949D01*
+X0228119Y0218830D01*
+X0228144Y0218713D01*
+X0228173Y0218596D01*
+X0228205Y0218480D01*
+X0228241Y0218365D01*
+X0228281Y0218252D01*
+X0228324Y0218140D01*
+X0228371Y0218029D01*
+X0228421Y0217920D01*
+X0228475Y0217812D01*
+X0228533Y0217707D01*
+X0228593Y0217603D01*
+X0228657Y0217501D01*
+X0228724Y0217402D01*
+X0228795Y0217304D01*
+X0228868Y0217209D01*
+X0228945Y0217116D01*
+X0229024Y0217026D01*
+X0229106Y0216938D01*
+X0229191Y0216853D01*
+X0229279Y0216771D01*
+X0229369Y0216692D01*
+X0229462Y0216615D01*
+X0229557Y0216542D01*
+X0229655Y0216471D01*
+X0229754Y0216404D01*
+X0229856Y0216340D01*
+X0229960Y0216280D01*
+X0230065Y0216222D01*
+X0230173Y0216168D01*
+X0230282Y0216118D01*
+X0230393Y0216071D01*
+X0230505Y0216028D01*
+X0230618Y0215988D01*
+X0230733Y0215952D01*
+X0230849Y0215920D01*
+X0230966Y0215891D01*
+X0231083Y0215866D01*
+X0231202Y0215845D01*
+X0231320Y0215828D01*
+X0231440Y0215814D01*
+X0231560Y0215805D01*
+X0231680Y0215799D01*
+X0231800Y0215797D01*
+X0265511Y0245758D02*
+X0285589Y0245758D01*
+X0285589Y0265836D01*
+X0265511Y0265836D01*
+X0285550Y0244508D02*
+X0284300Y0233297D01*
+X0296800Y0272047D02*
+X0326800Y0272047D01*
+X0326800Y0255797D01*
+X0336800Y0242047D01*
+X0358050Y0242047D01*
+X0363050Y0237047D01*
+X0364300Y0222047D01*
+X0364300Y0214202D01*
+X0361800Y0211702D01*
+X0361800Y0199891D02*
+X0361800Y0192047D01*
+X0360550Y0192047D01*
+X0364300Y0222047D02*
+X0364300Y0229547D01*
+X0184300Y0269547D02*
+X0181800Y0267047D01*
+X0170550Y0239557D02*
+X0170550Y0235797D01*
+X0153050Y0218297D01*
+X0123050Y0218297D01*
+X0090550Y0189547D01*
+X0071800Y0189547D01*
+X0071800Y0198287D01*
+X0071810Y0198297D01*
+X0071810Y0218287D01*
+X0063050Y0227047D01*
+X0065550Y0229547D01*
+X0065550Y0243307D01*
+X0065550Y0250787D02*
+X0065560Y0254547D01*
+X0081800Y0257391D02*
+X0081800Y0259547D01*
+X0081800Y0257391D02*
+X0084644Y0254547D01*
+X0096456Y0254547D02*
+X0095206Y0263742D01*
+X0095131Y0263816D01*
+X0092631Y0266215D01*
+X0091800Y0269547D01*
+X0096800Y0256141D01*
+X0102144Y0269202D02*
+X0101800Y0269547D01*
+X0114300Y0257391D02*
+X0118394Y0255797D01*
+X0133050Y0255797D01*
+X0126810Y0268297D02*
+X0125904Y0269202D01*
+X0130550Y0241141D02*
+X0131337Y0240797D01*
+X0114300Y0230797D01*
+X0105550Y0222047D01*
+X0100550Y0220797D01*
+X0101800Y0220797D01*
+X0087765Y0210787D02*
+X0079290Y0202312D01*
+X0079290Y0198297D01*
+X0054300Y0217047D02*
+X0054300Y0238297D01*
+X0055550Y0239547D01*
+X0045550Y0227047D02*
+X0026800Y0228297D01*
+X0026800Y0242047D01*
+X0014585Y0242047D01*
+X0014585Y0228297D01*
+X0026800Y0228297D01*
+X0027049Y0210782D01*
+X0020835Y0210787D01*
+X0014585Y0169547D01*
+X0026800Y0169547D01*
+X0026800Y0153297D01*
+X0014585Y0153297D01*
+X0014585Y0138297D01*
+X0018050Y0138297D01*
+X0026800Y0138297D01*
+X0026800Y0118297D01*
+X0014585Y0118297D02*
+X0014585Y0138297D01*
+X0026800Y0138297D02*
+X0026800Y0153297D01*
+X0014585Y0153297D02*
+X0014585Y0169547D01*
+X0026800Y0169547D02*
+X0026800Y0195334D01*
+X0020835Y0210787D02*
+X0014585Y0228297D01*
+X0014585Y0242047D02*
+X0014585Y0244832D01*
+X0031800Y0262047D01*
+X0040550Y0270797D01*
+X0080550Y0270797D02*
+X0081800Y0269547D01*
+X0130550Y0241141D02*
+X0138050Y0238297D01*
+X0146800Y0234547D01*
+X0131337Y0240797D01*
+X0265511Y0245758D02*
+X0265837Y0243694D01*
+X0266119Y0241624D01*
+X0266356Y0239548D01*
+X0266549Y0237468D01*
+X0266697Y0235384D01*
+X0266800Y0233297D01*
+X0096979Y0057047D02*
+X0096800Y0055975D01*
+X0066800Y0034547D02*
+X0066800Y0022047D01*
+X0055550Y0049547D02*
+X0055550Y0050944D01*
+X0186800Y0020797D02*
+X0190050Y0017547D01*
+X0333550Y0017547D01*
+X0345550Y0029547D01*
+D36*
+X0135550Y0030797D02*
+X0125402Y0020649D01*
+X0106800Y0020649D01*
+X0135550Y0030797D02*
+X0135550Y0062047D01*
+X0121800Y0075797D01*
+X0121800Y0099547D01*
+X0113050Y0108297D01*
+X0102272Y0108297D01*
+X0106800Y0057047D02*
+X0096979Y0057047D01*
+X0096800Y0055975D02*
+X0093744Y0047047D01*
+X0072217Y0047047D01*
+X0070550Y0049547D01*
+X0055550Y0049547D01*
+X0056800Y0022047D01*
+X0055550Y0050944D02*
+X0054812Y0053297D01*
+X0170550Y0247037D02*
+X0170550Y0267047D01*
+X0140402Y0267047D02*
+X0139152Y0268297D01*
+X0134290Y0268297D01*
+D37*
+X0183050Y0257047D02*
+X0198050Y0260797D01*
+X0263050Y0260797D01*
+X0190550Y0248297D02*
+X0183050Y0235797D01*
+X0158050Y0212047D01*
+X0126800Y0212047D01*
+X0103050Y0189547D01*
+X0094300Y0173297D01*
+X0094300Y0117047D01*
+X0126790Y0147047D02*
+X0138050Y0147047D01*
+X0133050Y0157047D02*
+X0118050Y0157047D01*
+X0118050Y0169547D01*
+X0120200Y0171697D01*
+X0128007Y0171697D01*
+X0129036Y0172123D01*
+X0129824Y0172911D01*
+X0130250Y0173940D01*
+X0130250Y0177654D01*
+X0129984Y0178297D01*
+X0130250Y0178940D01*
+X0130250Y0182654D01*
+X0129984Y0183297D01*
+X0130250Y0183940D01*
+X0130250Y0187654D01*
+X0129824Y0188683D01*
+X0129576Y0188931D01*
+X0129650Y0189207D01*
+X0129650Y0190797D01*
+X0129650Y0192386D01*
+X0129500Y0192946D01*
+X0129210Y0193448D01*
+X0128801Y0193857D01*
+X0128299Y0194147D01*
+X0127740Y0194297D01*
+X0123450Y0194297D01*
+X0120550Y0194297D01*
+X0120550Y0194456D01*
+X0129541Y0203447D01*
+X0142614Y0203447D01*
+X0143050Y0202923D01*
+X0143050Y0197047D01*
+X0139300Y0197047D01*
+X0139300Y0179547D01*
+X0134300Y0170797D01*
+X0134294Y0170735D01*
+X0133629Y0170070D01*
+X0133203Y0169041D01*
+X0133203Y0160053D01*
+X0133302Y0159814D01*
+X0133050Y0157047D01*
+X0133169Y0158356D02*
+X0118050Y0158356D01*
+X0118050Y0160754D02*
+X0121992Y0160754D01*
+X0121992Y0160320D02*
+X0122142Y0159761D01*
+X0122431Y0159259D01*
+X0122841Y0158849D01*
+X0123343Y0158560D01*
+X0123902Y0158410D01*
+X0126868Y0158410D01*
+X0126868Y0164270D01*
+X0127421Y0164270D01*
+X0127421Y0158410D01*
+X0130387Y0158410D01*
+X0130946Y0158560D01*
+X0131448Y0158849D01*
+X0131858Y0159259D01*
+X0132147Y0159761D01*
+X0132297Y0160320D01*
+X0132297Y0164270D01*
+X0127421Y0164270D01*
+X0127421Y0164823D01*
+X0132297Y0164823D01*
+X0132297Y0168773D01*
+X0132147Y0169333D01*
+X0131858Y0169835D01*
+X0131448Y0170244D01*
+X0130946Y0170534D01*
+X0130387Y0170684D01*
+X0127421Y0170684D01*
+X0127421Y0164823D01*
+X0126868Y0164823D01*
+X0126868Y0164270D01*
+X0121992Y0164270D01*
+X0121992Y0160320D01*
+X0121992Y0163153D02*
+X0118050Y0163153D01*
+X0118050Y0165551D02*
+X0121992Y0165551D01*
+X0121992Y0164823D02*
+X0126868Y0164823D01*
+X0126868Y0170684D01*
+X0123902Y0170684D01*
+X0123343Y0170534D01*
+X0122841Y0170244D01*
+X0122431Y0169835D01*
+X0122142Y0169333D01*
+X0121992Y0168773D01*
+X0121992Y0164823D01*
+X0121992Y0167950D02*
+X0118050Y0167950D01*
+X0118852Y0170348D02*
+X0123022Y0170348D01*
+X0126868Y0170348D02*
+X0127421Y0170348D01*
+X0127421Y0167950D02*
+X0126868Y0167950D01*
+X0126868Y0165551D02*
+X0127421Y0165551D01*
+X0127421Y0163153D02*
+X0126868Y0163153D01*
+X0126868Y0160754D02*
+X0127421Y0160754D01*
+X0132297Y0160754D02*
+X0133203Y0160754D01*
+X0133203Y0163153D02*
+X0132297Y0163153D01*
+X0132297Y0165551D02*
+X0133203Y0165551D01*
+X0133203Y0167950D02*
+X0132297Y0167950D01*
+X0131267Y0170348D02*
+X0133908Y0170348D01*
+X0135414Y0172747D02*
+X0129660Y0172747D01*
+X0130250Y0175145D02*
+X0136785Y0175145D01*
+X0138156Y0177544D02*
+X0130250Y0177544D01*
+X0130250Y0179942D02*
+X0139300Y0179942D01*
+X0139300Y0182341D02*
+X0130250Y0182341D01*
+X0130250Y0184740D02*
+X0139300Y0184740D01*
+X0139300Y0187138D02*
+X0130250Y0187138D01*
+X0129650Y0189537D02*
+X0139300Y0189537D01*
+X0139300Y0191935D02*
+X0129650Y0191935D01*
+X0129650Y0190797D02*
+X0129217Y0190797D01*
+X0129217Y0190797D01*
+X0129650Y0190797D01*
+X0123450Y0192047D02*
+X0123450Y0194297D01*
+X0123450Y0192047D01*
+X0123450Y0192047D01*
+X0120550Y0194334D02*
+X0139300Y0194334D01*
+X0139300Y0196732D02*
+X0122827Y0196732D01*
+X0125225Y0199131D02*
+X0143050Y0199131D01*
+X0143050Y0201529D02*
+X0127624Y0201529D01*
+X0147650Y0180797D02*
+X0147650Y0175797D01*
+X0210550Y0149547D02*
+X0214300Y0149547D01*
+X0223050Y0142047D01*
+X0226800Y0142057D01*
+X0138050Y0117047D02*
+X0138050Y0092047D01*
+X0169300Y0052047D01*
+X0309300Y0068297D02*
+X0315550Y0068297D01*
+D38*
+X0315552Y0068297D01*
+X0343394Y0068297D01*
+X0350550Y0089547D02*
+X0326800Y0089547D01*
+X0308050Y0089547D01*
+X0305550Y0092047D01*
+X0305550Y0094547D01*
+X0303050Y0097047D01*
+X0303050Y0122047D01*
+X0303050Y0142156D01*
+X0288050Y0157156D01*
+X0288050Y0158297D01*
+X0288050Y0170797D01*
+X0286800Y0172047D01*
+X0286800Y0190797D01*
+X0286800Y0205797D01*
+X0290550Y0205797D01*
+X0290644Y0205752D01*
+X0290740Y0205711D01*
+X0290838Y0205673D01*
+X0290937Y0205639D01*
+X0291037Y0205608D01*
+X0291138Y0205582D01*
+X0291240Y0205559D01*
+X0291342Y0205540D01*
+X0291446Y0205525D01*
+X0291550Y0205513D01*
+X0291654Y0205506D01*
+X0291758Y0205502D01*
+X0291863Y0205503D01*
+X0291967Y0205507D01*
+X0292072Y0205515D01*
+X0292175Y0205527D01*
+X0292279Y0205543D01*
+X0292381Y0205563D01*
+X0292483Y0205587D01*
+X0292584Y0205614D01*
+X0292684Y0205645D01*
+X0292782Y0205680D01*
+X0292880Y0205719D01*
+X0292975Y0205761D01*
+X0293069Y0205807D01*
+X0293161Y0205856D01*
+X0293252Y0205909D01*
+X0293340Y0205965D01*
+X0293426Y0206024D01*
+X0293510Y0206086D01*
+X0293591Y0206152D01*
+X0293670Y0206220D01*
+X0293747Y0206292D01*
+X0293820Y0206366D01*
+X0293891Y0206443D01*
+X0293959Y0206522D01*
+X0294024Y0206604D01*
+X0294086Y0206688D01*
+X0294144Y0206775D01*
+X0294200Y0206864D01*
+X0294251Y0206954D01*
+X0294300Y0207047D01*
+X0294300Y0213297D01*
+X0293050Y0220797D01*
+X0284300Y0222047D01*
+X0284300Y0233297D01*
+X0285550Y0244508D02*
+X0285589Y0245758D01*
+X0266800Y0233297D02*
+X0266800Y0223297D01*
+X0269300Y0212047D01*
+X0259300Y0212047D01*
+X0251800Y0204547D01*
+X0231800Y0204547D02*
+X0231800Y0215797D01*
+X0228050Y0219547D01*
+X0269300Y0212047D02*
+X0269348Y0211848D01*
+X0269401Y0211650D01*
+X0269460Y0211454D01*
+X0269522Y0211259D01*
+X0269590Y0211066D01*
+X0269663Y0210875D01*
+X0269740Y0210685D01*
+X0269821Y0210498D01*
+X0269908Y0210312D01*
+X0269999Y0210129D01*
+X0270094Y0209948D01*
+X0270194Y0209769D01*
+X0270298Y0209593D01*
+X0270406Y0209419D01*
+X0270519Y0209248D01*
+X0270636Y0209080D01*
+X0270757Y0208915D01*
+X0270881Y0208753D01*
+X0271010Y0208594D01*
+X0271143Y0208438D01*
+X0271279Y0208285D01*
+X0271420Y0208136D01*
+X0271563Y0207991D01*
+X0271711Y0207849D01*
+X0271861Y0207710D01*
+X0272016Y0207576D01*
+X0272173Y0207445D01*
+X0272333Y0207318D01*
+X0272497Y0207195D01*
+X0272664Y0207076D01*
+X0272833Y0206961D01*
+X0273005Y0206851D01*
+X0273180Y0206744D01*
+X0273358Y0206642D01*
+X0273538Y0206545D01*
+X0273720Y0206451D01*
+X0273904Y0206363D01*
+X0274091Y0206279D01*
+X0274279Y0206199D01*
+X0274470Y0206124D01*
+X0274662Y0206054D01*
+X0274856Y0205989D01*
+X0275051Y0205928D01*
+X0275248Y0205872D01*
+X0275447Y0205821D01*
+X0275646Y0205775D01*
+X0275846Y0205734D01*
+X0276048Y0205697D01*
+X0276250Y0205666D01*
+X0276453Y0205640D01*
+X0276657Y0205618D01*
+X0276861Y0205602D01*
+X0277065Y0205591D01*
+X0277270Y0205584D01*
+X0277474Y0205583D01*
+X0277679Y0205587D01*
+X0277883Y0205596D01*
+X0278088Y0205609D01*
+X0278291Y0205628D01*
+X0278495Y0205652D01*
+X0278697Y0205681D01*
+X0278899Y0205714D01*
+X0279100Y0205753D01*
+X0279300Y0205797D01*
+X0286800Y0205797D01*
+X0320550Y0240797D02*
+X0318050Y0252047D01*
+X0335550Y0233297D01*
+X0350550Y0233297D01*
+X0350550Y0203297D01*
+X0361800Y0192047D01*
+X0368050Y0158297D01*
+X0361800Y0153297D01*
+X0360653Y0151958D01*
+X0350550Y0141856D01*
+X0350550Y0089547D01*
+X0315552Y0068297D02*
+X0315560Y0061047D01*
+X0304300Y0057047D02*
+X0303040Y0057047D01*
+X0255550Y0147047D02*
+X0249300Y0147047D01*
+X0255550Y0147047D02*
+X0255550Y0150807D01*
+X0255550Y0158287D02*
+X0241800Y0158287D01*
+X0234300Y0153297D02*
+X0235498Y0150115D01*
+X0226800Y0149537D01*
+X0235498Y0150115D02*
+X0241800Y0150807D01*
+X0318050Y0252047D02*
+X0318050Y0264547D01*
+X0296800Y0272047D02*
+X0294939Y0273907D01*
+X0248050Y0273907D01*
+X0250550Y0269547D01*
+D39*
+X0354300Y0074547D02*
+X0354300Y0072037D01*
+X0274300Y0043297D02*
+X0206800Y0043297D01*
+X0198050Y0052047D01*
+X0169300Y0052047D01*
+D40*
+X0186800Y0020797D03*
+X0239300Y0020797D03*
+X0120550Y0035797D03*
+X0053050Y0098297D03*
+X0018050Y0138297D03*
+X0119300Y0165797D03*
+X0131800Y0199547D03*
+X0101800Y0220797D03*
+X0133050Y0255797D03*
+X0146800Y0234547D03*
+X0166800Y0117047D03*
+X0361800Y0192047D03*
+X0364300Y0222047D03*
+X0364300Y0229547D03*
+D41*
+X0354300Y0229242D02*
+X0229300Y0229242D01*
+X0229300Y0230040D02*
+X0354300Y0230040D01*
+X0354300Y0230839D02*
+X0229300Y0230839D01*
+X0229300Y0231637D02*
+X0354300Y0231637D01*
+X0354300Y0232436D02*
+X0229300Y0232436D01*
+X0229300Y0233234D02*
+X0354300Y0233234D01*
+X0354300Y0234033D02*
+X0229300Y0234033D01*
+X0229300Y0234463D02*
+X0229374Y0234562D01*
+X0229463Y0234909D01*
+X0229600Y0235240D01*
+X0229600Y0235444D01*
+X0229651Y0235641D01*
+X0229600Y0235996D01*
+X0229600Y0238297D01*
+X0230550Y0238297D01*
+X0230550Y0240258D01*
+X0231600Y0241308D01*
+X0231600Y0245285D01*
+X0230550Y0246335D01*
+X0230550Y0250258D01*
+X0231600Y0251308D01*
+X0231600Y0255285D01*
+X0230550Y0256335D01*
+X0230550Y0258297D01*
+X0219300Y0258297D01*
+X0219300Y0256736D01*
+X0218540Y0257497D01*
+X0217200Y0257497D01*
+X0217200Y0253697D01*
+X0216400Y0253697D01*
+X0216400Y0257497D01*
+X0215060Y0257497D01*
+X0212600Y0255036D01*
+X0212600Y0253697D01*
+X0216400Y0253697D01*
+X0216400Y0252897D01*
+X0212600Y0252897D01*
+X0212600Y0251557D01*
+X0213060Y0251097D01*
+X0210540Y0251097D01*
+X0211000Y0251557D01*
+X0211000Y0252897D01*
+X0207200Y0252897D01*
+X0207200Y0253697D01*
+X0206400Y0253697D01*
+X0206400Y0257497D01*
+X0205060Y0257497D01*
+X0202600Y0255036D01*
+X0202600Y0253697D01*
+X0206400Y0253697D01*
+X0206400Y0252897D01*
+X0202600Y0252897D01*
+X0202600Y0251557D01*
+X0203060Y0251097D01*
+X0201388Y0251097D01*
+X0201600Y0251308D01*
+X0201600Y0255285D01*
+X0198788Y0258097D01*
+X0194812Y0258097D01*
+X0192000Y0255285D01*
+X0192000Y0251308D01*
+X0192212Y0251097D01*
+X0192103Y0251097D01*
+X0191651Y0251368D01*
+X0190391Y0251556D01*
+X0189156Y0251247D01*
+X0188134Y0250489D01*
+X0187568Y0249547D01*
+X0180550Y0249547D01*
+X0180550Y0260047D01*
+X0183192Y0260047D01*
+X0185765Y0261112D01*
+X0187734Y0263082D01*
+X0187927Y0263547D01*
+X0251743Y0263547D01*
+X0253949Y0264460D01*
+X0255637Y0266148D01*
+X0256527Y0268297D01*
+X0259333Y0268297D01*
+X0259200Y0267978D01*
+X0258975Y0267136D01*
+X0258861Y0266272D01*
+X0258861Y0266236D01*
+X0265111Y0266236D01*
+X0265111Y0265436D01*
+X0258861Y0265436D01*
+X0258861Y0265400D01*
+X0258975Y0264536D01*
+X0259200Y0263694D01*
+X0259534Y0262888D01*
+X0259970Y0262133D01*
+X0260501Y0261442D01*
+X0261117Y0260825D01*
+X0261809Y0260295D01*
+X0262563Y0259859D01*
+X0263369Y0259525D01*
+X0264211Y0259299D01*
+X0265075Y0259186D01*
+X0265111Y0259186D01*
+X0265111Y0265436D01*
+X0265911Y0265436D01*
+X0265911Y0266236D01*
+X0272161Y0266236D01*
+X0272161Y0266272D01*
+X0272047Y0267136D01*
+X0271822Y0267978D01*
+X0271690Y0268297D01*
+X0279410Y0268297D01*
+X0279278Y0267978D01*
+X0279053Y0267136D01*
+X0278939Y0266272D01*
+X0278939Y0266236D01*
+X0285189Y0266236D01*
+X0285189Y0265436D01*
+X0278939Y0265436D01*
+X0278939Y0265400D01*
+X0279053Y0264536D01*
+X0279278Y0263694D01*
+X0279612Y0262888D01*
+X0280048Y0262133D01*
+X0280579Y0261442D01*
+X0281195Y0260825D01*
+X0281887Y0260295D01*
+X0282641Y0259859D01*
+X0283447Y0259525D01*
+X0284289Y0259299D01*
+X0285153Y0259186D01*
+X0285189Y0259186D01*
+X0285189Y0265436D01*
+X0285989Y0265436D01*
+X0285989Y0266236D01*
+X0292239Y0266236D01*
+X0292239Y0266272D01*
+X0292125Y0267136D01*
+X0291900Y0267978D01*
+X0291767Y0268297D01*
+X0294186Y0268297D01*
+X0294251Y0268232D01*
+X0295905Y0267547D01*
+X0321800Y0267547D01*
+X0321800Y0252047D01*
+X0334300Y0235797D01*
+X0354300Y0235797D01*
+X0354300Y0218297D01*
+X0353050Y0218297D01*
+X0353050Y0202047D01*
+X0356463Y0202047D01*
+X0356463Y0200291D01*
+X0361400Y0200291D01*
+X0361400Y0199491D01*
+X0362200Y0199491D01*
+X0362200Y0195538D01*
+X0365921Y0195538D01*
+X0366277Y0195634D01*
+X0366597Y0195818D01*
+X0366857Y0196079D01*
+X0367042Y0196398D01*
+X0367137Y0196754D01*
+X0367137Y0199491D01*
+X0362200Y0199491D01*
+X0362200Y0200291D01*
+X0367137Y0200291D01*
+X0367137Y0202047D01*
+X0371800Y0202047D01*
+X0371800Y0152047D01*
+X0365550Y0152047D01*
+X0359300Y0144547D01*
+X0359300Y0137047D01*
+X0355550Y0135797D01*
+X0355550Y0124547D01*
+X0351800Y0120797D01*
+X0351800Y0107047D01*
+X0353050Y0103297D01*
+X0353050Y0089547D01*
+X0349300Y0085797D01*
+X0304300Y0085797D01*
+X0304300Y0093297D01*
+X0300850Y0096747D01*
+X0300850Y0133854D01*
+X0300550Y0134578D01*
+X0300550Y0139547D01*
+X0289053Y0146253D01*
+X0285759Y0149548D01*
+X0286800Y0155797D01*
+X0284300Y0164547D01*
+X0284300Y0171211D01*
+X0284334Y0171294D01*
+X0284334Y0172799D01*
+X0284300Y0172882D01*
+X0284300Y0200797D01*
+X0273050Y0202047D01*
+X0229300Y0202047D01*
+X0229300Y0215375D01*
+X0231150Y0215375D01*
+X0231799Y0215478D01*
+X0232423Y0215681D01*
+X0233008Y0215979D01*
+X0233539Y0216365D01*
+X0234004Y0216829D01*
+X0234390Y0217360D01*
+X0234688Y0217945D01*
+X0234891Y0218570D01*
+X0234982Y0219147D01*
+X0229300Y0219147D01*
+X0229300Y0219947D01*
+X0234982Y0219947D01*
+X0234891Y0220524D01*
+X0234688Y0221148D01*
+X0234390Y0221733D01*
+X0234004Y0222264D01*
+X0233539Y0222729D01*
+X0233008Y0223115D01*
+X0232423Y0223413D01*
+X0231799Y0223616D01*
+X0231150Y0223718D01*
+X0229300Y0223718D01*
+X0229300Y0234463D01*
+X0229443Y0234831D02*
+X0354300Y0234831D01*
+X0354300Y0235630D02*
+X0229648Y0235630D01*
+X0229600Y0236428D02*
+X0333814Y0236428D01*
+X0333200Y0237227D02*
+X0229600Y0237227D01*
+X0229600Y0238025D02*
+X0332586Y0238025D01*
+X0331971Y0238824D02*
+X0239115Y0238824D01*
+X0238788Y0238497D02*
+X0241600Y0241308D01*
+X0241600Y0245285D01*
+X0238788Y0248097D01*
+X0234812Y0248097D01*
+X0232000Y0245285D01*
+X0232000Y0241308D01*
+X0234812Y0238497D01*
+X0238788Y0238497D01*
+X0239914Y0239622D02*
+X0262946Y0239622D01*
+X0262563Y0239781D02*
+X0263369Y0239447D01*
+X0264211Y0239221D01*
+X0265075Y0239108D01*
+X0265111Y0239108D01*
+X0265111Y0245358D01*
+X0258861Y0245358D01*
+X0258861Y0245322D01*
+X0258975Y0244458D01*
+X0259200Y0243616D01*
+X0259534Y0242810D01*
+X0259970Y0242055D01*
+X0260501Y0241364D01*
+X0261117Y0240747D01*
+X0261809Y0240217D01*
+X0262563Y0239781D01*
+X0261542Y0240421D02*
+X0240712Y0240421D01*
+X0241511Y0241219D02*
+X0260645Y0241219D01*
+X0259998Y0242018D02*
+X0241600Y0242018D01*
+X0241600Y0242816D02*
+X0259531Y0242816D01*
+X0259201Y0243615D02*
+X0241600Y0243615D01*
+X0241600Y0244413D02*
+X0258987Y0244413D01*
+X0258875Y0245212D02*
+X0241600Y0245212D01*
+X0240874Y0246011D02*
+X0265111Y0246011D01*
+X0265111Y0246158D02*
+X0265111Y0245358D01*
+X0265911Y0245358D01*
+X0265911Y0246158D01*
+X0265111Y0246158D01*
+X0265111Y0252408D01*
+X0265075Y0252408D01*
+X0264211Y0252294D01*
+X0263369Y0252068D01*
+X0262563Y0251735D01*
+X0261809Y0251299D01*
+X0261117Y0250768D01*
+X0260501Y0250152D01*
+X0259970Y0249460D01*
+X0259534Y0248705D01*
+X0259200Y0247900D01*
+X0258975Y0247058D01*
+X0258861Y0246194D01*
+X0258861Y0246158D01*
+X0265111Y0246158D01*
+X0265111Y0246809D02*
+X0265911Y0246809D01*
+X0265911Y0246158D02*
+X0265911Y0252408D01*
+X0265947Y0252408D01*
+X0266811Y0252294D01*
+X0267653Y0252068D01*
+X0268459Y0251735D01*
+X0269213Y0251299D01*
+X0269905Y0250768D01*
+X0270521Y0250152D01*
+X0271052Y0249460D01*
+X0271488Y0248705D01*
+X0271822Y0247900D01*
+X0272047Y0247058D01*
+X0272161Y0246194D01*
+X0272161Y0246158D01*
+X0265911Y0246158D01*
+X0265911Y0246011D02*
+X0285189Y0246011D01*
+X0285189Y0246158D02*
+X0285189Y0245358D01*
+X0278939Y0245358D01*
+X0278939Y0245322D01*
+X0279053Y0244458D01*
+X0279278Y0243616D01*
+X0279612Y0242810D01*
+X0280048Y0242055D01*
+X0280579Y0241364D01*
+X0281195Y0240747D01*
+X0281887Y0240217D01*
+X0282641Y0239781D01*
+X0283447Y0239447D01*
+X0284289Y0239221D01*
+X0285153Y0239108D01*
+X0285189Y0239108D01*
+X0285189Y0245358D01*
+X0285989Y0245358D01*
+X0285989Y0246158D01*
+X0285189Y0246158D01*
+X0285189Y0252408D01*
+X0285153Y0252408D01*
+X0284289Y0252294D01*
+X0283447Y0252068D01*
+X0282641Y0251735D01*
+X0281887Y0251299D01*
+X0281195Y0250768D01*
+X0280579Y0250152D01*
+X0280048Y0249460D01*
+X0279612Y0248705D01*
+X0279278Y0247900D01*
+X0279053Y0247058D01*
+X0278939Y0246194D01*
+X0278939Y0246158D01*
+X0285189Y0246158D01*
+X0285189Y0246809D02*
+X0285989Y0246809D01*
+X0285989Y0246158D02*
+X0285989Y0252408D01*
+X0286025Y0252408D01*
+X0286889Y0252294D01*
+X0287731Y0252068D01*
+X0288537Y0251735D01*
+X0289291Y0251299D01*
+X0289983Y0250768D01*
+X0290599Y0250152D01*
+X0291130Y0249460D01*
+X0291566Y0248705D01*
+X0291900Y0247900D01*
+X0292125Y0247058D01*
+X0292239Y0246194D01*
+X0292239Y0246158D01*
+X0285989Y0246158D01*
+X0285989Y0246011D02*
+X0326443Y0246011D01*
+X0325829Y0246809D02*
+X0292158Y0246809D01*
+X0291978Y0247608D02*
+X0325215Y0247608D01*
+X0324600Y0248406D02*
+X0291690Y0248406D01*
+X0291278Y0249205D02*
+X0323986Y0249205D01*
+X0323372Y0250003D02*
+X0290714Y0250003D01*
+X0289939Y0250802D02*
+X0322758Y0250802D01*
+X0322144Y0251600D02*
+X0288770Y0251600D01*
+X0285989Y0251600D02*
+X0285189Y0251600D01*
+X0285189Y0250802D02*
+X0285989Y0250802D01*
+X0285989Y0250003D02*
+X0285189Y0250003D01*
+X0285189Y0249205D02*
+X0285989Y0249205D01*
+X0285989Y0248406D02*
+X0285189Y0248406D01*
+X0285189Y0247608D02*
+X0285989Y0247608D01*
+X0285989Y0245358D02*
+X0292239Y0245358D01*
+X0292239Y0245322D01*
+X0292125Y0244458D01*
+X0291900Y0243616D01*
+X0291566Y0242810D01*
+X0291130Y0242055D01*
+X0290599Y0241364D01*
+X0289983Y0240747D01*
+X0289291Y0240217D01*
+X0288537Y0239781D01*
+X0287731Y0239447D01*
+X0286889Y0239221D01*
+X0286025Y0239108D01*
+X0285989Y0239108D01*
+X0285989Y0245358D01*
+X0285989Y0245212D02*
+X0285189Y0245212D01*
+X0285189Y0244413D02*
+X0285989Y0244413D01*
+X0285989Y0243615D02*
+X0285189Y0243615D01*
+X0285189Y0242816D02*
+X0285989Y0242816D01*
+X0285989Y0242018D02*
+X0285189Y0242018D01*
+X0285189Y0241219D02*
+X0285989Y0241219D01*
+X0285989Y0240421D02*
+X0285189Y0240421D01*
+X0285189Y0239622D02*
+X0285989Y0239622D01*
+X0288154Y0239622D02*
+X0331357Y0239622D01*
+X0330743Y0240421D02*
+X0289558Y0240421D01*
+X0290455Y0241219D02*
+X0330129Y0241219D01*
+X0329514Y0242018D02*
+X0291101Y0242018D01*
+X0291569Y0242816D02*
+X0328900Y0242816D01*
+X0328286Y0243615D02*
+X0291899Y0243615D01*
+X0292113Y0244413D02*
+X0327672Y0244413D01*
+X0327057Y0245212D02*
+X0292224Y0245212D01*
+X0283024Y0239622D02*
+X0268076Y0239622D01*
+X0268459Y0239781D02*
+X0269213Y0240217D01*
+X0269905Y0240747D01*
+X0270521Y0241364D01*
+X0271052Y0242055D01*
+X0271488Y0242810D01*
+X0271822Y0243616D01*
+X0272047Y0244458D01*
+X0272161Y0245322D01*
+X0272161Y0245358D01*
+X0265911Y0245358D01*
+X0265911Y0239108D01*
+X0265947Y0239108D01*
+X0266811Y0239221D01*
+X0267653Y0239447D01*
+X0268459Y0239781D01*
+X0269480Y0240421D02*
+X0281620Y0240421D01*
+X0280723Y0241219D02*
+X0270377Y0241219D01*
+X0271024Y0242018D02*
+X0280076Y0242018D01*
+X0279609Y0242816D02*
+X0271491Y0242816D01*
+X0271821Y0243615D02*
+X0279279Y0243615D01*
+X0279065Y0244413D02*
+X0272035Y0244413D01*
+X0272147Y0245212D02*
+X0278953Y0245212D01*
+X0279020Y0246809D02*
+X0272080Y0246809D01*
+X0271900Y0247608D02*
+X0279200Y0247608D01*
+X0279488Y0248406D02*
+X0271612Y0248406D01*
+X0271200Y0249205D02*
+X0279900Y0249205D01*
+X0280464Y0250003D02*
+X0278548Y0250003D01*
+X0279232Y0250286D02*
+X0281060Y0252115D01*
+X0282050Y0254504D01*
+X0282050Y0257090D01*
+X0281060Y0259479D01*
+X0279232Y0261307D01*
+X0276843Y0262297D01*
+X0274257Y0262297D01*
+X0271868Y0261307D01*
+X0270040Y0259479D01*
+X0269050Y0257090D01*
+X0269050Y0254504D01*
+X0270040Y0252115D01*
+X0271868Y0250286D01*
+X0274257Y0249297D01*
+X0276843Y0249297D01*
+X0279232Y0250286D01*
+X0279747Y0250802D02*
+X0281238Y0250802D01*
+X0280546Y0251600D02*
+X0282408Y0251600D01*
+X0281178Y0252399D02*
+X0285084Y0252399D01*
+X0285189Y0252399D02*
+X0285989Y0252399D01*
+X0286094Y0252399D02*
+X0321800Y0252399D01*
+X0321800Y0253197D02*
+X0281509Y0253197D01*
+X0281840Y0253996D02*
+X0321800Y0253996D01*
+X0321800Y0254794D02*
+X0282050Y0254794D01*
+X0282050Y0255593D02*
+X0321800Y0255593D01*
+X0321800Y0256391D02*
+X0282050Y0256391D01*
+X0282009Y0257190D02*
+X0321800Y0257190D01*
+X0321800Y0257988D02*
+X0281678Y0257988D01*
+X0281347Y0258787D02*
+X0321800Y0258787D01*
+X0321800Y0259585D02*
+X0287876Y0259585D01*
+X0287731Y0259525D02*
+X0288537Y0259859D01*
+X0289291Y0260295D01*
+X0289983Y0260825D01*
+X0290599Y0261442D01*
+X0291130Y0262133D01*
+X0291566Y0262888D01*
+X0291900Y0263694D01*
+X0292125Y0264536D01*
+X0292239Y0265400D01*
+X0292239Y0265436D01*
+X0285989Y0265436D01*
+X0285989Y0259186D01*
+X0286025Y0259186D01*
+X0286889Y0259299D01*
+X0287731Y0259525D01*
+X0285989Y0259585D02*
+X0285189Y0259585D01*
+X0285189Y0260384D02*
+X0285989Y0260384D01*
+X0285989Y0261182D02*
+X0285189Y0261182D01*
+X0285189Y0261981D02*
+X0285989Y0261981D01*
+X0285989Y0262779D02*
+X0285189Y0262779D01*
+X0285189Y0263578D02*
+X0285989Y0263578D01*
+X0285989Y0264376D02*
+X0285189Y0264376D01*
+X0285189Y0265175D02*
+X0285989Y0265175D01*
+X0285989Y0265973D02*
+X0321800Y0265973D01*
+X0321800Y0265175D02*
+X0292209Y0265175D01*
+X0292083Y0264376D02*
+X0321800Y0264376D01*
+X0321800Y0263578D02*
+X0291852Y0263578D01*
+X0291503Y0262779D02*
+X0321800Y0262779D01*
+X0321800Y0261981D02*
+X0291013Y0261981D01*
+X0290340Y0261182D02*
+X0321800Y0261182D01*
+X0321800Y0260384D02*
+X0289408Y0260384D01*
+X0283302Y0259585D02*
+X0280954Y0259585D01*
+X0280155Y0260384D02*
+X0281770Y0260384D01*
+X0280838Y0261182D02*
+X0279357Y0261182D01*
+X0280165Y0261981D02*
+X0277606Y0261981D01*
+X0279675Y0262779D02*
+X0271425Y0262779D01*
+X0271488Y0262888D02*
+X0271822Y0263694D01*
+X0272047Y0264536D01*
+X0272161Y0265400D01*
+X0272161Y0265436D01*
+X0265911Y0265436D01*
+X0265911Y0259186D01*
+X0265947Y0259186D01*
+X0266811Y0259299D01*
+X0267653Y0259525D01*
+X0268459Y0259859D01*
+X0269213Y0260295D01*
+X0269905Y0260825D01*
+X0270521Y0261442D01*
+X0271052Y0262133D01*
+X0271488Y0262888D01*
+X0271774Y0263578D02*
+X0279326Y0263578D01*
+X0279095Y0264376D02*
+X0272005Y0264376D01*
+X0272131Y0265175D02*
+X0278969Y0265175D01*
+X0279005Y0266772D02*
+X0272095Y0266772D01*
+X0271931Y0267570D02*
+X0279169Y0267570D01*
+X0285189Y0265973D02*
+X0265911Y0265973D01*
+X0265911Y0265175D02*
+X0265111Y0265175D01*
+X0265111Y0265973D02*
+X0255462Y0265973D01*
+X0255895Y0266772D02*
+X0258927Y0266772D01*
+X0259091Y0267570D02*
+X0256226Y0267570D01*
+X0254663Y0265175D02*
+X0258891Y0265175D01*
+X0259017Y0264376D02*
+X0253746Y0264376D01*
+X0251818Y0263578D02*
+X0259248Y0263578D01*
+X0259597Y0262779D02*
+X0187432Y0262779D01*
+X0186634Y0261981D02*
+X0260087Y0261981D01*
+X0260760Y0261182D02*
+X0185835Y0261182D01*
+X0184006Y0260384D02*
+X0261692Y0260384D01*
+X0263224Y0259585D02*
+X0180550Y0259585D01*
+X0180550Y0258787D02*
+X0269753Y0258787D01*
+X0269422Y0257988D02*
+X0238897Y0257988D01*
+X0238788Y0258097D02*
+X0234812Y0258097D01*
+X0232000Y0255285D01*
+X0232000Y0251308D01*
+X0234812Y0248497D01*
+X0238788Y0248497D01*
+X0241600Y0251308D01*
+X0241600Y0255285D01*
+X0238788Y0258097D01*
+X0239695Y0257190D02*
+X0269091Y0257190D01*
+X0269050Y0256391D02*
+X0240494Y0256391D01*
+X0241292Y0255593D02*
+X0269050Y0255593D01*
+X0269050Y0254794D02*
+X0241600Y0254794D01*
+X0241600Y0253996D02*
+X0269260Y0253996D01*
+X0269591Y0253197D02*
+X0241600Y0253197D01*
+X0241600Y0252399D02*
+X0265006Y0252399D01*
+X0265111Y0252399D02*
+X0265911Y0252399D01*
+X0266016Y0252399D02*
+X0269922Y0252399D01*
+X0270554Y0251600D02*
+X0268692Y0251600D01*
+X0269862Y0250802D02*
+X0271353Y0250802D01*
+X0270636Y0250003D02*
+X0272552Y0250003D01*
+X0265911Y0250003D02*
+X0265111Y0250003D01*
+X0265111Y0249205D02*
+X0265911Y0249205D01*
+X0265911Y0248406D02*
+X0265111Y0248406D01*
+X0265111Y0247608D02*
+X0265911Y0247608D01*
+X0265911Y0245212D02*
+X0265111Y0245212D01*
+X0265111Y0244413D02*
+X0265911Y0244413D01*
+X0265911Y0243615D02*
+X0265111Y0243615D01*
+X0265111Y0242816D02*
+X0265911Y0242816D01*
+X0265911Y0242018D02*
+X0265111Y0242018D01*
+X0265111Y0241219D02*
+X0265911Y0241219D01*
+X0265911Y0240421D02*
+X0265111Y0240421D01*
+X0265111Y0239622D02*
+X0265911Y0239622D01*
+X0258942Y0246809D02*
+X0240076Y0246809D01*
+X0239277Y0247608D02*
+X0259122Y0247608D01*
+X0259410Y0248406D02*
+X0230550Y0248406D01*
+X0230550Y0247608D02*
+X0234323Y0247608D01*
+X0233524Y0246809D02*
+X0230550Y0246809D01*
+X0230874Y0246011D02*
+X0232726Y0246011D01*
+X0232000Y0245212D02*
+X0231600Y0245212D01*
+X0231600Y0244413D02*
+X0232000Y0244413D01*
+X0232000Y0243615D02*
+X0231600Y0243615D01*
+X0231600Y0242816D02*
+X0232000Y0242816D01*
+X0232000Y0242018D02*
+X0231600Y0242018D01*
+X0231511Y0241219D02*
+X0232089Y0241219D01*
+X0232888Y0240421D02*
+X0230712Y0240421D01*
+X0230550Y0239622D02*
+X0233686Y0239622D01*
+X0234485Y0238824D02*
+X0230550Y0238824D01*
+X0229300Y0228443D02*
+X0354300Y0228443D01*
+X0354300Y0227645D02*
+X0229300Y0227645D01*
+X0229300Y0226846D02*
+X0354300Y0226846D01*
+X0354300Y0226048D02*
+X0229300Y0226048D01*
+X0229300Y0225249D02*
+X0354300Y0225249D01*
+X0354300Y0224451D02*
+X0229300Y0224451D01*
+X0231568Y0223652D02*
+X0354300Y0223652D01*
+X0354300Y0222854D02*
+X0233367Y0222854D01*
+X0234156Y0222055D02*
+X0354300Y0222055D01*
+X0354300Y0221257D02*
+X0234632Y0221257D01*
+X0234901Y0220458D02*
+X0354300Y0220458D01*
+X0354300Y0219660D02*
+X0229300Y0219660D01*
+X0232381Y0215667D02*
+X0353050Y0215667D01*
+X0353050Y0214869D02*
+X0229300Y0214869D01*
+X0229300Y0214070D02*
+X0353050Y0214070D01*
+X0353050Y0213272D02*
+X0229300Y0213272D01*
+X0229300Y0212473D02*
+X0353050Y0212473D01*
+X0353050Y0211675D02*
+X0229300Y0211675D01*
+X0229300Y0210876D02*
+X0353050Y0210876D01*
+X0353050Y0210077D02*
+X0229300Y0210077D01*
+X0229300Y0209279D02*
+X0353050Y0209279D01*
+X0353050Y0208480D02*
+X0229300Y0208480D01*
+X0229300Y0207682D02*
+X0353050Y0207682D01*
+X0353050Y0206883D02*
+X0229300Y0206883D01*
+X0229300Y0206085D02*
+X0353050Y0206085D01*
+X0353050Y0205286D02*
+X0229300Y0205286D01*
+X0229300Y0204488D02*
+X0353050Y0204488D01*
+X0353050Y0203689D02*
+X0229300Y0203689D01*
+X0229300Y0202891D02*
+X0353050Y0202891D01*
+X0353050Y0202092D02*
+X0229300Y0202092D01*
+X0233640Y0216466D02*
+X0353050Y0216466D01*
+X0353050Y0217264D02*
+X0234320Y0217264D01*
+X0234726Y0218063D02*
+X0353050Y0218063D01*
+X0354300Y0218861D02*
+X0234937Y0218861D01*
+X0234104Y0249205D02*
+X0230550Y0249205D01*
+X0230550Y0250003D02*
+X0233305Y0250003D01*
+X0232507Y0250802D02*
+X0231093Y0250802D01*
+X0231600Y0251600D02*
+X0232000Y0251600D01*
+X0232000Y0252399D02*
+X0231600Y0252399D01*
+X0231600Y0253197D02*
+X0232000Y0253197D01*
+X0232000Y0253996D02*
+X0231600Y0253996D01*
+X0231600Y0254794D02*
+X0232000Y0254794D01*
+X0232308Y0255593D02*
+X0231292Y0255593D01*
+X0230550Y0256391D02*
+X0233106Y0256391D01*
+X0233905Y0257190D02*
+X0230550Y0257190D01*
+X0230550Y0257988D02*
+X0234703Y0257988D01*
+X0241600Y0251600D02*
+X0262330Y0251600D01*
+X0261161Y0250802D02*
+X0241093Y0250802D01*
+X0240295Y0250003D02*
+X0260386Y0250003D01*
+X0259822Y0249205D02*
+X0239496Y0249205D01*
+X0219300Y0257190D02*
+X0218847Y0257190D01*
+X0219300Y0257988D02*
+X0198897Y0257988D01*
+X0199695Y0257190D02*
+X0204753Y0257190D01*
+X0203955Y0256391D02*
+X0200494Y0256391D01*
+X0201292Y0255593D02*
+X0203156Y0255593D01*
+X0202600Y0254794D02*
+X0201600Y0254794D01*
+X0201600Y0253996D02*
+X0202600Y0253996D01*
+X0201600Y0253197D02*
+X0206400Y0253197D01*
+X0206400Y0253996D02*
+X0207200Y0253996D01*
+X0207200Y0253697D02*
+X0207200Y0257497D01*
+X0208540Y0257497D01*
+X0211000Y0255036D01*
+X0211000Y0253697D01*
+X0207200Y0253697D01*
+X0207200Y0253197D02*
+X0216400Y0253197D01*
+X0216400Y0253996D02*
+X0217200Y0253996D01*
+X0217200Y0254794D02*
+X0216400Y0254794D01*
+X0216400Y0255593D02*
+X0217200Y0255593D01*
+X0217200Y0256391D02*
+X0216400Y0256391D01*
+X0216400Y0257190D02*
+X0217200Y0257190D01*
+X0214753Y0257190D02*
+X0208847Y0257190D01*
+X0209645Y0256391D02*
+X0213955Y0256391D01*
+X0213156Y0255593D02*
+X0210444Y0255593D01*
+X0211000Y0254794D02*
+X0212600Y0254794D01*
+X0212600Y0253996D02*
+X0211000Y0253996D01*
+X0211000Y0252399D02*
+X0212600Y0252399D01*
+X0212600Y0251600D02*
+X0211000Y0251600D01*
+X0207200Y0254794D02*
+X0206400Y0254794D01*
+X0206400Y0255593D02*
+X0207200Y0255593D01*
+X0207200Y0256391D02*
+X0206400Y0256391D01*
+X0206400Y0257190D02*
+X0207200Y0257190D01*
+X0202600Y0252399D02*
+X0201600Y0252399D01*
+X0201600Y0251600D02*
+X0202600Y0251600D01*
+X0194703Y0257988D02*
+X0180550Y0257988D01*
+X0180550Y0257190D02*
+X0193905Y0257190D01*
+X0193106Y0256391D02*
+X0180550Y0256391D01*
+X0180550Y0255593D02*
+X0192308Y0255593D01*
+X0192000Y0254794D02*
+X0180550Y0254794D01*
+X0180550Y0253996D02*
+X0192000Y0253996D01*
+X0192000Y0253197D02*
+X0180550Y0253197D01*
+X0180550Y0252399D02*
+X0192000Y0252399D01*
+X0192000Y0251600D02*
+X0180550Y0251600D01*
+X0180550Y0250802D02*
+X0188556Y0250802D01*
+X0187842Y0250003D02*
+X0180550Y0250003D01*
+X0265111Y0250802D02*
+X0265911Y0250802D01*
+X0265911Y0251600D02*
+X0265111Y0251600D01*
+X0265111Y0259585D02*
+X0265911Y0259585D01*
+X0265911Y0260384D02*
+X0265111Y0260384D01*
+X0265111Y0261182D02*
+X0265911Y0261182D01*
+X0265911Y0261981D02*
+X0265111Y0261981D01*
+X0265111Y0262779D02*
+X0265911Y0262779D01*
+X0265911Y0263578D02*
+X0265111Y0263578D01*
+X0265111Y0264376D02*
+X0265911Y0264376D01*
+X0270262Y0261182D02*
+X0271743Y0261182D01*
+X0270945Y0260384D02*
+X0269330Y0260384D01*
+X0270146Y0259585D02*
+X0267798Y0259585D01*
+X0270935Y0261981D02*
+X0273494Y0261981D01*
+X0292173Y0266772D02*
+X0321800Y0266772D01*
+X0295848Y0267570D02*
+X0292009Y0267570D01*
+X0279825Y0201294D02*
+X0356463Y0201294D01*
+X0356463Y0200495D02*
+X0284300Y0200495D01*
+X0284300Y0199697D02*
+X0361400Y0199697D01*
+X0361400Y0199491D02*
+X0356463Y0199491D01*
+X0356463Y0196754D01*
+X0356558Y0196398D01*
+X0356743Y0196079D01*
+X0357003Y0195818D01*
+X0357323Y0195634D01*
+X0357679Y0195538D01*
+X0361400Y0195538D01*
+X0361400Y0199491D01*
+X0361400Y0198898D02*
+X0362200Y0198898D01*
+X0362200Y0198100D02*
+X0361400Y0198100D01*
+X0361400Y0197301D02*
+X0362200Y0197301D01*
+X0362200Y0196503D02*
+X0361400Y0196503D01*
+X0361400Y0195704D02*
+X0362200Y0195704D01*
+X0362200Y0199697D02*
+X0371800Y0199697D01*
+X0371800Y0200495D02*
+X0367137Y0200495D01*
+X0367137Y0201294D02*
+X0371800Y0201294D01*
+X0371800Y0198898D02*
+X0367137Y0198898D01*
+X0367137Y0198100D02*
+X0371800Y0198100D01*
+X0371800Y0197301D02*
+X0367137Y0197301D01*
+X0367070Y0196503D02*
+X0371800Y0196503D01*
+X0371800Y0195704D02*
+X0366399Y0195704D01*
+X0371800Y0194906D02*
+X0284300Y0194906D01*
+X0284300Y0195704D02*
+X0357201Y0195704D01*
+X0356530Y0196503D02*
+X0284300Y0196503D01*
+X0284300Y0197301D02*
+X0356463Y0197301D01*
+X0356463Y0198100D02*
+X0284300Y0198100D01*
+X0284300Y0198898D02*
+X0356463Y0198898D01*
+X0371800Y0194107D02*
+X0284300Y0194107D01*
+X0284300Y0193309D02*
+X0371800Y0193309D01*
+X0371800Y0192510D02*
+X0284300Y0192510D01*
+X0284300Y0191712D02*
+X0371800Y0191712D01*
+X0371800Y0190913D02*
+X0284300Y0190913D01*
+X0284300Y0190115D02*
+X0371800Y0190115D01*
+X0371800Y0189316D02*
+X0284300Y0189316D01*
+X0284300Y0188518D02*
+X0371800Y0188518D01*
+X0371800Y0187719D02*
+X0284300Y0187719D01*
+X0284300Y0186921D02*
+X0371800Y0186921D01*
+X0371800Y0186122D02*
+X0284300Y0186122D01*
+X0284300Y0185324D02*
+X0371800Y0185324D01*
+X0371800Y0184525D02*
+X0284300Y0184525D01*
+X0284300Y0183727D02*
+X0371800Y0183727D01*
+X0371800Y0182928D02*
+X0284300Y0182928D01*
+X0284300Y0182130D02*
+X0371800Y0182130D01*
+X0371800Y0181331D02*
+X0284300Y0181331D01*
+X0284300Y0180533D02*
+X0371800Y0180533D01*
+X0371800Y0179734D02*
+X0284300Y0179734D01*
+X0284300Y0178936D02*
+X0371800Y0178936D01*
+X0371800Y0178137D02*
+X0284300Y0178137D01*
+X0284300Y0177339D02*
+X0371800Y0177339D01*
+X0371800Y0176540D02*
+X0284300Y0176540D01*
+X0284300Y0175742D02*
+X0371800Y0175742D01*
+X0371800Y0174943D02*
+X0284300Y0174943D01*
+X0284300Y0174144D02*
+X0371800Y0174144D01*
+X0371800Y0173346D02*
+X0284300Y0173346D01*
+X0284334Y0172547D02*
+X0371800Y0172547D01*
+X0371800Y0171749D02*
+X0284334Y0171749D01*
+X0284300Y0170950D02*
+X0371800Y0170950D01*
+X0371800Y0170152D02*
+X0284300Y0170152D01*
+X0284300Y0169353D02*
+X0371800Y0169353D01*
+X0371800Y0168555D02*
+X0284300Y0168555D01*
+X0284300Y0167756D02*
+X0371800Y0167756D01*
+X0371800Y0166958D02*
+X0284300Y0166958D01*
+X0284300Y0166159D02*
+X0371800Y0166159D01*
+X0371800Y0165361D02*
+X0284300Y0165361D01*
+X0284300Y0164562D02*
+X0371800Y0164562D01*
+X0371800Y0163764D02*
+X0284524Y0163764D01*
+X0284752Y0162965D02*
+X0371800Y0162965D01*
+X0371800Y0162167D02*
+X0284980Y0162167D01*
+X0285208Y0161368D02*
+X0371800Y0161368D01*
+X0371800Y0160570D02*
+X0285436Y0160570D01*
+X0285664Y0159771D02*
+X0371800Y0159771D01*
+X0371800Y0158973D02*
+X0285893Y0158973D01*
+X0286121Y0158174D02*
+X0371800Y0158174D01*
+X0371800Y0157376D02*
+X0286349Y0157376D01*
+X0286577Y0156577D02*
+X0371800Y0156577D01*
+X0371800Y0155779D02*
+X0286797Y0155779D01*
+X0286664Y0154980D02*
+X0371800Y0154980D01*
+X0371800Y0154182D02*
+X0286531Y0154182D01*
+X0286398Y0153383D02*
+X0371800Y0153383D01*
+X0371800Y0152585D02*
+X0286265Y0152585D01*
+X0286132Y0151786D02*
+X0365333Y0151786D01*
+X0364667Y0150988D02*
+X0285998Y0150988D01*
+X0285865Y0150189D02*
+X0364002Y0150189D01*
+X0363337Y0149391D02*
+X0285916Y0149391D01*
+X0286714Y0148592D02*
+X0362671Y0148592D01*
+X0362006Y0147794D02*
+X0287513Y0147794D01*
+X0288311Y0146995D02*
+X0361340Y0146995D01*
+X0360675Y0146197D02*
+X0289150Y0146197D01*
+X0290519Y0145398D02*
+X0360009Y0145398D01*
+X0359344Y0144600D02*
+X0291888Y0144600D01*
+X0293257Y0143801D02*
+X0359300Y0143801D01*
+X0359300Y0143003D02*
+X0294626Y0143003D01*
+X0295995Y0142204D02*
+X0359300Y0142204D01*
+X0359300Y0141406D02*
+X0297363Y0141406D01*
+X0298732Y0140607D02*
+X0359300Y0140607D01*
+X0359300Y0139809D02*
+X0300101Y0139809D01*
+X0300550Y0139010D02*
+X0359300Y0139010D01*
+X0359300Y0138211D02*
+X0300550Y0138211D01*
+X0300550Y0137413D02*
+X0359300Y0137413D01*
+X0358003Y0136614D02*
+X0300550Y0136614D01*
+X0300550Y0135816D02*
+X0355608Y0135816D01*
+X0355550Y0135017D02*
+X0300550Y0135017D01*
+X0300699Y0134219D02*
+X0355550Y0134219D01*
+X0355550Y0133420D02*
+X0300850Y0133420D01*
+X0300850Y0132622D02*
+X0355550Y0132622D01*
+X0355550Y0131823D02*
+X0300850Y0131823D01*
+X0300850Y0131025D02*
+X0355550Y0131025D01*
+X0355550Y0130226D02*
+X0300850Y0130226D01*
+X0300850Y0129428D02*
+X0355550Y0129428D01*
+X0355550Y0128629D02*
+X0300850Y0128629D01*
+X0300850Y0127831D02*
+X0355550Y0127831D01*
+X0355550Y0127032D02*
+X0300850Y0127032D01*
+X0300850Y0126234D02*
+X0355550Y0126234D01*
+X0355550Y0125435D02*
+X0300850Y0125435D01*
+X0300850Y0124637D02*
+X0355550Y0124637D01*
+X0354842Y0123838D02*
+X0300850Y0123838D01*
+X0300850Y0123040D02*
+X0354043Y0123040D01*
+X0353245Y0122241D02*
+X0300850Y0122241D01*
+X0300850Y0121443D02*
+X0352446Y0121443D01*
+X0351800Y0120644D02*
+X0300850Y0120644D01*
+X0300850Y0119846D02*
+X0351800Y0119846D01*
+X0351800Y0119047D02*
+X0300850Y0119047D01*
+X0300850Y0118249D02*
+X0351800Y0118249D01*
+X0351800Y0117450D02*
+X0300850Y0117450D01*
+X0300850Y0116652D02*
+X0351800Y0116652D01*
+X0351800Y0115853D02*
+X0300850Y0115853D01*
+X0300850Y0115055D02*
+X0351800Y0115055D01*
+X0351800Y0114256D02*
+X0300850Y0114256D01*
+X0300850Y0113458D02*
+X0351800Y0113458D01*
+X0351800Y0112659D02*
+X0300850Y0112659D01*
+X0300850Y0111861D02*
+X0351800Y0111861D01*
+X0351800Y0111062D02*
+X0300850Y0111062D01*
+X0300850Y0110264D02*
+X0351800Y0110264D01*
+X0351800Y0109465D02*
+X0300850Y0109465D01*
+X0300850Y0108667D02*
+X0351800Y0108667D01*
+X0351800Y0107868D02*
+X0300850Y0107868D01*
+X0300850Y0107070D02*
+X0351800Y0107070D01*
+X0352059Y0106271D02*
+X0300850Y0106271D01*
+X0300850Y0105473D02*
+X0352325Y0105473D01*
+X0352591Y0104674D02*
+X0300850Y0104674D01*
+X0300850Y0103875D02*
+X0352857Y0103875D01*
+X0353050Y0103077D02*
+X0300850Y0103077D01*
+X0300850Y0102278D02*
+X0353050Y0102278D01*
+X0353050Y0101480D02*
+X0300850Y0101480D01*
+X0300850Y0100681D02*
+X0353050Y0100681D01*
+X0353050Y0099883D02*
+X0300850Y0099883D01*
+X0300850Y0099084D02*
+X0353050Y0099084D01*
+X0353050Y0098286D02*
+X0300850Y0098286D01*
+X0300850Y0097487D02*
+X0353050Y0097487D01*
+X0353050Y0096689D02*
+X0300908Y0096689D01*
+X0301706Y0095890D02*
+X0353050Y0095890D01*
+X0353050Y0095092D02*
+X0302505Y0095092D01*
+X0303303Y0094293D02*
+X0353050Y0094293D01*
+X0353050Y0093495D02*
+X0304102Y0093495D01*
+X0304300Y0092696D02*
+X0353050Y0092696D01*
+X0353050Y0091898D02*
+X0304300Y0091898D01*
+X0304300Y0091099D02*
+X0353050Y0091099D01*
+X0353050Y0090301D02*
+X0304300Y0090301D01*
+X0304300Y0089502D02*
+X0353006Y0089502D01*
+X0352207Y0088704D02*
+X0304300Y0088704D01*
+X0304300Y0087905D02*
+X0351409Y0087905D01*
+X0350610Y0087107D02*
+X0304300Y0087107D01*
+X0304300Y0086308D02*
+X0349812Y0086308D01*
+D42*
+X0269300Y0212047D02*
+X0268050Y0213297D01*
+X0268050Y0216570D01*
+X0243050Y0232047D01*
+X0265511Y0245758D02*
+X0265511Y0265836D01*
+X0265511Y0265758D01*
+X0263050Y0260797D01*
+X0285589Y0245758D02*
+X0299300Y0244508D01*
+X0320550Y0244508D01*
+X0320550Y0240797D01*
+X0100550Y0220797D02*
+X0098050Y0221702D01*
+X0092706Y0227047D01*
+D43*
+X0104763Y0240797D02*
+X0084644Y0245915D01*
+X0084644Y0254547D01*
+X0153050Y0267047D02*
+X0164300Y0267047D01*
+X0170550Y0267047D01*
+X0181800Y0267047D01*
+X0023050Y0092047D02*
+X0023050Y0043494D01*
+X0031800Y0034744D01*
+X0031800Y0029547D01*
+D44*
+X0230550Y0172047D02*
+X0230550Y0184547D01*
+X0233994Y0184547D01*
+X0233955Y0184524D01*
+X0233712Y0184282D01*
+X0233541Y0183985D01*
+X0233453Y0183655D01*
+X0233453Y0179847D01*
+X0237405Y0179847D01*
+X0237405Y0179247D01*
+X0233453Y0179247D01*
+X0233453Y0175439D01*
+X0233541Y0175108D01*
+X0233712Y0174811D01*
+X0233955Y0174569D01*
+X0234251Y0174398D01*
+X0234582Y0174310D01*
+X0237406Y0174310D01*
+X0237406Y0179247D01*
+X0238005Y0179247D01*
+X0238005Y0174310D01*
+X0240829Y0174310D01*
+X0241160Y0174398D01*
+X0241456Y0174569D01*
+X0241699Y0174811D01*
+X0241870Y0175108D01*
+X0241958Y0175439D01*
+X0241958Y0179247D01*
+X0238006Y0179247D01*
+X0238006Y0179847D01*
+X0241958Y0179847D01*
+X0241958Y0183655D01*
+X0241870Y0183985D01*
+X0241699Y0184282D01*
+X0241456Y0184524D01*
+X0241417Y0184547D01*
+X0248400Y0184547D01*
+X0248400Y0180106D01*
+X0248960Y0179547D01*
+X0248400Y0178987D01*
+X0248400Y0172626D01*
+X0248980Y0172047D01*
+X0230550Y0172047D01*
+X0230550Y0172448D02*
+X0248579Y0172448D01*
+X0248400Y0173046D02*
+X0230550Y0173046D01*
+X0230550Y0173645D02*
+X0248400Y0173645D01*
+X0248400Y0174243D02*
+X0230550Y0174243D01*
+X0230550Y0174842D02*
+X0233695Y0174842D01*
+X0233453Y0175440D02*
+X0230550Y0175440D01*
+X0230550Y0176039D02*
+X0233453Y0176039D01*
+X0233453Y0176637D02*
+X0230550Y0176637D01*
+X0230550Y0177236D02*
+X0233453Y0177236D01*
+X0233453Y0177834D02*
+X0230550Y0177834D01*
+X0230550Y0178433D02*
+X0233453Y0178433D01*
+X0233453Y0179031D02*
+X0230550Y0179031D01*
+X0230550Y0179630D02*
+X0237405Y0179630D01*
+X0237406Y0179031D02*
+X0238005Y0179031D01*
+X0238005Y0178433D02*
+X0237406Y0178433D01*
+X0237406Y0177834D02*
+X0238005Y0177834D01*
+X0238005Y0177236D02*
+X0237406Y0177236D01*
+X0237406Y0176637D02*
+X0238005Y0176637D01*
+X0238005Y0176039D02*
+X0237406Y0176039D01*
+X0237406Y0175440D02*
+X0238005Y0175440D01*
+X0238005Y0174842D02*
+X0237406Y0174842D01*
+X0241716Y0174842D02*
+X0248400Y0174842D01*
+X0248400Y0175440D02*
+X0241958Y0175440D01*
+X0241958Y0176039D02*
+X0248400Y0176039D01*
+X0248400Y0176637D02*
+X0241958Y0176637D01*
+X0241958Y0177236D02*
+X0248400Y0177236D01*
+X0248400Y0177834D02*
+X0241958Y0177834D01*
+X0241958Y0178433D02*
+X0248400Y0178433D01*
+X0248445Y0179031D02*
+X0241958Y0179031D01*
+X0241958Y0180228D02*
+X0248400Y0180228D01*
+X0248400Y0180827D02*
+X0241958Y0180827D01*
+X0241958Y0181425D02*
+X0248400Y0181425D01*
+X0248400Y0182024D02*
+X0241958Y0182024D01*
+X0241958Y0182622D02*
+X0248400Y0182622D01*
+X0248400Y0183221D02*
+X0241958Y0183221D01*
+X0241914Y0183819D02*
+X0248400Y0183819D01*
+X0248400Y0184418D02*
+X0241562Y0184418D01*
+X0238006Y0179630D02*
+X0248877Y0179630D01*
+X0233453Y0180228D02*
+X0230550Y0180228D01*
+X0230550Y0180827D02*
+X0233453Y0180827D01*
+X0233453Y0181425D02*
+X0230550Y0181425D01*
+X0230550Y0182024D02*
+X0233453Y0182024D01*
+X0233453Y0182622D02*
+X0230550Y0182622D01*
+X0230550Y0183221D02*
+X0233453Y0183221D01*
+X0233497Y0183819D02*
+X0230550Y0183819D01*
+X0230550Y0184418D02*
+X0233849Y0184418D01*
+X0333050Y0258297D02*
+X0333050Y0274547D01*
+X0378050Y0274547D01*
+X0378050Y0063297D01*
+X0370550Y0063297D01*
+X0370550Y0235797D01*
+X0360550Y0248297D01*
+X0341800Y0248297D01*
+X0333050Y0258297D01*
+X0333050Y0258633D02*
+X0378050Y0258633D01*
+X0378050Y0258035D02*
+X0333279Y0258035D01*
+X0333803Y0257436D02*
+X0378050Y0257436D01*
+X0378050Y0256838D02*
+X0334327Y0256838D01*
+X0334850Y0256239D02*
+X0378050Y0256239D01*
+X0378050Y0255641D02*
+X0335374Y0255641D01*
+X0335898Y0255042D02*
+X0378050Y0255042D01*
+X0378050Y0254444D02*
+X0336421Y0254444D01*
+X0336945Y0253845D02*
+X0378050Y0253845D01*
+X0378050Y0253247D02*
+X0337469Y0253247D01*
+X0337992Y0252648D02*
+X0378050Y0252648D01*
+X0378050Y0252050D02*
+X0338516Y0252050D01*
+X0339040Y0251451D02*
+X0378050Y0251451D01*
+X0378050Y0250853D02*
+X0339563Y0250853D01*
+X0340087Y0250254D02*
+X0378050Y0250254D01*
+X0378050Y0249656D02*
+X0340611Y0249656D01*
+X0341135Y0249057D02*
+X0378050Y0249057D01*
+X0378050Y0248459D02*
+X0341658Y0248459D01*
+X0333050Y0259232D02*
+X0378050Y0259232D01*
+X0378050Y0259830D02*
+X0333050Y0259830D01*
+X0333050Y0260429D02*
+X0378050Y0260429D01*
+X0378050Y0261027D02*
+X0333050Y0261027D01*
+X0333050Y0261626D02*
+X0378050Y0261626D01*
+X0378050Y0262224D02*
+X0333050Y0262224D01*
+X0333050Y0262823D02*
+X0378050Y0262823D01*
+X0378050Y0263421D02*
+X0333050Y0263421D01*
+X0333050Y0264020D02*
+X0378050Y0264020D01*
+X0378050Y0264618D02*
+X0333050Y0264618D01*
+X0333050Y0265217D02*
+X0378050Y0265217D01*
+X0378050Y0265815D02*
+X0333050Y0265815D01*
+X0333050Y0266414D02*
+X0378050Y0266414D01*
+X0378050Y0267013D02*
+X0333050Y0267013D01*
+X0333050Y0267611D02*
+X0378050Y0267611D01*
+X0378050Y0268210D02*
+X0333050Y0268210D01*
+X0333050Y0268808D02*
+X0378050Y0268808D01*
+X0378050Y0269407D02*
+X0333050Y0269407D01*
+X0333050Y0270005D02*
+X0378050Y0270005D01*
+X0378050Y0270604D02*
+X0333050Y0270604D01*
+X0333050Y0271202D02*
+X0378050Y0271202D01*
+X0378050Y0271801D02*
+X0333050Y0271801D01*
+X0333050Y0272399D02*
+X0378050Y0272399D01*
+X0378050Y0272998D02*
+X0333050Y0272998D01*
+X0333050Y0273596D02*
+X0378050Y0273596D01*
+X0378050Y0274195D02*
+X0333050Y0274195D01*
+X0360899Y0247860D02*
+X0378050Y0247860D01*
+X0378050Y0247262D02*
+X0361378Y0247262D01*
+X0361857Y0246663D02*
+X0378050Y0246663D01*
+X0378050Y0246065D02*
+X0362336Y0246065D01*
+X0362814Y0245466D02*
+X0378050Y0245466D01*
+X0378050Y0244868D02*
+X0363293Y0244868D01*
+X0363772Y0244269D02*
+X0378050Y0244269D01*
+X0378050Y0243671D02*
+X0364251Y0243671D01*
+X0364730Y0243072D02*
+X0378050Y0243072D01*
+X0378050Y0242474D02*
+X0365209Y0242474D01*
+X0365687Y0241875D02*
+X0378050Y0241875D01*
+X0378050Y0241277D02*
+X0366166Y0241277D01*
+X0366645Y0240678D02*
+X0378050Y0240678D01*
+X0378050Y0240080D02*
+X0367124Y0240080D01*
+X0367603Y0239481D02*
+X0378050Y0239481D01*
+X0378050Y0238882D02*
+X0368081Y0238882D01*
+X0368560Y0238284D02*
+X0378050Y0238284D01*
+X0378050Y0237685D02*
+X0369039Y0237685D01*
+X0369518Y0237087D02*
+X0378050Y0237087D01*
+X0378050Y0236488D02*
+X0369997Y0236488D01*
+X0370475Y0235890D02*
+X0378050Y0235890D01*
+X0378050Y0235291D02*
+X0370550Y0235291D01*
+X0370550Y0234693D02*
+X0378050Y0234693D01*
+X0378050Y0234094D02*
+X0370550Y0234094D01*
+X0370550Y0233496D02*
+X0378050Y0233496D01*
+X0378050Y0232897D02*
+X0370550Y0232897D01*
+X0370550Y0232299D02*
+X0378050Y0232299D01*
+X0378050Y0231700D02*
+X0370550Y0231700D01*
+X0370550Y0231102D02*
+X0378050Y0231102D01*
+X0378050Y0230503D02*
+X0370550Y0230503D01*
+X0370550Y0229905D02*
+X0378050Y0229905D01*
+X0378050Y0229306D02*
+X0370550Y0229306D01*
+X0370550Y0228708D02*
+X0378050Y0228708D01*
+X0378050Y0228109D02*
+X0370550Y0228109D01*
+X0370550Y0227511D02*
+X0378050Y0227511D01*
+X0378050Y0226912D02*
+X0370550Y0226912D01*
+X0370550Y0226314D02*
+X0378050Y0226314D01*
+X0378050Y0225715D02*
+X0370550Y0225715D01*
+X0370550Y0225117D02*
+X0378050Y0225117D01*
+X0378050Y0224518D02*
+X0370550Y0224518D01*
+X0370550Y0223920D02*
+X0378050Y0223920D01*
+X0378050Y0223321D02*
+X0370550Y0223321D01*
+X0370550Y0222723D02*
+X0378050Y0222723D01*
+X0378050Y0222124D02*
+X0370550Y0222124D01*
+X0370550Y0221526D02*
+X0378050Y0221526D01*
+X0378050Y0220927D02*
+X0370550Y0220927D01*
+X0370550Y0220329D02*
+X0378050Y0220329D01*
+X0378050Y0219730D02*
+X0370550Y0219730D01*
+X0370550Y0219132D02*
+X0378050Y0219132D01*
+X0378050Y0218533D02*
+X0370550Y0218533D01*
+X0370550Y0217935D02*
+X0378050Y0217935D01*
+X0378050Y0217336D02*
+X0370550Y0217336D01*
+X0370550Y0216738D02*
+X0378050Y0216738D01*
+X0378050Y0216139D02*
+X0370550Y0216139D01*
+X0370550Y0215541D02*
+X0378050Y0215541D01*
+X0378050Y0214942D02*
+X0370550Y0214942D01*
+X0370550Y0214344D02*
+X0378050Y0214344D01*
+X0378050Y0213745D02*
+X0370550Y0213745D01*
+X0370550Y0213146D02*
+X0378050Y0213146D01*
+X0378050Y0212548D02*
+X0370550Y0212548D01*
+X0370550Y0211949D02*
+X0378050Y0211949D01*
+X0378050Y0211351D02*
+X0370550Y0211351D01*
+X0370550Y0210752D02*
+X0378050Y0210752D01*
+X0378050Y0210154D02*
+X0370550Y0210154D01*
+X0370550Y0209555D02*
+X0378050Y0209555D01*
+X0378050Y0208957D02*
+X0370550Y0208957D01*
+X0370550Y0208358D02*
+X0378050Y0208358D01*
+X0378050Y0207760D02*
+X0370550Y0207760D01*
+X0370550Y0207161D02*
+X0378050Y0207161D01*
+X0378050Y0206563D02*
+X0370550Y0206563D01*
+X0370550Y0205964D02*
+X0378050Y0205964D01*
+X0378050Y0205366D02*
+X0370550Y0205366D01*
+X0370550Y0204767D02*
+X0378050Y0204767D01*
+X0378050Y0204169D02*
+X0370550Y0204169D01*
+X0370550Y0203570D02*
+X0378050Y0203570D01*
+X0378050Y0202972D02*
+X0370550Y0202972D01*
+X0370550Y0202373D02*
+X0378050Y0202373D01*
+X0378050Y0201775D02*
+X0370550Y0201775D01*
+X0370550Y0201176D02*
+X0378050Y0201176D01*
+X0378050Y0200578D02*
+X0370550Y0200578D01*
+X0370550Y0199979D02*
+X0378050Y0199979D01*
+X0378050Y0199381D02*
+X0370550Y0199381D01*
+X0370550Y0198782D02*
+X0378050Y0198782D01*
+X0378050Y0198184D02*
+X0370550Y0198184D01*
+X0370550Y0197585D02*
+X0378050Y0197585D01*
+X0378050Y0196987D02*
+X0370550Y0196987D01*
+X0370550Y0196388D02*
+X0378050Y0196388D01*
+X0378050Y0195790D02*
+X0370550Y0195790D01*
+X0370550Y0195191D02*
+X0378050Y0195191D01*
+X0378050Y0194593D02*
+X0370550Y0194593D01*
+X0370550Y0193994D02*
+X0378050Y0193994D01*
+X0378050Y0193396D02*
+X0370550Y0193396D01*
+X0370550Y0192797D02*
+X0378050Y0192797D01*
+X0378050Y0192199D02*
+X0370550Y0192199D01*
+X0370550Y0191600D02*
+X0378050Y0191600D01*
+X0378050Y0191002D02*
+X0370550Y0191002D01*
+X0370550Y0190403D02*
+X0378050Y0190403D01*
+X0378050Y0189805D02*
+X0370550Y0189805D01*
+X0370550Y0189206D02*
+X0378050Y0189206D01*
+X0378050Y0188608D02*
+X0370550Y0188608D01*
+X0370550Y0188009D02*
+X0378050Y0188009D01*
+X0378050Y0187411D02*
+X0370550Y0187411D01*
+X0370550Y0186812D02*
+X0378050Y0186812D01*
+X0378050Y0186213D02*
+X0370550Y0186213D01*
+X0370550Y0185615D02*
+X0378050Y0185615D01*
+X0378050Y0185016D02*
+X0370550Y0185016D01*
+X0370550Y0184418D02*
+X0378050Y0184418D01*
+X0378050Y0183819D02*
+X0370550Y0183819D01*
+X0370550Y0183221D02*
+X0378050Y0183221D01*
+X0378050Y0182622D02*
+X0370550Y0182622D01*
+X0370550Y0182024D02*
+X0378050Y0182024D01*
+X0378050Y0181425D02*
+X0370550Y0181425D01*
+X0370550Y0180827D02*
+X0378050Y0180827D01*
+X0378050Y0180228D02*
+X0370550Y0180228D01*
+X0370550Y0179630D02*
+X0378050Y0179630D01*
+X0378050Y0179031D02*
+X0370550Y0179031D01*
+X0370550Y0178433D02*
+X0378050Y0178433D01*
+X0378050Y0177834D02*
+X0370550Y0177834D01*
+X0370550Y0177236D02*
+X0378050Y0177236D01*
+X0378050Y0176637D02*
+X0370550Y0176637D01*
+X0370550Y0176039D02*
+X0378050Y0176039D01*
+X0378050Y0175440D02*
+X0370550Y0175440D01*
+X0370550Y0174842D02*
+X0378050Y0174842D01*
+X0378050Y0174243D02*
+X0370550Y0174243D01*
+X0370550Y0173645D02*
+X0378050Y0173645D01*
+X0378050Y0173046D02*
+X0370550Y0173046D01*
+X0370550Y0172448D02*
+X0378050Y0172448D01*
+X0378050Y0171849D02*
+X0370550Y0171849D01*
+X0370550Y0171251D02*
+X0378050Y0171251D01*
+X0378050Y0170652D02*
+X0370550Y0170652D01*
+X0370550Y0170054D02*
+X0378050Y0170054D01*
+X0378050Y0169455D02*
+X0370550Y0169455D01*
+X0370550Y0168857D02*
+X0378050Y0168857D01*
+X0378050Y0168258D02*
+X0370550Y0168258D01*
+X0370550Y0167660D02*
+X0378050Y0167660D01*
+X0378050Y0167061D02*
+X0370550Y0167061D01*
+X0370550Y0166463D02*
+X0378050Y0166463D01*
+X0378050Y0165864D02*
+X0370550Y0165864D01*
+X0370550Y0165266D02*
+X0378050Y0165266D01*
+X0378050Y0164667D02*
+X0370550Y0164667D01*
+X0370550Y0164069D02*
+X0378050Y0164069D01*
+X0378050Y0163470D02*
+X0370550Y0163470D01*
+X0370550Y0162872D02*
+X0378050Y0162872D01*
+X0378050Y0162273D02*
+X0370550Y0162273D01*
+X0370550Y0161675D02*
+X0378050Y0161675D01*
+X0378050Y0161076D02*
+X0370550Y0161076D01*
+X0370550Y0160477D02*
+X0378050Y0160477D01*
+X0378050Y0159879D02*
+X0370550Y0159879D01*
+X0370550Y0159280D02*
+X0378050Y0159280D01*
+X0378050Y0158682D02*
+X0370550Y0158682D01*
+X0370550Y0158083D02*
+X0378050Y0158083D01*
+X0378050Y0157485D02*
+X0370550Y0157485D01*
+X0370550Y0156886D02*
+X0378050Y0156886D01*
+X0378050Y0156288D02*
+X0370550Y0156288D01*
+X0370550Y0155689D02*
+X0378050Y0155689D01*
+X0378050Y0155091D02*
+X0370550Y0155091D01*
+X0370550Y0154492D02*
+X0378050Y0154492D01*
+X0378050Y0153894D02*
+X0370550Y0153894D01*
+X0370550Y0153295D02*
+X0378050Y0153295D01*
+X0378050Y0152697D02*
+X0370550Y0152697D01*
+X0370550Y0152098D02*
+X0378050Y0152098D01*
+X0378050Y0151500D02*
+X0370550Y0151500D01*
+X0370550Y0150901D02*
+X0378050Y0150901D01*
+X0378050Y0150303D02*
+X0370550Y0150303D01*
+X0370550Y0149704D02*
+X0378050Y0149704D01*
+X0378050Y0149106D02*
+X0370550Y0149106D01*
+X0370550Y0148507D02*
+X0378050Y0148507D01*
+X0378050Y0147909D02*
+X0370550Y0147909D01*
+X0370550Y0147310D02*
+X0378050Y0147310D01*
+X0378050Y0146712D02*
+X0370550Y0146712D01*
+X0370550Y0146113D02*
+X0378050Y0146113D01*
+X0378050Y0145515D02*
+X0370550Y0145515D01*
+X0370550Y0144916D02*
+X0378050Y0144916D01*
+X0378050Y0144318D02*
+X0370550Y0144318D01*
+X0370550Y0143719D02*
+X0378050Y0143719D01*
+X0378050Y0143121D02*
+X0370550Y0143121D01*
+X0370550Y0142522D02*
+X0378050Y0142522D01*
+X0378050Y0141924D02*
+X0370550Y0141924D01*
+X0370550Y0141325D02*
+X0378050Y0141325D01*
+X0378050Y0140727D02*
+X0370550Y0140727D01*
+X0370550Y0140128D02*
+X0378050Y0140128D01*
+X0378050Y0139530D02*
+X0370550Y0139530D01*
+X0370550Y0138931D02*
+X0378050Y0138931D01*
+X0378050Y0138333D02*
+X0370550Y0138333D01*
+X0370550Y0137734D02*
+X0378050Y0137734D01*
+X0378050Y0137136D02*
+X0370550Y0137136D01*
+X0370550Y0136537D02*
+X0378050Y0136537D01*
+X0378050Y0135939D02*
+X0370550Y0135939D01*
+X0370550Y0135340D02*
+X0378050Y0135340D01*
+X0378050Y0134742D02*
+X0370550Y0134742D01*
+X0370550Y0134143D02*
+X0378050Y0134143D01*
+X0378050Y0133544D02*
+X0370550Y0133544D01*
+X0370550Y0132946D02*
+X0378050Y0132946D01*
+X0378050Y0132347D02*
+X0370550Y0132347D01*
+X0370550Y0131749D02*
+X0378050Y0131749D01*
+X0378050Y0131150D02*
+X0370550Y0131150D01*
+X0370550Y0130552D02*
+X0378050Y0130552D01*
+X0378050Y0129953D02*
+X0370550Y0129953D01*
+X0370550Y0129355D02*
+X0378050Y0129355D01*
+X0378050Y0128756D02*
+X0370550Y0128756D01*
+X0370550Y0128158D02*
+X0378050Y0128158D01*
+X0378050Y0127559D02*
+X0370550Y0127559D01*
+X0370550Y0126961D02*
+X0378050Y0126961D01*
+X0378050Y0126362D02*
+X0370550Y0126362D01*
+X0370550Y0125764D02*
+X0378050Y0125764D01*
+X0378050Y0125165D02*
+X0370550Y0125165D01*
+X0370550Y0124567D02*
+X0378050Y0124567D01*
+X0378050Y0123968D02*
+X0370550Y0123968D01*
+X0370550Y0123370D02*
+X0378050Y0123370D01*
+X0378050Y0122771D02*
+X0370550Y0122771D01*
+X0370550Y0122173D02*
+X0378050Y0122173D01*
+X0378050Y0121574D02*
+X0370550Y0121574D01*
+X0370550Y0120976D02*
+X0378050Y0120976D01*
+X0378050Y0120377D02*
+X0370550Y0120377D01*
+X0370550Y0119779D02*
+X0378050Y0119779D01*
+X0378050Y0119180D02*
+X0370550Y0119180D01*
+X0370550Y0118582D02*
+X0378050Y0118582D01*
+X0378050Y0117983D02*
+X0370550Y0117983D01*
+X0370550Y0117385D02*
+X0378050Y0117385D01*
+X0378050Y0116786D02*
+X0370550Y0116786D01*
+X0370550Y0116188D02*
+X0378050Y0116188D01*
+X0378050Y0115589D02*
+X0370550Y0115589D01*
+X0370550Y0114991D02*
+X0378050Y0114991D01*
+X0378050Y0114392D02*
+X0370550Y0114392D01*
+X0370550Y0113794D02*
+X0378050Y0113794D01*
+X0378050Y0113195D02*
+X0370550Y0113195D01*
+X0370550Y0112597D02*
+X0378050Y0112597D01*
+X0378050Y0111998D02*
+X0370550Y0111998D01*
+X0370550Y0111400D02*
+X0378050Y0111400D01*
+X0378050Y0110801D02*
+X0370550Y0110801D01*
+X0370550Y0110203D02*
+X0378050Y0110203D01*
+X0378050Y0109604D02*
+X0370550Y0109604D01*
+X0370550Y0109006D02*
+X0378050Y0109006D01*
+X0378050Y0108407D02*
+X0370550Y0108407D01*
+X0370550Y0107809D02*
+X0378050Y0107809D01*
+X0378050Y0107210D02*
+X0370550Y0107210D01*
+X0370550Y0106611D02*
+X0378050Y0106611D01*
+X0378050Y0106013D02*
+X0370550Y0106013D01*
+X0370550Y0105414D02*
+X0378050Y0105414D01*
+X0378050Y0104816D02*
+X0370550Y0104816D01*
+X0370550Y0104217D02*
+X0378050Y0104217D01*
+X0378050Y0103619D02*
+X0370550Y0103619D01*
+X0370550Y0103020D02*
+X0378050Y0103020D01*
+X0378050Y0102422D02*
+X0370550Y0102422D01*
+X0370550Y0101823D02*
+X0378050Y0101823D01*
+X0378050Y0101225D02*
+X0370550Y0101225D01*
+X0370550Y0100626D02*
+X0378050Y0100626D01*
+X0378050Y0100028D02*
+X0370550Y0100028D01*
+X0370550Y0099429D02*
+X0378050Y0099429D01*
+X0378050Y0098831D02*
+X0370550Y0098831D01*
+X0370550Y0098232D02*
+X0378050Y0098232D01*
+X0378050Y0097634D02*
+X0370550Y0097634D01*
+X0370550Y0097035D02*
+X0378050Y0097035D01*
+X0378050Y0096437D02*
+X0370550Y0096437D01*
+X0370550Y0095838D02*
+X0378050Y0095838D01*
+X0378050Y0095240D02*
+X0370550Y0095240D01*
+X0370550Y0094641D02*
+X0378050Y0094641D01*
+X0378050Y0094043D02*
+X0370550Y0094043D01*
+X0370550Y0093444D02*
+X0378050Y0093444D01*
+X0378050Y0092846D02*
+X0370550Y0092846D01*
+X0370550Y0092247D02*
+X0378050Y0092247D01*
+X0378050Y0091649D02*
+X0370550Y0091649D01*
+X0370550Y0091050D02*
+X0378050Y0091050D01*
+X0378050Y0090452D02*
+X0370550Y0090452D01*
+X0370550Y0089853D02*
+X0378050Y0089853D01*
+X0378050Y0089255D02*
+X0370550Y0089255D01*
+X0370550Y0088656D02*
+X0378050Y0088656D01*
+X0378050Y0088058D02*
+X0370550Y0088058D01*
+X0370550Y0087459D02*
+X0378050Y0087459D01*
+X0378050Y0086861D02*
+X0370550Y0086861D01*
+X0370550Y0086262D02*
+X0378050Y0086262D01*
+X0378050Y0085664D02*
+X0370550Y0085664D01*
+X0370550Y0085065D02*
+X0378050Y0085065D01*
+X0378050Y0084467D02*
+X0370550Y0084467D01*
+X0370550Y0083868D02*
+X0378050Y0083868D01*
+X0378050Y0083270D02*
+X0370550Y0083270D01*
+X0370550Y0082671D02*
+X0378050Y0082671D01*
+X0378050Y0082073D02*
+X0370550Y0082073D01*
+X0370550Y0081474D02*
+X0378050Y0081474D01*
+X0378050Y0080875D02*
+X0370550Y0080875D01*
+X0370550Y0080277D02*
+X0378050Y0080277D01*
+X0378050Y0079678D02*
+X0370550Y0079678D01*
+X0370550Y0079080D02*
+X0378050Y0079080D01*
+X0378050Y0078481D02*
+X0370550Y0078481D01*
+X0370550Y0077883D02*
+X0378050Y0077883D01*
+X0378050Y0077284D02*
+X0370550Y0077284D01*
+X0370550Y0076686D02*
+X0378050Y0076686D01*
+X0378050Y0076087D02*
+X0370550Y0076087D01*
+X0370550Y0075489D02*
+X0378050Y0075489D01*
+X0378050Y0074890D02*
+X0370550Y0074890D01*
+X0370550Y0074292D02*
+X0378050Y0074292D01*
+X0378050Y0073693D02*
+X0370550Y0073693D01*
+X0370550Y0073095D02*
+X0378050Y0073095D01*
+X0378050Y0072496D02*
+X0370550Y0072496D01*
+X0370550Y0071898D02*
+X0378050Y0071898D01*
+X0378050Y0071299D02*
+X0370550Y0071299D01*
+X0370550Y0070701D02*
+X0378050Y0070701D01*
+X0378050Y0070102D02*
+X0370550Y0070102D01*
+X0370550Y0069504D02*
+X0378050Y0069504D01*
+X0378050Y0068905D02*
+X0370550Y0068905D01*
+X0370550Y0068307D02*
+X0378050Y0068307D01*
+X0378050Y0067708D02*
+X0370550Y0067708D01*
+X0370550Y0067110D02*
+X0378050Y0067110D01*
+X0378050Y0066511D02*
+X0370550Y0066511D01*
+X0370550Y0065913D02*
+X0378050Y0065913D01*
+X0378050Y0065314D02*
+X0370550Y0065314D01*
+X0370550Y0064716D02*
+X0378050Y0064716D01*
+X0378050Y0064117D02*
+X0370550Y0064117D01*
+X0370550Y0063519D02*
+X0378050Y0063519D01*
+D45*
+X0120550Y0046141D02*
+X0120550Y0035797D01*
+X0120550Y0046141D02*
+X0107706Y0046141D01*
+X0106800Y0047047D01*
+X0087765Y0055275D02*
+X0068050Y0074990D01*
+X0068050Y0079891D01*
+X0068050Y0108297D01*
+X0086328Y0108297D01*
+X0068050Y0108297D02*
+X0068050Y0170797D01*
+X0054300Y0184547D01*
+X0054300Y0217047D01*
+X0063050Y0227047D02*
+X0080894Y0227047D01*
+X0055550Y0239547D02*
+X0055550Y0254547D01*
+X0065560Y0254547D01*
+X0084644Y0254547D01*
+X0081800Y0259547D02*
+X0081800Y0269547D01*
+X0102144Y0269202D02*
+X0114300Y0269202D01*
+X0125904Y0269202D01*
+X0140402Y0267047D02*
+X0153050Y0267047D01*
+X0068050Y0079891D02*
+X0066456Y0078297D01*
+X0076800Y0022047D02*
+X0090550Y0023641D01*
+X0106800Y0020649D01*
+D46*
+X0184300Y0269547D02*
+X0250550Y0269547D01*
+M02*
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.stc b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.stc
new file mode 100755
index 0000000..8e5d99d
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.stc
@@ -0,0 +1,3847 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+%ADD10C,0.00300*%
+%ADD11C,0.06343*%
+%ADD12R,0.10800X0.05800*%
+%ADD13R,0.10800X0.10800*%
+%ADD14C,0.06737*%
+%ADD15C,0.23800*%
+%ADD16C,0.09800*%
+%ADD17C,0.11300*%
+%ADD18C,0.09800*%
+%ADD19OC8,0.05800*%
+%ADD20C,0.05800*%
+%ADD21C,0.06400*%
+%ADD22OC8,0.06400*%
+%ADD23C,0.04369*%
+%ADD24C,0.05156*%
+D10*
+X0001800Y0012047D02*
+X0008050Y0012047D01*
+X0008050Y0279547D01*
+X0001800Y0279547D01*
+X0001800Y0012047D01*
+X0008050Y0012047D01*
+X0008050Y0012345D02*
+X0001800Y0012345D01*
+X0001800Y0012644D02*
+X0008050Y0012644D01*
+X0008050Y0012942D02*
+X0001800Y0012942D01*
+X0001800Y0013241D02*
+X0008050Y0013241D01*
+X0008050Y0013539D02*
+X0001800Y0013539D01*
+X0001800Y0013838D02*
+X0008050Y0013838D01*
+X0008050Y0014136D02*
+X0001800Y0014136D01*
+X0001800Y0014435D02*
+X0008050Y0014435D01*
+X0008050Y0014733D02*
+X0001800Y0014733D01*
+X0001800Y0015032D02*
+X0008050Y0015032D01*
+X0008050Y0015330D02*
+X0001800Y0015330D01*
+X0001800Y0015629D02*
+X0008050Y0015629D01*
+X0008050Y0015927D02*
+X0001800Y0015927D01*
+X0001800Y0016226D02*
+X0008050Y0016226D01*
+X0008050Y0016524D02*
+X0001800Y0016524D01*
+X0001800Y0016823D02*
+X0008050Y0016823D01*
+X0008050Y0017121D02*
+X0001800Y0017121D01*
+X0001800Y0017420D02*
+X0008050Y0017420D01*
+X0008050Y0017718D02*
+X0001800Y0017718D01*
+X0001800Y0018017D02*
+X0008050Y0018017D01*
+X0008050Y0018315D02*
+X0001800Y0018315D01*
+X0001800Y0018614D02*
+X0008050Y0018614D01*
+X0008050Y0018912D02*
+X0001800Y0018912D01*
+X0001800Y0019211D02*
+X0008050Y0019211D01*
+X0008050Y0019509D02*
+X0001800Y0019509D01*
+X0001800Y0019808D02*
+X0008050Y0019808D01*
+X0008050Y0020106D02*
+X0001800Y0020106D01*
+X0001800Y0020405D02*
+X0008050Y0020405D01*
+X0008050Y0020704D02*
+X0001800Y0020704D01*
+X0001800Y0021002D02*
+X0008050Y0021002D01*
+X0008050Y0021301D02*
+X0001800Y0021301D01*
+X0001800Y0021599D02*
+X0008050Y0021599D01*
+X0008050Y0021898D02*
+X0001800Y0021898D01*
+X0001800Y0022196D02*
+X0008050Y0022196D01*
+X0008050Y0022495D02*
+X0001800Y0022495D01*
+X0001800Y0022793D02*
+X0008050Y0022793D01*
+X0008050Y0023092D02*
+X0001800Y0023092D01*
+X0001800Y0023390D02*
+X0008050Y0023390D01*
+X0008050Y0023689D02*
+X0001800Y0023689D01*
+X0001800Y0023987D02*
+X0008050Y0023987D01*
+X0008050Y0024286D02*
+X0001800Y0024286D01*
+X0001800Y0024584D02*
+X0008050Y0024584D01*
+X0008050Y0024883D02*
+X0001800Y0024883D01*
+X0001800Y0025181D02*
+X0008050Y0025181D01*
+X0008050Y0025480D02*
+X0001800Y0025480D01*
+X0001800Y0025778D02*
+X0008050Y0025778D01*
+X0008050Y0026077D02*
+X0001800Y0026077D01*
+X0001800Y0026375D02*
+X0008050Y0026375D01*
+X0008050Y0026674D02*
+X0001800Y0026674D01*
+X0001800Y0026972D02*
+X0008050Y0026972D01*
+X0008050Y0027271D02*
+X0001800Y0027271D01*
+X0001800Y0027569D02*
+X0008050Y0027569D01*
+X0008050Y0027868D02*
+X0001800Y0027868D01*
+X0001800Y0028166D02*
+X0008050Y0028166D01*
+X0008050Y0028465D02*
+X0001800Y0028465D01*
+X0001800Y0028763D02*
+X0008050Y0028763D01*
+X0008050Y0029062D02*
+X0001800Y0029062D01*
+X0001800Y0029360D02*
+X0008050Y0029360D01*
+X0008050Y0029659D02*
+X0001800Y0029659D01*
+X0001800Y0029957D02*
+X0008050Y0029957D01*
+X0008050Y0030256D02*
+X0001800Y0030256D01*
+X0001800Y0030554D02*
+X0008050Y0030554D01*
+X0008050Y0030853D02*
+X0001800Y0030853D01*
+X0001800Y0031151D02*
+X0008050Y0031151D01*
+X0008050Y0031450D02*
+X0001800Y0031450D01*
+X0001800Y0031748D02*
+X0008050Y0031748D01*
+X0008050Y0032047D02*
+X0001800Y0032047D01*
+X0001800Y0032345D02*
+X0008050Y0032345D01*
+X0008050Y0032644D02*
+X0001800Y0032644D01*
+X0001800Y0032942D02*
+X0008050Y0032942D01*
+X0008050Y0033241D02*
+X0001800Y0033241D01*
+X0001800Y0033540D02*
+X0008050Y0033540D01*
+X0008050Y0033838D02*
+X0001800Y0033838D01*
+X0001800Y0034137D02*
+X0008050Y0034137D01*
+X0008050Y0034435D02*
+X0001800Y0034435D01*
+X0001800Y0034734D02*
+X0008050Y0034734D01*
+X0008050Y0035032D02*
+X0001800Y0035032D01*
+X0001800Y0035331D02*
+X0008050Y0035331D01*
+X0008050Y0035629D02*
+X0001800Y0035629D01*
+X0001800Y0035928D02*
+X0008050Y0035928D01*
+X0008050Y0036226D02*
+X0001800Y0036226D01*
+X0001800Y0036525D02*
+X0008050Y0036525D01*
+X0008050Y0036823D02*
+X0001800Y0036823D01*
+X0001800Y0037122D02*
+X0008050Y0037122D01*
+X0008050Y0037420D02*
+X0001800Y0037420D01*
+X0001800Y0037719D02*
+X0008050Y0037719D01*
+X0008050Y0038017D02*
+X0001800Y0038017D01*
+X0001800Y0038316D02*
+X0008050Y0038316D01*
+X0008050Y0038614D02*
+X0001800Y0038614D01*
+X0001800Y0038913D02*
+X0008050Y0038913D01*
+X0008050Y0039211D02*
+X0001800Y0039211D01*
+X0001800Y0039510D02*
+X0008050Y0039510D01*
+X0008050Y0039808D02*
+X0001800Y0039808D01*
+X0001800Y0040107D02*
+X0008050Y0040107D01*
+X0008050Y0040405D02*
+X0001800Y0040405D01*
+X0001800Y0040704D02*
+X0008050Y0040704D01*
+X0008050Y0041002D02*
+X0001800Y0041002D01*
+X0001800Y0041301D02*
+X0008050Y0041301D01*
+X0008050Y0041599D02*
+X0001800Y0041599D01*
+X0001800Y0041898D02*
+X0008050Y0041898D01*
+X0008050Y0042196D02*
+X0001800Y0042196D01*
+X0001800Y0042495D02*
+X0008050Y0042495D01*
+X0008050Y0042793D02*
+X0001800Y0042793D01*
+X0001800Y0043092D02*
+X0008050Y0043092D01*
+X0008050Y0043390D02*
+X0001800Y0043390D01*
+X0001800Y0043689D02*
+X0008050Y0043689D01*
+X0008050Y0043987D02*
+X0001800Y0043987D01*
+X0001800Y0044286D02*
+X0008050Y0044286D01*
+X0008050Y0044584D02*
+X0001800Y0044584D01*
+X0001800Y0044883D02*
+X0008050Y0044883D01*
+X0008050Y0045181D02*
+X0001800Y0045181D01*
+X0001800Y0045480D02*
+X0008050Y0045480D01*
+X0008050Y0045778D02*
+X0001800Y0045778D01*
+X0001800Y0046077D02*
+X0008050Y0046077D01*
+X0008050Y0046375D02*
+X0001800Y0046375D01*
+X0001800Y0046674D02*
+X0008050Y0046674D01*
+X0008050Y0046973D02*
+X0001800Y0046973D01*
+X0001800Y0047271D02*
+X0008050Y0047271D01*
+X0008050Y0047570D02*
+X0001800Y0047570D01*
+X0001800Y0047868D02*
+X0008050Y0047868D01*
+X0008050Y0048167D02*
+X0001800Y0048167D01*
+X0001800Y0048465D02*
+X0008050Y0048465D01*
+X0008050Y0048764D02*
+X0001800Y0048764D01*
+X0001800Y0049062D02*
+X0008050Y0049062D01*
+X0008050Y0049361D02*
+X0001800Y0049361D01*
+X0001800Y0049659D02*
+X0008050Y0049659D01*
+X0008050Y0049958D02*
+X0001800Y0049958D01*
+X0001800Y0050256D02*
+X0008050Y0050256D01*
+X0008050Y0050555D02*
+X0001800Y0050555D01*
+X0001800Y0050853D02*
+X0008050Y0050853D01*
+X0008050Y0051152D02*
+X0001800Y0051152D01*
+X0001800Y0051450D02*
+X0008050Y0051450D01*
+X0008050Y0051749D02*
+X0001800Y0051749D01*
+X0001800Y0052047D02*
+X0008050Y0052047D01*
+X0008050Y0052346D02*
+X0001800Y0052346D01*
+X0001800Y0052644D02*
+X0008050Y0052644D01*
+X0008050Y0052943D02*
+X0001800Y0052943D01*
+X0001800Y0053241D02*
+X0008050Y0053241D01*
+X0008050Y0053540D02*
+X0001800Y0053540D01*
+X0001800Y0053838D02*
+X0008050Y0053838D01*
+X0008050Y0054137D02*
+X0001800Y0054137D01*
+X0001800Y0054435D02*
+X0008050Y0054435D01*
+X0008050Y0054734D02*
+X0001800Y0054734D01*
+X0001800Y0055032D02*
+X0008050Y0055032D01*
+X0008050Y0055331D02*
+X0001800Y0055331D01*
+X0001800Y0055629D02*
+X0008050Y0055629D01*
+X0008050Y0055928D02*
+X0001800Y0055928D01*
+X0001800Y0056226D02*
+X0008050Y0056226D01*
+X0008050Y0056525D02*
+X0001800Y0056525D01*
+X0001800Y0056823D02*
+X0008050Y0056823D01*
+X0008050Y0057122D02*
+X0001800Y0057122D01*
+X0001800Y0057420D02*
+X0008050Y0057420D01*
+X0008050Y0057719D02*
+X0001800Y0057719D01*
+X0001800Y0058017D02*
+X0008050Y0058017D01*
+X0008050Y0058316D02*
+X0001800Y0058316D01*
+X0001800Y0058614D02*
+X0008050Y0058614D01*
+X0008050Y0058913D02*
+X0001800Y0058913D01*
+X0001800Y0059211D02*
+X0008050Y0059211D01*
+X0008050Y0059510D02*
+X0001800Y0059510D01*
+X0001800Y0059809D02*
+X0008050Y0059809D01*
+X0008050Y0060107D02*
+X0001800Y0060107D01*
+X0001800Y0060406D02*
+X0008050Y0060406D01*
+X0008050Y0060704D02*
+X0001800Y0060704D01*
+X0001800Y0061003D02*
+X0008050Y0061003D01*
+X0008050Y0061301D02*
+X0001800Y0061301D01*
+X0001800Y0061600D02*
+X0008050Y0061600D01*
+X0008050Y0061898D02*
+X0001800Y0061898D01*
+X0001800Y0062197D02*
+X0008050Y0062197D01*
+X0008050Y0062495D02*
+X0001800Y0062495D01*
+X0001800Y0062794D02*
+X0008050Y0062794D01*
+X0008050Y0063092D02*
+X0001800Y0063092D01*
+X0001800Y0063391D02*
+X0008050Y0063391D01*
+X0008050Y0063689D02*
+X0001800Y0063689D01*
+X0001800Y0063988D02*
+X0008050Y0063988D01*
+X0008050Y0064286D02*
+X0001800Y0064286D01*
+X0001800Y0064585D02*
+X0008050Y0064585D01*
+X0008050Y0064883D02*
+X0001800Y0064883D01*
+X0001800Y0065182D02*
+X0008050Y0065182D01*
+X0008050Y0065480D02*
+X0001800Y0065480D01*
+X0001800Y0065779D02*
+X0008050Y0065779D01*
+X0008050Y0066077D02*
+X0001800Y0066077D01*
+X0001800Y0066376D02*
+X0008050Y0066376D01*
+X0008050Y0066674D02*
+X0001800Y0066674D01*
+X0001800Y0066973D02*
+X0008050Y0066973D01*
+X0008050Y0067271D02*
+X0001800Y0067271D01*
+X0001800Y0067570D02*
+X0008050Y0067570D01*
+X0008050Y0067868D02*
+X0001800Y0067868D01*
+X0001800Y0068167D02*
+X0008050Y0068167D01*
+X0008050Y0068465D02*
+X0001800Y0068465D01*
+X0001800Y0068764D02*
+X0008050Y0068764D01*
+X0008050Y0069062D02*
+X0001800Y0069062D01*
+X0001800Y0069361D02*
+X0008050Y0069361D01*
+X0008050Y0069659D02*
+X0001800Y0069659D01*
+X0001800Y0069958D02*
+X0008050Y0069958D01*
+X0008050Y0070256D02*
+X0001800Y0070256D01*
+X0001800Y0070555D02*
+X0008050Y0070555D01*
+X0008050Y0070853D02*
+X0001800Y0070853D01*
+X0001800Y0071152D02*
+X0008050Y0071152D01*
+X0008050Y0071450D02*
+X0001800Y0071450D01*
+X0001800Y0071749D02*
+X0008050Y0071749D01*
+X0008050Y0072047D02*
+X0001800Y0072047D01*
+X0001800Y0072346D02*
+X0008050Y0072346D01*
+X0008050Y0072644D02*
+X0001800Y0072644D01*
+X0001800Y0072943D02*
+X0008050Y0072943D01*
+X0008050Y0073242D02*
+X0001800Y0073242D01*
+X0001800Y0073540D02*
+X0008050Y0073540D01*
+X0008050Y0073839D02*
+X0001800Y0073839D01*
+X0001800Y0074137D02*
+X0008050Y0074137D01*
+X0008050Y0074436D02*
+X0001800Y0074436D01*
+X0001800Y0074734D02*
+X0008050Y0074734D01*
+X0008050Y0075033D02*
+X0001800Y0075033D01*
+X0001800Y0075331D02*
+X0008050Y0075331D01*
+X0008050Y0075630D02*
+X0001800Y0075630D01*
+X0001800Y0075928D02*
+X0008050Y0075928D01*
+X0008050Y0076227D02*
+X0001800Y0076227D01*
+X0001800Y0076525D02*
+X0008050Y0076525D01*
+X0008050Y0076824D02*
+X0001800Y0076824D01*
+X0001800Y0077122D02*
+X0008050Y0077122D01*
+X0008050Y0077421D02*
+X0001800Y0077421D01*
+X0001800Y0077719D02*
+X0008050Y0077719D01*
+X0008050Y0078018D02*
+X0001800Y0078018D01*
+X0001800Y0078316D02*
+X0008050Y0078316D01*
+X0008050Y0078615D02*
+X0001800Y0078615D01*
+X0001800Y0078913D02*
+X0008050Y0078913D01*
+X0008050Y0079212D02*
+X0001800Y0079212D01*
+X0001800Y0079510D02*
+X0008050Y0079510D01*
+X0008050Y0079809D02*
+X0001800Y0079809D01*
+X0001800Y0080107D02*
+X0008050Y0080107D01*
+X0008050Y0080406D02*
+X0001800Y0080406D01*
+X0001800Y0080704D02*
+X0008050Y0080704D01*
+X0008050Y0081003D02*
+X0001800Y0081003D01*
+X0001800Y0081301D02*
+X0008050Y0081301D01*
+X0008050Y0081600D02*
+X0001800Y0081600D01*
+X0001800Y0081898D02*
+X0008050Y0081898D01*
+X0008050Y0082197D02*
+X0001800Y0082197D01*
+X0001800Y0082495D02*
+X0008050Y0082495D01*
+X0008050Y0082794D02*
+X0001800Y0082794D01*
+X0001800Y0083092D02*
+X0008050Y0083092D01*
+X0008050Y0083391D02*
+X0001800Y0083391D01*
+X0001800Y0083689D02*
+X0008050Y0083689D01*
+X0008050Y0083988D02*
+X0001800Y0083988D01*
+X0001800Y0084286D02*
+X0008050Y0084286D01*
+X0008050Y0084585D02*
+X0001800Y0084585D01*
+X0001800Y0084883D02*
+X0008050Y0084883D01*
+X0008050Y0085182D02*
+X0001800Y0085182D01*
+X0001800Y0085480D02*
+X0008050Y0085480D01*
+X0008050Y0085779D02*
+X0001800Y0085779D01*
+X0001800Y0086077D02*
+X0008050Y0086077D01*
+X0008050Y0086376D02*
+X0001800Y0086376D01*
+X0001800Y0086675D02*
+X0008050Y0086675D01*
+X0008050Y0086973D02*
+X0001800Y0086973D01*
+X0001800Y0087272D02*
+X0008050Y0087272D01*
+X0008050Y0087570D02*
+X0001800Y0087570D01*
+X0001800Y0087869D02*
+X0008050Y0087869D01*
+X0008050Y0088167D02*
+X0001800Y0088167D01*
+X0001800Y0088466D02*
+X0008050Y0088466D01*
+X0008050Y0088764D02*
+X0001800Y0088764D01*
+X0001800Y0089063D02*
+X0008050Y0089063D01*
+X0008050Y0089361D02*
+X0001800Y0089361D01*
+X0001800Y0089660D02*
+X0008050Y0089660D01*
+X0008050Y0089958D02*
+X0001800Y0089958D01*
+X0001800Y0090257D02*
+X0008050Y0090257D01*
+X0008050Y0090555D02*
+X0001800Y0090555D01*
+X0001800Y0090854D02*
+X0008050Y0090854D01*
+X0008050Y0091152D02*
+X0001800Y0091152D01*
+X0001800Y0091451D02*
+X0008050Y0091451D01*
+X0008050Y0091749D02*
+X0001800Y0091749D01*
+X0001800Y0092048D02*
+X0008050Y0092048D01*
+X0008050Y0092346D02*
+X0001800Y0092346D01*
+X0001800Y0092645D02*
+X0008050Y0092645D01*
+X0008050Y0092943D02*
+X0001800Y0092943D01*
+X0001800Y0093242D02*
+X0008050Y0093242D01*
+X0008050Y0093540D02*
+X0001800Y0093540D01*
+X0001800Y0093839D02*
+X0008050Y0093839D01*
+X0008050Y0094137D02*
+X0001800Y0094137D01*
+X0001800Y0094436D02*
+X0008050Y0094436D01*
+X0008050Y0094734D02*
+X0001800Y0094734D01*
+X0001800Y0095033D02*
+X0008050Y0095033D01*
+X0008050Y0095331D02*
+X0001800Y0095331D01*
+X0001800Y0095630D02*
+X0008050Y0095630D01*
+X0008050Y0095928D02*
+X0001800Y0095928D01*
+X0001800Y0096227D02*
+X0008050Y0096227D01*
+X0008050Y0096525D02*
+X0001800Y0096525D01*
+X0001800Y0096824D02*
+X0008050Y0096824D01*
+X0008050Y0097122D02*
+X0001800Y0097122D01*
+X0001800Y0097421D02*
+X0008050Y0097421D01*
+X0008050Y0097719D02*
+X0001800Y0097719D01*
+X0001800Y0098018D02*
+X0008050Y0098018D01*
+X0008050Y0098316D02*
+X0001800Y0098316D01*
+X0001800Y0098615D02*
+X0008050Y0098615D01*
+X0008050Y0098913D02*
+X0001800Y0098913D01*
+X0001800Y0099212D02*
+X0008050Y0099212D01*
+X0008050Y0099511D02*
+X0001800Y0099511D01*
+X0001800Y0099809D02*
+X0008050Y0099809D01*
+X0008050Y0100108D02*
+X0001800Y0100108D01*
+X0001800Y0100406D02*
+X0008050Y0100406D01*
+X0008050Y0100705D02*
+X0001800Y0100705D01*
+X0001800Y0101003D02*
+X0008050Y0101003D01*
+X0008050Y0101302D02*
+X0001800Y0101302D01*
+X0001800Y0101600D02*
+X0008050Y0101600D01*
+X0008050Y0101899D02*
+X0001800Y0101899D01*
+X0001800Y0102197D02*
+X0008050Y0102197D01*
+X0008050Y0102496D02*
+X0001800Y0102496D01*
+X0001800Y0102794D02*
+X0008050Y0102794D01*
+X0008050Y0103093D02*
+X0001800Y0103093D01*
+X0001800Y0103391D02*
+X0008050Y0103391D01*
+X0008050Y0103690D02*
+X0001800Y0103690D01*
+X0001800Y0103988D02*
+X0008050Y0103988D01*
+X0008050Y0104287D02*
+X0001800Y0104287D01*
+X0001800Y0104585D02*
+X0008050Y0104585D01*
+X0008050Y0104884D02*
+X0001800Y0104884D01*
+X0001800Y0105182D02*
+X0008050Y0105182D01*
+X0008050Y0105481D02*
+X0001800Y0105481D01*
+X0001800Y0105779D02*
+X0008050Y0105779D01*
+X0008050Y0106078D02*
+X0001800Y0106078D01*
+X0001800Y0106376D02*
+X0008050Y0106376D01*
+X0008050Y0106675D02*
+X0001800Y0106675D01*
+X0001800Y0106973D02*
+X0008050Y0106973D01*
+X0008050Y0107272D02*
+X0001800Y0107272D01*
+X0001800Y0107570D02*
+X0008050Y0107570D01*
+X0008050Y0107869D02*
+X0001800Y0107869D01*
+X0001800Y0108167D02*
+X0008050Y0108167D01*
+X0008050Y0108466D02*
+X0001800Y0108466D01*
+X0001800Y0108764D02*
+X0008050Y0108764D01*
+X0008050Y0109063D02*
+X0001800Y0109063D01*
+X0001800Y0109361D02*
+X0008050Y0109361D01*
+X0008050Y0109660D02*
+X0001800Y0109660D01*
+X0001800Y0109958D02*
+X0008050Y0109958D01*
+X0008050Y0110257D02*
+X0001800Y0110257D01*
+X0001800Y0110555D02*
+X0008050Y0110555D01*
+X0008050Y0110854D02*
+X0001800Y0110854D01*
+X0001800Y0111152D02*
+X0008050Y0111152D01*
+X0008050Y0111451D02*
+X0001800Y0111451D01*
+X0001800Y0111749D02*
+X0008050Y0111749D01*
+X0008050Y0112048D02*
+X0001800Y0112048D01*
+X0001800Y0112346D02*
+X0008050Y0112346D01*
+X0008050Y0112645D02*
+X0001800Y0112645D01*
+X0001800Y0112944D02*
+X0008050Y0112944D01*
+X0008050Y0113242D02*
+X0001800Y0113242D01*
+X0001800Y0113541D02*
+X0008050Y0113541D01*
+X0008050Y0113839D02*
+X0001800Y0113839D01*
+X0001800Y0114138D02*
+X0008050Y0114138D01*
+X0008050Y0114436D02*
+X0001800Y0114436D01*
+X0001800Y0114735D02*
+X0008050Y0114735D01*
+X0008050Y0115033D02*
+X0001800Y0115033D01*
+X0001800Y0115332D02*
+X0008050Y0115332D01*
+X0008050Y0115630D02*
+X0001800Y0115630D01*
+X0001800Y0115929D02*
+X0008050Y0115929D01*
+X0008050Y0116227D02*
+X0001800Y0116227D01*
+X0001800Y0116526D02*
+X0008050Y0116526D01*
+X0008050Y0116824D02*
+X0001800Y0116824D01*
+X0001800Y0117123D02*
+X0008050Y0117123D01*
+X0008050Y0117421D02*
+X0001800Y0117421D01*
+X0001800Y0117720D02*
+X0008050Y0117720D01*
+X0008050Y0118018D02*
+X0001800Y0118018D01*
+X0001800Y0118317D02*
+X0008050Y0118317D01*
+X0008050Y0118615D02*
+X0001800Y0118615D01*
+X0001800Y0118914D02*
+X0008050Y0118914D01*
+X0008050Y0119212D02*
+X0001800Y0119212D01*
+X0001800Y0119511D02*
+X0008050Y0119511D01*
+X0008050Y0119809D02*
+X0001800Y0119809D01*
+X0001800Y0120108D02*
+X0008050Y0120108D01*
+X0008050Y0120406D02*
+X0001800Y0120406D01*
+X0001800Y0120705D02*
+X0008050Y0120705D01*
+X0008050Y0121003D02*
+X0001800Y0121003D01*
+X0001800Y0121302D02*
+X0008050Y0121302D01*
+X0008050Y0121600D02*
+X0001800Y0121600D01*
+X0001800Y0121899D02*
+X0008050Y0121899D01*
+X0008050Y0122197D02*
+X0001800Y0122197D01*
+X0001800Y0122496D02*
+X0008050Y0122496D01*
+X0008050Y0122794D02*
+X0001800Y0122794D01*
+X0001800Y0123093D02*
+X0008050Y0123093D01*
+X0008050Y0123391D02*
+X0001800Y0123391D01*
+X0001800Y0123690D02*
+X0008050Y0123690D01*
+X0008050Y0123988D02*
+X0001800Y0123988D01*
+X0001800Y0124287D02*
+X0008050Y0124287D01*
+X0008050Y0124585D02*
+X0001800Y0124585D01*
+X0001800Y0124884D02*
+X0008050Y0124884D01*
+X0008050Y0125182D02*
+X0001800Y0125182D01*
+X0001800Y0125481D02*
+X0008050Y0125481D01*
+X0008050Y0125780D02*
+X0001800Y0125780D01*
+X0001800Y0126078D02*
+X0008050Y0126078D01*
+X0008050Y0126377D02*
+X0001800Y0126377D01*
+X0001800Y0126675D02*
+X0008050Y0126675D01*
+X0008050Y0126974D02*
+X0001800Y0126974D01*
+X0001800Y0127272D02*
+X0008050Y0127272D01*
+X0008050Y0127571D02*
+X0001800Y0127571D01*
+X0001800Y0127869D02*
+X0008050Y0127869D01*
+X0008050Y0128168D02*
+X0001800Y0128168D01*
+X0001800Y0128466D02*
+X0008050Y0128466D01*
+X0008050Y0128765D02*
+X0001800Y0128765D01*
+X0001800Y0129063D02*
+X0008050Y0129063D01*
+X0008050Y0129362D02*
+X0001800Y0129362D01*
+X0001800Y0129660D02*
+X0008050Y0129660D01*
+X0008050Y0129959D02*
+X0001800Y0129959D01*
+X0001800Y0130257D02*
+X0008050Y0130257D01*
+X0008050Y0130556D02*
+X0001800Y0130556D01*
+X0001800Y0130854D02*
+X0008050Y0130854D01*
+X0008050Y0131153D02*
+X0001800Y0131153D01*
+X0001800Y0131451D02*
+X0008050Y0131451D01*
+X0008050Y0131750D02*
+X0001800Y0131750D01*
+X0001800Y0132048D02*
+X0008050Y0132048D01*
+X0008050Y0132347D02*
+X0001800Y0132347D01*
+X0001800Y0132645D02*
+X0008050Y0132645D01*
+X0008050Y0132944D02*
+X0001800Y0132944D01*
+X0001800Y0133242D02*
+X0008050Y0133242D01*
+X0008050Y0133541D02*
+X0001800Y0133541D01*
+X0001800Y0133839D02*
+X0008050Y0133839D01*
+X0008050Y0134138D02*
+X0001800Y0134138D01*
+X0001800Y0134436D02*
+X0008050Y0134436D01*
+X0008050Y0134735D02*
+X0001800Y0134735D01*
+X0001800Y0135033D02*
+X0008050Y0135033D01*
+X0008050Y0135332D02*
+X0001800Y0135332D01*
+X0001800Y0135630D02*
+X0008050Y0135630D01*
+X0008050Y0135929D02*
+X0001800Y0135929D01*
+X0001800Y0136227D02*
+X0008050Y0136227D01*
+X0008050Y0136526D02*
+X0001800Y0136526D01*
+X0001800Y0136824D02*
+X0008050Y0136824D01*
+X0008050Y0137123D02*
+X0001800Y0137123D01*
+X0001800Y0137421D02*
+X0008050Y0137421D01*
+X0008050Y0137720D02*
+X0001800Y0137720D01*
+X0001800Y0138018D02*
+X0008050Y0138018D01*
+X0008050Y0138317D02*
+X0001800Y0138317D01*
+X0001800Y0138615D02*
+X0008050Y0138615D01*
+X0008050Y0138914D02*
+X0001800Y0138914D01*
+X0001800Y0139213D02*
+X0008050Y0139213D01*
+X0008050Y0139511D02*
+X0001800Y0139511D01*
+X0001800Y0139810D02*
+X0008050Y0139810D01*
+X0008050Y0140108D02*
+X0001800Y0140108D01*
+X0001800Y0140407D02*
+X0008050Y0140407D01*
+X0008050Y0140705D02*
+X0001800Y0140705D01*
+X0001800Y0141004D02*
+X0008050Y0141004D01*
+X0008050Y0141302D02*
+X0001800Y0141302D01*
+X0001800Y0141601D02*
+X0008050Y0141601D01*
+X0008050Y0141899D02*
+X0001800Y0141899D01*
+X0001800Y0142198D02*
+X0008050Y0142198D01*
+X0008050Y0142496D02*
+X0001800Y0142496D01*
+X0001800Y0142795D02*
+X0008050Y0142795D01*
+X0008050Y0143093D02*
+X0001800Y0143093D01*
+X0001800Y0143392D02*
+X0008050Y0143392D01*
+X0008050Y0143690D02*
+X0001800Y0143690D01*
+X0001800Y0143989D02*
+X0008050Y0143989D01*
+X0008050Y0144287D02*
+X0001800Y0144287D01*
+X0001800Y0144586D02*
+X0008050Y0144586D01*
+X0008050Y0144884D02*
+X0001800Y0144884D01*
+X0001800Y0145183D02*
+X0008050Y0145183D01*
+X0008050Y0145481D02*
+X0001800Y0145481D01*
+X0001800Y0145780D02*
+X0008050Y0145780D01*
+X0008050Y0146078D02*
+X0001800Y0146078D01*
+X0001800Y0146377D02*
+X0008050Y0146377D01*
+X0008050Y0146675D02*
+X0001800Y0146675D01*
+X0001800Y0146974D02*
+X0008050Y0146974D01*
+X0008050Y0147272D02*
+X0001800Y0147272D01*
+X0001800Y0147571D02*
+X0008050Y0147571D01*
+X0008050Y0147869D02*
+X0001800Y0147869D01*
+X0001800Y0148168D02*
+X0008050Y0148168D01*
+X0008050Y0148466D02*
+X0001800Y0148466D01*
+X0001800Y0148765D02*
+X0008050Y0148765D01*
+X0008050Y0149063D02*
+X0001800Y0149063D01*
+X0001800Y0149362D02*
+X0008050Y0149362D01*
+X0008050Y0149660D02*
+X0001800Y0149660D01*
+X0001800Y0149959D02*
+X0008050Y0149959D01*
+X0008050Y0150257D02*
+X0001800Y0150257D01*
+X0001800Y0150556D02*
+X0008050Y0150556D01*
+X0008050Y0150854D02*
+X0001800Y0150854D01*
+X0001800Y0151153D02*
+X0008050Y0151153D01*
+X0008050Y0151451D02*
+X0001800Y0151451D01*
+X0001800Y0151750D02*
+X0008050Y0151750D01*
+X0008050Y0152048D02*
+X0001800Y0152048D01*
+X0001800Y0152347D02*
+X0008050Y0152347D01*
+X0008050Y0152646D02*
+X0001800Y0152646D01*
+X0001800Y0152944D02*
+X0008050Y0152944D01*
+X0008050Y0153243D02*
+X0001800Y0153243D01*
+X0001800Y0153541D02*
+X0008050Y0153541D01*
+X0008050Y0153840D02*
+X0001800Y0153840D01*
+X0001800Y0154138D02*
+X0008050Y0154138D01*
+X0008050Y0154437D02*
+X0001800Y0154437D01*
+X0001800Y0154735D02*
+X0008050Y0154735D01*
+X0008050Y0155034D02*
+X0001800Y0155034D01*
+X0001800Y0155332D02*
+X0008050Y0155332D01*
+X0008050Y0155631D02*
+X0001800Y0155631D01*
+X0001800Y0155929D02*
+X0008050Y0155929D01*
+X0008050Y0156228D02*
+X0001800Y0156228D01*
+X0001800Y0156526D02*
+X0008050Y0156526D01*
+X0008050Y0156825D02*
+X0001800Y0156825D01*
+X0001800Y0157123D02*
+X0008050Y0157123D01*
+X0008050Y0157422D02*
+X0001800Y0157422D01*
+X0001800Y0157720D02*
+X0008050Y0157720D01*
+X0008050Y0158019D02*
+X0001800Y0158019D01*
+X0001800Y0158317D02*
+X0008050Y0158317D01*
+X0008050Y0158616D02*
+X0001800Y0158616D01*
+X0001800Y0158914D02*
+X0008050Y0158914D01*
+X0008050Y0159213D02*
+X0001800Y0159213D01*
+X0001800Y0159511D02*
+X0008050Y0159511D01*
+X0008050Y0159810D02*
+X0001800Y0159810D01*
+X0001800Y0160108D02*
+X0008050Y0160108D01*
+X0008050Y0160407D02*
+X0001800Y0160407D01*
+X0001800Y0160705D02*
+X0008050Y0160705D01*
+X0008050Y0161004D02*
+X0001800Y0161004D01*
+X0001800Y0161302D02*
+X0008050Y0161302D01*
+X0008050Y0161601D02*
+X0001800Y0161601D01*
+X0001800Y0161899D02*
+X0008050Y0161899D01*
+X0008050Y0162198D02*
+X0001800Y0162198D01*
+X0001800Y0162496D02*
+X0008050Y0162496D01*
+X0008050Y0162795D02*
+X0001800Y0162795D01*
+X0001800Y0163093D02*
+X0008050Y0163093D01*
+X0008050Y0163392D02*
+X0001800Y0163392D01*
+X0001800Y0163690D02*
+X0008050Y0163690D01*
+X0008050Y0163989D02*
+X0001800Y0163989D01*
+X0001800Y0164287D02*
+X0008050Y0164287D01*
+X0008050Y0164586D02*
+X0001800Y0164586D01*
+X0001800Y0164884D02*
+X0008050Y0164884D01*
+X0008050Y0165183D02*
+X0001800Y0165183D01*
+X0001800Y0165482D02*
+X0008050Y0165482D01*
+X0008050Y0165780D02*
+X0001800Y0165780D01*
+X0001800Y0166079D02*
+X0008050Y0166079D01*
+X0008050Y0166377D02*
+X0001800Y0166377D01*
+X0001800Y0166676D02*
+X0008050Y0166676D01*
+X0008050Y0166974D02*
+X0001800Y0166974D01*
+X0001800Y0167273D02*
+X0008050Y0167273D01*
+X0008050Y0167571D02*
+X0001800Y0167571D01*
+X0001800Y0167870D02*
+X0008050Y0167870D01*
+X0008050Y0168168D02*
+X0001800Y0168168D01*
+X0001800Y0168467D02*
+X0008050Y0168467D01*
+X0008050Y0168765D02*
+X0001800Y0168765D01*
+X0001800Y0169064D02*
+X0008050Y0169064D01*
+X0008050Y0169362D02*
+X0001800Y0169362D01*
+X0001800Y0169661D02*
+X0008050Y0169661D01*
+X0008050Y0169959D02*
+X0001800Y0169959D01*
+X0001800Y0170258D02*
+X0008050Y0170258D01*
+X0008050Y0170556D02*
+X0001800Y0170556D01*
+X0001800Y0170855D02*
+X0008050Y0170855D01*
+X0008050Y0171153D02*
+X0001800Y0171153D01*
+X0001800Y0171452D02*
+X0008050Y0171452D01*
+X0008050Y0171750D02*
+X0001800Y0171750D01*
+X0001800Y0172049D02*
+X0008050Y0172049D01*
+X0008050Y0172347D02*
+X0001800Y0172347D01*
+X0001800Y0172646D02*
+X0008050Y0172646D01*
+X0008050Y0172944D02*
+X0001800Y0172944D01*
+X0001800Y0173243D02*
+X0008050Y0173243D01*
+X0008050Y0173541D02*
+X0001800Y0173541D01*
+X0001800Y0173840D02*
+X0008050Y0173840D01*
+X0008050Y0174138D02*
+X0001800Y0174138D01*
+X0001800Y0174437D02*
+X0008050Y0174437D01*
+X0008050Y0174735D02*
+X0001800Y0174735D01*
+X0001800Y0175034D02*
+X0008050Y0175034D01*
+X0008050Y0175332D02*
+X0001800Y0175332D01*
+X0001800Y0175631D02*
+X0008050Y0175631D01*
+X0008050Y0175929D02*
+X0001800Y0175929D01*
+X0001800Y0176228D02*
+X0008050Y0176228D01*
+X0008050Y0176526D02*
+X0001800Y0176526D01*
+X0001800Y0176825D02*
+X0008050Y0176825D01*
+X0008050Y0177123D02*
+X0001800Y0177123D01*
+X0001800Y0177422D02*
+X0008050Y0177422D01*
+X0008050Y0177720D02*
+X0001800Y0177720D01*
+X0001800Y0178019D02*
+X0008050Y0178019D01*
+X0008050Y0178317D02*
+X0001800Y0178317D01*
+X0001800Y0178616D02*
+X0008050Y0178616D01*
+X0008050Y0178915D02*
+X0001800Y0178915D01*
+X0001800Y0179213D02*
+X0008050Y0179213D01*
+X0008050Y0179512D02*
+X0001800Y0179512D01*
+X0001800Y0179810D02*
+X0008050Y0179810D01*
+X0008050Y0180109D02*
+X0001800Y0180109D01*
+X0001800Y0180407D02*
+X0008050Y0180407D01*
+X0008050Y0180706D02*
+X0001800Y0180706D01*
+X0001800Y0181004D02*
+X0008050Y0181004D01*
+X0008050Y0181303D02*
+X0001800Y0181303D01*
+X0001800Y0181601D02*
+X0008050Y0181601D01*
+X0008050Y0181900D02*
+X0001800Y0181900D01*
+X0001800Y0182198D02*
+X0008050Y0182198D01*
+X0008050Y0182497D02*
+X0001800Y0182497D01*
+X0001800Y0182795D02*
+X0008050Y0182795D01*
+X0008050Y0183094D02*
+X0001800Y0183094D01*
+X0001800Y0183392D02*
+X0008050Y0183392D01*
+X0008050Y0183691D02*
+X0001800Y0183691D01*
+X0001800Y0183989D02*
+X0008050Y0183989D01*
+X0008050Y0184288D02*
+X0001800Y0184288D01*
+X0001800Y0184586D02*
+X0008050Y0184586D01*
+X0008050Y0184885D02*
+X0001800Y0184885D01*
+X0001800Y0185183D02*
+X0008050Y0185183D01*
+X0008050Y0185482D02*
+X0001800Y0185482D01*
+X0001800Y0185780D02*
+X0008050Y0185780D01*
+X0008050Y0186079D02*
+X0001800Y0186079D01*
+X0001800Y0186377D02*
+X0008050Y0186377D01*
+X0008050Y0186676D02*
+X0001800Y0186676D01*
+X0001800Y0186974D02*
+X0008050Y0186974D01*
+X0008050Y0187273D02*
+X0001800Y0187273D01*
+X0001800Y0187571D02*
+X0008050Y0187571D01*
+X0008050Y0187870D02*
+X0001800Y0187870D01*
+X0001800Y0188168D02*
+X0008050Y0188168D01*
+X0008050Y0188467D02*
+X0001800Y0188467D01*
+X0001800Y0188765D02*
+X0008050Y0188765D01*
+X0008050Y0189064D02*
+X0001800Y0189064D01*
+X0001800Y0189362D02*
+X0008050Y0189362D01*
+X0008050Y0189661D02*
+X0001800Y0189661D01*
+X0001800Y0189959D02*
+X0008050Y0189959D01*
+X0008050Y0190258D02*
+X0001800Y0190258D01*
+X0001800Y0190556D02*
+X0008050Y0190556D01*
+X0008050Y0190855D02*
+X0001800Y0190855D01*
+X0001800Y0191153D02*
+X0008050Y0191153D01*
+X0008050Y0191452D02*
+X0001800Y0191452D01*
+X0001800Y0191751D02*
+X0008050Y0191751D01*
+X0008050Y0192049D02*
+X0001800Y0192049D01*
+X0001800Y0192348D02*
+X0008050Y0192348D01*
+X0008050Y0192646D02*
+X0001800Y0192646D01*
+X0001800Y0192945D02*
+X0008050Y0192945D01*
+X0008050Y0193243D02*
+X0001800Y0193243D01*
+X0001800Y0193542D02*
+X0008050Y0193542D01*
+X0008050Y0193840D02*
+X0001800Y0193840D01*
+X0001800Y0194139D02*
+X0008050Y0194139D01*
+X0008050Y0194437D02*
+X0001800Y0194437D01*
+X0001800Y0194736D02*
+X0008050Y0194736D01*
+X0008050Y0195034D02*
+X0001800Y0195034D01*
+X0001800Y0195333D02*
+X0008050Y0195333D01*
+X0008050Y0195631D02*
+X0001800Y0195631D01*
+X0001800Y0195930D02*
+X0008050Y0195930D01*
+X0008050Y0196228D02*
+X0001800Y0196228D01*
+X0001800Y0196527D02*
+X0008050Y0196527D01*
+X0008050Y0196825D02*
+X0001800Y0196825D01*
+X0001800Y0197124D02*
+X0008050Y0197124D01*
+X0008050Y0197422D02*
+X0001800Y0197422D01*
+X0001800Y0197721D02*
+X0008050Y0197721D01*
+X0008050Y0198019D02*
+X0001800Y0198019D01*
+X0001800Y0198318D02*
+X0008050Y0198318D01*
+X0008050Y0198616D02*
+X0001800Y0198616D01*
+X0001800Y0198915D02*
+X0008050Y0198915D01*
+X0008050Y0199213D02*
+X0001800Y0199213D01*
+X0001800Y0199512D02*
+X0008050Y0199512D01*
+X0008050Y0199810D02*
+X0001800Y0199810D01*
+X0001800Y0200109D02*
+X0008050Y0200109D01*
+X0008050Y0200407D02*
+X0001800Y0200407D01*
+X0001800Y0200706D02*
+X0008050Y0200706D01*
+X0008050Y0201004D02*
+X0001800Y0201004D01*
+X0001800Y0201303D02*
+X0008050Y0201303D01*
+X0008050Y0201601D02*
+X0001800Y0201601D01*
+X0001800Y0201900D02*
+X0008050Y0201900D01*
+X0008050Y0202198D02*
+X0001800Y0202198D01*
+X0001800Y0202497D02*
+X0008050Y0202497D01*
+X0008050Y0202795D02*
+X0001800Y0202795D01*
+X0001800Y0203094D02*
+X0008050Y0203094D01*
+X0008050Y0203392D02*
+X0001800Y0203392D01*
+X0001800Y0203691D02*
+X0008050Y0203691D01*
+X0008050Y0203989D02*
+X0001800Y0203989D01*
+X0001800Y0204288D02*
+X0008050Y0204288D01*
+X0008050Y0204586D02*
+X0001800Y0204586D01*
+X0001800Y0204885D02*
+X0008050Y0204885D01*
+X0008050Y0205184D02*
+X0001800Y0205184D01*
+X0001800Y0205482D02*
+X0008050Y0205482D01*
+X0008050Y0205781D02*
+X0001800Y0205781D01*
+X0001800Y0206079D02*
+X0008050Y0206079D01*
+X0008050Y0206378D02*
+X0001800Y0206378D01*
+X0001800Y0206676D02*
+X0008050Y0206676D01*
+X0008050Y0206975D02*
+X0001800Y0206975D01*
+X0001800Y0207273D02*
+X0008050Y0207273D01*
+X0008050Y0207572D02*
+X0001800Y0207572D01*
+X0001800Y0207870D02*
+X0008050Y0207870D01*
+X0008050Y0208169D02*
+X0001800Y0208169D01*
+X0001800Y0208467D02*
+X0008050Y0208467D01*
+X0008050Y0208766D02*
+X0001800Y0208766D01*
+X0001800Y0209064D02*
+X0008050Y0209064D01*
+X0008050Y0209363D02*
+X0001800Y0209363D01*
+X0001800Y0209661D02*
+X0008050Y0209661D01*
+X0008050Y0209960D02*
+X0001800Y0209960D01*
+X0001800Y0210258D02*
+X0008050Y0210258D01*
+X0008050Y0210557D02*
+X0001800Y0210557D01*
+X0001800Y0210855D02*
+X0008050Y0210855D01*
+X0008050Y0211154D02*
+X0001800Y0211154D01*
+X0001800Y0211452D02*
+X0008050Y0211452D01*
+X0008050Y0211751D02*
+X0001800Y0211751D01*
+X0001800Y0212049D02*
+X0008050Y0212049D01*
+X0008050Y0212348D02*
+X0001800Y0212348D01*
+X0001800Y0212646D02*
+X0008050Y0212646D01*
+X0008050Y0212945D02*
+X0001800Y0212945D01*
+X0001800Y0213243D02*
+X0008050Y0213243D01*
+X0008050Y0213542D02*
+X0001800Y0213542D01*
+X0001800Y0213840D02*
+X0008050Y0213840D01*
+X0008050Y0214139D02*
+X0001800Y0214139D01*
+X0001800Y0214437D02*
+X0008050Y0214437D01*
+X0008050Y0214736D02*
+X0001800Y0214736D01*
+X0001800Y0215034D02*
+X0008050Y0215034D01*
+X0008050Y0215333D02*
+X0001800Y0215333D01*
+X0001800Y0215631D02*
+X0008050Y0215631D01*
+X0008050Y0215930D02*
+X0001800Y0215930D01*
+X0001800Y0216228D02*
+X0008050Y0216228D01*
+X0008050Y0216527D02*
+X0001800Y0216527D01*
+X0001800Y0216825D02*
+X0008050Y0216825D01*
+X0008050Y0217124D02*
+X0001800Y0217124D01*
+X0001800Y0217422D02*
+X0008050Y0217422D01*
+X0008050Y0217721D02*
+X0001800Y0217721D01*
+X0001800Y0218020D02*
+X0008050Y0218020D01*
+X0008050Y0218318D02*
+X0001800Y0218318D01*
+X0001800Y0218617D02*
+X0008050Y0218617D01*
+X0008050Y0218915D02*
+X0001800Y0218915D01*
+X0001800Y0219214D02*
+X0008050Y0219214D01*
+X0008050Y0219512D02*
+X0001800Y0219512D01*
+X0001800Y0219811D02*
+X0008050Y0219811D01*
+X0008050Y0220109D02*
+X0001800Y0220109D01*
+X0001800Y0220408D02*
+X0008050Y0220408D01*
+X0008050Y0220706D02*
+X0001800Y0220706D01*
+X0001800Y0221005D02*
+X0008050Y0221005D01*
+X0008050Y0221303D02*
+X0001800Y0221303D01*
+X0001800Y0221602D02*
+X0008050Y0221602D01*
+X0008050Y0221900D02*
+X0001800Y0221900D01*
+X0001800Y0222199D02*
+X0008050Y0222199D01*
+X0008050Y0222497D02*
+X0001800Y0222497D01*
+X0001800Y0222796D02*
+X0008050Y0222796D01*
+X0008050Y0223094D02*
+X0001800Y0223094D01*
+X0001800Y0223393D02*
+X0008050Y0223393D01*
+X0008050Y0223691D02*
+X0001800Y0223691D01*
+X0001800Y0223990D02*
+X0008050Y0223990D01*
+X0008050Y0224288D02*
+X0001800Y0224288D01*
+X0001800Y0224587D02*
+X0008050Y0224587D01*
+X0008050Y0224885D02*
+X0001800Y0224885D01*
+X0001800Y0225184D02*
+X0008050Y0225184D01*
+X0008050Y0225482D02*
+X0001800Y0225482D01*
+X0001800Y0225781D02*
+X0008050Y0225781D01*
+X0008050Y0226079D02*
+X0001800Y0226079D01*
+X0001800Y0226378D02*
+X0008050Y0226378D01*
+X0008050Y0226676D02*
+X0001800Y0226676D01*
+X0001800Y0226975D02*
+X0008050Y0226975D01*
+X0008050Y0227273D02*
+X0001800Y0227273D01*
+X0001800Y0227572D02*
+X0008050Y0227572D01*
+X0008050Y0227870D02*
+X0001800Y0227870D01*
+X0001800Y0228169D02*
+X0008050Y0228169D01*
+X0008050Y0228467D02*
+X0001800Y0228467D01*
+X0001800Y0228766D02*
+X0008050Y0228766D01*
+X0008050Y0229064D02*
+X0001800Y0229064D01*
+X0001800Y0229363D02*
+X0008050Y0229363D01*
+X0008050Y0229661D02*
+X0001800Y0229661D01*
+X0001800Y0229960D02*
+X0008050Y0229960D01*
+X0008050Y0230258D02*
+X0001800Y0230258D01*
+X0001800Y0230557D02*
+X0008050Y0230557D01*
+X0008050Y0230855D02*
+X0001800Y0230855D01*
+X0001800Y0231154D02*
+X0008050Y0231154D01*
+X0008050Y0231453D02*
+X0001800Y0231453D01*
+X0001800Y0231751D02*
+X0008050Y0231751D01*
+X0008050Y0232050D02*
+X0001800Y0232050D01*
+X0001800Y0232348D02*
+X0008050Y0232348D01*
+X0008050Y0232647D02*
+X0001800Y0232647D01*
+X0001800Y0232945D02*
+X0008050Y0232945D01*
+X0008050Y0233244D02*
+X0001800Y0233244D01*
+X0001800Y0233542D02*
+X0008050Y0233542D01*
+X0008050Y0233841D02*
+X0001800Y0233841D01*
+X0001800Y0234139D02*
+X0008050Y0234139D01*
+X0008050Y0234438D02*
+X0001800Y0234438D01*
+X0001800Y0234736D02*
+X0008050Y0234736D01*
+X0008050Y0235035D02*
+X0001800Y0235035D01*
+X0001800Y0235333D02*
+X0008050Y0235333D01*
+X0008050Y0235632D02*
+X0001800Y0235632D01*
+X0001800Y0235930D02*
+X0008050Y0235930D01*
+X0008050Y0236229D02*
+X0001800Y0236229D01*
+X0001800Y0236527D02*
+X0008050Y0236527D01*
+X0008050Y0236826D02*
+X0001800Y0236826D01*
+X0001800Y0237124D02*
+X0008050Y0237124D01*
+X0008050Y0237423D02*
+X0001800Y0237423D01*
+X0001800Y0237721D02*
+X0008050Y0237721D01*
+X0008050Y0238020D02*
+X0001800Y0238020D01*
+X0001800Y0238318D02*
+X0008050Y0238318D01*
+X0008050Y0238617D02*
+X0001800Y0238617D01*
+X0001800Y0238915D02*
+X0008050Y0238915D01*
+X0008050Y0239214D02*
+X0001800Y0239214D01*
+X0001800Y0239512D02*
+X0008050Y0239512D01*
+X0008050Y0239811D02*
+X0001800Y0239811D01*
+X0001800Y0240109D02*
+X0008050Y0240109D01*
+X0008050Y0240408D02*
+X0001800Y0240408D01*
+X0001800Y0240706D02*
+X0008050Y0240706D01*
+X0008050Y0241005D02*
+X0001800Y0241005D01*
+X0001800Y0241303D02*
+X0008050Y0241303D01*
+X0008050Y0241602D02*
+X0001800Y0241602D01*
+X0001800Y0241900D02*
+X0008050Y0241900D01*
+X0008050Y0242199D02*
+X0001800Y0242199D01*
+X0001800Y0242497D02*
+X0008050Y0242497D01*
+X0008050Y0242796D02*
+X0001800Y0242796D01*
+X0001800Y0243094D02*
+X0008050Y0243094D01*
+X0008050Y0243393D02*
+X0001800Y0243393D01*
+X0001800Y0243691D02*
+X0008050Y0243691D01*
+X0008050Y0243990D02*
+X0001800Y0243990D01*
+X0001800Y0244288D02*
+X0008050Y0244288D01*
+X0008050Y0244587D02*
+X0001800Y0244587D01*
+X0001800Y0244886D02*
+X0008050Y0244886D01*
+X0008050Y0245184D02*
+X0001800Y0245184D01*
+X0001800Y0245483D02*
+X0008050Y0245483D01*
+X0008050Y0245781D02*
+X0001800Y0245781D01*
+X0001800Y0246080D02*
+X0008050Y0246080D01*
+X0008050Y0246378D02*
+X0001800Y0246378D01*
+X0001800Y0246677D02*
+X0008050Y0246677D01*
+X0008050Y0246975D02*
+X0001800Y0246975D01*
+X0001800Y0247274D02*
+X0008050Y0247274D01*
+X0008050Y0247572D02*
+X0001800Y0247572D01*
+X0001800Y0247871D02*
+X0008050Y0247871D01*
+X0008050Y0248169D02*
+X0001800Y0248169D01*
+X0001800Y0248468D02*
+X0008050Y0248468D01*
+X0008050Y0248766D02*
+X0001800Y0248766D01*
+X0001800Y0249065D02*
+X0008050Y0249065D01*
+X0008050Y0249363D02*
+X0001800Y0249363D01*
+X0001800Y0249662D02*
+X0008050Y0249662D01*
+X0008050Y0249960D02*
+X0001800Y0249960D01*
+X0001800Y0250259D02*
+X0008050Y0250259D01*
+X0008050Y0250557D02*
+X0001800Y0250557D01*
+X0001800Y0250856D02*
+X0008050Y0250856D01*
+X0008050Y0251154D02*
+X0001800Y0251154D01*
+X0001800Y0251453D02*
+X0008050Y0251453D01*
+X0008050Y0251751D02*
+X0001800Y0251751D01*
+X0001800Y0252050D02*
+X0008050Y0252050D01*
+X0008050Y0252348D02*
+X0001800Y0252348D01*
+X0001800Y0252647D02*
+X0008050Y0252647D01*
+X0008050Y0252945D02*
+X0001800Y0252945D01*
+X0001800Y0253244D02*
+X0008050Y0253244D01*
+X0008050Y0253542D02*
+X0001800Y0253542D01*
+X0001800Y0253841D02*
+X0008050Y0253841D01*
+X0008050Y0254139D02*
+X0001800Y0254139D01*
+X0001800Y0254438D02*
+X0008050Y0254438D01*
+X0008050Y0254736D02*
+X0001800Y0254736D01*
+X0001800Y0255035D02*
+X0008050Y0255035D01*
+X0008050Y0255333D02*
+X0001800Y0255333D01*
+X0001800Y0255632D02*
+X0008050Y0255632D01*
+X0008050Y0255930D02*
+X0001800Y0255930D01*
+X0001800Y0256229D02*
+X0008050Y0256229D01*
+X0008050Y0256527D02*
+X0001800Y0256527D01*
+X0001800Y0256826D02*
+X0008050Y0256826D01*
+X0008050Y0257124D02*
+X0001800Y0257124D01*
+X0001800Y0257423D02*
+X0008050Y0257423D01*
+X0008050Y0257722D02*
+X0001800Y0257722D01*
+X0001800Y0258020D02*
+X0008050Y0258020D01*
+X0008050Y0258319D02*
+X0001800Y0258319D01*
+X0001800Y0258617D02*
+X0008050Y0258617D01*
+X0008050Y0258916D02*
+X0001800Y0258916D01*
+X0001800Y0259214D02*
+X0008050Y0259214D01*
+X0008050Y0259513D02*
+X0001800Y0259513D01*
+X0001800Y0259811D02*
+X0008050Y0259811D01*
+X0008050Y0260110D02*
+X0001800Y0260110D01*
+X0001800Y0260408D02*
+X0008050Y0260408D01*
+X0008050Y0260707D02*
+X0001800Y0260707D01*
+X0001800Y0261005D02*
+X0008050Y0261005D01*
+X0008050Y0261304D02*
+X0001800Y0261304D01*
+X0001800Y0261602D02*
+X0008050Y0261602D01*
+X0008050Y0261901D02*
+X0001800Y0261901D01*
+X0001800Y0262199D02*
+X0008050Y0262199D01*
+X0008050Y0262498D02*
+X0001800Y0262498D01*
+X0001800Y0262796D02*
+X0008050Y0262796D01*
+X0008050Y0263095D02*
+X0001800Y0263095D01*
+X0001800Y0263393D02*
+X0008050Y0263393D01*
+X0008050Y0263692D02*
+X0001800Y0263692D01*
+X0001800Y0263990D02*
+X0008050Y0263990D01*
+X0008050Y0264289D02*
+X0001800Y0264289D01*
+X0001800Y0264587D02*
+X0008050Y0264587D01*
+X0008050Y0264886D02*
+X0001800Y0264886D01*
+X0001800Y0265184D02*
+X0008050Y0265184D01*
+X0008050Y0265483D02*
+X0001800Y0265483D01*
+X0001800Y0265781D02*
+X0008050Y0265781D01*
+X0008050Y0266080D02*
+X0001800Y0266080D01*
+X0001800Y0266378D02*
+X0008050Y0266378D01*
+X0008050Y0266677D02*
+X0001800Y0266677D01*
+X0001800Y0266975D02*
+X0008050Y0266975D01*
+X0008050Y0267274D02*
+X0001800Y0267274D01*
+X0001800Y0267572D02*
+X0008050Y0267572D01*
+X0008050Y0267871D02*
+X0001800Y0267871D01*
+X0001800Y0268169D02*
+X0008050Y0268169D01*
+X0008050Y0268468D02*
+X0001800Y0268468D01*
+X0001800Y0268766D02*
+X0008050Y0268766D01*
+X0008050Y0269065D02*
+X0001800Y0269065D01*
+X0001800Y0269363D02*
+X0008050Y0269363D01*
+X0008050Y0269662D02*
+X0001800Y0269662D01*
+X0001800Y0269960D02*
+X0008050Y0269960D01*
+X0008050Y0270259D02*
+X0001800Y0270259D01*
+X0001800Y0270557D02*
+X0008050Y0270557D01*
+X0008050Y0270856D02*
+X0001800Y0270856D01*
+X0001800Y0271155D02*
+X0008050Y0271155D01*
+X0008050Y0271453D02*
+X0001800Y0271453D01*
+X0001800Y0271752D02*
+X0008050Y0271752D01*
+X0008050Y0272050D02*
+X0001800Y0272050D01*
+X0001800Y0272349D02*
+X0008050Y0272349D01*
+X0008050Y0272647D02*
+X0001800Y0272647D01*
+X0001800Y0272946D02*
+X0008050Y0272946D01*
+X0008050Y0273244D02*
+X0001800Y0273244D01*
+X0001800Y0273543D02*
+X0008050Y0273543D01*
+X0008050Y0273841D02*
+X0001800Y0273841D01*
+X0001800Y0274140D02*
+X0008050Y0274140D01*
+X0008050Y0274438D02*
+X0001800Y0274438D01*
+X0001800Y0274737D02*
+X0008050Y0274737D01*
+X0008050Y0275035D02*
+X0001800Y0275035D01*
+X0001800Y0275334D02*
+X0008050Y0275334D01*
+X0008050Y0275632D02*
+X0001800Y0275632D01*
+X0001800Y0275931D02*
+X0008050Y0275931D01*
+X0008050Y0276229D02*
+X0001800Y0276229D01*
+X0001800Y0276528D02*
+X0008050Y0276528D01*
+X0008050Y0276826D02*
+X0001800Y0276826D01*
+X0001800Y0277125D02*
+X0008050Y0277125D01*
+X0008050Y0277423D02*
+X0001800Y0277423D01*
+X0001800Y0277722D02*
+X0008050Y0277722D01*
+X0008050Y0278020D02*
+X0001800Y0278020D01*
+X0001800Y0278319D02*
+X0008050Y0278319D01*
+X0008050Y0278617D02*
+X0001800Y0278617D01*
+X0001800Y0278916D02*
+X0008050Y0278916D01*
+X0008050Y0279214D02*
+X0001800Y0279214D01*
+X0001800Y0279513D02*
+X0008050Y0279513D01*
+X0371800Y0279547D02*
+X0371800Y0012047D01*
+X0378050Y0012047D01*
+X0371800Y0012047D01*
+X0371800Y0012345D02*
+X0378050Y0012345D01*
+X0378050Y0012047D02*
+X0378050Y0279547D01*
+X0371800Y0279547D01*
+X0371800Y0279513D02*
+X0378050Y0279513D01*
+X0378050Y0279214D02*
+X0371800Y0279214D01*
+X0371800Y0278916D02*
+X0378050Y0278916D01*
+X0378050Y0278617D02*
+X0371800Y0278617D01*
+X0371800Y0278319D02*
+X0378050Y0278319D01*
+X0378050Y0278020D02*
+X0371800Y0278020D01*
+X0371800Y0277722D02*
+X0378050Y0277722D01*
+X0378050Y0277423D02*
+X0371800Y0277423D01*
+X0371800Y0277125D02*
+X0378050Y0277125D01*
+X0378050Y0276826D02*
+X0371800Y0276826D01*
+X0371800Y0276528D02*
+X0378050Y0276528D01*
+X0378050Y0276229D02*
+X0371800Y0276229D01*
+X0371800Y0275931D02*
+X0378050Y0275931D01*
+X0378050Y0275632D02*
+X0371800Y0275632D01*
+X0371800Y0275334D02*
+X0378050Y0275334D01*
+X0378050Y0275035D02*
+X0371800Y0275035D01*
+X0371800Y0274737D02*
+X0378050Y0274737D01*
+X0378050Y0274438D02*
+X0371800Y0274438D01*
+X0371800Y0274140D02*
+X0378050Y0274140D01*
+X0378050Y0273841D02*
+X0371800Y0273841D01*
+X0371800Y0273543D02*
+X0378050Y0273543D01*
+X0378050Y0273244D02*
+X0371800Y0273244D01*
+X0371800Y0272946D02*
+X0378050Y0272946D01*
+X0378050Y0272647D02*
+X0371800Y0272647D01*
+X0371800Y0272349D02*
+X0378050Y0272349D01*
+X0378050Y0272050D02*
+X0371800Y0272050D01*
+X0371800Y0271752D02*
+X0378050Y0271752D01*
+X0378050Y0271453D02*
+X0371800Y0271453D01*
+X0371800Y0271155D02*
+X0378050Y0271155D01*
+X0378050Y0270856D02*
+X0371800Y0270856D01*
+X0371800Y0270557D02*
+X0378050Y0270557D01*
+X0378050Y0270259D02*
+X0371800Y0270259D01*
+X0371800Y0269960D02*
+X0378050Y0269960D01*
+X0378050Y0269662D02*
+X0371800Y0269662D01*
+X0371800Y0269363D02*
+X0378050Y0269363D01*
+X0378050Y0269065D02*
+X0371800Y0269065D01*
+X0371800Y0268766D02*
+X0378050Y0268766D01*
+X0378050Y0268468D02*
+X0371800Y0268468D01*
+X0371800Y0268169D02*
+X0378050Y0268169D01*
+X0378050Y0267871D02*
+X0371800Y0267871D01*
+X0371800Y0267572D02*
+X0378050Y0267572D01*
+X0378050Y0267274D02*
+X0371800Y0267274D01*
+X0371800Y0266975D02*
+X0378050Y0266975D01*
+X0378050Y0266677D02*
+X0371800Y0266677D01*
+X0371800Y0266378D02*
+X0378050Y0266378D01*
+X0378050Y0266080D02*
+X0371800Y0266080D01*
+X0371800Y0265781D02*
+X0378050Y0265781D01*
+X0378050Y0265483D02*
+X0371800Y0265483D01*
+X0371800Y0265184D02*
+X0378050Y0265184D01*
+X0378050Y0264886D02*
+X0371800Y0264886D01*
+X0371800Y0264587D02*
+X0378050Y0264587D01*
+X0378050Y0264289D02*
+X0371800Y0264289D01*
+X0371800Y0263990D02*
+X0378050Y0263990D01*
+X0378050Y0263692D02*
+X0371800Y0263692D01*
+X0371800Y0263393D02*
+X0378050Y0263393D01*
+X0378050Y0263095D02*
+X0371800Y0263095D01*
+X0371800Y0262796D02*
+X0378050Y0262796D01*
+X0378050Y0262498D02*
+X0371800Y0262498D01*
+X0371800Y0262199D02*
+X0378050Y0262199D01*
+X0378050Y0261901D02*
+X0371800Y0261901D01*
+X0371800Y0261602D02*
+X0378050Y0261602D01*
+X0378050Y0261304D02*
+X0371800Y0261304D01*
+X0371800Y0261005D02*
+X0378050Y0261005D01*
+X0378050Y0260707D02*
+X0371800Y0260707D01*
+X0371800Y0260408D02*
+X0378050Y0260408D01*
+X0378050Y0260110D02*
+X0371800Y0260110D01*
+X0371800Y0259811D02*
+X0378050Y0259811D01*
+X0378050Y0259513D02*
+X0371800Y0259513D01*
+X0371800Y0259214D02*
+X0378050Y0259214D01*
+X0378050Y0258916D02*
+X0371800Y0258916D01*
+X0371800Y0258617D02*
+X0378050Y0258617D01*
+X0378050Y0258319D02*
+X0371800Y0258319D01*
+X0371800Y0258020D02*
+X0378050Y0258020D01*
+X0378050Y0257722D02*
+X0371800Y0257722D01*
+X0371800Y0257423D02*
+X0378050Y0257423D01*
+X0378050Y0257124D02*
+X0371800Y0257124D01*
+X0371800Y0256826D02*
+X0378050Y0256826D01*
+X0378050Y0256527D02*
+X0371800Y0256527D01*
+X0371800Y0256229D02*
+X0378050Y0256229D01*
+X0378050Y0255930D02*
+X0371800Y0255930D01*
+X0371800Y0255632D02*
+X0378050Y0255632D01*
+X0378050Y0255333D02*
+X0371800Y0255333D01*
+X0371800Y0255035D02*
+X0378050Y0255035D01*
+X0378050Y0254736D02*
+X0371800Y0254736D01*
+X0371800Y0254438D02*
+X0378050Y0254438D01*
+X0378050Y0254139D02*
+X0371800Y0254139D01*
+X0371800Y0253841D02*
+X0378050Y0253841D01*
+X0378050Y0253542D02*
+X0371800Y0253542D01*
+X0371800Y0253244D02*
+X0378050Y0253244D01*
+X0378050Y0252945D02*
+X0371800Y0252945D01*
+X0371800Y0252647D02*
+X0378050Y0252647D01*
+X0378050Y0252348D02*
+X0371800Y0252348D01*
+X0371800Y0252050D02*
+X0378050Y0252050D01*
+X0378050Y0251751D02*
+X0371800Y0251751D01*
+X0371800Y0251453D02*
+X0378050Y0251453D01*
+X0378050Y0251154D02*
+X0371800Y0251154D01*
+X0371800Y0250856D02*
+X0378050Y0250856D01*
+X0378050Y0250557D02*
+X0371800Y0250557D01*
+X0371800Y0250259D02*
+X0378050Y0250259D01*
+X0378050Y0249960D02*
+X0371800Y0249960D01*
+X0371800Y0249662D02*
+X0378050Y0249662D01*
+X0378050Y0249363D02*
+X0371800Y0249363D01*
+X0371800Y0249065D02*
+X0378050Y0249065D01*
+X0378050Y0248766D02*
+X0371800Y0248766D01*
+X0371800Y0248468D02*
+X0378050Y0248468D01*
+X0378050Y0248169D02*
+X0371800Y0248169D01*
+X0371800Y0247871D02*
+X0378050Y0247871D01*
+X0378050Y0247572D02*
+X0371800Y0247572D01*
+X0371800Y0247274D02*
+X0378050Y0247274D01*
+X0378050Y0246975D02*
+X0371800Y0246975D01*
+X0371800Y0246677D02*
+X0378050Y0246677D01*
+X0378050Y0246378D02*
+X0371800Y0246378D01*
+X0371800Y0246080D02*
+X0378050Y0246080D01*
+X0378050Y0245781D02*
+X0371800Y0245781D01*
+X0371800Y0245483D02*
+X0378050Y0245483D01*
+X0378050Y0245184D02*
+X0371800Y0245184D01*
+X0371800Y0244886D02*
+X0378050Y0244886D01*
+X0378050Y0244587D02*
+X0371800Y0244587D01*
+X0371800Y0244288D02*
+X0378050Y0244288D01*
+X0378050Y0243990D02*
+X0371800Y0243990D01*
+X0371800Y0243691D02*
+X0378050Y0243691D01*
+X0378050Y0243393D02*
+X0371800Y0243393D01*
+X0371800Y0243094D02*
+X0378050Y0243094D01*
+X0378050Y0242796D02*
+X0371800Y0242796D01*
+X0371800Y0242497D02*
+X0378050Y0242497D01*
+X0378050Y0242199D02*
+X0371800Y0242199D01*
+X0371800Y0241900D02*
+X0378050Y0241900D01*
+X0378050Y0241602D02*
+X0371800Y0241602D01*
+X0371800Y0241303D02*
+X0378050Y0241303D01*
+X0378050Y0241005D02*
+X0371800Y0241005D01*
+X0371800Y0240706D02*
+X0378050Y0240706D01*
+X0378050Y0240408D02*
+X0371800Y0240408D01*
+X0371800Y0240109D02*
+X0378050Y0240109D01*
+X0378050Y0239811D02*
+X0371800Y0239811D01*
+X0371800Y0239512D02*
+X0378050Y0239512D01*
+X0378050Y0239214D02*
+X0371800Y0239214D01*
+X0371800Y0238915D02*
+X0378050Y0238915D01*
+X0378050Y0238617D02*
+X0371800Y0238617D01*
+X0371800Y0238318D02*
+X0378050Y0238318D01*
+X0378050Y0238020D02*
+X0371800Y0238020D01*
+X0371800Y0237721D02*
+X0378050Y0237721D01*
+X0378050Y0237423D02*
+X0371800Y0237423D01*
+X0371800Y0237124D02*
+X0378050Y0237124D01*
+X0378050Y0236826D02*
+X0371800Y0236826D01*
+X0371800Y0236527D02*
+X0378050Y0236527D01*
+X0378050Y0236229D02*
+X0371800Y0236229D01*
+X0371800Y0235930D02*
+X0378050Y0235930D01*
+X0378050Y0235632D02*
+X0371800Y0235632D01*
+X0371800Y0235333D02*
+X0378050Y0235333D01*
+X0378050Y0235035D02*
+X0371800Y0235035D01*
+X0371800Y0234736D02*
+X0378050Y0234736D01*
+X0378050Y0234438D02*
+X0371800Y0234438D01*
+X0371800Y0234139D02*
+X0378050Y0234139D01*
+X0378050Y0233841D02*
+X0371800Y0233841D01*
+X0371800Y0233542D02*
+X0378050Y0233542D01*
+X0378050Y0233244D02*
+X0371800Y0233244D01*
+X0371800Y0232945D02*
+X0378050Y0232945D01*
+X0378050Y0232647D02*
+X0371800Y0232647D01*
+X0371800Y0232348D02*
+X0378050Y0232348D01*
+X0378050Y0232050D02*
+X0371800Y0232050D01*
+X0371800Y0231751D02*
+X0378050Y0231751D01*
+X0378050Y0231453D02*
+X0371800Y0231453D01*
+X0371800Y0231154D02*
+X0378050Y0231154D01*
+X0378050Y0230855D02*
+X0371800Y0230855D01*
+X0371800Y0230557D02*
+X0378050Y0230557D01*
+X0378050Y0230258D02*
+X0371800Y0230258D01*
+X0371800Y0229960D02*
+X0378050Y0229960D01*
+X0378050Y0229661D02*
+X0371800Y0229661D01*
+X0371800Y0229363D02*
+X0378050Y0229363D01*
+X0378050Y0229064D02*
+X0371800Y0229064D01*
+X0371800Y0228766D02*
+X0378050Y0228766D01*
+X0378050Y0228467D02*
+X0371800Y0228467D01*
+X0371800Y0228169D02*
+X0378050Y0228169D01*
+X0378050Y0227870D02*
+X0371800Y0227870D01*
+X0371800Y0227572D02*
+X0378050Y0227572D01*
+X0378050Y0227273D02*
+X0371800Y0227273D01*
+X0371800Y0226975D02*
+X0378050Y0226975D01*
+X0378050Y0226676D02*
+X0371800Y0226676D01*
+X0371800Y0226378D02*
+X0378050Y0226378D01*
+X0378050Y0226079D02*
+X0371800Y0226079D01*
+X0371800Y0225781D02*
+X0378050Y0225781D01*
+X0378050Y0225482D02*
+X0371800Y0225482D01*
+X0371800Y0225184D02*
+X0378050Y0225184D01*
+X0378050Y0224885D02*
+X0371800Y0224885D01*
+X0371800Y0224587D02*
+X0378050Y0224587D01*
+X0378050Y0224288D02*
+X0371800Y0224288D01*
+X0371800Y0223990D02*
+X0378050Y0223990D01*
+X0378050Y0223691D02*
+X0371800Y0223691D01*
+X0371800Y0223393D02*
+X0378050Y0223393D01*
+X0378050Y0223094D02*
+X0371800Y0223094D01*
+X0371800Y0222796D02*
+X0378050Y0222796D01*
+X0378050Y0222497D02*
+X0371800Y0222497D01*
+X0371800Y0222199D02*
+X0378050Y0222199D01*
+X0378050Y0221900D02*
+X0371800Y0221900D01*
+X0371800Y0221602D02*
+X0378050Y0221602D01*
+X0378050Y0221303D02*
+X0371800Y0221303D01*
+X0371800Y0221005D02*
+X0378050Y0221005D01*
+X0378050Y0220706D02*
+X0371800Y0220706D01*
+X0371800Y0220408D02*
+X0378050Y0220408D01*
+X0378050Y0220109D02*
+X0371800Y0220109D01*
+X0371800Y0219811D02*
+X0378050Y0219811D01*
+X0378050Y0219512D02*
+X0371800Y0219512D01*
+X0371800Y0219214D02*
+X0378050Y0219214D01*
+X0378050Y0218915D02*
+X0371800Y0218915D01*
+X0371800Y0218617D02*
+X0378050Y0218617D01*
+X0378050Y0218318D02*
+X0371800Y0218318D01*
+X0371800Y0218020D02*
+X0378050Y0218020D01*
+X0378050Y0217721D02*
+X0371800Y0217721D01*
+X0371800Y0217422D02*
+X0378050Y0217422D01*
+X0378050Y0217124D02*
+X0371800Y0217124D01*
+X0371800Y0216825D02*
+X0378050Y0216825D01*
+X0378050Y0216527D02*
+X0371800Y0216527D01*
+X0371800Y0216228D02*
+X0378050Y0216228D01*
+X0378050Y0215930D02*
+X0371800Y0215930D01*
+X0371800Y0215631D02*
+X0378050Y0215631D01*
+X0378050Y0215333D02*
+X0371800Y0215333D01*
+X0371800Y0215034D02*
+X0378050Y0215034D01*
+X0378050Y0214736D02*
+X0371800Y0214736D01*
+X0371800Y0214437D02*
+X0378050Y0214437D01*
+X0378050Y0214139D02*
+X0371800Y0214139D01*
+X0371800Y0213840D02*
+X0378050Y0213840D01*
+X0378050Y0213542D02*
+X0371800Y0213542D01*
+X0371800Y0213243D02*
+X0378050Y0213243D01*
+X0378050Y0212945D02*
+X0371800Y0212945D01*
+X0371800Y0212646D02*
+X0378050Y0212646D01*
+X0378050Y0212348D02*
+X0371800Y0212348D01*
+X0371800Y0212049D02*
+X0378050Y0212049D01*
+X0378050Y0211751D02*
+X0371800Y0211751D01*
+X0371800Y0211452D02*
+X0378050Y0211452D01*
+X0378050Y0211154D02*
+X0371800Y0211154D01*
+X0371800Y0210855D02*
+X0378050Y0210855D01*
+X0378050Y0210557D02*
+X0371800Y0210557D01*
+X0371800Y0210258D02*
+X0378050Y0210258D01*
+X0378050Y0209960D02*
+X0371800Y0209960D01*
+X0371800Y0209661D02*
+X0378050Y0209661D01*
+X0378050Y0209363D02*
+X0371800Y0209363D01*
+X0371800Y0209064D02*
+X0378050Y0209064D01*
+X0378050Y0208766D02*
+X0371800Y0208766D01*
+X0371800Y0208467D02*
+X0378050Y0208467D01*
+X0378050Y0208169D02*
+X0371800Y0208169D01*
+X0371800Y0207870D02*
+X0378050Y0207870D01*
+X0378050Y0207572D02*
+X0371800Y0207572D01*
+X0371800Y0207273D02*
+X0378050Y0207273D01*
+X0378050Y0206975D02*
+X0371800Y0206975D01*
+X0371800Y0206676D02*
+X0378050Y0206676D01*
+X0378050Y0206378D02*
+X0371800Y0206378D01*
+X0371800Y0206079D02*
+X0378050Y0206079D01*
+X0378050Y0205781D02*
+X0371800Y0205781D01*
+X0371800Y0205482D02*
+X0378050Y0205482D01*
+X0378050Y0205184D02*
+X0371800Y0205184D01*
+X0371800Y0204885D02*
+X0378050Y0204885D01*
+X0378050Y0204586D02*
+X0371800Y0204586D01*
+X0371800Y0204288D02*
+X0378050Y0204288D01*
+X0378050Y0203989D02*
+X0371800Y0203989D01*
+X0371800Y0203691D02*
+X0378050Y0203691D01*
+X0378050Y0203392D02*
+X0371800Y0203392D01*
+X0371800Y0203094D02*
+X0378050Y0203094D01*
+X0378050Y0202795D02*
+X0371800Y0202795D01*
+X0371800Y0202497D02*
+X0378050Y0202497D01*
+X0378050Y0202198D02*
+X0371800Y0202198D01*
+X0371800Y0201900D02*
+X0378050Y0201900D01*
+X0378050Y0201601D02*
+X0371800Y0201601D01*
+X0371800Y0201303D02*
+X0378050Y0201303D01*
+X0378050Y0201004D02*
+X0371800Y0201004D01*
+X0371800Y0200706D02*
+X0378050Y0200706D01*
+X0378050Y0200407D02*
+X0371800Y0200407D01*
+X0371800Y0200109D02*
+X0378050Y0200109D01*
+X0378050Y0199810D02*
+X0371800Y0199810D01*
+X0371800Y0199512D02*
+X0378050Y0199512D01*
+X0378050Y0199213D02*
+X0371800Y0199213D01*
+X0371800Y0198915D02*
+X0378050Y0198915D01*
+X0378050Y0198616D02*
+X0371800Y0198616D01*
+X0371800Y0198318D02*
+X0378050Y0198318D01*
+X0378050Y0198019D02*
+X0371800Y0198019D01*
+X0371800Y0197721D02*
+X0378050Y0197721D01*
+X0378050Y0197422D02*
+X0371800Y0197422D01*
+X0371800Y0197124D02*
+X0378050Y0197124D01*
+X0378050Y0196825D02*
+X0371800Y0196825D01*
+X0371800Y0196527D02*
+X0378050Y0196527D01*
+X0378050Y0196228D02*
+X0371800Y0196228D01*
+X0371800Y0195930D02*
+X0378050Y0195930D01*
+X0378050Y0195631D02*
+X0371800Y0195631D01*
+X0371800Y0195333D02*
+X0378050Y0195333D01*
+X0378050Y0195034D02*
+X0371800Y0195034D01*
+X0371800Y0194736D02*
+X0378050Y0194736D01*
+X0378050Y0194437D02*
+X0371800Y0194437D01*
+X0371800Y0194139D02*
+X0378050Y0194139D01*
+X0378050Y0193840D02*
+X0371800Y0193840D01*
+X0371800Y0193542D02*
+X0378050Y0193542D01*
+X0378050Y0193243D02*
+X0371800Y0193243D01*
+X0371800Y0192945D02*
+X0378050Y0192945D01*
+X0378050Y0192646D02*
+X0371800Y0192646D01*
+X0371800Y0192348D02*
+X0378050Y0192348D01*
+X0378050Y0192049D02*
+X0371800Y0192049D01*
+X0371800Y0191751D02*
+X0378050Y0191751D01*
+X0378050Y0191452D02*
+X0371800Y0191452D01*
+X0371800Y0191153D02*
+X0378050Y0191153D01*
+X0378050Y0190855D02*
+X0371800Y0190855D01*
+X0371800Y0190556D02*
+X0378050Y0190556D01*
+X0378050Y0190258D02*
+X0371800Y0190258D01*
+X0371800Y0189959D02*
+X0378050Y0189959D01*
+X0378050Y0189661D02*
+X0371800Y0189661D01*
+X0371800Y0189362D02*
+X0378050Y0189362D01*
+X0378050Y0189064D02*
+X0371800Y0189064D01*
+X0371800Y0188765D02*
+X0378050Y0188765D01*
+X0378050Y0188467D02*
+X0371800Y0188467D01*
+X0371800Y0188168D02*
+X0378050Y0188168D01*
+X0378050Y0187870D02*
+X0371800Y0187870D01*
+X0371800Y0187571D02*
+X0378050Y0187571D01*
+X0378050Y0187273D02*
+X0371800Y0187273D01*
+X0371800Y0186974D02*
+X0378050Y0186974D01*
+X0378050Y0186676D02*
+X0371800Y0186676D01*
+X0371800Y0186377D02*
+X0378050Y0186377D01*
+X0378050Y0186079D02*
+X0371800Y0186079D01*
+X0371800Y0185780D02*
+X0378050Y0185780D01*
+X0378050Y0185482D02*
+X0371800Y0185482D01*
+X0371800Y0185183D02*
+X0378050Y0185183D01*
+X0378050Y0184885D02*
+X0371800Y0184885D01*
+X0371800Y0184586D02*
+X0378050Y0184586D01*
+X0378050Y0184288D02*
+X0371800Y0184288D01*
+X0371800Y0183989D02*
+X0378050Y0183989D01*
+X0378050Y0183691D02*
+X0371800Y0183691D01*
+X0371800Y0183392D02*
+X0378050Y0183392D01*
+X0378050Y0183094D02*
+X0371800Y0183094D01*
+X0371800Y0182795D02*
+X0378050Y0182795D01*
+X0378050Y0182497D02*
+X0371800Y0182497D01*
+X0371800Y0182198D02*
+X0378050Y0182198D01*
+X0378050Y0181900D02*
+X0371800Y0181900D01*
+X0371800Y0181601D02*
+X0378050Y0181601D01*
+X0378050Y0181303D02*
+X0371800Y0181303D01*
+X0371800Y0181004D02*
+X0378050Y0181004D01*
+X0378050Y0180706D02*
+X0371800Y0180706D01*
+X0371800Y0180407D02*
+X0378050Y0180407D01*
+X0378050Y0180109D02*
+X0371800Y0180109D01*
+X0371800Y0179810D02*
+X0378050Y0179810D01*
+X0378050Y0179512D02*
+X0371800Y0179512D01*
+X0371800Y0179213D02*
+X0378050Y0179213D01*
+X0378050Y0178915D02*
+X0371800Y0178915D01*
+X0371800Y0178616D02*
+X0378050Y0178616D01*
+X0378050Y0178317D02*
+X0371800Y0178317D01*
+X0371800Y0178019D02*
+X0378050Y0178019D01*
+X0378050Y0177720D02*
+X0371800Y0177720D01*
+X0371800Y0177422D02*
+X0378050Y0177422D01*
+X0378050Y0177123D02*
+X0371800Y0177123D01*
+X0371800Y0176825D02*
+X0378050Y0176825D01*
+X0378050Y0176526D02*
+X0371800Y0176526D01*
+X0371800Y0176228D02*
+X0378050Y0176228D01*
+X0378050Y0175929D02*
+X0371800Y0175929D01*
+X0371800Y0175631D02*
+X0378050Y0175631D01*
+X0378050Y0175332D02*
+X0371800Y0175332D01*
+X0371800Y0175034D02*
+X0378050Y0175034D01*
+X0378050Y0174735D02*
+X0371800Y0174735D01*
+X0371800Y0174437D02*
+X0378050Y0174437D01*
+X0378050Y0174138D02*
+X0371800Y0174138D01*
+X0371800Y0173840D02*
+X0378050Y0173840D01*
+X0378050Y0173541D02*
+X0371800Y0173541D01*
+X0371800Y0173243D02*
+X0378050Y0173243D01*
+X0378050Y0172944D02*
+X0371800Y0172944D01*
+X0371800Y0172646D02*
+X0378050Y0172646D01*
+X0378050Y0172347D02*
+X0371800Y0172347D01*
+X0371800Y0172049D02*
+X0378050Y0172049D01*
+X0378050Y0171750D02*
+X0371800Y0171750D01*
+X0371800Y0171452D02*
+X0378050Y0171452D01*
+X0378050Y0171153D02*
+X0371800Y0171153D01*
+X0371800Y0170855D02*
+X0378050Y0170855D01*
+X0378050Y0170556D02*
+X0371800Y0170556D01*
+X0371800Y0170258D02*
+X0378050Y0170258D01*
+X0378050Y0169959D02*
+X0371800Y0169959D01*
+X0371800Y0169661D02*
+X0378050Y0169661D01*
+X0378050Y0169362D02*
+X0371800Y0169362D01*
+X0371800Y0169064D02*
+X0378050Y0169064D01*
+X0378050Y0168765D02*
+X0371800Y0168765D01*
+X0371800Y0168467D02*
+X0378050Y0168467D01*
+X0378050Y0168168D02*
+X0371800Y0168168D01*
+X0371800Y0167870D02*
+X0378050Y0167870D01*
+X0378050Y0167571D02*
+X0371800Y0167571D01*
+X0371800Y0167273D02*
+X0378050Y0167273D01*
+X0378050Y0166974D02*
+X0371800Y0166974D01*
+X0371800Y0166676D02*
+X0378050Y0166676D01*
+X0378050Y0166377D02*
+X0371800Y0166377D01*
+X0371800Y0166079D02*
+X0378050Y0166079D01*
+X0378050Y0165780D02*
+X0371800Y0165780D01*
+X0371800Y0165482D02*
+X0378050Y0165482D01*
+X0378050Y0165183D02*
+X0371800Y0165183D01*
+X0371800Y0164884D02*
+X0378050Y0164884D01*
+X0378050Y0164586D02*
+X0371800Y0164586D01*
+X0371800Y0164287D02*
+X0378050Y0164287D01*
+X0378050Y0163989D02*
+X0371800Y0163989D01*
+X0371800Y0163690D02*
+X0378050Y0163690D01*
+X0378050Y0163392D02*
+X0371800Y0163392D01*
+X0371800Y0163093D02*
+X0378050Y0163093D01*
+X0378050Y0162795D02*
+X0371800Y0162795D01*
+X0371800Y0162496D02*
+X0378050Y0162496D01*
+X0378050Y0162198D02*
+X0371800Y0162198D01*
+X0371800Y0161899D02*
+X0378050Y0161899D01*
+X0378050Y0161601D02*
+X0371800Y0161601D01*
+X0371800Y0161302D02*
+X0378050Y0161302D01*
+X0378050Y0161004D02*
+X0371800Y0161004D01*
+X0371800Y0160705D02*
+X0378050Y0160705D01*
+X0378050Y0160407D02*
+X0371800Y0160407D01*
+X0371800Y0160108D02*
+X0378050Y0160108D01*
+X0378050Y0159810D02*
+X0371800Y0159810D01*
+X0371800Y0159511D02*
+X0378050Y0159511D01*
+X0378050Y0159213D02*
+X0371800Y0159213D01*
+X0371800Y0158914D02*
+X0378050Y0158914D01*
+X0378050Y0158616D02*
+X0371800Y0158616D01*
+X0371800Y0158317D02*
+X0378050Y0158317D01*
+X0378050Y0158019D02*
+X0371800Y0158019D01*
+X0371800Y0157720D02*
+X0378050Y0157720D01*
+X0378050Y0157422D02*
+X0371800Y0157422D01*
+X0371800Y0157123D02*
+X0378050Y0157123D01*
+X0378050Y0156825D02*
+X0371800Y0156825D01*
+X0371800Y0156526D02*
+X0378050Y0156526D01*
+X0378050Y0156228D02*
+X0371800Y0156228D01*
+X0371800Y0155929D02*
+X0378050Y0155929D01*
+X0378050Y0155631D02*
+X0371800Y0155631D01*
+X0371800Y0155332D02*
+X0378050Y0155332D01*
+X0378050Y0155034D02*
+X0371800Y0155034D01*
+X0371800Y0154735D02*
+X0378050Y0154735D01*
+X0378050Y0154437D02*
+X0371800Y0154437D01*
+X0371800Y0154138D02*
+X0378050Y0154138D01*
+X0378050Y0153840D02*
+X0371800Y0153840D01*
+X0371800Y0153541D02*
+X0378050Y0153541D01*
+X0378050Y0153243D02*
+X0371800Y0153243D01*
+X0371800Y0152944D02*
+X0378050Y0152944D01*
+X0378050Y0152646D02*
+X0371800Y0152646D01*
+X0371800Y0152347D02*
+X0378050Y0152347D01*
+X0378050Y0152048D02*
+X0371800Y0152048D01*
+X0371800Y0151750D02*
+X0378050Y0151750D01*
+X0378050Y0151451D02*
+X0371800Y0151451D01*
+X0371800Y0151153D02*
+X0378050Y0151153D01*
+X0378050Y0150854D02*
+X0371800Y0150854D01*
+X0371800Y0150556D02*
+X0378050Y0150556D01*
+X0378050Y0150257D02*
+X0371800Y0150257D01*
+X0371800Y0149959D02*
+X0378050Y0149959D01*
+X0378050Y0149660D02*
+X0371800Y0149660D01*
+X0371800Y0149362D02*
+X0378050Y0149362D01*
+X0378050Y0149063D02*
+X0371800Y0149063D01*
+X0371800Y0148765D02*
+X0378050Y0148765D01*
+X0378050Y0148466D02*
+X0371800Y0148466D01*
+X0371800Y0148168D02*
+X0378050Y0148168D01*
+X0378050Y0147869D02*
+X0371800Y0147869D01*
+X0371800Y0147571D02*
+X0378050Y0147571D01*
+X0378050Y0147272D02*
+X0371800Y0147272D01*
+X0371800Y0146974D02*
+X0378050Y0146974D01*
+X0378050Y0146675D02*
+X0371800Y0146675D01*
+X0371800Y0146377D02*
+X0378050Y0146377D01*
+X0378050Y0146078D02*
+X0371800Y0146078D01*
+X0371800Y0145780D02*
+X0378050Y0145780D01*
+X0378050Y0145481D02*
+X0371800Y0145481D01*
+X0371800Y0145183D02*
+X0378050Y0145183D01*
+X0378050Y0144884D02*
+X0371800Y0144884D01*
+X0371800Y0144586D02*
+X0378050Y0144586D01*
+X0378050Y0144287D02*
+X0371800Y0144287D01*
+X0371800Y0143989D02*
+X0378050Y0143989D01*
+X0378050Y0143690D02*
+X0371800Y0143690D01*
+X0371800Y0143392D02*
+X0378050Y0143392D01*
+X0378050Y0143093D02*
+X0371800Y0143093D01*
+X0371800Y0142795D02*
+X0378050Y0142795D01*
+X0378050Y0142496D02*
+X0371800Y0142496D01*
+X0371800Y0142198D02*
+X0378050Y0142198D01*
+X0378050Y0141899D02*
+X0371800Y0141899D01*
+X0371800Y0141601D02*
+X0378050Y0141601D01*
+X0378050Y0141302D02*
+X0371800Y0141302D01*
+X0371800Y0141004D02*
+X0378050Y0141004D01*
+X0378050Y0140705D02*
+X0371800Y0140705D01*
+X0371800Y0140407D02*
+X0378050Y0140407D01*
+X0378050Y0140108D02*
+X0371800Y0140108D01*
+X0371800Y0139810D02*
+X0378050Y0139810D01*
+X0378050Y0139511D02*
+X0371800Y0139511D01*
+X0371800Y0139213D02*
+X0378050Y0139213D01*
+X0378050Y0138914D02*
+X0371800Y0138914D01*
+X0371800Y0138615D02*
+X0378050Y0138615D01*
+X0378050Y0138317D02*
+X0371800Y0138317D01*
+X0371800Y0138018D02*
+X0378050Y0138018D01*
+X0378050Y0137720D02*
+X0371800Y0137720D01*
+X0371800Y0137421D02*
+X0378050Y0137421D01*
+X0378050Y0137123D02*
+X0371800Y0137123D01*
+X0371800Y0136824D02*
+X0378050Y0136824D01*
+X0378050Y0136526D02*
+X0371800Y0136526D01*
+X0371800Y0136227D02*
+X0378050Y0136227D01*
+X0378050Y0135929D02*
+X0371800Y0135929D01*
+X0371800Y0135630D02*
+X0378050Y0135630D01*
+X0378050Y0135332D02*
+X0371800Y0135332D01*
+X0371800Y0135033D02*
+X0378050Y0135033D01*
+X0378050Y0134735D02*
+X0371800Y0134735D01*
+X0371800Y0134436D02*
+X0378050Y0134436D01*
+X0378050Y0134138D02*
+X0371800Y0134138D01*
+X0371800Y0133839D02*
+X0378050Y0133839D01*
+X0378050Y0133541D02*
+X0371800Y0133541D01*
+X0371800Y0133242D02*
+X0378050Y0133242D01*
+X0378050Y0132944D02*
+X0371800Y0132944D01*
+X0371800Y0132645D02*
+X0378050Y0132645D01*
+X0378050Y0132347D02*
+X0371800Y0132347D01*
+X0371800Y0132048D02*
+X0378050Y0132048D01*
+X0378050Y0131750D02*
+X0371800Y0131750D01*
+X0371800Y0131451D02*
+X0378050Y0131451D01*
+X0378050Y0131153D02*
+X0371800Y0131153D01*
+X0371800Y0130854D02*
+X0378050Y0130854D01*
+X0378050Y0130556D02*
+X0371800Y0130556D01*
+X0371800Y0130257D02*
+X0378050Y0130257D01*
+X0378050Y0129959D02*
+X0371800Y0129959D01*
+X0371800Y0129660D02*
+X0378050Y0129660D01*
+X0378050Y0129362D02*
+X0371800Y0129362D01*
+X0371800Y0129063D02*
+X0378050Y0129063D01*
+X0378050Y0128765D02*
+X0371800Y0128765D01*
+X0371800Y0128466D02*
+X0378050Y0128466D01*
+X0378050Y0128168D02*
+X0371800Y0128168D01*
+X0371800Y0127869D02*
+X0378050Y0127869D01*
+X0378050Y0127571D02*
+X0371800Y0127571D01*
+X0371800Y0127272D02*
+X0378050Y0127272D01*
+X0378050Y0126974D02*
+X0371800Y0126974D01*
+X0371800Y0126675D02*
+X0378050Y0126675D01*
+X0378050Y0126377D02*
+X0371800Y0126377D01*
+X0371800Y0126078D02*
+X0378050Y0126078D01*
+X0378050Y0125780D02*
+X0371800Y0125780D01*
+X0371800Y0125481D02*
+X0378050Y0125481D01*
+X0378050Y0125182D02*
+X0371800Y0125182D01*
+X0371800Y0124884D02*
+X0378050Y0124884D01*
+X0378050Y0124585D02*
+X0371800Y0124585D01*
+X0371800Y0124287D02*
+X0378050Y0124287D01*
+X0378050Y0123988D02*
+X0371800Y0123988D01*
+X0371800Y0123690D02*
+X0378050Y0123690D01*
+X0378050Y0123391D02*
+X0371800Y0123391D01*
+X0371800Y0123093D02*
+X0378050Y0123093D01*
+X0378050Y0122794D02*
+X0371800Y0122794D01*
+X0371800Y0122496D02*
+X0378050Y0122496D01*
+X0378050Y0122197D02*
+X0371800Y0122197D01*
+X0371800Y0121899D02*
+X0378050Y0121899D01*
+X0378050Y0121600D02*
+X0371800Y0121600D01*
+X0371800Y0121302D02*
+X0378050Y0121302D01*
+X0378050Y0121003D02*
+X0371800Y0121003D01*
+X0371800Y0120705D02*
+X0378050Y0120705D01*
+X0378050Y0120406D02*
+X0371800Y0120406D01*
+X0371800Y0120108D02*
+X0378050Y0120108D01*
+X0378050Y0119809D02*
+X0371800Y0119809D01*
+X0371800Y0119511D02*
+X0378050Y0119511D01*
+X0378050Y0119212D02*
+X0371800Y0119212D01*
+X0371800Y0118914D02*
+X0378050Y0118914D01*
+X0378050Y0118615D02*
+X0371800Y0118615D01*
+X0371800Y0118317D02*
+X0378050Y0118317D01*
+X0378050Y0118018D02*
+X0371800Y0118018D01*
+X0371800Y0117720D02*
+X0378050Y0117720D01*
+X0378050Y0117421D02*
+X0371800Y0117421D01*
+X0371800Y0117123D02*
+X0378050Y0117123D01*
+X0378050Y0116824D02*
+X0371800Y0116824D01*
+X0371800Y0116526D02*
+X0378050Y0116526D01*
+X0378050Y0116227D02*
+X0371800Y0116227D01*
+X0371800Y0115929D02*
+X0378050Y0115929D01*
+X0378050Y0115630D02*
+X0371800Y0115630D01*
+X0371800Y0115332D02*
+X0378050Y0115332D01*
+X0378050Y0115033D02*
+X0371800Y0115033D01*
+X0371800Y0114735D02*
+X0378050Y0114735D01*
+X0378050Y0114436D02*
+X0371800Y0114436D01*
+X0371800Y0114138D02*
+X0378050Y0114138D01*
+X0378050Y0113839D02*
+X0371800Y0113839D01*
+X0371800Y0113541D02*
+X0378050Y0113541D01*
+X0378050Y0113242D02*
+X0371800Y0113242D01*
+X0371800Y0112944D02*
+X0378050Y0112944D01*
+X0378050Y0112645D02*
+X0371800Y0112645D01*
+X0371800Y0112346D02*
+X0378050Y0112346D01*
+X0378050Y0112048D02*
+X0371800Y0112048D01*
+X0371800Y0111749D02*
+X0378050Y0111749D01*
+X0378050Y0111451D02*
+X0371800Y0111451D01*
+X0371800Y0111152D02*
+X0378050Y0111152D01*
+X0378050Y0110854D02*
+X0371800Y0110854D01*
+X0371800Y0110555D02*
+X0378050Y0110555D01*
+X0378050Y0110257D02*
+X0371800Y0110257D01*
+X0371800Y0109958D02*
+X0378050Y0109958D01*
+X0378050Y0109660D02*
+X0371800Y0109660D01*
+X0371800Y0109361D02*
+X0378050Y0109361D01*
+X0378050Y0109063D02*
+X0371800Y0109063D01*
+X0371800Y0108764D02*
+X0378050Y0108764D01*
+X0378050Y0108466D02*
+X0371800Y0108466D01*
+X0371800Y0108167D02*
+X0378050Y0108167D01*
+X0378050Y0107869D02*
+X0371800Y0107869D01*
+X0371800Y0107570D02*
+X0378050Y0107570D01*
+X0378050Y0107272D02*
+X0371800Y0107272D01*
+X0371800Y0106973D02*
+X0378050Y0106973D01*
+X0378050Y0106675D02*
+X0371800Y0106675D01*
+X0371800Y0106376D02*
+X0378050Y0106376D01*
+X0378050Y0106078D02*
+X0371800Y0106078D01*
+X0371800Y0105779D02*
+X0378050Y0105779D01*
+X0378050Y0105481D02*
+X0371800Y0105481D01*
+X0371800Y0105182D02*
+X0378050Y0105182D01*
+X0378050Y0104884D02*
+X0371800Y0104884D01*
+X0371800Y0104585D02*
+X0378050Y0104585D01*
+X0378050Y0104287D02*
+X0371800Y0104287D01*
+X0371800Y0103988D02*
+X0378050Y0103988D01*
+X0378050Y0103690D02*
+X0371800Y0103690D01*
+X0371800Y0103391D02*
+X0378050Y0103391D01*
+X0378050Y0103093D02*
+X0371800Y0103093D01*
+X0371800Y0102794D02*
+X0378050Y0102794D01*
+X0378050Y0102496D02*
+X0371800Y0102496D01*
+X0371800Y0102197D02*
+X0378050Y0102197D01*
+X0378050Y0101899D02*
+X0371800Y0101899D01*
+X0371800Y0101600D02*
+X0378050Y0101600D01*
+X0378050Y0101302D02*
+X0371800Y0101302D01*
+X0371800Y0101003D02*
+X0378050Y0101003D01*
+X0378050Y0100705D02*
+X0371800Y0100705D01*
+X0371800Y0100406D02*
+X0378050Y0100406D01*
+X0378050Y0100108D02*
+X0371800Y0100108D01*
+X0371800Y0099809D02*
+X0378050Y0099809D01*
+X0378050Y0099511D02*
+X0371800Y0099511D01*
+X0371800Y0099212D02*
+X0378050Y0099212D01*
+X0378050Y0098913D02*
+X0371800Y0098913D01*
+X0371800Y0098615D02*
+X0378050Y0098615D01*
+X0378050Y0098316D02*
+X0371800Y0098316D01*
+X0371800Y0098018D02*
+X0378050Y0098018D01*
+X0378050Y0097719D02*
+X0371800Y0097719D01*
+X0371800Y0097421D02*
+X0378050Y0097421D01*
+X0378050Y0097122D02*
+X0371800Y0097122D01*
+X0371800Y0096824D02*
+X0378050Y0096824D01*
+X0378050Y0096525D02*
+X0371800Y0096525D01*
+X0371800Y0096227D02*
+X0378050Y0096227D01*
+X0378050Y0095928D02*
+X0371800Y0095928D01*
+X0371800Y0095630D02*
+X0378050Y0095630D01*
+X0378050Y0095331D02*
+X0371800Y0095331D01*
+X0371800Y0095033D02*
+X0378050Y0095033D01*
+X0378050Y0094734D02*
+X0371800Y0094734D01*
+X0371800Y0094436D02*
+X0378050Y0094436D01*
+X0378050Y0094137D02*
+X0371800Y0094137D01*
+X0371800Y0093839D02*
+X0378050Y0093839D01*
+X0378050Y0093540D02*
+X0371800Y0093540D01*
+X0371800Y0093242D02*
+X0378050Y0093242D01*
+X0378050Y0092943D02*
+X0371800Y0092943D01*
+X0371800Y0092645D02*
+X0378050Y0092645D01*
+X0378050Y0092346D02*
+X0371800Y0092346D01*
+X0371800Y0092048D02*
+X0378050Y0092048D01*
+X0378050Y0091749D02*
+X0371800Y0091749D01*
+X0371800Y0091451D02*
+X0378050Y0091451D01*
+X0378050Y0091152D02*
+X0371800Y0091152D01*
+X0371800Y0090854D02*
+X0378050Y0090854D01*
+X0378050Y0090555D02*
+X0371800Y0090555D01*
+X0371800Y0090257D02*
+X0378050Y0090257D01*
+X0378050Y0089958D02*
+X0371800Y0089958D01*
+X0371800Y0089660D02*
+X0378050Y0089660D01*
+X0378050Y0089361D02*
+X0371800Y0089361D01*
+X0371800Y0089063D02*
+X0378050Y0089063D01*
+X0378050Y0088764D02*
+X0371800Y0088764D01*
+X0371800Y0088466D02*
+X0378050Y0088466D01*
+X0378050Y0088167D02*
+X0371800Y0088167D01*
+X0371800Y0087869D02*
+X0378050Y0087869D01*
+X0378050Y0087570D02*
+X0371800Y0087570D01*
+X0371800Y0087272D02*
+X0378050Y0087272D01*
+X0378050Y0086973D02*
+X0371800Y0086973D01*
+X0371800Y0086675D02*
+X0378050Y0086675D01*
+X0378050Y0086376D02*
+X0371800Y0086376D01*
+X0371800Y0086077D02*
+X0378050Y0086077D01*
+X0378050Y0085779D02*
+X0371800Y0085779D01*
+X0371800Y0085480D02*
+X0378050Y0085480D01*
+X0378050Y0085182D02*
+X0371800Y0085182D01*
+X0371800Y0084883D02*
+X0378050Y0084883D01*
+X0378050Y0084585D02*
+X0371800Y0084585D01*
+X0371800Y0084286D02*
+X0378050Y0084286D01*
+X0378050Y0083988D02*
+X0371800Y0083988D01*
+X0371800Y0083689D02*
+X0378050Y0083689D01*
+X0378050Y0083391D02*
+X0371800Y0083391D01*
+X0371800Y0083092D02*
+X0378050Y0083092D01*
+X0378050Y0082794D02*
+X0371800Y0082794D01*
+X0371800Y0082495D02*
+X0378050Y0082495D01*
+X0378050Y0082197D02*
+X0371800Y0082197D01*
+X0371800Y0081898D02*
+X0378050Y0081898D01*
+X0378050Y0081600D02*
+X0371800Y0081600D01*
+X0371800Y0081301D02*
+X0378050Y0081301D01*
+X0378050Y0081003D02*
+X0371800Y0081003D01*
+X0371800Y0080704D02*
+X0378050Y0080704D01*
+X0378050Y0080406D02*
+X0371800Y0080406D01*
+X0371800Y0080107D02*
+X0378050Y0080107D01*
+X0378050Y0079809D02*
+X0371800Y0079809D01*
+X0371800Y0079510D02*
+X0378050Y0079510D01*
+X0378050Y0079212D02*
+X0371800Y0079212D01*
+X0371800Y0078913D02*
+X0378050Y0078913D01*
+X0378050Y0078615D02*
+X0371800Y0078615D01*
+X0371800Y0078316D02*
+X0378050Y0078316D01*
+X0378050Y0078018D02*
+X0371800Y0078018D01*
+X0371800Y0077719D02*
+X0378050Y0077719D01*
+X0378050Y0077421D02*
+X0371800Y0077421D01*
+X0371800Y0077122D02*
+X0378050Y0077122D01*
+X0378050Y0076824D02*
+X0371800Y0076824D01*
+X0371800Y0076525D02*
+X0378050Y0076525D01*
+X0378050Y0076227D02*
+X0371800Y0076227D01*
+X0371800Y0075928D02*
+X0378050Y0075928D01*
+X0378050Y0075630D02*
+X0371800Y0075630D01*
+X0371800Y0075331D02*
+X0378050Y0075331D01*
+X0378050Y0075033D02*
+X0371800Y0075033D01*
+X0371800Y0074734D02*
+X0378050Y0074734D01*
+X0378050Y0074436D02*
+X0371800Y0074436D01*
+X0371800Y0074137D02*
+X0378050Y0074137D01*
+X0378050Y0073839D02*
+X0371800Y0073839D01*
+X0371800Y0073540D02*
+X0378050Y0073540D01*
+X0378050Y0073242D02*
+X0371800Y0073242D01*
+X0371800Y0072943D02*
+X0378050Y0072943D01*
+X0378050Y0072644D02*
+X0371800Y0072644D01*
+X0371800Y0072346D02*
+X0378050Y0072346D01*
+X0378050Y0072047D02*
+X0371800Y0072047D01*
+X0371800Y0071749D02*
+X0378050Y0071749D01*
+X0378050Y0071450D02*
+X0371800Y0071450D01*
+X0371800Y0071152D02*
+X0378050Y0071152D01*
+X0378050Y0070853D02*
+X0371800Y0070853D01*
+X0371800Y0070555D02*
+X0378050Y0070555D01*
+X0378050Y0070256D02*
+X0371800Y0070256D01*
+X0371800Y0069958D02*
+X0378050Y0069958D01*
+X0378050Y0069659D02*
+X0371800Y0069659D01*
+X0371800Y0069361D02*
+X0378050Y0069361D01*
+X0378050Y0069062D02*
+X0371800Y0069062D01*
+X0371800Y0068764D02*
+X0378050Y0068764D01*
+X0378050Y0068465D02*
+X0371800Y0068465D01*
+X0371800Y0068167D02*
+X0378050Y0068167D01*
+X0378050Y0067868D02*
+X0371800Y0067868D01*
+X0371800Y0067570D02*
+X0378050Y0067570D01*
+X0378050Y0067271D02*
+X0371800Y0067271D01*
+X0371800Y0066973D02*
+X0378050Y0066973D01*
+X0378050Y0066674D02*
+X0371800Y0066674D01*
+X0371800Y0066376D02*
+X0378050Y0066376D01*
+X0378050Y0066077D02*
+X0371800Y0066077D01*
+X0371800Y0065779D02*
+X0378050Y0065779D01*
+X0378050Y0065480D02*
+X0371800Y0065480D01*
+X0371800Y0065182D02*
+X0378050Y0065182D01*
+X0378050Y0064883D02*
+X0371800Y0064883D01*
+X0371800Y0064585D02*
+X0378050Y0064585D01*
+X0378050Y0064286D02*
+X0371800Y0064286D01*
+X0371800Y0063988D02*
+X0378050Y0063988D01*
+X0378050Y0063689D02*
+X0371800Y0063689D01*
+X0371800Y0063391D02*
+X0378050Y0063391D01*
+X0378050Y0063092D02*
+X0371800Y0063092D01*
+X0371800Y0062794D02*
+X0378050Y0062794D01*
+X0378050Y0062495D02*
+X0371800Y0062495D01*
+X0371800Y0062197D02*
+X0378050Y0062197D01*
+X0378050Y0061898D02*
+X0371800Y0061898D01*
+X0371800Y0061600D02*
+X0378050Y0061600D01*
+X0378050Y0061301D02*
+X0371800Y0061301D01*
+X0371800Y0061003D02*
+X0378050Y0061003D01*
+X0378050Y0060704D02*
+X0371800Y0060704D01*
+X0371800Y0060406D02*
+X0378050Y0060406D01*
+X0378050Y0060107D02*
+X0371800Y0060107D01*
+X0371800Y0059809D02*
+X0378050Y0059809D01*
+X0378050Y0059510D02*
+X0371800Y0059510D01*
+X0371800Y0059211D02*
+X0378050Y0059211D01*
+X0378050Y0058913D02*
+X0371800Y0058913D01*
+X0371800Y0058614D02*
+X0378050Y0058614D01*
+X0378050Y0058316D02*
+X0371800Y0058316D01*
+X0371800Y0058017D02*
+X0378050Y0058017D01*
+X0378050Y0057719D02*
+X0371800Y0057719D01*
+X0371800Y0057420D02*
+X0378050Y0057420D01*
+X0378050Y0057122D02*
+X0371800Y0057122D01*
+X0371800Y0056823D02*
+X0378050Y0056823D01*
+X0378050Y0056525D02*
+X0371800Y0056525D01*
+X0371800Y0056226D02*
+X0378050Y0056226D01*
+X0378050Y0055928D02*
+X0371800Y0055928D01*
+X0371800Y0055629D02*
+X0378050Y0055629D01*
+X0378050Y0055331D02*
+X0371800Y0055331D01*
+X0371800Y0055032D02*
+X0378050Y0055032D01*
+X0378050Y0054734D02*
+X0371800Y0054734D01*
+X0371800Y0054435D02*
+X0378050Y0054435D01*
+X0378050Y0054137D02*
+X0371800Y0054137D01*
+X0371800Y0053838D02*
+X0378050Y0053838D01*
+X0378050Y0053540D02*
+X0371800Y0053540D01*
+X0371800Y0053241D02*
+X0378050Y0053241D01*
+X0378050Y0052943D02*
+X0371800Y0052943D01*
+X0371800Y0052644D02*
+X0378050Y0052644D01*
+X0378050Y0052346D02*
+X0371800Y0052346D01*
+X0371800Y0052047D02*
+X0378050Y0052047D01*
+X0378050Y0051749D02*
+X0371800Y0051749D01*
+X0371800Y0051450D02*
+X0378050Y0051450D01*
+X0378050Y0051152D02*
+X0371800Y0051152D01*
+X0371800Y0050853D02*
+X0378050Y0050853D01*
+X0378050Y0050555D02*
+X0371800Y0050555D01*
+X0371800Y0050256D02*
+X0378050Y0050256D01*
+X0378050Y0049958D02*
+X0371800Y0049958D01*
+X0371800Y0049659D02*
+X0378050Y0049659D01*
+X0378050Y0049361D02*
+X0371800Y0049361D01*
+X0371800Y0049062D02*
+X0378050Y0049062D01*
+X0378050Y0048764D02*
+X0371800Y0048764D01*
+X0371800Y0048465D02*
+X0378050Y0048465D01*
+X0378050Y0048167D02*
+X0371800Y0048167D01*
+X0371800Y0047868D02*
+X0378050Y0047868D01*
+X0378050Y0047570D02*
+X0371800Y0047570D01*
+X0371800Y0047271D02*
+X0378050Y0047271D01*
+X0378050Y0046973D02*
+X0371800Y0046973D01*
+X0371800Y0046674D02*
+X0378050Y0046674D01*
+X0378050Y0046375D02*
+X0371800Y0046375D01*
+X0371800Y0046077D02*
+X0378050Y0046077D01*
+X0378050Y0045778D02*
+X0371800Y0045778D01*
+X0371800Y0045480D02*
+X0378050Y0045480D01*
+X0378050Y0045181D02*
+X0371800Y0045181D01*
+X0371800Y0044883D02*
+X0378050Y0044883D01*
+X0378050Y0044584D02*
+X0371800Y0044584D01*
+X0371800Y0044286D02*
+X0378050Y0044286D01*
+X0378050Y0043987D02*
+X0371800Y0043987D01*
+X0371800Y0043689D02*
+X0378050Y0043689D01*
+X0378050Y0043390D02*
+X0371800Y0043390D01*
+X0371800Y0043092D02*
+X0378050Y0043092D01*
+X0378050Y0042793D02*
+X0371800Y0042793D01*
+X0371800Y0042495D02*
+X0378050Y0042495D01*
+X0378050Y0042196D02*
+X0371800Y0042196D01*
+X0371800Y0041898D02*
+X0378050Y0041898D01*
+X0378050Y0041599D02*
+X0371800Y0041599D01*
+X0371800Y0041301D02*
+X0378050Y0041301D01*
+X0378050Y0041002D02*
+X0371800Y0041002D01*
+X0371800Y0040704D02*
+X0378050Y0040704D01*
+X0378050Y0040405D02*
+X0371800Y0040405D01*
+X0371800Y0040107D02*
+X0378050Y0040107D01*
+X0378050Y0039808D02*
+X0371800Y0039808D01*
+X0371800Y0039510D02*
+X0378050Y0039510D01*
+X0378050Y0039211D02*
+X0371800Y0039211D01*
+X0371800Y0038913D02*
+X0378050Y0038913D01*
+X0378050Y0038614D02*
+X0371800Y0038614D01*
+X0371800Y0038316D02*
+X0378050Y0038316D01*
+X0378050Y0038017D02*
+X0371800Y0038017D01*
+X0371800Y0037719D02*
+X0378050Y0037719D01*
+X0378050Y0037420D02*
+X0371800Y0037420D01*
+X0371800Y0037122D02*
+X0378050Y0037122D01*
+X0378050Y0036823D02*
+X0371800Y0036823D01*
+X0371800Y0036525D02*
+X0378050Y0036525D01*
+X0378050Y0036226D02*
+X0371800Y0036226D01*
+X0371800Y0035928D02*
+X0378050Y0035928D01*
+X0378050Y0035629D02*
+X0371800Y0035629D01*
+X0371800Y0035331D02*
+X0378050Y0035331D01*
+X0378050Y0035032D02*
+X0371800Y0035032D01*
+X0371800Y0034734D02*
+X0378050Y0034734D01*
+X0378050Y0034435D02*
+X0371800Y0034435D01*
+X0371800Y0034137D02*
+X0378050Y0034137D01*
+X0378050Y0033838D02*
+X0371800Y0033838D01*
+X0371800Y0033540D02*
+X0378050Y0033540D01*
+X0378050Y0033241D02*
+X0371800Y0033241D01*
+X0371800Y0032942D02*
+X0378050Y0032942D01*
+X0378050Y0032644D02*
+X0371800Y0032644D01*
+X0371800Y0032345D02*
+X0378050Y0032345D01*
+X0378050Y0032047D02*
+X0371800Y0032047D01*
+X0371800Y0031748D02*
+X0378050Y0031748D01*
+X0378050Y0031450D02*
+X0371800Y0031450D01*
+X0371800Y0031151D02*
+X0378050Y0031151D01*
+X0378050Y0030853D02*
+X0371800Y0030853D01*
+X0371800Y0030554D02*
+X0378050Y0030554D01*
+X0378050Y0030256D02*
+X0371800Y0030256D01*
+X0371800Y0029957D02*
+X0378050Y0029957D01*
+X0378050Y0029659D02*
+X0371800Y0029659D01*
+X0371800Y0029360D02*
+X0378050Y0029360D01*
+X0378050Y0029062D02*
+X0371800Y0029062D01*
+X0371800Y0028763D02*
+X0378050Y0028763D01*
+X0378050Y0028465D02*
+X0371800Y0028465D01*
+X0371800Y0028166D02*
+X0378050Y0028166D01*
+X0378050Y0027868D02*
+X0371800Y0027868D01*
+X0371800Y0027569D02*
+X0378050Y0027569D01*
+X0378050Y0027271D02*
+X0371800Y0027271D01*
+X0371800Y0026972D02*
+X0378050Y0026972D01*
+X0378050Y0026674D02*
+X0371800Y0026674D01*
+X0371800Y0026375D02*
+X0378050Y0026375D01*
+X0378050Y0026077D02*
+X0371800Y0026077D01*
+X0371800Y0025778D02*
+X0378050Y0025778D01*
+X0378050Y0025480D02*
+X0371800Y0025480D01*
+X0371800Y0025181D02*
+X0378050Y0025181D01*
+X0378050Y0024883D02*
+X0371800Y0024883D01*
+X0371800Y0024584D02*
+X0378050Y0024584D01*
+X0378050Y0024286D02*
+X0371800Y0024286D01*
+X0371800Y0023987D02*
+X0378050Y0023987D01*
+X0378050Y0023689D02*
+X0371800Y0023689D01*
+X0371800Y0023390D02*
+X0378050Y0023390D01*
+X0378050Y0023092D02*
+X0371800Y0023092D01*
+X0371800Y0022793D02*
+X0378050Y0022793D01*
+X0378050Y0022495D02*
+X0371800Y0022495D01*
+X0371800Y0022196D02*
+X0378050Y0022196D01*
+X0378050Y0021898D02*
+X0371800Y0021898D01*
+X0371800Y0021599D02*
+X0378050Y0021599D01*
+X0378050Y0021301D02*
+X0371800Y0021301D01*
+X0371800Y0021002D02*
+X0378050Y0021002D01*
+X0378050Y0020704D02*
+X0371800Y0020704D01*
+X0371800Y0020405D02*
+X0378050Y0020405D01*
+X0378050Y0020106D02*
+X0371800Y0020106D01*
+X0371800Y0019808D02*
+X0378050Y0019808D01*
+X0378050Y0019509D02*
+X0371800Y0019509D01*
+X0371800Y0019211D02*
+X0378050Y0019211D01*
+X0378050Y0018912D02*
+X0371800Y0018912D01*
+X0371800Y0018614D02*
+X0378050Y0018614D01*
+X0378050Y0018315D02*
+X0371800Y0018315D01*
+X0371800Y0018017D02*
+X0378050Y0018017D01*
+X0378050Y0017718D02*
+X0371800Y0017718D01*
+X0371800Y0017420D02*
+X0378050Y0017420D01*
+X0378050Y0017121D02*
+X0371800Y0017121D01*
+X0371800Y0016823D02*
+X0378050Y0016823D01*
+X0378050Y0016524D02*
+X0371800Y0016524D01*
+X0371800Y0016226D02*
+X0378050Y0016226D01*
+X0378050Y0015927D02*
+X0371800Y0015927D01*
+X0371800Y0015629D02*
+X0378050Y0015629D01*
+X0378050Y0015330D02*
+X0371800Y0015330D01*
+X0371800Y0015032D02*
+X0378050Y0015032D01*
+X0378050Y0014733D02*
+X0371800Y0014733D01*
+X0371800Y0014435D02*
+X0378050Y0014435D01*
+X0378050Y0014136D02*
+X0371800Y0014136D01*
+X0371800Y0013838D02*
+X0378050Y0013838D01*
+X0378050Y0013539D02*
+X0371800Y0013539D01*
+X0371800Y0013241D02*
+X0378050Y0013241D01*
+X0378050Y0012942D02*
+X0371800Y0012942D01*
+X0371800Y0012644D02*
+X0378050Y0012644D01*
+D11*
+X0270550Y0049547D02*
+X0265007Y0049547D01*
+X0265007Y0059547D02*
+X0270550Y0059547D01*
+X0270550Y0069547D02*
+X0265007Y0069547D01*
+X0265007Y0079547D02*
+X0270550Y0079547D01*
+X0270550Y0089547D02*
+X0265007Y0089547D01*
+X0265007Y0099547D02*
+X0270550Y0099547D01*
+X0270550Y0109547D02*
+X0265007Y0109547D01*
+X0265007Y0119547D02*
+X0270550Y0119547D01*
+X0270550Y0129547D02*
+X0265007Y0129547D01*
+X0265007Y0139547D02*
+X0270550Y0139547D01*
+X0270550Y0149547D02*
+X0265007Y0149547D01*
+X0265007Y0159547D02*
+X0270550Y0159547D01*
+X0270550Y0169547D02*
+X0265007Y0169547D01*
+X0265007Y0179547D02*
+X0270550Y0179547D01*
+X0270550Y0189547D02*
+X0265007Y0189547D01*
+X0230822Y0219547D02*
+X0225278Y0219547D01*
+X0216093Y0189547D02*
+X0210550Y0189547D01*
+X0210550Y0179547D02*
+X0216093Y0179547D01*
+X0216093Y0169547D02*
+X0210550Y0169547D01*
+X0210550Y0159547D02*
+X0216093Y0159547D01*
+X0216093Y0149547D02*
+X0210550Y0149547D01*
+X0210550Y0139547D02*
+X0216093Y0139547D01*
+X0216093Y0129547D02*
+X0210550Y0129547D01*
+X0210550Y0119547D02*
+X0216093Y0119547D01*
+X0216093Y0109547D02*
+X0210550Y0109547D01*
+X0210550Y0099547D02*
+X0216093Y0099547D01*
+X0216093Y0089547D02*
+X0210550Y0089547D01*
+X0210550Y0079547D02*
+X0216093Y0079547D01*
+X0216093Y0069547D02*
+X0210550Y0069547D01*
+X0210550Y0059547D02*
+X0216093Y0059547D01*
+X0216093Y0049547D02*
+X0210550Y0049547D01*
+X0189572Y0047047D02*
+X0184028Y0047047D01*
+X0184028Y0057047D02*
+X0189572Y0057047D01*
+X0189572Y0067047D02*
+X0184028Y0067047D01*
+X0184028Y0077047D02*
+X0189572Y0077047D01*
+X0189572Y0087047D02*
+X0184028Y0087047D01*
+X0184028Y0097047D02*
+X0189572Y0097047D01*
+X0109572Y0097047D02*
+X0104028Y0097047D01*
+X0104028Y0087047D02*
+X0109572Y0087047D01*
+X0109572Y0077047D02*
+X0104028Y0077047D01*
+X0104028Y0067047D02*
+X0109572Y0067047D01*
+X0109572Y0057047D02*
+X0104028Y0057047D01*
+X0104028Y0047047D02*
+X0109572Y0047047D01*
+D12*
+X0283050Y0103287D03*
+X0283050Y0119035D03*
+X0283050Y0134783D03*
+X0283050Y0150531D03*
+X0283050Y0166279D03*
+X0283050Y0182027D03*
+X0283050Y0197775D03*
+X0283050Y0213523D03*
+X0361790Y0213523D03*
+X0361790Y0197775D03*
+X0361790Y0182027D03*
+X0361790Y0166279D03*
+X0361790Y0150531D03*
+X0361790Y0134783D03*
+X0361790Y0119035D03*
+X0361790Y0103287D03*
+D13*
+X0310609Y0083602D03*
+X0328326Y0233208D03*
+D14*
+X0343089Y0183027D02*
+X0343089Y0177090D01*
+X0343089Y0169247D02*
+X0343089Y0163310D01*
+X0101800Y0266578D02*
+X0101800Y0272515D01*
+X0091800Y0272515D02*
+X0091800Y0266578D01*
+X0081800Y0266578D02*
+X0081800Y0272515D01*
+X0081828Y0210787D02*
+X0087765Y0210787D01*
+X0026772Y0210787D02*
+X0020835Y0210787D01*
+X0020835Y0055275D02*
+X0026772Y0055275D01*
+X0056800Y0025015D02*
+X0056800Y0019078D01*
+X0066800Y0019078D02*
+X0066800Y0025015D01*
+X0076800Y0025015D02*
+X0076800Y0019078D01*
+X0081828Y0055275D02*
+X0087765Y0055275D01*
+D15*
+X0031800Y0029547D03*
+X0170550Y0139547D03*
+X0031800Y0262047D03*
+X0345550Y0262047D03*
+X0345550Y0029547D03*
+D16*
+X0275550Y0255797D03*
+D17*
+X0265511Y0265836D03*
+X0285589Y0265836D03*
+X0285589Y0245758D03*
+X0265511Y0245758D03*
+D18*
+X0072050Y0227047D02*
+X0063050Y0227047D01*
+X0045550Y0227047D02*
+X0036550Y0227047D01*
+D19*
+X0294300Y0044547D03*
+X0294300Y0035547D03*
+X0314300Y0035547D03*
+X0314300Y0044547D03*
+D20*
+X0304300Y0044547D03*
+X0304300Y0035547D03*
+X0324300Y0035547D03*
+X0324300Y0044547D03*
+D21*
+X0196800Y0243297D03*
+D22*
+X0196800Y0253297D03*
+X0206800Y0253297D03*
+X0216800Y0253297D03*
+X0226800Y0253297D03*
+X0236800Y0253297D03*
+X0236800Y0243297D03*
+X0226800Y0243297D03*
+X0216800Y0243297D03*
+X0206800Y0243297D03*
+D23*
+X0183050Y0257047D03*
+X0243050Y0232047D03*
+X0266800Y0233297D03*
+X0266800Y0223297D03*
+X0269300Y0212047D03*
+X0251800Y0204547D03*
+X0231800Y0204547D03*
+X0244300Y0179547D03*
+X0234300Y0153297D03*
+X0249300Y0147047D03*
+X0200550Y0112047D03*
+X0196800Y0164547D03*
+X0180550Y0173297D03*
+X0170550Y0173297D03*
+X0160550Y0173297D03*
+X0170550Y0189547D03*
+X0180550Y0186058D03*
+X0196800Y0198297D03*
+X0160550Y0197047D03*
+X0130550Y0125797D03*
+X0108050Y0124547D03*
+X0055550Y0164547D03*
+X0010550Y0173297D03*
+X0010550Y0099547D03*
+X0258050Y0033297D03*
+X0285550Y0054547D03*
+X0290550Y0062047D03*
+X0280550Y0077047D03*
+X0333050Y0059547D03*
+X0365550Y0067047D03*
+X0370550Y0094547D03*
+X0364300Y0019547D03*
+X0369300Y0238297D03*
+X0369300Y0272047D03*
+X0320550Y0240797D03*
+X0303050Y0254547D03*
+X0318050Y0264547D03*
+D24*
+X0364300Y0229547D03*
+X0364300Y0222047D03*
+X0166800Y0117047D03*
+X0119300Y0165797D03*
+X0131800Y0199547D03*
+X0101800Y0220797D03*
+X0133050Y0255797D03*
+X0146800Y0234547D03*
+X0018050Y0138297D03*
+X0053050Y0098297D03*
+X0120550Y0035797D03*
+X0186800Y0020797D03*
+X0239300Y0020797D03*
+M02*
diff --git a/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.sts b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.sts
new file mode 100755
index 0000000..8cc4e64
--- /dev/null
+++ b/NPR70_modem_v05_PCB/NPR70_v05_c_gerbers/NPR70_v05.sts
@@ -0,0 +1,3926 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+%ADD10C,0.00300*%
+%ADD11C,0.06343*%
+%ADD12C,0.06737*%
+%ADD13C,0.23800*%
+%ADD14C,0.09800*%
+%ADD15C,0.11300*%
+%ADD16R,0.05918X0.07099*%
+%ADD17R,0.07099X0.05918*%
+%ADD18R,0.08674X0.06706*%
+%ADD19R,0.06706X0.08674*%
+%ADD20C,0.09800*%
+%ADD21R,0.06800X0.05524*%
+%ADD22R,0.08674X0.05524*%
+%ADD23R,0.07887X0.07300*%
+%ADD24R,0.07887X0.09265*%
+%ADD25R,0.09461X0.11036*%
+%ADD26R,0.12414X0.11430*%
+%ADD27R,0.06312X0.04737*%
+%ADD28OC8,0.05800*%
+%ADD29C,0.05800*%
+%ADD30R,0.08800X0.03400*%
+%ADD31C,0.06400*%
+%ADD32OC8,0.06400*%
+%ADD33R,0.07887X0.10249*%
+%ADD34C,0.04369*%
+%ADD35C,0.05156*%
+D10*
+X0001800Y0012047D02*
+X0008050Y0012047D01*
+X0008050Y0279547D01*
+X0001800Y0279547D01*
+X0001800Y0012047D01*
+X0008050Y0012047D01*
+X0008050Y0012345D02*
+X0001800Y0012345D01*
+X0001800Y0012644D02*
+X0008050Y0012644D01*
+X0008050Y0012942D02*
+X0001800Y0012942D01*
+X0001800Y0013241D02*
+X0008050Y0013241D01*
+X0008050Y0013539D02*
+X0001800Y0013539D01*
+X0001800Y0013838D02*
+X0008050Y0013838D01*
+X0008050Y0014136D02*
+X0001800Y0014136D01*
+X0001800Y0014435D02*
+X0008050Y0014435D01*
+X0008050Y0014733D02*
+X0001800Y0014733D01*
+X0001800Y0015032D02*
+X0008050Y0015032D01*
+X0008050Y0015330D02*
+X0001800Y0015330D01*
+X0001800Y0015629D02*
+X0008050Y0015629D01*
+X0008050Y0015927D02*
+X0001800Y0015927D01*
+X0001800Y0016226D02*
+X0008050Y0016226D01*
+X0008050Y0016524D02*
+X0001800Y0016524D01*
+X0001800Y0016823D02*
+X0008050Y0016823D01*
+X0008050Y0017121D02*
+X0001800Y0017121D01*
+X0001800Y0017420D02*
+X0008050Y0017420D01*
+X0008050Y0017718D02*
+X0001800Y0017718D01*
+X0001800Y0018017D02*
+X0008050Y0018017D01*
+X0008050Y0018315D02*
+X0001800Y0018315D01*
+X0001800Y0018614D02*
+X0008050Y0018614D01*
+X0008050Y0018912D02*
+X0001800Y0018912D01*
+X0001800Y0019211D02*
+X0008050Y0019211D01*
+X0008050Y0019509D02*
+X0001800Y0019509D01*
+X0001800Y0019808D02*
+X0008050Y0019808D01*
+X0008050Y0020106D02*
+X0001800Y0020106D01*
+X0001800Y0020405D02*
+X0008050Y0020405D01*
+X0008050Y0020704D02*
+X0001800Y0020704D01*
+X0001800Y0021002D02*
+X0008050Y0021002D01*
+X0008050Y0021301D02*
+X0001800Y0021301D01*
+X0001800Y0021599D02*
+X0008050Y0021599D01*
+X0008050Y0021898D02*
+X0001800Y0021898D01*
+X0001800Y0022196D02*
+X0008050Y0022196D01*
+X0008050Y0022495D02*
+X0001800Y0022495D01*
+X0001800Y0022793D02*
+X0008050Y0022793D01*
+X0008050Y0023092D02*
+X0001800Y0023092D01*
+X0001800Y0023390D02*
+X0008050Y0023390D01*
+X0008050Y0023689D02*
+X0001800Y0023689D01*
+X0001800Y0023987D02*
+X0008050Y0023987D01*
+X0008050Y0024286D02*
+X0001800Y0024286D01*
+X0001800Y0024584D02*
+X0008050Y0024584D01*
+X0008050Y0024883D02*
+X0001800Y0024883D01*
+X0001800Y0025181D02*
+X0008050Y0025181D01*
+X0008050Y0025480D02*
+X0001800Y0025480D01*
+X0001800Y0025778D02*
+X0008050Y0025778D01*
+X0008050Y0026077D02*
+X0001800Y0026077D01*
+X0001800Y0026375D02*
+X0008050Y0026375D01*
+X0008050Y0026674D02*
+X0001800Y0026674D01*
+X0001800Y0026972D02*
+X0008050Y0026972D01*
+X0008050Y0027271D02*
+X0001800Y0027271D01*
+X0001800Y0027569D02*
+X0008050Y0027569D01*
+X0008050Y0027868D02*
+X0001800Y0027868D01*
+X0001800Y0028166D02*
+X0008050Y0028166D01*
+X0008050Y0028465D02*
+X0001800Y0028465D01*
+X0001800Y0028763D02*
+X0008050Y0028763D01*
+X0008050Y0029062D02*
+X0001800Y0029062D01*
+X0001800Y0029360D02*
+X0008050Y0029360D01*
+X0008050Y0029659D02*
+X0001800Y0029659D01*
+X0001800Y0029957D02*
+X0008050Y0029957D01*
+X0008050Y0030256D02*
+X0001800Y0030256D01*
+X0001800Y0030554D02*
+X0008050Y0030554D01*
+X0008050Y0030853D02*
+X0001800Y0030853D01*
+X0001800Y0031151D02*
+X0008050Y0031151D01*
+X0008050Y0031450D02*
+X0001800Y0031450D01*
+X0001800Y0031748D02*
+X0008050Y0031748D01*
+X0008050Y0032047D02*
+X0001800Y0032047D01*
+X0001800Y0032345D02*
+X0008050Y0032345D01*
+X0008050Y0032644D02*
+X0001800Y0032644D01*
+X0001800Y0032942D02*
+X0008050Y0032942D01*
+X0008050Y0033241D02*
+X0001800Y0033241D01*
+X0001800Y0033540D02*
+X0008050Y0033540D01*
+X0008050Y0033838D02*
+X0001800Y0033838D01*
+X0001800Y0034137D02*
+X0008050Y0034137D01*
+X0008050Y0034435D02*
+X0001800Y0034435D01*
+X0001800Y0034734D02*
+X0008050Y0034734D01*
+X0008050Y0035032D02*
+X0001800Y0035032D01*
+X0001800Y0035331D02*
+X0008050Y0035331D01*
+X0008050Y0035629D02*
+X0001800Y0035629D01*
+X0001800Y0035928D02*
+X0008050Y0035928D01*
+X0008050Y0036226D02*
+X0001800Y0036226D01*
+X0001800Y0036525D02*
+X0008050Y0036525D01*
+X0008050Y0036823D02*
+X0001800Y0036823D01*
+X0001800Y0037122D02*
+X0008050Y0037122D01*
+X0008050Y0037420D02*
+X0001800Y0037420D01*
+X0001800Y0037719D02*
+X0008050Y0037719D01*
+X0008050Y0038017D02*
+X0001800Y0038017D01*
+X0001800Y0038316D02*
+X0008050Y0038316D01*
+X0008050Y0038614D02*
+X0001800Y0038614D01*
+X0001800Y0038913D02*
+X0008050Y0038913D01*
+X0008050Y0039211D02*
+X0001800Y0039211D01*
+X0001800Y0039510D02*
+X0008050Y0039510D01*
+X0008050Y0039808D02*
+X0001800Y0039808D01*
+X0001800Y0040107D02*
+X0008050Y0040107D01*
+X0008050Y0040405D02*
+X0001800Y0040405D01*
+X0001800Y0040704D02*
+X0008050Y0040704D01*
+X0008050Y0041002D02*
+X0001800Y0041002D01*
+X0001800Y0041301D02*
+X0008050Y0041301D01*
+X0008050Y0041599D02*
+X0001800Y0041599D01*
+X0001800Y0041898D02*
+X0008050Y0041898D01*
+X0008050Y0042196D02*
+X0001800Y0042196D01*
+X0001800Y0042495D02*
+X0008050Y0042495D01*
+X0008050Y0042793D02*
+X0001800Y0042793D01*
+X0001800Y0043092D02*
+X0008050Y0043092D01*
+X0008050Y0043390D02*
+X0001800Y0043390D01*
+X0001800Y0043689D02*
+X0008050Y0043689D01*
+X0008050Y0043987D02*
+X0001800Y0043987D01*
+X0001800Y0044286D02*
+X0008050Y0044286D01*
+X0008050Y0044584D02*
+X0001800Y0044584D01*
+X0001800Y0044883D02*
+X0008050Y0044883D01*
+X0008050Y0045181D02*
+X0001800Y0045181D01*
+X0001800Y0045480D02*
+X0008050Y0045480D01*
+X0008050Y0045778D02*
+X0001800Y0045778D01*
+X0001800Y0046077D02*
+X0008050Y0046077D01*
+X0008050Y0046375D02*
+X0001800Y0046375D01*
+X0001800Y0046674D02*
+X0008050Y0046674D01*
+X0008050Y0046973D02*
+X0001800Y0046973D01*
+X0001800Y0047271D02*
+X0008050Y0047271D01*
+X0008050Y0047570D02*
+X0001800Y0047570D01*
+X0001800Y0047868D02*
+X0008050Y0047868D01*
+X0008050Y0048167D02*
+X0001800Y0048167D01*
+X0001800Y0048465D02*
+X0008050Y0048465D01*
+X0008050Y0048764D02*
+X0001800Y0048764D01*
+X0001800Y0049062D02*
+X0008050Y0049062D01*
+X0008050Y0049361D02*
+X0001800Y0049361D01*
+X0001800Y0049659D02*
+X0008050Y0049659D01*
+X0008050Y0049958D02*
+X0001800Y0049958D01*
+X0001800Y0050256D02*
+X0008050Y0050256D01*
+X0008050Y0050555D02*
+X0001800Y0050555D01*
+X0001800Y0050853D02*
+X0008050Y0050853D01*
+X0008050Y0051152D02*
+X0001800Y0051152D01*
+X0001800Y0051450D02*
+X0008050Y0051450D01*
+X0008050Y0051749D02*
+X0001800Y0051749D01*
+X0001800Y0052047D02*
+X0008050Y0052047D01*
+X0008050Y0052346D02*
+X0001800Y0052346D01*
+X0001800Y0052644D02*
+X0008050Y0052644D01*
+X0008050Y0052943D02*
+X0001800Y0052943D01*
+X0001800Y0053241D02*
+X0008050Y0053241D01*
+X0008050Y0053540D02*
+X0001800Y0053540D01*
+X0001800Y0053838D02*
+X0008050Y0053838D01*
+X0008050Y0054137D02*
+X0001800Y0054137D01*
+X0001800Y0054435D02*
+X0008050Y0054435D01*
+X0008050Y0054734D02*
+X0001800Y0054734D01*
+X0001800Y0055032D02*
+X0008050Y0055032D01*
+X0008050Y0055331D02*
+X0001800Y0055331D01*
+X0001800Y0055629D02*
+X0008050Y0055629D01*
+X0008050Y0055928D02*
+X0001800Y0055928D01*
+X0001800Y0056226D02*
+X0008050Y0056226D01*
+X0008050Y0056525D02*
+X0001800Y0056525D01*
+X0001800Y0056823D02*
+X0008050Y0056823D01*
+X0008050Y0057122D02*
+X0001800Y0057122D01*
+X0001800Y0057420D02*
+X0008050Y0057420D01*
+X0008050Y0057719D02*
+X0001800Y0057719D01*
+X0001800Y0058017D02*
+X0008050Y0058017D01*
+X0008050Y0058316D02*
+X0001800Y0058316D01*
+X0001800Y0058614D02*
+X0008050Y0058614D01*
+X0008050Y0058913D02*
+X0001800Y0058913D01*
+X0001800Y0059211D02*
+X0008050Y0059211D01*
+X0008050Y0059510D02*
+X0001800Y0059510D01*
+X0001800Y0059809D02*
+X0008050Y0059809D01*
+X0008050Y0060107D02*
+X0001800Y0060107D01*
+X0001800Y0060406D02*
+X0008050Y0060406D01*
+X0008050Y0060704D02*
+X0001800Y0060704D01*
+X0001800Y0061003D02*
+X0008050Y0061003D01*
+X0008050Y0061301D02*
+X0001800Y0061301D01*
+X0001800Y0061600D02*
+X0008050Y0061600D01*
+X0008050Y0061898D02*
+X0001800Y0061898D01*
+X0001800Y0062197D02*
+X0008050Y0062197D01*
+X0008050Y0062495D02*
+X0001800Y0062495D01*
+X0001800Y0062794D02*
+X0008050Y0062794D01*
+X0008050Y0063092D02*
+X0001800Y0063092D01*
+X0001800Y0063391D02*
+X0008050Y0063391D01*
+X0008050Y0063689D02*
+X0001800Y0063689D01*
+X0001800Y0063988D02*
+X0008050Y0063988D01*
+X0008050Y0064286D02*
+X0001800Y0064286D01*
+X0001800Y0064585D02*
+X0008050Y0064585D01*
+X0008050Y0064883D02*
+X0001800Y0064883D01*
+X0001800Y0065182D02*
+X0008050Y0065182D01*
+X0008050Y0065480D02*
+X0001800Y0065480D01*
+X0001800Y0065779D02*
+X0008050Y0065779D01*
+X0008050Y0066077D02*
+X0001800Y0066077D01*
+X0001800Y0066376D02*
+X0008050Y0066376D01*
+X0008050Y0066674D02*
+X0001800Y0066674D01*
+X0001800Y0066973D02*
+X0008050Y0066973D01*
+X0008050Y0067271D02*
+X0001800Y0067271D01*
+X0001800Y0067570D02*
+X0008050Y0067570D01*
+X0008050Y0067868D02*
+X0001800Y0067868D01*
+X0001800Y0068167D02*
+X0008050Y0068167D01*
+X0008050Y0068465D02*
+X0001800Y0068465D01*
+X0001800Y0068764D02*
+X0008050Y0068764D01*
+X0008050Y0069062D02*
+X0001800Y0069062D01*
+X0001800Y0069361D02*
+X0008050Y0069361D01*
+X0008050Y0069659D02*
+X0001800Y0069659D01*
+X0001800Y0069958D02*
+X0008050Y0069958D01*
+X0008050Y0070256D02*
+X0001800Y0070256D01*
+X0001800Y0070555D02*
+X0008050Y0070555D01*
+X0008050Y0070853D02*
+X0001800Y0070853D01*
+X0001800Y0071152D02*
+X0008050Y0071152D01*
+X0008050Y0071450D02*
+X0001800Y0071450D01*
+X0001800Y0071749D02*
+X0008050Y0071749D01*
+X0008050Y0072047D02*
+X0001800Y0072047D01*
+X0001800Y0072346D02*
+X0008050Y0072346D01*
+X0008050Y0072644D02*
+X0001800Y0072644D01*
+X0001800Y0072943D02*
+X0008050Y0072943D01*
+X0008050Y0073242D02*
+X0001800Y0073242D01*
+X0001800Y0073540D02*
+X0008050Y0073540D01*
+X0008050Y0073839D02*
+X0001800Y0073839D01*
+X0001800Y0074137D02*
+X0008050Y0074137D01*
+X0008050Y0074436D02*
+X0001800Y0074436D01*
+X0001800Y0074734D02*
+X0008050Y0074734D01*
+X0008050Y0075033D02*
+X0001800Y0075033D01*
+X0001800Y0075331D02*
+X0008050Y0075331D01*
+X0008050Y0075630D02*
+X0001800Y0075630D01*
+X0001800Y0075928D02*
+X0008050Y0075928D01*
+X0008050Y0076227D02*
+X0001800Y0076227D01*
+X0001800Y0076525D02*
+X0008050Y0076525D01*
+X0008050Y0076824D02*
+X0001800Y0076824D01*
+X0001800Y0077122D02*
+X0008050Y0077122D01*
+X0008050Y0077421D02*
+X0001800Y0077421D01*
+X0001800Y0077719D02*
+X0008050Y0077719D01*
+X0008050Y0078018D02*
+X0001800Y0078018D01*
+X0001800Y0078316D02*
+X0008050Y0078316D01*
+X0008050Y0078615D02*
+X0001800Y0078615D01*
+X0001800Y0078913D02*
+X0008050Y0078913D01*
+X0008050Y0079212D02*
+X0001800Y0079212D01*
+X0001800Y0079510D02*
+X0008050Y0079510D01*
+X0008050Y0079809D02*
+X0001800Y0079809D01*
+X0001800Y0080107D02*
+X0008050Y0080107D01*
+X0008050Y0080406D02*
+X0001800Y0080406D01*
+X0001800Y0080704D02*
+X0008050Y0080704D01*
+X0008050Y0081003D02*
+X0001800Y0081003D01*
+X0001800Y0081301D02*
+X0008050Y0081301D01*
+X0008050Y0081600D02*
+X0001800Y0081600D01*
+X0001800Y0081898D02*
+X0008050Y0081898D01*
+X0008050Y0082197D02*
+X0001800Y0082197D01*
+X0001800Y0082495D02*
+X0008050Y0082495D01*
+X0008050Y0082794D02*
+X0001800Y0082794D01*
+X0001800Y0083092D02*
+X0008050Y0083092D01*
+X0008050Y0083391D02*
+X0001800Y0083391D01*
+X0001800Y0083689D02*
+X0008050Y0083689D01*
+X0008050Y0083988D02*
+X0001800Y0083988D01*
+X0001800Y0084286D02*
+X0008050Y0084286D01*
+X0008050Y0084585D02*
+X0001800Y0084585D01*
+X0001800Y0084883D02*
+X0008050Y0084883D01*
+X0008050Y0085182D02*
+X0001800Y0085182D01*
+X0001800Y0085480D02*
+X0008050Y0085480D01*
+X0008050Y0085779D02*
+X0001800Y0085779D01*
+X0001800Y0086077D02*
+X0008050Y0086077D01*
+X0008050Y0086376D02*
+X0001800Y0086376D01*
+X0001800Y0086675D02*
+X0008050Y0086675D01*
+X0008050Y0086973D02*
+X0001800Y0086973D01*
+X0001800Y0087272D02*
+X0008050Y0087272D01*
+X0008050Y0087570D02*
+X0001800Y0087570D01*
+X0001800Y0087869D02*
+X0008050Y0087869D01*
+X0008050Y0088167D02*
+X0001800Y0088167D01*
+X0001800Y0088466D02*
+X0008050Y0088466D01*
+X0008050Y0088764D02*
+X0001800Y0088764D01*
+X0001800Y0089063D02*
+X0008050Y0089063D01*
+X0008050Y0089361D02*
+X0001800Y0089361D01*
+X0001800Y0089660D02*
+X0008050Y0089660D01*
+X0008050Y0089958D02*
+X0001800Y0089958D01*
+X0001800Y0090257D02*
+X0008050Y0090257D01*
+X0008050Y0090555D02*
+X0001800Y0090555D01*
+X0001800Y0090854D02*
+X0008050Y0090854D01*
+X0008050Y0091152D02*
+X0001800Y0091152D01*
+X0001800Y0091451D02*
+X0008050Y0091451D01*
+X0008050Y0091749D02*
+X0001800Y0091749D01*
+X0001800Y0092048D02*
+X0008050Y0092048D01*
+X0008050Y0092346D02*
+X0001800Y0092346D01*
+X0001800Y0092645D02*
+X0008050Y0092645D01*
+X0008050Y0092943D02*
+X0001800Y0092943D01*
+X0001800Y0093242D02*
+X0008050Y0093242D01*
+X0008050Y0093540D02*
+X0001800Y0093540D01*
+X0001800Y0093839D02*
+X0008050Y0093839D01*
+X0008050Y0094137D02*
+X0001800Y0094137D01*
+X0001800Y0094436D02*
+X0008050Y0094436D01*
+X0008050Y0094734D02*
+X0001800Y0094734D01*
+X0001800Y0095033D02*
+X0008050Y0095033D01*
+X0008050Y0095331D02*
+X0001800Y0095331D01*
+X0001800Y0095630D02*
+X0008050Y0095630D01*
+X0008050Y0095928D02*
+X0001800Y0095928D01*
+X0001800Y0096227D02*
+X0008050Y0096227D01*
+X0008050Y0096525D02*
+X0001800Y0096525D01*
+X0001800Y0096824D02*
+X0008050Y0096824D01*
+X0008050Y0097122D02*
+X0001800Y0097122D01*
+X0001800Y0097421D02*
+X0008050Y0097421D01*
+X0008050Y0097719D02*
+X0001800Y0097719D01*
+X0001800Y0098018D02*
+X0008050Y0098018D01*
+X0008050Y0098316D02*
+X0001800Y0098316D01*
+X0001800Y0098615D02*
+X0008050Y0098615D01*
+X0008050Y0098913D02*
+X0001800Y0098913D01*
+X0001800Y0099212D02*
+X0008050Y0099212D01*
+X0008050Y0099511D02*
+X0001800Y0099511D01*
+X0001800Y0099809D02*
+X0008050Y0099809D01*
+X0008050Y0100108D02*
+X0001800Y0100108D01*
+X0001800Y0100406D02*
+X0008050Y0100406D01*
+X0008050Y0100705D02*
+X0001800Y0100705D01*
+X0001800Y0101003D02*
+X0008050Y0101003D01*
+X0008050Y0101302D02*
+X0001800Y0101302D01*
+X0001800Y0101600D02*
+X0008050Y0101600D01*
+X0008050Y0101899D02*
+X0001800Y0101899D01*
+X0001800Y0102197D02*
+X0008050Y0102197D01*
+X0008050Y0102496D02*
+X0001800Y0102496D01*
+X0001800Y0102794D02*
+X0008050Y0102794D01*
+X0008050Y0103093D02*
+X0001800Y0103093D01*
+X0001800Y0103391D02*
+X0008050Y0103391D01*
+X0008050Y0103690D02*
+X0001800Y0103690D01*
+X0001800Y0103988D02*
+X0008050Y0103988D01*
+X0008050Y0104287D02*
+X0001800Y0104287D01*
+X0001800Y0104585D02*
+X0008050Y0104585D01*
+X0008050Y0104884D02*
+X0001800Y0104884D01*
+X0001800Y0105182D02*
+X0008050Y0105182D01*
+X0008050Y0105481D02*
+X0001800Y0105481D01*
+X0001800Y0105779D02*
+X0008050Y0105779D01*
+X0008050Y0106078D02*
+X0001800Y0106078D01*
+X0001800Y0106376D02*
+X0008050Y0106376D01*
+X0008050Y0106675D02*
+X0001800Y0106675D01*
+X0001800Y0106973D02*
+X0008050Y0106973D01*
+X0008050Y0107272D02*
+X0001800Y0107272D01*
+X0001800Y0107570D02*
+X0008050Y0107570D01*
+X0008050Y0107869D02*
+X0001800Y0107869D01*
+X0001800Y0108167D02*
+X0008050Y0108167D01*
+X0008050Y0108466D02*
+X0001800Y0108466D01*
+X0001800Y0108764D02*
+X0008050Y0108764D01*
+X0008050Y0109063D02*
+X0001800Y0109063D01*
+X0001800Y0109361D02*
+X0008050Y0109361D01*
+X0008050Y0109660D02*
+X0001800Y0109660D01*
+X0001800Y0109958D02*
+X0008050Y0109958D01*
+X0008050Y0110257D02*
+X0001800Y0110257D01*
+X0001800Y0110555D02*
+X0008050Y0110555D01*
+X0008050Y0110854D02*
+X0001800Y0110854D01*
+X0001800Y0111152D02*
+X0008050Y0111152D01*
+X0008050Y0111451D02*
+X0001800Y0111451D01*
+X0001800Y0111749D02*
+X0008050Y0111749D01*
+X0008050Y0112048D02*
+X0001800Y0112048D01*
+X0001800Y0112346D02*
+X0008050Y0112346D01*
+X0008050Y0112645D02*
+X0001800Y0112645D01*
+X0001800Y0112944D02*
+X0008050Y0112944D01*
+X0008050Y0113242D02*
+X0001800Y0113242D01*
+X0001800Y0113541D02*
+X0008050Y0113541D01*
+X0008050Y0113839D02*
+X0001800Y0113839D01*
+X0001800Y0114138D02*
+X0008050Y0114138D01*
+X0008050Y0114436D02*
+X0001800Y0114436D01*
+X0001800Y0114735D02*
+X0008050Y0114735D01*
+X0008050Y0115033D02*
+X0001800Y0115033D01*
+X0001800Y0115332D02*
+X0008050Y0115332D01*
+X0008050Y0115630D02*
+X0001800Y0115630D01*
+X0001800Y0115929D02*
+X0008050Y0115929D01*
+X0008050Y0116227D02*
+X0001800Y0116227D01*
+X0001800Y0116526D02*
+X0008050Y0116526D01*
+X0008050Y0116824D02*
+X0001800Y0116824D01*
+X0001800Y0117123D02*
+X0008050Y0117123D01*
+X0008050Y0117421D02*
+X0001800Y0117421D01*
+X0001800Y0117720D02*
+X0008050Y0117720D01*
+X0008050Y0118018D02*
+X0001800Y0118018D01*
+X0001800Y0118317D02*
+X0008050Y0118317D01*
+X0008050Y0118615D02*
+X0001800Y0118615D01*
+X0001800Y0118914D02*
+X0008050Y0118914D01*
+X0008050Y0119212D02*
+X0001800Y0119212D01*
+X0001800Y0119511D02*
+X0008050Y0119511D01*
+X0008050Y0119809D02*
+X0001800Y0119809D01*
+X0001800Y0120108D02*
+X0008050Y0120108D01*
+X0008050Y0120406D02*
+X0001800Y0120406D01*
+X0001800Y0120705D02*
+X0008050Y0120705D01*
+X0008050Y0121003D02*
+X0001800Y0121003D01*
+X0001800Y0121302D02*
+X0008050Y0121302D01*
+X0008050Y0121600D02*
+X0001800Y0121600D01*
+X0001800Y0121899D02*
+X0008050Y0121899D01*
+X0008050Y0122197D02*
+X0001800Y0122197D01*
+X0001800Y0122496D02*
+X0008050Y0122496D01*
+X0008050Y0122794D02*
+X0001800Y0122794D01*
+X0001800Y0123093D02*
+X0008050Y0123093D01*
+X0008050Y0123391D02*
+X0001800Y0123391D01*
+X0001800Y0123690D02*
+X0008050Y0123690D01*
+X0008050Y0123988D02*
+X0001800Y0123988D01*
+X0001800Y0124287D02*
+X0008050Y0124287D01*
+X0008050Y0124585D02*
+X0001800Y0124585D01*
+X0001800Y0124884D02*
+X0008050Y0124884D01*
+X0008050Y0125182D02*
+X0001800Y0125182D01*
+X0001800Y0125481D02*
+X0008050Y0125481D01*
+X0008050Y0125780D02*
+X0001800Y0125780D01*
+X0001800Y0126078D02*
+X0008050Y0126078D01*
+X0008050Y0126377D02*
+X0001800Y0126377D01*
+X0001800Y0126675D02*
+X0008050Y0126675D01*
+X0008050Y0126974D02*
+X0001800Y0126974D01*
+X0001800Y0127272D02*
+X0008050Y0127272D01*
+X0008050Y0127571D02*
+X0001800Y0127571D01*
+X0001800Y0127869D02*
+X0008050Y0127869D01*
+X0008050Y0128168D02*
+X0001800Y0128168D01*
+X0001800Y0128466D02*
+X0008050Y0128466D01*
+X0008050Y0128765D02*
+X0001800Y0128765D01*
+X0001800Y0129063D02*
+X0008050Y0129063D01*
+X0008050Y0129362D02*
+X0001800Y0129362D01*
+X0001800Y0129660D02*
+X0008050Y0129660D01*
+X0008050Y0129959D02*
+X0001800Y0129959D01*
+X0001800Y0130257D02*
+X0008050Y0130257D01*
+X0008050Y0130556D02*
+X0001800Y0130556D01*
+X0001800Y0130854D02*
+X0008050Y0130854D01*
+X0008050Y0131153D02*
+X0001800Y0131153D01*
+X0001800Y0131451D02*
+X0008050Y0131451D01*
+X0008050Y0131750D02*
+X0001800Y0131750D01*
+X0001800Y0132048D02*
+X0008050Y0132048D01*
+X0008050Y0132347D02*
+X0001800Y0132347D01*
+X0001800Y0132645D02*
+X0008050Y0132645D01*
+X0008050Y0132944D02*
+X0001800Y0132944D01*
+X0001800Y0133242D02*
+X0008050Y0133242D01*
+X0008050Y0133541D02*
+X0001800Y0133541D01*
+X0001800Y0133839D02*
+X0008050Y0133839D01*
+X0008050Y0134138D02*
+X0001800Y0134138D01*
+X0001800Y0134436D02*
+X0008050Y0134436D01*
+X0008050Y0134735D02*
+X0001800Y0134735D01*
+X0001800Y0135033D02*
+X0008050Y0135033D01*
+X0008050Y0135332D02*
+X0001800Y0135332D01*
+X0001800Y0135630D02*
+X0008050Y0135630D01*
+X0008050Y0135929D02*
+X0001800Y0135929D01*
+X0001800Y0136227D02*
+X0008050Y0136227D01*
+X0008050Y0136526D02*
+X0001800Y0136526D01*
+X0001800Y0136824D02*
+X0008050Y0136824D01*
+X0008050Y0137123D02*
+X0001800Y0137123D01*
+X0001800Y0137421D02*
+X0008050Y0137421D01*
+X0008050Y0137720D02*
+X0001800Y0137720D01*
+X0001800Y0138018D02*
+X0008050Y0138018D01*
+X0008050Y0138317D02*
+X0001800Y0138317D01*
+X0001800Y0138615D02*
+X0008050Y0138615D01*
+X0008050Y0138914D02*
+X0001800Y0138914D01*
+X0001800Y0139213D02*
+X0008050Y0139213D01*
+X0008050Y0139511D02*
+X0001800Y0139511D01*
+X0001800Y0139810D02*
+X0008050Y0139810D01*
+X0008050Y0140108D02*
+X0001800Y0140108D01*
+X0001800Y0140407D02*
+X0008050Y0140407D01*
+X0008050Y0140705D02*
+X0001800Y0140705D01*
+X0001800Y0141004D02*
+X0008050Y0141004D01*
+X0008050Y0141302D02*
+X0001800Y0141302D01*
+X0001800Y0141601D02*
+X0008050Y0141601D01*
+X0008050Y0141899D02*
+X0001800Y0141899D01*
+X0001800Y0142198D02*
+X0008050Y0142198D01*
+X0008050Y0142496D02*
+X0001800Y0142496D01*
+X0001800Y0142795D02*
+X0008050Y0142795D01*
+X0008050Y0143093D02*
+X0001800Y0143093D01*
+X0001800Y0143392D02*
+X0008050Y0143392D01*
+X0008050Y0143690D02*
+X0001800Y0143690D01*
+X0001800Y0143989D02*
+X0008050Y0143989D01*
+X0008050Y0144287D02*
+X0001800Y0144287D01*
+X0001800Y0144586D02*
+X0008050Y0144586D01*
+X0008050Y0144884D02*
+X0001800Y0144884D01*
+X0001800Y0145183D02*
+X0008050Y0145183D01*
+X0008050Y0145481D02*
+X0001800Y0145481D01*
+X0001800Y0145780D02*
+X0008050Y0145780D01*
+X0008050Y0146078D02*
+X0001800Y0146078D01*
+X0001800Y0146377D02*
+X0008050Y0146377D01*
+X0008050Y0146675D02*
+X0001800Y0146675D01*
+X0001800Y0146974D02*
+X0008050Y0146974D01*
+X0008050Y0147272D02*
+X0001800Y0147272D01*
+X0001800Y0147571D02*
+X0008050Y0147571D01*
+X0008050Y0147869D02*
+X0001800Y0147869D01*
+X0001800Y0148168D02*
+X0008050Y0148168D01*
+X0008050Y0148466D02*
+X0001800Y0148466D01*
+X0001800Y0148765D02*
+X0008050Y0148765D01*
+X0008050Y0149063D02*
+X0001800Y0149063D01*
+X0001800Y0149362D02*
+X0008050Y0149362D01*
+X0008050Y0149660D02*
+X0001800Y0149660D01*
+X0001800Y0149959D02*
+X0008050Y0149959D01*
+X0008050Y0150257D02*
+X0001800Y0150257D01*
+X0001800Y0150556D02*
+X0008050Y0150556D01*
+X0008050Y0150854D02*
+X0001800Y0150854D01*
+X0001800Y0151153D02*
+X0008050Y0151153D01*
+X0008050Y0151451D02*
+X0001800Y0151451D01*
+X0001800Y0151750D02*
+X0008050Y0151750D01*
+X0008050Y0152048D02*
+X0001800Y0152048D01*
+X0001800Y0152347D02*
+X0008050Y0152347D01*
+X0008050Y0152646D02*
+X0001800Y0152646D01*
+X0001800Y0152944D02*
+X0008050Y0152944D01*
+X0008050Y0153243D02*
+X0001800Y0153243D01*
+X0001800Y0153541D02*
+X0008050Y0153541D01*
+X0008050Y0153840D02*
+X0001800Y0153840D01*
+X0001800Y0154138D02*
+X0008050Y0154138D01*
+X0008050Y0154437D02*
+X0001800Y0154437D01*
+X0001800Y0154735D02*
+X0008050Y0154735D01*
+X0008050Y0155034D02*
+X0001800Y0155034D01*
+X0001800Y0155332D02*
+X0008050Y0155332D01*
+X0008050Y0155631D02*
+X0001800Y0155631D01*
+X0001800Y0155929D02*
+X0008050Y0155929D01*
+X0008050Y0156228D02*
+X0001800Y0156228D01*
+X0001800Y0156526D02*
+X0008050Y0156526D01*
+X0008050Y0156825D02*
+X0001800Y0156825D01*
+X0001800Y0157123D02*
+X0008050Y0157123D01*
+X0008050Y0157422D02*
+X0001800Y0157422D01*
+X0001800Y0157720D02*
+X0008050Y0157720D01*
+X0008050Y0158019D02*
+X0001800Y0158019D01*
+X0001800Y0158317D02*
+X0008050Y0158317D01*
+X0008050Y0158616D02*
+X0001800Y0158616D01*
+X0001800Y0158914D02*
+X0008050Y0158914D01*
+X0008050Y0159213D02*
+X0001800Y0159213D01*
+X0001800Y0159511D02*
+X0008050Y0159511D01*
+X0008050Y0159810D02*
+X0001800Y0159810D01*
+X0001800Y0160108D02*
+X0008050Y0160108D01*
+X0008050Y0160407D02*
+X0001800Y0160407D01*
+X0001800Y0160705D02*
+X0008050Y0160705D01*
+X0008050Y0161004D02*
+X0001800Y0161004D01*
+X0001800Y0161302D02*
+X0008050Y0161302D01*
+X0008050Y0161601D02*
+X0001800Y0161601D01*
+X0001800Y0161899D02*
+X0008050Y0161899D01*
+X0008050Y0162198D02*
+X0001800Y0162198D01*
+X0001800Y0162496D02*
+X0008050Y0162496D01*
+X0008050Y0162795D02*
+X0001800Y0162795D01*
+X0001800Y0163093D02*
+X0008050Y0163093D01*
+X0008050Y0163392D02*
+X0001800Y0163392D01*
+X0001800Y0163690D02*
+X0008050Y0163690D01*
+X0008050Y0163989D02*
+X0001800Y0163989D01*
+X0001800Y0164287D02*
+X0008050Y0164287D01*
+X0008050Y0164586D02*
+X0001800Y0164586D01*
+X0001800Y0164884D02*
+X0008050Y0164884D01*
+X0008050Y0165183D02*
+X0001800Y0165183D01*
+X0001800Y0165482D02*
+X0008050Y0165482D01*
+X0008050Y0165780D02*
+X0001800Y0165780D01*
+X0001800Y0166079D02*
+X0008050Y0166079D01*
+X0008050Y0166377D02*
+X0001800Y0166377D01*
+X0001800Y0166676D02*
+X0008050Y0166676D01*
+X0008050Y0166974D02*
+X0001800Y0166974D01*
+X0001800Y0167273D02*
+X0008050Y0167273D01*
+X0008050Y0167571D02*
+X0001800Y0167571D01*
+X0001800Y0167870D02*
+X0008050Y0167870D01*
+X0008050Y0168168D02*
+X0001800Y0168168D01*
+X0001800Y0168467D02*
+X0008050Y0168467D01*
+X0008050Y0168765D02*
+X0001800Y0168765D01*
+X0001800Y0169064D02*
+X0008050Y0169064D01*
+X0008050Y0169362D02*
+X0001800Y0169362D01*
+X0001800Y0169661D02*
+X0008050Y0169661D01*
+X0008050Y0169959D02*
+X0001800Y0169959D01*
+X0001800Y0170258D02*
+X0008050Y0170258D01*
+X0008050Y0170556D02*
+X0001800Y0170556D01*
+X0001800Y0170855D02*
+X0008050Y0170855D01*
+X0008050Y0171153D02*
+X0001800Y0171153D01*
+X0001800Y0171452D02*
+X0008050Y0171452D01*
+X0008050Y0171750D02*
+X0001800Y0171750D01*
+X0001800Y0172049D02*
+X0008050Y0172049D01*
+X0008050Y0172347D02*
+X0001800Y0172347D01*
+X0001800Y0172646D02*
+X0008050Y0172646D01*
+X0008050Y0172944D02*
+X0001800Y0172944D01*
+X0001800Y0173243D02*
+X0008050Y0173243D01*
+X0008050Y0173541D02*
+X0001800Y0173541D01*
+X0001800Y0173840D02*
+X0008050Y0173840D01*
+X0008050Y0174138D02*
+X0001800Y0174138D01*
+X0001800Y0174437D02*
+X0008050Y0174437D01*
+X0008050Y0174735D02*
+X0001800Y0174735D01*
+X0001800Y0175034D02*
+X0008050Y0175034D01*
+X0008050Y0175332D02*
+X0001800Y0175332D01*
+X0001800Y0175631D02*
+X0008050Y0175631D01*
+X0008050Y0175929D02*
+X0001800Y0175929D01*
+X0001800Y0176228D02*
+X0008050Y0176228D01*
+X0008050Y0176526D02*
+X0001800Y0176526D01*
+X0001800Y0176825D02*
+X0008050Y0176825D01*
+X0008050Y0177123D02*
+X0001800Y0177123D01*
+X0001800Y0177422D02*
+X0008050Y0177422D01*
+X0008050Y0177720D02*
+X0001800Y0177720D01*
+X0001800Y0178019D02*
+X0008050Y0178019D01*
+X0008050Y0178317D02*
+X0001800Y0178317D01*
+X0001800Y0178616D02*
+X0008050Y0178616D01*
+X0008050Y0178915D02*
+X0001800Y0178915D01*
+X0001800Y0179213D02*
+X0008050Y0179213D01*
+X0008050Y0179512D02*
+X0001800Y0179512D01*
+X0001800Y0179810D02*
+X0008050Y0179810D01*
+X0008050Y0180109D02*
+X0001800Y0180109D01*
+X0001800Y0180407D02*
+X0008050Y0180407D01*
+X0008050Y0180706D02*
+X0001800Y0180706D01*
+X0001800Y0181004D02*
+X0008050Y0181004D01*
+X0008050Y0181303D02*
+X0001800Y0181303D01*
+X0001800Y0181601D02*
+X0008050Y0181601D01*
+X0008050Y0181900D02*
+X0001800Y0181900D01*
+X0001800Y0182198D02*
+X0008050Y0182198D01*
+X0008050Y0182497D02*
+X0001800Y0182497D01*
+X0001800Y0182795D02*
+X0008050Y0182795D01*
+X0008050Y0183094D02*
+X0001800Y0183094D01*
+X0001800Y0183392D02*
+X0008050Y0183392D01*
+X0008050Y0183691D02*
+X0001800Y0183691D01*
+X0001800Y0183989D02*
+X0008050Y0183989D01*
+X0008050Y0184288D02*
+X0001800Y0184288D01*
+X0001800Y0184586D02*
+X0008050Y0184586D01*
+X0008050Y0184885D02*
+X0001800Y0184885D01*
+X0001800Y0185183D02*
+X0008050Y0185183D01*
+X0008050Y0185482D02*
+X0001800Y0185482D01*
+X0001800Y0185780D02*
+X0008050Y0185780D01*
+X0008050Y0186079D02*
+X0001800Y0186079D01*
+X0001800Y0186377D02*
+X0008050Y0186377D01*
+X0008050Y0186676D02*
+X0001800Y0186676D01*
+X0001800Y0186974D02*
+X0008050Y0186974D01*
+X0008050Y0187273D02*
+X0001800Y0187273D01*
+X0001800Y0187571D02*
+X0008050Y0187571D01*
+X0008050Y0187870D02*
+X0001800Y0187870D01*
+X0001800Y0188168D02*
+X0008050Y0188168D01*
+X0008050Y0188467D02*
+X0001800Y0188467D01*
+X0001800Y0188765D02*
+X0008050Y0188765D01*
+X0008050Y0189064D02*
+X0001800Y0189064D01*
+X0001800Y0189362D02*
+X0008050Y0189362D01*
+X0008050Y0189661D02*
+X0001800Y0189661D01*
+X0001800Y0189959D02*
+X0008050Y0189959D01*
+X0008050Y0190258D02*
+X0001800Y0190258D01*
+X0001800Y0190556D02*
+X0008050Y0190556D01*
+X0008050Y0190855D02*
+X0001800Y0190855D01*
+X0001800Y0191153D02*
+X0008050Y0191153D01*
+X0008050Y0191452D02*
+X0001800Y0191452D01*
+X0001800Y0191751D02*
+X0008050Y0191751D01*
+X0008050Y0192049D02*
+X0001800Y0192049D01*
+X0001800Y0192348D02*
+X0008050Y0192348D01*
+X0008050Y0192646D02*
+X0001800Y0192646D01*
+X0001800Y0192945D02*
+X0008050Y0192945D01*
+X0008050Y0193243D02*
+X0001800Y0193243D01*
+X0001800Y0193542D02*
+X0008050Y0193542D01*
+X0008050Y0193840D02*
+X0001800Y0193840D01*
+X0001800Y0194139D02*
+X0008050Y0194139D01*
+X0008050Y0194437D02*
+X0001800Y0194437D01*
+X0001800Y0194736D02*
+X0008050Y0194736D01*
+X0008050Y0195034D02*
+X0001800Y0195034D01*
+X0001800Y0195333D02*
+X0008050Y0195333D01*
+X0008050Y0195631D02*
+X0001800Y0195631D01*
+X0001800Y0195930D02*
+X0008050Y0195930D01*
+X0008050Y0196228D02*
+X0001800Y0196228D01*
+X0001800Y0196527D02*
+X0008050Y0196527D01*
+X0008050Y0196825D02*
+X0001800Y0196825D01*
+X0001800Y0197124D02*
+X0008050Y0197124D01*
+X0008050Y0197422D02*
+X0001800Y0197422D01*
+X0001800Y0197721D02*
+X0008050Y0197721D01*
+X0008050Y0198019D02*
+X0001800Y0198019D01*
+X0001800Y0198318D02*
+X0008050Y0198318D01*
+X0008050Y0198616D02*
+X0001800Y0198616D01*
+X0001800Y0198915D02*
+X0008050Y0198915D01*
+X0008050Y0199213D02*
+X0001800Y0199213D01*
+X0001800Y0199512D02*
+X0008050Y0199512D01*
+X0008050Y0199810D02*
+X0001800Y0199810D01*
+X0001800Y0200109D02*
+X0008050Y0200109D01*
+X0008050Y0200407D02*
+X0001800Y0200407D01*
+X0001800Y0200706D02*
+X0008050Y0200706D01*
+X0008050Y0201004D02*
+X0001800Y0201004D01*
+X0001800Y0201303D02*
+X0008050Y0201303D01*
+X0008050Y0201601D02*
+X0001800Y0201601D01*
+X0001800Y0201900D02*
+X0008050Y0201900D01*
+X0008050Y0202198D02*
+X0001800Y0202198D01*
+X0001800Y0202497D02*
+X0008050Y0202497D01*
+X0008050Y0202795D02*
+X0001800Y0202795D01*
+X0001800Y0203094D02*
+X0008050Y0203094D01*
+X0008050Y0203392D02*
+X0001800Y0203392D01*
+X0001800Y0203691D02*
+X0008050Y0203691D01*
+X0008050Y0203989D02*
+X0001800Y0203989D01*
+X0001800Y0204288D02*
+X0008050Y0204288D01*
+X0008050Y0204586D02*
+X0001800Y0204586D01*
+X0001800Y0204885D02*
+X0008050Y0204885D01*
+X0008050Y0205184D02*
+X0001800Y0205184D01*
+X0001800Y0205482D02*
+X0008050Y0205482D01*
+X0008050Y0205781D02*
+X0001800Y0205781D01*
+X0001800Y0206079D02*
+X0008050Y0206079D01*
+X0008050Y0206378D02*
+X0001800Y0206378D01*
+X0001800Y0206676D02*
+X0008050Y0206676D01*
+X0008050Y0206975D02*
+X0001800Y0206975D01*
+X0001800Y0207273D02*
+X0008050Y0207273D01*
+X0008050Y0207572D02*
+X0001800Y0207572D01*
+X0001800Y0207870D02*
+X0008050Y0207870D01*
+X0008050Y0208169D02*
+X0001800Y0208169D01*
+X0001800Y0208467D02*
+X0008050Y0208467D01*
+X0008050Y0208766D02*
+X0001800Y0208766D01*
+X0001800Y0209064D02*
+X0008050Y0209064D01*
+X0008050Y0209363D02*
+X0001800Y0209363D01*
+X0001800Y0209661D02*
+X0008050Y0209661D01*
+X0008050Y0209960D02*
+X0001800Y0209960D01*
+X0001800Y0210258D02*
+X0008050Y0210258D01*
+X0008050Y0210557D02*
+X0001800Y0210557D01*
+X0001800Y0210855D02*
+X0008050Y0210855D01*
+X0008050Y0211154D02*
+X0001800Y0211154D01*
+X0001800Y0211452D02*
+X0008050Y0211452D01*
+X0008050Y0211751D02*
+X0001800Y0211751D01*
+X0001800Y0212049D02*
+X0008050Y0212049D01*
+X0008050Y0212348D02*
+X0001800Y0212348D01*
+X0001800Y0212646D02*
+X0008050Y0212646D01*
+X0008050Y0212945D02*
+X0001800Y0212945D01*
+X0001800Y0213243D02*
+X0008050Y0213243D01*
+X0008050Y0213542D02*
+X0001800Y0213542D01*
+X0001800Y0213840D02*
+X0008050Y0213840D01*
+X0008050Y0214139D02*
+X0001800Y0214139D01*
+X0001800Y0214437D02*
+X0008050Y0214437D01*
+X0008050Y0214736D02*
+X0001800Y0214736D01*
+X0001800Y0215034D02*
+X0008050Y0215034D01*
+X0008050Y0215333D02*
+X0001800Y0215333D01*
+X0001800Y0215631D02*
+X0008050Y0215631D01*
+X0008050Y0215930D02*
+X0001800Y0215930D01*
+X0001800Y0216228D02*
+X0008050Y0216228D01*
+X0008050Y0216527D02*
+X0001800Y0216527D01*
+X0001800Y0216825D02*
+X0008050Y0216825D01*
+X0008050Y0217124D02*
+X0001800Y0217124D01*
+X0001800Y0217422D02*
+X0008050Y0217422D01*
+X0008050Y0217721D02*
+X0001800Y0217721D01*
+X0001800Y0218020D02*
+X0008050Y0218020D01*
+X0008050Y0218318D02*
+X0001800Y0218318D01*
+X0001800Y0218617D02*
+X0008050Y0218617D01*
+X0008050Y0218915D02*
+X0001800Y0218915D01*
+X0001800Y0219214D02*
+X0008050Y0219214D01*
+X0008050Y0219512D02*
+X0001800Y0219512D01*
+X0001800Y0219811D02*
+X0008050Y0219811D01*
+X0008050Y0220109D02*
+X0001800Y0220109D01*
+X0001800Y0220408D02*
+X0008050Y0220408D01*
+X0008050Y0220706D02*
+X0001800Y0220706D01*
+X0001800Y0221005D02*
+X0008050Y0221005D01*
+X0008050Y0221303D02*
+X0001800Y0221303D01*
+X0001800Y0221602D02*
+X0008050Y0221602D01*
+X0008050Y0221900D02*
+X0001800Y0221900D01*
+X0001800Y0222199D02*
+X0008050Y0222199D01*
+X0008050Y0222497D02*
+X0001800Y0222497D01*
+X0001800Y0222796D02*
+X0008050Y0222796D01*
+X0008050Y0223094D02*
+X0001800Y0223094D01*
+X0001800Y0223393D02*
+X0008050Y0223393D01*
+X0008050Y0223691D02*
+X0001800Y0223691D01*
+X0001800Y0223990D02*
+X0008050Y0223990D01*
+X0008050Y0224288D02*
+X0001800Y0224288D01*
+X0001800Y0224587D02*
+X0008050Y0224587D01*
+X0008050Y0224885D02*
+X0001800Y0224885D01*
+X0001800Y0225184D02*
+X0008050Y0225184D01*
+X0008050Y0225482D02*
+X0001800Y0225482D01*
+X0001800Y0225781D02*
+X0008050Y0225781D01*
+X0008050Y0226079D02*
+X0001800Y0226079D01*
+X0001800Y0226378D02*
+X0008050Y0226378D01*
+X0008050Y0226676D02*
+X0001800Y0226676D01*
+X0001800Y0226975D02*
+X0008050Y0226975D01*
+X0008050Y0227273D02*
+X0001800Y0227273D01*
+X0001800Y0227572D02*
+X0008050Y0227572D01*
+X0008050Y0227870D02*
+X0001800Y0227870D01*
+X0001800Y0228169D02*
+X0008050Y0228169D01*
+X0008050Y0228467D02*
+X0001800Y0228467D01*
+X0001800Y0228766D02*
+X0008050Y0228766D01*
+X0008050Y0229064D02*
+X0001800Y0229064D01*
+X0001800Y0229363D02*
+X0008050Y0229363D01*
+X0008050Y0229661D02*
+X0001800Y0229661D01*
+X0001800Y0229960D02*
+X0008050Y0229960D01*
+X0008050Y0230258D02*
+X0001800Y0230258D01*
+X0001800Y0230557D02*
+X0008050Y0230557D01*
+X0008050Y0230855D02*
+X0001800Y0230855D01*
+X0001800Y0231154D02*
+X0008050Y0231154D01*
+X0008050Y0231453D02*
+X0001800Y0231453D01*
+X0001800Y0231751D02*
+X0008050Y0231751D01*
+X0008050Y0232050D02*
+X0001800Y0232050D01*
+X0001800Y0232348D02*
+X0008050Y0232348D01*
+X0008050Y0232647D02*
+X0001800Y0232647D01*
+X0001800Y0232945D02*
+X0008050Y0232945D01*
+X0008050Y0233244D02*
+X0001800Y0233244D01*
+X0001800Y0233542D02*
+X0008050Y0233542D01*
+X0008050Y0233841D02*
+X0001800Y0233841D01*
+X0001800Y0234139D02*
+X0008050Y0234139D01*
+X0008050Y0234438D02*
+X0001800Y0234438D01*
+X0001800Y0234736D02*
+X0008050Y0234736D01*
+X0008050Y0235035D02*
+X0001800Y0235035D01*
+X0001800Y0235333D02*
+X0008050Y0235333D01*
+X0008050Y0235632D02*
+X0001800Y0235632D01*
+X0001800Y0235930D02*
+X0008050Y0235930D01*
+X0008050Y0236229D02*
+X0001800Y0236229D01*
+X0001800Y0236527D02*
+X0008050Y0236527D01*
+X0008050Y0236826D02*
+X0001800Y0236826D01*
+X0001800Y0237124D02*
+X0008050Y0237124D01*
+X0008050Y0237423D02*
+X0001800Y0237423D01*
+X0001800Y0237721D02*
+X0008050Y0237721D01*
+X0008050Y0238020D02*
+X0001800Y0238020D01*
+X0001800Y0238318D02*
+X0008050Y0238318D01*
+X0008050Y0238617D02*
+X0001800Y0238617D01*
+X0001800Y0238915D02*
+X0008050Y0238915D01*
+X0008050Y0239214D02*
+X0001800Y0239214D01*
+X0001800Y0239512D02*
+X0008050Y0239512D01*
+X0008050Y0239811D02*
+X0001800Y0239811D01*
+X0001800Y0240109D02*
+X0008050Y0240109D01*
+X0008050Y0240408D02*
+X0001800Y0240408D01*
+X0001800Y0240706D02*
+X0008050Y0240706D01*
+X0008050Y0241005D02*
+X0001800Y0241005D01*
+X0001800Y0241303D02*
+X0008050Y0241303D01*
+X0008050Y0241602D02*
+X0001800Y0241602D01*
+X0001800Y0241900D02*
+X0008050Y0241900D01*
+X0008050Y0242199D02*
+X0001800Y0242199D01*
+X0001800Y0242497D02*
+X0008050Y0242497D01*
+X0008050Y0242796D02*
+X0001800Y0242796D01*
+X0001800Y0243094D02*
+X0008050Y0243094D01*
+X0008050Y0243393D02*
+X0001800Y0243393D01*
+X0001800Y0243691D02*
+X0008050Y0243691D01*
+X0008050Y0243990D02*
+X0001800Y0243990D01*
+X0001800Y0244288D02*
+X0008050Y0244288D01*
+X0008050Y0244587D02*
+X0001800Y0244587D01*
+X0001800Y0244886D02*
+X0008050Y0244886D01*
+X0008050Y0245184D02*
+X0001800Y0245184D01*
+X0001800Y0245483D02*
+X0008050Y0245483D01*
+X0008050Y0245781D02*
+X0001800Y0245781D01*
+X0001800Y0246080D02*
+X0008050Y0246080D01*
+X0008050Y0246378D02*
+X0001800Y0246378D01*
+X0001800Y0246677D02*
+X0008050Y0246677D01*
+X0008050Y0246975D02*
+X0001800Y0246975D01*
+X0001800Y0247274D02*
+X0008050Y0247274D01*
+X0008050Y0247572D02*
+X0001800Y0247572D01*
+X0001800Y0247871D02*
+X0008050Y0247871D01*
+X0008050Y0248169D02*
+X0001800Y0248169D01*
+X0001800Y0248468D02*
+X0008050Y0248468D01*
+X0008050Y0248766D02*
+X0001800Y0248766D01*
+X0001800Y0249065D02*
+X0008050Y0249065D01*
+X0008050Y0249363D02*
+X0001800Y0249363D01*
+X0001800Y0249662D02*
+X0008050Y0249662D01*
+X0008050Y0249960D02*
+X0001800Y0249960D01*
+X0001800Y0250259D02*
+X0008050Y0250259D01*
+X0008050Y0250557D02*
+X0001800Y0250557D01*
+X0001800Y0250856D02*
+X0008050Y0250856D01*
+X0008050Y0251154D02*
+X0001800Y0251154D01*
+X0001800Y0251453D02*
+X0008050Y0251453D01*
+X0008050Y0251751D02*
+X0001800Y0251751D01*
+X0001800Y0252050D02*
+X0008050Y0252050D01*
+X0008050Y0252348D02*
+X0001800Y0252348D01*
+X0001800Y0252647D02*
+X0008050Y0252647D01*
+X0008050Y0252945D02*
+X0001800Y0252945D01*
+X0001800Y0253244D02*
+X0008050Y0253244D01*
+X0008050Y0253542D02*
+X0001800Y0253542D01*
+X0001800Y0253841D02*
+X0008050Y0253841D01*
+X0008050Y0254139D02*
+X0001800Y0254139D01*
+X0001800Y0254438D02*
+X0008050Y0254438D01*
+X0008050Y0254736D02*
+X0001800Y0254736D01*
+X0001800Y0255035D02*
+X0008050Y0255035D01*
+X0008050Y0255333D02*
+X0001800Y0255333D01*
+X0001800Y0255632D02*
+X0008050Y0255632D01*
+X0008050Y0255930D02*
+X0001800Y0255930D01*
+X0001800Y0256229D02*
+X0008050Y0256229D01*
+X0008050Y0256527D02*
+X0001800Y0256527D01*
+X0001800Y0256826D02*
+X0008050Y0256826D01*
+X0008050Y0257124D02*
+X0001800Y0257124D01*
+X0001800Y0257423D02*
+X0008050Y0257423D01*
+X0008050Y0257722D02*
+X0001800Y0257722D01*
+X0001800Y0258020D02*
+X0008050Y0258020D01*
+X0008050Y0258319D02*
+X0001800Y0258319D01*
+X0001800Y0258617D02*
+X0008050Y0258617D01*
+X0008050Y0258916D02*
+X0001800Y0258916D01*
+X0001800Y0259214D02*
+X0008050Y0259214D01*
+X0008050Y0259513D02*
+X0001800Y0259513D01*
+X0001800Y0259811D02*
+X0008050Y0259811D01*
+X0008050Y0260110D02*
+X0001800Y0260110D01*
+X0001800Y0260408D02*
+X0008050Y0260408D01*
+X0008050Y0260707D02*
+X0001800Y0260707D01*
+X0001800Y0261005D02*
+X0008050Y0261005D01*
+X0008050Y0261304D02*
+X0001800Y0261304D01*
+X0001800Y0261602D02*
+X0008050Y0261602D01*
+X0008050Y0261901D02*
+X0001800Y0261901D01*
+X0001800Y0262199D02*
+X0008050Y0262199D01*
+X0008050Y0262498D02*
+X0001800Y0262498D01*
+X0001800Y0262796D02*
+X0008050Y0262796D01*
+X0008050Y0263095D02*
+X0001800Y0263095D01*
+X0001800Y0263393D02*
+X0008050Y0263393D01*
+X0008050Y0263692D02*
+X0001800Y0263692D01*
+X0001800Y0263990D02*
+X0008050Y0263990D01*
+X0008050Y0264289D02*
+X0001800Y0264289D01*
+X0001800Y0264587D02*
+X0008050Y0264587D01*
+X0008050Y0264886D02*
+X0001800Y0264886D01*
+X0001800Y0265184D02*
+X0008050Y0265184D01*
+X0008050Y0265483D02*
+X0001800Y0265483D01*
+X0001800Y0265781D02*
+X0008050Y0265781D01*
+X0008050Y0266080D02*
+X0001800Y0266080D01*
+X0001800Y0266378D02*
+X0008050Y0266378D01*
+X0008050Y0266677D02*
+X0001800Y0266677D01*
+X0001800Y0266975D02*
+X0008050Y0266975D01*
+X0008050Y0267274D02*
+X0001800Y0267274D01*
+X0001800Y0267572D02*
+X0008050Y0267572D01*
+X0008050Y0267871D02*
+X0001800Y0267871D01*
+X0001800Y0268169D02*
+X0008050Y0268169D01*
+X0008050Y0268468D02*
+X0001800Y0268468D01*
+X0001800Y0268766D02*
+X0008050Y0268766D01*
+X0008050Y0269065D02*
+X0001800Y0269065D01*
+X0001800Y0269363D02*
+X0008050Y0269363D01*
+X0008050Y0269662D02*
+X0001800Y0269662D01*
+X0001800Y0269960D02*
+X0008050Y0269960D01*
+X0008050Y0270259D02*
+X0001800Y0270259D01*
+X0001800Y0270557D02*
+X0008050Y0270557D01*
+X0008050Y0270856D02*
+X0001800Y0270856D01*
+X0001800Y0271155D02*
+X0008050Y0271155D01*
+X0008050Y0271453D02*
+X0001800Y0271453D01*
+X0001800Y0271752D02*
+X0008050Y0271752D01*
+X0008050Y0272050D02*
+X0001800Y0272050D01*
+X0001800Y0272349D02*
+X0008050Y0272349D01*
+X0008050Y0272647D02*
+X0001800Y0272647D01*
+X0001800Y0272946D02*
+X0008050Y0272946D01*
+X0008050Y0273244D02*
+X0001800Y0273244D01*
+X0001800Y0273543D02*
+X0008050Y0273543D01*
+X0008050Y0273841D02*
+X0001800Y0273841D01*
+X0001800Y0274140D02*
+X0008050Y0274140D01*
+X0008050Y0274438D02*
+X0001800Y0274438D01*
+X0001800Y0274737D02*
+X0008050Y0274737D01*
+X0008050Y0275035D02*
+X0001800Y0275035D01*
+X0001800Y0275334D02*
+X0008050Y0275334D01*
+X0008050Y0275632D02*
+X0001800Y0275632D01*
+X0001800Y0275931D02*
+X0008050Y0275931D01*
+X0008050Y0276229D02*
+X0001800Y0276229D01*
+X0001800Y0276528D02*
+X0008050Y0276528D01*
+X0008050Y0276826D02*
+X0001800Y0276826D01*
+X0001800Y0277125D02*
+X0008050Y0277125D01*
+X0008050Y0277423D02*
+X0001800Y0277423D01*
+X0001800Y0277722D02*
+X0008050Y0277722D01*
+X0008050Y0278020D02*
+X0001800Y0278020D01*
+X0001800Y0278319D02*
+X0008050Y0278319D01*
+X0008050Y0278617D02*
+X0001800Y0278617D01*
+X0001800Y0278916D02*
+X0008050Y0278916D01*
+X0008050Y0279214D02*
+X0001800Y0279214D01*
+X0001800Y0279513D02*
+X0008050Y0279513D01*
+X0371800Y0279547D02*
+X0371800Y0012047D01*
+X0378050Y0012047D01*
+X0378050Y0279547D01*
+X0371800Y0279547D01*
+X0371800Y0279513D02*
+X0378050Y0279513D01*
+X0378050Y0279214D02*
+X0371800Y0279214D01*
+X0371800Y0278916D02*
+X0378050Y0278916D01*
+X0378050Y0278617D02*
+X0371800Y0278617D01*
+X0371800Y0278319D02*
+X0378050Y0278319D01*
+X0378050Y0278020D02*
+X0371800Y0278020D01*
+X0371800Y0277722D02*
+X0378050Y0277722D01*
+X0378050Y0277423D02*
+X0371800Y0277423D01*
+X0371800Y0277125D02*
+X0378050Y0277125D01*
+X0378050Y0276826D02*
+X0371800Y0276826D01*
+X0371800Y0276528D02*
+X0378050Y0276528D01*
+X0378050Y0276229D02*
+X0371800Y0276229D01*
+X0371800Y0275931D02*
+X0378050Y0275931D01*
+X0378050Y0275632D02*
+X0371800Y0275632D01*
+X0371800Y0275334D02*
+X0378050Y0275334D01*
+X0378050Y0275035D02*
+X0371800Y0275035D01*
+X0371800Y0274737D02*
+X0378050Y0274737D01*
+X0378050Y0274438D02*
+X0371800Y0274438D01*
+X0371800Y0274140D02*
+X0378050Y0274140D01*
+X0378050Y0273841D02*
+X0371800Y0273841D01*
+X0371800Y0273543D02*
+X0378050Y0273543D01*
+X0378050Y0273244D02*
+X0371800Y0273244D01*
+X0371800Y0272946D02*
+X0378050Y0272946D01*
+X0378050Y0272647D02*
+X0371800Y0272647D01*
+X0371800Y0272349D02*
+X0378050Y0272349D01*
+X0378050Y0272050D02*
+X0371800Y0272050D01*
+X0371800Y0271752D02*
+X0378050Y0271752D01*
+X0378050Y0271453D02*
+X0371800Y0271453D01*
+X0371800Y0271155D02*
+X0378050Y0271155D01*
+X0378050Y0270856D02*
+X0371800Y0270856D01*
+X0371800Y0270557D02*
+X0378050Y0270557D01*
+X0378050Y0270259D02*
+X0371800Y0270259D01*
+X0371800Y0269960D02*
+X0378050Y0269960D01*
+X0378050Y0269662D02*
+X0371800Y0269662D01*
+X0371800Y0269363D02*
+X0378050Y0269363D01*
+X0378050Y0269065D02*
+X0371800Y0269065D01*
+X0371800Y0268766D02*
+X0378050Y0268766D01*
+X0378050Y0268468D02*
+X0371800Y0268468D01*
+X0371800Y0268169D02*
+X0378050Y0268169D01*
+X0378050Y0267871D02*
+X0371800Y0267871D01*
+X0371800Y0267572D02*
+X0378050Y0267572D01*
+X0378050Y0267274D02*
+X0371800Y0267274D01*
+X0371800Y0266975D02*
+X0378050Y0266975D01*
+X0378050Y0266677D02*
+X0371800Y0266677D01*
+X0371800Y0266378D02*
+X0378050Y0266378D01*
+X0378050Y0266080D02*
+X0371800Y0266080D01*
+X0371800Y0265781D02*
+X0378050Y0265781D01*
+X0378050Y0265483D02*
+X0371800Y0265483D01*
+X0371800Y0265184D02*
+X0378050Y0265184D01*
+X0378050Y0264886D02*
+X0371800Y0264886D01*
+X0371800Y0264587D02*
+X0378050Y0264587D01*
+X0378050Y0264289D02*
+X0371800Y0264289D01*
+X0371800Y0263990D02*
+X0378050Y0263990D01*
+X0378050Y0263692D02*
+X0371800Y0263692D01*
+X0371800Y0263393D02*
+X0378050Y0263393D01*
+X0378050Y0263095D02*
+X0371800Y0263095D01*
+X0371800Y0262796D02*
+X0378050Y0262796D01*
+X0378050Y0262498D02*
+X0371800Y0262498D01*
+X0371800Y0262199D02*
+X0378050Y0262199D01*
+X0378050Y0261901D02*
+X0371800Y0261901D01*
+X0371800Y0261602D02*
+X0378050Y0261602D01*
+X0378050Y0261304D02*
+X0371800Y0261304D01*
+X0371800Y0261005D02*
+X0378050Y0261005D01*
+X0378050Y0260707D02*
+X0371800Y0260707D01*
+X0371800Y0260408D02*
+X0378050Y0260408D01*
+X0378050Y0260110D02*
+X0371800Y0260110D01*
+X0371800Y0259811D02*
+X0378050Y0259811D01*
+X0378050Y0259513D02*
+X0371800Y0259513D01*
+X0371800Y0259214D02*
+X0378050Y0259214D01*
+X0378050Y0258916D02*
+X0371800Y0258916D01*
+X0371800Y0258617D02*
+X0378050Y0258617D01*
+X0378050Y0258319D02*
+X0371800Y0258319D01*
+X0371800Y0258020D02*
+X0378050Y0258020D01*
+X0378050Y0257722D02*
+X0371800Y0257722D01*
+X0371800Y0257423D02*
+X0378050Y0257423D01*
+X0378050Y0257124D02*
+X0371800Y0257124D01*
+X0371800Y0256826D02*
+X0378050Y0256826D01*
+X0378050Y0256527D02*
+X0371800Y0256527D01*
+X0371800Y0256229D02*
+X0378050Y0256229D01*
+X0378050Y0255930D02*
+X0371800Y0255930D01*
+X0371800Y0255632D02*
+X0378050Y0255632D01*
+X0378050Y0255333D02*
+X0371800Y0255333D01*
+X0371800Y0255035D02*
+X0378050Y0255035D01*
+X0378050Y0254736D02*
+X0371800Y0254736D01*
+X0371800Y0254438D02*
+X0378050Y0254438D01*
+X0378050Y0254139D02*
+X0371800Y0254139D01*
+X0371800Y0253841D02*
+X0378050Y0253841D01*
+X0378050Y0253542D02*
+X0371800Y0253542D01*
+X0371800Y0253244D02*
+X0378050Y0253244D01*
+X0378050Y0252945D02*
+X0371800Y0252945D01*
+X0371800Y0252647D02*
+X0378050Y0252647D01*
+X0378050Y0252348D02*
+X0371800Y0252348D01*
+X0371800Y0252050D02*
+X0378050Y0252050D01*
+X0378050Y0251751D02*
+X0371800Y0251751D01*
+X0371800Y0251453D02*
+X0378050Y0251453D01*
+X0378050Y0251154D02*
+X0371800Y0251154D01*
+X0371800Y0250856D02*
+X0378050Y0250856D01*
+X0378050Y0250557D02*
+X0371800Y0250557D01*
+X0371800Y0250259D02*
+X0378050Y0250259D01*
+X0378050Y0249960D02*
+X0371800Y0249960D01*
+X0371800Y0249662D02*
+X0378050Y0249662D01*
+X0378050Y0249363D02*
+X0371800Y0249363D01*
+X0371800Y0249065D02*
+X0378050Y0249065D01*
+X0378050Y0248766D02*
+X0371800Y0248766D01*
+X0371800Y0248468D02*
+X0378050Y0248468D01*
+X0378050Y0248169D02*
+X0371800Y0248169D01*
+X0371800Y0247871D02*
+X0378050Y0247871D01*
+X0378050Y0247572D02*
+X0371800Y0247572D01*
+X0371800Y0247274D02*
+X0378050Y0247274D01*
+X0378050Y0246975D02*
+X0371800Y0246975D01*
+X0371800Y0246677D02*
+X0378050Y0246677D01*
+X0378050Y0246378D02*
+X0371800Y0246378D01*
+X0371800Y0246080D02*
+X0378050Y0246080D01*
+X0378050Y0245781D02*
+X0371800Y0245781D01*
+X0371800Y0245483D02*
+X0378050Y0245483D01*
+X0378050Y0245184D02*
+X0371800Y0245184D01*
+X0371800Y0244886D02*
+X0378050Y0244886D01*
+X0378050Y0244587D02*
+X0371800Y0244587D01*
+X0371800Y0244288D02*
+X0378050Y0244288D01*
+X0378050Y0243990D02*
+X0371800Y0243990D01*
+X0371800Y0243691D02*
+X0378050Y0243691D01*
+X0378050Y0243393D02*
+X0371800Y0243393D01*
+X0371800Y0243094D02*
+X0378050Y0243094D01*
+X0378050Y0242796D02*
+X0371800Y0242796D01*
+X0371800Y0242497D02*
+X0378050Y0242497D01*
+X0378050Y0242199D02*
+X0371800Y0242199D01*
+X0371800Y0241900D02*
+X0378050Y0241900D01*
+X0378050Y0241602D02*
+X0371800Y0241602D01*
+X0371800Y0241303D02*
+X0378050Y0241303D01*
+X0378050Y0241005D02*
+X0371800Y0241005D01*
+X0371800Y0240706D02*
+X0378050Y0240706D01*
+X0378050Y0240408D02*
+X0371800Y0240408D01*
+X0371800Y0240109D02*
+X0378050Y0240109D01*
+X0378050Y0239811D02*
+X0371800Y0239811D01*
+X0371800Y0239512D02*
+X0378050Y0239512D01*
+X0378050Y0239214D02*
+X0371800Y0239214D01*
+X0371800Y0238915D02*
+X0378050Y0238915D01*
+X0378050Y0238617D02*
+X0371800Y0238617D01*
+X0371800Y0238318D02*
+X0378050Y0238318D01*
+X0378050Y0238020D02*
+X0371800Y0238020D01*
+X0371800Y0237721D02*
+X0378050Y0237721D01*
+X0378050Y0237423D02*
+X0371800Y0237423D01*
+X0371800Y0237124D02*
+X0378050Y0237124D01*
+X0378050Y0236826D02*
+X0371800Y0236826D01*
+X0371800Y0236527D02*
+X0378050Y0236527D01*
+X0378050Y0236229D02*
+X0371800Y0236229D01*
+X0371800Y0235930D02*
+X0378050Y0235930D01*
+X0378050Y0235632D02*
+X0371800Y0235632D01*
+X0371800Y0235333D02*
+X0378050Y0235333D01*
+X0378050Y0235035D02*
+X0371800Y0235035D01*
+X0371800Y0234736D02*
+X0378050Y0234736D01*
+X0378050Y0234438D02*
+X0371800Y0234438D01*
+X0371800Y0234139D02*
+X0378050Y0234139D01*
+X0378050Y0233841D02*
+X0371800Y0233841D01*
+X0371800Y0233542D02*
+X0378050Y0233542D01*
+X0378050Y0233244D02*
+X0371800Y0233244D01*
+X0371800Y0232945D02*
+X0378050Y0232945D01*
+X0378050Y0232647D02*
+X0371800Y0232647D01*
+X0371800Y0232348D02*
+X0378050Y0232348D01*
+X0378050Y0232050D02*
+X0371800Y0232050D01*
+X0371800Y0231751D02*
+X0378050Y0231751D01*
+X0378050Y0231453D02*
+X0371800Y0231453D01*
+X0371800Y0231154D02*
+X0378050Y0231154D01*
+X0378050Y0230855D02*
+X0371800Y0230855D01*
+X0371800Y0230557D02*
+X0378050Y0230557D01*
+X0378050Y0230258D02*
+X0371800Y0230258D01*
+X0371800Y0229960D02*
+X0378050Y0229960D01*
+X0378050Y0229661D02*
+X0371800Y0229661D01*
+X0371800Y0229363D02*
+X0378050Y0229363D01*
+X0378050Y0229064D02*
+X0371800Y0229064D01*
+X0371800Y0228766D02*
+X0378050Y0228766D01*
+X0378050Y0228467D02*
+X0371800Y0228467D01*
+X0371800Y0228169D02*
+X0378050Y0228169D01*
+X0378050Y0227870D02*
+X0371800Y0227870D01*
+X0371800Y0227572D02*
+X0378050Y0227572D01*
+X0378050Y0227273D02*
+X0371800Y0227273D01*
+X0371800Y0226975D02*
+X0378050Y0226975D01*
+X0378050Y0226676D02*
+X0371800Y0226676D01*
+X0371800Y0226378D02*
+X0378050Y0226378D01*
+X0378050Y0226079D02*
+X0371800Y0226079D01*
+X0371800Y0225781D02*
+X0378050Y0225781D01*
+X0378050Y0225482D02*
+X0371800Y0225482D01*
+X0371800Y0225184D02*
+X0378050Y0225184D01*
+X0378050Y0224885D02*
+X0371800Y0224885D01*
+X0371800Y0224587D02*
+X0378050Y0224587D01*
+X0378050Y0224288D02*
+X0371800Y0224288D01*
+X0371800Y0223990D02*
+X0378050Y0223990D01*
+X0378050Y0223691D02*
+X0371800Y0223691D01*
+X0371800Y0223393D02*
+X0378050Y0223393D01*
+X0378050Y0223094D02*
+X0371800Y0223094D01*
+X0371800Y0222796D02*
+X0378050Y0222796D01*
+X0378050Y0222497D02*
+X0371800Y0222497D01*
+X0371800Y0222199D02*
+X0378050Y0222199D01*
+X0378050Y0221900D02*
+X0371800Y0221900D01*
+X0371800Y0221602D02*
+X0378050Y0221602D01*
+X0378050Y0221303D02*
+X0371800Y0221303D01*
+X0371800Y0221005D02*
+X0378050Y0221005D01*
+X0378050Y0220706D02*
+X0371800Y0220706D01*
+X0371800Y0220408D02*
+X0378050Y0220408D01*
+X0378050Y0220109D02*
+X0371800Y0220109D01*
+X0371800Y0219811D02*
+X0378050Y0219811D01*
+X0378050Y0219512D02*
+X0371800Y0219512D01*
+X0371800Y0219214D02*
+X0378050Y0219214D01*
+X0378050Y0218915D02*
+X0371800Y0218915D01*
+X0371800Y0218617D02*
+X0378050Y0218617D01*
+X0378050Y0218318D02*
+X0371800Y0218318D01*
+X0371800Y0218020D02*
+X0378050Y0218020D01*
+X0378050Y0217721D02*
+X0371800Y0217721D01*
+X0371800Y0217422D02*
+X0378050Y0217422D01*
+X0378050Y0217124D02*
+X0371800Y0217124D01*
+X0371800Y0216825D02*
+X0378050Y0216825D01*
+X0378050Y0216527D02*
+X0371800Y0216527D01*
+X0371800Y0216228D02*
+X0378050Y0216228D01*
+X0378050Y0215930D02*
+X0371800Y0215930D01*
+X0371800Y0215631D02*
+X0378050Y0215631D01*
+X0378050Y0215333D02*
+X0371800Y0215333D01*
+X0371800Y0215034D02*
+X0378050Y0215034D01*
+X0378050Y0214736D02*
+X0371800Y0214736D01*
+X0371800Y0214437D02*
+X0378050Y0214437D01*
+X0378050Y0214139D02*
+X0371800Y0214139D01*
+X0371800Y0213840D02*
+X0378050Y0213840D01*
+X0378050Y0213542D02*
+X0371800Y0213542D01*
+X0371800Y0213243D02*
+X0378050Y0213243D01*
+X0378050Y0212945D02*
+X0371800Y0212945D01*
+X0371800Y0212646D02*
+X0378050Y0212646D01*
+X0378050Y0212348D02*
+X0371800Y0212348D01*
+X0371800Y0212049D02*
+X0378050Y0212049D01*
+X0378050Y0211751D02*
+X0371800Y0211751D01*
+X0371800Y0211452D02*
+X0378050Y0211452D01*
+X0378050Y0211154D02*
+X0371800Y0211154D01*
+X0371800Y0210855D02*
+X0378050Y0210855D01*
+X0378050Y0210557D02*
+X0371800Y0210557D01*
+X0371800Y0210258D02*
+X0378050Y0210258D01*
+X0378050Y0209960D02*
+X0371800Y0209960D01*
+X0371800Y0209661D02*
+X0378050Y0209661D01*
+X0378050Y0209363D02*
+X0371800Y0209363D01*
+X0371800Y0209064D02*
+X0378050Y0209064D01*
+X0378050Y0208766D02*
+X0371800Y0208766D01*
+X0371800Y0208467D02*
+X0378050Y0208467D01*
+X0378050Y0208169D02*
+X0371800Y0208169D01*
+X0371800Y0207870D02*
+X0378050Y0207870D01*
+X0378050Y0207572D02*
+X0371800Y0207572D01*
+X0371800Y0207273D02*
+X0378050Y0207273D01*
+X0378050Y0206975D02*
+X0371800Y0206975D01*
+X0371800Y0206676D02*
+X0378050Y0206676D01*
+X0378050Y0206378D02*
+X0371800Y0206378D01*
+X0371800Y0206079D02*
+X0378050Y0206079D01*
+X0378050Y0205781D02*
+X0371800Y0205781D01*
+X0371800Y0205482D02*
+X0378050Y0205482D01*
+X0378050Y0205184D02*
+X0371800Y0205184D01*
+X0371800Y0204885D02*
+X0378050Y0204885D01*
+X0378050Y0204586D02*
+X0371800Y0204586D01*
+X0371800Y0204288D02*
+X0378050Y0204288D01*
+X0378050Y0203989D02*
+X0371800Y0203989D01*
+X0371800Y0203691D02*
+X0378050Y0203691D01*
+X0378050Y0203392D02*
+X0371800Y0203392D01*
+X0371800Y0203094D02*
+X0378050Y0203094D01*
+X0378050Y0202795D02*
+X0371800Y0202795D01*
+X0371800Y0202497D02*
+X0378050Y0202497D01*
+X0378050Y0202198D02*
+X0371800Y0202198D01*
+X0371800Y0201900D02*
+X0378050Y0201900D01*
+X0378050Y0201601D02*
+X0371800Y0201601D01*
+X0371800Y0201303D02*
+X0378050Y0201303D01*
+X0378050Y0201004D02*
+X0371800Y0201004D01*
+X0371800Y0200706D02*
+X0378050Y0200706D01*
+X0378050Y0200407D02*
+X0371800Y0200407D01*
+X0371800Y0200109D02*
+X0378050Y0200109D01*
+X0378050Y0199810D02*
+X0371800Y0199810D01*
+X0371800Y0199512D02*
+X0378050Y0199512D01*
+X0378050Y0199213D02*
+X0371800Y0199213D01*
+X0371800Y0198915D02*
+X0378050Y0198915D01*
+X0378050Y0198616D02*
+X0371800Y0198616D01*
+X0371800Y0198318D02*
+X0378050Y0198318D01*
+X0378050Y0198019D02*
+X0371800Y0198019D01*
+X0371800Y0197721D02*
+X0378050Y0197721D01*
+X0378050Y0197422D02*
+X0371800Y0197422D01*
+X0371800Y0197124D02*
+X0378050Y0197124D01*
+X0378050Y0196825D02*
+X0371800Y0196825D01*
+X0371800Y0196527D02*
+X0378050Y0196527D01*
+X0378050Y0196228D02*
+X0371800Y0196228D01*
+X0371800Y0195930D02*
+X0378050Y0195930D01*
+X0378050Y0195631D02*
+X0371800Y0195631D01*
+X0371800Y0195333D02*
+X0378050Y0195333D01*
+X0378050Y0195034D02*
+X0371800Y0195034D01*
+X0371800Y0194736D02*
+X0378050Y0194736D01*
+X0378050Y0194437D02*
+X0371800Y0194437D01*
+X0371800Y0194139D02*
+X0378050Y0194139D01*
+X0378050Y0193840D02*
+X0371800Y0193840D01*
+X0371800Y0193542D02*
+X0378050Y0193542D01*
+X0378050Y0193243D02*
+X0371800Y0193243D01*
+X0371800Y0192945D02*
+X0378050Y0192945D01*
+X0378050Y0192646D02*
+X0371800Y0192646D01*
+X0371800Y0192348D02*
+X0378050Y0192348D01*
+X0378050Y0192049D02*
+X0371800Y0192049D01*
+X0371800Y0191751D02*
+X0378050Y0191751D01*
+X0378050Y0191452D02*
+X0371800Y0191452D01*
+X0371800Y0191153D02*
+X0378050Y0191153D01*
+X0378050Y0190855D02*
+X0371800Y0190855D01*
+X0371800Y0190556D02*
+X0378050Y0190556D01*
+X0378050Y0190258D02*
+X0371800Y0190258D01*
+X0371800Y0189959D02*
+X0378050Y0189959D01*
+X0378050Y0189661D02*
+X0371800Y0189661D01*
+X0371800Y0189362D02*
+X0378050Y0189362D01*
+X0378050Y0189064D02*
+X0371800Y0189064D01*
+X0371800Y0188765D02*
+X0378050Y0188765D01*
+X0378050Y0188467D02*
+X0371800Y0188467D01*
+X0371800Y0188168D02*
+X0378050Y0188168D01*
+X0378050Y0187870D02*
+X0371800Y0187870D01*
+X0371800Y0187571D02*
+X0378050Y0187571D01*
+X0378050Y0187273D02*
+X0371800Y0187273D01*
+X0371800Y0186974D02*
+X0378050Y0186974D01*
+X0378050Y0186676D02*
+X0371800Y0186676D01*
+X0371800Y0186377D02*
+X0378050Y0186377D01*
+X0378050Y0186079D02*
+X0371800Y0186079D01*
+X0371800Y0185780D02*
+X0378050Y0185780D01*
+X0378050Y0185482D02*
+X0371800Y0185482D01*
+X0371800Y0185183D02*
+X0378050Y0185183D01*
+X0378050Y0184885D02*
+X0371800Y0184885D01*
+X0371800Y0184586D02*
+X0378050Y0184586D01*
+X0378050Y0184288D02*
+X0371800Y0184288D01*
+X0371800Y0183989D02*
+X0378050Y0183989D01*
+X0378050Y0183691D02*
+X0371800Y0183691D01*
+X0371800Y0183392D02*
+X0378050Y0183392D01*
+X0378050Y0183094D02*
+X0371800Y0183094D01*
+X0371800Y0182795D02*
+X0378050Y0182795D01*
+X0378050Y0182497D02*
+X0371800Y0182497D01*
+X0371800Y0182198D02*
+X0378050Y0182198D01*
+X0378050Y0181900D02*
+X0371800Y0181900D01*
+X0371800Y0181601D02*
+X0378050Y0181601D01*
+X0378050Y0181303D02*
+X0371800Y0181303D01*
+X0371800Y0181004D02*
+X0378050Y0181004D01*
+X0378050Y0180706D02*
+X0371800Y0180706D01*
+X0371800Y0180407D02*
+X0378050Y0180407D01*
+X0378050Y0180109D02*
+X0371800Y0180109D01*
+X0371800Y0179810D02*
+X0378050Y0179810D01*
+X0378050Y0179512D02*
+X0371800Y0179512D01*
+X0371800Y0179213D02*
+X0378050Y0179213D01*
+X0378050Y0178915D02*
+X0371800Y0178915D01*
+X0371800Y0178616D02*
+X0378050Y0178616D01*
+X0378050Y0178317D02*
+X0371800Y0178317D01*
+X0371800Y0178019D02*
+X0378050Y0178019D01*
+X0378050Y0177720D02*
+X0371800Y0177720D01*
+X0371800Y0177422D02*
+X0378050Y0177422D01*
+X0378050Y0177123D02*
+X0371800Y0177123D01*
+X0371800Y0176825D02*
+X0378050Y0176825D01*
+X0378050Y0176526D02*
+X0371800Y0176526D01*
+X0371800Y0176228D02*
+X0378050Y0176228D01*
+X0378050Y0175929D02*
+X0371800Y0175929D01*
+X0371800Y0175631D02*
+X0378050Y0175631D01*
+X0378050Y0175332D02*
+X0371800Y0175332D01*
+X0371800Y0175034D02*
+X0378050Y0175034D01*
+X0378050Y0174735D02*
+X0371800Y0174735D01*
+X0371800Y0174437D02*
+X0378050Y0174437D01*
+X0378050Y0174138D02*
+X0371800Y0174138D01*
+X0371800Y0173840D02*
+X0378050Y0173840D01*
+X0378050Y0173541D02*
+X0371800Y0173541D01*
+X0371800Y0173243D02*
+X0378050Y0173243D01*
+X0378050Y0172944D02*
+X0371800Y0172944D01*
+X0371800Y0172646D02*
+X0378050Y0172646D01*
+X0378050Y0172347D02*
+X0371800Y0172347D01*
+X0371800Y0172049D02*
+X0378050Y0172049D01*
+X0378050Y0171750D02*
+X0371800Y0171750D01*
+X0371800Y0171452D02*
+X0378050Y0171452D01*
+X0378050Y0171153D02*
+X0371800Y0171153D01*
+X0371800Y0170855D02*
+X0378050Y0170855D01*
+X0378050Y0170556D02*
+X0371800Y0170556D01*
+X0371800Y0170258D02*
+X0378050Y0170258D01*
+X0378050Y0169959D02*
+X0371800Y0169959D01*
+X0371800Y0169661D02*
+X0378050Y0169661D01*
+X0378050Y0169362D02*
+X0371800Y0169362D01*
+X0371800Y0169064D02*
+X0378050Y0169064D01*
+X0378050Y0168765D02*
+X0371800Y0168765D01*
+X0371800Y0168467D02*
+X0378050Y0168467D01*
+X0378050Y0168168D02*
+X0371800Y0168168D01*
+X0371800Y0167870D02*
+X0378050Y0167870D01*
+X0378050Y0167571D02*
+X0371800Y0167571D01*
+X0371800Y0167273D02*
+X0378050Y0167273D01*
+X0378050Y0166974D02*
+X0371800Y0166974D01*
+X0371800Y0166676D02*
+X0378050Y0166676D01*
+X0378050Y0166377D02*
+X0371800Y0166377D01*
+X0371800Y0166079D02*
+X0378050Y0166079D01*
+X0378050Y0165780D02*
+X0371800Y0165780D01*
+X0371800Y0165482D02*
+X0378050Y0165482D01*
+X0378050Y0165183D02*
+X0371800Y0165183D01*
+X0371800Y0164884D02*
+X0378050Y0164884D01*
+X0378050Y0164586D02*
+X0371800Y0164586D01*
+X0371800Y0164287D02*
+X0378050Y0164287D01*
+X0378050Y0163989D02*
+X0371800Y0163989D01*
+X0371800Y0163690D02*
+X0378050Y0163690D01*
+X0378050Y0163392D02*
+X0371800Y0163392D01*
+X0371800Y0163093D02*
+X0378050Y0163093D01*
+X0378050Y0162795D02*
+X0371800Y0162795D01*
+X0371800Y0162496D02*
+X0378050Y0162496D01*
+X0378050Y0162198D02*
+X0371800Y0162198D01*
+X0371800Y0161899D02*
+X0378050Y0161899D01*
+X0378050Y0161601D02*
+X0371800Y0161601D01*
+X0371800Y0161302D02*
+X0378050Y0161302D01*
+X0378050Y0161004D02*
+X0371800Y0161004D01*
+X0371800Y0160705D02*
+X0378050Y0160705D01*
+X0378050Y0160407D02*
+X0371800Y0160407D01*
+X0371800Y0160108D02*
+X0378050Y0160108D01*
+X0378050Y0159810D02*
+X0371800Y0159810D01*
+X0371800Y0159511D02*
+X0378050Y0159511D01*
+X0378050Y0159213D02*
+X0371800Y0159213D01*
+X0371800Y0158914D02*
+X0378050Y0158914D01*
+X0378050Y0158616D02*
+X0371800Y0158616D01*
+X0371800Y0158317D02*
+X0378050Y0158317D01*
+X0378050Y0158019D02*
+X0371800Y0158019D01*
+X0371800Y0157720D02*
+X0378050Y0157720D01*
+X0378050Y0157422D02*
+X0371800Y0157422D01*
+X0371800Y0157123D02*
+X0378050Y0157123D01*
+X0378050Y0156825D02*
+X0371800Y0156825D01*
+X0371800Y0156526D02*
+X0378050Y0156526D01*
+X0378050Y0156228D02*
+X0371800Y0156228D01*
+X0371800Y0155929D02*
+X0378050Y0155929D01*
+X0378050Y0155631D02*
+X0371800Y0155631D01*
+X0371800Y0155332D02*
+X0378050Y0155332D01*
+X0378050Y0155034D02*
+X0371800Y0155034D01*
+X0371800Y0154735D02*
+X0378050Y0154735D01*
+X0378050Y0154437D02*
+X0371800Y0154437D01*
+X0371800Y0154138D02*
+X0378050Y0154138D01*
+X0378050Y0153840D02*
+X0371800Y0153840D01*
+X0371800Y0153541D02*
+X0378050Y0153541D01*
+X0378050Y0153243D02*
+X0371800Y0153243D01*
+X0371800Y0152944D02*
+X0378050Y0152944D01*
+X0378050Y0152646D02*
+X0371800Y0152646D01*
+X0371800Y0152347D02*
+X0378050Y0152347D01*
+X0378050Y0152048D02*
+X0371800Y0152048D01*
+X0371800Y0151750D02*
+X0378050Y0151750D01*
+X0378050Y0151451D02*
+X0371800Y0151451D01*
+X0371800Y0151153D02*
+X0378050Y0151153D01*
+X0378050Y0150854D02*
+X0371800Y0150854D01*
+X0371800Y0150556D02*
+X0378050Y0150556D01*
+X0378050Y0150257D02*
+X0371800Y0150257D01*
+X0371800Y0149959D02*
+X0378050Y0149959D01*
+X0378050Y0149660D02*
+X0371800Y0149660D01*
+X0371800Y0149362D02*
+X0378050Y0149362D01*
+X0378050Y0149063D02*
+X0371800Y0149063D01*
+X0371800Y0148765D02*
+X0378050Y0148765D01*
+X0378050Y0148466D02*
+X0371800Y0148466D01*
+X0371800Y0148168D02*
+X0378050Y0148168D01*
+X0378050Y0147869D02*
+X0371800Y0147869D01*
+X0371800Y0147571D02*
+X0378050Y0147571D01*
+X0378050Y0147272D02*
+X0371800Y0147272D01*
+X0371800Y0146974D02*
+X0378050Y0146974D01*
+X0378050Y0146675D02*
+X0371800Y0146675D01*
+X0371800Y0146377D02*
+X0378050Y0146377D01*
+X0378050Y0146078D02*
+X0371800Y0146078D01*
+X0371800Y0145780D02*
+X0378050Y0145780D01*
+X0378050Y0145481D02*
+X0371800Y0145481D01*
+X0371800Y0145183D02*
+X0378050Y0145183D01*
+X0378050Y0144884D02*
+X0371800Y0144884D01*
+X0371800Y0144586D02*
+X0378050Y0144586D01*
+X0378050Y0144287D02*
+X0371800Y0144287D01*
+X0371800Y0143989D02*
+X0378050Y0143989D01*
+X0378050Y0143690D02*
+X0371800Y0143690D01*
+X0371800Y0143392D02*
+X0378050Y0143392D01*
+X0378050Y0143093D02*
+X0371800Y0143093D01*
+X0371800Y0142795D02*
+X0378050Y0142795D01*
+X0378050Y0142496D02*
+X0371800Y0142496D01*
+X0371800Y0142198D02*
+X0378050Y0142198D01*
+X0378050Y0141899D02*
+X0371800Y0141899D01*
+X0371800Y0141601D02*
+X0378050Y0141601D01*
+X0378050Y0141302D02*
+X0371800Y0141302D01*
+X0371800Y0141004D02*
+X0378050Y0141004D01*
+X0378050Y0140705D02*
+X0371800Y0140705D01*
+X0371800Y0140407D02*
+X0378050Y0140407D01*
+X0378050Y0140108D02*
+X0371800Y0140108D01*
+X0371800Y0139810D02*
+X0378050Y0139810D01*
+X0378050Y0139511D02*
+X0371800Y0139511D01*
+X0371800Y0139213D02*
+X0378050Y0139213D01*
+X0378050Y0138914D02*
+X0371800Y0138914D01*
+X0371800Y0138615D02*
+X0378050Y0138615D01*
+X0378050Y0138317D02*
+X0371800Y0138317D01*
+X0371800Y0138018D02*
+X0378050Y0138018D01*
+X0378050Y0137720D02*
+X0371800Y0137720D01*
+X0371800Y0137421D02*
+X0378050Y0137421D01*
+X0378050Y0137123D02*
+X0371800Y0137123D01*
+X0371800Y0136824D02*
+X0378050Y0136824D01*
+X0378050Y0136526D02*
+X0371800Y0136526D01*
+X0371800Y0136227D02*
+X0378050Y0136227D01*
+X0378050Y0135929D02*
+X0371800Y0135929D01*
+X0371800Y0135630D02*
+X0378050Y0135630D01*
+X0378050Y0135332D02*
+X0371800Y0135332D01*
+X0371800Y0135033D02*
+X0378050Y0135033D01*
+X0378050Y0134735D02*
+X0371800Y0134735D01*
+X0371800Y0134436D02*
+X0378050Y0134436D01*
+X0378050Y0134138D02*
+X0371800Y0134138D01*
+X0371800Y0133839D02*
+X0378050Y0133839D01*
+X0378050Y0133541D02*
+X0371800Y0133541D01*
+X0371800Y0133242D02*
+X0378050Y0133242D01*
+X0378050Y0132944D02*
+X0371800Y0132944D01*
+X0371800Y0132645D02*
+X0378050Y0132645D01*
+X0378050Y0132347D02*
+X0371800Y0132347D01*
+X0371800Y0132048D02*
+X0378050Y0132048D01*
+X0378050Y0131750D02*
+X0371800Y0131750D01*
+X0371800Y0131451D02*
+X0378050Y0131451D01*
+X0378050Y0131153D02*
+X0371800Y0131153D01*
+X0371800Y0130854D02*
+X0378050Y0130854D01*
+X0378050Y0130556D02*
+X0371800Y0130556D01*
+X0371800Y0130257D02*
+X0378050Y0130257D01*
+X0378050Y0129959D02*
+X0371800Y0129959D01*
+X0371800Y0129660D02*
+X0378050Y0129660D01*
+X0378050Y0129362D02*
+X0371800Y0129362D01*
+X0371800Y0129063D02*
+X0378050Y0129063D01*
+X0378050Y0128765D02*
+X0371800Y0128765D01*
+X0371800Y0128466D02*
+X0378050Y0128466D01*
+X0378050Y0128168D02*
+X0371800Y0128168D01*
+X0371800Y0127869D02*
+X0378050Y0127869D01*
+X0378050Y0127571D02*
+X0371800Y0127571D01*
+X0371800Y0127272D02*
+X0378050Y0127272D01*
+X0378050Y0126974D02*
+X0371800Y0126974D01*
+X0371800Y0126675D02*
+X0378050Y0126675D01*
+X0378050Y0126377D02*
+X0371800Y0126377D01*
+X0371800Y0126078D02*
+X0378050Y0126078D01*
+X0378050Y0125780D02*
+X0371800Y0125780D01*
+X0371800Y0125481D02*
+X0378050Y0125481D01*
+X0378050Y0125182D02*
+X0371800Y0125182D01*
+X0371800Y0124884D02*
+X0378050Y0124884D01*
+X0378050Y0124585D02*
+X0371800Y0124585D01*
+X0371800Y0124287D02*
+X0378050Y0124287D01*
+X0378050Y0123988D02*
+X0371800Y0123988D01*
+X0371800Y0123690D02*
+X0378050Y0123690D01*
+X0378050Y0123391D02*
+X0371800Y0123391D01*
+X0371800Y0123093D02*
+X0378050Y0123093D01*
+X0378050Y0122794D02*
+X0371800Y0122794D01*
+X0371800Y0122496D02*
+X0378050Y0122496D01*
+X0378050Y0122197D02*
+X0371800Y0122197D01*
+X0371800Y0121899D02*
+X0378050Y0121899D01*
+X0378050Y0121600D02*
+X0371800Y0121600D01*
+X0371800Y0121302D02*
+X0378050Y0121302D01*
+X0378050Y0121003D02*
+X0371800Y0121003D01*
+X0371800Y0120705D02*
+X0378050Y0120705D01*
+X0378050Y0120406D02*
+X0371800Y0120406D01*
+X0371800Y0120108D02*
+X0378050Y0120108D01*
+X0378050Y0119809D02*
+X0371800Y0119809D01*
+X0371800Y0119511D02*
+X0378050Y0119511D01*
+X0378050Y0119212D02*
+X0371800Y0119212D01*
+X0371800Y0118914D02*
+X0378050Y0118914D01*
+X0378050Y0118615D02*
+X0371800Y0118615D01*
+X0371800Y0118317D02*
+X0378050Y0118317D01*
+X0378050Y0118018D02*
+X0371800Y0118018D01*
+X0371800Y0117720D02*
+X0378050Y0117720D01*
+X0378050Y0117421D02*
+X0371800Y0117421D01*
+X0371800Y0117123D02*
+X0378050Y0117123D01*
+X0378050Y0116824D02*
+X0371800Y0116824D01*
+X0371800Y0116526D02*
+X0378050Y0116526D01*
+X0378050Y0116227D02*
+X0371800Y0116227D01*
+X0371800Y0115929D02*
+X0378050Y0115929D01*
+X0378050Y0115630D02*
+X0371800Y0115630D01*
+X0371800Y0115332D02*
+X0378050Y0115332D01*
+X0378050Y0115033D02*
+X0371800Y0115033D01*
+X0371800Y0114735D02*
+X0378050Y0114735D01*
+X0378050Y0114436D02*
+X0371800Y0114436D01*
+X0371800Y0114138D02*
+X0378050Y0114138D01*
+X0378050Y0113839D02*
+X0371800Y0113839D01*
+X0371800Y0113541D02*
+X0378050Y0113541D01*
+X0378050Y0113242D02*
+X0371800Y0113242D01*
+X0371800Y0112944D02*
+X0378050Y0112944D01*
+X0378050Y0112645D02*
+X0371800Y0112645D01*
+X0371800Y0112346D02*
+X0378050Y0112346D01*
+X0378050Y0112048D02*
+X0371800Y0112048D01*
+X0371800Y0111749D02*
+X0378050Y0111749D01*
+X0378050Y0111451D02*
+X0371800Y0111451D01*
+X0371800Y0111152D02*
+X0378050Y0111152D01*
+X0378050Y0110854D02*
+X0371800Y0110854D01*
+X0371800Y0110555D02*
+X0378050Y0110555D01*
+X0378050Y0110257D02*
+X0371800Y0110257D01*
+X0371800Y0109958D02*
+X0378050Y0109958D01*
+X0378050Y0109660D02*
+X0371800Y0109660D01*
+X0371800Y0109361D02*
+X0378050Y0109361D01*
+X0378050Y0109063D02*
+X0371800Y0109063D01*
+X0371800Y0108764D02*
+X0378050Y0108764D01*
+X0378050Y0108466D02*
+X0371800Y0108466D01*
+X0371800Y0108167D02*
+X0378050Y0108167D01*
+X0378050Y0107869D02*
+X0371800Y0107869D01*
+X0371800Y0107570D02*
+X0378050Y0107570D01*
+X0378050Y0107272D02*
+X0371800Y0107272D01*
+X0371800Y0106973D02*
+X0378050Y0106973D01*
+X0378050Y0106675D02*
+X0371800Y0106675D01*
+X0371800Y0106376D02*
+X0378050Y0106376D01*
+X0378050Y0106078D02*
+X0371800Y0106078D01*
+X0371800Y0105779D02*
+X0378050Y0105779D01*
+X0378050Y0105481D02*
+X0371800Y0105481D01*
+X0371800Y0105182D02*
+X0378050Y0105182D01*
+X0378050Y0104884D02*
+X0371800Y0104884D01*
+X0371800Y0104585D02*
+X0378050Y0104585D01*
+X0378050Y0104287D02*
+X0371800Y0104287D01*
+X0371800Y0103988D02*
+X0378050Y0103988D01*
+X0378050Y0103690D02*
+X0371800Y0103690D01*
+X0371800Y0103391D02*
+X0378050Y0103391D01*
+X0378050Y0103093D02*
+X0371800Y0103093D01*
+X0371800Y0102794D02*
+X0378050Y0102794D01*
+X0378050Y0102496D02*
+X0371800Y0102496D01*
+X0371800Y0102197D02*
+X0378050Y0102197D01*
+X0378050Y0101899D02*
+X0371800Y0101899D01*
+X0371800Y0101600D02*
+X0378050Y0101600D01*
+X0378050Y0101302D02*
+X0371800Y0101302D01*
+X0371800Y0101003D02*
+X0378050Y0101003D01*
+X0378050Y0100705D02*
+X0371800Y0100705D01*
+X0371800Y0100406D02*
+X0378050Y0100406D01*
+X0378050Y0100108D02*
+X0371800Y0100108D01*
+X0371800Y0099809D02*
+X0378050Y0099809D01*
+X0378050Y0099511D02*
+X0371800Y0099511D01*
+X0371800Y0099212D02*
+X0378050Y0099212D01*
+X0378050Y0098913D02*
+X0371800Y0098913D01*
+X0371800Y0098615D02*
+X0378050Y0098615D01*
+X0378050Y0098316D02*
+X0371800Y0098316D01*
+X0371800Y0098018D02*
+X0378050Y0098018D01*
+X0378050Y0097719D02*
+X0371800Y0097719D01*
+X0371800Y0097421D02*
+X0378050Y0097421D01*
+X0378050Y0097122D02*
+X0371800Y0097122D01*
+X0371800Y0096824D02*
+X0378050Y0096824D01*
+X0378050Y0096525D02*
+X0371800Y0096525D01*
+X0371800Y0096227D02*
+X0378050Y0096227D01*
+X0378050Y0095928D02*
+X0371800Y0095928D01*
+X0371800Y0095630D02*
+X0378050Y0095630D01*
+X0378050Y0095331D02*
+X0371800Y0095331D01*
+X0371800Y0095033D02*
+X0378050Y0095033D01*
+X0378050Y0094734D02*
+X0371800Y0094734D01*
+X0371800Y0094436D02*
+X0378050Y0094436D01*
+X0378050Y0094137D02*
+X0371800Y0094137D01*
+X0371800Y0093839D02*
+X0378050Y0093839D01*
+X0378050Y0093540D02*
+X0371800Y0093540D01*
+X0371800Y0093242D02*
+X0378050Y0093242D01*
+X0378050Y0092943D02*
+X0371800Y0092943D01*
+X0371800Y0092645D02*
+X0378050Y0092645D01*
+X0378050Y0092346D02*
+X0371800Y0092346D01*
+X0371800Y0092048D02*
+X0378050Y0092048D01*
+X0378050Y0091749D02*
+X0371800Y0091749D01*
+X0371800Y0091451D02*
+X0378050Y0091451D01*
+X0378050Y0091152D02*
+X0371800Y0091152D01*
+X0371800Y0090854D02*
+X0378050Y0090854D01*
+X0378050Y0090555D02*
+X0371800Y0090555D01*
+X0371800Y0090257D02*
+X0378050Y0090257D01*
+X0378050Y0089958D02*
+X0371800Y0089958D01*
+X0371800Y0089660D02*
+X0378050Y0089660D01*
+X0378050Y0089361D02*
+X0371800Y0089361D01*
+X0371800Y0089063D02*
+X0378050Y0089063D01*
+X0378050Y0088764D02*
+X0371800Y0088764D01*
+X0371800Y0088466D02*
+X0378050Y0088466D01*
+X0378050Y0088167D02*
+X0371800Y0088167D01*
+X0371800Y0087869D02*
+X0378050Y0087869D01*
+X0378050Y0087570D02*
+X0371800Y0087570D01*
+X0371800Y0087272D02*
+X0378050Y0087272D01*
+X0378050Y0086973D02*
+X0371800Y0086973D01*
+X0371800Y0086675D02*
+X0378050Y0086675D01*
+X0378050Y0086376D02*
+X0371800Y0086376D01*
+X0371800Y0086077D02*
+X0378050Y0086077D01*
+X0378050Y0085779D02*
+X0371800Y0085779D01*
+X0371800Y0085480D02*
+X0378050Y0085480D01*
+X0378050Y0085182D02*
+X0371800Y0085182D01*
+X0371800Y0084883D02*
+X0378050Y0084883D01*
+X0378050Y0084585D02*
+X0371800Y0084585D01*
+X0371800Y0084286D02*
+X0378050Y0084286D01*
+X0378050Y0083988D02*
+X0371800Y0083988D01*
+X0371800Y0083689D02*
+X0378050Y0083689D01*
+X0378050Y0083391D02*
+X0371800Y0083391D01*
+X0371800Y0083092D02*
+X0378050Y0083092D01*
+X0378050Y0082794D02*
+X0371800Y0082794D01*
+X0371800Y0082495D02*
+X0378050Y0082495D01*
+X0378050Y0082197D02*
+X0371800Y0082197D01*
+X0371800Y0081898D02*
+X0378050Y0081898D01*
+X0378050Y0081600D02*
+X0371800Y0081600D01*
+X0371800Y0081301D02*
+X0378050Y0081301D01*
+X0378050Y0081003D02*
+X0371800Y0081003D01*
+X0371800Y0080704D02*
+X0378050Y0080704D01*
+X0378050Y0080406D02*
+X0371800Y0080406D01*
+X0371800Y0080107D02*
+X0378050Y0080107D01*
+X0378050Y0079809D02*
+X0371800Y0079809D01*
+X0371800Y0079510D02*
+X0378050Y0079510D01*
+X0378050Y0079212D02*
+X0371800Y0079212D01*
+X0371800Y0078913D02*
+X0378050Y0078913D01*
+X0378050Y0078615D02*
+X0371800Y0078615D01*
+X0371800Y0078316D02*
+X0378050Y0078316D01*
+X0378050Y0078018D02*
+X0371800Y0078018D01*
+X0371800Y0077719D02*
+X0378050Y0077719D01*
+X0378050Y0077421D02*
+X0371800Y0077421D01*
+X0371800Y0077122D02*
+X0378050Y0077122D01*
+X0378050Y0076824D02*
+X0371800Y0076824D01*
+X0371800Y0076525D02*
+X0378050Y0076525D01*
+X0378050Y0076227D02*
+X0371800Y0076227D01*
+X0371800Y0075928D02*
+X0378050Y0075928D01*
+X0378050Y0075630D02*
+X0371800Y0075630D01*
+X0371800Y0075331D02*
+X0378050Y0075331D01*
+X0378050Y0075033D02*
+X0371800Y0075033D01*
+X0371800Y0074734D02*
+X0378050Y0074734D01*
+X0378050Y0074436D02*
+X0371800Y0074436D01*
+X0371800Y0074137D02*
+X0378050Y0074137D01*
+X0378050Y0073839D02*
+X0371800Y0073839D01*
+X0371800Y0073540D02*
+X0378050Y0073540D01*
+X0378050Y0073242D02*
+X0371800Y0073242D01*
+X0371800Y0072943D02*
+X0378050Y0072943D01*
+X0378050Y0072644D02*
+X0371800Y0072644D01*
+X0371800Y0072346D02*
+X0378050Y0072346D01*
+X0378050Y0072047D02*
+X0371800Y0072047D01*
+X0371800Y0071749D02*
+X0378050Y0071749D01*
+X0378050Y0071450D02*
+X0371800Y0071450D01*
+X0371800Y0071152D02*
+X0378050Y0071152D01*
+X0378050Y0070853D02*
+X0371800Y0070853D01*
+X0371800Y0070555D02*
+X0378050Y0070555D01*
+X0378050Y0070256D02*
+X0371800Y0070256D01*
+X0371800Y0069958D02*
+X0378050Y0069958D01*
+X0378050Y0069659D02*
+X0371800Y0069659D01*
+X0371800Y0069361D02*
+X0378050Y0069361D01*
+X0378050Y0069062D02*
+X0371800Y0069062D01*
+X0371800Y0068764D02*
+X0378050Y0068764D01*
+X0378050Y0068465D02*
+X0371800Y0068465D01*
+X0371800Y0068167D02*
+X0378050Y0068167D01*
+X0378050Y0067868D02*
+X0371800Y0067868D01*
+X0371800Y0067570D02*
+X0378050Y0067570D01*
+X0378050Y0067271D02*
+X0371800Y0067271D01*
+X0371800Y0066973D02*
+X0378050Y0066973D01*
+X0378050Y0066674D02*
+X0371800Y0066674D01*
+X0371800Y0066376D02*
+X0378050Y0066376D01*
+X0378050Y0066077D02*
+X0371800Y0066077D01*
+X0371800Y0065779D02*
+X0378050Y0065779D01*
+X0378050Y0065480D02*
+X0371800Y0065480D01*
+X0371800Y0065182D02*
+X0378050Y0065182D01*
+X0378050Y0064883D02*
+X0371800Y0064883D01*
+X0371800Y0064585D02*
+X0378050Y0064585D01*
+X0378050Y0064286D02*
+X0371800Y0064286D01*
+X0371800Y0063988D02*
+X0378050Y0063988D01*
+X0378050Y0063689D02*
+X0371800Y0063689D01*
+X0371800Y0063391D02*
+X0378050Y0063391D01*
+X0378050Y0063092D02*
+X0371800Y0063092D01*
+X0371800Y0062794D02*
+X0378050Y0062794D01*
+X0378050Y0062495D02*
+X0371800Y0062495D01*
+X0371800Y0062197D02*
+X0378050Y0062197D01*
+X0378050Y0061898D02*
+X0371800Y0061898D01*
+X0371800Y0061600D02*
+X0378050Y0061600D01*
+X0378050Y0061301D02*
+X0371800Y0061301D01*
+X0371800Y0061003D02*
+X0378050Y0061003D01*
+X0378050Y0060704D02*
+X0371800Y0060704D01*
+X0371800Y0060406D02*
+X0378050Y0060406D01*
+X0378050Y0060107D02*
+X0371800Y0060107D01*
+X0371800Y0059809D02*
+X0378050Y0059809D01*
+X0378050Y0059510D02*
+X0371800Y0059510D01*
+X0371800Y0059211D02*
+X0378050Y0059211D01*
+X0378050Y0058913D02*
+X0371800Y0058913D01*
+X0371800Y0058614D02*
+X0378050Y0058614D01*
+X0378050Y0058316D02*
+X0371800Y0058316D01*
+X0371800Y0058017D02*
+X0378050Y0058017D01*
+X0378050Y0057719D02*
+X0371800Y0057719D01*
+X0371800Y0057420D02*
+X0378050Y0057420D01*
+X0378050Y0057122D02*
+X0371800Y0057122D01*
+X0371800Y0056823D02*
+X0378050Y0056823D01*
+X0378050Y0056525D02*
+X0371800Y0056525D01*
+X0371800Y0056226D02*
+X0378050Y0056226D01*
+X0378050Y0055928D02*
+X0371800Y0055928D01*
+X0371800Y0055629D02*
+X0378050Y0055629D01*
+X0378050Y0055331D02*
+X0371800Y0055331D01*
+X0371800Y0055032D02*
+X0378050Y0055032D01*
+X0378050Y0054734D02*
+X0371800Y0054734D01*
+X0371800Y0054435D02*
+X0378050Y0054435D01*
+X0378050Y0054137D02*
+X0371800Y0054137D01*
+X0371800Y0053838D02*
+X0378050Y0053838D01*
+X0378050Y0053540D02*
+X0371800Y0053540D01*
+X0371800Y0053241D02*
+X0378050Y0053241D01*
+X0378050Y0052943D02*
+X0371800Y0052943D01*
+X0371800Y0052644D02*
+X0378050Y0052644D01*
+X0378050Y0052346D02*
+X0371800Y0052346D01*
+X0371800Y0052047D02*
+X0378050Y0052047D01*
+X0378050Y0051749D02*
+X0371800Y0051749D01*
+X0371800Y0051450D02*
+X0378050Y0051450D01*
+X0378050Y0051152D02*
+X0371800Y0051152D01*
+X0371800Y0050853D02*
+X0378050Y0050853D01*
+X0378050Y0050555D02*
+X0371800Y0050555D01*
+X0371800Y0050256D02*
+X0378050Y0050256D01*
+X0378050Y0049958D02*
+X0371800Y0049958D01*
+X0371800Y0049659D02*
+X0378050Y0049659D01*
+X0378050Y0049361D02*
+X0371800Y0049361D01*
+X0371800Y0049062D02*
+X0378050Y0049062D01*
+X0378050Y0048764D02*
+X0371800Y0048764D01*
+X0371800Y0048465D02*
+X0378050Y0048465D01*
+X0378050Y0048167D02*
+X0371800Y0048167D01*
+X0371800Y0047868D02*
+X0378050Y0047868D01*
+X0378050Y0047570D02*
+X0371800Y0047570D01*
+X0371800Y0047271D02*
+X0378050Y0047271D01*
+X0378050Y0046973D02*
+X0371800Y0046973D01*
+X0371800Y0046674D02*
+X0378050Y0046674D01*
+X0378050Y0046375D02*
+X0371800Y0046375D01*
+X0371800Y0046077D02*
+X0378050Y0046077D01*
+X0378050Y0045778D02*
+X0371800Y0045778D01*
+X0371800Y0045480D02*
+X0378050Y0045480D01*
+X0378050Y0045181D02*
+X0371800Y0045181D01*
+X0371800Y0044883D02*
+X0378050Y0044883D01*
+X0378050Y0044584D02*
+X0371800Y0044584D01*
+X0371800Y0044286D02*
+X0378050Y0044286D01*
+X0378050Y0043987D02*
+X0371800Y0043987D01*
+X0371800Y0043689D02*
+X0378050Y0043689D01*
+X0378050Y0043390D02*
+X0371800Y0043390D01*
+X0371800Y0043092D02*
+X0378050Y0043092D01*
+X0378050Y0042793D02*
+X0371800Y0042793D01*
+X0371800Y0042495D02*
+X0378050Y0042495D01*
+X0378050Y0042196D02*
+X0371800Y0042196D01*
+X0371800Y0041898D02*
+X0378050Y0041898D01*
+X0378050Y0041599D02*
+X0371800Y0041599D01*
+X0371800Y0041301D02*
+X0378050Y0041301D01*
+X0378050Y0041002D02*
+X0371800Y0041002D01*
+X0371800Y0040704D02*
+X0378050Y0040704D01*
+X0378050Y0040405D02*
+X0371800Y0040405D01*
+X0371800Y0040107D02*
+X0378050Y0040107D01*
+X0378050Y0039808D02*
+X0371800Y0039808D01*
+X0371800Y0039510D02*
+X0378050Y0039510D01*
+X0378050Y0039211D02*
+X0371800Y0039211D01*
+X0371800Y0038913D02*
+X0378050Y0038913D01*
+X0378050Y0038614D02*
+X0371800Y0038614D01*
+X0371800Y0038316D02*
+X0378050Y0038316D01*
+X0378050Y0038017D02*
+X0371800Y0038017D01*
+X0371800Y0037719D02*
+X0378050Y0037719D01*
+X0378050Y0037420D02*
+X0371800Y0037420D01*
+X0371800Y0037122D02*
+X0378050Y0037122D01*
+X0378050Y0036823D02*
+X0371800Y0036823D01*
+X0371800Y0036525D02*
+X0378050Y0036525D01*
+X0378050Y0036226D02*
+X0371800Y0036226D01*
+X0371800Y0035928D02*
+X0378050Y0035928D01*
+X0378050Y0035629D02*
+X0371800Y0035629D01*
+X0371800Y0035331D02*
+X0378050Y0035331D01*
+X0378050Y0035032D02*
+X0371800Y0035032D01*
+X0371800Y0034734D02*
+X0378050Y0034734D01*
+X0378050Y0034435D02*
+X0371800Y0034435D01*
+X0371800Y0034137D02*
+X0378050Y0034137D01*
+X0378050Y0033838D02*
+X0371800Y0033838D01*
+X0371800Y0033540D02*
+X0378050Y0033540D01*
+X0378050Y0033241D02*
+X0371800Y0033241D01*
+X0371800Y0032942D02*
+X0378050Y0032942D01*
+X0378050Y0032644D02*
+X0371800Y0032644D01*
+X0371800Y0032345D02*
+X0378050Y0032345D01*
+X0378050Y0032047D02*
+X0371800Y0032047D01*
+X0371800Y0031748D02*
+X0378050Y0031748D01*
+X0378050Y0031450D02*
+X0371800Y0031450D01*
+X0371800Y0031151D02*
+X0378050Y0031151D01*
+X0378050Y0030853D02*
+X0371800Y0030853D01*
+X0371800Y0030554D02*
+X0378050Y0030554D01*
+X0378050Y0030256D02*
+X0371800Y0030256D01*
+X0371800Y0029957D02*
+X0378050Y0029957D01*
+X0378050Y0029659D02*
+X0371800Y0029659D01*
+X0371800Y0029360D02*
+X0378050Y0029360D01*
+X0378050Y0029062D02*
+X0371800Y0029062D01*
+X0371800Y0028763D02*
+X0378050Y0028763D01*
+X0378050Y0028465D02*
+X0371800Y0028465D01*
+X0371800Y0028166D02*
+X0378050Y0028166D01*
+X0378050Y0027868D02*
+X0371800Y0027868D01*
+X0371800Y0027569D02*
+X0378050Y0027569D01*
+X0378050Y0027271D02*
+X0371800Y0027271D01*
+X0371800Y0026972D02*
+X0378050Y0026972D01*
+X0378050Y0026674D02*
+X0371800Y0026674D01*
+X0371800Y0026375D02*
+X0378050Y0026375D01*
+X0378050Y0026077D02*
+X0371800Y0026077D01*
+X0371800Y0025778D02*
+X0378050Y0025778D01*
+X0378050Y0025480D02*
+X0371800Y0025480D01*
+X0371800Y0025181D02*
+X0378050Y0025181D01*
+X0378050Y0024883D02*
+X0371800Y0024883D01*
+X0371800Y0024584D02*
+X0378050Y0024584D01*
+X0378050Y0024286D02*
+X0371800Y0024286D01*
+X0371800Y0023987D02*
+X0378050Y0023987D01*
+X0378050Y0023689D02*
+X0371800Y0023689D01*
+X0371800Y0023390D02*
+X0378050Y0023390D01*
+X0378050Y0023092D02*
+X0371800Y0023092D01*
+X0371800Y0022793D02*
+X0378050Y0022793D01*
+X0378050Y0022495D02*
+X0371800Y0022495D01*
+X0371800Y0022196D02*
+X0378050Y0022196D01*
+X0378050Y0021898D02*
+X0371800Y0021898D01*
+X0371800Y0021599D02*
+X0378050Y0021599D01*
+X0378050Y0021301D02*
+X0371800Y0021301D01*
+X0371800Y0021002D02*
+X0378050Y0021002D01*
+X0378050Y0020704D02*
+X0371800Y0020704D01*
+X0371800Y0020405D02*
+X0378050Y0020405D01*
+X0378050Y0020106D02*
+X0371800Y0020106D01*
+X0371800Y0019808D02*
+X0378050Y0019808D01*
+X0378050Y0019509D02*
+X0371800Y0019509D01*
+X0371800Y0019211D02*
+X0378050Y0019211D01*
+X0378050Y0018912D02*
+X0371800Y0018912D01*
+X0371800Y0018614D02*
+X0378050Y0018614D01*
+X0378050Y0018315D02*
+X0371800Y0018315D01*
+X0371800Y0018017D02*
+X0378050Y0018017D01*
+X0378050Y0017718D02*
+X0371800Y0017718D01*
+X0371800Y0017420D02*
+X0378050Y0017420D01*
+X0378050Y0017121D02*
+X0371800Y0017121D01*
+X0371800Y0016823D02*
+X0378050Y0016823D01*
+X0378050Y0016524D02*
+X0371800Y0016524D01*
+X0371800Y0016226D02*
+X0378050Y0016226D01*
+X0378050Y0015927D02*
+X0371800Y0015927D01*
+X0371800Y0015629D02*
+X0378050Y0015629D01*
+X0378050Y0015330D02*
+X0371800Y0015330D01*
+X0371800Y0015032D02*
+X0378050Y0015032D01*
+X0378050Y0014733D02*
+X0371800Y0014733D01*
+X0371800Y0014435D02*
+X0378050Y0014435D01*
+X0378050Y0014136D02*
+X0371800Y0014136D01*
+X0371800Y0013838D02*
+X0378050Y0013838D01*
+X0378050Y0013539D02*
+X0371800Y0013539D01*
+X0371800Y0013241D02*
+X0378050Y0013241D01*
+X0378050Y0012942D02*
+X0371800Y0012942D01*
+X0371800Y0012644D02*
+X0378050Y0012644D01*
+X0378050Y0012345D02*
+X0371800Y0012345D01*
+X0371800Y0012047D02*
+X0378050Y0012047D01*
+D11*
+X0270550Y0049547D02*
+X0265007Y0049547D01*
+X0265007Y0059547D02*
+X0270550Y0059547D01*
+X0270550Y0069547D02*
+X0265007Y0069547D01*
+X0265007Y0079547D02*
+X0270550Y0079547D01*
+X0270550Y0089547D02*
+X0265007Y0089547D01*
+X0265007Y0099547D02*
+X0270550Y0099547D01*
+X0270550Y0109547D02*
+X0265007Y0109547D01*
+X0265007Y0119547D02*
+X0270550Y0119547D01*
+X0270550Y0129547D02*
+X0265007Y0129547D01*
+X0265007Y0139547D02*
+X0270550Y0139547D01*
+X0270550Y0149547D02*
+X0265007Y0149547D01*
+X0265007Y0159547D02*
+X0270550Y0159547D01*
+X0270550Y0169547D02*
+X0265007Y0169547D01*
+X0265007Y0179547D02*
+X0270550Y0179547D01*
+X0270550Y0189547D02*
+X0265007Y0189547D01*
+X0230822Y0219547D02*
+X0225278Y0219547D01*
+X0216093Y0189547D02*
+X0210550Y0189547D01*
+X0210550Y0179547D02*
+X0216093Y0179547D01*
+X0216093Y0169547D02*
+X0210550Y0169547D01*
+X0210550Y0159547D02*
+X0216093Y0159547D01*
+X0216093Y0149547D02*
+X0210550Y0149547D01*
+X0210550Y0139547D02*
+X0216093Y0139547D01*
+X0216093Y0129547D02*
+X0210550Y0129547D01*
+X0210550Y0119547D02*
+X0216093Y0119547D01*
+X0216093Y0109547D02*
+X0210550Y0109547D01*
+X0210550Y0099547D02*
+X0216093Y0099547D01*
+X0216093Y0089547D02*
+X0210550Y0089547D01*
+X0210550Y0079547D02*
+X0216093Y0079547D01*
+X0216093Y0069547D02*
+X0210550Y0069547D01*
+X0210550Y0059547D02*
+X0216093Y0059547D01*
+X0216093Y0049547D02*
+X0210550Y0049547D01*
+X0189572Y0047047D02*
+X0184028Y0047047D01*
+X0184028Y0057047D02*
+X0189572Y0057047D01*
+X0189572Y0067047D02*
+X0184028Y0067047D01*
+X0184028Y0077047D02*
+X0189572Y0077047D01*
+X0189572Y0087047D02*
+X0184028Y0087047D01*
+X0184028Y0097047D02*
+X0189572Y0097047D01*
+X0109572Y0097047D02*
+X0104028Y0097047D01*
+X0104028Y0087047D02*
+X0109572Y0087047D01*
+X0109572Y0077047D02*
+X0104028Y0077047D01*
+X0104028Y0067047D02*
+X0109572Y0067047D01*
+X0109572Y0057047D02*
+X0104028Y0057047D01*
+X0104028Y0047047D02*
+X0109572Y0047047D01*
+D12*
+X0087765Y0055275D02*
+X0081828Y0055275D01*
+X0076800Y0025015D02*
+X0076800Y0019078D01*
+X0066800Y0019078D02*
+X0066800Y0025015D01*
+X0056800Y0025015D02*
+X0056800Y0019078D01*
+X0026772Y0055275D02*
+X0020835Y0055275D01*
+X0020835Y0210787D02*
+X0026772Y0210787D01*
+X0081828Y0210787D02*
+X0087765Y0210787D01*
+X0091800Y0266578D02*
+X0091800Y0272515D01*
+X0101800Y0272515D02*
+X0101800Y0266578D01*
+X0081800Y0266578D02*
+X0081800Y0272515D01*
+X0343089Y0183027D02*
+X0343089Y0177090D01*
+X0343089Y0169247D02*
+X0343089Y0163310D01*
+D13*
+X0345550Y0262047D03*
+X0170550Y0139547D03*
+X0031800Y0029547D03*
+X0031800Y0262047D03*
+X0345550Y0029547D03*
+D14*
+X0275550Y0255797D03*
+D15*
+X0265511Y0265836D03*
+X0285589Y0265836D03*
+X0285589Y0245758D03*
+X0265511Y0245758D03*
+D16*
+X0199290Y0179547D03*
+X0191810Y0179547D03*
+X0126790Y0147047D03*
+X0119310Y0147047D03*
+X0079290Y0198297D03*
+X0071810Y0198297D03*
+X0126810Y0268297D03*
+X0134290Y0268297D03*
+X0315560Y0061047D03*
+X0323040Y0061047D03*
+X0303040Y0057047D03*
+X0295560Y0057047D03*
+X0315560Y0026047D03*
+X0323040Y0026047D03*
+D17*
+X0286300Y0036307D03*
+X0286300Y0043787D03*
+X0249300Y0035787D03*
+X0249300Y0028307D03*
+X0354300Y0064557D03*
+X0354300Y0072037D03*
+X0255550Y0150807D03*
+X0255550Y0158287D03*
+X0241800Y0158287D03*
+X0241800Y0150807D03*
+X0226800Y0149537D03*
+X0226800Y0142057D03*
+X0253050Y0175807D03*
+X0253050Y0183287D03*
+X0170550Y0239557D03*
+X0170550Y0247037D03*
+X0065550Y0243307D03*
+X0065550Y0250787D03*
+D18*
+X0114300Y0257391D03*
+X0114300Y0269202D03*
+X0361800Y0211702D03*
+X0361800Y0199891D03*
+X0341800Y0069202D03*
+X0341800Y0057391D03*
+X0120550Y0057952D03*
+X0120550Y0046141D03*
+X0090550Y0035452D03*
+X0090550Y0023641D03*
+D19*
+X0067706Y0037047D03*
+X0055894Y0037047D03*
+X0054644Y0078297D03*
+X0066456Y0078297D03*
+X0127144Y0164547D03*
+X0138956Y0164547D03*
+X0092706Y0227047D03*
+X0080894Y0227047D03*
+X0084644Y0254547D03*
+X0096456Y0254547D03*
+X0225894Y0179547D03*
+X0237706Y0179547D03*
+D20*
+X0072050Y0227047D02*
+X0063050Y0227047D01*
+X0045550Y0227047D02*
+X0036550Y0227047D01*
+D21*
+X0054812Y0053297D03*
+D22*
+X0042538Y0053297D03*
+D23*
+X0106800Y0020649D03*
+D24*
+X0106800Y0034694D03*
+D25*
+X0148050Y0247204D03*
+X0148050Y0266889D03*
+D26*
+X0131337Y0240797D03*
+X0104763Y0240797D03*
+D27*
+X0266219Y0033287D03*
+X0266219Y0025807D03*
+X0274881Y0029547D03*
+D28*
+X0294300Y0035547D03*
+X0294300Y0044547D03*
+X0314300Y0044547D03*
+X0314300Y0035547D03*
+D29*
+X0304300Y0035547D03*
+X0304300Y0044547D03*
+X0324300Y0044547D03*
+X0324300Y0035547D03*
+D30*
+X0147650Y0175797D03*
+X0147650Y0180797D03*
+X0147650Y0185797D03*
+X0147650Y0190797D03*
+X0123450Y0190797D03*
+X0123450Y0185797D03*
+X0123450Y0180797D03*
+X0123450Y0175797D03*
+D31*
+X0196800Y0243297D03*
+D32*
+X0196800Y0253297D03*
+X0206800Y0253297D03*
+X0216800Y0253297D03*
+X0226800Y0253297D03*
+X0236800Y0253297D03*
+X0236800Y0243297D03*
+X0226800Y0243297D03*
+X0216800Y0243297D03*
+X0206800Y0243297D03*
+D33*
+X0102272Y0108297D03*
+X0086328Y0108297D03*
+D34*
+X0108050Y0124547D03*
+X0130550Y0125797D03*
+X0160550Y0173297D03*
+X0170550Y0173297D03*
+X0180550Y0173297D03*
+X0180550Y0186058D03*
+X0170550Y0189547D03*
+X0160550Y0197047D03*
+X0196800Y0198297D03*
+X0231800Y0204547D03*
+X0251800Y0204547D03*
+X0269300Y0212047D03*
+X0266800Y0223297D03*
+X0266800Y0233297D03*
+X0243050Y0232047D03*
+X0183050Y0257047D03*
+X0244300Y0179547D03*
+X0234300Y0153297D03*
+X0249300Y0147047D03*
+X0200550Y0112047D03*
+X0196800Y0164547D03*
+X0280550Y0077047D03*
+X0290550Y0062047D03*
+X0285550Y0054547D03*
+X0258050Y0033297D03*
+X0333050Y0059547D03*
+X0365550Y0067047D03*
+X0370550Y0094547D03*
+X0364300Y0019547D03*
+X0369300Y0238297D03*
+X0369300Y0272047D03*
+X0320550Y0240797D03*
+X0303050Y0254547D03*
+X0318050Y0264547D03*
+X0055550Y0164547D03*
+X0010550Y0173297D03*
+X0010550Y0099547D03*
+D35*
+X0053050Y0098297D03*
+X0018050Y0138297D03*
+X0119300Y0165797D03*
+X0131800Y0199547D03*
+X0101800Y0220797D03*
+X0133050Y0255797D03*
+X0146800Y0234547D03*
+X0166800Y0117047D03*
+X0120550Y0035797D03*
+X0186800Y0020797D03*
+X0239300Y0020797D03*
+X0364300Y0222047D03*
+X0364300Y0229547D03*
+M02*
diff --git a/NPR70_modem_v05_PCB/NPR70_v05b_bot.PNG b/NPR70_modem_v05_PCB/NPR70_v05b_bot.PNG
new file mode 100755
index 0000000..5a940f3
Binary files /dev/null and b/NPR70_modem_v05_PCB/NPR70_v05b_bot.PNG differ
diff --git a/NPR70_modem_v05_PCB/NPR70_v05b_top.PNG b/NPR70_modem_v05_PCB/NPR70_v05b_top.PNG
new file mode 100755
index 0000000..cdcd9fb
Binary files /dev/null and b/NPR70_modem_v05_PCB/NPR70_v05b_top.PNG differ
diff --git a/NPR70_modem_v05_PCB/NPR_advanced_guide_v2.14.pdf b/NPR70_modem_v05_PCB/NPR_advanced_guide_v2.14.pdf
new file mode 100755
index 0000000..7f10ce7
Binary files /dev/null and b/NPR70_modem_v05_PCB/NPR_advanced_guide_v2.14.pdf differ
diff --git a/NPR70_modem_v05_PCB/PickAndPlace_NPR70_v05_2021-09-17.csv b/NPR70_modem_v05_PCB/PickAndPlace_NPR70_v05_2021-09-17.csv
new file mode 100755
index 0000000..79ad63b
Binary files /dev/null and b/NPR70_modem_v05_PCB/PickAndPlace_NPR70_v05_2021-09-17.csv differ
diff --git a/NPR70_modem_v05_PCB/TAPR_Open_Hardware_License_v1.0.pdf b/NPR70_modem_v05_PCB/TAPR_Open_Hardware_License_v1.0.pdf
new file mode 100755
index 0000000..01fceb2
Binary files /dev/null and b/NPR70_modem_v05_PCB/TAPR_Open_Hardware_License_v1.0.pdf differ
diff --git a/NPR70_modem_v05_PCB/eagle/NPR70_v05.brd b/NPR70_modem_v05_PCB/eagle/NPR70_v05.brd
new file mode 100755
index 0000000..04c7f69
--- /dev/null
+++ b/NPR70_modem_v05_PCB/eagle/NPR70_v05.brd
@@ -0,0 +1,3371 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="8.5.1">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="12.5" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="5" altunitdist="mil" altunit="mil"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/>
+<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="9" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="24" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="yes" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="yes" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="yes"/>
+<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="yes"/>
+<layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/>
+<layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/>
+<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
+<layer number="57" name="tCAD" color="7" fill="1" visible="no" active="no"/>
+<layer number="59" name="tCarbon" color="7" fill="1" visible="no" active="no"/>
+<layer number="60" name="bCarbon" color="7" fill="1" visible="no" active="no"/>
+<layer number="88" name="SimResults" color="9" fill="1" visible="no" active="no"/>
+<layer number="89" name="SimProbes" color="9" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="no" active="no"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
+<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+<layer number="99" name="SpiceOrder" color="5" fill="1" visible="no" active="no"/>
+<layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/>
+<layer number="101" name="Patch_Top" color="12" fill="4" visible="no" active="yes"/>
+<layer number="102" name="Vscore" color="7" fill="1" visible="no" active="yes"/>
+<layer number="103" name="tMap" color="7" fill="1" visible="no" active="yes"/>
+<layer number="104" name="Name" color="16" fill="1" visible="no" active="yes"/>
+<layer number="105" name="tPlate" color="7" fill="1" visible="no" active="yes"/>
+<layer number="106" name="bPlate" color="7" fill="1" visible="no" active="yes"/>
+<layer number="107" name="Crop" color="7" fill="1" visible="no" active="yes"/>
+<layer number="108" name="tplace-old" color="10" fill="1" visible="no" active="yes"/>
+<layer number="109" name="ref-old" color="11" fill="1" visible="no" active="yes"/>
+<layer number="110" name="fp0" color="7" fill="1" visible="no" active="yes"/>
+<layer number="111" name="LPC17xx" color="7" fill="1" visible="no" active="yes"/>
+<layer number="112" name="tSilk" color="7" fill="1" visible="no" active="yes"/>
+<layer number="113" name="IDFDebug" color="7" fill="1" visible="no" active="yes"/>
+<layer number="114" name="Badge_Outline" color="11" fill="1" visible="no" active="no"/>
+<layer number="115" name="ReferenceISLANDS" color="7" fill="1" visible="no" active="yes"/>
+<layer number="116" name="Patch_BOT" color="9" fill="4" visible="no" active="yes"/>
+<layer number="117" name="BACKMAAT1" color="7" fill="1" visible="no" active="no"/>
+<layer number="118" name="Rect_Pads" color="7" fill="1" visible="no" active="yes"/>
+<layer number="119" name="KAP_TEKEN" color="7" fill="1" visible="no" active="no"/>
+<layer number="120" name="KAP_MAAT1" color="7" fill="1" visible="no" active="no"/>
+<layer number="121" name="_tsilk" color="7" fill="1" visible="no" active="yes"/>
+<layer number="122" name="_bsilk" color="7" fill="1" visible="no" active="yes"/>
+<layer number="123" name="tTestmark" color="7" fill="1" visible="no" active="yes"/>
+<layer number="124" name="bTestmark" color="7" fill="1" visible="no" active="yes"/>
+<layer number="125" name="_tNames" color="7" fill="1" visible="no" active="yes"/>
+<layer number="126" name="_bNames" color="7" fill="1" visible="no" active="yes"/>
+<layer number="127" name="_tValues" color="7" fill="1" visible="no" active="yes"/>
+<layer number="128" name="_bValues" color="7" fill="1" visible="no" active="yes"/>
+<layer number="129" name="Mask" color="7" fill="1" visible="no" active="yes"/>
+<layer number="130" name="SMDSTROOK" color="7" fill="1" visible="no" active="no"/>
+<layer number="131" name="tAdjust" color="7" fill="1" visible="no" active="yes"/>
+<layer number="132" name="bAdjust" color="7" fill="1" visible="no" active="yes"/>
+<layer number="133" name="bottom_silk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="144" name="Drill_legend" color="7" fill="1" visible="no" active="yes"/>
+<layer number="150" name="Notes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="151" name="HeatSink" color="7" fill="1" visible="no" active="yes"/>
+<layer number="152" name="_bDocu" color="7" fill="1" visible="no" active="yes"/>
+<layer number="153" name="FabDoc1" color="7" fill="1" visible="no" active="yes"/>
+<layer number="154" name="FabDoc2" color="7" fill="1" visible="no" active="yes"/>
+<layer number="155" name="FabDoc3" color="7" fill="1" visible="no" active="yes"/>
+<layer number="199" name="Contour" color="7" fill="1" visible="no" active="yes"/>
+<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="yes"/>
+<layer number="201" name="201bmp" color="2" fill="10" visible="no" active="yes"/>
+<layer number="202" name="202bmp" color="3" fill="10" visible="no" active="yes"/>
+<layer number="203" name="203bmp" color="4" fill="10" visible="no" active="yes"/>
+<layer number="204" name="204bmp" color="5" fill="10" visible="no" active="yes"/>
+<layer number="205" name="205bmp" color="6" fill="10" visible="no" active="yes"/>
+<layer number="206" name="206bmp" color="7" fill="10" visible="no" active="yes"/>
+<layer number="207" name="207bmp" color="8" fill="10" visible="no" active="yes"/>
+<layer number="208" name="208bmp" color="9" fill="10" visible="no" active="yes"/>
+<layer number="209" name="209bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="210" name="210bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="211" name="211bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="212" name="212bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="213" name="213bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="214" name="214bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="215" name="215bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="216" name="216bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="217" name="217bmp" color="18" fill="1" visible="no" active="no"/>
+<layer number="218" name="218bmp" color="19" fill="1" visible="no" active="no"/>
+<layer number="219" name="219bmp" color="20" fill="1" visible="no" active="no"/>
+<layer number="220" name="220bmp" color="21" fill="1" visible="no" active="no"/>
+<layer number="221" name="221bmp" color="22" fill="1" visible="no" active="no"/>
+<layer number="222" name="222bmp" color="23" fill="1" visible="no" active="no"/>
+<layer number="223" name="223bmp" color="24" fill="1" visible="no" active="no"/>
+<layer number="224" name="224bmp" color="25" fill="1" visible="no" active="no"/>
+<layer number="225" name="225bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="226" name="226bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="227" name="227bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="228" name="228bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="229" name="229bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="230" name="230bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="231" name="231bmp" color="7" fill="1" visible="no" active="yes"/>
+<layer number="232" name="Eagle3D_PG2" color="7" fill="1" visible="no" active="no"/>
+<layer number="233" name="Eagle3D_PG3" color="7" fill="1" visible="no" active="no"/>
+<layer number="248" name="Housing" color="7" fill="1" visible="no" active="yes"/>
+<layer number="249" name="Edge" color="7" fill="1" visible="no" active="yes"/>
+<layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/>
+<layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/>
+<layer number="254" name="cooling" color="7" fill="1" visible="no" active="yes"/>
+<layer number="255" name="routoute" color="7" fill="1" visible="no" active="yes"/>
+</layers>
+<board>
+<plain>
+<wire x1="0" y1="0" x2="95.555" y2="0" width="0" layer="20"/>
+<wire x1="95.555" y1="0" x2="95.555" y2="67.935" width="0" layer="20"/>
+<wire x1="95.555" y1="67.935" x2="0" y2="67.935" width="0" layer="20"/>
+<wire x1="0" y1="67.935" x2="0" y2="0" width="0" layer="20"/>
+<polygon width="0.2032" layer="41">
+<vertex x="77.7875" y="21.9075"/>
+<vertex x="77.7875" y="29.21"/>
+<vertex x="74.93" y="33.3375"/>
+<vertex x="74.93" y="45.72"/>
+<vertex x="75.8825" y="46.6725"/>
+<vertex x="75.8825" y="54.2925"/>
+<vertex x="86.995" y="54.2925"/>
+<vertex x="86.995" y="45.4025"/>
+<vertex x="85.4075" y="44.1325"/>
+<vertex x="85.4075" y="37.7825"/>
+<vertex x="86.995" y="36.5125"/>
+<vertex x="86.995" y="21.9075"/>
+</polygon>
+<text x="49.53" y="54.9275" size="1.9304" layer="25" rot="R180">NPR70 modem v05
+designed by F4HDK</text>
+<polygon width="0.0762" layer="29">
+<vertex x="93.98" y="67.945"/>
+<vertex x="95.5675" y="67.945"/>
+<vertex x="95.5675" y="0"/>
+<vertex x="93.98" y="0"/>
+</polygon>
+<polygon width="0.0762" layer="30">
+<vertex x="95.5675" y="0"/>
+<vertex x="93.98" y="0"/>
+<vertex x="93.98" y="67.945"/>
+<vertex x="95.5675" y="67.945"/>
+</polygon>
+<polygon width="0.0762" layer="30">
+<vertex x="0" y="0"/>
+<vertex x="1.5875" y="0"/>
+<vertex x="1.5875" y="67.945"/>
+<vertex x="0" y="67.945"/>
+</polygon>
+<polygon width="0.0762" layer="29">
+<vertex x="0" y="0"/>
+<vertex x="1.5875" y="0"/>
+<vertex x="1.5875" y="67.945"/>
+<vertex x="0" y="67.945"/>
+</polygon>
+<text x="15.875" y="53.0225" size="1.778" layer="26" rot="MR180">+</text>
+<text x="8.89" y="53.0225" size="1.778" layer="26" rot="MR180">-</text>
+<text x="15.875" y="56.1975" size="1.778" layer="25">+</text>
+<text x="9.2075" y="56.1975" size="1.778" layer="25">-</text>
+</plain>
+<libraries>
+<library name="NPR_70">
+<packages>
+<package name="RF4463F30">
+<smd name="8" x="-19" y="4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="7" x="-19" y="0" dx="2.54" dy="1.27" layer="1"/>
+<smd name="6" x="-19" y="-4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="5" x="-19" y="-8" dx="2.54" dy="1.27" layer="1"/>
+<smd name="4" x="-19" y="-12" dx="2.54" dy="1.27" layer="1"/>
+<smd name="3" x="-19" y="-16" dx="2.54" dy="1.27" layer="1"/>
+<smd name="2" x="-19" y="-20" dx="2.54" dy="1.27" layer="1"/>
+<smd name="1" x="-19" y="-24" dx="2.54" dy="1.27" layer="1"/>
+<smd name="16" x="1" y="-24" dx="2.54" dy="1.27" layer="1"/>
+<smd name="15" x="1" y="-20" dx="2.54" dy="1.27" layer="1"/>
+<smd name="14" x="1" y="-16" dx="2.54" dy="1.27" layer="1"/>
+<smd name="13" x="1" y="-12" dx="2.54" dy="1.27" layer="1"/>
+<smd name="12" x="1" y="-8" dx="2.54" dy="1.27" layer="1"/>
+<smd name="11" x="1" y="-4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="10" x="1" y="0" dx="2.54" dy="1.27" layer="1"/>
+<smd name="9" x="1" y="4" dx="2.54" dy="1.27" layer="1"/>
+<text x="-7.65" y="-17.86" size="1.778" layer="25" rot="R90">RF4463F30</text>
+<circle x="-16" y="-26" radius="1" width="0.127" layer="21"/>
+<smd name="SHLD_1" x="-6" y="9" dx="2.54" dy="2.54" layer="1"/>
+<smd name="SHLD_2" x="-10.5" y="-29" dx="2.54" dy="2.54" layer="1"/>
+<wire x1="-19" y1="9" x2="-9" y2="9" width="0.1524" layer="21"/>
+<wire x1="-3" y1="9" x2="1" y2="9" width="0.1524" layer="21"/>
+<wire x1="-19" y1="6" x2="-19" y2="9" width="0.1524" layer="21"/>
+<wire x1="-19" y1="2.5" x2="-19" y2="1.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-1.5" x2="-19" y2="-2.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-5.5" x2="-19" y2="-6.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-9.5" x2="-19" y2="-10.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-13.5" x2="-19" y2="-14.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-17.5" x2="-19" y2="-18.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-21.5" x2="-19" y2="-22.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-26" x2="-19" y2="-29" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-29" x2="-13" y2="-29" width="0.1524" layer="21"/>
+<wire x1="-8" y1="-29" x2="1" y2="-29" width="0.1524" layer="21"/>
+<wire x1="1" y1="-29" x2="1" y2="-26" width="0.1524" layer="21"/>
+<wire x1="1" y1="-22.5" x2="1" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-18.5" x2="1" y2="-17.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-14.5" x2="1" y2="-13.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-10.5" x2="1" y2="-9.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-6.5" x2="1" y2="-5.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-2.5" x2="1" y2="-1.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="1.5" x2="1" y2="2.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="6" x2="1" y2="9" width="0.1524" layer="21"/>
+<pad name="SHLD_4" x="-14.25" y="-15.5" drill="1" shape="long" rot="R90" thermals="no"/>
+<pad name="SHLD_3" x="-14.25" y="-12" drill="1" shape="long" rot="R90" thermals="no"/>
+</package>
+<package name="STM_NUCLEO32">
+<pad name="1" x="-7.62" y="17.78" drill="0.9" shape="offset"/>
+<pad name="2" x="-7.62" y="15.24" drill="0.9" shape="offset"/>
+<pad name="3" x="-7.62" y="12.7" drill="0.9" shape="offset"/>
+<pad name="4" x="-7.62" y="10.16" drill="0.9" shape="offset"/>
+<pad name="5" x="-7.62" y="7.62" drill="0.9" shape="offset"/>
+<pad name="6" x="-7.62" y="5.08" drill="0.9" shape="offset"/>
+<pad name="7" x="-7.62" y="2.54" drill="0.9" shape="offset"/>
+<pad name="8" x="-7.62" y="0" drill="0.9" shape="offset"/>
+<pad name="9" x="-7.62" y="-2.54" drill="0.9" shape="offset"/>
+<pad name="10" x="-7.62" y="-5.08" drill="0.9" shape="offset"/>
+<pad name="11" x="-7.62" y="-7.62" drill="0.9" shape="offset"/>
+<pad name="12" x="-7.62" y="-10.16" drill="0.9" shape="offset"/>
+<pad name="13" x="-7.62" y="-12.7" drill="0.9" shape="offset"/>
+<pad name="18" x="7.62" y="-12.7" drill="0.9" shape="offset" rot="R180"/>
+<pad name="19" x="7.62" y="-10.16" drill="0.9" shape="offset" rot="R180"/>
+<pad name="20" x="7.62" y="-7.62" drill="0.9" shape="offset" rot="R180"/>
+<pad name="21" x="7.62" y="-5.08" drill="0.9" shape="offset" rot="R180"/>
+<pad name="22" x="7.62" y="-2.54" drill="0.9" shape="offset" rot="R180"/>
+<pad name="23" x="7.62" y="0" drill="0.9" shape="offset" rot="R180"/>
+<pad name="24" x="7.62" y="2.54" drill="0.9" shape="offset" rot="R180"/>
+<pad name="25" x="7.62" y="5.08" drill="0.9" shape="offset" rot="R180"/>
+<pad name="26" x="7.62" y="7.62" drill="0.9" shape="offset" rot="R180"/>
+<pad name="27" x="7.62" y="10.16" drill="0.9" shape="offset" rot="R180"/>
+<pad name="28" x="7.62" y="12.7" drill="0.9" shape="offset" rot="R180"/>
+<pad name="29" x="7.62" y="15.24" drill="0.9" shape="offset" rot="R180"/>
+<pad name="30" x="7.62" y="17.78" drill="0.9" shape="offset" rot="R180"/>
+<pad name="14" x="-7.62" y="-15.24" drill="0.9" shape="offset"/>
+<pad name="15" x="-7.62" y="-17.78" drill="0.9" shape="offset"/>
+<pad name="17" x="7.62" y="-15.24" drill="0.9" shape="offset" rot="R180"/>
+<pad name="16" x="7.62" y="-17.78" drill="0.9" shape="offset" rot="R180"/>
+<text x="3.175" y="-4.445" size="2.54" layer="21" rot="R90">NUCLEO
+L432KC</text>
+<text x="-6.35" y="20.955" size="1.778" layer="21">D1</text>
+<text x="3.175" y="20.955" size="1.778" layer="21">VIN</text>
+<text x="-5.715" y="-22.225" size="1.778" layer="21">D12</text>
+<text x="1.905" y="-22.225" size="1.778" layer="21">D13</text>
+<pad name="SHLD" x="3.175" y="-25.4" drill="0.9" shape="long"/>
+<wire x1="-9.525" y1="-24.13" x2="-9.525" y2="-21.59" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="27.305" x2="-9.525" y2="25.4" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="27.305" x2="-7.62" y2="27.305" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="27.305" x2="7.62" y2="27.305" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="-24.13" x2="-7.62" y2="-24.13" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="-24.13" x2="9.525" y2="-24.13" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="-24.13" x2="9.525" y2="-22.225" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="25.4" x2="9.525" y2="27.305" width="0.1524" layer="21"/>
+</package>
+<package name="VOLT_REGUL">
+<pad name="IN-" x="-8.5" y="20" drill="1" shape="offset"/>
+<pad name="IN+" x="8.5" y="20" drill="1" shape="offset" rot="R180"/>
+<pad name="OUT-" x="-8.5" y="-19.5" drill="1" shape="offset"/>
+<pad name="OUT+" x="8.5" y="-19.5" drill="1" shape="offset" rot="R180"/>
+<wire x1="10.5" y1="22" x2="-10.5" y2="22" width="0.1524" layer="21"/>
+<wire x1="-10.5" y1="22" x2="-10.5" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="-10.5" y1="-21.5" x2="10.5" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="10.5" y1="-21.5" x2="10.5" y2="22" width="0.1524" layer="21"/>
+<text x="2" y="-7" size="1.778" layer="21" rot="R90">VOLTAGE 
+REGULATOR</text>
+<text x="-8.5" y="16" size="1.778" layer="21">IN -</text>
+<text x="4" y="16" size="1.778" layer="21">IN +</text>
+<text x="8" y="-16.5" size="1.778" layer="21" rot="R90">OUT +</text>
+<text x="-6.5" y="-17" size="1.778" layer="21" rot="R90">OUT -</text>
+<rectangle x1="3.81" y1="-16.51" x2="10.16" y2="-1.27" layer="41"/>
+</package>
+<package name="POWER_CABLES">
+<pad name="P$1" x="-1.27" y="0" drill="1.524" shape="offset" rot="R180"/>
+<pad name="P$2" x="3.175" y="0" drill="1.524" shape="offset"/>
+<text x="-2.54" y="1.27" size="1.016" layer="21">+</text>
+<text x="3.175" y="1.27" size="1.27" layer="21">-</text>
+<text x="7.62" y="0" size="1.27" layer="25">&gt;NAME</text>
+</package>
+<package name="TO220">
+<description>&lt;b&gt;VOLTAGE REGULATOR&lt;/b&gt;</description>
+<wire x1="5.08" y1="-1.143" x2="5.08" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-4.318" x2="5.08" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-4.318" x2="-4.826" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-4.064" x2="-4.826" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-4.064" x2="-5.08" y2="-1.143" width="0.1524" layer="21"/>
+<circle x="-4.6228" y="-3.7084" radius="0.254" width="0" layer="21"/>
+<pad name="1" x="-2.54" y="-2.54" drill="1" shape="long" rot="R90"/>
+<pad name="2" x="0" y="-2.54" drill="1" shape="long" rot="R90"/>
+<pad name="3" x="2.54" y="-2.54" drill="1" shape="long" rot="R90"/>
+<text x="-5.08" y="-6.0452" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<rectangle x1="-5.334" y1="-1.27" x2="-3.429" y2="0" layer="21"/>
+<rectangle x1="-3.429" y1="-0.762" x2="-1.651" y2="0" layer="21"/>
+<rectangle x1="-1.651" y1="-1.27" x2="-0.889" y2="0" layer="21"/>
+<rectangle x1="-0.889" y1="-0.762" x2="0.889" y2="0" layer="21"/>
+<rectangle x1="0.889" y1="-1.27" x2="1.651" y2="0" layer="21"/>
+<rectangle x1="1.651" y1="-0.762" x2="3.429" y2="0" layer="21"/>
+<rectangle x1="3.429" y1="-1.27" x2="5.334" y2="0" layer="21"/>
+<rectangle x1="-3.429" y1="-1.27" x2="-1.651" y2="-0.762" layer="51"/>
+<rectangle x1="-0.889" y1="-1.27" x2="0.889" y2="-0.762" layer="51"/>
+<rectangle x1="1.651" y1="-1.27" x2="3.429" y2="-0.762" layer="51"/>
+</package>
+<package name="3,6-PAD">
+<description>&lt;b&gt;MOUNTING PAD&lt;/b&gt; 3.6 mm, round</description>
+<wire x1="-2.159" y1="0" x2="0" y2="-2.159" width="2.4892" layer="51" curve="90" cap="flat"/>
+<wire x1="0" y1="2.159" x2="2.159" y2="0" width="2.4892" layer="51" curve="-90" cap="flat"/>
+<circle x="0" y="0" radius="3.429" width="0.1524" layer="21"/>
+<circle x="0" y="0" radius="0.762" width="0.4572" layer="51"/>
+<circle x="0" y="0" radius="3.683" width="1.397" layer="39"/>
+<circle x="0" y="0" radius="3.683" width="1.397" layer="40"/>
+<circle x="0" y="0" radius="3.556" width="1.016" layer="43"/>
+<circle x="0" y="0" radius="1.9" width="0.2032" layer="21"/>
+<pad name="B3,6" x="0" y="0" drill="3.6" diameter="5.842" thermals="no"/>
+</package>
+<package name="BU-SMA-H">
+<description>FEMALE &lt;b&gt;SMA CONNECTOR&lt;/b&gt;&lt;p&gt;
+Radiall&lt;p&gt;</description>
+<wire x1="-1.1" y1="3.2" x2="1.1" y2="3.2" width="0.2032" layer="21"/>
+<wire x1="3.2" y1="1.1" x2="3.2" y2="-1.1" width="0.2032" layer="21"/>
+<wire x1="1.1" y1="-3.2" x2="-1.1" y2="-3.2" width="0.2032" layer="21"/>
+<wire x1="-3.2" y1="-1.1" x2="-3.2" y2="1.1" width="0.2032" layer="21"/>
+<wire x1="-3.1999" y1="3.1999" x2="3.2" y2="3.2" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="3.2" x2="3.2" y2="2.9" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="2.9" x2="3.2" y2="-2.9" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="-2.9" x2="3.1999" y2="-3.1999" width="0.2032" layer="51"/>
+<wire x1="3.1999" y1="-3.1999" x2="-3.2" y2="-3.2" width="0.2032" layer="51"/>
+<wire x1="-3.2" y1="-3.2" x2="-3.1999" y2="3.1999" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="2.9" x2="4.3" y2="2.9" width="0.2032" layer="51"/>
+<wire x1="4.3" y1="2.9" x2="8.3" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="2.9" x2="8.6" y2="3.4" width="0.2032" layer="21"/>
+<wire x1="10.7" y1="3.4" x2="11" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="11" y1="2.9" x2="11.6" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="11.6" y1="-2.9" x2="11.6" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.6" y1="3.4" x2="10.7" y2="3.4" width="0.2032" layer="21"/>
+<wire x1="3.2" y1="-2.9" x2="4.3" y2="-2.9" width="0.2032" layer="51"/>
+<wire x1="4.3" y1="-2.9" x2="8.3" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="-2.9" x2="8.6" y2="-3.4" width="0.2032" layer="21"/>
+<wire x1="10.7" y1="-3.4" x2="11" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="11" y1="-2.9" x2="11.6" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="8.6" y1="-3.4" x2="10.7" y2="-3.4" width="0.2032" layer="21"/>
+<wire x1="11" y1="-2.9" x2="11" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="-2.9" x2="8.3" y2="2.9" width="0.2032" layer="21"/>
+<circle x="0" y="0" radius="3.1999" width="0.2032" layer="51"/>
+<circle x="0" y="0" radius="1.7" width="0.2032" layer="21"/>
+<pad name="1" x="0" y="0" drill="1.524"/>
+<pad name="2" x="-2.5499" y="2.5499" drill="1.778"/>
+<pad name="3" x="2.5499" y="2.5499" drill="1.778"/>
+<pad name="4" x="2.5499" y="-2.5499" drill="1.778"/>
+<pad name="5" x="-2.5499" y="-2.5499" drill="1.778"/>
+<text x="-2.54" y="4.445" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.175" y="-5.715" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="W5500LITE">
+<dimension x1="-6.35" y1="-12.7" x2="16.51" y2="-12.7" x3="5.08" y3="-13.97" textsize="1.778" layer="48"/>
+<dimension x1="-6.35" y1="-12.7" x2="-6.35" y2="12.7" x3="-11.43" y3="0" textsize="1.778" layer="48"/>
+<wire x1="-6.35" y1="12.7" x2="-6.35" y2="-12.7" width="0.1524" layer="49"/>
+<wire x1="-6.35" y1="-12.7" x2="16.51" y2="-12.7" width="0.1524" layer="49"/>
+<wire x1="16.51" y1="-12.7" x2="16.51" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="-6.35" y1="12.7" x2="-1.27" y2="12.7" width="0.1524" layer="49"/>
+<pad name="P$1" x="-5.08" y="-6.35" drill="0.9" shape="long"/>
+<pad name="P$2" x="-5.08" y="-3.81" drill="0.9" shape="long"/>
+<pad name="P$3" x="-5.08" y="-1.27" drill="0.9" shape="long"/>
+<pad name="P$4" x="-5.08" y="1.27" drill="0.9" shape="long"/>
+<pad name="P$5" x="-5.08" y="3.81" drill="0.9" shape="long"/>
+<pad name="P$6" x="-5.08" y="6.35" drill="0.9" shape="long"/>
+<pad name="P$7" x="15.24" y="6.35" drill="0.9" shape="long"/>
+<pad name="P$8" x="15.24" y="3.81" drill="0.9" shape="long"/>
+<pad name="P$9" x="15.24" y="1.27" drill="0.9" shape="long"/>
+<pad name="P$10" x="15.24" y="-1.27" drill="0.9" shape="long"/>
+<pad name="P$11" x="15.24" y="-3.81" drill="0.9" shape="long"/>
+<pad name="P$12" x="15.24" y="-6.35" drill="0.9" shape="long"/>
+<wire x1="-1.27" y1="12.7" x2="11.43" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="11.43" y1="12.7" x2="16.51" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="-1.27" y1="12.7" x2="-1.27" y2="16.51" width="0.1524" layer="49"/>
+<wire x1="-1.27" y1="16.51" x2="11.43" y2="16.51" width="0.1524" layer="49"/>
+<wire x1="11.43" y1="16.51" x2="11.43" y2="12.7" width="0.1524" layer="49"/>
+<text x="12.7" y="-10.16" size="1.778" layer="26" rot="MR0">WS5500 LITE</text>
+<text x="10.16" y="8.89" size="1.778" layer="26" rot="MR0">USR-ES1</text>
+<wire x1="-6.35" y1="-12.7" x2="-6.35" y2="12.7" width="0.1524" layer="22"/>
+<wire x1="-6.35" y1="12.7" x2="16.51" y2="12.7" width="0.1524" layer="22"/>
+<wire x1="16.51" y1="12.7" x2="16.51" y2="-12.7" width="0.1524" layer="22"/>
+<wire x1="16.51" y1="-12.7" x2="-6.35" y2="-12.7" width="0.1524" layer="22"/>
+</package>
+<package name="D/7343-31W">
+<description>&lt;b&gt;Chip Capacitor Type KEMET D / EIA 7343-21&lt;/b&gt;&lt;p&gt;
+KEMET V / EIA 7343-20, KEMET X / EIA 7343-43 Wafe solder</description>
+<wire x1="-3.45" y1="2.1" x2="3.45" y2="2.1" width="0.1016" layer="51"/>
+<wire x1="3.45" y1="2.1" x2="3.45" y2="-2.1" width="0.1016" layer="51"/>
+<wire x1="3.45" y1="-2.1" x2="-3.45" y2="-2.1" width="0.1016" layer="51"/>
+<wire x1="-3.45" y1="-2.1" x2="-3.45" y2="2.1" width="0.1016" layer="51"/>
+<smd name="+" x="3.375" y="0" dx="2.95" dy="2.7" layer="1"/>
+<smd name="-" x="-3.375" y="0" dx="2.95" dy="2.7" layer="1"/>
+<text x="-3.65" y="2.3" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.65" y="-3.575" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.65" y1="-1.2" x2="-3.5" y2="1.2" layer="51"/>
+<rectangle x1="3.5" y1="-1.2" x2="3.65" y2="1.2" layer="51"/>
+<rectangle x1="2.675" y1="-2.125" x2="3.15" y2="2.125" layer="51"/>
+<wire x1="-3.4925" y1="2.2225" x2="1.5875" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="2.2225" x2="3.4925" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="-3.4925" y1="-2.2225" x2="1.5875" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-2.2225" x2="3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="2.2225" x2="1.5875" y2="-2.2225" width="0.3048" layer="21"/>
+<wire x1="-3.4925" y1="1.5875" x2="-3.4925" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="3.4925" y1="2.2225" x2="3.4925" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-3.4925" y1="-1.5875" x2="-3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="3.4925" y1="-1.5875" x2="3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+</package>
+<package name="CT6032">
+<description>&lt;b&gt;TANTALUM CAPACITOR&lt;/b&gt;</description>
+<wire x1="-4.473" y1="1.983" x2="4.473" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="-1.983" x2="-4.473" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-4.473" y1="-1.983" x2="-4.473" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="1.983" x2="4.473" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-2.932" y1="-1.637" x2="-2.932" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="-3.073" y1="1.067" x2="-3.073" y2="-1.067" width="0.1524" layer="51"/>
+<wire x1="2.957" y1="1.637" x2="-2.932" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="2.957" y1="-1.637" x2="-2.932" y2="-1.637" width="0.2032" layer="51"/>
+<wire x1="3.073" y1="1.067" x2="3.073" y2="-1.067" width="0.1524" layer="51"/>
+<wire x1="2.957" y1="-1.637" x2="2.957" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="-1.18" y1="0" x2="-2.45" y2="0" width="0.2032" layer="51"/>
+<wire x1="-1.8" y1="0.63" x2="-1.8" y2="-0.64" width="0.2032" layer="51"/>
+<smd name="+" x="-2.5" y="0" dx="2.6" dy="2.2" layer="1"/>
+<smd name="-" x="2.5" y="0" dx="2.6" dy="2.2" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+<wire x1="-2.8575" y1="1.27" x2="-2.8575" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-2.8575" y1="1.5875" x2="-0.9525" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="1.5875" x2="2.8575" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="1.5875" x2="2.8575" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="-1.27" x2="2.8575" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="-1.5875" x2="-0.9525" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="-1.5875" x2="-2.8575" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="-2.8575" y1="-1.5875" x2="-2.8575" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="1.5875" x2="-0.9525" y2="-1.5875" width="0.254" layer="21"/>
+</package>
+<package name="B/3528-21W">
+<description>&lt;b&gt;Chip Capacitor Type KEMET B / EIA 3528-21 Wave solder&lt;/b&gt;&lt;p&gt;
+KEMET T / EIA 3528-12</description>
+<wire x1="-1.6" y1="1.2" x2="1.6" y2="1.2" width="0.1016" layer="51"/>
+<wire x1="1.6" y1="1.2" x2="1.6" y2="-1.2" width="0.1016" layer="51"/>
+<wire x1="1.6" y1="-1.2" x2="-1.6" y2="-1.2" width="0.1016" layer="51"/>
+<wire x1="-1.6" y1="-1.2" x2="-1.6" y2="1.2" width="0.1016" layer="51"/>
+<smd name="+" x="1.9425" y="0" dx="1.651" dy="1.8" layer="1"/>
+<smd name="-" x="-1.625" y="0" dx="2.15" dy="1.8" layer="1"/>
+<text x="-1.95" y="1.6" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.95" y="-2.925" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.75" y1="-0.6" x2="-1.625" y2="0.6" layer="51"/>
+<rectangle x1="1.625" y1="-0.6" x2="1.75" y2="0.6" layer="51"/>
+<rectangle x1="0.95" y1="-1.225" x2="1.25" y2="1.225" layer="51"/>
+<wire x1="-1.5875" y1="1.27" x2="0.9525" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="1.27" x2="1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="0.9525" x2="1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="0.9525" x2="-1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.9525" x2="-1.5875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-1.27" x2="0.9525" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="-1.27" x2="1.5875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-1.27" x2="1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="1.27" x2="0.9525" y2="-1.27" width="0.254" layer="21"/>
+</package>
+<package name="CT3216">
+<description>&lt;b&gt;TANTALUM CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.973" y1="1.483" x2="2.973" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-1.483" x2="-2.973" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-1.483" x2="-2.973" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="1.483" x2="2.973" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-1.651" y1="0.559" x2="-1.651" y2="-0.559" width="0.1524" layer="51"/>
+<wire x1="1.651" y1="0.559" x2="1.651" y2="-0.559" width="0.1524" layer="51"/>
+<wire x1="-1.535" y1="0.798" x2="-1.535" y2="-0.798" width="0.2032" layer="51"/>
+<wire x1="-1.535" y1="-0.798" x2="1.535" y2="-0.798" width="0.2032" layer="51"/>
+<wire x1="1.535" y1="-0.798" x2="1.535" y2="0.798" width="0.2032" layer="51"/>
+<wire x1="1.535" y1="0.798" x2="-1.535" y2="0.798" width="0.2032" layer="51"/>
+<wire x1="-0.7" y1="0" x2="-1.26" y2="0" width="0.2032" layer="51"/>
+<wire x1="-0.97" y1="0.26" x2="-0.97" y2="-0.3" width="0.2032" layer="51"/>
+<smd name="+" x="-1.7175" y="0" dx="1.524" dy="1.2" layer="1"/>
+<smd name="-" x="1.4" y="0" dx="2" dy="1.2" layer="1"/>
+<text x="-2.54" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.1999" y1="-0.5999" x2="0.1999" y2="0.5999" layer="35"/>
+<wire x1="1.5875" y1="0.635" x2="1.5875" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="0.9525" x2="-0.635" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="0.9525" x2="-1.5875" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="0.9525" x2="-1.5875" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.635" x2="-1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.9525" x2="-0.635" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="-0.9525" x2="1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-0.9525" x2="1.5875" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="0.9525" x2="-0.635" y2="-0.9525" width="0.254" layer="21"/>
+</package>
+<package name="SO08">
+<description>&lt;b&gt;Small Outline Package&lt;/b&gt; SOIC 150 mil</description>
+<wire x1="2.159" y1="1.9558" x2="-2.159" y2="1.9558" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.9558" x2="2.54" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.54" y1="1.5748" x2="-2.159" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="1.9558" x2="2.54" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.54" y1="-1.5748" x2="-2.159" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.159" y1="-1.9558" x2="2.159" y2="-1.9558" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-1.5748" x2="2.54" y2="1.5748" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="1.5748" x2="-2.54" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.508" x2="-2.54" y2="-1.5748" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-2.54" y1="-1.6002" x2="2.54" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="8" x="-1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="2" x="-0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="3" x="0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="7" x="-0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="6" x="0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="4" x="1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="5" x="1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<text x="3.937" y="-2.032" size="1.27" layer="27" ratio="10" rot="R90">&gt;VALUE</text>
+<rectangle x1="1.651" y1="1.9558" x2="2.159" y2="3.0988" layer="51"/>
+<rectangle x1="-2.159" y1="-3.0988" x2="-1.651" y2="-1.9558" layer="51"/>
+<rectangle x1="-0.889" y1="-3.0988" x2="-0.381" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="-3.0734" x2="0.889" y2="-1.9304" layer="51"/>
+<rectangle x1="1.651" y1="-3.0988" x2="2.159" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="1.9558" x2="0.889" y2="3.0988" layer="51"/>
+<rectangle x1="-0.889" y1="1.9558" x2="-0.381" y2="3.0988" layer="51"/>
+<rectangle x1="-2.159" y1="1.9558" x2="-1.651" y2="3.0988" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="resistor" urn="urn:adsk.eagle:library:348">
+<description>&lt;b&gt;Resistors, Capacitors, Inductors&lt;/b&gt;&lt;p&gt;
+Based on the previous libraries:
+&lt;ul&gt;
+&lt;li&gt;r.lbr
+&lt;li&gt;cap.lbr 
+&lt;li&gt;cap-fe.lbr
+&lt;li&gt;captant.lbr
+&lt;li&gt;polcap.lbr
+&lt;li&gt;ipc-smd.lbr
+&lt;/ul&gt;
+All SMD packages are defined according to the IPC specifications and  CECC&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;p&gt;
+&lt;p&gt;
+for Electrolyt Capacitors see also :&lt;p&gt;
+www.bccomponents.com &lt;p&gt;
+www.panasonic.com&lt;p&gt;
+www.kemet.com&lt;p&gt;
+&lt;p&gt;
+for trimmer refence see : &lt;u&gt;www.electrospec-inc.com/cross_references/trimpotcrossref.asp&lt;/u&gt;&lt;p&gt;
+
+&lt;map name="nav_main"&gt;
+&lt;area shape="rect" coords="0,1,140,23" href="../military_specs.asp" title=""&gt;
+&lt;area shape="rect" coords="0,24,140,51" href="../about.asp" title=""&gt;
+&lt;area shape="rect" coords="1,52,140,77" href="../rfq.asp" title=""&gt;
+&lt;area shape="rect" coords="0,78,139,103" href="../products.asp" title=""&gt;
+&lt;area shape="rect" coords="1,102,138,128" href="../excess_inventory.asp" title=""&gt;
+&lt;area shape="rect" coords="1,129,138,150" href="../edge.asp" title=""&gt;
+&lt;area shape="rect" coords="1,151,139,178" href="../industry_links.asp" title=""&gt;
+&lt;area shape="rect" coords="0,179,139,201" href="../comments.asp" title=""&gt;
+&lt;area shape="rect" coords="1,203,138,231" href="../directory.asp" title=""&gt;
+&lt;area shape="default" nohref&gt;
+&lt;/map&gt;
+
+&lt;html&gt;
+
+&lt;title&gt;&lt;/title&gt;
+
+ &lt;LINK REL="StyleSheet" TYPE="text/css" HREF="style-sheet.css"&gt;
+
+&lt;body bgcolor="#ffffff" text="#000000" marginwidth="0" marginheight="0" topmargin="0" leftmargin="0"&gt;
+&lt;table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0 height="55%"&gt;
+&lt;tr valign="top"&gt;
+
+&lt;/td&gt;
+&lt;! &lt;td width="10"&gt;&amp;nbsp;&lt;/td&gt;
+&lt;td width="90%"&gt;
+
+&lt;b&gt;&lt;font color="#0000FF" size="4"&gt;TRIM-POT CROSS REFERENCE&lt;/font&gt;&lt;/b&gt;
+&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;RECTANGULAR MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BOURNS&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BI&amp;nbsp;TECH&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;DALE-VISHAY&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PHILIPS/MEPCO&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MURATA&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PANASONIC&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;SPECTROL&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MILSPEC&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;&lt;TD&gt;&amp;nbsp;&lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3 &gt;
+      3005P&lt;BR&gt;
+      3006P&lt;BR&gt;
+      3006W&lt;BR&gt;
+      3006Y&lt;BR&gt;
+      3009P&lt;BR&gt;
+      3009W&lt;BR&gt;
+      3009Y&lt;BR&gt;
+      3057J&lt;BR&gt;
+      3057L&lt;BR&gt;
+      3057P&lt;BR&gt;
+      3057Y&lt;BR&gt;
+      3059J&lt;BR&gt;
+      3059L&lt;BR&gt;
+      3059P&lt;BR&gt;
+      3059Y&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      89P&lt;BR&gt;
+      89W&lt;BR&gt;
+      89X&lt;BR&gt;
+      89PH&lt;BR&gt;
+      76P&lt;BR&gt;
+      89XH&lt;BR&gt;
+      78SLT&lt;BR&gt;
+      78L&amp;nbsp;ALT&lt;BR&gt;
+      56P&amp;nbsp;ALT&lt;BR&gt;
+      78P&amp;nbsp;ALT&lt;BR&gt;
+      T8S&lt;BR&gt;
+      78L&lt;BR&gt;
+      56P&lt;BR&gt;
+      78P&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      T18/784&lt;BR&gt;
+      783&lt;BR&gt;
+      781&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      2199&lt;BR&gt;
+      1697/1897&lt;BR&gt;
+      1680/1880&lt;BR&gt;
+      2187&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      8035EKP/CT20/RJ-20P&lt;BR&gt;
+      -&lt;BR&gt;
+      RJ-20X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      1211L&lt;BR&gt;
+      8012EKQ&amp;nbsp;ALT&lt;BR&gt;
+      8012EKR&amp;nbsp;ALT&lt;BR&gt;
+      1211P&lt;BR&gt;
+      8012EKJ&lt;BR&gt;
+      8012EKL&lt;BR&gt;
+      8012EKQ&lt;BR&gt;
+      8012EKR&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      2101P&lt;BR&gt;
+      2101W&lt;BR&gt;
+      2101Y&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      2102L&lt;BR&gt;
+      2102S&lt;BR&gt;
+      2102Y&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      EVMCOG&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      43P&lt;BR&gt;
+      43W&lt;BR&gt;
+      43Y&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      40L&lt;BR&gt;
+      40P&lt;BR&gt;
+      40Y&lt;BR&gt;
+      70Y-T602&lt;BR&gt;
+      70L&lt;BR&gt;
+      70P&lt;BR&gt;
+      70Y&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      RT/RTR12&lt;BR&gt;
+      RT/RTR12&lt;BR&gt;
+      RT/RTR12&lt;BR&gt;
+      -&lt;BR&gt;
+      RJ/RJR12&lt;BR&gt;
+      RJ/RJR12&lt;BR&gt;
+      RJ/RJR12&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;&amp;nbsp;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SQUARE MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+   &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MURATA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;SPECTROL&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MILSPEC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3250L&lt;BR&gt;
+      3250P&lt;BR&gt;
+      3250W&lt;BR&gt;
+      3250X&lt;BR&gt;
+      3252P&lt;BR&gt;
+      3252W&lt;BR&gt;
+      3252X&lt;BR&gt;
+      3260P&lt;BR&gt;
+      3260W&lt;BR&gt;
+      3260X&lt;BR&gt;
+      3262P&lt;BR&gt;
+      3262W&lt;BR&gt;
+      3262X&lt;BR&gt;
+      3266P&lt;BR&gt;
+      3266W&lt;BR&gt;
+      3266X&lt;BR&gt;
+      3290H&lt;BR&gt;
+      3290P&lt;BR&gt;
+      3290W&lt;BR&gt;
+      3292P&lt;BR&gt;
+      3292W&lt;BR&gt;
+      3292X&lt;BR&gt;
+      3296P&lt;BR&gt;
+      3296W&lt;BR&gt;
+      3296X&lt;BR&gt;
+      3296Y&lt;BR&gt;
+      3296Z&lt;BR&gt;
+      3299P&lt;BR&gt;
+      3299W&lt;BR&gt;
+      3299X&lt;BR&gt;
+      3299Y&lt;BR&gt;
+      3299Z&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      66P&amp;nbsp;ALT&lt;BR&gt;
+      66W&amp;nbsp;ALT&lt;BR&gt;
+      66X&amp;nbsp;ALT&lt;BR&gt;
+      66P&amp;nbsp;ALT&lt;BR&gt;
+      66W&amp;nbsp;ALT&lt;BR&gt;
+      66X&amp;nbsp;ALT&lt;BR&gt;
+      -&lt;BR&gt;
+      64W&amp;nbsp;ALT&lt;BR&gt;
+      -&lt;BR&gt;
+      64P&amp;nbsp;ALT&lt;BR&gt;
+      64W&amp;nbsp;ALT&lt;BR&gt;
+      64X&amp;nbsp;ALT&lt;BR&gt;
+      64P&lt;BR&gt;
+      64W&lt;BR&gt;
+      64X&lt;BR&gt;
+      66X&amp;nbsp;ALT&lt;BR&gt;
+      66P&amp;nbsp;ALT&lt;BR&gt;
+      66W&amp;nbsp;ALT&lt;BR&gt;
+      66P&lt;BR&gt;
+      66W&lt;BR&gt;
+      66X&lt;BR&gt;
+      67P&lt;BR&gt;
+      67W&lt;BR&gt;
+      67X&lt;BR&gt;
+      67Y&lt;BR&gt;
+      67Z&lt;BR&gt;
+      68P&lt;BR&gt;
+      68W&lt;BR&gt;
+      68X&lt;BR&gt;
+      67Y&amp;nbsp;ALT&lt;BR&gt;
+      67Z&amp;nbsp;ALT&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      5050&lt;BR&gt;
+      5091&lt;BR&gt;
+      5080&lt;BR&gt;
+      5087&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      T63YB&lt;BR&gt;
+      T63XB&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      5887&lt;BR&gt;
+      5891&lt;BR&gt;
+      5880&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      T93Z&lt;BR&gt;
+      T93YA&lt;BR&gt;
+      T93XA&lt;BR&gt;
+      T93YB&lt;BR&gt;
+      T93XB&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      8026EKP&lt;BR&gt;
+      8026EKW&lt;BR&gt;
+      8026EKM&lt;BR&gt;
+      8026EKP&lt;BR&gt;
+      8026EKB&lt;BR&gt;
+      8026EKM&lt;BR&gt;
+      1309X&lt;BR&gt;
+      1309P&lt;BR&gt;
+      1309W&lt;BR&gt;
+      8024EKP&lt;BR&gt;
+      8024EKW&lt;BR&gt;
+      8024EKN&lt;BR&gt;
+      RJ-9P/CT9P&lt;BR&gt;
+      RJ-9W&lt;BR&gt;
+      RJ-9X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3103P&lt;BR&gt;
+      3103Y&lt;BR&gt;
+      3103Z&lt;BR&gt;
+      3103P&lt;BR&gt;
+      3103Y&lt;BR&gt;
+      3103Z&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3105P/3106P&lt;BR&gt;
+      3105W/3106W&lt;BR&gt;
+      3105X/3106X&lt;BR&gt;
+      3105Y/3106Y&lt;BR&gt;
+      3105Z/3105Z&lt;BR&gt;
+      3102P&lt;BR&gt;
+      3102W&lt;BR&gt;
+      3102X&lt;BR&gt;
+      3102Y&lt;BR&gt;
+      3102Z&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMCBG&lt;BR&gt;
+      EVMCCG&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      55-1-X&lt;BR&gt;
+      55-4-X&lt;BR&gt;
+      55-3-X&lt;BR&gt;
+      55-2-X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      50-2-X&lt;BR&gt;
+      50-4-X&lt;BR&gt;
+      50-3-X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      64P&lt;BR&gt;
+      64W&lt;BR&gt;
+      64X&lt;BR&gt;
+      64Y&lt;BR&gt;
+      64Z&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      RT/RTR22&lt;BR&gt;
+      RT/RTR22&lt;BR&gt;
+      RT/RTR22&lt;BR&gt;
+      RT/RTR22&lt;BR&gt;
+      RJ/RJR22&lt;BR&gt;
+      RJ/RJR22&lt;BR&gt;
+      RJ/RJR22&lt;BR&gt;
+      RT/RTR26&lt;BR&gt;
+      RT/RTR26&lt;BR&gt;
+      RT/RTR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RT/RTR24&lt;BR&gt;
+      RT/RTR24&lt;BR&gt;
+      RT/RTR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;&amp;nbsp;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SINGLE TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MURATA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;SPECTROL&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MILSPEC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3323P&lt;BR&gt;
+      3323S&lt;BR&gt;
+      3323W&lt;BR&gt;
+      3329H&lt;BR&gt;
+      3329P&lt;BR&gt;
+      3329W&lt;BR&gt;
+      3339H&lt;BR&gt;
+      3339P&lt;BR&gt;
+      3339W&lt;BR&gt;
+      3352E&lt;BR&gt;
+      3352H&lt;BR&gt;
+      3352K&lt;BR&gt;
+      3352P&lt;BR&gt;
+      3352T&lt;BR&gt;
+      3352V&lt;BR&gt;
+      3352W&lt;BR&gt;
+      3362H&lt;BR&gt;
+      3362M&lt;BR&gt;
+      3362P&lt;BR&gt;
+      3362R&lt;BR&gt;
+      3362S&lt;BR&gt;
+      3362U&lt;BR&gt;
+      3362W&lt;BR&gt;
+      3362X&lt;BR&gt;
+      3386B&lt;BR&gt;
+      3386C&lt;BR&gt;
+      3386F&lt;BR&gt;
+      3386H&lt;BR&gt;
+      3386K&lt;BR&gt;
+      3386M&lt;BR&gt;
+      3386P&lt;BR&gt;
+      3386S&lt;BR&gt;
+      3386W&lt;BR&gt;
+      3386X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      25P&lt;BR&gt;
+      25S&lt;BR&gt;
+      25RX&lt;BR&gt;
+      82P&lt;BR&gt;
+      82M&lt;BR&gt;
+      82PA&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      91E&lt;BR&gt;
+      91X&lt;BR&gt;
+      91T&lt;BR&gt;
+      91B&lt;BR&gt;
+      91A&lt;BR&gt;
+      91V&lt;BR&gt;
+      91W&lt;BR&gt;
+      25W&lt;BR&gt;
+      25V&lt;BR&gt;
+      25P&lt;BR&gt;
+      -&lt;BR&gt;
+      25S&lt;BR&gt;
+      25U&lt;BR&gt;
+      25RX&lt;BR&gt;
+      25X&lt;BR&gt;
+      72XW&lt;BR&gt;
+      72XL&lt;BR&gt;
+      72PM&lt;BR&gt;
+      72RX&lt;BR&gt;
+      -&lt;BR&gt;
+      72PX&lt;BR&gt;
+      72P&lt;BR&gt;
+      72RXW&lt;BR&gt;
+      72RXL&lt;BR&gt;
+      72X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      T7YB&lt;BR&gt;
+      T7YA&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      TXD&lt;BR&gt;
+      TYA&lt;BR&gt;
+      TYP&lt;BR&gt;
+      -&lt;BR&gt;
+      TYD&lt;BR&gt;
+      TX&lt;BR&gt;
+      -&lt;BR&gt;
+      150SX&lt;BR&gt;
+      100SX&lt;BR&gt;
+      102T&lt;BR&gt;
+      101S&lt;BR&gt;
+      190T&lt;BR&gt;
+      150TX&lt;BR&gt;
+      101&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      101SX&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      ET6P&lt;BR&gt;
+      ET6S&lt;BR&gt;
+      ET6X&lt;BR&gt;
+      RJ-6W/8014EMW&lt;BR&gt;
+      RJ-6P/8014EMP&lt;BR&gt;
+      RJ-6X/8014EMX&lt;BR&gt;
+      TM7W&lt;BR&gt;
+      TM7P&lt;BR&gt;
+      TM7X&lt;BR&gt;
+      -&lt;BR&gt;
+      8017SMS&lt;BR&gt;
+      -&lt;BR&gt;
+      8017SMB&lt;BR&gt;
+      8017SMA&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      CT-6W&lt;BR&gt;
+      CT-6H&lt;BR&gt;
+      CT-6P&lt;BR&gt;
+      CT-6R&lt;BR&gt;
+      -&lt;BR&gt;
+      CT-6V&lt;BR&gt;
+      CT-6X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      8038EKV&lt;BR&gt;
+      -&lt;BR&gt;
+      8038EKX&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      8038EKP&lt;BR&gt;
+      8038EKZ&lt;BR&gt;
+      8038EKW&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3321H&lt;BR&gt;
+      3321P&lt;BR&gt;
+      3321N&lt;BR&gt;
+      1102H&lt;BR&gt;
+      1102P&lt;BR&gt;
+      1102T&lt;BR&gt;
+      RVA0911V304A&lt;BR&gt;
+      -&lt;BR&gt;
+      RVA0911H413A&lt;BR&gt;
+      RVG0707V100A&lt;BR&gt;
+      RVA0607V(H)306A&lt;BR&gt;
+      RVA1214H213A&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3104B&lt;BR&gt;
+      3104C&lt;BR&gt;
+      3104F&lt;BR&gt;
+      3104H&lt;BR&gt;
+      -&lt;BR&gt;
+      3104M&lt;BR&gt;
+      3104P&lt;BR&gt;
+      3104S&lt;BR&gt;
+      3104W&lt;BR&gt;
+      3104X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      EVMQ0G&lt;BR&gt;
+      EVMQIG&lt;BR&gt;
+      EVMQ3G&lt;BR&gt;
+      EVMS0G&lt;BR&gt;
+      EVMQ0G&lt;BR&gt;
+      EVMG0G&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMK4GA00B&lt;BR&gt;
+      EVM30GA00B&lt;BR&gt;
+      EVMK0GA00B&lt;BR&gt;
+      EVM38GA00B&lt;BR&gt;
+      EVMB6&lt;BR&gt;
+      EVLQ0&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMMSG&lt;BR&gt;
+      EVMMBG&lt;BR&gt;
+      EVMMAG&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMMCS&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMM1&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMM0&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMM3&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      62-3-1&lt;BR&gt;
+      62-1-2&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      67R&lt;BR&gt;
+      -&lt;BR&gt;
+      67P&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      67X&lt;BR&gt;
+      63V&lt;BR&gt;
+      63S&lt;BR&gt;
+      63M&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      63H&lt;BR&gt;
+      63P&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      63X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      RJ/RJR50&lt;BR&gt;
+      RJ/RJR50&lt;BR&gt;
+      RJ/RJR50&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+&lt;/TABLE&gt;
+&lt;P&gt;&amp;nbsp;&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;
+      &lt;FONT color="#0000FF" SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SMD TRIM-POT CROSS REFERENCE&lt;/B&gt;&lt;/FONT&gt;
+      &lt;P&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURNS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;TOCOS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;AUX/KYOCERA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3224G&lt;BR&gt;
+      3224J&lt;BR&gt;
+      3224W&lt;BR&gt;
+      3269P&lt;BR&gt;
+      3269W&lt;BR&gt;
+      3269X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      44G&lt;BR&gt;
+      44J&lt;BR&gt;
+      44W&lt;BR&gt;
+      84P&lt;BR&gt;
+      84W&lt;BR&gt;
+      84X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      ST63Z&lt;BR&gt;
+      ST63Y&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      ST5P&lt;BR&gt;
+      ST5W&lt;BR&gt;
+      ST5X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;&amp;nbsp;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SINGLE TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURNS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;TOCOS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;AUX/KYOCERA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3314G&lt;BR&gt;
+      3314J&lt;BR&gt;
+      3364A/B&lt;BR&gt;
+      3364C/D&lt;BR&gt;
+      3364W/X&lt;BR&gt;
+      3313G&lt;BR&gt;
+      3313J&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      23B&lt;BR&gt;
+      23A&lt;BR&gt;
+      21X&lt;BR&gt;
+      21W&lt;BR&gt;
+      -&lt;BR&gt;
+      22B&lt;BR&gt;
+      22A&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      ST5YL/ST53YL&lt;BR&gt;
+      ST5YJ/5T53YJ&lt;BR&gt;
+      ST-23A&lt;BR&gt;
+      ST-22B&lt;BR&gt;
+      ST-22&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      ST-4B&lt;BR&gt;
+      ST-4A&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      ST-3B&lt;BR&gt;
+      ST-3A&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      EVM-6YS&lt;BR&gt;
+      EVM-1E&lt;BR&gt;
+      EVM-1G&lt;BR&gt;
+      EVM-1D&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      G4B&lt;BR&gt;
+      G4A&lt;BR&gt;
+      TR04-3S1&lt;BR&gt;
+      TRG04-2S1&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      DVR-43A&lt;BR&gt;
+      CVR-42C&lt;BR&gt;
+      CVR-42A/C&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+&lt;/TABLE&gt;
+&lt;P&gt;
+&lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;ALT =&amp;nbsp;ALTERNATE&lt;/B&gt;&lt;/FONT&gt;
+&lt;P&gt;
+
+&amp;nbsp;
+&lt;P&gt;
+&lt;/td&gt;
+&lt;/tr&gt;
+&lt;/table&gt;
+&lt;/BODY&gt;&lt;/HTML&gt;</description>
+<packages>
+<package name="M0805" urn="urn:adsk.eagle:footprint:25647/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.10 W</description>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="0.7112" y1="0.635" x2="-0.7112" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="0.7112" y1="-0.635" x2="-0.7112" y2="-0.635" width="0.1524" layer="51"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.6" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.6" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.0414" y1="-0.7112" x2="-0.6858" y2="0.7112" layer="51"/>
+<rectangle x1="0.6858" y1="-0.7112" x2="1.0414" y2="0.7112" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.5999" x2="0.1999" y2="0.5999" layer="35"/>
+</package>
+<package name="C1206K" urn="urn:adsk.eagle:footprint:25772/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 1206 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 3216</description>
+<wire x1="-1.525" y1="0.75" x2="1.525" y2="0.75" width="0.1016" layer="51"/>
+<wire x1="1.525" y1="-0.75" x2="-1.525" y2="-0.75" width="0.1016" layer="51"/>
+<smd name="1" x="-1.5" y="0" dx="1.5" dy="2" layer="1"/>
+<smd name="2" x="1.5" y="0" dx="1.5" dy="2" layer="1"/>
+<text x="-1.6" y="1.1" size="1.016" layer="25">&gt;NAME</text>
+<text x="-1.6" y="-2.1" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.6" y1="-0.8" x2="-1.1" y2="0.8" layer="51"/>
+<rectangle x1="1.1" y1="-0.8" x2="1.6" y2="0.8" layer="51"/>
+</package>
+</packages>
+<packages3d>
+<package3d name="M0805" urn="urn:adsk.eagle:package:26079/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.10 W</description>
+</package3d>
+<package3d name="C1206K" urn="urn:adsk.eagle:package:26202/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 1206 reflow solder
+Metric Code Size 3216</description>
+</package3d>
+</packages3d>
+</library>
+<library name="transistor" urn="urn:adsk.eagle:library:402">
+<description>&lt;b&gt;Transistors&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="SOT23" urn="urn:adsk.eagle:footprint:28669/1" library_version="5">
+<description>&lt;b&gt;SOT-23&lt;/b&gt;</description>
+<wire x1="1.4224" y1="0.6604" x2="1.4224" y2="-0.6604" width="0.1524" layer="51"/>
+<wire x1="1.4224" y1="-0.6604" x2="-1.4224" y2="-0.6604" width="0.1524" layer="51"/>
+<wire x1="-1.4224" y1="-0.6604" x2="-1.4224" y2="0.6604" width="0.1524" layer="51"/>
+<wire x1="-1.4224" y1="0.6604" x2="1.4224" y2="0.6604" width="0.1524" layer="51"/>
+<smd name="3" x="0" y="1.1" dx="1" dy="1.4" layer="1"/>
+<smd name="2" x="0.95" y="-1.1" dx="1" dy="1.4" layer="1"/>
+<smd name="1" x="-0.95" y="-1.1" dx="1" dy="1.4" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.2286" y1="0.7112" x2="0.2286" y2="1.2954" layer="51"/>
+<rectangle x1="0.7112" y1="-1.2954" x2="1.1684" y2="-0.7112" layer="51"/>
+<rectangle x1="-1.1684" y1="-1.2954" x2="-0.7112" y2="-0.7112" layer="51"/>
+</package>
+</packages>
+<packages3d>
+<package3d name="SOT23" urn="urn:adsk.eagle:package:28738/2" type="model" library_version="5">
+<description>SOT-23</description>
+</package3d>
+</packages3d>
+</library>
+<library name="mfj-236">
+<description>2 x 3mm-leds in vertial, left = K, right = A</description>
+<packages>
+<package name="LEDX2_V_K_A">
+<pad name="K1" x="-1.27" y="3.81" drill="0.6" diameter="1.27" shape="octagon"/>
+<pad name="A1" x="1.27" y="3.81" drill="0.6" diameter="1.27"/>
+<pad name="K2" x="-1.27" y="1.524" drill="0.6" diameter="1.27" shape="octagon"/>
+<pad name="A2" x="1.27" y="1.524" drill="0.6" diameter="1.27"/>
+<wire x1="-2.413" y1="4.826" x2="2.413" y2="4.826" width="0.127" layer="21"/>
+<wire x1="-2.413" y1="4.826" x2="-2.413" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="2.413" y1="4.826" x2="2.413" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-4.191" x2="2.413" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="-2.413" y1="-4.191" x2="-1.524" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="-1.524" y1="-4.191" x2="1.524" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-4.191" x2="1.524" y2="-5.842" width="0.127" layer="21"/>
+<wire x1="-1.524" y1="-5.842" x2="-1.524" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-5.842" x2="-1.524" y2="-5.842" width="0.127" layer="21" curve="-165.749967"/>
+<wire x1="2.54" y1="-5.08" x2="3.683" y2="-5.969" width="0.127" layer="21"/>
+<wire x1="3.683" y1="-5.969" x2="3.683" y2="-5.588" width="0.127" layer="21"/>
+<wire x1="3.683" y1="-5.969" x2="3.302" y2="-5.969" width="0.127" layer="21"/>
+<wire x1="2.032" y1="-5.842" x2="3.175" y2="-6.731" width="0.127" layer="21"/>
+<wire x1="3.175" y1="-6.731" x2="3.175" y2="-6.35" width="0.127" layer="21"/>
+<wire x1="3.175" y1="-6.731" x2="2.794" y2="-6.731" width="0.127" layer="21"/>
+<text x="-2.413" y="5.588" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-8.89" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="con-harting" urn="urn:adsk.eagle:library:151">
+<description>&lt;b&gt;Harting Ribbon Cable Connectors&lt;/b&gt;&lt;p&gt;
+This library includes the former libraries ribcon.lbr and ribcon4.lbr.&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="CON10" urn="urn:adsk.eagle:footprint:7079/1" library_version="1">
+<description>&lt;b&gt;CONNECTOR&lt;/b&gt;</description>
+<wire x1="8.8646" y1="-3.4798" x2="8.8646" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="3.5052" x2="8.001" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="3.5052" x2="-8.89" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-3.4798" x2="-8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-4.1656" x2="-6.35" y2="-4.1656" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="8.255" x2="6.35" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="-5.5118" y1="-2.3368" x2="-4.6482" y2="-2.3368" width="0.1524" layer="21"/>
+<wire x1="-4.6482" y1="-2.3368" x2="-5.08" y2="-3.175" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-3.175" x2="-5.5118" y2="-2.3368" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="-3.4798" x2="-6.35" y2="-4.1656" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-3.4798" x2="6.35" y2="-4.1656" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="3.5052" x2="6.35" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="3.5052" x2="-6.35" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="0" y1="9.525" x2="3.81" y2="8.255" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="9.525" x2="-2.54" y2="8.255" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="8.255" x2="0" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-3.175" x2="-5.08" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="3.5052" x2="8.001" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="2.159" x2="8.8646" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="0.635" x2="8.8646" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="3.5052" x2="6.35" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="2.159" x2="8.8646" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="0.635" x2="8.8646" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="3.5052" x2="-6.35" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-2.159" x2="8.8646" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-2.159" x2="8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="-2.159" x2="8.8646" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-0.635" x2="8.8646" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="-0.635" x2="8.8646" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-3.4798" x2="8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="3.5052" x2="-8.001" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="-3.4798" x2="6.35" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="0.635" x2="8.001" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="3.5052" x2="-8.001" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="3.5052" x2="-8.89" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="2.159" x2="-8.001" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="0.635" x2="-8.001" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="0.635" x2="-8.001" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-0.635" x2="-8.001" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-2.159" x2="-8.001" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="-2.159" x2="-8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="0.635" x2="-8.89" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="2.159" x2="-8.89" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-0.635" x2="-8.89" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-2.159" x2="-8.89" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="-3.4798" x2="-6.35" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-3.4798" x2="8.8646" y2="-3.4798" width="0.1524" layer="21"/>
+<pad name="1" x="-5.08" y="-1.27" drill="0.9144"/>
+<pad name="2" x="-5.08" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="3" x="-2.54" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="4" x="-2.54" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="5" x="0" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="6" x="0" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="7" x="2.54" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="8" x="2.54" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="9" x="5.08" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="10" x="5.08" y="1.27" drill="0.9144" shape="octagon"/>
+<text x="-7.493" y="-1.905" size="1.524" layer="21" ratio="10">1</text>
+<text x="-5.715" y="6.0198" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.715" y="4.191" size="1.27" layer="21" ratio="10">R-Cable10P</text>
+<text x="-6.35" y="-5.715" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-5.334" y1="-2.7686" x2="-4.826" y2="-2.5146" layer="21"/>
+<rectangle x1="-5.461" y1="-2.5146" x2="-5.08" y2="-2.3876" layer="21"/>
+<rectangle x1="-5.08" y1="-2.5146" x2="-4.699" y2="-2.3876" layer="21"/>
+<rectangle x1="-5.207" y1="-2.9718" x2="-4.953" y2="-2.7178" layer="21"/>
+</package>
+</packages>
+<packages3d>
+<package3d name="CON10" urn="urn:adsk.eagle:package:7121/1" type="box" library_version="1">
+<description>CONNECTOR</description>
+</package3d>
+</packages3d>
+</library>
+<library name="diode" urn="urn:adsk.eagle:library:210">
+<description>&lt;b&gt;Diodes&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Motorola : www.onsemi.com
+&lt;li&gt;Fairchild : www.fairchildsemi.com
+&lt;li&gt;Philips : www.semiconductors.com
+&lt;li&gt;Vishay : www.vishay.de
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DO-214AC" urn="urn:adsk.eagle:footprint:43216/1" library_version="2">
+<description>&lt;b&gt;SURFACE MOUNT GENERAL RECTIFIER&lt;/b&gt; JEDEC DO-214AC molded platic body&lt;p&gt;
+Method 2026&lt;br&gt;
+Source: http://www.kingtronics.com/SMD_M7/M7_SMD_4007.pdf</description>
+<wire x1="-2.15" y1="1.3" x2="2.15" y2="1.3" width="0.2032" layer="51"/>
+<wire x1="2.15" y1="1.3" x2="2.15" y2="-1.3" width="0.2032" layer="51"/>
+<wire x1="2.15" y1="-1.3" x2="-2.15" y2="-1.3" width="0.2032" layer="51"/>
+<wire x1="-2.15" y1="-1.3" x2="-2.15" y2="1.3" width="0.2032" layer="51"/>
+<wire x1="-1.035" y1="1.3" x2="1.025" y2="1.3" width="0.2032" layer="21"/>
+<wire x1="1.025" y1="-1.3" x2="-1.035" y2="-1.3" width="0.2032" layer="21"/>
+<smd name="C" x="-2.025" y="0" dx="1.8" dy="2.4" layer="1"/>
+<smd name="A" x="2.025" y="0" dx="1.8" dy="2.4" layer="1" rot="R180"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.825" y1="-1.1" x2="-2.175" y2="1.1" layer="51"/>
+<rectangle x1="2.175" y1="-1.1" x2="2.825" y2="1.1" layer="51" rot="R180"/>
+<rectangle x1="-1.065" y1="-1.225" x2="-0.39" y2="1.225" layer="21"/>
+<rectangle x1="-1.75" y1="-1.225" x2="-1.075" y2="1.225" layer="51"/>
+</package>
+</packages>
+<packages3d>
+<package3d name="DO214AC" urn="urn:adsk.eagle:package:43417/2" type="model" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="DO-214AC" urn="urn:adsk.eagle:package:43416/2" type="model" library_version="2">
+<description>SURFACE MOUNT GENERAL RECTIFIER JEDEC DO-214AC molded platic body
+Method 2026
+Source: http://www.kingtronics.com/SMD_M7/M7_SMD_4007.pdf</description>
+</package3d>
+</packages3d>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="default *">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+The default Design Rules have been set to cover
+a wide range of applications. Your particular design
+may have different requirements, so please make the
+necessary adjustments and save your customized
+design rules under a new name.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>
+<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>
+<param name="mdWireWire" value="12mil"/>
+<param name="mdWirePad" value="12mil"/>
+<param name="mdWireVia" value="12mil"/>
+<param name="mdPadPad" value="12mil"/>
+<param name="mdPadVia" value="12mil"/>
+<param name="mdViaVia" value="12mil"/>
+<param name="mdSmdPad" value="6mil"/>
+<param name="mdSmdVia" value="6mil"/>
+<param name="mdSmdSmd" value="6mil"/>
+<param name="mdViaViaSameLayer" value="6mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="0mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="6mil"/>
+<param name="msDrill" value="0.35mm"/>
+<param name="msMicroVia" value="9.99mm"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="10mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="10mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="10mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="8mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="8mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="4mil"/>
+<param name="mlMaxStopFrame" value="4mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="40mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="checkStop" value="0"/>
+<param name="checkValues" value="0"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="9mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="2"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="*"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="*"/>
+<param name="cfVia" value="90"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+<param name="cfVia" value="8"/>
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfBonusStep" value="0"/>
+<param name="cfMalusStep" value="0"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+</pass>
+</autorouter>
+<elements>
+<element name="U$2" library="NPR_70" package="STM_NUCLEO32" value="NUCLEO_STM32L432KC" x="60.6425" y="27.305" smashed="yes" rot="R180"/>
+<element name="U$3" library="NPR_70" package="RF4463F30" value="" x="72.4375" y="27.175" smashed="yes" rot="R180"/>
+<element name="H2" library="NPR_70" package="3,6-PAD" value="MOUNT_HOLE" x="87.3125" y="63.5" smashed="yes"/>
+<element name="X1" library="NPR_70" package="BU-SMA-H" value="BU-SMA-H" x="69.5325" y="61.9125" smashed="yes" rot="R90">
+<attribute name="MF" value="" x="69.5325" y="61.9125" size="1.778" layer="27" rot="R90" display="off"/>
+<attribute name="MPN" value="" x="69.5325" y="61.9125" size="1.778" layer="27" rot="R90" display="off"/>
+<attribute name="NAME" x="65.0875" y="59.3725" size="1.27" layer="25" rot="R90"/>
+<attribute name="OC_FARNELL" value="unknown" x="69.5325" y="61.9125" size="1.778" layer="27" rot="R90" display="off"/>
+<attribute name="OC_NEWARK" value="unknown" x="69.5325" y="61.9125" size="1.778" layer="27" rot="R90" display="off"/>
+<attribute name="VALUE" x="75.2475" y="58.7375" size="1.27" layer="27" rot="R90"/>
+</element>
+<element name="U$4" library="NPR_70" package="VOLT_REGUL" value="VOLT_REGUL" x="13.335" y="30.48" smashed="yes"/>
+<element name="H1" library="NPR_70" package="3,6-PAD" value="MOUNT_HOLE" x="7.62" y="63.5" smashed="yes"/>
+<element name="H3" library="NPR_70" package="3,6-PAD" value="MOUNT_HOLE" x="7.62" y="4.445" smashed="yes"/>
+<element name="H4" library="NPR_70" package="3,6-PAD" value="MOUNT_HOLE" x="42.8625" y="32.385" smashed="yes"/>
+<element name="H5" library="NPR_70" package="3,6-PAD" value="MOUNT_HOLE" x="87.3125" y="4.445" smashed="yes"/>
+<element name="R1" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="49.2125" y="42.545" smashed="yes" rot="MR0">
+<attribute name="NAME" x="50.4825" y="43.815" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="50.4825" y="40.005" size="1.27" layer="28" rot="MR0"/>
+</element>
+<element name="R2" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="89.535" y="14.2875" smashed="yes" rot="MR90">
+<attribute name="NAME" x="90.805" y="16.51" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="86.995" y="13.0175" size="1.27" layer="28" rot="MR90"/>
+</element>
+<element name="R4" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="63.8175" y="42.545" smashed="yes" rot="MR270">
+<attribute name="NAME" x="62.865" y="46.0375" size="1.27" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="66.3575" y="43.815" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="R5" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="57.15" y="33.9725" smashed="yes" rot="MR270">
+<attribute name="NAME" x="56.1975" y="31.4325" size="1.27" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="59.69" y="35.2425" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="R6" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="60.96" y="36.195" smashed="yes" rot="MR270">
+<attribute name="NAME" x="59.69" y="33.9725" size="1.27" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="63.5" y="37.465" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="R7" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="64.4525" y="36.195" smashed="yes" rot="MR90">
+<attribute name="NAME" x="65.405" y="32.385" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="61.9125" y="34.925" size="1.27" layer="28" rot="MR90"/>
+</element>
+<element name="C2" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="30.1625" y="10.16" smashed="yes" rot="MR90">
+<attribute name="NAME" x="31.58" y="9.5125" size="1.016" layer="26" rot="MR90"/>
+<attribute name="VALUE" x="28.0625" y="8.56" size="1.016" layer="28" rot="MR90"/>
+</element>
+<element name="C3" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="58.42" y="42.545" smashed="yes" rot="MR0">
+<attribute name="NAME" x="59.385" y="43.9625" size="1.016" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="60.02" y="40.445" size="1.016" layer="28" rot="MR0"/>
+</element>
+<element name="C5" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="91.44" y="49.2125" smashed="yes" rot="MR270">
+<attribute name="NAME" x="89.705" y="49.5425" size="1.016" layer="26" rot="MR270"/>
+<attribute name="VALUE" x="93.54" y="50.8125" size="1.016" layer="28" rot="MR270"/>
+</element>
+<element name="R8" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="80.645" y="12.446" smashed="yes" rot="MR180">
+<attribute name="NAME" x="79.375" y="15.3035" size="1.27" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="79.375" y="14.986" size="1.27" layer="28" rot="MR180"/>
+</element>
+<element name="R9" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="80.645" y="3.556" smashed="yes" rot="MR180">
+<attribute name="NAME" x="78.4225" y="2.794" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="79.375" y="6.096" size="1.27" layer="28" rot="MR180"/>
+</element>
+<element name="R10" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="72.263" y="7.112" smashed="yes" rot="MR270">
+<attribute name="NAME" x="71.12" y="8.9535" size="1.27" layer="26" rot="MR270"/>
+<attribute name="VALUE" x="74.803" y="8.382" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="R11" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="75.565" y="11.43" smashed="yes" rot="MR180">
+<attribute name="NAME" x="75.565" y="13.6525" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="74.295" y="13.97" size="1.27" layer="28" rot="MR180"/>
+</element>
+<element name="UEXT" library="NPR_70" package="POWER_CABLES" value="POWER_CABLE" x="14.2875" y="54.61" smashed="yes" rot="R180">
+<attribute name="NAME" x="7.3025" y="55.245" size="1.27" layer="25" rot="R180"/>
+</element>
+<element name="C6" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="22.5425" y="61.595" smashed="yes" rot="MR180">
+<attribute name="NAME" x="19.855" y="62.2425" size="1.016" layer="26" rot="MR270"/>
+<attribute name="VALUE" x="20.9425" y="63.695" size="1.016" layer="28" rot="MR180"/>
+</element>
+<element name="C7" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="28.575" y="63.8175" smashed="yes" rot="MR270">
+<attribute name="NAME" x="29.9925" y="61.5825" size="1.016" layer="26" rot="MR90"/>
+<attribute name="VALUE" x="30.675" y="65.4175" size="1.016" layer="28" rot="MR270"/>
+</element>
+<element name="L4940_5V" library="NPR_70" package="TO220" value="REGUL" x="22.86" y="67.945" smashed="yes">
+<attribute name="NAME" x="17.78" y="61.8998" size="1.27" layer="25" ratio="10"/>
+</element>
+<element name="LM2937_3V3" library="NPR_70" package="TO220" value="REGUL" x="16.51" y="0" smashed="yes" rot="R180">
+<attribute name="NAME" x="21.59" y="6.0452" size="1.27" layer="25" ratio="10" rot="R180"/>
+</element>
+<element name="C8" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="15.24" y="6.35" smashed="yes" rot="MR180">
+<attribute name="NAME" x="15.8875" y="7.7675" size="1.016" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="13.64" y="8.45" size="1.016" layer="28" rot="MR180"/>
+</element>
+<element name="C9" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="22.5425" y="4.445" smashed="yes" rot="MR90">
+<attribute name="NAME" x="22.8725" y="7.1325" size="1.016" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="20.4425" y="2.845" size="1.016" layer="28" rot="MR90"/>
+</element>
+<element name="C1" library="NPR_70" package="CT3216" value="" x="11.7475" y="10.4775" smashed="yes" rot="MR0">
+<attribute name="NAME" x="11.7925" y="11.76" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="13.6975" y="7.5525" size="1.27" layer="28" rot="MR0"/>
+</element>
+<element name="C10" library="NPR_70" package="B/3528-21W" value="" x="26.67" y="4.1275" smashed="yes" rot="MR270">
+<attribute name="NAME" x="28.5875" y="1.86" size="1.27" layer="26" rot="MR90"/>
+<attribute name="VALUE" x="29.595" y="6.0775" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="C11" library="NPR_70" package="CT6032" value="" x="37.1475" y="62.23" smashed="yes" rot="MR270">
+<attribute name="NAME" x="39.065" y="60.915" size="1.27" layer="26" rot="MR90"/>
+<attribute name="VALUE" x="40.0725" y="64.18" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="C12" library="NPR_70" package="D/7343-31W" value="" x="29.5275" y="58.1025" smashed="yes" rot="MR0">
+<attribute name="NAME" x="28.75" y="55.325" size="1.27" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="36.3375" y="61.085" size="1.27" layer="28" rot="MR0"/>
+</element>
+<element name="C13" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="21.59" y="54.61" smashed="yes" rot="MR180">
+<attribute name="NAME" x="20.625" y="53.1925" size="1.016" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="19.99" y="56.71" size="1.016" layer="28" rot="MR180"/>
+</element>
+<element name="C14" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="14.9225" y="16.8275" smashed="yes" rot="MR0">
+<attribute name="NAME" x="16.205" y="18.245" size="1.016" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="16.5225" y="14.7275" size="1.016" layer="28" rot="MR0"/>
+</element>
+<element name="T1" library="transistor" library_urn="urn:adsk.eagle:library:402" package="SOT23" package3d_urn="urn:adsk.eagle:package:28738/2" value="BC847" x="68.2625" y="4.445" smashed="yes" rot="MR90">
+<attribute name="NAME" x="71.12" y="2.2225" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="67.6275" y="1.5875" size="1.27" layer="28" rot="MR0"/>
+</element>
+<element name="R12" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="62.865" y="5.08" smashed="yes" rot="MR270">
+<attribute name="NAME" x="61.595" y="6.35" size="1.27" layer="26" rot="MR270"/>
+<attribute name="VALUE" x="65.405" y="6.35" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="U$1" library="NPR_70" package="W5500LITE" value="W5500_LITEUSR-ES1" x="41.91" y="15.24" smashed="yes" rot="MR0"/>
+<element name="C15" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="86.36" y="13.0175" smashed="yes" rot="MR90">
+<attribute name="NAME" x="86.69" y="16.0225" size="1.016" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="84.26" y="11.4175" size="1.016" layer="28" rot="MR90"/>
+</element>
+<element name="LED1" library="mfj-236" package="LEDX2_V_K_A" value="Y-G" x="75.565" y="4.445" smashed="yes">
+<attribute name="NAME" x="73.152" y="9.652" size="1.27" layer="25"/>
+<attribute name="VALUE" x="76.8985" y="3.175" size="1.27" layer="27" rot="R180"/>
+</element>
+<element name="LED2" library="mfj-236" package="LEDX2_V_K_A" value="R-R" x="80.645" y="4.445" smashed="yes">
+<attribute name="NAME" x="78.359" y="9.652" size="1.27" layer="25"/>
+<attribute name="VALUE" x="82.296" y="3.2385" size="1.27" layer="27" rot="R180"/>
+</element>
+<element name="U$5" library="NPR_70" package="SO08" value="SRAM" x="33.9725" y="43.4975" rot="MR90"/>
+<element name="C16" library="resistor" library_urn="urn:adsk.eagle:library:348" package="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1" value="" x="33.3375" y="38.735" smashed="yes" rot="MR180">
+<attribute name="NAME" x="32.055" y="37.3175" size="1.016" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="31.7375" y="40.835" size="1.016" layer="28" rot="MR180"/>
+</element>
+<element name="SB2" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="16.1925" y="59.69" rot="MR270"/>
+<element name="SB1" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="18.7325" y="47.3075" smashed="yes" rot="MR0">
+<attribute name="NAME" x="17.4625" y="45.72" size="1.27" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="20.0025" y="44.7675" size="1.27" layer="28" rot="MR0"/>
+</element>
+<element name="SB4" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="42.8625" y="58.7375" smashed="yes" rot="MR270">
+<attribute name="NAME" x="44.1325" y="57.4675" size="1.27" layer="26" rot="MR90"/>
+<attribute name="VALUE" x="45.4025" y="60.0075" size="1.27" layer="28" rot="MR270"/>
+</element>
+<element name="SB3" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="32.7025" y="65.0875" smashed="yes" rot="MR0">
+<attribute name="NAME" x="31.4325" y="63.8175" size="1.016" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="33.9725" y="62.5475" size="1.27" layer="28" rot="MR0"/>
+</element>
+<element name="GPIO" library="con-harting" library_urn="urn:adsk.eagle:library:151" package="CON10" package3d_urn="urn:adsk.eagle:package:7121/1" value="" x="54.61" y="60.0075">
+<attribute name="MF" value="" x="54.61" y="60.0075" size="1.778" layer="27" display="off"/>
+<attribute name="MPN" value="" x="54.61" y="60.0075" size="1.778" layer="27" display="off"/>
+<attribute name="OC_FARNELL" value="unknown" x="54.61" y="60.0075" size="1.778" layer="27" display="off"/>
+<attribute name="OC_NEWARK" value="unknown" x="54.61" y="60.0075" size="1.778" layer="27" display="off"/>
+</element>
+<element name="D1" library="diode" library_urn="urn:adsk.eagle:library:210" package="DO-214AC" package3d_urn="urn:adsk.eagle:package:43416/2" value="" x="23.495" y="24.4475" smashed="yes" rot="MR0">
+<attribute name="NAME" x="24.13" y="26.3525" size="1.27" layer="26" rot="MR0"/>
+<attribute name="VALUE" x="26.035" y="21.2725" size="1.27" layer="28" rot="MR0"/>
+</element>
+<element name="R3" library="resistor" library_urn="urn:adsk.eagle:library:348" package="M0805" package3d_urn="urn:adsk.eagle:package:26079/1" value="" x="30.7975" y="34.29" smashed="yes" rot="MR0">
+<attribute name="NAME" x="29.845" y="33.02" size="1.27" layer="26" rot="MR180"/>
+<attribute name="VALUE" x="32.0675" y="31.75" size="1.27" layer="28" rot="MR0"/>
+</element>
+</elements>
+<signals>
+<signal name="CLK_SPI3">
+<contactref element="U$2" pad="16"/>
+<contactref element="U$1" pad="P$4"/>
+<contactref element="U$5" pad="6"/>
+<wire x1="45.085" y1="43.815" x2="46.6725" y2="43.815" width="0.4064" layer="16"/>
+<wire x1="45.085" y1="43.815" x2="38.4175" y2="43.815" width="0.4064" layer="16"/>
+<wire x1="38.4175" y1="43.815" x2="38.1" y2="44.1325" width="0.4064" layer="16"/>
+<wire x1="38.1" y1="44.1325" x2="37.0459" y2="44.1325" width="0.4064" layer="16"/>
+<wire x1="46.99" y1="16.51" x2="45.085" y2="16.51" width="0.4064" layer="16"/>
+<wire x1="45.085" y1="16.51" x2="38.1" y2="24.765" width="0.4064" layer="16"/>
+<wire x1="38.1" y1="24.765" x2="38.1" y2="34.925" width="0.4064" layer="16"/>
+<wire x1="38.1" y1="34.925" x2="45.4025" y2="40.9575" width="0.4064" layer="16"/>
+<via x="45.4025" y="40.9575" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="45.4025" y="44.1988" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="45.4025" y1="44.1988" x2="45.085" y2="43.815" width="0.4064" layer="16"/>
+<wire x1="45.4025" y1="40.9575" x2="45.4025" y2="44.1988" width="0.4064" layer="1"/>
+<wire x1="46.6725" y1="43.815" x2="46.99" y2="44.1325" width="0.4064" layer="16"/>
+<wire x1="52.07" y1="44.1325" x2="53.0225" y2="45.085" width="0.4064" layer="16"/>
+<wire x1="46.99" y1="44.1325" x2="52.07" y2="44.1325" width="0.4064" layer="16"/>
+</signal>
+<signal name="3V3">
+<contactref element="R1" pad="2"/>
+<contactref element="R2" pad="1"/>
+<contactref element="C2" pad="2"/>
+<contactref element="LM2937_3V3" pad="3"/>
+<contactref element="C8" pad="1"/>
+<contactref element="R8" pad="1"/>
+<wire x1="13.74" y1="6.35" x2="13.565" y2="4.215" width="1.27" layer="16"/>
+<wire x1="13.565" y1="4.215" x2="13.97" y2="2.54" width="1.27" layer="16"/>
+<wire x1="13.97" y1="2.54" x2="13.6525" y2="9.525" width="1.524" layer="16"/>
+<wire x1="13.6525" y1="9.525" x2="17.4625" y2="9.525" width="1.524" layer="16"/>
+<wire x1="17.4625" y1="9.525" x2="17.885834375" y2="8.89" width="1.524" layer="16"/>
+<wire x1="17.885834375" y1="8.89" x2="23.353890625" y2="8.89" width="1.524" layer="16"/>
+<wire x1="23.353890625" y1="8.89" x2="24.13" y2="11.15785625" width="1.524" layer="16"/>
+<contactref element="C1" pad="+"/>
+<wire x1="69.85" y1="12.3825" x2="69.85" y2="8.5725" width="0.4064" layer="16"/>
+<wire x1="79.6925" y1="14.2875" x2="78.105" y2="14.2875" width="0.6096" layer="16"/>
+<wire x1="78.105" y1="14.2875" x2="77.47" y2="14.9225" width="0.4064" layer="16"/>
+<wire x1="77.47" y1="14.9225" x2="72.39" y2="14.9225" width="0.4064" layer="16"/>
+<wire x1="79.692928125" y1="14.2875" x2="79.695" y2="12.446" width="0.8128" layer="16"/>
+<wire x1="89.535" y1="13.3375" x2="88.5825" y2="13.335" width="0.4064" layer="16"/>
+<contactref element="R9" pad="1"/>
+<wire x1="69.85" y1="8.5725" x2="69.215" y2="7.9375" width="0.4064" layer="16"/>
+<wire x1="72.39" y1="14.9225" x2="69.85" y2="12.3825" width="0.4064" layer="16"/>
+<wire x1="88.5825" y1="13.335" x2="87.63" y2="14.2875" width="0.4064" layer="16"/>
+<wire x1="86.765" y1="14.2875" x2="79.692928125" y2="14.2875" width="0.8128" layer="16"/>
+<wire x1="79.692928125" y1="14.2875" x2="79.6925" y2="14.2875" width="0.8128" layer="16"/>
+<wire x1="79.4385" y1="12.446" x2="79.695" y2="12.446" width="0.4064" layer="16"/>
+<contactref element="U$1" pad="P$10"/>
+<contactref element="U$1" pad="P$11"/>
+<wire x1="13.6525" y1="9.525" x2="13.6525" y2="9.88" width="1.27" layer="16"/>
+<wire x1="13.6525" y1="9.88" x2="13.465" y2="10.4775" width="1.524" layer="16"/>
+<contactref element="C15" pad="2"/>
+<wire x1="86.36" y1="14.5175" x2="86.765" y2="14.2875" width="0.4064" layer="16"/>
+<wire x1="86.765" y1="14.2875" x2="87.63" y2="14.2875" width="0.4064" layer="16"/>
+<wire x1="26.67" y1="13.97" x2="26.67" y2="11.43" width="1.27" layer="16"/>
+<wire x1="24.13" y1="11.15785625" x2="24.17535625" y2="11.43" width="1.27" layer="16"/>
+<wire x1="24.17535625" y1="11.43" x2="26.67" y2="11.43" width="1.524" layer="16"/>
+<wire x1="26.67" y1="11.43" x2="25.9475" y2="11.66" width="1.27" layer="16" curve="-90"/>
+<wire x1="25.9475" y1="11.66" x2="30.1625" y2="11.66" width="1.27" layer="16"/>
+<wire x1="23.495" y1="13.97" x2="23.495" y2="26.67" width="1.27" layer="16"/>
+<wire x1="23.495" y1="13.97" x2="24.17535625" y2="11.43" width="1.27" layer="16"/>
+<wire x1="79.695" y1="12.446" x2="79.695" y2="10.7925" width="0.4064" layer="16"/>
+<wire x1="79.695" y1="10.7925" x2="80.645" y2="9.8425" width="0.4064" layer="16"/>
+<wire x1="80.645" y1="9.8425" x2="80.645" y2="5.08" width="0.4064" layer="16"/>
+<wire x1="80.645" y1="5.08" x2="79.6925" y2="4.1275" width="0.4064" layer="16"/>
+<wire x1="79.6925" y1="4.1275" x2="79.6925" y2="3.5585" width="0.4064" layer="16"/>
+<wire x1="79.6925" y1="3.5585" x2="79.695" y2="3.556" width="0.4064" layer="16"/>
+<contactref element="U$5" pad="8"/>
+<contactref element="U$5" pad="7"/>
+<contactref element="C16" pad="2"/>
+<contactref element="GPIO" pad="8"/>
+<wire x1="48.2625" y1="42.545" x2="39.0525" y2="42.545" width="1.27" layer="16"/>
+<wire x1="34.8375" y1="38.735" x2="35.79" y2="40.6541" width="1.27" layer="16"/>
+<wire x1="35.79" y1="40.6541" x2="37.0459" y2="41.5925" width="1.27" layer="16"/>
+<wire x1="37.0459" y1="42.8625" x2="37.0459" y2="41.5925" width="0.6096" layer="16"/>
+<wire x1="23.495" y1="26.67" x2="30.6225" y2="26.67" width="1.27" layer="16"/>
+<wire x1="52.07" y1="7.9375" x2="49.8475" y2="10.16" width="0.508" layer="16"/>
+<wire x1="30.25" y1="11.7475" x2="30.1625" y2="11.66" width="0.4064" layer="16"/>
+<wire x1="69.215" y1="7.9375" x2="52.07" y2="7.9375" width="0.508" layer="16"/>
+<wire x1="39.0525" y1="42.545" x2="37.465" y2="42.2275" width="1.27" layer="16"/>
+<wire x1="37.465" y1="42.2275" x2="37.0459" y2="41.5925" width="1.27" layer="16"/>
+<wire x1="49.8475" y1="10.16" x2="42.545" y2="10.16" width="0.508" layer="16"/>
+<wire x1="42.545" y1="10.16" x2="34.6075" y2="20.32" width="0.6096" layer="16"/>
+<wire x1="23.495" y1="26.67" x2="23.495" y2="40.9575" width="0.6096" layer="16"/>
+<wire x1="23.495" y1="40.9575" x2="25.7175" y2="45.085" width="0.6096" layer="16"/>
+<wire x1="25.7175" y1="45.085" x2="31.75" y2="50.8" width="0.6096" layer="16"/>
+<wire x1="31.75" y1="50.8" x2="39.6875" y2="50.8" width="0.6096" layer="16"/>
+<wire x1="39.6875" y1="50.8" x2="46.0375" y2="56.8325" width="0.6096" layer="16"/>
+<wire x1="46.0375" y1="56.8325" x2="47.9425" y2="60.0075" width="0.6096" layer="16"/>
+<wire x1="47.9425" y1="60.0075" x2="56.1975" y2="60.0075" width="0.4064" layer="16"/>
+<wire x1="56.1975" y1="60.0075" x2="57.15" y2="61.2775" width="0.4064" layer="16"/>
+<wire x1="34.925" y1="38.965" x2="34.925" y2="37.7825" width="1.27" layer="16"/>
+<wire x1="34.925" y1="38.965" x2="34.8375" y2="38.735" width="1.27" layer="16"/>
+<wire x1="30.655" y1="26.67" x2="30.6225" y2="26.67" width="0.4064" layer="16"/>
+<wire x1="34.925" y1="37.7825" x2="34.6075" y2="36.195" width="1.27" layer="16"/>
+<wire x1="34.6075" y1="36.195" x2="34.6075" y2="34.29" width="1.27" layer="16"/>
+<wire x1="34.6075" y1="34.29" x2="34.6075" y2="26.67" width="1.27" layer="16"/>
+<wire x1="34.6075" y1="26.67" x2="30.6225" y2="26.67" width="1.27" layer="16"/>
+<wire x1="34.6075" y1="20.32" x2="34.6075" y2="26.67" width="0.6096" layer="16"/>
+<contactref element="R3" pad="1"/>
+<wire x1="31.7475" y1="34.29" x2="34.6075" y2="34.29" width="0.6096" layer="16"/>
+</signal>
+<signal name="RAND">
+<contactref element="U$2" pad="19"/>
+<contactref element="R7" pad="2"/>
+<contactref element="R6" pad="1"/>
+<wire x1="64.4525" y1="37.145" x2="60.96" y2="37.145" width="0.8128" layer="16"/>
+<wire x1="60.96" y1="37.145" x2="53.3425" y2="37.145" width="0.4064" layer="16"/>
+<wire x1="53.3425" y1="37.145" x2="53.0225" y2="37.465" width="0.4064" layer="16" curve="-90"/>
+</signal>
+<signal name="SDN_SI4463">
+<contactref element="U$2" pad="20"/>
+<contactref element="U$3" pad="5"/>
+<contactref element="R5" pad="2"/>
+<wire x1="53.0225" y1="34.925" x2="53.975" y2="34.925" width="0.6096" layer="16"/>
+<wire x1="53.975" y1="34.925" x2="56.1975" y2="33.02" width="0.6096" layer="16"/>
+<wire x1="56.1975" y1="33.02" x2="57.15" y2="33.0225" width="0.6096" layer="16"/>
+<wire x1="91.4375" y1="35.175" x2="91.4375" y2="34.61" width="0.4064" layer="1"/>
+<wire x1="91.4375" y1="34.61" x2="92.075" y2="33.3375" width="0.4064" layer="1"/>
+<via x="92.075" y="33.3375" extent="1-16" drill="0.5"/>
+<wire x1="88.9" y1="17.78" x2="75.565" y2="17.78" width="0.4064" layer="16"/>
+<wire x1="59.3725" y1="33.02" x2="65.405" y2="33.02" width="0.4064" layer="16"/>
+<wire x1="59.3725" y1="33.02" x2="57.15" y2="33.0225" width="0.4064" layer="16"/>
+<wire x1="74.295" y1="19.05" x2="74.295" y2="30.53329375" width="0.4064" layer="16"/>
+<wire x1="71.17329375" y1="33.655" x2="74.295" y2="30.53329375" width="0.4064" layer="16"/>
+<wire x1="65.405" y1="33.02" x2="66.04" y2="33.655" width="0.4064" layer="16"/>
+<wire x1="66.04" y1="33.655" x2="71.17329375" y2="33.655" width="0.4064" layer="16"/>
+<wire x1="75.565" y1="17.78" x2="74.295" y2="19.05" width="0.4064" layer="16"/>
+<wire x1="88.9" y1="17.78" x2="90.17" y2="19.05" width="0.4064" layer="16"/>
+<wire x1="89.8525" y1="26.9875" x2="90.805" y2="27.94" width="0.4064" layer="16"/>
+<wire x1="90.17" y1="19.05" x2="90.17" y2="23.8125" width="0.4064" layer="16"/>
+<wire x1="90.17" y1="23.8125" x2="89.8525" y2="24.13" width="0.4064" layer="16"/>
+<wire x1="89.8525" y1="24.13" x2="89.8525" y2="26.9875" width="0.4064" layer="16"/>
+<wire x1="90.805" y1="27.94" x2="90.805" y2="29.845" width="0.4064" layer="16"/>
+<wire x1="90.805" y1="29.845" x2="92.075" y2="31.115" width="0.4064" layer="16"/>
+<wire x1="92.075" y1="31.115" x2="92.075" y2="33.3375" width="0.4064" layer="16"/>
+</signal>
+<signal name="IT_SI4463">
+<contactref element="U$2" pad="21"/>
+<contactref element="U$3" pad="6"/>
+<wire x1="91.4375" y1="31.175" x2="91.4375" y2="30.165" width="0.4064" layer="1"/>
+<wire x1="91.4375" y1="30.165" x2="92.075" y2="29.5275" width="0.4064" layer="1"/>
+<via x="92.075" y="29.5275" extent="1-16" drill="0.5"/>
+<wire x1="92.075" y1="29.5275" x2="92.075" y2="27.6225" width="0.4064" layer="16"/>
+<wire x1="53.6575" y1="32.385" x2="55.245" y2="31.115" width="0.4064" layer="16"/>
+<wire x1="53.6575" y1="32.385" x2="53.0225" y2="32.385" width="0.4064" layer="16"/>
+<wire x1="73.3425" y1="30.1625" x2="73.3425" y2="18.415" width="0.4064" layer="16"/>
+<wire x1="71.755" y1="31.75" x2="73.3425" y2="30.1625" width="0.4064" layer="16"/>
+<wire x1="55.245" y1="31.115" x2="68.8975" y2="31.115" width="0.4064" layer="16"/>
+<wire x1="73.3425" y1="18.415" x2="74.93" y2="16.8275" width="0.4064" layer="16"/>
+<wire x1="89.535" y1="16.8275" x2="74.93" y2="16.8275" width="0.4064" layer="16"/>
+<wire x1="92.075" y1="27.6225" x2="90.805" y2="26.3525" width="0.4064" layer="16"/>
+<wire x1="90.805" y1="26.3525" x2="90.805" y2="24.765" width="0.4064" layer="16"/>
+<wire x1="90.805" y1="24.765" x2="91.1225" y2="24.4475" width="0.4064" layer="16"/>
+<wire x1="91.1225" y1="24.4475" x2="91.1225" y2="18.415" width="0.4064" layer="16"/>
+<wire x1="91.1225" y1="18.415" x2="89.535" y2="16.8275" width="0.4064" layer="16"/>
+<wire x1="68.8975" y1="31.115" x2="69.5325" y2="31.75" width="0.4064" layer="16"/>
+<wire x1="69.5325" y1="31.75" x2="71.755" y2="31.75" width="0.4064" layer="16"/>
+</signal>
+<signal name="CS_SI4463">
+<contactref element="U$2" pad="22"/>
+<contactref element="U$3" pad="7"/>
+<contactref element="R2" pad="2"/>
+<wire x1="89.535" y1="15.875" x2="90.17" y2="15.875" width="0.4064" layer="16"/>
+<via x="92.075" y="25.4" extent="1-16" drill="0.5"/>
+<wire x1="92.075" y1="25.4" x2="91.4375" y2="25.4" width="0.6096" layer="1"/>
+<wire x1="91.4375" y1="25.4" x2="91.4375" y2="27.175" width="0.6096" layer="1"/>
+<wire x1="89.535" y1="15.2375" x2="89.535" y2="15.875" width="0.508" layer="16"/>
+<wire x1="49.2125" y1="23.857853125" x2="52.308125" y2="20.955" width="0.4064" layer="16"/>
+<wire x1="57.15" y1="20.955" x2="52.308125" y2="20.955" width="0.4064" layer="16"/>
+<wire x1="89.535" y1="15.875" x2="72.0725" y2="15.875" width="0.4064" layer="16"/>
+<wire x1="72.0725" y1="15.875" x2="71.4375" y2="15.24" width="0.4064" layer="16"/>
+<wire x1="71.4375" y1="15.24" x2="70.1675" y2="15.24" width="0.4064" layer="16"/>
+<wire x1="70.1675" y1="15.24" x2="69.5325" y2="15.875" width="0.4064" layer="16"/>
+<wire x1="69.5325" y1="15.875" x2="64.4525" y2="15.875" width="0.4064" layer="16"/>
+<wire x1="53.0225" y1="29.845" x2="52.228746875" y2="29.845" width="0.4064" layer="16"/>
+<wire x1="90.17" y1="15.875" x2="92.075" y2="17.78" width="0.4064" layer="16"/>
+<wire x1="92.075" y1="17.78" x2="92.075" y2="25.4" width="0.4064" layer="16"/>
+<wire x1="64.4525" y1="15.875" x2="57.15" y2="20.955" width="0.4064" layer="16"/>
+<wire x1="49.2125" y1="26.67" x2="52.228746875" y2="29.845" width="0.4064" layer="16"/>
+<wire x1="49.2125" y1="23.857853125" x2="49.2125" y2="26.67" width="0.4064" layer="16"/>
+</signal>
+<signal name="MISO_SPI1">
+<contactref element="U$2" pad="24"/>
+<contactref element="U$3" pad="11"/>
+<wire x1="71.4375" y1="31.175" x2="70.8025" y2="30.54" width="0.4064" layer="1"/>
+<wire x1="70.8025" y1="30.54" x2="70.8025" y2="29.845" width="0.4064" layer="1"/>
+<via x="70.8025" y="29.845" extent="1-16" drill="0.5"/>
+<wire x1="52.3875" y1="28.575" x2="51.7525" y2="27.94" width="0.4064" layer="16"/>
+<wire x1="53.0225" y1="24.765" x2="51.7525" y2="26.035" width="0.4064" layer="16"/>
+<wire x1="51.7525" y1="26.035" x2="51.7525" y2="27.94" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="29.845" x2="69.5325" y2="28.575" width="0.4064" layer="16"/>
+<wire x1="69.5325" y1="28.575" x2="52.3875" y2="28.575" width="0.4064" layer="16"/>
+</signal>
+<signal name="MOSI_SPI1">
+<contactref element="U$2" pad="25"/>
+<contactref element="U$3" pad="10"/>
+<wire x1="71.4375" y1="26.44625" x2="71.12" y2="25.7175" width="0.4064" layer="1"/>
+<via x="71.12" y="25.7175" extent="1-16" drill="0.5"/>
+<wire x1="66.04" y1="18.415" x2="70.1675" y2="18.415" width="0.4064" layer="16"/>
+<wire x1="66.04" y1="18.415" x2="60.325" y2="22.225" width="0.4064" layer="16"/>
+<wire x1="60.325" y1="22.225" x2="53.0225" y2="22.225" width="0.4064" layer="16"/>
+<wire x1="70.1675" y1="18.415" x2="71.4375" y2="19.685" width="0.4064" layer="16"/>
+<wire x1="71.4375" y1="19.685" x2="71.4375" y2="25.4" width="0.4064" layer="16"/>
+<wire x1="71.4375" y1="25.4" x2="71.12" y2="25.7175" width="0.4064" layer="16"/>
+<wire x1="71.4375" y1="27.175" x2="71.4375" y2="26.44625" width="0.4064" layer="1"/>
+</signal>
+<signal name="GND">
+<contactref element="U$2" pad="29"/>
+<contactref element="U$2" pad="4"/>
+<contactref element="U$3" pad="2"/>
+<contactref element="U$3" pad="15"/>
+<contactref element="U$3" pad="8"/>
+<contactref element="X1" pad="5"/>
+<contactref element="X1" pad="3"/>
+<contactref element="X1" pad="4"/>
+<contactref element="X1" pad="2"/>
+<contactref element="H2" pad="B3,6"/>
+<contactref element="U$3" pad="SHLD_2"/>
+<contactref element="U$3" pad="SHLD_1"/>
+<contactref element="U$4" pad="IN-"/>
+<contactref element="U$4" pad="OUT-"/>
+<contactref element="H5" pad="B3,6"/>
+<contactref element="H4" pad="B3,6"/>
+<contactref element="H3" pad="B3,6"/>
+<contactref element="H1" pad="B3,6"/>
+<contactref element="R7" pad="1"/>
+<contactref element="C2" pad="1"/>
+<contactref element="C5" pad="2"/>
+<contactref element="UEXT" pad="P$2"/>
+<contactref element="C6" pad="2"/>
+<contactref element="C7" pad="2"/>
+<contactref element="C3" pad="1"/>
+<contactref element="L4940_5V" pad="2"/>
+<contactref element="LM2937_3V3" pad="2"/>
+<contactref element="C9" pad="2"/>
+<contactref element="C8" pad="2"/>
+<wire x1="72.0824" y1="59.3626" x2="71.755" y2="53.34" width="1.27" layer="1" curve="-0.198849"/>
+<wire x1="71.755" y1="53.34" x2="74.6125" y2="53.34" width="1.27" layer="1"/>
+<wire x1="74.6125" y1="53.34" x2="74.6125" y2="56.1975" width="1.27" layer="1"/>
+<wire x1="74.6125" y1="56.1975" x2="80.1025" y2="56.1975" width="1.27" layer="1"/>
+<wire x1="80.1025" y1="56.1975" x2="82.9375" y2="56.175" width="1.27" layer="1"/>
+<wire x1="82.9375" y1="56.175" x2="86.6775" y2="62.455" width="1.27" layer="1"/>
+<wire x1="86.6775" y1="62.455" x2="87.3125" y2="63.5" width="1.27" layer="1"/>
+<wire x1="71.4375" y1="47.175" x2="73.66" y2="47.175" width="1.27" layer="1"/>
+<wire x1="73.66" y1="47.175" x2="74.6125" y2="47.175" width="1.27" layer="1"/>
+<wire x1="74.6125" y1="47.175" x2="74.6125" y2="53.34" width="1.27" layer="1"/>
+<wire x1="71.4375" y1="47.175" x2="70.6175" y2="47.175" width="1.27" layer="1"/>
+<wire x1="70.6175" y1="47.175" x2="66.9925" y2="50.8" width="1.27" layer="1" curve="-90"/>
+<wire x1="66.9925" y1="50.8" x2="66.9925" y2="59.0352" width="1.27" layer="1"/>
+<wire x1="66.9925" y1="59.0352" x2="66.9826" y2="59.3626" width="1.27" layer="1" curve="90"/>
+<wire x1="82.9375" y1="56.175" x2="88.5825" y2="56.175" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="56.175" x2="88.5825" y2="46.99" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="46.99" x2="91.4375" y2="46.99" width="1.27" layer="1"/>
+<wire x1="91.4375" y1="46.99" x2="91.4375" y2="47.175" width="1.27" layer="1"/>
+<wire x1="91.4375" y1="47.175" x2="91.4375" y2="45.72" width="0.8128" layer="1"/>
+<wire x1="91.4375" y1="45.72" x2="91.44" y2="45.72" width="0.8128" layer="1"/>
+<via x="91.44" y="45.72" extent="1-16" drill="0.7"/>
+<wire x1="91.44" y1="45.72" x2="91.1225" y2="45.72" width="1.27" layer="16"/>
+<wire x1="88.5825" y1="46.99" x2="88.5825" y2="42.545" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="42.545" x2="88.5825" y2="39.0525" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="39.0525" x2="88.5825" y2="37.1475" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="37.1475" x2="88.5825" y2="28.8925" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="28.8925" x2="88.5825" y2="23.175" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="23.175" x2="91.4375" y2="23.175" width="1.27" layer="1"/>
+<wire x1="78.4375" y1="18.175" x2="88.5825" y2="18.175" width="1.27" layer="1"/>
+<wire x1="88.5825" y1="18.175" x2="88.5825" y2="23.175" width="1.27" layer="1"/>
+<wire x1="78.4375" y1="18.175" x2="80.9625" y2="18.175" width="0.4064" layer="1"/>
+<wire x1="88.5825" y1="18.175" x2="89.8525" y2="18.175" width="0.4064" layer="1"/>
+<wire x1="89.8525" y1="18.175" x2="88.37679375" y2="10.19805625" width="1.27" layer="1"/>
+<wire x1="88.37679375" y1="10.19805625" x2="87.3125" y2="4.445" width="1.27" layer="1"/>
+<wire x1="53.0225" y1="12.065" x2="61.2775" y2="12.065" width="0.8128" layer="1"/>
+<wire x1="61.2775" y1="12.065" x2="61.2775" y2="17.145" width="0.8128" layer="1"/>
+<wire x1="61.2775" y1="17.145" x2="68.2625" y2="17.145" width="0.8128" layer="1"/>
+<wire x1="61.2775" y1="17.145" x2="61.2775" y2="26.3525" width="0.4064" layer="1"/>
+<wire x1="61.2775" y1="26.3525" x2="61.2775" y2="32.385" width="0.4064" layer="1"/>
+<wire x1="61.2775" y1="32.385" x2="62.865" y2="34.29" width="0.4064" layer="1" curve="-90"/>
+<via x="62.865" y="34.29" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="62.865" y1="34.29" x2="64.4525" y2="34.29" width="0.8128" layer="16"/>
+<wire x1="64.4525" y1="34.29" x2="64.4525" y2="35.245" width="0.8128" layer="16"/>
+<wire x1="61.2775" y1="32.385" x2="61.2775" y2="33.655" width="0.4064" layer="1"/>
+<wire x1="46.99" y1="33.655" x2="42.8625" y2="32.385" width="0.4064" layer="1"/>
+<wire x1="61.2775" y1="33.655" x2="51.1175" y2="33.655" width="0.4064" layer="1"/>
+<via x="61.595" y="42.545" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="51.1175" y1="33.655" x2="46.99" y2="33.655" width="1.27" layer="1"/>
+<wire x1="61.595" y1="42.545" x2="62.865" y2="34.29" width="0.8128" layer="1"/>
+<wire x1="59.92" y1="42.545" x2="61.595" y2="42.545" width="1.27" layer="16"/>
+<wire x1="22.86" y1="60.96" x2="23.01875" y2="60.80125" width="0.4064" layer="1"/>
+<wire x1="23.01875" y1="60.80125" x2="23.1775" y2="60.6425" width="0.4064" layer="1"/>
+<wire x1="23.1775" y1="60.6425" x2="24.13" y2="61.2775" width="0.4064" layer="1"/>
+<wire x1="31.115" y1="61.2775" x2="24.13" y2="61.2775" width="0.4064" layer="1"/>
+<wire x1="24.13" y1="61.2775" x2="25.4" y2="53.0225" width="1.016" layer="1"/>
+<via x="25.4" y="53.0225" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="20.79625" y1="61.43625" x2="23.01875" y2="60.80125" width="0.8128" layer="1"/>
+<wire x1="11.1125" y1="54.61" x2="5.79" y2="54.9275" width="0.8128" layer="1"/>
+<wire x1="5.79" y1="54.9275" x2="4.835" y2="50.48" width="0.8128" layer="1" curve="90"/>
+<wire x1="42.8625" y1="32.385" x2="46.6725" y2="36.5125" width="1.27" layer="1"/>
+<wire x1="73.66" y1="20.955" x2="78.4225" y2="20.955" width="0.4064" layer="1"/>
+<wire x1="78.4225" y1="20.955" x2="78.4225" y2="20.6375" width="0.4064" layer="1"/>
+<wire x1="78.4225" y1="20.6375" x2="78.4225" y2="18.19" width="0.4064" layer="1"/>
+<wire x1="78.4225" y1="18.19" x2="78.4375" y2="18.175" width="0.4064" layer="1"/>
+<wire x1="24.13" y1="62" x2="22.86" y2="65.405" width="1.27" layer="16"/>
+<wire x1="73.66" y1="47.175" x2="73.66" y2="45.4025" width="0.4064" layer="1"/>
+<via x="70.485" y="49.2125" extent="1-16" drill="0.5"/>
+<via x="67.945" y="50.8" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="67.31" y="56.1975" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="71.755" y="53.34" extent="1-16" drill="0.5"/>
+<via x="73.9775" y="53.0225" extent="1-16" drill="0.5"/>
+<via x="71.755" y="56.1975" extent="1-16" drill="0.5"/>
+<via x="73.3425" y="49.2125" extent="1-16" drill="0.5"/>
+<wire x1="73.66" y1="45.4025" x2="73.66" y2="37.1475" width="0.4064" layer="1"/>
+<wire x1="73.66" y1="37.1475" x2="73.66" y2="27.94" width="0.4064" layer="1"/>
+<wire x1="73.66" y1="27.94" x2="73.66" y2="20.955" width="0.4064" layer="1"/>
+<wire x1="72.0824" y1="59.3626" x2="72.0725" y2="59.0451" width="0.8128" layer="16"/>
+<wire x1="72.0725" y1="59.0451" x2="71.755" y2="56.1975" width="1.27" layer="16"/>
+<wire x1="71.755" y1="56.1975" x2="71.755" y2="53.34" width="0.8128" layer="16"/>
+<wire x1="71.755" y1="53.34" x2="73.9775" y2="53.0225" width="0.8128" layer="16"/>
+<via x="74.295" y="51.1175" extent="1-16" drill="0.5"/>
+<wire x1="73.9775" y1="53.0225" x2="74.295" y2="51.1175" width="0.8128" layer="16"/>
+<wire x1="74.295" y1="51.1175" x2="74.295" y2="49.53" width="0.8128" layer="16"/>
+<wire x1="74.295" y1="49.53" x2="73.3425" y2="49.2125" width="0.8128" layer="16" curve="-90"/>
+<wire x1="72.39" y1="49.2125" x2="70.485" y2="49.2125" width="0.8128" layer="16"/>
+<wire x1="70.485" y1="49.2125" x2="67.945" y2="50.8" width="0.8128" layer="16" curve="-90"/>
+<wire x1="67.945" y1="50.8" x2="67.31" y2="53.6575" width="0.8128" layer="16"/>
+<wire x1="67.31" y1="53.6575" x2="67.31" y2="56.1975" width="0.8128" layer="16"/>
+<wire x1="67.31" y1="56.1975" x2="66.9826" y2="59.3626" width="1.27" layer="16" curve="7.389452"/>
+<via x="80.3275" y="64.135" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="88.5825" y="56.1975" extent="1-16" drill="0.5"/>
+<wire x1="80.3275" y1="64.135" x2="87.3125" y2="63.5" width="1.27" layer="1"/>
+<wire x1="80.3275" y1="64.135" x2="80.3275" y2="60.96" width="0.8128" layer="16"/>
+<wire x1="80.3275" y1="60.96" x2="84.7725" y2="56.1975" width="0.8128" layer="16"/>
+<wire x1="84.7725" y1="56.1975" x2="88.5825" y2="56.1975" width="0.8128" layer="16"/>
+<wire x1="88.5825" y1="56.1975" x2="88.5825" y2="48.5775" width="0.8128" layer="16"/>
+<wire x1="88.5825" y1="48.5775" x2="91.44" y2="45.72" width="0.8128" layer="16"/>
+<via x="77.1525" y="20.32" extent="1-16" drill="0.5"/>
+<via x="88.5825" y="19.685" extent="1-16" drill="0.5"/>
+<wire x1="77.1525" y1="20.32" x2="78.105" y2="20.32" width="0.8128" layer="1"/>
+<wire x1="78.105" y1="20.32" x2="78.4225" y2="20.6375" width="0.8128" layer="1"/>
+<wire x1="88.5825" y1="19.685" x2="87.63" y2="19.1275" width="0.8128" layer="1"/>
+<wire x1="87.63" y1="19.1275" x2="88.5825" y2="18.175" width="0.8128" layer="1"/>
+<wire x1="77.1525" y1="20.32" x2="77.1525" y2="20.955" width="0.8128" layer="16"/>
+<wire x1="77.1525" y1="20.955" x2="76.5175" y2="21.59" width="0.8128" layer="16"/>
+<wire x1="76.5175" y1="21.59" x2="76.5175" y2="27.94" width="0.8128" layer="16"/>
+<wire x1="72.39" y1="40.64" x2="72.39" y2="45.4025" width="0.8128" layer="16"/>
+<wire x1="72.39" y1="45.4025" x2="72.39" y2="49.2125" width="0.8128" layer="16"/>
+<wire x1="72.39" y1="49.2125" x2="73.3425" y2="49.2125" width="0.8128" layer="16"/>
+<wire x1="77.1525" y1="20.32" x2="77.7875" y2="19.685" width="0.8128" layer="16"/>
+<wire x1="77.7875" y1="19.685" x2="82.55" y2="19.685" width="0.8128" layer="16"/>
+<wire x1="82.55" y1="19.685" x2="88.5825" y2="19.685" width="0.8128" layer="16"/>
+<wire x1="91.148646875" y1="35.5375875" x2="91.44" y2="35.8775" width="0.8128" layer="16"/>
+<wire x1="91.44" y1="35.8775" x2="93.0275" y2="37.1475" width="0.8128" layer="16"/>
+<wire x1="93.0275" y1="37.1475" x2="91.44" y2="45.72" width="0.8128" layer="16"/>
+<via x="93.0275" y="37.1475" extent="1-16" drill="0.5"/>
+<wire x1="88.5825" y1="37.1475" x2="93.0275" y2="37.1475" width="0.1524" layer="1"/>
+<via x="72.7075" y="37.1475" extent="1-16" drill="0.5"/>
+<wire x1="72.7075" y1="37.1475" x2="73.66" y2="37.1475" width="0.1524" layer="1"/>
+<wire x1="73.3425" y1="49.2125" x2="73.66" y2="47.175" width="0.1524" layer="1"/>
+<wire x1="70.485" y1="49.2125" x2="70.6175" y2="47.175" width="0.1524" layer="1"/>
+<via x="80.9625" y="58.1025" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="80.9625" y1="58.1025" x2="81.01" y2="58.1025" width="0.8128" layer="1"/>
+<wire x1="81.01" y1="58.1025" x2="82.9375" y2="56.175" width="0.8128" layer="1"/>
+<wire x1="80.9625" y1="58.1025" x2="80.3275" y2="60.96" width="0.8128" layer="16"/>
+<via x="88.9" y="28.8925" extent="1-16" drill="0.5"/>
+<via x="76.5175" y="27.94" extent="1-16" drill="0.5"/>
+<wire x1="76.5175" y1="27.94" x2="73.66" y2="27.94" width="0.4064" layer="1"/>
+<polygon width="0.3048" layer="1" isolate="0.4064">
+<vertex x="0" y="66.9925"/>
+<vertex x="95.5675" y="66.9925"/>
+<vertex x="95.5675" y="1.27"/>
+<vertex x="0" y="1.27"/>
+</polygon>
+<via x="67.31" y="53.6575" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<polygon width="0.2032" layer="16" isolate="0.4064">
+<vertex x="57.785" y="48.26"/>
+<vertex x="57.785" y="57.4675"/>
+<vertex x="58.1025" y="57.4675"/>
+<vertex x="58.1025" y="62.5475"/>
+<vertex x="55.245" y="62.5475"/>
+<vertex x="55.245" y="60.325"/>
+<vertex x="45.4025" y="60.325"/>
+<vertex x="45.4025" y="65.0875"/>
+<vertex x="81.28" y="65.0875"/>
+<vertex x="81.28" y="60.96"/>
+<vertex x="84.455" y="56.8325"/>
+<vertex x="89.535" y="56.8325"/>
+<vertex x="89.535" y="52.3875"/>
+<vertex x="89.2175" y="52.3875"/>
+<vertex x="89.2175" y="48.26"/>
+<vertex x="93.98" y="48.26"/>
+<vertex x="93.98" y="35.56"/>
+<vertex x="92.3925" y="35.56"/>
+<vertex x="90.805" y="33.655"/>
+<vertex x="90.805" y="31.75"/>
+<vertex x="89.8525" y="31.4325"/>
+<vertex x="89.8525" y="28.575"/>
+<vertex x="88.9" y="27.6225"/>
+<vertex x="88.9" y="24.13"/>
+<vertex x="89.2175" y="23.1775"/>
+<vertex x="89.2175" y="19.685"/>
+<vertex x="88.265" y="18.7325"/>
+<vertex x="76.835" y="18.7325"/>
+<vertex x="76.835" y="20.6375"/>
+<vertex x="75.8825" y="21.59"/>
+<vertex x="75.8825" y="32.385"/>
+<vertex x="72.0725" y="34.6075"/>
+<vertex x="72.39" y="36.5125"/>
+<vertex x="71.755" y="38.735"/>
+<vertex x="71.755" y="47.9425"/>
+<vertex x="68.8975" y="48.26"/>
+</polygon>
+<wire x1="66.9826" y1="59.3626" x2="66.9826" y2="64.4624" width="1.016" layer="16"/>
+<wire x1="72.0824" y1="59.3626" x2="66.9826" y2="59.3626" width="1.27" layer="16"/>
+<wire x1="72.0824" y1="59.3626" x2="75.565" y2="59.0451" width="1.016" layer="16"/>
+<wire x1="75.565" y1="59.0451" x2="80.9625" y2="59.0451" width="1.016" layer="16"/>
+<wire x1="80.9625" y1="59.0451" x2="80.9625" y2="58.1025" width="1.016" layer="16"/>
+<wire x1="88.9" y1="28.8925" x2="88.5825" y2="28.8925" width="0.2032" layer="1"/>
+<via x="61.2775" y="55.88" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="46.0375" y="62.23" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="46.0375" y1="62.23" x2="49.8475" y2="63.1825" width="0.6096" layer="16"/>
+<wire x1="49.8475" y1="63.1825" x2="66.3575" y2="63.1825" width="0.6096" layer="16"/>
+<wire x1="66.3575" y1="63.1825" x2="66.9826" y2="64.4426" width="1.016" layer="16"/>
+<wire x1="66.9826" y1="64.4426" x2="66.9826" y2="64.4624" width="1.016" layer="16"/>
+<wire x1="61.2775" y1="55.88" x2="67.6275" y2="51.949046875" width="1.016" layer="16"/>
+<wire x1="67.6275" y1="51.949046875" x2="67.6275" y2="51.1175" width="1.016" layer="16"/>
+<wire x1="7.62" y1="4.445" x2="7.3025" y2="4.445" width="1.27" layer="1"/>
+<wire x1="7.3025" y1="4.445" x2="10.16" y2="7.3025" width="1.27" layer="1"/>
+<wire x1="46.0375" y1="62.23" x2="46.99" y2="63.5" width="1.27" layer="1"/>
+<wire x1="46.99" y1="63.5" x2="44.1325" y2="63.5" width="1.27" layer="1"/>
+<wire x1="44.1325" y1="63.5" x2="42.83266875" y2="62.59011875" width="1.27" layer="1"/>
+<wire x1="42.83266875" y1="62.59011875" x2="40.9575" y2="61.2775" width="1.27" layer="1"/>
+<wire x1="61.2775" y1="55.88" x2="60.6425" y2="53.6575" width="0.4064" layer="1"/>
+<wire x1="60.6425" y1="53.6575" x2="67.31" y2="53.6575" width="0.4064" layer="1"/>
+<wire x1="16.51" y1="2.54" x2="16.51" y2="5.715" width="1.27" layer="16"/>
+<wire x1="16.51" y1="5.715" x2="16.74" y2="5.945" width="1.27" layer="16"/>
+<wire x1="17.0575" y1="5.945" x2="22.5425" y2="5.945" width="1.27" layer="16"/>
+<wire x1="16.51" y1="7.3025" x2="16.51" y2="4.1275" width="1.27" layer="1"/>
+<wire x1="16.51" y1="4.1275" x2="16.51" y2="2.54" width="1.27" layer="1"/>
+<wire x1="11.90625" y1="61.43625" x2="20.79625" y2="61.43625" width="0.254" layer="1"/>
+<wire x1="7.62" y1="63.5" x2="3.2475" y2="59.1275" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="59.1275" x2="3.2475" y2="58.42" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="58.42" x2="3.2475" y2="54.9275" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="54.9275" x2="4.835" y2="50.48" width="1.27" layer="16"/>
+<wire x1="4.835" y1="50.48" x2="3.2475" y2="40.005" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="40.005" x2="3.2475" y2="35.8775" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="35.8775" x2="3.2475" y2="32.0675" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="32.0675" x2="3.2475" y2="26.9875" width="1.27" layer="16"/>
+<via x="4.1275" y="32.0675" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="3.2475" y1="26.9875" x2="3.2475" y2="22.5425" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="22.5425" x2="3.2475" y2="20.32" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="20.32" x2="4.835" y2="10.98" width="1.27" layer="16"/>
+<wire x1="4.1275" y1="32.0675" x2="3.2475" y2="32.0675" width="1.27" layer="16"/>
+<wire x1="4.835" y1="50.48" x2="3.2475" y2="32.0675" width="1.27" layer="1"/>
+<wire x1="3.2475" y1="32.0675" x2="3.2475" y2="21.9075" width="1.27" layer="1"/>
+<wire x1="3.2475" y1="21.9075" x2="4.835" y2="10.98" width="1.27" layer="1"/>
+<wire x1="4.1275" y1="32.0675" x2="3.2475" y2="32.0675" width="1.27" layer="1"/>
+<contactref element="C12" pad="-"/>
+<contactref element="C11" pad="-"/>
+<contactref element="C10" pad="-"/>
+<contactref element="C1" pad="-"/>
+<wire x1="10.3475" y1="10.4775" x2="9.0075" y2="20.32" width="1.27" layer="16"/>
+<wire x1="9.0075" y1="20.32" x2="5.3975" y2="20.32" width="1.27" layer="16"/>
+<wire x1="5.3975" y1="20.32" x2="3.2475" y2="20.32" width="1.27" layer="16"/>
+<wire x1="13.0175" y1="20.52" x2="10.3475" y2="10.4775" width="1.27" layer="16"/>
+<via x="13.0175" y="21.9075" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="13.0175" y1="21.9075" x2="13.0175" y2="20.52" width="1.27" layer="16"/>
+<wire x1="13.0175" y1="21.9075" x2="3.2475" y2="21.9075" width="1.27" layer="1"/>
+<via x="30.1625" y="6.0325" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="28.497375" y1="6.110125" x2="26.67" y2="5.7525" width="1.27" layer="16"/>
+<via x="36.83" y="56.515" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="36.83" y1="56.515" x2="25.4" y2="53.0225" width="1.27" layer="1"/>
+<wire x1="36.83" y1="56.515" x2="34.6075" y2="57.4675" width="1.27" layer="16"/>
+<wire x1="34.6075" y1="57.4675" x2="32.7025" y2="58.19" width="1.27" layer="16"/>
+<wire x1="11.1125" y1="54.61" x2="6.35" y2="54.9275" width="1.27" layer="16"/>
+<wire x1="6.35" y1="54.9275" x2="3.2475" y2="54.9275" width="1.27" layer="16"/>
+<wire x1="6.35" y1="58.42" x2="3.2475" y2="58.42" width="1.27" layer="16"/>
+<wire x1="6.413321875" y1="50.47888125" x2="6.35" y2="54.9275" width="1.27" layer="16"/>
+<wire x1="4.835" y1="50.48" x2="6.413321875" y2="50.47888125" width="1.27" layer="16"/>
+<wire x1="4.835" y1="10.98" x2="5.563475" y2="7.518615625" width="1.27" layer="16"/>
+<wire x1="5.563475" y1="7.518615625" x2="7.62" y2="4.445" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="22.5425" x2="3.8825" y2="21.9075" width="1.27" layer="16" curve="90"/>
+<wire x1="3.8825" y1="21.9075" x2="6.35" y2="21.9075" width="1.27" layer="16"/>
+<wire x1="6.35" y1="21.9075" x2="13.0175" y2="21.9075" width="1.27" layer="16"/>
+<wire x1="6.35" y1="46.555" x2="6.35" y2="40.005" width="1.27" layer="16"/>
+<wire x1="6.35" y1="40.005" x2="6.35" y2="35.8775" width="1.27" layer="16"/>
+<wire x1="6.35" y1="35.8775" x2="6.35" y2="32.0675" width="1.27" layer="16"/>
+<wire x1="6.35" y1="32.0675" x2="6.35" y2="26.9875" width="1.27" layer="16"/>
+<wire x1="6.35" y1="26.9875" x2="6.35" y2="21.9075" width="1.27" layer="16"/>
+<wire x1="4.1275" y1="32.0675" x2="6.35" y2="32.0675" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="40.005" x2="6.35" y2="40.005" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="26.9875" x2="6.35" y2="26.9875" width="1.27" layer="16"/>
+<wire x1="3.2475" y1="35.8775" x2="6.35" y2="35.8775" width="1.27" layer="16"/>
+<wire x1="5.3975" y1="20.32" x2="6.35" y2="20.6375" width="1.27" layer="16" curve="90"/>
+<wire x1="6.35" y1="20.6375" x2="6.35" y2="21.9075" width="1.27" layer="16"/>
+<contactref element="U$2" pad="SHLD"/>
+<wire x1="57.4675" y1="52.705" x2="58.42" y2="51.7525" width="1.27" layer="16" curve="90"/>
+<wire x1="58.42" y1="51.7525" x2="61.2775" y2="55.88" width="1.27" layer="16"/>
+<wire x1="57.4675" y1="52.705" x2="58.42" y2="51.7525" width="1.27" layer="1" curve="90"/>
+<wire x1="58.42" y1="51.7525" x2="61.2775" y2="55.88" width="1.27" layer="1"/>
+<wire x1="5.3975" y1="20.32" x2="5.3975" y2="7.987640625" width="2.54" layer="16"/>
+<wire x1="5.3975" y1="7.987640625" x2="5.563475" y2="7.518615625" width="1.27" layer="16"/>
+<wire x1="6.35" y1="54.9275" x2="6.35" y2="58.42" width="1.27" layer="16"/>
+<wire x1="16.74" y1="5.945" x2="17.0575" y2="5.945" width="1.27" layer="16"/>
+<wire x1="17.0575" y1="5.945" x2="16.74" y2="6.35" width="1.27" layer="16"/>
+<wire x1="7.62" y1="4.445" x2="4.878321875" y2="8.542625" width="1.27" layer="1"/>
+<wire x1="4.878321875" y1="8.542625" x2="4.835" y2="10.98" width="1.27" layer="1"/>
+<wire x1="66.9826" y1="59.3626" x2="66.9826" y2="64.4624" width="1.27" layer="1"/>
+<wire x1="72.0824" y1="64.4624" x2="72.0824" y2="61.595" width="1.27" layer="1"/>
+<wire x1="72.0824" y1="61.595" x2="72.0824" y2="59.3626" width="1.27" layer="1"/>
+<wire x1="80.3275" y1="64.135" x2="72.0824" y2="64.4624" width="1.27" layer="1"/>
+<wire x1="66.9826" y1="64.4624" x2="60.0075" y2="64.1449" width="1.27" layer="1"/>
+<wire x1="60.0075" y1="64.1449" x2="60.0075" y2="63.5" width="1.27" layer="1"/>
+<via x="58.42" y="48.895" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="72.39" y="45.4025" extent="1-16" drill="0.5"/>
+<wire x1="72.39" y1="45.4025" x2="73.66" y2="45.4025" width="0.4064" layer="1"/>
+<via x="76.5175" y="61.595" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="76.5175" y1="61.595" x2="75.565" y2="59.0451" width="0.4064" layer="16"/>
+<wire x1="76.5175" y1="61.595" x2="72.0824" y2="61.595" width="0.4064" layer="1"/>
+<via x="63.5" y="48.895" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="72.0824" y1="64.4624" x2="72.0824" y2="59.3626" width="1.27" layer="16"/>
+<via x="46.99" y="2.2225" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="49.8475" y1="30.1625" x2="51.7525" y2="26.035" width="0.4064" layer="1"/>
+<wire x1="49.8475" y1="30.1625" x2="42.8625" y2="32.385" width="1.27" layer="1"/>
+<wire x1="7.62" y1="63.5" x2="11.7475" y2="63.5" width="1.27" layer="1"/>
+<polygon width="0.4064" layer="16">
+<vertex x="15.24" y="67.31"/>
+<vertex x="0" y="67.31"/>
+<vertex x="0" y="0.9525"/>
+<vertex x="11.7475" y="0.9525"/>
+<vertex x="11.7475" y="6.0325"/>
+<vertex x="10.795" y="9.525"/>
+<vertex x="10.795" y="12.7"/>
+<vertex x="14.2875" y="15.24"/>
+<vertex x="14.2875" y="39.0525"/>
+<vertex x="10.4775" y="42.8625"/>
+<vertex x="10.4775" y="51.1175"/>
+<vertex x="11.43" y="52.3875"/>
+<vertex x="11.43" y="58.1025"/>
+<vertex x="15.24" y="61.595"/>
+</polygon>
+<polygon width="0.4064" layer="16" isolate="0.6096">
+<vertex x="95.5675" y="17.78"/>
+<vertex x="89.8525" y="14.605"/>
+<vertex x="89.8525" y="11.7475"/>
+<vertex x="85.4075" y="11.7475"/>
+<vertex x="85.4075" y="12.3825"/>
+<vertex x="83.5025" y="13.0175"/>
+<vertex x="83.5025" y="0.635"/>
+<vertex x="95.5675" y="0.635"/>
+</polygon>
+<via x="92.075" y="1.905" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="84.1375" y="12.065" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="46.99" y1="2.2225" x2="47.8155" y2="1.397" width="1.27" layer="16"/>
+<wire x1="84.2645" y1="1.397" x2="87.3125" y2="4.445" width="1.27" layer="16"/>
+<wire x1="47.8155" y1="1.397" x2="84.2645" y2="1.397" width="1.27" layer="16"/>
+<wire x1="7.62" y1="63.5" x2="7.62" y2="59.055" width="1.27" layer="1"/>
+<wire x1="7.62" y1="59.055" x2="11.1125" y2="54.61" width="1.27" layer="1"/>
+<wire x1="7.62" y1="4.445" x2="11.43" y2="4.445" width="1.27" layer="1"/>
+<wire x1="11.43" y1="4.445" x2="12.3825" y2="5.3975" width="1.27" layer="1"/>
+<wire x1="12.3825" y1="5.3975" x2="15.24" y2="5.3975" width="1.27" layer="1"/>
+<wire x1="15.24" y1="5.3975" x2="16.51" y2="4.1275" width="1.27" layer="1"/>
+<wire x1="87.3125" y1="4.445" x2="92.075" y2="4.445" width="1.27" layer="1"/>
+<wire x1="92.075" y1="4.445" x2="92.075" y2="1.905" width="1.27" layer="1"/>
+<wire x1="84.1375" y1="12.065" x2="84.1375" y2="7.3025" width="1.27" layer="1"/>
+<wire x1="84.1375" y1="7.3025" x2="86.995" y2="4.445" width="1.27" layer="1"/>
+<wire x1="86.995" y1="4.445" x2="87.3125" y2="4.445" width="1.27" layer="1"/>
+<contactref element="U$3" pad="SHLD_3"/>
+<contactref element="U$3" pad="SHLD_4"/>
+<wire x1="66.9826" y1="64.4624" x2="72.0824" y2="64.4624" width="1.27" layer="16"/>
+<contactref element="C13" pad="2"/>
+<contactref element="C14" pad="2"/>
+<wire x1="13.4225" y1="16.8275" x2="13.0175" y2="17.8675" width="1.27" layer="16" curve="-90"/>
+<wire x1="13.0175" y1="17.8675" x2="13.0175" y2="21.9075" width="1.27" layer="16"/>
+<contactref element="T1" pad="2"/>
+<via x="82.55" y="19.685" extent="1-16" drill="0.5"/>
+<polygon width="0.1524" layer="16">
+<vertex x="95.5675" y="66.675"/>
+<vertex x="84.1375" y="66.675"/>
+<vertex x="84.1375" y="62.5475"/>
+<vertex x="86.36" y="60.0075"/>
+<vertex x="91.1225" y="60.0075"/>
+<vertex x="93.6625" y="56.8325"/>
+<vertex x="93.6625" y="13.0175"/>
+<vertex x="95.5675" y="13.0175"/>
+</polygon>
+<via x="93.345" y="66.04" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<polygon width="0.4064" layer="16" isolate="0.6096">
+<vertex x="62.5475" y="1.27"/>
+<vertex x="46.0375" y="1.27"/>
+<vertex x="45.085" y="2.2225"/>
+<vertex x="44.45" y="2.2225"/>
+<vertex x="44.45" y="9.2075"/>
+<vertex x="48.598665625" y="9.2075"/>
+<vertex x="52.9209" y="5.6515"/>
+<vertex x="62.5475" y="4.1275"/>
+</polygon>
+<polygon width="0.4064" layer="16" isolate="0.6096">
+<vertex x="29.21" y="9.525"/>
+<vertex x="28.2575" y="10.16"/>
+<vertex x="25.0825" y="10.16"/>
+<vertex x="25.0825" y="9.8425"/>
+<vertex x="22.86" y="9.525"/>
+<vertex x="22.86" y="7.9375"/>
+<vertex x="15.5575" y="7.9375"/>
+<vertex x="15.5575" y="4.7625"/>
+<vertex x="30.7975" y="4.7625"/>
+<vertex x="31.115" y="5.08"/>
+<vertex x="31.194375" y="6.0325"/>
+<vertex x="30.7975" y="6.6675"/>
+</polygon>
+<polygon width="0.4064" layer="16" isolate="0.6096">
+<vertex x="37.7825" y="62.23"/>
+<vertex x="24.13" y="62.23"/>
+<vertex x="24.13" y="67.31"/>
+<vertex x="22.86" y="67.31"/>
+<vertex x="22.5425" y="51.7525"/>
+<vertex x="26.67" y="51.7525"/>
+<vertex x="29.845" y="54.2925"/>
+<vertex x="37.7825" y="55.5625"/>
+</polygon>
+<polygon width="0.1524" layer="16">
+<vertex x="62.865" y="43.815"/>
+<vertex x="58.1025" y="43.815"/>
+<vertex x="58.1025" y="40.64"/>
+<vertex x="62.865" y="40.64"/>
+</polygon>
+<wire x1="40.9575" y1="61.2775" x2="31.115" y2="61.2775" width="1.27" layer="1"/>
+<contactref element="U$1" pad="P$1"/>
+<contactref element="U$1" pad="P$2"/>
+<wire x1="10.16" y1="7.3025" x2="16.51" y2="7.3025" width="1.27" layer="1"/>
+<wire x1="30.7975" y1="7.9375" x2="46.99" y2="8.89" width="1.27" layer="1"/>
+<wire x1="30.1625" y1="6.0325" x2="28.497375" y2="6.110125" width="1.27" layer="16"/>
+<wire x1="22.5425" y1="5.945" x2="28.6625" y2="5.945" width="1.27" layer="16"/>
+<wire x1="28.6625" y1="5.945" x2="29.05125" y2="5.55625" width="1.27" layer="16"/>
+<wire x1="29.05125" y1="5.55625" x2="29.41" y2="5.915" width="1.27" layer="16"/>
+<wire x1="58.42" y1="48.895" x2="58.42" y2="51.7525" width="0.8128" layer="16"/>
+<wire x1="58.42" y1="51.7525" x2="57.4675" y2="52.705" width="0.8128" layer="16"/>
+<wire x1="67.945" y1="50.8" x2="65.405" y2="50.8" width="0.8128" layer="16"/>
+<wire x1="65.405" y1="50.8" x2="63.5" y2="48.895" width="0.8128" layer="16"/>
+<wire x1="46.99" y1="63.5" x2="60.0075" y2="63.5" width="0.8128" layer="1"/>
+<wire x1="93.345" y1="66.04" x2="89.535" y2="63.5" width="0.8128" layer="1"/>
+<wire x1="89.535" y1="63.5" x2="87.3125" y2="63.5" width="0.8128" layer="1"/>
+<wire x1="86.6875" y1="39.175" x2="86.6875" y2="42.675" width="0.8128" layer="1"/>
+<wire x1="86.6875" y1="42.675" x2="86.8175" y2="42.545" width="0.8128" layer="1"/>
+<wire x1="86.8175" y1="42.545" x2="88.5825" y2="42.545" width="0.8128" layer="1"/>
+<wire x1="86.6875" y1="39.175" x2="86.81" y2="39.0525" width="0.8128" layer="1"/>
+<wire x1="86.81" y1="39.0525" x2="88.5825" y2="39.0525" width="0.8128" layer="1"/>
+<wire x1="29.41" y1="5.915" x2="30.48" y2="5.915" width="1.27" layer="16"/>
+<wire x1="30.48" y1="5.915" x2="26.035" y2="8.455" width="1.27" layer="16"/>
+<wire x1="26.035" y1="8.455" x2="26.67" y2="5.7525" width="1.27" layer="16"/>
+<wire x1="67.6275" y1="51.1175" x2="67.945" y2="50.8" width="1.016" layer="16"/>
+<wire x1="7.62" y1="4.445" x2="7.62" y2="5.765140625" width="2.54" layer="16"/>
+<wire x1="7.62" y1="5.765140625" x2="5.3975" y2="7.987640625" width="2.54" layer="16"/>
+<wire x1="72.7075" y1="37.1475" x2="72.7075" y2="40.3225" width="0.8128" layer="16"/>
+<wire x1="72.7075" y1="40.3225" x2="72.39" y2="40.64" width="0.8128" layer="16"/>
+<wire x1="76.5175" y1="27.94" x2="76.5175" y2="33.047703125" width="0.8128" layer="16"/>
+<wire x1="72.7075" y1="36.857703125" x2="72.7075" y2="37.1475" width="0.8128" layer="16"/>
+<wire x1="76.5175" y1="33.047703125" x2="72.7075" y2="36.857703125" width="0.8128" layer="16"/>
+<wire x1="88.5825" y1="19.685" x2="88.5825" y2="32.971440625" width="0.8128" layer="16"/>
+<wire x1="88.5825" y1="32.971440625" x2="91.148646875" y2="35.5375875" width="0.8128" layer="16"/>
+<wire x1="27.305" y1="7.62" x2="29.845" y2="7.62" width="1.27" layer="1"/>
+<wire x1="30.1625" y1="6.0325" x2="30.7975" y2="7.9375" width="1.27" layer="1"/>
+<wire x1="29.845" y1="7.62" x2="30.1625" y2="6.0325" width="1.27" layer="1"/>
+<wire x1="26.9875" y1="7.9375" x2="27.305" y2="7.62" width="1.27" layer="1"/>
+<wire x1="60.96" y1="26.035" x2="61.2775" y2="26.3525" width="0.4064" layer="1"/>
+<wire x1="51.7525" y1="26.035" x2="60.96" y2="26.035" width="0.4064" layer="1"/>
+<contactref element="U$1" pad="P$12"/>
+<via x="60.325" y="2.2225" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<via x="92.3925" y="13.97" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="9.8425" y1="65.7225" x2="7.62" y2="63.5" width="1.27" layer="16"/>
+<wire x1="24.0425" y1="61.595" x2="23.725" y2="63.9306" width="1.27" layer="16"/>
+<wire x1="23.725" y1="63.9306" x2="23.7062" y2="63.9494" width="1.27" layer="16"/>
+<wire x1="23.7062" y1="63.9494" x2="23.0712" y2="64.5588" width="1.27" layer="16"/>
+<wire x1="23.0712" y1="64.5588" x2="22.86" y2="65.405" width="1.27" layer="16"/>
+<wire x1="25.4" y1="53.0225" x2="25.0825" y2="53.0225" width="1.27" layer="16"/>
+<wire x1="25.0825" y1="53.0225" x2="26.3525" y2="53.34" width="1.27" layer="16"/>
+<wire x1="26.3525" y1="53.34" x2="28.575" y2="55.5625" width="1.27" layer="16"/>
+<wire x1="32.7025" y1="58.19" x2="32.9025" y2="58.1025" width="1.27" layer="16"/>
+<wire x1="36.83" y1="56.515" x2="32.9025" y2="58.1025" width="1.27" layer="16"/>
+<wire x1="28.575" y1="55.5625" x2="32.9025" y2="58.1025" width="1.27" layer="16"/>
+<via x="33.3375" y="61.9125" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<contactref element="C15" pad="1"/>
+<via x="93.6625" y="20.955" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="93.0275" y="41.275" extent="1-16" drill="0.5"/>
+<via x="93.6625" y="28.8925" extent="1-16" drill="0.5"/>
+<via x="2.2225" y="22.225" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="2.2225" y="40.9575" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="93.345" y="57.4675" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="13.6525" y="38.735" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="46.6725" y1="55.88" x2="40.9575" y2="61.2775" width="0.4064" layer="1"/>
+<wire x1="46.6725" y1="36.5125" x2="46.6725" y2="55.88" width="0.4064" layer="1"/>
+<contactref element="LED1" pad="K1"/>
+<contactref element="LED1" pad="K2"/>
+<contactref element="LED2" pad="K1"/>
+<via x="65.0875" y="5.3975" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="65.0875" y1="5.3975" x2="67.16" y2="5.3975" width="0.4064" layer="16"/>
+<wire x1="67.16" y1="5.3975" x2="67.1625" y2="5.395" width="0.4064" layer="16"/>
+<contactref element="U$5" pad="4"/>
+<contactref element="C16" pad="1"/>
+<wire x1="23.09" y1="54.61" x2="24.4475" y2="53.2525" width="1.016" layer="16"/>
+<wire x1="24.4475" y1="53.2525" x2="25.0825" y2="53.0225" width="1.016" layer="16"/>
+<wire x1="91.44" y1="47.7125" x2="91.44" y2="45.72" width="1.27" layer="16"/>
+<wire x1="28.575" y1="62.3175" x2="29.615" y2="61.9125" width="1.27" layer="16"/>
+<wire x1="29.615" y1="61.9125" x2="33.3375" y2="61.9125" width="1.27" layer="16"/>
+<wire x1="30.1625" y1="8.66" x2="30.1625" y2="6.0325" width="1.778" layer="16"/>
+<wire x1="26.67" y1="8.89" x2="26.9" y2="8.66" width="1.778" layer="16"/>
+<wire x1="26.9" y1="8.66" x2="30.1625" y2="8.66" width="1.778" layer="16"/>
+<contactref element="GPIO" pad="6"/>
+<contactref element="GPIO" pad="4"/>
+<via x="29.845" y="39.0525" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<via x="33.02" y="47.625" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<polygon width="0.6096" layer="16" isolate="0.4064">
+<vertex x="35.8775" y="48.895"/>
+<vertex x="32.385" y="48.895"/>
+<vertex x="30.1625" y="46.6725"/>
+<vertex x="30.1625" y="45.72"/>
+<vertex x="32.385" y="45.72"/>
+<vertex x="32.0675" y="40.9575"/>
+<vertex x="30.48" y="40.9575"/>
+<vertex x="29.5275" y="40.005"/>
+<vertex x="29.5275" y="36.83"/>
+<vertex x="33.3375" y="36.83"/>
+<vertex x="33.655" y="40.3225"/>
+<vertex x="34.925" y="42.545"/>
+<vertex x="34.925" y="46.99"/>
+<vertex x="35.8775" y="46.99"/>
+</polygon>
+<polygon width="0.4064" layer="16">
+<vertex x="46.99" y="34.29"/>
+<vertex x="45.4025" y="35.8775"/>
+<vertex x="41.5925" y="35.8775"/>
+<vertex x="39.37" y="33.9725"/>
+<vertex x="39.37" y="26.035"/>
+<vertex x="40.3225" y="25.0825"/>
+<vertex x="43.4975" y="25.0825"/>
+<vertex x="44.45" y="26.035"/>
+<vertex x="44.45" y="28.8925"/>
+<vertex x="46.99" y="31.4325"/>
+</polygon>
+<via x="41.91" y="26.67" extent="1-16" drill="0.7" alwaysstop="yes"/>
+</signal>
+<signal name="GPIO_10">
+<contactref element="U$2" pad="1"/>
+<contactref element="GPIO" pad="3"/>
+<wire x1="68.2625" y1="9.525" x2="61.9125" y2="9.525" width="0.4064" layer="16"/>
+<wire x1="61.9125" y1="9.525" x2="57.15" y2="10.795" width="0.4064" layer="16"/>
+<wire x1="57.15" y1="10.795" x2="51.435" y2="10.795" width="0.4064" layer="16"/>
+<wire x1="51.435" y1="10.795" x2="49.53" y2="12.7" width="0.4064" layer="16"/>
+<wire x1="49.53" y1="12.7" x2="43.815" y2="12.7" width="0.4064" layer="16"/>
+<wire x1="43.815" y1="12.7" x2="36.195" y2="22.225" width="0.4064" layer="16"/>
+<wire x1="36.195" y1="36.195" x2="36.195" y2="22.225" width="0.4064" layer="16"/>
+<via x="40.3225" y="40.9575" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="40.3225" y1="40.9575" x2="40.3225" y2="46.99" width="0.4064" layer="1"/>
+<via x="40.3225" y="46.99" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="40.3225" y1="46.99" x2="52.07" y2="58.7375" width="0.4064" layer="16"/>
+<wire x1="40.3225" y1="40.9575" x2="36.195" y2="36.195" width="0.4064" layer="16"/>
+</signal>
+<signal name="GPIO_11">
+<contactref element="U$2" pad="2"/>
+<contactref element="GPIO" pad="5"/>
+<wire x1="50.4825" y1="20.955" x2="48.26" y2="23.1775" width="0.4064" layer="16"/>
+<wire x1="48.26" y1="27.305" x2="48.26" y2="23.1775" width="0.4064" layer="16"/>
+<via x="49.53" y="38.735" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="49.53" y1="38.735" x2="49.53" y2="47.3075" width="0.4064" layer="1"/>
+<via x="49.53" y="47.3075" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="49.53" y1="47.3075" x2="54.61" y2="57.4675" width="0.4064" layer="16"/>
+<wire x1="54.61" y1="57.4675" x2="54.61" y2="58.7375" width="0.4064" layer="16"/>
+<wire x1="50.165" y1="36.83" x2="50.165" y2="29.5275" width="0.4064" layer="16"/>
+<wire x1="50.165" y1="36.83" x2="49.53" y2="37.465" width="0.4064" layer="16"/>
+<wire x1="49.53" y1="37.465" x2="49.53" y2="38.735" width="0.4064" layer="16"/>
+<wire x1="50.165" y1="29.5275" x2="48.26" y2="27.305" width="0.4064" layer="16"/>
+<wire x1="68.2625" y1="12.065" x2="64.4525" y2="12.065" width="0.4064" layer="16"/>
+<wire x1="64.4525" y1="12.065" x2="56.1975" y2="18.415" width="0.4064" layer="16"/>
+<wire x1="56.1975" y1="18.415" x2="51.7525" y2="18.415" width="0.4064" layer="16"/>
+<wire x1="51.7525" y1="18.415" x2="50.4825" y2="20.955" width="0.4064" layer="16"/>
+</signal>
+<signal name="MISO_SPI3">
+<contactref element="U$2" pad="15"/>
+<contactref element="U$1" pad="P$7"/>
+<contactref element="U$5" pad="2"/>
+<wire x1="68.2625" y1="45.085" x2="66.9925" y2="46.355" width="0.4064" layer="16"/>
+<wire x1="56.8325" y1="46.355" x2="55.5625" y2="47.625" width="0.4064" layer="16"/>
+<wire x1="55.5625" y1="47.625" x2="51.435" y2="47.625" width="0.4064" layer="16"/>
+<wire x1="51.435" y1="47.625" x2="50.8" y2="46.0375" width="0.4064" layer="16"/>
+<wire x1="39.37" y1="45.72" x2="36.195" y2="49.53" width="0.4064" layer="16"/>
+<wire x1="26.9875" y1="44.45" x2="26.9875" y2="42.8625" width="0.4064" layer="16"/>
+<wire x1="26.9875" y1="42.8625" x2="30.8991" y2="42.8625" width="0.4064" layer="16"/>
+<wire x1="66.9925" y1="46.355" x2="56.8325" y2="46.355" width="0.4064" layer="16"/>
+<wire x1="50.8" y1="46.0375" x2="47.625" y2="46.0375" width="0.4064" layer="16"/>
+<wire x1="47.625" y1="46.0375" x2="46.99" y2="46.355" width="0.4064" layer="16"/>
+<wire x1="46.99" y1="46.355" x2="42.2275" y2="46.355" width="0.4064" layer="16"/>
+<wire x1="42.2275" y1="46.355" x2="41.275" y2="45.72" width="0.4064" layer="16"/>
+<wire x1="41.275" y1="45.72" x2="39.37" y2="45.72" width="0.4064" layer="16"/>
+<wire x1="36.195" y1="49.53" x2="32.0675" y2="49.53" width="0.4064" layer="16"/>
+<wire x1="32.0675" y1="49.53" x2="26.9875" y2="44.45" width="0.4064" layer="16"/>
+<wire x1="26.9875" y1="42.8625" x2="26.9875" y2="28.575" width="0.4064" layer="16"/>
+<via x="26.9875" y="28.575" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="26.9875" y1="28.575" x2="26.9875" y2="21.9075" width="0.4064" layer="1"/>
+<wire x1="26.9875" y1="21.9075" x2="26.67" y2="21.59" width="0.4064" layer="1"/>
+</signal>
+<signal name="MOSI_SPI3">
+<contactref element="U$2" pad="14"/>
+<contactref element="U$1" pad="P$3"/>
+<contactref element="U$5" pad="5"/>
+<wire x1="68.2625" y1="42.545" x2="67.31" y2="42.545" width="0.4064" layer="16"/>
+<wire x1="67.31" y1="42.545" x2="64.4525" y2="45.4025" width="0.4064" layer="16"/>
+<wire x1="64.4525" y1="45.4025" x2="56.1975" y2="45.4025" width="0.4064" layer="16"/>
+<wire x1="56.1975" y1="45.4025" x2="54.9275" y2="46.6725" width="0.4064" layer="16"/>
+<wire x1="54.9275" y1="46.6725" x2="52.07" y2="46.6725" width="0.4064" layer="16"/>
+<wire x1="52.07" y1="46.6725" x2="51.435" y2="45.085" width="0.4064" layer="16"/>
+<wire x1="51.435" y1="45.085" x2="46.99" y2="45.085" width="0.4064" layer="16"/>
+<wire x1="46.99" y1="45.085" x2="46.355" y2="45.4025" width="0.4064" layer="16"/>
+<wire x1="46.355" y1="45.4025" x2="42.8625" y2="45.4025" width="0.4064" layer="16"/>
+<wire x1="42.8625" y1="45.4025" x2="41.91" y2="44.7675" width="0.4064" layer="16"/>
+<wire x1="41.91" y1="44.7675" x2="39.0525" y2="44.7675" width="0.4064" layer="16"/>
+<wire x1="39.0525" y1="44.7675" x2="38.1" y2="45.4025" width="0.4064" layer="16"/>
+<wire x1="38.1" y1="45.4025" x2="37.0459" y2="45.4025" width="0.4064" layer="16"/>
+<wire x1="46.99" y1="13.97" x2="44.7675" y2="13.97" width="0.4064" layer="16"/>
+<wire x1="44.7675" y1="13.97" x2="37.1475" y2="23.495" width="0.4064" layer="16"/>
+<wire x1="37.1475" y1="23.495" x2="37.1475" y2="35.56" width="0.4064" layer="16"/>
+<wire x1="37.1475" y1="35.56" x2="42.8625" y2="40.9575" width="0.4064" layer="16"/>
+<via x="42.8625" y="40.9575" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="42.8625" y1="40.9575" x2="42.8625" y2="45.085" width="0.4064" layer="1"/>
+<via x="42.8625" y="45.085" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="42.8625" y1="45.085" x2="42.8625" y2="45.4025" width="0.4064" layer="16"/>
+</signal>
+<signal name="CS_W5500">
+<contactref element="U$2" pad="13"/>
+<contactref element="R4" pad="2"/>
+<contactref element="U$1" pad="P$5"/>
+<wire x1="68.2625" y1="40.005" x2="63.8175" y2="40.005" width="0.4064" layer="16"/>
+<wire x1="63.8175" y1="40.005" x2="63.8175" y2="41.595" width="0.4064" layer="16"/>
+<wire x1="63.8175" y1="40.005" x2="56.8325" y2="40.005" width="0.4064" layer="16"/>
+<wire x1="56.8325" y1="40.005" x2="55.5625" y2="41.275" width="0.4064" layer="16"/>
+<wire x1="51.7525" y1="41.275" x2="51.435" y2="40.9575" width="0.4064" layer="16"/>
+<wire x1="55.5625" y1="41.275" x2="51.7525" y2="41.275" width="0.4064" layer="16"/>
+<wire x1="48.26" y1="40.9575" x2="47.3075" y2="40.005" width="0.4064" layer="16"/>
+<wire x1="47.3075" y1="40.005" x2="47.3075" y2="35.8775" width="0.4064" layer="16"/>
+<wire x1="47.3075" y1="35.8775" x2="48.26" y2="34.925" width="0.4064" layer="16"/>
+<wire x1="48.26" y1="34.925" x2="48.26" y2="30.7975" width="0.4064" layer="16"/>
+<wire x1="48.26" y1="30.7975" x2="46.355" y2="28.575" width="0.4064" layer="16"/>
+<wire x1="46.355" y1="28.575" x2="46.355" y2="23.495" width="0.4064" layer="16"/>
+<wire x1="46.355" y1="23.495" x2="44.7675" y2="22.5425" width="0.4064" layer="16"/>
+<wire x1="44.7675" y1="22.5425" x2="44.7675" y2="20.0025" width="0.4064" layer="16"/>
+<wire x1="44.7675" y1="20.0025" x2="45.4025" y2="19.05" width="0.4064" layer="16"/>
+<wire x1="45.4025" y1="19.05" x2="46.99" y2="19.05" width="0.4064" layer="16"/>
+<wire x1="51.435" y1="40.9575" x2="48.26" y2="40.9575" width="0.4064" layer="16"/>
+</signal>
+<signal name="IT_W5500">
+<contactref element="U$2" pad="12"/>
+<contactref element="U$1" pad="P$6"/>
+<wire x1="68.2625" y1="37.465" x2="66.675" y2="37.465" width="0.4064" layer="16"/>
+<wire x1="66.675" y1="37.465" x2="65.405" y2="38.735" width="0.4064" layer="16"/>
+<wire x1="51.435" y1="38.735" x2="50.165" y2="40.005" width="0.4064" layer="16"/>
+<wire x1="48.895" y1="40.005" x2="48.26" y2="39.37" width="0.4064" layer="16"/>
+<wire x1="48.26" y1="39.37" x2="48.26" y2="36.83" width="0.4064" layer="16"/>
+<wire x1="48.26" y1="36.83" x2="49.2125" y2="35.8775" width="0.4064" layer="16"/>
+<wire x1="49.2125" y1="35.8775" x2="49.2125" y2="30.1625" width="0.4064" layer="16"/>
+<wire x1="49.2125" y1="30.1625" x2="47.3075" y2="27.94" width="0.4064" layer="16"/>
+<wire x1="47.3075" y1="27.94" x2="47.3075" y2="21.9075" width="0.4064" layer="16"/>
+<wire x1="47.3075" y1="21.9075" x2="46.99" y2="21.59" width="0.4064" layer="16"/>
+<wire x1="65.405" y1="38.735" x2="51.435" y2="38.735" width="0.4064" layer="16"/>
+<wire x1="50.165" y1="40.005" x2="48.895" y2="40.005" width="0.4064" layer="16"/>
+</signal>
+<signal name="LED_RX">
+<contactref element="U$2" pad="9"/>
+<contactref element="R10" pad="1"/>
+<via x="70.8025" y="16.51" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="72.0725" y="10.795" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="72.39" y1="29.845" x2="72.39" y2="18.415" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="16.51" x2="72.39" y2="18.415" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="16.51" x2="71.12" y2="11.7475" width="0.4064" layer="1"/>
+<wire x1="71.12" y1="11.7475" x2="72.0725" y2="10.795" width="0.4064" layer="1"/>
+<wire x1="72.39" y1="29.845" x2="71.40270625" y2="30.83229375" width="0.4064" layer="16"/>
+<wire x1="71.40270625" y1="30.83229375" x2="69.88479375" y2="30.83229375" width="0.4064" layer="16"/>
+<wire x1="69.88479375" y1="30.83229375" x2="68.8975" y2="29.845" width="0.4064" layer="16"/>
+<wire x1="68.8975" y1="29.845" x2="68.2625" y2="29.845" width="0.4064" layer="16"/>
+<wire x1="72.263" y1="8.062" x2="72.0725" y2="8.2525" width="0.4064" layer="16"/>
+<wire x1="72.0725" y1="8.2525" x2="72.0725" y2="10.795" width="0.4064" layer="16"/>
+</signal>
+<signal name="RF_VCC">
+<contactref element="U$3" pad="1"/>
+<contactref element="C5" pad="1"/>
+<via x="92.075" y="53.34" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="91.7575" y1="57.15" x2="90.4875" y2="58.42" width="1.27" layer="16"/>
+<wire x1="90.4875" y1="58.42" x2="85.09" y2="58.42" width="1.27" layer="16"/>
+<wire x1="85.09" y1="58.42" x2="82.55" y2="61.9125" width="1.27" layer="16"/>
+<via x="92.075" y="55.245" extent="1-16" drill="0.7" alwaysstop="yes"/>
+<wire x1="91.4375" y1="51.175" x2="91.4375" y2="53.34" width="1.27" layer="1"/>
+<wire x1="91.4375" y1="53.34" x2="92.075" y2="55.245" width="1.27" layer="1"/>
+<wire x1="92.075" y1="55.245" x2="92.075" y2="53.34" width="1.27" layer="16"/>
+<wire x1="92.075" y1="53.34" x2="91.7575" y2="57.15" width="1.27" layer="16"/>
+<wire x1="92.075" y1="53.34" x2="92.075" y2="55.245" width="1.27" layer="1"/>
+<wire x1="82.55" y1="61.9125" x2="82.55" y2="66.04" width="1.27" layer="16"/>
+<wire x1="82.55" y1="66.04" x2="74.93" y2="66.04" width="1.27" layer="16"/>
+<wire x1="74.93" y1="66.04" x2="74.4574" y2="66.5126" width="0.8128" layer="16"/>
+<wire x1="62.5475" y1="66.5126" x2="74.4574" y2="66.5126" width="0.8128" layer="16"/>
+<contactref element="C11" pad="+"/>
+<wire x1="38.4175" y1="64.77" x2="41.275" y2="64.77" width="2.54" layer="16"/>
+<wire x1="41.275" y1="64.77" x2="42.8625" y2="64.77" width="2.54" layer="16"/>
+<wire x1="42.8625" y1="64.77" x2="45.72" y2="64.77" width="2.54" layer="16"/>
+<wire x1="63.1825" y1="65.405" x2="62.5475" y2="66.5126" width="0.8128" layer="16"/>
+<wire x1="45.72" y1="64.77" x2="46.355" y2="65.405" width="1.27" layer="16"/>
+<wire x1="46.355" y1="65.405" x2="63.1825" y2="65.405" width="2.032" layer="16"/>
+<wire x1="38.4175" y1="64.77" x2="35.205" y2="64.77" width="1.778" layer="16"/>
+<wire x1="37.1475" y1="64.73" x2="36.235" y2="64.77" width="0.4064" layer="16"/>
+<wire x1="36.235" y1="64.77" x2="38.4175" y2="64.77" width="0.4064" layer="16"/>
+<wire x1="41.691453125" y1="64.5975" x2="41.275" y2="64.77" width="0.4064" layer="16" curve="-45"/>
+<contactref element="SB3" pad="1"/>
+<contactref element="SB4" pad="1"/>
+<wire x1="42.8625" y1="59.6875" x2="42.8625" y2="64.77" width="1.524" layer="16"/>
+<wire x1="91.44" y1="50.7125" x2="92.075" y2="51.3475" width="1.27" layer="16"/>
+<wire x1="92.075" y1="51.3475" x2="92.075" y2="53.34" width="1.27" layer="16"/>
+<wire x1="35.205" y1="64.77" x2="34.8875" y2="65.0875" width="1.524" layer="16"/>
+<wire x1="34.8875" y1="65.0875" x2="33.6525" y2="65.0875" width="1.524" layer="16"/>
+</signal>
+<signal name="CLK_SPI1">
+<contactref element="U$3" pad="9"/>
+<contactref element="U$2" pad="23"/>
+<via x="70.1675" y="20.955" extent="1-16" drill="0.5"/>
+<wire x1="60.325" y1="27.305" x2="64.4525" y2="26.035" width="0.4064" layer="16"/>
+<wire x1="60.325" y1="27.305" x2="53.0225" y2="27.305" width="0.4064" layer="16"/>
+<wire x1="71.4375" y1="22.225" x2="70.1675" y2="20.955" width="0.4064" layer="1"/>
+<wire x1="64.4525" y1="26.035" x2="68.8975" y2="26.035" width="0.4064" layer="16"/>
+<wire x1="68.8975" y1="26.035" x2="70.1675" y2="24.765" width="0.4064" layer="16"/>
+<wire x1="70.1675" y1="24.765" x2="70.1675" y2="20.955" width="0.4064" layer="16"/>
+<wire x1="71.4375" y1="22.225" x2="71.4375" y2="23.175" width="0.4064" layer="1"/>
+</signal>
+<signal name="GPIO_0">
+<via x="70.8025" y="40.64" extent="1-16" drill="0.5"/>
+<contactref element="U$3" pad="13"/>
+<wire x1="70.8025" y1="40.64" x2="71.4375" y2="39.175" width="0.4064" layer="1"/>
+<wire x1="57.785" y1="47.3075" x2="55.245" y2="49.53" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="46.99" x2="70.485" y2="47.3075" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="40.64" x2="70.8025" y2="46.99" width="0.4064" layer="16"/>
+<wire x1="70.485" y1="47.3075" x2="57.785" y2="47.3075" width="0.4064" layer="16"/>
+<contactref element="GPIO" pad="7"/>
+<wire x1="55.245" y1="49.53" x2="55.245" y2="54.2925" width="0.4064" layer="16"/>
+<wire x1="55.245" y1="54.2925" x2="57.15" y2="56.8325" width="0.4064" layer="16"/>
+<wire x1="57.15" y1="56.8325" x2="57.15" y2="58.7375" width="0.4064" layer="16"/>
+</signal>
+<signal name="LED_TX">
+<via x="71.12" y="36.5125" extent="1-16" drill="0.5"/>
+<via x="75.565" y="19.685" extent="1-16" drill="0.5"/>
+<via x="76.2" y="13.6525" extent="1-16" drill="0.5"/>
+<wire x1="75.565" y1="19.685" x2="75.2475" y2="19.685" width="0.4064" layer="16"/>
+<wire x1="75.2475" y1="19.685" x2="75.2475" y2="30.7975" width="0.4064" layer="16"/>
+<contactref element="U$3" pad="12"/>
+<wire x1="71.4375" y1="35.175" x2="71.12" y2="36.5125" width="0.4064" layer="1"/>
+<contactref element="R12" pad="1"/>
+<wire x1="76.2" y1="13.6525" x2="76.2" y2="13.97" width="0.4064" layer="16"/>
+<wire x1="72.7075" y1="13.97" x2="76.2" y2="13.97" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="7.9375" x2="70.8025" y2="12.065" width="0.4064" layer="16"/>
+<wire x1="62.8675" y1="6.6675" x2="62.865" y2="6.03" width="0.4064" layer="16"/>
+<wire x1="75.565" y1="14.2875" x2="76.2" y2="13.6525" width="0.4064" layer="1"/>
+<wire x1="75.565" y1="19.685" x2="75.565" y2="14.2875" width="0.4064" layer="1"/>
+<wire x1="75.2475" y1="30.7975" x2="71.12" y2="34.925" width="0.4064" layer="16"/>
+<wire x1="71.12" y1="34.925" x2="71.12" y2="36.5125" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="7.9375" x2="69.85" y2="6.6675" width="0.4064" layer="16"/>
+<wire x1="69.85" y1="6.6675" x2="62.8675" y2="6.6675" width="0.4064" layer="16"/>
+<wire x1="70.8025" y1="12.065" x2="72.7075" y2="13.97" width="0.4064" layer="16"/>
+</signal>
+<signal name="RF_OUT">
+<contactref element="U$3" pad="16"/>
+<contactref element="X1" pad="1"/>
+<wire x1="71.4375" y1="51.175" x2="71.0625" y2="51.175" width="1.524" layer="1"/>
+<wire x1="71.0625" y1="51.175" x2="69.5325" y2="52.705" width="1.524" layer="1" curve="-90"/>
+<wire x1="69.5325" y1="52.705" x2="69.5325" y2="61.9125" width="1.524" layer="1"/>
+</signal>
+<signal name="6V">
+<contactref element="U$4" pad="OUT+"/>
+<contactref element="C6" pad="1"/>
+<contactref element="L4940_5V" pad="1"/>
+<wire x1="20.32" y1="62.865" x2="20.32" y2="65.405" width="1.778" layer="16"/>
+<contactref element="C12" pad="+"/>
+<contactref element="C14" pad="1"/>
+<wire x1="20.0025" y1="65.7225" x2="20.32" y2="65.405" width="1.27" layer="16"/>
+<wire x1="21.0425" y1="61.595" x2="21.0425" y2="59.4025" width="2.54" layer="16"/>
+<wire x1="21.0425" y1="59.4025" x2="26.1525" y2="58.1025" width="2.54" layer="16"/>
+<contactref element="SB2" pad="1"/>
+<wire x1="21.0425" y1="61.595" x2="20.32" y2="62.3175" width="1.27" layer="16"/>
+<wire x1="20.32" y1="62.3175" x2="20.32" y2="62.865" width="1.27" layer="16"/>
+<wire x1="21.0425" y1="61.595" x2="16.195" y2="61.595" width="1.778" layer="16"/>
+<wire x1="16.195" y1="61.595" x2="16.1925" y2="60.64" width="1.27" layer="16"/>
+<wire x1="16.195" y1="61.595" x2="13.6525" y2="61.595" width="1.778" layer="16"/>
+<wire x1="13.6525" y1="61.595" x2="13.6525" y2="57.785" width="1.778" layer="16"/>
+<wire x1="13.6525" y1="57.785" x2="13.335" y2="57.4675" width="1.27" layer="16"/>
+<wire x1="13.335" y1="57.4675" x2="13.335" y2="52.07" width="1.27" layer="16"/>
+<wire x1="13.335" y1="43.815" x2="16.8275" y2="40.3225" width="1.778" layer="16"/>
+<wire x1="16.8275" y1="17.2325" x2="16.4225" y2="16.8275" width="1.778" layer="16"/>
+<wire x1="13.335" y1="52.07" x2="13.335" y2="43.815" width="1.778" layer="16"/>
+<wire x1="16.8275" y1="40.3225" x2="16.8275" y2="24.4475" width="1.778" layer="16"/>
+<wire x1="16.8275" y1="24.4475" x2="16.8275" y2="17.2325" width="1.778" layer="16"/>
+<wire x1="21.835" y1="10.98" x2="16.8275" y2="15.9875" width="1.778" layer="16"/>
+<wire x1="16.8275" y1="15.9875" x2="16.8275" y2="17.2325" width="1.778" layer="16"/>
+<contactref element="D1" pad="A"/>
+<wire x1="21.47" y1="24.4475" x2="16.8275" y2="24.4475" width="1.778" layer="16"/>
+</signal>
+<signal name="3V3NUCLEO">
+<contactref element="U$2" pad="17"/>
+<contactref element="R1" pad="1"/>
+<contactref element="C3" pad="2"/>
+<wire x1="50.1625" y1="42.545" x2="53.0225" y2="42.545" width="1.27" layer="16"/>
+<wire x1="53.0225" y1="42.545" x2="56.92" y2="42.545" width="1.27" layer="16"/>
+<contactref element="R6" pad="2"/>
+<contactref element="R5" pad="1"/>
+<wire x1="60.96" y1="35.245" x2="59.35928125" y2="35.06936875" width="0.8128" layer="16"/>
+<wire x1="59.35928125" y1="35.06936875" x2="57.15" y2="34.9225" width="0.8128" layer="16"/>
+<wire x1="59.35928125" y1="35.06936875" x2="59.055" y2="35.8775" width="0.8128" layer="16"/>
+<via x="59.055" y="35.8775" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="53.0225" y1="42.545" x2="55.5625" y2="42.545" width="0.4064" layer="1"/>
+<contactref element="R4" pad="1"/>
+<wire x1="56.92" y1="42.545" x2="56.92" y2="43.815" width="0.4064" layer="16"/>
+<wire x1="55.5625" y1="42.545" x2="59.055" y2="35.8775" width="0.4064" layer="1"/>
+<wire x1="56.92" y1="43.815" x2="57.555" y2="44.45" width="0.4064" layer="16"/>
+<wire x1="57.555" y1="44.45" x2="63.5" y2="44.45" width="0.4064" layer="16"/>
+<wire x1="63.5" y1="44.45" x2="64.4525" y2="43.4975" width="0.4064" layer="16"/>
+<wire x1="64.4525" y1="43.4975" x2="63.8175" y2="43.495" width="0.4064" layer="16"/>
+</signal>
+<signal name="LED-TX">
+<contactref element="R9" pad="2"/>
+<contactref element="LED2" pad="A2"/>
+<wire x1="81.595" y1="3.556" x2="81.915" y2="3.876" width="0.4064" layer="16"/>
+<wire x1="81.915" y1="5.969" x2="81.595" y2="5.649" width="0.4064" layer="16"/>
+<wire x1="81.595" y1="5.649" x2="81.595" y2="3.556" width="0.4064" layer="16"/>
+</signal>
+<signal name="LED-RX">
+<contactref element="R10" pad="2"/>
+<contactref element="LED1" pad="A2"/>
+<wire x1="72.263" y1="6.162" x2="72.263" y2="4.572" width="0.4064" layer="16"/>
+<wire x1="72.263" y1="4.572" x2="72.7075" y2="4.1275" width="0.4064" layer="16"/>
+<wire x1="72.7075" y1="4.1275" x2="74.9935" y2="4.1275" width="0.4064" layer="16"/>
+<wire x1="74.9935" y1="4.1275" x2="76.835" y2="5.969" width="0.4064" layer="16"/>
+</signal>
+<signal name="LED-CON">
+<contactref element="R11" pad="2"/>
+<wire x1="76.515" y1="11.43" x2="76.835" y2="11.43" width="0.8128" layer="16"/>
+<contactref element="LED1" pad="A1"/>
+<wire x1="76.515" y1="11.43" x2="76.835" y2="11.11" width="0.4064" layer="16"/>
+<wire x1="76.835" y1="11.11" x2="76.835" y2="8.255" width="0.4064" layer="16"/>
+</signal>
+<signal name="LED_CON">
+<contactref element="R11" pad="1"/>
+<contactref element="U$2" pad="5"/>
+<wire x1="68.8975" y1="19.05" x2="71.4375" y2="19.05" width="0.4064" layer="1"/>
+<wire x1="73.3425" y1="17.145" x2="71.4375" y2="19.05" width="0.4064" layer="1"/>
+<via x="73.3425" y="12.7" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="73.3425" y1="12.7" x2="74.612509375" y2="11.429990625" width="0.4064" layer="16"/>
+<wire x1="74.612509375" y1="11.429990625" x2="74.615" y2="11.43" width="0.4064" layer="16"/>
+<wire x1="73.3425" y1="12.7" x2="73.3425" y2="17.145" width="0.4064" layer="1"/>
+<wire x1="68.2625" y1="19.685" x2="68.8975" y2="19.05" width="0.4064" layer="1"/>
+</signal>
+<signal name="LED..TX">
+<contactref element="T1" pad="3"/>
+<contactref element="LED2" pad="K2"/>
+<wire x1="76.581" y1="3.175" x2="79.375" y2="5.969" width="0.4064" layer="16"/>
+<wire x1="69.3625" y1="4.445" x2="71.9025" y2="3.175" width="0.4064" layer="16"/>
+<wire x1="71.9025" y1="3.175" x2="76.581" y2="3.175" width="0.4064" layer="16"/>
+</signal>
+<signal name="LED.TX">
+<contactref element="T1" pad="1"/>
+<contactref element="R12" pad="2"/>
+<wire x1="62.865" y1="4.13" x2="62.865" y2="3.495" width="0.4064" layer="16"/>
+<wire x1="62.865" y1="3.495" x2="67.1625" y2="3.495" width="0.4064" layer="16"/>
+</signal>
+<signal name="N$1">
+<contactref element="R8" pad="2"/>
+<contactref element="LED2" pad="A1"/>
+<wire x1="81.595" y1="12.446" x2="81.915" y2="12.126" width="0.4064" layer="16"/>
+<wire x1="81.915" y1="12.126" x2="81.915" y2="8.255" width="0.4064" layer="16"/>
+</signal>
+<signal name="CS_SRAM">
+<contactref element="U$5" pad="1"/>
+<contactref element="U$2" pad="6"/>
+<wire x1="68.2625" y1="22.225" x2="64.77" y2="22.225" width="0.4064" layer="16"/>
+<wire x1="64.77" y1="22.225" x2="61.595" y2="23.495" width="0.4064" layer="16"/>
+<wire x1="61.595" y1="23.495" x2="51.7525" y2="23.495" width="0.4064" layer="16"/>
+<wire x1="51.7525" y1="23.495" x2="50.4825" y2="25.4" width="0.4064" layer="16"/>
+<via x="50.4825" y="25.4" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<via x="32.7025" y="28.8925" extent="1-16" drill="0.5" alwaysstop="yes"/>
+<wire x1="29.5275" y1="41.5925" x2="28.2575" y2="40.3225" width="0.4064" layer="16"/>
+<wire x1="29.5275" y1="41.5925" x2="30.8991" y2="41.5925" width="0.4064" layer="16"/>
+<wire x1="50.4825" y1="25.4" x2="45.72" y2="28.2575" width="0.4064" layer="1"/>
+<wire x1="45.72" y1="28.2575" x2="32.7025" y2="28.8925" width="0.4064" layer="1"/>
+<contactref element="R3" pad="2"/>
+<wire x1="28.2575" y1="33.02" x2="32.385" y2="28.8925" width="0.4064" layer="16"/>
+<wire x1="32.385" y1="28.8925" x2="32.7025" y2="28.8925" width="0.4064" layer="16"/>
+<wire x1="28.2575" y1="40.3225" x2="28.2575" y2="34.29" width="0.4064" layer="16"/>
+<wire x1="28.2575" y1="34.29" x2="28.2575" y2="33.02" width="0.4064" layer="16"/>
+<wire x1="29.8475" y1="34.29" x2="28.2575" y2="34.29" width="0.4064" layer="16"/>
+</signal>
+<signal name="UEXT">
+<contactref element="UEXT" pad="P$1"/>
+<contactref element="SB2" pad="2"/>
+<contactref element="C13" pad="1"/>
+<contactref element="SB1" pad="2"/>
+<contactref element="SB4" pad="2"/>
+<wire x1="20.09" y1="54.61" x2="15.5575" y2="54.61" width="1.778" layer="16"/>
+<wire x1="16.1925" y1="58.74" x2="16.1925" y2="55.245" width="1.27" layer="16"/>
+<wire x1="16.1925" y1="55.245" x2="15.5575" y2="54.61" width="1.27" layer="16"/>
+<wire x1="42.8625" y1="57.7875" x2="42.8625" y2="56.8325" width="1.27" layer="16"/>
+<wire x1="38.4175" y1="52.3875" x2="30.7975" y2="52.3875" width="1.27" layer="16"/>
+<wire x1="30.7975" y1="52.3875" x2="22.5425" y2="45.085" width="1.27" layer="16"/>
+<wire x1="42.8625" y1="56.8325" x2="38.4175" y2="52.3875" width="1.27" layer="16"/>
+<wire x1="22.5425" y1="45.085" x2="17.78" y2="45.085" width="1.27" layer="16"/>
+<wire x1="17.78" y1="45.085" x2="17.78" y2="47.305" width="1.27" layer="16"/>
+<wire x1="17.78" y1="47.305" x2="17.7825" y2="47.3075" width="1.27" layer="16"/>
+<wire x1="17.7825" y1="47.3075" x2="17.7825" y2="52.385" width="1.27" layer="16"/>
+<wire x1="17.7825" y1="52.385" x2="15.5575" y2="54.61" width="1.27" layer="16"/>
+</signal>
+<signal name="12V">
+<contactref element="U$4" pad="IN+"/>
+<contactref element="SB1" pad="1"/>
+<wire x1="21.835" y1="50.48" x2="19.6825" y2="48.3275" width="1.27" layer="16"/>
+<wire x1="19.6825" y1="48.3275" x2="19.6825" y2="47.3075" width="1.27" layer="16"/>
+</signal>
+<signal name="5V">
+<contactref element="L4940_5V" pad="3"/>
+<contactref element="SB3" pad="2"/>
+<contactref element="C7" pad="1"/>
+<wire x1="25.4" y1="65.405" x2="25.4875" y2="65.3175" width="1.27" layer="16"/>
+<wire x1="25.4875" y1="65.3175" x2="28.575" y2="65.3175" width="1.778" layer="16"/>
+<wire x1="31.7525" y1="65.0875" x2="31.5225" y2="65.3175" width="1.27" layer="16"/>
+<wire x1="31.5225" y1="65.3175" x2="28.575" y2="65.3175" width="1.778" layer="16"/>
+</signal>
+<signal name="3VREGIN">
+<contactref element="LM2937_3V3" pad="1"/>
+<contactref element="C10" pad="+"/>
+<contactref element="C9" pad="1"/>
+<contactref element="D1" pad="C"/>
+<wire x1="26.67" y1="2.185" x2="22.5425" y2="2.945" width="1.778" layer="16"/>
+<wire x1="22.5425" y1="2.945" x2="19.05" y2="2.54" width="1.778" layer="16"/>
+<wire x1="25.52" y1="24.4475" x2="28.2575" y2="24.4475" width="1.524" layer="16"/>
+<wire x1="30.48" y1="22.225" x2="30.48" y2="16.1925" width="1.524" layer="16"/>
+<wire x1="30.48" y1="16.1925" x2="33.9725" y2="12.7" width="1.524" layer="16"/>
+<wire x1="33.9725" y1="12.7" x2="33.9725" y2="4.7625" width="1.524" layer="16"/>
+<wire x1="31.395" y1="2.185" x2="26.67" y2="2.185" width="1.524" layer="16"/>
+<wire x1="28.2575" y1="24.4475" x2="30.48" y2="22.225" width="1.524" layer="16"/>
+<wire x1="33.9725" y1="4.7625" x2="31.395" y2="2.185" width="1.524" layer="16"/>
+</signal>
+</signals>
+</board>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+<note version="8.2" severity="warning">
+Since Version 8.2, EAGLE supports online libraries. The ids
+of those online libraries will not be understood (or retained)
+with this version.
+</note>
+<note version="8.3" severity="warning">
+Since Version 8.3, EAGLE supports URNs for individual library
+assets (packages, symbols, and devices). The URNs of those assets
+will not be understood (or retained) with this version.
+</note>
+<note version="8.3" severity="warning">
+Since Version 8.3, EAGLE supports the association of 3D packages
+with devices in libraries, schematics, and board files. Those 3D
+packages will not be understood (or retained) with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/NPR70_modem_v05_PCB/eagle/NPR70_v05.sch b/NPR70_modem_v05_PCB/eagle/NPR70_v05.sch
new file mode 100755
index 0000000..bceabef
--- /dev/null
+++ b/NPR70_modem_v05_PCB/eagle/NPR70_v05.sch
@@ -0,0 +1,11652 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="8.5.1">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/>
+<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="24" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/>
+<layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/>
+<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
+<layer number="57" name="tCAD" color="7" fill="1" visible="no" active="no"/>
+<layer number="59" name="tCarbon" color="7" fill="1" visible="no" active="no"/>
+<layer number="60" name="bCarbon" color="7" fill="1" visible="no" active="no"/>
+<layer number="88" name="SimResults" color="9" fill="1" visible="yes" active="yes"/>
+<layer number="89" name="SimProbes" color="9" fill="1" visible="yes" active="yes"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="99" name="SpiceOrder" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/>
+<layer number="101" name="Patch_Top" color="12" fill="4" visible="yes" active="yes"/>
+<layer number="102" name="Vscore" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="103" name="tMap" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="104" name="Name" color="16" fill="1" visible="yes" active="yes"/>
+<layer number="105" name="tPlate" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="106" name="bPlate" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="107" name="Crop" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="108" name="tplace-old" color="10" fill="1" visible="yes" active="yes"/>
+<layer number="109" name="ref-old" color="11" fill="1" visible="yes" active="yes"/>
+<layer number="110" name="fp0" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="111" name="LPC17xx" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="112" name="tSilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="113" name="IDFDebug" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="114" name="Badge_Outline" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="115" name="ReferenceISLANDS" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="116" name="Patch_BOT" color="9" fill="4" visible="yes" active="yes"/>
+<layer number="117" name="BACKMAAT1" color="7" fill="1" visible="no" active="no"/>
+<layer number="118" name="Rect_Pads" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="119" name="KAP_TEKEN" color="7" fill="1" visible="no" active="no"/>
+<layer number="120" name="KAP_MAAT1" color="7" fill="1" visible="no" active="no"/>
+<layer number="121" name="_tsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="123" name="tTestmark" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="124" name="bTestmark" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="125" name="_tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="126" name="_bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="127" name="_tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="128" name="_bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="129" name="Mask" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="130" name="SMDSTROOK" color="7" fill="1" visible="no" active="no"/>
+<layer number="131" name="tAdjust" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="132" name="bAdjust" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="133" name="bottom_silk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="144" name="Drill_legend" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="150" name="Notes" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="152" name="_bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="153" name="FabDoc1" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="154" name="FabDoc2" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="155" name="FabDoc3" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="199" name="Contour" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="200" name="200bmp" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="201" name="201bmp" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="202" name="202bmp" color="3" fill="10" visible="yes" active="yes"/>
+<layer number="203" name="203bmp" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="204" name="204bmp" color="5" fill="10" visible="yes" active="yes"/>
+<layer number="205" name="205bmp" color="6" fill="10" visible="yes" active="yes"/>
+<layer number="206" name="206bmp" color="7" fill="10" visible="yes" active="yes"/>
+<layer number="207" name="207bmp" color="8" fill="10" visible="yes" active="yes"/>
+<layer number="208" name="208bmp" color="9" fill="10" visible="yes" active="yes"/>
+<layer number="209" name="209bmp" color="10" fill="10" visible="yes" active="yes"/>
+<layer number="210" name="210bmp" color="11" fill="10" visible="yes" active="yes"/>
+<layer number="211" name="211bmp" color="12" fill="10" visible="yes" active="yes"/>
+<layer number="212" name="212bmp" color="13" fill="10" visible="yes" active="yes"/>
+<layer number="213" name="213bmp" color="14" fill="10" visible="yes" active="yes"/>
+<layer number="214" name="214bmp" color="15" fill="10" visible="yes" active="yes"/>
+<layer number="215" name="215bmp" color="16" fill="10" visible="yes" active="yes"/>
+<layer number="216" name="216bmp" color="17" fill="10" visible="yes" active="yes"/>
+<layer number="217" name="217bmp" color="18" fill="10" visible="yes" active="yes"/>
+<layer number="218" name="218bmp" color="19" fill="10" visible="yes" active="yes"/>
+<layer number="219" name="219bmp" color="20" fill="10" visible="yes" active="yes"/>
+<layer number="220" name="220bmp" color="21" fill="10" visible="yes" active="yes"/>
+<layer number="221" name="221bmp" color="22" fill="10" visible="yes" active="yes"/>
+<layer number="222" name="222bmp" color="23" fill="10" visible="yes" active="yes"/>
+<layer number="223" name="223bmp" color="24" fill="10" visible="yes" active="yes"/>
+<layer number="224" name="224bmp" color="25" fill="10" visible="yes" active="yes"/>
+<layer number="225" name="225bmp" color="26" fill="10" visible="yes" active="yes"/>
+<layer number="226" name="226bmp" color="27" fill="10" visible="yes" active="yes"/>
+<layer number="227" name="227bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="228" name="228bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="229" name="229bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="230" name="230bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="231" name="231bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="232" name="Eagle3D_PG2" color="7" fill="1" visible="no" active="no"/>
+<layer number="233" name="Eagle3D_PG3" color="7" fill="1" visible="no" active="no"/>
+<layer number="248" name="Housing" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="249" name="Edge" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/>
+<layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/>
+<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="255" name="routoute" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="NPR_70">
+<packages>
+<package name="RF4463F30">
+<smd name="8" x="-19" y="4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="7" x="-19" y="0" dx="2.54" dy="1.27" layer="1"/>
+<smd name="6" x="-19" y="-4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="5" x="-19" y="-8" dx="2.54" dy="1.27" layer="1"/>
+<smd name="4" x="-19" y="-12" dx="2.54" dy="1.27" layer="1"/>
+<smd name="3" x="-19" y="-16" dx="2.54" dy="1.27" layer="1"/>
+<smd name="2" x="-19" y="-20" dx="2.54" dy="1.27" layer="1"/>
+<smd name="1" x="-19" y="-24" dx="2.54" dy="1.27" layer="1"/>
+<smd name="16" x="1" y="-24" dx="2.54" dy="1.27" layer="1"/>
+<smd name="15" x="1" y="-20" dx="2.54" dy="1.27" layer="1"/>
+<smd name="14" x="1" y="-16" dx="2.54" dy="1.27" layer="1"/>
+<smd name="13" x="1" y="-12" dx="2.54" dy="1.27" layer="1"/>
+<smd name="12" x="1" y="-8" dx="2.54" dy="1.27" layer="1"/>
+<smd name="11" x="1" y="-4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="10" x="1" y="0" dx="2.54" dy="1.27" layer="1"/>
+<smd name="9" x="1" y="4" dx="2.54" dy="1.27" layer="1"/>
+<text x="-7.65" y="-17.86" size="1.778" layer="25" rot="R90">RF4463F30</text>
+<circle x="-16" y="-26" radius="1" width="0.127" layer="21"/>
+<smd name="SHLD_1" x="-6" y="9" dx="2.54" dy="2.54" layer="1"/>
+<smd name="SHLD_2" x="-10.5" y="-29" dx="2.54" dy="2.54" layer="1"/>
+<wire x1="-19" y1="9" x2="-9" y2="9" width="0.1524" layer="21"/>
+<wire x1="-3" y1="9" x2="1" y2="9" width="0.1524" layer="21"/>
+<wire x1="-19" y1="6" x2="-19" y2="9" width="0.1524" layer="21"/>
+<wire x1="-19" y1="2.5" x2="-19" y2="1.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-1.5" x2="-19" y2="-2.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-5.5" x2="-19" y2="-6.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-9.5" x2="-19" y2="-10.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-13.5" x2="-19" y2="-14.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-17.5" x2="-19" y2="-18.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-21.5" x2="-19" y2="-22.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-26" x2="-19" y2="-29" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-29" x2="-13" y2="-29" width="0.1524" layer="21"/>
+<wire x1="-8" y1="-29" x2="1" y2="-29" width="0.1524" layer="21"/>
+<wire x1="1" y1="-29" x2="1" y2="-26" width="0.1524" layer="21"/>
+<wire x1="1" y1="-22.5" x2="1" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-18.5" x2="1" y2="-17.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-14.5" x2="1" y2="-13.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-10.5" x2="1" y2="-9.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-6.5" x2="1" y2="-5.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-2.5" x2="1" y2="-1.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="1.5" x2="1" y2="2.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="6" x2="1" y2="9" width="0.1524" layer="21"/>
+<pad name="SHLD_4" x="-14.25" y="-15.5" drill="1" shape="long" rot="R90" thermals="no"/>
+<pad name="SHLD_3" x="-14.25" y="-12" drill="1" shape="long" rot="R90" thermals="no"/>
+</package>
+<package name="STM_NUCLEO32">
+<pad name="1" x="-7.62" y="17.78" drill="0.9" shape="offset"/>
+<pad name="2" x="-7.62" y="15.24" drill="0.9" shape="offset"/>
+<pad name="3" x="-7.62" y="12.7" drill="0.9" shape="offset"/>
+<pad name="4" x="-7.62" y="10.16" drill="0.9" shape="offset"/>
+<pad name="5" x="-7.62" y="7.62" drill="0.9" shape="offset"/>
+<pad name="6" x="-7.62" y="5.08" drill="0.9" shape="offset"/>
+<pad name="7" x="-7.62" y="2.54" drill="0.9" shape="offset"/>
+<pad name="8" x="-7.62" y="0" drill="0.9" shape="offset"/>
+<pad name="9" x="-7.62" y="-2.54" drill="0.9" shape="offset"/>
+<pad name="10" x="-7.62" y="-5.08" drill="0.9" shape="offset"/>
+<pad name="11" x="-7.62" y="-7.62" drill="0.9" shape="offset"/>
+<pad name="12" x="-7.62" y="-10.16" drill="0.9" shape="offset"/>
+<pad name="13" x="-7.62" y="-12.7" drill="0.9" shape="offset"/>
+<pad name="18" x="7.62" y="-12.7" drill="0.9" shape="offset" rot="R180"/>
+<pad name="19" x="7.62" y="-10.16" drill="0.9" shape="offset" rot="R180"/>
+<pad name="20" x="7.62" y="-7.62" drill="0.9" shape="offset" rot="R180"/>
+<pad name="21" x="7.62" y="-5.08" drill="0.9" shape="offset" rot="R180"/>
+<pad name="22" x="7.62" y="-2.54" drill="0.9" shape="offset" rot="R180"/>
+<pad name="23" x="7.62" y="0" drill="0.9" shape="offset" rot="R180"/>
+<pad name="24" x="7.62" y="2.54" drill="0.9" shape="offset" rot="R180"/>
+<pad name="25" x="7.62" y="5.08" drill="0.9" shape="offset" rot="R180"/>
+<pad name="26" x="7.62" y="7.62" drill="0.9" shape="offset" rot="R180"/>
+<pad name="27" x="7.62" y="10.16" drill="0.9" shape="offset" rot="R180"/>
+<pad name="28" x="7.62" y="12.7" drill="0.9" shape="offset" rot="R180"/>
+<pad name="29" x="7.62" y="15.24" drill="0.9" shape="offset" rot="R180"/>
+<pad name="30" x="7.62" y="17.78" drill="0.9" shape="offset" rot="R180"/>
+<pad name="14" x="-7.62" y="-15.24" drill="0.9" shape="offset"/>
+<pad name="15" x="-7.62" y="-17.78" drill="0.9" shape="offset"/>
+<pad name="17" x="7.62" y="-15.24" drill="0.9" shape="offset" rot="R180"/>
+<pad name="16" x="7.62" y="-17.78" drill="0.9" shape="offset" rot="R180"/>
+<text x="3.175" y="-4.445" size="2.54" layer="21" rot="R90">NUCLEO
+L432KC</text>
+<text x="-6.35" y="20.955" size="1.778" layer="21">D1</text>
+<text x="3.175" y="20.955" size="1.778" layer="21">VIN</text>
+<text x="-5.715" y="-22.225" size="1.778" layer="21">D12</text>
+<text x="1.905" y="-22.225" size="1.778" layer="21">D13</text>
+<pad name="SHLD" x="3.175" y="-25.4" drill="0.9" shape="long"/>
+<wire x1="-9.525" y1="-24.13" x2="-9.525" y2="-21.59" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="27.305" x2="-9.525" y2="25.4" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="27.305" x2="-7.62" y2="27.305" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="27.305" x2="7.62" y2="27.305" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="-24.13" x2="-7.62" y2="-24.13" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="-24.13" x2="9.525" y2="-24.13" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="-24.13" x2="9.525" y2="-22.225" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="25.4" x2="9.525" y2="27.305" width="0.1524" layer="21"/>
+</package>
+<package name="VOLT_REGUL">
+<pad name="IN-" x="-8.5" y="20" drill="1" shape="offset"/>
+<pad name="IN+" x="8.5" y="20" drill="1" shape="offset" rot="R180"/>
+<pad name="OUT-" x="-8.5" y="-19.5" drill="1" shape="offset"/>
+<pad name="OUT+" x="8.5" y="-19.5" drill="1" shape="offset" rot="R180"/>
+<wire x1="10.5" y1="22" x2="-10.5" y2="22" width="0.1524" layer="21"/>
+<wire x1="-10.5" y1="22" x2="-10.5" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="-10.5" y1="-21.5" x2="10.5" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="10.5" y1="-21.5" x2="10.5" y2="22" width="0.1524" layer="21"/>
+<text x="2" y="-7" size="1.778" layer="21" rot="R90">VOLTAGE 
+REGULATOR</text>
+<text x="-8.5" y="16" size="1.778" layer="21">IN -</text>
+<text x="4" y="16" size="1.778" layer="21">IN +</text>
+<text x="8" y="-16.5" size="1.778" layer="21" rot="R90">OUT +</text>
+<text x="-6.5" y="-17" size="1.778" layer="21" rot="R90">OUT -</text>
+<rectangle x1="3.81" y1="-16.51" x2="10.16" y2="-1.27" layer="41"/>
+</package>
+<package name="POWER_CABLES">
+<pad name="P$1" x="-1.27" y="0" drill="1.524" shape="offset" rot="R180"/>
+<pad name="P$2" x="3.175" y="0" drill="1.524" shape="offset"/>
+<text x="-2.54" y="1.27" size="1.016" layer="21">+</text>
+<text x="3.175" y="1.27" size="1.27" layer="21">-</text>
+<text x="7.62" y="0" size="1.27" layer="25">&gt;NAME</text>
+</package>
+<package name="TO220">
+<description>&lt;b&gt;VOLTAGE REGULATOR&lt;/b&gt;</description>
+<wire x1="5.08" y1="-1.143" x2="5.08" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-4.318" x2="5.08" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-4.318" x2="-4.826" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-4.064" x2="-4.826" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-4.064" x2="-5.08" y2="-1.143" width="0.1524" layer="21"/>
+<circle x="-4.6228" y="-3.7084" radius="0.254" width="0" layer="21"/>
+<pad name="1" x="-2.54" y="-2.54" drill="1" shape="long" rot="R90"/>
+<pad name="2" x="0" y="-2.54" drill="1" shape="long" rot="R90"/>
+<pad name="3" x="2.54" y="-2.54" drill="1" shape="long" rot="R90"/>
+<text x="-5.08" y="-6.0452" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<rectangle x1="-5.334" y1="-1.27" x2="-3.429" y2="0" layer="21"/>
+<rectangle x1="-3.429" y1="-0.762" x2="-1.651" y2="0" layer="21"/>
+<rectangle x1="-1.651" y1="-1.27" x2="-0.889" y2="0" layer="21"/>
+<rectangle x1="-0.889" y1="-0.762" x2="0.889" y2="0" layer="21"/>
+<rectangle x1="0.889" y1="-1.27" x2="1.651" y2="0" layer="21"/>
+<rectangle x1="1.651" y1="-0.762" x2="3.429" y2="0" layer="21"/>
+<rectangle x1="3.429" y1="-1.27" x2="5.334" y2="0" layer="21"/>
+<rectangle x1="-3.429" y1="-1.27" x2="-1.651" y2="-0.762" layer="51"/>
+<rectangle x1="-0.889" y1="-1.27" x2="0.889" y2="-0.762" layer="51"/>
+<rectangle x1="1.651" y1="-1.27" x2="3.429" y2="-0.762" layer="51"/>
+</package>
+<package name="3,6-PAD">
+<description>&lt;b&gt;MOUNTING PAD&lt;/b&gt; 3.6 mm, round</description>
+<wire x1="-2.159" y1="0" x2="0" y2="-2.159" width="2.4892" layer="51" curve="90" cap="flat"/>
+<wire x1="0" y1="2.159" x2="2.159" y2="0" width="2.4892" layer="51" curve="-90" cap="flat"/>
+<circle x="0" y="0" radius="3.429" width="0.1524" layer="21"/>
+<circle x="0" y="0" radius="0.762" width="0.4572" layer="51"/>
+<circle x="0" y="0" radius="3.683" width="1.397" layer="39"/>
+<circle x="0" y="0" radius="3.683" width="1.397" layer="40"/>
+<circle x="0" y="0" radius="3.556" width="1.016" layer="43"/>
+<circle x="0" y="0" radius="1.9" width="0.2032" layer="21"/>
+<pad name="B3,6" x="0" y="0" drill="3.6" diameter="5.842" thermals="no"/>
+</package>
+<package name="BU-SMA-H">
+<description>FEMALE &lt;b&gt;SMA CONNECTOR&lt;/b&gt;&lt;p&gt;
+Radiall&lt;p&gt;</description>
+<wire x1="-1.1" y1="3.2" x2="1.1" y2="3.2" width="0.2032" layer="21"/>
+<wire x1="3.2" y1="1.1" x2="3.2" y2="-1.1" width="0.2032" layer="21"/>
+<wire x1="1.1" y1="-3.2" x2="-1.1" y2="-3.2" width="0.2032" layer="21"/>
+<wire x1="-3.2" y1="-1.1" x2="-3.2" y2="1.1" width="0.2032" layer="21"/>
+<wire x1="-3.1999" y1="3.1999" x2="3.2" y2="3.2" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="3.2" x2="3.2" y2="2.9" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="2.9" x2="3.2" y2="-2.9" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="-2.9" x2="3.1999" y2="-3.1999" width="0.2032" layer="51"/>
+<wire x1="3.1999" y1="-3.1999" x2="-3.2" y2="-3.2" width="0.2032" layer="51"/>
+<wire x1="-3.2" y1="-3.2" x2="-3.1999" y2="3.1999" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="2.9" x2="4.3" y2="2.9" width="0.2032" layer="51"/>
+<wire x1="4.3" y1="2.9" x2="8.3" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="2.9" x2="8.6" y2="3.4" width="0.2032" layer="21"/>
+<wire x1="10.7" y1="3.4" x2="11" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="11" y1="2.9" x2="11.6" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="11.6" y1="-2.9" x2="11.6" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.6" y1="3.4" x2="10.7" y2="3.4" width="0.2032" layer="21"/>
+<wire x1="3.2" y1="-2.9" x2="4.3" y2="-2.9" width="0.2032" layer="51"/>
+<wire x1="4.3" y1="-2.9" x2="8.3" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="-2.9" x2="8.6" y2="-3.4" width="0.2032" layer="21"/>
+<wire x1="10.7" y1="-3.4" x2="11" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="11" y1="-2.9" x2="11.6" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="8.6" y1="-3.4" x2="10.7" y2="-3.4" width="0.2032" layer="21"/>
+<wire x1="11" y1="-2.9" x2="11" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="-2.9" x2="8.3" y2="2.9" width="0.2032" layer="21"/>
+<circle x="0" y="0" radius="3.1999" width="0.2032" layer="51"/>
+<circle x="0" y="0" radius="1.7" width="0.2032" layer="21"/>
+<pad name="1" x="0" y="0" drill="1.524"/>
+<pad name="2" x="-2.5499" y="2.5499" drill="1.778"/>
+<pad name="3" x="2.5499" y="2.5499" drill="1.778"/>
+<pad name="4" x="2.5499" y="-2.5499" drill="1.778"/>
+<pad name="5" x="-2.5499" y="-2.5499" drill="1.778"/>
+<text x="-2.54" y="4.445" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.175" y="-5.715" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="W5500LITE">
+<dimension x1="-6.35" y1="-12.7" x2="16.51" y2="-12.7" x3="5.08" y3="-13.97" textsize="1.778" layer="48"/>
+<dimension x1="-6.35" y1="-12.7" x2="-6.35" y2="12.7" x3="-11.43" y3="0" textsize="1.778" layer="48"/>
+<wire x1="-6.35" y1="12.7" x2="-6.35" y2="-12.7" width="0.1524" layer="49"/>
+<wire x1="-6.35" y1="-12.7" x2="16.51" y2="-12.7" width="0.1524" layer="49"/>
+<wire x1="16.51" y1="-12.7" x2="16.51" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="-6.35" y1="12.7" x2="-1.27" y2="12.7" width="0.1524" layer="49"/>
+<pad name="P$1" x="-5.08" y="-6.35" drill="0.9" shape="long"/>
+<pad name="P$2" x="-5.08" y="-3.81" drill="0.9" shape="long"/>
+<pad name="P$3" x="-5.08" y="-1.27" drill="0.9" shape="long"/>
+<pad name="P$4" x="-5.08" y="1.27" drill="0.9" shape="long"/>
+<pad name="P$5" x="-5.08" y="3.81" drill="0.9" shape="long"/>
+<pad name="P$6" x="-5.08" y="6.35" drill="0.9" shape="long"/>
+<pad name="P$7" x="15.24" y="6.35" drill="0.9" shape="long"/>
+<pad name="P$8" x="15.24" y="3.81" drill="0.9" shape="long"/>
+<pad name="P$9" x="15.24" y="1.27" drill="0.9" shape="long"/>
+<pad name="P$10" x="15.24" y="-1.27" drill="0.9" shape="long"/>
+<pad name="P$11" x="15.24" y="-3.81" drill="0.9" shape="long"/>
+<pad name="P$12" x="15.24" y="-6.35" drill="0.9" shape="long"/>
+<wire x1="-1.27" y1="12.7" x2="11.43" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="11.43" y1="12.7" x2="16.51" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="-1.27" y1="12.7" x2="-1.27" y2="16.51" width="0.1524" layer="49"/>
+<wire x1="-1.27" y1="16.51" x2="11.43" y2="16.51" width="0.1524" layer="49"/>
+<wire x1="11.43" y1="16.51" x2="11.43" y2="12.7" width="0.1524" layer="49"/>
+<text x="12.7" y="-10.16" size="1.778" layer="26" rot="MR0">WS5500 LITE</text>
+<text x="10.16" y="8.89" size="1.778" layer="26" rot="MR0">USR-ES1</text>
+<wire x1="-6.35" y1="-12.7" x2="-6.35" y2="12.7" width="0.1524" layer="22"/>
+<wire x1="-6.35" y1="12.7" x2="16.51" y2="12.7" width="0.1524" layer="22"/>
+<wire x1="16.51" y1="12.7" x2="16.51" y2="-12.7" width="0.1524" layer="22"/>
+<wire x1="16.51" y1="-12.7" x2="-6.35" y2="-12.7" width="0.1524" layer="22"/>
+</package>
+<package name="D/7343-31W">
+<description>&lt;b&gt;Chip Capacitor Type KEMET D / EIA 7343-21&lt;/b&gt;&lt;p&gt;
+KEMET V / EIA 7343-20, KEMET X / EIA 7343-43 Wafe solder</description>
+<wire x1="-3.45" y1="2.1" x2="3.45" y2="2.1" width="0.1016" layer="51"/>
+<wire x1="3.45" y1="2.1" x2="3.45" y2="-2.1" width="0.1016" layer="51"/>
+<wire x1="3.45" y1="-2.1" x2="-3.45" y2="-2.1" width="0.1016" layer="51"/>
+<wire x1="-3.45" y1="-2.1" x2="-3.45" y2="2.1" width="0.1016" layer="51"/>
+<smd name="+" x="3.375" y="0" dx="2.95" dy="2.7" layer="1"/>
+<smd name="-" x="-3.375" y="0" dx="2.95" dy="2.7" layer="1"/>
+<text x="-3.65" y="2.3" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.65" y="-3.575" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.65" y1="-1.2" x2="-3.5" y2="1.2" layer="51"/>
+<rectangle x1="3.5" y1="-1.2" x2="3.65" y2="1.2" layer="51"/>
+<rectangle x1="2.675" y1="-2.125" x2="3.15" y2="2.125" layer="51"/>
+<wire x1="-3.4925" y1="2.2225" x2="1.5875" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="2.2225" x2="3.4925" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="-3.4925" y1="-2.2225" x2="1.5875" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-2.2225" x2="3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="2.2225" x2="1.5875" y2="-2.2225" width="0.3048" layer="21"/>
+<wire x1="-3.4925" y1="1.5875" x2="-3.4925" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="3.4925" y1="2.2225" x2="3.4925" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-3.4925" y1="-1.5875" x2="-3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="3.4925" y1="-1.5875" x2="3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+</package>
+<package name="CT6032">
+<description>&lt;b&gt;TANTALUM CAPACITOR&lt;/b&gt;</description>
+<wire x1="-4.473" y1="1.983" x2="4.473" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="-1.983" x2="-4.473" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-4.473" y1="-1.983" x2="-4.473" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="1.983" x2="4.473" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-2.932" y1="-1.637" x2="-2.932" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="-3.073" y1="1.067" x2="-3.073" y2="-1.067" width="0.1524" layer="51"/>
+<wire x1="2.957" y1="1.637" x2="-2.932" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="2.957" y1="-1.637" x2="-2.932" y2="-1.637" width="0.2032" layer="51"/>
+<wire x1="3.073" y1="1.067" x2="3.073" y2="-1.067" width="0.1524" layer="51"/>
+<wire x1="2.957" y1="-1.637" x2="2.957" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="-1.18" y1="0" x2="-2.45" y2="0" width="0.2032" layer="51"/>
+<wire x1="-1.8" y1="0.63" x2="-1.8" y2="-0.64" width="0.2032" layer="51"/>
+<smd name="+" x="-2.5" y="0" dx="2.6" dy="2.2" layer="1"/>
+<smd name="-" x="2.5" y="0" dx="2.6" dy="2.2" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+<wire x1="-2.8575" y1="1.27" x2="-2.8575" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-2.8575" y1="1.5875" x2="-0.9525" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="1.5875" x2="2.8575" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="1.5875" x2="2.8575" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="-1.27" x2="2.8575" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="-1.5875" x2="-0.9525" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="-1.5875" x2="-2.8575" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="-2.8575" y1="-1.5875" x2="-2.8575" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="1.5875" x2="-0.9525" y2="-1.5875" width="0.254" layer="21"/>
+</package>
+<package name="B/3528-21W">
+<description>&lt;b&gt;Chip Capacitor Type KEMET B / EIA 3528-21 Wave solder&lt;/b&gt;&lt;p&gt;
+KEMET T / EIA 3528-12</description>
+<wire x1="-1.6" y1="1.2" x2="1.6" y2="1.2" width="0.1016" layer="51"/>
+<wire x1="1.6" y1="1.2" x2="1.6" y2="-1.2" width="0.1016" layer="51"/>
+<wire x1="1.6" y1="-1.2" x2="-1.6" y2="-1.2" width="0.1016" layer="51"/>
+<wire x1="-1.6" y1="-1.2" x2="-1.6" y2="1.2" width="0.1016" layer="51"/>
+<smd name="+" x="1.9425" y="0" dx="1.651" dy="1.8" layer="1"/>
+<smd name="-" x="-1.625" y="0" dx="2.15" dy="1.8" layer="1"/>
+<text x="-1.95" y="1.6" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.95" y="-2.925" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.75" y1="-0.6" x2="-1.625" y2="0.6" layer="51"/>
+<rectangle x1="1.625" y1="-0.6" x2="1.75" y2="0.6" layer="51"/>
+<rectangle x1="0.95" y1="-1.225" x2="1.25" y2="1.225" layer="51"/>
+<wire x1="-1.5875" y1="1.27" x2="0.9525" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="1.27" x2="1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="0.9525" x2="1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="0.9525" x2="-1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.9525" x2="-1.5875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-1.27" x2="0.9525" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="-1.27" x2="1.5875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-1.27" x2="1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="1.27" x2="0.9525" y2="-1.27" width="0.254" layer="21"/>
+</package>
+<package name="CT3216">
+<description>&lt;b&gt;TANTALUM CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.973" y1="1.483" x2="2.973" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-1.483" x2="-2.973" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-1.483" x2="-2.973" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="1.483" x2="2.973" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-1.651" y1="0.559" x2="-1.651" y2="-0.559" width="0.1524" layer="51"/>
+<wire x1="1.651" y1="0.559" x2="1.651" y2="-0.559" width="0.1524" layer="51"/>
+<wire x1="-1.535" y1="0.798" x2="-1.535" y2="-0.798" width="0.2032" layer="51"/>
+<wire x1="-1.535" y1="-0.798" x2="1.535" y2="-0.798" width="0.2032" layer="51"/>
+<wire x1="1.535" y1="-0.798" x2="1.535" y2="0.798" width="0.2032" layer="51"/>
+<wire x1="1.535" y1="0.798" x2="-1.535" y2="0.798" width="0.2032" layer="51"/>
+<wire x1="-0.7" y1="0" x2="-1.26" y2="0" width="0.2032" layer="51"/>
+<wire x1="-0.97" y1="0.26" x2="-0.97" y2="-0.3" width="0.2032" layer="51"/>
+<smd name="+" x="-1.7175" y="0" dx="1.524" dy="1.2" layer="1"/>
+<smd name="-" x="1.4" y="0" dx="2" dy="1.2" layer="1"/>
+<text x="-2.54" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.1999" y1="-0.5999" x2="0.1999" y2="0.5999" layer="35"/>
+<wire x1="1.5875" y1="0.635" x2="1.5875" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="0.9525" x2="-0.635" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="0.9525" x2="-1.5875" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="0.9525" x2="-1.5875" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.635" x2="-1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.9525" x2="-0.635" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="-0.9525" x2="1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-0.9525" x2="1.5875" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="0.9525" x2="-0.635" y2="-0.9525" width="0.254" layer="21"/>
+</package>
+<package name="SO08">
+<description>&lt;b&gt;Small Outline Package&lt;/b&gt; SOIC 150 mil</description>
+<wire x1="2.159" y1="1.9558" x2="-2.159" y2="1.9558" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.9558" x2="2.54" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.54" y1="1.5748" x2="-2.159" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="1.9558" x2="2.54" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.54" y1="-1.5748" x2="-2.159" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.159" y1="-1.9558" x2="2.159" y2="-1.9558" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-1.5748" x2="2.54" y2="1.5748" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="1.5748" x2="-2.54" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.508" x2="-2.54" y2="-1.5748" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-2.54" y1="-1.6002" x2="2.54" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="8" x="-1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="2" x="-0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="3" x="0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="7" x="-0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="6" x="0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="4" x="1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="5" x="1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<text x="3.937" y="-2.032" size="1.27" layer="27" ratio="10" rot="R90">&gt;VALUE</text>
+<rectangle x1="1.651" y1="1.9558" x2="2.159" y2="3.0988" layer="51"/>
+<rectangle x1="-2.159" y1="-3.0988" x2="-1.651" y2="-1.9558" layer="51"/>
+<rectangle x1="-0.889" y1="-3.0988" x2="-0.381" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="-3.0734" x2="0.889" y2="-1.9304" layer="51"/>
+<rectangle x1="1.651" y1="-3.0988" x2="2.159" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="1.9558" x2="0.889" y2="3.0988" layer="51"/>
+<rectangle x1="-0.889" y1="1.9558" x2="-0.381" y2="3.0988" layer="51"/>
+<rectangle x1="-2.159" y1="1.9558" x2="-1.651" y2="3.0988" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="NUCLEO_STM32L432KC">
+<wire x1="-15.24" y1="38.1" x2="-15.24" y2="-38.1" width="0.254" layer="94"/>
+<wire x1="-15.24" y1="-38.1" x2="17.78" y2="-38.1" width="0.254" layer="94"/>
+<wire x1="17.78" y1="-38.1" x2="17.78" y2="38.1" width="0.254" layer="94"/>
+<wire x1="17.78" y1="38.1" x2="-15.24" y2="38.1" width="0.254" layer="94"/>
+<pin name="D1_PA9" x="-20.32" y="35.56" length="middle"/>
+<pin name="D0_PA10" x="-20.32" y="30.48" length="middle"/>
+<pin name="RESET" x="-20.32" y="25.4" length="middle"/>
+<pin name="GND1" x="-20.32" y="20.32" length="middle"/>
+<pin name="D2_PA12" x="-20.32" y="15.24" length="middle"/>
+<pin name="D3_PB0" x="-20.32" y="10.16" length="middle"/>
+<pin name="D4_PB7" x="-20.32" y="5.08" length="middle"/>
+<pin name="D5_PB6" x="-20.32" y="0" length="middle"/>
+<pin name="D6_PB1" x="-20.32" y="-5.08" length="middle"/>
+<pin name="D7_PC14" x="-20.32" y="-10.16" length="middle"/>
+<pin name="D8_PC15" x="-20.32" y="-15.24" length="middle"/>
+<pin name="D9_PA8" x="-20.32" y="-20.32" length="middle"/>
+<pin name="D10_PA11" x="-20.32" y="-25.4" length="middle"/>
+<pin name="D11_PB5" x="-20.32" y="-30.48" length="middle"/>
+<pin name="D12_PB4" x="-20.32" y="-35.56" length="middle"/>
+<pin name="D13_PB3" x="22.86" y="-35.56" length="middle" rot="R180"/>
+<pin name="3V3" x="22.86" y="-30.48" length="middle" rot="R180"/>
+<pin name="AREF" x="22.86" y="-25.4" length="middle" rot="R180"/>
+<pin name="A0_PA0" x="22.86" y="-20.32" length="middle" rot="R180"/>
+<pin name="PA_PA1" x="22.86" y="-15.24" length="middle" rot="R180"/>
+<pin name="A2_PA3" x="22.86" y="-10.16" length="middle" rot="R180"/>
+<pin name="A3_PA4" x="22.86" y="-5.08" length="middle" rot="R180"/>
+<pin name="A4_PA5" x="22.86" y="0" length="middle" rot="R180"/>
+<pin name="A5_PA6" x="22.86" y="5.08" length="middle" rot="R180"/>
+<pin name="A6_PA7" x="22.86" y="10.16" length="middle" rot="R180"/>
+<pin name="A7_PA2" x="22.86" y="15.24" length="middle" rot="R180"/>
+<pin name="5V" x="22.86" y="20.32" length="middle" rot="R180"/>
+<pin name="RESET2" x="22.86" y="25.4" length="middle" rot="R180"/>
+<pin name="GND2" x="22.86" y="30.48" length="middle" rot="R180"/>
+<pin name="VIN" x="22.86" y="35.56" length="middle" rot="R180"/>
+<pin name="SHLD" x="2.54" y="-43.18" length="middle" rot="R90"/>
+<text x="-12.7" y="38.1" size="2.54" layer="97">NUCLEO L432KC</text>
+</symbol>
+<symbol name="RF4463F30">
+<wire x1="-17.78" y1="-20.32" x2="-17.78" y2="25.4" width="0.254" layer="94"/>
+<wire x1="-17.78" y1="25.4" x2="12.7" y2="25.4" width="0.254" layer="94"/>
+<wire x1="12.7" y1="25.4" x2="12.7" y2="-20.32" width="0.254" layer="94"/>
+<wire x1="12.7" y1="-20.32" x2="-17.78" y2="-20.32" width="0.254" layer="94"/>
+<pin name="GND1" x="-22.86" y="20.32" length="middle"/>
+<pin name="CS" x="-22.86" y="15.24" length="middle"/>
+<pin name="IRQ" x="-22.86" y="10.16" length="middle"/>
+<pin name="SDN" x="-22.86" y="5.08" length="middle"/>
+<pin name="NC1" x="-22.86" y="0" length="middle"/>
+<pin name="NC2" x="-22.86" y="-5.08" length="middle"/>
+<pin name="GND2" x="-22.86" y="-10.16" length="middle"/>
+<pin name="VCC" x="-22.86" y="-15.24" length="middle"/>
+<pin name="ANT" x="17.78" y="-15.24" length="middle" rot="R180"/>
+<pin name="RF_GND" x="17.78" y="-10.16" length="middle" rot="R180"/>
+<pin name="NC3" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="GPIO_0" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="GPIO_1" x="17.78" y="5.08" length="middle" rot="R180"/>
+<pin name="SDO" x="17.78" y="10.16" length="middle" rot="R180"/>
+<pin name="SDI" x="17.78" y="15.24" length="middle" rot="R180"/>
+<pin name="CLK" x="17.78" y="20.32" length="middle" rot="R180"/>
+<pin name="SHLD_1" x="-2.54" y="30.48" length="middle" rot="R270"/>
+<pin name="SHLD_2" x="-2.54" y="-25.4" length="middle" rot="R90"/>
+<text x="-10.16" y="2.54" size="2.54" layer="97">SI4463</text>
+<pin name="SHLD_4" x="5.08" y="-25.4" length="middle" rot="R90"/>
+<pin name="SHLD_3" x="5.08" y="30.48" length="middle" rot="R270"/>
+</symbol>
+<symbol name="VOLT_REGUL">
+<wire x1="-12.7" y1="10.16" x2="20.32" y2="10.16" width="0.1524" layer="94"/>
+<wire x1="20.32" y1="10.16" x2="20.32" y2="-10.16" width="0.1524" layer="94"/>
+<wire x1="20.32" y1="-10.16" x2="-12.7" y2="-10.16" width="0.1524" layer="94"/>
+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.1524" layer="94"/>
+<pin name="IN+" x="-17.78" y="7.62" length="middle"/>
+<pin name="IN-" x="-17.78" y="-7.62" length="middle"/>
+<pin name="OUT+" x="25.4" y="7.62" length="middle" rot="R180"/>
+<pin name="OUT-" x="25.4" y="-7.62" length="middle" rot="R180"/>
+<text x="-10.16" y="-2.54" size="2.54" layer="97">step down
+voltage regulator</text>
+</symbol>
+<symbol name="POWER_CABLES">
+<wire x1="-2.54" y1="5.08" x2="2.54" y2="5.08" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="5.08" x2="2.54" y2="-5.08" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="-5.08" x2="-2.54" y2="-5.08" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="-5.08" x2="-2.54" y2="5.08" width="0.1524" layer="94"/>
+<pin name="+" x="7.62" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="7.62" y="-2.54" length="middle" rot="R180"/>
+</symbol>
+<symbol name="REGUL">
+<wire x1="-5.08" y1="5.08" x2="7.62" y2="5.08" width="0.1524" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-5.08" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="-5.08" y1="-2.54" x2="-5.08" y2="5.08" width="0.1524" layer="94"/>
+<pin name="IN" x="-10.16" y="2.54" length="middle"/>
+<pin name="GND" x="0" y="-7.62" length="middle" rot="R90"/>
+<pin name="OUT" x="12.7" y="2.54" length="middle" rot="R180"/>
+<text x="-2.54" y="5.08" size="1.778" layer="97">&gt;NAME</text>
+</symbol>
+<symbol name="MOUNT-PAD">
+<wire x1="0.254" y1="2.032" x2="2.032" y2="0.254" width="1.016" layer="94" curve="-75.749967" cap="flat"/>
+<wire x1="-2.032" y1="0.254" x2="-0.254" y2="2.032" width="1.016" layer="94" curve="-75.749967" cap="flat"/>
+<wire x1="-2.032" y1="-0.254" x2="-0.254" y2="-2.032" width="1.016" layer="94" curve="75.749967" cap="flat"/>
+<wire x1="0.254" y1="-2.032" x2="2.032" y2="-0.254" width="1.016" layer="94" curve="75.749967" cap="flat"/>
+<circle x="0" y="0" radius="1.524" width="0.0508" layer="94"/>
+<text x="2.794" y="0.5842" size="1.778" layer="95">&gt;NAME</text>
+<text x="2.794" y="-2.4638" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="MOUNT" x="-2.54" y="0" visible="off" length="short" direction="pas"/>
+</symbol>
+<symbol name="BNC-FGND-1">
+<wire x1="0" y1="-2.54" x2="-0.762" y2="-1.778" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-0.508" y2="0" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="0.508" x2="-0.762" y2="0.508" width="0.254" layer="94"/>
+<wire x1="-0.762" y1="0.508" x2="-0.508" y2="0" width="0.254" layer="94"/>
+<wire x1="-0.508" y1="0" x2="-0.762" y2="-0.508" width="0.254" layer="94"/>
+<wire x1="-0.762" y1="-0.508" x2="-2.54" y2="-0.508" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="2.54" x2="0" y2="0.508" width="0.3048" layer="94" curve="-79.611142" cap="flat"/>
+<wire x1="-2.54" y1="-2.54" x2="0" y2="-0.508" width="0.3048" layer="94" curve="79.611142" cap="flat"/>
+<text x="-2.54" y="-5.08" size="1.778" layer="96">&gt;VALUE</text>
+<text x="-2.54" y="3.302" size="1.778" layer="95">&gt;NAME</text>
+<pin name="1" x="2.54" y="0" visible="off" length="short" direction="pas" rot="R180"/>
+<pin name="2" x="2.54" y="-2.54" visible="off" length="short" direction="pas" rot="R180"/>
+</symbol>
+<symbol name="W5500LITE">
+<wire x1="-27.94" y1="30.48" x2="-27.94" y2="-5.08" width="0.1524" layer="94"/>
+<wire x1="-27.94" y1="-5.08" x2="-27.94" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="-27.94" y1="-7.62" x2="0" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="0" y1="-7.62" x2="0" y2="30.48" width="0.1524" layer="94"/>
+<wire x1="0" y1="30.48" x2="-27.94" y2="30.48" width="0.1524" layer="94"/>
+<pin name="GND" x="0" y="22.86" length="middle"/>
+<pin name="3V3" x="0" y="17.78" length="middle"/>
+<pin name="3V3." x="0" y="12.7" length="middle"/>
+<pin name="NC" x="0" y="7.62" length="middle"/>
+<pin name="RST" x="0" y="2.54" length="middle"/>
+<pin name="MISO" x="0" y="-2.54" length="middle"/>
+<pin name="GND," x="-27.94" y="22.86" length="middle" rot="R180"/>
+<pin name="GND." x="-27.94" y="17.78" length="middle" rot="R180"/>
+<pin name="MOSI" x="-27.94" y="12.7" length="middle" rot="R180"/>
+<pin name="SLCK" x="-27.94" y="7.62" length="middle" rot="R180"/>
+<pin name="CS" x="-27.94" y="2.54" length="middle" rot="R180"/>
+<pin name="INT" x="-27.94" y="-2.54" length="middle" rot="R180"/>
+</symbol>
+<symbol name="CPOL-US">
+<wire x1="-2.54" y1="0" x2="2.54" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="-1.016" x2="0" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="0" y1="-1" x2="2.4892" y2="-1.8542" width="0.254" layer="94" curve="-37.878202" cap="flat"/>
+<wire x1="-2.4669" y1="-1.8504" x2="0" y2="-1.0161" width="0.254" layer="94" curve="-37.376341" cap="flat"/>
+<text x="1.016" y="0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.016" y="-4.191" size="1.778" layer="96">&gt;VALUE</text>
+<text x="0" y="2.54" size="0.4064" layer="99" align="center">SpiceOrder 1</text>
+<text x="0" y="-5.08" size="0.4064" layer="99" align="center">SpiceOrder 2</text>
+<rectangle x1="-2.253" y1="0.668" x2="-1.364" y2="0.795" layer="94"/>
+<rectangle x1="-1.872" y1="0.287" x2="-1.745" y2="1.176" layer="94"/>
+<pin name="+" x="0" y="2.54" visible="off" length="short" direction="pas" swaplevel="1" rot="R270"/>
+<pin name="-" x="0" y="-5.08" visible="off" length="short" direction="pas" swaplevel="1" rot="R90"/>
+</symbol>
+<symbol name="SPI_SRAM">
+<wire x1="-10.16" y1="15.24" x2="15.24" y2="15.24" width="0.1524" layer="94"/>
+<wire x1="15.24" y1="15.24" x2="15.24" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="15.24" y1="-7.62" x2="-10.16" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="-10.16" y1="-7.62" x2="-10.16" y2="15.24" width="0.1524" layer="94"/>
+<pin name="CS" x="-15.24" y="12.7" length="middle"/>
+<pin name="MISO" x="-15.24" y="7.62" length="middle"/>
+<pin name="SIO2" x="-15.24" y="2.54" length="middle"/>
+<pin name="GND" x="-15.24" y="-2.54" length="middle"/>
+<pin name="MOSI" x="20.32" y="-2.54" length="middle" rot="R180"/>
+<pin name="SCK" x="20.32" y="2.54" length="middle" rot="R180"/>
+<pin name="HOLD" x="20.32" y="7.62" length="middle" rot="R180"/>
+<pin name="VCC" x="20.32" y="12.7" length="middle" rot="R180"/>
+<text x="-7.62" y="15.24" size="1.9304" layer="97">SRAM (23LC1024)</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="NUCLEO_STM32L432KC">
+<gates>
+<gate name="G$1" symbol="NUCLEO_STM32L432KC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="STM_NUCLEO32">
+<connects>
+<connect gate="G$1" pin="3V3" pad="17"/>
+<connect gate="G$1" pin="5V" pad="27"/>
+<connect gate="G$1" pin="A0_PA0" pad="19"/>
+<connect gate="G$1" pin="A2_PA3" pad="21"/>
+<connect gate="G$1" pin="A3_PA4" pad="22"/>
+<connect gate="G$1" pin="A4_PA5" pad="23"/>
+<connect gate="G$1" pin="A5_PA6" pad="24"/>
+<connect gate="G$1" pin="A6_PA7" pad="25"/>
+<connect gate="G$1" pin="A7_PA2" pad="26"/>
+<connect gate="G$1" pin="AREF" pad="18"/>
+<connect gate="G$1" pin="D0_PA10" pad="2"/>
+<connect gate="G$1" pin="D10_PA11" pad="13"/>
+<connect gate="G$1" pin="D11_PB5" pad="14"/>
+<connect gate="G$1" pin="D12_PB4" pad="15"/>
+<connect gate="G$1" pin="D13_PB3" pad="16"/>
+<connect gate="G$1" pin="D1_PA9" pad="1"/>
+<connect gate="G$1" pin="D2_PA12" pad="5"/>
+<connect gate="G$1" pin="D3_PB0" pad="6"/>
+<connect gate="G$1" pin="D4_PB7" pad="7"/>
+<connect gate="G$1" pin="D5_PB6" pad="8"/>
+<connect gate="G$1" pin="D6_PB1" pad="9"/>
+<connect gate="G$1" pin="D7_PC14" pad="10"/>
+<connect gate="G$1" pin="D8_PC15" pad="11"/>
+<connect gate="G$1" pin="D9_PA8" pad="12"/>
+<connect gate="G$1" pin="GND1" pad="4"/>
+<connect gate="G$1" pin="GND2" pad="29"/>
+<connect gate="G$1" pin="PA_PA1" pad="20"/>
+<connect gate="G$1" pin="RESET" pad="3"/>
+<connect gate="G$1" pin="RESET2" pad="28"/>
+<connect gate="G$1" pin="SHLD" pad="SHLD"/>
+<connect gate="G$1" pin="VIN" pad="30"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="RF4463F30" prefix="RF" uservalue="yes">
+<gates>
+<gate name="SI4463" symbol="RF4463F30" x="2.54" y="0"/>
+</gates>
+<devices>
+<device name="" package="RF4463F30">
+<connects>
+<connect gate="SI4463" pin="ANT" pad="16"/>
+<connect gate="SI4463" pin="CLK" pad="9"/>
+<connect gate="SI4463" pin="CS" pad="7"/>
+<connect gate="SI4463" pin="GND1" pad="8"/>
+<connect gate="SI4463" pin="GND2" pad="2"/>
+<connect gate="SI4463" pin="GPIO_0" pad="13"/>
+<connect gate="SI4463" pin="GPIO_1" pad="12"/>
+<connect gate="SI4463" pin="IRQ" pad="6"/>
+<connect gate="SI4463" pin="NC1" pad="4"/>
+<connect gate="SI4463" pin="NC2" pad="3"/>
+<connect gate="SI4463" pin="NC3" pad="14"/>
+<connect gate="SI4463" pin="RF_GND" pad="15"/>
+<connect gate="SI4463" pin="SDI" pad="10"/>
+<connect gate="SI4463" pin="SDN" pad="5"/>
+<connect gate="SI4463" pin="SDO" pad="11"/>
+<connect gate="SI4463" pin="SHLD_1" pad="SHLD_1"/>
+<connect gate="SI4463" pin="SHLD_2" pad="SHLD_2"/>
+<connect gate="SI4463" pin="SHLD_3" pad="SHLD_3"/>
+<connect gate="SI4463" pin="SHLD_4" pad="SHLD_4"/>
+<connect gate="SI4463" pin="VCC" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="VOLT_REGUL">
+<gates>
+<gate name="G$1" symbol="VOLT_REGUL" x="-2.54" y="0"/>
+</gates>
+<devices>
+<device name="" package="VOLT_REGUL">
+<connects>
+<connect gate="G$1" pin="IN+" pad="IN+"/>
+<connect gate="G$1" pin="IN-" pad="IN-"/>
+<connect gate="G$1" pin="OUT+" pad="OUT+"/>
+<connect gate="G$1" pin="OUT-" pad="OUT-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="POWER_CABLE">
+<gates>
+<gate name="G$1" symbol="POWER_CABLES" x="-2.54" y="0"/>
+</gates>
+<devices>
+<device name="" package="POWER_CABLES">
+<connects>
+<connect gate="G$1" pin="+" pad="P$1"/>
+<connect gate="G$1" pin="GND" pad="P$2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="REGUL">
+<gates>
+<gate name="G$1" symbol="REGUL" x="-2.54" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="TO220">
+<connects>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="3"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="MOUNT_HOLE">
+<gates>
+<gate name="G$1" symbol="MOUNT-PAD" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="3,6-PAD">
+<connects>
+<connect gate="G$1" pin="MOUNT" pad="B3,6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="BU-SMA-H" prefix="X">
+<description>FEMALE &lt;b&gt;SMA CONNECTOR&lt;/b&gt;&lt;p&gt;
+Radiall&lt;p&gt;</description>
+<gates>
+<gate name="G$1" symbol="BNC-FGND-1" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="BU-SMA-H">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2 3 4 5"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="W5500_LITE">
+<gates>
+<gate name="G$1" symbol="W5500LITE" x="7.62" y="0"/>
+</gates>
+<devices>
+<device name="USR-ES1" package="W5500LITE">
+<connects>
+<connect gate="G$1" pin="3V3" pad="P$11"/>
+<connect gate="G$1" pin="3V3." pad="P$10"/>
+<connect gate="G$1" pin="CS" pad="P$5"/>
+<connect gate="G$1" pin="GND" pad="P$12"/>
+<connect gate="G$1" pin="GND," pad="P$2"/>
+<connect gate="G$1" pin="GND." pad="P$1"/>
+<connect gate="G$1" pin="INT" pad="P$6"/>
+<connect gate="G$1" pin="MISO" pad="P$7"/>
+<connect gate="G$1" pin="MOSI" pad="P$3"/>
+<connect gate="G$1" pin="NC" pad="P$9"/>
+<connect gate="G$1" pin="RST" pad="P$8"/>
+<connect gate="G$1" pin="SLCK" pad="P$4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_D/7343_31W">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="D/7343-31W">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_CT6032">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="CT6032">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_B/3528_21W">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="B/3528-21W">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_CT3216">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="CT3216">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SRAM">
+<gates>
+<gate name="G$1" symbol="SPI_SRAM" x="-2.54" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="SO08">
+<connects>
+<connect gate="G$1" pin="CS" pad="1"/>
+<connect gate="G$1" pin="GND" pad="4"/>
+<connect gate="G$1" pin="HOLD" pad="7"/>
+<connect gate="G$1" pin="MISO" pad="2"/>
+<connect gate="G$1" pin="MOSI" pad="5"/>
+<connect gate="G$1" pin="SCK" pad="6"/>
+<connect gate="G$1" pin="SIO2" pad="3"/>
+<connect gate="G$1" pin="VCC" pad="8"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="resistor" urn="urn:adsk.eagle:library:348">
+<description>&lt;b&gt;Resistors, Capacitors, Inductors&lt;/b&gt;&lt;p&gt;
+Based on the previous libraries:
+&lt;ul&gt;
+&lt;li&gt;r.lbr
+&lt;li&gt;cap.lbr 
+&lt;li&gt;cap-fe.lbr
+&lt;li&gt;captant.lbr
+&lt;li&gt;polcap.lbr
+&lt;li&gt;ipc-smd.lbr
+&lt;/ul&gt;
+All SMD packages are defined according to the IPC specifications and  CECC&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;p&gt;
+&lt;p&gt;
+for Electrolyt Capacitors see also :&lt;p&gt;
+www.bccomponents.com &lt;p&gt;
+www.panasonic.com&lt;p&gt;
+www.kemet.com&lt;p&gt;
+&lt;p&gt;
+for trimmer refence see : &lt;u&gt;www.electrospec-inc.com/cross_references/trimpotcrossref.asp&lt;/u&gt;&lt;p&gt;
+
+&lt;map name="nav_main"&gt;
+&lt;area shape="rect" coords="0,1,140,23" href="../military_specs.asp" title=""&gt;
+&lt;area shape="rect" coords="0,24,140,51" href="../about.asp" title=""&gt;
+&lt;area shape="rect" coords="1,52,140,77" href="../rfq.asp" title=""&gt;
+&lt;area shape="rect" coords="0,78,139,103" href="../products.asp" title=""&gt;
+&lt;area shape="rect" coords="1,102,138,128" href="../excess_inventory.asp" title=""&gt;
+&lt;area shape="rect" coords="1,129,138,150" href="../edge.asp" title=""&gt;
+&lt;area shape="rect" coords="1,151,139,178" href="../industry_links.asp" title=""&gt;
+&lt;area shape="rect" coords="0,179,139,201" href="../comments.asp" title=""&gt;
+&lt;area shape="rect" coords="1,203,138,231" href="../directory.asp" title=""&gt;
+&lt;area shape="default" nohref&gt;
+&lt;/map&gt;
+
+&lt;html&gt;
+
+&lt;title&gt;&lt;/title&gt;
+
+ &lt;LINK REL="StyleSheet" TYPE="text/css" HREF="style-sheet.css"&gt;
+
+&lt;body bgcolor="#ffffff" text="#000000" marginwidth="0" marginheight="0" topmargin="0" leftmargin="0"&gt;
+&lt;table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0 height="55%"&gt;
+&lt;tr valign="top"&gt;
+
+&lt;/td&gt;
+&lt;! &lt;td width="10"&gt;&amp;nbsp;&lt;/td&gt;
+&lt;td width="90%"&gt;
+
+&lt;b&gt;&lt;font color="#0000FF" size="4"&gt;TRIM-POT CROSS REFERENCE&lt;/font&gt;&lt;/b&gt;
+&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;RECTANGULAR MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BOURNS&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BI&amp;nbsp;TECH&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;DALE-VISHAY&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PHILIPS/MEPCO&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MURATA&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PANASONIC&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;SPECTROL&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MILSPEC&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;&lt;TD&gt;&amp;nbsp;&lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3 &gt;
+      3005P&lt;BR&gt;
+      3006P&lt;BR&gt;
+      3006W&lt;BR&gt;
+      3006Y&lt;BR&gt;
+      3009P&lt;BR&gt;
+      3009W&lt;BR&gt;
+      3009Y&lt;BR&gt;
+      3057J&lt;BR&gt;
+      3057L&lt;BR&gt;
+      3057P&lt;BR&gt;
+      3057Y&lt;BR&gt;
+      3059J&lt;BR&gt;
+      3059L&lt;BR&gt;
+      3059P&lt;BR&gt;
+      3059Y&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      89P&lt;BR&gt;
+      89W&lt;BR&gt;
+      89X&lt;BR&gt;
+      89PH&lt;BR&gt;
+      76P&lt;BR&gt;
+      89XH&lt;BR&gt;
+      78SLT&lt;BR&gt;
+      78L&amp;nbsp;ALT&lt;BR&gt;
+      56P&amp;nbsp;ALT&lt;BR&gt;
+      78P&amp;nbsp;ALT&lt;BR&gt;
+      T8S&lt;BR&gt;
+      78L&lt;BR&gt;
+      56P&lt;BR&gt;
+      78P&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      T18/784&lt;BR&gt;
+      783&lt;BR&gt;
+      781&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      2199&lt;BR&gt;
+      1697/1897&lt;BR&gt;
+      1680/1880&lt;BR&gt;
+      2187&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      8035EKP/CT20/RJ-20P&lt;BR&gt;
+      -&lt;BR&gt;
+      RJ-20X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      1211L&lt;BR&gt;
+      8012EKQ&amp;nbsp;ALT&lt;BR&gt;
+      8012EKR&amp;nbsp;ALT&lt;BR&gt;
+      1211P&lt;BR&gt;
+      8012EKJ&lt;BR&gt;
+      8012EKL&lt;BR&gt;
+      8012EKQ&lt;BR&gt;
+      8012EKR&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      2101P&lt;BR&gt;
+      2101W&lt;BR&gt;
+      2101Y&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      2102L&lt;BR&gt;
+      2102S&lt;BR&gt;
+      2102Y&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      EVMCOG&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      43P&lt;BR&gt;
+      43W&lt;BR&gt;
+      43Y&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      40L&lt;BR&gt;
+      40P&lt;BR&gt;
+      40Y&lt;BR&gt;
+      70Y-T602&lt;BR&gt;
+      70L&lt;BR&gt;
+      70P&lt;BR&gt;
+      70Y&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      RT/RTR12&lt;BR&gt;
+      RT/RTR12&lt;BR&gt;
+      RT/RTR12&lt;BR&gt;
+      -&lt;BR&gt;
+      RJ/RJR12&lt;BR&gt;
+      RJ/RJR12&lt;BR&gt;
+      RJ/RJR12&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;&amp;nbsp;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SQUARE MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+   &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MURATA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;SPECTROL&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MILSPEC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3250L&lt;BR&gt;
+      3250P&lt;BR&gt;
+      3250W&lt;BR&gt;
+      3250X&lt;BR&gt;
+      3252P&lt;BR&gt;
+      3252W&lt;BR&gt;
+      3252X&lt;BR&gt;
+      3260P&lt;BR&gt;
+      3260W&lt;BR&gt;
+      3260X&lt;BR&gt;
+      3262P&lt;BR&gt;
+      3262W&lt;BR&gt;
+      3262X&lt;BR&gt;
+      3266P&lt;BR&gt;
+      3266W&lt;BR&gt;
+      3266X&lt;BR&gt;
+      3290H&lt;BR&gt;
+      3290P&lt;BR&gt;
+      3290W&lt;BR&gt;
+      3292P&lt;BR&gt;
+      3292W&lt;BR&gt;
+      3292X&lt;BR&gt;
+      3296P&lt;BR&gt;
+      3296W&lt;BR&gt;
+      3296X&lt;BR&gt;
+      3296Y&lt;BR&gt;
+      3296Z&lt;BR&gt;
+      3299P&lt;BR&gt;
+      3299W&lt;BR&gt;
+      3299X&lt;BR&gt;
+      3299Y&lt;BR&gt;
+      3299Z&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      66P&amp;nbsp;ALT&lt;BR&gt;
+      66W&amp;nbsp;ALT&lt;BR&gt;
+      66X&amp;nbsp;ALT&lt;BR&gt;
+      66P&amp;nbsp;ALT&lt;BR&gt;
+      66W&amp;nbsp;ALT&lt;BR&gt;
+      66X&amp;nbsp;ALT&lt;BR&gt;
+      -&lt;BR&gt;
+      64W&amp;nbsp;ALT&lt;BR&gt;
+      -&lt;BR&gt;
+      64P&amp;nbsp;ALT&lt;BR&gt;
+      64W&amp;nbsp;ALT&lt;BR&gt;
+      64X&amp;nbsp;ALT&lt;BR&gt;
+      64P&lt;BR&gt;
+      64W&lt;BR&gt;
+      64X&lt;BR&gt;
+      66X&amp;nbsp;ALT&lt;BR&gt;
+      66P&amp;nbsp;ALT&lt;BR&gt;
+      66W&amp;nbsp;ALT&lt;BR&gt;
+      66P&lt;BR&gt;
+      66W&lt;BR&gt;
+      66X&lt;BR&gt;
+      67P&lt;BR&gt;
+      67W&lt;BR&gt;
+      67X&lt;BR&gt;
+      67Y&lt;BR&gt;
+      67Z&lt;BR&gt;
+      68P&lt;BR&gt;
+      68W&lt;BR&gt;
+      68X&lt;BR&gt;
+      67Y&amp;nbsp;ALT&lt;BR&gt;
+      67Z&amp;nbsp;ALT&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      5050&lt;BR&gt;
+      5091&lt;BR&gt;
+      5080&lt;BR&gt;
+      5087&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      T63YB&lt;BR&gt;
+      T63XB&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      5887&lt;BR&gt;
+      5891&lt;BR&gt;
+      5880&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      T93Z&lt;BR&gt;
+      T93YA&lt;BR&gt;
+      T93XA&lt;BR&gt;
+      T93YB&lt;BR&gt;
+      T93XB&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      8026EKP&lt;BR&gt;
+      8026EKW&lt;BR&gt;
+      8026EKM&lt;BR&gt;
+      8026EKP&lt;BR&gt;
+      8026EKB&lt;BR&gt;
+      8026EKM&lt;BR&gt;
+      1309X&lt;BR&gt;
+      1309P&lt;BR&gt;
+      1309W&lt;BR&gt;
+      8024EKP&lt;BR&gt;
+      8024EKW&lt;BR&gt;
+      8024EKN&lt;BR&gt;
+      RJ-9P/CT9P&lt;BR&gt;
+      RJ-9W&lt;BR&gt;
+      RJ-9X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3103P&lt;BR&gt;
+      3103Y&lt;BR&gt;
+      3103Z&lt;BR&gt;
+      3103P&lt;BR&gt;
+      3103Y&lt;BR&gt;
+      3103Z&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3105P/3106P&lt;BR&gt;
+      3105W/3106W&lt;BR&gt;
+      3105X/3106X&lt;BR&gt;
+      3105Y/3106Y&lt;BR&gt;
+      3105Z/3105Z&lt;BR&gt;
+      3102P&lt;BR&gt;
+      3102W&lt;BR&gt;
+      3102X&lt;BR&gt;
+      3102Y&lt;BR&gt;
+      3102Z&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMCBG&lt;BR&gt;
+      EVMCCG&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      55-1-X&lt;BR&gt;
+      55-4-X&lt;BR&gt;
+      55-3-X&lt;BR&gt;
+      55-2-X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      50-2-X&lt;BR&gt;
+      50-4-X&lt;BR&gt;
+      50-3-X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      64P&lt;BR&gt;
+      64W&lt;BR&gt;
+      64X&lt;BR&gt;
+      64Y&lt;BR&gt;
+      64Z&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      RT/RTR22&lt;BR&gt;
+      RT/RTR22&lt;BR&gt;
+      RT/RTR22&lt;BR&gt;
+      RT/RTR22&lt;BR&gt;
+      RJ/RJR22&lt;BR&gt;
+      RJ/RJR22&lt;BR&gt;
+      RJ/RJR22&lt;BR&gt;
+      RT/RTR26&lt;BR&gt;
+      RT/RTR26&lt;BR&gt;
+      RT/RTR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RJ/RJR26&lt;BR&gt;
+      RT/RTR24&lt;BR&gt;
+      RT/RTR24&lt;BR&gt;
+      RT/RTR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      RJ/RJR24&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;&amp;nbsp;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SINGLE TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MURATA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;SPECTROL&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;MILSPEC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3323P&lt;BR&gt;
+      3323S&lt;BR&gt;
+      3323W&lt;BR&gt;
+      3329H&lt;BR&gt;
+      3329P&lt;BR&gt;
+      3329W&lt;BR&gt;
+      3339H&lt;BR&gt;
+      3339P&lt;BR&gt;
+      3339W&lt;BR&gt;
+      3352E&lt;BR&gt;
+      3352H&lt;BR&gt;
+      3352K&lt;BR&gt;
+      3352P&lt;BR&gt;
+      3352T&lt;BR&gt;
+      3352V&lt;BR&gt;
+      3352W&lt;BR&gt;
+      3362H&lt;BR&gt;
+      3362M&lt;BR&gt;
+      3362P&lt;BR&gt;
+      3362R&lt;BR&gt;
+      3362S&lt;BR&gt;
+      3362U&lt;BR&gt;
+      3362W&lt;BR&gt;
+      3362X&lt;BR&gt;
+      3386B&lt;BR&gt;
+      3386C&lt;BR&gt;
+      3386F&lt;BR&gt;
+      3386H&lt;BR&gt;
+      3386K&lt;BR&gt;
+      3386M&lt;BR&gt;
+      3386P&lt;BR&gt;
+      3386S&lt;BR&gt;
+      3386W&lt;BR&gt;
+      3386X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      25P&lt;BR&gt;
+      25S&lt;BR&gt;
+      25RX&lt;BR&gt;
+      82P&lt;BR&gt;
+      82M&lt;BR&gt;
+      82PA&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      91E&lt;BR&gt;
+      91X&lt;BR&gt;
+      91T&lt;BR&gt;
+      91B&lt;BR&gt;
+      91A&lt;BR&gt;
+      91V&lt;BR&gt;
+      91W&lt;BR&gt;
+      25W&lt;BR&gt;
+      25V&lt;BR&gt;
+      25P&lt;BR&gt;
+      -&lt;BR&gt;
+      25S&lt;BR&gt;
+      25U&lt;BR&gt;
+      25RX&lt;BR&gt;
+      25X&lt;BR&gt;
+      72XW&lt;BR&gt;
+      72XL&lt;BR&gt;
+      72PM&lt;BR&gt;
+      72RX&lt;BR&gt;
+      -&lt;BR&gt;
+      72PX&lt;BR&gt;
+      72P&lt;BR&gt;
+      72RXW&lt;BR&gt;
+      72RXL&lt;BR&gt;
+      72X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      T7YB&lt;BR&gt;
+      T7YA&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      TXD&lt;BR&gt;
+      TYA&lt;BR&gt;
+      TYP&lt;BR&gt;
+      -&lt;BR&gt;
+      TYD&lt;BR&gt;
+      TX&lt;BR&gt;
+      -&lt;BR&gt;
+      150SX&lt;BR&gt;
+      100SX&lt;BR&gt;
+      102T&lt;BR&gt;
+      101S&lt;BR&gt;
+      190T&lt;BR&gt;
+      150TX&lt;BR&gt;
+      101&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      101SX&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      ET6P&lt;BR&gt;
+      ET6S&lt;BR&gt;
+      ET6X&lt;BR&gt;
+      RJ-6W/8014EMW&lt;BR&gt;
+      RJ-6P/8014EMP&lt;BR&gt;
+      RJ-6X/8014EMX&lt;BR&gt;
+      TM7W&lt;BR&gt;
+      TM7P&lt;BR&gt;
+      TM7X&lt;BR&gt;
+      -&lt;BR&gt;
+      8017SMS&lt;BR&gt;
+      -&lt;BR&gt;
+      8017SMB&lt;BR&gt;
+      8017SMA&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      CT-6W&lt;BR&gt;
+      CT-6H&lt;BR&gt;
+      CT-6P&lt;BR&gt;
+      CT-6R&lt;BR&gt;
+      -&lt;BR&gt;
+      CT-6V&lt;BR&gt;
+      CT-6X&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      8038EKV&lt;BR&gt;
+      -&lt;BR&gt;
+      8038EKX&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      8038EKP&lt;BR&gt;
+      8038EKZ&lt;BR&gt;
+      8038EKW&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3321H&lt;BR&gt;
+      3321P&lt;BR&gt;
+      3321N&lt;BR&gt;
+      1102H&lt;BR&gt;
+      1102P&lt;BR&gt;
+      1102T&lt;BR&gt;
+      RVA0911V304A&lt;BR&gt;
+      -&lt;BR&gt;
+      RVA0911H413A&lt;BR&gt;
+      RVG0707V100A&lt;BR&gt;
+      RVA0607V(H)306A&lt;BR&gt;
+      RVA1214H213A&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      3104B&lt;BR&gt;
+      3104C&lt;BR&gt;
+      3104F&lt;BR&gt;
+      3104H&lt;BR&gt;
+      -&lt;BR&gt;
+      3104M&lt;BR&gt;
+      3104P&lt;BR&gt;
+      3104S&lt;BR&gt;
+      3104W&lt;BR&gt;
+      3104X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      EVMQ0G&lt;BR&gt;
+      EVMQIG&lt;BR&gt;
+      EVMQ3G&lt;BR&gt;
+      EVMS0G&lt;BR&gt;
+      EVMQ0G&lt;BR&gt;
+      EVMG0G&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMK4GA00B&lt;BR&gt;
+      EVM30GA00B&lt;BR&gt;
+      EVMK0GA00B&lt;BR&gt;
+      EVM38GA00B&lt;BR&gt;
+      EVMB6&lt;BR&gt;
+      EVLQ0&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMMSG&lt;BR&gt;
+      EVMMBG&lt;BR&gt;
+      EVMMAG&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMMCS&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMM1&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMM0&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      EVMM3&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      62-3-1&lt;BR&gt;
+      62-1-2&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      67R&lt;BR&gt;
+      -&lt;BR&gt;
+      67P&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      67X&lt;BR&gt;
+      63V&lt;BR&gt;
+      63S&lt;BR&gt;
+      63M&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      63H&lt;BR&gt;
+      63P&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      63X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      RJ/RJR50&lt;BR&gt;
+      RJ/RJR50&lt;BR&gt;
+      RJ/RJR50&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+&lt;/TABLE&gt;
+&lt;P&gt;&amp;nbsp;&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;
+      &lt;FONT color="#0000FF" SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SMD TRIM-POT CROSS REFERENCE&lt;/B&gt;&lt;/FONT&gt;
+      &lt;P&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURNS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;TOCOS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;AUX/KYOCERA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3224G&lt;BR&gt;
+      3224J&lt;BR&gt;
+      3224W&lt;BR&gt;
+      3269P&lt;BR&gt;
+      3269W&lt;BR&gt;
+      3269X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      44G&lt;BR&gt;
+      44J&lt;BR&gt;
+      44W&lt;BR&gt;
+      84P&lt;BR&gt;
+      84W&lt;BR&gt;
+      84X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      ST63Z&lt;BR&gt;
+      ST63Y&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      ST5P&lt;BR&gt;
+      ST5W&lt;BR&gt;
+      ST5X&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;&amp;nbsp;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;
+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SINGLE TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURNS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;TOCOS&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;AUX/KYOCERA&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      3314G&lt;BR&gt;
+      3314J&lt;BR&gt;
+      3364A/B&lt;BR&gt;
+      3364C/D&lt;BR&gt;
+      3364W/X&lt;BR&gt;
+      3313G&lt;BR&gt;
+      3313J&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      23B&lt;BR&gt;
+      23A&lt;BR&gt;
+      21X&lt;BR&gt;
+      21W&lt;BR&gt;
+      -&lt;BR&gt;
+      22B&lt;BR&gt;
+      22A&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      ST5YL/ST53YL&lt;BR&gt;
+      ST5YJ/5T53YJ&lt;BR&gt;
+      ST-23A&lt;BR&gt;
+      ST-22B&lt;BR&gt;
+      ST-22&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      ST-4B&lt;BR&gt;
+      ST-4A&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      ST-3B&lt;BR&gt;
+      ST-3A&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      EVM-6YS&lt;BR&gt;
+      EVM-1E&lt;BR&gt;
+      EVM-1G&lt;BR&gt;
+      EVM-1D&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      G4B&lt;BR&gt;
+      G4A&lt;BR&gt;
+      TR04-3S1&lt;BR&gt;
+      TRG04-2S1&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      DVR-43A&lt;BR&gt;
+      CVR-42C&lt;BR&gt;
+      CVR-42A/C&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+&lt;/TABLE&gt;
+&lt;P&gt;
+&lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;ALT =&amp;nbsp;ALTERNATE&lt;/B&gt;&lt;/FONT&gt;
+&lt;P&gt;
+
+&amp;nbsp;
+&lt;P&gt;
+&lt;/td&gt;
+&lt;/tr&gt;
+&lt;/table&gt;
+&lt;/BODY&gt;&lt;/HTML&gt;</description>
+<packages>
+<package name="R0402" urn="urn:adsk.eagle:footprint:25625/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-0.245" y1="0.224" x2="0.245" y2="0.224" width="0.1524" layer="51"/>
+<wire x1="0.245" y1="-0.224" x2="-0.245" y2="-0.224" width="0.1524" layer="51"/>
+<wire x1="-1.473" y1="0.483" x2="1.473" y2="0.483" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.483" x2="1.473" y2="-0.483" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.483" x2="-1.473" y2="-0.483" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.483" x2="-1.473" y2="0.483" width="0.0508" layer="39"/>
+<smd name="1" x="-0.65" y="0" dx="0.7" dy="0.9" layer="1"/>
+<smd name="2" x="0.65" y="0" dx="0.7" dy="0.9" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.554" y1="-0.3048" x2="-0.254" y2="0.2951" layer="51"/>
+<rectangle x1="0.2588" y1="-0.3048" x2="0.5588" y2="0.2951" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/>
+</package>
+<package name="R0603" urn="urn:adsk.eagle:footprint:25626/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-0.432" y1="-0.356" x2="0.432" y2="-0.356" width="0.1524" layer="51"/>
+<wire x1="0.432" y1="0.356" x2="-0.432" y2="0.356" width="0.1524" layer="51"/>
+<wire x1="-1.473" y1="0.983" x2="1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.983" x2="1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.983" x2="-1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.983" x2="-1.473" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-0.85" y="0" dx="1" dy="1.1" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1" dy="1.1" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="0.4318" y1="-0.4318" x2="0.8382" y2="0.4318" layer="51"/>
+<rectangle x1="-0.8382" y1="-0.4318" x2="-0.4318" y2="0.4318" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/>
+</package>
+<package name="R0805" urn="urn:adsk.eagle:footprint:25627/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;</description>
+<wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="-0.635" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/>
+<rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.5001" x2="0.1999" y2="0.5001" layer="35"/>
+</package>
+<package name="R0805W" urn="urn:adsk.eagle:footprint:25628/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt; wave soldering&lt;p&gt;</description>
+<wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-1.0525" y="0" dx="1.5" dy="1" layer="1"/>
+<smd name="2" x="1.0525" y="0" dx="1.5" dy="1" layer="1"/>
+<text x="-0.635" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/>
+<rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.5001" x2="0.1999" y2="0.5001" layer="35"/>
+</package>
+<package name="R1206" urn="urn:adsk.eagle:footprint:25629/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="0.9525" y1="-0.8128" x2="-0.9652" y2="-0.8128" width="0.1524" layer="51"/>
+<wire x1="0.9525" y1="0.8128" x2="-0.9652" y2="0.8128" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/>
+<smd name="2" x="1.422" y="0" dx="1.6" dy="1.803" layer="1"/>
+<smd name="1" x="-1.422" y="0" dx="1.6" dy="1.803" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.6891" y1="-0.8763" x2="-0.9525" y2="0.8763" layer="51"/>
+<rectangle x1="0.9525" y1="-0.8763" x2="1.6891" y2="0.8763" layer="51"/>
+<rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/>
+</package>
+<package name="R1206W" urn="urn:adsk.eagle:footprint:25630/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-0.913" y1="0.8" x2="0.888" y2="0.8" width="0.1524" layer="51"/>
+<wire x1="-0.913" y1="-0.8" x2="0.888" y2="-0.8" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-1.499" y="0" dx="1.8" dy="1.2" layer="1"/>
+<smd name="2" x="1.499" y="0" dx="1.8" dy="1.2" layer="1"/>
+<text x="-1.905" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-0.8763" x2="-0.9009" y2="0.8738" layer="51"/>
+<rectangle x1="0.889" y1="-0.8763" x2="1.6391" y2="0.8738" layer="51"/>
+<rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/>
+</package>
+<package name="R1210" urn="urn:adsk.eagle:footprint:25631/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-0.913" y1="1.219" x2="0.939" y2="1.219" width="0.1524" layer="51"/>
+<wire x1="-0.913" y1="-1.219" x2="0.939" y2="-1.219" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-1.3081" x2="-0.9009" y2="1.2918" layer="51"/>
+<rectangle x1="0.9144" y1="-1.3081" x2="1.6645" y2="1.2918" layer="51"/>
+<rectangle x1="-0.3" y1="-0.8999" x2="0.3" y2="0.8999" layer="35"/>
+</package>
+<package name="R1210W" urn="urn:adsk.eagle:footprint:25632/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-0.913" y1="1.219" x2="0.939" y2="1.219" width="0.1524" layer="51"/>
+<wire x1="-0.913" y1="-1.219" x2="0.939" y2="-1.219" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.499" y="0" dx="1.8" dy="1.8" layer="1"/>
+<smd name="2" x="1.499" y="0" dx="1.8" dy="1.8" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-1.3081" x2="-0.9009" y2="1.2918" layer="51"/>
+<rectangle x1="0.9144" y1="-1.3081" x2="1.6645" y2="1.2918" layer="51"/>
+<rectangle x1="-0.3" y1="-0.8001" x2="0.3" y2="0.8001" layer="35"/>
+</package>
+<package name="R2010" urn="urn:adsk.eagle:footprint:25633/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-1.662" y1="1.245" x2="1.662" y2="1.245" width="0.1524" layer="51"/>
+<wire x1="-1.637" y1="-1.245" x2="1.687" y2="-1.245" width="0.1524" layer="51"/>
+<wire x1="-3.473" y1="1.483" x2="3.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="1.483" x2="3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="-1.483" x2="-3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-3.473" y1="-1.483" x2="-3.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-2.2" y="0" dx="1.8" dy="2.7" layer="1"/>
+<smd name="2" x="2.2" y="0" dx="1.8" dy="2.7" layer="1"/>
+<text x="-3.175" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.175" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.4892" y1="-1.3208" x2="-1.6393" y2="1.3292" layer="51"/>
+<rectangle x1="1.651" y1="-1.3208" x2="2.5009" y2="1.3292" layer="51"/>
+</package>
+<package name="R2010W" urn="urn:adsk.eagle:footprint:25634/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-1.662" y1="1.245" x2="1.662" y2="1.245" width="0.1524" layer="51"/>
+<wire x1="-1.637" y1="-1.245" x2="1.687" y2="-1.245" width="0.1524" layer="51"/>
+<wire x1="-3.473" y1="1.483" x2="3.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="1.483" x2="3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="-1.483" x2="-3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-3.473" y1="-1.483" x2="-3.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-2.311" y="0" dx="2" dy="1.8" layer="1"/>
+<smd name="2" x="2.311" y="0" dx="2" dy="1.8" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.4892" y1="-1.3208" x2="-1.6393" y2="1.3292" layer="51"/>
+<rectangle x1="1.651" y1="-1.3208" x2="2.5009" y2="1.3292" layer="51"/>
+</package>
+<package name="R2012" urn="urn:adsk.eagle:footprint:25635/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-0.85" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="-0.635" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/>
+<rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/>
+<rectangle x1="-0.1001" y1="-0.5999" x2="0.1001" y2="0.5999" layer="35"/>
+</package>
+<package name="R2012W" urn="urn:adsk.eagle:footprint:25636/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-0.94" y="0" dx="1.5" dy="1" layer="1"/>
+<smd name="2" x="0.94" y="0" dx="1.5" dy="1" layer="1"/>
+<text x="-0.635" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/>
+<rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/>
+<rectangle x1="-0.1001" y1="-0.5999" x2="0.1001" y2="0.5999" layer="35"/>
+</package>
+<package name="R2512" urn="urn:adsk.eagle:footprint:25637/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-2.362" y1="1.473" x2="2.387" y2="1.473" width="0.1524" layer="51"/>
+<wire x1="-2.362" y1="-1.473" x2="2.387" y2="-1.473" width="0.1524" layer="51"/>
+<wire x1="-3.973" y1="1.983" x2="3.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="1.983" x2="3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="-1.983" x2="-3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-3.973" y1="-1.983" x2="-3.973" y2="1.983" width="0.0508" layer="39"/>
+<smd name="1" x="-2.8" y="0" dx="1.8" dy="3.2" layer="1"/>
+<smd name="2" x="2.8" y="0" dx="1.8" dy="3.2" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.2004" y1="-1.5494" x2="-2.3505" y2="1.5507" layer="51"/>
+<rectangle x1="2.3622" y1="-1.5494" x2="3.2121" y2="1.5507" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="R2512W" urn="urn:adsk.eagle:footprint:25638/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-2.362" y1="1.473" x2="2.387" y2="1.473" width="0.1524" layer="51"/>
+<wire x1="-2.362" y1="-1.473" x2="2.387" y2="-1.473" width="0.1524" layer="51"/>
+<wire x1="-3.973" y1="1.983" x2="3.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="1.983" x2="3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="-1.983" x2="-3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-3.973" y1="-1.983" x2="-3.973" y2="1.983" width="0.0508" layer="39"/>
+<smd name="1" x="-2.896" y="0" dx="2" dy="2.1" layer="1"/>
+<smd name="2" x="2.896" y="0" dx="2" dy="2.1" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.2004" y1="-1.5494" x2="-2.3505" y2="1.5507" layer="51"/>
+<rectangle x1="2.3622" y1="-1.5494" x2="3.2121" y2="1.5507" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="R3216" urn="urn:adsk.eagle:footprint:25639/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-0.913" y1="0.8" x2="0.888" y2="0.8" width="0.1524" layer="51"/>
+<wire x1="-0.913" y1="-0.8" x2="0.888" y2="-0.8" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="1.8" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="1.8" layer="1"/>
+<text x="-1.905" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-0.8763" x2="-0.9009" y2="0.8738" layer="51"/>
+<rectangle x1="0.889" y1="-0.8763" x2="1.6391" y2="0.8738" layer="51"/>
+<rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/>
+</package>
+<package name="R3216W" urn="urn:adsk.eagle:footprint:25640/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-0.913" y1="0.8" x2="0.888" y2="0.8" width="0.1524" layer="51"/>
+<wire x1="-0.913" y1="-0.8" x2="0.888" y2="-0.8" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-1.499" y="0" dx="1.8" dy="1.2" layer="1"/>
+<smd name="2" x="1.499" y="0" dx="1.8" dy="1.2" layer="1"/>
+<text x="-1.905" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-0.8763" x2="-0.9009" y2="0.8738" layer="51"/>
+<rectangle x1="0.889" y1="-0.8763" x2="1.6391" y2="0.8738" layer="51"/>
+<rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/>
+</package>
+<package name="R3225" urn="urn:adsk.eagle:footprint:25641/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-0.913" y1="1.219" x2="0.939" y2="1.219" width="0.1524" layer="51"/>
+<wire x1="-0.913" y1="-1.219" x2="0.939" y2="-1.219" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-1.3081" x2="-0.9009" y2="1.2918" layer="51"/>
+<rectangle x1="0.9144" y1="-1.3081" x2="1.6645" y2="1.2918" layer="51"/>
+<rectangle x1="-0.3" y1="-1" x2="0.3" y2="1" layer="35"/>
+</package>
+<package name="R3225W" urn="urn:adsk.eagle:footprint:25642/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-0.913" y1="1.219" x2="0.939" y2="1.219" width="0.1524" layer="51"/>
+<wire x1="-0.913" y1="-1.219" x2="0.939" y2="-1.219" width="0.1524" layer="51"/>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.499" y="0" dx="1.8" dy="1.8" layer="1"/>
+<smd name="2" x="1.499" y="0" dx="1.8" dy="1.8" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-1.3081" x2="-0.9009" y2="1.2918" layer="51"/>
+<rectangle x1="0.9144" y1="-1.3081" x2="1.6645" y2="1.2918" layer="51"/>
+<rectangle x1="-0.3" y1="-1" x2="0.3" y2="1" layer="35"/>
+</package>
+<package name="R5025" urn="urn:adsk.eagle:footprint:25643/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;</description>
+<wire x1="-1.662" y1="1.245" x2="1.662" y2="1.245" width="0.1524" layer="51"/>
+<wire x1="-1.637" y1="-1.245" x2="1.687" y2="-1.245" width="0.1524" layer="51"/>
+<wire x1="-3.473" y1="1.483" x2="3.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="1.483" x2="3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="-1.483" x2="-3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-3.473" y1="-1.483" x2="-3.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-2.2" y="0" dx="1.8" dy="2.7" layer="1"/>
+<smd name="2" x="2.2" y="0" dx="1.8" dy="2.7" layer="1"/>
+<text x="-3.175" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.175" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.4892" y1="-1.3208" x2="-1.6393" y2="1.3292" layer="51"/>
+<rectangle x1="1.651" y1="-1.3208" x2="2.5009" y2="1.3292" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="R5025W" urn="urn:adsk.eagle:footprint:25644/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+wave soldering</description>
+<wire x1="-1.662" y1="1.245" x2="1.662" y2="1.245" width="0.1524" layer="51"/>
+<wire x1="-1.637" y1="-1.245" x2="1.687" y2="-1.245" width="0.1524" layer="51"/>
+<wire x1="-3.473" y1="1.483" x2="3.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="1.483" x2="3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="3.473" y1="-1.483" x2="-3.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-3.473" y1="-1.483" x2="-3.473" y2="1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-2.311" y="0" dx="2" dy="1.8" layer="1"/>
+<smd name="2" x="2.311" y="0" dx="2" dy="1.8" layer="1"/>
+<text x="-3.175" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.175" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.4892" y1="-1.3208" x2="-1.6393" y2="1.3292" layer="51"/>
+<rectangle x1="1.651" y1="-1.3208" x2="2.5009" y2="1.3292" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="R6332" urn="urn:adsk.eagle:footprint:25645/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf</description>
+<wire x1="-2.362" y1="1.473" x2="2.387" y2="1.473" width="0.1524" layer="51"/>
+<wire x1="-2.362" y1="-1.473" x2="2.387" y2="-1.473" width="0.1524" layer="51"/>
+<wire x1="-3.973" y1="1.983" x2="3.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="1.983" x2="3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="-1.983" x2="-3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-3.973" y1="-1.983" x2="-3.973" y2="1.983" width="0.0508" layer="39"/>
+<smd name="1" x="-3.1" y="0" dx="1" dy="3.2" layer="1"/>
+<smd name="2" x="3.1" y="0" dx="1" dy="3.2" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.2004" y1="-1.5494" x2="-2.3505" y2="1.5507" layer="51"/>
+<rectangle x1="2.3622" y1="-1.5494" x2="3.2121" y2="1.5507" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="R6332W" urn="urn:adsk.eagle:footprint:25646/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt; wave soldering&lt;p&gt;
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf</description>
+<wire x1="-2.362" y1="1.473" x2="2.387" y2="1.473" width="0.1524" layer="51"/>
+<wire x1="-2.362" y1="-1.473" x2="2.387" y2="-1.473" width="0.1524" layer="51"/>
+<wire x1="-3.973" y1="1.983" x2="3.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="1.983" x2="3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="3.973" y1="-1.983" x2="-3.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-3.973" y1="-1.983" x2="-3.973" y2="1.983" width="0.0508" layer="39"/>
+<smd name="1" x="-3.196" y="0" dx="1.2" dy="3.2" layer="1"/>
+<smd name="2" x="3.196" y="0" dx="1.2" dy="3.2" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.2004" y1="-1.5494" x2="-2.3505" y2="1.5507" layer="51"/>
+<rectangle x1="2.3622" y1="-1.5494" x2="3.2121" y2="1.5507" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="M0805" urn="urn:adsk.eagle:footprint:25647/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.10 W</description>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="0.7112" y1="0.635" x2="-0.7112" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="0.7112" y1="-0.635" x2="-0.7112" y2="-0.635" width="0.1524" layer="51"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.6" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.6" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.0414" y1="-0.7112" x2="-0.6858" y2="0.7112" layer="51"/>
+<rectangle x1="0.6858" y1="-0.7112" x2="1.0414" y2="0.7112" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.5999" x2="0.1999" y2="0.5999" layer="35"/>
+</package>
+<package name="M1206" urn="urn:adsk.eagle:footprint:25648/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.25 W</description>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="1.143" y1="0.8382" x2="-1.143" y2="0.8382" width="0.1524" layer="51"/>
+<wire x1="1.143" y1="-0.8382" x2="-1.143" y2="-0.8382" width="0.1524" layer="51"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.7018" y1="-0.9144" x2="-1.1176" y2="0.9144" layer="51"/>
+<rectangle x1="1.1176" y1="-0.9144" x2="1.7018" y2="0.9144" layer="51"/>
+<rectangle x1="-0.3" y1="-0.8001" x2="0.3" y2="0.8001" layer="35"/>
+</package>
+<package name="M1406" urn="urn:adsk.eagle:footprint:25649/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.12 W</description>
+<wire x1="-2.973" y1="0.983" x2="2.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-0.983" x2="-2.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-0.983" x2="-2.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="0.983" x2="2.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.3208" y1="0.762" x2="-1.3208" y2="0.762" width="0.1524" layer="51"/>
+<wire x1="1.3208" y1="-0.762" x2="-1.3208" y2="-0.762" width="0.1524" layer="51"/>
+<smd name="1" x="-1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<smd name="2" x="1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.8542" y1="-0.8382" x2="-1.2954" y2="0.8382" layer="51"/>
+<rectangle x1="1.2954" y1="-0.8382" x2="1.8542" y2="0.8382" layer="51"/>
+<rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/>
+</package>
+<package name="M2012" urn="urn:adsk.eagle:footprint:25650/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.10 W</description>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="0.7112" y1="0.635" x2="-0.7112" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="0.7112" y1="-0.635" x2="-0.7112" y2="-0.635" width="0.1524" layer="51"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.6" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.6" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.0414" y1="-0.7112" x2="-0.6858" y2="0.7112" layer="51"/>
+<rectangle x1="0.6858" y1="-0.7112" x2="1.0414" y2="0.7112" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.5999" x2="0.1999" y2="0.5999" layer="35"/>
+</package>
+<package name="M2309" urn="urn:adsk.eagle:footprint:25651/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.25 W</description>
+<wire x1="-4.473" y1="1.483" x2="4.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="-1.483" x2="-4.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-4.473" y1="-1.483" x2="-4.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="1.483" x2="4.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="2.413" y1="1.1684" x2="-2.4384" y2="1.1684" width="0.1524" layer="51"/>
+<wire x1="2.413" y1="-1.1684" x2="-2.413" y2="-1.1684" width="0.1524" layer="51"/>
+<smd name="1" x="-2.85" y="0" dx="1.5" dy="2.6" layer="1"/>
+<smd name="2" x="2.85" y="0" dx="1.5" dy="2.6" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.048" y1="-1.2446" x2="-2.3876" y2="1.2446" layer="51"/>
+<rectangle x1="2.3876" y1="-1.2446" x2="3.048" y2="1.2446" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="M3216" urn="urn:adsk.eagle:footprint:25652/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.25 W</description>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="1.143" y1="0.8382" x2="-1.143" y2="0.8382" width="0.1524" layer="51"/>
+<wire x1="1.143" y1="-0.8382" x2="-1.143" y2="-0.8382" width="0.1524" layer="51"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.7018" y1="-0.9144" x2="-1.1176" y2="0.9144" layer="51"/>
+<rectangle x1="1.1176" y1="-0.9144" x2="1.7018" y2="0.9144" layer="51"/>
+<rectangle x1="-0.3" y1="-0.8001" x2="0.3" y2="0.8001" layer="35"/>
+</package>
+<package name="M3516" urn="urn:adsk.eagle:footprint:25653/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.12 W</description>
+<wire x1="-2.973" y1="0.983" x2="2.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-0.983" x2="-2.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-0.983" x2="-2.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="0.983" x2="2.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.3208" y1="0.762" x2="-1.3208" y2="0.762" width="0.1524" layer="51"/>
+<wire x1="1.3208" y1="-0.762" x2="-1.3208" y2="-0.762" width="0.1524" layer="51"/>
+<smd name="1" x="-1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<smd name="2" x="1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.8542" y1="-0.8382" x2="-1.2954" y2="0.8382" layer="51"/>
+<rectangle x1="1.2954" y1="-0.8382" x2="1.8542" y2="0.8382" layer="51"/>
+<rectangle x1="-0.4001" y1="-0.7" x2="0.4001" y2="0.7" layer="35"/>
+</package>
+<package name="M5923" urn="urn:adsk.eagle:footprint:25654/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+MELF 0.25 W</description>
+<wire x1="-4.473" y1="1.483" x2="4.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="-1.483" x2="-4.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-4.473" y1="-1.483" x2="-4.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="1.483" x2="4.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="2.413" y1="1.1684" x2="-2.4384" y2="1.1684" width="0.1524" layer="51"/>
+<wire x1="2.413" y1="-1.1684" x2="-2.413" y2="-1.1684" width="0.1524" layer="51"/>
+<smd name="1" x="-2.85" y="0" dx="1.5" dy="2.6" layer="1"/>
+<smd name="2" x="2.85" y="0" dx="1.5" dy="2.6" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.048" y1="-1.2446" x2="-2.3876" y2="1.2446" layer="51"/>
+<rectangle x1="2.3876" y1="-1.2446" x2="3.048" y2="1.2446" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="0204/5" urn="urn:adsk.eagle:footprint:25500/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0204, grid 5 mm</description>
+<wire x1="2.54" y1="0" x2="2.032" y2="0" width="0.508" layer="51"/>
+<wire x1="-2.54" y1="0" x2="-2.032" y2="0" width="0.508" layer="51"/>
+<wire x1="-1.778" y1="0.635" x2="-1.524" y2="0.889" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-1.778" y1="-0.635" x2="-1.524" y2="-0.889" width="0.1524" layer="21" curve="90"/>
+<wire x1="1.524" y1="-0.889" x2="1.778" y2="-0.635" width="0.1524" layer="21" curve="90"/>
+<wire x1="1.524" y1="0.889" x2="1.778" y2="0.635" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-1.778" y1="-0.635" x2="-1.778" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="-1.524" y1="0.889" x2="-1.27" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-1.143" y1="0.762" x2="-1.27" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-1.524" y1="-0.889" x2="-1.27" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="-1.143" y1="-0.762" x2="-1.27" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="0.762" x2="1.27" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="0.762" x2="-1.143" y2="0.762" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="-0.762" x2="1.27" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="-0.762" x2="-1.143" y2="-0.762" width="0.1524" layer="21"/>
+<wire x1="1.524" y1="0.889" x2="1.27" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="1.524" y1="-0.889" x2="1.27" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="-0.635" x2="1.778" y2="0.635" width="0.1524" layer="51"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.0066" y="1.1684" size="0.9906" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.1336" y="-2.3114" size="0.9906" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.032" y1="-0.254" x2="-1.778" y2="0.254" layer="51"/>
+<rectangle x1="1.778" y1="-0.254" x2="2.032" y2="0.254" layer="51"/>
+</package>
+<package name="0204/7" urn="urn:adsk.eagle:footprint:25507/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0204, grid 7.5 mm</description>
+<wire x1="3.81" y1="0" x2="2.921" y2="0" width="0.508" layer="51"/>
+<wire x1="-3.81" y1="0" x2="-2.921" y2="0" width="0.508" layer="51"/>
+<wire x1="-2.54" y1="0.762" x2="-2.286" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.54" y1="-0.762" x2="-2.286" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.286" y1="-1.016" x2="2.54" y2="-0.762" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.286" y1="1.016" x2="2.54" y2="0.762" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.54" y1="-0.762" x2="-2.54" y2="0.762" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="1.016" x2="-1.905" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-1.778" y1="0.889" x2="-1.905" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="-1.016" x2="-1.905" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-1.778" y1="-0.889" x2="-1.905" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="0.889" x2="1.905" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="0.889" x2="-1.778" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="-0.889" x2="1.905" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="-0.889" x2="-1.778" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="2.286" y1="1.016" x2="1.905" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="2.286" y1="-1.016" x2="1.905" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.762" x2="2.54" y2="0.762" width="0.1524" layer="21"/>
+<pad name="1" x="-3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="3.81" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.54" y="1.2954" size="0.9906" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.6256" y="-0.4826" size="0.9906" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="2.54" y1="-0.254" x2="2.921" y2="0.254" layer="21"/>
+<rectangle x1="-2.921" y1="-0.254" x2="-2.54" y2="0.254" layer="21"/>
+</package>
+<package name="0204V" urn="urn:adsk.eagle:footprint:25508/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0204, grid 2.5 mm</description>
+<wire x1="-1.27" y1="0" x2="1.27" y2="0" width="0.508" layer="51"/>
+<wire x1="-0.127" y1="0" x2="0.127" y2="0" width="0.508" layer="21"/>
+<circle x="-1.27" y="0" radius="0.889" width="0.1524" layer="51"/>
+<circle x="-1.27" y="0" radius="0.635" width="0.0508" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.1336" y="1.1684" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.1336" y="-2.3114" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="0207/10" urn="urn:adsk.eagle:footprint:25501/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0207, grid 10 mm</description>
+<wire x1="5.08" y1="0" x2="4.064" y2="0" width="0.6096" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.064" y2="0" width="0.6096" layer="51"/>
+<wire x1="-3.175" y1="0.889" x2="-2.921" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-2.921" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="-1.143" x2="3.175" y2="-0.889" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="1.143" x2="3.175" y2="0.889" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-3.175" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="1.143" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.016" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="-1.143" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="-1.016" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="-2.413" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="-2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="1.143" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="-1.143" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-0.889" x2="3.175" y2="0.889" width="0.1524" layer="21"/>
+<pad name="1" x="-5.08" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="5.08" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.048" y="1.524" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.2606" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="3.175" y1="-0.3048" x2="4.0386" y2="0.3048" layer="21"/>
+<rectangle x1="-4.0386" y1="-0.3048" x2="-3.175" y2="0.3048" layer="21"/>
+</package>
+<package name="0207/12" urn="urn:adsk.eagle:footprint:25502/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0207, grid 12 mm</description>
+<wire x1="6.35" y1="0" x2="5.334" y2="0" width="0.6096" layer="51"/>
+<wire x1="-6.35" y1="0" x2="-5.334" y2="0" width="0.6096" layer="51"/>
+<wire x1="-3.175" y1="0.889" x2="-2.921" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-2.921" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="-1.143" x2="3.175" y2="-0.889" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="1.143" x2="3.175" y2="0.889" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-3.175" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="1.143" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.016" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="-1.143" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="-1.016" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="-2.413" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="-2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="1.143" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="-1.143" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-0.889" x2="3.175" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="0" x2="4.064" y2="0" width="0.6096" layer="21"/>
+<wire x1="-4.445" y1="0" x2="-4.064" y2="0" width="0.6096" layer="21"/>
+<pad name="1" x="-6.35" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="6.35" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.175" y="1.397" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-0.6858" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="3.175" y1="-0.3048" x2="4.0386" y2="0.3048" layer="21"/>
+<rectangle x1="-4.0386" y1="-0.3048" x2="-3.175" y2="0.3048" layer="21"/>
+<rectangle x1="4.445" y1="-0.3048" x2="5.3086" y2="0.3048" layer="21"/>
+<rectangle x1="-5.3086" y1="-0.3048" x2="-4.445" y2="0.3048" layer="21"/>
+</package>
+<package name="0207/15" urn="urn:adsk.eagle:footprint:25506/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0207, grid 15mm</description>
+<wire x1="7.62" y1="0" x2="6.604" y2="0" width="0.6096" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.604" y2="0" width="0.6096" layer="51"/>
+<wire x1="-3.175" y1="0.889" x2="-2.921" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-2.921" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="-1.143" x2="3.175" y2="-0.889" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="1.143" x2="3.175" y2="0.889" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-3.175" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="1.143" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.016" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="-1.143" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="-1.016" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="-2.413" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="-2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="1.143" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="-1.143" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-0.889" x2="3.175" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="5.715" y1="0" x2="4.064" y2="0" width="0.6096" layer="21"/>
+<wire x1="-5.715" y1="0" x2="-4.064" y2="0" width="0.6096" layer="21"/>
+<pad name="1" x="-7.62" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="7.62" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.175" y="1.397" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-0.6858" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="3.175" y1="-0.3048" x2="4.0386" y2="0.3048" layer="21"/>
+<rectangle x1="-4.0386" y1="-0.3048" x2="-3.175" y2="0.3048" layer="21"/>
+<rectangle x1="5.715" y1="-0.3048" x2="6.5786" y2="0.3048" layer="21"/>
+<rectangle x1="-6.5786" y1="-0.3048" x2="-5.715" y2="0.3048" layer="21"/>
+</package>
+<package name="0207/2V" urn="urn:adsk.eagle:footprint:25503/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0207, grid 2.5 mm</description>
+<wire x1="-1.27" y1="0" x2="-0.381" y2="0" width="0.6096" layer="51"/>
+<wire x1="-0.254" y1="0" x2="0.254" y2="0" width="0.6096" layer="21"/>
+<wire x1="0.381" y1="0" x2="1.27" y2="0" width="0.6096" layer="51"/>
+<circle x="-1.27" y="0" radius="1.27" width="0.1524" layer="21"/>
+<circle x="-1.27" y="0" radius="1.016" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-0.0508" y="1.016" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.0508" y="-2.2352" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="0207/5V" urn="urn:adsk.eagle:footprint:25504/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0207, grid 5 mm</description>
+<wire x1="-2.54" y1="0" x2="-0.889" y2="0" width="0.6096" layer="51"/>
+<wire x1="-0.762" y1="0" x2="0.762" y2="0" width="0.6096" layer="21"/>
+<wire x1="0.889" y1="0" x2="2.54" y2="0" width="0.6096" layer="51"/>
+<circle x="-2.54" y="0" radius="1.27" width="0.1016" layer="21"/>
+<circle x="-2.54" y="0" radius="1.016" width="0.1524" layer="51"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-1.143" y="0.889" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.143" y="-2.159" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="0207/7" urn="urn:adsk.eagle:footprint:25505/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0207, grid 7.5 mm</description>
+<wire x1="-3.81" y1="0" x2="-3.429" y2="0" width="0.6096" layer="51"/>
+<wire x1="-3.175" y1="0.889" x2="-2.921" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-2.921" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="-1.143" x2="3.175" y2="-0.889" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.921" y1="1.143" x2="3.175" y2="0.889" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.175" y1="-0.889" x2="-3.175" y2="0.889" width="0.1524" layer="51"/>
+<wire x1="-2.921" y1="1.143" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.016" x2="-2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="-1.143" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="-1.016" x2="-2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="-2.413" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="-2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="1.143" x2="2.54" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="-1.143" x2="2.54" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-0.889" x2="3.175" y2="0.889" width="0.1524" layer="51"/>
+<wire x1="3.429" y1="0" x2="3.81" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="3.81" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.54" y="1.397" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-0.5588" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.429" y1="-0.3048" x2="-3.175" y2="0.3048" layer="51"/>
+<rectangle x1="3.175" y1="-0.3048" x2="3.429" y2="0.3048" layer="51"/>
+</package>
+<package name="0309/10" urn="urn:adsk.eagle:footprint:25655/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0309, grid 10mm</description>
+<wire x1="-4.699" y1="0" x2="-5.08" y2="0" width="0.6096" layer="51"/>
+<wire x1="-4.318" y1="1.27" x2="-4.064" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-4.318" y1="-1.27" x2="-4.064" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="4.064" y1="-1.524" x2="4.318" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="4.064" y1="1.524" x2="4.318" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-4.318" y1="-1.27" x2="-4.318" y2="1.27" width="0.1524" layer="51"/>
+<wire x1="-4.064" y1="1.524" x2="-3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-3.302" y1="1.397" x2="-3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-4.064" y1="-1.524" x2="-3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="-3.302" y1="-1.397" x2="-3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="1.397" x2="3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="1.397" x2="-3.302" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="-1.397" x2="3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="-1.397" x2="-3.302" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="4.064" y1="1.524" x2="3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="4.064" y1="-1.524" x2="3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="-1.27" x2="4.318" y2="1.27" width="0.1524" layer="51"/>
+<wire x1="5.08" y1="0" x2="4.699" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-5.08" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="5.08" y="0" drill="0.8128" shape="octagon"/>
+<text x="-4.191" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.6858" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-4.6228" y1="-0.3048" x2="-4.318" y2="0.3048" layer="51"/>
+<rectangle x1="4.318" y1="-0.3048" x2="4.6228" y2="0.3048" layer="51"/>
+</package>
+<package name="0309/12" urn="urn:adsk.eagle:footprint:25656/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0309, grid 12.5 mm</description>
+<wire x1="6.35" y1="0" x2="5.08" y2="0" width="0.6096" layer="51"/>
+<wire x1="-6.35" y1="0" x2="-5.08" y2="0" width="0.6096" layer="51"/>
+<wire x1="-4.318" y1="1.27" x2="-4.064" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-4.318" y1="-1.27" x2="-4.064" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="4.064" y1="-1.524" x2="4.318" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="4.064" y1="1.524" x2="4.318" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-4.318" y1="-1.27" x2="-4.318" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-4.064" y1="1.524" x2="-3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-3.302" y1="1.397" x2="-3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-4.064" y1="-1.524" x2="-3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="-3.302" y1="-1.397" x2="-3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="1.397" x2="3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="1.397" x2="-3.302" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="-1.397" x2="3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="-1.397" x2="-3.302" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="4.064" y1="1.524" x2="3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="4.064" y1="-1.524" x2="3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="-1.27" x2="4.318" y2="1.27" width="0.1524" layer="21"/>
+<pad name="1" x="-6.35" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="6.35" y="0" drill="0.8128" shape="octagon"/>
+<text x="-4.191" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.6858" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="4.318" y1="-0.3048" x2="5.1816" y2="0.3048" layer="21"/>
+<rectangle x1="-5.1816" y1="-0.3048" x2="-4.318" y2="0.3048" layer="21"/>
+</package>
+<package name="0309V" urn="urn:adsk.eagle:footprint:25657/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0309, grid 2.5 mm</description>
+<wire x1="1.27" y1="0" x2="0.635" y2="0" width="0.6096" layer="51"/>
+<wire x1="-0.635" y1="0" x2="-1.27" y2="0" width="0.6096" layer="51"/>
+<circle x="-1.27" y="0" radius="1.524" width="0.1524" layer="21"/>
+<circle x="-1.27" y="0" radius="0.762" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="0.254" y="1.016" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="0.254" y="-2.2098" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="0.254" y1="-0.3048" x2="0.5588" y2="0.3048" layer="51"/>
+<rectangle x1="-0.635" y1="-0.3048" x2="-0.3302" y2="0.3048" layer="51"/>
+<rectangle x1="-0.3302" y1="-0.3048" x2="0.254" y2="0.3048" layer="21"/>
+</package>
+<package name="0411/12" urn="urn:adsk.eagle:footprint:25658/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0411, grid 12.5 mm</description>
+<wire x1="6.35" y1="0" x2="5.461" y2="0" width="0.762" layer="51"/>
+<wire x1="-6.35" y1="0" x2="-5.461" y2="0" width="0.762" layer="51"/>
+<wire x1="5.08" y1="-1.651" x2="5.08" y2="1.651" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="2.032" x2="5.08" y2="1.651" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-5.08" y1="-1.651" x2="-4.699" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="4.699" y1="-2.032" x2="5.08" y2="-1.651" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.651" x2="-4.699" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="2.032" x2="4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="3.937" y1="1.905" x2="4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-2.032" x2="4.064" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="3.937" y1="-1.905" x2="4.064" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="1.905" x2="-4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="1.905" x2="3.937" y2="1.905" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="-1.905" x2="-4.064" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="-1.905" x2="3.937" y2="-1.905" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="1.651" x2="-5.08" y2="-1.651" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="2.032" x2="-4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="-2.032" x2="-4.064" y2="-2.032" width="0.1524" layer="21"/>
+<pad name="1" x="-6.35" y="0" drill="0.9144" shape="octagon"/>
+<pad name="2" x="6.35" y="0" drill="0.9144" shape="octagon"/>
+<text x="-5.08" y="2.413" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.5814" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-5.3594" y1="-0.381" x2="-5.08" y2="0.381" layer="21"/>
+<rectangle x1="5.08" y1="-0.381" x2="5.3594" y2="0.381" layer="21"/>
+</package>
+<package name="0411/15" urn="urn:adsk.eagle:footprint:25659/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0411, grid 15 mm</description>
+<wire x1="5.08" y1="-1.651" x2="5.08" y2="1.651" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="2.032" x2="5.08" y2="1.651" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-5.08" y1="-1.651" x2="-4.699" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="4.699" y1="-2.032" x2="5.08" y2="-1.651" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.651" x2="-4.699" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="2.032" x2="4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="3.937" y1="1.905" x2="4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-2.032" x2="4.064" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="3.937" y1="-1.905" x2="4.064" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="1.905" x2="-4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="1.905" x2="3.937" y2="1.905" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="-1.905" x2="-4.064" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-3.937" y1="-1.905" x2="3.937" y2="-1.905" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="1.651" x2="-5.08" y2="-1.651" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="2.032" x2="-4.064" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="-2.032" x2="-4.064" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-6.35" y2="0" width="0.762" layer="51"/>
+<wire x1="6.35" y1="0" x2="7.62" y2="0" width="0.762" layer="51"/>
+<pad name="1" x="-7.62" y="0" drill="0.9144" shape="octagon"/>
+<pad name="2" x="7.62" y="0" drill="0.9144" shape="octagon"/>
+<text x="-5.08" y="2.413" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.5814" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="5.08" y1="-0.381" x2="6.477" y2="0.381" layer="21"/>
+<rectangle x1="-6.477" y1="-0.381" x2="-5.08" y2="0.381" layer="21"/>
+</package>
+<package name="0411V" urn="urn:adsk.eagle:footprint:25660/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0411, grid 3.81 mm</description>
+<wire x1="1.27" y1="0" x2="0.3048" y2="0" width="0.762" layer="51"/>
+<wire x1="-1.5748" y1="0" x2="-2.54" y2="0" width="0.762" layer="51"/>
+<circle x="-2.54" y="0" radius="2.032" width="0.1524" layer="21"/>
+<circle x="-2.54" y="0" radius="1.016" width="0.1524" layer="51"/>
+<pad name="1" x="-2.54" y="0" drill="0.9144" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.9144" shape="octagon"/>
+<text x="-0.508" y="1.143" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.5334" y="-2.413" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.4732" y1="-0.381" x2="0.2032" y2="0.381" layer="21"/>
+</package>
+<package name="0414/15" urn="urn:adsk.eagle:footprint:25661/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0414, grid 15 mm</description>
+<wire x1="7.62" y1="0" x2="6.604" y2="0" width="0.8128" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.604" y2="0" width="0.8128" layer="51"/>
+<wire x1="-6.096" y1="1.905" x2="-5.842" y2="2.159" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-6.096" y1="-1.905" x2="-5.842" y2="-2.159" width="0.1524" layer="21" curve="90"/>
+<wire x1="5.842" y1="-2.159" x2="6.096" y2="-1.905" width="0.1524" layer="21" curve="90"/>
+<wire x1="5.842" y1="2.159" x2="6.096" y2="1.905" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-6.096" y1="-1.905" x2="-6.096" y2="1.905" width="0.1524" layer="21"/>
+<wire x1="-5.842" y1="2.159" x2="-4.953" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="2.032" x2="-4.953" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-5.842" y1="-2.159" x2="-4.953" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-2.032" x2="-4.953" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="2.032" x2="4.953" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="2.032" x2="-4.826" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-2.032" x2="4.953" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-2.032" x2="-4.826" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="5.842" y1="2.159" x2="4.953" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="5.842" y1="-2.159" x2="4.953" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="-1.905" x2="6.096" y2="1.905" width="0.1524" layer="21"/>
+<pad name="1" x="-7.62" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.62" y="0" drill="1.016" shape="octagon"/>
+<text x="-6.096" y="2.5654" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.318" y="-0.5842" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="6.096" y1="-0.4064" x2="6.5024" y2="0.4064" layer="21"/>
+<rectangle x1="-6.5024" y1="-0.4064" x2="-6.096" y2="0.4064" layer="21"/>
+</package>
+<package name="0414V" urn="urn:adsk.eagle:footprint:25662/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0414, grid 5 mm</description>
+<wire x1="2.54" y1="0" x2="1.397" y2="0" width="0.8128" layer="51"/>
+<wire x1="-2.54" y1="0" x2="-1.397" y2="0" width="0.8128" layer="51"/>
+<circle x="-2.54" y="0" radius="2.159" width="0.1524" layer="21"/>
+<circle x="-2.54" y="0" radius="1.143" width="0.1524" layer="51"/>
+<pad name="1" x="-2.54" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="1.016" shape="octagon"/>
+<text x="-0.381" y="1.1684" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.381" y="-2.3622" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.2954" y1="-0.4064" x2="1.2954" y2="0.4064" layer="21"/>
+</package>
+<package name="0617/17" urn="urn:adsk.eagle:footprint:25663/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0617, grid 17.5 mm</description>
+<wire x1="-8.89" y1="0" x2="-8.636" y2="0" width="0.8128" layer="51"/>
+<wire x1="-7.874" y1="3.048" x2="-6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="2.794" x2="-6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-7.874" y1="-3.048" x2="-6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="-2.794" x2="-6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="2.794" x2="6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="2.794" x2="-6.731" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="-2.794" x2="6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="-2.794" x2="-6.731" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="7.874" y1="3.048" x2="6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="7.874" y1="-3.048" x2="6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-8.255" y1="-2.667" x2="-8.255" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-8.255" y1="1.016" x2="-8.255" y2="-1.016" width="0.1524" layer="51"/>
+<wire x1="-8.255" y1="1.016" x2="-8.255" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="8.255" y1="-2.667" x2="8.255" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="8.255" y1="1.016" x2="8.255" y2="-1.016" width="0.1524" layer="51"/>
+<wire x1="8.255" y1="1.016" x2="8.255" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="8.636" y1="0" x2="8.89" y2="0" width="0.8128" layer="51"/>
+<wire x1="-8.255" y1="2.667" x2="-7.874" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="7.874" y1="3.048" x2="8.255" y2="2.667" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-8.255" y1="-2.667" x2="-7.874" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="7.874" y1="-3.048" x2="8.255" y2="-2.667" width="0.1524" layer="21" curve="90"/>
+<pad name="1" x="-8.89" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="8.89" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.128" y="3.4544" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-6.096" y="-0.7112" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-8.5344" y1="-0.4064" x2="-8.2296" y2="0.4064" layer="51"/>
+<rectangle x1="8.2296" y1="-0.4064" x2="8.5344" y2="0.4064" layer="51"/>
+</package>
+<package name="0617/22" urn="urn:adsk.eagle:footprint:25664/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0617, grid 22.5 mm</description>
+<wire x1="-10.287" y1="0" x2="-11.43" y2="0" width="0.8128" layer="51"/>
+<wire x1="-8.255" y1="-2.667" x2="-8.255" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="-7.874" y1="3.048" x2="-6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="2.794" x2="-6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-7.874" y1="-3.048" x2="-6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="-2.794" x2="-6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="2.794" x2="6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="2.794" x2="-6.731" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="-2.794" x2="6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="-2.794" x2="-6.731" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="7.874" y1="3.048" x2="6.985" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="7.874" y1="-3.048" x2="6.985" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="8.255" y1="-2.667" x2="8.255" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="11.43" y1="0" x2="10.287" y2="0" width="0.8128" layer="51"/>
+<wire x1="-8.255" y1="2.667" x2="-7.874" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-8.255" y1="-2.667" x2="-7.874" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="7.874" y1="3.048" x2="8.255" y2="2.667" width="0.1524" layer="21" curve="-90"/>
+<wire x1="7.874" y1="-3.048" x2="8.255" y2="-2.667" width="0.1524" layer="21" curve="90"/>
+<pad name="1" x="-11.43" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.43" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.255" y="3.4544" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-6.477" y="-0.5842" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-10.1854" y1="-0.4064" x2="-8.255" y2="0.4064" layer="21"/>
+<rectangle x1="8.255" y1="-0.4064" x2="10.1854" y2="0.4064" layer="21"/>
+</package>
+<package name="0617V" urn="urn:adsk.eagle:footprint:25665/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0617, grid 5 mm</description>
+<wire x1="-2.54" y1="0" x2="-1.27" y2="0" width="0.8128" layer="51"/>
+<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.8128" layer="51"/>
+<circle x="-2.54" y="0" radius="3.048" width="0.1524" layer="21"/>
+<circle x="-2.54" y="0" radius="1.143" width="0.1524" layer="51"/>
+<pad name="1" x="-2.54" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="1.016" shape="octagon"/>
+<text x="0.635" y="1.4224" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="0.635" y="-2.6162" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.3208" y1="-0.4064" x2="1.3208" y2="0.4064" layer="21"/>
+</package>
+<package name="0922/22" urn="urn:adsk.eagle:footprint:25666/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0922, grid 22.5 mm</description>
+<wire x1="11.43" y1="0" x2="10.795" y2="0" width="0.8128" layer="51"/>
+<wire x1="-11.43" y1="0" x2="-10.795" y2="0" width="0.8128" layer="51"/>
+<wire x1="-10.16" y1="-4.191" x2="-10.16" y2="4.191" width="0.1524" layer="21"/>
+<wire x1="-9.779" y1="4.572" x2="-8.89" y2="4.572" width="0.1524" layer="21"/>
+<wire x1="-8.636" y1="4.318" x2="-8.89" y2="4.572" width="0.1524" layer="21"/>
+<wire x1="-9.779" y1="-4.572" x2="-8.89" y2="-4.572" width="0.1524" layer="21"/>
+<wire x1="-8.636" y1="-4.318" x2="-8.89" y2="-4.572" width="0.1524" layer="21"/>
+<wire x1="8.636" y1="4.318" x2="8.89" y2="4.572" width="0.1524" layer="21"/>
+<wire x1="8.636" y1="4.318" x2="-8.636" y2="4.318" width="0.1524" layer="21"/>
+<wire x1="8.636" y1="-4.318" x2="8.89" y2="-4.572" width="0.1524" layer="21"/>
+<wire x1="8.636" y1="-4.318" x2="-8.636" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="9.779" y1="4.572" x2="8.89" y2="4.572" width="0.1524" layer="21"/>
+<wire x1="9.779" y1="-4.572" x2="8.89" y2="-4.572" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="-4.191" x2="10.16" y2="4.191" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-4.191" x2="-9.779" y2="-4.572" width="0.1524" layer="21" curve="90"/>
+<wire x1="-10.16" y1="4.191" x2="-9.779" y2="4.572" width="0.1524" layer="21" curve="-90"/>
+<wire x1="9.779" y1="-4.572" x2="10.16" y2="-4.191" width="0.1524" layer="21" curve="90"/>
+<wire x1="9.779" y1="4.572" x2="10.16" y2="4.191" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-11.43" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.43" y="0" drill="1.016" shape="octagon"/>
+<text x="-10.16" y="5.1054" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-6.477" y="-0.5842" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-10.7188" y1="-0.4064" x2="-10.16" y2="0.4064" layer="51"/>
+<rectangle x1="10.16" y1="-0.4064" x2="10.3124" y2="0.4064" layer="21"/>
+<rectangle x1="-10.3124" y1="-0.4064" x2="-10.16" y2="0.4064" layer="21"/>
+<rectangle x1="10.16" y1="-0.4064" x2="10.7188" y2="0.4064" layer="51"/>
+</package>
+<package name="P0613V" urn="urn:adsk.eagle:footprint:25667/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0613, grid 5 mm</description>
+<wire x1="2.54" y1="0" x2="1.397" y2="0" width="0.8128" layer="51"/>
+<wire x1="-2.54" y1="0" x2="-1.397" y2="0" width="0.8128" layer="51"/>
+<circle x="-2.54" y="0" radius="2.286" width="0.1524" layer="21"/>
+<circle x="-2.54" y="0" radius="1.143" width="0.1524" layer="51"/>
+<pad name="1" x="-2.54" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="1.016" shape="octagon"/>
+<text x="-0.254" y="1.143" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.254" y="-2.413" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.2954" y1="-0.4064" x2="1.3208" y2="0.4064" layer="21"/>
+</package>
+<package name="P0613/15" urn="urn:adsk.eagle:footprint:25668/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0613, grid 15 mm</description>
+<wire x1="7.62" y1="0" x2="6.985" y2="0" width="0.8128" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.985" y2="0" width="0.8128" layer="51"/>
+<wire x1="-6.477" y1="2.032" x2="-6.223" y2="2.286" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-6.477" y1="-2.032" x2="-6.223" y2="-2.286" width="0.1524" layer="21" curve="90"/>
+<wire x1="6.223" y1="-2.286" x2="6.477" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="6.223" y1="2.286" x2="6.477" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-6.223" y1="2.286" x2="-5.334" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="2.159" x2="-5.334" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="-6.223" y1="-2.286" x2="-5.334" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="-2.159" x2="-5.334" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="2.159" x2="5.334" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="2.159" x2="-5.207" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-2.159" x2="5.334" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-2.159" x2="-5.207" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="6.223" y1="2.286" x2="5.334" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="6.223" y1="-2.286" x2="5.334" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="6.477" y1="-0.635" x2="6.477" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="6.477" y1="-0.635" x2="6.477" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="6.477" y1="2.032" x2="6.477" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-6.477" y1="-2.032" x2="-6.477" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-6.477" y1="0.635" x2="-6.477" y2="-0.635" width="0.1524" layer="51"/>
+<wire x1="-6.477" y1="0.635" x2="-6.477" y2="2.032" width="0.1524" layer="21"/>
+<pad name="1" x="-7.62" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.62" y="0" drill="1.016" shape="octagon"/>
+<text x="-6.477" y="2.6924" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.318" y="-0.7112" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-7.0358" y1="-0.4064" x2="-6.477" y2="0.4064" layer="51"/>
+<rectangle x1="6.477" y1="-0.4064" x2="7.0358" y2="0.4064" layer="51"/>
+</package>
+<package name="P0817/22" urn="urn:adsk.eagle:footprint:25669/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0817, grid 22.5 mm</description>
+<wire x1="-10.414" y1="0" x2="-11.43" y2="0" width="0.8128" layer="51"/>
+<wire x1="-8.509" y1="-3.429" x2="-8.509" y2="3.429" width="0.1524" layer="21"/>
+<wire x1="-8.128" y1="3.81" x2="-7.239" y2="3.81" width="0.1524" layer="21"/>
+<wire x1="-6.985" y1="3.556" x2="-7.239" y2="3.81" width="0.1524" layer="21"/>
+<wire x1="-8.128" y1="-3.81" x2="-7.239" y2="-3.81" width="0.1524" layer="21"/>
+<wire x1="-6.985" y1="-3.556" x2="-7.239" y2="-3.81" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="3.556" x2="7.239" y2="3.81" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="3.556" x2="-6.985" y2="3.556" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="-3.556" x2="7.239" y2="-3.81" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="-3.556" x2="-6.985" y2="-3.556" width="0.1524" layer="21"/>
+<wire x1="8.128" y1="3.81" x2="7.239" y2="3.81" width="0.1524" layer="21"/>
+<wire x1="8.128" y1="-3.81" x2="7.239" y2="-3.81" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="-3.429" x2="8.509" y2="3.429" width="0.1524" layer="21"/>
+<wire x1="11.43" y1="0" x2="10.414" y2="0" width="0.8128" layer="51"/>
+<wire x1="-8.509" y1="3.429" x2="-8.128" y2="3.81" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-8.509" y1="-3.429" x2="-8.128" y2="-3.81" width="0.1524" layer="21" curve="90"/>
+<wire x1="8.128" y1="3.81" x2="8.509" y2="3.429" width="0.1524" layer="21" curve="-90"/>
+<wire x1="8.128" y1="-3.81" x2="8.509" y2="-3.429" width="0.1524" layer="21" curve="90"/>
+<pad name="1" x="-11.43" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.43" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.382" y="4.2164" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-6.223" y="-0.5842" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="6.604" y="-2.2606" size="1.27" layer="51" ratio="10" rot="R90">0817</text>
+<rectangle x1="8.509" y1="-0.4064" x2="10.3124" y2="0.4064" layer="21"/>
+<rectangle x1="-10.3124" y1="-0.4064" x2="-8.509" y2="0.4064" layer="21"/>
+</package>
+<package name="P0817V" urn="urn:adsk.eagle:footprint:25670/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0817, grid 6.35 mm</description>
+<wire x1="-3.81" y1="0" x2="-5.08" y2="0" width="0.8128" layer="51"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.8128" layer="51"/>
+<circle x="-5.08" y="0" radius="3.81" width="0.1524" layer="21"/>
+<circle x="-5.08" y="0" radius="1.27" width="0.1524" layer="51"/>
+<pad name="1" x="-5.08" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="1.016" shape="octagon"/>
+<text x="-1.016" y="1.27" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.016" y="-2.54" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-6.858" y="2.032" size="1.016" layer="21" ratio="12">0817</text>
+<rectangle x1="-3.81" y1="-0.4064" x2="0" y2="0.4064" layer="21"/>
+</package>
+<package name="V234/12" urn="urn:adsk.eagle:footprint:25671/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type V234, grid 12.5 mm</description>
+<wire x1="-4.953" y1="1.524" x2="-4.699" y2="1.778" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="1.778" x2="4.953" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="-1.778" x2="4.953" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="-4.953" y1="-1.524" x2="-4.699" y2="-1.778" width="0.1524" layer="21" curve="90"/>
+<wire x1="-4.699" y1="1.778" x2="4.699" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="1.524" x2="-4.953" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-1.778" x2="-4.699" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="1.524" x2="4.953" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="0" x2="5.461" y2="0" width="0.8128" layer="51"/>
+<wire x1="-6.35" y1="0" x2="-5.461" y2="0" width="0.8128" layer="51"/>
+<pad name="1" x="-6.35" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="6.35" y="0" drill="1.016" shape="octagon"/>
+<text x="-4.953" y="2.159" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.81" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="4.953" y1="-0.4064" x2="5.4102" y2="0.4064" layer="21"/>
+<rectangle x1="-5.4102" y1="-0.4064" x2="-4.953" y2="0.4064" layer="21"/>
+</package>
+<package name="V235/17" urn="urn:adsk.eagle:footprint:25672/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type V235, grid 17.78 mm</description>
+<wire x1="-6.731" y1="2.921" x2="6.731" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-7.112" y1="2.54" x2="-7.112" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="-2.921" x2="-6.731" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="7.112" y1="2.54" x2="7.112" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="8.89" y1="0" x2="7.874" y2="0" width="1.016" layer="51"/>
+<wire x1="-7.874" y1="0" x2="-8.89" y2="0" width="1.016" layer="51"/>
+<wire x1="-7.112" y1="-2.54" x2="-6.731" y2="-2.921" width="0.1524" layer="21" curve="90"/>
+<wire x1="6.731" y1="2.921" x2="7.112" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="6.731" y1="-2.921" x2="7.112" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-7.112" y1="2.54" x2="-6.731" y2="2.921" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-8.89" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="8.89" y="0" drill="1.1938" shape="octagon"/>
+<text x="-6.858" y="3.302" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.842" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="7.112" y1="-0.508" x2="7.747" y2="0.508" layer="21"/>
+<rectangle x1="-7.747" y1="-0.508" x2="-7.112" y2="0.508" layer="21"/>
+</package>
+<package name="V526-0" urn="urn:adsk.eagle:footprint:25673/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type V526-0, grid 2.5 mm</description>
+<wire x1="-2.54" y1="1.016" x2="-2.286" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.286" y1="1.27" x2="2.54" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.286" y1="-1.27" x2="2.54" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.54" y1="-1.016" x2="-2.286" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.286" y1="1.27" x2="-2.286" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="-1.27" x2="2.286" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="1.016" x2="-2.54" y2="-1.016" width="0.1524" layer="21"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.413" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.413" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="MINI_MELF-0102R" urn="urn:adsk.eagle:footprint:25674/1" library_version="1">
+<description>&lt;b&gt;CECC Size RC2211&lt;/b&gt; Reflow Soldering&lt;p&gt;
+source Beyschlag</description>
+<wire x1="-1" y1="-0.5" x2="1" y2="-0.5" width="0.2032" layer="51"/>
+<wire x1="1" y1="-0.5" x2="1" y2="0.5" width="0.2032" layer="51"/>
+<wire x1="1" y1="0.5" x2="-1" y2="0.5" width="0.2032" layer="51"/>
+<wire x1="-1" y1="0.5" x2="-1" y2="-0.5" width="0.2032" layer="51"/>
+<smd name="1" x="-0.9" y="0" dx="0.5" dy="1.3" layer="1"/>
+<smd name="2" x="0.9" y="0" dx="0.5" dy="1.3" layer="1"/>
+<text x="-1.27" y="0.9525" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.2225" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="MINI_MELF-0102W" urn="urn:adsk.eagle:footprint:25675/1" library_version="1">
+<description>&lt;b&gt;CECC Size RC2211&lt;/b&gt; Wave Soldering&lt;p&gt;
+source Beyschlag</description>
+<wire x1="-1" y1="-0.5" x2="1" y2="-0.5" width="0.2032" layer="51"/>
+<wire x1="1" y1="-0.5" x2="1" y2="0.5" width="0.2032" layer="51"/>
+<wire x1="1" y1="0.5" x2="-1" y2="0.5" width="0.2032" layer="51"/>
+<wire x1="-1" y1="0.5" x2="-1" y2="-0.5" width="0.2032" layer="51"/>
+<smd name="1" x="-0.95" y="0" dx="0.6" dy="1.3" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="0.6" dy="1.3" layer="1"/>
+<text x="-1.27" y="0.9525" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.2225" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="MINI_MELF-0204R" urn="urn:adsk.eagle:footprint:25676/1" library_version="1">
+<description>&lt;b&gt;CECC Size RC3715&lt;/b&gt; Reflow Soldering&lt;p&gt;
+source Beyschlag</description>
+<wire x1="-1.7" y1="-0.6" x2="1.7" y2="-0.6" width="0.2032" layer="51"/>
+<wire x1="1.7" y1="-0.6" x2="1.7" y2="0.6" width="0.2032" layer="51"/>
+<wire x1="1.7" y1="0.6" x2="-1.7" y2="0.6" width="0.2032" layer="51"/>
+<wire x1="-1.7" y1="0.6" x2="-1.7" y2="-0.6" width="0.2032" layer="51"/>
+<wire x1="0.938" y1="0.6" x2="-0.938" y2="0.6" width="0.2032" layer="21"/>
+<wire x1="-0.938" y1="-0.6" x2="0.938" y2="-0.6" width="0.2032" layer="21"/>
+<smd name="1" x="-1.5" y="0" dx="0.8" dy="1.6" layer="1"/>
+<smd name="2" x="1.5" y="0" dx="0.8" dy="1.6" layer="1"/>
+<text x="-1.27" y="0.9525" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.2225" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="MINI_MELF-0204W" urn="urn:adsk.eagle:footprint:25677/1" library_version="1">
+<description>&lt;b&gt;CECC Size RC3715&lt;/b&gt; Wave Soldering&lt;p&gt;
+source Beyschlag</description>
+<wire x1="-1.7" y1="-0.6" x2="1.7" y2="-0.6" width="0.2032" layer="51"/>
+<wire x1="1.7" y1="-0.6" x2="1.7" y2="0.6" width="0.2032" layer="51"/>
+<wire x1="1.7" y1="0.6" x2="-1.7" y2="0.6" width="0.2032" layer="51"/>
+<wire x1="-1.7" y1="0.6" x2="-1.7" y2="-0.6" width="0.2032" layer="51"/>
+<wire x1="0.684" y1="0.6" x2="-0.684" y2="0.6" width="0.2032" layer="21"/>
+<wire x1="-0.684" y1="-0.6" x2="0.684" y2="-0.6" width="0.2032" layer="21"/>
+<smd name="1" x="-1.5" y="0" dx="1.2" dy="1.6" layer="1"/>
+<smd name="2" x="1.5" y="0" dx="1.2" dy="1.6" layer="1"/>
+<text x="-1.27" y="0.9525" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.2225" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="MINI_MELF-0207R" urn="urn:adsk.eagle:footprint:25678/1" library_version="1">
+<description>&lt;b&gt;CECC Size RC6123&lt;/b&gt; Reflow Soldering&lt;p&gt;
+source Beyschlag</description>
+<wire x1="-2.8" y1="-1" x2="2.8" y2="-1" width="0.2032" layer="51"/>
+<wire x1="2.8" y1="-1" x2="2.8" y2="1" width="0.2032" layer="51"/>
+<wire x1="2.8" y1="1" x2="-2.8" y2="1" width="0.2032" layer="51"/>
+<wire x1="-2.8" y1="1" x2="-2.8" y2="-1" width="0.2032" layer="51"/>
+<wire x1="1.2125" y1="1" x2="-1.2125" y2="1" width="0.2032" layer="21"/>
+<wire x1="-1.2125" y1="-1" x2="1.2125" y2="-1" width="0.2032" layer="21"/>
+<smd name="1" x="-2.25" y="0" dx="1.6" dy="2.5" layer="1"/>
+<smd name="2" x="2.25" y="0" dx="1.6" dy="2.5" layer="1"/>
+<text x="-2.2225" y="1.5875" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.2225" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="MINI_MELF-0207W" urn="urn:adsk.eagle:footprint:25679/1" library_version="1">
+<description>&lt;b&gt;CECC Size RC6123&lt;/b&gt; Wave Soldering&lt;p&gt;
+source Beyschlag</description>
+<wire x1="-2.8" y1="-1" x2="2.8" y2="-1" width="0.2032" layer="51"/>
+<wire x1="2.8" y1="-1" x2="2.8" y2="1" width="0.2032" layer="51"/>
+<wire x1="2.8" y1="1" x2="-2.8" y2="1" width="0.2032" layer="51"/>
+<wire x1="-2.8" y1="1" x2="-2.8" y2="-1" width="0.2032" layer="51"/>
+<wire x1="1.149" y1="1" x2="-1.149" y2="1" width="0.2032" layer="21"/>
+<wire x1="-1.149" y1="-1" x2="1.149" y2="-1" width="0.2032" layer="21"/>
+<smd name="1" x="-2.6" y="0" dx="2.4" dy="2.5" layer="1"/>
+<smd name="2" x="2.6" y="0" dx="2.4" dy="2.5" layer="1"/>
+<text x="-2.54" y="1.5875" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="0922V" urn="urn:adsk.eagle:footprint:25680/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0922, grid 7.5 mm</description>
+<wire x1="2.54" y1="0" x2="1.397" y2="0" width="0.8128" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-3.81" y2="0" width="0.8128" layer="51"/>
+<circle x="-5.08" y="0" radius="4.572" width="0.1524" layer="21"/>
+<circle x="-5.08" y="0" radius="1.905" width="0.1524" layer="21"/>
+<pad name="1" x="-5.08" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="1.016" shape="octagon"/>
+<text x="-0.508" y="1.6764" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.508" y="-2.9972" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-6.858" y="2.54" size="1.016" layer="21" ratio="12">0922</text>
+<rectangle x1="-3.81" y1="-0.4064" x2="1.3208" y2="0.4064" layer="21"/>
+</package>
+<package name="RDH/15" urn="urn:adsk.eagle:footprint:25681/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type RDH, grid 15 mm</description>
+<wire x1="-7.62" y1="0" x2="-6.858" y2="0" width="0.8128" layer="51"/>
+<wire x1="-6.096" y1="3.048" x2="-5.207" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="2.794" x2="-5.207" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-6.096" y1="-3.048" x2="-5.207" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="-2.794" x2="-5.207" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="2.794" x2="5.207" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="2.794" x2="-4.953" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="-2.794" x2="5.207" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="-2.794" x2="-4.953" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="3.048" x2="5.207" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="-3.048" x2="5.207" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-6.477" y1="-2.667" x2="-6.477" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-6.477" y1="1.016" x2="-6.477" y2="-1.016" width="0.1524" layer="51"/>
+<wire x1="-6.477" y1="1.016" x2="-6.477" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="6.477" y1="-2.667" x2="6.477" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="6.477" y1="1.016" x2="6.477" y2="-1.016" width="0.1524" layer="51"/>
+<wire x1="6.477" y1="1.016" x2="6.477" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="6.858" y1="0" x2="7.62" y2="0" width="0.8128" layer="51"/>
+<wire x1="-6.477" y1="2.667" x2="-6.096" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="6.096" y1="3.048" x2="6.477" y2="2.667" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-6.477" y1="-2.667" x2="-6.096" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="6.096" y1="-3.048" x2="6.477" y2="-2.667" width="0.1524" layer="21" curve="90"/>
+<pad name="1" x="-7.62" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.62" y="0" drill="1.016" shape="octagon"/>
+<text x="-6.35" y="3.4544" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.318" y="-0.5842" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="4.572" y="-1.7272" size="1.27" layer="51" ratio="10" rot="R90">RDH</text>
+<rectangle x1="-6.7564" y1="-0.4064" x2="-6.4516" y2="0.4064" layer="51"/>
+<rectangle x1="6.4516" y1="-0.4064" x2="6.7564" y2="0.4064" layer="51"/>
+</package>
+<package name="MINI_MELF-0102AX" urn="urn:adsk.eagle:footprint:25682/1" library_version="1">
+<description>&lt;b&gt;Mini MELF 0102 Axial&lt;/b&gt;</description>
+<circle x="0" y="0" radius="0.6" width="0" layer="51"/>
+<circle x="0" y="0" radius="0.6" width="0" layer="52"/>
+<smd name="1" x="0" y="0" dx="1.9" dy="1.9" layer="1" roundness="100"/>
+<smd name="2" x="0" y="0" dx="1.9" dy="1.9" layer="16" roundness="100"/>
+<text x="-1.27" y="0.9525" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.2225" size="1.27" layer="27">&gt;VALUE</text>
+<hole x="0" y="0" drill="1.3"/>
+</package>
+<package name="R0201" urn="urn:adsk.eagle:footprint:25683/1" library_version="1">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt; chip&lt;p&gt;
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf</description>
+<smd name="1" x="-0.255" y="0" dx="0.28" dy="0.43" layer="1"/>
+<smd name="2" x="0.255" y="0" dx="0.28" dy="0.43" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.3" y1="-0.15" x2="-0.15" y2="0.15" layer="51"/>
+<rectangle x1="0.15" y1="-0.15" x2="0.3" y2="0.15" layer="51"/>
+<rectangle x1="-0.15" y1="-0.15" x2="0.15" y2="0.15" layer="21"/>
+</package>
+<package name="VTA52" urn="urn:adsk.eagle:footprint:25684/1" library_version="1">
+<description>&lt;b&gt;Bulk Metal® Foil Technology&lt;/b&gt;, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements&lt;p&gt;
+MIL SIZE RBR52&lt;br&gt;
+Source: VISHAY .. vta56.pdf</description>
+<wire x1="-15.24" y1="0" x2="-13.97" y2="0" width="0.6096" layer="51"/>
+<wire x1="12.6225" y1="0.025" x2="12.6225" y2="4.725" width="0.1524" layer="21"/>
+<wire x1="12.6225" y1="4.725" x2="-12.6225" y2="4.725" width="0.1524" layer="21"/>
+<wire x1="-12.6225" y1="4.725" x2="-12.6225" y2="0.025" width="0.1524" layer="21"/>
+<wire x1="-12.6225" y1="0.025" x2="-12.6225" y2="-4.65" width="0.1524" layer="21"/>
+<wire x1="-12.6225" y1="-4.65" x2="12.6225" y2="-4.65" width="0.1524" layer="21"/>
+<wire x1="12.6225" y1="-4.65" x2="12.6225" y2="0.025" width="0.1524" layer="21"/>
+<wire x1="13.97" y1="0" x2="15.24" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-15.24" y="0" drill="1.1" shape="octagon"/>
+<pad name="2" x="15.24" y="0" drill="1.1" shape="octagon"/>
+<text x="-3.81" y="5.08" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-13.97" y1="-0.3048" x2="-12.5675" y2="0.3048" layer="21"/>
+<rectangle x1="12.5675" y1="-0.3048" x2="13.97" y2="0.3048" layer="21"/>
+</package>
+<package name="VTA53" urn="urn:adsk.eagle:footprint:25685/1" library_version="1">
+<description>&lt;b&gt;Bulk Metal® Foil Technology&lt;/b&gt;, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements&lt;p&gt;
+MIL SIZE RBR53&lt;br&gt;
+Source: VISHAY .. vta56.pdf</description>
+<wire x1="-12.065" y1="0" x2="-10.795" y2="0" width="0.6096" layer="51"/>
+<wire x1="9.8975" y1="0" x2="9.8975" y2="4.7" width="0.1524" layer="21"/>
+<wire x1="9.8975" y1="4.7" x2="-9.8975" y2="4.7" width="0.1524" layer="21"/>
+<wire x1="-9.8975" y1="4.7" x2="-9.8975" y2="0" width="0.1524" layer="21"/>
+<wire x1="-9.8975" y1="0" x2="-9.8975" y2="-4.675" width="0.1524" layer="21"/>
+<wire x1="-9.8975" y1="-4.675" x2="9.8975" y2="-4.675" width="0.1524" layer="21"/>
+<wire x1="9.8975" y1="-4.675" x2="9.8975" y2="0" width="0.1524" layer="21"/>
+<wire x1="10.795" y1="0" x2="12.065" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-12.065" y="0" drill="1.1" shape="octagon"/>
+<pad name="2" x="12.065" y="0" drill="1.1" shape="octagon"/>
+<text x="-3.81" y="5.08" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-10.795" y1="-0.3048" x2="-9.8425" y2="0.3048" layer="21"/>
+<rectangle x1="9.8425" y1="-0.3048" x2="10.795" y2="0.3048" layer="21"/>
+</package>
+<package name="VTA54" urn="urn:adsk.eagle:footprint:25686/1" library_version="1">
+<description>&lt;b&gt;Bulk Metal® Foil Technology&lt;/b&gt;, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements&lt;p&gt;
+MIL SIZE RBR54&lt;br&gt;
+Source: VISHAY .. vta56.pdf</description>
+<wire x1="-12.065" y1="0" x2="-10.795" y2="0" width="0.6096" layer="51"/>
+<wire x1="9.8975" y1="0" x2="9.8975" y2="3.3" width="0.1524" layer="21"/>
+<wire x1="9.8975" y1="3.3" x2="-9.8975" y2="3.3" width="0.1524" layer="21"/>
+<wire x1="-9.8975" y1="3.3" x2="-9.8975" y2="0" width="0.1524" layer="21"/>
+<wire x1="-9.8975" y1="0" x2="-9.8975" y2="-3.3" width="0.1524" layer="21"/>
+<wire x1="-9.8975" y1="-3.3" x2="9.8975" y2="-3.3" width="0.1524" layer="21"/>
+<wire x1="9.8975" y1="-3.3" x2="9.8975" y2="0" width="0.1524" layer="21"/>
+<wire x1="10.795" y1="0" x2="12.065" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-12.065" y="0" drill="1.1" shape="octagon"/>
+<pad name="2" x="12.065" y="0" drill="1.1" shape="octagon"/>
+<text x="-3.81" y="3.81" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-10.795" y1="-0.3048" x2="-9.8425" y2="0.3048" layer="21"/>
+<rectangle x1="9.8425" y1="-0.3048" x2="10.795" y2="0.3048" layer="21"/>
+</package>
+<package name="VTA55" urn="urn:adsk.eagle:footprint:25687/1" library_version="1">
+<description>&lt;b&gt;Bulk Metal® Foil Technology&lt;/b&gt;, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements&lt;p&gt;
+MIL SIZE RBR55&lt;br&gt;
+Source: VISHAY .. vta56.pdf</description>
+<wire x1="-8.255" y1="0" x2="-6.985" y2="0" width="0.6096" layer="51"/>
+<wire x1="6.405" y1="0" x2="6.405" y2="3.3" width="0.1524" layer="21"/>
+<wire x1="6.405" y1="3.3" x2="-6.405" y2="3.3" width="0.1524" layer="21"/>
+<wire x1="-6.405" y1="3.3" x2="-6.405" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.405" y1="0" x2="-6.405" y2="-3.3" width="0.1524" layer="21"/>
+<wire x1="-6.405" y1="-3.3" x2="6.405" y2="-3.3" width="0.1524" layer="21"/>
+<wire x1="6.405" y1="-3.3" x2="6.405" y2="0" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="0" x2="8.255" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-8.255" y="0" drill="1.1" shape="octagon"/>
+<pad name="2" x="8.255" y="0" drill="1.1" shape="octagon"/>
+<text x="-3.81" y="3.81" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-6.985" y1="-0.3048" x2="-6.35" y2="0.3048" layer="21"/>
+<rectangle x1="6.35" y1="-0.3048" x2="6.985" y2="0.3048" layer="21"/>
+</package>
+<package name="VTA56" urn="urn:adsk.eagle:footprint:25688/1" library_version="1">
+<description>&lt;b&gt;Bulk Metal® Foil Technology&lt;/b&gt;, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements&lt;p&gt;
+MIL SIZE RBR56&lt;br&gt;
+Source: VISHAY .. vta56.pdf</description>
+<wire x1="-6.35" y1="0" x2="-5.08" y2="0" width="0.6096" layer="51"/>
+<wire x1="4.5" y1="0" x2="4.5" y2="3.3" width="0.1524" layer="21"/>
+<wire x1="4.5" y1="3.3" x2="-4.5" y2="3.3" width="0.1524" layer="21"/>
+<wire x1="-4.5" y1="3.3" x2="-4.5" y2="0" width="0.1524" layer="21"/>
+<wire x1="-4.5" y1="0" x2="-4.5" y2="-3.3" width="0.1524" layer="21"/>
+<wire x1="-4.5" y1="-3.3" x2="4.5" y2="-3.3" width="0.1524" layer="21"/>
+<wire x1="4.5" y1="-3.3" x2="4.5" y2="0" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0" x2="6.35" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-6.35" y="0" drill="1.1" shape="octagon"/>
+<pad name="2" x="6.35" y="0" drill="1.1" shape="octagon"/>
+<text x="-3.81" y="3.81" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-5.08" y1="-0.3048" x2="-4.445" y2="0.3048" layer="21"/>
+<rectangle x1="4.445" y1="-0.3048" x2="5.08" y2="0.3048" layer="21"/>
+</package>
+<package name="VMTA55" urn="urn:adsk.eagle:footprint:25689/1" library_version="1">
+<description>&lt;b&gt;Bulk Metal® Foil Technology&lt;/b&gt;, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements&lt;p&gt;
+MIL SIZE RNC55&lt;br&gt;
+Source: VISHAY .. vta56.pdf</description>
+<wire x1="-5.08" y1="0" x2="-4.26" y2="0" width="0.6096" layer="51"/>
+<wire x1="3.3375" y1="-1.45" x2="3.3375" y2="1.45" width="0.1524" layer="21"/>
+<wire x1="3.3375" y1="1.45" x2="-3.3625" y2="1.45" width="0.1524" layer="21"/>
+<wire x1="-3.3625" y1="1.45" x2="-3.3625" y2="-1.45" width="0.1524" layer="21"/>
+<wire x1="-3.3625" y1="-1.45" x2="3.3375" y2="-1.45" width="0.1524" layer="21"/>
+<wire x1="4.235" y1="0" x2="5.08" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-5.08" y="0" drill="1.1" shape="octagon"/>
+<pad name="2" x="5.08" y="0" drill="1.1" shape="octagon"/>
+<text x="-3.175" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-4.26" y1="-0.3048" x2="-3.3075" y2="0.3048" layer="21"/>
+<rectangle x1="3.2825" y1="-0.3048" x2="4.235" y2="0.3048" layer="21"/>
+</package>
+<package name="VMTB60" urn="urn:adsk.eagle:footprint:25690/1" library_version="1">
+<description>&lt;b&gt;Bulk Metal® Foil Technology&lt;/b&gt;, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements&lt;p&gt;
+MIL SIZE RNC60&lt;br&gt;
+Source: VISHAY .. vta56.pdf</description>
+<wire x1="-6.35" y1="0" x2="-5.585" y2="0" width="0.6096" layer="51"/>
+<wire x1="4.6875" y1="-1.95" x2="4.6875" y2="1.95" width="0.1524" layer="21"/>
+<wire x1="4.6875" y1="1.95" x2="-4.6875" y2="1.95" width="0.1524" layer="21"/>
+<wire x1="-4.6875" y1="1.95" x2="-4.6875" y2="-1.95" width="0.1524" layer="21"/>
+<wire x1="-4.6875" y1="-1.95" x2="4.6875" y2="-1.95" width="0.1524" layer="21"/>
+<wire x1="5.585" y1="0" x2="6.35" y2="0" width="0.6096" layer="51"/>
+<pad name="1" x="-6.35" y="0" drill="1.1" shape="octagon"/>
+<pad name="2" x="6.35" y="0" drill="1.1" shape="octagon"/>
+<text x="-4.445" y="2.54" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.445" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-5.585" y1="-0.3048" x2="-4.6325" y2="0.3048" layer="21"/>
+<rectangle x1="4.6325" y1="-0.3048" x2="5.585" y2="0.3048" layer="21"/>
+</package>
+<package name="R4527" urn="urn:adsk.eagle:footprint:25691/1" library_version="1">
+<description>&lt;b&gt;Package 4527&lt;/b&gt;&lt;p&gt;
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf</description>
+<wire x1="-5.675" y1="-3.375" x2="5.65" y2="-3.375" width="0.2032" layer="21"/>
+<wire x1="5.65" y1="-3.375" x2="5.65" y2="3.375" width="0.2032" layer="51"/>
+<wire x1="5.65" y1="3.375" x2="-5.675" y2="3.375" width="0.2032" layer="21"/>
+<wire x1="-5.675" y1="3.375" x2="-5.675" y2="-3.375" width="0.2032" layer="51"/>
+<smd name="1" x="-4.575" y="0" dx="3.94" dy="5.84" layer="1"/>
+<smd name="2" x="4.575" y="0" dx="3.94" dy="5.84" layer="1"/>
+<text x="-5.715" y="3.81" size="1.27" layer="25">&gt;NAME</text>
+<text x="-5.715" y="-5.08" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="WSC0001" urn="urn:adsk.eagle:footprint:25692/1" library_version="1">
+<description>&lt;b&gt;Wirewound Resistors, Precision Power&lt;/b&gt;&lt;p&gt;
+Source: VISHAY wscwsn.pdf</description>
+<wire x1="-3.075" y1="1.8" x2="-3.075" y2="-1.8" width="0.2032" layer="51"/>
+<wire x1="-3.075" y1="-1.8" x2="3.075" y2="-1.8" width="0.2032" layer="21"/>
+<wire x1="3.075" y1="-1.8" x2="3.075" y2="1.8" width="0.2032" layer="51"/>
+<wire x1="3.075" y1="1.8" x2="-3.075" y2="1.8" width="0.2032" layer="21"/>
+<wire x1="-3.075" y1="1.8" x2="-3.075" y2="1.606" width="0.2032" layer="21"/>
+<wire x1="-3.075" y1="-1.606" x2="-3.075" y2="-1.8" width="0.2032" layer="21"/>
+<wire x1="3.075" y1="1.606" x2="3.075" y2="1.8" width="0.2032" layer="21"/>
+<wire x1="3.075" y1="-1.8" x2="3.075" y2="-1.606" width="0.2032" layer="21"/>
+<smd name="1" x="-2.675" y="0" dx="2.29" dy="2.92" layer="1"/>
+<smd name="2" x="2.675" y="0" dx="2.29" dy="2.92" layer="1"/>
+<text x="-2.544" y="2.229" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.544" y="-3.501" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="WSC0002" urn="urn:adsk.eagle:footprint:25693/1" library_version="1">
+<description>&lt;b&gt;Wirewound Resistors, Precision Power&lt;/b&gt;&lt;p&gt;
+Source: VISHAY wscwsn.pdf</description>
+<wire x1="-5.55" y1="3.375" x2="-5.55" y2="-3.375" width="0.2032" layer="51"/>
+<wire x1="-5.55" y1="-3.375" x2="5.55" y2="-3.375" width="0.2032" layer="21"/>
+<wire x1="5.55" y1="-3.375" x2="5.55" y2="3.375" width="0.2032" layer="51"/>
+<wire x1="5.55" y1="3.375" x2="-5.55" y2="3.375" width="0.2032" layer="21"/>
+<smd name="1" x="-4.575" y="0.025" dx="3.94" dy="5.84" layer="1"/>
+<smd name="2" x="4.575" y="0" dx="3.94" dy="5.84" layer="1"/>
+<text x="-5.65" y="3.9" size="1.27" layer="25">&gt;NAME</text>
+<text x="-5.65" y="-5.15" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="WSC01/2" urn="urn:adsk.eagle:footprint:25694/1" library_version="1">
+<description>&lt;b&gt;Wirewound Resistors, Precision Power&lt;/b&gt;&lt;p&gt;
+Source: VISHAY wscwsn.pdf</description>
+<wire x1="-2.45" y1="1.475" x2="-2.45" y2="-1.475" width="0.2032" layer="51"/>
+<wire x1="-2.45" y1="-1.475" x2="2.45" y2="-1.475" width="0.2032" layer="21"/>
+<wire x1="2.45" y1="-1.475" x2="2.45" y2="1.475" width="0.2032" layer="51"/>
+<wire x1="2.45" y1="1.475" x2="-2.45" y2="1.475" width="0.2032" layer="21"/>
+<wire x1="-2.45" y1="1.475" x2="-2.45" y2="1.106" width="0.2032" layer="21"/>
+<wire x1="-2.45" y1="-1.106" x2="-2.45" y2="-1.475" width="0.2032" layer="21"/>
+<wire x1="2.45" y1="1.106" x2="2.45" y2="1.475" width="0.2032" layer="21"/>
+<wire x1="2.45" y1="-1.475" x2="2.45" y2="-1.106" width="0.2032" layer="21"/>
+<smd name="1" x="-2.1" y="0" dx="2.16" dy="1.78" layer="1"/>
+<smd name="2" x="2.1" y="0" dx="2.16" dy="1.78" layer="1"/>
+<text x="-2.544" y="1.904" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.544" y="-3.176" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="WSC2515" urn="urn:adsk.eagle:footprint:25695/1" library_version="1">
+<description>&lt;b&gt;Wirewound Resistors, Precision Power&lt;/b&gt;&lt;p&gt;
+Source: VISHAY wscwsn.pdf</description>
+<wire x1="-3.075" y1="1.8" x2="-3.075" y2="-1.8" width="0.2032" layer="51"/>
+<wire x1="-3.075" y1="-1.8" x2="3.05" y2="-1.8" width="0.2032" layer="21"/>
+<wire x1="3.05" y1="-1.8" x2="3.05" y2="1.8" width="0.2032" layer="51"/>
+<wire x1="3.05" y1="1.8" x2="-3.075" y2="1.8" width="0.2032" layer="21"/>
+<wire x1="-3.075" y1="1.8" x2="-3.075" y2="1.606" width="0.2032" layer="21"/>
+<wire x1="-3.075" y1="-1.606" x2="-3.075" y2="-1.8" width="0.2032" layer="21"/>
+<wire x1="3.05" y1="1.606" x2="3.05" y2="1.8" width="0.2032" layer="21"/>
+<wire x1="3.05" y1="-1.8" x2="3.05" y2="-1.606" width="0.2032" layer="21"/>
+<smd name="1" x="-2.675" y="0" dx="2.29" dy="2.92" layer="1"/>
+<smd name="2" x="2.675" y="0" dx="2.29" dy="2.92" layer="1"/>
+<text x="-3.2" y="2.15" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.2" y="-3.4" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="WSC4527" urn="urn:adsk.eagle:footprint:25696/1" library_version="1">
+<description>&lt;b&gt;Wirewound Resistors, Precision Power&lt;/b&gt;&lt;p&gt;
+Source: VISHAY wscwsn.pdf</description>
+<wire x1="-5.675" y1="3.4" x2="-5.675" y2="-3.375" width="0.2032" layer="51"/>
+<wire x1="-5.675" y1="-3.375" x2="5.675" y2="-3.375" width="0.2032" layer="21"/>
+<wire x1="5.675" y1="-3.375" x2="5.675" y2="3.4" width="0.2032" layer="51"/>
+<wire x1="5.675" y1="3.4" x2="-5.675" y2="3.4" width="0.2032" layer="21"/>
+<smd name="1" x="-4.575" y="0.025" dx="3.94" dy="5.84" layer="1"/>
+<smd name="2" x="4.575" y="0" dx="3.94" dy="5.84" layer="1"/>
+<text x="-5.775" y="3.925" size="1.27" layer="25">&gt;NAME</text>
+<text x="-5.775" y="-5.15" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="WSC6927" urn="urn:adsk.eagle:footprint:25697/1" library_version="1">
+<description>&lt;b&gt;Wirewound Resistors, Precision Power&lt;/b&gt;&lt;p&gt;
+Source: VISHAY wscwsn.pdf</description>
+<wire x1="-8.65" y1="3.375" x2="-8.65" y2="-3.375" width="0.2032" layer="51"/>
+<wire x1="-8.65" y1="-3.375" x2="8.65" y2="-3.375" width="0.2032" layer="21"/>
+<wire x1="8.65" y1="-3.375" x2="8.65" y2="3.375" width="0.2032" layer="51"/>
+<wire x1="8.65" y1="3.375" x2="-8.65" y2="3.375" width="0.2032" layer="21"/>
+<smd name="1" x="-7.95" y="0.025" dx="3.94" dy="5.97" layer="1"/>
+<smd name="2" x="7.95" y="0" dx="3.94" dy="5.97" layer="1"/>
+<text x="-8.75" y="3.9" size="1.27" layer="25">&gt;NAME</text>
+<text x="-8.75" y="-5.15" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="R1218" urn="urn:adsk.eagle:footprint:25698/1" library_version="1">
+<description>&lt;b&gt;CRCW1218 Thick Film, Rectangular Chip Resistors&lt;/b&gt;&lt;p&gt;
+Source: http://www.vishay.com .. dcrcw.pdf</description>
+<wire x1="-0.913" y1="-2.219" x2="0.939" y2="-2.219" width="0.1524" layer="51"/>
+<wire x1="0.913" y1="2.219" x2="-0.939" y2="2.219" width="0.1524" layer="51"/>
+<smd name="1" x="-1.475" y="0" dx="1.05" dy="4.9" layer="1"/>
+<smd name="2" x="1.475" y="0" dx="1.05" dy="4.9" layer="1"/>
+<text x="-2.54" y="2.54" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.81" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-2.3" x2="-0.9009" y2="2.3" layer="51"/>
+<rectangle x1="0.9144" y1="-2.3" x2="1.6645" y2="2.3" layer="51"/>
+</package>
+<package name="1812X7R" urn="urn:adsk.eagle:footprint:25699/1" library_version="1">
+<description>&lt;b&gt;Chip Monolithic Ceramic Capacitors&lt;/b&gt; Medium Voltage High Capacitance for General Use&lt;p&gt;
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf</description>
+<wire x1="-1.1" y1="1.5" x2="1.1" y2="1.5" width="0.2032" layer="51"/>
+<wire x1="1.1" y1="-1.5" x2="-1.1" y2="-1.5" width="0.2032" layer="51"/>
+<wire x1="-0.6" y1="1.5" x2="0.6" y2="1.5" width="0.2032" layer="21"/>
+<wire x1="0.6" y1="-1.5" x2="-0.6" y2="-1.5" width="0.2032" layer="21"/>
+<smd name="1" x="-1.425" y="0" dx="0.8" dy="3.5" layer="1"/>
+<smd name="2" x="1.425" y="0" dx="0.8" dy="3.5" layer="1" rot="R180"/>
+<text x="-1.9456" y="1.9958" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.9456" y="-3.7738" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.4" y1="-1.6" x2="-1.1" y2="1.6" layer="51"/>
+<rectangle x1="1.1" y1="-1.6" x2="1.4" y2="1.6" layer="51" rot="R180"/>
+</package>
+<package name="PRL1632" urn="urn:adsk.eagle:footprint:25700/1" library_version="1">
+<description>&lt;b&gt;PRL1632 are realized as 1W for 3.2 × 1.6mm(1206)&lt;/b&gt;&lt;p&gt;
+Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf</description>
+<wire x1="0.7275" y1="-1.5228" x2="-0.7277" y2="-1.5228" width="0.1524" layer="51"/>
+<wire x1="0.7275" y1="1.5228" x2="-0.7152" y2="1.5228" width="0.1524" layer="51"/>
+<smd name="2" x="0.822" y="0" dx="1" dy="3.2" layer="1"/>
+<smd name="1" x="-0.822" y="0" dx="1" dy="3.2" layer="1"/>
+<text x="-1.4" y="1.8" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.4" y="-3" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.8" y1="-1.6" x2="-0.4" y2="1.6" layer="51"/>
+<rectangle x1="0.4" y1="-1.6" x2="0.8" y2="1.6" layer="51"/>
+</package>
+<package name="R01005" urn="urn:adsk.eagle:footprint:25701/1" library_version="1">
+<smd name="1" x="-0.1625" y="0" dx="0.2" dy="0.25" layer="1"/>
+<smd name="2" x="0.1625" y="0" dx="0.2" dy="0.25" layer="1"/>
+<text x="-0.4" y="0.3" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.4" y="-1.6" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.2" y1="-0.1" x2="-0.075" y2="0.1" layer="51"/>
+<rectangle x1="0.075" y1="-0.1" x2="0.2" y2="0.1" layer="51"/>
+<rectangle x1="-0.15" y1="0.05" x2="0.15" y2="0.1" layer="51"/>
+<rectangle x1="-0.15" y1="-0.1" x2="0.15" y2="-0.05" layer="51"/>
+</package>
+<package name="C0402" urn="urn:adsk.eagle:footprint:25704/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-0.245" y1="0.224" x2="0.245" y2="0.224" width="0.1524" layer="51"/>
+<wire x1="0.245" y1="-0.224" x2="-0.245" y2="-0.224" width="0.1524" layer="51"/>
+<wire x1="-1.473" y1="0.483" x2="1.473" y2="0.483" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.483" x2="1.473" y2="-0.483" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.483" x2="-1.473" y2="-0.483" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.483" x2="-1.473" y2="0.483" width="0.0508" layer="39"/>
+<smd name="1" x="-0.65" y="0" dx="0.7" dy="0.9" layer="1"/>
+<smd name="2" x="0.65" y="0" dx="0.7" dy="0.9" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.554" y1="-0.3048" x2="-0.254" y2="0.2951" layer="51"/>
+<rectangle x1="0.2588" y1="-0.3048" x2="0.5588" y2="0.2951" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/>
+</package>
+<package name="C0504" urn="urn:adsk.eagle:footprint:25705/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-1.473" y1="0.983" x2="1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.983" x2="1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.983" x2="-1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.983" x2="-1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="-0.294" y1="0.559" x2="0.294" y2="0.559" width="0.1016" layer="51"/>
+<wire x1="-0.294" y1="-0.559" x2="0.294" y2="-0.559" width="0.1016" layer="51"/>
+<smd name="1" x="-0.7" y="0" dx="1" dy="1.3" layer="1"/>
+<smd name="2" x="0.7" y="0" dx="1" dy="1.3" layer="1"/>
+<text x="-0.635" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.6604" y1="-0.6223" x2="-0.2804" y2="0.6276" layer="51"/>
+<rectangle x1="0.2794" y1="-0.6223" x2="0.6594" y2="0.6276" layer="51"/>
+<rectangle x1="-0.1001" y1="-0.4001" x2="0.1001" y2="0.4001" layer="35"/>
+</package>
+<package name="C0603" urn="urn:adsk.eagle:footprint:25706/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-1.473" y1="0.983" x2="1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.983" x2="1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.983" x2="-1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.983" x2="-1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="-0.356" y1="0.432" x2="0.356" y2="0.432" width="0.1016" layer="51"/>
+<wire x1="-0.356" y1="-0.419" x2="0.356" y2="-0.419" width="0.1016" layer="51"/>
+<smd name="1" x="-0.85" y="0" dx="1.1" dy="1" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1.1" dy="1" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.8382" y1="-0.4699" x2="-0.3381" y2="0.4801" layer="51"/>
+<rectangle x1="0.3302" y1="-0.4699" x2="0.8303" y2="0.4801" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/>
+</package>
+<package name="C0805" urn="urn:adsk.eagle:footprint:25707/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;</description>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="-0.381" y1="0.66" x2="0.381" y2="0.66" width="0.1016" layer="51"/>
+<wire x1="-0.356" y1="-0.66" x2="0.381" y2="-0.66" width="0.1016" layer="51"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.0922" y1="-0.7239" x2="-0.3421" y2="0.7262" layer="51"/>
+<rectangle x1="0.3556" y1="-0.7239" x2="1.1057" y2="0.7262" layer="51"/>
+<rectangle x1="-0.1001" y1="-0.4001" x2="0.1001" y2="0.4001" layer="35"/>
+</package>
+<package name="C1206" urn="urn:adsk.eagle:footprint:25708/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-0.965" y1="0.787" x2="0.965" y2="0.787" width="0.1016" layer="51"/>
+<wire x1="-0.965" y1="-0.787" x2="0.965" y2="-0.787" width="0.1016" layer="51"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="1.8" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="1.8" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.7018" y1="-0.8509" x2="-0.9517" y2="0.8491" layer="51"/>
+<rectangle x1="0.9517" y1="-0.8491" x2="1.7018" y2="0.8509" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/>
+</package>
+<package name="C1210" urn="urn:adsk.eagle:footprint:25709/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="-0.9652" y1="1.2446" x2="0.9652" y2="1.2446" width="0.1016" layer="51"/>
+<wire x1="-0.9652" y1="-1.2446" x2="0.9652" y2="-1.2446" width="0.1016" layer="51"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.7018" y1="-1.2954" x2="-0.9517" y2="1.3045" layer="51"/>
+<rectangle x1="0.9517" y1="-1.3045" x2="1.7018" y2="1.2954" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/>
+</package>
+<package name="C1310" urn="urn:adsk.eagle:footprint:25710/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-1.473" y1="0.983" x2="1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.983" x2="1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.983" x2="-1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.983" x2="-1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="-0.294" y1="0.559" x2="0.294" y2="0.559" width="0.1016" layer="51"/>
+<wire x1="-0.294" y1="-0.559" x2="0.294" y2="-0.559" width="0.1016" layer="51"/>
+<smd name="1" x="-0.7" y="0" dx="1" dy="1.3" layer="1"/>
+<smd name="2" x="0.7" y="0" dx="1" dy="1.3" layer="1"/>
+<text x="-0.635" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.6604" y1="-0.6223" x2="-0.2804" y2="0.6276" layer="51"/>
+<rectangle x1="0.2794" y1="-0.6223" x2="0.6594" y2="0.6276" layer="51"/>
+<rectangle x1="-0.1001" y1="-0.3" x2="0.1001" y2="0.3" layer="35"/>
+</package>
+<package name="C1608" urn="urn:adsk.eagle:footprint:25711/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-1.473" y1="0.983" x2="1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.983" x2="1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.983" x2="-1.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.983" x2="-1.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="-0.356" y1="0.432" x2="0.356" y2="0.432" width="0.1016" layer="51"/>
+<wire x1="-0.356" y1="-0.419" x2="0.356" y2="-0.419" width="0.1016" layer="51"/>
+<smd name="1" x="-0.85" y="0" dx="1.1" dy="1" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1.1" dy="1" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.8382" y1="-0.4699" x2="-0.3381" y2="0.4801" layer="51"/>
+<rectangle x1="0.3302" y1="-0.4699" x2="0.8303" y2="0.4801" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/>
+</package>
+<package name="C1812" urn="urn:adsk.eagle:footprint:25712/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.973" y1="1.983" x2="2.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-1.983" x2="-2.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-1.983" x2="-2.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="-1.4732" y1="1.6002" x2="1.4732" y2="1.6002" width="0.1016" layer="51"/>
+<wire x1="-1.4478" y1="-1.6002" x2="1.4732" y2="-1.6002" width="0.1016" layer="51"/>
+<wire x1="2.973" y1="1.983" x2="2.973" y2="-1.983" width="0.0508" layer="39"/>
+<smd name="1" x="-1.95" y="0" dx="1.9" dy="3.4" layer="1"/>
+<smd name="2" x="1.95" y="0" dx="1.9" dy="3.4" layer="1"/>
+<text x="-1.905" y="2.54" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.81" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.3876" y1="-1.651" x2="-1.4376" y2="1.649" layer="51"/>
+<rectangle x1="1.4478" y1="-1.651" x2="2.3978" y2="1.649" layer="51"/>
+<rectangle x1="-0.3" y1="-0.4001" x2="0.3" y2="0.4001" layer="35"/>
+</package>
+<package name="C1825" urn="urn:adsk.eagle:footprint:25713/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.973" y1="3.483" x2="2.973" y2="3.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-3.483" x2="-2.973" y2="-3.483" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-3.483" x2="-2.973" y2="3.483" width="0.0508" layer="39"/>
+<wire x1="-1.4986" y1="3.2766" x2="1.4732" y2="3.2766" width="0.1016" layer="51"/>
+<wire x1="-1.4732" y1="-3.2766" x2="1.4986" y2="-3.2766" width="0.1016" layer="51"/>
+<wire x1="2.973" y1="3.483" x2="2.973" y2="-3.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.95" y="0" dx="1.9" dy="6.8" layer="1"/>
+<smd name="2" x="1.95" y="0" dx="1.9" dy="6.8" layer="1"/>
+<text x="-1.905" y="3.81" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-5.08" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.413" y1="-3.3528" x2="-1.463" y2="3.3472" layer="51"/>
+<rectangle x1="1.4478" y1="-3.3528" x2="2.3978" y2="3.3472" layer="51"/>
+<rectangle x1="-0.7" y1="-0.7" x2="0.7" y2="0.7" layer="35"/>
+</package>
+<package name="C2012" urn="urn:adsk.eagle:footprint:25714/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="-0.381" y1="0.66" x2="0.381" y2="0.66" width="0.1016" layer="51"/>
+<wire x1="-0.356" y1="-0.66" x2="0.381" y2="-0.66" width="0.1016" layer="51"/>
+<smd name="1" x="-0.85" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.0922" y1="-0.7239" x2="-0.3421" y2="0.7262" layer="51"/>
+<rectangle x1="0.3556" y1="-0.7239" x2="1.1057" y2="0.7262" layer="51"/>
+<rectangle x1="-0.1001" y1="-0.4001" x2="0.1001" y2="0.4001" layer="35"/>
+</package>
+<package name="C3216" urn="urn:adsk.eagle:footprint:25715/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/>
+<wire x1="-0.965" y1="0.787" x2="0.965" y2="0.787" width="0.1016" layer="51"/>
+<wire x1="-0.965" y1="-0.787" x2="0.965" y2="-0.787" width="0.1016" layer="51"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="1.8" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="1.8" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.7018" y1="-0.8509" x2="-0.9517" y2="0.8491" layer="51"/>
+<rectangle x1="0.9517" y1="-0.8491" x2="1.7018" y2="0.8509" layer="51"/>
+<rectangle x1="-0.3" y1="-0.5001" x2="0.3" y2="0.5001" layer="35"/>
+</package>
+<package name="C3225" urn="urn:adsk.eagle:footprint:25716/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="-0.9652" y1="1.2446" x2="0.9652" y2="1.2446" width="0.1016" layer="51"/>
+<wire x1="-0.9652" y1="-1.2446" x2="0.9652" y2="-1.2446" width="0.1016" layer="51"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2.7" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.7018" y1="-1.2954" x2="-0.9517" y2="1.3045" layer="51"/>
+<rectangle x1="0.9517" y1="-1.3045" x2="1.7018" y2="1.2954" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.5001" x2="0.1999" y2="0.5001" layer="35"/>
+</package>
+<package name="C4532" urn="urn:adsk.eagle:footprint:25717/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.973" y1="1.983" x2="2.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-1.983" x2="-2.973" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-1.983" x2="-2.973" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="-1.4732" y1="1.6002" x2="1.4732" y2="1.6002" width="0.1016" layer="51"/>
+<wire x1="-1.4478" y1="-1.6002" x2="1.4732" y2="-1.6002" width="0.1016" layer="51"/>
+<wire x1="2.973" y1="1.983" x2="2.973" y2="-1.983" width="0.0508" layer="39"/>
+<smd name="1" x="-1.95" y="0" dx="1.9" dy="3.4" layer="1"/>
+<smd name="2" x="1.95" y="0" dx="1.9" dy="3.4" layer="1"/>
+<text x="-1.905" y="2.54" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.81" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.3876" y1="-1.651" x2="-1.4376" y2="1.649" layer="51"/>
+<rectangle x1="1.4478" y1="-1.651" x2="2.3978" y2="1.649" layer="51"/>
+<rectangle x1="-0.4001" y1="-0.7" x2="0.4001" y2="0.7" layer="35"/>
+</package>
+<package name="C4564" urn="urn:adsk.eagle:footprint:25718/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.973" y1="3.483" x2="2.973" y2="3.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-3.483" x2="-2.973" y2="-3.483" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-3.483" x2="-2.973" y2="3.483" width="0.0508" layer="39"/>
+<wire x1="-1.4986" y1="3.2766" x2="1.4732" y2="3.2766" width="0.1016" layer="51"/>
+<wire x1="-1.4732" y1="-3.2766" x2="1.4986" y2="-3.2766" width="0.1016" layer="51"/>
+<wire x1="2.973" y1="3.483" x2="2.973" y2="-3.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.95" y="0" dx="1.9" dy="6.8" layer="1"/>
+<smd name="2" x="1.95" y="0" dx="1.9" dy="6.8" layer="1"/>
+<text x="-1.905" y="3.81" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-5.08" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.413" y1="-3.3528" x2="-1.463" y2="3.3472" layer="51"/>
+<rectangle x1="1.4478" y1="-3.3528" x2="2.3978" y2="3.3472" layer="51"/>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+</package>
+<package name="C025-024X044" urn="urn:adsk.eagle:footprint:25719/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 2.4 x 4.4 mm</description>
+<wire x1="-2.159" y1="-0.635" x2="-2.159" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.635" x2="-1.651" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.159" y1="-0.635" x2="-1.651" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="1.651" y1="1.143" x2="-1.651" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.159" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.651" y1="-1.143" x2="-1.651" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="1.651" y1="1.143" x2="2.159" y2="0.635" width="0.1524" layer="21" curve="-90"/>
+<wire x1="1.651" y1="-1.143" x2="2.159" y2="-0.635" width="0.1524" layer="21" curve="90"/>
+<wire x1="-0.3048" y1="0.762" x2="-0.3048" y2="-0.762" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0.762" x2="0.3302" y2="-0.762" width="0.3048" layer="21"/>
+<wire x1="1.27" y1="0" x2="0.3302" y2="0" width="0.1524" layer="51"/>
+<wire x1="-1.27" y1="0" x2="-0.3048" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-1.778" y="1.397" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.778" y="-2.667" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025-025X050" urn="urn:adsk.eagle:footprint:25720/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 2.5 x 5 mm</description>
+<wire x1="-2.159" y1="1.27" x2="2.159" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.27" x2="-2.159" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.016" x2="-2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="1.27" x2="2.413" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="1.016" x2="-2.159" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-1.27" x2="2.413" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-1.016" x2="-2.159" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.762" y1="0" x2="0.381" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="1.524" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025-030X050" urn="urn:adsk.eagle:footprint:25721/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 3 x 5 mm</description>
+<wire x1="-2.159" y1="1.524" x2="2.159" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.524" x2="-2.159" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.27" x2="2.413" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.27" x2="-2.413" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="1.524" x2="2.413" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="1.27" x2="-2.159" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-1.524" x2="2.413" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-1.27" x2="-2.159" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.762" y1="0" x2="0.381" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-3.048" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025-040X050" urn="urn:adsk.eagle:footprint:25722/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 4 x 5 mm</description>
+<wire x1="-2.159" y1="1.905" x2="2.159" y2="1.905" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.905" x2="-2.159" y2="-1.905" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.651" x2="2.413" y2="-1.651" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.651" x2="-2.413" y2="-1.651" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="1.905" x2="2.413" y2="1.651" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="1.651" x2="-2.159" y2="1.905" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-1.905" x2="2.413" y2="-1.651" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-1.651" x2="-2.159" y2="-1.905" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.762" y1="0" x2="0.381" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="2.159" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-3.429" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025-050X050" urn="urn:adsk.eagle:footprint:25723/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 5 x 5 mm</description>
+<wire x1="-2.159" y1="2.286" x2="2.159" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-2.286" x2="-2.159" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="2.032" x2="2.413" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="2.032" x2="-2.413" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="2.286" x2="2.413" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="2.032" x2="-2.159" y2="2.286" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-2.286" x2="2.413" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-2.032" x2="-2.159" y2="-2.286" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.762" y1="0" x2="0.381" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="2.54" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-3.81" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025-060X050" urn="urn:adsk.eagle:footprint:25724/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 6 x 5 mm</description>
+<wire x1="-2.159" y1="2.794" x2="2.159" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-2.794" x2="-2.159" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="2.54" x2="2.413" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="2.54" x2="-2.413" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="2.794" x2="2.413" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="2.54" x2="-2.159" y2="2.794" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-2.794" x2="2.413" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-2.54" x2="-2.159" y2="-2.794" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.762" y1="0" x2="0.381" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="3.048" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.032" y="-2.413" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025_050-024X070" urn="urn:adsk.eagle:footprint:25725/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm</description>
+<wire x1="-2.159" y1="-0.635" x2="-2.159" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="-2.159" y1="0.635" x2="-1.651" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.159" y1="-0.635" x2="-1.651" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="1.651" y1="1.143" x2="-1.651" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.159" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="1.651" y1="-1.143" x2="-1.651" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="1.651" y1="1.143" x2="2.159" y2="0.635" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-4.191" y1="-1.143" x2="-3.9624" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="-4.191" y1="1.143" x2="-3.9624" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="-0.635" x2="-4.191" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="1.651" y1="-1.143" x2="2.159" y2="-0.635" width="0.1524" layer="21" curve="90"/>
+<wire x1="-4.699" y1="0.635" x2="-4.191" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-4.699" y1="-0.635" x2="-4.699" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="1.143" x2="-2.5654" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-1.143" x2="-2.5654" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="-0.3048" y1="0.762" x2="-0.3048" y2="-0.762" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0.762" x2="0.3302" y2="-0.762" width="0.3048" layer="21"/>
+<wire x1="1.27" y1="0" x2="0.3302" y2="0" width="0.1524" layer="51"/>
+<wire x1="-1.27" y1="0" x2="-0.3048" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="3" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.81" y="1.397" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.81" y="-2.667" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025_050-025X075" urn="urn:adsk.eagle:footprint:25726/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm</description>
+<wire x1="-2.159" y1="1.27" x2="2.159" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.27" x2="-2.159" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.016" x2="-2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="1.27" x2="2.413" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="1.016" x2="-2.159" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-1.27" x2="2.413" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-1.016" x2="-2.159" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<wire x1="4.953" y1="1.016" x2="4.953" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="1.27" x2="4.953" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="-1.27" x2="4.953" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.794" y1="1.27" x2="4.699" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-1.27" x2="2.794" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="2.413" y2="0.762" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-0.762" x2="2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="0.254" x2="2.413" y2="-0.254" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="0" x2="2.286" y2="0" width="0.1524" layer="51"/>
+<wire x1="2.286" y1="0" x2="2.794" y2="0" width="0.1524" layer="21"/>
+<wire x1="2.794" y1="0" x2="3.302" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.762" y1="0" x2="0.381" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="3" x="3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.159" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.159" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025_050-035X075" urn="urn:adsk.eagle:footprint:25727/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm</description>
+<wire x1="-2.159" y1="1.778" x2="2.159" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.778" x2="-2.159" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.524" x2="-2.413" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="1.778" x2="2.413" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="1.524" x2="-2.159" y2="1.778" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-1.778" x2="2.413" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-1.524" x2="-2.159" y2="-1.778" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<wire x1="4.953" y1="1.524" x2="4.953" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="1.778" x2="4.953" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="-1.778" x2="4.953" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.794" y1="1.778" x2="4.699" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-1.778" x2="2.794" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.524" x2="2.413" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.016" x2="2.413" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="0.508" x2="2.413" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="0.381" y1="0" x2="0.762" y2="0" width="0.1524" layer="51"/>
+<wire x1="2.286" y1="0" x2="2.794" y2="0" width="0.1524" layer="21"/>
+<wire x1="2.794" y1="0" x2="3.302" y2="0" width="0.1524" layer="51"/>
+<wire x1="2.286" y1="0" x2="1.778" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="3" x="3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="2.159" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-3.302" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025_050-045X075" urn="urn:adsk.eagle:footprint:25728/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm</description>
+<wire x1="-2.159" y1="2.286" x2="2.159" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-2.286" x2="-2.159" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="2.032" x2="-2.413" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="2.286" x2="2.413" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="2.032" x2="-2.159" y2="2.286" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-2.286" x2="2.413" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-2.032" x2="-2.159" y2="-2.286" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<wire x1="4.953" y1="2.032" x2="4.953" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="2.286" x2="4.953" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="-2.286" x2="4.953" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.794" y1="2.286" x2="4.699" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-2.286" x2="2.794" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="2.032" x2="2.413" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-1.397" x2="2.413" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="0.762" x2="2.413" y2="-0.762" width="0.1524" layer="21"/>
+<wire x1="2.286" y1="0" x2="2.794" y2="0" width="0.1524" layer="21"/>
+<wire x1="2.794" y1="0" x2="3.302" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.762" y2="0" width="0.1524" layer="51"/>
+<wire x1="2.286" y1="0" x2="1.778" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="3" x="3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="2.667" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-3.81" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C025_050-055X075" urn="urn:adsk.eagle:footprint:25729/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm</description>
+<wire x1="-2.159" y1="2.794" x2="2.159" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-2.794" x2="-2.159" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="2.54" x2="-2.413" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="2.794" x2="2.413" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="2.54" x2="-2.159" y2="2.794" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-2.794" x2="2.413" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-2.54" x2="-2.159" y2="-2.794" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<wire x1="4.953" y1="2.54" x2="4.953" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="2.794" x2="4.953" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="-2.794" x2="4.953" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.794" y1="2.794" x2="4.699" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-2.794" x2="2.794" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="2.54" x2="2.413" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-2.032" x2="2.413" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="0.762" x2="2.413" y2="-0.762" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="0" x2="2.286" y2="0" width="0.1524" layer="51"/>
+<wire x1="2.286" y1="0" x2="2.794" y2="0" width="0.1524" layer="21"/>
+<wire x1="2.794" y1="0" x2="3.302" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.762" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="3" x="3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="3.175" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.032" y="-2.286" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050-024X044" urn="urn:adsk.eagle:footprint:25730/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 2.4 x 4.4 mm</description>
+<wire x1="-2.159" y1="-0.635" x2="-2.159" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="-2.159" y1="0.635" x2="-1.651" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.159" y1="-0.635" x2="-1.651" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="1.651" y1="1.143" x2="-1.651" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.159" y2="0.635" width="0.1524" layer="51"/>
+<wire x1="1.651" y1="-1.143" x2="-1.651" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="1.651" y1="1.143" x2="2.159" y2="0.635" width="0.1524" layer="21" curve="-90"/>
+<wire x1="1.651" y1="-1.143" x2="2.159" y2="-0.635" width="0.1524" layer="21" curve="90"/>
+<wire x1="-0.3048" y1="0.762" x2="-0.3048" y2="0" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-0.3048" y2="-0.762" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0.762" x2="0.3302" y2="0" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="0.3302" y2="-0.762" width="0.3048" layer="21"/>
+<wire x1="1.27" y1="0" x2="0.3302" y2="0" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0" x2="-0.3048" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.159" y="1.397" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.159" y="-2.667" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="2.159" y1="-0.381" x2="2.54" y2="0.381" layer="51"/>
+<rectangle x1="-2.54" y1="-0.381" x2="-2.159" y2="0.381" layer="51"/>
+</package>
+<package name="C050-025X075" urn="urn:adsk.eagle:footprint:25731/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 2.5 x 7.5 mm</description>
+<wire x1="-0.3048" y1="0.635" x2="-0.3048" y2="0" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-0.3048" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.3302" y1="0.635" x2="0.3302" y2="0" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="0.3302" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="1.016" x2="-3.683" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-1.27" x2="3.429" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="-1.016" x2="3.683" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="1.27" x2="-3.429" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="1.27" x2="3.683" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.429" y1="-1.27" x2="3.683" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="-1.016" x2="-3.429" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="1.016" x2="-3.429" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.429" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.429" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050-045X075" urn="urn:adsk.eagle:footprint:25732/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 4.5 x 7.5 mm</description>
+<wire x1="-0.3048" y1="0.635" x2="-0.3048" y2="0" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-0.3048" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.3302" y1="0.635" x2="0.3302" y2="0" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="0.3302" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="2.032" x2="-3.683" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-2.286" x2="3.429" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="-2.032" x2="3.683" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="2.286" x2="-3.429" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="2.286" x2="3.683" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.429" y1="-2.286" x2="3.683" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="-2.032" x2="-3.429" y2="-2.286" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="2.032" x2="-3.429" y2="2.286" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.556" y="2.667" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.556" y="-3.81" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050-030X075" urn="urn:adsk.eagle:footprint:25733/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 3 x 7.5 mm</description>
+<wire x1="-0.3048" y1="0.635" x2="-0.3048" y2="0" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-0.3048" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.3302" y1="0.635" x2="0.3302" y2="0" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="0.3302" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="1.27" x2="-3.683" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-1.524" x2="3.429" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="-1.27" x2="3.683" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="1.524" x2="-3.429" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="1.524" x2="3.683" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.429" y1="-1.524" x2="3.683" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="-1.27" x2="-3.429" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="1.27" x2="-3.429" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.556" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.556" y="-3.048" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050-050X075" urn="urn:adsk.eagle:footprint:25734/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 5 x 7.5 mm</description>
+<wire x1="-0.3048" y1="0.635" x2="-0.3048" y2="0" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-0.3048" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.3302" y1="0.635" x2="0.3302" y2="0" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="0.3302" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="2.286" x2="-3.683" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-2.54" x2="3.429" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="-2.286" x2="3.683" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="2.54" x2="-3.429" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="2.54" x2="3.683" y2="2.286" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.429" y1="-2.54" x2="3.683" y2="-2.286" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="-2.286" x2="-3.429" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="2.286" x2="-3.429" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.429" y="2.921" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-2.159" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050-055X075" urn="urn:adsk.eagle:footprint:25735/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 5.5 x 7.5 mm</description>
+<wire x1="-0.3048" y1="0.635" x2="-0.3048" y2="0" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-0.3048" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.3302" y1="0.635" x2="0.3302" y2="0" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="0.3302" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="2.54" x2="-3.683" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-2.794" x2="3.429" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="-2.54" x2="3.683" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="2.794" x2="-3.429" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="2.794" x2="3.683" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.429" y1="-2.794" x2="3.683" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="-2.54" x2="-3.429" y2="-2.794" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="2.54" x2="-3.429" y2="2.794" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.429" y="3.175" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.302" y="-2.286" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050-075X075" urn="urn:adsk.eagle:footprint:25736/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 7.5 x 7.5 mm</description>
+<wire x1="-1.524" y1="0" x2="-0.4572" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.4572" y1="0" x2="-0.4572" y2="0.762" width="0.4064" layer="21"/>
+<wire x1="-0.4572" y1="0" x2="-0.4572" y2="-0.762" width="0.4064" layer="21"/>
+<wire x1="0.4318" y1="0.762" x2="0.4318" y2="0" width="0.4064" layer="21"/>
+<wire x1="0.4318" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.4318" y1="0" x2="0.4318" y2="-0.762" width="0.4064" layer="21"/>
+<wire x1="-3.683" y1="3.429" x2="-3.683" y2="-3.429" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-3.683" x2="3.429" y2="-3.683" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="-3.429" x2="3.683" y2="3.429" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="3.683" x2="-3.429" y2="3.683" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="3.683" x2="3.683" y2="3.429" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.429" y1="-3.683" x2="3.683" y2="-3.429" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="-3.429" x2="-3.429" y2="-3.683" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="3.429" x2="-3.429" y2="3.683" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.429" y="4.064" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-2.921" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050H075X075" urn="urn:adsk.eagle:footprint:25737/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm</description>
+<wire x1="-3.683" y1="7.112" x2="-3.683" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="0.508" x2="-3.302" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-3.302" y1="0.508" x2="-1.778" y2="0.508" width="0.1524" layer="51"/>
+<wire x1="-1.778" y1="0.508" x2="1.778" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="1.778" y1="0.508" x2="3.302" y2="0.508" width="0.1524" layer="51"/>
+<wire x1="3.302" y1="0.508" x2="3.683" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="0.508" x2="3.683" y2="7.112" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="7.62" x2="-3.175" y2="7.62" width="0.1524" layer="21"/>
+<wire x1="-0.3048" y1="2.413" x2="-0.3048" y2="1.778" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="1.778" x2="-0.3048" y2="1.143" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="1.778" x2="-1.651" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="0.3302" y1="2.413" x2="0.3302" y2="1.778" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="1.778" x2="0.3302" y2="1.143" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="1.778" x2="1.651" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="7.112" x2="-3.175" y2="7.62" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.175" y1="7.62" x2="3.683" y2="7.112" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.54" y1="0" x2="-2.54" y2="0.254" width="0.508" layer="51"/>
+<wire x1="2.54" y1="0" x2="2.54" y2="0.254" width="0.508" layer="51"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.302" y="8.001" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="3.175" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.794" y1="0.127" x2="-2.286" y2="0.508" layer="51"/>
+<rectangle x1="2.286" y1="0.127" x2="2.794" y2="0.508" layer="51"/>
+</package>
+<package name="C075-032X103" urn="urn:adsk.eagle:footprint:25738/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 7.5 mm, outline 3.2 x 10.3 mm</description>
+<wire x1="4.826" y1="1.524" x2="-4.826" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="1.27" x2="-5.08" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-1.524" x2="4.826" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-1.27" x2="5.08" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="1.524" x2="5.08" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.826" y1="-1.524" x2="5.08" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="-1.27" x2="-4.826" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.27" x2="-4.826" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="0.508" y1="0" x2="2.54" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.889" x2="-0.508" y2="0" width="0.4064" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.889" width="0.4064" layer="21"/>
+<wire x1="0.508" y1="0.889" x2="0.508" y2="0" width="0.4064" layer="21"/>
+<wire x1="0.508" y1="0" x2="0.508" y2="-0.889" width="0.4064" layer="21"/>
+<pad name="1" x="-3.81" y="0" drill="0.9144" shape="octagon"/>
+<pad name="2" x="3.81" y="0" drill="0.9144" shape="octagon"/>
+<text x="-4.826" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.826" y="-3.048" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C075-042X103" urn="urn:adsk.eagle:footprint:25739/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 7.5 mm, outline 4.2 x 10.3 mm</description>
+<wire x1="4.826" y1="2.032" x2="-4.826" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="1.778" x2="-5.08" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-2.032" x2="4.826" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-1.778" x2="5.08" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="2.032" x2="5.08" y2="1.778" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.826" y1="-2.032" x2="5.08" y2="-1.778" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="-1.778" x2="-4.826" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.778" x2="-4.826" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-1.27" y1="0" x2="2.667" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.667" y1="0" x2="-2.159" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="1.27" x2="-2.159" y2="0" width="0.4064" layer="21"/>
+<wire x1="-2.159" y1="0" x2="-2.159" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-1.27" y1="1.27" x2="-1.27" y2="0" width="0.4064" layer="21"/>
+<wire x1="-1.27" y1="0" x2="-1.27" y2="-1.27" width="0.4064" layer="21"/>
+<pad name="1" x="-3.81" y="0" drill="0.9144" shape="octagon"/>
+<pad name="2" x="3.81" y="0" drill="0.9144" shape="octagon"/>
+<text x="-4.699" y="2.413" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.635" y="-1.651" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C075-052X106" urn="urn:adsk.eagle:footprint:25740/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 7.5 mm, outline 5.2 x 10.6 mm</description>
+<wire x1="4.953" y1="2.54" x2="-4.953" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="2.286" x2="-5.207" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="-2.54" x2="4.953" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-2.286" x2="5.207" y2="2.286" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="2.54" x2="5.207" y2="2.286" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.953" y1="-2.54" x2="5.207" y2="-2.286" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.207" y1="-2.286" x2="-4.953" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.207" y1="2.286" x2="-4.953" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-1.27" y1="0" x2="2.667" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.667" y1="0" x2="-2.159" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="1.27" x2="-2.159" y2="0" width="0.4064" layer="21"/>
+<wire x1="-2.159" y1="0" x2="-2.159" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-1.27" y1="1.27" x2="-1.27" y2="0" width="0.4064" layer="21"/>
+<wire x1="-1.27" y1="0" x2="-1.27" y2="-1.27" width="0.4064" layer="21"/>
+<pad name="1" x="-3.81" y="0" drill="0.9144" shape="octagon"/>
+<pad name="2" x="3.81" y="0" drill="0.9144" shape="octagon"/>
+<text x="-4.826" y="2.921" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.635" y="-2.032" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C102-043X133" urn="urn:adsk.eagle:footprint:25741/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 10.2 mm, outline 4.3 x 13.3 mm</description>
+<wire x1="-3.175" y1="1.27" x2="-3.175" y2="0" width="0.4064" layer="21"/>
+<wire x1="-2.286" y1="1.27" x2="-2.286" y2="0" width="0.4064" layer="21"/>
+<wire x1="3.81" y1="0" x2="-2.286" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="0" x2="-2.286" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-3.175" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-6.096" y1="2.032" x2="6.096" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="6.604" y1="1.524" x2="6.604" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="-2.032" x2="-6.096" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="-6.604" y1="-1.524" x2="-6.604" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="2.032" x2="6.604" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="6.096" y1="-2.032" x2="6.604" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="-1.524" x2="-6.096" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="1.524" x2="-6.096" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-5.08" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="5.08" y="0" drill="1.016" shape="octagon"/>
+<text x="-6.096" y="2.413" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.524" y="-1.651" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C102-054X133" urn="urn:adsk.eagle:footprint:25742/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 10.2 mm, outline 5.4 x 13.3 mm</description>
+<wire x1="-3.175" y1="1.27" x2="-3.175" y2="0" width="0.4064" layer="21"/>
+<wire x1="-2.286" y1="1.27" x2="-2.286" y2="0" width="0.4064" layer="21"/>
+<wire x1="3.81" y1="0" x2="-2.286" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="0" x2="-2.286" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-3.175" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-6.096" y1="2.54" x2="6.096" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="6.604" y1="2.032" x2="6.604" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="-2.54" x2="-6.096" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-6.604" y1="-2.032" x2="-6.604" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="2.54" x2="6.604" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="6.096" y1="-2.54" x2="6.604" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="-2.032" x2="-6.096" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="2.032" x2="-6.096" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-5.08" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="5.08" y="0" drill="1.016" shape="octagon"/>
+<text x="-6.096" y="2.921" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.524" y="-1.905" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C102-064X133" urn="urn:adsk.eagle:footprint:25743/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 10.2 mm, outline 6.4 x 13.3 mm</description>
+<wire x1="-3.175" y1="1.27" x2="-3.175" y2="0" width="0.4064" layer="21"/>
+<wire x1="-2.286" y1="1.27" x2="-2.286" y2="0" width="0.4064" layer="21"/>
+<wire x1="3.81" y1="0" x2="-2.286" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="0" x2="-2.286" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-3.175" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-6.096" y1="3.048" x2="6.096" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="6.604" y1="2.54" x2="6.604" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="-3.048" x2="-6.096" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-6.604" y1="-2.54" x2="-6.604" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="6.096" y1="3.048" x2="6.604" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="6.096" y1="-3.048" x2="6.604" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="-2.54" x2="-6.096" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="2.54" x2="-6.096" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-5.08" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="5.08" y="0" drill="1.016" shape="octagon"/>
+<text x="-6.096" y="3.429" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.524" y="-2.032" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C102_152-062X184" urn="urn:adsk.eagle:footprint:25744/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm</description>
+<wire x1="-2.286" y1="1.27" x2="-2.286" y2="0" width="0.4064" layer="21"/>
+<wire x1="-2.286" y1="0" x2="-2.286" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-3.175" y1="1.27" x2="-3.175" y2="0" width="0.4064" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-3.175" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-3.683" y1="0" x2="-3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="0" x2="3.683" y2="0" width="0.1524" layer="21"/>
+<wire x1="6.477" y1="0" x2="8.636" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.096" y1="3.048" x2="6.223" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="6.223" y1="-3.048" x2="-6.096" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-6.604" y1="-2.54" x2="-6.604" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="6.223" y1="3.048" x2="6.731" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="6.223" y1="-3.048" x2="6.731" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="-2.54" x2="-6.096" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="-6.604" y1="2.54" x2="-6.096" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="6.731" y1="2.54" x2="6.731" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="11.176" y1="3.048" x2="11.684" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="11.176" y1="-3.048" x2="11.684" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="11.176" y1="-3.048" x2="7.112" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="7.112" y1="3.048" x2="11.176" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="11.684" y1="2.54" x2="11.684" y2="-2.54" width="0.1524" layer="21"/>
+<pad name="1" x="-5.08" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="5.08" y="0" drill="1.016" shape="octagon"/>
+<pad name="3" x="10.033" y="0" drill="1.016" shape="octagon"/>
+<text x="-5.969" y="3.429" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.524" y="-2.286" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C150-054X183" urn="urn:adsk.eagle:footprint:25745/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 15 mm, outline 5.4 x 18.3 mm</description>
+<wire x1="-5.08" y1="1.27" x2="-5.08" y2="0" width="0.4064" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-5.08" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="1.27" x2="-4.191" y2="0" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="-4.191" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="9.017" y1="2.032" x2="9.017" y2="-2.032" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="-2.54" x2="-8.509" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-9.017" y1="-2.032" x2="-9.017" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="-8.509" y1="2.54" x2="8.509" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="2.54" x2="9.017" y2="2.032" width="0.1524" layer="21" curve="-90"/>
+<wire x1="8.509" y1="-2.54" x2="9.017" y2="-2.032" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="-2.032" x2="-8.509" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="2.032" x2="-8.509" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-7.493" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.493" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.382" y="2.921" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.429" y="-2.032" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C150-064X183" urn="urn:adsk.eagle:footprint:25746/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 15 mm, outline 6.4 x 18.3 mm</description>
+<wire x1="-5.08" y1="1.27" x2="-5.08" y2="0" width="0.4064" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-5.08" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="1.27" x2="-4.191" y2="0" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="-4.191" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="9.017" y1="2.54" x2="9.017" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="-3.048" x2="-8.509" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-9.017" y1="-2.54" x2="-9.017" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="-8.509" y1="3.048" x2="8.509" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="3.048" x2="9.017" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="8.509" y1="-3.048" x2="9.017" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="-2.54" x2="-8.509" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="2.54" x2="-8.509" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-7.493" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.493" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.509" y="3.429" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.429" y="-2.032" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C150-072X183" urn="urn:adsk.eagle:footprint:25747/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 15 mm, outline 7.2 x 18.3 mm</description>
+<wire x1="-5.08" y1="1.27" x2="-5.08" y2="0" width="0.4064" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-5.08" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="1.27" x2="-4.191" y2="0" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="-4.191" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="9.017" y1="3.048" x2="9.017" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="-3.556" x2="-8.509" y2="-3.556" width="0.1524" layer="21"/>
+<wire x1="-9.017" y1="-3.048" x2="-9.017" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-8.509" y1="3.556" x2="8.509" y2="3.556" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="3.556" x2="9.017" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="8.509" y1="-3.556" x2="9.017" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="-3.048" x2="-8.509" y2="-3.556" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="3.048" x2="-8.509" y2="3.556" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-7.493" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.493" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.509" y="3.937" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.429" y="-2.286" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C150-084X183" urn="urn:adsk.eagle:footprint:25748/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 15 mm, outline 8.4 x 18.3 mm</description>
+<wire x1="-5.08" y1="1.27" x2="-5.08" y2="0" width="0.4064" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-5.08" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="1.27" x2="-4.191" y2="0" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="-4.191" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="9.017" y1="3.556" x2="9.017" y2="-3.556" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="-4.064" x2="-8.509" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="-9.017" y1="-3.556" x2="-9.017" y2="3.556" width="0.1524" layer="21"/>
+<wire x1="-8.509" y1="4.064" x2="8.509" y2="4.064" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="4.064" x2="9.017" y2="3.556" width="0.1524" layer="21" curve="-90"/>
+<wire x1="8.509" y1="-4.064" x2="9.017" y2="-3.556" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="-3.556" x2="-8.509" y2="-4.064" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="3.556" x2="-8.509" y2="4.064" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-7.493" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.493" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.509" y="4.445" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.429" y="-2.54" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C150-091X182" urn="urn:adsk.eagle:footprint:25749/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 15 mm, outline 9.1 x 18.2 mm</description>
+<wire x1="-5.08" y1="1.27" x2="-5.08" y2="0" width="0.4064" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-5.08" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="1.27" x2="-4.191" y2="0" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="-4.191" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-4.191" y1="0" x2="6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0" x2="-6.096" y2="0" width="0.1524" layer="21"/>
+<wire x1="9.017" y1="3.937" x2="9.017" y2="-3.937" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="-4.445" x2="-8.509" y2="-4.445" width="0.1524" layer="21"/>
+<wire x1="-9.017" y1="-3.937" x2="-9.017" y2="3.937" width="0.1524" layer="21"/>
+<wire x1="-8.509" y1="4.445" x2="8.509" y2="4.445" width="0.1524" layer="21"/>
+<wire x1="8.509" y1="4.445" x2="9.017" y2="3.937" width="0.1524" layer="21" curve="-90"/>
+<wire x1="8.509" y1="-4.445" x2="9.017" y2="-3.937" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="-3.937" x2="-8.509" y2="-4.445" width="0.1524" layer="21" curve="90"/>
+<wire x1="-9.017" y1="3.937" x2="-8.509" y2="4.445" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-7.493" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="7.493" y="0" drill="1.016" shape="octagon"/>
+<text x="-8.509" y="4.826" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.429" y="-2.54" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C225-062X268" urn="urn:adsk.eagle:footprint:25750/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 22.5 mm, outline 6.2 x 26.8 mm</description>
+<wire x1="-12.827" y1="3.048" x2="12.827" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="13.335" y1="2.54" x2="13.335" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="12.827" y1="-3.048" x2="-12.827" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="-13.335" y1="-2.54" x2="-13.335" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="12.827" y1="3.048" x2="13.335" y2="2.54" width="0.1524" layer="21" curve="-90"/>
+<wire x1="12.827" y1="-3.048" x2="13.335" y2="-2.54" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="-2.54" x2="-12.827" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="2.54" x2="-12.827" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-9.652" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="9.652" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-11.303" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.303" y="0" drill="1.016" shape="octagon"/>
+<text x="-12.7" y="3.429" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C225-074X268" urn="urn:adsk.eagle:footprint:25751/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 22.5 mm, outline 7.4 x 26.8 mm</description>
+<wire x1="-12.827" y1="3.556" x2="12.827" y2="3.556" width="0.1524" layer="21"/>
+<wire x1="13.335" y1="3.048" x2="13.335" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="12.827" y1="-3.556" x2="-12.827" y2="-3.556" width="0.1524" layer="21"/>
+<wire x1="-13.335" y1="-3.048" x2="-13.335" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="12.827" y1="3.556" x2="13.335" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="12.827" y1="-3.556" x2="13.335" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="-3.048" x2="-12.827" y2="-3.556" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="3.048" x2="-12.827" y2="3.556" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-9.652" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="9.652" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-11.303" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.303" y="0" drill="1.016" shape="octagon"/>
+<text x="-12.827" y="3.937" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C225-087X268" urn="urn:adsk.eagle:footprint:25752/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 22.5 mm, outline 8.7 x 26.8 mm</description>
+<wire x1="-12.827" y1="4.318" x2="12.827" y2="4.318" width="0.1524" layer="21"/>
+<wire x1="13.335" y1="3.81" x2="13.335" y2="-3.81" width="0.1524" layer="21"/>
+<wire x1="12.827" y1="-4.318" x2="-12.827" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-13.335" y1="-3.81" x2="-13.335" y2="3.81" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="12.827" y1="4.318" x2="13.335" y2="3.81" width="0.1524" layer="21" curve="-90"/>
+<wire x1="12.827" y1="-4.318" x2="13.335" y2="-3.81" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="-3.81" x2="-12.827" y2="-4.318" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="3.81" x2="-12.827" y2="4.318" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-9.652" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="9.652" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-11.303" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.303" y="0" drill="1.016" shape="octagon"/>
+<text x="-12.827" y="4.699" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C225-108X268" urn="urn:adsk.eagle:footprint:25753/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 22.5 mm, outline 10.8 x 26.8 mm</description>
+<wire x1="-12.827" y1="5.334" x2="12.827" y2="5.334" width="0.1524" layer="21"/>
+<wire x1="13.335" y1="4.826" x2="13.335" y2="-4.826" width="0.1524" layer="21"/>
+<wire x1="12.827" y1="-5.334" x2="-12.827" y2="-5.334" width="0.1524" layer="21"/>
+<wire x1="-13.335" y1="-4.826" x2="-13.335" y2="4.826" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="12.827" y1="5.334" x2="13.335" y2="4.826" width="0.1524" layer="21" curve="-90"/>
+<wire x1="12.827" y1="-5.334" x2="13.335" y2="-4.826" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="-4.826" x2="-12.827" y2="-5.334" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="4.826" x2="-12.827" y2="5.334" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-9.652" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="9.652" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-11.303" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.303" y="0" drill="1.016" shape="octagon"/>
+<text x="-12.954" y="5.715" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C225-113X268" urn="urn:adsk.eagle:footprint:25754/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 22.5 mm, outline 11.3 x 26.8 mm</description>
+<wire x1="-12.827" y1="5.588" x2="12.827" y2="5.588" width="0.1524" layer="21"/>
+<wire x1="13.335" y1="5.08" x2="13.335" y2="-5.08" width="0.1524" layer="21"/>
+<wire x1="12.827" y1="-5.588" x2="-12.827" y2="-5.588" width="0.1524" layer="21"/>
+<wire x1="-13.335" y1="-5.08" x2="-13.335" y2="5.08" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="12.827" y1="5.588" x2="13.335" y2="5.08" width="0.1524" layer="21" curve="-90"/>
+<wire x1="12.827" y1="-5.588" x2="13.335" y2="-5.08" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="-5.08" x2="-12.827" y2="-5.588" width="0.1524" layer="21" curve="90"/>
+<wire x1="-13.335" y1="5.08" x2="-12.827" y2="5.588" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-9.652" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="9.652" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-11.303" y="0" drill="1.016" shape="octagon"/>
+<pad name="2" x="11.303" y="0" drill="1.016" shape="octagon"/>
+<text x="-12.954" y="5.969" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C275-093X316" urn="urn:adsk.eagle:footprint:25755/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 27.5 mm, outline 9.3 x 31.6 mm</description>
+<wire x1="-15.24" y1="4.572" x2="15.24" y2="4.572" width="0.1524" layer="21"/>
+<wire x1="15.748" y1="4.064" x2="15.748" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="-4.572" x2="-15.24" y2="-4.572" width="0.1524" layer="21"/>
+<wire x1="-15.748" y1="-4.064" x2="-15.748" y2="4.064" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="15.24" y1="4.572" x2="15.748" y2="4.064" width="0.1524" layer="21" curve="-90"/>
+<wire x1="15.24" y1="-4.572" x2="15.748" y2="-4.064" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="-4.064" x2="-15.24" y2="-4.572" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="4.064" x2="-15.24" y2="4.572" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-11.557" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="11.557" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-13.716" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="13.716" y="0" drill="1.1938" shape="octagon"/>
+<text x="-15.24" y="4.953" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C275-113X316" urn="urn:adsk.eagle:footprint:25756/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 27.5 mm, outline 11.3 x 31.6 mm</description>
+<wire x1="-15.24" y1="5.588" x2="15.24" y2="5.588" width="0.1524" layer="21"/>
+<wire x1="15.748" y1="5.08" x2="15.748" y2="-5.08" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="-5.588" x2="-15.24" y2="-5.588" width="0.1524" layer="21"/>
+<wire x1="-15.748" y1="-5.08" x2="-15.748" y2="5.08" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="15.24" y1="5.588" x2="15.748" y2="5.08" width="0.1524" layer="21" curve="-90"/>
+<wire x1="15.24" y1="-5.588" x2="15.748" y2="-5.08" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="-5.08" x2="-15.24" y2="-5.588" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="5.08" x2="-15.24" y2="5.588" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-11.557" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="11.557" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-13.716" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="13.716" y="0" drill="1.1938" shape="octagon"/>
+<text x="-15.24" y="5.969" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C275-134X316" urn="urn:adsk.eagle:footprint:25757/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 27.5 mm, outline 13.4 x 31.6 mm</description>
+<wire x1="-15.24" y1="6.604" x2="15.24" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="15.748" y1="6.096" x2="15.748" y2="-6.096" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="-6.604" x2="-15.24" y2="-6.604" width="0.1524" layer="21"/>
+<wire x1="-15.748" y1="-6.096" x2="-15.748" y2="6.096" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="15.24" y1="6.604" x2="15.748" y2="6.096" width="0.1524" layer="21" curve="-90"/>
+<wire x1="15.24" y1="-6.604" x2="15.748" y2="-6.096" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="-6.096" x2="-15.24" y2="-6.604" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="6.096" x2="-15.24" y2="6.604" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-11.557" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="11.557" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-13.716" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="13.716" y="0" drill="1.1938" shape="octagon"/>
+<text x="-15.24" y="6.985" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C275-205X316" urn="urn:adsk.eagle:footprint:25758/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 27.5 mm, outline 20.5 x 31.6 mm</description>
+<wire x1="-15.24" y1="10.16" x2="15.24" y2="10.16" width="0.1524" layer="21"/>
+<wire x1="15.748" y1="9.652" x2="15.748" y2="-9.652" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="-10.16" x2="-15.24" y2="-10.16" width="0.1524" layer="21"/>
+<wire x1="-15.748" y1="-9.652" x2="-15.748" y2="9.652" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="15.24" y1="10.16" x2="15.748" y2="9.652" width="0.1524" layer="21" curve="-90"/>
+<wire x1="15.24" y1="-10.16" x2="15.748" y2="-9.652" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="-9.652" x2="-15.24" y2="-10.16" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="9.652" x2="-15.24" y2="10.16" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-11.557" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="11.557" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-13.716" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="13.716" y="0" drill="1.1938" shape="octagon"/>
+<text x="-15.24" y="10.541" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-4.318" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C325-137X374" urn="urn:adsk.eagle:footprint:25759/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 32.5 mm, outline 13.7 x 37.4 mm</description>
+<wire x1="-14.2748" y1="0" x2="-12.7" y2="0" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="1.905" x2="-12.7" y2="0" width="0.4064" layer="21"/>
+<wire x1="-11.811" y1="1.905" x2="-11.811" y2="0" width="0.4064" layer="21"/>
+<wire x1="-11.811" y1="0" x2="14.2748" y2="0" width="0.1524" layer="21"/>
+<wire x1="-11.811" y1="0" x2="-11.811" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-12.7" y1="0" x2="-12.7" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="18.542" y1="6.731" x2="18.542" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="-18.542" y1="6.731" x2="-18.542" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="-18.542" y1="-6.731" x2="18.542" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="18.542" y1="6.731" x2="-18.542" y2="6.731" width="0.1524" layer="21"/>
+<pad name="1" x="-16.256" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="16.256" y="0" drill="1.1938" shape="octagon"/>
+<text x="-18.2372" y="7.0612" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-10.8458" y="-2.8702" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C325-162X374" urn="urn:adsk.eagle:footprint:25760/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 32.5 mm, outline 16.2 x 37.4 mm</description>
+<wire x1="-14.2748" y1="0" x2="-12.7" y2="0" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="1.905" x2="-12.7" y2="0" width="0.4064" layer="21"/>
+<wire x1="-11.811" y1="1.905" x2="-11.811" y2="0" width="0.4064" layer="21"/>
+<wire x1="-11.811" y1="0" x2="14.2748" y2="0" width="0.1524" layer="21"/>
+<wire x1="-11.811" y1="0" x2="-11.811" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-12.7" y1="0" x2="-12.7" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="18.542" y1="8.001" x2="18.542" y2="-8.001" width="0.1524" layer="21"/>
+<wire x1="-18.542" y1="8.001" x2="-18.542" y2="-8.001" width="0.1524" layer="21"/>
+<wire x1="-18.542" y1="-8.001" x2="18.542" y2="-8.001" width="0.1524" layer="21"/>
+<wire x1="18.542" y1="8.001" x2="-18.542" y2="8.001" width="0.1524" layer="21"/>
+<pad name="1" x="-16.256" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="16.256" y="0" drill="1.1938" shape="octagon"/>
+<text x="-18.3642" y="8.3312" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-10.8458" y="-2.8702" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C325-182X374" urn="urn:adsk.eagle:footprint:25761/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 32.5 mm, outline 18.2 x 37.4 mm</description>
+<wire x1="-14.2748" y1="0" x2="-12.7" y2="0" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="1.905" x2="-12.7" y2="0" width="0.4064" layer="21"/>
+<wire x1="-11.811" y1="1.905" x2="-11.811" y2="0" width="0.4064" layer="21"/>
+<wire x1="-11.811" y1="0" x2="14.2748" y2="0" width="0.1524" layer="21"/>
+<wire x1="-11.811" y1="0" x2="-11.811" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-12.7" y1="0" x2="-12.7" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="18.542" y1="9.017" x2="18.542" y2="-9.017" width="0.1524" layer="21"/>
+<wire x1="-18.542" y1="9.017" x2="-18.542" y2="-9.017" width="0.1524" layer="21"/>
+<wire x1="-18.542" y1="-9.017" x2="18.542" y2="-9.017" width="0.1524" layer="21"/>
+<wire x1="18.542" y1="9.017" x2="-18.542" y2="9.017" width="0.1524" layer="21"/>
+<pad name="1" x="-16.256" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="16.256" y="0" drill="1.1938" shape="octagon"/>
+<text x="-18.3642" y="9.3472" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-10.8458" y="-2.8702" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C375-192X418" urn="urn:adsk.eagle:footprint:25762/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 37.5 mm, outline 19.2 x 41.8 mm</description>
+<wire x1="-20.32" y1="8.509" x2="20.32" y2="8.509" width="0.1524" layer="21"/>
+<wire x1="20.828" y1="8.001" x2="20.828" y2="-8.001" width="0.1524" layer="21"/>
+<wire x1="20.32" y1="-8.509" x2="-20.32" y2="-8.509" width="0.1524" layer="21"/>
+<wire x1="-20.828" y1="-8.001" x2="-20.828" y2="8.001" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="20.32" y1="8.509" x2="20.828" y2="8.001" width="0.1524" layer="21" curve="-90"/>
+<wire x1="20.32" y1="-8.509" x2="20.828" y2="-8.001" width="0.1524" layer="21" curve="90"/>
+<wire x1="-20.828" y1="-8.001" x2="-20.32" y2="-8.509" width="0.1524" layer="21" curve="90"/>
+<wire x1="-20.828" y1="8.001" x2="-20.32" y2="8.509" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-16.002" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="16.002" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-18.796" y="0" drill="1.3208" shape="octagon"/>
+<pad name="2" x="18.796" y="0" drill="1.3208" shape="octagon"/>
+<text x="-20.447" y="8.89" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C375-203X418" urn="urn:adsk.eagle:footprint:25763/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 37.5 mm, outline 20.3 x 41.8 mm</description>
+<wire x1="-20.32" y1="10.16" x2="20.32" y2="10.16" width="0.1524" layer="21"/>
+<wire x1="20.828" y1="9.652" x2="20.828" y2="-9.652" width="0.1524" layer="21"/>
+<wire x1="20.32" y1="-10.16" x2="-20.32" y2="-10.16" width="0.1524" layer="21"/>
+<wire x1="-20.828" y1="-9.652" x2="-20.828" y2="9.652" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="20.32" y1="10.16" x2="20.828" y2="9.652" width="0.1524" layer="21" curve="-90"/>
+<wire x1="20.32" y1="-10.16" x2="20.828" y2="-9.652" width="0.1524" layer="21" curve="90"/>
+<wire x1="-20.828" y1="-9.652" x2="-20.32" y2="-10.16" width="0.1524" layer="21" curve="90"/>
+<wire x1="-20.828" y1="9.652" x2="-20.32" y2="10.16" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-16.002" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="16.002" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-18.796" y="0" drill="1.3208" shape="octagon"/>
+<pad name="2" x="18.796" y="0" drill="1.3208" shape="octagon"/>
+<text x="-20.32" y="10.541" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C050-035X075" urn="urn:adsk.eagle:footprint:25764/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 5 mm, outline 3.5 x 7.5 mm</description>
+<wire x1="-0.3048" y1="0.635" x2="-0.3048" y2="0" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-0.3048" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="-0.3048" y1="0" x2="-1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.3302" y1="0.635" x2="0.3302" y2="0" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="0.3302" y2="-0.635" width="0.3048" layer="21"/>
+<wire x1="0.3302" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.683" y1="1.524" x2="-3.683" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="-3.429" y1="-1.778" x2="3.429" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="3.683" y1="-1.524" x2="3.683" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="1.778" x2="-3.429" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="3.429" y1="1.778" x2="3.683" y2="1.524" width="0.1524" layer="21" curve="-90"/>
+<wire x1="3.429" y1="-1.778" x2="3.683" y2="-1.524" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="-1.524" x2="-3.429" y2="-1.778" width="0.1524" layer="21" curve="90"/>
+<wire x1="-3.683" y1="1.524" x2="-3.429" y2="1.778" width="0.1524" layer="21" curve="-90"/>
+<pad name="1" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-3.556" y="2.159" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.556" y="-3.429" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C375-155X418" urn="urn:adsk.eagle:footprint:25765/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 37.5 mm, outline 15.5 x 41.8 mm</description>
+<wire x1="-20.32" y1="7.62" x2="20.32" y2="7.62" width="0.1524" layer="21"/>
+<wire x1="20.828" y1="7.112" x2="20.828" y2="-7.112" width="0.1524" layer="21"/>
+<wire x1="20.32" y1="-7.62" x2="-20.32" y2="-7.62" width="0.1524" layer="21"/>
+<wire x1="-20.828" y1="-7.112" x2="-20.828" y2="7.112" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="20.32" y1="7.62" x2="20.828" y2="7.112" width="0.1524" layer="21" curve="-90"/>
+<wire x1="20.32" y1="-7.62" x2="20.828" y2="-7.112" width="0.1524" layer="21" curve="90"/>
+<wire x1="-20.828" y1="-7.112" x2="-20.32" y2="-7.62" width="0.1524" layer="21" curve="90"/>
+<wire x1="-20.828" y1="7.112" x2="-20.32" y2="7.62" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-16.002" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="16.002" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-18.796" y="0" drill="1.3208" shape="octagon"/>
+<pad name="2" x="18.796" y="0" drill="1.3208" shape="octagon"/>
+<text x="-20.447" y="8.001" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C075-063X106" urn="urn:adsk.eagle:footprint:25766/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 7.5 mm, outline 6.3 x 10.6 mm</description>
+<wire x1="4.953" y1="3.048" x2="-4.953" y2="3.048" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="2.794" x2="-5.207" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="-3.048" x2="4.953" y2="-3.048" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-2.794" x2="5.207" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="3.048" x2="5.207" y2="2.794" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.953" y1="-3.048" x2="5.207" y2="-2.794" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.207" y1="-2.794" x2="-4.953" y2="-3.048" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.207" y1="2.794" x2="-4.953" y2="3.048" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-1.27" y1="0" x2="2.667" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.667" y1="0" x2="-2.159" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="1.27" x2="-2.159" y2="0" width="0.4064" layer="21"/>
+<wire x1="-2.159" y1="0" x2="-2.159" y2="-1.27" width="0.4064" layer="21"/>
+<wire x1="-1.27" y1="1.27" x2="-1.27" y2="0" width="0.4064" layer="21"/>
+<wire x1="-1.27" y1="0" x2="-1.27" y2="-1.27" width="0.4064" layer="21"/>
+<pad name="1" x="-3.81" y="0" drill="0.9144" shape="octagon"/>
+<pad name="2" x="3.81" y="0" drill="0.9144" shape="octagon"/>
+<text x="-4.826" y="3.429" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-0.635" y="-2.54" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C275-154X316" urn="urn:adsk.eagle:footprint:25767/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 27.5 mm, outline 15.4 x 31.6 mm</description>
+<wire x1="-15.24" y1="7.62" x2="15.24" y2="7.62" width="0.1524" layer="21"/>
+<wire x1="15.748" y1="7.112" x2="15.748" y2="-7.112" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="-7.62" x2="-15.24" y2="-7.62" width="0.1524" layer="21"/>
+<wire x1="-15.748" y1="-7.112" x2="-15.748" y2="7.112" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="15.24" y1="7.62" x2="15.748" y2="7.112" width="0.1524" layer="21" curve="-90"/>
+<wire x1="15.24" y1="-7.62" x2="15.748" y2="-7.112" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="-7.112" x2="-15.24" y2="-7.62" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="7.112" x2="-15.24" y2="7.62" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-11.557" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="11.557" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-13.716" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="13.716" y="0" drill="1.1938" shape="octagon"/>
+<text x="-15.24" y="8.001" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C275-173X316" urn="urn:adsk.eagle:footprint:25768/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 27.5 mm, outline 17.3 x 31.6 mm</description>
+<wire x1="-15.24" y1="8.509" x2="15.24" y2="8.509" width="0.1524" layer="21"/>
+<wire x1="15.748" y1="8.001" x2="15.748" y2="-8.001" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="-8.509" x2="-15.24" y2="-8.509" width="0.1524" layer="21"/>
+<wire x1="-15.748" y1="-8.001" x2="-15.748" y2="8.001" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="1.905" x2="-6.731" y2="0" width="0.4064" layer="21"/>
+<wire x1="-6.731" y1="0" x2="-6.731" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="1.905" x2="-7.62" y2="0" width="0.4064" layer="21"/>
+<wire x1="-7.62" y1="0" x2="-7.62" y2="-1.905" width="0.4064" layer="21"/>
+<wire x1="15.24" y1="8.509" x2="15.748" y2="8.001" width="0.1524" layer="21" curve="-90"/>
+<wire x1="15.24" y1="-8.509" x2="15.748" y2="-8.001" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="-8.001" x2="-15.24" y2="-8.509" width="0.1524" layer="21" curve="90"/>
+<wire x1="-15.748" y1="8.001" x2="-15.24" y2="8.509" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-11.557" y1="0" x2="-7.62" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0" x2="11.557" y2="0" width="0.1524" layer="21"/>
+<pad name="1" x="-13.716" y="0" drill="1.1938" shape="octagon"/>
+<pad name="2" x="13.716" y="0" drill="1.1938" shape="octagon"/>
+<text x="-15.24" y="8.89" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C0402K" urn="urn:adsk.eagle:footprint:25769/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 0204 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 1005</description>
+<wire x1="-0.425" y1="0.2" x2="0.425" y2="0.2" width="0.1016" layer="51"/>
+<wire x1="0.425" y1="-0.2" x2="-0.425" y2="-0.2" width="0.1016" layer="51"/>
+<smd name="1" x="-0.6" y="0" dx="0.925" dy="0.74" layer="1"/>
+<smd name="2" x="0.6" y="0" dx="0.925" dy="0.74" layer="1"/>
+<text x="-0.5" y="0.425" size="1.016" layer="25">&gt;NAME</text>
+<text x="-0.5" y="-1.45" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.5" y1="-0.25" x2="-0.225" y2="0.25" layer="51"/>
+<rectangle x1="0.225" y1="-0.25" x2="0.5" y2="0.25" layer="51"/>
+</package>
+<package name="C0603K" urn="urn:adsk.eagle:footprint:25770/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 0603 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 1608</description>
+<wire x1="-0.725" y1="0.35" x2="0.725" y2="0.35" width="0.1016" layer="51"/>
+<wire x1="0.725" y1="-0.35" x2="-0.725" y2="-0.35" width="0.1016" layer="51"/>
+<smd name="1" x="-0.875" y="0" dx="1.05" dy="1.08" layer="1"/>
+<smd name="2" x="0.875" y="0" dx="1.05" dy="1.08" layer="1"/>
+<text x="-0.8" y="0.65" size="1.016" layer="25">&gt;NAME</text>
+<text x="-0.8" y="-1.65" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.8" y1="-0.4" x2="-0.45" y2="0.4" layer="51"/>
+<rectangle x1="0.45" y1="-0.4" x2="0.8" y2="0.4" layer="51"/>
+</package>
+<package name="C0805K" urn="urn:adsk.eagle:footprint:25771/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 0805 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 2012</description>
+<wire x1="-0.925" y1="0.6" x2="0.925" y2="0.6" width="0.1016" layer="51"/>
+<wire x1="0.925" y1="-0.6" x2="-0.925" y2="-0.6" width="0.1016" layer="51"/>
+<smd name="1" x="-1" y="0" dx="1.3" dy="1.6" layer="1"/>
+<smd name="2" x="1" y="0" dx="1.3" dy="1.6" layer="1"/>
+<text x="-1" y="0.875" size="1.016" layer="25">&gt;NAME</text>
+<text x="-1" y="-1.9" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-1" y1="-0.65" x2="-0.5" y2="0.65" layer="51"/>
+<rectangle x1="0.5" y1="-0.65" x2="1" y2="0.65" layer="51"/>
+</package>
+<package name="C1206K" urn="urn:adsk.eagle:footprint:25772/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 1206 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 3216</description>
+<wire x1="-1.525" y1="0.75" x2="1.525" y2="0.75" width="0.1016" layer="51"/>
+<wire x1="1.525" y1="-0.75" x2="-1.525" y2="-0.75" width="0.1016" layer="51"/>
+<smd name="1" x="-1.5" y="0" dx="1.5" dy="2" layer="1"/>
+<smd name="2" x="1.5" y="0" dx="1.5" dy="2" layer="1"/>
+<text x="-1.6" y="1.1" size="1.016" layer="25">&gt;NAME</text>
+<text x="-1.6" y="-2.1" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.6" y1="-0.8" x2="-1.1" y2="0.8" layer="51"/>
+<rectangle x1="1.1" y1="-0.8" x2="1.6" y2="0.8" layer="51"/>
+</package>
+<package name="C1210K" urn="urn:adsk.eagle:footprint:25773/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 1210 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 3225</description>
+<wire x1="-1.525" y1="1.175" x2="1.525" y2="1.175" width="0.1016" layer="51"/>
+<wire x1="1.525" y1="-1.175" x2="-1.525" y2="-1.175" width="0.1016" layer="51"/>
+<smd name="1" x="-1.5" y="0" dx="1.5" dy="2.9" layer="1"/>
+<smd name="2" x="1.5" y="0" dx="1.5" dy="2.9" layer="1"/>
+<text x="-1.6" y="1.55" size="1.016" layer="25">&gt;NAME</text>
+<text x="-1.6" y="-2.575" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.6" y1="-1.25" x2="-1.1" y2="1.25" layer="51"/>
+<rectangle x1="1.1" y1="-1.25" x2="1.6" y2="1.25" layer="51"/>
+</package>
+<package name="C1812K" urn="urn:adsk.eagle:footprint:25774/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 1812 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 4532</description>
+<wire x1="-2.175" y1="1.525" x2="2.175" y2="1.525" width="0.1016" layer="51"/>
+<wire x1="2.175" y1="-1.525" x2="-2.175" y2="-1.525" width="0.1016" layer="51"/>
+<smd name="1" x="-2.05" y="0" dx="1.8" dy="3.7" layer="1"/>
+<smd name="2" x="2.05" y="0" dx="1.8" dy="3.7" layer="1"/>
+<text x="-2.25" y="1.95" size="1.016" layer="25">&gt;NAME</text>
+<text x="-2.25" y="-2.975" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.25" y1="-1.6" x2="-1.65" y2="1.6" layer="51"/>
+<rectangle x1="1.65" y1="-1.6" x2="2.25" y2="1.6" layer="51"/>
+</package>
+<package name="C1825K" urn="urn:adsk.eagle:footprint:25775/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 1825 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 4564</description>
+<wire x1="-1.525" y1="3.125" x2="1.525" y2="3.125" width="0.1016" layer="51"/>
+<wire x1="1.525" y1="-3.125" x2="-1.525" y2="-3.125" width="0.1016" layer="51"/>
+<smd name="1" x="-1.5" y="0" dx="1.8" dy="6.9" layer="1"/>
+<smd name="2" x="1.5" y="0" dx="1.8" dy="6.9" layer="1"/>
+<text x="-1.6" y="3.55" size="1.016" layer="25">&gt;NAME</text>
+<text x="-1.6" y="-4.625" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.6" y1="-3.2" x2="-1.1" y2="3.2" layer="51"/>
+<rectangle x1="1.1" y1="-3.2" x2="1.6" y2="3.2" layer="51"/>
+</package>
+<package name="C2220K" urn="urn:adsk.eagle:footprint:25776/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 2220 reflow solder&lt;/b&gt;&lt;p&gt;Metric Code Size 5650</description>
+<wire x1="-2.725" y1="2.425" x2="2.725" y2="2.425" width="0.1016" layer="51"/>
+<wire x1="2.725" y1="-2.425" x2="-2.725" y2="-2.425" width="0.1016" layer="51"/>
+<smd name="1" x="-2.55" y="0" dx="1.85" dy="5.5" layer="1"/>
+<smd name="2" x="2.55" y="0" dx="1.85" dy="5.5" layer="1"/>
+<text x="-2.8" y="2.95" size="1.016" layer="25">&gt;NAME</text>
+<text x="-2.8" y="-3.975" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.8" y1="-2.5" x2="-2.2" y2="2.5" layer="51"/>
+<rectangle x1="2.2" y1="-2.5" x2="2.8" y2="2.5" layer="51"/>
+</package>
+<package name="C2225K" urn="urn:adsk.eagle:footprint:25777/1" library_version="1">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 2225 reflow solder&lt;/b&gt;&lt;p&gt;Metric Code Size 5664</description>
+<wire x1="-2.725" y1="3.075" x2="2.725" y2="3.075" width="0.1016" layer="51"/>
+<wire x1="2.725" y1="-3.075" x2="-2.725" y2="-3.075" width="0.1016" layer="51"/>
+<smd name="1" x="-2.55" y="0" dx="1.85" dy="6.8" layer="1"/>
+<smd name="2" x="2.55" y="0" dx="1.85" dy="6.8" layer="1"/>
+<text x="-2.8" y="3.6" size="1.016" layer="25">&gt;NAME</text>
+<text x="-2.8" y="-4.575" size="1.016" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.8" y1="-3.15" x2="-2.2" y2="3.15" layer="51"/>
+<rectangle x1="2.2" y1="-3.15" x2="2.8" y2="3.15" layer="51"/>
+</package>
+<package name="HPC0201" urn="urn:adsk.eagle:footprint:25783/1" library_version="1">
+<description>&lt;b&gt; &lt;/b&gt;&lt;p&gt;
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf</description>
+<smd name="1" x="-0.18" y="0" dx="0.2" dy="0.35" layer="1"/>
+<smd name="2" x="0.18" y="0" dx="0.2" dy="0.35" layer="1"/>
+<text x="-0.75" y="0.74" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.785" y="-1.865" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.305" y1="-0.15" x2="0.305" y2="0.15" layer="51"/>
+</package>
+<package name="C0201" urn="urn:adsk.eagle:footprint:25778/1" library_version="1">
+<description>Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf</description>
+<smd name="1" x="-0.25" y="0" dx="0.25" dy="0.35" layer="1"/>
+<smd name="2" x="0.25" y="0" dx="0.25" dy="0.35" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.3" y1="-0.15" x2="-0.15" y2="0.15" layer="51"/>
+<rectangle x1="0.15" y1="-0.15" x2="0.3" y2="0.15" layer="51"/>
+<rectangle x1="-0.15" y1="0.1" x2="0.15" y2="0.15" layer="51"/>
+<rectangle x1="-0.15" y1="-0.15" x2="0.15" y2="-0.1" layer="51"/>
+</package>
+<package name="C1808" urn="urn:adsk.eagle:footprint:25779/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+Source: AVX .. aphvc.pdf</description>
+<wire x1="-1.4732" y1="0.9502" x2="1.4732" y2="0.9502" width="0.1016" layer="51"/>
+<wire x1="-1.4478" y1="-0.9502" x2="1.4732" y2="-0.9502" width="0.1016" layer="51"/>
+<smd name="1" x="-1.95" y="0" dx="1.6" dy="2.2" layer="1"/>
+<smd name="2" x="1.95" y="0" dx="1.6" dy="2.2" layer="1"/>
+<text x="-2.233" y="1.827" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.233" y="-2.842" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.275" y1="-1.015" x2="-1.225" y2="1.015" layer="51"/>
+<rectangle x1="1.225" y1="-1.015" x2="2.275" y2="1.015" layer="51"/>
+</package>
+<package name="C3640" urn="urn:adsk.eagle:footprint:25780/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+Source: AVX .. aphvc.pdf</description>
+<wire x1="-3.8322" y1="5.0496" x2="3.8322" y2="5.0496" width="0.1016" layer="51"/>
+<wire x1="-3.8322" y1="-5.0496" x2="3.8322" y2="-5.0496" width="0.1016" layer="51"/>
+<smd name="1" x="-4.267" y="0" dx="2.6" dy="10.7" layer="1"/>
+<smd name="2" x="4.267" y="0" dx="2.6" dy="10.7" layer="1"/>
+<text x="-4.647" y="6.465" size="1.27" layer="25">&gt;NAME</text>
+<text x="-4.647" y="-7.255" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-4.57" y1="-5.1" x2="-3.05" y2="5.1" layer="51"/>
+<rectangle x1="3.05" y1="-5.1" x2="4.5688" y2="5.1" layer="51"/>
+</package>
+<package name="C01005" urn="urn:adsk.eagle:footprint:25781/1" library_version="1">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<wire x1="-1.473" y1="0.483" x2="1.473" y2="0.483" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="0.483" x2="1.473" y2="-0.483" width="0.0508" layer="39"/>
+<wire x1="1.473" y1="-0.483" x2="-1.473" y2="-0.483" width="0.0508" layer="39"/>
+<wire x1="-1.473" y1="-0.483" x2="-1.473" y2="0.483" width="0.0508" layer="39"/>
+<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/>
+<rectangle x1="-0.2" y1="-0.1" x2="-0.075" y2="0.1" layer="51"/>
+<rectangle x1="0.075" y1="-0.1" x2="0.2" y2="0.1" layer="51"/>
+<rectangle x1="-0.15" y1="0.05" x2="0.15" y2="0.1" layer="51"/>
+<rectangle x1="-0.15" y1="-0.1" x2="0.15" y2="-0.05" layer="51"/>
+<smd name="1" x="-0.1625" y="0" dx="0.2" dy="0.25" layer="1"/>
+<smd name="2" x="0.1625" y="0" dx="0.2" dy="0.25" layer="1"/>
+<text x="-0.4" y="0.3" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.4" y="-1.6" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+<packages3d>
+<package3d name="M0805" urn="urn:adsk.eagle:package:26079/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.10 W</description>
+</package3d>
+<package3d name="C1206K" urn="urn:adsk.eagle:package:26202/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 1206 reflow solder
+Metric Code Size 3216</description>
+</package3d>
+<package3d name="R0402" urn="urn:adsk.eagle:package:26058/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R0603" urn="urn:adsk.eagle:package:26057/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R0805" urn="urn:adsk.eagle:package:26059/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R0805W" urn="urn:adsk.eagle:package:26060/1" type="box" library_version="1">
+<description>RESISTOR wave soldering</description>
+</package3d>
+<package3d name="R1206" urn="urn:adsk.eagle:package:26062/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R1206W" urn="urn:adsk.eagle:package:26064/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R1210" urn="urn:adsk.eagle:package:26063/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R1210W" urn="urn:adsk.eagle:package:26065/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R2010" urn="urn:adsk.eagle:package:26066/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R2010W" urn="urn:adsk.eagle:package:26068/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R2012" urn="urn:adsk.eagle:package:26067/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R2012W" urn="urn:adsk.eagle:package:26069/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R2512" urn="urn:adsk.eagle:package:26070/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R2512W" urn="urn:adsk.eagle:package:26072/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R3216" urn="urn:adsk.eagle:package:26071/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R3216W" urn="urn:adsk.eagle:package:26074/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R3225" urn="urn:adsk.eagle:package:26073/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R3225W" urn="urn:adsk.eagle:package:26075/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R5025" urn="urn:adsk.eagle:package:26080/1" type="box" library_version="1">
+<description>RESISTOR</description>
+</package3d>
+<package3d name="R5025W" urn="urn:adsk.eagle:package:26077/1" type="box" library_version="1">
+<description>RESISTOR
+wave soldering</description>
+</package3d>
+<package3d name="R6332" urn="urn:adsk.eagle:package:26076/1" type="box" library_version="1">
+<description>RESISTOR
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf</description>
+</package3d>
+<package3d name="R6332W" urn="urn:adsk.eagle:package:26078/1" type="box" library_version="1">
+<description>RESISTOR wave soldering
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf</description>
+</package3d>
+<package3d name="M1206" urn="urn:adsk.eagle:package:26088/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.25 W</description>
+</package3d>
+<package3d name="M1406" urn="urn:adsk.eagle:package:26081/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.12 W</description>
+</package3d>
+<package3d name="M2012" urn="urn:adsk.eagle:package:26082/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.10 W</description>
+</package3d>
+<package3d name="M2309" urn="urn:adsk.eagle:package:26085/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.25 W</description>
+</package3d>
+<package3d name="M3216" urn="urn:adsk.eagle:package:26083/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.25 W</description>
+</package3d>
+<package3d name="M3516" urn="urn:adsk.eagle:package:26086/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.12 W</description>
+</package3d>
+<package3d name="M5923" urn="urn:adsk.eagle:package:26084/1" type="box" library_version="1">
+<description>RESISTOR
+MELF 0.25 W</description>
+</package3d>
+<package3d name="0204/5" urn="urn:adsk.eagle:package:25955/1" type="box" library_version="1">
+<description>RESISTOR
+type 0204, grid 5 mm</description>
+</package3d>
+<package3d name="0204/7" urn="urn:adsk.eagle:package:25945/1" type="box" library_version="1">
+<description>RESISTOR
+type 0204, grid 7.5 mm</description>
+</package3d>
+<package3d name="0204V" urn="urn:adsk.eagle:package:25948/1" type="box" library_version="1">
+<description>RESISTOR
+type 0204, grid 2.5 mm</description>
+</package3d>
+<package3d name="0207/10" urn="urn:adsk.eagle:package:25939/1" type="box" library_version="1">
+<description>RESISTOR
+type 0207, grid 10 mm</description>
+</package3d>
+<package3d name="0207/12" urn="urn:adsk.eagle:package:25938/1" type="box" library_version="1">
+<description>RESISTOR
+type 0207, grid 12 mm</description>
+</package3d>
+<package3d name="0207/15" urn="urn:adsk.eagle:package:25947/1" type="box" library_version="1">
+<description>RESISTOR
+type 0207, grid 15mm</description>
+</package3d>
+<package3d name="0207/2V" urn="urn:adsk.eagle:package:25941/1" type="box" library_version="1">
+<description>RESISTOR
+type 0207, grid 2.5 mm</description>
+</package3d>
+<package3d name="0207/5V" urn="urn:adsk.eagle:package:25944/1" type="box" library_version="1">
+<description>RESISTOR
+type 0207, grid 5 mm</description>
+</package3d>
+<package3d name="0207/7" urn="urn:adsk.eagle:package:25942/1" type="box" library_version="1">
+<description>RESISTOR
+type 0207, grid 7.5 mm</description>
+</package3d>
+<package3d name="0309/10" urn="urn:adsk.eagle:package:26087/1" type="box" library_version="1">
+<description>RESISTOR
+type 0309, grid 10mm</description>
+</package3d>
+<package3d name="0309/12" urn="urn:adsk.eagle:package:26089/1" type="box" library_version="1">
+<description>RESISTOR
+type 0309, grid 12.5 mm</description>
+</package3d>
+<package3d name="0309V" urn="urn:adsk.eagle:package:26090/1" type="box" library_version="1">
+<description>RESISTOR
+type 0309, grid 2.5 mm</description>
+</package3d>
+<package3d name="0411/12" urn="urn:adsk.eagle:package:26091/1" type="box" library_version="1">
+<description>RESISTOR
+type 0411, grid 12.5 mm</description>
+</package3d>
+<package3d name="0411/15" urn="urn:adsk.eagle:package:26093/1" type="box" library_version="1">
+<description>RESISTOR
+type 0411, grid 15 mm</description>
+</package3d>
+<package3d name="0411V" urn="urn:adsk.eagle:package:26092/1" type="box" library_version="1">
+<description>RESISTOR
+type 0411, grid 3.81 mm</description>
+</package3d>
+<package3d name="0414/15" urn="urn:adsk.eagle:package:26094/1" type="box" library_version="1">
+<description>RESISTOR
+type 0414, grid 15 mm</description>
+</package3d>
+<package3d name="0414V" urn="urn:adsk.eagle:package:26095/1" type="box" library_version="1">
+<description>RESISTOR
+type 0414, grid 5 mm</description>
+</package3d>
+<package3d name="0617/17" urn="urn:adsk.eagle:package:26096/1" type="box" library_version="1">
+<description>RESISTOR
+type 0617, grid 17.5 mm</description>
+</package3d>
+<package3d name="0617/22" urn="urn:adsk.eagle:package:26103/1" type="box" library_version="1">
+<description>RESISTOR
+type 0617, grid 22.5 mm</description>
+</package3d>
+<package3d name="0617V" urn="urn:adsk.eagle:package:26097/1" type="box" library_version="1">
+<description>RESISTOR
+type 0617, grid 5 mm</description>
+</package3d>
+<package3d name="0922/22" urn="urn:adsk.eagle:package:26107/1" type="box" library_version="1">
+<description>RESISTOR
+type 0922, grid 22.5 mm</description>
+</package3d>
+<package3d name="P0613V" urn="urn:adsk.eagle:package:26106/1" type="box" library_version="1">
+<description>RESISTOR
+type 0613, grid 5 mm</description>
+</package3d>
+<package3d name="P0613/15" urn="urn:adsk.eagle:package:26098/1" type="box" library_version="1">
+<description>RESISTOR
+type 0613, grid 15 mm</description>
+</package3d>
+<package3d name="P0817/22" urn="urn:adsk.eagle:package:26099/1" type="box" library_version="1">
+<description>RESISTOR
+type 0817, grid 22.5 mm</description>
+</package3d>
+<package3d name="P0817V" urn="urn:adsk.eagle:package:26100/1" type="box" library_version="1">
+<description>RESISTOR
+type 0817, grid 6.35 mm</description>
+</package3d>
+<package3d name="V234/12" urn="urn:adsk.eagle:package:26108/1" type="box" library_version="1">
+<description>RESISTOR
+type V234, grid 12.5 mm</description>
+</package3d>
+<package3d name="V235/17" urn="urn:adsk.eagle:package:26102/1" type="box" library_version="1">
+<description>RESISTOR
+type V235, grid 17.78 mm</description>
+</package3d>
+<package3d name="V526-0" urn="urn:adsk.eagle:package:26101/1" type="box" library_version="1">
+<description>RESISTOR
+type V526-0, grid 2.5 mm</description>
+</package3d>
+<package3d name="MINI_MELF-0102R" urn="urn:adsk.eagle:package:26104/1" type="box" library_version="1">
+<description>CECC Size RC2211 Reflow Soldering
+source Beyschlag</description>
+</package3d>
+<package3d name="MINI_MELF-0102W" urn="urn:adsk.eagle:package:26105/1" type="box" library_version="1">
+<description>CECC Size RC2211 Wave Soldering
+source Beyschlag</description>
+</package3d>
+<package3d name="MINI_MELF-0204R" urn="urn:adsk.eagle:package:26109/1" type="box" library_version="1">
+<description>CECC Size RC3715 Reflow Soldering
+source Beyschlag</description>
+</package3d>
+<package3d name="MINI_MELF-0204W" urn="urn:adsk.eagle:package:26111/1" type="box" library_version="1">
+<description>CECC Size RC3715 Wave Soldering
+source Beyschlag</description>
+</package3d>
+<package3d name="MINI_MELF-0207R" urn="urn:adsk.eagle:package:26113/1" type="box" library_version="1">
+<description>CECC Size RC6123 Reflow Soldering
+source Beyschlag</description>
+</package3d>
+<package3d name="MINI_MELF-0207W" urn="urn:adsk.eagle:package:26112/1" type="box" library_version="1">
+<description>CECC Size RC6123 Wave Soldering
+source Beyschlag</description>
+</package3d>
+<package3d name="0922V" urn="urn:adsk.eagle:package:26110/1" type="box" library_version="1">
+<description>RESISTOR
+type 0922, grid 7.5 mm</description>
+</package3d>
+<package3d name="RDH/15" urn="urn:adsk.eagle:package:26114/1" type="box" library_version="1">
+<description>RESISTOR
+type RDH, grid 15 mm</description>
+</package3d>
+<package3d name="MINI_MELF-0102AX" urn="urn:adsk.eagle:package:26115/1" type="box" library_version="1">
+<description>Mini MELF 0102 Axial</description>
+</package3d>
+<package3d name="R0201" urn="urn:adsk.eagle:package:26117/1" type="box" library_version="1">
+<description>RESISTOR chip
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf</description>
+</package3d>
+<package3d name="VTA52" urn="urn:adsk.eagle:package:26116/1" type="box" library_version="1">
+<description>Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
+MIL SIZE RBR52
+Source: VISHAY .. vta56.pdf</description>
+</package3d>
+<package3d name="VTA53" urn="urn:adsk.eagle:package:26118/1" type="box" library_version="1">
+<description>Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
+MIL SIZE RBR53
+Source: VISHAY .. vta56.pdf</description>
+</package3d>
+<package3d name="VTA54" urn="urn:adsk.eagle:package:26119/1" type="box" library_version="1">
+<description>Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
+MIL SIZE RBR54
+Source: VISHAY .. vta56.pdf</description>
+</package3d>
+<package3d name="VTA55" urn="urn:adsk.eagle:package:26120/1" type="box" library_version="1">
+<description>Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
+MIL SIZE RBR55
+Source: VISHAY .. vta56.pdf</description>
+</package3d>
+<package3d name="VTA56" urn="urn:adsk.eagle:package:26129/1" type="box" library_version="1">
+<description>Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
+MIL SIZE RBR56
+Source: VISHAY .. vta56.pdf</description>
+</package3d>
+<package3d name="VMTA55" urn="urn:adsk.eagle:package:26121/1" type="box" library_version="1">
+<description>Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
+MIL SIZE RNC55
+Source: VISHAY .. vta56.pdf</description>
+</package3d>
+<package3d name="VMTB60" urn="urn:adsk.eagle:package:26122/1" type="box" library_version="1">
+<description>Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
+MIL SIZE RNC60
+Source: VISHAY .. vta56.pdf</description>
+</package3d>
+<package3d name="R4527" urn="urn:adsk.eagle:package:26124/1" type="box" library_version="1">
+<description>Package 4527
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf</description>
+</package3d>
+<package3d name="WSC0001" urn="urn:adsk.eagle:package:26123/1" type="box" library_version="1">
+<description>Wirewound Resistors, Precision Power
+Source: VISHAY wscwsn.pdf</description>
+</package3d>
+<package3d name="WSC0002" urn="urn:adsk.eagle:package:26125/1" type="box" library_version="1">
+<description>Wirewound Resistors, Precision Power
+Source: VISHAY wscwsn.pdf</description>
+</package3d>
+<package3d name="WSC01/2" urn="urn:adsk.eagle:package:26127/1" type="box" library_version="1">
+<description>Wirewound Resistors, Precision Power
+Source: VISHAY wscwsn.pdf</description>
+</package3d>
+<package3d name="WSC2515" urn="urn:adsk.eagle:package:26134/1" type="box" library_version="1">
+<description>Wirewound Resistors, Precision Power
+Source: VISHAY wscwsn.pdf</description>
+</package3d>
+<package3d name="WSC4527" urn="urn:adsk.eagle:package:26126/1" type="box" library_version="1">
+<description>Wirewound Resistors, Precision Power
+Source: VISHAY wscwsn.pdf</description>
+</package3d>
+<package3d name="WSC6927" urn="urn:adsk.eagle:package:26128/1" type="box" library_version="1">
+<description>Wirewound Resistors, Precision Power
+Source: VISHAY wscwsn.pdf</description>
+</package3d>
+<package3d name="R1218" urn="urn:adsk.eagle:package:26131/1" type="box" library_version="1">
+<description>CRCW1218 Thick Film, Rectangular Chip Resistors
+Source: http://www.vishay.com .. dcrcw.pdf</description>
+</package3d>
+<package3d name="1812X7R" urn="urn:adsk.eagle:package:26130/1" type="box" library_version="1">
+<description>Chip Monolithic Ceramic Capacitors Medium Voltage High Capacitance for General Use
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf</description>
+</package3d>
+<package3d name="PRL1632" urn="urn:adsk.eagle:package:26132/1" type="box" library_version="1">
+<description>PRL1632 are realized as 1W for 3.2 × 1.6mm(1206)
+Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf</description>
+</package3d>
+<package3d name="R01005" urn="urn:adsk.eagle:package:26133/1" type="box" library_version="1">
+</package3d>
+<package3d name="C0402" urn="urn:adsk.eagle:package:26136/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C0504" urn="urn:adsk.eagle:package:26135/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C0603" urn="urn:adsk.eagle:package:26138/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C0805" urn="urn:adsk.eagle:package:26137/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C1206" urn="urn:adsk.eagle:package:26140/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C1210" urn="urn:adsk.eagle:package:26139/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C1310" urn="urn:adsk.eagle:package:26142/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C1608" urn="urn:adsk.eagle:package:26141/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C1812" urn="urn:adsk.eagle:package:26143/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C1825" urn="urn:adsk.eagle:package:26144/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C2012" urn="urn:adsk.eagle:package:26145/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C3216" urn="urn:adsk.eagle:package:26146/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C3225" urn="urn:adsk.eagle:package:26147/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C4532" urn="urn:adsk.eagle:package:26148/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C4564" urn="urn:adsk.eagle:package:26155/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+<package3d name="C025-024X044" urn="urn:adsk.eagle:package:26149/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 mm, outline 2.4 x 4.4 mm</description>
+</package3d>
+<package3d name="C025-025X050" urn="urn:adsk.eagle:package:26151/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 mm, outline 2.5 x 5 mm</description>
+</package3d>
+<package3d name="C025-030X050" urn="urn:adsk.eagle:package:26154/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 mm, outline 3 x 5 mm</description>
+</package3d>
+<package3d name="C025-040X050" urn="urn:adsk.eagle:package:26150/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 mm, outline 4 x 5 mm</description>
+</package3d>
+<package3d name="C025-050X050" urn="urn:adsk.eagle:package:26152/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 mm, outline 5 x 5 mm</description>
+</package3d>
+<package3d name="C025-060X050" urn="urn:adsk.eagle:package:26153/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 mm, outline 6 x 5 mm</description>
+</package3d>
+<package3d name="C025_050-024X070" urn="urn:adsk.eagle:package:26157/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm</description>
+</package3d>
+<package3d name="C025_050-025X075" urn="urn:adsk.eagle:package:26158/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C025_050-035X075" urn="urn:adsk.eagle:package:26156/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C025_050-045X075" urn="urn:adsk.eagle:package:26159/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C025_050-055X075" urn="urn:adsk.eagle:package:26163/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C050-024X044" urn="urn:adsk.eagle:package:26162/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 2.4 x 4.4 mm</description>
+</package3d>
+<package3d name="C050-025X075" urn="urn:adsk.eagle:package:26160/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 2.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C050-045X075" urn="urn:adsk.eagle:package:26165/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 4.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C050-030X075" urn="urn:adsk.eagle:package:26161/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 3 x 7.5 mm</description>
+</package3d>
+<package3d name="C050-050X075" urn="urn:adsk.eagle:package:26164/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 5 x 7.5 mm</description>
+</package3d>
+<package3d name="C050-055X075" urn="urn:adsk.eagle:package:26166/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 5.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C050-075X075" urn="urn:adsk.eagle:package:26182/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 7.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C050H075X075" urn="urn:adsk.eagle:package:26167/1" type="box" library_version="1">
+<description>CAPACITOR
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C075-032X103" urn="urn:adsk.eagle:package:26168/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 7.5 mm, outline 3.2 x 10.3 mm</description>
+</package3d>
+<package3d name="C075-042X103" urn="urn:adsk.eagle:package:26170/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 7.5 mm, outline 4.2 x 10.3 mm</description>
+</package3d>
+<package3d name="C075-052X106" urn="urn:adsk.eagle:package:26169/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 7.5 mm, outline 5.2 x 10.6 mm</description>
+</package3d>
+<package3d name="C102-043X133" urn="urn:adsk.eagle:package:26171/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 10.2 mm, outline 4.3 x 13.3 mm</description>
+</package3d>
+<package3d name="C102-054X133" urn="urn:adsk.eagle:package:26172/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 10.2 mm, outline 5.4 x 13.3 mm</description>
+</package3d>
+<package3d name="C102-064X133" urn="urn:adsk.eagle:package:26173/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 10.2 mm, outline 6.4 x 13.3 mm</description>
+</package3d>
+<package3d name="C102_152-062X184" urn="urn:adsk.eagle:package:26189/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm</description>
+</package3d>
+<package3d name="C150-054X183" urn="urn:adsk.eagle:package:26175/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 15 mm, outline 5.4 x 18.3 mm</description>
+</package3d>
+<package3d name="C150-064X183" urn="urn:adsk.eagle:package:26178/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 15 mm, outline 6.4 x 18.3 mm</description>
+</package3d>
+<package3d name="C150-072X183" urn="urn:adsk.eagle:package:26174/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 15 mm, outline 7.2 x 18.3 mm</description>
+</package3d>
+<package3d name="C150-084X183" urn="urn:adsk.eagle:package:26176/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 15 mm, outline 8.4 x 18.3 mm</description>
+</package3d>
+<package3d name="C150-091X182" urn="urn:adsk.eagle:package:26177/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 15 mm, outline 9.1 x 18.2 mm</description>
+</package3d>
+<package3d name="C225-062X268" urn="urn:adsk.eagle:package:26179/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 22.5 mm, outline 6.2 x 26.8 mm</description>
+</package3d>
+<package3d name="C225-074X268" urn="urn:adsk.eagle:package:26180/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 22.5 mm, outline 7.4 x 26.8 mm</description>
+</package3d>
+<package3d name="C225-087X268" urn="urn:adsk.eagle:package:26181/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 22.5 mm, outline 8.7 x 26.8 mm</description>
+</package3d>
+<package3d name="C225-108X268" urn="urn:adsk.eagle:package:26184/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 22.5 mm, outline 10.8 x 26.8 mm</description>
+</package3d>
+<package3d name="C225-113X268" urn="urn:adsk.eagle:package:26183/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 22.5 mm, outline 11.3 x 26.8 mm</description>
+</package3d>
+<package3d name="C275-093X316" urn="urn:adsk.eagle:package:26185/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 27.5 mm, outline 9.3 x 31.6 mm</description>
+</package3d>
+<package3d name="C275-113X316" urn="urn:adsk.eagle:package:26186/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 27.5 mm, outline 11.3 x 31.6 mm</description>
+</package3d>
+<package3d name="C275-134X316" urn="urn:adsk.eagle:package:26187/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 27.5 mm, outline 13.4 x 31.6 mm</description>
+</package3d>
+<package3d name="C275-205X316" urn="urn:adsk.eagle:package:26188/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 27.5 mm, outline 20.5 x 31.6 mm</description>
+</package3d>
+<package3d name="C325-137X374" urn="urn:adsk.eagle:package:26190/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 32.5 mm, outline 13.7 x 37.4 mm</description>
+</package3d>
+<package3d name="C325-162X374" urn="urn:adsk.eagle:package:26198/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 32.5 mm, outline 16.2 x 37.4 mm</description>
+</package3d>
+<package3d name="C325-182X374" urn="urn:adsk.eagle:package:26191/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 32.5 mm, outline 18.2 x 37.4 mm</description>
+</package3d>
+<package3d name="C375-192X418" urn="urn:adsk.eagle:package:26192/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 37.5 mm, outline 19.2 x 41.8 mm</description>
+</package3d>
+<package3d name="C375-203X418" urn="urn:adsk.eagle:package:26194/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 37.5 mm, outline 20.3 x 41.8 mm</description>
+</package3d>
+<package3d name="C050-035X075" urn="urn:adsk.eagle:package:26193/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 5 mm, outline 3.5 x 7.5 mm</description>
+</package3d>
+<package3d name="C375-155X418" urn="urn:adsk.eagle:package:26195/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 37.5 mm, outline 15.5 x 41.8 mm</description>
+</package3d>
+<package3d name="C075-063X106" urn="urn:adsk.eagle:package:26196/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 7.5 mm, outline 6.3 x 10.6 mm</description>
+</package3d>
+<package3d name="C275-154X316" urn="urn:adsk.eagle:package:26197/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 27.5 mm, outline 15.4 x 31.6 mm</description>
+</package3d>
+<package3d name="C275-173X316" urn="urn:adsk.eagle:package:26203/1" type="box" library_version="1">
+<description>CAPACITOR
+grid 27.5 mm, outline 17.3 x 31.6 mm</description>
+</package3d>
+<package3d name="C0402K" urn="urn:adsk.eagle:package:26199/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 0204 reflow solder
+Metric Code Size 1005</description>
+</package3d>
+<package3d name="C0603K" urn="urn:adsk.eagle:package:26200/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 0603 reflow solder
+Metric Code Size 1608</description>
+</package3d>
+<package3d name="C0805K" urn="urn:adsk.eagle:package:26201/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 0805 reflow solder
+Metric Code Size 2012</description>
+</package3d>
+<package3d name="C1210K" urn="urn:adsk.eagle:package:26204/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 1210 reflow solder
+Metric Code Size 3225</description>
+</package3d>
+<package3d name="C1812K" urn="urn:adsk.eagle:package:26207/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 1812 reflow solder
+Metric Code Size 4532</description>
+</package3d>
+<package3d name="C1825K" urn="urn:adsk.eagle:package:26205/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 1825 reflow solder
+Metric Code Size 4564</description>
+</package3d>
+<package3d name="C2220K" urn="urn:adsk.eagle:package:26206/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 2220 reflow solderMetric Code Size 5650</description>
+</package3d>
+<package3d name="C2225K" urn="urn:adsk.eagle:package:26208/1" type="box" library_version="1">
+<description>Ceramic Chip Capacitor KEMET 2225 reflow solderMetric Code Size 5664</description>
+</package3d>
+<package3d name="HPC0201" urn="urn:adsk.eagle:package:26213/1" type="box" library_version="1">
+<description> 
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf</description>
+</package3d>
+<package3d name="C0201" urn="urn:adsk.eagle:package:26209/1" type="box" library_version="1">
+<description>Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf</description>
+</package3d>
+<package3d name="C1808" urn="urn:adsk.eagle:package:26212/1" type="box" library_version="1">
+<description>CAPACITOR
+Source: AVX .. aphvc.pdf</description>
+</package3d>
+<package3d name="C3640" urn="urn:adsk.eagle:package:26210/1" type="box" library_version="1">
+<description>CAPACITOR
+Source: AVX .. aphvc.pdf</description>
+</package3d>
+<package3d name="C01005" urn="urn:adsk.eagle:package:26211/1" type="box" library_version="1">
+<description>CAPACITOR</description>
+</package3d>
+</packages3d>
+<symbols>
+<symbol name="R-EU-1" urn="urn:adsk.eagle:symbol:25624/1" library_version="1">
+<wire x1="-2.54" y1="-0.889" x2="2.54" y2="-0.889" width="0.254" layer="94"/>
+<wire x1="2.54" y1="0.889" x2="-2.54" y2="0.889" width="0.254" layer="94"/>
+<wire x1="2.54" y1="-0.889" x2="2.54" y2="0.889" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-0.889" x2="-2.54" y2="0.889" width="0.254" layer="94"/>
+<text x="-3.81" y="1.4986" size="1.778" layer="95">&gt;NAME</text>
+<text x="-3.81" y="-3.302" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+</symbol>
+<symbol name="C-EU-1" urn="urn:adsk.eagle:symbol:25782/1" library_version="1">
+<wire x1="0" y1="0" x2="0" y2="-0.508" width="0.1524" layer="94"/>
+<wire x1="0" y1="-2.54" x2="0" y2="-2.032" width="0.1524" layer="94"/>
+<text x="1.524" y="0.381" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.524" y="-4.699" size="1.778" layer="96">&gt;VALUE</text>
+<rectangle x1="-2.032" y1="-2.032" x2="2.032" y2="-1.524" layer="94"/>
+<rectangle x1="-2.032" y1="-1.016" x2="2.032" y2="-0.508" layer="94"/>
+<pin name="1" x="0" y="2.54" visible="off" length="short" direction="pas" swaplevel="1" rot="R270"/>
+<pin name="2" x="0" y="-5.08" visible="off" length="short" direction="pas" swaplevel="1" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="R-EU_" urn="urn:adsk.eagle:component:26223/1" prefix="R" uservalue="yes" library_version="1">
+<description>&lt;B&gt;RESISTOR&lt;/B&gt;, European symbol</description>
+<gates>
+<gate name="G$1" symbol="R-EU-1" x="0" y="0"/>
+</gates>
+<devices>
+<device name="R0402" package="R0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26058/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0603" package="R0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26057/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0805" package="R0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26059/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0805W" package="R0805W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26060/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1206" package="R1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26062/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1206W" package="R1206W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26064/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1210" package="R1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26063/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1210W" package="R1210W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26065/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2010" package="R2010">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26066/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2010W" package="R2010W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26068/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2012" package="R2012">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26067/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2012W" package="R2012W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26069/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2512" package="R2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26070/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2512W" package="R2512W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26072/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3216" package="R3216">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26071/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3216W" package="R3216W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26074/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3225" package="R3225">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26073/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3225W" package="R3225W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26075/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R5025" package="R5025">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26080/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R5025W" package="R5025W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26077/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R6332" package="R6332">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26076/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R6332W" package="R6332W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26078/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M0805" package="M0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26079/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M1206" package="M1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26088/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M1406" package="M1406">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26081/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M2012" package="M2012">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26082/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M2309" package="M2309">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26085/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M3216" package="M3216">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26083/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M3516" package="M3516">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26086/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M5923" package="M5923">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26084/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0204/5" package="0204/5">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25955/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0204/7" package="0204/7">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25945/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0204/2V" package="0204V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25948/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/10" package="0207/10">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25939/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/12" package="0207/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25938/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/15" package="0207/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25947/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/2V" package="0207/2V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25941/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/5V" package="0207/5V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25944/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/7" package="0207/7">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:25942/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0309/10" package="0309/10">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26087/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0309/12" package="0309/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26089/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0309/V" package="0309V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26090/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0411/12" package="0411/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26091/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0411/15" package="0411/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26093/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0411/3V" package="0411V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26092/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0414/15" package="0414/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26094/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0414/5V" package="0414V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26095/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0617/17" package="0617/17">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26096/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0617/22" package="0617/22">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26103/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0617/5V" package="0617V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26097/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0922/22" package="0922/22">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26107/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0613/5V" package="P0613V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26106/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0613/15" package="P0613/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26098/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0817/22" package="P0817/22">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26099/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0817/7V" package="P0817V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26100/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="V234/12" package="V234/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26108/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="V235/17" package="V235/17">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26102/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="V526-0" package="V526-0">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26101/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0102R" package="MINI_MELF-0102R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26104/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0102W" package="MINI_MELF-0102W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26105/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0204R" package="MINI_MELF-0204R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26109/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0204W" package="MINI_MELF-0204W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26111/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0207R" package="MINI_MELF-0207R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26113/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0207W" package="MINI_MELF-0207W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26112/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0922V" package="0922V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26110/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="RDH/15" package="RDH/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26114/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0102AX" package="MINI_MELF-0102AX">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26115/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0201" package="R0201">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26117/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA52" package="VTA52">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26116/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA53" package="VTA53">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26118/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA54" package="VTA54">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26119/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA55" package="VTA55">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26120/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA56" package="VTA56">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26129/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VMTA55" package="VMTA55">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26121/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VMTB60" package="VMTB60">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26122/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R4527" package="R4527">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26124/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC0001" package="WSC0001">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26123/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC0002" package="WSC0002">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26125/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC01/2" package="WSC01/2">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26127/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC2515" package="WSC2515">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26134/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC4527" package="WSC4527">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26126/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC6927" package="WSC6927">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26128/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1218" package="R1218">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26131/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1812X7R" package="1812X7R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26130/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="PRL1632" package="PRL1632">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26132/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="01005" package="R01005">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26133/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="C-EU" urn="urn:adsk.eagle:component:26226/1" prefix="C" uservalue="yes" library_version="1">
+<description>&lt;B&gt;CAPACITOR&lt;/B&gt;, European symbol</description>
+<gates>
+<gate name="G$1" symbol="C-EU-1" x="0" y="0"/>
+</gates>
+<devices>
+<device name="C0402" package="C0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26136/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0504" package="C0504">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26135/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0603" package="C0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26138/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0805" package="C0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26137/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1206" package="C1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26140/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1210" package="C1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26139/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1310" package="C1310">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26142/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1608" package="C1608">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26141/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1812" package="C1812">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26143/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1825" package="C1825">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26144/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C2012" package="C2012">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26145/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C3216" package="C3216">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26146/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C3225" package="C3225">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26147/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C4532" package="C4532">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26148/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C4564" package="C4564">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26155/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025-024X044" package="C025-024X044">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26149/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025-025X050" package="C025-025X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26151/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025-030X050" package="C025-030X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26154/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025-040X050" package="C025-040X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26150/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025-050X050" package="C025-050X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26152/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025-060X050" package="C025-060X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26153/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C025_050-024X070" package="C025_050-024X070">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26157/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-025X075" package="C025_050-025X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26158/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-035X075" package="C025_050-035X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26156/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-045X075" package="C025_050-045X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26159/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-055X075" package="C025_050-055X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26163/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-024X044" package="C050-024X044">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26162/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-025X075" package="C050-025X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26160/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-045X075" package="C050-045X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26165/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-030X075" package="C050-030X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26161/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-050X075" package="C050-050X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26164/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-055X075" package="C050-055X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26166/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-075X075" package="C050-075X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26182/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050H075X075" package="C050H075X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26167/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="075-032X103" package="C075-032X103">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26168/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="075-042X103" package="C075-042X103">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26170/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="075-052X106" package="C075-052X106">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26169/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="102-043X133" package="C102-043X133">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26171/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="102-054X133" package="C102-054X133">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26172/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="102-064X133" package="C102-064X133">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26173/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="102_152-062X184" package="C102_152-062X184">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26189/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="150-054X183" package="C150-054X183">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26175/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="150-064X183" package="C150-064X183">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26178/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="150-072X183" package="C150-072X183">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26174/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="150-084X183" package="C150-084X183">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26176/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="150-091X182" package="C150-091X182">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26177/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="225-062X268" package="C225-062X268">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26179/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="225-074X268" package="C225-074X268">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26180/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="225-087X268" package="C225-087X268">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26181/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="225-108X268" package="C225-108X268">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26184/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="225-113X268" package="C225-113X268">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26183/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="275-093X316" package="C275-093X316">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26185/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="275-113X316" package="C275-113X316">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26186/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="275-134X316" package="C275-134X316">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26187/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="275-205X316" package="C275-205X316">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26188/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="325-137X374" package="C325-137X374">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26190/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="325-162X374" package="C325-162X374">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26198/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="325-182X374" package="C325-182X374">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26191/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="375-192X418" package="C375-192X418">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26192/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="375-203X418" package="C375-203X418">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26194/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="050-035X075" package="C050-035X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26193/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="375-155X418" package="C375-155X418">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26195/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="075-063X106" package="C075-063X106">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26196/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="275-154X316" package="C275-154X316">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26197/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="275-173X316" package="C275-173X316">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26203/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0402K" package="C0402K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26199/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0603K" package="C0603K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26200/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0805K" package="C0805K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26201/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1206K" package="C1206K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26202/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1210K" package="C1210K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26204/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1812K" package="C1812K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26207/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1825K" package="C1825K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26205/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C2220K" package="C2220K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26206/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C2225K" package="C2225K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26208/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="HPC0201" package="HPC0201">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26213/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0201" package="C0201">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26209/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1808" package="C1808">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26212/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C3640" package="C3640">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26210/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="01005" package="C01005">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:26211/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="transistor" urn="urn:adsk.eagle:library:402">
+<description>&lt;b&gt;Transistors&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="SOT23" urn="urn:adsk.eagle:footprint:28669/1" library_version="5">
+<description>&lt;b&gt;SOT-23&lt;/b&gt;</description>
+<wire x1="1.4224" y1="0.6604" x2="1.4224" y2="-0.6604" width="0.1524" layer="51"/>
+<wire x1="1.4224" y1="-0.6604" x2="-1.4224" y2="-0.6604" width="0.1524" layer="51"/>
+<wire x1="-1.4224" y1="-0.6604" x2="-1.4224" y2="0.6604" width="0.1524" layer="51"/>
+<wire x1="-1.4224" y1="0.6604" x2="1.4224" y2="0.6604" width="0.1524" layer="51"/>
+<smd name="3" x="0" y="1.1" dx="1" dy="1.4" layer="1"/>
+<smd name="2" x="0.95" y="-1.1" dx="1" dy="1.4" layer="1"/>
+<smd name="1" x="-0.95" y="-1.1" dx="1" dy="1.4" layer="1"/>
+<text x="-1.905" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.905" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.2286" y1="0.7112" x2="0.2286" y2="1.2954" layer="51"/>
+<rectangle x1="0.7112" y1="-1.2954" x2="1.1684" y2="-0.7112" layer="51"/>
+<rectangle x1="-1.1684" y1="-1.2954" x2="-0.7112" y2="-0.7112" layer="51"/>
+</package>
+</packages>
+<packages3d>
+<package3d name="SOT23" urn="urn:adsk.eagle:package:28738/2" type="model" library_version="5">
+<description>SOT-23</description>
+</package3d>
+</packages3d>
+<symbols>
+<symbol name="NPN" urn="urn:adsk.eagle:symbol:29821/1" library_version="2">
+<wire x1="2.54" y1="2.54" x2="0.508" y2="1.524" width="0.1524" layer="94"/>
+<wire x1="1.778" y1="-1.524" x2="2.54" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="-2.54" x2="1.27" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="1.778" y2="-1.524" width="0.1524" layer="94"/>
+<wire x1="1.54" y1="-2.04" x2="0.308" y2="-1.424" width="0.1524" layer="94"/>
+<wire x1="1.524" y1="-2.413" x2="2.286" y2="-2.413" width="0.254" layer="94"/>
+<wire x1="2.286" y1="-2.413" x2="1.778" y2="-1.778" width="0.254" layer="94"/>
+<wire x1="1.778" y1="-1.778" x2="1.524" y2="-2.286" width="0.254" layer="94"/>
+<wire x1="1.524" y1="-2.286" x2="1.905" y2="-2.286" width="0.254" layer="94"/>
+<wire x1="1.905" y1="-2.286" x2="1.778" y2="-2.032" width="0.254" layer="94"/>
+<text x="-10.16" y="7.62" size="1.778" layer="95">&gt;NAME</text>
+<text x="-10.16" y="5.08" size="1.778" layer="96">&gt;VALUE</text>
+<rectangle x1="-0.254" y1="-2.54" x2="0.508" y2="2.54" layer="94"/>
+<pin name="B" x="-2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="E" x="2.54" y="-5.08" visible="off" length="short" direction="pas" swaplevel="3" rot="R90"/>
+<pin name="C" x="2.54" y="5.08" visible="off" length="short" direction="pas" swaplevel="2" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="BC847" urn="urn:adsk.eagle:component:30053/3" prefix="T" library_version="5">
+<description>&lt;b&gt;NPN TRANSISTOR&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="NPN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SOT23">
+<connects>
+<connect gate="G$1" pin="B" pad="1"/>
+<connect gate="G$1" pin="C" pad="3"/>
+<connect gate="G$1" pin="E" pad="2"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:28738/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="mfj-236">
+<description>2 x 3mm-leds in vertial, left = K, right = A</description>
+<packages>
+<package name="LEDX2_V_K_A">
+<pad name="K1" x="-1.27" y="3.81" drill="0.6" diameter="1.27" shape="octagon"/>
+<pad name="A1" x="1.27" y="3.81" drill="0.6" diameter="1.27"/>
+<pad name="K2" x="-1.27" y="1.524" drill="0.6" diameter="1.27" shape="octagon"/>
+<pad name="A2" x="1.27" y="1.524" drill="0.6" diameter="1.27"/>
+<wire x1="-2.413" y1="4.826" x2="2.413" y2="4.826" width="0.127" layer="21"/>
+<wire x1="-2.413" y1="4.826" x2="-2.413" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="2.413" y1="4.826" x2="2.413" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-4.191" x2="2.413" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="-2.413" y1="-4.191" x2="-1.524" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="-1.524" y1="-4.191" x2="1.524" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-4.191" x2="1.524" y2="-5.842" width="0.127" layer="21"/>
+<wire x1="-1.524" y1="-5.842" x2="-1.524" y2="-4.191" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-5.842" x2="-1.524" y2="-5.842" width="0.127" layer="21" curve="-165.749967"/>
+<wire x1="2.54" y1="-5.08" x2="3.683" y2="-5.969" width="0.127" layer="21"/>
+<wire x1="3.683" y1="-5.969" x2="3.683" y2="-5.588" width="0.127" layer="21"/>
+<wire x1="3.683" y1="-5.969" x2="3.302" y2="-5.969" width="0.127" layer="21"/>
+<wire x1="2.032" y1="-5.842" x2="3.175" y2="-6.731" width="0.127" layer="21"/>
+<wire x1="3.175" y1="-6.731" x2="3.175" y2="-6.35" width="0.127" layer="21"/>
+<wire x1="3.175" y1="-6.731" x2="2.794" y2="-6.731" width="0.127" layer="21"/>
+<text x="-2.413" y="5.588" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-8.89" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LEDX2_V">
+<wire x1="3.81" y1="0" x2="2.54" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="2.54" y1="-2.54" x2="1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="3.81" y1="-2.54" x2="2.54" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="2.54" y1="-2.54" x2="1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="3.81" y1="0" x2="1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="0.508" y1="-0.762" x2="-0.889" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="0.635" y1="-1.905" x2="-0.762" y2="-3.302" width="0.1524" layer="94"/>
+<text x="4.064" y="8.128" size="1.778" layer="95" rot="R180">&gt;NAME</text>
+<text x="4.572" y="-8.509" size="1.778" layer="96" rot="R180">&gt;VALUE</text>
+<pin name="K2" x="2.54" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A2" x="2.54" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-0.889" y="-2.159"/>
+<vertex x="-0.508" y="-1.27"/>
+<vertex x="0" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-0.762" y="-3.302"/>
+<vertex x="-0.381" y="-2.413"/>
+<vertex x="0.127" y="-2.921"/>
+</polygon>
+<wire x1="-1.27" y1="0" x2="-2.54" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-2.54" x2="-3.81" y2="0" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="-2.54" x2="-2.54" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-2.54" x2="-3.81" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="0" x2="-3.81" y2="0" width="0.254" layer="94"/>
+<wire x1="-4.572" y1="-0.762" x2="-5.969" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-4.445" y1="-1.905" x2="-5.842" y2="-3.302" width="0.1524" layer="94"/>
+<pin name="K1" x="-2.54" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A1" x="-2.54" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-5.969" y="-2.159"/>
+<vertex x="-5.588" y="-1.27"/>
+<vertex x="-5.08" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-5.842" y="-3.302"/>
+<vertex x="-5.461" y="-2.413"/>
+<vertex x="-4.953" y="-2.921"/>
+</polygon>
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-7.62" x2="-7.62" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-7.62" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="-6.858" y="-0.762" size="1.27" layer="94">UP</text>
+<text x="6.858" y="0.508" size="1.27" layer="94" rot="R180">DN</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LEDX2_V">
+<gates>
+<gate name="G$1" symbol="LEDX2_V" x="2.54" y="0"/>
+</gates>
+<devices>
+<device name="K-A" package="LEDX2_V_K_A">
+<connects>
+<connect gate="G$1" pin="A1" pad="A1"/>
+<connect gate="G$1" pin="A2" pad="A2"/>
+<connect gate="G$1" pin="K1" pad="K1"/>
+<connect gate="G$1" pin="K2" pad="K2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="con-harting" urn="urn:adsk.eagle:library:151">
+<description>&lt;b&gt;Harting Ribbon Cable Connectors&lt;/b&gt;&lt;p&gt;
+This library includes the former libraries ribcon.lbr and ribcon4.lbr.&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="CON10" urn="urn:adsk.eagle:footprint:7079/1" library_version="1">
+<description>&lt;b&gt;CONNECTOR&lt;/b&gt;</description>
+<wire x1="8.8646" y1="-3.4798" x2="8.8646" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="3.5052" x2="8.001" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="3.5052" x2="-8.89" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-3.4798" x2="-8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-4.1656" x2="-6.35" y2="-4.1656" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="8.255" x2="6.35" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="-5.5118" y1="-2.3368" x2="-4.6482" y2="-2.3368" width="0.1524" layer="21"/>
+<wire x1="-4.6482" y1="-2.3368" x2="-5.08" y2="-3.175" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-3.175" x2="-5.5118" y2="-2.3368" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="-3.4798" x2="-6.35" y2="-4.1656" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-3.4798" x2="6.35" y2="-4.1656" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="3.5052" x2="6.35" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="3.5052" x2="-6.35" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="0" y1="9.525" x2="3.81" y2="8.255" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="9.525" x2="-2.54" y2="8.255" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="8.255" x2="0" y2="9.525" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-3.175" x2="-5.08" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="3.5052" x2="8.001" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="2.159" x2="8.8646" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="0.635" x2="8.8646" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="3.5052" x2="6.35" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="2.159" x2="8.8646" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="0.635" x2="8.8646" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="3.5052" x2="-6.35" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-2.159" x2="8.8646" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-2.159" x2="8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="-2.159" x2="8.8646" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-0.635" x2="8.8646" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="8.8646" y1="-0.635" x2="8.8646" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-3.4798" x2="8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="3.5052" x2="-8.001" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="-3.4798" x2="6.35" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="0.635" x2="8.001" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="3.5052" x2="-8.001" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="3.5052" x2="-8.89" y2="3.5052" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="2.159" x2="-8.001" y2="2.159" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="0.635" x2="-8.001" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="0.635" x2="-8.001" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-0.635" x2="-8.001" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-2.159" x2="-8.001" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="-2.159" x2="-8.001" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="0.635" x2="-8.89" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="2.159" x2="-8.89" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-0.635" x2="-8.89" y2="-2.159" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-2.159" x2="-8.89" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="-8.001" y1="-3.4798" x2="-6.35" y2="-3.4798" width="0.1524" layer="21"/>
+<wire x1="8.001" y1="-3.4798" x2="8.8646" y2="-3.4798" width="0.1524" layer="21"/>
+<pad name="1" x="-5.08" y="-1.27" drill="0.9144"/>
+<pad name="2" x="-5.08" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="3" x="-2.54" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="4" x="-2.54" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="5" x="0" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="6" x="0" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="7" x="2.54" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="8" x="2.54" y="1.27" drill="0.9144" shape="octagon"/>
+<pad name="9" x="5.08" y="-1.27" drill="0.9144" shape="octagon"/>
+<pad name="10" x="5.08" y="1.27" drill="0.9144" shape="octagon"/>
+<text x="-7.493" y="-1.905" size="1.524" layer="21" ratio="10">1</text>
+<text x="-5.715" y="6.0198" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.715" y="4.191" size="1.27" layer="21" ratio="10">R-Cable10P</text>
+<text x="-6.35" y="-5.715" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-5.334" y1="-2.7686" x2="-4.826" y2="-2.5146" layer="21"/>
+<rectangle x1="-5.461" y1="-2.5146" x2="-5.08" y2="-2.3876" layer="21"/>
+<rectangle x1="-5.08" y1="-2.5146" x2="-4.699" y2="-2.3876" layer="21"/>
+<rectangle x1="-5.207" y1="-2.9718" x2="-4.953" y2="-2.7178" layer="21"/>
+</package>
+</packages>
+<packages3d>
+<package3d name="CON10" urn="urn:adsk.eagle:package:7121/1" type="box" library_version="1">
+<description>CONNECTOR</description>
+</package3d>
+</packages3d>
+<symbols>
+<symbol name="05-2" urn="urn:adsk.eagle:symbol:7078/1" library_version="1">
+<wire x1="3.81" y1="-7.62" x2="-3.81" y2="-7.62" width="0.4064" layer="94"/>
+<wire x1="-3.81" y1="7.62" x2="-3.81" y2="-7.62" width="0.4064" layer="94"/>
+<wire x1="-3.81" y1="7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
+<wire x1="3.81" y1="-7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
+<circle x="1.905" y="-5.08" radius="0.635" width="0.254" layer="94"/>
+<circle x="1.905" y="-2.54" radius="0.635" width="0.254" layer="94"/>
+<circle x="1.905" y="0" radius="0.635" width="0.254" layer="94"/>
+<circle x="1.905" y="2.54" radius="0.635" width="0.254" layer="94"/>
+<circle x="1.905" y="5.08" radius="0.635" width="0.254" layer="94"/>
+<circle x="-1.905" y="-5.08" radius="0.635" width="0.254" layer="94"/>
+<circle x="-1.905" y="-2.54" radius="0.635" width="0.254" layer="94"/>
+<circle x="-1.905" y="0" radius="0.635" width="0.254" layer="94"/>
+<circle x="-1.905" y="2.54" radius="0.635" width="0.254" layer="94"/>
+<circle x="-1.905" y="5.08" radius="0.635" width="0.254" layer="94"/>
+<text x="-3.81" y="-10.16" size="1.778" layer="96">&gt;VALUE</text>
+<text x="-3.81" y="8.382" size="1.778" layer="95">&gt;NAME</text>
+<pin name="1" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="2" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
+<pin name="3" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="4" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
+<pin name="5" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="6" x="-7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1"/>
+<pin name="7" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="8" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
+<pin name="9" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="10" x="-7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="CON10" urn="urn:adsk.eagle:component:7145/1" prefix="CON" uservalue="yes" library_version="1">
+<description>&lt;b&gt;CONNECTOR&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="05-2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="CON10">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:7121/1"/>
+</package3dinstances>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="diode" urn="urn:adsk.eagle:library:210">
+<description>&lt;b&gt;Diodes&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Motorola : www.onsemi.com
+&lt;li&gt;Fairchild : www.fairchildsemi.com
+&lt;li&gt;Philips : www.semiconductors.com
+&lt;li&gt;Vishay : www.vishay.de
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DO41-10" urn="urn:adsk.eagle:footprint:43094/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 2.54 mm, horizontal, grid 10.16 mm</description>
+<wire x1="2.032" y1="-1.27" x2="-2.032" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.032" y1="-1.27" x2="2.032" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-2.032" y1="1.27" x2="2.032" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-2.032" y1="1.27" x2="-2.032" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0" x2="4.064" y2="0" width="0.762" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.064" y2="0" width="0.762" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<pad name="A" x="5.08" y="0" drill="1.1176"/>
+<pad name="C" x="-5.08" y="0" drill="1.1176"/>
+<text x="-2.032" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.032" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-1.27" x2="-1.143" y2="1.27" layer="21"/>
+<rectangle x1="2.032" y1="-0.381" x2="3.937" y2="0.381" layer="21"/>
+<rectangle x1="-3.937" y1="-0.381" x2="-2.032" y2="0.381" layer="21"/>
+</package>
+<package name="DO35-10" urn="urn:adsk.eagle:footprint:43092/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 2 mm, horizontal, grid 10.16 mm</description>
+<wire x1="5.08" y1="0" x2="4.191" y2="0" width="0.508" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.191" y2="0" width="0.508" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.032" y1="1.016" x2="2.286" y2="0.762" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.286" y1="0.762" x2="-2.032" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.286" y1="-0.762" x2="-2.032" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.032" y1="-1.016" x2="2.286" y2="-0.762" width="0.1524" layer="21" curve="90"/>
+<wire x1="2.286" y1="-0.762" x2="2.286" y2="0.762" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="0.762" x2="-2.286" y2="-0.762" width="0.1524" layer="21"/>
+<wire x1="-2.032" y1="1.016" x2="2.032" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-2.032" y1="-1.016" x2="2.032" y2="-1.016" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="0.8128" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="0.8128" shape="long"/>
+<text x="-2.159" y="1.27" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.159" y="-2.667" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.905" y1="-1.016" x2="-1.397" y2="1.016" layer="21"/>
+<rectangle x1="2.286" y1="-0.254" x2="4.191" y2="0.254" layer="21"/>
+<rectangle x1="-4.191" y1="-0.254" x2="-2.286" y2="0.254" layer="21"/>
+</package>
+<package name="DO204-10" urn="urn:adsk.eagle:footprint:43129/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 4 mm, horizontal, grid 10 mm</description>
+<wire x1="2.54" y1="0.635" x2="2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="2.5255" y2="0.6542" width="0.1524" layer="21" curve="-105.826017"/>
+<wire x1="-2.5255" y1="-0.6542" x2="2.54" y2="-0.635" width="0.1524" layer="21" curve="105.826017"/>
+<wire x1="2.54" y1="0.635" x2="2.921" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="3.048" y1="0.508" x2="2.921" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.635" x2="2.921" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="3.048" y1="-0.508" x2="2.921" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="3.048" y1="-0.508" x2="3.048" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-2.921" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-3.048" y1="0.508" x2="-2.921" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.635" x2="-2.921" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-3.048" y1="-0.508" x2="-2.921" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-3.048" y1="-0.508" x2="-3.048" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-1.778" y1="1.016" x2="-1.778" y2="-1.016" width="0.6096" layer="21"/>
+<wire x1="-2.286" y1="0.508" x2="-2.286" y2="-0.508" width="0.6096" layer="21"/>
+<wire x1="-2.032" y1="-0.762" x2="-2.286" y2="-0.508" width="0.6096" layer="21"/>
+<wire x1="-2.286" y1="0.508" x2="-2.032" y2="0.762" width="0.6096" layer="21"/>
+<wire x1="-2.794" y1="0.381" x2="-2.794" y2="-0.381" width="0.6096" layer="21"/>
+<wire x1="2.794" y1="0.381" x2="2.794" y2="-0.381" width="0.6096" layer="21"/>
+<wire x1="5.08" y1="0" x2="3.683" y2="0" width="0.8128" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-3.683" y2="0" width="0.8128" layer="51"/>
+<wire x1="-0.889" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.508" x2="0.508" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.508" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.889" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.508" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.508" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="1.1176" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.1176" shape="long"/>
+<text x="-2.54" y="2.286" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-3.556" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="3.048" y1="-0.4064" x2="3.6068" y2="0.4064" layer="21"/>
+<rectangle x1="-3.6068" y1="-0.4064" x2="-3.048" y2="0.4064" layer="21"/>
+</package>
+<package name="DO15-12" urn="urn:adsk.eagle:footprint:43132/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, horizontal, grid 12.7 mm</description>
+<wire x1="-3.81" y1="-1.778" x2="3.81" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="1.778" x2="-3.81" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="-1.778" x2="3.81" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="-3.81" y1="1.778" x2="-3.81" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="0" x2="5.334" y2="0" width="0.762" layer="51"/>
+<wire x1="-6.35" y1="0" x2="-5.334" y2="0" width="0.762" layer="51"/>
+<pad name="C" x="-6.35" y="0" drill="1.1176" shape="long"/>
+<pad name="A" x="6.35" y="0" drill="1.1176" shape="long"/>
+<text x="-3.683" y="2.159" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.159" y="-1.397" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.048" y1="-1.778" x2="-2.413" y2="1.778" layer="21"/>
+<rectangle x1="-5.207" y1="-0.381" x2="-3.81" y2="0.381" layer="21"/>
+<rectangle x1="3.81" y1="-0.381" x2="5.207" y2="0.381" layer="21"/>
+</package>
+<package name="SOD57-10" urn="urn:adsk.eagle:footprint:43130/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 4 mm, vertical, grid 10.16 mm</description>
+<wire x1="5.08" y1="0" x2="3.81" y2="0" width="0.8128" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-3.81" y2="0" width="0.8128" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="1.016" x2="-2.286" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.286" y1="-1.016" x2="2.286" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-1.397" y1="1.016" x2="1.397" y2="1.016" width="0.1524" layer="21" curve="-131.11209"/>
+<wire x1="-1.397" y1="-1.016" x2="1.397" y2="-1.016" width="0.1524" layer="21" curve="131.11209"/>
+<wire x1="-2.286" y1="1.016" x2="-1.397" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="2.286" y1="1.016" x2="1.397" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-2.286" y1="-1.016" x2="-1.397" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="1.397" y1="-1.016" x2="2.286" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="1.1938" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.1938" shape="long"/>
+<text x="-2.286" y="2.286" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-3.556" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.905" y1="-1.016" x2="-1.397" y2="1.016" layer="21"/>
+<rectangle x1="-3.8354" y1="-0.4064" x2="-2.286" y2="0.4064" layer="21"/>
+<rectangle x1="2.286" y1="-0.4064" x2="3.8354" y2="0.4064" layer="21"/>
+</package>
+<package name="DO201-15" urn="urn:adsk.eagle:footprint:43127/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 5.6 mm, horizontal, grid 15.24 mm</description>
+<wire x1="-1.27" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.5842" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.143" y2="0.5842" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="0.5842" x2="1.143" y2="-0.5842" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="-0.5842" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="2.286" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.5842" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-2.794" x2="-5.08" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="2.794" x2="5.08" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="2.794" x2="5.08" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-2.794" x2="-5.08" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0" x2="6.223" y2="0" width="1.27" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.223" y2="0" width="1.27" layer="51"/>
+<pad name="C" x="-7.62" y="0" drill="1.4986" shape="long"/>
+<pad name="A" x="7.62" y="0" drill="1.4986" shape="long"/>
+<text x="-5.08" y="3.175" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-2.159" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-4.191" y1="-2.794" x2="-3.429" y2="2.794" layer="21"/>
+<rectangle x1="-5.969" y1="-0.635" x2="-5.08" y2="0.635" layer="21"/>
+<rectangle x1="5.08" y1="-0.635" x2="5.969" y2="0.635" layer="21"/>
+</package>
+<package name="DO07" urn="urn:adsk.eagle:footprint:43160/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 2.54 mm, horizontal, grid 10.16 mm</description>
+<wire x1="5.08" y1="0" x2="4.191" y2="0" width="0.508" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.191" y2="0" width="0.508" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="3.302" y1="1.27" x2="3.556" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.556" y1="1.016" x2="-3.302" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-3.556" y1="-1.016" x2="-3.302" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="3.302" y1="-1.27" x2="3.556" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="3.556" y1="-1.016" x2="3.556" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-3.556" y1="1.016" x2="-3.556" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-3.302" y1="1.27" x2="3.302" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-3.302" y1="-1.27" x2="3.302" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="0.8128" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="0.8128" shape="long"/>
+<text x="-3.429" y="1.524" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.429" y="-2.921" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.429" y1="-1.27" x2="-1.651" y2="1.27" layer="21"/>
+<rectangle x1="3.556" y1="-0.254" x2="4.191" y2="0.254" layer="21"/>
+<rectangle x1="-4.191" y1="-0.254" x2="-3.556" y2="0.254" layer="21"/>
+</package>
+<package name="P1-10" urn="urn:adsk.eagle:footprint:43138/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3 mm, horizontal, grid 10.16 mm</description>
+<wire x1="-3.175" y1="-1.524" x2="3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="1.524" x2="-3.175" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.524" x2="3.175" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.524" x2="-3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0" x2="4.064" y2="0" width="0.762" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.064" y2="0" width="0.762" layer="51"/>
+<pad name="C" x="-5.08" y="0" drill="1.1176" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.1176" shape="long"/>
+<text x="-3.048" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-3.048" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.794" y1="-1.524" x2="-2.032" y2="1.524" layer="21"/>
+<rectangle x1="-3.937" y1="-0.381" x2="-3.175" y2="0.381" layer="21"/>
+<rectangle x1="3.175" y1="-0.381" x2="3.937" y2="0.381" layer="21"/>
+</package>
+<package name="P2-15" urn="urn:adsk.eagle:footprint:43106/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 5 mm, horizontal, grid 12.7 mm</description>
+<wire x1="-4.826" y1="-2.54" x2="-4.826" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="2.54" x2="4.826" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="2.54" x2="4.826" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-2.54" x2="-4.826" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-1.143" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="2.54" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0" x2="6.223" y2="0" width="1.27" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.223" y2="0" width="1.27" layer="51"/>
+<pad name="C" x="-7.62" y="0" drill="1.4986" shape="long"/>
+<pad name="A" x="7.62" y="0" drill="1.4986" shape="long"/>
+<text x="-4.8006" y="2.8194" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.9022" y="-4.699" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.429" y1="-2.54" x2="-2.921" y2="2.54" layer="21"/>
+<rectangle x1="4.826" y1="-0.635" x2="5.969" y2="0.635" layer="21"/>
+<rectangle x1="-5.969" y1="-0.635" x2="-4.826" y2="0.635" layer="21"/>
+</package>
+<package name="DO34-7" urn="urn:adsk.eagle:footprint:43109/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 1.8 mm, horizontal, grid 7.62 mm</description>
+<wire x1="-1.524" y1="-0.889" x2="1.524" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="1.524" y1="0.889" x2="-1.524" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="1.524" y1="-0.889" x2="1.524" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-1.524" y1="0.889" x2="-1.524" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="0" x2="2.921" y2="0" width="0.508" layer="51"/>
+<wire x1="-3.81" y1="0" x2="-2.921" y2="0" width="0.508" layer="51"/>
+<wire x1="-0.508" y1="0" x2="-0.127" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.889" y1="0.508" x2="0.889" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="0.889" y1="-0.508" x2="-0.127" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.127" y1="0" x2="1.27" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.127" y1="0" x2="0.889" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-0.127" y1="0.508" x2="-0.127" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.127" y1="0" x2="-0.127" y2="-0.508" width="0.1524" layer="21"/>
+<pad name="C" x="-3.81" y="0" drill="0.8128" shape="long"/>
+<pad name="A" x="3.81" y="0" drill="0.8128" shape="long"/>
+<text x="-1.524" y="1.143" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.524" y="-2.413" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.143" y1="-0.889" x2="-0.762" y2="0.889" layer="21"/>
+<rectangle x1="1.524" y1="-0.254" x2="2.921" y2="0.254" layer="21"/>
+<rectangle x1="-2.921" y1="-0.254" x2="-1.524" y2="0.254" layer="21"/>
+</package>
+<package name="SOT54H" urn="urn:adsk.eagle:footprint:43111/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+2-lead plastic, vertical</description>
+<wire x1="-1.651" y1="2.032" x2="1.651" y2="2.032" width="0.1524" layer="21" curve="280.388858"/>
+<wire x1="1.651" y1="2.032" x2="-1.651" y2="2.032" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-1.905" x2="0.508" y2="-0.635" width="0.2032" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.381" y2="-1.27" width="0.2032" layer="21"/>
+<wire x1="-0.381" y1="-1.27" x2="0.508" y2="-1.905" width="0.2032" layer="21"/>
+<wire x1="-0.508" y1="-1.905" x2="-0.508" y2="-0.635" width="0.2032" layer="21"/>
+<pad name="A" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="C" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="3.175" y="0.635" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="3.175" y="-1.27" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SOD523" urn="urn:adsk.eagle:footprint:43179/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;</description>
+<wire x1="-0.59" y1="0.4" x2="0.59" y2="0.4" width="0.1016" layer="51"/>
+<wire x1="0.59" y1="0.4" x2="0.59" y2="-0.4" width="0.1016" layer="51"/>
+<wire x1="0.59" y1="-0.4" x2="-0.59" y2="-0.4" width="0.1016" layer="51"/>
+<wire x1="-0.59" y1="-0.4" x2="-0.59" y2="0.4" width="0.1016" layer="51"/>
+<smd name="A" x="0.7" y="0" dx="0.7" dy="0.5" layer="1"/>
+<smd name="C" x="-0.6" y="0" dx="0.7" dy="0.5" layer="1"/>
+<text x="-0.635" y="0.635" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.635" y="-1.905" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.75" y1="-0.17" x2="-0.54" y2="0.17" layer="51"/>
+<rectangle x1="0.54" y1="-0.17" x2="0.75" y2="0.17" layer="51"/>
+<rectangle x1="-0.59" y1="-0.4" x2="-0.3" y2="0.4" layer="51"/>
+</package>
+<package name="TO18D" urn="urn:adsk.eagle:footprint:43190/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+2-lead metall, vertical</description>
+<wire x1="1.651" y1="-2.286" x2="2.286" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="2.286" y1="-2.921" x2="2.921" y2="-2.286" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="-2.286" x2="2.286" y2="-1.651" width="0.1524" layer="21"/>
+<circle x="0" y="0.0254" radius="2.7686" width="0.1524" layer="21"/>
+<circle x="0" y="0" radius="2.54" width="0.0508" layer="21"/>
+<pad name="A" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="C" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="3.175" y="0.762" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="3.175" y="-1.143" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="C1702-05" urn="urn:adsk.eagle:footprint:43191/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, vertical, grid 5.08 mm</description>
+<wire x1="2.54" y1="0" x2="0.762" y2="0" width="1.0668" layer="51"/>
+<wire x1="-2.54" y1="0" x2="-0.889" y2="0" width="1.0668" layer="51"/>
+<circle x="-2.54" y="0" radius="1.778" width="0.1524" layer="21"/>
+<pad name="C" x="-2.54" y="0" drill="1.397" shape="octagon"/>
+<pad name="A" x="2.54" y="0" drill="1.397" shape="octagon"/>
+<text x="-4.318" y="2.032" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.318" y="-3.302" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-0.7366" y1="-0.5334" x2="0.635" y2="0.5334" layer="21"/>
+</package>
+<package name="C1702-15" urn="urn:adsk.eagle:footprint:43117/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, horizontal, grid 15.24 mm</description>
+<wire x1="-4.572" y1="-1.778" x2="-4.572" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="4.572" y1="1.778" x2="-4.572" y2="1.778" width="0.1524" layer="21"/>
+<wire x1="4.572" y1="1.778" x2="4.572" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="-4.572" y1="-1.778" x2="4.572" y2="-1.778" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0" x2="6.096" y2="0" width="1.1176" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.096" y2="0" width="1.1176" layer="51"/>
+<pad name="C" x="-7.62" y="0" drill="1.397" shape="long"/>
+<pad name="A" x="7.62" y="0" drill="1.397" shape="long"/>
+<text x="-4.572" y="2.159" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.794" y="-1.397" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.81" y1="-1.778" x2="-3.302" y2="1.778" layer="21"/>
+<rectangle x1="4.572" y1="-0.5334" x2="5.9436" y2="0.5334" layer="21"/>
+<rectangle x1="-5.9436" y1="-0.5334" x2="-4.572" y2="0.5334" layer="21"/>
+</package>
+<package name="SGA-10" urn="urn:adsk.eagle:footprint:43154/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 4 mm, vertical, grid 10.16 mm</description>
+<wire x1="5.08" y1="0" x2="3.175" y2="0" width="0.8128" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-3.175" y2="0" width="0.8128" layer="51"/>
+<wire x1="-0.762" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="0.508" x2="0.635" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-0.508" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="0.635" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0.508" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.381" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="2.032" y1="0.381" x2="2.032" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-1.397" y1="1.1938" x2="-1.397" y2="-1.1938" width="0.254" layer="21"/>
+<wire x1="-1.5748" y1="1.0414" x2="-1.5748" y2="-1.016" width="0.254" layer="21"/>
+<wire x1="-2.032" y1="0.381" x2="-2.032" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.032" y1="0.381" x2="2.032" y2="0.381" width="0.1524" layer="21" curve="-145.291951"/>
+<wire x1="-2.032" y1="-0.381" x2="2.032" y2="-0.381" width="0.1524" layer="21" curve="145.291951"/>
+<pad name="C" x="-5.08" y="0" drill="1.1176" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.1176" shape="long"/>
+<text x="-2.54" y="2.286" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-3.556" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="2.032" y1="-0.4064" x2="3.8608" y2="0.4064" layer="21"/>
+<rectangle x1="-3.8608" y1="-0.4064" x2="-2.032" y2="0.4064" layer="21"/>
+</package>
+<package name="SOD64-10" urn="urn:adsk.eagle:footprint:43140/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 4.8 mm, vertical, grid 10.16 mm</description>
+<wire x1="5.08" y1="0" x2="3.556" y2="0" width="1.3716" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-3.556" y2="0" width="1.3716" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="1.397" x2="-2.54" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-1.397" x2="2.54" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="-1.397" y1="1.397" x2="1.397" y2="1.397" width="0.1524" layer="21" curve="-131.11209"/>
+<wire x1="-1.397" y1="-1.397" x2="1.397" y2="-1.397" width="0.1524" layer="21" curve="131.11209"/>
+<wire x1="-2.54" y1="1.397" x2="-1.397" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="1.397" x2="1.397" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-1.397" x2="-1.397" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="1.397" y1="-1.397" x2="2.54" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="1.6002" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.6002" shape="long"/>
+<text x="-2.54" y="2.54" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-3.937" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.905" y1="-1.397" x2="-1.397" y2="1.397" layer="21"/>
+<rectangle x1="2.54" y1="-0.6604" x2="3.3274" y2="0.6604" layer="21"/>
+<rectangle x1="-3.3274" y1="-0.6604" x2="-2.54" y2="0.6604" layer="21"/>
+</package>
+<package name="SOD61A" urn="urn:adsk.eagle:footprint:43141/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, vertical, grid 10.16 mm</description>
+<wire x1="5.08" y1="0" x2="4.064" y2="0" width="0.6604" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.064" y2="0" width="0.6604" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-2.921" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-2.54" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="0.381" x2="-2.921" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="-0.381" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="2.921" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="0.381" x2="2.921" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.635" x2="2.921" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.635" x2="2.54" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="-0.381" x2="2.794" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.508" x2="2.794" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.508" x2="2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.921" y1="0.381" x2="2.794" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.508" x2="2.794" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.508" x2="2.54" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="0.381" x2="-2.794" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.794" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.921" y1="-0.381" x2="-2.794" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.508" x2="-2.794" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.508" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.794" y1="0.381" x2="2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.381" x2="2.54" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="2.794" y1="-0.381" x2="2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.381" x2="2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.794" y1="-0.381" x2="-2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.381" x2="-2.54" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-2.794" y1="0.381" x2="-2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.381" x2="-2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="2.5178" y2="0.655" width="0.1524" layer="21" curve="-84.093979"/>
+<wire x1="-2.5178" y1="-0.655" x2="2.54" y2="-0.635" width="0.1524" layer="21" curve="84.093979"/>
+<pad name="C" x="-5.08" y="0" drill="0.9144" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="0.9144" shape="long"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-3.048" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="2.921" y1="-0.3302" x2="4.0132" y2="0.3302" layer="21"/>
+<rectangle x1="-4.0132" y1="-0.3302" x2="-2.921" y2="0.3302" layer="21"/>
+<rectangle x1="2.54" y1="-0.381" x2="2.921" y2="0.381" layer="21"/>
+<rectangle x1="-2.921" y1="-0.381" x2="-2.54" y2="0.381" layer="21"/>
+</package>
+<package name="SOD61B" urn="urn:adsk.eagle:footprint:43142/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, vertical, grid 15.24 mm</description>
+<wire x1="7.62" y1="0" x2="6.604" y2="0" width="0.6604" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.604" y2="0" width="0.6604" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.635" x2="-4.826" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.635" x2="-4.445" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.381" x2="-4.826" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-0.381" x2="-4.445" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="0.635" x2="4.826" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="0.381" x2="4.826" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-0.635" x2="4.826" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-0.635" x2="4.445" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-0.381" x2="4.699" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-0.508" x2="4.699" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-0.508" x2="4.445" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="0.381" x2="4.699" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="0.508" x2="4.699" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="0.508" x2="4.445" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.381" x2="-4.699" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.508" x2="-4.699" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.508" x2="-4.445" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-0.381" x2="-4.699" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="-0.508" x2="-4.699" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="-0.508" x2="-4.445" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="0.381" x2="4.445" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="0.381" x2="4.445" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-0.381" x2="4.445" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-0.381" x2="4.445" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="-0.381" x2="-4.445" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="-0.381" x2="-4.445" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="0.381" x2="-4.445" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.381" x2="-4.445" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.635" x2="4.4429" y2="0.636" width="0.1524" layer="21" curve="-52.21463"/>
+<wire x1="-4.4429" y1="-0.636" x2="4.445" y2="-0.635" width="0.1524" layer="21" curve="52.21463"/>
+<pad name="C" x="-7.62" y="0" drill="0.9144" shape="long"/>
+<pad name="A" x="7.62" y="0" drill="0.9144" shape="long"/>
+<text x="-2.794" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.794" y="-3.302" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="4.445" y1="-0.381" x2="4.826" y2="0.381" layer="21"/>
+<rectangle x1="-4.826" y1="-0.381" x2="-4.445" y2="0.381" layer="21"/>
+<rectangle x1="4.826" y1="-0.3302" x2="6.5278" y2="0.3302" layer="21"/>
+<rectangle x1="-6.5278" y1="-0.3302" x2="-4.826" y2="0.3302" layer="21"/>
+</package>
+<package name="SOD61C" urn="urn:adsk.eagle:footprint:43143/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, vertical, grid 17.78 mm</description>
+<wire x1="8.89" y1="0" x2="7.874" y2="0" width="0.6604" layer="51"/>
+<wire x1="-8.89" y1="0" x2="-7.874" y2="0" width="0.6604" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="0.635" x2="-5.969" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="0.635" x2="-5.588" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-5.969" y1="0.381" x2="-5.969" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-5.969" y1="-0.381" x2="-5.588" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="0.635" x2="5.969" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="5.969" y1="0.381" x2="5.969" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="-0.635" x2="5.969" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="-0.635" x2="5.588" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="5.969" y1="-0.381" x2="5.842" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="-0.508" x2="5.842" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="-0.508" x2="5.588" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="5.969" y1="0.381" x2="5.842" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="0.508" x2="5.842" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="0.508" x2="5.588" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-5.969" y1="0.381" x2="-5.842" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="0.508" x2="-5.842" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="0.508" x2="-5.588" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.969" y1="-0.381" x2="-5.842" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="-0.508" x2="-5.842" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="-0.508" x2="-5.588" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="5.842" y1="0.381" x2="5.588" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="0.381" x2="5.588" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="5.842" y1="-0.381" x2="5.588" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="5.588" y1="-0.381" x2="5.588" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.842" y1="-0.381" x2="-5.588" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="-0.381" x2="-5.588" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-5.842" y1="0.381" x2="-5.588" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.588" y1="0.381" x2="-5.588" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-5.55" y1="0.65" x2="-4.55" y2="1" width="0.1524" layer="21"/>
+<wire x1="-4.55" y1="1" x2="-3.4" y2="1.3" width="0.1524" layer="21"/>
+<wire x1="-3.4" y1="1.3" x2="-2.05" y2="1.55" width="0.1524" layer="21"/>
+<wire x1="-2.05" y1="1.55" x2="-1" y2="1.65" width="0.1524" layer="21"/>
+<wire x1="-1" y1="1.65" x2="0" y2="1.7" width="0.1524" layer="21"/>
+<wire x1="5.55" y1="-0.65" x2="4.55" y2="-1" width="0.1524" layer="21"/>
+<wire x1="4.55" y1="-1" x2="3.4" y2="-1.3" width="0.1524" layer="21"/>
+<wire x1="3.4" y1="-1.3" x2="2.05" y2="-1.55" width="0.1524" layer="21"/>
+<wire x1="2.05" y1="-1.55" x2="1" y2="-1.65" width="0.1524" layer="21"/>
+<wire x1="1" y1="-1.65" x2="0" y2="-1.7" width="0.1524" layer="21"/>
+<wire x1="5.55" y1="0.65" x2="4.55" y2="1" width="0.1524" layer="21"/>
+<wire x1="4.55" y1="1" x2="3.4" y2="1.3" width="0.1524" layer="21"/>
+<wire x1="3.4" y1="1.3" x2="2.05" y2="1.55" width="0.1524" layer="21"/>
+<wire x1="2.05" y1="1.55" x2="1" y2="1.65" width="0.1524" layer="21"/>
+<wire x1="1" y1="1.65" x2="0" y2="1.7" width="0.1524" layer="21"/>
+<wire x1="-5.55" y1="-0.65" x2="-4.55" y2="-1" width="0.1524" layer="21"/>
+<wire x1="-4.55" y1="-1" x2="-3.4" y2="-1.3" width="0.1524" layer="21"/>
+<wire x1="-3.4" y1="-1.3" x2="-2.05" y2="-1.55" width="0.1524" layer="21"/>
+<wire x1="-2.05" y1="-1.55" x2="-1" y2="-1.65" width="0.1524" layer="21"/>
+<wire x1="-1" y1="-1.65" x2="0" y2="-1.7" width="0.1524" layer="21"/>
+<pad name="C" x="-8.89" y="0" drill="0.9144" shape="long"/>
+<pad name="A" x="8.89" y="0" drill="0.9144" shape="long"/>
+<text x="-2.286" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-3.302" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="5.588" y1="-0.381" x2="5.969" y2="0.381" layer="21"/>
+<rectangle x1="-5.969" y1="-0.381" x2="-5.588" y2="0.381" layer="21"/>
+<rectangle x1="5.969" y1="-0.3302" x2="7.8232" y2="0.3302" layer="21"/>
+<rectangle x1="-7.8232" y1="-0.3302" x2="-5.969" y2="0.3302" layer="21"/>
+</package>
+<package name="SOD61D" urn="urn:adsk.eagle:footprint:43144/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, vertical, grid 15.24 mm</description>
+<wire x1="7.62" y1="0" x2="6.604" y2="0" width="0.6604" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.604" y2="0" width="0.6604" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.635" x2="-5.207" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.635" x2="-4.826" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="0.381" x2="-5.207" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="-0.381" x2="-4.826" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="0.635" x2="5.207" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="0.381" x2="5.207" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-0.635" x2="5.207" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-0.635" x2="4.826" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-0.381" x2="5.08" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-0.508" x2="5.08" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-0.508" x2="4.826" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="0.381" x2="5.08" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="0.508" x2="5.08" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="0.508" x2="4.826" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="0.381" x2="-5.08" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.508" x2="-5.08" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.508" x2="-4.826" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="-0.381" x2="-5.08" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-0.508" x2="-5.08" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-0.508" x2="-4.826" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0.381" x2="4.826" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="0.381" x2="4.826" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-0.381" x2="4.826" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-0.381" x2="4.826" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.381" x2="-4.826" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="-0.381" x2="-4.826" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.381" x2="-4.826" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.381" x2="-4.826" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="0.635" x2="4.8254" y2="0.6353" width="0.1524" layer="21" curve="-49.511667"/>
+<wire x1="-4.8254" y1="-0.6353" x2="4.826" y2="-0.635" width="0.1524" layer="21" curve="49.511667"/>
+<pad name="C" x="-7.62" y="0" drill="0.9144" shape="long"/>
+<pad name="A" x="7.62" y="0" drill="0.9144" shape="long"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-3.302" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="4.826" y1="-0.381" x2="5.207" y2="0.381" layer="21"/>
+<rectangle x1="-5.207" y1="-0.381" x2="-4.826" y2="0.381" layer="21"/>
+<rectangle x1="5.207" y1="-0.3302" x2="6.5278" y2="0.3302" layer="21"/>
+<rectangle x1="-6.5278" y1="-0.3302" x2="-5.207" y2="0.3302" layer="21"/>
+</package>
+<package name="SOD61E" urn="urn:adsk.eagle:footprint:43145/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.5 mm, vertical, grid 20.32 mm</description>
+<wire x1="10.16" y1="0" x2="9.144" y2="0" width="0.6604" layer="51"/>
+<wire x1="-10.16" y1="0" x2="-9.144" y2="0" width="0.6604" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="0.635" x2="-6.731" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="0.635" x2="-6.35" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0.381" x2="-6.731" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="-0.381" x2="-6.35" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="0.635" x2="6.731" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="0.381" x2="6.731" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-0.635" x2="6.731" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-0.635" x2="6.35" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="-0.381" x2="6.604" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-0.508" x2="6.604" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-0.508" x2="6.35" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="6.731" y1="0.381" x2="6.604" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="0.508" x2="6.604" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="0.508" x2="6.35" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="0.381" x2="-6.604" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="0.508" x2="-6.604" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="0.508" x2="-6.35" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-6.731" y1="-0.381" x2="-6.604" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="-0.508" x2="-6.604" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="-0.508" x2="-6.35" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="6.604" y1="0.381" x2="6.35" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="0.381" x2="6.35" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="6.604" y1="-0.381" x2="6.35" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="6.35" y1="-0.381" x2="6.35" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-6.604" y1="-0.381" x2="-6.35" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="-0.381" x2="-6.35" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-6.604" y1="0.381" x2="-6.35" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="0.381" x2="-6.35" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-6.35" y1="0.635" x2="6.3161" y2="0.6464" width="0.1524" layer="21" curve="-37.137105"/>
+<wire x1="-6.3161" y1="-0.6464" x2="6.35" y2="-0.635" width="0.1524" layer="21" curve="37.137105"/>
+<pad name="C" x="-10.16" y="0" drill="0.9144" shape="long"/>
+<pad name="A" x="10.16" y="0" drill="0.9144" shape="long"/>
+<text x="-3.048" y="2.159" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.048" y="-3.302" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="6.35" y1="-0.381" x2="6.731" y2="0.381" layer="21"/>
+<rectangle x1="-6.731" y1="-0.381" x2="-6.35" y2="0.381" layer="21"/>
+<rectangle x1="6.731" y1="-0.3302" x2="9.0678" y2="0.3302" layer="21"/>
+<rectangle x1="-9.0678" y1="-0.3302" x2="-6.731" y2="0.3302" layer="21"/>
+</package>
+<package name="DO27-15" urn="urn:adsk.eagle:footprint:43095/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 5 mm, horizontal, grid 15.24 mm</description>
+<wire x1="-1.27" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.5842" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.143" y2="0.5842" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="0.5842" x2="1.143" y2="-0.5842" width="0.1524" layer="21"/>
+<wire x1="1.143" y1="-0.5842" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="2.286" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.5842" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-2.54" x2="-5.08" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="2.54" x2="5.08" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="2.54" x2="5.08" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-2.54" x2="-5.08" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0" x2="6.223" y2="0" width="1.27" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.223" y2="0" width="1.27" layer="51"/>
+<pad name="C" x="-7.62" y="0" drill="1.4986" shape="long"/>
+<pad name="A" x="7.62" y="0" drill="1.4986" shape="long"/>
+<text x="-5.08" y="2.921" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-2.159" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-4.191" y1="-2.54" x2="-3.429" y2="2.54" layer="21"/>
+<rectangle x1="-5.969" y1="-0.635" x2="-5.08" y2="0.635" layer="21"/>
+<rectangle x1="5.08" y1="-0.635" x2="5.969" y2="0.635" layer="21"/>
+</package>
+<package name="SOD81" urn="urn:adsk.eagle:footprint:43125/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 2.3 mm, vertical, grid 10.16 mm</description>
+<wire x1="-1.905" y1="1.143" x2="1.905" y2="1.143" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0" x2="4.064" y2="0" width="0.762" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.064" y2="0" width="0.762" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.635" x2="-2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.635" x2="-2.159" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.381" x2="-2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.381" x2="-2.159" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.635" x2="-2.159" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.635" x2="2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.381" x2="2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.159" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.381" x2="2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.508" x2="2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.508" x2="2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.381" x2="2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.508" x2="2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.508" x2="2.159" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.381" x2="-2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.508" x2="-2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.508" x2="-2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.381" x2="-2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.508" x2="-2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.508" x2="-2.159" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="0.381" x2="2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.381" x2="2.159" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-0.381" x2="2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.381" x2="2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="-0.381" x2="-2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.381" x2="-2.159" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="0.381" x2="-2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.381" x2="-2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="-1.143" x2="2.159" y2="-0.889" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.159" y1="0.889" x2="-1.905" y2="1.143" width="0.1524" layer="21" curve="-90"/>
+<wire x1="1.905" y1="1.143" x2="2.159" y2="0.889" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.159" y1="-0.889" x2="-1.905" y2="-1.143" width="0.1524" layer="21" curve="90"/>
+<wire x1="-1.905" y1="-1.143" x2="1.905" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.159" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.635" x2="2.159" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.635" x2="-2.159" y2="0.889" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="1.1176" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.1176" shape="long"/>
+<text x="-2.032" y="1.397" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.032" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-1.143" x2="-1.143" y2="1.143" layer="21"/>
+<rectangle x1="-3.937" y1="-0.381" x2="-2.159" y2="0.381" layer="21"/>
+<rectangle x1="2.159" y1="-0.381" x2="3.937" y2="0.381" layer="21"/>
+</package>
+<package name="SOD84" urn="urn:adsk.eagle:footprint:43139/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3.3 mm, vertical, grid 10.16 mm</description>
+<wire x1="-1.905" y1="1.651" x2="1.905" y2="1.651" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0" x2="4.064" y2="0" width="0.762" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-4.064" y2="0" width="0.762" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.635" x2="-2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.635" x2="-2.159" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.381" x2="-2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.381" x2="-2.159" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.635" x2="-2.159" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.635" x2="2.54" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.381" x2="2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.54" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.159" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.381" x2="2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.508" x2="2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.508" x2="2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.381" x2="2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.508" x2="2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.508" x2="2.159" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.381" x2="-2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.508" x2="-2.413" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.508" x2="-2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.381" x2="-2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.508" x2="-2.413" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.508" x2="-2.159" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="0.381" x2="2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.381" x2="2.159" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="-0.381" x2="2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.381" x2="2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="-0.381" x2="-2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="-0.381" x2="-2.159" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="0.381" x2="-2.159" y2="0.381" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.381" x2="-2.159" y2="-0.381" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="-1.651" x2="2.159" y2="-1.397" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.159" y1="1.397" x2="-1.905" y2="1.651" width="0.1524" layer="21" curve="-90"/>
+<wire x1="1.905" y1="1.651" x2="2.159" y2="1.397" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.159" y1="-1.397" x2="-1.905" y2="-1.651" width="0.1524" layer="21" curve="90"/>
+<wire x1="-1.905" y1="-1.651" x2="1.905" y2="-1.651" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-0.635" x2="2.159" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="0.635" x2="2.159" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="-2.159" y1="0.635" x2="-2.159" y2="1.397" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="1.1176" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.1176" shape="long"/>
+<text x="-2.032" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.032" y="-3.302" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.937" y1="-0.381" x2="-2.159" y2="0.381" layer="21"/>
+<rectangle x1="2.159" y1="-0.381" x2="3.937" y2="0.381" layer="21"/>
+<rectangle x1="-1.651" y1="-1.651" x2="-1.143" y2="1.651" layer="21"/>
+</package>
+<package name="F126-10" urn="urn:adsk.eagle:footprint:43161/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 3 mm, horizontal, grid 10.16 mm</description>
+<wire x1="-3.175" y1="-1.524" x2="3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="1.524" x2="-3.175" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.524" x2="3.175" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.524" x2="-3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0" x2="3.81" y2="0" width="0.8128" layer="51"/>
+<wire x1="-5.08" y1="0" x2="-3.81" y2="0" width="0.8128" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<pad name="C" x="-5.08" y="0" drill="1.016" shape="long"/>
+<pad name="A" x="5.08" y="0" drill="1.016" shape="long"/>
+<text x="-3.175" y="1.778" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-3.048" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.54" y1="-1.524" x2="-1.778" y2="1.524" layer="21"/>
+<rectangle x1="3.175" y1="-0.4064" x2="3.7338" y2="0.4064" layer="21"/>
+<rectangle x1="-3.7338" y1="-0.4064" x2="-3.175" y2="0.4064" layer="21"/>
+</package>
+<package name="DO220S" urn="urn:adsk.eagle:footprint:43133/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+2-lead molded, vertical</description>
+<wire x1="5.08" y1="-1.143" x2="4.953" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-4.318" x2="4.953" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-4.318" x2="-4.699" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="-4.064" x2="-4.699" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="-4.064" x2="-5.08" y2="-1.143" width="0.1524" layer="21"/>
+<circle x="-4.4958" y="-3.7084" radius="0.254" width="0" layer="21"/>
+<pad name="C" x="-2.54" y="-2.54" drill="1.016" shape="long" rot="R90"/>
+<pad name="A" x="2.54" y="-2.54" drill="1.016" shape="long" rot="R90"/>
+<text x="-4.572" y="-6.0452" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-4.572" y="-7.62" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-5.334" y1="-0.762" x2="5.334" y2="0" layer="21"/>
+<rectangle x1="-5.334" y1="-1.27" x2="-3.429" y2="-0.762" layer="21"/>
+<rectangle x1="-3.429" y1="-1.27" x2="-1.651" y2="-0.762" layer="51"/>
+<rectangle x1="3.429" y1="-1.27" x2="5.334" y2="-0.762" layer="21"/>
+<rectangle x1="1.651" y1="-1.27" x2="3.429" y2="-0.762" layer="51"/>
+<rectangle x1="-1.651" y1="-1.27" x2="1.651" y2="-0.762" layer="21"/>
+</package>
+<package name="TO220AC" urn="urn:adsk.eagle:footprint:43128/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+2-lead molded, horizontal</description>
+<wire x1="-5.207" y1="-1.27" x2="5.207" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="14.605" x2="-5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-1.27" x2="5.207" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="11.176" x2="4.318" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="11.176" x2="4.318" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="12.7" x2="5.207" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="12.7" x2="5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="-1.27" x2="-5.207" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="11.176" x2="-4.318" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="-4.318" y1="11.176" x2="-4.318" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="-4.318" y1="12.7" x2="-5.207" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="12.7" x2="-5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="-4.572" y1="-0.635" x2="4.572" y2="-0.635" width="0.0508" layer="21"/>
+<wire x1="4.572" y1="7.62" x2="4.572" y2="-0.635" width="0.0508" layer="21"/>
+<wire x1="4.572" y1="7.62" x2="-4.572" y2="7.62" width="0.0508" layer="21"/>
+<wire x1="-4.572" y1="-0.635" x2="-4.572" y2="7.62" width="0.0508" layer="21"/>
+<circle x="0" y="11.176" radius="1.8034" width="0.1524" layer="21"/>
+<circle x="0" y="11.176" radius="2.921" width="0" layer="42"/>
+<circle x="0" y="11.176" radius="2.921" width="0" layer="43"/>
+<pad name="C" x="-2.54" y="-6.35" drill="1.1176" shape="long" rot="R90"/>
+<pad name="A" x="2.54" y="-6.35" drill="1.1176" shape="long" rot="R90"/>
+<text x="-5.461" y="-1.27" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-3.937" y="2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-4.445" y="7.874" size="0.9906" layer="21" ratio="10">A17,5mm</text>
+<rectangle x1="2.159" y1="-4.445" x2="2.921" y2="-3.81" layer="21"/>
+<rectangle x1="-2.921" y1="-4.445" x2="-2.159" y2="-3.81" layer="21"/>
+<rectangle x1="-3.175" y1="-3.81" x2="-1.905" y2="-1.27" layer="21"/>
+<rectangle x1="1.905" y1="-3.81" x2="3.175" y2="-1.27" layer="21"/>
+<rectangle x1="2.159" y1="-6.35" x2="2.921" y2="-4.445" layer="51"/>
+<rectangle x1="-2.921" y1="-6.35" x2="-2.159" y2="-4.445" layer="51"/>
+<hole x="0" y="11.176" drill="3.302"/>
+</package>
+<package name="TO220ACS" urn="urn:adsk.eagle:footprint:43137/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+2-lead molded, vertical</description>
+<wire x1="5.08" y1="-1.143" x2="4.953" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-4.318" x2="4.953" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-4.318" x2="-4.699" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="-4.064" x2="-4.699" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-4.953" y1="-4.064" x2="-5.08" y2="-1.143" width="0.1524" layer="21"/>
+<circle x="-4.4958" y="-3.7084" radius="0.254" width="0" layer="21"/>
+<pad name="C" x="-2.54" y="-2.54" drill="1.016" shape="long" rot="R90"/>
+<pad name="A" x="2.54" y="-2.54" drill="1.016" shape="long" rot="R90"/>
+<text x="-5.08" y="-6.0452" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-7.62" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-5.334" y1="-0.762" x2="5.334" y2="0" layer="21"/>
+<rectangle x1="-5.334" y1="-1.27" x2="-3.429" y2="-0.762" layer="21"/>
+<rectangle x1="-3.429" y1="-1.27" x2="-1.651" y2="-0.762" layer="51"/>
+<rectangle x1="3.429" y1="-1.27" x2="5.334" y2="-0.762" layer="21"/>
+<rectangle x1="1.651" y1="-1.27" x2="3.429" y2="-0.762" layer="51"/>
+<rectangle x1="-1.651" y1="-1.27" x2="1.651" y2="-0.762" layer="21"/>
+</package>
+<package name="G4-12" urn="urn:adsk.eagle:footprint:43131/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 7.62 mm, horizontal, grid 12.7 mm</description>
+<wire x1="3.556" y1="1.27" x2="3.556" y2="-1.27" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-3.556" y1="-1.27" x2="-3.556" y2="1.27" width="0.1524" layer="21" curve="-180"/>
+<wire x1="6.35" y1="0" x2="5.08" y2="0" width="1.27" layer="51"/>
+<wire x1="-6.35" y1="0" x2="-5.08" y2="0" width="1.27" layer="51"/>
+<wire x1="3.937" y1="0.889" x2="4.318" y2="0.508" width="0.6096" layer="21"/>
+<wire x1="4.318" y1="-0.508" x2="3.937" y2="-0.889" width="0.6096" layer="21"/>
+<wire x1="-4.318" y1="0.508" x2="-3.937" y2="0.889" width="0.6096" layer="21"/>
+<wire x1="-4.318" y1="-0.508" x2="-3.937" y2="-0.889" width="0.6096" layer="21"/>
+<wire x1="-2.667" y1="-2.286" x2="-2.667" y2="2.286" width="0.6096" layer="21"/>
+<wire x1="-3.175" y1="1.524" x2="-3.175" y2="-1.524" width="0.6096" layer="21"/>
+<wire x1="-3.556" y1="1.016" x2="-3.556" y2="-1.016" width="0.6096" layer="21"/>
+<wire x1="-3.175" y1="-1.524" x2="-2.921" y2="-2.032" width="0.6096" layer="21"/>
+<wire x1="-2.921" y1="2.032" x2="-3.175" y2="1.524" width="0.6096" layer="21"/>
+<wire x1="-0.762" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="0.508" x2="0.635" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-0.508" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="0.635" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0.508" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.381" y2="-0.508" width="0.1524" layer="21"/>
+<circle x="0" y="0" radius="3.81" width="0.1524" layer="21"/>
+<pad name="C" x="-6.35" y="0" drill="1.6002" shape="long"/>
+<pad name="A" x="6.35" y="0" drill="1.6002" shape="long"/>
+<text x="-3.429" y="4.064" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.905" y="-2.54" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="3.81" y1="-0.635" x2="4.953" y2="0.635" layer="21"/>
+<rectangle x1="-4.953" y1="-0.635" x2="-3.81" y2="0.635" layer="21"/>
+</package>
+<package name="SOD83-12" urn="urn:adsk.eagle:footprint:43146/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 4.8 mm, vertical, grid 12.7 mm</description>
+<wire x1="6.35" y1="0" x2="4.826" y2="0" width="1.3716" layer="51"/>
+<wire x1="-6.35" y1="0" x2="-4.826" y2="0" width="1.3716" layer="51"/>
+<wire x1="-1.143" y1="0" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="0.635" x2="0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.508" y1="-0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="1.016" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-3.81" y1="1.397" x2="-3.81" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="-1.397" x2="3.81" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="-3.81" y1="1.397" x2="-2.667" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="1.397" x2="2.667" y2="1.397" width="0.1524" layer="21"/>
+<wire x1="-3.81" y1="-1.397" x2="-2.667" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="2.667" y1="-1.397" x2="3.81" y2="-1.397" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.635" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-2.667" y1="1.397" x2="2.6841" y2="1.3841" width="0.1524" layer="21" curve="-74.015899"/>
+<wire x1="-2.6841" y1="-1.3841" x2="2.667" y2="-1.397" width="0.1524" layer="21" curve="74.015899"/>
+<pad name="C" x="-6.35" y="0" drill="1.6002" shape="long"/>
+<pad name="A" x="6.35" y="0" drill="1.6002" shape="long"/>
+<text x="-2.54" y="2.54" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-3.937" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.175" y1="-1.397" x2="-2.667" y2="1.397" layer="21"/>
+<rectangle x1="3.81" y1="-0.6604" x2="4.6228" y2="0.6604" layer="21"/>
+<rectangle x1="-4.6228" y1="-0.6604" x2="-3.81" y2="0.6604" layer="21"/>
+</package>
+<package name="SMB" urn="urn:adsk.eagle:footprint:43181/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;</description>
+<wire x1="-2.2606" y1="1.905" x2="2.2606" y2="1.905" width="0.1016" layer="21"/>
+<wire x1="-2.2606" y1="-1.905" x2="2.2606" y2="-1.905" width="0.1016" layer="21"/>
+<wire x1="-2.2606" y1="-1.905" x2="-2.2606" y2="1.905" width="0.1016" layer="51"/>
+<wire x1="2.2606" y1="-1.905" x2="2.2606" y2="1.905" width="0.1016" layer="51"/>
+<wire x1="0.193" y1="1" x2="-0.83" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.83" y1="0" x2="0.193" y2="-1" width="0.2032" layer="21"/>
+<wire x1="0.193" y1="-1" x2="0.193" y2="1" width="0.2032" layer="21"/>
+<smd name="C" x="-2.2" y="0" dx="2.4" dy="2.4" layer="1"/>
+<smd name="A" x="2.2" y="0" dx="2.4" dy="2.4" layer="1"/>
+<text x="-2.159" y="2.159" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.159" y="-3.429" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.794" y1="-1.0922" x2="-2.2606" y2="1.0922" layer="51"/>
+<rectangle x1="2.2606" y1="-1.0922" x2="2.794" y2="1.0922" layer="51"/>
+<rectangle x1="-1.35" y1="-1.9" x2="-0.8" y2="1.9" layer="51"/>
+</package>
+<package name="P6-15" urn="urn:adsk.eagle:footprint:43097/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 9 mm, horizontal, grid 15.24 mm</description>
+<wire x1="-4.699" y1="-4.572" x2="-4.699" y2="4.572" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="4.572" x2="4.699" y2="-4.572" width="0.1524" layer="21"/>
+<wire x1="-4.699" y1="4.572" x2="4.699" y2="4.572" width="0.1524" layer="21"/>
+<wire x1="4.699" y1="-4.572" x2="-4.699" y2="-4.572" width="0.1524" layer="21"/>
+<wire x1="-1.143" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="2.54" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0" x2="6.223" y2="0" width="1.27" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.223" y2="0" width="1.27" layer="51"/>
+<pad name="C" x="-7.62" y="0" drill="1.6002" shape="long"/>
+<pad name="A" x="7.62" y="0" drill="1.6002" shape="long"/>
+<text x="-4.6736" y="4.8514" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.3622" y="-3.302" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.429" y1="-4.572" x2="-2.921" y2="4.572" layer="21"/>
+<rectangle x1="4.699" y1="-0.635" x2="5.969" y2="0.635" layer="21"/>
+<rectangle x1="-5.969" y1="-0.635" x2="-4.699" y2="0.635" layer="21"/>
+</package>
+<package name="C2673" urn="urn:adsk.eagle:footprint:43156/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+diameter 5.2 mm, horizontal, grid 15.24 mm</description>
+<wire x1="4.826" y1="-2.667" x2="-4.826" y2="-2.667" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-2.667" x2="4.826" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="2.667" x2="4.826" y2="2.667" width="0.1524" layer="21"/>
+<wire x1="-4.826" y1="2.667" x2="-4.826" y2="-2.667" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0" x2="6.096" y2="0" width="1.27" layer="51"/>
+<wire x1="-7.62" y1="0" x2="-6.096" y2="0" width="1.27" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<pad name="A" x="7.62" y="0" drill="1.4986" shape="long"/>
+<pad name="C" x="-7.62" y="0" drill="1.4986" shape="long"/>
+<text x="-4.699" y="3.048" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.159" y="-2.159" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-3.937" y1="-2.667" x2="-2.54" y2="2.667" layer="21"/>
+<rectangle x1="4.826" y1="-0.635" x2="5.969" y2="0.635" layer="21"/>
+<rectangle x1="-5.969" y1="-0.635" x2="-4.826" y2="0.635" layer="21"/>
+</package>
+<package name="C221B1A" urn="urn:adsk.eagle:footprint:43158/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;&lt;p&gt;
+2-lead molded, horizontal</description>
+<wire x1="-5.207" y1="-1.27" x2="5.207" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="14.478" x2="-5.207" y2="14.478" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="8.001" x2="-5.207" y2="8.001" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="8.001" x2="5.207" y2="14.478" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="8.001" x2="-5.207" y2="14.478" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-1.27" x2="5.207" y2="8.001" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="-1.27" x2="-5.207" y2="8.001" width="0.1524" layer="21"/>
+<wire x1="4.953" y1="6.731" x2="4.953" y2="-1.016" width="0.0508" layer="21"/>
+<wire x1="4.953" y1="6.731" x2="-4.953" y2="6.731" width="0.0508" layer="21"/>
+<wire x1="4.953" y1="-1.016" x2="-4.953" y2="-1.016" width="0.0508" layer="21"/>
+<wire x1="-4.953" y1="6.731" x2="-4.953" y2="-1.016" width="0.0508" layer="21"/>
+<wire x1="-2.794" y1="-4.191" x2="-3.175" y2="-3.81" width="0.508" layer="21"/>
+<wire x1="3.175" y1="-3.81" x2="2.794" y2="-4.191" width="0.508" layer="21"/>
+<circle x="0" y="11.176" radius="1.8034" width="0.1524" layer="21"/>
+<circle x="0" y="11.176" radius="2.921" width="0" layer="42"/>
+<circle x="0" y="11.176" radius="2.921" width="0" layer="43"/>
+<pad name="C" x="-2.54" y="-6.35" drill="1.1176" shape="long" rot="R90"/>
+<pad name="A" x="2.54" y="-6.35" drill="1.1176" shape="long" rot="R90"/>
+<text x="-2.54" y="4.191" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.81" y="1.651" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-4.826" y="8.382" size="0.9906" layer="21" ratio="10">A17,5mm</text>
+<rectangle x1="2.159" y1="-4.445" x2="2.921" y2="-3.81" layer="21"/>
+<rectangle x1="-2.921" y1="-4.445" x2="-2.159" y2="-3.81" layer="21"/>
+<rectangle x1="-3.429" y1="-3.81" x2="-2.159" y2="-1.27" layer="21"/>
+<rectangle x1="2.159" y1="-3.81" x2="3.429" y2="-1.27" layer="21"/>
+<rectangle x1="2.159" y1="-6.35" x2="2.921" y2="-4.445" layer="51"/>
+<rectangle x1="-2.921" y1="-6.35" x2="-2.159" y2="-4.445" layer="51"/>
+<hole x="0" y="11.176" drill="3.302"/>
+</package>
+<package name="SOD80C" urn="urn:adsk.eagle:footprint:43180/1" library_version="2">
+<description>&lt;B&gt;DIODE&lt;/B&gt;</description>
+<wire x1="1.3208" y1="0.7874" x2="-1.3208" y2="0.7874" width="0.1524" layer="51"/>
+<wire x1="1.3208" y1="-0.7874" x2="-1.3208" y2="-0.7874" width="0.1524" layer="51"/>
+<wire x1="0.627" y1="0.6" x2="-0.373" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.373" y1="0" x2="0.627" y2="-0.6" width="0.2032" layer="21"/>
+<wire x1="0.627" y1="-0.6" x2="0.627" y2="0.6" width="0.2032" layer="21"/>
+<smd name="C" x="-1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<smd name="A" x="1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<text x="-1.524" y="1.143" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.524" y="-2.413" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.8542" y1="-0.8636" x2="-1.2954" y2="0.8636" layer="51"/>
+<rectangle x1="1.2954" y1="-0.8636" x2="1.8542" y2="0.8636" layer="51"/>
+<rectangle x1="-0.8636" y1="-0.7874" x2="-0.254" y2="0.7874" layer="21"/>
+</package>
+<package name="D-10" urn="urn:adsk.eagle:footprint:43192/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="3.175" y1="1.524" x2="-3.175" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="-1.524" x2="3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-3.937" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.524" x2="-3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="3.937" y1="0" x2="3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.524" x2="3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="0" x2="3.175" y2="1.524" width="0.1524" layer="21"/>
+<pad name="A" x="5.08" y="0" drill="0.8128" shape="long"/>
+<pad name="C" x="-5.08" y="0" drill="0.8128" shape="long"/>
+<text x="-3.175" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-3.175" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.286" y1="-1.524" x2="-1.524" y2="1.524" layer="21"/>
+</package>
+<package name="D-12.5" urn="urn:adsk.eagle:footprint:43193/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="3.175" y1="1.524" x2="-3.175" y2="1.524" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="-1.524" x2="3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-5.207" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.524" x2="-3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="0" x2="3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.524" x2="3.175" y2="0" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="0" x2="-3.175" y2="-1.524" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="0" x2="3.175" y2="1.524" width="0.1524" layer="21"/>
+<pad name="A" x="6.35" y="0" drill="0.8128" shape="long"/>
+<pad name="C" x="-6.35" y="0" drill="0.8128" shape="long"/>
+<text x="-3.175" y="1.905" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.175" y="-3.175" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.286" y1="-1.524" x2="-1.524" y2="1.524" layer="21"/>
+<rectangle x1="-2.286" y1="-1.524" x2="-1.524" y2="1.524" layer="21"/>
+</package>
+<package name="D-2.5" urn="urn:adsk.eagle:footprint:43194/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="0.508" y1="0.762" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="-0.762" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0.762" x2="-0.508" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.508" y1="0" x2="-1.27" y2="0" width="0.1524" layer="51"/>
+<wire x1="-0.508" y1="0" x2="-0.508" y2="-0.762" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0" x2="0.508" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.508" y1="-0.762" x2="0.508" y2="0.762" width="0.1524" layer="21"/>
+<pad name="A" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="C" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-1.651" y="1.143" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.651" y="-2.413" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="D-5" urn="urn:adsk.eagle:footprint:43195/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="1.397" y1="0.889" x2="-1.397" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-1.397" y1="-0.889" x2="1.397" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="-1.397" y1="0" x2="-1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="-1.397" y1="0.889" x2="-1.397" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.524" y1="0" x2="1.397" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.397" y1="-0.889" x2="1.397" y2="0" width="0.1524" layer="21"/>
+<wire x1="-1.397" y1="0" x2="-1.397" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="1.397" y1="0" x2="1.397" y2="0.889" width="0.1524" layer="21"/>
+<pad name="A" x="2.54" y="0" drill="0.8128" shape="octagon"/>
+<pad name="C" x="-2.54" y="0" drill="0.8128" shape="octagon"/>
+<text x="-1.905" y="1.27" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.905" y="-2.54" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.016" y1="-0.889" x2="-0.508" y2="0.889" layer="21"/>
+</package>
+<package name="D-7.5" urn="urn:adsk.eagle:footprint:43196/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="1.905" y1="0.889" x2="-1.905" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="-0.889" x2="1.905" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="0" x2="-2.794" y2="0" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="0.889" x2="-1.905" y2="0" width="0.1524" layer="21"/>
+<wire x1="2.794" y1="0" x2="1.905" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="-0.889" x2="1.905" y2="0" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="0" x2="-1.905" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="0" x2="1.905" y2="0.889" width="0.1524" layer="21"/>
+<pad name="A" x="3.81" y="0" drill="0.8128" shape="long"/>
+<pad name="C" x="-3.81" y="0" drill="0.8128" shape="long"/>
+<text x="-1.905" y="1.27" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.905" y="-2.54" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.27" y1="-0.889" x2="-0.762" y2="0.889" layer="21"/>
+</package>
+<package name="SOD106-R" urn="urn:adsk.eagle:footprint:43197/1" library_version="2">
+<description>&lt;b&gt;SOD106 Reflow soldering&lt;/b&gt; Philips SC01_Mounting_1996.pdf</description>
+<wire x1="1.8208" y1="0.7874" x2="-1.8208" y2="0.7874" width="0.1524" layer="51"/>
+<wire x1="1.8208" y1="-0.7874" x2="-1.8208" y2="-0.7874" width="0.1524" layer="51"/>
+<wire x1="0.127" y1="0.6" x2="-0.873" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.873" y1="0" x2="0.127" y2="-0.6" width="0.2032" layer="21"/>
+<wire x1="0.127" y1="-0.6" x2="0.127" y2="0.6" width="0.2032" layer="21"/>
+<smd name="C" x="-2.25" y="0" dx="1.6" dy="2.1" layer="1"/>
+<smd name="A" x="2.25" y="0" dx="1.6" dy="2.1" layer="1"/>
+<text x="-1.524" y="1.293" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.524" y="-2.563" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.3542" y1="-0.8636" x2="-1.7954" y2="0.8636" layer="51"/>
+<rectangle x1="1.7954" y1="-0.8636" x2="2.3542" y2="0.8636" layer="51"/>
+<rectangle x1="-1.3636" y1="-0.7874" x2="-0.754" y2="0.7874" layer="21"/>
+</package>
+<package name="SMC" urn="urn:adsk.eagle:footprint:43198/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="-3.5606" y1="3.105" x2="3.5606" y2="3.105" width="0.1016" layer="21"/>
+<wire x1="-3.5606" y1="-3.105" x2="3.5606" y2="-3.105" width="0.1016" layer="21"/>
+<wire x1="-3.5606" y1="-3.105" x2="-3.5606" y2="3.105" width="0.1016" layer="51"/>
+<wire x1="3.5606" y1="-3.105" x2="3.5606" y2="3.105" width="0.1016" layer="51"/>
+<wire x1="0.543" y1="1" x2="-0.83" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.83" y1="0" x2="0.543" y2="-1" width="0.2032" layer="21"/>
+<wire x1="0.543" y1="-1" x2="0.543" y2="1" width="0.2032" layer="21"/>
+<smd name="C" x="-3.7" y="0" dx="2.8" dy="3.8" layer="1"/>
+<smd name="A" x="3.7" y="0" dx="2.8" dy="3.8" layer="1"/>
+<text x="-3.459" y="3.359" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.459" y="-4.629" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-4.094" y1="-1.0922" x2="-3.5606" y2="1.0922" layer="51"/>
+<rectangle x1="3.5606" y1="-1.0922" x2="4.094" y2="1.0922" layer="51"/>
+<rectangle x1="-2.1" y1="-3.1" x2="-0.85" y2="3.1" layer="21"/>
+</package>
+<package name="SOD106-W" urn="urn:adsk.eagle:footprint:43199/1" library_version="2">
+<description>&lt;b&gt;SOD106 Wave soldering&lt;/b&gt; Philips SC01_Mounting_1996.pdf</description>
+<wire x1="1.8208" y1="0.7874" x2="-1.8208" y2="0.7874" width="0.1524" layer="51"/>
+<wire x1="1.8208" y1="-0.7874" x2="-1.8208" y2="-0.7874" width="0.1524" layer="51"/>
+<wire x1="0.127" y1="0.6" x2="-0.873" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.873" y1="0" x2="0.127" y2="-0.6" width="0.2032" layer="21"/>
+<wire x1="0.127" y1="-0.6" x2="0.127" y2="0.6" width="0.2032" layer="21"/>
+<smd name="C" x="-2.85" y="0" dx="2.3" dy="3.2" layer="1"/>
+<smd name="A" x="2.85" y="0" dx="2.3" dy="3.2" layer="1"/>
+<text x="-3.374" y="1.793" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.324" y="-3.163" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.3542" y1="-0.8636" x2="-1.7954" y2="0.8636" layer="51"/>
+<rectangle x1="1.7954" y1="-0.8636" x2="2.3542" y2="0.8636" layer="51"/>
+<rectangle x1="-1.3636" y1="-0.7874" x2="-0.754" y2="0.7874" layer="21"/>
+</package>
+<package name="SOD106A-R" urn="urn:adsk.eagle:footprint:43200/1" library_version="2">
+<description>&lt;b&gt;SOD106A Reflow soldering&lt;/b&gt; Philips SC01_Mounting_1996.pdf</description>
+<wire x1="1.8208" y1="0.7874" x2="-1.8208" y2="0.7874" width="0.1524" layer="51"/>
+<wire x1="1.8208" y1="-0.7874" x2="-1.8208" y2="-0.7874" width="0.1524" layer="51"/>
+<wire x1="0.127" y1="0.6" x2="-0.873" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.873" y1="0" x2="0.127" y2="-0.6" width="0.2032" layer="21"/>
+<wire x1="0.127" y1="-0.6" x2="0.127" y2="0.6" width="0.2032" layer="21"/>
+<smd name="C" x="-2.2" y="0" dx="1.7" dy="2.1" layer="1"/>
+<smd name="A" x="2.2" y="0" dx="1.7" dy="2.1" layer="1"/>
+<text x="-2.374" y="1.293" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.374" y="-2.513" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.3542" y1="-0.8636" x2="-1.7954" y2="0.8636" layer="51"/>
+<rectangle x1="1.7954" y1="-0.8636" x2="2.3542" y2="0.8636" layer="51"/>
+<rectangle x1="-1.3636" y1="-0.7874" x2="-0.754" y2="0.7874" layer="51"/>
+</package>
+<package name="SOD110-W" urn="urn:adsk.eagle:footprint:43201/1" library_version="2">
+<description>&lt;b&gt;SOD110 Wave soldering&lt;/b&gt; Philips SC01_Mounting_1996.pdf</description>
+<wire x1="-1" y1="0.5" x2="1.05" y2="0.5" width="0.1016" layer="51"/>
+<wire x1="1.05" y1="0.5" x2="1.05" y2="-0.5" width="0.1016" layer="51"/>
+<wire x1="1.05" y1="-0.5" x2="-1" y2="-0.5" width="0.1016" layer="51"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1016" layer="51"/>
+<smd name="C" x="-1.15" y="0" dx="1" dy="1.2" layer="1"/>
+<smd name="A" x="1.15" y="0" dx="1" dy="1.2" layer="1"/>
+<text x="-1.524" y="1.143" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.524" y="-2.413" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.65" y1="-0.45" x2="-0.4" y2="0.45" layer="51"/>
+</package>
+<package name="SOD110-R" urn="urn:adsk.eagle:footprint:43202/1" library_version="2">
+<description>&lt;b&gt;SOD110 Reflow soldering&lt;/b&gt; Philips SC01_Mounting_1996.pdf</description>
+<wire x1="-1" y1="0.5" x2="1.05" y2="0.5" width="0.1016" layer="51"/>
+<wire x1="1.05" y1="0.5" x2="1.05" y2="-0.5" width="0.1016" layer="51"/>
+<wire x1="1.05" y1="-0.5" x2="-1" y2="-0.5" width="0.1016" layer="51"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1016" layer="51"/>
+<smd name="C" x="-0.95" y="0" dx="0.8" dy="1" layer="1"/>
+<smd name="A" x="0.95" y="0" dx="0.8" dy="1" layer="1"/>
+<text x="-1.524" y="1.143" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.524" y="-2.413" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.65" y1="-0.45" x2="-0.4" y2="0.45" layer="51"/>
+</package>
+<package name="SOD123" urn="urn:adsk.eagle:footprint:43203/1" library_version="2">
+<description>&lt;b&gt;Diode&lt;/b&gt;</description>
+<wire x1="-1.1" y1="0.7" x2="1.1" y2="0.7" width="0.254" layer="51"/>
+<wire x1="1.1" y1="0.7" x2="1.1" y2="-0.7" width="0.254" layer="51"/>
+<wire x1="1.1" y1="-0.7" x2="-1.1" y2="-0.7" width="0.254" layer="51"/>
+<wire x1="-1.1" y1="-0.7" x2="-1.1" y2="0.7" width="0.254" layer="51"/>
+<smd name="C" x="-1.9" y="0" dx="1.4" dy="1.4" layer="1"/>
+<smd name="A" x="1.9" y="0" dx="1.4" dy="1.4" layer="1"/>
+<text x="-1.1" y="1" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.1" y="-2.3" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.95" y1="-0.45" x2="-1.2" y2="0.4" layer="51"/>
+<rectangle x1="1.2" y1="-0.45" x2="1.95" y2="0.4" layer="51"/>
+<rectangle x1="-1.05" y1="-0.65" x2="-0.15" y2="0.7" layer="51"/>
+</package>
+<package name="SOD323-R" urn="urn:adsk.eagle:footprint:43204/1" library_version="2">
+<description>&lt;b&gt;SOD323 Reflow soldering&lt;/b&gt; Philips SC01_Mounting_1996.pdf</description>
+<wire x1="-1" y1="0.7" x2="1" y2="0.7" width="0.1524" layer="21"/>
+<wire x1="1" y1="0.7" x2="1" y2="-0.7" width="0.1524" layer="51"/>
+<wire x1="1" y1="-0.7" x2="-1" y2="-0.7" width="0.1524" layer="21"/>
+<wire x1="-1" y1="-0.7" x2="-1" y2="0.7" width="0.1524" layer="51"/>
+<wire x1="-0.5" y1="0" x2="0.1" y2="0.4" width="0.1524" layer="21"/>
+<wire x1="0.1" y1="0.4" x2="0.1" y2="-0.4" width="0.1524" layer="21"/>
+<wire x1="0.1" y1="-0.4" x2="-0.5" y2="0" width="0.1524" layer="21"/>
+<smd name="C" x="-1.1" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="A" x="1.1" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="-1.1" y="1" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.1" y="-2.3" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.7" y1="-0.7" x2="-0.5" y2="0.7" layer="51"/>
+</package>
+<package name="SOD323-W" urn="urn:adsk.eagle:footprint:43205/1" library_version="2">
+<description>&lt;b&gt;SOD323 Wave soldering&lt;/b&gt; Philips SC01_Mounting_1996.pdf</description>
+<wire x1="-1" y1="0.7" x2="1" y2="0.7" width="0.1524" layer="51"/>
+<wire x1="1" y1="0.7" x2="1" y2="-0.7" width="0.1524" layer="51"/>
+<wire x1="1" y1="-0.7" x2="-1" y2="-0.7" width="0.1524" layer="51"/>
+<wire x1="-1" y1="-0.7" x2="-1" y2="0.7" width="0.1524" layer="51"/>
+<wire x1="-0.5" y1="0" x2="0.1" y2="0.4" width="0.1524" layer="21"/>
+<wire x1="0.1" y1="0.4" x2="0.1" y2="-0.4" width="0.1524" layer="21"/>
+<wire x1="0.1" y1="-0.4" x2="-0.5" y2="0" width="0.1524" layer="21"/>
+<smd name="C" x="-1.45" y="0" dx="1.5" dy="1.2" layer="1"/>
+<smd name="A" x="1.45" y="0" dx="1.5" dy="1.2" layer="1"/>
+<text x="-1.1" y="1" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.1" y="-2.3" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.7" y1="-0.7" x2="-0.5" y2="0.7" layer="51"/>
+</package>
+<package name="GF1" urn="urn:adsk.eagle:footprint:43206/1" library_version="2">
+<description>&lt;b&gt;GF1&lt;/b&gt;&lt;p&gt;
+General Semiconductor</description>
+<wire x1="-2.24" y1="1.32" x2="2.24" y2="1.32" width="0.254" layer="21"/>
+<wire x1="2.24" y1="1.32" x2="2.24" y2="-1.32" width="0.254" layer="21"/>
+<wire x1="2.24" y1="-1.32" x2="-2.24" y2="-1.32" width="0.254" layer="21"/>
+<wire x1="-2.24" y1="-1.32" x2="-2.24" y2="1.32" width="0.254" layer="21"/>
+<smd name="C" x="-2.12" y="0" dx="1.32" dy="1.68" layer="1"/>
+<smd name="A" x="1.87" y="0" dx="1.85" dy="1.68" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.86" y1="-0.84" x2="-2.32" y2="0.84" layer="51"/>
+<rectangle x1="2.34" y1="-0.84" x2="2.86" y2="0.84" layer="51"/>
+<rectangle x1="-1.9" y1="-1.05" x2="-1.25" y2="1.05" layer="51"/>
+<rectangle x1="-1.4" y1="-1.05" x2="-1.25" y2="1.05" layer="21"/>
+</package>
+<package name="MINIMELF" urn="urn:adsk.eagle:footprint:43207/1" library_version="2">
+<description>&lt;b&gt;Mini Melf Diode&lt;/b&gt;</description>
+<wire x1="1.3208" y1="0.7874" x2="-1.3208" y2="0.7874" width="0.1524" layer="51"/>
+<wire x1="1.3208" y1="-0.7874" x2="-1.3208" y2="-0.7874" width="0.1524" layer="51"/>
+<wire x1="0.5" y1="0.5" x2="-0.5" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.5" y1="0" x2="0.5" y2="-0.5" width="0.2032" layer="21"/>
+<wire x1="0.5" y1="-0.5" x2="0.5" y2="0.5" width="0.2032" layer="21"/>
+<smd name="C" x="-1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<smd name="A" x="1.7" y="0" dx="1.4" dy="1.8" layer="1"/>
+<text x="-1.651" y="1.143" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.651" y="-2.413" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.8542" y1="-0.8636" x2="-1.2954" y2="0.8636" layer="51"/>
+<rectangle x1="1.2954" y1="-0.8636" x2="1.8542" y2="0.8636" layer="51"/>
+<rectangle x1="-0.8636" y1="-0.7874" x2="-0.254" y2="0.7874" layer="21"/>
+</package>
+<package name="MELF-MLL41" urn="urn:adsk.eagle:footprint:43208/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;&lt;p&gt;
+Package DO-213AB = http://www.diotec.com/pdf/sm4001.pdf</description>
+<wire x1="2.0828" y1="1.1938" x2="-2.159" y2="1.1938" width="0.1524" layer="51"/>
+<wire x1="2.0828" y1="-1.1938" x2="-2.1336" y2="-1.1938" width="0.1524" layer="51"/>
+<wire x1="0.627" y1="1" x2="-0.746" y2="0" width="0.2032" layer="21"/>
+<wire x1="-0.746" y1="0" x2="0.627" y2="-1" width="0.2032" layer="21"/>
+<wire x1="0.627" y1="-1" x2="0.627" y2="1" width="0.2032" layer="21"/>
+<wire x1="1.1208" y1="1.1938" x2="-1.097" y2="1.1938" width="0.1524" layer="21"/>
+<wire x1="1.1208" y1="-1.1938" x2="-1.0716" y2="-1.1938" width="0.1524" layer="21"/>
+<smd name="C" x="-2.625" y="0" dx="2.5" dy="3" layer="1"/>
+<smd name="A" x="2.625" y="0" dx="2.5" dy="3" layer="1"/>
+<text x="-2.663" y="1.724" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.663" y="-2.994" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="2.0574" y1="-1.27" x2="2.5654" y2="1.27" layer="51"/>
+<rectangle x1="-2.6162" y1="-1.27" x2="-2.1082" y2="1.27" layer="51"/>
+<rectangle x1="-1.4478" y1="-1.1938" x2="-0.5588" y2="1.1938" layer="51"/>
+</package>
+<package name="MICROMELF-R" urn="urn:adsk.eagle:footprint:43209/1" library_version="2">
+<description>&lt;b&gt;Micro Melf Diode Reflow soldering&lt;/b&gt; VISHAY mcl4148.pdf</description>
+<wire x1="-0.65" y1="0.55" x2="0.65" y2="0.55" width="0.1524" layer="51"/>
+<wire x1="-0.65" y1="-0.55" x2="0.65" y2="-0.55" width="0.1524" layer="51"/>
+<smd name="C" x="-0.8" y="0" dx="0.8" dy="1.2" layer="1"/>
+<smd name="A" x="0.8" y="0" dx="0.8" dy="1.2" layer="1"/>
+<text x="-1.201" y="0.843" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.201" y="-2.063" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.95" y1="-0.65" x2="-0.65" y2="0.65" layer="51"/>
+<rectangle x1="0.65" y1="-0.65" x2="0.95" y2="0.65" layer="51"/>
+<rectangle x1="-0.5" y1="-0.55" x2="-0.2" y2="0.55" layer="51"/>
+</package>
+<package name="MICROMELF-W" urn="urn:adsk.eagle:footprint:43210/1" library_version="2">
+<description>&lt;b&gt;Micro Melf Diode Wave soldering&lt;/b&gt; VISHAY mcl4148.pdf</description>
+<wire x1="-0.65" y1="0.55" x2="0.65" y2="0.55" width="0.1524" layer="51"/>
+<wire x1="-0.65" y1="-0.55" x2="0.65" y2="-0.55" width="0.1524" layer="51"/>
+<smd name="C" x="-0.95" y="0" dx="0.9" dy="1.4" layer="1"/>
+<smd name="A" x="0.95" y="0" dx="0.9" dy="1.4" layer="1"/>
+<text x="-1.201" y="0.843" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.201" y="-2.063" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.95" y1="-0.65" x2="-0.65" y2="0.65" layer="51"/>
+<rectangle x1="0.65" y1="-0.65" x2="0.95" y2="0.65" layer="51"/>
+<rectangle x1="-0.5" y1="-0.5" x2="-0.2" y2="0.55" layer="51"/>
+</package>
+<package name="SC79_INFINEON" urn="urn:adsk.eagle:footprint:43211/1" library_version="2">
+<description>&lt;b&gt;Diode Package&lt;/b&gt; Reflow soldering&lt;p&gt;
+INFINEON, www.infineon.com/cmc_upload/0/000/010/257/eh_db_5b.pdf</description>
+<wire x1="-0.55" y1="0.35" x2="0.55" y2="0.35" width="0.1016" layer="21"/>
+<wire x1="0.55" y1="0.35" x2="0.55" y2="-0.35" width="0.1016" layer="51"/>
+<wire x1="0.55" y1="-0.35" x2="-0.55" y2="-0.35" width="0.1016" layer="21"/>
+<wire x1="-0.55" y1="-0.35" x2="-0.55" y2="0.35" width="0.1016" layer="51"/>
+<smd name="C" x="-0.675" y="0" dx="0.35" dy="0.35" layer="1"/>
+<smd name="A" x="0.675" y="0" dx="0.35" dy="0.35" layer="1"/>
+<text x="-0.8" y="0.6" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.8" y="-1.8" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.8" y1="-0.15" x2="-0.55" y2="0.15" layer="51"/>
+<rectangle x1="0.55" y1="-0.15" x2="0.8" y2="0.15" layer="51"/>
+<rectangle x1="-0.55" y1="-0.35" x2="0" y2="0.35" layer="51"/>
+</package>
+<package name="SCD80_INFINEON" urn="urn:adsk.eagle:footprint:43212/1" library_version="2">
+<description>&lt;b&gt;Diode Package&lt;/b&gt; Reflow soldering&lt;p&gt;
+INFINEON, www.infineon.com/cmc_upload/0/000/010/257/eh_db_5b.pdf</description>
+<wire x1="-0.6" y1="0.35" x2="-0.6" y2="-0.35" width="0.1016" layer="51"/>
+<wire x1="-0.6" y1="-0.35" x2="0.6" y2="-0.35" width="0.1016" layer="21"/>
+<wire x1="0.6" y1="-0.35" x2="0.6" y2="0.35" width="0.1016" layer="51"/>
+<wire x1="0.6" y1="0.35" x2="-0.6" y2="0.35" width="0.1016" layer="21"/>
+<smd name="C" x="-0.725" y="0" dx="0.35" dy="0.35" layer="1"/>
+<smd name="A" x="0.725" y="0" dx="0.35" dy="0.35" layer="1"/>
+<text x="-0.9" y="0.5" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.9" y="-1.8" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.6" y1="-0.35" x2="0" y2="0.35" layer="51"/>
+<rectangle x1="-0.85" y1="-0.15" x2="-0.6" y2="0.15" layer="51"/>
+<rectangle x1="0.6" y1="-0.15" x2="0.85" y2="0.15" layer="51"/>
+</package>
+<package name="DO214AA" urn="urn:adsk.eagle:footprint:43213/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="-2.4" y1="1.1" x2="2.4" y2="1.1" width="0.254" layer="51"/>
+<wire x1="2.4" y1="1.1" x2="2.4" y2="-1.1" width="0.254" layer="51"/>
+<wire x1="2.4" y1="-1.1" x2="-2.4" y2="-1.1" width="0.254" layer="51"/>
+<wire x1="-2.4" y1="-1.1" x2="-2.4" y2="1.1" width="0.254" layer="51"/>
+<wire x1="-1.2" y1="0" x2="0.05" y2="0.7" width="0.254" layer="21"/>
+<wire x1="0.05" y1="0.7" x2="0.05" y2="-0.7" width="0.254" layer="21"/>
+<wire x1="0.05" y1="-0.7" x2="-1.2" y2="0" width="0.254" layer="21"/>
+<smd name="C" x="-2.55" y="0" dx="1.8" dy="2.2" layer="1"/>
+<smd name="A" x="2.55" y="0" dx="1.8" dy="2.2" layer="1"/>
+<text x="-2.64" y="1.436" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.64" y="-2.706" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.75" y1="-0.7" x2="-2.5" y2="0.65" layer="51"/>
+<rectangle x1="2.5" y1="-0.7" x2="2.75" y2="0.65" layer="51"/>
+<rectangle x1="-1.4" y1="-1.05" x2="-1.1" y2="1.05" layer="21"/>
+</package>
+<package name="DO214AC" urn="urn:adsk.eagle:footprint:43214/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="-2.3" y1="1" x2="2.3" y2="1" width="0.254" layer="51"/>
+<wire x1="2.3" y1="1" x2="2.3" y2="-0.95" width="0.254" layer="51"/>
+<wire x1="2.3" y1="-0.95" x2="-2.3" y2="-0.95" width="0.254" layer="51"/>
+<wire x1="-2.3" y1="-0.95" x2="-2.3" y2="1" width="0.254" layer="51"/>
+<wire x1="-0.8" y1="0" x2="0.25" y2="0.75" width="0.254" layer="21"/>
+<wire x1="0.25" y1="0.75" x2="0.25" y2="-0.7" width="0.254" layer="21"/>
+<wire x1="0.25" y1="-0.7" x2="-0.8" y2="0" width="0.254" layer="21"/>
+<smd name="C" x="-2.05" y="0" dx="1.8" dy="1.7" layer="1"/>
+<smd name="A" x="2.05" y="0" dx="1.8" dy="1.7" layer="1"/>
+<text x="-2.64" y="1.286" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.64" y="-2.556" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.65" y1="-0.7" x2="-2.4" y2="0.65" layer="51"/>
+<rectangle x1="2.4" y1="-0.7" x2="2.65" y2="0.65" layer="51"/>
+<rectangle x1="-1" y1="-1.05" x2="-0.7" y2="1.05" layer="21"/>
+</package>
+<package name="DO214BA" urn="urn:adsk.eagle:footprint:43215/1" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<wire x1="-2.5" y1="1.35" x2="2.5" y2="1.35" width="0.254" layer="51"/>
+<wire x1="2.5" y1="1.35" x2="2.5" y2="-1.35" width="0.254" layer="51"/>
+<wire x1="2.5" y1="-1.35" x2="-2.5" y2="-1.35" width="0.254" layer="51"/>
+<wire x1="-2.5" y1="-1.35" x2="-2.5" y2="1.35" width="0.254" layer="51"/>
+<wire x1="-0.8" y1="0" x2="0.65" y2="0.95" width="0.254" layer="21"/>
+<wire x1="0.65" y1="0.95" x2="0.65" y2="-0.95" width="0.254" layer="21"/>
+<wire x1="0.65" y1="-0.95" x2="-0.8" y2="0" width="0.254" layer="21"/>
+<smd name="C" x="-2.05" y="0" dx="1.8" dy="1.7" layer="1"/>
+<smd name="A" x="2.05" y="0" dx="1.8" dy="1.7" layer="1"/>
+<text x="-2.64" y="1.736" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.64" y="-3.056" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.85" y1="-0.7" x2="-2.6" y2="0.65" layer="51"/>
+<rectangle x1="2.6" y1="-0.7" x2="2.85" y2="0.65" layer="51"/>
+<rectangle x1="-1" y1="-1.05" x2="-0.7" y2="1.05" layer="21"/>
+</package>
+<package name="DO-214AC" urn="urn:adsk.eagle:footprint:43216/1" library_version="2">
+<description>&lt;b&gt;SURFACE MOUNT GENERAL RECTIFIER&lt;/b&gt; JEDEC DO-214AC molded platic body&lt;p&gt;
+Method 2026&lt;br&gt;
+Source: http://www.kingtronics.com/SMD_M7/M7_SMD_4007.pdf</description>
+<wire x1="-2.15" y1="1.3" x2="2.15" y2="1.3" width="0.2032" layer="51"/>
+<wire x1="2.15" y1="1.3" x2="2.15" y2="-1.3" width="0.2032" layer="51"/>
+<wire x1="2.15" y1="-1.3" x2="-2.15" y2="-1.3" width="0.2032" layer="51"/>
+<wire x1="-2.15" y1="-1.3" x2="-2.15" y2="1.3" width="0.2032" layer="51"/>
+<wire x1="-1.035" y1="1.3" x2="1.025" y2="1.3" width="0.2032" layer="21"/>
+<wire x1="1.025" y1="-1.3" x2="-1.035" y2="-1.3" width="0.2032" layer="21"/>
+<smd name="C" x="-2.025" y="0" dx="1.8" dy="2.4" layer="1"/>
+<smd name="A" x="2.025" y="0" dx="1.8" dy="2.4" layer="1" rot="R180"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-2.825" y1="-1.1" x2="-2.175" y2="1.1" layer="51"/>
+<rectangle x1="2.175" y1="-1.1" x2="2.825" y2="1.1" layer="51" rot="R180"/>
+<rectangle x1="-1.065" y1="-1.225" x2="-0.39" y2="1.225" layer="21"/>
+<rectangle x1="-1.75" y1="-1.225" x2="-1.075" y2="1.225" layer="51"/>
+</package>
+<package name="DO41-7.6" urn="urn:adsk.eagle:footprint:43217/1" library_version="2">
+<description>&lt;b&gt;DO41&lt;/b&gt; 7.6mm x 2mm&lt;p&gt;
+Source: http://www.diodes.com/datasheets/ds23001.pdf</description>
+<wire x1="2.082" y1="-0.92" x2="-2.082" y2="-0.92" width="0.1524" layer="21"/>
+<wire x1="2.082" y1="-0.92" x2="2.082" y2="0.92" width="0.1524" layer="21"/>
+<wire x1="-2.082" y1="0.92" x2="2.082" y2="0.92" width="0.1524" layer="21"/>
+<wire x1="-2.082" y1="0.92" x2="-2.082" y2="-0.92" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="0" x2="2.494" y2="0" width="0.85" layer="51"/>
+<wire x1="-3.81" y1="0" x2="-2.519" y2="0" width="0.85" layer="51"/>
+<wire x1="-0.635" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="0.635" x2="1.016" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.016" y1="-0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.524" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="1.016" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="0" width="0.1524" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<pad name="C" x="-3.81" y="0" drill="1.1" diameter="1.7"/>
+<pad name="A" x="3.81" y="0" drill="1.1" diameter="1.7"/>
+<text x="-2.032" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.032" y="-2.921" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.651" y1="-0.95" x2="-1.143" y2="0.92" layer="21"/>
+<rectangle x1="2.082" y1="-0.425" x2="2.717" y2="0.425" layer="21"/>
+<rectangle x1="-2.717" y1="-0.425" x2="-2.082" y2="0.425" layer="21"/>
+</package>
+</packages>
+<packages3d>
+<package3d name="DO41-10" urn="urn:adsk.eagle:package:43336/1" type="box" library_version="2">
+<description>DIODE
+diameter 2.54 mm, horizontal, grid 10.16 mm</description>
+</package3d>
+<package3d name="DO35-10" urn="urn:adsk.eagle:package:43344/2" type="model" library_version="2">
+<description>DIODE
+diameter 2 mm, horizontal, grid 10.16 mm</description>
+</package3d>
+<package3d name="DO204-10" urn="urn:adsk.eagle:package:43366/1" type="box" library_version="2">
+<description>DIODE
+diameter 4 mm, horizontal, grid 10 mm</description>
+</package3d>
+<package3d name="DO15-12" urn="urn:adsk.eagle:package:43369/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, horizontal, grid 12.7 mm</description>
+</package3d>
+<package3d name="SOD57-10" urn="urn:adsk.eagle:package:43367/1" type="box" library_version="2">
+<description>DIODE
+diameter 4 mm, vertical, grid 10.16 mm</description>
+</package3d>
+<package3d name="DO201-15" urn="urn:adsk.eagle:package:43365/1" type="box" library_version="2">
+<description>DIODE
+diameter 5.6 mm, horizontal, grid 15.24 mm</description>
+</package3d>
+<package3d name="DO07" urn="urn:adsk.eagle:package:43394/1" type="box" library_version="2">
+<description>DIODE
+diameter 2.54 mm, horizontal, grid 10.16 mm</description>
+</package3d>
+<package3d name="P1-10" urn="urn:adsk.eagle:package:43375/1" type="box" library_version="2">
+<description>DIODE
+diameter 3 mm, horizontal, grid 10.16 mm</description>
+</package3d>
+<package3d name="P2-15" urn="urn:adsk.eagle:package:43345/1" type="box" library_version="2">
+<description>DIODE
+diameter 5 mm, horizontal, grid 12.7 mm</description>
+</package3d>
+<package3d name="DO34-7" urn="urn:adsk.eagle:package:43348/1" type="box" library_version="2">
+<description>DIODE
+diameter 1.8 mm, horizontal, grid 7.62 mm</description>
+</package3d>
+<package3d name="SOT54H" urn="urn:adsk.eagle:package:43359/1" type="box" library_version="2">
+<description>DIODE
+2-lead plastic, vertical</description>
+</package3d>
+<package3d name="SOD523" urn="urn:adsk.eagle:package:43410/1" type="box" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="TO18D" urn="urn:adsk.eagle:package:43443/1" type="box" library_version="2">
+<description>DIODE
+2-lead metall, vertical</description>
+</package3d>
+<package3d name="C1702-05" urn="urn:adsk.eagle:package:43430/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, vertical, grid 5.08 mm</description>
+</package3d>
+<package3d name="C1702-15" urn="urn:adsk.eagle:package:43351/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, horizontal, grid 15.24 mm</description>
+</package3d>
+<package3d name="SGA-10" urn="urn:adsk.eagle:package:43388/1" type="box" library_version="2">
+<description>DIODE
+diameter 4 mm, vertical, grid 10.16 mm</description>
+</package3d>
+<package3d name="SOD64-10" urn="urn:adsk.eagle:package:43385/1" type="box" library_version="2">
+<description>DIODE
+diameter 4.8 mm, vertical, grid 10.16 mm</description>
+</package3d>
+<package3d name="SOD61A" urn="urn:adsk.eagle:package:43377/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, vertical, grid 10.16 mm</description>
+</package3d>
+<package3d name="SOD61B" urn="urn:adsk.eagle:package:43379/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, vertical, grid 15.24 mm</description>
+</package3d>
+<package3d name="SOD61C" urn="urn:adsk.eagle:package:43378/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, vertical, grid 17.78 mm</description>
+</package3d>
+<package3d name="SOD61D" urn="urn:adsk.eagle:package:43381/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, vertical, grid 15.24 mm</description>
+</package3d>
+<package3d name="SOD61E" urn="urn:adsk.eagle:package:43380/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.5 mm, vertical, grid 20.32 mm</description>
+</package3d>
+<package3d name="DO27-15" urn="urn:adsk.eagle:package:43337/1" type="box" library_version="2">
+<description>DIODE
+diameter 5 mm, horizontal, grid 15.24 mm</description>
+</package3d>
+<package3d name="SOD81" urn="urn:adsk.eagle:package:43363/1" type="box" library_version="2">
+<description>DIODE
+diameter 2.3 mm, vertical, grid 10.16 mm</description>
+</package3d>
+<package3d name="SOD84" urn="urn:adsk.eagle:package:43376/1" type="box" library_version="2">
+<description>DIODE
+diameter 3.3 mm, vertical, grid 10.16 mm</description>
+</package3d>
+<package3d name="F126-10" urn="urn:adsk.eagle:package:43396/1" type="box" library_version="2">
+<description>DIODE
+diameter 3 mm, horizontal, grid 10.16 mm</description>
+</package3d>
+<package3d name="DO220S" urn="urn:adsk.eagle:package:43371/1" type="box" library_version="2">
+<description>DIODE
+2-lead molded, vertical</description>
+</package3d>
+<package3d name="TO220AC" urn="urn:adsk.eagle:package:43370/1" type="box" library_version="2">
+<description>DIODE
+2-lead molded, horizontal</description>
+</package3d>
+<package3d name="TO220ACS" urn="urn:adsk.eagle:package:43373/2" type="model" library_version="2">
+<description>DIODE
+2-lead molded, vertical</description>
+</package3d>
+<package3d name="G4-12" urn="urn:adsk.eagle:package:43368/1" type="box" library_version="2">
+<description>DIODE
+diameter 7.62 mm, horizontal, grid 12.7 mm</description>
+</package3d>
+<package3d name="SOD83-12" urn="urn:adsk.eagle:package:43382/1" type="box" library_version="2">
+<description>DIODE
+diameter 4.8 mm, vertical, grid 12.7 mm</description>
+</package3d>
+<package3d name="SMB" urn="urn:adsk.eagle:package:43404/2" type="model" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="P6-15" urn="urn:adsk.eagle:package:43343/1" type="box" library_version="2">
+<description>DIODE
+diameter 9 mm, horizontal, grid 15.24 mm</description>
+</package3d>
+<package3d name="C2673" urn="urn:adsk.eagle:package:43390/1" type="box" library_version="2">
+<description>DIODE
+diameter 5.2 mm, horizontal, grid 15.24 mm</description>
+</package3d>
+<package3d name="C221B1A" urn="urn:adsk.eagle:package:43391/1" type="box" library_version="2">
+<description>DIODE
+2-lead molded, horizontal</description>
+</package3d>
+<package3d name="SOD80C" urn="urn:adsk.eagle:package:43405/2" type="model" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="D-10" urn="urn:adsk.eagle:package:43434/1" type="box" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="D-12.5" urn="urn:adsk.eagle:package:43427/1" type="box" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="D-2.5" urn="urn:adsk.eagle:package:43419/1" type="box" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="D-5" urn="urn:adsk.eagle:package:43440/1" type="box" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="D-7.5" urn="urn:adsk.eagle:package:43423/1" type="box" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="SOD106-R" urn="urn:adsk.eagle:package:43424/2" type="model" library_version="2">
+<description>SOD106 Reflow soldering Philips SC01_Mounting_1996.pdf</description>
+</package3d>
+<package3d name="SMC" urn="urn:adsk.eagle:package:43425/2" type="model" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="SOD106-W" urn="urn:adsk.eagle:package:43431/1" type="box" library_version="2">
+<description>SOD106 Wave soldering Philips SC01_Mounting_1996.pdf</description>
+</package3d>
+<package3d name="SOD106A-R" urn="urn:adsk.eagle:package:43438/2" type="model" library_version="2">
+<description>SOD106A Reflow soldering Philips SC01_Mounting_1996.pdf</description>
+</package3d>
+<package3d name="SOD110-W" urn="urn:adsk.eagle:package:43428/1" type="box" library_version="2">
+<description>SOD110 Wave soldering Philips SC01_Mounting_1996.pdf</description>
+</package3d>
+<package3d name="SOD110-R" urn="urn:adsk.eagle:package:43426/1" type="box" library_version="2">
+<description>SOD110 Reflow soldering Philips SC01_Mounting_1996.pdf</description>
+</package3d>
+<package3d name="SOD123" urn="urn:adsk.eagle:package:43420/1" type="box" library_version="2">
+<description>Diode</description>
+</package3d>
+<package3d name="SOD323-R" urn="urn:adsk.eagle:package:43437/1" type="box" library_version="2">
+<description>SOD323 Reflow soldering Philips SC01_Mounting_1996.pdf</description>
+</package3d>
+<package3d name="SOD323-W" urn="urn:adsk.eagle:package:43418/1" type="box" library_version="2">
+<description>SOD323 Wave soldering Philips SC01_Mounting_1996.pdf</description>
+</package3d>
+<package3d name="GF1" urn="urn:adsk.eagle:package:43422/1" type="box" library_version="2">
+<description>GF1
+General Semiconductor</description>
+</package3d>
+<package3d name="MINIMELF" urn="urn:adsk.eagle:package:43429/1" type="box" library_version="2">
+<description>Mini Melf Diode</description>
+</package3d>
+<package3d name="MELF-MLL41" urn="urn:adsk.eagle:package:43444/1" type="box" library_version="2">
+<description>DIODE
+Package DO-213AB = http://www.diotec.com/pdf/sm4001.pdf</description>
+</package3d>
+<package3d name="MICROMELF-R" urn="urn:adsk.eagle:package:43436/1" type="box" library_version="2">
+<description>Micro Melf Diode Reflow soldering VISHAY mcl4148.pdf</description>
+</package3d>
+<package3d name="MICROMELF-W" urn="urn:adsk.eagle:package:43441/1" type="box" library_version="2">
+<description>Micro Melf Diode Wave soldering VISHAY mcl4148.pdf</description>
+</package3d>
+<package3d name="SC79_INFINEON" urn="urn:adsk.eagle:package:43432/1" type="box" library_version="2">
+<description>Diode Package Reflow soldering
+INFINEON, www.infineon.com/cmc_upload/0/000/010/257/eh_db_5b.pdf</description>
+</package3d>
+<package3d name="SCD80_INFINEON" urn="urn:adsk.eagle:package:43414/1" type="box" library_version="2">
+<description>Diode Package Reflow soldering
+INFINEON, www.infineon.com/cmc_upload/0/000/010/257/eh_db_5b.pdf</description>
+</package3d>
+<package3d name="DO214AA" urn="urn:adsk.eagle:package:43433/2" type="model" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="DO214AC" urn="urn:adsk.eagle:package:43417/2" type="model" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="DO214BA" urn="urn:adsk.eagle:package:43453/2" type="model" library_version="2">
+<description>DIODE</description>
+</package3d>
+<package3d name="DO-214AC" urn="urn:adsk.eagle:package:43416/2" type="model" library_version="2">
+<description>SURFACE MOUNT GENERAL RECTIFIER JEDEC DO-214AC molded platic body
+Method 2026
+Source: http://www.kingtronics.com/SMD_M7/M7_SMD_4007.pdf</description>
+</package3d>
+<package3d name="DO41-7.6" urn="urn:adsk.eagle:package:43421/1" type="box" library_version="2">
+<description>DO41 7.6mm x 2mm
+Source: http://www.diodes.com/datasheets/ds23001.pdf</description>
+</package3d>
+</packages3d>
+<symbols>
+<symbol name="D" urn="urn:adsk.eagle:symbol:43091/1" library_version="2">
+<wire x1="-1.27" y1="-1.27" x2="1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="-1.27" y2="1.27" width="0.254" layer="94"/>
+<wire x1="1.27" y1="1.27" x2="1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="1.27" x2="-1.27" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="1.27" y2="-1.27" width="0.254" layer="94"/>
+<text x="2.54" y="0.4826" size="1.778" layer="95">&gt;NAME</text>
+<text x="2.54" y="-2.3114" size="1.778" layer="96">&gt;VALUE</text>
+<text x="-2.54" y="0" size="0.4064" layer="99" align="center">SpiceOrder 1</text>
+<text x="2.54" y="0" size="0.4064" layer="99" align="center">SpiceOrder 2</text>
+<pin name="A" x="-2.54" y="0" visible="off" length="short" direction="pas"/>
+<pin name="C" x="2.54" y="0" visible="off" length="short" direction="pas" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="DIODE-" urn="urn:adsk.eagle:component:43657/13" prefix="D" uservalue="yes" library_version="2">
+<description>&lt;b&gt;DIODE&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="D" x="0" y="0"/>
+</gates>
+<devices>
+<device name="DO41-10" package="DO41-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43336/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO35-10" package="DO35-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43344/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO204-10" package="DO204-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43366/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO15-12" package="DO15-12">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43369/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD57-10" package="SOD57-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43367/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO201-15" package="DO201-15">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43365/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO07" package="DO07">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43394/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P1-10" package="P1-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43375/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P2-15" package="P2-15">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43345/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO34-7" package="DO34-7">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43348/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOT54H" package="SOT54H">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43359/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD523" package="SOD523">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43410/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="TO18D" package="TO18D">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43443/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1702-05" package="C1702-05">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43430/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1702-15" package="C1702-15">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43351/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SGA-10" package="SGA-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43388/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD64-10" package="SOD64-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43385/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD61A" package="SOD61A">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43377/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD61B" package="SOD61B">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43379/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD61C" package="SOD61C">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43378/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD61D" package="SOD61D">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43381/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD61E" package="SOD61E">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43380/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO27-15" package="DO27-15">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43337/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD81" package="SOD81">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43363/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD84" package="SOD84">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43376/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="F126-10" package="F126-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43396/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO220S" package="DO220S">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43371/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="TO220H" package="TO220AC">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43370/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="TO220V" package="TO220ACS">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43373/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="G4-12" package="G4-12">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43368/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD83-12" package="SOD83-12">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43382/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMB" package="SMB">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43404/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P6-15" package="P6-15">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43343/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C2673" package="C2673">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43390/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C221B1A" package="C221B1A">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43391/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD80C" package="SOD80C">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43405/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="D-10" package="D-10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43434/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="D-12.5" package="D-12.5">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43427/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="D-2.5" package="D-2.5">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43419/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="D-5" package="D-5">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43440/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="D-7.5" package="D-7.5">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43423/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD106-R" package="SOD106-R">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43424/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMC" package="SMC">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43425/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD106-W" package="SOD106-W">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43431/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD106A-R" package="SOD106A-R">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43438/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD110-W" package="SOD110-W">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43428/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD110-R" package="SOD110-R">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43426/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD123" package="SOD123">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43420/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD323-R" package="SOD323-R">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43437/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOD323-W" package="SOD323-W">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43418/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="GF1" package="GF1">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43422/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MINIMELF" package="MINIMELF">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43429/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF-MLL41" package="MELF-MLL41">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43444/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MICROMELF-R" package="MICROMELF-R">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43436/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MICROMELF-W" package="MICROMELF-W">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43441/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SC79_INFINEON" package="SC79_INFINEON">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43432/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SCD80-INFINEON" package="SCD80_INFINEON">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43414/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO214AA" package="DO214AA">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43433/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO214AC" package="DO214AC">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43417/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO214BA" package="DO214BA">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43453/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO-214AC" package="DO-214AC">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43416/2"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="DO41-7.6" package="DO41-7.6">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<package3dinstances>
+<package3dinstance package3d_urn="urn:adsk.eagle:package:43421/1"/>
+</package3dinstances>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="U$2" library="NPR_70" deviceset="NUCLEO_STM32L432KC" device=""/>
+<part name="U$3" library="NPR_70" deviceset="RF4463F30" device=""/>
+<part name="H2" library="NPR_70" deviceset="MOUNT_HOLE" device=""/>
+<part name="X1" library="NPR_70" deviceset="BU-SMA-H" device=""/>
+<part name="U$4" library="NPR_70" deviceset="VOLT_REGUL" device=""/>
+<part name="H1" library="NPR_70" deviceset="MOUNT_HOLE" device=""/>
+<part name="H3" library="NPR_70" deviceset="MOUNT_HOLE" device=""/>
+<part name="H4" library="NPR_70" deviceset="MOUNT_HOLE" device=""/>
+<part name="H5" library="NPR_70" deviceset="MOUNT_HOLE" device=""/>
+<part name="R1" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R2" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R4" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R5" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R6" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R7" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="C2" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="C3" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="C5" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="R8" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R9" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R10" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="R11" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="UEXT" library="NPR_70" deviceset="POWER_CABLE" device=""/>
+<part name="C6" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="C7" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="L4940_5V" library="NPR_70" deviceset="REGUL" device=""/>
+<part name="LM2937_3V3" library="NPR_70" deviceset="REGUL" device=""/>
+<part name="C8" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="C9" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="C1" library="NPR_70" deviceset="CPOL_CT3216" device="" value=""/>
+<part name="C10" library="NPR_70" deviceset="CPOL_B/3528_21W" device="" value=""/>
+<part name="C11" library="NPR_70" deviceset="CPOL_CT6032" device="" value=""/>
+<part name="C12" library="NPR_70" deviceset="CPOL_D/7343_31W" device="" value=""/>
+<part name="C13" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="C14" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="T1" library="transistor" library_urn="urn:adsk.eagle:library:402" deviceset="BC847" device="" package3d_urn="urn:adsk.eagle:package:28738/2"/>
+<part name="R12" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="U$1" library="NPR_70" deviceset="W5500_LITE" device="USR-ES1"/>
+<part name="C15" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="LED1" library="mfj-236" deviceset="LEDX2_V" device="K-A" value="Y-G"/>
+<part name="LED2" library="mfj-236" deviceset="LEDX2_V" device="K-A" value="R-R"/>
+<part name="U$5" library="NPR_70" deviceset="SRAM" device=""/>
+<part name="C16" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-EU" device="C1206K" package3d_urn="urn:adsk.eagle:package:26202/1"/>
+<part name="SB2" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="SB1" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="SB4" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="SB3" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+<part name="GPIO" library="con-harting" library_urn="urn:adsk.eagle:library:151" deviceset="CON10" device="" package3d_urn="urn:adsk.eagle:package:7121/1"/>
+<part name="D1" library="diode" library_urn="urn:adsk.eagle:library:210" deviceset="DIODE-" device="DO-214AC" package3d_urn="urn:adsk.eagle:package:43416/2"/>
+<part name="R3" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-EU_" device="M0805" package3d_urn="urn:adsk.eagle:package:26079/1"/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<text x="-17.272" y="37.084" size="1.778" layer="97">TX</text>
+<text x="-17.018" y="30.988" size="1.778" layer="97">POW</text>
+<text x="-7.62" y="9.398" size="1.778" layer="97">RX</text>
+<text x="-6.604" y="3.556" size="1.778" layer="97">CON</text>
+</plain>
+<instances>
+<instance part="U$2" gate="G$1" x="88.9" y="48.26" smashed="yes"/>
+<instance part="U$3" gate="SI4463" x="170.18" y="53.34" smashed="yes"/>
+<instance part="H2" gate="G$1" x="-55.88" y="83.82" smashed="yes">
+<attribute name="NAME" x="-53.086" y="84.4042" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-53.086" y="81.3562" size="1.778" layer="96"/>
+</instance>
+<instance part="X1" gate="G$1" x="203.2" y="38.1" smashed="yes" rot="R180">
+<attribute name="VALUE" x="205.74" y="43.18" size="1.778" layer="96" rot="R180"/>
+<attribute name="NAME" x="205.74" y="34.798" size="1.778" layer="95" rot="R180"/>
+</instance>
+<instance part="U$4" gate="G$1" x="63.5" y="147.32" smashed="yes"/>
+<instance part="H1" gate="G$1" x="-55.88" y="76.2" smashed="yes">
+<attribute name="NAME" x="-53.086" y="76.7842" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-53.086" y="73.7362" size="1.778" layer="96"/>
+</instance>
+<instance part="H3" gate="G$1" x="-55.88" y="68.58" smashed="yes">
+<attribute name="NAME" x="-53.086" y="69.1642" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-53.086" y="66.1162" size="1.778" layer="96"/>
+</instance>
+<instance part="H4" gate="G$1" x="-55.88" y="60.96" smashed="yes">
+<attribute name="NAME" x="-53.086" y="61.5442" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-53.086" y="58.4962" size="1.778" layer="96"/>
+</instance>
+<instance part="H5" gate="G$1" x="-55.88" y="53.34" smashed="yes">
+<attribute name="NAME" x="-53.086" y="53.9242" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-53.086" y="50.8762" size="1.778" layer="96"/>
+</instance>
+<instance part="R1" gate="G$1" x="147.32" y="17.78" smashed="yes">
+<attribute name="NAME" x="143.51" y="19.2786" size="1.778" layer="95"/>
+<attribute name="VALUE" x="143.51" y="14.478" size="1.778" layer="96"/>
+</instance>
+<instance part="R2" gate="G$1" x="129.54" y="154.94" smashed="yes">
+<attribute name="NAME" x="125.73" y="156.4386" size="1.778" layer="95"/>
+<attribute name="VALUE" x="125.73" y="151.638" size="1.778" layer="96"/>
+</instance>
+<instance part="R4" gate="G$1" x="129.54" y="149.86" smashed="yes">
+<attribute name="NAME" x="125.73" y="151.3586" size="1.778" layer="95"/>
+<attribute name="VALUE" x="125.73" y="146.558" size="1.778" layer="96"/>
+</instance>
+<instance part="R5" gate="G$1" x="129.54" y="144.78" smashed="yes">
+<attribute name="NAME" x="125.73" y="146.2786" size="1.778" layer="95"/>
+<attribute name="VALUE" x="125.73" y="141.478" size="1.778" layer="96"/>
+</instance>
+<instance part="R6" gate="G$1" x="180.34" y="132.08" smashed="yes" rot="R90">
+<attribute name="NAME" x="178.8414" y="128.27" size="1.778" layer="95" rot="R90"/>
+<attribute name="VALUE" x="183.642" y="128.27" size="1.778" layer="96" rot="R90"/>
+</instance>
+<instance part="R7" gate="G$1" x="180.34" y="116.84" smashed="yes" rot="R90">
+<attribute name="NAME" x="178.8414" y="113.03" size="1.778" layer="95" rot="R90"/>
+<attribute name="VALUE" x="183.642" y="113.03" size="1.778" layer="96" rot="R90"/>
+</instance>
+<instance part="C2" gate="G$1" x="127" y="132.08" smashed="yes" rot="R180">
+<attribute name="NAME" x="125.476" y="131.699" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="125.476" y="136.779" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="C3" gate="G$1" x="134.62" y="12.7" smashed="yes" rot="R180">
+<attribute name="NAME" x="133.096" y="12.319" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="133.096" y="17.399" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="C5" gate="G$1" x="144.78" y="33.02" smashed="yes">
+<attribute name="NAME" x="146.304" y="33.401" size="1.778" layer="95"/>
+<attribute name="VALUE" x="146.304" y="28.321" size="1.778" layer="96"/>
+</instance>
+<instance part="R8" gate="G$1" x="-27.94" y="15.24" smashed="yes">
+<attribute name="NAME" x="-31.75" y="16.7386" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-31.75" y="11.938" size="1.778" layer="96"/>
+</instance>
+<instance part="R9" gate="G$1" x="-30.48" y="35.56" smashed="yes">
+<attribute name="NAME" x="-34.29" y="37.0586" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-34.29" y="32.258" size="1.778" layer="96"/>
+</instance>
+<instance part="R10" gate="G$1" x="-20.32" y="7.62" smashed="yes">
+<attribute name="NAME" x="-22.86" y="9.1186" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-24.13" y="4.318" size="1.778" layer="96"/>
+</instance>
+<instance part="R11" gate="G$1" x="-20.32" y="0" smashed="yes">
+<attribute name="NAME" x="-22.606" y="1.4986" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-24.13" y="-3.302" size="1.778" layer="96"/>
+</instance>
+<instance part="UEXT" gate="G$1" x="-2.54" y="142.24" smashed="yes"/>
+<instance part="C6" gate="G$1" x="-45.72" y="116.84" smashed="yes">
+<attribute name="NAME" x="-44.196" y="117.221" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-44.196" y="112.141" size="1.778" layer="96"/>
+</instance>
+<instance part="C7" gate="G$1" x="-15.24" y="114.3" smashed="yes">
+<attribute name="NAME" x="-13.716" y="114.681" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-13.716" y="109.601" size="1.778" layer="96"/>
+</instance>
+<instance part="L4940_5V" gate="G$1" x="-30.48" y="116.84" smashed="yes">
+<attribute name="NAME" x="-33.02" y="121.92" size="1.778" layer="97"/>
+</instance>
+<instance part="LM2937_3V3" gate="G$1" x="60.96" y="114.3" smashed="yes">
+<attribute name="NAME" x="58.42" y="119.38" size="1.778" layer="97"/>
+</instance>
+<instance part="C8" gate="G$1" x="76.2" y="111.76" smashed="yes">
+<attribute name="NAME" x="77.724" y="112.141" size="1.778" layer="95"/>
+<attribute name="VALUE" x="77.724" y="107.061" size="1.778" layer="96"/>
+</instance>
+<instance part="C9" gate="G$1" x="48.26" y="111.76" smashed="yes">
+<attribute name="NAME" x="49.784" y="112.141" size="1.778" layer="95"/>
+<attribute name="VALUE" x="49.784" y="107.061" size="1.778" layer="96"/>
+</instance>
+<instance part="C1" gate="G$1" x="88.9" y="111.76" smashed="yes">
+<attribute name="NAME" x="89.916" y="112.395" size="1.778" layer="95"/>
+<attribute name="VALUE" x="89.916" y="107.569" size="1.778" layer="96"/>
+</instance>
+<instance part="C10" gate="G$1" x="40.64" y="111.76" smashed="yes">
+<attribute name="NAME" x="41.656" y="112.395" size="1.778" layer="95"/>
+<attribute name="VALUE" x="41.656" y="107.569" size="1.778" layer="96"/>
+</instance>
+<instance part="C11" gate="G$1" x="7.62" y="114.3" smashed="yes">
+<attribute name="NAME" x="8.636" y="114.935" size="1.778" layer="95"/>
+<attribute name="VALUE" x="8.636" y="110.109" size="1.778" layer="96"/>
+</instance>
+<instance part="C12" gate="G$1" x="-58.42" y="114.3" smashed="yes">
+<attribute name="NAME" x="-57.404" y="114.935" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-57.404" y="110.109" size="1.778" layer="96"/>
+</instance>
+<instance part="C13" gate="G$1" x="17.78" y="144.78" smashed="yes">
+<attribute name="NAME" x="19.304" y="145.161" size="1.778" layer="95"/>
+<attribute name="VALUE" x="19.304" y="140.081" size="1.778" layer="96"/>
+</instance>
+<instance part="C14" gate="G$1" x="93.98" y="149.86" smashed="yes">
+<attribute name="NAME" x="95.504" y="150.241" size="1.778" layer="95"/>
+<attribute name="VALUE" x="95.504" y="145.161" size="1.778" layer="96"/>
+</instance>
+<instance part="T1" gate="G$1" x="-5.08" y="33.02" smashed="yes" rot="R90">
+<attribute name="NAME" x="0" y="30.48" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="-2.54" y="38.1" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="R12" gate="G$1" x="7.62" y="27.94" smashed="yes" rot="R180">
+<attribute name="NAME" x="11.43" y="26.4414" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="11.43" y="31.242" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="U$1" gate="G$1" x="30.48" y="50.8" smashed="yes"/>
+<instance part="C15" gate="G$1" x="119.38" y="132.08" smashed="yes" rot="R180">
+<attribute name="NAME" x="117.856" y="131.699" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="117.856" y="136.779" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="LED1" gate="G$1" x="-10.16" y="5.08" smashed="yes" rot="R90">
+<attribute name="NAME" x="-11.43" y="13.208" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-16.256" y="-5.207" size="1.778" layer="96"/>
+</instance>
+<instance part="LED2" gate="G$1" x="-20.32" y="33.02" smashed="yes" rot="R90">
+<attribute name="NAME" x="-22.098" y="23.114" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-26.416" y="41.783" size="1.778" layer="96"/>
+</instance>
+<instance part="U$5" gate="G$1" x="129.54" y="99.06"/>
+<instance part="C16" gate="G$1" x="134.62" y="132.08" smashed="yes" rot="R180">
+<attribute name="NAME" x="133.096" y="131.699" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="133.096" y="136.779" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="SB2" gate="G$1" x="78.74" y="162.56" smashed="yes" rot="R180">
+<attribute name="NAME" x="82.55" y="161.0614" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="82.55" y="165.862" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="SB1" gate="G$1" x="25.4" y="154.94" smashed="yes" rot="R180">
+<attribute name="NAME" x="29.21" y="153.4414" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="29.21" y="158.242" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="SB4" gate="G$1" x="-5.08" y="129.54" smashed="yes" rot="R180">
+<attribute name="NAME" x="-1.27" y="128.0414" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="-1.27" y="132.842" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="SB3" gate="G$1" x="-5.08" y="119.38" smashed="yes" rot="R180">
+<attribute name="NAME" x="-1.27" y="117.8814" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="-1.27" y="122.682" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="GPIO" gate="G$1" x="27.94" y="10.16"/>
+<instance part="D1" gate="G$1" x="33.02" y="116.84"/>
+<instance part="R3" gate="G$1" x="129.54" y="160.02" smashed="yes">
+<attribute name="NAME" x="125.73" y="161.5186" size="1.778" layer="95"/>
+<attribute name="VALUE" x="125.73" y="156.718" size="1.778" layer="96"/>
+</instance>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="CLK_SPI3" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D13_PB3"/>
+<wire x1="111.76" y1="12.7" x2="119.38" y2="12.7" width="0.1524" layer="91"/>
+<label x="116.84" y="12.7" size="1.778" layer="95"/>
+<label x="116.84" y="12.7" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="-2.54" y1="58.42" x2="-15.24" y2="58.42" width="0.1524" layer="91"/>
+<label x="-17.78" y="58.42" size="1.778" layer="95"/>
+<wire x1="-15.24" y1="58.42" x2="-17.78" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="-15.24" y1="58.42" x2="2.54" y2="58.42" width="0.1524" layer="91"/>
+<junction x="-15.24" y="58.42"/>
+<pinref part="U$1" gate="G$1" pin="SLCK"/>
+</segment>
+<segment>
+<pinref part="U$5" gate="G$1" pin="SCK"/>
+<wire x1="149.86" y1="101.6" x2="160.02" y2="101.6" width="0.1524" layer="91"/>
+<label x="154.94" y="101.6" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="3V3" class="0">
+<segment>
+<label x="43.18" y="68.58" size="1.778" layer="95"/>
+<wire x1="43.18" y1="68.58" x2="40.64" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="68.58" x2="40.64" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="3V3."/>
+<wire x1="40.64" y1="63.5" x2="30.48" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="3V3"/>
+<wire x1="40.64" y1="68.58" x2="30.48" y2="68.58" width="0.1524" layer="91"/>
+<junction x="40.64" y="68.58"/>
+</segment>
+<segment>
+<pinref part="R1" gate="G$1" pin="2"/>
+<wire x1="152.4" y1="17.78" x2="157.48" y2="17.78" width="0.1524" layer="91"/>
+<label x="154.94" y="17.78" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="1"/>
+<wire x1="124.46" y1="154.94" x2="121.92" y2="154.94" width="0.1524" layer="91"/>
+<label x="116.84" y="154.94" size="1.778" layer="95"/>
+<pinref part="R3" gate="G$1" pin="1"/>
+<wire x1="121.92" y1="154.94" x2="116.84" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="160.02" x2="121.92" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="160.02" x2="121.92" y2="154.94" width="0.1524" layer="91"/>
+<junction x="121.92" y="154.94"/>
+</segment>
+<segment>
+<wire x1="116.84" y1="137.16" x2="119.38" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="137.16" x2="127" y2="137.16" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<junction x="119.38" y="137.16"/>
+<label x="116.84" y="137.16" size="1.778" layer="95"/>
+<pinref part="C15" gate="G$1" pin="2"/>
+<pinref part="C16" gate="G$1" pin="2"/>
+<wire x1="127" y1="137.16" x2="134.62" y2="137.16" width="0.1524" layer="91"/>
+<junction x="127" y="137.16"/>
+</segment>
+<segment>
+<pinref part="LM2937_3V3" gate="G$1" pin="OUT"/>
+<wire x1="73.66" y1="116.84" x2="76.2" y2="116.84" width="0.1524" layer="91"/>
+<label x="76.2" y="116.84" size="1.778" layer="95"/>
+<pinref part="C8" gate="G$1" pin="1"/>
+<wire x1="76.2" y1="116.84" x2="88.9" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="114.3" x2="76.2" y2="116.84" width="0.1524" layer="91"/>
+<junction x="76.2" y="116.84"/>
+<pinref part="C1" gate="G$1" pin="+"/>
+<wire x1="88.9" y1="114.3" x2="88.9" y2="116.84" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R8" gate="G$1" pin="1"/>
+<wire x1="-45.72" y1="15.24" x2="-35.56" y2="15.24" width="0.1524" layer="91"/>
+<label x="-43.18" y="15.24" size="1.778" layer="95"/>
+<pinref part="R9" gate="G$1" pin="1"/>
+<wire x1="-35.56" y1="15.24" x2="-33.02" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="-35.56" y1="15.24" x2="-35.56" y2="35.56" width="0.1524" layer="91"/>
+<junction x="-35.56" y="15.24"/>
+</segment>
+<segment>
+<pinref part="U$5" gate="G$1" pin="VCC"/>
+<wire x1="149.86" y1="111.76" x2="160.02" y2="111.76" width="0.1524" layer="91"/>
+<label x="154.94" y="111.76" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$5" gate="G$1" pin="HOLD"/>
+<wire x1="149.86" y1="106.68" x2="160.02" y2="106.68" width="0.1524" layer="91"/>
+<label x="154.94" y="106.68" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="GPIO" gate="G$1" pin="8"/>
+<wire x1="20.32" y1="12.7" x2="10.16" y2="12.7" width="0.1524" layer="91"/>
+<label x="10.16" y="12.7" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="RAND" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="A0_PA0"/>
+<wire x1="111.76" y1="27.94" x2="119.38" y2="27.94" width="0.1524" layer="91"/>
+<label x="114.3" y="27.94" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="R7" gate="G$1" pin="2"/>
+<pinref part="R6" gate="G$1" pin="1"/>
+<wire x1="180.34" y1="121.92" x2="180.34" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="180.34" y1="124.46" x2="180.34" y2="127" width="0.1524" layer="91"/>
+<wire x1="180.34" y1="124.46" x2="185.42" y2="124.46" width="0.1524" layer="91"/>
+<junction x="180.34" y="124.46"/>
+<label x="182.88" y="124.46" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="SDN_SI4463" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="PA_PA1"/>
+<wire x1="111.76" y1="33.02" x2="121.92" y2="33.02" width="0.1524" layer="91"/>
+<label x="114.3" y="33.02" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="SDN"/>
+<wire x1="147.32" y1="58.42" x2="134.62" y2="58.42" width="0.1524" layer="91"/>
+<label x="134.62" y="58.42" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="R5" gate="G$1" pin="2"/>
+<wire x1="134.62" y1="144.78" x2="144.78" y2="144.78" width="0.1524" layer="91"/>
+<label x="137.16" y="144.78" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="IT_SI4463" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="A2_PA3"/>
+<wire x1="111.76" y1="38.1" x2="121.92" y2="38.1" width="0.1524" layer="91"/>
+<label x="114.3" y="38.1" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="IRQ"/>
+<wire x1="147.32" y1="63.5" x2="134.62" y2="63.5" width="0.1524" layer="91"/>
+<label x="134.62" y="63.5" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="CS_SI4463" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="A3_PA4"/>
+<wire x1="111.76" y1="43.18" x2="121.92" y2="43.18" width="0.1524" layer="91"/>
+<label x="114.3" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="CS"/>
+<wire x1="147.32" y1="68.58" x2="134.62" y2="68.58" width="0.1524" layer="91"/>
+<label x="134.62" y="68.58" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="2"/>
+<wire x1="134.62" y1="154.94" x2="144.78" y2="154.94" width="0.1524" layer="91"/>
+<label x="137.16" y="154.94" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="MISO_SPI1" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="A5_PA6"/>
+<wire x1="111.76" y1="53.34" x2="119.38" y2="53.34" width="0.1524" layer="91"/>
+<label x="114.3" y="53.34" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="SDO"/>
+<wire x1="187.96" y1="63.5" x2="200.66" y2="63.5" width="0.1524" layer="91"/>
+<label x="190.5" y="63.5" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="MOSI_SPI1" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="A6_PA7"/>
+<wire x1="111.76" y1="58.42" x2="121.92" y2="58.42" width="0.1524" layer="91"/>
+<label x="114.3" y="58.42" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="SDI"/>
+<wire x1="187.96" y1="68.58" x2="200.66" y2="68.58" width="0.1524" layer="91"/>
+<label x="190.5" y="68.58" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="GND2"/>
+<wire x1="119.38" y1="78.74" x2="111.76" y2="78.74" width="0.1524" layer="91"/>
+<label x="114.3" y="78.74" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$2" gate="G$1" pin="GND1"/>
+<wire x1="68.58" y1="68.58" x2="60.96" y2="68.58" width="0.1524" layer="91"/>
+<label x="55.88" y="68.58" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="GND2"/>
+<wire x1="147.32" y1="43.18" x2="134.62" y2="43.18" width="0.1524" layer="91"/>
+<label x="134.62" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="RF_GND"/>
+<wire x1="187.96" y1="43.18" x2="198.12" y2="43.18" width="0.1524" layer="91"/>
+<label x="190.5" y="43.18" size="1.778" layer="95"/>
+<pinref part="X1" gate="G$1" pin="2"/>
+<wire x1="200.66" y1="40.64" x2="198.12" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="40.64" x2="198.12" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="GND1"/>
+<wire x1="147.32" y1="73.66" x2="134.62" y2="73.66" width="0.1524" layer="91"/>
+<label x="134.62" y="73.66" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="-17.78" y1="73.66" x2="-15.24" y2="73.66" width="0.1524" layer="91"/>
+<label x="-17.78" y="73.66" size="1.778" layer="95"/>
+<wire x1="-10.16" y1="73.66" x2="-2.54" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="2.54" y1="73.66" x2="-10.16" y2="73.66" width="0.1524" layer="91"/>
+<junction x="-15.24" y="73.66"/>
+<wire x1="-10.16" y1="73.66" x2="-15.24" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="43.18" y1="73.66" x2="40.64" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="73.66" x2="40.64" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="86.36" x2="-10.16" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="-10.16" y1="86.36" x2="-10.16" y2="73.66" width="0.1524" layer="91"/>
+<junction x="-10.16" y="73.66"/>
+<pinref part="U$1" gate="G$1" pin="GND,"/>
+<pinref part="U$1" gate="G$1" pin="GND"/>
+<wire x1="40.64" y1="73.66" x2="30.48" y2="73.66" width="0.1524" layer="91"/>
+<junction x="40.64" y="73.66"/>
+</segment>
+<segment>
+<pinref part="H2" gate="G$1" pin="MOUNT"/>
+<wire x1="-58.42" y1="83.82" x2="-60.96" y2="83.82" width="0.1524" layer="91"/>
+<label x="-63.5" y="86.36" size="1.778" layer="95"/>
+<wire x1="-60.96" y1="83.82" x2="-60.96" y2="76.2" width="0.1524" layer="91"/>
+<pinref part="H5" gate="G$1" pin="MOUNT"/>
+<wire x1="-60.96" y1="76.2" x2="-60.96" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="-60.96" y1="68.58" x2="-60.96" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="-60.96" y1="60.96" x2="-60.96" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="-60.96" y1="53.34" x2="-58.42" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="H4" gate="G$1" pin="MOUNT"/>
+<wire x1="-58.42" y1="60.96" x2="-60.96" y2="60.96" width="0.1524" layer="91"/>
+<junction x="-60.96" y="60.96"/>
+<pinref part="H3" gate="G$1" pin="MOUNT"/>
+<wire x1="-58.42" y1="68.58" x2="-60.96" y2="68.58" width="0.1524" layer="91"/>
+<junction x="-60.96" y="68.58"/>
+<pinref part="H1" gate="G$1" pin="MOUNT"/>
+<wire x1="-58.42" y1="76.2" x2="-60.96" y2="76.2" width="0.1524" layer="91"/>
+<junction x="-60.96" y="76.2"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="SHLD_2"/>
+<wire x1="167.64" y1="27.94" x2="167.64" y2="25.4" width="0.1524" layer="91"/>
+<label x="157.48" y="25.4" size="1.778" layer="95"/>
+<pinref part="C5" gate="G$1" pin="2"/>
+<wire x1="144.78" y1="27.94" x2="144.78" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="25.4" x2="167.64" y2="25.4" width="0.1524" layer="91"/>
+<pinref part="U$3" gate="SI4463" pin="SHLD_4"/>
+<wire x1="175.26" y1="27.94" x2="175.26" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="25.4" x2="167.64" y2="25.4" width="0.1524" layer="91"/>
+<junction x="167.64" y="25.4"/>
+</segment>
+<segment>
+<pinref part="U$3" gate="SI4463" pin="SHLD_1"/>
+<wire x1="167.64" y1="83.82" x2="167.64" y2="91.44" width="0.1524" layer="91"/>
+<label x="167.64" y="88.9" size="1.778" layer="95" rot="R90"/>
+<pinref part="U$3" gate="SI4463" pin="SHLD_3"/>
+<wire x1="167.64" y1="91.44" x2="167.64" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="83.82" x2="175.26" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="91.44" x2="167.64" y2="91.44" width="0.1524" layer="91"/>
+<junction x="167.64" y="91.44"/>
+</segment>
+<segment>
+<wire x1="-10.16" y1="68.58" x2="2.54" y2="68.58" width="0.1524" layer="91"/>
+<label x="-10.16" y="68.58" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="GND."/>
+</segment>
+<segment>
+<pinref part="U$4" gate="G$1" pin="IN-"/>
+<wire x1="45.72" y1="139.7" x2="38.1" y2="139.7" width="0.1524" layer="91"/>
+<label x="35.56" y="139.7" size="1.778" layer="95"/>
+<pinref part="C13" gate="G$1" pin="2"/>
+<wire x1="38.1" y1="139.7" x2="33.02" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="139.7" x2="38.1" y2="139.7" width="0.1524" layer="91"/>
+<junction x="38.1" y="139.7"/>
+<pinref part="UEXT" gate="G$1" pin="GND"/>
+<wire x1="5.08" y1="139.7" x2="17.78" y2="139.7" width="0.1524" layer="91"/>
+<label x="7.62" y="139.7" size="1.778" layer="95"/>
+<junction x="17.78" y="139.7"/>
+</segment>
+<segment>
+<pinref part="U$4" gate="G$1" pin="OUT-"/>
+<wire x1="88.9" y1="139.7" x2="93.98" y2="139.7" width="0.1524" layer="91"/>
+<label x="91.44" y="139.7" size="1.778" layer="95"/>
+<pinref part="C14" gate="G$1" pin="2"/>
+<wire x1="93.98" y1="139.7" x2="99.06" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="144.78" x2="93.98" y2="139.7" width="0.1524" layer="91"/>
+<junction x="93.98" y="139.7"/>
+</segment>
+<segment>
+<pinref part="R7" gate="G$1" pin="1"/>
+<wire x1="180.34" y1="111.76" x2="180.34" y2="106.68" width="0.1524" layer="91"/>
+<label x="180.34" y="106.68" size="1.778" layer="95" rot="R90"/>
+</segment>
+<segment>
+<wire x1="116.84" y1="127" x2="119.38" y2="127" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="127" x2="127" y2="127" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="1"/>
+<wire x1="127" y1="129.54" x2="127" y2="127" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="129.54" x2="119.38" y2="127" width="0.1524" layer="91"/>
+<junction x="119.38" y="127"/>
+<label x="132.08" y="127" size="1.778" layer="95"/>
+<pinref part="C15" gate="G$1" pin="1"/>
+<wire x1="142.24" y1="129.54" x2="142.24" y2="127" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="127" x2="134.62" y2="127" width="0.1524" layer="91"/>
+<junction x="127" y="127"/>
+<pinref part="C16" gate="G$1" pin="1"/>
+<wire x1="134.62" y1="127" x2="127" y2="127" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="129.54" x2="134.62" y2="127" width="0.1524" layer="91"/>
+<junction x="134.62" y="127"/>
+</segment>
+<segment>
+<label x="2.54" y="-7.366" size="1.778" layer="95" rot="R90"/>
+<wire x1="0" y1="15.24" x2="0" y2="7.62" width="0.1524" layer="91"/>
+<wire x1="0" y1="7.62" x2="0" y2="0" width="0.1524" layer="91"/>
+<wire x1="0" y1="0" x2="0" y2="-7.62" width="0.1524" layer="91"/>
+<junction x="0" y="7.62"/>
+<junction x="0" y="0"/>
+<pinref part="T1" gate="G$1" pin="E"/>
+<wire x1="0" y1="15.24" x2="0" y2="35.56" width="0.1524" layer="91"/>
+<junction x="0" y="15.24"/>
+<pinref part="LED1" gate="G$1" pin="K1"/>
+<wire x1="-5.08" y1="2.54" x2="-5.08" y2="0" width="0.1524" layer="91"/>
+<wire x1="-5.08" y1="0" x2="0" y2="0" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="K2"/>
+<wire x1="-5.08" y1="7.62" x2="0" y2="7.62" width="0.1524" layer="91"/>
+<pinref part="LED2" gate="G$1" pin="K1"/>
+<wire x1="-15.24" y1="30.48" x2="-15.24" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="-15.24" y1="15.24" x2="0" y2="15.24" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="-30.48" y1="109.22" x2="-30.48" y2="106.68" width="0.1524" layer="91"/>
+<label x="-30.48" y="106.68" size="1.778" layer="95" rot="R270"/>
+<pinref part="C6" gate="G$1" pin="2"/>
+<wire x1="-30.48" y1="106.68" x2="-30.48" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="-30.48" y1="106.68" x2="-45.72" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="-45.72" y1="106.68" x2="-45.72" y2="111.76" width="0.1524" layer="91"/>
+<junction x="-30.48" y="106.68"/>
+<wire x1="-30.48" y1="106.68" x2="-15.24" y2="106.68" width="0.1524" layer="91"/>
+<pinref part="C7" gate="G$1" pin="2"/>
+<wire x1="-15.24" y1="106.68" x2="-15.24" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="L4940_5V" gate="G$1" pin="GND"/>
+<pinref part="C12" gate="G$1" pin="-"/>
+<wire x1="-58.42" y1="109.22" x2="-58.42" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="-58.42" y1="106.68" x2="-45.72" y2="106.68" width="0.1524" layer="91"/>
+<junction x="-45.72" y="106.68"/>
+<pinref part="C11" gate="G$1" pin="-"/>
+<wire x1="7.62" y1="109.22" x2="7.62" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="7.62" y1="106.68" x2="-15.24" y2="106.68" width="0.1524" layer="91"/>
+<junction x="-15.24" y="106.68"/>
+</segment>
+<segment>
+<pinref part="C3" gate="G$1" pin="1"/>
+<wire x1="134.62" y1="10.16" x2="134.62" y2="5.08" width="0.1524" layer="91"/>
+<label x="134.62" y="5.08" size="1.778" layer="95" rot="R90"/>
+</segment>
+<segment>
+<pinref part="LM2937_3V3" gate="G$1" pin="GND"/>
+<wire x1="60.96" y1="106.68" x2="60.96" y2="104.14" width="0.1524" layer="91"/>
+<label x="60.96" y="104.14" size="1.778" layer="95" rot="R270"/>
+<wire x1="60.96" y1="104.14" x2="60.96" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="104.14" x2="76.2" y2="104.14" width="0.1524" layer="91"/>
+<junction x="60.96" y="104.14"/>
+<wire x1="76.2" y1="104.14" x2="88.9" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="104.14" x2="48.26" y2="104.14" width="0.1524" layer="91"/>
+<pinref part="C9" gate="G$1" pin="2"/>
+<wire x1="48.26" y1="104.14" x2="40.64" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="106.68" x2="48.26" y2="104.14" width="0.1524" layer="91"/>
+<junction x="48.26" y="104.14"/>
+<pinref part="C8" gate="G$1" pin="2"/>
+<wire x1="76.2" y1="106.68" x2="76.2" y2="104.14" width="0.1524" layer="91"/>
+<junction x="76.2" y="104.14"/>
+<pinref part="C10" gate="G$1" pin="-"/>
+<wire x1="40.64" y1="106.68" x2="40.64" y2="104.14" width="0.1524" layer="91"/>
+<pinref part="C1" gate="G$1" pin="-"/>
+<wire x1="88.9" y1="106.68" x2="88.9" y2="104.14" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$2" gate="G$1" pin="SHLD"/>
+<wire x1="91.44" y1="5.08" x2="91.44" y2="-5.08" width="0.1524" layer="91"/>
+<label x="91.44" y="-5.08" size="1.778" layer="95" rot="R90"/>
+</segment>
+<segment>
+<pinref part="U$5" gate="G$1" pin="GND"/>
+<wire x1="114.3" y1="96.52" x2="106.68" y2="96.52" width="0.1524" layer="91"/>
+<label x="106.68" y="96.52" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="GPIO" gate="G$1" pin="6"/>
+<wire x1="20.32" y1="10.16" x2="10.16" y2="10.16" width="0.1524" layer="91"/>
+<wire x1="10.16" y1="10.16" x2="10.16" y2="7.62" width="0.1524" layer="91"/>
+<pinref part="GPIO" gate="G$1" pin="4"/>
+<wire x1="10.16" y1="7.62" x2="20.32" y2="7.62" width="0.1524" layer="91"/>
+<label x="12.7" y="10.16" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="GPIO_10" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D1_PA9"/>
+<wire x1="68.58" y1="83.82" x2="60.96" y2="83.82" width="0.1524" layer="91"/>
+<label x="55.88" y="83.82" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="GPIO" gate="G$1" pin="3"/>
+<wire x1="35.56" y1="7.62" x2="43.18" y2="7.62" width="0.1524" layer="91"/>
+<label x="38.1" y="7.62" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="GPIO_11" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D0_PA10"/>
+<wire x1="68.58" y1="78.74" x2="60.96" y2="78.74" width="0.1524" layer="91"/>
+<label x="55.88" y="78.74" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="GPIO" gate="G$1" pin="5"/>
+<wire x1="35.56" y1="10.16" x2="43.18" y2="10.16" width="0.1524" layer="91"/>
+<label x="38.1" y="10.16" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="MISO_SPI3" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D12_PB4"/>
+<wire x1="68.58" y1="12.7" x2="60.96" y2="12.7" width="0.1524" layer="91"/>
+<label x="55.88" y="12.7" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="55.88" y1="48.26" x2="30.48" y2="48.26" width="0.1524" layer="91"/>
+<label x="45.72" y="48.26" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="MISO"/>
+</segment>
+<segment>
+<pinref part="U$5" gate="G$1" pin="MISO"/>
+<wire x1="114.3" y1="106.68" x2="106.68" y2="106.68" width="0.1524" layer="91"/>
+<label x="106.68" y="106.68" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="MOSI_SPI3" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D11_PB5"/>
+<wire x1="68.58" y1="17.78" x2="55.88" y2="17.78" width="0.1524" layer="91"/>
+<label x="55.88" y="17.78" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="-2.54" y1="63.5" x2="-15.24" y2="63.5" width="0.1524" layer="91"/>
+<label x="-17.78" y="63.5" size="1.778" layer="95"/>
+<wire x1="-15.24" y1="63.5" x2="-17.78" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="-15.24" y1="63.5" x2="2.54" y2="63.5" width="0.1524" layer="91"/>
+<junction x="-15.24" y="63.5"/>
+<pinref part="U$1" gate="G$1" pin="MOSI"/>
+</segment>
+<segment>
+<pinref part="U$5" gate="G$1" pin="MOSI"/>
+<wire x1="149.86" y1="96.52" x2="160.02" y2="96.52" width="0.1524" layer="91"/>
+<label x="154.94" y="96.52" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="CS_W5500" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D10_PA11"/>
+<wire x1="68.58" y1="22.86" x2="55.88" y2="22.86" width="0.1524" layer="91"/>
+<label x="55.88" y="22.86" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="-2.54" y1="53.34" x2="-15.24" y2="53.34" width="0.1524" layer="91"/>
+<label x="-17.78" y="53.34" size="1.778" layer="95"/>
+<wire x1="-15.24" y1="53.34" x2="-17.78" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="-15.24" y1="53.34" x2="2.54" y2="53.34" width="0.1524" layer="91"/>
+<junction x="-15.24" y="53.34"/>
+<pinref part="U$1" gate="G$1" pin="CS"/>
+</segment>
+<segment>
+<pinref part="R4" gate="G$1" pin="2"/>
+<wire x1="134.62" y1="149.86" x2="144.78" y2="149.86" width="0.1524" layer="91"/>
+<label x="137.16" y="149.86" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="IT_W5500" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D9_PA8"/>
+<wire x1="68.58" y1="27.94" x2="55.88" y2="27.94" width="0.1524" layer="91"/>
+<label x="55.88" y="27.94" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="2.54" y1="48.26" x2="-15.24" y2="48.26" width="0.1524" layer="91"/>
+<label x="-15.24" y="48.26" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="INT"/>
+</segment>
+</net>
+<net name="LED_RX" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="D6_PB1"/>
+<wire x1="68.58" y1="43.18" x2="55.88" y2="43.18" width="0.1524" layer="91"/>
+<label x="55.88" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="R10" gate="G$1" pin="1"/>
+<wire x1="-30.48" y1="7.62" x2="-25.4" y2="7.62" width="0.1524" layer="91"/>
+<label x="-35.56" y="7.62" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="RF_VCC" class="0">
+<segment>
+<pinref part="U$3" gate="SI4463" pin="VCC"/>
+<wire x1="147.32" y1="38.1" x2="144.78" y2="38.1" width="0.1524" layer="91"/>
+<label x="134.62" y="38.1" size="1.778" layer="95"/>
+<pinref part="C5" gate="G$1" pin="1"/>
+<wire x1="144.78" y1="38.1" x2="134.62" y2="38.1" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="35.56" x2="144.78" y2="38.1" width="0.1524" layer="91"/>
+<junction x="144.78" y="38.1"/>
+</segment>
+<segment>
+<pinref part="C11" gate="G$1" pin="+"/>
+<wire x1="7.62" y1="116.84" x2="7.62" y2="119.38" width="0.1524" layer="91"/>
+<pinref part="SB3" gate="G$1" pin="1"/>
+<wire x1="0" y1="119.38" x2="7.62" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="7.62" y1="119.38" x2="7.62" y2="129.54" width="0.1524" layer="91"/>
+<junction x="7.62" y="119.38"/>
+<pinref part="SB4" gate="G$1" pin="1"/>
+<wire x1="7.62" y1="129.54" x2="0" y2="129.54" width="0.1524" layer="91"/>
+<label x="2.54" y="129.54" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="CLK_SPI1" class="0">
+<segment>
+<pinref part="U$3" gate="SI4463" pin="CLK"/>
+<wire x1="187.96" y1="73.66" x2="200.66" y2="73.66" width="0.1524" layer="91"/>
+<label x="190.5" y="73.66" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$2" gate="G$1" pin="A4_PA5"/>
+<wire x1="111.76" y1="48.26" x2="119.38" y2="48.26" width="0.1524" layer="91"/>
+<label x="114.3" y="48.26" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="GPIO_0" class="0">
+<segment>
+<label x="190.5" y="53.34" size="1.778" layer="95"/>
+<wire x1="187.96" y1="53.34" x2="200.66" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="U$3" gate="SI4463" pin="GPIO_0"/>
+</segment>
+<segment>
+<pinref part="GPIO" gate="G$1" pin="7"/>
+<wire x1="35.56" y1="12.7" x2="43.18" y2="12.7" width="0.1524" layer="91"/>
+<label x="38.1" y="12.7" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="LED_TX" class="0">
+<segment>
+<label x="190.5" y="58.42" size="1.778" layer="95"/>
+<wire x1="187.96" y1="58.42" x2="200.66" y2="58.42" width="0.1524" layer="91"/>
+<pinref part="U$3" gate="SI4463" pin="GPIO_1"/>
+</segment>
+<segment>
+<pinref part="R12" gate="G$1" pin="1"/>
+<wire x1="12.7" y1="27.94" x2="17.78" y2="27.94" width="0.1524" layer="91"/>
+<label x="12.446" y="28.702" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="RF_OUT" class="0">
+<segment>
+<pinref part="U$3" gate="SI4463" pin="ANT"/>
+<wire x1="187.96" y1="38.1" x2="200.66" y2="38.1" width="0.1524" layer="91"/>
+<label x="190.5" y="38.1" size="1.778" layer="95"/>
+<pinref part="X1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="6V" class="0">
+<segment>
+<pinref part="U$4" gate="G$1" pin="OUT+"/>
+<wire x1="88.9" y1="154.94" x2="93.98" y2="154.94" width="0.1524" layer="91"/>
+<label x="91.44" y="162.56" size="1.778" layer="95"/>
+<pinref part="C14" gate="G$1" pin="1"/>
+<wire x1="93.98" y1="154.94" x2="99.06" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="152.4" x2="93.98" y2="154.94" width="0.1524" layer="91"/>
+<junction x="93.98" y="154.94"/>
+<pinref part="SB2" gate="G$1" pin="1"/>
+<wire x1="83.82" y1="162.56" x2="93.98" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="162.56" x2="93.98" y2="154.94" width="0.1524" layer="91"/>
+<label x="96.52" y="154.94" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="-40.64" y1="119.38" x2="-45.72" y2="119.38" width="0.1524" layer="91"/>
+<label x="-48.26" y="119.38" size="1.778" layer="95"/>
+<pinref part="C6" gate="G$1" pin="1"/>
+<junction x="-45.72" y="119.38"/>
+<pinref part="L4940_5V" gate="G$1" pin="IN"/>
+<pinref part="C12" gate="G$1" pin="+"/>
+<wire x1="-58.42" y1="116.84" x2="-58.42" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="-58.42" y1="119.38" x2="-45.72" y2="119.38" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="D1" gate="G$1" pin="A"/>
+<wire x1="30.48" y1="116.84" x2="25.4" y2="116.84" width="0.1524" layer="91"/>
+<label x="25.4" y="116.84" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="3V3NUCLEO" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="3V3"/>
+<pinref part="R1" gate="G$1" pin="1"/>
+<wire x1="111.76" y1="17.78" x2="134.62" y2="17.78" width="0.1524" layer="91"/>
+<label x="111.76" y="17.78" size="1.778" layer="95"/>
+<pinref part="C3" gate="G$1" pin="2"/>
+<wire x1="134.62" y1="17.78" x2="142.24" y2="17.78" width="0.1524" layer="91"/>
+<junction x="134.62" y="17.78"/>
+</segment>
+<segment>
+<pinref part="R6" gate="G$1" pin="2"/>
+<wire x1="180.34" y1="137.16" x2="180.34" y2="147.32" width="0.1524" layer="91"/>
+<label x="180.34" y="142.24" size="1.778" layer="95" rot="R90"/>
+</segment>
+<segment>
+<pinref part="R5" gate="G$1" pin="1"/>
+<wire x1="124.46" y1="144.78" x2="119.38" y2="144.78" width="0.1524" layer="91"/>
+<label x="114.3" y="144.78" size="1.778" layer="95"/>
+<pinref part="R4" gate="G$1" pin="1"/>
+<wire x1="119.38" y1="144.78" x2="111.76" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="149.86" x2="119.38" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="149.86" x2="119.38" y2="144.78" width="0.1524" layer="91"/>
+<junction x="119.38" y="144.78"/>
+</segment>
+</net>
+<net name="LED-TX" class="0">
+<segment>
+<pinref part="R9" gate="G$1" pin="2"/>
+<wire x1="-25.4" y1="35.56" x2="-22.86" y2="35.56" width="0.1524" layer="91"/>
+<pinref part="LED2" gate="G$1" pin="A2"/>
+</segment>
+</net>
+<net name="LED-RX" class="0">
+<segment>
+<pinref part="R10" gate="G$1" pin="2"/>
+<pinref part="LED1" gate="G$1" pin="A2"/>
+<wire x1="-12.7" y1="7.62" x2="-15.24" y2="7.62" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="LED-CON" class="0">
+<segment>
+<pinref part="R11" gate="G$1" pin="2"/>
+<wire x1="-15.24" y1="0" x2="-12.7" y2="0" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="A1"/>
+<wire x1="-12.7" y1="0" x2="-12.7" y2="2.54" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="LED_CON" class="0">
+<segment>
+<pinref part="R11" gate="G$1" pin="1"/>
+<wire x1="-30.48" y1="0" x2="-25.4" y2="0" width="0.1524" layer="91"/>
+<label x="-35.56" y="0" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$2" gate="G$1" pin="D2_PA12"/>
+<wire x1="68.58" y1="63.5" x2="55.88" y2="63.5" width="0.1524" layer="91"/>
+<label x="55.88" y="63.5" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="LED..TX" class="0">
+<segment>
+<pinref part="T1" gate="G$1" pin="C"/>
+<wire x1="-15.24" y1="35.56" x2="-10.16" y2="35.56" width="0.1524" layer="91"/>
+<pinref part="LED2" gate="G$1" pin="K2"/>
+</segment>
+</net>
+<net name="LED.TX" class="0">
+<segment>
+<pinref part="T1" gate="G$1" pin="B"/>
+<wire x1="-5.08" y1="30.48" x2="-5.08" y2="27.94" width="0.1524" layer="91"/>
+<pinref part="R12" gate="G$1" pin="2"/>
+<wire x1="-5.08" y1="27.94" x2="2.54" y2="27.94" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$1" class="0">
+<segment>
+<pinref part="R8" gate="G$1" pin="2"/>
+<pinref part="LED2" gate="G$1" pin="A1"/>
+<wire x1="-22.86" y1="15.24" x2="-22.86" y2="30.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="CS_SRAM" class="0">
+<segment>
+<pinref part="U$5" gate="G$1" pin="CS"/>
+<wire x1="114.3" y1="111.76" x2="106.68" y2="111.76" width="0.1524" layer="91"/>
+<label x="106.68" y="111.76" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$2" gate="G$1" pin="D3_PB0"/>
+<wire x1="68.58" y1="58.42" x2="55.88" y2="58.42" width="0.1524" layer="91"/>
+<label x="55.88" y="58.42" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="R3" gate="G$1" pin="2"/>
+<wire x1="134.62" y1="160.02" x2="144.78" y2="160.02" width="0.1524" layer="91"/>
+<label x="137.16" y="160.02" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="UEXT" class="0">
+<segment>
+<pinref part="UEXT" gate="G$1" pin="+"/>
+<wire x1="5.08" y1="144.78" x2="12.7" y2="144.78" width="0.1524" layer="91"/>
+<label x="7.62" y="144.78" size="1.778" layer="95"/>
+<wire x1="12.7" y1="144.78" x2="12.7" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="12.7" y1="154.94" x2="17.78" y2="154.94" width="0.1524" layer="91"/>
+<pinref part="C13" gate="G$1" pin="1"/>
+<wire x1="17.78" y1="154.94" x2="17.78" y2="147.32" width="0.1524" layer="91"/>
+<pinref part="SB1" gate="G$1" pin="2"/>
+<wire x1="20.32" y1="154.94" x2="17.78" y2="154.94" width="0.1524" layer="91"/>
+<junction x="17.78" y="154.94"/>
+</segment>
+<segment>
+<pinref part="SB2" gate="G$1" pin="2"/>
+<wire x1="73.66" y1="162.56" x2="63.5" y2="162.56" width="0.1524" layer="91"/>
+<label x="66.04" y="162.56" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="SB4" gate="G$1" pin="2"/>
+<wire x1="-10.16" y1="129.54" x2="-17.78" y2="129.54" width="0.1524" layer="91"/>
+<label x="-17.78" y="129.54" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="12V" class="0">
+<segment>
+<pinref part="U$4" gate="G$1" pin="IN+"/>
+<wire x1="45.72" y1="154.94" x2="30.48" y2="154.94" width="0.1524" layer="91"/>
+<label x="33.02" y="154.94" size="1.778" layer="95"/>
+<pinref part="SB1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="5V" class="0">
+<segment>
+<pinref part="L4940_5V" gate="G$1" pin="OUT"/>
+<pinref part="SB3" gate="G$1" pin="2"/>
+<wire x1="-17.78" y1="119.38" x2="-15.24" y2="119.38" width="0.1524" layer="91"/>
+<pinref part="C7" gate="G$1" pin="1"/>
+<wire x1="-15.24" y1="119.38" x2="-10.16" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="-15.24" y1="116.84" x2="-15.24" y2="119.38" width="0.1524" layer="91"/>
+<junction x="-15.24" y="119.38"/>
+<label x="-15.24" y="119.38" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="3VREGIN" class="0">
+<segment>
+<pinref part="LM2937_3V3" gate="G$1" pin="IN"/>
+<wire x1="50.8" y1="116.84" x2="48.26" y2="116.84" width="0.1524" layer="91"/>
+<pinref part="C10" gate="G$1" pin="+"/>
+<wire x1="48.26" y1="116.84" x2="40.64" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="116.84" x2="40.64" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="C9" gate="G$1" pin="1"/>
+<wire x1="48.26" y1="114.3" x2="48.26" y2="116.84" width="0.1524" layer="91"/>
+<junction x="48.26" y="116.84"/>
+<label x="40.64" y="116.84" size="1.778" layer="95"/>
+<pinref part="D1" gate="G$1" pin="C"/>
+<wire x1="35.56" y1="116.84" x2="40.64" y2="116.84" width="0.1524" layer="91"/>
+<junction x="40.64" y="116.84"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+<note version="8.2" severity="warning">
+Since Version 8.2, EAGLE supports online libraries. The ids
+of those online libraries will not be understood (or retained)
+with this version.
+</note>
+<note version="8.3" severity="warning">
+Since Version 8.3, EAGLE supports URNs for individual library
+assets (packages, symbols, and devices). The URNs of those assets
+will not be understood (or retained) with this version.
+</note>
+<note version="8.3" severity="warning">
+Since Version 8.3, EAGLE supports the association of 3D packages
+with devices in libraries, schematics, and board files. Those 3D
+packages will not be understood (or retained) with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/NPR70_modem_v05_PCB/eagle/NPR_70.lbr b/NPR70_modem_v05_PCB/eagle/NPR_70.lbr
new file mode 100755
index 0000000..d7e0015
--- /dev/null
+++ b/NPR70_modem_v05_PCB/eagle/NPR_70.lbr
@@ -0,0 +1,1488 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="8.5.1">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="50" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="5" altunitdist="mil" altunit="mil"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/>
+<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="24" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="88" name="SimResults" color="9" fill="1" visible="yes" active="yes"/>
+<layer number="89" name="SimProbes" color="9" fill="1" visible="yes" active="yes"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="99" name="SpiceOrder" color="5" fill="1" visible="yes" active="yes"/>
+</layers>
+<library>
+<packages>
+<package name="DIL16">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="10.16" y1="2.921" x2="-10.16" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="2.921" x2="-10.16" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="-10.16" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="1.016" x2="-10.16" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-10.541" y="-2.921" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-7.493" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="DIL40">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="25.4" y1="6.731" x2="-25.4" y2="6.731" width="0.1524" layer="21"/>
+<wire x1="-25.4" y1="-6.731" x2="25.4" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="25.4" y1="6.731" x2="25.4" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="-25.4" y1="6.731" x2="-25.4" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-25.4" y1="-6.731" x2="-25.4" y2="-1.143" width="0.1524" layer="21"/>
+<wire x1="-25.4" y1="0.889" x2="-25.4" y2="-1.143" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-24.13" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-21.59" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-19.05" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="19.05" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="21.59" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="24.13" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="24.13" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="21.59" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="19.05" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="25" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="26" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="27" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="28" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="29" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="30" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="31" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="32" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="33" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="34" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="35" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="36" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="37" x="-16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="38" x="-19.05" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="39" x="-21.59" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="40" x="-24.13" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-25.908" y="-6.604" size="1.778" layer="25" rot="R90">&gt;NAME</text>
+<text x="-17.145" y="-1.016" size="1.778" layer="27">&gt;VALUE</text>
+</package>
+<package name="RF4463F30">
+<smd name="8" x="-19" y="4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="7" x="-19" y="0" dx="2.54" dy="1.27" layer="1"/>
+<smd name="6" x="-19" y="-4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="5" x="-19" y="-8" dx="2.54" dy="1.27" layer="1"/>
+<smd name="4" x="-19" y="-12" dx="2.54" dy="1.27" layer="1"/>
+<smd name="3" x="-19" y="-16" dx="2.54" dy="1.27" layer="1"/>
+<smd name="2" x="-19" y="-20" dx="2.54" dy="1.27" layer="1"/>
+<smd name="1" x="-19" y="-24" dx="2.54" dy="1.27" layer="1"/>
+<smd name="16" x="1" y="-24" dx="2.54" dy="1.27" layer="1"/>
+<smd name="15" x="1" y="-20" dx="2.54" dy="1.27" layer="1"/>
+<smd name="14" x="1" y="-16" dx="2.54" dy="1.27" layer="1"/>
+<smd name="13" x="1" y="-12" dx="2.54" dy="1.27" layer="1"/>
+<smd name="12" x="1" y="-8" dx="2.54" dy="1.27" layer="1"/>
+<smd name="11" x="1" y="-4" dx="2.54" dy="1.27" layer="1"/>
+<smd name="10" x="1" y="0" dx="2.54" dy="1.27" layer="1"/>
+<smd name="9" x="1" y="4" dx="2.54" dy="1.27" layer="1"/>
+<text x="-7.65" y="-17.86" size="1.778" layer="25" rot="R90">RF4463F30</text>
+<circle x="-16" y="-26" radius="1" width="0.127" layer="21"/>
+<smd name="SHLD_1" x="-6" y="9" dx="2.54" dy="2.54" layer="1"/>
+<smd name="SHLD_2" x="-10.5" y="-29" dx="2.54" dy="2.54" layer="1"/>
+<wire x1="-19" y1="9" x2="-9" y2="9" width="0.1524" layer="21"/>
+<wire x1="-3" y1="9" x2="1" y2="9" width="0.1524" layer="21"/>
+<wire x1="-19" y1="6" x2="-19" y2="9" width="0.1524" layer="21"/>
+<wire x1="-19" y1="2.5" x2="-19" y2="1.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-1.5" x2="-19" y2="-2.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-5.5" x2="-19" y2="-6.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-9.5" x2="-19" y2="-10.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-13.5" x2="-19" y2="-14.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-17.5" x2="-19" y2="-18.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-21.5" x2="-19" y2="-22.5" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-26" x2="-19" y2="-29" width="0.1524" layer="21"/>
+<wire x1="-19" y1="-29" x2="-13" y2="-29" width="0.1524" layer="21"/>
+<wire x1="-8" y1="-29" x2="1" y2="-29" width="0.1524" layer="21"/>
+<wire x1="1" y1="-29" x2="1" y2="-26" width="0.1524" layer="21"/>
+<wire x1="1" y1="-22.5" x2="1" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-18.5" x2="1" y2="-17.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-14.5" x2="1" y2="-13.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-10.5" x2="1" y2="-9.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-6.5" x2="1" y2="-5.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="-2.5" x2="1" y2="-1.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="1.5" x2="1" y2="2.5" width="0.1524" layer="21"/>
+<wire x1="1" y1="6" x2="1" y2="9" width="0.1524" layer="21"/>
+<pad name="SHLD_4" x="-14.25" y="-15.5" drill="1" shape="long" rot="R90" thermals="no"/>
+<pad name="SHLD_3" x="-14.25" y="-12" drill="1" shape="long" rot="R90" thermals="no"/>
+</package>
+<package name="STM_NUCLEO32">
+<pad name="1" x="-7.62" y="17.78" drill="0.9" shape="offset"/>
+<pad name="2" x="-7.62" y="15.24" drill="0.9" shape="offset"/>
+<pad name="3" x="-7.62" y="12.7" drill="0.9" shape="offset"/>
+<pad name="4" x="-7.62" y="10.16" drill="0.9" shape="offset"/>
+<pad name="5" x="-7.62" y="7.62" drill="0.9" shape="offset"/>
+<pad name="6" x="-7.62" y="5.08" drill="0.9" shape="offset"/>
+<pad name="7" x="-7.62" y="2.54" drill="0.9" shape="offset"/>
+<pad name="8" x="-7.62" y="0" drill="0.9" shape="offset"/>
+<pad name="9" x="-7.62" y="-2.54" drill="0.9" shape="offset"/>
+<pad name="10" x="-7.62" y="-5.08" drill="0.9" shape="offset"/>
+<pad name="11" x="-7.62" y="-7.62" drill="0.9" shape="offset"/>
+<pad name="12" x="-7.62" y="-10.16" drill="0.9" shape="offset"/>
+<pad name="13" x="-7.62" y="-12.7" drill="0.9" shape="offset"/>
+<pad name="18" x="7.62" y="-12.7" drill="0.9" shape="offset" rot="R180"/>
+<pad name="19" x="7.62" y="-10.16" drill="0.9" shape="offset" rot="R180"/>
+<pad name="20" x="7.62" y="-7.62" drill="0.9" shape="offset" rot="R180"/>
+<pad name="21" x="7.62" y="-5.08" drill="0.9" shape="offset" rot="R180"/>
+<pad name="22" x="7.62" y="-2.54" drill="0.9" shape="offset" rot="R180"/>
+<pad name="23" x="7.62" y="0" drill="0.9" shape="offset" rot="R180"/>
+<pad name="24" x="7.62" y="2.54" drill="0.9" shape="offset" rot="R180"/>
+<pad name="25" x="7.62" y="5.08" drill="0.9" shape="offset" rot="R180"/>
+<pad name="26" x="7.62" y="7.62" drill="0.9" shape="offset" rot="R180"/>
+<pad name="27" x="7.62" y="10.16" drill="0.9" shape="offset" rot="R180"/>
+<pad name="28" x="7.62" y="12.7" drill="0.9" shape="offset" rot="R180"/>
+<pad name="29" x="7.62" y="15.24" drill="0.9" shape="offset" rot="R180"/>
+<pad name="30" x="7.62" y="17.78" drill="0.9" shape="offset" rot="R180"/>
+<pad name="14" x="-7.62" y="-15.24" drill="0.9" shape="offset"/>
+<pad name="15" x="-7.62" y="-17.78" drill="0.9" shape="offset"/>
+<pad name="17" x="7.62" y="-15.24" drill="0.9" shape="offset" rot="R180"/>
+<pad name="16" x="7.62" y="-17.78" drill="0.9" shape="offset" rot="R180"/>
+<text x="3.175" y="-4.445" size="2.54" layer="21" rot="R90">NUCLEO
+L432KC</text>
+<text x="-6.35" y="20.955" size="1.778" layer="21">D1</text>
+<text x="3.175" y="20.955" size="1.778" layer="21">VIN</text>
+<text x="-5.715" y="-22.225" size="1.778" layer="21">D12</text>
+<text x="1.905" y="-22.225" size="1.778" layer="21">D13</text>
+<pad name="SHLD" x="3.175" y="-25.4" drill="0.9" shape="long"/>
+<wire x1="-9.525" y1="-24.13" x2="-9.525" y2="-21.59" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="27.305" x2="-9.525" y2="25.4" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="27.305" x2="-7.62" y2="27.305" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="27.305" x2="7.62" y2="27.305" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="-24.13" x2="-7.62" y2="-24.13" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="-24.13" x2="9.525" y2="-24.13" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="-24.13" x2="9.525" y2="-22.225" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="25.4" x2="9.525" y2="27.305" width="0.1524" layer="21"/>
+</package>
+<package name="ETH_WIZ_CLICK">
+<pad name="P$1" x="-12.7" y="10.16" drill="0.9" shape="long"/>
+<pad name="P$2" x="-12.7" y="7.62" drill="0.9" shape="long"/>
+<pad name="P$3" x="-12.7" y="5.08" drill="0.9" shape="long"/>
+<pad name="P$4" x="-12.7" y="2.54" drill="0.9" shape="long"/>
+<pad name="P$5" x="-12.7" y="0" drill="0.9" shape="long"/>
+<pad name="P$6" x="-12.7" y="-2.54" drill="0.9" shape="long"/>
+<pad name="P$7" x="-12.7" y="-5.08" drill="0.9" shape="long"/>
+<pad name="P$8" x="-12.7" y="-7.62" drill="0.9" shape="long"/>
+<pad name="P$9" x="10.16" y="-7.62" drill="0.9" shape="long"/>
+<pad name="P$10" x="10.16" y="-5.08" drill="0.9" shape="long"/>
+<pad name="P$11" x="10.16" y="-2.54" drill="0.9" shape="long"/>
+<pad name="P$12" x="10.16" y="0" drill="0.9" shape="long"/>
+<pad name="P$13" x="10.16" y="2.54" drill="0.9" shape="long"/>
+<pad name="P$14" x="10.16" y="5.08" drill="0.9" shape="long"/>
+<pad name="P$15" x="10.16" y="7.62" drill="0.9" shape="long"/>
+<pad name="P$16" x="10.16" y="10.16" drill="0.9" shape="long"/>
+<wire x1="-13.97" y1="13.97" x2="11.43" y2="13.97" width="0.1524" layer="21"/>
+<wire x1="11.43" y1="13.97" x2="11.43" y2="-43.18" width="0.1524" layer="21"/>
+<wire x1="11.43" y1="-43.18" x2="-13.97" y2="-43.18" width="0.1524" layer="21"/>
+<wire x1="-13.97" y1="-43.18" x2="-13.97" y2="13.97" width="0.1524" layer="21"/>
+<text x="1.27" y="-34.29" size="2.54" layer="21" rot="R90">ETH WIZ click
+W5500</text>
+<pad name="SHLD" x="12.7" y="-27.94" drill="0.9" shape="long"/>
+</package>
+<package name="VOLT_REGUL">
+<pad name="IN-" x="-8.5" y="20" drill="1" shape="offset"/>
+<pad name="IN+" x="8.5" y="20" drill="1" shape="offset" rot="R180"/>
+<pad name="OUT-" x="-8.5" y="-19.5" drill="1" shape="offset"/>
+<pad name="OUT+" x="8.5" y="-19.5" drill="1" shape="offset" rot="R180"/>
+<wire x1="10.5" y1="22" x2="-10.5" y2="22" width="0.1524" layer="21"/>
+<wire x1="-10.5" y1="22" x2="-10.5" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="-10.5" y1="-21.5" x2="10.5" y2="-21.5" width="0.1524" layer="21"/>
+<wire x1="10.5" y1="-21.5" x2="10.5" y2="22" width="0.1524" layer="21"/>
+<text x="2" y="-7" size="1.778" layer="21" rot="R90">VOLTAGE 
+REGULATOR</text>
+<text x="-8.5" y="16" size="1.778" layer="21">IN -</text>
+<text x="4" y="16" size="1.778" layer="21">IN +</text>
+<text x="8" y="-16.5" size="1.778" layer="21" rot="R90">OUT +</text>
+<text x="-6.5" y="-17" size="1.778" layer="21" rot="R90">OUT -</text>
+<rectangle x1="3.81" y1="-16.51" x2="10.16" y2="-1.27" layer="41"/>
+</package>
+<package name="DIL8">
+<description>&lt;B&gt;Dual In Line&lt;/B&gt;&lt;p&gt;
+package type P</description>
+<wire x1="-5.08" y1="-0.635" x2="-5.08" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.635" x2="-5.08" y2="0.635" width="0.1524" layer="21" curve="180"/>
+<wire x1="5.08" y1="-2.54" x2="-5.08" y2="-2.54" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-2.54" x2="5.08" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="2.54" x2="5.08" y2="2.54" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="2.54" x2="-5.08" y2="0.635" width="0.1524" layer="21"/>
+<pad name="1" x="-3.81" y="-3.81" drill="0.9" shape="long" rot="R90" first="yes"/>
+<pad name="2" x="-1.27" y="-3.81" drill="0.9" shape="long" rot="R90"/>
+<pad name="3" x="1.27" y="-3.81" drill="0.9" shape="long" rot="R90"/>
+<pad name="4" x="3.81" y="-3.81" drill="0.9" shape="long" rot="R90"/>
+<pad name="5" x="3.81" y="3.81" drill="0.9" shape="long" rot="R90"/>
+<pad name="6" x="1.27" y="3.81" drill="0.9" shape="long" rot="R90"/>
+<pad name="7" x="-1.27" y="3.81" drill="0.9" shape="long" rot="R90"/>
+<pad name="8" x="-3.81" y="3.81" drill="0.9" shape="long" rot="R90"/>
+<text x="-3.81" y="-1.27" size="1.778" layer="21">SRAM</text>
+</package>
+<package name="CON_5V">
+<pad name="P$1" x="0" y="2.54" drill="1" shape="long"/>
+<pad name="P$2" x="2.8575" y="-0.3175" drill="1" shape="long" rot="R90"/>
+<pad name="P$3" x="0" y="-2.54" drill="1" shape="long"/>
+<wire x1="-2.54" y1="2.54" x2="-2.54" y2="-8.89" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-8.89" x2="2.54" y2="-8.89" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-8.89" x2="2.54" y2="-3.81" width="0.1524" layer="21"/>
+</package>
+<package name="733989-5">
+<description>&lt;b&gt;FEMALE PRINT CONNECTOR&lt;/b&gt;&lt;p&gt;
+Außen-Ø 4,2 mm, Innen 1.1 mm&lt;br&gt;
+FUK HING Industries, distributor Conrad</description>
+<wire x1="-2.4" y1="-4.98" x2="2.4" y2="-4.98" width="0.2032" layer="21"/>
+<wire x1="2.4" y1="-4.98" x2="2.4" y2="5.92" width="0.2032" layer="21"/>
+<wire x1="2.4" y1="5.92" x2="-2.4" y2="5.92" width="0.2032" layer="51"/>
+<wire x1="-2.4" y1="5.92" x2="-2.4" y2="-4.98" width="0.2032" layer="21"/>
+<wire x1="-1.1" y1="6.07" x2="1.1" y2="6.07" width="0" layer="46"/>
+<wire x1="1.1" y1="6.07" x2="1.1" y2="5.57" width="0" layer="46"/>
+<wire x1="1.1" y1="5.57" x2="-1.1" y2="5.57" width="0" layer="46"/>
+<wire x1="-1.1" y1="5.57" x2="-1.1" y2="6.07" width="0" layer="46"/>
+<wire x1="-1" y1="1.07" x2="1" y2="1.07" width="0" layer="46"/>
+<wire x1="1" y1="1.07" x2="1" y2="0.77" width="0" layer="46"/>
+<wire x1="1" y1="0.77" x2="-1" y2="0.77" width="0" layer="46"/>
+<wire x1="-1" y1="0.77" x2="-1" y2="1.07" width="0" layer="46"/>
+<wire x1="2.5" y1="4.02" x2="2.9" y2="4.02" width="0" layer="46"/>
+<wire x1="2.9" y1="4.02" x2="2.9" y2="2.82" width="0" layer="46"/>
+<wire x1="2.9" y1="2.82" x2="2.5" y2="2.82" width="0" layer="46"/>
+<wire x1="2.5" y1="2.82" x2="2.5" y2="4.02" width="0" layer="46"/>
+<wire x1="-2" y1="-4.88" x2="-2" y2="-4.28" width="0.1016" layer="25"/>
+<wire x1="-2" y1="-3.78" x2="-2" y2="-3.18" width="0.1016" layer="25"/>
+<wire x1="-2" y1="-2.68" x2="-2" y2="-2.08" width="0.1016" layer="25"/>
+<wire x1="-2" y1="-1.58" x2="-2" y2="-0.98" width="0.1016" layer="25"/>
+<wire x1="2" y1="-4.88" x2="2" y2="-4.28" width="0.1016" layer="25"/>
+<wire x1="2" y1="-3.78" x2="2" y2="-3.18" width="0.1016" layer="25"/>
+<wire x1="2" y1="-2.68" x2="2" y2="-2.08" width="0.1016" layer="25"/>
+<wire x1="2" y1="-1.58" x2="2" y2="-0.98" width="0.1016" layer="25"/>
+<wire x1="-2" y1="-0.48" x2="-2" y2="0.12" width="0.1016" layer="25"/>
+<wire x1="-1.4" y1="0.62" x2="-2" y2="0.62" width="0.1016" layer="51"/>
+<wire x1="2" y1="-0.48" x2="2" y2="0.12" width="0.1016" layer="25"/>
+<wire x1="2" y1="0.62" x2="1.4" y2="0.62" width="0.1016" layer="51"/>
+<wire x1="-0.2" y1="0.62" x2="-0.8" y2="0.62" width="0.1016" layer="51"/>
+<wire x1="1" y1="0.62" x2="0.4" y2="0.62" width="0.1016" layer="51"/>
+<wire x1="-0.5" y1="-4.78" x2="-0.5" y2="-3.38" width="0.1016" layer="21"/>
+<wire x1="0.5" y1="-4.78" x2="0.5" y2="-3.38" width="0.1016" layer="21"/>
+<wire x1="-0.5" y1="-2.98" x2="-0.5" y2="-1.58" width="0.1016" layer="21"/>
+<wire x1="0.5" y1="-2.98" x2="0.5" y2="-1.58" width="0.1016" layer="21"/>
+<wire x1="-0.5" y1="-1.18" x2="-0.5" y2="0.22" width="0.1016" layer="21"/>
+<wire x1="0.5" y1="-1.18" x2="0.5" y2="0.22" width="0.1016" layer="21"/>
+<pad name="2" x="0" y="0.92" drill="1" diameter="1.5" shape="long"/>
+<pad name="1" x="0" y="5.82" drill="1" diameter="1.5" shape="long"/>
+<pad name="3" x="2.7" y="3.42" drill="1" diameter="1.5" shape="long" rot="R90"/>
+<text x="3.81" y="-4.445" size="1.27" layer="25" rot="R90">&gt;NAME</text>
+<text x="-2.54" y="-4.445" size="1.27" layer="27" rot="R90">&gt;VALUE</text>
+<hole x="0" y="3.42" drill="2.4"/>
+</package>
+<package name="POWER_CABLES">
+<pad name="P$1" x="-1.27" y="0" drill="1.524" shape="offset" rot="R180"/>
+<pad name="P$2" x="3.175" y="0" drill="1.524" shape="offset"/>
+<text x="-2.54" y="1.27" size="1.016" layer="21">+</text>
+<text x="3.175" y="1.27" size="1.27" layer="21">-</text>
+<text x="7.62" y="0" size="1.27" layer="25">&gt;NAME</text>
+</package>
+<package name="TO220">
+<description>&lt;b&gt;VOLTAGE REGULATOR&lt;/b&gt;</description>
+<wire x1="5.08" y1="-1.143" x2="5.08" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-4.318" x2="5.08" y2="-4.064" width="0.1524" layer="21"/>
+<wire x1="4.826" y1="-4.318" x2="-4.826" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-4.064" x2="-4.826" y2="-4.318" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-4.064" x2="-5.08" y2="-1.143" width="0.1524" layer="21"/>
+<circle x="-4.6228" y="-3.7084" radius="0.254" width="0" layer="21"/>
+<pad name="1" x="-2.54" y="-2.54" drill="1" shape="long" rot="R90"/>
+<pad name="2" x="0" y="-2.54" drill="1" shape="long" rot="R90"/>
+<pad name="3" x="2.54" y="-2.54" drill="1" shape="long" rot="R90"/>
+<text x="-5.08" y="-6.0452" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<rectangle x1="-5.334" y1="-1.27" x2="-3.429" y2="0" layer="21"/>
+<rectangle x1="-3.429" y1="-0.762" x2="-1.651" y2="0" layer="21"/>
+<rectangle x1="-1.651" y1="-1.27" x2="-0.889" y2="0" layer="21"/>
+<rectangle x1="-0.889" y1="-0.762" x2="0.889" y2="0" layer="21"/>
+<rectangle x1="0.889" y1="-1.27" x2="1.651" y2="0" layer="21"/>
+<rectangle x1="1.651" y1="-0.762" x2="3.429" y2="0" layer="21"/>
+<rectangle x1="3.429" y1="-1.27" x2="5.334" y2="0" layer="21"/>
+<rectangle x1="-3.429" y1="-1.27" x2="-1.651" y2="-0.762" layer="51"/>
+<rectangle x1="-0.889" y1="-1.27" x2="0.889" y2="-0.762" layer="51"/>
+<rectangle x1="1.651" y1="-1.27" x2="3.429" y2="-0.762" layer="51"/>
+</package>
+<package name="SO08">
+<description>&lt;b&gt;Small Outline Package&lt;/b&gt; SOIC 150 mil</description>
+<wire x1="2.159" y1="1.9558" x2="-2.159" y2="1.9558" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.9558" x2="2.54" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.54" y1="1.5748" x2="-2.159" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="1.9558" x2="2.54" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.54" y1="-1.5748" x2="-2.159" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.159" y1="-1.9558" x2="2.159" y2="-1.9558" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-1.5748" x2="2.54" y2="1.5748" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="1.5748" x2="-2.54" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.508" x2="-2.54" y2="-1.5748" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-2.54" y1="-1.6002" x2="2.54" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="8" x="-1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="2" x="-0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="3" x="0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="7" x="-0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="6" x="0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="4" x="1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="5" x="1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<text x="3.937" y="-2.032" size="1.27" layer="27" ratio="10" rot="R90">&gt;VALUE</text>
+<rectangle x1="1.651" y1="1.9558" x2="2.159" y2="3.0988" layer="51"/>
+<rectangle x1="-2.159" y1="-3.0988" x2="-1.651" y2="-1.9558" layer="51"/>
+<rectangle x1="-0.889" y1="-3.0988" x2="-0.381" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="-3.0734" x2="0.889" y2="-1.9304" layer="51"/>
+<rectangle x1="1.651" y1="-3.0988" x2="2.159" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="1.9558" x2="0.889" y2="3.0988" layer="51"/>
+<rectangle x1="-0.889" y1="1.9558" x2="-0.381" y2="3.0988" layer="51"/>
+<rectangle x1="-2.159" y1="1.9558" x2="-1.651" y2="3.0988" layer="51"/>
+</package>
+<package name="3,6-PAD">
+<description>&lt;b&gt;MOUNTING PAD&lt;/b&gt; 3.6 mm, round</description>
+<wire x1="-2.159" y1="0" x2="0" y2="-2.159" width="2.4892" layer="51" curve="90" cap="flat"/>
+<wire x1="0" y1="2.159" x2="2.159" y2="0" width="2.4892" layer="51" curve="-90" cap="flat"/>
+<circle x="0" y="0" radius="3.429" width="0.1524" layer="21"/>
+<circle x="0" y="0" radius="0.762" width="0.4572" layer="51"/>
+<circle x="0" y="0" radius="3.683" width="1.397" layer="39"/>
+<circle x="0" y="0" radius="3.683" width="1.397" layer="40"/>
+<circle x="0" y="0" radius="3.556" width="1.016" layer="43"/>
+<circle x="0" y="0" radius="1.9" width="0.2032" layer="21"/>
+<pad name="B3,6" x="0" y="0" drill="3.6" diameter="5.842" thermals="no"/>
+</package>
+<package name="BU-SMA-H">
+<description>FEMALE &lt;b&gt;SMA CONNECTOR&lt;/b&gt;&lt;p&gt;
+Radiall&lt;p&gt;</description>
+<wire x1="-1.1" y1="3.2" x2="1.1" y2="3.2" width="0.2032" layer="21"/>
+<wire x1="3.2" y1="1.1" x2="3.2" y2="-1.1" width="0.2032" layer="21"/>
+<wire x1="1.1" y1="-3.2" x2="-1.1" y2="-3.2" width="0.2032" layer="21"/>
+<wire x1="-3.2" y1="-1.1" x2="-3.2" y2="1.1" width="0.2032" layer="21"/>
+<wire x1="-3.1999" y1="3.1999" x2="3.2" y2="3.2" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="3.2" x2="3.2" y2="2.9" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="2.9" x2="3.2" y2="-2.9" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="-2.9" x2="3.1999" y2="-3.1999" width="0.2032" layer="51"/>
+<wire x1="3.1999" y1="-3.1999" x2="-3.2" y2="-3.2" width="0.2032" layer="51"/>
+<wire x1="-3.2" y1="-3.2" x2="-3.1999" y2="3.1999" width="0.2032" layer="51"/>
+<wire x1="3.2" y1="2.9" x2="4.3" y2="2.9" width="0.2032" layer="51"/>
+<wire x1="4.3" y1="2.9" x2="8.3" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="2.9" x2="8.6" y2="3.4" width="0.2032" layer="21"/>
+<wire x1="10.7" y1="3.4" x2="11" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="11" y1="2.9" x2="11.6" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="11.6" y1="-2.9" x2="11.6" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.6" y1="3.4" x2="10.7" y2="3.4" width="0.2032" layer="21"/>
+<wire x1="3.2" y1="-2.9" x2="4.3" y2="-2.9" width="0.2032" layer="51"/>
+<wire x1="4.3" y1="-2.9" x2="8.3" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="-2.9" x2="8.6" y2="-3.4" width="0.2032" layer="21"/>
+<wire x1="10.7" y1="-3.4" x2="11" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="11" y1="-2.9" x2="11.6" y2="-2.9" width="0.2032" layer="21"/>
+<wire x1="8.6" y1="-3.4" x2="10.7" y2="-3.4" width="0.2032" layer="21"/>
+<wire x1="11" y1="-2.9" x2="11" y2="2.9" width="0.2032" layer="21"/>
+<wire x1="8.3" y1="-2.9" x2="8.3" y2="2.9" width="0.2032" layer="21"/>
+<circle x="0" y="0" radius="3.1999" width="0.2032" layer="51"/>
+<circle x="0" y="0" radius="1.7" width="0.2032" layer="21"/>
+<pad name="1" x="0" y="0" drill="1.524"/>
+<pad name="2" x="-2.5499" y="2.5499" drill="1.778"/>
+<pad name="3" x="2.5499" y="2.5499" drill="1.778"/>
+<pad name="4" x="2.5499" y="-2.5499" drill="1.778"/>
+<pad name="5" x="-2.5499" y="-2.5499" drill="1.778"/>
+<text x="-2.54" y="4.445" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.175" y="-5.715" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="W5500LITE">
+<dimension x1="-6.35" y1="-12.7" x2="16.51" y2="-12.7" x3="5.08" y3="-13.97" textsize="1.778" layer="48"/>
+<dimension x1="-6.35" y1="-12.7" x2="-6.35" y2="12.7" x3="-11.43" y3="0" textsize="1.778" layer="48"/>
+<wire x1="-6.35" y1="12.7" x2="-6.35" y2="-12.7" width="0.1524" layer="49"/>
+<wire x1="-6.35" y1="-12.7" x2="16.51" y2="-12.7" width="0.1524" layer="49"/>
+<wire x1="16.51" y1="-12.7" x2="16.51" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="-6.35" y1="12.7" x2="-1.27" y2="12.7" width="0.1524" layer="49"/>
+<pad name="P$1" x="-5.08" y="-6.35" drill="0.9" shape="long"/>
+<pad name="P$2" x="-5.08" y="-3.81" drill="0.9" shape="long"/>
+<pad name="P$3" x="-5.08" y="-1.27" drill="0.9" shape="long"/>
+<pad name="P$4" x="-5.08" y="1.27" drill="0.9" shape="long"/>
+<pad name="P$5" x="-5.08" y="3.81" drill="0.9" shape="long"/>
+<pad name="P$6" x="-5.08" y="6.35" drill="0.9" shape="long"/>
+<pad name="P$7" x="15.24" y="6.35" drill="0.9" shape="long"/>
+<pad name="P$8" x="15.24" y="3.81" drill="0.9" shape="long"/>
+<pad name="P$9" x="15.24" y="1.27" drill="0.9" shape="long"/>
+<pad name="P$10" x="15.24" y="-1.27" drill="0.9" shape="long"/>
+<pad name="P$11" x="15.24" y="-3.81" drill="0.9" shape="long"/>
+<pad name="P$12" x="15.24" y="-6.35" drill="0.9" shape="long"/>
+<wire x1="-1.27" y1="12.7" x2="11.43" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="11.43" y1="12.7" x2="16.51" y2="12.7" width="0.1524" layer="49"/>
+<wire x1="-1.27" y1="12.7" x2="-1.27" y2="16.51" width="0.1524" layer="49"/>
+<wire x1="-1.27" y1="16.51" x2="11.43" y2="16.51" width="0.1524" layer="49"/>
+<wire x1="11.43" y1="16.51" x2="11.43" y2="12.7" width="0.1524" layer="49"/>
+<text x="12.7" y="-10.16" size="1.778" layer="26" rot="MR0">WS5500 LITE</text>
+<text x="10.16" y="8.89" size="1.778" layer="26" rot="MR0">USR-ES1</text>
+<wire x1="-6.35" y1="-12.7" x2="-6.35" y2="12.7" width="0.1524" layer="22"/>
+<wire x1="-6.35" y1="12.7" x2="16.51" y2="12.7" width="0.1524" layer="22"/>
+<wire x1="16.51" y1="12.7" x2="16.51" y2="-12.7" width="0.1524" layer="22"/>
+<wire x1="16.51" y1="-12.7" x2="-6.35" y2="-12.7" width="0.1524" layer="22"/>
+</package>
+<package name="D/7343-31W">
+<description>&lt;b&gt;Chip Capacitor Type KEMET D / EIA 7343-21&lt;/b&gt;&lt;p&gt;
+KEMET V / EIA 7343-20, KEMET X / EIA 7343-43 Wafe solder</description>
+<wire x1="-3.45" y1="2.1" x2="3.45" y2="2.1" width="0.1016" layer="51"/>
+<wire x1="3.45" y1="2.1" x2="3.45" y2="-2.1" width="0.1016" layer="51"/>
+<wire x1="3.45" y1="-2.1" x2="-3.45" y2="-2.1" width="0.1016" layer="51"/>
+<wire x1="-3.45" y1="-2.1" x2="-3.45" y2="2.1" width="0.1016" layer="51"/>
+<smd name="+" x="3.375" y="0" dx="2.95" dy="2.7" layer="1"/>
+<smd name="-" x="-3.375" y="0" dx="2.95" dy="2.7" layer="1"/>
+<text x="-3.65" y="2.3" size="1.27" layer="25">&gt;NAME</text>
+<text x="-3.65" y="-3.575" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-3.65" y1="-1.2" x2="-3.5" y2="1.2" layer="51"/>
+<rectangle x1="3.5" y1="-1.2" x2="3.65" y2="1.2" layer="51"/>
+<rectangle x1="2.675" y1="-2.125" x2="3.15" y2="2.125" layer="51"/>
+<wire x1="-3.4925" y1="2.2225" x2="1.5875" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="2.2225" x2="3.4925" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="-3.4925" y1="-2.2225" x2="1.5875" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-2.2225" x2="3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="2.2225" x2="1.5875" y2="-2.2225" width="0.3048" layer="21"/>
+<wire x1="-3.4925" y1="1.5875" x2="-3.4925" y2="2.2225" width="0.1524" layer="21"/>
+<wire x1="3.4925" y1="2.2225" x2="3.4925" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-3.4925" y1="-1.5875" x2="-3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+<wire x1="3.4925" y1="-1.5875" x2="3.4925" y2="-2.2225" width="0.1524" layer="21"/>
+</package>
+<package name="CT6032">
+<description>&lt;b&gt;TANTALUM CAPACITOR&lt;/b&gt;</description>
+<wire x1="-4.473" y1="1.983" x2="4.473" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="-1.983" x2="-4.473" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-4.473" y1="-1.983" x2="-4.473" y2="1.983" width="0.0508" layer="39"/>
+<wire x1="4.473" y1="1.983" x2="4.473" y2="-1.983" width="0.0508" layer="39"/>
+<wire x1="-2.932" y1="-1.637" x2="-2.932" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="-3.073" y1="1.067" x2="-3.073" y2="-1.067" width="0.1524" layer="51"/>
+<wire x1="2.957" y1="1.637" x2="-2.932" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="2.957" y1="-1.637" x2="-2.932" y2="-1.637" width="0.2032" layer="51"/>
+<wire x1="3.073" y1="1.067" x2="3.073" y2="-1.067" width="0.1524" layer="51"/>
+<wire x1="2.957" y1="-1.637" x2="2.957" y2="1.637" width="0.2032" layer="51"/>
+<wire x1="-1.18" y1="0" x2="-2.45" y2="0" width="0.2032" layer="51"/>
+<wire x1="-1.8" y1="0.63" x2="-1.8" y2="-0.64" width="0.2032" layer="51"/>
+<smd name="+" x="-2.5" y="0" dx="2.6" dy="2.2" layer="1"/>
+<smd name="-" x="2.5" y="0" dx="2.6" dy="2.2" layer="1"/>
+<text x="-2.54" y="1.905" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.5001" y1="-1" x2="0.5001" y2="1" layer="35"/>
+<wire x1="-2.8575" y1="1.27" x2="-2.8575" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-2.8575" y1="1.5875" x2="-0.9525" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="1.5875" x2="2.8575" y2="1.5875" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="1.5875" x2="2.8575" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="-1.27" x2="2.8575" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="2.8575" y1="-1.5875" x2="-0.9525" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="-1.5875" x2="-2.8575" y2="-1.5875" width="0.1524" layer="21"/>
+<wire x1="-2.8575" y1="-1.5875" x2="-2.8575" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="1.5875" x2="-0.9525" y2="-1.5875" width="0.254" layer="21"/>
+</package>
+<package name="CT3216">
+<description>&lt;b&gt;TANTALUM CAPACITOR&lt;/b&gt;</description>
+<wire x1="-2.973" y1="1.483" x2="2.973" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="-1.483" x2="-2.973" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.973" y1="-1.483" x2="-2.973" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.973" y1="1.483" x2="2.973" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-1.651" y1="0.559" x2="-1.651" y2="-0.559" width="0.1524" layer="51"/>
+<wire x1="1.651" y1="0.559" x2="1.651" y2="-0.559" width="0.1524" layer="51"/>
+<wire x1="-1.535" y1="0.798" x2="-1.535" y2="-0.798" width="0.2032" layer="51"/>
+<wire x1="-1.535" y1="-0.798" x2="1.535" y2="-0.798" width="0.2032" layer="51"/>
+<wire x1="1.535" y1="-0.798" x2="1.535" y2="0.798" width="0.2032" layer="51"/>
+<wire x1="1.535" y1="0.798" x2="-1.535" y2="0.798" width="0.2032" layer="51"/>
+<wire x1="-0.7" y1="0" x2="-1.26" y2="0" width="0.2032" layer="51"/>
+<wire x1="-0.97" y1="0.26" x2="-0.97" y2="-0.3" width="0.2032" layer="51"/>
+<smd name="+" x="-1.7175" y="0" dx="1.524" dy="1.2" layer="1"/>
+<smd name="-" x="1.4" y="0" dx="2" dy="1.2" layer="1"/>
+<text x="-2.54" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-2.54" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.1999" y1="-0.5999" x2="0.1999" y2="0.5999" layer="35"/>
+<wire x1="1.5875" y1="0.635" x2="1.5875" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="0.9525" x2="-0.635" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="0.9525" x2="-1.5875" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="0.9525" x2="-1.5875" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.635" x2="-1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.9525" x2="-0.635" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="-0.9525" x2="1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-0.9525" x2="1.5875" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="0.9525" x2="-0.635" y2="-0.9525" width="0.254" layer="21"/>
+</package>
+<package name="B/3528-21W">
+<description>&lt;b&gt;Chip Capacitor Type KEMET B / EIA 3528-21 Wave solder&lt;/b&gt;&lt;p&gt;
+KEMET T / EIA 3528-12</description>
+<wire x1="-1.6" y1="1.2" x2="1.6" y2="1.2" width="0.1016" layer="51"/>
+<wire x1="1.6" y1="1.2" x2="1.6" y2="-1.2" width="0.1016" layer="51"/>
+<wire x1="1.6" y1="-1.2" x2="-1.6" y2="-1.2" width="0.1016" layer="51"/>
+<wire x1="-1.6" y1="-1.2" x2="-1.6" y2="1.2" width="0.1016" layer="51"/>
+<smd name="+" x="1.9425" y="0" dx="1.651" dy="1.8" layer="1"/>
+<smd name="-" x="-1.625" y="0" dx="2.15" dy="1.8" layer="1"/>
+<text x="-1.95" y="1.6" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.95" y="-2.925" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-1.75" y1="-0.6" x2="-1.625" y2="0.6" layer="51"/>
+<rectangle x1="1.625" y1="-0.6" x2="1.75" y2="0.6" layer="51"/>
+<rectangle x1="0.95" y1="-1.225" x2="1.25" y2="1.225" layer="51"/>
+<wire x1="-1.5875" y1="1.27" x2="0.9525" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="1.27" x2="1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="0.9525" x2="1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="0.9525" x2="-1.5875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-0.9525" x2="-1.5875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.5875" y1="-1.27" x2="0.9525" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="-1.27" x2="1.5875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.5875" y1="-1.27" x2="1.5875" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="1.27" x2="0.9525" y2="-1.27" width="0.254" layer="21"/>
+</package>
+<package name="NUCLEO_64">
+<pad name="A37" x="2.54" y="5.08" drill="0.9" shape="square"/>
+<pad name="A38" x="5.08" y="5.08" drill="0.9" shape="square"/>
+<pad name="A35" x="2.54" y="7.62" drill="0.9" shape="square"/>
+<pad name="A36" x="5.08" y="7.62" drill="0.9" shape="square"/>
+<pad name="A34" x="5.08" y="10.16" drill="0.9" shape="square"/>
+<pad name="A33" x="2.54" y="10.16" drill="0.9" shape="square"/>
+<pad name="A31" x="2.54" y="12.7" drill="0.9" shape="square"/>
+<pad name="A32" x="5.08" y="12.7" drill="0.9" shape="square"/>
+<pad name="A29" x="2.54" y="15.24" drill="0.9" shape="square"/>
+<pad name="A30" x="5.08" y="15.24" drill="0.9" shape="square"/>
+<pad name="A28" x="5.08" y="17.78" drill="0.9" shape="square"/>
+<pad name="A27" x="2.54" y="17.78" drill="0.9" shape="square"/>
+<pad name="A25" x="2.54" y="20.32" drill="0.9" shape="square"/>
+<pad name="A23" x="2.54" y="22.86" drill="0.9" shape="square"/>
+<pad name="A21" x="2.54" y="25.4" drill="0.9" shape="square"/>
+<pad name="A19" x="2.54" y="27.94" drill="0.9" shape="square"/>
+<pad name="A17" x="2.54" y="30.48" drill="0.9" shape="square"/>
+<pad name="A15" x="2.54" y="33.02" drill="0.9" shape="square"/>
+<pad name="A13" x="2.54" y="35.56" drill="0.9" shape="square"/>
+<pad name="A11" x="2.54" y="38.1" drill="0.9" shape="square"/>
+<pad name="A9" x="2.54" y="40.64" drill="0.9" shape="square"/>
+<pad name="A7" x="2.54" y="43.18" drill="0.9" shape="square"/>
+<pad name="A5" x="2.54" y="45.72" drill="0.9" shape="square"/>
+<pad name="A3" x="2.54" y="48.26" drill="0.9" shape="square"/>
+<pad name="A1" x="2.54" y="50.8" drill="0.9" shape="square"/>
+<pad name="A2" x="5.08" y="50.8" drill="0.9" shape="square"/>
+<pad name="A4" x="5.08" y="48.26" drill="0.9" shape="square"/>
+<pad name="A6" x="5.08" y="45.72" drill="0.9" shape="square"/>
+<pad name="A8" x="5.08" y="43.18" drill="0.9" shape="square"/>
+<pad name="A10" x="5.08" y="40.64" drill="0.9" shape="square"/>
+<pad name="A12" x="5.08" y="38.1" drill="0.9" shape="square"/>
+<pad name="A14" x="5.08" y="35.56" drill="0.9" shape="square"/>
+<pad name="A16" x="5.08" y="33.02" drill="0.9" shape="square"/>
+<pad name="A18" x="5.08" y="30.48" drill="0.9" shape="square"/>
+<pad name="A20" x="5.08" y="27.94" drill="0.9" shape="square"/>
+<pad name="A22" x="5.08" y="25.4" drill="0.9" shape="square"/>
+<pad name="A24" x="5.08" y="22.86" drill="0.9" shape="square"/>
+<pad name="A26" x="5.08" y="20.32" drill="0.9" shape="square"/>
+<pad name="GND2" x="2.54" y="76.2" drill="0.9" shape="square"/>
+<pad name="GND1" x="2.54" y="78.74" drill="0.9" shape="square"/>
+<pad name="B37" x="63.5" y="5.08" drill="0.9" shape="square"/>
+<pad name="B38" x="66.04" y="5.08" drill="0.9" shape="square"/>
+<pad name="B35" x="63.5" y="7.62" drill="0.9" shape="square"/>
+<pad name="B36" x="66.04" y="7.62" drill="0.9" shape="square"/>
+<pad name="B34" x="66.04" y="10.16" drill="0.9" shape="square"/>
+<pad name="B33" x="63.5" y="10.16" drill="0.9" shape="square"/>
+<pad name="B31" x="63.5" y="12.7" drill="0.9" shape="square"/>
+<pad name="B32" x="66.04" y="12.7" drill="0.9" shape="square"/>
+<pad name="B29" x="63.5" y="15.24" drill="0.9" shape="square"/>
+<pad name="B30" x="66.04" y="15.24" drill="0.9" shape="square"/>
+<pad name="B28" x="66.04" y="17.78" drill="0.9" shape="square"/>
+<pad name="B27" x="63.5" y="17.78" drill="0.9" shape="square"/>
+<pad name="B25" x="63.5" y="20.32" drill="0.9" shape="square"/>
+<pad name="B23" x="63.5" y="22.86" drill="0.9" shape="square"/>
+<pad name="B21" x="63.5" y="25.4" drill="0.9" shape="square"/>
+<pad name="B19" x="63.5" y="27.94" drill="0.9" shape="square"/>
+<pad name="B17" x="63.5" y="30.48" drill="0.9" shape="square"/>
+<pad name="B15" x="63.5" y="33.02" drill="0.9" shape="square"/>
+<pad name="B13" x="63.5" y="35.56" drill="0.9" shape="square"/>
+<pad name="B11" x="63.5" y="38.1" drill="0.9" shape="square"/>
+<pad name="B9" x="63.5" y="40.64" drill="0.9" shape="square"/>
+<pad name="B7" x="63.5" y="43.18" drill="0.9" shape="square"/>
+<pad name="B5" x="63.5" y="45.72" drill="0.9" shape="square"/>
+<pad name="B3" x="63.5" y="48.26" drill="0.9" shape="square"/>
+<pad name="B1" x="63.5" y="50.8" drill="0.9" shape="square"/>
+<pad name="B2" x="66.04" y="50.8" drill="0.9" shape="square"/>
+<pad name="B4" x="66.04" y="48.26" drill="0.9" shape="square"/>
+<pad name="B6" x="66.04" y="45.72" drill="0.9" shape="square"/>
+<pad name="B8" x="66.04" y="43.18" drill="0.9" shape="square"/>
+<pad name="B10" x="66.04" y="40.64" drill="0.9" shape="square"/>
+<pad name="B12" x="66.04" y="38.1" drill="0.9" shape="square"/>
+<pad name="B14" x="66.04" y="35.56" drill="0.9" shape="square"/>
+<pad name="B16" x="66.04" y="33.02" drill="0.9" shape="square"/>
+<pad name="B18" x="66.04" y="30.48" drill="0.9" shape="square"/>
+<pad name="B20" x="66.04" y="27.94" drill="0.9" shape="square"/>
+<pad name="B22" x="66.04" y="25.4" drill="0.9" shape="square"/>
+<pad name="B24" x="66.04" y="22.86" drill="0.9" shape="square"/>
+<pad name="B26" x="66.04" y="20.32" drill="0.9" shape="square"/>
+<pad name="GND7" x="66.04" y="76.2" drill="0.9" shape="square" rot="R180"/>
+<pad name="GND6" x="66.04" y="78.74" drill="0.9" shape="square" rot="R180"/>
+<wire x1="0" y1="0" x2="0" y2="82.55" width="0.1524" layer="21"/>
+<wire x1="0" y1="82.55" x2="68.58" y2="82.55" width="0.1524" layer="21"/>
+<wire x1="68.58" y1="82.55" x2="68.58" y2="0" width="0.1524" layer="21"/>
+<wire x1="68.58" y1="0" x2="0" y2="0" width="0.1524" layer="21"/>
+<text x="34.29" y="31.75" size="2.54" layer="21" rot="R90">NUCLEO 64</text>
+</package>
+<package name="1X01">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="-0.9525" y1="1.27" x2="0.9525" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="1.27" x2="1.27" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.9525" x2="1.27" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.9525" x2="0.9525" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.9525" x2="-1.27" y2="-0.9525" width="0.1524" layer="21"/>
+<wire x1="-0.9525" y1="1.27" x2="-1.27" y2="0.9525" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.9525" x2="-0.9525" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.9525" y1="-1.27" x2="-0.9525" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="1" x="0" y="0" drill="1.016" shape="square"/>
+<text x="-1.3462" y="1.8288" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<rectangle x1="-0.254" y1="-0.254" x2="0.254" y2="0.254" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ETH_WIZ_CLICK_W5500">
+<wire x1="-17.78" y1="30.48" x2="-17.78" y2="-22.86" width="0.254" layer="94"/>
+<wire x1="-17.78" y1="-22.86" x2="15.24" y2="-22.86" width="0.254" layer="94"/>
+<wire x1="15.24" y1="-22.86" x2="15.24" y2="30.48" width="0.254" layer="94"/>
+<wire x1="-17.78" y1="30.48" x2="15.24" y2="30.48" width="0.254" layer="94"/>
+<pin name="GND" x="-22.86" y="-20.32" length="middle"/>
+<pin name="3V3" x="-22.86" y="-15.24" length="middle"/>
+<pin name="SDI" x="-22.86" y="-10.16" length="middle"/>
+<pin name="SDO" x="-22.86" y="-5.08" length="middle"/>
+<pin name="CLK" x="-22.86" y="0" length="middle"/>
+<pin name="CS" x="-22.86" y="5.08" length="middle"/>
+<pin name="RST" x="-22.86" y="10.16" length="middle"/>
+<pin name="NC" x="-22.86" y="15.24" length="middle"/>
+<pin name="NC7" x="20.32" y="15.24" length="middle" rot="R180"/>
+<pin name="INT" x="20.32" y="10.16" length="middle" rot="R180"/>
+<pin name="NC6" x="20.32" y="5.08" length="middle" rot="R180"/>
+<pin name="NC5" x="20.32" y="0" length="middle" rot="R180"/>
+<pin name="NC4" x="20.32" y="-5.08" length="middle" rot="R180"/>
+<pin name="NC3" x="20.32" y="-10.16" length="middle" rot="R180"/>
+<pin name="NC2" x="20.32" y="-15.24" length="middle" rot="R180"/>
+<pin name="GND2" x="20.32" y="-20.32" length="middle" rot="R180"/>
+<pin name="SHLD" x="-22.86" y="27.94" length="middle"/>
+<text x="-10.16" y="30.48" size="2.54" layer="97">Eth Wiz click
+W5500</text>
+</symbol>
+<symbol name="RF4463F30">
+<wire x1="-17.78" y1="-20.32" x2="-17.78" y2="25.4" width="0.254" layer="94"/>
+<wire x1="-17.78" y1="25.4" x2="12.7" y2="25.4" width="0.254" layer="94"/>
+<wire x1="12.7" y1="25.4" x2="12.7" y2="-20.32" width="0.254" layer="94"/>
+<wire x1="12.7" y1="-20.32" x2="-17.78" y2="-20.32" width="0.254" layer="94"/>
+<pin name="GND1" x="-22.86" y="20.32" length="middle"/>
+<pin name="CS" x="-22.86" y="15.24" length="middle"/>
+<pin name="IRQ" x="-22.86" y="10.16" length="middle"/>
+<pin name="SDN" x="-22.86" y="5.08" length="middle"/>
+<pin name="NC1" x="-22.86" y="0" length="middle"/>
+<pin name="NC2" x="-22.86" y="-5.08" length="middle"/>
+<pin name="GND2" x="-22.86" y="-10.16" length="middle"/>
+<pin name="VCC" x="-22.86" y="-15.24" length="middle"/>
+<pin name="ANT" x="17.78" y="-15.24" length="middle" rot="R180"/>
+<pin name="RF_GND" x="17.78" y="-10.16" length="middle" rot="R180"/>
+<pin name="NC3" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="GPIO_0" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="GPIO_1" x="17.78" y="5.08" length="middle" rot="R180"/>
+<pin name="SDO" x="17.78" y="10.16" length="middle" rot="R180"/>
+<pin name="SDI" x="17.78" y="15.24" length="middle" rot="R180"/>
+<pin name="CLK" x="17.78" y="20.32" length="middle" rot="R180"/>
+<pin name="SHLD_1" x="-2.54" y="30.48" length="middle" rot="R270"/>
+<pin name="SHLD_2" x="-2.54" y="-25.4" length="middle" rot="R90"/>
+<text x="-10.16" y="2.54" size="2.54" layer="97">SI4463</text>
+<pin name="SHLD_4" x="5.08" y="-25.4" length="middle" rot="R90"/>
+<pin name="SHLD_3" x="5.08" y="30.48" length="middle" rot="R270"/>
+</symbol>
+<symbol name="NUCLEO_STM32L432KC">
+<wire x1="-15.24" y1="38.1" x2="-15.24" y2="-38.1" width="0.254" layer="94"/>
+<wire x1="-15.24" y1="-38.1" x2="17.78" y2="-38.1" width="0.254" layer="94"/>
+<wire x1="17.78" y1="-38.1" x2="17.78" y2="38.1" width="0.254" layer="94"/>
+<wire x1="17.78" y1="38.1" x2="-15.24" y2="38.1" width="0.254" layer="94"/>
+<pin name="D1_PA9" x="-20.32" y="35.56" length="middle"/>
+<pin name="D0_PA10" x="-20.32" y="30.48" length="middle"/>
+<pin name="RESET" x="-20.32" y="25.4" length="middle"/>
+<pin name="GND1" x="-20.32" y="20.32" length="middle"/>
+<pin name="D2_PA12" x="-20.32" y="15.24" length="middle"/>
+<pin name="D3_PB0" x="-20.32" y="10.16" length="middle"/>
+<pin name="D4_PB7" x="-20.32" y="5.08" length="middle"/>
+<pin name="D5_PB6" x="-20.32" y="0" length="middle"/>
+<pin name="D6_PB1" x="-20.32" y="-5.08" length="middle"/>
+<pin name="D7_PC14" x="-20.32" y="-10.16" length="middle"/>
+<pin name="D8_PC15" x="-20.32" y="-15.24" length="middle"/>
+<pin name="D9_PA8" x="-20.32" y="-20.32" length="middle"/>
+<pin name="D10_PA11" x="-20.32" y="-25.4" length="middle"/>
+<pin name="D11_PB5" x="-20.32" y="-30.48" length="middle"/>
+<pin name="D12_PB4" x="-20.32" y="-35.56" length="middle"/>
+<pin name="D13_PB3" x="22.86" y="-35.56" length="middle" rot="R180"/>
+<pin name="3V3" x="22.86" y="-30.48" length="middle" rot="R180"/>
+<pin name="AREF" x="22.86" y="-25.4" length="middle" rot="R180"/>
+<pin name="A0_PA0" x="22.86" y="-20.32" length="middle" rot="R180"/>
+<pin name="PA_PA1" x="22.86" y="-15.24" length="middle" rot="R180"/>
+<pin name="A2_PA3" x="22.86" y="-10.16" length="middle" rot="R180"/>
+<pin name="A3_PA4" x="22.86" y="-5.08" length="middle" rot="R180"/>
+<pin name="A4_PA5" x="22.86" y="0" length="middle" rot="R180"/>
+<pin name="A5_PA6" x="22.86" y="5.08" length="middle" rot="R180"/>
+<pin name="A6_PA7" x="22.86" y="10.16" length="middle" rot="R180"/>
+<pin name="A7_PA2" x="22.86" y="15.24" length="middle" rot="R180"/>
+<pin name="5V" x="22.86" y="20.32" length="middle" rot="R180"/>
+<pin name="RESET2" x="22.86" y="25.4" length="middle" rot="R180"/>
+<pin name="GND2" x="22.86" y="30.48" length="middle" rot="R180"/>
+<pin name="VIN" x="22.86" y="35.56" length="middle" rot="R180"/>
+<pin name="SHLD" x="2.54" y="-43.18" length="middle" rot="R90"/>
+<text x="-12.7" y="38.1" size="2.54" layer="97">NUCLEO L432KC</text>
+</symbol>
+<symbol name="VOLT_REGUL">
+<wire x1="-12.7" y1="10.16" x2="20.32" y2="10.16" width="0.1524" layer="94"/>
+<wire x1="20.32" y1="10.16" x2="20.32" y2="-10.16" width="0.1524" layer="94"/>
+<wire x1="20.32" y1="-10.16" x2="-12.7" y2="-10.16" width="0.1524" layer="94"/>
+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.1524" layer="94"/>
+<pin name="IN+" x="-17.78" y="7.62" length="middle"/>
+<pin name="IN-" x="-17.78" y="-7.62" length="middle"/>
+<pin name="OUT+" x="25.4" y="7.62" length="middle" rot="R180"/>
+<pin name="OUT-" x="25.4" y="-7.62" length="middle" rot="R180"/>
+<text x="-10.16" y="-2.54" size="2.54" layer="97">step down
+voltage regulator</text>
+</symbol>
+<symbol name="SPI_SRAM">
+<wire x1="-10.16" y1="15.24" x2="15.24" y2="15.24" width="0.1524" layer="94"/>
+<wire x1="15.24" y1="15.24" x2="15.24" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="15.24" y1="-7.62" x2="-10.16" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="-10.16" y1="-7.62" x2="-10.16" y2="15.24" width="0.1524" layer="94"/>
+<pin name="CS" x="-15.24" y="12.7" length="middle"/>
+<pin name="MISO" x="-15.24" y="7.62" length="middle"/>
+<pin name="SIO2" x="-15.24" y="2.54" length="middle"/>
+<pin name="GND" x="-15.24" y="-2.54" length="middle"/>
+<pin name="MOSI" x="20.32" y="-2.54" length="middle" rot="R180"/>
+<pin name="SCK" x="20.32" y="2.54" length="middle" rot="R180"/>
+<pin name="HOLD" x="20.32" y="7.62" length="middle" rot="R180"/>
+<pin name="VCC" x="20.32" y="12.7" length="middle" rot="R180"/>
+<text x="-7.62" y="15.24" size="1.9304" layer="97">SRAM (23LC1024)</text>
+</symbol>
+<symbol name="CON_5V">
+<wire x1="-5.08" y1="10.16" x2="7.62" y2="10.16" width="0.1524" layer="94"/>
+<wire x1="7.62" y1="10.16" x2="7.62" y2="-10.16" width="0.1524" layer="94"/>
+<wire x1="7.62" y1="-10.16" x2="-5.08" y2="-10.16" width="0.1524" layer="94"/>
+<wire x1="-5.08" y1="-10.16" x2="-5.08" y2="10.16" width="0.1524" layer="94"/>
+<pin name="CENTER" x="12.7" y="7.62" length="middle" rot="R180"/>
+<pin name="GND" x="12.7" y="0" length="middle" rot="R180"/>
+<pin name="GND2" x="12.7" y="-7.62" length="middle" rot="R180"/>
+<text x="-5.08" y="10.16" size="1.778" layer="97">5V connector 
+2.1mm</text>
+</symbol>
+<symbol name="POWER_CABLES">
+<wire x1="-2.54" y1="5.08" x2="2.54" y2="5.08" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="5.08" x2="2.54" y2="-5.08" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="-5.08" x2="-2.54" y2="-5.08" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="-5.08" x2="-2.54" y2="5.08" width="0.1524" layer="94"/>
+<pin name="+" x="7.62" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="7.62" y="-2.54" length="middle" rot="R180"/>
+</symbol>
+<symbol name="REGUL">
+<wire x1="-5.08" y1="5.08" x2="7.62" y2="5.08" width="0.1524" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-5.08" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="-5.08" y1="-2.54" x2="-5.08" y2="5.08" width="0.1524" layer="94"/>
+<pin name="IN" x="-10.16" y="2.54" length="middle"/>
+<pin name="GND" x="0" y="-7.62" length="middle" rot="R90"/>
+<pin name="OUT" x="12.7" y="2.54" length="middle" rot="R180"/>
+<text x="-2.54" y="5.08" size="1.778" layer="97">&gt;NAME</text>
+</symbol>
+<symbol name="MOUNT-HOLE">
+<wire x1="0" y1="1.27" x2="1.27" y2="0" width="1.524" layer="94" curve="-90" cap="flat"/>
+<wire x1="-1.27" y1="0" x2="0" y2="-1.27" width="1.524" layer="94" curve="90" cap="flat"/>
+<wire x1="-0.508" y1="0" x2="0.508" y2="0" width="0.0508" layer="94"/>
+<wire x1="0" y1="0.508" x2="0" y2="-0.508" width="0.0508" layer="94"/>
+<circle x="0" y="0" radius="2.032" width="0.0508" layer="94"/>
+<circle x="0" y="0" radius="0.508" width="0.0508" layer="94"/>
+<text x="2.032" y="0.5842" size="1.778" layer="95">&gt;NAME</text>
+<text x="2.032" y="-2.4638" size="1.778" layer="96">&gt;VALUE</text>
+</symbol>
+<symbol name="MOUNT-PAD">
+<wire x1="0.254" y1="2.032" x2="2.032" y2="0.254" width="1.016" layer="94" curve="-75.749967" cap="flat"/>
+<wire x1="-2.032" y1="0.254" x2="-0.254" y2="2.032" width="1.016" layer="94" curve="-75.749967" cap="flat"/>
+<wire x1="-2.032" y1="-0.254" x2="-0.254" y2="-2.032" width="1.016" layer="94" curve="75.749967" cap="flat"/>
+<wire x1="0.254" y1="-2.032" x2="2.032" y2="-0.254" width="1.016" layer="94" curve="75.749967" cap="flat"/>
+<circle x="0" y="0" radius="1.524" width="0.0508" layer="94"/>
+<text x="2.794" y="0.5842" size="1.778" layer="95">&gt;NAME</text>
+<text x="2.794" y="-2.4638" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="MOUNT" x="-2.54" y="0" visible="off" length="short" direction="pas"/>
+</symbol>
+<symbol name="BNC-FGND">
+<wire x1="0" y1="-2.54" x2="-0.762" y2="-1.778" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-0.508" y2="0" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="0.508" x2="-0.762" y2="0.508" width="0.254" layer="94"/>
+<wire x1="-0.762" y1="0.508" x2="-0.508" y2="0" width="0.254" layer="94"/>
+<wire x1="-0.508" y1="0" x2="-0.762" y2="-0.508" width="0.254" layer="94"/>
+<wire x1="-0.762" y1="-0.508" x2="-2.54" y2="-0.508" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="2.54" x2="0" y2="0.508" width="0.3048" layer="94" curve="-79.611142" cap="flat"/>
+<wire x1="-2.54" y1="-2.54" x2="0" y2="-0.508" width="0.3048" layer="94" curve="79.611142" cap="flat"/>
+<text x="-2.54" y="-5.08" size="1.778" layer="96">&gt;VALUE</text>
+<text x="-2.54" y="3.302" size="1.778" layer="95">&gt;NAME</text>
+<pin name="1" x="2.54" y="0" visible="off" length="short" direction="pas" rot="R180"/>
+<pin name="2" x="2.54" y="-2.54" visible="off" length="short" direction="pas" rot="R180"/>
+</symbol>
+<symbol name="BNC-FGND-1">
+<wire x1="0" y1="-2.54" x2="-0.762" y2="-1.778" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-0.508" y2="0" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="0.508" x2="-0.762" y2="0.508" width="0.254" layer="94"/>
+<wire x1="-0.762" y1="0.508" x2="-0.508" y2="0" width="0.254" layer="94"/>
+<wire x1="-0.508" y1="0" x2="-0.762" y2="-0.508" width="0.254" layer="94"/>
+<wire x1="-0.762" y1="-0.508" x2="-2.54" y2="-0.508" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="2.54" x2="0" y2="0.508" width="0.3048" layer="94" curve="-79.611142" cap="flat"/>
+<wire x1="-2.54" y1="-2.54" x2="0" y2="-0.508" width="0.3048" layer="94" curve="79.611142" cap="flat"/>
+<text x="-2.54" y="-5.08" size="1.778" layer="96">&gt;VALUE</text>
+<text x="-2.54" y="3.302" size="1.778" layer="95">&gt;NAME</text>
+<pin name="1" x="2.54" y="0" visible="off" length="short" direction="pas" rot="R180"/>
+<pin name="2" x="2.54" y="-2.54" visible="off" length="short" direction="pas" rot="R180"/>
+</symbol>
+<symbol name="W5500LITE">
+<wire x1="-27.94" y1="30.48" x2="-27.94" y2="-5.08" width="0.1524" layer="94"/>
+<wire x1="-27.94" y1="-5.08" x2="-27.94" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="-27.94" y1="-7.62" x2="0" y2="-7.62" width="0.1524" layer="94"/>
+<wire x1="0" y1="-7.62" x2="0" y2="30.48" width="0.1524" layer="94"/>
+<wire x1="0" y1="30.48" x2="-27.94" y2="30.48" width="0.1524" layer="94"/>
+<pin name="GND" x="0" y="22.86" length="middle"/>
+<pin name="3V3" x="0" y="17.78" length="middle"/>
+<pin name="3V3." x="0" y="12.7" length="middle"/>
+<pin name="NC" x="0" y="7.62" length="middle"/>
+<pin name="RST" x="0" y="2.54" length="middle"/>
+<pin name="MISO" x="0" y="-2.54" length="middle"/>
+<pin name="GND," x="-27.94" y="22.86" length="middle" rot="R180"/>
+<pin name="GND." x="-27.94" y="17.78" length="middle" rot="R180"/>
+<pin name="MOSI" x="-27.94" y="12.7" length="middle" rot="R180"/>
+<pin name="SLCK" x="-27.94" y="7.62" length="middle" rot="R180"/>
+<pin name="CS" x="-27.94" y="2.54" length="middle" rot="R180"/>
+<pin name="INT" x="-27.94" y="-2.54" length="middle" rot="R180"/>
+</symbol>
+<symbol name="CPOL-US">
+<wire x1="-2.54" y1="0" x2="2.54" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="-1.016" x2="0" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="0" y1="-1" x2="2.4892" y2="-1.8542" width="0.254" layer="94" curve="-37.878202" cap="flat"/>
+<wire x1="-2.4669" y1="-1.8504" x2="0" y2="-1.0161" width="0.254" layer="94" curve="-37.376341" cap="flat"/>
+<text x="1.016" y="0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.016" y="-4.191" size="1.778" layer="96">&gt;VALUE</text>
+<text x="0" y="2.54" size="0.4064" layer="99" align="center">SpiceOrder 1</text>
+<text x="0" y="-5.08" size="0.4064" layer="99" align="center">SpiceOrder 2</text>
+<rectangle x1="-2.253" y1="0.668" x2="-1.364" y2="0.795" layer="94"/>
+<rectangle x1="-1.872" y1="0.287" x2="-1.745" y2="1.176" layer="94"/>
+<pin name="+" x="0" y="2.54" visible="off" length="short" direction="pas" swaplevel="1" rot="R270"/>
+<pin name="-" x="0" y="-5.08" visible="off" length="short" direction="pas" swaplevel="1" rot="R90"/>
+</symbol>
+<symbol name="NUCLEO_L476">
+<pin name="GND1" x="-30.48" y="25.4" length="short"/>
+<pin name="GND2" x="-30.48" y="22.86" length="short"/>
+<pin name="PC10" x="-30.48" y="15.24" length="short"/>
+<pin name="PC12" x="-30.48" y="12.7" length="short"/>
+<pin name="VDD" x="-30.48" y="10.16" length="short"/>
+<pin name="BOOT" x="-30.48" y="7.62" length="short"/>
+<pin name="NC" x="-30.48" y="5.08" length="short"/>
+<pin name="NC2" x="-30.48" y="2.54" length="short"/>
+<pin name="PA13" x="-30.48" y="0" length="short"/>
+<pin name="PA14" x="-30.48" y="-2.54" length="short"/>
+<pin name="PA15" x="-30.48" y="-5.08" length="short"/>
+<pin name="GND" x="-30.48" y="-7.62" length="short"/>
+<pin name="PB7" x="-30.48" y="-10.16" length="short"/>
+<pin name="PC13" x="-30.48" y="-12.7" length="short"/>
+<pin name="PC14" x="-30.48" y="-15.24" length="short"/>
+<pin name="PC15" x="-30.48" y="-17.78" length="short"/>
+<pin name="PH0" x="-30.48" y="-20.32" length="short"/>
+<pin name="PH1" x="-30.48" y="-22.86" length="short"/>
+<pin name="VBAT" x="-30.48" y="-25.4" length="short"/>
+<pin name="PC2" x="-30.48" y="-27.94" length="short"/>
+<pin name="PC3" x="-30.48" y="-30.48" length="short"/>
+<pin name="PC11" x="-7.62" y="15.24" length="short" rot="R180"/>
+<pin name="PD2" x="-7.62" y="12.7" length="short" rot="R180"/>
+<pin name="E5V" x="-7.62" y="10.16" length="short" rot="R180"/>
+<pin name="GND3" x="-7.62" y="7.62" length="short" rot="R180"/>
+<pin name="NC3" x="-7.62" y="5.08" length="short" rot="R180"/>
+<pin name="IOREF" x="-7.62" y="2.54" length="short" rot="R180"/>
+<pin name="RESET" x="-7.62" y="0" length="short" rot="R180"/>
+<pin name="3V3" x="-7.62" y="-2.54" length="short" rot="R180"/>
+<pin name="5V" x="-7.62" y="-5.08" length="short" rot="R180"/>
+<pin name="GND4" x="-7.62" y="-7.62" length="short" rot="R180"/>
+<pin name="GND5" x="-7.62" y="-10.16" length="short" rot="R180"/>
+<pin name="VIN" x="-7.62" y="-12.7" length="short" rot="R180"/>
+<pin name="NC4" x="-7.62" y="-15.24" length="short" rot="R180"/>
+<pin name="PA0" x="-7.62" y="-17.78" length="short" rot="R180"/>
+<pin name="PA1" x="-7.62" y="-20.32" length="short" rot="R180"/>
+<pin name="PA4" x="-7.62" y="-22.86" length="short" rot="R180"/>
+<pin name="PB0" x="-7.62" y="-25.4" length="short" rot="R180"/>
+<pin name="PC1" x="-7.62" y="-27.94" length="short" rot="R180"/>
+<pin name="PC0" x="-7.62" y="-30.48" length="short" rot="R180"/>
+<wire x1="-27.94" y1="27.94" x2="-25.4" y2="27.94" width="0.1524" layer="94"/>
+<wire x1="-25.4" y1="27.94" x2="-10.16" y2="27.94" width="0.1524" layer="94"/>
+<wire x1="-10.16" y1="27.94" x2="-10.16" y2="-33.02" width="0.1524" layer="94"/>
+<wire x1="-10.16" y1="-33.02" x2="-25.4" y2="-33.02" width="0.1524" layer="94"/>
+<wire x1="-25.4" y1="-33.02" x2="-27.94" y2="-33.02" width="0.1524" layer="94"/>
+<wire x1="-27.94" y1="-33.02" x2="-27.94" y2="27.94" width="0.1524" layer="94"/>
+<pin name="GND6" x="38.1" y="25.4" length="short" rot="R180"/>
+<pin name="GND7" x="38.1" y="22.86" length="short" rot="R180"/>
+<pin name="PC9" x="15.24" y="15.24" length="short"/>
+<pin name="PB8" x="15.24" y="12.7" length="short"/>
+<pin name="PB9" x="15.24" y="10.16" length="short"/>
+<pin name="AVDD" x="15.24" y="7.62" length="short"/>
+<pin name="GND8" x="15.24" y="5.08" length="short"/>
+<pin name="PA5" x="15.24" y="2.54" length="short"/>
+<pin name="PA6" x="15.24" y="0" length="short"/>
+<pin name="PA7" x="15.24" y="-2.54" length="short"/>
+<pin name="PB6" x="15.24" y="-5.08" length="short"/>
+<pin name="PC7" x="15.24" y="-7.62" length="short"/>
+<pin name="PA9" x="15.24" y="-10.16" length="short"/>
+<pin name="PA8" x="15.24" y="-12.7" length="short"/>
+<pin name="PB10" x="15.24" y="-15.24" length="short"/>
+<pin name="PB4" x="15.24" y="-17.78" length="short"/>
+<pin name="PB5" x="15.24" y="-20.32" length="short"/>
+<pin name="PB3" x="15.24" y="-22.86" length="short"/>
+<pin name="PA10" x="15.24" y="-25.4" length="short"/>
+<pin name="PA2" x="15.24" y="-27.94" length="short"/>
+<pin name="PA3" x="15.24" y="-30.48" length="short"/>
+<pin name="PC8" x="38.1" y="15.24" length="short" rot="R180"/>
+<pin name="PC6" x="38.1" y="12.7" length="short" rot="R180"/>
+<pin name="PC5" x="38.1" y="10.16" length="short" rot="R180"/>
+<pin name="U5V" x="38.1" y="7.62" length="short" rot="R180"/>
+<pin name="NC6" x="38.1" y="5.08" length="short" rot="R180"/>
+<pin name="PA12" x="38.1" y="2.54" length="short" rot="R180"/>
+<pin name="PA11" x="38.1" y="0" length="short" rot="R180"/>
+<pin name="PB12" x="38.1" y="-2.54" length="short" rot="R180"/>
+<pin name="PB11" x="38.1" y="-5.08" length="short" rot="R180"/>
+<pin name="GND10" x="38.1" y="-7.62" length="short" rot="R180"/>
+<pin name="PB2" x="38.1" y="-10.16" length="short" rot="R180"/>
+<pin name="PB1" x="38.1" y="-12.7" length="short" rot="R180"/>
+<pin name="PB15" x="38.1" y="-15.24" length="short" rot="R180"/>
+<pin name="PB14" x="38.1" y="-17.78" length="short" rot="R180"/>
+<pin name="PB13" x="38.1" y="-20.32" length="short" rot="R180"/>
+<pin name="AGND" x="38.1" y="-22.86" length="short" rot="R180"/>
+<pin name="PC4" x="38.1" y="-25.4" length="short" rot="R180"/>
+<pin name="NC7" x="38.1" y="-27.94" length="short" rot="R180"/>
+<pin name="NC8" x="38.1" y="-30.48" length="short" rot="R180"/>
+<wire x1="17.78" y1="27.94" x2="33.02" y2="27.94" width="0.1524" layer="94"/>
+<wire x1="33.02" y1="27.94" x2="35.56" y2="27.94" width="0.1524" layer="94"/>
+<wire x1="35.56" y1="27.94" x2="35.56" y2="-33.02" width="0.1524" layer="94"/>
+<wire x1="35.56" y1="-33.02" x2="33.02" y2="-33.02" width="0.1524" layer="94"/>
+<wire x1="33.02" y1="-33.02" x2="17.78" y2="-33.02" width="0.1524" layer="94"/>
+<wire x1="17.78" y1="-33.02" x2="17.78" y2="27.94" width="0.1524" layer="94"/>
+<wire x1="-25.4" y1="27.94" x2="-25.4" y2="30.48" width="0.1524" layer="94"/>
+<wire x1="-25.4" y1="30.48" x2="33.02" y2="30.48" width="0.1524" layer="94"/>
+<wire x1="33.02" y1="30.48" x2="33.02" y2="27.94" width="0.1524" layer="94"/>
+<wire x1="-25.4" y1="-33.02" x2="-25.4" y2="-35.56" width="0.1524" layer="94"/>
+<wire x1="-25.4" y1="-35.56" x2="33.02" y2="-35.56" width="0.1524" layer="94"/>
+<wire x1="33.02" y1="-35.56" x2="33.02" y2="-33.02" width="0.1524" layer="94"/>
+</symbol>
+<symbol name="PINHD1">
+<wire x1="-6.35" y1="-2.54" x2="1.27" y2="-2.54" width="0.4064" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="1.27" y2="2.54" width="0.4064" layer="94"/>
+<wire x1="1.27" y1="2.54" x2="-6.35" y2="2.54" width="0.4064" layer="94"/>
+<wire x1="-6.35" y1="2.54" x2="-6.35" y2="-2.54" width="0.4064" layer="94"/>
+<text x="-6.35" y="3.175" size="1.778" layer="95">&gt;NAME</text>
+<text x="-6.35" y="-5.08" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="1" x="-2.54" y="0" visible="pad" length="short" direction="pas" function="dot"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="NUCLEO_STM32L432KC">
+<gates>
+<gate name="G$1" symbol="NUCLEO_STM32L432KC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="STM_NUCLEO32">
+<connects>
+<connect gate="G$1" pin="3V3" pad="17"/>
+<connect gate="G$1" pin="5V" pad="27"/>
+<connect gate="G$1" pin="A0_PA0" pad="19"/>
+<connect gate="G$1" pin="A2_PA3" pad="21"/>
+<connect gate="G$1" pin="A3_PA4" pad="22"/>
+<connect gate="G$1" pin="A4_PA5" pad="23"/>
+<connect gate="G$1" pin="A5_PA6" pad="24"/>
+<connect gate="G$1" pin="A6_PA7" pad="25"/>
+<connect gate="G$1" pin="A7_PA2" pad="26"/>
+<connect gate="G$1" pin="AREF" pad="18"/>
+<connect gate="G$1" pin="D0_PA10" pad="2"/>
+<connect gate="G$1" pin="D10_PA11" pad="13"/>
+<connect gate="G$1" pin="D11_PB5" pad="14"/>
+<connect gate="G$1" pin="D12_PB4" pad="15"/>
+<connect gate="G$1" pin="D13_PB3" pad="16"/>
+<connect gate="G$1" pin="D1_PA9" pad="1"/>
+<connect gate="G$1" pin="D2_PA12" pad="5"/>
+<connect gate="G$1" pin="D3_PB0" pad="6"/>
+<connect gate="G$1" pin="D4_PB7" pad="7"/>
+<connect gate="G$1" pin="D5_PB6" pad="8"/>
+<connect gate="G$1" pin="D6_PB1" pad="9"/>
+<connect gate="G$1" pin="D7_PC14" pad="10"/>
+<connect gate="G$1" pin="D8_PC15" pad="11"/>
+<connect gate="G$1" pin="D9_PA8" pad="12"/>
+<connect gate="G$1" pin="GND1" pad="4"/>
+<connect gate="G$1" pin="GND2" pad="29"/>
+<connect gate="G$1" pin="PA_PA1" pad="20"/>
+<connect gate="G$1" pin="RESET" pad="3"/>
+<connect gate="G$1" pin="RESET2" pad="28"/>
+<connect gate="G$1" pin="SHLD" pad="SHLD"/>
+<connect gate="G$1" pin="VIN" pad="30"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="RF4463F30" prefix="RF" uservalue="yes">
+<gates>
+<gate name="SI4463" symbol="RF4463F30" x="2.54" y="0"/>
+</gates>
+<devices>
+<device name="" package="RF4463F30">
+<connects>
+<connect gate="SI4463" pin="ANT" pad="16"/>
+<connect gate="SI4463" pin="CLK" pad="9"/>
+<connect gate="SI4463" pin="CS" pad="7"/>
+<connect gate="SI4463" pin="GND1" pad="8"/>
+<connect gate="SI4463" pin="GND2" pad="2"/>
+<connect gate="SI4463" pin="GPIO_0" pad="13"/>
+<connect gate="SI4463" pin="GPIO_1" pad="12"/>
+<connect gate="SI4463" pin="IRQ" pad="6"/>
+<connect gate="SI4463" pin="NC1" pad="4"/>
+<connect gate="SI4463" pin="NC2" pad="3"/>
+<connect gate="SI4463" pin="NC3" pad="14"/>
+<connect gate="SI4463" pin="RF_GND" pad="15"/>
+<connect gate="SI4463" pin="SDI" pad="10"/>
+<connect gate="SI4463" pin="SDN" pad="5"/>
+<connect gate="SI4463" pin="SDO" pad="11"/>
+<connect gate="SI4463" pin="SHLD_1" pad="SHLD_1"/>
+<connect gate="SI4463" pin="SHLD_2" pad="SHLD_2"/>
+<connect gate="SI4463" pin="SHLD_3" pad="SHLD_3"/>
+<connect gate="SI4463" pin="SHLD_4" pad="SHLD_4"/>
+<connect gate="SI4463" pin="VCC" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="ETH_WIZ_CLICK_W5500">
+<gates>
+<gate name="G$1" symbol="ETH_WIZ_CLICK_W5500" x="2.54" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="ETH_WIZ_CLICK">
+<connects>
+<connect gate="G$1" pin="3V3" pad="P$15"/>
+<connect gate="G$1" pin="CLK" pad="P$12"/>
+<connect gate="G$1" pin="CS" pad="P$11"/>
+<connect gate="G$1" pin="GND" pad="P$16"/>
+<connect gate="G$1" pin="GND2" pad="P$1"/>
+<connect gate="G$1" pin="INT" pad="P$7"/>
+<connect gate="G$1" pin="NC" pad="P$9"/>
+<connect gate="G$1" pin="NC2" pad="P$2"/>
+<connect gate="G$1" pin="NC3" pad="P$3"/>
+<connect gate="G$1" pin="NC4" pad="P$4"/>
+<connect gate="G$1" pin="NC5" pad="P$5"/>
+<connect gate="G$1" pin="NC6" pad="P$6"/>
+<connect gate="G$1" pin="NC7" pad="P$8"/>
+<connect gate="G$1" pin="RST" pad="P$10"/>
+<connect gate="G$1" pin="SDI" pad="P$14"/>
+<connect gate="G$1" pin="SDO" pad="P$13"/>
+<connect gate="G$1" pin="SHLD" pad="SHLD"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="VOLT_REGUL">
+<gates>
+<gate name="G$1" symbol="VOLT_REGUL" x="-2.54" y="0"/>
+</gates>
+<devices>
+<device name="" package="VOLT_REGUL">
+<connects>
+<connect gate="G$1" pin="IN+" pad="IN+"/>
+<connect gate="G$1" pin="IN-" pad="IN-"/>
+<connect gate="G$1" pin="OUT+" pad="OUT+"/>
+<connect gate="G$1" pin="OUT-" pad="OUT-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SRAM">
+<gates>
+<gate name="G$1" symbol="SPI_SRAM" x="-2.54" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="SO08">
+<connects>
+<connect gate="G$1" pin="CS" pad="1"/>
+<connect gate="G$1" pin="GND" pad="4"/>
+<connect gate="G$1" pin="HOLD" pad="7"/>
+<connect gate="G$1" pin="MISO" pad="2"/>
+<connect gate="G$1" pin="MOSI" pad="5"/>
+<connect gate="G$1" pin="SCK" pad="6"/>
+<connect gate="G$1" pin="SIO2" pad="3"/>
+<connect gate="G$1" pin="VCC" pad="8"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CON_5V">
+<gates>
+<gate name="G$1" symbol="CON_5V" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="CON_5V">
+<connects>
+<connect gate="G$1" pin="CENTER" pad="P$1"/>
+<connect gate="G$1" pin="GND" pad="P$2"/>
+<connect gate="G$1" pin="GND2" pad="P$3"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="POWER_CABLE">
+<gates>
+<gate name="G$1" symbol="POWER_CABLES" x="-2.54" y="0"/>
+</gates>
+<devices>
+<device name="" package="POWER_CABLES">
+<connects>
+<connect gate="G$1" pin="+" pad="P$1"/>
+<connect gate="G$1" pin="GND" pad="P$2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="REGUL">
+<gates>
+<gate name="G$1" symbol="REGUL" x="-2.54" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="TO220">
+<connects>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="3"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="MOUNT_HOLE">
+<gates>
+<gate name="G$1" symbol="MOUNT-PAD" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="3,6-PAD">
+<connects>
+<connect gate="G$1" pin="MOUNT" pad="B3,6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="BU-SMA-H" prefix="X">
+<description>FEMALE &lt;b&gt;SMA CONNECTOR&lt;/b&gt;&lt;p&gt;
+Radiall&lt;p&gt;</description>
+<gates>
+<gate name="G$1" symbol="BNC-FGND-1" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="BU-SMA-H">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2 3 4 5"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="W5500_LITE">
+<gates>
+<gate name="G$1" symbol="W5500LITE" x="7.62" y="0"/>
+</gates>
+<devices>
+<device name="USR-ES1" package="W5500LITE">
+<connects>
+<connect gate="G$1" pin="3V3" pad="P$11"/>
+<connect gate="G$1" pin="3V3." pad="P$10"/>
+<connect gate="G$1" pin="CS" pad="P$5"/>
+<connect gate="G$1" pin="GND" pad="P$12"/>
+<connect gate="G$1" pin="GND," pad="P$2"/>
+<connect gate="G$1" pin="GND." pad="P$1"/>
+<connect gate="G$1" pin="INT" pad="P$6"/>
+<connect gate="G$1" pin="MISO" pad="P$7"/>
+<connect gate="G$1" pin="MOSI" pad="P$3"/>
+<connect gate="G$1" pin="NC" pad="P$9"/>
+<connect gate="G$1" pin="RST" pad="P$8"/>
+<connect gate="G$1" pin="SLCK" pad="P$4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_D/7343_31W">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="D/7343-31W">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_CT6032">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="CT6032">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_CT3216">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="CT3216">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CPOL_B/3528_21W">
+<gates>
+<gate name="G$1" symbol="CPOL-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="B/3528-21W">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="NUCLEO_L476RG">
+<gates>
+<gate name="G$1" symbol="NUCLEO_L476" x="-2.54" y="2.54"/>
+</gates>
+<devices>
+<device name="" package="NUCLEO_64">
+<connects>
+<connect gate="G$1" pin="3V3" pad="A16"/>
+<connect gate="G$1" pin="5V" pad="A18"/>
+<connect gate="G$1" pin="AGND" pad="B32"/>
+<connect gate="G$1" pin="AVDD" pad="B7"/>
+<connect gate="G$1" pin="BOOT" pad="A7"/>
+<connect gate="G$1" pin="E5V" pad="A6"/>
+<connect gate="G$1" pin="GND" pad="A8"/>
+<connect gate="G$1" pin="GND1" pad="GND1"/>
+<connect gate="G$1" pin="GND10" pad="B20"/>
+<connect gate="G$1" pin="GND2" pad="GND2"/>
+<connect gate="G$1" pin="GND3" pad="A19"/>
+<connect gate="G$1" pin="GND4" pad="A20"/>
+<connect gate="G$1" pin="GND5" pad="A22"/>
+<connect gate="G$1" pin="GND6" pad="GND6"/>
+<connect gate="G$1" pin="GND7" pad="GND7"/>
+<connect gate="G$1" pin="GND8" pad="B9"/>
+<connect gate="G$1" pin="IOREF" pad="A12"/>
+<connect gate="G$1" pin="NC" pad="A9"/>
+<connect gate="G$1" pin="NC2" pad="A11"/>
+<connect gate="G$1" pin="NC3" pad="A10"/>
+<connect gate="G$1" pin="NC4" pad="A26"/>
+<connect gate="G$1" pin="NC6" pad="B10"/>
+<connect gate="G$1" pin="NC7" pad="B36"/>
+<connect gate="G$1" pin="NC8" pad="B38"/>
+<connect gate="G$1" pin="PA0" pad="A28"/>
+<connect gate="G$1" pin="PA1" pad="A30"/>
+<connect gate="G$1" pin="PA10" pad="B33"/>
+<connect gate="G$1" pin="PA11" pad="B14"/>
+<connect gate="G$1" pin="PA12" pad="B12"/>
+<connect gate="G$1" pin="PA13" pad="A13"/>
+<connect gate="G$1" pin="PA14" pad="A15"/>
+<connect gate="G$1" pin="PA15" pad="A17"/>
+<connect gate="G$1" pin="PA2" pad="B35"/>
+<connect gate="G$1" pin="PA3" pad="B37"/>
+<connect gate="G$1" pin="PA4" pad="A32"/>
+<connect gate="G$1" pin="PA5" pad="B11"/>
+<connect gate="G$1" pin="PA6" pad="B13"/>
+<connect gate="G$1" pin="PA7" pad="B15"/>
+<connect gate="G$1" pin="PA8" pad="B23"/>
+<connect gate="G$1" pin="PA9" pad="B21"/>
+<connect gate="G$1" pin="PB0" pad="A34"/>
+<connect gate="G$1" pin="PB1" pad="B24"/>
+<connect gate="G$1" pin="PB10" pad="B25"/>
+<connect gate="G$1" pin="PB11" pad="B18"/>
+<connect gate="G$1" pin="PB12" pad="B16"/>
+<connect gate="G$1" pin="PB13" pad="B30"/>
+<connect gate="G$1" pin="PB14" pad="B28"/>
+<connect gate="G$1" pin="PB15" pad="B26"/>
+<connect gate="G$1" pin="PB2" pad="B22"/>
+<connect gate="G$1" pin="PB3" pad="B31"/>
+<connect gate="G$1" pin="PB4" pad="B27"/>
+<connect gate="G$1" pin="PB5" pad="B29"/>
+<connect gate="G$1" pin="PB6" pad="B17"/>
+<connect gate="G$1" pin="PB7" pad="A21"/>
+<connect gate="G$1" pin="PB8" pad="B3"/>
+<connect gate="G$1" pin="PB9" pad="B5"/>
+<connect gate="G$1" pin="PC0" pad="A38"/>
+<connect gate="G$1" pin="PC1" pad="A36"/>
+<connect gate="G$1" pin="PC10" pad="A1"/>
+<connect gate="G$1" pin="PC11" pad="A2"/>
+<connect gate="G$1" pin="PC12" pad="A3"/>
+<connect gate="G$1" pin="PC13" pad="A23"/>
+<connect gate="G$1" pin="PC14" pad="A25"/>
+<connect gate="G$1" pin="PC15" pad="A27"/>
+<connect gate="G$1" pin="PC2" pad="A35"/>
+<connect gate="G$1" pin="PC3" pad="A37"/>
+<connect gate="G$1" pin="PC4" pad="B34"/>
+<connect gate="G$1" pin="PC5" pad="B6"/>
+<connect gate="G$1" pin="PC6" pad="B4"/>
+<connect gate="G$1" pin="PC7" pad="B19"/>
+<connect gate="G$1" pin="PC8" pad="B2"/>
+<connect gate="G$1" pin="PC9" pad="B1"/>
+<connect gate="G$1" pin="PD2" pad="A4"/>
+<connect gate="G$1" pin="PH0" pad="A29"/>
+<connect gate="G$1" pin="PH1" pad="A31"/>
+<connect gate="G$1" pin="RESET" pad="A14"/>
+<connect gate="G$1" pin="U5V" pad="B8"/>
+<connect gate="G$1" pin="VBAT" pad="A33"/>
+<connect gate="G$1" pin="VDD" pad="A5"/>
+<connect gate="G$1" pin="VIN" pad="A24"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="PINHEAD1X">
+<gates>
+<gate name="G$1" symbol="PINHD1" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="1X01">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/NPR70_modem_v05_PCB/montage.png b/NPR70_modem_v05_PCB/montage.png
new file mode 100755
index 0000000..6c838c4
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diff --git a/NPR70_modem_v05_PCB/montage1.png b/NPR70_modem_v05_PCB/montage1.png
new file mode 100755
index 0000000..1513f6b
Binary files /dev/null and b/NPR70_modem_v05_PCB/montage1.png differ
diff --git a/NPR70_modem_v05_PCB/sch_NPR70_v05.pdf b/NPR70_modem_v05_PCB/sch_NPR70_v05.pdf
new file mode 100755
index 0000000..db6bbe6
Binary files /dev/null and b/NPR70_modem_v05_PCB/sch_NPR70_v05.pdf differ
diff --git a/NPR_14.bin b/NPR_14.bin
new file mode 100755
index 0000000..41eee60
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/.mbed b/NPR_FW_source_2020_06_29/NPR_14/.mbed
new file mode 100755
index 0000000..a0584aa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/.mbed
@@ -0,0 +1,3 @@
+ROOT=.
+TARGET=NUCLEO_L432KC
+TOOLCHAIN=GCC_ARM
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.bin b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.bin
new file mode 100755
index 0000000..41eee60
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.bin differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.elf b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.elf
new file mode 100755
index 0000000..918fc40
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.elf differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.hex b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.hex
new file mode 100755
index 0000000..03d615f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.hex
@@ -0,0 +1,8988 @@
+:020000040800F2
+:1000000000000120FD3E0008353F0008353F000894
+:10001000353F0008353F0008353F0008000000006C
+:100020000000000000000000000000008521000822
+:10003000353F0008000000001B2200082B220008AA
+:10004000353F0008353F0008353F0008353F0008C0
+:10005000353F0008353F0008353F0008353F0008B0
+:10006000353F0008353F0008353F0008353F0008A0
+:10007000353F0008353F0008353F0008353F000890
+:10008000353F0008353F0008353F0008056F000880
+:10009000096E0008353F0008096F0008353F000869
+:1000A000353F0008353F0008353F0008353F000860
+:1000B000353F00080000000000000000353F000848
+:1000C000353F00080000000000000000353F000838
+:1000D00000000000353F0008353F00080000000028
+:1000E000353F0008353F0008000000000000000018
+:1000F0000000000000000000000000000000000000
+:10010000000000000000000000000000353F000873
+:100110000000000000000000353F0008353F0008E7
+:10012000353F0008353F0008353F0008353F0008DF
+:10013000353F000800000000000000000000000043
+:10014000353F0008353F0008353F0008353F0008BF
+:10015000353F0008353F0008353F0008353F0008AF
+:10016000353F0008353F0008353F0008000000001B
+:10017000353F0008353F0008000000000000000087
+:10018000353F0008353F0008353F00080348044B61
+:10019000834202D0034B03B118477047900E0020F2
+:1001A000900E002000000000054806490B1AD90FE8
+:1001B00001EBA301491002D0034B03B1184770476C
+:1001C000900E0020900E00200000000010B5064C9C
+:1001D000237843B9FFF7DAFF044B13B10448AFF3B8
+:1001E00000800123237010BD900E0020000000004D
+:1001F0004C24020808B5044B1BB104490448AFF372
+:100200000080BDE80840CFE700000000940E002009
+:100210004C240208A3F5803A704700BF154B002B11
+:1002200008BF114B9D46FFF7F5FF00218B460F4697
+:100230001148124A121A10F051FF0C4B002B00D03B
+:1002400098470B4B002B00D098470020002104005A
+:100250000D000B4801F0E7FC10F082FA20002900A5
+:1002600001F0BEFE01F0DCFC000008000000000010
+:10027000F11F000800000120900E002004E600207D
+:1002800089FC0008036818470B68036070477047D3
+:10029000C36810B504460BB19B689847204610BD53
+:1002A000884238B504460D4609D0FFF7F1FFEB68E8
+:1002B0001BB15B68294620469847EB68E3602046FF
+:1002C00038BD7047704738B515460C4606F0DAFB66
+:1002D000B5FBF0F200FB12553DB9B4FBF0F300FBA7
+:1002E0001341B1FA81F0400938BD0020FCE700005D
+:1002F00070B50546044655F8043B73B90C4E4FF0F3
+:10030000FF31306802F0B8FF23681BB9284601F0BE
+:10031000C5FD2560306802F0CDFF2368AB4204D0F4
+:10032000044905485B2201F029FA206870BD00BF2E
+:10033000A8E20020E8D301080DD4010838B50B4D20
+:1003400004462846FFF7D4FF4FF0FF3101F0ADFD22
+:10035000204606F0EDFA04462846FFF7C9FF01F0F3
+:10036000A7FD201E18BF0120404238BDE00E00202E
+:1003700038B50B4D04462846FFF7BAFF4FF0FF3162
+:1003800001F093FD204606F0D5FA04462846FFF713
+:10039000AFFF01F08DFD201E18BF0120404238BD87
+:1003A000E00E0020F7B50D4F019304463846154680
+:1003B0000E46FFF79DFF4FF0FF3101F076FD019BE8
+:1003C00032462946204600F091FD04463846FFF7A4
+:1003D0008FFF01F06DFD204603B0F0BDE00E002060
+:1003E0002DE9F04114461D460746884606F068FB95
+:1003F00021460646384606F045FBB4FBF6F306FBFD
+:10040000134333BBB5FBF6F306FB13530BBBB542EB
+:100410001FD3B4FBF0F300FB13432B44834218D8E3
+:100420000D48FFF765FF4FF0FF3101F03EFD21461B
+:100430002B464246384606F0CDFA003818BF012058
+:1004400044420548FFF754FF01F032FD2046BDE865
+:10045000F0814FF0FF34F9E7E00E0020F8B50646D2
+:100460000D461446FFF72FFF20B31448FFF740FF57
+:100470004FF0FF3101F019FD34B12946304606F046
+:100480005BFA40B14FF0FF340C48FFF731FF01F049
+:100490000FFD2046F8BD2946304606F0F3FA224605
+:1004A000074629463046FFF70EFF0028EAD0E41B36
+:1004B0003D44E1E74FF0FF34EBE700BFE00E0020E2
+:1004C000C36810B504460BB19B689847204610BD21
+:1004D000F8B50546144B45F8043B04460E4604F1B6
+:1004E00020071C220021284610F0F8FD10220021D0
+:1004F000384610F0F3FD1022002104F1300010F016
+:10050000EDFD1022002104F1400010F0E7FD074A44
+:1005100023463146384606F071FE2846314600F043
+:1005200012FD2046F8BD00BF50D401084D0600085A
+:1005300083681A6843681A4214BF0120002070477C
+:1005400083681A6843681A4214BF0120002070476C
+:1005500010B5084B044640F8203B06F00FFF04F1AD
+:100560004000FFF795FE04F13000FFF791FE2046B2
+:1005700010BD00BF50D4010810B50446FFF7E8FFD6
+:10058000204601F07BFB204610BDF0B50D4685B03E
+:10059000044601F075F9EE6804F13007203466B1C5
+:1005A00029463846FFF77CFE01220121204606F04D
+:1005B000B5FD01F091F905B0F0BD10223146684655
+:1005C00010F08CFD69463846FFF76AFE6846FFF773
+:1005D0005FFE3246E9E7F0B50D4685B0044601F00E
+:1005E0004FF9EE6804F14007203466B129463846D9
+:1005F000FFF756FE01220221204606F08FFD01F092
+:100600006BF905B0F0BD10223146684610F066FD6A
+:1006100069463846FFF744FE6846FFF739FE324622
+:10062000E9E70000C36810B504462BB90549064840
+:1006300040F20E2201F0A2F8E36820461B68BDE8F4
+:100640001040184721D4010842D40108012908B5F7
+:1006500002D0022907D008BDC36B002BFBD030307D
+:10066000FFF7E0FFF7E7C36C002BF4D04030F7E76B
+:1006700038B5102204460D4619B910F02FFD20465A
+:1006800038BD002110F02AFD014B2560E360F6E73C
+:1006900058D4010870B4044670B1D2E9005000F09B
+:1006A000010205B942B1461004EB60000AB1A3593A
+:1006B0005D592B4670BC184770BC7047043007F07A
+:1006C0000FBA000037B50A4D2B68834204460CD0A0
+:1006D000D4E9361204300023019007F04BF9D4F826
+:1006E000E010019807F070F92C6003B030BD00BF36
+:1006F000AC0F0020036870B5DB6804460D46164653
+:1007000098470B4B1B68A342C4E936560BD1002314
+:1007100032462946201D07F02DF9236820461B6923
+:10072000BDE8704018472046FFF7CCFFF5E700BF53
+:10073000AC0F0020036870B5DB6804460D4698478F
+:10074000094BC4F8E0501B68A34209D12946201D7B
+:1007500007F03AF9236820461B69BDE87040184746
+:100760002046FFF7AFFFF5E7AC0F002037B5036871
+:1007700001910446DB6898472046FFF7A3FF0199E3
+:10078000201D07F041F9236805461B69204698475C
+:10079000284603B030BD30B5056887B00446CDE9C2
+:1007A00004210393ED68A8472046FFF78BFF94F8D8
+:1007B000E40001900A9805990090DDE90332201DBC
+:1007C00007F053F9236805461B69204698472846D9
+:1007D00007B030BD2DE9F04106469046254A46F85F
+:1007E000042B86B0044600250F469C22002130468B
+:1007F000039310F073FCCDE9045506AB13E9030035
+:1008000004F1A40282E803001B49C4F8AC1048F2CA
+:100810000701C4F8B010C4F8B850C4F8B440C4F824
+:10082000BC20164AC4F8C020BFF36F8FBFF34F8FB0
+:100830001022294604F1C40010F050FC0822C4E93B
+:1008400036250F4AC4F8E020FF2284F8E420BDF9E1
+:100850003020039B009239464246304684F8D450FB
+:1008600006F0E4FF2046FFF72DFF204606B0BDE866
+:10087000F08100BF6CD4010801A090E89506000843
+:1008800040420F0010B5044B044640F8C43BFFF74C
+:1008900017FE204610BD00BF6CD4010810B50446F9
+:1008A000FFF7F0FF204601F0E9F9204610BD10B532
+:1008B000044630B14430FFF703FE04F11800FFF79F
+:1008C000FFFD204610BD10B500210446282240F847
+:1008D000041B10F003FC1022002104F1180010F09A
+:1008E000FDFB204610BD000008B50448FFF700FDE1
+:1008F000BDE808404FF0FF3101F0D7BA780F002073
+:1009000008B50348FFF7F4FCBDE8084001F0D0BA91
+:10091000780F002010B50A4C2046FFF7D4FF04F1F1
+:100920002C00FFF7D0FF0023A3652046E365054AAE
+:1009300084F860300449BDE8104001F06FB900BF91
+:10094000140F002088010020AF08000803681B690D
+:10095000184703689B69184703689B6A18474FF05C
+:10096000FF30704711207047704700F0A9B8A0F120
+:100970004C00FFF7FABF00F0A6B8A0F14C00FFF75B
+:10098000FABF4FF0FF31643001F08FBAA0F14C0094
+:10099000FFF7F7BF643001F08BBAA0F14C00FFF70E
+:1009A000F9BF00000B4B10B503F10802026003F120
+:1009B000280284330446C2640365643001F07BFA84
+:1009C00004F14C0000F09AFE204600F009F92046A0
+:1009D00010BD00BF88D40108A0F14C00E2E7A0F1EF
+:1009E0005000DFE710B50446FFF7DCFF204601F0BA
+:1009F00045F9204610BDA0F14C00F3E7A0F15000EE
+:100A0000F0E7000038B504461D46049B00F062F88C
+:100A1000294604F14C0000F049FE074B03F108029F
+:100A2000226003F128028433E264236504F1640048
+:100A300001F034FA204638BD88D401087047000020
+:100A4000090170B501F128050544EB6873B144183C
+:100A5000636B2BB90649074840F20E2200F08EFE68
+:100A6000636B28461B68BDE87040184770BD00BF27
+:100A700021D4010842D4010870B50646044656F850
+:100A8000043B0D461B6898473046294606F002F99C
+:100A90002368A56420465B68BDE87040184738B5F8
+:100AA0000546044655F8043B1B689847284606F05F
+:100AB00079FE236805465B6820469847284638BD7E
+:100AC000043006F059B910B504300C4606F06AF946
+:100AD000204610BD2DE9FF4705469846224B45F8B4
+:100AE000043B04460E46174604F1280A242200213E
+:100AF000284610F0F3FA04F138091022002150467C
+:100B000010F0ECFA10220021484610F0E7FA10220B
+:100B1000C4F848800021684610F0E0FA6946504663
+:100B2000FFF7BEFB6846FFF7B3FB102200216846C3
+:100B300010F0D4FA69464846FFF7B2FB6846FFF763
+:100B4000A7FB3A463146284605F0FEFFA16C284631
+:100B500006F0A0F828460549224606F09FF82046F0
+:100B600004B0BDE8F08700BF1CD50108410A0008A9
+:100B70002DE9FF410368044615460F461B6804EB48
+:100B800005169847283600F07BFEFA68F36804F1F2
+:100B90000408A2B10BB900F057FA39463046FFF706
+:100BA0007FFB01222946404606F084F800F094FEBF
+:100BB000236820465B68984704B0BDE8F0810BB11C
+:100BC00000F05CFA10220021684610F087FA6946AE
+:100BD0003046FFF765FB6846FFF75AFB0022E1E766
+:100BE0001FB5144B0360044610220021684610F024
+:100BF00075FA694600222046FFF7BAFF6846FFF7FC
+:100C000047FB10220021684610F068FA012269466D
+:100C10002046FFF7ADFF6846FFF73AFB04F13800C6
+:100C2000FFF736FB04F12800FFF732FB204604B043
+:100C300010BD00BF1CD5010810B50446FFF7D0FF5A
+:100C4000204601F01BF8204610BD70B5D0E908130E
+:100C5000D0E902250446521845EB030300F022F9BF
+:100C6000636B2BB104F128001B68BDE87040184786
+:100C700070BD70B5044615461E4600F001FE2046C4
+:100C800000F01AF9C4E90856A06900F0CDFB42193A
+:100C900041EB0603204600F005F9BDE8704000F086
+:100CA0001BBE30B5044685B000F0EAFD204600F0DA
+:100CB00003F9636B23B194F838300BB100F0DEF91F
+:100CC0001022002104F12805684610F007FA284692
+:100CD000FFF7DEFA039B1BB15B686946284698471D
+:100CE000039B63636846FFF7D3FA00F0F5FD05B098
+:100CF00030BD000038B50546064B45F8283B044694
+:100D0000FFF7CFFF2846FFF7C3FA204600F0DAF8D6
+:100D1000204638BD34D5010810B50446FFF7EAFF78
+:100D2000204600F0ABFF204610BD0000436B70B5BD
+:100D3000044600F128052BB90549064840F20E2269
+:100D400000F01CFD636B28461B68BDE87040184727
+:100D500021D4010842D4010810B5034B03600446B6
+:100D6000FFF7C8FF204610BD48D5010810B504465E
+:100D7000FFF7F2FF204600F081FF204610BD10B5BE
+:100D8000044600F07DFD23681BB1237F0BB100F00A
+:100D900075F90023236000F09FFD204610BD10B5BB
+:100DA000044600F06DFD236853B9237F0BB100F0BA
+:100DB0004BF9A06900F038FBC4E90201012323606C
+:100DC000BDE8104000F088BD38B5044600F058FD7D
+:100DD000236863B1A06900F027FBD4E90235C41A87
+:100DE00061EB050500F078FD2046294638BD00245A
+:100DF0002546F7E773B5054600F042FD2846D5E9DC
+:100E00000446FFF7E1FF201846EB01010190009135
+:100E100000F062FDDDE9001002B070BD08B5FFF71B
+:100E2000E9FF08BD10B5044600F02AFDA06900F0F6
+:100E3000FBFA00220023C4E90201C4E90423BDE84F
+:100E4000104000F049BD002310B5002203600023CC
+:100E5000C0E90223C0E90423044600F0F9FA0123A3
+:100E6000A06123772046FFF7DDFF204610BD036811
+:100E70009B681847094B10B5002203600023C0E9A6
+:100E800002230023C0E90433044600F0E1FA0449D8
+:100E9000A06100F057FA204610BD00BF5CD50108E4
+:100EA0006F0E000807B5009000F10801806900F09E
+:100EB00077FA03B05DF804FB00F10801806900F0E7
+:100EC00098BA000010B5034B03600446FFF7F4FF27
+:100ED000204610BD5CD50108036801221B69002172
+:100EE0001847036800221B691146184708B51046C9
+:100EF0001A460FF0EDFF002008BD70B50E460446FF
+:100F0000154606F065F8013609D02046002106F0A6
+:100F100085F829462046BDE8704006F07BB870BDD4
+:100F200038B5036804460D465AB1826813602046FE
+:100F3000012106F073F829462046BDE8384006F046
+:100F400069B8C268F2E70022FFF7D7BF37B50D4690
+:100F50000446019206F03CF8013507D0019A0021C1
+:100F6000204603B0BDE83040FFF7DABF03B030BD24
+:100F70000022FFF7EBBF000010B50446601C0DD146
+:100F800010BDA34209D12046896806F0E9FA20463F
+:100F90000021BDE8104006F07DBB0C31B1F90030F6
+:100FA0005A1CEED1BDE81040014800F0CDBC00BF96
+:100FB00068D50108884208B508D0431C06D0013125
+:100FC00006D0044800F0C0FC4FF0FF31084608BDD1
+:100FD0000146FBE779D50108B1F900305A1C01D16F
+:100FE00018467047834201D1486870470C31F3E7D7
+:100FF000421C10B5044607D0FFF7EEFF431C044621
+:1010000002D1024800F0A0FC204610BD8AD501089C
+:10101000B1F900305A1C01D118467047834201D102
+:10102000886870470C31F3E7421C10B5044607D0BE
+:10103000FFF7EEFF431C044602D1024800F084FC97
+:10104000204610BDAAD5010808B500F019FC094BCF
+:101050001A884FF6FF739A4204D100F03DFC06480F
+:1010600000F072FC0348012100F054FCBDE8084088
+:1010700000F032BCB00F0020C8D5010808B500F060
+:10108000FFFB084B1B8823B900F026FC064800F044
+:101090005BFC0448012100F04AFCBDE8084000F078
+:1010A0001BBC00BFB00F0020F5D5010808B500F04B
+:1010B000E7FB06F093FBBDE8084000F00DBC000024
+:1010C0002DE9F047D0E9003405465B6898476B6826
+:1010D0001B6A83422ED0236AE2682062C31A13403F
+:1010E0002848A26882429C464FF0000E1AD0B2F502
+:1010F000004FD4E90A5AA3FB000128D1C0F30E0324
+:101100005E194FF0000242EB0A07002F4FEAD03C75
+:1011100008BFB6F5004F4CEA414C4FEAD13E0BD226
+:10112000C4E90A67D4E90C0110EB0C0041EB0E0195
+:10113000C4E90C01BDE8F0871CF1010C4EF1000E72
+:10114000B6F5004247F1FF33C4E90A23EAE7002776
+:101150003B4616461BF07AFF12EB050843EB0A09E3
+:10116000B94508BFB04584468E4602D2C4E90A8913
+:10117000D8E710F1010C41F1000EB8EB060269EB63
+:101180000703E1E740420F00824206D98A420BD9A9
+:10119000884294BF002001207047884206D98A42C5
+:1011A0008CBF00200120704701207047002070474D
+:1011B0002DE9F3470646D0F80480FFF781FF7768F2
+:1011C000D6F800907B68002B4CD0D7E90C01D3E90E
+:1011D0000023994208BF904205D3D9F8143002B0D9
+:1011E000BDE8F0471847141A63EB0105D7E9062359
+:1011F000AB4208BFA242D7F810A006D3BB68224A70
+:10120000934219D1A24528BFA2463A6AD9F81030B4
+:101210009244FA680AEA020210460192984733683B
+:101220005B689847019A0146D8F82000FFF7ACFFA9
+:1012300030B333685B69D2E7B3F5004F0BD1E903F4
+:10124000114A0023E00341EA54411BF0FFFE8245AE
+:1012500028BF8246D9E7A3FB040103FB05110A4A14
+:101260000023F2E7D8F81030D8F82000D8F80C2086
+:101270001844D9F81030104002B0BDE8F0471847C4
+:1012800002B0BDE8F08700BF40420F002DE9F84FE3
+:10129000036804461B68984723689B69984705685C
+:1012A00006462DB924492548254D292200F066FA25
+:1012B0007668331F1C2B05D91F4920482F2200F0C8
+:1012C0005DFA2026331F072715F1FF3807FA03F7C9
+:1012D0001B494FF0000343F1FF39C1FB07892A4640
+:1012E000404649461BF0B2FED4F804800023C8E90A
+:1012F000003323685B688A46834698470122636807
+:10130000C8F8200002FA06F64FF000084FF0000976
+:10131000013E2046C3E90A89C3E90367C3E906BA67
+:10132000C3E90C899D6083F83820FFF7C9FE204689
+:10133000BDE8F84FFFF73CBF1BD601083CD60108BB
+:1013400040420F0038B5436893F8383004460D46E4
+:101350000BB9FFF79BFF63681D6038BD036870B56C
+:10136000DB680446984763685B68A3B12046FFF7D3
+:10137000A7FE65686E68D5E90C01D6E9002399429D
+:1013800008BF904207D3F3686B602B68002BEAD04C
+:10139000B0689847E7E72046BDE87040FFF708BF10
+:1013A0002DE9F7430A9D01900C469046994600F0BE
+:1013B00067FA0198FFF784FE0198A5604168C4E9C7
+:1013C00000894B6800224BB9E36082B94C60FFF79B
+:1013D000EFFE03B0BDE8F04300F07EBAD3E900674A
+:1013E000B94508BFB045EFD31A46DB68EBE7D460D8
+:1013F000EDE738B505460C4600F042FA6A685368D6
+:10140000A34209D1DB6853602846FFF7D1FEBDE84F
+:10141000384000F061BA1346002BF8D0DA68A242D7
+:10142000F9D1E268DA60F2E7436893F8383010B532
+:1014300004460BB9FFF72AFF2046FFF741FE636819
+:10144000D3E90C0110BD08B5FFF7EEFF08BD0000A1
+:101450000048704740D601080148FFF77FBF00BF32
+:1014600040D60108007B704738B50E4B036000235F
+:10147000C0E90131027304460B480D46FEF738FF00
+:101480004FF0FF3100F011FD55B1084B1A68626052
+:101490001C600548FEF72CFF00F00AFD204638BD11
+:1014A0006560F6E76CD60108FC0F0020F80F0020FD
+:1014B000124B10B5036004461148FEF719FF4FF0B8
+:1014C000FF3100F0F2FCA3682BB10E4962680B6893
+:1014D000A3420CD10A600A48FEF70AFF00F0E8FCBC
+:1014E000237B13B9201F00F0D1FB204610BD194605
+:1014F0005B68A342FBD14A60EDE700BF6CD60108F0
+:10150000FC0F0020F80F002010B50446FFF7D0FFB5
+:10151000204600F0B3FB204610BD000070B5064623
+:101520000F480D46FEF7E4FE4FF0FF3100F0BDFC22
+:101530000C4B1C685CB1A06880B12A46314610F0A3
+:101540006DFD58B9A06810F0FBFCA84206D1044814
+:10155000FEF7CEFE00F0ACFC204670BD6468E9E703
+:10156000FC0F0020F80F002000207047002070477B
+:10157000036870B51B690122002104469847051EC7
+:101580000DDB236802221B6900212046984723684F
+:10159000064629461B6900222046984735462846BC
+:1015A00070BD00F045BB10B50A7800232F2AC0E9B2
+:1015B000003304460DD14A785AB1481C20601946C0
+:1015C00023681A782F2A06D101332360FFF7A6FF7C
+:1015D0006060204610BD002AF8D00133013123603D
+:1015E000EEE700687047406808B520B1FFF73AFFA2
+:1015F000431E5842584108BD10B50446FFF7F3FF9B
+:1016000010B1606800B1043810BD406808B520B161
+:10161000FFF728FFB0FA80F0400908BD10B5044676
+:10162000FFF7F3FF10B1606800B1043810BD4068E7
+:10163000003818BF0120704770477047002070477E
+:10164000F8B50368DB6C0D4604468F1898472E46A4
+:10165000BE42236806D05B6C16F8011B20469847F3
+:101660000130F5D1236820461B6D9847701BF8BDEB
+:10167000F8B50368DB6C0D4604468F1898472E4674
+:10168000BE42236807D09B6C20469847431C02D07B
+:1016900006F8010BF4E7236820461B6D9847701B82
+:1016A000F8BD002070470020704770470F4B10B501
+:1016B0000022044640F8043BFFF7D6FE0C4B2360A3
+:1016C0005C33636000230B4963612046FFF769FFC9
+:1016D000606118B100F0A9FA204610BD0EF0CAF8FA
+:1016E0000168054800F030F9F6E700BF7CD6010834
+:1016F00048D70108C0D60108C3D601080A4B03F138
+:101700000802643310B504460260436040690EF07D
+:10171000FBF8064B236020464C3340F8043FFFF7AC
+:10172000C7FE204610BD00BF40D70108ECD6010817
+:101730000EB43FB507AD036855F8041BDB6C01918F
+:1017400004469847606903950EF094F9039A01994D
+:10175000606914F023FA236805461B6D20469847FC
+:10176000284604B0BDE8304003B070470FF0A6B87B
+:101770000FF09ABD0EF03CBB0EF04CB837B50446E6
+:101780000D46019200F07CF8019B05482A4621464F
+:1017900000F05CF803B0BDE8304000F003B800BFD3
+:1017A000ACD7010810B588B000F06AF8132101A881
+:1017B000FFF7DEFB0424039B019A1A60962000F0D9
+:1017C0003AFB049B019A1A60962000F034FB013C1E
+:1017D000F1D10424039B019A1A604FF4C87000F001
+:1017E0002AFB049B019A1A604FF4C87000F023FB97
+:1017F000013CEFD1DEE70000F0B5A3B0019000910D
+:1018000000F03EF8DDE90032802102A814F040FA31
+:10181000051E12DD0B4B1B6823B90B480F2202215A
+:1018200005F092F9084F02AC002614F8011B384667
+:10183000013605F0B7FAB542F7D100F04DF823B004
+:10184000F0BD00BFFC170020A0E500200FB407B5D5
+:1018500004A951F8040B0191FFF7CEFF03B05DF826
+:1018600004EB04B07047EFF31080C04300F00100B8
+:101870007047EFF30580003818BF01207047000063
+:1018800038B5FFF7F0FF054672B60E4C236823B952
+:101890000D4A80F00103DBB213702368013304D1D9
+:1018A0000A490B484322FFF769FF23682BB125B192
+:1018B000064908484722FFF761FF23680133236088
+:1018C00038BD00BF3410002030100020DDD70108E3
+:1018D00001D8010827D8010810B50A4C236883B144
+:1018E000FFF7C1FF20B1084908485822FFF746FF1B
+:1018F0002368013B236023681BB9054B1B7803B9A0
+:1019000062B610BD34100020DDD7010827D80108C9
+:101910003010002038B505460C46FFF7B1FF288887
+:101920000444A4B22C80FFF7D7FF204638BD38B559
+:1019300005460C46FFF7A4FF2B88191B8CB22C80A0
+:10194000FFF7CAFF204638BD0FB413B5084B1A780D
+:101950004AB90498012405A91C700191FFF74CFFB6
+:10196000204600F05DF902B0BDE8104004B07047B9
+:101970003810002008B5084B1B685BB907480221E6
+:101980000F2205F0E1F8BDE8084004484FF4165175
+:1019900005F080B908BD00BFFC170020A0E50020BD
+:1019A000022810B501DC002010BD0C4AC31E002126
+:1019B00052F8230042F8231030B90DF05BFF0923E1
+:1019C00003604FF0FF30EFE703685B699847041E40
+:1019D000E9DA0DF04FFF64420460F2E73C100020AA
+:1019E000F8B505460E461446FFF743FFA0B1194867
+:1019F000FFF7AAFF022D14DC174B1B680BB9FFF78A
+:101A0000B9FF35463719154EBD4215D015F8011BE3
+:101A1000304605F0C7F9F7E7FFF725FF0028E6D0C5
+:101A2000E8E70F4B033D53F8250038B90DF022FFCE
+:101A3000092303604FF0FF342046F8BD03682246B7
+:101A4000DB6831469847041EF6DA0DF013FF634257
+:101A50000360F1E73BD80108FC170020A0E5002057
+:101A60003C10002070B504460D461646FFF701FFF6
+:101A700080B11748FFF768FF022C10DC154B1B687C
+:101A80000BB9FFF777FF144805F076F901242870A9
+:101A9000204670BDFFF7E7FE0028EAD0ECE70F4BC9
+:101AA000033C53F8240030B90DF0E4FE0923036031
+:101AB0004FF0FF34ECE7036832469B6829469847AD
+:101AC000041EE5DA0DF0D6FE63420360E0E700BFD6
+:101AD00075D80108FC170020A0E500203C1000206C
+:101AE000022810B516DD0C4B033853F820402CB9F2
+:101AF0000DF0C0FE09230360204610BD2368204678
+:101B0000DB699847041EF7DA0DF0B4FE6442046006
+:101B10000024F1E70124EFE73C100020022810B573
+:101B200007DC0DF0A7FE1D2303604FF0FF342046B5
+:101B300010BD094B033853F8200018B90DF09AFE78
+:101B40000923F1E703681B699847041EEFDA0DF0DB
+:101B500091FE64420460E8E73C100020022838B59A
+:101B60000C4604DC4FF400534B6000200AE00E4B9F
+:101B7000033853F8205035B90DF07CFE092303607B
+:101B80004FF0FF3038BD2B682846DB6998470028A6
+:101B900014BF4FF400534FF4004363602B68284692
+:101BA0009B6A98472061E0E73C10002008B50120BF
+:101BB00000F036F80C4A116810B50B18EFF30880E6
+:101BC000834206D3094B0C221A604FF0FF310846BE
+:101BD00010BD0748046824B10648006820448342C9
+:101BE000F0D21360F3E700BF8C01002000E6002074
+:101BF0007011002074110020074D08B52B680446B1
+:101C000098680DF037FF2B68D8680DF033FF0CB1E2
+:101C1000FFF7C8FDFEE700BFC804002001207047A1
+:101C200008B5FFF7E9FF0120704700210FF0F4BD70
+:101C30001FB504220C463A230DEB020101900DF171
+:101C400009008DF808300FF043F9214602A80EF084
+:101C500077F8044638B101980368DB69984710B1FA
+:101C60002046FFF7E2FF204604B010BD08B500F0A3
+:101C7000DFF908BD08B500F0E3F908BD08B10EF0C2
+:101C800015BE704700487047B4D8010810B5044627
+:101C90000C48FEF72DFB4FF0FF3100F006F90A4A21
+:101CA0004023002152F8040BA04208BF42F8041C54
+:101CB000013BF7D10348FEF71BFBBDE8104000F0E5
+:101CC000F7B800BF3C1100203C1000202DE9F04384
+:101CD000884685B0434905460FF056FF044628B9AB
+:101CE000FFF748FE204605B0BDE8F0833E49284690
+:101CF0000FF04AFF18B9FFF73DFE0124F2E73B4918
+:101D000028460FF041FF18B9FFF734FE0224E9E737
+:101D10003748FEF7EDFA4FF0FF3100F0C6F8354BCB
+:101D200000241E4653F8047B002F42D00134402C7F
+:101D3000F8D10DF09FFD182303602D48FEF7D8FA67
+:101D400000F0B6F80EE0294602A8FFF72CFC02A826
+:101D5000FFF76DFC054640B90DF08CFD02230360D2
+:101D600046F824504FF0FF34BCE702A8FFF74DFCC3
+:101D7000074602A81FB1FFF751FC01902DE0FFF7C5
+:101D80003BFC05460028E7D0036802A8D3F808907A
+:101D9000FFF727FC28F48033024601A92846C847EC
+:101DA0000546D0B10DF066FD6D42056046F8247021
+:101DB000D8E74FF0FF330E4846F82430FEF798FA84
+:101DC00000F076F82B7801973A2BBCD10422691CDD
+:101DD00002A80FF07DF8029B0193019B46F8243086
+:101DE00003347FE7C4D80108CBD80108BCD8010868
+:101DF0003C1100203C10002070B50446FFF728FB82
+:101E00000646FFF720FBB4F57A7F05460CDBFFF7AB
+:101E10002AFD48B1FFF718F94FF47A7094FBF0F0FF
+:101E200001F0E4FFFFF72AF93046FFF70CFB431BF4
+:101E3000A342F9D370BD4FF47A735843FFF7DCBF68
+:101E4000F8B5044600F114070D461C220021261D9A
+:101E500038460FF043F91022002130460FF03EF9CA
+:101E60000B4BE760002D08BF1D461C2323610B238D
+:101E70006560A360304601F0D3F9206030B9BDE859
+:101E8000F840044904483122FFF778BCF8BD00BF90
+:101E9000D3D80108ECD8010806D9010810B50021F3
+:101EA0000446FFF7CDFF204610BD006801F0E4B9FD
+:101EB000006801F0FFB910B50446006801F016FA99
+:101EC000204610BD154838B5154B03600B251C2462
+:101ED000144B4560C460836001F0A2F9124B186096
+:101EE0001248134BC460C0E90035124B836001F007
+:101EF00097F9114B18601148114BC460C0E90035C7
+:101F0000104B836001F08CF90F4B18600EF028FC29
+:101F10000021BDE83840084600F062B8E4E1002046
+:101F20000AD90108ACE20020A8E2002010E200205B
+:101F30001AD9010868E20020E0E10020C8E2002090
+:101F400027D90108F4E10020D8D100200A4A0B4823
+:101F5000C2F1005303F58033B3F5806F194628BFF3
+:101F60004FF480615B1A01600549981808600549C3
+:101F70000B60054B1A60704704E6002078110020C2
+:101F80007C110020701100207411002070470000A7
+:101F90000D4A0E4808B50E4B13614FF48053536140
+:101FA0004823D3600B4B93601823936100210A4BA5
+:101FB000136001F075FE10B90848FFF7C5FCBDE8D5
+:101FC000084000F011BB00BF84E20020C51E0008DD
+:101FD000E0D1002020E2002031D901083DD90108DC
+:101FE00008B5FFF7D3FFBDE808400CF0B1BB000017
+:101FF00008B5FFF7ABFF0C4B0C4998684FF0005346
+:10200000C21802F16042126843F8042B8B42F7D1E8
+:10201000054B4FF000529A6005F07AFA00F09AFAF8
+:10202000BDE80840FFF7B4BF00ED00E088010020E4
+:10203000024B4FF0FF31186801F01EB9E0E10020BB
+:10204000014B186801F036B9E0E1002008B500F056
+:1020500091F8FCE708B505460C4601F03DFE6B1E05
+:102060000246042B24D8DFE803F0030D13191E00E9
+:10207000204601F019FE2246034601210F48FFF7D2
+:1020800063FCFEE70E4823460221FFF75DFCF8E7FC
+:102090000C4823460321FFF757FCF2E70A480421C6
+:1020A000FFF752FCEDE709480521FFF74DFCE8E793
+:1020B00007482946FFF748FCE3E700BF59D9010864
+:1020C000AAD9010800DA010865DA0108C0DA0108B6
+:1020D00020DB0108821D2ABF034B044A53F822204B
+:1020E00001460348FFF730BC68DC01085ADB0108F1
+:1020F00062DB01088A1D2ABF044B054B53F82230CE
+:102100000A4601460348FFF71FBC00BF68DC010810
+:102110005ADB010878DB01088A1D2ABF044B054BF6
+:1021200053F822300A4601460348FFF70DBC00BFB2
+:1021300068DC01085ADB010891DB01080A46014608
+:102140000148FFF701BC00BFA9DB010808B501F099
+:10215000C3FDBDE8084001F041BE08B5FFF790FBA4
+:10216000FEF772FFFEF7A2FFFEF788FFBDE808400A
+:10217000FFF7B2BB08B5024C23689847FCE700BFE5
+:1021800090010020EFF30980816911F8021CB9BBAE
+:1021900001B590E80F10E047BDE800508CE803005F
+:1021A000264B93E80600914208BF704741B91EF0E4
+:1021B000100F10D12249086820F0010008600AE0E1
+:1021C0002CE9F00F1EF0100F08BF2CED108AC1F89B
+:1021D00038C081F822E001F03DFB184B93E806007F
+:1021E0001A6092F82210906B61F0FF0E1EF0100F33
+:1021F00008BFB0EC108AB0E8F00F80F30988704790
+:1022000010B5104A1368994206D852F821400FC8F9
+:10221000A047EFF30984206010BD10B501F090F8DD
+:10222000BDE81040EFF3098CBAE710B501F024F9CE
+:10223000BDE81040EFF3098CB2E70000B4010020C4
+:1022400034EF00E02CDD010808B5014610B1132081
+:1022500001F092FC002008BD10B5044600F02EF8F5
+:10226000EFF305832BB9EFF3108313B9EFF3118369
+:102270003BB100206FF00501FFF73CFF6FF0050058
+:1022800010BDDFF808C0204600DFF9E7492200084A
+:102290007047704770477047704770477047704786
+:1022A0007047704770477047704770477047704776
+:1022B0007047704770477047704770477047704766
+:1022C0007047704770477047704770477047704756
+:1022D0007047704770477047704770477047704746
+:1022E0007047704770477047704770477047704736
+:1022F000704770477047704770B55F48017A012991
+:10230000054603D1FFF7CBFF002006E031B14FF0C7
+:10231000FF30FFF7DFFE4FF0FF3070BD574CA822B3
+:1023200008300EF0DBFE636D472B02D86FF00A0019
+:10233000EFE7E268002AEAD0238A002BE7D0D4E94D
+:102340000B61A5F85C303046A3686A66AB6400F0A8
+:1023500081F908B1C5F88860D4E90561304600F01C
+:1023600079F908B9D5F88860EE67D4E90761304695
+:1023700000F070F908B9D5F88860C5F88060D4E934
+:102380000961304600F066F908B9D5F88860C5F8EB
+:102390008460666B46B1D6E902233168304600F0AE
+:1023A000D2F908B1C5F88C60A66B46B1D6E9022314
+:1023B0003168304600F0C7F908B1C5F89060E66BA7
+:1023C00046B1D6E902233168304600F0BCF908B1C5
+:1023D000C5F89460266C46B1D6E9022331683046D0
+:1023E00000F0B1F908B1C5F89860666C46B1D6E95D
+:1023F00002233168304600F0A6F908B1C5F89C60A8
+:10240000A66C46B1D6E902233168304600F09BF94C
+:1024100008B1C5F8A060E66C46B1D6E90223316880
+:10242000304600F090F908B1C5F8A460246D44B1BD
+:10243000D4E902232168204600F085F908B1C5F8E7
+:10244000A8400F4AFF2382F8223092F82230D16848
+:1024500063F0FF03DB43B3FA83F3C3F12003C1F35B
+:1024600002218B4298BF4B1CFE2101FA03F3DBB221
+:10247000D37701232B7245E798010020C4DC0108C3
+:1024800000ED00E010B5034C207AFFF709FF207A39
+:1024900010BD00BF9801002038B5274C237A012BCE
+:1024A00006D06FF00600FFF715FE4FF0FF3038BD85
+:1024B000236B224D4BB9AA6D2148194601F05AFAF7
+:1024C000206310B94FF0FF30EDE76B6E4BB1236D19
+:1024D0003BB9EA6D1B48194601F04CFA206500280B
+:1024E000F0D0194801F0B7F80028EBD001F0D4F98A
+:1024F0002B68DB074CBF0223032383F31488134BA1
+:102500001B68E36000F092FF0028A0610CDB104A1A
+:102510001318FF2183F800134111012300F01F005D
+:1025200003FA00F042F8210000F09AFF0223237220
+:10253000FFF7B8FE0020BAE798010020C4DC0108CC
+:102540004D200008913D0008BC01002048020020F9
+:1025500000E100E008B5FFF7A1FEEFF305832BB91A
+:10256000EFF3108313B9EFF3118333B16FF005006C
+:10257000FFF7B0FD6FF0050008BDDFF828C0EFF3EE
+:10258000148313F0020F0AD113F0040FEFF3088342
+:102590000CBF203B683B23F0070383F3098800DF6F
+:1025A000EAE700BFF922000808B5EFF305832BB96D
+:1025B000EFF3108313B9EFF3118333B14FF0FF3012
+:1025C000FFF76EFE4FF0FF3008BDEFF31483DB071B
+:1025D00003D4BDE80840FFF755BFDFF808C000DFAF
+:1025E000F2E700BF8524000808B5FFF75AFEEFF3B5
+:1025F00005832BB9EFF3108313B9EFF3118333B1D4
+:102600006FF00500FFF766FD6FF0050008BDFFF7EE
+:10261000CBFF022805D00D4B1B6813B15B6803B1DB
+:102620009847DFF82CC0EFF3148313F0020F0AD1A0
+:1026300013F0040FEFF308830CBF203B683B23F03B
+:10264000070383F3098800DFE0E700BFD8E200203A
+:102650009924000838B50C46034630B140EA01021F
+:1026600012F0070201D1172906D818460022214688
+:10267000FFF70EFE002038BDA1F1080410254560CB
+:102680002518016085602250C2600122FFF700FE1C
+:102690000120F0E7F8B518B111B132F0030305D00D
+:1026A0000023FFF7F6FD00242046F8BD0F3121F08E
+:1026B000070100F108052B462D68D3F804C0EC1A79
+:1026C0002CF00306A41BA14206D92C68002CF2D1E1
+:1026D0002346FFF7DEFDE7E744680C44446042EA26
+:1026E0000107BCF1000F03D15F6003F10804EFE7BD
+:1026F0009C199D5167601C600834E9E738B500B14A
+:1027000021B90022FFF7C6FD002038BDA1F1080560
+:1027100000F108030022AB420CD15C6824F00305F1
+:102720004468641B44605AB95A600122FFF7B2FD45
+:102730000120EAE71C681A46002CE2D02346EAE7AB
+:102740001B681360F1E72DE9F0410C4617461E4661
+:10275000F8B1B9B1FAB103B34FF0000C02FB01F8C4
+:10276000C0E901C203EB080CC36043610160C0F81B
+:1027700010C0FFF790FD3346013C06D1A8EB0707D8
+:10278000F45101242046BDE8F081DA191A6013469D
+:10279000F2E70446F6E71446F4E71C46F2E738B5DC
+:1027A000044628B90146FFF777FD2546284638BD7F
+:1027B000034653F8042B53E8001F8A4202D8BFF3A4
+:1027C0002F8F04E0481C43E8000505B1F3E72368B8
+:1027D0008B4211D904F1140353E8005F15B9BFF31C
+:1027E0002F8F04E02A6843E8002101B1F4E729466D
+:1027F0002046FFF751FDD9E70025F8E738B528B1A5
+:10280000C3688B4202D803698B4207D86FF003027A
+:10281000FFF743FD6FF00304204638BD031D53E866
+:10282000002F12B9BFF32F8F04E0541E43E8004578
+:1028300005B1F4E79AB100F114031A680A60BFF316
+:102840005F8F53E8002F0C689442F6D143E80015DF
+:1028500005B1F2E700242246FFF71FFDDCE76FF029
+:102860000204F8E7036B30B5E3B1CD780024DA78E1
+:10287000AA420FD31A46C1E901248AB19160A4B1DA
+:102880006160283050E8003F5A1C40E8002101B147
+:10289000F8E730BD5A681C46002AECD01346E6E73C
+:1028A000C162ECE7C1E90133C1620163E9E7D1E943
+:1028B000013223B19A608A681AB153607047C262CC
+:1028C000F9E70363704700002DE9F74F074600B1B1
+:1028D00049B96FF003010020FFF730FC00252846BE
+:1028E00003B0BDE8F08F033121F0030303F10C08BE
+:1028F0000193B8FA88F1B0FA80F30B441F2BE8DD9E
+:1029000008FB00F9F2B194683CB1A30702D1D36887
+:10291000332B05D86FF00801DDE7D368002BF9D120
+:10292000D2E90453D2F800A03DB115F0030B01D158
+:1029300099455FD96FF00901CDE7002BFAD11CB1A1
+:102940009B4619E0924615462C4BD3F8A80048B197
+:10295000FFF725FF044660B96FF00401FFF7EEFBB7
+:102960002546BCE7D3F8880001223421FFF792FE08
+:10297000F0E74FF0010B0DBB204E0022D6F884008B
+:102980004946FFF787FE054690B96FF00401FFF74F
+:10299000D5FBBBF1000FA2D0D6F8A800214610B19C
+:1029A000FFF72CFF9BE7D6F88800FFF7A7FE96E716
+:1029B0004A4600210EF092FB4BF0020B019A84F87C
+:1029C00002B04FF4847323800023C4E90923C4E9CF
+:1029D0000B33A36042462B46C4F804A0394604F1E9
+:1029E0000C00FFF7B0FE054B054A9A672046FFF73B
+:1029F00077FCB5E7002CE1D1A6E700BF98010020E5
+:102A0000F52A00082DE9F0410E4690461D46044681
+:102A100018B10378082B00D141B920466FF00301AB
+:102A2000FFF78CFB6FF00300BDE8F081437833B90A
+:102A30006FF00201FFF782FB6FF00200F4E783689A
+:102A4000FBB15B78832B1CD1FFF74FFC204600F0D5
+:102A500002FE01220546002100F05CFF284600F03E
+:102A60007BFE0546626A806831460EF031FAEB68FB
+:102A70000BB183F80080A9682046FFF73BFC0020DB
+:102A8000D2E704F10C00FFF78AFE0746A0B1626AA4
+:102A900031460C300EF01CFA002540F2071339467F
+:102AA00020463B80BD7087F80380FFF7DBFE314690
+:102AB0002046FFF71AFCE2E7A5B12A463146204638
+:102AC000FFF710FC0A4B2046D96900F0B1FD2946FA
+:102AD000932001F051F8EFF309836FF00100C3E98F
+:102AE0000268A1E731462046FFF700FCA4E700BFDB
+:102AF00098010020F8B543780446002B76D08778FB
+:102B0000002F3CD0C5686B78002B6FD001460027A2
+:102B1000284605F10C06FFF7CAFE67703046FFF73E
+:102B20006DFEAB68002B61D05B78932B5ED1304695
+:102B3000FFF735FE0446002858D0284600F08BFDEC
+:102B40003A463946064600F0E5FE304600F004FEFF
+:102B50006A6A8168064604F10C000EF0B9F940F289
+:102B600007132380A770F368E37021462846FFF718
+:102B700079FEB1682846BDE8F840FFF7B6BB856826
+:102B80006B789BB3AB68416828463BB35B78832B7B
+:102B900024D1FFF7AAFB284600F05DFD3A46064621
+:102BA000394600F0B7FE304600F0D6FD06466A6AA8
+:102BB000806804F10C010EF08BF9F3680BB1E27838
+:102BC0001A70B1682846FFF795FB00236370214611
+:102BD00005F10C00BDE8F840FFF710BEFFF785FBDC
+:102BE00021462846BDE8F840FFF73CBEF8BD10B5C9
+:102BF00000F1280353E8002F12B9BFF32F8F04E030
+:102C0000511E43E8001404B1F4E70AB9002010BDD6
+:102C1000C06A01230028F9D0821CD2E84F1FC2E805
+:102C2000443F04B1F9E711F0FF0FF0D08068F1E7FD
+:102C30002DE9F0410D4617469846044618B1037831
+:102C4000082B00D141B920466FF00301FFF776FA57
+:102C50006FF00300BDE8F081437833B96FF00201F3
+:102C6000FFF76CFA6FF00200F4E7FFF7C0FF0646CB
+:102C7000E0B101462046FFF71AFE626A06F10C0138
+:102C800028460EF025F90FB1F3783B70294620460F
+:102C9000002504F10C07FFF72DFB7570314638460F
+:102CA000FFF7ACFDA368F3B90020D3E7B8F1000F3C
+:102CB00014D0424629462046FFF71AFB1F4B2046F8
+:102CC000D96900F0B5FC4146832000F055FFEFF3D1
+:102CD00009836FF00100C3E90257BBE7294620468C
+:102CE000FFF709FBBEE75B78932BDDD13846FFF792
+:102CF00056FD06460028D7D0204600F0ACFC012245
+:102D00000746294600F006FE384600F025FD626AB7
+:102D10008168074606F10C000EF0DAF840F207135E
+:102D20003380B570FB68F37031462046FFF79AFD9B
+:102D30002046B968FFF7D9FA28468BE798010020AA
+:102D400070B506460D461446FFF7C9FAEFF3058342
+:102D50002BB9EFF3108313B9EFF3118333B10020D4
+:102D60006FF00501FFF7EAF9002070BDDFF82CC015
+:102D7000304629462246EFF3148313F0020F0AD19E
+:102D800013F0040FEFF308830CBF203B683B23F0E4
+:102D9000070383F3098800DFE7E700BFC9280008BD
+:102DA0002DE9F04105460F4690461C46FFF799FA7B
+:102DB000EFF305832BB9EFF3108313B9EFF311830E
+:102DC000CBB325B12B78082B01D107B144B12846EC
+:102DD0006FF00301FFF7B2F96FF00300BDE8F08177
+:102DE0006B783BB96FF002012846FFF7A7F96FF047
+:102DF0000200F3E705F10C00FFF7D1FC0646A8B18D
+:102E00006A6A39460C300EF063F840F207133380DB
+:102E10003046C6E90175B47086F8038000F0D4FA34
+:102E200028463946FFF760FA2046D7E73946284654
+:102E3000FFF75CFADBE7DFF810C028463946424668
+:102E4000234600DFCAE700BF052A0008F8B504469C
+:102E50000D4617461E46FFF74AFAEFF305832BB9D6
+:102E6000EFF3108313B9EFF31183A3B324B12378E5
+:102E7000082B01D105B13EB120466FF00301FFF7E9
+:102E80005DF96FF00300F8BD63783BB96FF00201A4
+:102E90002046FFF753F96FF00200F4E72046FFF7F2
+:102EA000A6FE064690B100F10C01626A28460EF0BB
+:102EB0000FF80FB1F3783B7029462046FFF71AFA56
+:102EC0003046F46000F080FA0020DCE72946204616
+:102ED000FFF711FADFE7DFF810C0204629463A462F
+:102EE000334600DFCFE700BF312C000870B5002863
+:102EF00039D08468D0E900566CB114F0030302D1D4
+:102F0000C2681B2A1FD86FF008010020FFF704F9E0
+:102F10000024204670BDC368002BF4D1134BD3F8B6
+:102F20009C0030B9D3F8880001221C21FFF7B2FBC6
+:102F300001E0FFF734FC044620B96FF00401FFF70D
+:102F4000EBF8E6E701234FF48272A3700023C4E993
+:102F50000233C4E904332280E6706560237620469C
+:102F6000FFF7B1F9D5E705460646D7E798010020F7
+:102F7000304B70B5DD6904460E4635B96FF0070178
+:102F8000FFF7CAF84FF0FF3070BD10B10378042B83
+:102F900007D020466FF00301FFF7BEF86FF0030083
+:102FA000F2E7437833B96FF00201FFF7B5F86FF03D
+:102FB0000200E9E7017E69B9EA6AC560C0E9041266
+:102FC00002B110610121EC6220462176FFF77FF902
+:102FD0000020D9E7C278D3070BD5C368AB4208D12C
+:102FE000FF2902D16FF00F01DFE70131C9B201768D
+:102FF000ECE7DEB193070AD5E06895F9203090F947
+:1030000020209A4203DA80F8203000F03EFB31465F
+:103010002046FFF75AF92946204600F009FB3146C1
+:10302000532000F0A9FD6FF00100ADE72046FFF747
+:103030004FF9BCE79801002038B5334BDD690446F1
+:1030400035B96FF00701FFF767F84FF0FF3038BD73
+:1030500010B10378042B07D020466FF00301FFF76F
+:103060005BF86FF00300F2E7437833B96FF00201C9
+:10307000FFF752F86FF00200E9E7C368AB4202D0F5
+:103080006FF00D01F4E7017E11B96FF00E01EFE76B
+:103090000139C9B20176FFF71DF9237E3BBB636995
+:1030A0000BB122691A6122691AB35361E3789B0755
+:1030B00005D595F92120EB6AEBB985F82020A368A6
+:1030C00093B1204600F0C7FA00220546114600F0F1
+:1030D00021FCEB6A636101210023E5602361204646
+:1030E000EC622176FFF7F3F8002000F0E5FB00200A
+:1030F000ADE7EB62DAE7996821B191F920108A42D5
+:10310000B8BF0A465B69D7E79801002010B50446AE
+:1031100010B10378042B07D020466FF00301FEF7AF
+:10312000FBFF6FF0030010BD437833B96FF002016D
+:10313000FEF7F2FF6FF00200F5E700234370037E15
+:10314000DBB16369C0680BB122691A6122691AB3E5
+:103150005361E3789A070BD590F92130C26AEAB936
+:1031600090F920209A4203D080F8203000F08DFAA8
+:10317000A368E3B9002000F09FFBA378DB0706D526
+:10318000124BD3F89C002146D0B1FFF737FB204605
+:10319000FFF7A2F80020C6E7C362DAE7916821B121
+:1031A00091F920108B42B8BF0B465269D7E72046F1
+:1031B00000F051FA00226FF0020100F0ABFBD7E7FC
+:1031C000D3F88800FFF79AFAE1E700BF98010020E2
+:1031D0002DE9F0410446002601270CB9BDE8F08135
+:1031E000E378D4F814801B0718D5267600212046F2
+:1031F000FFF770F8A3688BB1204600F02CFA00228C
+:103200000546114600F086FBEB6AE560C4E90463FD
+:103210000121EC6220462776FFF759F84446DCE7A7
+:1032200010B50446FFF74EF8EFF305832BB9EFF323
+:10323000108313B9EFF3118333B100206FF0050150
+:10324000FEF76AFF002010BDDFF828C02046EFF32C
+:10325000148313F0020F0AD113F0040FEFF3088365
+:103260000CBF203B683B23F0070383F3098800DF92
+:10327000E9E700BFED2E000838B504460D46FFF71C
+:1032800023F8EFF305832BB9EFF3108313B9EFF3B2
+:1032900011833BB120466FF00501FEF73DFF6FF053
+:1032A000050038BDDFF808C02046294600DFF8E7F2
+:1032B000712F000810B50446FFF70BF8EFF30583F4
+:1032C0002BB9EFF3108313B9EFF311833BB1204611
+:1032D0006FF00501FEF720FF6FF0050010BDDFF86D
+:1032E00008C0204600DFF9E73930000810B5044671
+:1032F000FEF7F1FFEFF305832BB9EFF3108313B95A
+:10330000EFF311833BB120466FF00501FEF704FF98
+:103310006FF0050010BDDFF808C0204600DFF9E7B8
+:103320000D31000810B5D0E85F3F5A1C914200D81B
+:103330000022C0E8542F04B1F5E798B210BD000098
+:1033400070B5204C04F15E0504F16206B4F85C101F
+:10335000D5E85F3F13B9BFF32F8F04E05A1EC5E8CD
+:10336000502F00B1F4E79BB23BB33046FFF7DAFFD2
+:10337000636E53F8200000B30378013B062BE5D8B9
+:1033800001A252F823F000BFA53300084D33000816
+:10339000AB3300084D330008AF330008B3330008E7
+:1033A000B7330008A36E9847D0E7E36EFBE7236FBF
+:1033B000F9E7636FF7E7A36FF5E7BDE8704000201A
+:1033C00000F07ABA9801002070B5164C0546B4F8A2
+:1033D0005C1004F15E02D2E85F3F994202D8BFF36D
+:1033E0002F8F04E0581CC2E8560F06B1F3E79BB2DA
+:1033F000994205D829460220BDE87040FEF72ABE52
+:1034000004F16000FFF78EFF636E43F82050637A8B
+:1034100023B9054B4FF080525A6070BD0123E3720F
+:10342000FBE700BF9801002000ED00E0084B094ACF
+:10343000DB685268B3FBF2F3074A013B5360002399
+:103440009360064BFF2283F823204FF0FF30704734
+:1034500098010020C4DC010810E000E000ED00E06D
+:10346000014B07221A60704710E000E0014B1B6817
+:10347000704700BF10E000E038B51C4CFFF7F6FFC6
+:10348000D4E90432013342F10002C4E90432A36DED
+:1034900003B1984700F06AF9002000F00DFAA36C20
+:1034A0001BB3226C216A8A4202D0216463641CE04F
+:1034B000636CB3B9237A022B17D1E56AADB195F9E4
+:1034C000201092F9203099420FD1284600F0D4F80C
+:1034D000206C00F0EDF8284600F0DEF9A36C2564BE
+:1034E000E4E7013B6364002BE4D038BD9801002081
+:1034F00007B5044BD8690190FEF7D8FE019803B0D8
+:103500005DF804FB9801002008B5FEF71FFEDFF808
+:1035100010C000DF4FF0FF310020FEF7EBFDFEE7AB
+:10352000C53B0008930710B502F0010422D400F156
+:10353000280384B153E8000F00EA01028A4203D055
+:10354000BFF32F8F002005E020EA010243E80024AA
+:1035500004B1EFE710BD53E8000F084203D1BFF3F9
+:103560002F8F002005E020EA010243E8002404B187
+:10357000F1E7EFE7806A01EA00031CB1994218BF46
+:103580000020E7E7002B08BF0020E3E710B5002389
+:10359000437083789A07044608D513F0100F016B27
+:1035A0000E4B0FD0D3F88C00FFF728F9A378DB0778
+:1035B00012D50A4BD3F89000214638B1BDE810402F
+:1035C000FFF71CB9D86FFFF799F8EFE7BDE8104097
+:1035D000D3F88800FFF792B810BD00BF9801002013
+:1035E00010B5044610B10378012B05D02046002108
+:1035F000FEF75BFE002010BD4378002BF6D041683B
+:10360000FEF753FE6068F6E710B5084A936B002199
+:103610003BB94FF0FF34C0E90431C46121B1086106
+:1036200010BD19461B69F3E79063F9E79801002084
+:1036300010B561B191F9202083681BB193F9204046
+:10364000944205DAC1E90230816003B1D96010BD4E
+:1036500018469B68F1E783682BB19A68826002B1D3
+:10366000D0600022DA601846704710B10378012B51
+:1036700000D07047C068F8E7C2682AB183689360D9
+:1036800003B1DA600023C360704710B501460446F9
+:103690002378012B07D00846FFF7EEFF2046BDE850
+:1036A0001040FFF7C5BFE468002CF1D110BD000049
+:1036B0000123014643700148FFF7BABFBC01002057
+:1036C0004B1C30B4024602D130BCFFF79DBF0C4802
+:1036D000436B002413B1DD698D420BD9C2E9043478
+:1036E000D1615CB122611BB1D8695A61411AD961BB
+:1036F00030BC70471C46491B1B69EBE74263F2E78D
+:103700009801002010B5C4694269631C10D11AB930
+:10371000104B9B6B98420AD1036903B15A6142690D
+:103720001AB113610023436101E00A4A936310BD9B
+:103730001AB9084B5B6B8342F9D103691BB1D96994
+:103740005A612144D9614269002AEAD1014A53638E
+:10375000EDE700BF9801002090F82220836BD2068D
+:1037600054BF03F1600003F12000704738B52C4DC1
+:103770006C6B14B3E369013BE361F3B96378632BCA
+:103780003CD023D8432B33D018D8132B2AD0332B3B
+:103790002BD02046FFF7E0FF01682046FEF789FDA9
+:1037A0002046FFF769FFFFF783FF246924B1E3692F
+:1037B000002BE3D0002363616C6338BD532BE8D149
+:1037C0002046FFF752FFFEF781FDE2E7832B1BD077
+:1037D000932B1FD0732BDCD12046FFF746FFFEF75B
+:1037E0007DFDD6E7FEF76BFDD3E7FEF765FDD0E77D
+:1037F0002046FFF73AFFFEF764FDCAE72046FFF7D1
+:1038000034FFFEF76AFDC4E72046FFF72EFFFEF700
+:1038100070FDBEE72046FFF728FFFEF764FDB8E71E
+:103820009801002010B50A4A90F920100123437036
+:10383000D36A24321BB193F920408C4205DCC0E9E5
+:103840000232906003B1D86010BD1A469B68F1E760
+:1038500098010020044B1B682BB11B691BB1034A64
+:10386000126A506C18477047D8E200209801002077
+:10387000074BD96951B10B6B8A6B934203D21A681B
+:10388000044B9A4202D00120FEF7E4BB704700BF10
+:1038900098010020A52E5AE210B502234370054B73
+:1038A00004461862FFF7E4FF2046BDE81040FEF72B
+:1038B00001BD00BF9801002010B5154B04461A7ACF
+:1038C000D969A8B9022ADC6A20D1F9B1F4B194F916
+:1038D000202091F920309A4218DD2046FFF7CCFED7
+:1038E0000846FFF79FFF2046BDE81040FFF7D4BF12
+:1038F000022A06D129B190F9202091F920309A426C
+:10390000EEDC2046BDE81040FFF7D2BE10BD00BF80
+:103910009801002070B504460E461546FEF7C9FC16
+:103920002046FFF719FF06602046FFF7EBFE1DB1AA
+:10393000BDE87040FFF7C0BFBDE87040FFF7B8BEFC
+:1039400038B54378332B044613D190F82320416ACD
+:10395000FFF7E8FD054660B1014600222046FFF76B
+:10396000D9FF94F82310606A2A46BDE83840FEF774
+:10397000A4BC38BD2DE9F04F85B0CDE902318046B9
+:1039800040B96FF00301FEF7B5FB0026304605B0E5
+:10399000BDE8F08F002A36D0946844B1A50702D163
+:1039A000D368472B06D86FF008010020EBE7D368F7
+:1039B000002BF8D1D2E9046597693EB1700702D1B6
+:1039C000002D40F0C2806FF00A01EEE72FB17B1EA0
+:1039D000372B03D96FF00B01E7E71827002D40F0D4
+:1039E000B880D2E900930193D4B95D4BD3F890002D
+:1039F00078B1FEF7D4FE044698BB6FF00401FEF7E1
+:103A000079FB2646C2E791461646182715460192CD
+:103A1000EBE7D3F8880001224821FEF73BFEEAE7F6
+:103A20004FF0000B2EBBDFF838A1002D76D14D4AA8
+:103A3000DAF88C00556D002870D0FEF7B0FE98B90A
+:103A40006FF004010020FEF755FBBBF1000F9DD085
+:103A5000DAF890502146002D69D02846FEF7CEFEB8
+:103A600094E74FF0010BDDE74BF0100B4BF0020B2E
+:103A70000646019BE3700023C4E90233C4E9043322
+:103A8000C4E90633C4E90933C4E90B36A5F14003A0
+:103A900040F201123344C4E90E382280324B84F8DC
+:103AA00002B07FB2FD226284C4F8049084F82070D2
+:103AB00084F82170656333602A4B1B685B073246CC
+:103AC0003ED5AD08A5F111034FF0CC31002B33D119
+:103AD000103D06EB850606F134023346002143F81B
+:103AE000041B9A42FBD1214B214AC6E90D384FF005
+:103AF0008073F363039B3362194B20469A66FEF78B
+:103B0000D3FB1C4B1B68EBB19B68DBB102992046D1
+:103B1000984760642046FFF7CFFE72E7DAF87C0032
+:103B200032462946FEF7B6FD00289FD188E7DAF82D
+:103B30008800FEF7E3FD28E742F8041F013BC5E7D4
+:103B4000A66BC8E7029B6364E4E7002F7FF43FAFF6
+:103B5000182769077FF437AF472D3FF642AF32E7AA
+:103B600098010020C4DC0108A52E5AE2093500089E
+:103B700041390008D8E20020F8B5114DEC6907463C
+:103B80000E46D4B12B7A022B04D02046FFF774FDE9
+:103B90000020F8BDE86A0028FBD02046FEF788FB2D
+:103BA000314620466770FFF78BFD05F12400FFF7D3
+:103BB00052FDFFF771FE0120EBE72046E9E700BF69
+:103BC0009801002038B51B4DEC69002C30D0E06A1C
+:103BD000FFF7FEFAA06930B100221146FFF79AFE06
+:103BE000A069FEF764FB2B7A022B21D1EB6AFBB1B3
+:103BF000EFF309831048A363FFF72DFDFFF74CFE99
+:103C00000023EB61E378DB0701D5A3693BB12046D4
+:103C1000FFF7BCFC2046BDE83840FEF74CBB042251
+:103C20006270E360EB6BA36003B1DC60EC63F1E70F
+:103C300038BD00BF98010020BC01002073B50646C6
+:103C40000D4614460193FEF72EFBEFF3058232B9C1
+:103C5000EFF310821AB9EFF31182019B3AB1002001
+:103C60006FF00501FEF746FA002002B070BDDFF8E4
+:103C70002CC0304629462246EFF3148414F0020F7C
+:103C80000AD114F0040FEFF308840CBF203C683C09
+:103C900024F0070484F3098800DFE6E7753900089B
+:103CA0000023FFF7CBBF000008B50346EFF3058202
+:103CB0002AB9EFF3108212B9EFF311822AB1184634
+:103CC0000021FEF7F2FA002008BDDFF808C000DF8F
+:103CD000FAE700BFE135000808B5EFF305832BB91B
+:103CE000EFF3108313B9EFF3118323B10020FEF734
+:103CF000DDFA002008BDDFF808C000DFFAE700BFEA
+:103D0000F13400080C4AD36C30B5002413B11D699E
+:103D10008D420AD9C0E9024301611BB11D69986057
+:103D2000691A19612CB1E06030BD1C46491BDB6883
+:103D3000ECE7D064F8E700BF9801002070B5134DA0
+:103D4000EC6C04B32369013B236101262369D3B9D9
+:103D5000E3680BB1A2689A60EB640023686D1A46B1
+:103D600004F11801FFF71CF818B121460320FEF7F3
+:103D700071F9E378012B07D161692046FFF7C2FF93
+:103D8000EC6C002CE2D170BD6670F9E79801002060
+:103D90000F4B13B51A6E586E0E4C0821FEF7D0FF6C
+:103DA000606590B10C4BA365606D4FF0FF3300224E
+:103DB0006946FFF74BF80028F6D1DDE90001FEF770
+:103DC0007FFADDE900309847EEE702B010BD00BF92
+:103DD000C4DC0108980100203D3D0008024B1B682F
+:103DE00003B11847704700BFD8170020FEF734BA58
+:103DF0000F49D1F8883043F47003C1F888300D4B77
+:103E00001A68002042F001021A6098601A6822F0D5
+:103E1000A85222F410221A604FF48052DA601A6815
+:103E200022F480221A6098614FF000638B60704723
+:103E300000ED00E00010024070B5ACB0142200218B
+:103E400001A80DF04BF94022002107A80DF046F91A
+:103E50005422002117A80DF041F90423069306A867
+:103E60000123089301F0D0F820B9204A136843F0E9
+:103E70000403136001F02CFE1323B02206930E926C
+:103E800001230222CDE910230C9306262823CDE935
+:103E9000126300240723042606A8CDE914360794EC
+:103EA00009940D94169601F0AFF80546D8B901F0C3
+:103EB0001DFE4FF40053179317A84FF0406327934C
+:103EC00001F0C4FC0F210323CDE901130DEB060023
+:103ED0003146CDE90355059501F0FEFAB0FA80F0C0
+:103EE00040092CB070BD2046FBE700BF0010024027
+:103EF00008B5FFF7A1FF00B9FEE708BDDFF824D041
+:103F0000002103E0084B5B58435004310748084B3D
+:103F100042189A42F6D3FFF76BFFFCF77FF9704720
+:103F2000FEE700000000012058240208880100205C
+:103F3000900E0020FEE730B5054687B0182200211C
+:103F400068460DF0CBF895F86A30122B4BD8DFE8B5
+:103F500003F00A26282A2C2E30323436383A3C3EDA
+:103F60004042444648000023012269460093002451
+:103F700004232846CDE90123CDE90344059400F04C
+:103F800013FA284600F04EFC0A21284600F0B8F942
+:103F900058BB284600F005FA80B207B030BD0123B7
+:103FA000E2E70223E0E70323DEE70423DCE705235F
+:103FB000DAE70623D8E70723D6E70823D4E709235F
+:103FC000D2E70A23D0E70B23CEE70C23CCE70D235F
+:103FD000CAE70E23C8E70F23C6E71023C4E711235F
+:103FE000C2E71223C0E70020D7E72046D5E700004C
+:103FF000A1F1F0039BB20F2B73B504460D465BD9BC
+:1040000034492846FCF7F4FF324920602846FDF782
+:104010000BF8304906462846FCF7AEFF236801330B
+:1040200004D12D492D483E22FDF7A8FB731C04D175
+:1040300029492B483F22FDF7A1FB2A4AA4F86850E2
+:104040001368C6F3043684F86A60002B3FD101215F
+:104050001160254AD06C40F40050D064D06C00F45C
+:10406000005001900198D2F8880040F04050C2F80A
+:1040700088004FF48022C4E901230422C4E9052307
+:104080004FF48052C4E90333C4E90731C4E909316C
+:10409000C4E90B13C4E90E23A3656363204600F053
+:1040A0004DF810B11148FDF74FFC0021204602B039
+:1040B000BDE8704000F02BBC0D492846FCF798FF86
+:1040C0000B4920602846FCF7AFFF0646A6E702B082
+:1040D00070BD00BF90DD010894DF0108D0DF01084A
+:1040E000FADF0108DC1700200010024013E001088D
+:1040F000FCDD010808B5FFF71EFFC0F3032343EA08
+:10410000001080B208BD08B5032000F03FFC0F206E
+:1041100003F08AF900F04EFE002008BD024A136841
+:1041200001331360704700BFDCE20020014B1868C8
+:10413000704700BFDCE2002070470000F7B50023A5
+:1041400001930446002800F0D080856D25B9FFF763
+:10415000F3FFE56584F8545023689A68920042BFE3
+:104160009A6822F000529A609A68D70040F19880CD
+:104170009A68D60040F1A7800020A26DD50600F114
+:10418000B0809A68510700F1AC80A26D42F0020243
+:10419000A2659A6802F00302012A02D11A68D207C6
+:1041A00006D4534965688A6822F47C122A438A60DF
+:1041B0004FF4005595FAA5F54FF48032666AB5FACA
+:1041C00085F592FAA2F2E768A16B3943A7683943F3
+:1041D000E769B2FA82F207FA05F5294306FA02F214
+:1041E000012E42EA010209D14FF4602191FAA1F1B6
+:1041F000B1FA81F5A16A0139A9400A43E16A0129AE
+:1042000003D0256B0DB129430A43DD6839492940A4
+:104210000A43DA609A6812F00C0F2AD14FF48042F8
+:1042200092FAA2F20225B2FA82F695FAA5F5A269EF
+:10423000D968B240666BB5FA85F506FA05F521F442
+:1042400080412A4321F002010A43DA60E26B012A2D
+:1042500043D1D4E91025196921F4FF6121F005014A
+:104260002A430A43A16C0A43E16C0A4342F001026B
+:104270001A612269012A05BF196B226A1A6B02F1C1
+:10428000FF3206BF21F00F010A4322F00F021A632A
+:10429000A36D23F0030343F00103A36503B0F0BD56
+:1042A0009A68154942F080529A60144A1268B2FB2B
+:1042B000F1F10A224A430192019A002A3FF458AFD1
+:1042C000019A013AF7E7A26D42F01002A265E26D91
+:1042D00042F00102E26501204FE71A6922F0010273
+:1042E000C6E7A36D43F01003A3650120D6E700BF26
+:1042F0000003045007C0F0FF80841E004802002025
+:10430000F8B54569082D04460E460AD00368DB68F7
+:10431000D90705D5836D43F0200383650120F8BDDF
+:104320000425FFF703FF074623681A6815420DD0DE
+:104330001968DA68082D01F0080119D11D60A06D17
+:1043400040F40070A065C1B90020E8E7721CECD011
+:1043500046B9A36D43F00403A365002384F85430E9
+:104360000320DCE7FFF7E2FEC01BB042DCD9F0E738
+:1043700050045CBF04201860E1E7DB6802F40052DF
+:1043800003F440631343DFD1A36D23F48073A3656B
+:10439000A06D10F48050D7D1A36D43F00103A36545
+:1043A000BDE70368186C70472DE9F34100230193C2
+:1043B00090F85430CD68012B00F0F681036801229B
+:1043C00080F854209C68670700F1E981D1E9002456
+:1043D000042C4FF4F8664AD81F6B96FAA6FCBCFA78
+:1043E0008CFC96FAA6F64FF01F0E04FB0CFCB6FAF6
+:1043F00086F60EFA0CFC744327EA0C0702FA04F462
+:104400003C431C639C6814F00C0F40F0A480092A04
+:10441000D1F808C04FF0380476D9D3F818E094FAF0
+:10442000A4F8B8FA88F8A2F10A0794FAA4F4B4FA46
+:1044300084F607FB08F44FF0070808FA04F47E43FB
+:104440002EEA04040CFA06F626439E61DE680F6924
+:10445000C6F3C10674004E69013FA6404FF0F84410
+:10446000032F00F2B580DFE807F0668091A2092CE7
+:1044700018D8D3F834C096FAA6FEBEFA8EFE671F8F
+:1044800096FAA6F6B6FA86F407FB0EFE1F2606FA83
+:104490000EFE7C432CEA0E0C02FA04F44CEA0404EF
+:1044A0005C63AFE70E2C17D89F6B96FAA6FCBCFA9C
+:1044B0008CFC0A3C96FAA6F64FF01F0E04FB0CFC8F
+:1044C000B6FA86F60EFA0CFC744327EA0C0702FAD9
+:1044D00004F43C439C6395E7DF6B96FAA6FCBCFAB8
+:1044E0008CFC0F3C96FAA6F64FF01F0E04FB0CFC5A
+:1044F000B6FA86F60EFA0CFC744327EA0C0702FAA9
+:1045000004F43C43DC637DE75E6994FAA4F7B7FAF0
+:1045100087F794FAA4F44FF0070EB4FA84F45743E3
+:104520000EFA07FE544326EA0E0E0CFA04F64EEA83
+:1045300006065E618AE7D3F860C094FAA4F49B4F44
+:10454000B4FA84F40CEA070702FA04F43C43264365
+:1045500046F000461E669C6804F00304012C7AD1E4
+:104560001C68E60777D50022F8E0D3F864C094FA17
+:10457000A4F48E4FB4FA84F40CEA070702FA04F4A8
+:104580003C43264346F000465E66E4E7D3F868C045
+:1045900094FAA4F4854FB4FA84F40CEA070702FAFB
+:1045A00004F43C43264346F000469E66D3E7D3F826
+:1045B0006CC094FAA4F47D4FB4FA84F40CEA0707B3
+:1045C00002FA04F43C43264346F00046DE66C2E7A6
+:1045D0001E6E94FAA4F4B4FA84F402FA04F406F019
+:1045E000F846A64202BF1C6E24F000441C665E6EB4
+:1045F0004FF0F84494FAA4F4B4FA84F402FA04F400
+:1046000006F0F846A64202BF5C6E24F000445C66E9
+:104610009E6E4FF0F84494FAA4F4B4FA84F402FACB
+:1046200004F406F0F846A64202BF9C6E24F0004453
+:104630009C66DE6E4FF0F84494FAA4F4B4FA84F465
+:1046400002FA04F406F0F846A64202BFDC6E24F03B
+:104650000044DC667FE70124B5F1804F04FA02F4E0
+:1046600030D0D3F8B01021EA0404C3F8B040112AC6
+:1046700068D14F49896811F4000F7FF474AF9968CD
+:1046800001F00301012902D11C68E40761D4112A59
+:104690006BD1484A93427FF466AFD2F8083343F4B3
+:1046A0000003C2F80833444B444A1B68B3FBF2F2E0
+:1046B000782353430193019B002B3FF454AF019B9C
+:1046C000013BF7E7D3F8B0508E682C43082AC3F8B3
+:1046D000B0404FF0380117D99D6991FAA1F7B7FAA8
+:1046E00087F7A2F1090491FAA1F14FF0070CB1FA92
+:1046F00081F167430CFA07F7614325EA070506FADB
+:1047000001F129439961B2E75F6991FAA1F4B4FA22
+:1047100084F4551C91FAA1F14FF0070CB1FA81F124
+:104720006C430CFA04F4694327EA040706FA01F122
+:1047300039435961002A7FF416AF1D49896811F485
+:10474000800F9AE7122AF5D11949896811F0807F04
+:1047500093E7836D43F0200383650A46002380F8C6
+:104760005430104602B0BDE8F081122A09D1114A36
+:10477000934202BFD2F8083343F08073C2F8083383
+:10478000F1E6002A7FF4EFAE0A498B427FF4EBAEEC
+:10479000D1F8083343F48003C1F80833DEE7836DB2
+:1047A00043F020038365D9E70222DAE700F0FF0334
+:1047B00000030450000004504802002080841E00C2
+:1047C00038B503689A6802F00302012A044604D14E
+:1047D0001A68D10701D5002038BD9968104A1142E6
+:1047E00009D0A36D43F01003A365E36D43F001030B
+:1047F000E3650120F0E79A6842F001029A60FFF752
+:1048000095FC054623681A68D207E4D49A6842F0FA
+:1048100001029A60FFF78AFC401B0228F2D9E0E708
+:104820003F00008038B503689D6815F00405044614
+:1048300034D190F85430012B30D0012380F854301B
+:10484000FFF7BEFF38BBA36DDA0449BFE36DE06537
+:1048500023F00603E365A36D226823F4706323F05D
+:10486000010343F48073A365A36D23F48013A36550
+:104870001C231360D3689B0141BFA36D23F44053F5
+:1048800043F48053A365002384F85430936843F0C5
+:104890000403936038BD84F85450FBE70220F9E725
+:1048A00038B503680446986800F00300012801D079
+:1048B000002038BD1A68D207FAD59A6802F00D02B6
+:1048C000012A1BD19A6842F002029A6003221A6000
+:1048D000FFF72CFC054623689B68DB07E8D5FFF74C
+:1048E00025FC401B0228F6D9A36D43F01003A365F5
+:1048F000E36D43F00103E3650120DAE7A36D43F0C4
+:104900001003A365E36D43F00103E365D1E738B518
+:1049100090F85430012B04460D4635D0012380F821
+:104920005430FFF7BDFFA36D58BB23F4885323F029
+:10493000020343F00203A36523689A6822F08042D1
+:104940002A439A609A6842F000429A604FF47A4291
+:104950009968002909DBA36D23F0030343F00103E9
+:10496000A365002384F854300AE0013AF0D1A36D26
+:1049700084F8542023F0120343F01003A3650120B0
+:1049800038BD43F01003EBE70220F9E70749CA6896
+:1049900022F4E0620302120403F4E063120C1343F6
+:1049A00043F0BF6343F40033CB60704700ED00E099
+:1049B000384B1A69900741BF37494A6842F00102F3
+:1049C0004A601B69190741BF334A536843F0020329
+:1049D0005360304B1A69D20641BF2F494A6842F0F2
+:1049E00004024A601B699B0641BF2B4A536843F08F
+:1049F00008035360274B1A69500641BF26494A688D
+:104A000042F010024A601B69190641BF224A5368EE
+:104A100043F0200353601F4B1A69D20541BF1E4962
+:104A20004A6842F040024A601B699B0541BF1A4A2E
+:104A3000536843F080035360164B1A69500441BF1A
+:104A400015494A6842F480724A601B69190441BFE3
+:104A5000114A536843F4007353600E4B9A69002A5D
+:104A6000BFBF0D494A6842F480624A601A699203E6
+:104A700007D509494A6842F400624A604FF400329F
+:104A80001A61044B9A6942F000429A614CF2FA3280
+:104A90001A61704700200240E0E20020074A536993
+:104AA00043F48023536172B60023CA58C2500433C2
+:104AB000B3F5807FF9D162B6704700BF0020024095
+:104AC000064B5A69002ABFBF054A9A6002F1883234
+:104AD0000020B4BF9A600120704700BF0020024050
+:104AE00023016745034A536943F0004353610020A3
+:104AF000704700BF0020024070B50546FFF716FB67
+:104B00001F4C46192369DB0329D42369980722D453
+:104B1000236919071FD42369DA061CD423699B066D
+:104B200019D423695E0616D423691D0613D423699C
+:104B3000D80510D4236999050DD423695A040AD4E1
+:104B40000F4A13691B0406D49369002B03DB116918
+:104B500011F400310BD0FFF72BFF012070BD6A1C50
+:104B6000D0D0FFF7E3FAB042CCD30320F6E71069C8
+:104B700010F00100F2D0012313610846EEE700BFF8
+:104B8000002002402DE9F843244C99462378012B5C
+:104B900006460F4690463FD001234CF2503023701A
+:104BA000FFF7AAFF054620BB1D4D60602A6812F47E
+:104BB000806217BF2B68227723F480632B601CBFB1
+:104BC00002232377D6B96B6943F001036B61012699
+:104BD000C7F80080C7F804904CF25030FFF78CFF04
+:104BE000054626B10E4A536923EA0606566100F0CF
+:104BF00041F8002323702846BDE8F883731E012B7B
+:104C000001D90026E8E741463846FFF747FF022E64
+:104C1000F7D14FF48026DFE70225ECE7E0E2002041
+:104C200000200240064B10F0010F1EBF5A6942F0EF
+:104C300004025A615A6942F480325A61704700BFD7
+:104C4000002002400A4B4FF4FF615A6991FAA1F12A
+:104C5000B1FA81F122F4FF628840104358615A6929
+:104C600042F002025A615A6942F480325A61704736
+:104C700000200240144B1A7F012A02D01A7F032A17
+:104C80000CD1124A116841F400611160116821F4DD
+:104C900000611160116841F4007111601A7F022AED
+:104CA00002D01A7F032A0CD1084A116841F48051BE
+:104CB0001160116821F480511160116841F4806124
+:104CC000116000221A777047E0E2002000200240C5
+:104CD0002DE9F047344D2B78012B0646884660D0ED
+:104CE00001274CF250302F70FFF706FF044630BB0F
+:104CF0002E4B68601A6812F4007F1A6824D022F4E0
+:104D000000721A601A68510506D51A6822F480628A
+:104D10001A6003232B7700E02F773368012B1DD116
+:104D20007068FFF77FFF4CF25030FFF7E5FE1F4A37
+:104D3000536923F0040304465361FFF79BFF0023EC
+:104D40002B702046BDE8F087520505D51A6822F47D
+:104D500080621A600223DDE72877DEE74FF0FF3339
+:104D6000C8F80030B768DFF84490DFF844A0D6E90F
+:104D700002321344BB42E0D971683846FFF762FF44
+:104D80004CF25030FFF7B8FED9F8143003EA0A03AA
+:104D9000C9F8143018B1C8F800700446CDE70137DF
+:104DA000E5E70224CDE700BFE0E20020002002405A
+:104DB00005F8FFFF704700000D4B10B55B690C460E
+:104DC00060B99A0501D500F027F80A4A1369012C49
+:104DD00023F00403136106D130BF10BD9B05F4D44A
+:104DE00000F012F8F1E740BF20BF20BFF5E700BF99
+:104DF0000070004000ED00E0024B186800F4C06055
+:104E0000704700BF00700040024A136843F48043BB
+:104E100013607047007000400C4B0D491A6822F473
+:104E200080421A600B4A1268B2FBF1F132224A4307
+:104E300012B15969890506D45B6913F4007F14BF68
+:104E4000032000207047013AF2E700BF00700040E5
+:104E500040420F004802002037B51E4DAB6DDA000E
+:104E6000044618D5FFF7C8FFB0F5007F23D1802C8A
+:104E700029D9A02C8CBF0224012417490A6822F0EA
+:104E8000070222430A60086800F00700001B18BFF1
+:104E9000012003B030BDAB6D43F08053AB65AB6D0B
+:104EA00003F080530193019BFFF7A6FFAB6D23F046
+:104EB0008053AB65D8E7802C07D808D0A4F17003E5
+:104EC0005C425C41D9E70024D7E70324D5E70224FC
+:104ED000D3E700BF0010024000200240464B9A6812
+:104EE00012F00C0F30B509D09A6802F00C020C2AAF
+:104EF00049D1DA6802F00302012A44D11A68120784
+:104F000038D4D3F894204FF4706191FAA1F1B1FA3A
+:104F100081F102F47062CA40384951F822409A681F
+:104F200012F00C0F0CBF204600209A6802F00C0211
+:104F30000C2A55D1DD68D86805F00305702191FA77
+:104F4000A1F1B1FA81F100F07000C840022D00F12A
+:104F500001014FF4FE4228D0032D42D0D86892FAC6
+:104F6000A2F2B2FA82F200F4FE40D040B4FBF1F1BA
+:104F7000484327E01A68F02191FAA1F1B1FA81F1D2
+:104F800002F0F002C7E79A6802F00C02042A07D088
+:104F90009A6802F00C02082A04D119480024C4E7D8
+:104FA0001848FBE700200446BFE7D86892FAA2F24F
+:104FB00000F4FE40B2FA82F220FA02F21148B0FB8D
+:104FC000F1F05043DB684FF0C06292FAA2F2B2FAFD
+:104FD00082F203F0C063D34001335B00B0FBF3F017
+:104FE00030BDD86892FAA2F200F4FE40B2FA82F222
+:104FF00020FA02F20248E2E70010024054E0010801
+:1050000000127A000024F40003682DE9F3410446FD
+:10501000D8063FD5A74DAB6813F00C0F68D12B68AD
+:10502000990703D5A3690BB9012085E02B68206A95
+:105030001A0756BFD5F894302B681B0903F0F0030C
+:10504000984240D9FFF708FF0028EDD12B6843F0C4
+:1050500008032B602B68226A23F0F00313432B60B4
+:105060006B68E26923F47F4343EA02236B60FFF736
+:1050700035FFAB68F02292FAA2F2B2FA82F203F0A4
+:10508000F003D3408C4AD35CD8408C4B18600F207F
+:1050900002F0CAF92368D80761D42368990700F1A0
+:1050A000A98023681A0700F1ED8023685B0700F1EF
+:1050B0001B8123689A0600F18281A26A002A40F0CF
+:1050C000A981002038E02B6843F008032B602B688F
+:1050D00023F0F00303432B606B68E26923F47F4302
+:1050E00043EA02236B60FFF7B7FE0028BFD09BE7BF
+:1050F000A36923B32B6843F001032B60FFF716F875
+:1051000006462B689B0711D52B6843F008032B60DC
+:105110002B68226A23F0F00313432B606B68E2696B
+:1051200023F47F4343EA02236B60B3E7FEF7FEFFFD
+:10513000801B0228E5D9032002B0BDE8F0812B686E
+:1051400023F001032B60FEF7F1FF06462B689F0753
+:10515000A0D5FEF7EBFF801B0228F7D9EBE7554DF2
+:10516000AB6803F00C03082B09D0AB6803F00C0309
+:105170000C2B0BD1EB6803F00303032B06D12B6838
+:105180009A038AD56368002B87D14DE76368B3F52E
+:10519000803F10D12B6843F480332B60FEF7C6FFAD
+:1051A00006462B689B033FF578AFFEF7BFFF801BD9
+:1051B000C828F6D9BFE7B3F5A02F04D12B6843F474
+:1051C00080232B60E6E72A6822F480322A602A686E
+:1051D00022F480222A60002BE0D1FEF7A7FF0646CA
+:1051E0002B689F037FF559AFFEF7A0FF801BC828EF
+:1051F000F6D9A0E72F4DAB6803F00C03042B09D0C0
+:10520000AB6803F00C030C2B19D1EB6803F003031C
+:10521000022B14D12B685E0503D5E368002B3FF405
+:1052200003AF69684FF0F85393FAA3F3B3FA83F22C
+:105230002369934021F0F85213436B6031E7E36830
+:105240007BB12B6843F480732B60FEF76FFF06463B
+:105250002B685805E5D4FEF769FF801B0228F7D9B3
+:1052600069E72B6823F480732B60FEF75FFF064627
+:105270002B6859057FF515AFFEF758FF801B0228F4
+:10528000F6D958E763690B4DD3B1D5F8943043F0A4
+:105290000103C5F89430FEF749FF0646D5F894306F
+:1052A0009F073FF502AFFEF741FF801B0228F5D9AB
+:1052B00041E700BF001002403AE001084802002028
+:1052C000D5F8943023F00103C5F89430FEF72EFF93
+:1052D0000646D5F8943098077FF5E7AEFEF726FF2F
+:1052E000801B0228F5D926E7794DAB6DD90027D46C
+:1052F000AB6D43F08053AB65AB6D03F0805301930E
+:10530000019B0127734E3368DA051BD5A368012B77
+:1053100029D1D5F8903043F00103C5F89030FEF75D
+:1053200005FF41F288380646D5F89030980740D5F9
+:10533000002F3FF4BEAEAB6D23F08053AB65B8E6F3
+:105340000027DFE7336843F480733360FEF7EEFE37
+:1053500080463368DB05D9D4FEF7E8FEA0EB0800F1
+:105360000228F6D9E7E6052B06D1D5F8903043F0B0
+:105370000403C5F89030CCE7D5F8902022F0010264
+:10538000C5F89020D5F8902022F00402C5F89020AE
+:10539000002BC4D1FEF7CAFE41F288380646D5F884
+:1053A00090309907C4D5FEF7C1FE801B4045F6D961
+:1053B000C1E6FEF7BBFE801B4045B5D9BBE6636A7C
+:1053C000434D9BB1D5F8983043F00103C5F89830B0
+:1053D000FEF7ACFE0646D5F898309B073FF56DAE5C
+:1053E000FEF7A4FE801B0228F5D9A4E6D5F8983074
+:1053F00023F00103C5F89830FEF798FE0646D5F86D
+:1054000098309F077FF559AEFEF790FE801B02286B
+:10541000F5D990E62E4DAB6803F00C030C2B3FF44E
+:1054200003AE2B68022A23F080732B6036D1FEF77F
+:105430007DFE06462B6898012AD4D4E90D23DB06AD
+:1054400043EA0223E26A1343226B013A43EA02135E
+:10545000E26B5208013A43EA4253226C5208013A85
+:1054600043EA4263EB602B6843F080732B60EB6888
+:1054700043F08073EB60FEF759FE04462B689901F8
+:105480003FF51FAEFEF752FE001B0228F6D952E68A
+:10549000FEF74CFE801B0228CCD94CE62B681A0183
+:1054A0005EBFEB6823F00303EB60EB6823F08873C7
+:1054B00023F48033EB60FEF739FE04462B689B0132
+:1054C0007FF5FFADFEF732FE001B0228F6D932E66B
+:1054D0000010024000700040584A136803F00703B0
+:1054E0008B422DE9F04105460E462FD32A689107DD
+:1054F00039D4D2073FD4514A136803F00703B342AB
+:1055000000F289802A684E4C12F0040F40F08E8021
+:10551000130706D5A3682A6923F4605343EAC2033C
+:10552000A360FFF7DBFCA368F02292FAA2F2B2FAC2
+:1055300082F203F0F003D340424AD35CD840424B9E
+:1055400018600F2001F070FF00200AE0136823F0BC
+:1055500007030B431360136803F007038B42C5D0A6
+:105560000120BDE8F0813649A8688B6823F0F0037C
+:1055700003438B60BDE76A68314C022A23681BD164
+:1055800013F4003FECD0A36823F003031343A3609C
+:10559000FEF7CCFD6B68022B074641F2883817D125
+:1055A000A36803F00C03082BA5D0FEF7BFFDC01BBA
+:1055B0004045F5D90320D4E7032A02D113F0007F38
+:1055C000E0E712B913F0020FDCE713F4806FD9E7BC
+:1055D000032B0AD1A36803F00C030C2B8BD0FEF72E
+:1055E000A5FDC01B4045F5D9E4E773B9A36813F0E6
+:1055F0000C0F80D0FEF79AFDC01B4045F6D9D9E7C5
+:10560000FEF794FDC01B4045D4D8A36803F00C03FB
+:10561000042BF5D16FE7136823F0070333431360BE
+:10562000136803F00703B3429AD16BE7A368E968F4
+:1056300023F4E0630B43A3606AE700BF002002404D
+:10564000001002403AE0010848020020084B4FF4E5
+:10565000E0629B6892FAA2F2B2FA82F203F4E0638B
+:10566000D340044AD35C044A1068D840704700BF56
+:10567000001002404AE0010848020020084B4FF4A5
+:1056800060529B6892FAA2F2B2FA82F203F460537B
+:10569000D340044AD35C044A1068D840704700BF26
+:1056A000001002404AE00108480200200F23036076
+:1056B0000B4B9A6802F0030242609A6802F0F00213
+:1056C00082609A6802F4E062C2609B68DB0803F4BF
+:1056D000E0630361034B1B6803F007030B60704733
+:1056E0000010024000200240F8B5574BDA6812F073
+:1056F000030F04460E4600681D4639D0DA6802F0F2
+:105700000302824250D1002A4ED0DB68702292FA06
+:10571000A2F2B2FA82F203F07003D340626801335E
+:10572000934241D12B6823F080632B60FEF7FEFC8F
+:1057300007462B681A0140D4A0684FF4FE43002EA0
+:1057400042D0012E296965D193FAA3F34FF4C00228
+:10575000B3FA83F392FAA2F2B2FA82F622695208FD
+:10576000013AB24000FA03F3134321F4C0023DE0D2
+:10577000022815D0032819D0012815D11B689F07CE
+:1057800021D5EA68702393FAA3F3B3FA83F163682F
+:1057900022F07302013B8B4010431843E860C1E7DD
+:1057A0001B6813F4806FECD101200CE01A689103A0
+:1057B000E7D41B6813F4802FF5E7FEF7B7FCC01B96
+:1057C0000228B6D90320F8BD296993FAA3F34FF054
+:1057D0007842B3FA83F392FAA2F2B2FA82F6E2685E
+:1057E00000FA03F3B240134321F0784222F4FE4260
+:1057F00013432B612B6843F080632B60FEF796FC0C
+:1058000006462B681B0119D52B69A26913432B612E
+:105810000020D8E793FAA3F34FF0C062B3FA83F302
+:1058200092FAA2F2B2FA82F662695208013AB240E2
+:1058300000FA03F3134321F0C062D7E7FEF776FCCA
+:10584000801B0228DDD9BDE7001002402DE9F74397
+:10585000056815F40065044609D0C16BB1F5000F69
+:1058600032D0B1F5400F34D000293DD00125236856
+:105870009E0351D5944EB36DD8003CD4B36D43F024
+:105880008053B365B36D03F080530193019B4FF0D8
+:1058900001088E4F3B6843F480733B60FEF746FC83
+:1058A00081463B68D90529D57DBBD6F8903013F4E5
+:1058B000407340F0CA80D6F89030226D23F44073D4
+:1058C0001343C6F8903020E07F4AD36843F4803316
+:1058D000D3607D4AE16BD2F8883023F440030B4358
+:1058E000C2F888300025C2E70430FFF7FDFE054608
+:1058F0000028BCD1EDE74FF00008CAE7FEF716FC20
+:10590000A0EB09000228CCD90325B8F1000F03D081
+:10591000B36D23F08053B3652368DF0708D56A4968
+:10592000206AD1F8882022F003020243C1F88820BF
+:105930009E0708D56449606AD1F8882022F00C02DD
+:105940000243C1F88820980608D55F49A06AD1F8BB
+:10595000882022F440620243C1F88820990508D5C6
+:105960005949606BD1F8882022F440220243C1F8E3
+:1059700088205A0508D55449A06BD1F8882022F414
+:1059800040120243C1F888205F0608D54E49E06AFC
+:10599000D1F8882022F440520243C1F88820DE0565
+:1059A00008D54949206BD1F8882022F440320243BF
+:1059B000C1F8882098040FD5434A216CD2F888306A
+:1059C00023F040630B43B1F1006FC2F8883065D11A
+:1059D000D36843F48013D360236859030FD53A4A40
+:1059E000616CD2F8883023F040630B43B1F1006F53
+:1059F000C2F888305DD1D36843F48013D360236844
+:105A00005A0412D53049A26CD1F8883023F04053A3
+:105A10001343B2F1805FC1F8883006D10221201D06
+:105A2000FFF762FE002818BF054623681B0408D54F
+:105A3000254AE16CD2F8883023F080430B43C2F84A
+:105A40008830284603B0BDE8F083226D93423FF4CE
+:105A500032AFD6F89020D6F8903043F48033C6F8B1
+:105A60009030D6F8903022F4407123F48033D2077E
+:105A7000C6F89030C6F890107FF51DAFFEF756FBC4
+:105A800041F288390746D6F890309B073FF513AFAF
+:105A9000FEF74CFBC01B4845F5D935E7B1F1806FE7
+:105AA0009AD10121201DFFF71FFE002818BF0546CF
+:105AB00092E7B1F1806FA2D10121201DFFF714FE02
+:105AC000002818BF05469AE7001002400070004009
+:105AD000054BD3F8902022F02002C3F890209A6959
+:105AE00022F400729A61704700100240024A136863
+:105AF00043F00403136070470010024003685A68C3
+:105B000022F0E0025A604268B2F5827F0AD18268D0
+:105B1000B2F5004F02D0B2F5806F03D11A6822F0BF
+:105B200040021A60826AB2F5005F09D11A6822F455
+:105B300000521204120C1A601A6842F400521A60E1
+:105B4000012380F85D30002380F85C30032070472B
+:105B50002DE9F34107460E4615461C46FEF7E6FAC8
+:105B600080463A6893683340AB4203D1002002B0CC
+:105B7000BDE8F081B6F5C06F06D12DB9137BDBB25D
+:105B80008DF807309DF80730631CEBD02CB93846F0
+:105B900002B0BDE8F041FFF7B1BFFEF7C7FAA0EBD6
+:105BA0000800A042DDD3F2E72DE9F04105460F469B
+:105BB00016461C46FEF7BAFA80462A6893683B40B0
+:105BC000B34202D10020BDE8F081631CF6D024B9B5
+:105BD0002846BDE8F041FFF791BFFEF7A7FAA0EB1A
+:105BE0000800A042E9D3F3E713B50B460191002268
+:105BF0004FF4C0510446FFF7ABFF019B024628B1AA
+:105C0000236E43F020032366032005E08021204615
+:105C1000FFF7CAFF0028F3D102B010BD37B54268C4
+:105C2000B2F5827F04460B460BD18268B2F5004F75
+:105C300002D0B2F5806F04D121680A6822F04002D8
+:105C40000A600022802120460193FFF7ADFF019BEF
+:105C5000054628B1236E43F020032366032512E096
+:105C60006268B2F5827F0ED1A268B2F5004F02D011
+:105C7000B2F5806F07D100224FF4C0612046FFF7D4
+:105C800067FF0028E6D1284603B030BD704770B5E5
+:105C9000044600284DD090F85D3003F0FF021BB998
+:105CA00080F85C20FFF7F2FF2268E568022384F8A1
+:105CB0005D301368B5F5E06F23F0400313604FF0DB
+:105CC000000338D84FF4805100D0A362236B2BB966
+:105CD000B5F5E06F8CBF022301232363D4E90136BD
+:105CE00033432669A069334366693343E669334326
+:105CF000266A3343A66A334300F4007633431360C5
+:105D0000236B022B02BF136843F400631360636AC2
+:105D10002B43656B000C00F004002B4303430B4343
+:105D20005360E36A136100200123206684F85D302C
+:105D300070BD0120FCE71946B5F5706FC4E72DE989
+:105D4000F34104461D4688461746FEF7EFF994F8DE
+:105D50005C30012B064600F09F80012384F85C3004
+:105D600094F85D30012BD8B240F09480B8F1000F68
+:105D70006DD0002F6BD00323A26884F85D30002320
+:105D80002366C4E910332368C4F83880B2F5004FA5
+:105D900008BF1A68A78708BF42F48042E78708BF98
+:105DA0001A60A26AB2F5005F09D11A6822F40052A3
+:105DB0001204120C1A601A6842F400521A601A682F
+:105DC00051065EBF1A6842F040021A60E368B3F5FC
+:105DD000E06F1AD8E28FDAB121688B6898074FD547
+:105DE000012AA36B44D933F8020BC860023AA363BB
+:105DF000E287EFE721688A68920726D5A26B013B0C
+:105E000032F8020BC860A263E387E38F002BF1D165
+:105E1000A36AB3F5005F04D12268136843F480538A
+:105E2000136029462046FFF7DFFE08B120232366D2
+:105E3000A3682BB92368DA6801929B680193019BE0
+:105E4000206E003818BF012001E04DB90320012366
+:105E500084F85D30002384F85C3002B0BDE8F08146
+:105E60006F1CD2D0FEF762F9801BA842CDD3EDE7BC
+:105E70005A1CA2631B780B73E38F013BE387A9E7EE
+:105E8000002DE3D06B1CA5D0FEF750F9801BA84273
+:105E9000A0D3DBE70220DAE70220DEE72DE9F743B3
+:105EA00004461D460A9E88469146FEF73FF994F83F
+:105EB0005C30012B074600F02581012384F85C301B
+:105EC00094F85D30012B40F01B81B8F1000F0AD12E
+:105ED0000125012384F85D30002384F85C302846D6
+:105EE00003B0BDE8F083B9F1000FF1D0002DEFD081
+:105EF000052384F85D3000232366A36A2268C4F872
+:105F00004090B3F5005FA4F84650A4F84450C4F89C
+:105F10003880E587A58709D1136823F400531B0453
+:105F20001B0C1360136843F400531360E16853685B
+:105F3000B1F5E06F01D8012D14D923F480535360DB
+:105F4000136858065EBF136843F040031360B1F551
+:105F5000E06F37D8E28F002A4CD1B4F84630002BDE
+:105F600060D136E043F48053E9E7226891688907FD
+:105F700010D5A16B013B31F8025BD5609BB2A163E8
+:105F8000E3873BB9A36AB3F5005F02BF136843F42C
+:105F90008053136068B123689A68D20709D5DA681C
+:105FA000236C23F8022B2364B4F84630013BA4F899
+:105FB0004630731C06D0FEF7B9F8C01BB04201D3BF
+:105FC000032586E7E38FB4F84600002BCDD10028E7
+:105FD000E1D1A36AB3F5005F65D1012233461146D2
+:105FE0002046FFF7E1FD002852D0236E43F0020364
+:105FF0002366E5E721688B689D0713D5012AA36B0B
+:1060000034D933F8020BC860023AA363E287E38F06
+:1060100043B9A36AB3F5005F01BF2268136843F474
+:1060200080531360B4F84610B1B122689368D80762
+:1060300012D50129236C21D9D16823F8021B2364CE
+:10604000B4F84630023B9BB2012BA4F8463003D88B
+:10605000536843F480535360731C3FF47BAFFEF7E7
+:1060600065F8C01BB042FFF475AFA9E75A1CA263E4
+:106070001B780B73E38F013BE387C8E7591C21644E
+:10608000127B1A70B4F84630013BA4F84630E3E7BF
+:10609000E2682368B2F5706F1ED1DB689BB2ADF881
+:1060A0000630BDF806302268956815F0100507D057
+:1060B000236E43F0020323664FF6EF7393600125CE
+:1060C00031462046FFF790FD08B120232366236E5A
+:1060D000002B7FF4FDAEFCE61B7BADF80630BDF86F
+:1060E0000630236B022BDED10122334611462046B7
+:1060F000FFF75AFD00287FF478AF23681B7BCEE7BB
+:106100000225E6E60225EAE62DE9FF4104461D46A2
+:106110000F461646FEF70AF86368B3F5827F80469D
+:106120000BD1A3684BB9009533463A463946204611
+:10613000FFF7B4FE04B0BDE8F08194F85C30012BA9
+:1061400000F0E980012384F85C3094F85D30012B85
+:10615000D8B240F0DE80002F00F08780002E00F0E3
+:106160008480042384F85D300023C4E90E33236661
+:10617000A36A21682764B3F5005FA4F84460A4F81B
+:1061800046600CD10B6823F400531B041B0C0B60FE
+:106190000B68013E43F400530B60A4F84660E268CC
+:1061A0004B68B2F5E06F8CBF23F4805343F4805307
+:1061B0004B60A368B3F5004F02BF0B6823F4804324
+:1061C0000B600B685F065EBF0B6843F040030B601B
+:1061D000B2F5E06F1FD9B4F8463003B323689A686C
+:1061E000D10752D5DA68236C23F8022B2364B4F864
+:1061F0004630013BA4F84630EDE722689368DE079D
+:1062000031D5236C591C2164127B1A70B4F84630C6
+:10621000013BA4F84630B4F84630002BEDD1A36A18
+:10622000B3F5005F47D12268136843F480531360CD
+:1062300001222B4611462046FFF7B6FCA0B9E168C3
+:106240002268236CB1F5E06F8BBFD268127B1A8095
+:106250001A7001222B4611462046FFF7A5FCF8B123
+:106260000223236600E03DB90320012384F85D305A
+:10627000002384F85C305DE7681CCCD0FDF756FF46
+:10628000A0EB0800A842C6D3EEE7002DECD06A1CB4
+:10629000A1D0FDF74BFFA0EB0800A8429BD3E3E79A
+:1062A000E2682368B2F5706F1CD1DB689BB2ADF871
+:1062B0000E30BDF80E3029462046FFF7AFFC08B17E
+:1062C0002023236622689368DB0606D5236E43F0FD
+:1062D000020323664FF6EF739360206E003818BFF9
+:1062E0000120C2E71B7BADF80E30B2F5E06FBDF8C0
+:1062F0000E30E0D1266B022EDDD101222B46114655
+:106300002046FFF751FC08B12666ADE723681B7BEA
+:10631000CDE70220A9E702200CE77047184A03687E
+:10632000904210B502D0B0F1804F09D14C6823F0F3
+:106330007003904243EA040309D0B0F1804F06D0C5
+:10634000104A904203D002F58062904203D1CA689D
+:1063500023F44073134303608B68C3620B6883624A
+:10636000074B984207D003F5A053984203D003F59A
+:106370008063984201D10B6903630123436110BD1F
+:10638000002C01400040014010B50446A0B190F837
+:10639000393003F0FF021BB980F83820FFF7BDFF4A
+:1063A0000223206884F83930211DFFF7B7FF01234D
+:1063B00084F83930002010BD0120FCE7036A10B5D5
+:1063C00001248C4023EA04030362036A02FA01F108
+:1063D0000B43036210BD000010B5044601220068A3
+:1063E000FFF7ECFF23680A4A934207D002F5A05258
+:1063F000934203D002F58062934203D15A6C42F477
+:1064000000425A641A6842F001021A60002010BD6E
+:10641000002C014070470000F8B5C169036882682C
+:106420001D680446006902436069024396480A43B6
+:10643000284002431A605A68E06822F4405202433E
+:106440005A60924AA06993421CBF226A10439A681C
+:1064500022F4306202439A608D4A93421DD102F5C4
+:106460005842D2F8882002F00302013A022A00F2D0
+:10647000F5808848855CB1F5004F40F0B880082D64
+:1064800000F2FF80DFE815F086009700A200FD0013
+:10649000AB00FD00FD00FD00AE007F4A934207D136
+:1064A00002F5E6327D48D2F8882002F00C02E1E7DE
+:1064B000764A934240F0E180794BD3F8885005F456
+:1064C0004065B5F5006F27D005D85DB1B5F5806F93
+:1064D0001ED0012538E0B5F5406FFAD108254FF4FC
+:1064E000004004E0FFF7B2F8002800F0C4806268C2
+:1064F00002EB42038342ECD8B0EB023FE9D8082D0F
+:1065000046D8DFE805F00C4523452F4545453C00BE
+:10651000FEF7E4FC0425E7E762480225E7E7FFF71A
+:1065200095F862684FF4807156080027E1FB006718
+:1065300000233046394616F089FD5B4BA0F54072CA
+:106540009A42C6D82368D8602846F8BD57485508EF
+:10655000002140194FF0000341F1000116F076FDD3
+:106560000025EAE7FEF7BAFC62684FF4807156082E
+:106570000027E1FB0067002330463946EEE750086C
+:1065800010F500004FF000032CBF01210021E5E7CA
+:106590000125D2E7FFF75AF863685A0802EB40007A
+:1065A000B0FBF3F39BB223F00F022168C3F3420365
+:1065B0001343CB60C8E7FFF761F863685A0802EB42
+:1065C0004000B0FBF3F39BB20025ECE76268530890
+:1065D00003F1F47303F59043B3FBF2F3F3E7FEF733
+:1065E0007DFCEAE76268530803F58033F4E7082D81
+:1065F0003FF66FAF01A252F825F000BF21660008F8
+:106600006366000837660008D36400084D6600081A
+:10661000D3640008D3640008D364000853660008FC
+:10662000FFF714F8D4E9002300EB5300B0FBF3F0BC
+:1066300080B2D06088E761684A0802F5740202F50A
+:106640001052B2FBF1F292B2DA6014E0FEF746FCAF
+:1066500009E061684A0802F50042F2E7B1F5004F2F
+:10666000A9D0FFF70BF8D4E9002300EB5300B0FBEF
+:10667000F3F080B2D060002566E7B1F5004F7FF4FB
+:1066800028AF012500238EE7F369FFEF008000406B
+:10669000003801402AE00108004400402DE00108D4
+:1066A000001002400024F400FFFC0F00000024F45E
+:1066B000436ADA0710B506D50168846A4A6822F48D
+:1066C000003222434A609C0706D50168C46A4A68C2
+:1066D00022F4803222434A60590706D50168046BD0
+:1066E0004A6822F4802222434A601A0706D50168CC
+:1066F000446B4A6822F4004222434A60DC0606D515
+:106700000168846B8A6822F4805222438A60990669
+:1067100006D50168C46B8A6822F4005222438A605D
+:106720005A060FD50168046C4A6822F4801222438D
+:10673000B4F5801F4A6005D14A68446C22F4C00257
+:1067400022434A601B0606D50268816C536823F415
+:1067500000230B43536010BD2DE9F041DDF8188094
+:1067600004460E4615461F462268D36936EA0303DF
+:106770000CBF01230023AB4201D0002017E0B8F189
+:10678000FF3FF2D0B8F1000F13D123681A6822F44A
+:10679000D0721A609A6822F001029A60202384F86D
+:1067A000693084F86A30002384F868300320BDE83B
+:1067B000F081FDF7BBFCC01B4045D5D9E5E730B5FE
+:1067C0000446002585B0C566FDF7B0FC2268126856
+:1067D0001107034616D422681268520709D56FF0D4
+:1067E0007E4200924FF4800100222046FFF7B4FF62
+:1067F000A8B92023002084F8693084F8680084F860
+:106800006A300DE06FF07E42009203902A464FF40A
+:1068100000112046FFF7A0FF039B0028DBD00320D8
+:1068200005B030BD10B5044660B390F8693003F090
+:10683000FF021BB980F86820FFF7ECFD22682423D3
+:1068400084F86930136823F0010313602046FFF7D2
+:10685000E3FD012816D0636A13B12046FFF728FF35
+:1068600023685A6822F490425A609A6822F02A02F9
+:106870009A601A6842F0010220461A60BDE8104092
+:10688000FFF79DBF012010BD234A24491368244807
+:106890001B0755BFD2F894301368C3F30323C3F327
+:1068A000031310B551F82340916801F00C01082939
+:1068B0000ED00C290ED004292CD11A4B03609368FA
+:1068C000194AC3F30313D25C0368D340036010BDBD
+:1068D000164BF3E7D168D36801F00301C3F3021349
+:1068E000022903F1010304D0032911D0B4FBF3F30F
+:1068F00002E00C49B1FBF3F3D468D168C1F3416104
+:10690000C4F30624013163434900B3FBF1F3D5E737
+:106910000649EFE70460D2E70010024054E00108A6
+:10692000480200200024F4003AE0010800127A0036
+:10693000002070470020704730B5234D87B00C46CB
+:106940000023298801934FF6FF7399421DBF1F4B07
+:1069500003EA812303F100634FF00163A34204D8EB
+:106960004FF0FF34204607B030BDB4F1006FF7D3CD
+:10697000FEF7A6F80028F3D1154B4FF400421A6138
+:106980002B884FF6FF7293421DBF104901EA832105
+:1069900001F100614FF001618C422CBF641A04F1D7
+:1069A000784401230022E40A01A902A8CDE90443A6
+:1069B000CDE90223FEF78CF9003818BF01204442CC
+:1069C000FEF790F8CEE700BFE075FF1F00FC3F0028
+:1069D00000200240F7B51F46284B1B8816464FF68D
+:1069E000FF7293421DBF264A02EA832202F100622F
+:1069F0004FF001628A420C4604D84FF0FF3528461A
+:106A000003B0F0BDB1F1006FF7D37B07F5D1FEF70E
+:106A100057F80028F1D116F00305274428D1A742E2
+:106A200020D9EDB9D6E9002321462846FEF7AAF879
+:106A300000BB08340836F2E72A46B35C0DF8023092
+:106A40000132082AF9D1DDE9002321460020FEF7B2
+:106A500099F850B908340836A74203D9002DEBD075
+:106A60004FF0FF35FEF73EF8C9E74FF0FF35F3E78B
+:106A70000546F1E74FF0FF35D1E700BFE075FF1F96
+:106A800000FC3F000C4B1A884FF6FF739A421DBF63
+:106A90000A4B03EA822303F100634FF001638B4248
+:106AA00007D9B1F1006F34BF4FF0FF304FF40060F1
+:106AB00070474FF0FF307047E075FF1F00FC3F004C
+:106AC0000820704773B5184E044656F82000002879
+:106AD00028D07023154D6343EB58DA69120606D5AA
+:106AE000DB69190603D5124B01211B6898477023F7
+:106AF0006343EB58DA69920608D5DB69980605D539
+:106B00000B4B56F824001B68002198477020444323
+:106B10002B59DA69110705D5DA69120742BF9B8C38
+:106B20009BB2019302B070BDE417002000E3002087
+:106B3000E01700200020FFF7C5BF0120FFF7C2BF0C
+:106B40000520FFF7BFBF0000F0B50E4685B04849ED
+:106B5000044630461546FAF74BFA4649074628469A
+:106B6000FAF746FA01463846FAF724FA206001306F
+:106B700004D1414941483E22FAF700FE2368404AC9
+:106B8000934214D13F4B1A6C42F480421A641A6C3F
+:106B900022F480421A641A6E42F480421A661B6E16
+:106BA00003F480430193019B0023636006E0364AAF
+:106BB000934233D002F57052934243D02C49304671
+:106BC000FAF7DAF928462B49FAF7D6F9701C03D000
+:106BD0000121304600F05EFD691C03D001212846EA
+:106BE00000F058FD00234FF41652C4E90223C4E913
+:106BF0000433E36126836583204600F09BFD226811
+:106C0000214B9A4232D1214B214801221A60214660
+:106C1000242205B0BDE8F0400AF05AB9194B9A6B2E
+:106C200042F400329A639A6B22F400329A639A6DAE
+:106C300042F400329A659B6D03F400330293029B89
+:106C40000123B2E70F4BDA6B42F00102DA63DA6B31
+:106C500022F00102DA63DA6D42F00102DA65DB6DDF
+:106C600003F001030393039B05239EE705B0F0BDEA
+:106C700058DF010810DF010844E1010881E1010843
+:106C8000003801400010024000440040FC17002082
+:106C9000A0E50020816000F04DBD0000034B1960AD
+:106CA0004168034B43F82120704700BFE0170020E4
+:106CB000E417002030B5D0E90035274883421AD1C7
+:106CC000264C252370206843254D285832B302688E
+:106CD00009BB42F020020260224A03F110019268CF
+:106CE00042F8214003F007025909012393401E4A4C
+:106CF00042F8213030BD1D48834206D000F5705067
+:106D0000834205D000242346DCE7194C2623D9E72B
+:106D1000184C4623D6E742F08002DCE70268A1B9AE
+:106D200022F020020260026812F0800FE2D103F02C
+:106D300007015A0901238B4020320B4941F82230C8
+:106D4000BFF34F8FBFF36F8FD4E722F08002026052
+:106D5000026812F0200FE9E700380140356B0008A7
+:106D600000E3002000ED00E000E100E0004400400E
+:106D70003B6B0008416B000838B545680446204667
+:106D800000F010FD0028FAD07023054A6B43D35859
+:106D9000E268988C0AB9C0B238BDC0F30800FBE7BE
+:106DA00000E3002070B5466805460C46284600F012
+:106DB00009FD0028FAD07023054A7343D358EA68C6
+:106DC00012B9E4B21C8570BDC4F30804FAE700BF31
+:106DD00000E3002008B50A4A836E934207D002F50B
+:106DE0007442934207D1BDE80840FEF747BCBDE8B6
+:106DF0000840FEF72BBC0348FAF7A6FD002008BDAB
+:106E0000003C00409DE10108384B5A69D20770B53B
+:106E10002ED59D68364C996836489A6805EA04066E
+:106E2000AC4301EA000104BF01249C6022F06F42E0
+:106E300081422E4B08BF4FF4807022F47C0208BFC1
+:106E40009860120C2C481204824204BF4FF4803028
+:106E50009860274B9E4205D0264B994202D0264B84
+:106E60009A4205D1254B264A1B6810680121984794
+:106E70001E4BDA685B69960707D09D0705D51F4B47
+:106E80001F4A1B68106800219847184B99695A6976
+:106E90005B698C0709D5900507D5190405D5174BF3
+:106EA000174A1B68106805219847104A956954696C
+:106EB000526915F0040504F4806408D03CB1120452
+:106EC00005D50E4B0E4A1B68106807219847074BE3
+:106ED0005B6955B14CB11B0407D5084B084A1B68C8
+:106EE0001068BDE870400221184770BD0064004082
+:106EF0000300000400030008000003100418002031
+:106F000000180020FFF780BFFFF77EBF1FB50728DE
+:106F100038D8DFE800F004131F373737372B1C4B06
+:106F2000DA6C42F00102DA64DB6C03F001030093D7
+:106F3000009B4FF0904005B05DF804FB144B1548E2
+:106F4000DA6C42F00202DA64DB6C03F002030193B4
+:106F5000019BF0E70E4B1048DA6C42F00402DA6451
+:106F6000DB6C03F004030293029BE4E7084B0B483D
+:106F7000DA6C42F08002DA64DB6C03F08003039386
+:106F8000039BD8E70648FAF7DFFC0020D3E700BFF1
+:106F9000001002400004004800080048001C00489F
+:106FA000B7E10108431C10B5044604D1064907485F
+:106FB0007422FAF7E3FB2046002100F0D1FA04F036
+:106FC0000F040120A04010BDD8E1010801E2010832
+:106FD0004B1C70B504460E46018218D0C1F3031055
+:106FE000FFF794FF05463046FFF7DCFF238A084A87
+:106FF000656103F00F03206052F82330A36105F1AF
+:107000001003636005F118032835A360E56070BDC7
+:107010008CE20108B0F9100000F03CBB10B5D0E9DB
+:10702000054371B9216893FAA3F2B2FA82F2032000
+:10703000520000FA02F221EA020293FAA3F322605C
+:1070400010BD226893FAA3F1B1FA81F193FAA3F388
+:107050000320490000FA01F1B3FA83F322EA0102A6
+:107060005B00012101FA03F313432360E8E700000A
+:10707000184B4C22F0B502FB0033174F0446002595
+:107080009C460126DCF8000006FA05F2024215D003
+:107090005A6B786906FA02F210420FD0D3F81CE05E
+:1070A0007A61586850B1DEF810100C4B1142BDE8FF
+:1070B000F0401B680CBF0221012118470135A9428D
+:1070C00003F10403DED121460548BDE8F040FAF79C
+:1070D0003BBC00BF08180020000401401C1A00201F
+:1070E00014E2010806210846FFF7C2BF0521084641
+:1070F000FFF7BEBF01210420FFF7BABF0121032023
+:10710000FFF7B6BF01210220FFF7B2BF01210846F9
+:10711000FFF7AEBF01210020FFF7AABF012910B57C
+:1071200014D18389154C03F00F039940836832B161
+:10713000A2681143A16043F00103836010BDA268FF
+:1071400022EA0101A16023F00103F6E70229F5D14B
+:1071500081890A4C01F00F030121994083682AB10B
+:10716000E2681143E16043F00203E6E7E26822EAE5
+:107170000101E16023F00203DFE700BF00040140EA
+:107180008389B0F90C1070B503F00C0404F180444D
+:1071900004F5803403F00F0603F00303A5689B0099
+:1071A0000F229A40C1F3031125EA020501FA03F305
+:1071B0002B43A3600F4B01221968B24011431960A1
+:1071C0008468E50742BF996811439960A10742BFEF
+:1071D000D9680A43DA6090F90030002B08DB5909BE
+:1071E000012203F01F0302FA03F3034A42F821309D
+:1071F00070BD00BF0004014000E100E02DE9F74F41
+:107200009B464B1C06460C46904663D0324B1A6E8A
+:1072100042F001021A661B6E03F001030193019B09
+:107220002E4B01F00F090C2202FB0932C1F30310AF
+:107230005568062D46D8DFE805F004393B3D3F414F
+:107240004300274FFFF762FE244BB4810C2202FB60
+:1072500009F299189C5891F908C0224986F800C093
+:107260004C236B43012202FA04FECA5875604FF0AA
+:10727000000A42EA0E02C6F808A0CA50132303FB14
+:10728000054501EB85030CF1100CD861C3F804B07F
+:10729000C3F83490144BC3F80080144B9B683046FD
+:1072A00043F82C70FFF76CFF504610E0104FC9E711
+:1072B000104FC7E7104FC5E7104FC3E7104FC1E7A6
+:1072C000104FBFE71048FAF73FFB4FF0FF3003B015
+:1072D000BDE8F08F0846FAE70010024084E001089C
+:1072E00015710008081800201C1A002000ED00E0AD
+:1072F0000D71000805710008FD700008F5700008A8
+:10730000ED700008E57000083EE20108194A838923
+:1073100010B503F00F039468012101FA03F324EA86
+:1073200003049460D46824EA0304D460146824EA53
+:107330000303136090F90030002B0CDB5A0903F0B3
+:107340001F0301FA03F320320B4941F82230BFF347
+:107350004F8FBFF36F8F90F90030002B09DB5A0974
+:10736000012103F01F0301FA03F36032024941F8DF
+:10737000223010BD0004014000E100E0838903F0E9
+:107380000F010C234B43104970B54468CE58FFF7EA
+:10739000BDFF4C210D4A6143012000FA06F550580B
+:1073A000132303FB046320EA0500505002EB830023
+:1073B00000214160981D0C3302EB800002EB830337
+:1073C0004160596070BD00BF84E0010808180020CA
+:1073D00070B5134C23681A69950707D5DA689007CA
+:1073E00004D56FF002021A61FAF736F823681A69B9
+:1073F000510713D5DA68520710D50A4E6FF0040210
+:107400001A615D6A3368EB1AB3F57A7F06D3FCF72D
+:1074100085FE236805F57A729A63356070BD00BFFA
+:10742000C4E50020201A002030B589B001A903A8C6
+:10743000FEF73CF9FEF70AF9244B01909A6D244CB3
+:1074400042F001029A659A6D02F001020292029ADC
+:107450009A6B42F001029A639A6B22F001029A63DE
+:10746000069A4FF0804323604FF0FF33E360194BDF
+:1074700052BBB0FBF3F00138002560601448256171
+:10748000A5606561FEF780FF134B144A9B681048A6
+:10749000C3F8B020124B4FF080521A602946FEF715
+:1074A0009BFF04210A48FEF797FF23680D4A596A9B
+:1074B0001160126802F57A729A63DA68284642F01F
+:1074C0000402DA6009B030BD4000D2E7001002408B
+:1074D000C4E5002040420F0000ED00E0D173000839
+:1074E00000E100E0201A0020034B1A68D36823F063
+:1074F0000403D360704700BFC4E50020034B1A6843
+:10750000D36843F00403D360704700BFC4E5002094
+:1075100008B5FFF7B9F9FCF7F6FDFCF7E9FCBDE8A3
+:107520000840FFF7B1B930B5C36891FAA1F4B4FAD5
+:1075300084F491FAA1F10325B1FA81F1640005FA0E
+:1075400004F4490023EA04038A401343C36030BDB6
+:10755000012A02D0022A18BF0022FFF7E4BF000070
+:107560002DE9F0410E46411C044604D145494648E8
+:107570003E22FAF703F904F00F02444BC4F3031060
+:1075800053F82250FFF7C2FC1FFA84F8836806F014
+:107590000707044695FAA5F1B1FA81F195FAA5F22B
+:1075A0000320490000FA01F1B2FA82F223EA010352
+:1075B0005200022101FA02F21343A360874236D837
+:1075C000DFE807F01D1D021D18F0080FC6F30320A9
+:1075D00017D0626A2B0A93FAA3F1B1FA81F193FAF8
+:1075E000A3F34FF00F0CB3FA83F389000CFA01F107
+:1075F0009B0022EA010200FA03F3134363623B4655
+:107600001BE0226A95FAA5F3B3FA83F395FAA5F184
+:107610004FF00F0CB1FA81F19B000CFA03F38900D3
+:1076200022EA030200FA01F313432362E7E7154954
+:1076300017486722FAF7A2F80023226895FAA5F006
+:10764000B0FA80F095FAA5F14FF0030CB1FA81F190
+:1076500040000CFA00F0490022EA00028B40013F92
+:107660001343012F236005D8636832074CBF2B43B7
+:10767000AB436360C6F3011229462046BDE8F041E2
+:10768000FFF766BF65E2010801E201088CE201082C
+:107690003CD60108431C70B506460C4604D122496D
+:1076A00022488822FAF76AF806F00F02204BC6F348
+:1076B000031053F82250FFF729FC066895FAA5F14C
+:1076C000B1FA81F395FAA5F259000323B2FA82F2D6
+:1076D0008B4033405200D340013B012B1AD8E31EAC
+:1076E000022B436809D82B43032C43601AD1012293
+:1076F0002946BDE87040FFF72BBF23EA0503012CA4
+:107700004360F4D0022C0BD029460022BDE8704023
+:10771000FFF709BF04F0FD03012BE8D0052CF1D1E0
+:107720000222E5E7052CEEE765E2010801E2010827
+:107730008CE201084168034670224A43174910B59C
+:107740001C68545050189A684260DA6882601A695E
+:10775000C2605A690261DA6982610022A0F852208F
+:10776000C261A0F85020A0F85A20A0F85820B3F920
+:107770001A20013209D108234361FFF753F858B1A9
+:10778000BDE810400648FAF7DFB8B3F91830013306
+:107790000CBF04230C23EFE710BD00BF00E3002063
+:1077A000CCE20108426870235343054AD358DA6992
+:1077B000120744BF08221A62D869C0F3401070470C
+:1077C00000E30020426870235343034AD358D8692A
+:1077D000C0F3C010704700BF00E3002008B5FAF7FF
+:1077E0004FF8FFF781FE01210020FDF7E5FAFFF7D2
+:1077F00085FEBDE80840FAF76FB80000026813681C
+:1078000023F0400310B513600446FEF740FA10B1B0
+:107810000548FAF799F8A36823B92268136843F07A
+:107820004003136010BD00BFE4E201082DE9F04FF2
+:107830000F4685B04649BDF938800446384615469E
+:107840001E46F9F7D5FB434981462846F9F7D0FB98
+:10785000414901903046F9F7CBFB4049824640460A
+:10786000F9F7C6FB019B834619464846F9F7A2FB88
+:10787000594681465046F9F79DFB01464846F9F7BF
+:1078800099FBA066013004D1354936486A22F9F7E0
+:1078900075FFA36E344A934246D1344B1A6E42F4BC
+:1078A00080521A661B6E03F480530293029B2323BB
+:1078B00084F8643026493846F9F75EFB25492846A6
+:1078C000F9F75AFB24493046F9F756FBB8F1FF3F68
+:1078D000A4F86C50A4F86E70A4F87060A4F87280DC
+:1078E00031D01E494046F9F747FBA36E23604FF4A1
+:1078F0008273636038230135E3614FF0000314BFE6
+:107900001A464FF40042A2600722E26220464FF47A
+:10791000E062C4E90433C4E90833A362E26005B05D
+:10792000BDE8F04FFFF76ABF114A9342C2D10F4B37
+:107930009A6D42F400429A659B6D03F400430393F1
+:10794000039B3323B4E74FF40073A361CDE700BF7B
+:1079500068DE01082CDE0108A4DE0108E0DE010873
+:10796000FAE2010826E3010800300140001002405D
+:10797000003C004010290CBF4FF470614FF4E061EF
+:10798000012AC16016D0022A17D0CAB90261426129
+:107990008269B2F5007F05D0002B14BF00224FF49E
+:1079A00080228261002B14BF00234FF48273436056
+:1079B000FFF724BF00210161E9E702610022E6E749
+:1079C000022202610122E2E738B504460D46FFF7C4
+:1079D00001FA00EBD0735B100022AB42D1B203DDA1
+:1079E0000132082A09D10721064B33F81130E3612F
+:1079F0002046BDE83840FFF701BF03EBD3735B10AF
+:107A0000EBE700BF42E3010807B582680191B2F5D8
+:107A1000004F034607D10A23012201A9FEF78FF97F
+:107A200003B05DF804FB9A6EC0685168B0F5706FE2
+:107A30000CBF21F4805141F4805151609168890755
+:107A4000FCD50199B0F5706F15BFC9B289B2117339
+:107A500091819A6E9168C907FCD5DB68D068B3F54F
+:107A6000706F0CBF80B2C0B2DAE72DE9F84FDDF8D5
+:107A7000288084689DF82CB09045464607468A4683
+:107A800015469946B8BF16462CB33AB10A2353435C
+:107A900092B2FEF754F9002818BF0026B8F1000F83
+:107AA0001BD00A2303FB08F31FFA88F24946384625
+:107AB000FEF72AFB002818BF00260EE0AC42B4BF38
+:107AC0001AF8041059463846FFF79EFF4445B8BFE0
+:107AD00009F804000134B442F0DB3046BDE8F88F09
+:107AE00013B514461A46049B9C4238BF1C46032318
+:107AF0000093A3B2FEF7D2F9002002B010BD704788
+:107B00004FF08043586A7047054B1B68DA6822F0D3
+:107B10000202DA605863DA6842F00202DA60704703
+:107B2000C4E50020034B1A68536943F00203536114
+:107B3000704700BFC4E50020034B1A68D36823F0E8
+:107B40000203D360704700BFC4E50020024B1B68EE
+:107B50006FF002021A617047C4E5002030B5421E82
+:107B6000431D0139012012F8015F11F8014FA542B0
+:107B700018BF00209A42F6D130BD00000023044A0D
+:107B800019460133202B02F8011BFAD1704700BFC0
+:107B9000E41B00202DE9F04100240A4E0A4D8846DE
+:107BA000274641463046FFF7D9FF10B12B7803B185
+:107BB0002F700134202C06F1060605F10105F0D1E5
+:107BC000BDE8F081A41A0020E41B00202DE9F74F46
+:107BD000804610461E460C9F0091144600F048FD5A
+:107BE000DFF864B281464FF0000AFF25062303FB4D
+:107BF0000AB00099FFF7B2FF8F4A062320B11AF8A6
+:107C00000210002918BF55460AF1010ABAF1200FE7
+:107C1000EDD1FF2DDFF82CA215D05AF825304B45B9
+:107C200011D1012F03D1844B5F5501230CE0032FA9
+:107C3000FBD1814B814802225A55F9F7EFF8804B6E
+:107C400043F82500F1E70023D8F804204A452FD84F
+:107C5000D8F808100A444A4594BF00220122794806
+:107C6000DFF8D4E14FF0010B002150F804CBCC45F4
+:107C700008D111F80EC0BCF1020F03D18D4218BF1C
+:107C80004FF0000B01312029EFD1012A18BF934694
+:107C9000FF2D75D0002B40F09B80BBF1010F60D110
+:107CA000654A012F535500F0B6804FF000083DE0C3
+:107CB0000022D4E7BBF1010F33D1314600F0E3FCE1
+:107CC0004FF003085C4AFF241F231146985C0228EA
+:107CD00018BF1C46013BF9D2FF2C00F09580BBF188
+:107CE000020F01F804B005D15448F9F797F8544B46
+:107CF00043F82400304600F0BBFC53494AF8240006
+:107D0000062202FB0414009B009A013B511D13F84C
+:107D1000012F04F8012B9942F9D175E0BBF1010F55
+:107D20007BD0984670E09846002B54D1BBF1010FF0
+:107D30006AD1631E711E033413F8012F01F8012F5D
+:107D4000A342F9D1032F0CBF4FF0020B4FF0010BF0
+:107D50004FF00108B6E7012352E04FF0010BD8467F
+:107D6000B0E7012FA1D131465AF82500019300F068
+:107D70008AFC314A019B012151554FF00308D3E79A
+:107D8000012FCBD1BBF1000F47D1D8F80820DFF885
+:107D9000A8C0013A4FF0FF30002A8BDBD8F804105E
+:107DA000574611440125002457F804EB8E4505D1B0
+:107DB00014F80CE0BEF1020F08BF00250134202C9E
+:107DC000F2D1012D04BF4FF0010B0846013AE3E761
+:107DD000012F1DD09846BBF1010F15D1611E013E48
+:107DE000033411F8013F06F8013F8C42F9D1032F0B
+:107DF000B1D11248F9F712F8114B43F825000223CC
+:107E00000D4A53554FF00108404603B0BDE8F08FCE
+:107E1000BBF1000FA7D0FF2D85D1631E711E033467
+:107E200013F8012F01F8012F9C42F9D1032F94D1AF
+:107E30004FF0020B8CE700BFE41B0020B062002073
+:107E4000641B0020241A0020A41A00202DE9F04F02
+:107E50000E468FB000250446032130460A958DF862
+:107E60002C5005F061FDA84240F3FE80A04F032195
+:107E70003A46304605F0ADFD3B7A0390012B3A4679
+:107E800040F0F2800DF1300807F12401434601353E
+:107E900011F8010B03F8010B062DF8D1137B0493A5
+:107EA000537B0593937B92F814C0577D907DD17DD1
+:107EB00006934FF0000ED37BDFF834B207938DF8B2
+:107EC00028C08DF829708DF82A008DF82B10F82223
+:107ED00075461BF802900BEB0203B9F1320F93F8D1
+:107EE00001A000F0B080B9F1350F00D19D78524467
+:107EF000B9F1FF0F02F1020240F0AD80BEF1000FB8
+:107F000007D08DF828C08DF829708DF82A008DF8DB
+:107F10002B10784A0023174619460133B3F5C87F62
+:107F200002F8011BF9D1049A3A71059A7A71022379
+:107F3000069A3B70BA710123079A7B70FA71062387
+:107F40006D4ABB70F97018F8011B02F8011B013B68
+:107F5000F9D18222632387F8ED20532287F8EC3091
+:107F600087F8EE2087F8EF300AAA009509AB0CA934
+:107F70002046FFF72BFE012D72D19DF824303B7473
+:107F80009DF825307B749DF82630BB749DF8273012
+:107F9000FB74352387F8F03087F8F150022387F817
+:107FA000F350042587F8F23087F8F4505349E0681D
+:107FB00000F069FB237D012B40F08180032387F8CB
+:107FC000F93087F8FA504E49206900F05CFBFF2534
+:107FD000637D012B0CD106237B557B1904225A703B
+:107FE000A91CA069394400F04EFB05F1060845467E
+:107FF00007EB0508002233237B5588F8022088F818
+:1080000003206822042388F805204FF00109362256
+:1080100088F8013088F8062088F8073088F804903E
+:1080200005F108013944206800F02DFBFF23314A97
+:1080300088F80C300321CDF8009005F10D0330468F
+:1080400005F091FD10E093F802C0DF7818795979B6
+:108050004FF0010E4BE7039B93423FF73AAF4DE7DA
+:10806000032D04D0072D2CD00FB0BDE8F08F68B3DE
+:108070009DF824303B749DF825307B749DF82630A4
+:10808000BB749DF82730FB74352387F8F030052248
+:1080900001234FF0040887F8F13087F8F33087F8B0
+:1080A000F22087F8F4801549E06800F0ECFA237DAF
+:1080B000012B04D187F8F95087F8FA8083E7F92576
+:1080C00086E70CA92046FFF765FDCDE7352306229C
+:1080D00087F8F03087F8F2200123FF2287F8F1308B
+:1080E00087F8F32029460093024AF423A7E700BF4C
+:1080F000941D0020041C0020201C0020F91C0020DE
+:10810000FF1C00202DE9F043394F3A4DDFF80C8178
+:10811000DFF80C91384C87B0002617F8013B002B94
+:1081200057D058F8260003A900F0ADFA17F8013C23
+:1081300032464946204609F041FC00F0E1FC9DF83A
+:108140000F3001939DF80E309DF80C202B490093C1
+:1081500020469DF80D3009F031FC00F0D1FC2A7862
+:108160002749204609F02AFC00F0CAFC6A78244915
+:10817000204609F023FC00F0C3FCAA7820492046E1
+:1081800009F01CFC00F0BCFCEA781D49204609F00F
+:1081900015FC00F0B5FC2A791949204609F00EFCBF
+:1081A00000F0AEFC6A791749204609F007FC00F0A0
+:1081B000A7FC1548F8F732FE144B154953F8262052
+:1081C000801A144AB0FBF2F2204609F0F7FB00F0E7
+:1081D00097FC0136202E05F106059ED10E49064872
+:1081E00009F0ECFB00F08CFC07B0BDE8F08300BFA9
+:1081F000E41B0020A41A00201463002064E301089B
+:1082000075E301087BE30108B0620020641B0020D5
+:1082100081E3010840420F0064EF0108241A0020A6
+:1082200052E30108F0B5424B93B005AA044603F1AE
+:108230001007154618685968164603C60833BB422E
+:108240003246F7D1186899889B79B3711B22306048
+:10825000B1800DF12B00002108F040FF04F11C005B
+:1082600000F006FA03AF064604F1260000F000FA1B
+:1082700004F115033A461B3413F8011F02F8011BE1
+:10828000A342F9D12B490B6883420CD02A4A1278B9
+:10829000012A0AD1294B1B68834204D8284A126854
+:1082A000134483420DD813B0F0BDCA684340134055
+:1082B0004A68824203D889680A448242F3D8002B74
+:1082C000F1D12A4639460023013311F8014B02F857
+:1082D000014B062BF8D11B4A0DF11A01144614F874
+:1082E00001CB01F801CB013BF9D10DF12A010623A5
+:1082F00012F8014B01F8014B013BF9D10CA900F038
+:10830000C2F906240DAB17F8012B03F8012B013C31
+:10831000F9D10DF13A01304600F0B5F90A48009460
+:1083200000682A232A46214605F01DFCBBE700BF52
+:108330008DE301088C630020F4C90020B86100209F
+:10834000B0610020A8610020F0C90020F0B5234BE7
+:1083500091B003AA054603F110071646186859683C
+:10836000144603C40833BB422246F7D118689988E3
+:108370009B792060A180A3711B2200210DF12300B5
+:1083800008F0ACFE164B0DF112011846062210F84B
+:10839000014B01F8014B013AF9D10DF122020624FB
+:1083A00013F8011B02F8011B013CF9D10D4B0AA97E
+:1083B000186800F068F90DF1320128460B94ADF809
+:1083C000304000F060F90848009400682A233246E3
+:1083D000214605F0C8FB11B0F0BD00BFBFE30108A6
+:1083E000A86100208C630020F0C90020F7B5044686
+:1083F0001C3000F03DF9054604F1260000F038F984
+:108400006A4604F1150311461B3413F8016F01F895
+:10841000016BA342F9D1254B1B68834224D1244828
+:1084200000231C461946064650F8047BAF4208BF9D
+:108430001C4603F1010308BF0121202BF4D10129BF
+:1084400018D11C49062303FB041112F8010B01F893
+:10845000010B013BF9D1184B02221A551748F8F7C6
+:10846000DDFC174B43F82400284603B0BDE8F0407C
+:1084700000F012B910491F23FF2408465F5C002F4B
+:1084800008BF1C46013BF9D21F2CEDDC094906232D
+:1084900003FB041112F8017B01F8017B013BF9D1C8
+:1084A0000223035546F82450D8E700BF8C63002010
+:1084B000241A0020A41A0020E41B0020B06200202F
+:1084C000641B002037B5027C437C03EB0223B3F529
+:1084D000006F044625D1027D437D03EB0223012B6F
+:1084E0001DD11C30019100F0C3F8054604F12600AF
+:1084F00000F0BEF8854214D00199204603B0BDE8D3
+:108500003040FFF78FBE084B1B7F13B1074B1B7822
+:108510003BB1204603B0BDE83040FFF767BF022BF8
+:10852000F1D003B030BD00BF8C630020F4C900203F
+:108530002DE9F0410C4D0D4E0D4FDFF83880002431
+:108540003046F8F76BFC15F8013B022B07D157F8C2
+:108550002430C01A404584BF032305F8013C013490
+:10856000202CEDD1BDE8F081E41B0020B06200209A
+:10857000641B0020002A751570B5344B1B7F012B3E
+:108580000E460446324920D1324B1B78EBB93248B3
+:108590004FF4967251F8045BB54203D11D5C022D75
+:1085A00008BF1A460133202BF4D11F2A4CDC2B4B79
+:1085B000062101FB0232631E053412F8011B03F889
+:1085C000011FA342F9D1012070BD23484FF49675D5
+:1085D000002351F8042BB24204D11A5C023A012A5A
+:1085E00098BF1D460133202BF3D11F2D29DC1C48D9
+:1085F000F8F714FC1B4B53F82530C01A1A4B98425D
+:108600000CD8164A062303FB0525631E053415F80E
+:10861000012B03F8012FA342F9D1D4E7134B984261
+:108620000FD80E4B062202FB0535631E053415F8E4
+:10863000012B03F8012FA342F9D13046FFF786FE44
+:10864000C1E73046FFF782FE0020BDE78C630020C3
+:10865000241A0020F4C90020E41B0020A41A0020E2
+:10866000B0620020641B0020FF94BA0AFF29751530
+:108670004378027803EB02228378C07803EB02236D
+:1086800000EB03207047030E0B70030C4B70030AC2
+:108690008B70C8707047000013B50B4C2368002B1B
+:1086A00010DD0A4B196881420AD10948FFF764FFBF
+:1086B00008482368064A00210091006805F053FA33
+:1086C0000023236002B010BD302600202C2600209D
+:1086D000EC1F0020F0C90020F0B50A4C0A4D002321
+:1086E000FA2154F8042B55F8047B8242DEB203D8F9
+:1086F0003A44824288BF31460133072BF1D1084604
+:10870000F0BD00BFBC610020D86100202DE9F04120
+:108710000E4629490546421E0123053012F8017F05
+:1087200011F8014BA74218BF00239042F6D1012B4C
+:108730001AD105F11E00FFF79BFF204A1278012A8B
+:10874000034615D11E4A126882420DD01D4A126896
+:10875000824209D81C4909680A44824204D9FFF7B9
+:10876000BBFFF92802461AD9BDE8F08192B914E09E
+:10877000002AF9D1124C22689A42F5D0E1685A4099
+:108780000A4061689942F1D8A06801449942EDD944
+:10879000002AE9D0237D012BE6D10C4B1A780C4B33
+:1087A0001B68022BE0D1A6F10E0105F10E00BDE819
+:1087B000F04102F09FB800BFA8610020F4C900207A
+:1087C0008C630020B8610020B06100203D030020D0
+:1087D000FCC90020836870B55A681B681268364E61
+:1087E0001A42ADF5C86D054633D1FF23012202219F
+:1087F00005F075F8012333600021284605F094F850
+:10880000041E29DD6A460021284605F047F92B4A57
+:108810001368013313609DF80E209DF80F308442D9
+:1088200003EB022340F60602D4BF00240124934246
+:108830000146346014D1224B1B781BB1214B1B78AD
+:10884000012B04D802390DF10200FFF73BFE012095
+:1088500003E03368012BCFD000200DF5C86D70BD4B
+:10886000B3F5006FF3D1164B1B78012B1DD1154BBF
+:108870001C78012C19D19DF8195008A8FFF7F8FEB3
+:10888000112D12D1104B1B6883420ED19DF826206A
+:108890009DF8273003EB022341F63C22934204D19A
+:1088A0002C390BA802F076FBD1E702390DF102005A
+:1088B000FFF72CFFCBE700BF34260020D463002055
+:1088C000F4C90020A16100208C6300202DE9F3474A
+:1088D00004461E30FFF7CCFE237C677C07EB0327A2
+:1088E0003E4B1E78012E4FF00008054661D13C49F1
+:1088F0000B68CA68434013403A4A1268824204D85F
+:10890000394800680244AA425FD833B940F2E553BF
+:108910009F4257DC4FF0000A24E000260B7D012B1C
+:1089200059D1D1F81090002E53D02846FFF7D4FE2D
+:10893000F92880468CBF4FF0000A4FF0010A66B953
+:10894000BAF1000F3ED002234246394604F10E0030
+:1089500002B0BDE8F04701F0CDBF40F2E5539F42C1
+:10896000EEDC4D46214A631D04F10B0112F8010BA8
+:1089700003F8010F8B42F9D1082300262373667395
+:1089800029462046FFF7F8FD07F10E0338B11848D5
+:10899000009600682246314605F0E5F8D0E7154A12
+:1089A00015481560154A214613601A4608F090FADA
+:1089B000C6E73EB90A4A5368AB4203D892681344EB
+:1089C000AB42A3D802B0BDE8F087002BA6D10026A9
+:1089D000ABE74D469AE7002EF9D1F3E7F4C9002042
+:1089E0008C630020B8610020B0610020A8610020E5
+:1089F000F0C900202C260020EC1F0020302600208B
+:108A0000BFF34F8F0549064BCA6802F4E062134377
+:108A1000CB60BFF34F8F00BFFDE700BF00ED00E06C
+:108A20000400FA0508B5064B1968012905D1054867
+:108A300008230068052204F052FFFFF7E1FF00BFA2
+:108A4000A0260020F0C9002037B5104D2C68012C5D
+:108A500019D10F4B69461868FFF715FE0D4808231A
+:108A600000680522214604F03AFF0B4A0B481460C7
+:108A70000B4A00232B60136008F0A6FB094B1B6810
+:108A8000986806F0F7FF03B030BD00BFA0260020B5
+:108A90008C630020F0C9002064020020F1E301088B
+:108AA000B0260020C804002070B50E4E0E4D34686C
+:108AB000012C15D10D48082300680522214604F039
+:108AC0000EFF0B4A0B4814600B4A002333601360FF
+:108AD00008F07AFB2B68BDE87040986806F0CABFC2
+:108AE0000648F5E7A0260020C8040020F0C90020B1
+:108AF00064020020F1E30108B026002012E401081E
+:108B00000F4B1B6807B573B10E4809F019FA002224
+:108B100003460D48009200680A4A012105F023F837
+:108B200003B05DF804FB0749084808F04DFB084B0B
+:108B30001B68986803B05DF804EB06F09BBF00BFAC
+:108B4000A026002014630020F0C9002036E40108AC
+:108B5000C8040020094A08B513686BB901211160E7
+:108B6000074A08491360084A0848136008F026FFBE
+:108B7000BDE80840FFF7C4BF08BD00BF6402002085
+:108B8000B026002066EF0108A42600201463002010
+:108B900008B5074B1B78012B07D10649064808F09A
+:108BA0000DFFFFF7ADFF002008BD0120FCE700BF6F
+:108BB000AB62002039E401081463002073B5054658
+:108BC000FFF7E6FF0128044649D101AA2549264EB0
+:108BD000284608F015FF2549254808F0EFFEFFF765
+:108BE0008FFF03F0EBFC3220F9F725F904F03AF996
+:108BF0002046F9F720F91F4B186800252A46294618
+:108C0000C56003F072F80A20F9F715F9347003F023
+:108C1000F5FE0A20F9F70FF9174B35701B7823B9C9
+:108C2000164B1C60164B7E221A703220F9F703F99E
+:108C3000462004F00DFC019A12490D4808F0BEFED2
+:108C4000FFF75EFF019B4FF47A705843019003F0E9
+:108C500059FB0D49064808F0B1FEFFF751FF02B07D
+:108C600070BD00BF21E70108AB62002065E4010888
+:108C700014630020DC620020F4C90020FCC900203D
+:108C80003D0300207EE4010866EF01082DE9F04372
+:108C90002DED028BB24AB34E5179B34D3378B348C0
+:108CA0009FEDB38AB34C8DB005EB83030591117929
+:108CB0000491D178039191780291517801911278C1
+:108CC000AD490092AD4A08F079FEFFF719FFAC4BB1
+:108CD000AC491A78A54808F071FEFFF711FFAA4BBE
+:108CE000AA491A68A14805EB820208F067FEFFF75F
+:108CF00007FFA74B1B8807EE903AF8EE677A87EEDE
+:108D0000887ADFEDA47A77EE277A17EE900A13F0CF
+:108D1000FDFD0B46A04909780391A049097802910D
+:108D20009F490246CDE90823B1F9003007EE903A99
+:108D3000F8EEE77AC7EE887A17EE900A13F0E6FDB0
+:108D4000DDE90823CDE900019649884808F036FEA0
+:108D5000FFF7D6FE944B954A1B78127894498348C6
+:108D600005EB830308F02AFEFFF7CAFE914B924AF7
+:108D70001B78127891497D4805EB830305EB82024D
+:108D800008F01CFEFFF7BCFE20680AA9FFF77BFC79
+:108D9000E0680BA9FFF777FC9DF82F3005939DF84D
+:108DA0002E3004939DF82D3003939DF82C300293C0
+:108DB0009DF82B3001939DF82A309DF8282080499A
+:108DC00000936A489DF8293008F0F8FDFFF798FEF7
+:108DD0003378012B40F097807A4F7B4B3A787B4970
+:108DE000624802EB82021A4408F0E8FDFFF788FEB1
+:108DF0003378012B40F087803B78012B19D93B78E1
+:108E0000022B40F0A280724B0AA91868FFF73BFCC6
+:108E10009DF82B3001939DF82A309DF828206D494C
+:108E2000009352489DF8293008F0C8FDFFF768FE0E
+:108E300069E0694B1B78002B40F08780DFF8A89130
+:108E4000DFF8B881D9F800000AA9FFF71CFCD8F8B0
+:108E50000030D9F8000018440BA90138FFF713FCC3
+:108E60009DF82F3006939DF82E3005939DF82D30F8
+:108E700004939DF82C300393D8F8003002939DF8AA
+:108E80002B3001939DF82A309DF8282053490093F8
+:108E900036489DF8293008F091FDFFF731FE206932
+:108EA0000AA9FFF7F0FB9DF82B30227D02939DF875
+:108EB0002A3001939DF829304949009305EB82023D
+:108EC0009DF82830294808F079FDFFF719FEA069C0
+:108ED0000AA9FFF7D8FB9DF82B30627D02939DF81D
+:108EE0002A3001939DF829303E49009305EB820218
+:108EF0009DF828301D4808F061FDFFF701FE33782A
+:108F0000012B3FF47CAF3378FBB9374B0AA91868C3
+:108F1000FFF7B9FB9DF82B3001939DF82A309DF89F
+:108F200028203249009311489DF8293008F046FD69
+:108F3000FFF7E6FD237F2E4A2E4912680B4805EB0A
+:108F4000830308F03BFDFFF7DBFD2B49074808F0E2
+:108F500035FDFFF7D5FD0DB0BDEC028BBDE8F0830C
+:108F6000A8610020F4C900204C02002014630020F6
+:108F700000007A44AC630020A2E401089C62002057
+:108F8000F4020020F5E401083803002006E501089A
+:108F90009E6100200000D24399620020240300203B
+:108FA0009C61002017E5010887620020AA6200206A
+:108FB00067E50108F5C900203C03002096E501089B
+:108FC000C1E50108A161002054020020F3E5010879
+:108FD000A4610020B2E60108AD62002006E60108A7
+:108FE0004EE6010885E60108B8610020D2E60108D6
+:108FF000B4610020ECE6010866EF0108B0610020D2
+:1090000010B58AB007AB019306AB0093134905ABCB
+:1090100004AA08F0F5FC049B8DF80830059B8DF838
+:109020000930069B8DF80A300428079B8DF80B3019
+:109030000CD102A8FFF71CFB09490446094808F0B7
+:10904000BDFCFFF75DFD20460AB010BD064905488E
+:1090500008F0B4FC0024FFF753FDF4E718E701081B
+:1090600024E701081463002030E7010810B50A491D
+:10907000044608F089FD60B10849204608F084FDE7
+:1090800030B10749074808F099FCFFF739FDFF2088
+:1090900010BD0120FCE700BF47E701084BE70108CE
+:1090A0004EE7010814630020F0B52DED028B0C464D
+:1090B0008FB00546002800F0E282002900F0DF8230
+:1090C000A44908F061FD0646E0B9A34D012003F074
+:1090D00009F92146284608F0C1FEA04A6E731179AD
+:1090E000527905F8012C012205F8021C1046314680
+:1090F00003F086FE9A492A469A4808F05FFCFFF77B
+:10910000FFFC0FE19849284608F03EFD064618BBD3
+:109110002046FFF7ABFF0128054600F2038101203E
+:1091200003F0E0F8914F0122314610463D7003F004
+:1091300067FE3B7873B18E4B1B7F012B0AD18D49A3
+:1091400001A808F08BFE8C4901AB2246854808F047
+:1091500035FCD4E78949F3E78949284608F014FD2E
+:1091600080B92046FFF782FF0128054600F2DA8029
+:10917000844B1B680BB1FFF797FC834B83491D7031
+:109180002246B9E78249284608F0FEFC50B920463D
+:10919000FFF76CFF012800F2C5807E4B7E491870F6
+:1091A0002246A9E77D49284608F0EEFC064698B914
+:1091B0002046FFF75BFF0128054600F2B38001203F
+:1091C00003F090F801226A4B314610465D7503F0BA
+:1091D00017FE734922468FE77249284608F0D4FCEF
+:1091E000064698B92046FFF741FF0128054600F2E0
+:1091F0009980012003F076F801225D4B314610463C
+:109200001D7503F0FDFD6849224675E7674928464C
+:1092100008F0BAFCA0BB6649204608F0B5FC40B98E
+:10922000644B00241C70012003F05CF801222146ED
+:109230000DE06149204608F0A7FC054678B90124F5
+:109240005C4B20461C7003F04DF822462946104620
+:1092500003F0D6FD5949434808F0B0FB4FE72046DC
+:10926000574908F091FC044618B9524B02221A7073
+:10927000D9E754493B4808F0A1FBFFF741FCE9E777
+:109280005149284608F080FC48B92046FFF7EEFE19
+:10929000012847D84D4B4E49187022462CE74D49BE
+:1092A000284608F071FCA8B92046FFF7DFFE012828
+:1092B00038D82F4B18772D4B1B784BB1012807D18D
+:1092C0002C4901A808F0CAFD434901AB22463DE7FD
+:1092D0002A49F6E74149284608F056FC064658B99F
+:1092E0002046FFF78DFE0190E0B1012002F0FAFF69
+:1092F0001F4B019A1A6010E03949284608F044FCD7
+:10930000064698B92046FFF77BFE019050B1012038
+:1093100002F0E8FF164B019ADA600122314610464E
+:1093200003F06EFD0FB0BDEC028BF0BD2D49284659
+:1093300008F02AFC0646002856D12046FFF760FEBA
+:1093400001900028EED0012002F0CCFF084B019ADA
+:109350001A61E2E773E701089C620020A86100201F
+:109360007CE701081463002097E70108F4C9002096
+:10937000AC630020A1E70108CBE7010888EB0108F6
+:10938000E2E70108A02600203C030020F0E70108E6
+:109390000CE80108F5C900201AE8010836E80108C0
+:1093A00041E801085AE801086BE801088EE8010865
+:1093B0004BE70108A161002099E8010866EF010868
+:1093C0009EE80108A1E80108B1E8010887620020D1
+:1093D000C3E80108E3E80108EFE801080CE9010827
+:1093E00015E901081DE90108A949284608F0CCFB48
+:1093F000064660B92046FFF703FE0190002891D091
+:10940000012002F06FFFA34B019A9A6185E7A24900
+:10941000284608F0B9FB064658B92046FFF7F0FD8C
+:10942000019000283FF47EAF012002F05BFF9B4BD0
+:109430005FE79B49284608F0A7FB064658B9204637
+:10944000FFF7DEFD019000283FF46CAF012002F031
+:1094500049FF944B4DE79449284608F095FBA0B985
+:10946000924901AA204608F0CBFA012800900AD1BF
+:10947000019B43B102F036FF8D4B019A1A60002127
+:109480000122104656E08B49E5E68B49284608F054
+:109490007BFB70B9854901AA204608F0B1FA012882
+:1094A0000090F0D1019B002BEDD002F01BFF834B0D
+:1094B000E3E78349284608F067FB00283FD12046B0
+:1094C000804901AA08F09CFA01280446009034D192
+:1094D000DDED017A9FED7C7AF4EEC77AF1EE10FAB9
+:1094E0002BD89FED7A8AF4EEC87AF1EE10FA24DDDB
+:1094F000002002F0F7FEDDED017A9FED757A77EE40
+:10950000C87A67EE877A17EE900A13F0FFF95EA328
+:10951000D3E9002313F09CF813F048FD07EE900AFE
+:109520006C4B0190FDEEE77A17EE902A21461A80E7
+:109530002246002003F064FC62E067498BE667493D
+:10954000284608F021FB064638BB20465D4901AAA3
+:1095500008F056FA012804460090EED1DDED017ABC
+:10956000B2EE047AF4EEC77AF1EE10FAE5D8BAEE6C
+:10957000047AF4EEC77AF1EE10FADEDB304602F040
+:10958000B1FEDDED017A9FED527A554B67EE877A99
+:10959000CDED017AFDEEE77AC6E75249284608F09C
+:1095A000F3FA0646D0B920464F496A4608F028FA31
+:1095B0000128044601900FD1009B7F2B0CDC304624
+:1095C00002F090FE494B009A1A70494B186802F05D
+:1095D00079FA22463146ACE746493CE646492846F8
+:1095E00008F0D2FA80B940496A46204608F008FAE5
+:1095F0000128019006D1009B072B03DC3F4A137022
+:109600003F4928E63F4926E63F49284608F0BCFA8C
+:10961000D8B935496A46204608F0F2F90128019088
+:1096200011D19DF80040A4F10B03032B03D9A4F141
+:109630001403042B07D8012002F054FE334B1C7096
+:10964000012211461DE7324905E63249284608F055
+:109650009BFA90B924496A46204608F0D1F90128BE
+:10966000019008D19DF800500F2D04D802F03AFE69
+:10967000294B1D70E4E72949EDE52949EBE5294926
+:10968000E9E500BFAFF30080333333333333D33FE7
+:109690002BE90108AC63002035E90108B86100201E
+:1096A0003EE90108A46100204DE901085CE90108D8
+:1096B000B061002060E9010875E90108B46100208B
+:1096C00085E901088FE901080000E1430000D24369
+:1096D00000007A449E61002092E90108ACE901088B
+:1096E0009C610020B7E9010821E70108240300205C
+:1096F000DC620020C0E90108E8E90108F40200206A
+:1097000024E70108F1E9010817EA0108996200203D
+:1097100022EA010842EA0108AA62002050EA010890
+:109720006DEA01088BEA01082DE9F04F564B95B020
+:1097300007AA03F12006154618685968144603C4A1
+:109740000833B3422246F7D11B8823801022002120
+:109750000DF13E0007F0C2FC4C4B1B680BB98DF8B5
+:109760001C304B4A4B4900924B484C4FDFF8648108
+:10977000DFF86491DFF864A1DFF864B12A4608F0ED
+:109780001DF9FFF7BDF9464B464D186805A9FEF7D0
+:109790007AFF9DF8173003939DF8163002939DF8D9
+:1097A000153001939DF8143000933F4B3F4A1B78CE
+:1097B0003F49394808F002F9FFF7A2F93D49364818
+:1097C00008F0FCF8FFF79CF93B48F7F727FB00246B
+:1097D000064699F8002057F8043B002A4DD1F31AA9
+:1097E000B3FBFAF318F8012B002A48D0092B46D80E
+:1097F000324B3349284803EB0413224608F0DEF8C5
+:10980000FFF77EF9286805A9FEF73DFF9DF81730A0
+:1098100001939DF816309DF814202A4900931E48A4
+:109820009DF8153008F0CAF8FFF76AF9264B28684A
+:1098300053F82430184405A90138FEF724FF9DF899
+:10984000173001939DF8163000939DF814209DF871
+:1098500015301E49104808F0B1F80134FFF750F9EF
+:10986000072C05F10405B4D119490B4808F0A6F8F6
+:10987000FFF746F915B0BDE8F08F0023B2E759466F
+:10988000054808F09BF8E8E7C1EF010838260020FA
+:109890008B620020B1EA010814630020646200209A
+:1098A0008C630020BC6100203D0300209C620020EE
+:1098B000D3EA010800EB0108B0620020F661002045
+:1098C0000BEB01081FEB0108D861002035EB010804
+:1098D00060ED010880620020F4C9002040420F00C2
+:1098E0004AEB0108000000002DE9F0472DED028B46
+:1098F000994B9A4A8EB0CDE90823A3F1CE53A3F534
+:1099000018531A3B0A93964B0B93964BD3F800804F
+:10991000B8F1000F01D18DF82080DFF8D0A2924D70
+:10992000DAF80000914C12F0DFFF87A3D3E900239F
+:1099300013F044F813F03AFB0646286812F0D4FFFF
+:1099400081A3D3E9002313F039F813F02FFB227819
+:1099500007460346A946002A40F0AA80844A1178A7
+:10996000844A52F8210037461E46834B1B78002B51
+:1099700040F0A08081498248434608AA08F01EF8BA
+:10998000FFF7BEF82378012B40F0C6807D4B1B7893
+:10999000022B40F0C1807C4B7C491A68784808F063
+:1099A0000DF8FFF7ADF8384612F0B0FF2578024603
+:1099B0000B46002D40F0BC80754F3968002900F03F
+:1099C000B78074499FED748ACDE906230B887349EB
+:1099D00007EE903A0B88FBEECC7AB6EE007AA7EE53
+:1099E000878A07EE903A9FED6E7AF8EE677AC7EEB7
+:1099F000877A17EE900A12F089FFCDE9020118EE7E
+:109A0000100A12F083FFDDE90623CDE90001654964
+:109A10005B4807F0D3FFFFF773F8634B3D601D60B1
+:109A2000304612F073FF0B4621780246002940F0C1
+:109A300086805E490968022940F081804C495C4873
+:109A400009789FED558ACDE9062330F81130594841
+:109A500007EE903A30F81130F8EE677AB6EE007AF9
+:109A6000A7EE878A07EE903A9FED4D7AF8EE677A77
+:109A7000C7EE877A17EE900A12F048FFCDE902018F
+:109A800018EE100A12F042FFDDE90623CDE90001CD
+:109A900049493B4807F092FFFFF732F80023CAF824
+:109AA0000030C9F800300EB0BDEC028BBDE8F08785
+:109AB00000205AE73D4B1D68032D0ED13F4B404A15
+:109AC0001B7840492E48023BC3EB03131344009319
+:109AD00008AA434607F072FF52E707EE900A3A4B96
+:109AE000F8EEE77A1B68049317EE900A12F00EFF67
+:109AF00017A3D3E9002312F061FF344B1622013D76
+:109B000002FB0535CDE90201009531491C48434669
+:109B100008AA07F053FF33E72E4B2F4A1B68009328
+:109B20002E4B12681B682E49154807F047FF38E78F
+:109B30002C49134807F042FFFEF7E2FF70E72A497D
+:109B40000F4807F03BFFA7E7FCA9F1D24D62703F39
+:109B5000333333333333C33F5B411B5B1B5B411BED
+:109B60001B5B41003826002010630020F4C9002050
+:109B70003D03002038840020AB62002089EB0108FF
+:109B800014630020A1610020E883002012EC01088A
+:109B9000CC630020E4620020000008C3E2620020E1
+:109BA0000000FA4373EC0108D0630020FCC90020D8
+:109BB000FE620020F0620020E2EC0108E06200207A
+:109BC000AA020020B4EB01080C6300206802002008
+:109BD000E4EB0108E4830020D4630020ECC90020FA
+:109BE00037EC0108ABEC01082DED0108E86200201C
+:109BF00008B5094B1B682BB1FFF776FE074A1368BF
+:109C000001331360064B1B682BB1FFF78DFD034A30
+:109C100013680133136008BDB026002038260020E9
+:109C2000A4260020F8B5834908F036FA8149054694
+:109C3000002008F031FA7F490646002008F02CFA8F
+:109C40000746002D00F0F3807B49284607F09CFF73
+:109C500000286BD17949304607F096FF00285AD189
+:109C6000774B1B7823B901221146104603F07EF88A
+:109C70007449754807F0A2FEFEF742FF01247349BC
+:109C8000284607F081FF18B93046FEF797FF0124F8
+:109C90006F49284607F078FF002849D16D4B6E4A7E
+:109CA00001241C60002313606C4A13606C4A13602B
+:109CB0006C4A1360FFF79CFF6B49284607F064FF6E
+:109CC00040B96A49304607F05FFF002837D1FEF7F8
+:109CD000DDFF01246649284607F056FF20B93946C2
+:109CE0003046FFF7E1F901246249284607F04CFFAE
+:109CF000002839D1604B5A4A01241C6000231360AC
+:109D0000584A1360FFF774FF5C49284607F03CFF90
+:109D100088BBFEF787FE5A49304607F035FF18B971
+:109D2000012002F089FAA3E75649A2E70024A6E73A
+:109D30005549284607F028FF0028AFD0BCE7534913
+:109D4000304607F021FF0028C3D05149304607F0C4
+:109D50001BFF10B9FEF7D6F9BBE74E493A4807F0AA
+:109D60002DFEFEF7CDFEB4E74B49284607F00CFF69
+:109D70000028BFD0C8E74949284607F005FF064636
+:109D800088B902F0AFFA04F05FFC012204463146C4
+:109D9000304603F035F8224641492B4807F00EFEC5
+:109DA000FEF7AEFE01243F49284607F0EDFE0646C9
+:109DB00090B93D49244807F001FEFEF7A1FE304668
+:109DC00002F090FA04F0C0F938491F4807F0F6FD98
+:109DD000FEF796FEFEF714FE3549284607F0D4FE3E
+:109DE00040B9344B344A3549174807F0E7FDFEF7D0
+:109DF00087FE01243249284607F0C6FE70B9FEF7F7
+:109E000053FE3049284607F0BFFE90B92E490E4850
+:109E100007F0D4FDBDE8F840FEF772BE002CF0D18B
+:109E20002A49094807F0CAFDFEF76AFEE9E7284912
+:109E3000EDE7F8BD28F0010874ED010860EE0108B7
+:109E4000AB62002024E70108146300209DED0108A7
+:109E5000A5ED0108B0260020E86200201063002074
+:109E60003826002064020020ACED0108B4ED0108A2
+:109E7000B3E10108ECED0108A4260020F2ED010891
+:109E80007AED01087EED010837E40108BBED010819
+:109E9000C2ED0108CBED0108F0ED0108F9ED010874
+:109EA000FEED010816EE010827EE010842EE01085A
+:109EB0005BEE010863EE010868EE010873EE01082D
+:109EC00098EE0108B6EE0108BBEE01089DEE010810
+:109ED00066EF01082DE9F04F0522B5B003210546D4
+:109EE00003F0DDFC1728DFF8AC829A4F064640D11C
+:109EF00098F80030172B3AD004230093052202ABC8
+:109F00000C21284603F014FC9DF80B309DF8092025
+:109F10009DF80810009390489DF80A3007F054F916
+:109F20008E4B1B68986805F0A5FD8D4A8D4B8E49B8
+:109F30000024CDE91B231BA80323ADF8743007F0E0
+:109F4000FFFD1B231BAA01212846009403F00BFEF2
+:109F5000864A87481460874A01233B601360864B1A
+:109F60001C60864B1C60F6F759FF854B1860002477
+:109F700026E01C280BD0002800F085801328F6D19D
+:109F8000022305220121284603F0A9FCEFE7052260
+:109F900010230121284603F0A2FC7A4807F014F9A7
+:109FA0006E4B1B68986805F065FD704B00241C60C3
+:109FB000704B3C6001221A606F4B1C606F4B1C6041
+:109FC0003B6888F80060002B00F0B980012128462A
+:109FD00003F0AAFC6A4E80466548F6F71FFF326818
+:109FE000801A694A904217D96848082300680522F8
+:109FF000012103F074FC5F4A6248012111605E4A4E
+:10A00000002313605D4A3B60136007F0DDF8534B9B
+:10A010001B68986805F02EFDB8F1000F40F38F80A3
+:10A020005348DFF85091DFF868A1F6F7F7FE434692
+:10A03000306002AA0121284603F092FC34AB03EB06
+:10A0400008020024494E02F8C84CA34634AB5B44D6
+:10A050000BF1010713F8C83CA3F120025E2A1AD8BD
+:10A060003268612A0BDCD9F8001041B134A92144CF
+:10A070000AF80230013201F8643C0134326047458D
+:10A0800053DABB46E2E7012305221946284603F0CE
+:10A0900026FC012494E7FF2B0AD134AB1F4417F8A8
+:10A0A000C83CF42B01D1FEF755FD0BF10307E6E7A1
+:10A0B000082B01D07F2B14D1D9F80020002A42D0E0
+:10A0C0003368002BDBDD013B336034AB23440822D3
+:10A0D000202103F8642C03F8631C03F8622C03347A
+:10A0E000CDE70D2B31D1D9F80020002AC7D034AAF2
+:10A0F00022444FF0000B02F8643C0A2302F8633C50
+:10A1000033680AF803B0013333601BAAA31C012192
+:10A110002846CDF800B003F026FD31681C48FFF753
+:10A1200081FD5C46C6F800B0A9E73CB1002300936E
+:10A130001BAA23460121284603F015FD01242046D1
+:10A1400035B0BDE8F08F0D2B99D0032B97D1FEF7DA
+:10A1500001FD94E7A02600206EEF0108C80400204E
+:10A16000FFFB01FFFD03FFFBAEEF0108AC26002063
+:10A17000B062002064020020B0260020A426002047
+:10A18000A8260020F1E3010800A3E111F0C9002096
+:10A190003C260020B4260020F8B52B4D2846F6F7C3
+:10A1A0007EFC2E46D8B1286E06F0B8FA274B1F6801
+:10A1B000A7B9C4B2A4F120035E2B11D8244E336892
+:10A1C000612B0BDC234B1B6843B1296E204607F043
+:10A1D0003BF83368204AD454013333600120F8BD82
+:10A1E000082C01D07F2C15D11A4B1B682BB3184AB1
+:10A1F0001368002BF2DD013B316E1360082007F07D
+:10A2000023F8316E202007F01FF8316E082007F088
+:10A210001BF8E3E70D2C12D10E4B1B68002BDDD091
+:10A220000B4C0E4806F0D0FF21680B484754013113
+:10A230002160FFF7F7FC2760D0E70D2CCED0032C70
+:10A24000CCD1FEF787FCC9E700CA0020A026002079
+:10A25000AC260020640200203C26002086EB01088A
+:10A26000F7B51E4B1E491B680A68934234D91D4C32
+:10A270001D480023A64606469D18C5F30C0501336C
+:10A28000455D04F8015B042BF6D1131DC3F30C03E9
+:10A29000164DC35C8EF8043002F1050C03F15A0729
+:10A2A000002000EB0C04C4F30C040130345D05F80D
+:10A2B000014B8742F5DC5F321A440A600C480022E9
+:10A2C00000925F33074A0068042103F04CFC094800
+:10A2D000F6F7A4FD084B186003B0F0BDE083002042
+:10A2E000D863002037270020E06300203C270020AF
+:10A2F000F0C90020B0620020F8C900202DE9F04F1D
+:10A300000323074692FBF3F303EB4300824218BF9B
+:10A31000013387B05A1C90005C0002EB4202A51C7E
+:10A320000392CA18029504927D1E0092C7F101079C
+:10A33000002201904E1E9446964693460597059F2F
+:10A340002F44BB421CDD15F801AF009815F80390AF
+:10A3500015F8048006F801AF00F8019F00900298FC
+:10A360008AEA090706F80080039888EA0707375445
+:10A370008BEA0A0B8EEA090E8CEA080C7A40DEE7BB
+:10A3800003EB430304980C440B4480F800B084F8BA
+:10A3900001E083F802C0019B1944184601F8012C22
+:10A3A00007B0BDE8F08F00002DE9F04F85B000291F
+:10A3B00003927F4ADFF8FCC1D2F800A000910F465B
+:10A3C000B8BFCF1CBB1003EB43020AEBA707002466
+:10A3D000029207EB430201924FEA430E03EB070B95
+:10A3E000A0462546264622469C4222DA0AEB04096C
+:10A3F000C9F30C0901991CF8099082EA090207EBDC
+:10A400000409C9F30C091CF8099086EA09060BEB4C
+:10A410000409C9F30C091CF8099085EA090501EB48
+:10A420000409C9F30C0901341CF8099088EA0908E9
+:10A43000DAE7141E18BF012406B1013405B1013456
+:10A44000B8F1000F00D001340399012C0C6000F228
+:10A45000A4805C1E04EB440C7AB9DFF85491DFF859
+:10A460005481D9F80070A2422CDA1744C7F30C07C4
+:10A4700018F8077087540132F3E7DFF834B1DFF8DA
+:10A4800034910027A742DBF800201BDA1A4407EBBF
+:10A490000208C8F30C081A4419F808A007EB0208D0
+:10A4A000C8F30C081A443A4419F80880C2F30C02A5
+:10A4B0008AEA080819F802A088EA0A0800F8078062
+:10A4C0000137DFE79F1E26B3DFF8E4B0DFF8E49042
+:10A4D000C6190027A742DBF800202DDA07EB020897
+:10A4E000C8F30C08724419F808A007EB0208C8F377
+:10A4F0000C081A443A4419F80880C2F30C028AEA9C
+:10A50000080819F802A088EA0A0806F8018F01373E
+:10A51000E0E7DFF89C90DFF89C800744A642D9F87A
+:10A52000002009DA1A443244C2F30C02013618F84A
+:10A53000022007F8012FF1E7AEF102021C4E104491
+:10A54000F5B1DFF870E00025A542326827DAAF18D0
+:10A55000C7F30C0702991EF807809F182F440A447E
+:10A560002A44C7F30C07C2F30C021EF807701EF84A
+:10A57000022088EA07077A4000F8012B0135E3E75B
+:10A580000C4A3368A5420ADA73442B44C3F30C0324
+:10A590000135D35C00F8013BF3E74FF0000C044AAF
+:10A5A0000099136860461944116005B0BDE8F08F4A
+:10A5B000D8630020E0630020032390FBF3F303EB58
+:10A5C0004302801A0028C8BF0133581C800070471E
+:10A5D000F8B51F4C1F4E05462068802900F07F000B
+:10A5E00006EBC0100ADC8022294606F071FC2368C5
+:10A5F00001332360184B22681A60F8BDB1F5807FE3
+:10A6000005F180074FF0800229460BDC06F060FC64
+:10A61000206801302060802200F07F00394606EB80
+:10A62000C010E2E706F054FC20680130206000F022
+:10A630007F008022394606EBC01006F049FC2068F6
+:10A6400001302060802200F07F0005F58071E6E790
+:10A65000E4C90020E0890020E8C90020F7B51D46C4
+:10A6600043680E46D9681B680B600E49130ACA700E
+:10A67000120C8B704A70044600680B4B076804226A
+:10A680000092BF68B8472068074B0268009597683A
+:10A6900031462A46B84763689A681B68136003B05E
+:10A6A000F0BD00BFCE020020B52600202DE9F84302
+:10A6B000354CDFF8E0802268344FC2F3090280296C
+:10A6C00005460E46D8F800004FEAC2120FDC0B46D2
+:10A6D0002946FFF7C3FF23686978C3F30902B95419
+:10A6E000013323602A4B22681A60BDE8F883B6F56F
+:10A6F000807F05F180094FF08003294617DCFFF7C2
+:10A70000ADFF22686978D8F80000C2F3090301326E
+:10A710002260C2F30902F954D201A6F1800349462E
+:10A72000FFF79CFF23680021C3F30902D7E7FFF777
+:10A7300095FF22686978D8F80000C2F30903013256
+:10A740002260C2F30902F954D20149468023FFF77F
+:10A7500085FF2268D8F80000C2F3090301324FF0E8
+:10A7600000092260C2F3090207F80390D201A6F59E
+:10A77000807305F58071FFF771FF2368C3F3090249
+:10A7800007F80290ACE700BFD8850020E0850020E4
+:10A79000DC85002030840020034B1B68012B01D195
+:10A7A000FFF784BFFFF714BF38030020044B1A687B
+:10A7B000044B02F07F0203EBC21358785B30704702
+:10A7C000E0C90020E08900202DE9F0411F4C204E17
+:10A7D000216801F07F0106EBC11105464F785C3717
+:10A7E000802F08DC802206F073FB2368013323608E
+:10A7F0003846BDE8F081B7F5807F00F180084FF062
+:10A8000080020BDC06F064FB21680131216001F05D
+:10A810007F01802206EBC1114046E4E706F058FBB9
+:10A8200021680131216001F07F01802206EBC11116
+:10A83000404606F04DFB21680131216001F07F01A7
+:10A84000802206EBC11105F58070CCE7E0C900203D
+:10A85000E0890020094A0A4B12681868094B012A4E
+:10A860001B6805D1084A12681044C01A074B1B68C0
+:10A87000C01A0323B0FBF3F0704700BF3803002079
+:10A88000E8C90020E0C90020DC850020D485002034
+:10A89000064B074A1B68126801280CBF6E207820FF
+:10A8A0009B1A9842ACBF002001207047E4C90020E9
+:10A8B000E0C90020084B094A1B6812680128A3EB75
+:10A8C000020340F2B63018BF4FF47A709842ACBF22
+:10A8D00000200120704700BFD8850020D4850020CB
+:10A8E000034B1B68012B01D1FFF7E4BFFFF7D0BF7B
+:10A8F000380300202DE9F04FD3B01746029340F201
+:10A90000E553994201906ADC0120FFF7E9FF044614
+:10A91000002864D1364ADFF8EC8013680D463F29E1
+:10A9200019441160334A136803F10103B8BF3F258E
+:10A9300013608246FC2D5FFA8AF253DC3F2D2E46CF
+:10A94000AB46B8BF3F2608212B48DFF8BC90CDE9C5
+:10A950000412F6F763FAF31C000C88F8000018469E
+:10A960000393FFF729FE593820EAE07088F80100C8
+:10A970000120059A88F8020099F800000499029BCA
+:10A980008DF81D3000F00F0002F0070202EB0012FC
+:10A9900011441A48019B8DF81E1007F07F02191907
+:10A9A000825C3A448DF81C200DF11F00324606F0FF
+:10A9B0008FFA039B12491A4607A8FFF79FFCA5EBE5
+:10A9C0000B05C11C0F48FFF7E7FE002D34440AF1C8
+:10A9D000010AAFDC99F80030013389F8003053B038
+:10A9E000BDE8F08F4FF0FC0B00215E46ACE700BFE6
+:10A9F00010630020ECC90020B06200204404002055
+:10AA0000A22800209F2800201F2A00202DE9F341C2
+:10AA10001D464368114F0E46D9681B680B601049EC
+:10AA2000130ACA70120C4A708B7004460068042224
+:10AA300003680092D3F808803B46C047206803684B
+:10AA40000095D3F808802A4633463946C0476368E4
+:10AA50009A681B68136002B0BDE8F081B52600203B
+:10AA6000C80200202DE9F74F2F48304C304F314DB0
+:10AA7000DFF8D490F6F7D2F9030C22682E4901933F
+:10AA80003B682868D31A0A684FF0000A121A4FF080
+:10AA900001088B46002A43DD092B41DC01262A6888
+:10AAA00021682648C2F3090201F07F010068802373
+:10AAB000D20109EBC111FFF7A9FF012E12D12368C2
+:10AAC00003F07F03DA0109EBC31319F802A05B78E6
+:10AAD0005C33802B22DDB3F5807FD4BF4FF00208BA
+:10AAE0004FF003082A689DF80430511C144A29606D
+:10AAF0001268A3EB0A039342B8BF236806F101066C
+:10AB0000BCBF01332360B045C9DA0E4A2368136025
+:10AB10003A689B1ADBF80020521ABBE7B046E1E71F
+:10AB200003B0BDE8F08F00BFB0620020E4C9002090
+:10AB3000E0C90020D4850020D88500203084002082
+:10AB40000C030020E8C90020E089002037B5124A34
+:10AB5000124C4FF0FF33CDE900232068042340F668
+:10AB600029126946FFF77AFD04230DEB03012068E3
+:10AB700040F62912FFF74AFF01AA6B460120002187
+:10AB800012F8015B13F8014B0131A54218BF0020F8
+:10AB90000429F5D103B030BD3C4AF31230840020C3
+:10ABA000064A00231360064A1360064A1360064AE9
+:10ABB0001360064A1360064A13607047E4C9002018
+:10ABC000E0C90020E8C90020D8850020D4850020F5
+:10ABD000DC850020000000002DE9F8431E463E4BB6
+:10ABE0001B781546002B3FD000293BD13B4B1B5C0B
+:10ABF000C3B300F07F04062C34D8394F37F8140063
+:10AC000011F072FE32A3D3E9002311F0D7FE804683
+:10AC10001A206843894611F067FE02460B464046FB
+:10AC2000494611F015FD12F0A1F92E4D27F8140038
+:10AC300035F8140011F058FE25A3D3E9002311F0D4
+:10AC4000BDFE804640F2E2407043894611F03CFE72
+:10AC500002460B464046494611F0FAFC12F086F9CE
+:10AC600025F81400BDE8F8830029FBD01E4C1F4FC7
+:10AC7000208811F039FE16A3D3E9002311F09EFEBF
+:10AC800080461A206843894611F02EFE02460B4684
+:10AC90004046494611F0DCFC12F068F92080388803
+:10ACA00011F022FE0AA3D3E9002311F087FE044627
+:10ACB00040F2E24070430D4611F006FE02460B469C
+:10ACC0002046294611F0C4FC12F050F93880C9E73B
+:10ACD000CDCCCCCCCCCCEC3FF4C90020440300203C
+:10ACE000FE620020F0620020E4620020E2620020A8
+:10ACF0002DE9F04F904B914E1A6833682DED028B81
+:10AD00009A4285B040F213818D48F6F787F8326891
+:10AD10000446C2F30C038B48C15C531CC3F30C0301
+:10AD2000C75C931CC3F30C03C55C2D0405EB07251E
+:10AD3000D31C0D44511DC3F30C03C1F30C0110F8D7
+:10AD400003B010F80180131D911D0732C2F30C02ED
+:10AD50003160825C7C4EC1F30C0108EE102AC3F313
+:10AD60000C037A4AC35C10F801901178009208F045
+:10AD7000400A593300297DD04A464146284601936E
+:10AD800002F0AEF83268019BA11A714A126802F50E
+:10AD9000742202F510729142074606D914203460DD
+:10ADA000F7F749F801F048FD019B3460694E1946F8
+:10ADB00003AA3046FFF7F8FA039B04465A46514669
+:10ADC0004846FFF709FF002C40F39080009B96F85F
+:10ADD00000B01A780BF07F0B002A40F091805E4B98
+:10ADE0001B785B4503D0BBF17F0F40F09580BAF133
+:10ADF000000F00F091804FF0000B7378022B5DD1B3
+:10AE0000BBF1060F6BD8B678DFF884A1534F06F07C
+:10AE10000803310916F00706A4F1030400932BD1AF
+:10AE20004F4B03F80B104F4B4F494FF4C86022466D
+:10AE300000FB0B3006F04CF84AF82B40009B07F85B
+:10AE40000B60002B68D05AF82B10002964DD474BAB
+:10AE50004FF4C8600E3100FB0B30FDF737FD444A5C
+:10AE60005AF82B3011680B441360424A13680133BF
+:10AE7000136051E0404F98E717F80B3001339E42C2
+:10AE800018D1374B13F80B308B4213D15AF82B30B3
+:10AE9000354903F10E004FF4C86303FB0B0333483D
+:10AEA0002246184406F014F85AF82B0002194AF802
+:10AEB0002B20C3E700234AF82B30BFE71E2B05D118
+:10AEC00024483A46214604F027FB25E01F2B05D1F4
+:10AED0002AB92048214602F0DBFA1DE0E3B1274BF6
+:10AEE0001B68CBB1264806F06FF915E0234B1B68B1
+:10AEF00093B12448F7E7BBF17E0F3FF47EAF0BE040
+:10AF0000BAF1000F08D1BBF1060FF4D81E4B13F8AD
+:10AF10000B30002B7FF471AF18EE102A2B464946F8
+:10AF2000404602F00FFB194A13680133136005B065
+:10AF3000BDEC028BBDE8F08FE0830020D8630020D9
+:10AF4000B0620020E0630020F8C90020F4C90020AE
+:10AF500028030020372700203D030020035600204F
+:10AF6000FC5500204A2A00203A2700203C2A0020D5
+:10AF7000E8620020E4830020A086010098CA002037
+:10AF8000F3EF010802F00108806200200C56002057
+:10AF9000202A002010B50A1D0C460146064805F07F
+:10AFA00097FF064B00221A60054B1C60054BBDE85D
+:10AFB00010401868FFF79CBEE0630020D8630020B3
+:10AFC000E0830020F0C90020BFF34F8F0549064BF6
+:10AFD000CA6802F4E0621343CB60BFF34F8F00BF37
+:10AFE000FDE700BF00ED00E00400FA0510B50446DF
+:10AFF000F5F740FF2046074B40F8283B1022002180
+:10B0000006F06CF8012384F83830034B23602046A7
+:10B0100010BD00BF34D5010848D5010830B54368DC
+:10B020000446D8681B68036020688BB003680092F0
+:10B030009D6802ABA84763689A681B68136001208B
+:10B04000F6F7DAFE0BB030BD2DE9F04788B01F46A9
+:10B0500044238DF814304368044615460068DA68C6
+:10B060001B681360022603680096D3F8088089469F
+:10B0700002AB324605A9C0474FF000089DF80930E1
+:10B08000FF2B18D0B84516DA63689A681B681360FE
+:10B090001420F6F7B1FE63682068DA681B68136055
+:10B0A00003680096D3F808A0022202AB05A9D04796
+:10B0B00008F10108E2E7002D07DD2068036800952C
+:10B0C0009E682A464B4605A9B04763689A681B6884
+:10B0D00013600120F6F790FEB845ACBF00200120B8
+:10B0E00008B0BDE8F08700002DE9F043DFF8C49117
+:10B0F00095B004460F46002317F803805E1CB8F194
+:10B10000000F00F0D2804246B9192046FFF786FFB3
+:10B1100047F23053002249462046FFF795FF051EAF
+:10B1200018BF012508EB0603B8F1000F01D0012D6F
+:10B13000E2D05F4E0520F6F77EFE3068B3880090BF
+:10B140000027052269462046ADF80430CDF8067088
+:10B15000FFF764FF57494FF448733A462046FFF71C
+:10B1600073FFB8424FF0050008BF3D46F6F763FE97
+:10B170003346062253F80A0F03909B798DF812305C
+:10B1800003A945F601132046ADF81030ADF8137051
+:10B190008DF81570FFF742FF46494FF448733A4661
+:10B1A0002046FFF751FFB8424FF0050008BF3D466B
+:10B1B000F6F741FE3346062253F8140F06909B79AA
+:10B1C0008DF81E3006A945F65A232046ADF81C30EE
+:10B1D000ADF81F708DF82170FFF720FF4FF4487312
+:10B1E0003A4634492046FFF72FFFB8424FF005009A
+:10B1F00008BF3D46F6F71FFE06F11E030FAA2E36C6
+:10B2000018685968174603C70833B3423A46F7D15E
+:10B210001B783B70284FBB88ADF83430274B38681B
+:10B220001B780C9014AA00261344ADF84D608DF8DD
+:10B230004F6013F8143C8DF834300CA920460522D9
+:10B24000CDF83660ADF83A60FFF7E8FE32461949AE
+:10B250004FF448732046FFF7F7FE0520F6F7EBFDA5
+:10B2600057F80C0F0990BB88ADF82830144BCDF877
+:10B270002A601B7809A903F07F03204605228DF878
+:10B280002830FFF7CBFE0B494FF448733246204677
+:10B29000FFF7DAFEB0424FF0050008BF3546F6F77B
+:10B2A000CAFD284615B0BDE8F08301253AE700BF86
+:10B2B0004FF001086C58002081F00108AA620020BC
+:10B2C0002403002010B5ADF59D6D0446234940F2DE
+:10B2D000CC4201A805F0FCFD162200210DF59A6074
+:10B2E00005F0FCFE1E4B1F4A1A601F4B47F67032DA
+:10B2F0001A601E4B43F29C121A601D4B4FF496725B
+:10B300001A601C4B40F214521A601B4B4FF4FA6245
+:10B310001A601A4B40F66E221A60194B40F6A7626B
+:10B320001A60184B50221A60174B14221A70174BD0
+:10B3300010221A70164B78221A60164B164A1A60A1
+:10B34000164B174A1A60174B022201A920461A60B1
+:10B35000FFF7CAFE0DF59D6D10BD00BF97F0010807
+:10B36000FC020020808B0800000300203003002036
+:10B370000403002008030020F8020020200300201E
+:10B380001C03002014030020AE610020AF610020E8
+:10B390000C03002028030020008793032C030020C7
+:10B3A000809698003403002010B5ADF59D6D0446DD
+:10B3B000234940F2CC4201A805F08AFD1622002163
+:10B3C0000DF59A6005F08AFE1E4B1F4A1A601F4B4E
+:10B3D00047F22A621A601E4B42F6B4521A601D4BA5
+:10B3E0004FF496721A601C4B40F214521A601B4BB9
+:10B3F0004FF4FA621A601A4B40F272621A60194BEB
+:10B4000040F6A9121A60184B50221A60174B1922E5
+:10B410001A70174B10221A70164B78221A60164BAE
+:10B42000164A1A60164B174A1A60174B022201A9D6
+:10B4300020461A60FFF758FE0DF59D6D10BD00BF48
+:10B4400079F50108FC020020A83108000003002063
+:10B45000300300200403002008030020F80200202D
+:10B46000200300201C03002014030020AE610020F4
+:10B47000AF6100200C030020280300200087930305
+:10B480002C030020809698003403002010B5ADF501
+:10B490009D6D0446234940F2CC4201A805F018FDF9
+:10B4A000162200210DF59A6005F018FE1E4B1F4A6A
+:10B4B0001A601F4B43F6AC721A601E4B41F68A327B
+:10B4C0001A601D4B4FF496721A601C4B40F21452D6
+:10B4D0001A601B4B4FF4FA621A601A4B40F20E626C
+:10B4E0001A60194B40F642121A60184B1E221A605D
+:10B4F000174B19221A70174B10221A70164B5A222A
+:10B500001A60164B164A1A60164B174A1A60174BE8
+:10B51000012201A920461A60FFF7E6FD0DF59D6D99
+:10B5200010BD00BF5BFA0108FC020020647E04002D
+:10B530000003002030030020040300200803002043
+:10B54000F8020020200300201C0300201403002028
+:10B55000AE610020AF6100200C0300202803002012
+:10B56000008793032C030020404B4C003403002041
+:10B5700010B5ADF59D6D0446234940F2CC4201A8BB
+:10B5800005F0A6FC162200210DF59A6005F0A6FD37
+:10B590001E4B1F4A1A601F4B44F294321A601E4B16
+:10B5A00041F6EE321A601D4B4FF496721A601C4B36
+:10B5B00040F214521A601B4B4FF4FA621A601A4B95
+:10B5C00040F206421A60194B40F2E5621A60184BCD
+:10B5D0002D221A60174B20221A70174B10221A7056
+:10B5E000164B64221A60164B164A1A60164B174AFD
+:10B5F0001A60174B012201A920461A60FFF774FD5B
+:10B600000DF59D6D10BD00BF3DFF0108FC0200203F
+:10B61000C0C2040000030020300300200403002007
+:10B6200008030020F8020020200300201C03002053
+:10B6300014030020AE610020AF6100200C03002045
+:10B6400028030020008793032C030020404B4C006C
+:10B650003403002010B5ADF59D6D0446234940F23A
+:10B66000CC4201A805F034FC162200210DF59A60A9
+:10B6700005F034FD1E4B1F4A1A601F4B42F2085260
+:10B680001A601E4B41F2EA021A601D4B4FF496728B
+:10B690001A601C4B40F214521A601B4B4FF4FA62B2
+:10B6A0001A601A4B40F27A321A60194B40F2AC62BF
+:10B6B0001A60184B17221A60174B20221A70174B6A
+:10B6C00010221A70164B3C221A60164B164A1A604A
+:10B6D000164B174A1A60174B012201A920461A601F
+:10B6E000FFF702FD0DF59D6D10BD00BF1F040208A0
+:10B6F000FC02002080AF0200000300203003002085
+:10B700000403002008030020F8020020200300208A
+:10B710001C03002014030020AE610020AF61002054
+:10B720000C03002028030020005A62022C03002092
+:10B73000404B4C003403002010B5ADF59D6D044620
+:10B74000234940F2CC4201A805F0C2FB1622002199
+:10B750000DF59A6005F0C2FC1E4B1F4A1A601F4B84
+:10B7600042F6E0121A601E4B41F2BC121A601D4BE9
+:10B770004FF496721A601C4B40F214521A601B4B25
+:10B780004FF4FA621A601A4B40F24E221A60194BBB
+:10B790004FF4AF621A60184B1B221A60174B2A2213
+:10B7A0001A70174B10221A70164B3C221A60164B57
+:10B7B000164A1A60164B174A1A60174B012201A944
+:10B7C00020461A60FFF790FC0DF59D6D10BD00BF7F
+:10B7D00001090208FC020020880103000003002088
+:10B7E000300300200403002008030020F80200209A
+:10B7F000200300201C03002014030020AE61002061
+:10B80000AF6100200C03002028030020005A6202D0
+:10B810002C030020404B4C003403002010B5ADF544
+:10B820009D6D0446234940F2CC4201A805F050FB2F
+:10B83000162200210DF59A6005F050FC1E4B1F4AA0
+:10B840001A601F4B41F2CA721A601E4B40F6B832A2
+:10B850001A601D4B4FF496721A601C4B40F2145242
+:10B860001A601B4B4FF4FA621A601A4B40F23A22EC
+:10B870001A60194B40F255521A60184B0E221A608A
+:10B88000174B2A221A70174B10221A70164B1E22C1
+:10B890001A60164B164A1A60164B174A1A60174B55
+:10B8A000012201A920461A60FFF71EFC0DF59D6DCF
+:10B8B00010BD00BFE30D0208FC02002008C9010012
+:10B8C00000030020300300200403002008030020B0
+:10B8D000F8020020200300201C0300201403002095
+:10B8E000AE610020AF6100200C030020280300207F
+:10B8F00080C3C9012C030020404B4C0034030020BE
+:10B9000010B5ADF59D6D0446224940F2CC4201A828
+:10B9100005F0DEFA162200210DF59A6005F0DEFB37
+:10B920001D4B1E4A1A601E4B41F6B8221A601D4B71
+:10B9300040F63A421A601C4B4FF496721A601B4B49
+:10B9400040F214521A601A4B4FF4FA621A60194B03
+:10B950004FF4C8721A60184B40F2B6421A60174A88
+:10B9600010231360164A3C211170164A1370164BAF
+:10B970001E221A60154B164A1A60164B164A1A6098
+:10B98000164B012201A920461A60FFF7ADFB0DF509
+:10B990009D6D10BDC5120208FC020020D0FB010005
+:10B9A00000030020300300200403002008030020CF
+:10B9B000F8020020200300201C03002014030020B4
+:10B9C000AE610020AF6100200C030020280300209E
+:10B9D00080C3C9012C030020404B4C0034030020DD
+:10B9E00010B5ADF59D6D0446234940F2CC4201A847
+:10B9F00005F06EFA162200210DF59A6005F06EFB37
+:10BA00001E4B1F4A1A601F4B40F6DC721A601E4B19
+:10BA100040F6A2021A601D4B4FF496721A601C4B3E
+:10BA200040F214521A601B4B4FF4FA621A601A4B20
+:10BA30004FF4C3721A60194B40F2A4421A60184BBB
+:10BA400008221A60174B3C221A70174B10221A70EA
+:10BA5000164B1E221A60164B164A1A60164B174ACE
+:10BA60001A60174B012201A920461A60FFF73CFB20
+:10BA70000DF59D6D10BD00BFA7170208FC02002048
+:10BA8000943D010000030020300300200403002047
+:10BA900008030020F8020020200300201C030020DF
+:10BAA00014030020AE610020AF6100200C030020D1
+:10BAB0002803002080C3C9012C030020404B4C0008
+:10BAC0003403002030B5114B044653F83E0F85B0C7
+:10BAD0009B88ADF808300E4B01901B78002503F0D1
+:10BAE0007F0301A9204605228DF80830CDF80A50C1
+:10BAF000FFF794FA0749C8232A462046FFF7A4FA1D
+:10BB00000520F6F798F9284605B030BD4FF001083A
+:10BB1000240300206C5800202DE9F04387B0012257
+:10BB2000044669468DF80020FFF778FAC8230822FA
+:10BB300003A92046FFF788FA21492248DFF88C90B4
+:10BB4000DFF8808005F03AFFFCF7DAFF03AE3746F6
+:10BB5000002517F8012B49464046013505F02EFF18
+:10BB6000FCF7CEFF082DF4D11748184F05F02CFB39
+:10BB700010232046012269468DF80030FFF74EFA67
+:10BB80002A46C82303A92046FFF75EFA10490D484C
+:10BB90000C4D05F013FFFCF7B3FF002416F8012B42
+:10BBA00039462846013405F009FFFCF7A9FF062CA9
+:10BBB000F4D1054805F008FB07B0BDE8F08300BFED
+:10BBC0000EF001081463002086EB01087BE30108F6
+:10BBD0001AF0010870B586B0012B14464FF015021B
+:10BBE0000CBF0323002306460D468DF8002069464E
+:10BBF00002228DF80130FFF711FA0523022203A972
+:10BC00003046FFF721FA9DF80C302B609DF80D307F
+:10BC1000236006B070BD13B5342304468DF80110BF
+:10BC2000022269468DF80030FFF7F8F91E23002242
+:10BC300069462046FFF708FA02B010BD10B50B4662
+:10BC40000649044608224B70FFF7E8F920460349ED
+:10BC5000BDE8104037230022FFF7F6B9D8020020D4
+:10BC6000044B5970C2F30421D9701A711946082285
+:10BC7000FFF7D4B9E402002070B586B050238DF8E8
+:10BC8000083043680546DA6800681B68136003687B
+:10BC9000052200920C469E6802A904ABB0476B686F
+:10BCA0009A681B6813600120F6F7A6F8631E0DF171
+:10BCB0001102033412F8011B03F8011FA342F9D14A
+:10BCC00006B070BD1FB504463323694601228DF8C6
+:10BCD0000030FFF7A3F93723022202A92046FFF71D
+:10BCE000B3F99DF8080004B010BD07B520238DF806
+:10BCF00000308DF801108DF80220002304226946DF
+:10BD00008DF80330FFF78AF903B05DF804FB0000FB
+:10BD100030B50E4B0E4C18689B8887B00025ADF8E7
+:10BD2000103003908DF810102068CDF8125003A940
+:10BD30000522FFF773F91420F6F75EF82068142344
+:10BD40002A466946FFF780F907B030BD891C020812
+:10BD5000DC6200200000000010B51D4A86B0002300
+:10BD6000CDE9032303A903220446ADF81430FFF7FD
+:10BD700055F91420F6F740F84FF4FA6306226946A5
+:10BD80002046FFF761F9A8B19DF805309DF8040041
+:10BD900003EB002010F0A8FD09A3D3E9002310F065
+:10BDA0000DFE09A3D3E9002310F050FC11F0B6F802
+:10BDB00006B010BD4FF6FF70FAE700BFAFF300808A
+:10BDC0007F6ABC749318CC3F0000000000507240A2
+:10BDD0001410A0002DE9F347DFF884801D4ED8F839
+:10BDE000003034681C4F81461868C4F30C040368A3
+:10BDF00004EB0902B2F5005FD3F808A004EB0703D7
+:10BE00001FD3C4F500552A4614490095D04733681E
+:10BE100012491D44D8F8003035601868A4F5005266
+:10BE2000036802EB09040094C5F30C052246D3F81D
+:10BE300008807B19C04732681444346002B0BDE802
+:10BE4000F0870649CDF800904A46D04734684C4404
+:10BE5000F3E700BFDC630020E06300206C580020A3
+:10BE6000DC620020F0B5134D2B685A68D168126867
+:10BE70000A6085B066228DF80820044618680E4BCB
+:10BE80000168012200928E6802A9B0472A680B4E11
+:10BE90001068094B02680094976831682246B847D9
+:10BEA0002B6830685B689A681B68136020443060B8
+:10BEB00005B0F0BDDC6200206C5800205058002016
+:10BEC00010B50A4C0A4920680722FFF7A7F814208A
+:10BED000F5F792FF2068074932230022FFF7B4F8F4
+:10BEE000BDE810401420F5F787BF00BFDC620020DA
+:10BEF0007C6100206C5800202DE9F04F89488A4D64
+:10BF000087B0F4F78BFF05900A20F5F775FF00273F
+:10BF1000BA46B9462E4685492868FFF7ADFE834AE2
+:10BF20005378147803F00103049304F0010303939E
+:10BF30002B689868F4F704FB049BC4F3001499453C
+:10BF4000BB4627462DD0794A794B92781A70794BA7
+:10BF5000DFF808C205991B689CF800C0CB1A764927
+:10BF6000BCF1010F0B600DD1DFF8F4C19CF800C0EB
+:10BF7000BCF1020F01BFDFF8ECC1DCF800C0A3EB9D
+:10BF80000C030B606D490B6813446D4A0B6013681A
+:10BF90000133136033681B699A681B6813604FF0A4
+:10BFA0000109039B9A4501D1A34572D0DFF89C811A
+:10BFB0003368D8F800204AEA0B0A5AEA02015AD13B
+:10BFC0006049DFF894B1487077220A705A68D068E7
+:10BFD000126802601868022203680092D3F808A071
+:10BFE0005B46D0479BF801A00AF15A0AC8F800A0A6
+:10BFF000002C3DD033681B69DA681B681360DFF8DA
+:10C0000050C14D4B504A1968DCF80030C3F30C00A6
+:10C010004FEA112E1154581CC0F30C00090C02F801
+:10C0200000E0981CC0F30C001154D91C4048C1F327
+:10C030000C0100785054191DC1F30C019BF801004C
+:10C04000505405335046CCF80030FFF7C3FE2B6840
+:10C050005B689A681B6813600120F5F7CDFE3B4AC8
+:10C060001368A3EB0A031360384B1B687BB90AE023
+:10C070004FF0590AC3E7A3452CD15A2A924628BF4C
+:10C080004FF05A0A62BB324B1A68324B1A60DDF825
+:10C090000CA028686FEA09020AEB0411D2B281F001
+:10C0A000FF01FFF722FE049B8BB92B689868F4F719
+:10C0B0003FFA122458B90120F5F79EFE33689868BC
+:10C0C000F4F736FA013CF5D100283FF424AF07B06D
+:10C0D000BDE8F08F1969C868096801609246D1E728
+:10C0E000184977220A705A68D06812680260186886
+:10C0F000012203680092D3F808B0174BD847504686
+:10C10000FFF768FE33685B6899681B680B60012263
+:10C110001046F5F771FED8F80030A3EB0A03C8F813
+:10C120000030A1E7B0620020DC620020025900204C
+:10C13000075900201C03002014590020D063002060
+:10C14000CC63002018590020E063002054580020E0
+:10C15000DC630020E083002008590020F4C900209F
+:10C16000A161002034840020F8B51448144EF4F77F
+:10C1700055FE144B144A1F68144BD3F800C01368C3
+:10C180000024C0F307409F4202D804B11360F8BDF9
+:10C1900003F07F01CD0106EBC111755D451B6545BF
+:10C1A000F3DD49785C31802902D801330124EAE7C4
+:10C1B000B1F5807F94BF02330333F7E7B06200200C
+:10C1C000E0890020E8C90020E0C900200C0300201D
+:10C1D0007FB5154B154C1E687578721C5B351A605F
+:10C1E000256000F057FEB0701E20FFF73BFE23686D
+:10C1F0000F4E1E3B23600F4B306819782A46FFF71D
+:10C200002FFD25685F2D28BF5F252846FFF72AFEF2
+:10C2100030683723002201A9FEF716FF23685D1B53
+:10C22000256004B070BD00BF505800205858002051
+:10C23000DC6200209B61002037B5224B00221A707F
+:10C24000214B1B7833B9012804D1204B1860204BB7
+:10C250007E221A701F4C6420F5F7EDFD01AA1146ED
+:10C2600020680123FFF7B6FC23680025DD601B6909
+:10C27000DA681B6813600A20F5F7BEFD2068032109
+:10C28000FFF7C9FC0A20F5F7B7FD01AA0123114603
+:10C290002068FFF79FFC0A20F5F7AEFD2A462068CC
+:10C2A0002946FFF722FD0A20F5F7C5FD0A4B1A685B
+:10C2B0000A4B1A600A4B1B68DA681B68136003B0EC
+:10C2C00030BD00BFAB620020F4C90020FCC90020D3
+:10C2D0003D030020DC620020E0830020DC630020BE
+:10C2E000D8620020054B1A78054B012A02D11A604A
+:10C2F000FFF7A2BF00221A60704700BFAB620020A8
+:10C3000064580020F7B5204A204C21491160214D86
+:10C310006A464FF47A7601231146464320682B7013
+:10C32000FFF758FC002211462068FFF7DEFC236867
+:10C330000227DF601420F5F75FFD002201A92068C5
+:10C340001423FEF781FE2368E620DF6001F080F809
+:10C350000020FFF73DFF10480F4FF4F75FFD044644
+:10C360000220F5F768FD3846F4F758FD031B9E429E
+:10C37000F6D80023C8202B70F5F75DFD0120FFF7EC
+:10C380005BFF03B0F0BD00BF50580020DC6200200E
+:10C39000548400205C580020B062002007EE900A10
+:10C3A000B2EE007ADFED266A264B27EE877A30B5AB
+:10C3B000C7EE267A85B0002400930294CDF80B4096
+:10C3C000214DBCEEE77A17EE102A013A07EE102A4B
+:10C3D000B8EE477A8DF8042077EEC77A9FED1B7A86
+:10C3E00067EE877AFCEEE77A17EE903A07EE901A3E
+:10C3F00067EE877A1A0C17EE900A5BBA8DF8052063
+:10C40000ADF8063010F082FA114B002210F000FC5B
+:10C4100010F0ACFD40BA6946ADF808000A22286861
+:10C42000FEF7FCFD6420F5F706FD0A492868C823DD
+:10C430002246FEF709FE6420F5F7FDFC05B030BD8D
+:10C440000000704211400600DC620020000000493C
+:10C4500000001E406C5800204A4BDFED4B6A1B88E1
+:10C4600007EE903AF8EE677A484B87EEA67AB3F972
+:10C47000003030B4DFED467A37EE277A07EE903A97
+:10C48000F8EEE77A434B87EEA66A1B78012B36EE6F
+:10C49000076A0BD1404B1B78012B17BFF0EE477A90
+:10C4A000B0EE476AB0EE467AB0EE676AF2EE005A36
+:10C4B0009FED3A5A9FED3A4ADFED3A4A3A4A66EE24
+:10C4C000256A3724C6EE857A14700024D471362587
+:10C4D000FCEEE76A16EE900A013806EE900AF8EED6
+:10C4E000666A507077EEE66A66EE846AFCEEE67A7B
+:10C4F00017EE903A66EE247A180CC7EE856A9070B3
+:10C50000180AD070137166EEA56AFCEEE67A67EE43
+:10C51000256A17EE901AC6EE857A0B0A53716423CA
+:10C5200013729171214A157027EE247AFCEEE76AA6
+:10C5300016EE900A013806EE900AF8EE666A507020
+:10C5400077EEE67A67EE847AFCEEE77A17EE903AB9
+:10C55000C7EE057A180C90701371180AD07016EE99
+:10C56000100A67EEA57AFCEEE77A17EE901A0B0A2E
+:10C5700053710F4B91711C700E4B0F491C7030BCE6
+:10C58000FFF70CBF9E61002000007A449C610020F0
+:10C590000000D243F4C90020A161002000007042D5
+:10C5A00000000049000000428B6100207C610020F7
+:10C5B0009B6100209A61002000002041F7B52F4CBC
+:10C5C0002F4F23685B69DA681B6813600A20F5F750
+:10C5D00032FC23685B699A681B6813604FF4FA7039
+:10C5E000F5F729FC23685B69DA681B681360C820CB
+:10C5F000F5F721FC05263D463B78142B3BD12068FE
+:10C60000FEF760FE2B780B2B02D12068FEF7CCFEE4
+:10C610002B78152B02D12068FEF738FF2B780C2BD6
+:10C6200002D12068FEF7A4FF2B78162B02D12068D8
+:10C63000FFF710F82B780D2B02D12068FFF77CF85C
+:10C640002B78172B02D12068FFF7E8F82B780E2BF8
+:10C6500002D12068FFF754F92B78182B02D12068FB
+:10C66000FFF7BEF90190FFF7F7FE019808B9013E08
+:10C67000C2D103B0F0BD0020C4E700BFDC620020DF
+:10C680009962002038B50B4C0B4DFFF765FB236812
+:10C690002860B3F5967F01D1206038BDC01A0E30F6
+:10C6A0001C28FAD9FFF78AFF2B6823600028F4D1F1
+:10C6B000FEF78AFCD40200200C6300202DE9F04133
+:10C6C00004461E460D461746F5F7DAF8636B23B9A4
+:10C6D00094F838300BB1F4F7B7FC04F12808A845FA
+:10C6E0000AD04046F3F7D4FDEB681BB15B682946DE
+:10C6F00040469847EB6863633A4633462046F4F772
+:10C70000B8FABDE8F041F5F7E7B8000038B50D46D6
+:10C7100004461022002104F0E1FC2B682360014B49
+:10C72000E36038BD58D4010870B5324886B0F4F7DC
+:10C7300075FB314B1B78ABB1304A314B12781B780B
+:10C74000022A11D173B12F4B019301A902A8FFF75F
+:10C75000DDFF2D482D4A002302A9FFF7AFFF02A8F5
+:10C76000F3F796FD06B070BD002BFBD0284B1B687D
+:10C77000C01A284B1B6803F5742303F51073984205
+:10C78000F0D9254D254B264E264C00221A602B68E9
+:10C790002068B3F5967F04BF33682B60FFF7DCFA9F
+:10C7A0002B683060C31A0E331C2BDBD9236828603A
+:10C7B0000025DD601C4B1A681C4B1A60FFF7FEFE5B
+:10C7C00008B9FEF701FC1A4B20681978FFF736FA12
+:10C7D00020682A462946FFF788FA052302222068A6
+:10C7E00002A9FEF731FC134B1D6023680122DA60B9
+:10C7F000B8E700BFB0620020F4C90020A1610020AA
+:10C80000AB62002039C80008F083002020A1070097
+:10C81000F8C9002028030020D4020020EC62002088
+:10C820000C630020DC620020E0830020DC63002039
+:10C830009A6100205458002030B5274C27482368BF
+:10C840001B69DA681B681360254B1B689A681B68B4
+:10C85000136087B0F4F7E2FA224B1B78002B39D033
+:10C86000214D23682A780024DC60FAB11F4B1B7825
+:10C87000012B1BD81E4B00F543401B685030C01ADB
+:10C880001C4B1B6820F0004098420FD21A4B0193BA
+:10C8900001A902A8FFF73AFF184B19481A6802A924
+:10C8A0002346FFF70BFF02A8F3F7F2FC154B0193A9
+:10C8B00001A902A8FFF72AFF002313484FF4AF7223
+:10C8C00002A9FFF7FBFE02A8F3F7E2FC2B780BB1FD
+:10C8D00000F0D6FB07B030BDDC620020B062002063
+:10C8E000D8620020AB620020F4C90020A1610020C2
+:10C8F000F8C900202803002039C80008FC020020E5
+:10C90000F08300203DC900089056002038B5084843
+:10C91000084DF4F783FA2B68C21A074B1B6803EB28
+:10C92000C3039A42044602D9FFF786FF2C6038BD44
+:10C93000B0620020F8C90020FC02002010B5244B92
+:10C940001B7886B0002B40D02248234CF4F766FABF
+:10C95000224B1B6803F212231844214B01A91860D3
+:10C96000204B019302A8FFF7D1FE40F212220023D0
+:10C9700002A91D48FFF7A2FE02A8F3F789FC206870
+:10C980000521FFF748F9194B20681A68184B1A60FF
+:10C9900001AA11460123FFF71DF90022154B20685B
+:10C9A0001A601146FFF7A1F923680221D96014200B
+:10C9B000F5F722FA142302A920680022FEF744FBAF
+:10C9C0000D4B20681978FFF7A3F906B010BD00BF22
+:10C9D000AB620020B0620020DC620020C4040020B2
+:10C9E00060580020BDCA000810560020E0830020D7
+:10C9F000DC63002068580020AE61002070B5254C33
+:10CA0000254D20688AB001AA01231146FFF7E2F8FC
+:10CA10002B6820680026012BC66002D1FFF732FE8A
+:10CA20002E601E4B20681978FFF708F9FFF748FAC7
+:10CA3000002220681146FFF758F9206805230222DA
+:10CA400003A9FEF701FB164B00221A60154B1B6869
+:10CA5000DA681B68136023680122DA60124B1C78C5
+:10CA6000ACB9124B1B78182B11D1114B029302A9B0
+:10CA700006A8FFF74BFE0F4B0F481B680A225A43CC
+:10CA800006A92346FFF71AFE06A8F3F701FC0AB031
+:10CA900070BD00BFDC620020EC6200209A610020C3
+:10CAA00054580020D8620020F4C900209962002068
+:10CAB0000DC90008FC02002050560020484B70B5FC
+:10CAC00000251D60FFF750FB464B1A68464B1B685C
+:10CAD0009A4229D2FDF76AFE012504464348F4F73D
+:10CAE0009DF9434B434A1B681268323B9B1A18441A
+:10CAF000414B1B6803FB0400404C236813B9404AB8
+:10CB0000126810443F4A1278B3FA83F676096AB97C
+:10CB10003D4B1B78012B42D13C4B3D4A1A603046BD
+:10CB2000BDE87040FFF754BB7824D7E7394A127844
+:10CB3000002A38D0384E3278022A30D0B3B9334B7D
+:10CB4000334A1A6000F05CFA3378012B04D1334B7E
+:10CB50001B689A681B6813600120FFF739FB304B94
+:10CB60001978304B1868FFF7D3F80BE075B100283F
+:10CB70000CDA2D4D2846FDF727FE244B00201D60C2
+:10CB8000FFF726FB23680133236070BD0023012AD1
+:10CB9000236004D1214B1B68DA681B681360BDE871
+:10CBA0007040FFF72BBF75B9BBB9204B1B68022B38
+:10CBB00013D1164B164A1A600120FFF709FB2368B0
+:10CBC000002BDFD1CBE7002807DA174D2846FDF709
+:10CBD000FBFD0E4B30461D60EFE700232360DEE7D0
+:10CBE00094CA0020E0C90020E8C90020B0620020FB
+:10CBF0002003002060580020140300206858002003
+:10CC000010030020AB6200205C5800205058002028
+:10CC100054840020F4C90020A1610020D4620020C7
+:10CC2000AF610020DC620020D0560020FCC900204B
+:10CC30002DE9F843234FDFF890800025A9463E46B2
+:10CC400021493868FFF718F898F80030C3F340041A
+:10CC5000C3F340139D4221D0FFF730FF012504EBC1
+:10CC600005116FEA410130680022C9B2FFF73DF8B3
+:10CC700033689868F3F75CFC4FF0190950B901204C
+:10CC8000F5F7BAF833689868F3F752FCB9F101097F
+:10CC9000F4D108B1BDE8F883A146D1E7A145DED0C3
+:10CCA000DFF82890D9F8004054B15A2C28BF5A24F4
+:10CCB0002046FFF7D7F8D9F80000001BC9F800009C
+:10CCC0000124CCE7DC6200202259002058580020C3
+:10CCD00010B5094C2268D268012A04D1074B1B7891
+:10CCE0004BB1FFF709F92368DB68022B03D1BDE8DC
+:10CCF0001040FFF79DBF10BDDC620020AB6200203A
+:10CD000037B5154C227822BB144D01920120F5F75E
+:10CD100092F8019A28681146C260FEF7E6FF4FF4C8
+:10CD20001673019A0E492868FEF78EF901232370C5
+:10CD30000C4B1B7843B10C4B1B78012B04D803B070
+:10CD4000BDE83040FFF778BD03B0BDE83040FFF7E5
+:10CD500055BE03B030BD00BFAB620020DC620020D6
+:10CD60006C580020F4C90020A161002070B5044671
+:10CD70001B480E461546F4F751F81A4B186032203E
+:10CD8000F5F759F8012E0FD12DB11749174804F0C6
+:10CD900015FEFBF7B5FEFFF711FC2DB11449134842
+:10CDA00004F00CFEFBF7ACFE012C0BD1114B1B78F1
+:10CDB000012B114B1BBF1C60104B02227E220CBFAB
+:10CDC0001A601A70462000F043FB012C01D100F0DC
+:10CDD00049F8FDF7E5FEBDE87040FFF791BF00BFE1
+:10CDE000B0620020F8C9002065E401081463002047
+:10CDF0002AF00108F4C90020FCC900203D030020EE
+:10CE0000034B1B68012B01D1FFF7B0BF704700BF78
+:10CE10006458002010B50E4C2046FEF7E7F8204677
+:10CE20000C4C0D4A0D49F4F7F9FE2046FEF7DEF8EA
+:10CE300020460B4C084A0949F4F7F0FE2046FEF75D
+:10CE4000D5F82046044A0549BDE81040F4F7E6BE8F
+:10CE5000905600201056002088010020590D00082F
+:10CE60005056002008480949094A70B50723002692
+:10CE700020250124013B00F8016B41F8045B42F8D6
+:10CE8000044BF7D170BD00BF705900207C590020C1
+:10CE90004C59002010B50E4B1B78044653B10D4978
+:10CEA0000A7802F01F03403368B101320A70203360
+:10CEB000DBB208E0FDF7CEFC1E28034628BF1E2388
+:10CEC000DBB2002CF3D1044AD05C1844C0B210BDD0
+:10CED000F4C900202759002044040020000000006D
+:10CEE0002DE9F0418D06044662D5480660D43648E7
+:10CEF000415C00295CD0815C002959D002F07F059B
+:10CF0000324A1278012A1FBF314A106820F07F4050
+:10CF1000241A712B16DCC3F172000FF0E5FC26A376
+:10CF2000D3E900230FF04AFD064620460F460FF0D6
+:10CF3000DBFC02460B46304639460FF089FB0FF00A
+:10CF4000EDFF0446062D2BD8224B5B5D83B3224BAD
+:10CF500053F825000A2303FB104404F1C70240F6EE
+:10CF600096039A4219D8DFF8788058F825000FF018
+:10CF7000BBFC13A3D3E900230FF020FD0646204697
+:10CF80000F460FF0B1FC02460B46304639460FF013
+:10CF90005FFB0FF0C3FF48F8250020B2BDE8F08129
+:10CFA0007E2D05D10D4B18680A2303FB1044F4E7CE
+:10CFB00047F6FF74F1E700BF333333333333EB3FCE
+:10CFC000CDCCCCCCCCCCEC3F44030020A1610020E4
+:10CFD00034840020806200203059002078590020DD
+:10CFE0003884002040F6960301F1C7029A429FBFA1
+:10CFF0000A235943014B43F820107047388400201E
+:10D0000008B50348F3F70AFF024B186008BD00BFDC
+:10D01000B06200203484002008B50548F3F7FEFE16
+:10D02000044B054A186013680133136008BD00BF44
+:10D03000B062002034840020E8830020F0B50C4B5F
+:10D040000C4C0D4A0D4F00212026012514F8010B30
+:10D0500050B1106800B918600131072903F10403C9
+:10D0600002F10402F2D1F0BDC85516601D60F3E76D
+:10D070004C590020806200207C590020705900200B
+:10D080002DE9F04FB24BB34AB34C85B0184600932C
+:10D090000125002310F8011B39B111680029C2BF16
+:10D0A00001F1FF3144F8235011600133072B02F1E5
+:10D0B0000402EFD1A94B1B789B0701D1FFF7BEFFFC
+:10D0C000FDF7C8FBA64BA74CA14D07211E46002724
+:10D0D00015F8012B2AB122781AB91A780AB1013A47
+:10D0E0001A70013904F8017B03F10103F0D19E4C61
+:10D0F0000123237028B11E2828BF1E20013800F00C
+:10D10000FF004FF0000C0123914D934FDFF85CE2DC
+:10D110006246984615F8011B81B157F8221069B193
+:10D12000B15C02F80E800DF108090CF1010C09F850
+:10D13000021011B1013909F8021001330132072A36
+:10D14000E8D10127DFF810A20025BE460E2B00F320
+:10D150006C81BEF1000F40F0298105B12770227863
+:10D160007D4F8248009E0132D2B20133002116F871
+:10D17000015B45B157F821502DB10F2B1FBF05782A
+:10D180000135057001330131072900F10100EED1AD
+:10D190000F2BE6D12270764B24781968754B6C4EB4
+:10D1A0001D68754B6C4F1A68744BDFF8C0E10A4478
+:10D1B00005FB0422601E01FB00201860704B1A68FA
+:10D1C000704B1B680A441A4402444FF00A0C0020BA
+:10D1D00045F2EE5B01EB05084FF0640916F8013BE0
+:10D1E000ABB157F8203093B1B2FBFCF3664C54F866
+:10D1F000204004F2CF7ADA459CBF94FBF9F41B1B64
+:10D20000624C44F820301EF8003008FB0322013045
+:10D210000728E3D15D4CDFF838C1DFF83CE1DFF8E7
+:10D2200068B12646002045F2EE584FF064090A27FF
+:10D23000B2FBF7F71CF8013B6BB15EF8203053B935
+:10D240005BF8203003F2CF7AC2459DBF93FBF9F320
+:10D25000FB1A336037600130042806F10406E9D177
+:10D2600029440A440A23B2FBF3F3494A3A49464D9A
+:10D27000136045F2EE566427354A825C6AB151F874
+:10D28000202052B955F8202002F2CF7CB4459DBF32
+:10D2900092FBF7F29A1A226123610130072804F108
+:10D2A0000404E9D13B492C4F0191FF220A701F224F
+:10D2B0004A70002402220846009E16F8015B009680
+:10D2C00002F1050C25B3314E57F8241056F82460AE
+:10D2D00002F1010A02F102095FFA86FBE5B2C6F328
+:10D2E00007260129855402F1030800F80AB002F16B
+:10D2F000040E00F8096040F09D801C4AA25C02F018
+:10D300000F0200F808204FF0000200F80E206246DD
+:10D310000134072CD0D101997E2088541144063263
+:10D320004B701B0A422A8B704FF00103B8BF422298
+:10D33000CB7023230B711046FF234B710092FDF736
+:10D340003BF91549009A59384870002326E000BF80
+:10D35000806200207C5900204C5900202759002071
+:10D360007059002068590020775900202859002062
+:10D37000040300200003002030030020C404002028
+:10D3800008030020F80200203884002030590020D3
+:10D390007859002098590020548400202A480B70A6
+:10D3A000033105B0BDE8F04FFCF7A8BF98B1421EAD
+:10D3B0007E1C12F0FF02F6B203F1010109D00F2921
+:10D3C00007D0BCF1010F04DDBE1C821EF6B2D2B242
+:10D3D000991C012502E03E4602461946DFF86C80A2
+:10D3E000DDF8009096460B46002019F8011BA1B10C
+:10D3F0005AF820708FB102A9095C71B10F2B0CD0C3
+:10D4000098F80070013788F80070013902AFC9B28E
+:10D410008E44395401335FFA8EFE0130072808F13B
+:10D420000108E2D13746104690E6002D3FF4B3AE36
+:10D430002770B0E605F003054FF00102203500F833
+:10D44000082000F80E5062E7985900202859002063
+:10D4500010B50C4B0C491B78C95CC4B00B440024BC
+:10D460008DF80C3001908DF80D40FDF7A5F80749B7
+:10D47000019A0C7059384870033103A8FCF73EFF3D
+:10D4800044B010BD3D03002044040020548400201B
+:10D490002DE9F74F224B234A93F800E0224B90F8F6
+:10D4A00002C01B680093214B15781B6801938946C5
+:10D4B0001F4B20491C680E780027C0F1020A4FF06C
+:10D4C0000A08BCF1FF0F06D117B10E7015701C6071
+:10D4D00003B0BDE8F08F0AEB000BD945F4DDE6455B
+:10D4E0001AD10579C478009E04EB0524124D08FB7F
+:10D4F00004F42C60447904F00F04651E7443019E0B
+:10D5000006FB05440D4D2C6084790D4D04F00F068B
+:10D51000240901272D5D002490F807C00530D0E7CD
+:10D520003D0300206F590020000300200403002069
+:10D53000F00200202F59002040030020C4040020E6
+:10D54000931C0208F0B5314A1C46135C87B0DBB16E
+:10D550002F4B1B78D3B1430616D401F07F03062B63
+:10D5600012D8525C82B12B4A00F01F01D1542A49D3
+:10D57000012210F01E0FCA5406D02849202041F87D
+:10D580002300274941F8232007B0F0BD00F01F0316
+:10D59000244A00F0600060281370F5D1224A234D20
+:10D5A00014602A68012AEFD8214A1278002AEBD0A9
+:10D5B000204A12785340204A12781340E4D11F4881
+:10D5C0000193F3F72BFC1E4A1E4F12681E491444A8
+:10D5D000064624F07F4402A83C60F3F749F81B4953
+:10D5E0003A680868019B121A921B22F07F42184881
+:10D5F00002A9FFF763F802A8F2F74AFE2B6801338D
+:10D600002B60144B01221A60BEE700BF44030020C8
+:10D61000F4C9002070590020685900207C5900206E
+:10D620004C5900202759002034840020F0020020AB
+:10D63000AB6200202F5900206F590020B0620020FB
+:10D64000400300209CCA002039C8000818030020AD
+:10D65000F083002094CA0020F0B5274887B0F3F784
+:10D66000DDFB264B1968264B1A68064602F5FA536D
+:10D67000401A83423ED202F51C531033834239D9FB
+:10D68000204C2368012B35D81F4D2B68002B31D13E
+:10D690001E4B1B78002B2DD01D480378013303F05F
+:10D6A0001F0303701B48007843401B480078034069
+:10D6B00020D11144194A1A4F12680193114421F0E4
+:10D6C0007F41396002A81749F2F7D2FF16493A683C
+:10D6D0000868019B121A921B144822F07F4202A98B
+:10D6E000FEF7ECFF02A8F2F7D3FD236801332360B5
+:10D6F00001232B6007B0F0BDB0620020348400200D
+:10D70000FC020020F002002094CA0020AB6200203E
+:10D71000275900202F5900206F5900204003002076
+:10D720009CCA002039C8000818030020F08300209C
+:10D73000F0B58DB01D46D20043688DF80A2049BA75
+:10D74000DA68ADF808101B68136000232B700446DC
+:10D750000068129E0368032200929F6802A907AB2B
+:10D76000B847206803680096324607A99F682B4691
+:10D77000B8470120F4F740FB63689A681B681360A0
+:10D780000220F4F739FB0DB0F0BD00007FB51D4657
+:10D79000D200436849BA04328DF80E20ADF80C105F
+:10D7A000DA681B681360044600680E4B01680322A8
+:10D7B00000928E6803A9B04720680A4B02680021D6
+:10D7C00000919668089A2946B0470120F4F714FBA7
+:10D7D00063689A681B6813600220F4F70DFB04B0BD
+:10D7E00070BD00BF345A0020F0B58DB0D2001D4688
+:10D7F00043688DF80A2049BADA68ADF80810129E1D
+:10D800001B68136004460068F21C036800929F685E
+:10D8100002A907ABB8470DF11F030022B24204DA98
+:10D8200013F8011BA9540132F8E70120F4F7E4FAD8
+:10D8300063689A681B6813600220F4F7DDFA0DB084
+:10D84000F0BD70B588B049BAADF80810D100043108
+:10D850000C9D8DF80A1004460DF10B020021A9421F
+:10D8600004DA585C02F8010B0131F8E763682068BC
+:10D87000DA681B68136003680022009202A9EA1CA0
+:10D880009E6805ABB0470120F4F7B6FA63689A6862
+:10D890001B6813600220F4F7AFFA08B070BD30B512
+:10D8A0008DB04368D2008DF80A2049BAADF808104F
+:10D8B000DA681B681360044600680422036800925B
+:10D8C0009D6802A907ABA8470120F4F795FA6368A1
+:10D8D0009A681B6813609DF81F000DB030BD30B50D
+:10D8E00089B0D2008DF80B30436849BA04328DF804
+:10D8F0000A20ADF80810DA681B6813600446006857
+:10D9000000220368009202A99D68042205ABA84783
+:10D910000120F4F771FA63689A681B6813600220AB
+:10D92000F4F76AFA09B030BDF0B58C00013487B065
+:10D930000746E4B242F20F75022603AB2246009678
+:10D9400026213846FFF750FF2B469DF80C209DF806
+:10D950000D5005EB0225AB42EFD1284607B0F0BDD4
+:10D960002DE9F0478900CDB286B06F1CFFB24FF0B1
+:10D9700002089946924603AB3A46CDF8008028212A
+:10D980000646FFF731FF9DF80C409DF80D10CDF8CD
+:10D99000009001EB04218CB2EA1C5346214630462C
+:10D9A000D2B2FFF7C5FE04EB09035CBA3A4603ABFB
+:10D9B0003046CDF800802821ADF80C40FFF741FF3C
+:10D9C00040233A4601213046FFF789FF06B0BDE803
+:10D9D000F0872DE9F0478D0090B06F1CFFB24FF03B
+:10D9E0000208914603AB3A46CDF800802821044650
+:10D9F000FFF7FAFE9DF80D309DF80C208DF82D30C4
+:10DA0000033503EB0226ED0063688DF82C208DF8BA
+:10DA10002E50DA6820681B681360036803220092A6
+:10DA20009D680BA906ABA8472068082203680092EE
+:10DA30009D6806A94B46A84799F8062099F8075013
+:10DA4000206805EB02250368009506A92A46D3F84D
+:10DA500008A009F10803D0470120F4F7CDF9636865
+:10DA60009A681B6813600835B6B240462E44F4F736
+:10DA7000C3F976BA03AB3A462046CDF80080282198
+:10DA8000ADF80C60FFF7DDFE204640233A46012149
+:10DA9000FFF725FF284610B0BDE8F0872DE9F047D5
+:10DAA0008D0090B005F101084FF002095FFA88F887
+:10DAB000174603AB4246CDF8009028210446FFF7F5
+:10DAC00093FE9DF80D309DF80C208DF82D30033518
+:10DAD00003EB0226ED0063688DF82C208DF82E50A4
+:10DAE000DA6820681B6813600368032200929D684F
+:10DAF0000BA906ABA84720680368CDF800909D6885
+:10DB00004A463B4606A9A8473B787D78206805EB46
+:10DB10000325AA1E0368009206A9D3F808A007EB04
+:10DB20000903D0470120F4F767F963689A681B6816
+:10DB30001360B6B248462E44F4F75EF976BA03ABEA
+:10DB400042462046CDF800902821ADF80C60FFF742
+:10DB500078FE2046402342460121FFF7C0FE2846BA
+:10DB600010B0BDE8F0872DE9F04F8900CDB287B045
+:10DB70006F1CFFB24FF002099A46934603AB3A4638
+:10DB8000CDF8009024210646DDF84080FFF72CFEFA
+:10DB90009DF80C109DF80D40CDF800A004EB012479
+:10DBA000A4B205EB09025B462146304602F0FE02B4
+:10DBB000FFF7ECFD04EB0A035CBA3A4603AB3046D0
+:10DBC000CDF800902421ADF80C40FFF73AFEB8F1F3
+:10DBD000010F0CBF212320233A4601213046FFF7D5
+:10DBE0007EFE07B0BDE8F08F014B02221A6070473D
+:10DBF000305A0020F0B52E4D2B68042B87B0044618
+:10DC00002F460DD12B4B1B78DB00403B03F0F80374
+:10DC100000222E21FFF763FE01232B6007B0F0BD29
+:10DC2000032B01D10423F8E7022BF7D1224D03A9DE
+:10DC300028680426FAF727FD03AB00220F212046AF
+:10DC40000096FFF7A3FDE86803A9FAF71CFD03ABF4
+:10DC50000096002205212046FFF798FD2B7DF3B1A9
+:10DC6000164B1B78DBB1164B1B78C3B1286903A98F
+:10DC7000FAF709FD009603AB002201212046FFF7C9
+:10DC800085FD0C4B1B78DB00403303F0F8030022CA
+:10DC90002E212046FFF723FE03233B60BEE703A9A6
+:10DCA0004FF00130FAF7EFFC04230093E3E700BFE5
+:10DCB000305A0020F40200208C630020F5C90020B7
+:10DCC000F4C9002070B5002288B0114680230446B4
+:10DCD000FFF705FE4FF4FA70F4F7ADF8CA4D0023D4
+:10DCE0001A4619462046FFF7FAFD2B78DB00403331
+:10DCF00003F0F80300222E212046FFF7F0FD4FF439
+:10DD0000C860F4F798F82B78C04DDB00403B03F077
+:10DD1000F80300222E212046FFF7E1FDBC4B1868D6
+:10DD20009A8803909B79ADF8102000210D220DF107
+:10DD300013008DF8123003F0D1F90623002200936E
+:10DD40000921B44B2046FFF721FD0426286803A9CA
+:10DD5000FAF799FC03AB0F21009600222046FFF74B
+:10DD600015FDAD4B1B7803A9002B00F04781AB4B91
+:10DD70001B78002B00F042812869FAF784FC00969A
+:10DD800003AB002220460121FFF700FDE86803A94C
+:10DD90000425FAF778FC03AB204600950022052104
+:10DDA000FFF7F4FC2046012300221821FFF797FD1E
+:10DDB0002046082301221E21FFF791FD2046022361
+:10DDC00005221E21FFF78BFD2B46204609221E212E
+:10DDD000FFF785FD204602230D221E21FFF77FFD60
+:10DDE0002046002311221E21FFF779FD2046002343
+:10DDF00015221E21FFF773FD2046002319221E2144
+:10DE0000FFF76DFD204600231D221E21FFF767FD51
+:10DE10002B46204601221F21FFF761FD20460223E9
+:10DE200005221F21FFF75BFD2B46204609221F21FB
+:10DE3000FFF755FD204602230D221F21FFF74FFD5E
+:10DE40002046022311221F21FFF749FD204600230F
+:10DE500015221F21FFF743FD2046002319221F2111
+:10DE6000FFF73DFD204600231D221F21FFF737FD50
+:10DE70002046342301220021FFF731FD2B460122E9
+:10DE80002C212046FFF72BFD0A20F3F7D4FF0123B6
+:10DE90001A4619462046FFF722FD012305220021DC
+:10DEA0002046FFF71CFD0A20F3F7C5FF02264FF4BA
+:10DEB000B853ADF80C30294603AB20460096052236
+:10DEC000FFF7BFFC4223092200212046FFF707FD90
+:10DED0000A20F3F7B0FF4EF60573ADF80C30294673
+:10DEE00003AB204600960922FFF7ABFC4EF6054334
+:10DEF000ADF80C30204603AB009609221021FFF745
+:10DF0000A0FC0123194620460922FFF7E8FC444BF8
+:10DF10000393204603AB009509220C21FFF791FCE7
+:10DF200033460D2200212046FFF7D9FC0A20F3F7E3
+:10DF300082FF4FF48643ADF80C30294603AB2046F0
+:10DF400000960D22FFF77DFC4FF48843ADF80C30AE
+:10DF5000204603AB00960D221021FFF772FC01232F
+:10DF6000194620460D22FFF7BAFC4FF0FF3303930A
+:10DF7000ADF81030204603AB00950D220C21FFF7C1
+:10DF800060FC0621009103AB20460D22FFF759FCEF
+:10DF90004223112200212046FFF7A1FC0A20F3F7BB
+:10DFA0004AFF43F61A63ADF80C30294603AB20460E
+:10DFB00000961122FFF745FC43F61A43ADF80C30EA
+:10DFC000204603AB009611221021FFF73AFC0123F3
+:10DFD000112219462046FFF782FC124B03A918684C
+:10DFE000FAF751FB03AB009511220C212046FFF7F5
+:10DFF00028FC0D4B01221A6008B070BD0020FAF712
+:10E0000042FB04230093BBE6F40200208C63002053
+:10E010009B1C0208A8610020F5C90020F4C900205B
+:10E020000A97003CA4610020305A0020F0B585B06A
+:10E03000054601A8F2F745F901A8F2F77FF91C4F50
+:10E040001C4E002404233A460DEB030002A9F2F70C
+:10E05000A9F99DF809309DF808201B0403EB026321
+:10E060009DF80A2003EB02239DF80B2013445A1C51
+:10E0700002D09C4238BF1C4607F58077B742E1D1F9
+:10E0800064B104F03F0202F5002202F570724FF411
+:10E0900080731202294601A8F2F784F901A8F2F769
+:10E0A00067F901A8F2F70EF9204605B0F0BD00BFF0
+:10E0B00000C003080000040873B50C46064601A81A
+:10E0C000F2F7FFF8002C08BFFF24013404F03F05ED
+:10E0D00005F5002501A8F2F731F905F5707563071C
+:10E0E0004FEA05250CD1154915482A4603F066FC70
+:10E0F000FAF706FD4FF40062294601A8F2F7AEF9DF
+:10E10000230E3370230C7370230A2A46B3703146F2
+:10E110004FF48073F47001A8F2F762F909490848D6
+:10E1200003F04CFCFAF7ECFC01A8F2F721F901A886
+:10E13000F2F7C8F8204602B070BD00BFAF1C02085D
+:10E1400014630020C21C020807B501A8F2F7B9F851
+:10E1500001A8F2F7F3F807494FF4804201A8F2F75B
+:10E160007DF901A8F2F704F901A8F2F7ABF803B0C2
+:10E170005DF804FB00C003082DE9F04100260546C8
+:10E18000B046071D2B6828469B6898473846F5F728
+:10E19000B1FF2B680446DB682846C4F30014984797
+:10E1A000B44004200136F3F746FE4444082E5FFADB
+:10E1B00084F8E7D14046BDE8F08100002DE9F04346
+:10E1C0000346824E13F8042F3270814A044687B00A
+:10E1D0001430114613F8015F02F8015B8342F9D154
+:10E1E0000023CB737B4B627D1A70A27D02F03F034C
+:10E1F000A3F10B01032904D9A3F11401042988BF59
+:10E2000018237549DFF828820B70744B744D754FD5
+:10E2100092091A70744BE27D1A70744B227E1A7048
+:10E22000734B627E1A7004F11A00FAF721FA04F1B6
+:10E230001F09A37FC8F8000048463B772B77FAF701
+:10E2400017FA38604846FAF713FA04F123092860F0
+:10E250004846FAF70DFAF8604846FAF709FAE86016
+:10E2600004F12700FAF704FA624B04F12C09186054
+:10E2700094F82B307B7548466B75FAF7F9F9B8615D
+:10E280004846FAF7F5F904F1310994F83030A861FD
+:10E2900048463B752B75FAF7EBF938614846FAF7B3
+:10E2A000E7F9286104F13500FAF7E2F9524B94F8E6
+:10E2B00039201A70514B5249DFF8789108604E228C
+:10E2C0001A7046225A7050229A705222DA7094F8CC
+:10E2D0003A201A7194F83B205A714A4B94F83C202A
+:10E2E0001A70494B94F83D201A7094F8402094F825
+:10E2F000413043EA02235A1E92B247F22F50824223
+:10E30000424A88BF44F26823138094F8422094F86C
+:10E31000433043EA02233E4A13803E4B94F84420A4
+:10E320001A7004F1460094F8453089F800304746E9
+:10E330008846FAF79DF9384B384A186094F84A3005
+:10E340001033DBB2072B28BF072313702B7F012B61
+:10E3500001BFD8F800306B603B68AB603378012BAD
+:10E3600028D199F80050012D16D099F80030022BD1
+:10E3700020D12B4B2B4C1D681022F4B9214602A84A
+:10E3800002F0ACFE02A92846F2F7FFF8059B8BB11C
+:10E390009B6802A898470DE0234B18680190F3F79B
+:10E3A0006FFA01982946F8F739FEF3F795FA3378B2
+:10E3B000012BDAD007B0BDE8F083002102A802F0FB
+:10E3C0008DFE1A4B02940593DCE700BFF4C90020D0
+:10E3D0009A6200203C03002099620020A061002086
+:10E3E0008C630020AC63002088620020AA620020B9
+:10E3F000AC620020B0610020F5C90020A8610020B7
+:10E40000B861002087620020240300209E61002064
+:10E410009C610020AD620020A4610020F402002075
+:10E42000D062002019D00008D462002058D401081E
+:10E43000B4610020A161002070B5C2B02049214D17
+:10E44000214C4C22064601A802F042FDB8220021D0
+:10E4500014A802F043FE1C48FFF7E8FD2860E0B96D
+:10E4600001AB21464FF4807213F8010B01F8010B48
+:10E47000013AF9D13046FFF77FFE84F83A00304682
+:10E48000FFF77AFE94F83A3084F83B00A0712968CF
+:10E490000D486371FFF710FE28600B48FFF78EFEF2
+:10E4A0000A4B1B78012B0A4B1DBF01221A60094B36
+:10E4B000022216BF7E221A601A7042B070BD00BFE1
+:10E4C000EF1C02087460002078600020F4C900206E
+:10E4D000FCC900203D03002038B5454B1A7803469F
+:10E4E000044603F8042F434A00F1140112F8010B0B
+:10E4F00003F8010F8B42F9D13F4B404D1B786375F8
+:10E500003F4B1A783F4B1B7803F03F0303EB82131A
+:10E51000A3753D4B1B78E3753C4B1B7823763C4B36
+:10E520001B7863763B4B04F11A011868FAF7ABF8D5
+:10E530002B7FA377286804F11F01FAF7A4F8E86895
+:10E5400004F12301FAF79FF8334B04F1270118680F
+:10E55000FAF799F86B7DA86984F82B3004F12C0147
+:10E56000FAF791F82B7D286984F8303004F13101F5
+:10E57000FAF789F8294B04F135011868FAF783F89E
+:10E58000274B1B7884F83930264B1A795B7984F84D
+:10E590003B30254B84F83A201B7884F83C30234BE1
+:10E5A0001B7884F83D30224B1B8884F841301A0ACE
+:10E5B000204B84F84020B3F9002093F9013084F80F
+:10E5C00042301D4B84F843201B7884F844301B4BA9
+:10E5D0001B7884F845301A4B04F146011868FAF7A5
+:10E5E00052F8184B1B78103B84F84A3038BD00BFF6
+:10E5F000F4C900209A6200203C030020AC63002094
+:10E60000A06100209962002088620020AA62002098
+:10E61000AC620020B4610020B0610020B86100202D
+:10E62000F5C90020A8610020876200202403002093
+:10E630009E6100209C610020AD620020A16100204D
+:10E64000A4610020F402002010B50B4B0B4C1A788B
+:10E650000AB19B783BB90A490A4803F0AFF9FAF7C7
+:10E660004FFA206810BD0848FFF736FF21680648BA
+:10E67000FFF722FD2060F4E79A620020746000201A
+:10E68000D21C0208146300207860002037B5194CB2
+:10E69000194D4FF4165300930F22002302212046F8
+:10E6A000F2F7B0F92046154C15492A46F3F7B6FAA9
+:10E6B0002046F2F7DFFB2046124B40F8283B1022A1
+:10E6C000002102F00BFD012384F838300E4B23604B
+:10E6D00020460E4C0E492A46F3F7A0FA2046F2F7E0
+:10E6E000B2FB0C492A46204603B0BDE83040F3F7A0
+:10E6F00095BA00BF00CA002088010020F0830020E6
+:10E70000A509000834D5010848D50108B0620020E9
+:10E71000590D00087F0D0008036811B1826813606D
+:10E720007047C268FBE7704710B50446F3F7A6FAD6
+:10E73000204610BD38B51C2204460D46002102F0CB
+:10E74000CDFC20462946F2F713FC204638BD0000D8
+:10E750002DE9F04FC82091B0F3F76DFBB048B14FF1
+:10E76000B14EDFF874A3DFF87483B04CDFF870B3F8
+:10E77000DFF87093AE4D4FF46121F2F77DF9AD4AA9
+:10E78000AD49AE48F2F7D4FF08A8F2F75CFBAC4BFA
+:10E79000AC4A1F60AC4B1360AC4A1E60C3F804A0C7
+:10E7A0009A60AB4BAB4A1E601360C3F80480AA4B5F
+:10E7B000AA4A9A60AA4AC3F800B01360C3F804904A
+:10E7C0001C615D61A74BA84A1A60A84AA84BA949D9
+:10E7D00011603846A84A1A60F9F7D0F9304600228D
+:10E7E0000821F1F787FF002258460821F1F782FF40
+:10E7F0003046A249F1F79EFFA1495846F1F79AFF2A
+:10E80000984BA04A186801900026167056709670B2
+:10E81000D670167156719671F3F732F83146019839
+:10E82000994EF8F7FBFBF3F757F8914B1B68DA6842
+:10E830001B681360E36822681A60F36832681A6024
+:10E84000DAF80830DAF800201A60D9F80830D9F878
+:10E8500000201A60D8F80830D8F800201A60AB6899
+:10E860002A681A601420F3F7E6FAFCF76FF9874B71
+:10E8700022681860A368DFF8E8911A60704BCDE950
+:10E880000137704F4FF00708B346AA46C820F3F788
+:10E89000D2FA626865481168226811420CBF0121F2
+:10E8A0000021FFF739FF72681168326811420CBF0E
+:10E8B000012100215846FFF72FFF6A6811682A6876
+:10E8C00011420CBF012100215046FFF725FFB8F18E
+:10E8D0000108DBD1E26821681160F26831681160DB
+:10E8E000AA682B6813606A4802F06EFC694B6A489C
+:10E8F000C3F80080694BC3F80080694BC3F80080FF
+:10E90000F2F790FA6448F2F74AFAFEF7ABFA654B71
+:10E91000444608F10108B8F5005F03F8014BF8D14F
+:10E92000614802F051FC614BC3E90044C3E9024471
+:10E93000C3E904449C61554B03931A68002A00F014
+:10E9400009815B4802F040FC6420F3F774FA5948EF
+:10E95000FFF772FDD9F80000FDF7B4F9FDF72EFEC0
+:10E96000012840F0F9805449544803F027F8FAF799
+:10E97000C7F83868524CFFF7A5F90220F3F75BFAA5
+:10E980004620FEF765FDD9F80000FDF77BFE10225A
+:10E99000002C40F0018121460DEB020002F09EFBAD
+:10E9A0002E4804A9F1F717FE079B13B19B6804A832
+:10E9B0009847444B1B7823B1012200211046FEF7F3
+:10E9C000D5F941493D4802F0F9FFFAF799F808A84E
+:10E9D000F2F7E5F90025A9462C46A8464FF0640B4E
+:10E9E0003A4B1B78012B40F0E080394B1B78022B0F
+:10E9F00040F0DB80FBF734FC3868F9F7EBFEFEF7FC
+:10EA00002BFE039B1B68012B01D1FCF72BF808A8F8
+:10EA1000F2F704FA2F4B984282466ED964E000BFA9
+:10EA200000CA00208C630020C8CD0020CCCB002081
+:10EA300090CC002068EE0108F31D02084CCA0020AB
+:10EA4000ACCC0020F0C90020B0CC0020B0CB00201E
+:10EA5000D8CC002030840020C0CC002060CB002027
+:10EA6000DC620020D462002044CB0020D062002071
+:10EA7000D8620020F4CA002004CC0020002D31010F
+:10EA80008096980080620020E8CB002038030020A8
+:10EA900086EB0108DC630020B0620020D863002010
+:10EAA000E0830020E063002080EB0108BC610020CF
+:10EAB000031E020820CC0020341E0208146300202C
+:10EAC000D1CC00088762002066EF0108F4C900205D
+:10EAD000A161002090290A00A0CA0020D8CA002005
+:10EAE000E0CC0020BCCA0020013408A8F2F79AF953
+:10EAF000022C5EDDFBF77CF80024BBF1010B7FF4F8
+:10EB00006FAF434B1B78002B6DD0424B1B78012B12
+:10EB100065D14148CAF3C041FFF7FEFD3F4B1B786A
+:10EB200033B101350A2D03DD3868FBF7D3F9002531
+:10EB3000FBF732FB029B1B7F012B7FF44FAF344B63
+:10EB40001B78002B7FF44AAF019B39681868F9F7EE
+:10EB50007DF943E73248F5E63249334802F02EFFAB
+:10EB6000F9F7CEFFD9F80000FCF7D6FF41F2883064
+:10EB7000F3F761F9FBF710FB00287FF4FAAEBFF35F
+:10EB80004F8F2A492A4BCA6802F4E0621343CB60D4
+:10EB9000BFF34F8F00BFFDE700210DEB020002F035
+:10EBA0009DFA244B04940793FAE63868FCF7A0F822
+:10EBB00022E7012C20D1204B1B6809F101094B45AC
+:10EBC0009BDC00F05DFD4FF0000996E71B4B012236
+:10EBD0001A600224FDF7A8FD4FF000088DE7F368E6
+:10EBE00032681A609AE7164A33681268022A0CBF24
+:10EBF000B268F268136091E7F9F79AFC08F101082E
+:10EC00003868FEF7F7FFB8F10F0FDFDC022474E776
+:10EC1000F4C90020AB620020E8CB00203C030020B8
+:10EC20001A1E0208481E02081463002000ED00E0CE
+:10EC30000400FA0558D4010834030020EC620020D7
+:10EC4000FCC9002008B50348F1F752FBBDE80840B5
+:10EC5000F3F72EB9AC0E002008B50448F1F748FBD5
+:10EC6000BDE808404FF0FF31F3F71FB9AC0E0020AC
+:10EC70003C4B2DE9F3411C26184632463A4D3B4C9D
+:10EC8000DFF82881002102F029FA0A21F2F75BF966
+:10EC90000A212846F1F71CFC224641462846F2F795
+:10ECA000BDFF09213248334DFFF744FD01213248B1
+:10ECB000FFF740FD314B2B602846FFF7CDFF0021C9
+:10ECC000281DF5F795F92846FFF7BCFF22462C4989
+:10ECD0002846F2F7A3FF11212A482B4DFFF72AFD02
+:10ECE0000C212A48FFF726FD294B32461846002101
+:10ECF00002F0F4F90821F2F726F9264E26484FF0E3
+:10ED0000FF370B21FFF716FD13230097142215215F
+:10ED10002846F1F75FFD2246314628461F4DF2F79F
+:10ED20007DFF10211E48FFF705FD03212846F1F75E
+:10ED3000CFFB2246414628461A4DF2F76FFF0421C9
+:10ED40001948FFF7F7FC00970523062207212846FC
+:10ED5000F1F740FD22463146284602B0BDE8F041B9
+:10ED6000F2F75CBF44CB0020F4CA002088010020E9
+:10ED700004CC002020CC002090CC0020701E020883
+:10ED800027E70008CCCB0020C8CD0020E8CB00202E
+:10ED9000B0CB002085080008A0CA002060CB00206E
+:10EDA000D8CA0020E0CC0020BCCA002051050008D1
+:10EDB000F7B504460E46104669461F461546F9F754
+:10EDC00062FC194B1B782BB97F2C05D117483146B3
+:10EDD00003F044F803B0F0BD062CFBD81448F2F75A
+:10EDE0001DF8144B43F824001348144B02223146FB
+:10EDF00000EB04101A5503F031F8114B9DF8202058
+:10EE000043F824500F4B43F824700F4B23F8142081
+:10EE10000E4BBDF8242023F814200D4BBDF92820FB
+:10EE200043F82420D6E700BFF4C9002089620020FF
+:10EE3000B062002064620020F46100208062002043
+:10EE4000BC610020D8610020FE620020F06200203A
+:10EE500038840020254BDFF8A0C02DE9F047054697
+:10EE60001868234B234F1C68044461462346002244
+:10EE700011F8016B36B157F82260864202D3B342D3
+:10EE800028BF33460132072AF2D11B1A1A4FDFF886
+:10EE900064E0DFF86880AB4238BF4FF0FF300023FA
+:10EEA00017F8012BE2B15EF8232058F82310114423
+:10EEB000814215D2E1462246002619F801ABBAF18B
+:10EEC000000F06D05EF826A08A4502D3524528BF1F
+:10EED00052460136072EF0D1521AAA4228BF0846E0
+:10EEE0000133072BDCD1BDE8F08700BFB8610020FB
+:10EEF000B0610020BC61002080620020D861002049
+:10EF0000F8B50446324B14F8112B1A700746462008
+:10EF1000FEF79EFA2046F9F7ABFB2E4C05466668D5
+:10EF2000606007F11500F9F7A3FBA368834241D1A4
+:10EF3000751B18BF012507F11901A060264802F0D2
+:10EF40008DFF07F12900F9F793FB236820608342C6
+:10EF500018BF012507F12D00F9F78AFBE368227D30
+:10EF6000E060834218BF012597F83130237507F11F
+:10EF700032009A4218BF0125F9F77AFB2369627DB6
+:10EF80002061834218BF012597F83630637507F179
+:10EF900037009A4218BF0125F9F76AFBA36983423B
+:10EFA0000AD0A061F9F750FD0A48F8F7E7FDFEF72F
+:10EFB0001BFE03E00125BEE7002DF3D1074B022223
+:10EFC0001A60074A00231360064A1360F8BD00BFA9
+:10EFD0003D0300208C63002089620020FCC90020D2
+:10EFE000BCCF0020B8CF0020044B1870044B032284
+:10EFF0001A60044B00221A60704700BFE0620020D4
+:10F00000FCC90020BCCF0020044B05221A60044B31
+:10F010007E2246201A70FEF71BBA00BFFCC90020F2
+:10F020003D0300200A4B1B787BB90A4B0A491B7829
+:10F0300003F07F028A5C1344DBB2084A13701E237C
+:10F040005370074B02221A607047FF23F5E700BF99
+:10F05000F4C900203D03002044040020B0CE00206D
+:10F06000B4CF00202DE9F041164DDFF864802C6804
+:10F07000FF2308F8043008EB040300200234587022
+:10F080002C60FBF72DFC0746B8B9452C0E480F4EF7
+:10F09000B8BF4524F1F7C2FE000C30702046FBF7E4
+:10F0A0008BFA59387070F11C22464046B770FBF756
+:10F0B00025F9C11C3046FBF76FFB00232B60BDE830
+:10F0C000F08100BFB4CF0020B0620020E8CF002064
+:10F0D000B0CE0020F8B50D4C236806460D460BB99E
+:10F0E000FFF7A0FF20680A4F4319F72B08DC3146D1
+:10F0F0002A46384401F0ECFE216829442160F8BD1D
+:10F10000FFF7B0FFFFF78EFF2068F0E7B4CF0020D5
+:10F11000B0CE00202DE9F843154CBDF82460A07056
+:10F120001F46012390462370E01C1E23BDF9285082
+:10F130009DF82090637002F091FE002304F113010A
+:10F140004046A374F9F79FFA04F117013846F9F71E
+:10F150009AFA2677A577360A2D1284F81B906677DF
+:10F16000E57720462021BDE8F843FFF7B3BF00BF95
+:10F17000C0CF00202DE9FF41294B1C78002C32D054
+:10F180000024CDE90144274A009412682649274DFE
+:10F19000274E284FDFF8C08023467F20FFF7BAFFB5
+:10F1A00015F8013BCBB1244B0A2253F8243093FBD2
+:10F1B000F2F31BB20293214B57F8242033F814309A
+:10F1C00001931F4B33F814301B0A009308EB041112
+:10F1D00056F82430E0B2FFF79DFF0134072CDFD151
+:10F1E00004B0BDE8F081174B1B68022BF8D1164B19
+:10F1F00002941B880193154B0A4D1B781448009309
+:10F20000D5E9012308490078FFF784FFCDE90144DF
+:10F2100000942A680F4923467F20FFF77BFFDFE732
+:10F22000F4C900208C6300209A62002080620020D4
+:10F23000D8610020BC61002038840020F0620020EA
+:10F24000FE620020FCC90020E2620020E46200208F
+:10F250003D03002089620020F46100202DE9F84F71
+:10F26000DFF8B09107460E4698464FF0FF35002470
+:10F27000CA464946384602F087FC002808BF2546A2
+:10F280000134072C09F11009F3D1691CDFF888B1AA
+:10F2900079D0594A1BF8059052F82510B1420ED189
+:10F2A000012156480BF80510F1F7B8FD524A5449B0
+:10F2B00052F8252041F82500B242ECB21CD00022C1
+:10F2C00030460BF80520FFF7C5FD421C7FD0ECB29D
+:10F2D0004C4B43F82400484B012239460AEB0410FA
+:10F2E00043F824600BF8042002F0B8FD4348F1F71E
+:10F2F00095FD434B43F82400B9F1000F03D141467B
+:10F300002046FDF76FFE404D06232B7039463B2308
+:10F31000E81C6B70AC7002F0A1FD3A4B05F11301D3
+:10F3200053F82400F9F7AFF9334B05F1170153F8FF
+:10F330002400364CF9F7A7F9354905F11B0002F016
+:10F340008DFD206805F12B01F9F79DF9E06805F1C5
+:10F350002F01F9F798F9237D206985F8333005F1FD
+:10F360003401F9F790F9637DA06985F8383005F12B
+:10F370003901F9F788F93D212846FFF7ABFEBDE8D2
+:10F38000F84FFFF76FBEFF2406221BF8021001B9E9
+:10F39000D4B2013AF9D2FF2C2CD03046FFF75AFDF7
+:10F3A000431C14D0174B43F82400134B0122394659
+:10F3B0000AEB041043F824600BF8042002F04EFD21
+:10F3C0000E48F1F72BFD0E4B43F8240097E702257A
+:10F3D0000D4C0723237039462123A01C637002F0D3
+:10F3E0003DFD0B49A57404F1130002F037FD232104
+:10F3F0002046C2E70325EBE7D8610020B062002079
+:10F4000064620020BC61002064D100208C63002075
+:10F410009A620020F46100208062002010B50D4C3B
+:10F420000D4905232370A01C1523637002F016FDFF
+:10F430000A4B04F112011868F9F725F9084B204628
+:10F440001B78A3751721FFF745FEBDE81040FFF7B5
+:10F4500009BE00BFC0CF00209A620020B461002026
+:10F46000AC62002010B50A4C0A490B23237011230B
+:10F470006370094BE01C1B78A37002F0EFFC204680
+:10F480001321FFF727FEBDE81040FFF7EBBD00BFDB
+:10F49000C0CF00209A6200203D03002010B5084C28
+:10F4A0000C232370A0701123E01C637002F0D6FCC3
+:10F4B00020461321FFF70EFEBDE81040FFF7D2BD36
+:10F4C000C0CF00202DE9F041DFF8488005460C460A
+:10F4D0004FF0FF3600274146204602F055FB00283A
+:10F4E00008BF3E460137072F08F11008F3D1731CFF
+:10F4F00018BF074B214628461CBF00229A55FFF72C
+:10F50000CDFF21462846BDE8F041FFF7C7BF00BF49
+:10F5100080620020F46100202DE9F04F2DED028B78
+:10F5200089B008EE102ADFF85081DFF850A105916C
+:10F530000546022400272E1915F804B073780493A9
+:10F540000BF1FF330B2B2FD8DFE803F0062E2E2E06
+:10F550003E54652E2E2E7681E11C294404F11300C1
+:10F5600096F80290CF7328440791F9F781F8069036
+:10F5700004F117002844F9F77BF896F81FC00346FA
+:10F58000B07F00EB0C2000B20290707F96F81CC098
+:10F590000CEB002C1FFA8CF00190F07E0090DDE95E
+:10F5A00006214846FFF704FC049B23441C46BBF19C
+:10F5B000FF0F04F1020402D0059B9C42BBDB09B0A3
+:10F5C000BDEC028BBDE8F08F04F10209A94404F1FF
+:10F5D000120089F80F702844F9F74AF898F80030BB
+:10F5E0000146002BE0D018EE103AB27D4846FFF7F6
+:10F5F00035FED9E7E01C284498F80030C773002B8B
+:10F60000D2D1514602F0C0FA0028CDD1A01C284426
+:10F61000FFF776FCC8E7A01C284498F80030C773B1
+:10F62000002BC1D15146B67C02F0AEFA0028BBD106
+:10F630003046FFF7D9FCB7E7E11C294498F80030C1
+:10F64000B078CF73002BAFD0FFF73CFFACE796F854
+:10F65000029098F80030E61C2E44F773002BA3D1DB
+:10F660005146304602F090FA00289DD13146484676
+:10F67000FFF7CAFC98E700BFF4C900209A62002097
+:10F680002DE9F043534F97F8009085B0B9F1000F82
+:10F6900014D05148F1F7C2FB0023504A50491C4690
+:10F6A00012F8015B012D05D151F82350854218BF96
+:10F6B00002F8014C0133072BF2D177E0494D4A4C57
+:10F6C0002B68DFF84C81012B37D12368022B46DDF4
+:10F6D000FFF7A4FE4048C4F80090F1F79FFB434BAE
+:10F6E0001B68C01A424B1B68984226D9414E102213
+:10F6F000002E66D13146684601F0F0FC3E4EF2F72E
+:10F70000BFF8736B23B996F838300BB1F1F79CFC56
+:10F710003A48F0F7BDFD039B1BB15B68374869466B
+:10F720009847039B3448364A73630023F1F7A1FAE4
+:10F73000F2F7D2F86846F0F7ABFD2B68022B04D144
+:10F740002368052B0EDDFFF769FE2B68032B06D11E
+:10F7500023680F2B1EDDFFF761FE002323602B685B
+:10F76000022B0DD1D8F800300A2B13DD01232B60BA
+:10F77000FBF716FA234B7E2246201A70FDF768FE2F
+:10F780002B68042B06D12368022B03DDFFF76AFEEA
+:10F7900000232360236801332360D8F8003001334D
+:10F7A000C8F800303B78002B7FF473AFFFF7E2FC22
+:10F7B000154B1B68002B01DDFFF754FC05B0BDE8BD
+:10F7C000F0834946684601F089FC104B009603938C
+:10F7D00094E700BFF4C90020B062002080620020DE
+:10F7E00064620020FCC90020BCCF0020F8C90020C2
+:10F7F0002C03002039C80008F08300201884002062
+:10F8000020A107003D030020B4CF002058D40108F8
+:10F81000B8CF002010B502FB01F1F1F7A7FF0446B5
+:10F8200068B150F8042C22F00302043A242A18D8B4
+:10F83000132A06D802460023C2E90033936020460B
+:10F8400010BD00231B2AC0E900330FD9242AC0E9C8
+:10F8500002330ABFC0E9043300F1100200F11802BC
+:10F86000E9E7002101F03AFC204610BD00F1080252
+:10F87000E1E700BF014B1868704700BFC8040020D3
+:10F8800070B539B10C46054608B1836B83B3B4F942
+:10F890000C3013B90026304670BD2146284600F0D2
+:10F8A0003BF8E36A064633B1E169284698470028E9
+:10F8B000B8BF4FF0FF36A3891B0620D4216B41B19E
+:10F8C00004F14003994202D02846F1F753FF002388
+:10F8D0002363616C21B12846F1F74CFF0023636478
+:10F8E00000F0B6F90023A38100F0B4F9304670BDF2
+:10F8F00000F0AAF9B4F90C30002BCBD0CDE7216988
+:10F900002846F1F737FFD9E7024B01461868FFF7A1
+:10F91000B7BF00BFC8040020B1F90C202DE9F041A9
+:10F920000D461107804647D46B6842F40062002BF5
+:10F93000AA815DDDAC6A002C57D00023D8F80060A6
+:10F94000C8F8003093B212F4805255D10123E9690E
+:10F950004046A047431C66D0AB89AC6A5F0705D51B
+:10F960006A682B6B801A0BB1EB6BC01AE96902460F
+:10F9700000234046A047411C40D1D8F80030002B5E
+:10F980003CD01D2B01D0162B55D1AB892A692A609A
+:10F9900023F400630022AB816A60296BC8F8006021
+:10F9A00019B305F14003994202D04046F1F7E2FE57
+:10F9B00000202863BDE8F0812F69B7B193B22E68AB
+:10F9C0002F609A070CBF6B690023F61BAB600AE03F
+:10F9D0006C6AE96933463A464046A047041EA6EBE6
+:10F9E0000406274417DD002EF2DC0020BDE8F0817C
+:10F9F000EB6B002B9EDCF8E7286DAFE7B5F90C3018
+:10FA00002A692A6023F400630022AB81DB046A6068
+:10FA1000C3D52865C1E7AB8943F04003AB814FF004
+:10FA2000FF30BDE8F081D8F80030002B94D01D2BBA
+:10FA300006D0162B04D0AB8943F04003AB81D5E749
+:10FA4000C8F80060D1E700BF38B50D46044608B1DC
+:10FA5000836B1BB1B5F90C0030B938BD00F0F4F878
+:10FA6000B5F90C000028F8D029462046BDE83840FA
+:10FA7000FFF752BF014618B1044B1868FFF7E4BF07
+:10FA8000034B0449186800F007BE00BFC8040020FB
+:10FA9000801E020849FA000800207047014900F062
+:10FAA000FBBD00BF81F800082DE9F84F45682C4BDD
+:10FAB000C3630024074600F53B7204230321C0E919
+:10FAC000B912C0F8E0422146EB60C5E90044C5E93F
+:10FAD000044405F15C006C66AC60AC61082201F086
+:10FAE000FDFADFF888B0BE68DFF884A0DFF8849004
+:10FAF000DFF884801B4BC5F82C80C5E9075BC5E99E
+:10FB000009A92146F3600822C6E90044C6E9044475
+:10FB100006F15C007466B460B46101F0DFFAFD6860
+:10FB2000114BC6F82C80C6E9076BC6E909A9214626
+:10FB3000EB60C5E90044C5E904446C66AC60AC61A7
+:10FB400005F15C00082201F0C9FA0123C5E9075B51
+:10FB5000C5E909A9C5F82C80BB63BDE8F88F00BFD3
+:10FB60009DFA00080900010012000200B11A010804
+:10FB7000D91A0108191B0108391B01080020704718
+:10FB800070B54A1E682505FB02F50E4605F17401A5
+:10FB9000F1F7ECFD044640B100210C30666005F140
+:10FBA00068022160A06001F099FA204670BD00BF94
+:10FBB000F8B51E4B1E68B36B074643B306F538769F
+:10FBC000D6E90134013B04D51DE05A1C04F1680458
+:10FBD00019D0B4F90C50013B002DF6D1144B6566D9
+:10FBE000C4E90055C4E90455A560A561E360082295
+:10FBF000294604F15C0001F071FAC4E90C55C4E92E
+:10FC000011552046F8BD34682CB12646D8E7304659
+:10FC1000FFF74AFFD2E704213846FFF7B1FF044659
+:10FC200030600028F1D10C233B60EAE7801E020817
+:10FC30000100FFFF024B0349186800F02DBD00BF13
+:10FC4000801E020881F80008836B03B170472BE720
+:10FC5000704700BF704700BF704700BF704700BFCC
+:10FC6000024B0349186800F0F7BC00BFC80400202D
+:10FC700099FA0008024B0349186800F0EDBC00BF78
+:10FC8000C80400207DFB000838B5084B084D5B1BFD
+:10FC90009C1007D0043B1D44013C55F8043998479B
+:10FCA000002CF9D1BDE838400DF098BB900E002033
+:10FCB0008C0E0020F0B583B00D46114601AA074610
+:10FCC00007F016F9F0B106463846FFF771FF044613
+:10FCD000C0B14FF4DB73019A2946384601F04EFA61
+:10FCE000031E1CDB12481349134AE381134BE362E2
+:10FCF000F305C4E90740C4E90912A68106D42046E9
+:10FD000003B0F0BD0024204603B0F0BD3846022306
+:10FD10000022214600F070F9204603B0F0BD002516
+:10FD2000FFF796FFA581FFF795FF2C46E7E700BF99
+:10FD3000B11A0108D91A0108191B0108391B010859
+:10FD4000024B0A4601461868FFF7B4BFC8040020FA
+:10FD5000F8B5244F0C460646F1F788FFBB685D688E
+:10FD6000C4F57E610F3125F003054B1923F47F6341
+:10FD700023F00F03A3F58054B4F5805F07DB002167
+:10FD8000304601F037FDBB682B44984204D0304622
+:10FD9000F1F770FF0020F8BD6142304601F02AFD06
+:10FDA00001300DD0104AB96813682D1B45F00105CC
+:10FDB00030461B1B4D601360F1F75CFF0120F8BD5E
+:10FDC0000021304601F016FDBA68831A0F2BDEDDE4
+:10FDD000064C0549246843F00103001B536008608A
+:10FDE000D5E700BFF8080020A4D10020000D0020B6
+:10FDF00000295ED0F8B50C460646F1F737FF54F8F7
+:10FE0000043CDFF8F0C123F00101A4F1080042181E
+:10FE1000DCF808705568974225F0030500F08880EB
+:10FE2000DF07556033D454F8087CC01B0CF108047C
+:10FE30008368A342394469D05719D0F80CE07F6831
+:10FE4000C3F80CE0CEF80830FB0740F1968041F093
+:10FE5000010343601160B1F5007F33D2CB08DCF8B9
+:10FE6000044001334A090121914021430CEBC302B4
+:10FE70005CF83340CCF80410083AC0E902424CF870
+:10FE80003300E0603046BDE8F840F1F7F3BE5319A7
+:10FE90005B68DF070ED429440CF108049368A34281
+:10FEA00073D0D468DC6041F00102A360426041502D
+:10FEB000D1E7704741F00103B1F5007F44F8043CFD
+:10FEC0001160CBD3B1F5206F4FEA51234AD28B0991
+:10FED00003F13905ED0003F138025CF805300CEB55
+:10FEE0000504083C9C4259D05A6822F003028A4219
+:10FEF00002D99B689C42F7D1DC68C0E90234A0605B
+:10FF0000D8603046BDE8F840F1F7B4BE53195B68DD
+:10FF1000DB0766D4D2E90223294441F00104D3600F
+:10FF20009A60446041503046BDE8F840F1F7A2BE07
+:10FF3000DB07294407D454F8083CC01A1944D0E917
+:10FF40000223D3609A60294B1B6841F001028B4267
+:10FF50004260CCF8080095D8254B30461968FFF769
+:10FF6000F7FE8FE7142B0AD9542B21D80B0B03F182
+:10FF70006F05ED0003F16E02AFE729448EE703F150
+:10FF80005C05ED0003F15B02A7E741F00103CCE95A
+:10FF90000400C0E902444360415073E7DCF80410F8
+:10FFA0009210012505FA02F20A43CCF80420A4E7D6
+:10FFB000B3F5AA7F06D8CB0B03F17805ED0003F16A
+:10FFC00077028AE740F25452934206D88B0C03F131
+:10FFD0007D05ED0003F17C027FE74FF47E757E2204
+:10FFE0007BE741F00103436011604BE7040D002003
+:10FFF000A0D10020F808002000F00CB830B4044C68
+:020000040801F1
+:100000000D46134601462A46206830BC00F002B86F
+:10001000C80400202DE9F04F0C4697B017461E4645
+:10002000054608B1836BC3B1A38903F48473B3F5A8
+:10003000847F1AD0D4F82890B9F1000F00F0238102
+:10004000012E17D036F002085BD016232B604FF03C
+:10005000FF38404617B0BDE8F08FFFF7F5FDA389E4
+:1000600003F48473B3F5847FE4D121462846FFF777
+:10007000EBFCDFE72146284600F02EF9B0F1FF3F08
+:100080008046E4D02369B34607440026002B3CD0C9
+:10009000B4F90C3040F61A02134299B207D1480560
+:1000A00051D47B4A914535D043F40063A381214666
+:1000B0002846FFF7C9FC80460028C8D1E1693346CD
+:1000C0003A462846C8470130C1D0216B41B104F1FE
+:1000D0004003994202D02846F1F74CFB00232363EA
+:1000E000A3892269226023F402630021A381616055
+:1000F00004F15C00082200F0F1FF404617B0BDE8B3
+:10010000F08F2369C346002BC2D12146284600F058
+:1001100079FBBDE7B4F90E100029C5DB6A46284615
+:1001200000F0C4F8002840F09580019B03F4704370
+:10013000B3F5004F40F08E80A3894FF4806243F402
+:100140008063A381E264002E5DD1BA46BBF1000F4B
+:1001500068D1A389D90474D5236D6068216BA3EBA2
+:1001600000080346002964D0D4F83CC0A8EB0C0872
+:10017000A36B226980449B1AA8EB03086344C24521
+:1001800003DB08EB0300504567D8E26CE16952429B
+:1001900002EA0A08424600232846C847013086D0B2
+:1001A0002369216B23600023636041B104F14003A4
+:1001B000994202D02846F1F7DDFA00232363A38990
+:1001C000BAEB080A23F02003A38110D02146284669
+:1001D00001F064FA00287FF46AAF63685345FFF4C6
+:1001E00066AF2268A3EB0A035244C4E9002304F17A
+:1001F0005C000822002100F071FF4FF0000840462B
+:1002000017B0BDE8F08FB4F90E106A46284600F02A
+:100210004DF800287FF44BAF049B07EB030ABBF1BA
+:10022000000F96D0216B19B16068D4F83CC09FE7ED
+:10023000636821682269891AA8EB01080B44002130
+:100240009DE75A460123E1692846C847421C0346F8
+:1002500083D12CE7B4F90C3026E7AAEB0808424416
+:10026000A3EB0803C4E9002341B104F14003994220
+:1002700002D02846F1F77EFA00232363A38923F0F6
+:100280002003A381B3E71D232B604FF0FF38E0E686
+:10029000191B010830B4044C0D46134601462A468A
+:1002A000206830BCFFF7B6BEC804002038B50C4645
+:1002B000084D03461146204600221C462A60F1F7ED
+:1002C0004DFC431C00D038BD2B68002BFBD02360B5
+:1002D00038BD00BF00E6002070B50C46054608B1E9
+:1002E000836B33B3A66A002E39D0A38903F00C02C6
+:1002F000082A21D013F480520FD1E1692846012346
+:10030000B047411C28D0A3895A0709D56268236BDE
+:10031000801A0BB1E36BC01A70BD5A07206DF5D47B
+:100320001B07F9D52368002BF6D022699B1A1844C5
+:1003300070BDFFF789FCD5E72268002ADAD0216971
+:10034000521A002AD6DDDA05D4D52846E1690223FF
+:100350000022B047451CD6D14FF0FF3070BD1D23A1
+:100360002B604FF0FF3070BD024B01461868FFF75D
+:10037000B3BF00BFC80400209368002B00F08A8040
+:100380002DE9F04F9046B1F90C200C46110783B0CF
+:10039000814693B225D522691AB313F00207D8F823
+:1003A00000502DD00026DFF8ACB23746AA465F4594
+:1003B0003B46324628BF5B464846002F4FD0E16996
+:1003C000656AA84700285BDDD8F808301B1A064488
+:1003D0003F1AC8F80830002BE9D1002003B0BDE86F
+:1003E000F08F2146484605F0D9FC002840F02F81C7
+:1003F000B4F90C20D8F8005093B213F00207D1D111
+:1004000013F0010A48D156462EB39A05A76840F169
+:100410008C80B742BB4600F2B78013F4906F40F077
+:10042000CB80206851465A4600F0ECFDA168236855
+:10043000C91B5B443746A16023600026D8F808300A
+:10044000DB1BBA44C8F80830002BC6D0B4F90C3016
+:100450009BB2002ED9D1D5E900A60835D4E7DAE958
+:1004600000670AF1080AA2E729465A4600F0CAFDC9
+:1004700023685B44236021464846FFF7E5FA58B3FA
+:10048000B4F90C3043F040034FF0FF30A38103B0C8
+:10049000BDE8F08F002070473E46AA4638463D46EC
+:1004A00000976EB3002833D0009A2068D4E9041373
+:1004B000B24228BF3246884204D9A16803EB010B3F
+:1004C0005A45D1DC93426ADCE169676A2A464846AC
+:1004D000B847B0F1000BD3DD009BB3EB0B030093E7
+:1004E00056D00120D8F80830A3EB0B035D44A6EBEF
+:1004F0000B06C8F80830002B3FF46FAF002ED1D1A7
+:100500000AF1080353E902569A460833002EF9D03F
+:1005100032460A21284600F08BFC002800F08E802D
+:100520000130431B00931A46BFE7206823699842B5
+:1005300014D86169B14211D86FF00043B34228BFAB
+:100540003346676A93FBF1F3524601FB03F34846D7
+:10055000E169B847071E93DDF61B6FE7B74228BF76
+:1005600037463A46514600F04DFDA3682268DB1B32
+:100570003A44A3602260002BEED121464846FFF7A3
+:1005800063FA0028E8D07BE720683746B34649E79E
+:1005900021464846FFF758FA0028A3D070E72946BD
+:1005A000019200F02FFD019AA1682368891A134473
+:1005B000A160236093468FE7D4E90417226807EB14
+:1005C0004707A2EB010B07EBD7770BF101007F1078
+:1005D0003044B8423A4684BF07463A465B051BD5CD
+:1005E00011464846F1F7C2F858B35A4621690090BF
+:1005F00000F06EFCA289009B22F4906242F080021F
+:10060000A281A7EB0B0203EB0B0067612361206063
+:10061000A2603746B34605E74846F1F7A9F8034616
+:100620000028EED121694846F1F7A4F8B4F90C305E
+:100630000C2223F08003C9F8002023E7721C0092EB
+:1006400033E70C23C9F80030B4F90C301AE74FF047
+:10065000FF30C3E600FCFF7F2DE9F04100F538775D
+:1006600088460026D7E90154013D0FD4A389012B08
+:1006700005F1FF3506D9B4F90E30013302D020461A
+:10068000C04706436B1C04F16804EFD13F68002F9C
+:10069000E8D13046BDE8F0812DE9F84307468846A9
+:1006A00000F538764FF00009D6E90154013D11D428
+:1006B000A389012B05F1FF3508D9B4F90E300133B8
+:1006C00004D021463846C04749EA00096B1C04F1B2
+:1006D0006804EDD13668002EE6D14846BDE8F883BF
+:1006E00038B50D46044608B1836B4BB16B68013BCE
+:1006F000002B6B600BDB2B685A1C2A60187838BD06
+:10070000FFF7A2FA6B68013B002B6B60F3DA294616
+:100710002046BDE8384001F04BB800BF38B50F4B5C
+:100720001D6804460DB1AB6B4BB16368013B002BF8
+:1007300063600CDB23685A1C2260187838BD284699
+:10074000FFF782FA6368013B002B6360F2DA21460F
+:100750002846BDE8384001F02BB800BFC80400208F
+:1007600070B50D4E0D4D761BB61006D0002455F811
+:10077000043B01349847A642F9D1094E094D761B36
+:100780000CF026FEB61006D0002455F8043B0134C8
+:100790009847A642F9D170BD780E0020780E00204F
+:1007A0008C0E0020780E002070B50C46B1F90E10AA
+:1007B000002996B015461E4614DB6A46FFF776FD03
+:1007C00000280FDB019A02F47042A2F50052B2FA3F
+:1007D00082F252094FF480634FF4006032602B6064
+:1007E00016B070BDA189002311F08000336004D0E1
+:1007F000402218462A6016B070BD4FF480632B600B
+:1008000016B070BD70B58B899D0782B00C4607D5B8
+:1008100001F143030122C1E904320B6002B070BD53
+:1008200001AB6A460646FFF7BFFF00990546304612
+:10083000F0F79CFF80B1B4F90C20174BF3630199DA
+:10084000206042F08003009AA381C4E9040299B9B0
+:100850002B43A38102B070BDB4F90C309A05DDD4EE
+:1008600023F0030304F1430243F002030121C4E92E
+:100870000421A3812260D1E7B4F90E10304606F0BE
+:1008800075FB10B9B4F90C30E2E7A28922F003023B
+:1008900042F0010213B2DBE79DFA0008024B014669
+:1008A0001868F0F763BF00BFC8040020024B014680
+:1008B0001868F0F75FBF00BFC80400202DE9F04FB3
+:1008C00001F10B05162D83B0064624D8102900F23D
+:1008D000B780F1F7CBF9102502211823DFF8408506
+:1008E0004344A3F108025C68944200F0B580636859
+:1008F00023F003032344D4E902515A68E96042F02B
+:10090000010230468D605A60F1F7B4F90834204690
+:1009100003B0BDE8F08F35F0070500F19180A942E2
+:1009200000F28E80F1F7A2F9B5F5FC7FC0F0978157
+:100930006B0A00F08C80042B00F26D81AB0903F18F
+:10094000390103F13807CB00DFF8D4844344A3F125
+:1009500008005C68A04206D10CE0002A80F22981E0
+:10096000E468A04206D0636823F003035A1B0F2AF1
+:10097000F3DD3946D8F81040DFF8A8C4644577D0D5
+:10098000626822F00302531B0F2B00F37681002BC9
+:10099000C8E904CC80F26781B2F5007F80F017814E
+:1009A000D3080133500901228240D8F8040058F8D6
+:1009B0003370A76008EBC30E0243AEF10800E0609D
+:1009C000C8F8042048F83340FC608B1001209840A0
+:1009D000904254D8104206D121F003014000104249
+:1009E00001F10401FAD008EBC1094C468E46E768D4
+:1009F000BC4207D11BE1002B80F22281FF68BC4280
+:100A000000F015817A6822F00302531B0F2BF2DDF0
+:100A1000D7E902E4791945F001057D6043F001054D
+:100A2000CEF80C403046C4F808E0C8E90411C1E92A
+:100A300002CC4D60BB50F1F71DF907F1080402E04C
+:100A40000C2333600024204603B0BDE8F08F4FF440
+:100A5000007340213F2777E7DC68A34208BF0231DB
+:100A60007FF445AFD8F81040DFF8B8C3644587D1AC
+:100A7000D8F804208B10012098409042AAD9D8F8C9
+:100A80000840676827F00307BD4202D87B1B0F2B85
+:100A90007EDCDFF89493D8F80824D9F800300132CE
+:100AA00004EB070A2B4400F0358103F580530F3324
+:100AB00023F47F6B2BF00F0B5946304600F09AFE63
+:100AC000411C024600F0F280824500F2ED80D9F828
+:100AD00004105944C9F804100B4600F05381D8F8AB
+:100AE000081401311BBFA2EB0A0A5344C8F80824BA
+:100AF000C9F8043012F0070300F01A81C3F10801AD
+:100B00000A44C3F5805193440831A1EB0B01C1F3B2
+:100B10000B0A514630460193009200F06BFE421CD6
+:100B2000DDE9002300F05481831A03EB0A0BD9F8A6
+:100B30000400C8F808204BF001030AEB000144450B
+:100B40005360C9F8041000F02A810F2F40F2298168
+:100B50006368A7F10C0020F0070003F001032718D9
+:100B600003434FF0050C0F286360C7E901CC00F286
+:100B7000368153681446D9F82C208A42D9F830209F
+:100B800038BFC9F82C108A4238BFC9F8301090E03D
+:100B9000621943F0010345F0010565603046C8F86D
+:100BA00008205360F1F766F80834204603B0BDE82A
+:100BB000F08F2344E1685A68A56842F00102E960B9
+:100BC00030468D605A60F1F755F808343BE7B2F5CE
+:100BD000206F4FEA522361D3142B00F2BB8003F144
+:100BE0005C00C0005B3308EB000758F80000083FCA
+:100BF000874200F09280436823F00303934202D9B6
+:100C000080688742F7D1C768D8F80420C4E9020792
+:100C1000BC60C460D9E6142B59D9542B00F2A280D1
+:100C20002B0B03F16F0103F16E07CB008CE60EF185
+:100C3000010E1EF0030F04F108047FF4D8AE51E05A
+:100C40003A443C465368F96854F8085F43F001039E
+:100C500053603046E9608D60F1F70CF8F3E6E9087F
+:100C600005F108033AE622443046536843F0010395
+:100C700053600834F0F7FEFFE5E6611943F0010721
+:100C800045F0010565603046C8E90411C1E902CCB0
+:100C90004F60A350F0F7EEFF0834D4E6930903F158
+:100CA0003900C00038339EE7444565D0D8F8084085
+:100CB000636823F0030B5D45ABEB050302D80F2BF4
+:100CC0003FF766AF3046F0F7D5FF0024BBE603F1EF
+:100CD0005C0103F15B07CB0036E659F808394B4558
+:100CE00040F09B8011F0030F01F1FF31F5D1D8F8EE
+:100CF000043023EA0003C8F80430400098423FF66D
+:100D0000BEAE18B9BBE640000EF1040E1842FAD090
+:100D1000714668E603F1100BCEE69A104FF0010E13
+:100D2000D8F804300EFA02F21A43C8F804206DE72E
+:100D300002EB0B014942C1F30B0A514630460193C5
+:100D4000009200F057FD431CDDE900237FF4ECAE78
+:100D50009A46ECE6542B27D8130B03F16F00C00022
+:100D60006E3340E7B3F5AA7F27D8EB0B03F1780188
+:100D700003F17707CB00E7E5D9F804305B44C9F805
+:100D80000430ACE6CAF30B0000287FF4A8AED8F814
+:100D9000084007EB0B0343F001036360EBE61446E6
+:100DA000E9E6012353608DE7B3F5AA7F22D8D30B80
+:100DB00003F17800C000773315E740F254529342B4
+:100DC00022D8AB0C03F17D0103F17C07CB00BBE51E
+:100DD000083B9B44ABEB020B4FF0000AA7E604F183
+:100DE00008013046F0F7C6FCD8F80840D9F80410DE
+:100DF0006368C0E640F2545083420AD8930C03F172
+:100E00007D00C0007C33EEE64FF47E737F217E27A9
+:100E10009AE54FF47E707E23E5E6D8F804306CE75F
+:100E2000F808002000090020A0D1002000000000E8
+:100E300001F0FF01102A2BDB10F0070F08D010F88B
+:100E4000013B013A8B422DD010F0070F42B3F6D18F
+:100E5000F0B441EA012141EA014122F007047FF0A8
+:100E600000070023F0E80256083C85EA010586EAFF
+:100E7000010685FA47F5A3FA87F586FA47F6A5FA3B
+:100E800087F68EB9EED1F0BC01F0FF0102F0070247
+:100E900032B110F8013B013A83EA010313B1F8D1F2
+:100EA0000020704701387047002D06BF35460338D3
+:100EB000073815F0010F07D1013015F4807F02BF0C
+:100EC000013015F4C03F0130F0BC0138704700BF5D
+:100ED000844641EA000313F003036DD1403A41D345
+:100EE00051F8043B40F8043B51F8043B40F8043B04
+:100EF00051F8043B40F8043B51F8043B40F8043BF4
+:100F000051F8043B40F8043B51F8043B40F8043BE3
+:100F100051F8043B40F8043B51F8043B40F8043BD3
+:100F200051F8043B40F8043B51F8043B40F8043BC3
+:100F300051F8043B40F8043B51F8043B40F8043BB3
+:100F400051F8043B40F8043B51F8043B40F8043BA3
+:100F500051F8043B40F8043B51F8043B40F8043B93
+:100F6000403ABDD2303211D351F8043B40F8043B33
+:100F700051F8043B40F8043B51F8043B40F8043B73
+:100F800051F8043B40F8043B103AEDD20C3205D343
+:100F900051F8043B40F8043B043AF9D2043208D03B
+:100FA000D2071CBF11F8013B00F8013B01D30B88AD
+:100FB00003806046704700BF082A13D38B078DD08B
+:100FC00010F003038AD0C3F10403D21ADB071CBF5D
+:100FD00011F8013B00F8013B80D331F8023B20F8C7
+:100FE000023B7BE7043AD9D3013A11F8013B00F800
+:100FF000013BF9D20B7803704B7843708B78837088
+:10100000604670478842F0B40DD98B1883420AD9E4
+:10101000841832B1224613F8014D02F8014D99426D
+:10102000F9D1F0BC70470F2A0ED80346541E002A8F
+:10103000F7D001340C44013B11F8012B03F8012FC8
+:10104000A142F9D1F0BC704740EA01039B073FD1B0
+:10105000A2F1100323F00F0401F1200727441B091C
+:1010600001F1100400F1100554F8106C45F8106CF3
+:1010700054F80C6C45F80C6C54F8086C45F8086C86
+:1010800054F8046C45F8046C1034BC4205F11005AA
+:10109000EAD1013312F00C0F01EB031102F00F043F
+:1010A00000EB031317D0043C24F0030CA5089C4468
+:1010B0001C1F0E4656F8047B44F8047F6445F9D1A2
+:1010C0006C1C03EB840301EB840102F00302ADE727
+:1010D000541E0346ADE72246A8E700BFF0B48607DA
+:1010E00046D0541E002A3CD0CAB2034601E0013C5F
+:1010F00037D303F8012B9D07F9D1032C2AD9CDB2A0
+:1011000045EA05250F2C45EA054534D9A4F110021E
+:1011100022F00F0C03F120071609674403F11002B7
+:1011200042E9045542E902551032BA42F8D1721C24
+:1011300014F00C0F03EB021204F00F0613D0331F50
+:1011400023F003030433134442F8045B9342FBD1BE
+:1011500006F003042CB1CAB21C4403F8012B9C42D4
+:10116000FBD1F0BC704734461346002CF3D1F8E7AE
+:1011700014460346C1E71A462646E0E770B50C461A
+:10118000084D114600261A46034620462E601C468E
+:10119000F0F79CFD431C00D070BD2B68002BFBD0EA
+:1011A000236070BD00E600200EB400B582B003AB32
+:1011B000816853F8042B019303F066FA02B05DF8DE
+:1011C00004EB03B0704700BF0FB400B5074983B00C
+:1011D00004AB086853F8042B8168019303F054FAB8
+:1011E00003B05DF804EB04B0704700BFC8040020F2
+:1011F00070B50D461646044608B1836B7BB1B368E3
+:10120000013B002BB36011DAB069834214DBE8B212
+:101210000A2811D033685C1C34601D7070BDFEF765
+:1012200013FDB368013B002BB360EDDB33685C1C3E
+:1012300034601D70E8B270BD324629462046BDE8D4
+:10124000704004F035BD00BF164B70B51E680546F2
+:101250000C460EB1B36B7BB1A368013B002BA360BE
+:1012600012DAA269934215DBE8B20A2812D0236889
+:101270005A1C22601D7070BD3046FEF7E5FCA36865
+:10128000013B002BA360ECDB23685A1C22601D701D
+:10129000E8B270BD224629463046BDE8704004F0F1
+:1012A00007BD00BFC80400202DE9F84F17460029EC
+:1012B00000F0BC8007F10B050C468046F0F7D6FC29
+:1012C000162D5FD810252A46AF4260D854F8041C6A
+:1012D00021F003069642A4F1080980F28680C94BEA
+:1012E000D3F808C009EB0600844500F0BA80D0F8B6
+:1012F00004C02CF0010303445B68DB0700F18B8022
+:101300002CF0030C06EB0C03934280F21681CB0702
+:101310000FD454F8083CA9EB030ADAF8043023F0A0
+:1013200003018C44B444944538DA7318934280F234
+:10133000108139464046F0F719FA0746E0B154F8F3
+:10134000043C23F001034B44A0F10802934200F057
+:10135000FA80321F242A00F21D81132A00F2CE8067
+:1013600003462246116819605168596092689A6074
+:1013700021464046F0F7FEF94046F0F77BFC384640
+:10138000BDE8F88F25F00705002D2A469CDA0C23CE
+:10139000C8F8003000273846BDE8F88FD0E90223AE
+:1013A0005746D3609A6057F8081FDAF80C30CB60C4
+:1013B000321F242A996000F20881132A40F2038127
+:1013C0002368CAF808306368CAF80C301B2A00F298
+:1013D0001B8108340AF1100322681A6062685A609F
+:1013E000A2689A606646D1463C46731B0F2B22D8F2
+:1013F000D9F8043003F0010333434E44C9F80430F4
+:10140000736843F00103736040462746F0F732FCEF
+:101410003846BDE8F88FC9078BD454F8083CA9EBCF
+:10142000030ADAF8041021F003017EE7BDE8F84F63
+:101430001146F0F79BB9D9F8042009EB050102F039
+:1014400001024E4443F001031543C9F804504B60B8
+:10145000736843F00103083173604046F0F78AF97E
+:10146000D2E7DCF8040020F0030B06EB0B0C05F1CF
+:10147000100084454DDAC9073FF55BAF54F8081CEE
+:10148000A9EB010ADAF8041021F003018B44B344FC
+:1014900058453FF74AAF5746DAF80C1057F8080F8F
+:1014A000321F242AC160886000F2BC80132A40F2F7
+:1014B000B7802168CAF808106168CAF80C101B2AA6
+:1014C00000F2C08008340AF11002216811606168DE
+:1014D0005160A16891600AEB0501ABEB050242F097
+:1014E000010299604A60DAF8043003F001031D43F9
+:1014F0004046CAF80450F0F7BDFB4CE72368036090
+:10150000636843601B2A49D804F1080200F108030C
+:1015100028E709EB0501ACEB050242F001029960F6
+:101520004A6054F8043C03F001031D43404644F86C
+:10153000045CF0F79FFB27462DE7D0E902121E4618
+:10154000CA60916051E750F8043C23F003031E4445
+:101550004BE75746DAF80C1057F8080F321F242AC9
+:10156000C160886027D8132A23D92168CAF80810D7
+:101570006168CAF80C101B2A2FD808340AF110022F
+:101580002168116061685160A16891601E46D14672
+:101590003C462AE72146FFF735FDE9E6A36883606C
+:1015A000E368C360242A24D004F1100200F1100380
+:1015B000D8E63A46E4E7214638461E46D146FFF7CC
+:1015C00021FD3C4611E73B4606E721463846664684
+:1015D000D146FFF717FD3C4607E7A168CAF810108F
+:1015E000E168CAF81410242A22D010340AF1180233
+:1015F000C6E7236903616369436104F1180200F1DE
+:101600001803AFE6F8080020A368CAF81030E368B2
+:10161000CAF81430242A21D010340AF11803DBE66A
+:101620003A4652E721463846FFF7ECFC154B52E7A5
+:101630002269CAF818206269CAF81C2018340AF115
+:1016400020029DE7A168CAF81010E168CAF81410DA
+:10165000242A0DD010340AF1180236E72369CAF89B
+:1016600018306369CAF81C3018340AF12003B3E655
+:101670002269CAF818206269CAF81C2018340AF1D5
+:10168000200222E7F8080020838903F00903092BD0
+:1016900001D000207047FEF7EDB900BFF8B50C4649
+:1016A000054610B1836B002B41D0B4F90C309F0478
+:1016B0009AB207D4626E43F4005322F40052626679
+:1016C000A3819AB20021960661605AD450071BD4B8
+:1016D000D10659D512073ED443F00403A3812369F0
+:1016E000002B44D0B4F90C60B307B7B222D1226901
+:1016F0006369E16922602846256AA847002860607E
+:10170000C8BF002038DDF8BD216B0029E7D004F107
+:101710004003994202D02846F0F72CF8E36B63604F
+:1017200000202063002BDAD0A36B2360F8BDFEF706
+:101730008BFABAE71C4B1D4918680123A38107F0F7
+:101740000907FEF789FF092FA681D0D12146284637
+:10175000FEF7E2F8CBE721462846FEF775F980B997
+:10176000B4F90C30A060A06123F00803B4E721466F
+:101770002846FFF747F8B5E7A3890DD143F02003CA
+:10178000A3814FF0FF30F8BD43F0400309222A60E7
+:101790004FF0FF30A381F8BD002243F04003A38146
+:1017A00062604FF0FF30F8BD801E02088916010804
+:1017B00038B50C46054608B1836B63B1284621460F
+:1017C000FFF76CFF50B9D4E90023013B511CC4E979
+:1017D0000013107838BDFEF737FAEFE74FF0FF300F
+:1017E00038BD00BF024B01461868FFF7E1BF00BFDC
+:1017F000C804002038B5074D0022044608462A6078
+:10180000F0F7D8F9431C00D038BD2B68002BFBD073
+:10181000236038BD00E6002000290CBF0222002210
+:101820004FF4806300F000B82DE9F043544CD4F835
+:10183000009083B004460F4690461E46B9F1000F53
+:1018400003D0D9F83830002B65D0B8F1020F05D09D
+:10185000B8F1010F00F28180002E7EDB2146484660
+:10186000FEF7F2F8216B41B104F14003994202D036
+:101870004846EFF77FFF00232363B4F90C500023A1
+:10188000A36163602B064ED425F44A6525F0030559
+:10189000B8F1020FA5814DD001AB6A4621464846FA
+:1018A000FEF782FFA3891843A08116B317B3D9F8B6
+:1018B000383063B3009BB4F90C502760B3421CBFAF
+:1018C00045F40065A581B8F1010F04BF45F001059D
+:1018D000A58115F00800C4E90476ABB21FD013F05F
+:1018E000010036D000207642A661A06003B0BDE8BA
+:1018F000F083009E3046FEF7D1FF074680B3A389F0
+:1019000043F08003A381D9F83830002BD2D1484668
+:10191000FEF79AF9CEE74846FEF796F995E7A060FC
+:1019200003B0BDE8F08321694846EFF723FFB4F91F
+:101930000C50A9E7002004F1430345F00205002103
+:101940000122C4E90432A581A160236003B0BDE88F
+:10195000F083A66003B0BDE8F0834FF0FF30DFE70F
+:10196000009DB54204D02846FEF798FF074620B9EF
+:10197000B4F90C504FF0FF30DDE72E46BFE700BF53
+:10198000C80400200CB430B59DB020AB0A4D53F80C
+:10199000042B02916FF00044069102A90193CDE956
+:1019A0000445079400F0BCFB029B00221A701DB096
+:1019B000BDE8304002B070470802FFFF0EB430B5FA
+:1019C0009CB01FAB0C4C0D4D53F8042B01930146FA
+:1019D00002910691206802A96FF00044CDE9044508
+:1019E000079400F09DFB029B00221A701CB0BDE81A
+:1019F000304003B0704700BFC80400200802FFFF5A
+:101A00000EB470B59FB023AC4FF4017154F8042BA1
+:101A10000192ADF81C100490089000F091FA0C4B64
+:101A200003940146059109910A4E1868019A0C9693
+:101A300023464FF6FF75002404A910941594ADF8C1
+:101A40001E5001F0C5FD1FB0BDE8704003B07047E7
+:101A5000C8040020D51A01080CB470B59EB022ACA1
+:101A6000054654F8042B01924FF401730846049183
+:101A70000891ADF81C3000F063FA01462346039448
+:101A8000059100240991019A084E0C96284604A954
+:101A90004FF6FF7510941594ADF81E5001F098FDA7
+:101AA0001EB0BDE8704002B0704700BFD51A0108F3
+:101AB00010B50C46B1F90E1006F030F8002803DB23
+:101AC000236D0344236510BDA38923F48053A381B0
+:101AD00010BD00BF002070472DE9F041B1F90C5056
+:101AE0009846EB050C46174606460BD425F4805560
+:101AF000B4F90E10A58143463A463046BDE8F041A0
+:101B000004F036B9B1F90E100223002205F086FA6E
+:101B1000B4F90C50EAE700BF10B50C46B1F90E104D
+:101B200005F07CFAA389421C0EBF23F4805343F4D2
+:101B300080532065A38110BDB1F90E1004F096B951
+:101B4000830710B5044610D10268A2F1013323EADD
+:101B5000020313F0803F08D150F8042FA2F10133A3
+:101B600023EA020313F0803FF6D003781BB110F88C
+:101B7000013F002BFBD100F071F9204610BD00BFE2
+:101B8000A2EB0300704700BF02780B78012A28BF40
+:101B90009A42F5D16DE9044540EA0104CDE90267B6
+:101BA0006FF0000C4FEA447212B380EA010414F0A3
+:101BB000070F6AD100F0070420F0070004F00305C6
+:101BC00021F007014FEAC505F0E8042314F0040FE3
+:101BD000F1E804670CFA05F462EA040266EA040616
+:101BE0000AD063EA0403624667EA0407664603E034
+:101BF000F0E80423F1E8046782FA4CF582EA06046F
+:101C0000A4FA8CF46CBB83FA4CF583EA0705A5FAB9
+:101C10008CF595B950E9022351E9026782FA4CF537
+:101C200082EA0604A4FA8CF483FA4CF583EA0705E9
+:101C3000A5FA8CF52543DBD09CB92DBAB5FA85F40D
+:101C400024F0070427FA04F1DDE9026723FA04F31C
+:101C500003F0FF0001F0FF01FDE80445A0EB0100E7
+:101C6000704724BAB4FA84F424F0070426FA04F185
+:101C7000DDE9026722FA04F202F0FF0001F0FF0141
+:101C8000FDE80445A0EB0100704714F0030F3CD1C0
+:101C900010F0030428D150F8082B51F8083B82FAC1
+:101CA0004CF582EA0305A5FA8CF55DB950F8042CD1
+:101CB00051F8043C82FA4CF582EA0305A5FA8CF54A
+:101CC000002DE8D02DBAB5FA85F424F0070423FAE4
+:101CD00004F122FA04F202F0FF0001F0FF01FDE836
+:101CE0000445A0EB010070474FEAC40420F0030054
+:101CF00050F8082B21F0030151F8083B0CFA04F4CA
+:101D000062EA040263EA0403C9E710F003041AD08C
+:101D1000A1EB040120F00300E40750F8042B06D0E7
+:101D20000FD28B785FFAA2F4E41A06D12BB1CB78EC
+:101D30005FFAB2F4E41A00D11BB920465DF8104BEB
+:101D4000704701F1040150F8042BCC0721F0030186
+:101D500051F8043B48D824D222F07F4482FA4CF553
+:101D600094EA1325A5FA8CF50AD165B951F8043B1C
+:101D700084EA0204B4EB036F0ED150F8042BEBE7B6
+:101D80004FEA132355E035F07F454DD10878FDE843
+:101D90000445C0F1000070474FEA126203F0FF03F0
+:101DA00047E002EA1C4482FA4CF594EA1345A5FA8E
+:101DB0008CF50AD165B951F8043B84EA0204B4EB0E
+:101DC000034F0CD150F8042BEBE74FEA134330E0FC
+:101DD00015EA1C4528D10B884FEA124229E04FEA48
+:101DE000124203EA1C4324E002F0FF0482FA4CF59D
+:101DF00094EA1365A5FA8CF50AD165B951F8043B4C
+:101E000084EA0204B4EB032F09D150F8042BEBE76A
+:101E10004FEA13630DE015F0FF0F05D10B684FEA91
+:101E2000122223F07F4304E04FF00000FDE8044558
+:101E3000704712BA1BBA82FA4CF482EA0304A4FA7D
+:101E40008CF5B5FA85F402FA04F203FA04F34FEACA
+:101E50001260FDE80445A0EB1360704780EA0102C0
+:101E6000844612F0030F4FD111F0030F32D14DF819
+:101E7000044D11F0040F51F8043B0BD0A3F10132D3
+:101E80009A4312F0803F04BF4CF8043B51F8043BE6
+:101E900016D100BF51F8044BA3F101329A4312F05E
+:101EA000803FA4F101320BD14CF8043BA24312F065
+:101EB000803F04BF51F8043B4CF8044BEAD0234662
+:101EC0000CF8013B13F0FF0F4FEA3323F8D15DF814
+:101ED000044B704711F0010F06D011F8012B0CF8DC
+:101EE000012B002A08BF704711F0020FBFD031F854
+:101EF000022B12F0FF0F16BF2CF8022B8CF80020DB
+:101F000012F47F4FB3D1704711F8012B0CF8012B5D
+:101F1000002AF9D1704700BF000000000000000057
+:101F200000000000000000000000000000000000B1
+:101F300000000000000000000000000000000000A1
+:101F400090F800F06DE9024520F007016FF0000CF9
+:101F500010F0070491F820F040F049804FF00004A1
+:101F60006FF00700D1E9002391F840F000F108007C
+:101F700082FA4CF2A4FA8CF283FA4CF3A2FA8CF3B4
+:101F80004BBBD1E9022382FA4CF200F10800A4FA1B
+:101F90008CF283FA4CF3A2FA8CF3E3B9D1E904236F
+:101FA00082FA4CF200F10800A4FA8CF283FA4CF3A6
+:101FB000A2FA8CF37BB9D1E9062301F1200182FA60
+:101FC0004CF200F10800A4FA8CF283FA4CF3A2FA66
+:101FD0008CF3002BC6D0002A04BF04301A4612BA74
+:101FE000B2FA82F2FDE8024500EBD2007047D1E977
+:101FF000002304F00305C4F100004FEAC50514F006
+:10200000040F91F840F00CFA05F562EA05021CBFD6
+:1020100063EA050362464FF00004A9E79AB3F0B4FF
+:1020200040EA0105AD0704460346084628D020785B
+:102030000E78864229D1012A2AD0254650B115F8BA
+:10204000010F11F8016FEB43B04213441DD1E318A7
+:10205000F4D11846F0BC704707681C4653F8045B7F
+:10206000A5F10136BD42014626EA050600F104004D
+:10207000DDD1043A1C4601460AD016F0803F07D154
+:10208000032AE9D8D3E710467047801BF0BC70479D
+:102090000020F0BC704700BF024B1A6801235C327D
+:1020A00000F002B8C8040020844618B3B0B46746F4
+:1020B0000D4617F8010B01E0A04216D015F8014BB0
+:1020C000002CF9D1E8B117F8015B0C4601E0002BB8
+:1020D000F9D014F8013B9D42F9D14DB1002307F826
+:1020E000013C17606046B0BC70476BB1BC46DEE790
+:1020F0002F46F6E7D2F800C0BCF1000FD6D16046FB
+:102100007047B0BC10607047176060468CF80030B4
+:10211000E9E700BF0123FFF7C7BF00BF00000000D1
+:102120002DE9F04F2DED068BBFB00C4609EE101ACD
+:1021300092460D9309EE900A04F068FF0368159328
+:102140001846FFF7FDFEA3891490190603D52369ED
+:10215000002B00F03D879FED8E7B00238DED107BE3
+:10216000CDE922331293139316930A9319EE908AB2
+:102170002EAB219399469AF80030002B00F0ED80A9
+:10218000544604E014F8013F002B00F0C680252BD4
+:10219000F8D1B4EB0A0540F0C3802378002B00F09F
+:1021A000DC8000231A468DF8673019460B939B4656
+:1021B00066784FF0FF3304F1010A09930AF1010A2E
+:1021C000A6F12003582B00F2E780DFE813F0440269
+:1021D000E500E5003F02E500E500E500E500E5007B
+:1021E000E500F2013A02E500FD010202E5003502D8
+:1021F0005900590059005900590059005900590017
+:102200005900E500E500E500E500E500E500E50032
+:10221000E500E500E5001C026301E5006301E5005F
+:10222000E500E500E5007F02E500E5007700E50058
+:10223000E500E500E500E5006800E500E5005A027C
+:10224000E500E500E500E500E500E500E500E50066
+:10225000E500E5004C02C0016301630163017A02FD
+:10226000C001E500E500E902E500D3027900C30200
+:10227000BE02E5009B02E5006A00E500E50084027D
+:10228000A6F1300300201AF8016B00EB800003EB8D
+:102290004000A6F13003092BF5D90B9090E74BF0E5
+:1022A000100B1BF0200F00F046810D9B073323F02D
+:1022B0000703F3E802450D9301230DE04BF0100BEB
+:1022C0001BF0200300F029810D9B073323F0070347
+:1022D000F3E802450D93002300228DF867200E924B
+:1022E000099A1146013100F075822BF080010791A7
+:1022F00054EA050140F06C82002A40F0FF82002B76
+:1023000040F04C811BF001030C9300F0A0853023BA
+:102310008DF8B7300DF1B70783E2B4EB0A051CD096
+:10232000DDE9223201332A44072BCDE92232C9F8F4
+:1023300000A0C9F8045006DC09F108090A9A2378BC
+:102340002A440A922AE719EE101A21AA404607F0F9
+:1023500017F858B90DF1B809F0E7239B33B119EE1E
+:10236000900A19EE101A21AA07F00AF819EE103A8D
+:102370009B8913F0400F0A9B18BF4FF0FF330A935D
+:102380000A983FB0BDEC068BBDE8F08FAFF300803C
+:102390000000000000000000002A40F0C987002E65
+:1023A000DBD00122002308928DF890608DF8673011
+:1023B0000C9224AF00230993CDF81CB00F93079B18
+:1023C00013F0020302D0089A02320892079A12F020
+:1023D000840B05D10B9A0899551A002D00F38583BB
+:1023E000239C9DF8672072B1229A013201340DF1CD
+:1023F00067000121072ACDE92224C9E9000100F381
+:10240000C28309F108096BB1229B013302341AA976
+:102410000222072BCDE92234C9E9001200F3C88358
+:1024200009F10809BBF1800F00F08682099B0C9A24
+:10243000A3EB020BBBF1000F00F3C182079BDD058C
+:1024400000F1FF81229B0C9AC9F8007001331444FB
+:10245000072B2394C9F80420229300F3398309F150
+:102460000809079B5B0705D50B9B089A9D1A002D51
+:1024700000F3AB83DDE90A3208998A42ACBF9B18AE
+:102480005B180A93002C40F0D582002322930DF1B3
+:10249000B80970E6002A40F0FD870D9B073323F052
+:1024A0000703B3EC027B8DED107BDDE910450D9346
+:1024B00025F0004308EE903A08EE104ABF4B51EC6D
+:1024C000180B4FF0FF320AF013FD002840F0CC84C7
+:1024D000BA4B51EC180B4FF0FF320AF0EBFC00281E
+:1024E00040F0C28400220023204629460AF0D8FC8E
+:1024F000002840F0F0869DF867300E93B04FB14B46
+:10250000032200212BF08000CDE908210790472EFF
+:10251000C8BF1F460C920F918BE11BF0100242D1F5
+:102520001BF040033FD00D9951F8044B0D91134619
+:10253000A4B20025D0E60D9A1BF0100F52F8044B00
+:102540000D924FF0010300F084840025C4E6002AB8
+:1025500040F0AC871BF0200F0D9B5DD0073323F0BC
+:1025600007031946F1E802230D9114461D46002A7F
+:1025700073F10003C0F24084099B013300F0A7858A
+:102580002BF0800307939DF867300E9354EA050300
+:1025900040F0E882099B002B40F01E87002309933E
+:1025A0000C932EAF3DE10D9A52F8044B0D9200258D
+:1025B00092E60D9B53F8040B0B90002880F24284A6
+:1025C0000B980D9340420B909AF800604BF0040B6F
+:1025D000F4E5504610F8016B2A2E00F0D687A6F1DC
+:1025E0003003092B824698BF002000F257871AF863
+:1025F000016B00EB800003EB4000A6F13003092BD8
+:10260000F5D90990DCE5002A40F04C874BF0100B1F
+:102610001BF0200F0D9BA1D11BF0100F53F8044BA2
+:1026200040F0E1831BF0400F00F0DD8324B2E5179A
+:102630000D9322462B469AE79AF800604BF0800BE8
+:10264000BCE59AF8006001222B21B7E59AF80060FA
+:102650004BF0010BB2E59AF8006000297FF4AEADB3
+:1026600001222021AAE50D9B53F8041B8DF8901040
+:102670000022012108910D938DF867200C9124AF61
+:1026800098E6002A40F016874F4B13931BF0200F5B
+:102690000D9B29D0073323F00703F3E802450D9380
+:1026A0001BF0010F0BD054EA050308D030238DF83E
+:1026B00068308DF869604BF0020B02230CE60223B0
+:1026C0000AE69AF800604BF0400B77E59AF8006054
+:1026D0004BF0080B72E5002A40F0D4863B4B139375
+:1026E0001BF0200F0D9BD5D153F8044B0D931BF01D
+:1026F000100F40F076831BF0400F00F07283A4B2FD
+:102700000025CDE70D9C54F8047B00258DF867501B
+:10271000002F00F01685099A1346013300F04D840E
+:1027200029463846FEF784FB002800F09E86C31B2E
+:102730000C9309950D94CDF81CB023EAE37308932C
+:102740009DF867300F950E9373E09AF800604BF098
+:10275000200B33E50D9B53F8044B0D9347F63002E5
+:102760001A4B1393ADF868204BF0020B002502239F
+:102770007826B1E5002A40F089861BF0200F40F052
+:10278000DD831BF0100F40F031841BF0400F00F090
+:102790002D840D9B0A9953F8042B0D931180EAE4C4
+:1027A0009AF800606C2E03BF9AF801604BF0200B82
+:1027B0000AF1010A4BF0100B00E500BFFFFFEF7FAD
+:1027C000841E0208881E0208941E0208A81E020821
+:1027D000DDF81CB0012B00F0C781022B00F09680C1
+:1027E0002EAFE20842EA4572E90804F007030D46FD
+:1027F0001446303354EA05013A4607F8013DF0D15A
+:102800001BF0010F00F09280302B00F08F803023FE
+:10281000023A07F8013C2EAB9B1ACDF81CB00C9382
+:102820001746099B0C9A9342B8BF1346089300239E
+:102830000F930E9B002B3FF4C2AD089B013308930E
+:10284000BDE5652E40F30081DDE910010022002383
+:102850000AF01CFB002800F0F381229BD14AC9F842
+:102860000020013301340122072BCDE92234C9F8BD
+:10287000042000F33C8409F108091B9B129A93423F
+:1028800003DB079BD8077FF5ECAD229B159AC9F8AF
+:102890000020149AC9F8042001331444072B239410
+:1028A000229300F3408409F10809129B5E1E002E5A
+:1028B0007FF7D7AD102E229BBB4D40F30C8419EE51
+:1028C00010BA102705E009F10809103E102E40F358
+:1028D000028401331034072BCDE92234C9E90057B3
+:1028E000F1DD21AA5946404606F04AFD00287FF452
+:1028F0003DADDDE922340DF1B809E6E7012B00F02A
+:102900006B85022BDDF81CB07FF46AAF13982EAFF5
+:10291000230904F00F0143EA05732A091C461546F2
+:10292000435C07F8013D54EA0503F1D12EABDB1BF4
+:10293000CDF81CB00C9374E70B9B089AA3EB020B29
+:10294000BBF1000F7FF772ADBBF1100F229A964DCD
+:1029500027DD2146102319EE104A06E0ABF1100BDB
+:10296000BBF1100F09F108091ADD01321031072AF5
+:10297000CDE92221C9E90053F0DD21AA21464046D4
+:1029800006F0FEFC00287FF4F1ACABF1100BBBF1BC
+:10299000100FDDE922210DF1B8094FF01003E4DC3E
+:1029A0000C4601325C44072ACDE92224C9F80050C4
+:1029B000C9F804B000F3A98309F1080936E5BBF1B1
+:1029C000100F229A784D27DD2146102319EE104A68
+:1029D00006E0ABF1100BBBF1100F09F108091ADD8D
+:1029E00001321031072ACDE92221C9E90053F0DD77
+:1029F00021AA2146404606F0C3FC00287FF4B6AC6D
+:102A0000ABF1100BBBF1100FDDE922210DF1B8097C
+:102A10004FF01003E4DC0C4601325C44072ACDE998
+:102A20002224C9F80050C9F804B000F3CC8109F1A0
+:102A3000080903E519EE101A21AA404606F0A0FC89
+:102A400000283FF422AD91E4129B229E012B40F31B
+:102A50007281013601340123072ECDE92264C9F8C1
+:102A60000070C9F8043000F3D18109F10809149B02
+:102A7000159A01361C44072ECDE92264C9E90023CA
+:102A800000F3D28109F108090023DDE910010022D9
+:102A90000AF0FCF9129B002840F06B81013B0136E3
+:102AA00001371C44072ECDE92264C9F80070C9F82B
+:102AB000043000F3508109F10809169A01361444D4
+:102AC0001DAB072ECDE92264C9E900327FF7C7AC00
+:102AD00019EE101A21AA404606F052FC00287FF495
+:102AE00045AC239C0DF1B809BBE4102DDDE9222192
+:102AF00029DD0E9310244B460846B946374619EE99
+:102B0000106A04E0103D102D03F1080316DD0132B8
+:102B100026491030072ACDE92220C3E90014F1DD4F
+:102B200021AA3146404606F02BFC00287FF41EAC5B
+:102B3000103D102DDDE922202EABE8DC3E464F464D
+:102B400099460E9B014601321848C9F800006C18DE
+:102B5000072ACDE92224C9F8045000F3A88209F11C
+:102B600008093EE4DDF81CB0002D08BF0A2C80F0F7
+:102B70004B82303401238DF8B740CDF81CB00C9354
+:102B80000DF1B7074DE619EE101A21AA40460E9333
+:102B900006F0F6FB00287FF4E9AB239C0E9B0DF1B9
+:102BA000B80930E4C41E0208D81E0208C81E020874
+:102BB00019EE101A21AA404606F0E2FB00287FF425
+:102BC000D5AB239C0DF1B8092CE4102D229B20DD00
+:102BD00019EE107A102604E0103D102D09F10809B5
+:102BE00017DD01339E4A1034072BCDE92234C9E9A1
+:102BF0000026F1DD21AA3946404606F0C1FB002837
+:102C00007FF4B4AB103D102DDDE922340DF1B8098D
+:102C1000E7DC0133924AC9F800202C44072BCDE9A8
+:102C20002234C9F804507FF725AC19EE101A21AAF6
+:102C3000404606F0A5FB00287FF498AB239C19E4DE
+:102C40001B99002940F3FF81129B0F9A9342A8BF62
+:102C50001346002B1E460DDD229BC9F80070013380
+:102C60003444072B2394C9F80460229300F3DD83D6
+:102C700009F108090F9B002EA8BF9B1B002B1E46C5
+:102C800000F375811B9A129B9A4280F26381229B0A
+:102C90001599C9F800101499C9F8041001330C44AF
+:102CA000072B2394229300F31C8309F10809129B3C
+:102CB0000F999A1A5B1A9342A8BF1346002B1E461F
+:102CC0000EDD229BC9F8046001330F443444072B06
+:102CD000CDE92234C9F8007000F3B48309F1080982
+:102CE000002EACBF961B1646002E7FF7BAAB102EF7
+:102CF000229B5C4D40F3EF8119EE10BA102705E0DE
+:102D000009F10809103E102E40F3E581013310341B
+:102D1000072BCDE92234C9E90057F1DD21AA594634
+:102D2000404606F02DFB00287FF420ABDDE922347D
+:102D30000DF1B809E6E7079BDA073FF58AAE0136E1
+:102D400001340123072ECDE92264C9F80070C9F8C7
+:102D500004307FF7B0AE19EE101A21AA404606F0F3
+:102D60000FFB00287FF402ABDDE922640DF1B80906
+:102D7000A3E65F1E002F7FF7A0AE102F394D40F362
+:102D80002282CDF824A04FF0100B19EE10AA05E016
+:102D900009F10809103F102F40F313820136103457
+:102DA000072ECDE92264C9E9005BF1DD21AA514675
+:102DB000404606F0E5FA00287FF4D8AADDE922644F
+:102DC0000DF1B809E6E719EE101A21AA404606F0FF
+:102DD000D7FA00287FF4CAAA239C0DF1B809FFF79F
+:102DE0002DBB00255CE4E51722460D93002A2B46F7
+:102DF00073F10003BFF6C0AB2D2364428DF867303A
+:102E00000E9365EB45050123FFF76ABA19EE101A18
+:102E100021AA404606F0B4FA00287FF4A7AADDE90B
+:102E200022640DF1B80922E619EE101A21AA4046D3
+:102E300006F0A6FA00287FF499AADDE922640DF1D4
+:102E4000B80921E69AF800600D93FFF7B7B92EAFE5
+:102E5000E7E41BF0400F18BFA4B20025FFF73CBA0F
+:102E6000C81E0208D81E0208DDE9100102460B4602
+:102E70000AF03EF8002840F07383099B013326F0E6
+:102E8000200500F0EF82472D00F0B880DDE9100149
+:102E90004BF4807200290792C0F23F829DED107BB7
+:102EA00000231793B0EE47AAF0EE67AA662E00F053
+:102EB0009481462E00F09181452D00F09182099C6D
+:102EC00001941FA81CA91BAA0223CDE9031002929A
+:102ED0000093404653EC1A2B03F068F8672E074620
+:102EE00040F06E831BF0010F40F08E821F9B472D38
+:102EF000A3EB0703129340F060831B9B0F93DA1C34
+:102F0000C0F2B281099A934200F3AE810F9B1299ED
+:102F10008B42C0F2D3821BF0010F40F0078323EAFB
+:102F2000E37208920C936726179B002B00F07682C1
+:102F30002D238DF86730002309937EE40D9B53F811
+:102F4000041B0D930A9BDD171A462B46C1E900238B
+:102F5000FFF711B9079BD9073FF599AE12990F9B5F
+:102F60008A1ACB1A9342A8BF13461E46B8E6102E03
+:102F7000229BBA4D40F3A28122464FF0100B19EE6E
+:102F8000104A05E009F10809103E102E40F3958122
+:102F900001331032072BCDE92232C9E9005BF1DDA4
+:102FA00021AA2146404606F0EBF900287FF4DEA96D
+:102FB000DDE922320DF1B809E6E73846FEF7C0FF39
+:102FC0000995CDE90C04CDF81CB00346FFF7B5BB5D
+:102FD00019EE900A4021EEF7C9FB2060206100281D
+:102FE00000F0E28240236361FFF7B5B80D9B0A99B8
+:102FF00053F8042B11600D93FFF7BDB8099B002B0C
+:1030000008BF0123099341E72EAF204629460A2233
+:1030100000230AF01BF8303207F8012D00230A22A2
+:10302000204629460AF012F82B462246002B08BFFC
+:103030000A2A04460D46E8D22EABDB1BCDF81CB0A5
+:103040000C93FFF7EEBB229B854AC9F800200133A1
+:1030500001340122072BCDE92234C9F8042000F302
+:103060004E8109F10809002975D1079B129A03F0D6
+:10307000010313433FF4F5A9229B1499159AC9F84B
+:10308000002001330A19072B2392C9F80410229358
+:1030900000F3528109F10809129901338C18072BAA
+:1030A000CDE92234C9E900717FF7D9A910E519EEFD
+:1030B000101A21AA40460E9306F062F900287FF408
+:1030C00055A9239C0E9B0DF1B809FFF78AB99DF80D
+:1030D00067300E9348E501333444072BC9F800509C
+:1030E000CDE92234C9F804607FF7B9A9F0E419EEFC
+:1030F000101A21AA404606F043F900287FF436A9A9
+:10310000239C0DF1B809FFF7B8BB19EE101A21AADC
+:10311000404606F035F900287FF428A9239C0DF1DC
+:10312000B809FFF783B919EE101A21AA404606F034
+:1031300027F900287FF41AA9239C0DF1B809FFF79D
+:10314000B4BB099B474F062B28BF0623CDE90C349F
+:103150000893FFF72FB9229B1498159AC9F80020FD
+:1031600001330219072B2392C9F80400229300F3BC
+:10317000E38009F1080900298EDA4E421031374DFB
+:1031800080F2AF8119EE10BA102405E009F10809A8
+:10319000103E102E40F3A58101331032072BCDE9EC
+:1031A0002232C9E90054F1DD21AA5946404606F011
+:1031B000E7F800287FF4DAA8DDE922320DF1B8093A
+:1031C000E6E7DDF824A001363C44072ECDE9226471
+:1031D000C9E900577FF76FACBDE5099C01941FA8B2
+:1031E0001CA91BAA0323CDE90310029200934046B9
+:1031F00053EC1A2B02F0DAFE074604193B78302B09
+:1032000000F086811B9B1C4451EC1A0B002200230A
+:1032100009F03CFE002840F089801F9BA34206D2A3
+:1032200030215A1C1F9219701F9B9C42F9D8DB1B3E
+:10323000472D12933FF461AE662E40F0BE811B9A7B
+:103240000F92002A0BF0010340F3E08009990B4331
+:1032500040F075810F9B08930C9365E6D81E020819
+:10326000C41E0208BC1E0208023E0F9A8DF874604C
+:10327000531E002B1B93B6BFC2F101032B222D223C
+:10328000092B8DF8752073DC303330228DF87730C0
+:1032900004238DF876201693129A169B012A134464
+:1032A0000C9340F354810C9B149A13440C9323EA1F
+:1032B000E373089300230F9336E614460133344436
+:1032C000072BCDE92234C9F80050C9F8046042DC6C
+:1032D00009F10809D6E42D238DF867300E93FFF726
+:1032E0000DB919EE101A21AA404606F049F8002837
+:1032F0007FF43CA81B9A239C0DF1B809D7E419EE82
+:10330000101A21AA404606F03BF800287FF42EA8A8
+:103310001B99239C0DF1B809A5E601F100430AEEC3
+:10332000903A2D230AEE100A1793BFE523467EE755
+:103330008DF86710FFF733B819EE101A21AA40462E
+:1033400006F01EF800287FF411A8DDE922321B994F
+:103350000DF1B8090FE719EE101A21AA404606F040
+:103360000FF800287FF402A8239C0DF1B80989E426
+:103370000DF1830C934D644685FB0321DA17C2EBF4
+:10338000A10202EB8201A3EB41019E463031BEF166
+:10339000630F204604F8011C134604F1FF34EBDCF4
+:1033A0003033821EDBB29445214604F8013C40F2E2
+:1033B000F8800DF1760201E011F8013B02F8013BC3
+:1033C0008C45F9D10DF185030DF176021B1A1344DA
+:1033D0001DAA9B1A16935FE7DDF81CB0FFF7C9BB67
+:1033E000099B1FA85C1C1CA91BAA0223CDE9031082
+:1033F00002920093019453EC1A2B404602F0D6FD42
+:103400000746472E3FF46EAD3C44FDE6099A134350
+:1034100040F0B380012308930C9385E59DF8673055
+:103420000E93179B0993FFF704BA19EE101A21AAFD
+:10343000404605F0A5FF00287EF498AF239C0DF1CF
+:10344000B80917E419EE101A21AA404605F098FFB2
+:1034500000287EF48BAF1B9A129B239C9A1A0DF1C5
+:10346000B8093DE40623099310E5099B08930C93E2
+:103470009DF8673009900D94CDF81CB00F900E9315
+:10348000FFF7D7B98DF86710FFF728B98DF86710E7
+:10349000FFF773B98DF86710FEF7FFBF002309939C
+:1034A000FEF78EBE8DF86710FFF7B0B88DF8671085
+:1034B000FFF750B88DF86710FFF7E6B8149A129B23
+:1034C00013440F9A0C93002A06DC0F9B0C9AC3F14D
+:1034D00001031A4413460C9223EAE3730893672608
+:1034E00022E501333244072BCDE92232C9E90056E7
+:1034F0007FF7D0AD19EE101A21AA404605F040FF23
+:1035000000287EF433AFDDE922320DF1B809C3E5BE
+:1035100051EC1A0B0022002309F0B8FC00287FF4BC
+:1035200071AE099BC3F101031B936CE60F9B149AC8
+:1035300013440C9323EAE37308936726F4E4149B83
+:10354000D318194421EAE1730C910893ECE41BF0C1
+:1035500001020F927FF4A7AE23EAE3730893E3E43A
+:10356000119B194F002BB6BF2D239DF867308DF8A6
+:1035700067300E93154BFEF7C3BF149B01331A44FB
+:1035800022EAE2730C920893CEE40D9B9AF8016054
+:1035900053F8044B0D93824644EAE4700990FEF719
+:1035A0000DBE0223169377E619EE902A0C231360C2
+:1035B0004FF0FF330A93FEF7E3BE1B9B0F9354E6D5
+:1035C000099C1EE7676666668C1E0208901E02084C
+:1035D0002DE9F04F2DED028B8A46B1F90C10ADF5B7
+:1035E0002F7D83468804079309D4DAF8643041F4C8
+:1035F000005123F40053AAF80C10CAF864301346A3
+:1036000013F8012B03931192002A00F02F87DFF8A3
+:10361000C49708EE10BA19F802B000231BF0080B8B
+:10362000CDE9083306939846049340F0A580252AF7
+:103630007FD1039802785D465C46A2F12503411CC8
+:10364000532B6ED8DFE813F074006D006D006D0031
+:103650006D0036046D006D006D006D006D00C100E1
+:10366000C100C100C100C100C100C100C100C10052
+:10367000C1006D006D006D006D006D006D006D008E
+:103680006D006D006D00D003CC006D00CC006D00AE
+:103690006D006D006D00E6036D006D00EE036D00C2
+:1036A0006D006D006D006D006D006D006D006D03AF
+:1036B0006D006D00DE036D006D006D006D006D002E
+:1036C0006D006D00D903D203CC00CC00CC00040403
+:1036D0000D046D006D0014046D0020045B06F703FB
+:1036E0006D006D00FA036D00FD036D006D006D034C
+:1036F00018EE100A514606F01FFC002800F08084E6
+:103700003B46059F002B00F0A084049A002A00F09D
+:10371000E386BAF80C3013F0400F18BF4FF0FF32B9
+:10372000049204980DF52F7DBDEC028BBDE8F08F5F
+:103730000391DAF80430002B3FDDDAF80030039A09
+:10374000197812F8012C9142EBD1DAF804200133F8
+:10375000013ACAF8003008F10108CAF80420039BB6
+:1037600013F8012B03931192002ADAD019F802B052
+:103770001BF0080B3FF45BAFDAF8042018EE104A98
+:1037800012E0DAF800301A7819F8022012F0080F67
+:1037900003F10103E3D0DAF80420CAF80030013A5B
+:1037A00008F10108CAF80420002AEADC5146204644
+:1037B00006F0C2FB0028E4D0D1E718EE100A51460B
+:1037C00006F0BAFB0028B8D09FE715F08F0FA8D1FC
+:1037D00004EB840402EB4404303C427808462CE7B6
+:1037E00003910426DAF80430002B40F3A8826F0618
+:1037F00040F1B082731E032B00F2AB86DFE813F0BA
+:103800009E015D01A100040018EE100A03F0FEFB0A
+:10381000631E02680C92B3F5AE7F40F294836FF49E
+:10382000AE7163180E9340F25D14002356AF5146FB
+:103830000A9745F4F0650F930D931E460B939A4635
+:103840000B681878A0F12B0EBEF14E0F50D8DFE8B0
+:103850001EF0C0014F00C0014F004F005B0272001C
+:1038600072007200720072007200720072007200C8
+:103870004F004F004F004F004F004F004F00BB0163
+:103880004F004F004F003C0235024F004F00DE0159
+:103890004F004F004F004F00C6014F004F004F0038
+:1038A0004F004F00B4014F004F004F004F00AD01DB
+:1038B0004F004F004F004F004F004F004F00BB0123
+:1038C0004F004F004F003C0235024F004F00DE0119
+:1038D0004F004F004F004F00C6014F004F004F00F8
+:1038E0004F004F00B4014F004F004F004F00AD019B
+:1038F0000C9A92F800E0864514D1AA0512D525F459
+:103900002075CDF82CA007F8010B013C4868013860
+:10391000002808F10108486040F3E482581C086060
+:10392000002C8DD1334656468A46002E00F0808109
+:1039300025F480757CE116EB0B0FF3D125F4C075EF
+:10394000E1E7631EB3F5AE7F86BF6FF4AE7204EBA2
+:10395000020B4FF0000B4FF00007534656AECDF868
+:1039600014B0DDF818B00A96C24688BF40F25D1464
+:10397000B84645F458651F463A681078A0F12B0305
+:103980004D2B60D8DFE813F00E025F000E025F00DF
+:103990005F009E02BA01BA01BA01BA01BA01BA01C6
+:1039A000BA01280228025F005F005F005F005F002D
+:1039B0005F005F004E004E004E004E004E004E0075
+:1039C0005F005F005F005F005F005F005F005F00FF
+:1039D0005F005F005F005F005F005F005F005F00EF
+:1039E0005F0014025F005F005F005F005F005F0028
+:1039F0005F005F004E004E004E004E004E004E0035
+:103A00005F005F005F005F005F005F005F005F00BE
+:103A10005F005F005F005F005F005F005F005F00AE
+:103A20005F001402BBF10A0F0DDD25F4386506F8BE
+:103A3000010B7B68013B002B7B6040F3608201320D
+:103A40003A60013C98D13B46E9054746CDF818B0AD
+:103A5000D0469A4607D50A9B9E4200F2B5840A9B3F
+:103A60009E423FF45EAE15F0100240F05982069B74
+:103A70000A99089C327018EE100AA047AA0600F1B5
+:103A800047826B0700F1468415F0010240F0408246
+:103A9000AC0740F13D82CD4B0899994218EE100ACF
+:103AA000069B0A9900F0248505F0A2FA079B53F8BB
+:103AB000042B0793C2E900012FE2002C08BF4FF04E
+:103AC000FF34EE0700F14882DAF80020E8061378A8
+:103AD00040F1188319F8033019073FF540AEDAF8C2
+:103AE00004300132013B012CCAE9002308BF08F170
+:103AF00001083FF434AE18EE106A01251A4613E0AF
+:103B0000DAF800301A7819F80220120703F10103DD
+:103B100012D4DAF80420CAF800300135013AAC4278
+:103B2000CAF8042000F07F84002AE9DC51463046C0
+:103B300006F002FA0028E3D0A84410E6002C08BFE3
+:103B40004FF0FF34EA0700F11F83DAF80020E9069E
+:103B5000137816AF40F18382FB5C002B3FF4E1AD9C
+:103B6000DAF804300132013B012CCAE900231BD0F2
+:103B700018EE105A1A460FE0DAF800301A78BA5CDC
+:103B800001338AB1DAF80420CAF800300136013A6C
+:103B9000B442CAF8042007D0002AEDDC514628467A
+:103BA00006F0CAF90028E7D0B044D8E5BBF1070F0A
+:103BB0007FF4B8AE4FF0080BA5E6BBF1060F7FF41B
+:103BC000B1AE4FF0070B9EE6012E7FF4ABAE02269E
+:103BD00099E62A067FF5A6AE25F0800593E6002E2D
+:103BE00040F0AC81BAF1000F05D105F4E06EBEF5EE
+:103BF000E06F00F02184BBF1010F03D0BBF1040F93
+:103C00007FF490AE0BF1010B5FFA8BFB7BE6BBF10F
+:103C1000000F40F08A81BAF1000F40F0978105F45F
+:103C2000E06EBEF5E06F00F00184334656468A46EA
+:103C3000013B012B40F240840BF1FF33062B40F295
+:103C40002283E80514D5690500F1588417F8011C92
+:103C5000652907F1FF3408F1FF3B02D0452940F008
+:103C6000438318EE100A524606F026F9D846274636
+:103C700015F010027FF473AD05F4C063B3F5806FE7
+:103C80003A7000F09B830D9B002B40F06383002271
+:103C90000A9918EE100A04F06BFFEA0706460F4671
+:103CA00002D4AB0740F13C83079B53F8042BC2E9D5
+:103CB00000670793049B0133049350E5BBF1020FA7
+:103CC0007FF430AE4FF0030B1DE605F4A06EBEF599
+:103CD000806F05D06A057FF525AEBAF1000FA4D03C
+:103CE000AA0504D40B9A0F97AAEB02020D9225F4B1
+:103CF000F06545F4C0754FF0000A04E6344B25F436
+:103D0000386533F91BB092E6EA057FF514AE0E9ADA
+:103D100025F080050AF1010A002A40F0ED81013CFE
+:103D2000F4E545F40075294B089310230693DAF85F
+:103D300004300391002B4FF003063FF758AD18EE07
+:103D4000100A514606F0F8F800287FF4DEAC6F0642
+:103D50003FF550ADDAF80020137819F80330180752
+:103D60007FF548AD18EE107A07E0CAF80020137806
+:103D700019F8033019077FF53DADDAF80430013B3F
+:103D8000002B08F10108CAF8043002F10102ECDC52
+:103D90005146384606F0D0F800287FF4B6ACDAF881
+:103DA0000020E4E72B067FF54EAE25F080053EE6C9
+:103DB00005F4C063B3F5007F7FF445AE25F40075CC
+:103DC00045F4A0654FF0100B31E600BF619101088A
+:103DD000F01E0208351F0208AD4B33F91BB0BBF1D2
+:103DE000080F3FF722AE2EE645F00105A94B0893D8
+:103DF0000A23039106930326F4E445F0400503915A
+:103E00000026EFE416A803F09FFE45F0400503905E
+:103E10000126E7E42F077FF484AC427845F00205E1
+:103E200008460AE49C4B0893082345F001050391DA
+:103E300006930326D6E445F4087574E70391022639
+:103E4000D0E4954B08930A23039106930326C9E413
+:103E50002E077FF466AC427845F004050846FFF76C
+:103E6000ECBB8C4B08930023039106930326B9E423
+:103E70002B077FF456AC42786C2A00F0AF8245F0F5
+:103E800001050846FFF7D9BBEC0600F12A82680756
+:103E900000F15782EA0700F1EC82AB0740F1E982BA
+:103EA000079B039153F8040B07934246D317C0E9CD
+:103EB000002354E42C437FF434AC427810250846A8
+:103EC000FFF7BBBB2B057FF5B2ADBBF1000F03D1F4
+:103ED00045F400754FF0080B690540F1F78125F4B2
+:103EE000B065A4E518EE100A059106F025F80599CD
+:103EF00000287FF417AD002C7FF4A2AC12E518EE79
+:103F0000100A394606F018F800283FF49AAD9AE5F1
+:103F1000079B53F8042B10600793049B0133049311
+:103F20000A9BF61A3744B84419E4BBF1030F3FF477
+:103F300069AEBBF1050F3FF465AEF3E4022E7FF4EA
+:103F40005AAE0326DFE400230E936EE4334625F4D5
+:103F5000807556468A466BE615F0100702BF079B30
+:103F600053F804BB0793DAF800301B7819F80330D4
+:103F700018BF0DF1440B13F0080566D156AE059736
+:103F80000A9403F033F8A8423FF4BFABDAE9002308
+:103F900012F8011B7155013BCAE90023099B032B51
+:103FA00005F1010714AC02D12368042B04D00822C8
+:103FB00000212046FDF792F8324618EE100A0094D0
+:103FC0003B46594603F040F80246013209903FF45F
+:103FD0009CAB002840F03582CBF8000002F0D8FFFF
+:103FE000E0B9B8440A9B013B0A93059F002F40F0BB
+:103FF0004D820BF1040BDAF80430002B7FF778AB1D
+:10400000DAF800301B7819F803301C0700F1EC8156
+:104010000A9B002B00F0E8813D46B2E73B46059F36
+:104020009BB1CDF81480D046BA4618EE107A3544CC
+:1040300029784246384605F03FFFAE4205F1FF358C
+:10404000F6D15746C246DDF81480002F7FF487ABC7
+:10405000049BCBF8007001330493FFF780BB079DEE
+:10406000FB5C55F8046B002B3FF45BABDAF80430D3
+:10407000511C013BCAE90013B34613780BF8013B0E
+:10408000012C2BD034440595254618EE104A17E034
+:10409000F01E0208418E010861910108DAF8001053
+:1040A0000B78FB5C481C5BB3DAF80430CAF80000FC
+:1040B000013BCAF804300B780BF8013BAB451FD02D
+:1040C000DAF80430002BE9DC5146204605F034FFD5
+:1040D0000028E3D05E45059D3FF417ABBBEB060619
+:1040E0003FF41FAB049A0795002301320492B044B9
+:1040F0008BF80030FFF733BB0E9A013A0E9205E4BD
+:10410000059DEBE719F80330079D1F0755F8046B71
+:1041100000F1F281DAF80430511C013BCAE90013C6
+:104120003746137807F8013B012C00F0F78118EEB1
+:1041300010BA344414E0DAF800301A7819F8022082
+:10414000100703F1010115D4DAF80420CAF80010B1
+:10415000013ACAF804201B7807F8013BA74209D0AE
+:10416000DAF80430002BE6DC5146584605F0E4FE50
+:104170000028E0D0BE1BB044049A0795002301320A
+:1041800004923B70FFF7EBBA15F010030C9340F06C
+:10419000BE80079B53F8042B0A92079305940026D0
+:1041A000099CCDF82C8056ADF0EE488A34E038609A
+:1041B000074614AB1846082200210993FCF78EFF2E
+:1041C000C848099BD0F8E0003A4610A9074618EE07
+:1041D000900AB847012800F0E880002216AB9B5CEB
+:1041E000002B00F055810B9B032C5B440B9300F0DC
+:1041F000DF80059B013B05930C9E002E40F0D38091
+:104200000A9B04330A93DAF80430002B40F3B6809B
+:10421000059B002B00F0368102F0E8FEB0423FF42F
+:1042200074AADAE9002312F8011BA955013B032CFB
+:10423000CAE9002306F1010B0DF1480803D1D8F8B3
+:104240000030042B04D0082200214046FCF746FF32
+:104250000A9FCDF800805B4618EE900A2A46394640
+:1042600002F0F2FE431C04463FF44FAA00289ED001
+:10427000A01C08BF5E46C6D00A9B1B681F460133C0
+:1042800097D13A46AAE7BBF1020F40F25181BBF148
+:10429000030F3FF4D6ACABF10404E4B26FEA040BB5
+:1042A00005955546A24618EE104ABB4417F8011D65
+:1042B0002A46204605F000FEBB45F7D1544608F1DA
+:1042C000FF38AA46A8EB0408059DBAE4059B25F42F
+:1042D000607513B1013B0593013408F10108FFF744
+:1042E000A8BB0391FFF73BBA18EE100A524605F03F
+:1042F000E3FDA8F1020B17F8021CBC1EB1E47A4BD7
+:1043000008930823039106930326FFF76BBA11ABBA
+:104310000A9343E7079B53F8042B07931080FCE5AF
+:1043200002460B4608F0E4FD079C54F8045B0028A5
+:1043300040F0F7803046394608F038FE0794286090
+:10434000B8E4079B039153F8042B0793A2F800806D
+:10435000FFF705BA0F9F0A2318EE100A791C04F024
+:104360006FFD0D9BC21A0DF2AB239F4228BF0DF2C9
+:10437000AA275E493846FDF721FB88E418EE900A2B
+:10438000514605F0D9FD00283FF442AFDDF82C80FE
+:104390000994002E7FF4B9A90C9B002B7FF4DFA9B0
+:1043A0000A9A136086E400262DE79DF8402015E761
+:1043B000D8F80030042B7FF41CAF1DE70B9BB342F1
+:1043C000A3EB0602CFD162E416F8011C18EE100A26
+:1043D000524605F071FD013EFFF741BB827845F082
+:1043E00002050230FFF729B9059F002F7FF4B7A916
+:1043F0002EE61344CAF800301444B61A05F09CFDAA
+:10440000002840F01681DAF80420DAF800309642ED
+:1044100018EE100A5146ECDC921B3344CAF8042013
+:104420003444CAF80030A044FFF799B925F4F06588
+:104430004FF0010BFFF767BA25F4F0650126FFF78F
+:1044400062BA099B02333FF4D6ADDBF8000002F0FC
+:104450009FFD00287FF4E2AD099B032BB8447FF455
+:10446000C1AD2368042B7FF4BDADBEE50492FFF718
+:1044700058B9079B039153F8042BC2F800800793A7
+:10448000FFF76DB9DDF82C80099485E70027B2E5C8
+:10449000DDF82C800994BBF1000F3FF47DAF18EEDE
+:1044A000107A2E4431785246384605F005FDAE426A
+:1044B00006F1FF36F6D16FE70A9CA74218EE10BA54
+:1044C0007FF62FA917F8011D5246584605F0F4FC57
+:1044D000A742F7D1FFF725B94FF0FF330493FFF759
+:1044E00020B900BF080D002061910108E81E0208F4
+:1044F00004F02CFFFFF7DABA37463DE60A9CA742E4
+:1045000018EE10BA7FF60DA917F8011D524658464D
+:1045100005F0D2FCA742F7D1FFF703B908F1010873
+:104520002AE6574803F054FB07942860FFF7C2BB04
+:104530000A9B9F4218EE10BA7FF6F3A817F8011DE8
+:104540005246584605F0B8FC0A9B9F42F6D1FFF749
+:10455000E8B8012C38BF0124264615F0010417D114
+:10456000E9063FF550AF079C18EE100A54F8041BFB
+:10457000CDF800A03346012205F0FCFC00283FF4F2
+:10458000C4A8049B0794013380440493FFF7E7B861
+:1045900015F0100708BF079B099A06BF53F8045B84
+:1045A0000793002500240DF5AC7B059202F01EFD5B
+:1045B000A0423FF4AAA8DAE90003059A10F8011B0B
+:1045C0000BF80410032A03F1FF31CAF8000004F1CC
+:1045D0000103CAF8041014AC02D12268042A06D0E0
+:1045E0000822002120460593FCF778FD059B0094E6
+:1045F0005A4618EE100A2946059302F025FD431C81
+:1046000002463FF482A8059BC8B907B92F609844B9
+:10461000013E07B90435DAF80430002B4FF00004EE
+:1046200014DD002EC1D10992002F3FF443ABFFF7F8
+:1046300096B8002C3FF469A8A044FFF790B8901CEE
+:1046400016D1DAF8041000291C46AEDC18EE100A68
+:104650005146059205F070FC059A0028E1D00992B8
+:10466000002C7FF452A8002F3FF424ABFFF777B85B
+:10467000032A9844CCD12368042BC9D1C9E700BFD1
+:10468000D0220208000000002DE9F04F2DED068B2E
+:10469000BFB01C4609EE101A924609EE900A054674
+:1046A00002F0B4FC03680D9418461593FDF748FC1E
+:1046B00013901DB1AB6B002B00F0398219EE101A6C
+:1046C000B1F90C20950419EE100A93B207D4496E83
+:1046D00042F4005321F40051838141669BB21907D3
+:1046E00040F1AF8019EE102A1269002A00F0A9806B
+:1046F00003F01A030A2B00F0B5809FED9D7B002389
+:104700008DED107BCDE922331293149316930B9306
+:1047100019EE908A2EAB219399469AF80030002B1F
+:1047200000F00F81544604E014F8013F002B00F024
+:10473000E880252BF8D1B4EB0A0540F0E58023781A
+:10474000002B00F0FE8000231A468DF867301946D2
+:104750000A939B4666784FF0FF3304F1010A0993F0
+:104760000AF1010AA6F12003582B00F20581DFE8C7
+:1047700013F06E0203010301690203010301030147
+:104780000301030103011C026402030127022C023E
+:1047900003015F025900590059005900590059009E
+:1047A00059005900590003010301030103010301EA
+:1047B0000301030103010301030146028101030117
+:1047C00081010301030103010301A40203010301A9
+:1047D0009900030103010301030103018A0003019E
+:1047E0000301840203010301030103010301030127
+:1047F00003010301030103017602E201810181014A
+:104800008101A902E20103010301D9020301C302EC
+:104810009B00B302AE020301070303018C000301F6
+:104820000301E602A6F1300300201AF8016B00EB49
+:10483000800003EB4000A6F13003092BF5D90A9064
+:1048400090E719EE101A19EE900A01F0A7FA002865
+:1048500041F0318119EE103A9B8903F01A030A2BBB
+:104860007FF44BAF19EE103AB3F90E30002BFFF680
+:1048700044AF19EE101A19EE900A2346524601F081
+:1048800099F90B906CE04BF0100B1BF0200F00F02F
+:1048900042810D9B073323F00703F3E802450D9394
+:1048A00001230DE04BF0100B1BF0200300F02581DD
+:1048B0000D9B073323F00703F3E802450D93002314
+:1048C00000228DF867200E92099A1146013100F0FE
+:1048D0007C822BF08001079154EA050140F073823D
+:1048E000002A40F00383002B40F02E851BF00103CB
+:1048F0000C9300F0858530238DF8B7300DF1B707A4
+:104900008AE2B4EB0A051CD0DDE9223201332A44E5
+:10491000072BCDE92232C9F800A0C9F8045006DC03
+:1049200009F108090B9A23782A440B9208E719EE3B
+:10493000101A21AA404606F057FA58B90DF1B809E5
+:10494000F0E7239B33B119EE900A19EE101A21AA51
+:1049500006F04AFA19EE103A9B895B0601F1AB802A
+:104960000B983FB0BDEC068BBDE8F08FAFF3008035
+:104970000000000000000000002A40F0D187002E57
+:10498000DFD00122002308928DF890608DF8673007
+:104990000C9224AF00230993CDF81CB00F93079B12
+:1049A00013F0020302D0089A02320892079A12F01A
+:1049B000840B05D10A9A0899551A002D00F38D83AE
+:1049C000239C9DF8672072B1229A013201340DF1C7
+:1049D00067000121072ACDE92224C9E9000100F37B
+:1049E000B98309F108096BB1229B013302341AA97A
+:1049F0000222072BCDE92234C9E9001200F3B98362
+:104A000009F10809BBF1800F00F08E82099B0C9A16
+:104A1000A3EB020BBBF1000F00F3C982079BDB0580
+:104A200000F10A82229B0C9AC9F8007001331444E9
+:104A3000072B2394C9F80420229300F3418309F142
+:104A40000809079B5A0705D50A9B089A9D1A002D4D
+:104A500000F3A283DDE90A2308998A42ACBF9B18C0
+:104A60005B180B93002C40F0DD82002322930DF1A4
+:104A7000B80952E6002A41F012800D9B073323F05B
+:104A80000703B3EC027B8DED107BDDE910450D9340
+:104A900025F0004308EE903A08EE104AB34B51EC73
+:104AA000180B4FF0FF3208F023FA002840F0C284C0
+:104AB000AE4B51EC180B4FF0FF3208F0FBF9002819
+:104AC00040F0B884002200232046294608F0E8F987
+:104AD000002840F0FA869DF867300E93A44FA54B4E
+:104AE000032200212BF08000CDE908210790472EFA
+:104AF000C8BF1F460C920F9196E11BF010024ED1D9
+:104B00001BF040034BD00D9951F8044B0D91134607
+:104B1000A4B20025D4E60D9A1BF0100F52F8044BF6
+:104B20000D924FF0010300F079840025C8E6284675
+:104B3000FBF78AF8C2E5002A40F0A9871BF0200F96
+:104B40000D9B65D0073323F007031946F1E80223D4
+:104B50000D9114461D46002A73F10003C0F23C84F7
+:104B6000099B013300F00C852BF0800307939DF81F
+:104B700067300E9354EA050300F0E283DDF81CB0C1
+:104B8000002D08BF0A2C80F00385303401238DF8F6
+:104B9000B740CDF81CB00C930DF1B7073CE10D9A6E
+:104BA00052F8044B0D9200258AE60D9B53F8040B36
+:104BB0000A90002880F21F840A980D9340420A90C0
+:104BC0009AF800604BF0040BCAE5504610F8016BF0
+:104BD0002A2E00F0CB87A6F13003092B824698BF1E
+:104BE000002000F260871AF8016B00EB800003EBF5
+:104BF0004000A6F13003092BF5D90990B2E5002A4F
+:104C000040F055874BF0100B1BF0200F0D9B99D1F6
+:104C10001BF0100F53F8044B40F0D5831BF0400FEE
+:104C200000F0D18324B2E5170D9322462B4692E77C
+:104C30009AF800604BF0800B92E59AF80060012230
+:104C40002B218DE59AF800604BF0010B88E59AF86E
+:104C5000006000297FF484AD0122202180E50D9BB6
+:104C600053F8041B8DF890100022012108910D9338
+:104C70008DF867200C9124AF8CE6002A40F0FF8667
+:104C80003D4B14931BF0200F0D9B61D0073323F095
+:104C90000703F3E802450D931BF0010F0BD054EA14
+:104CA000050308D030238DF868308DF869604BF02B
+:104CB000020B022304E6022302E69AF800604BF09E
+:104CC000080B4DE59AF800604BF0400B48E59AF868
+:104CD00000604BF0200B43E50D9B53F8044B0D9304
+:104CE00047F63002254B1493ADF868204BF0020BC9
+:104CF000002502237826E3E5002A40F0C4861BF055
+:104D0000200F40F07F831BF0100F40F0A9841BF0B0
+:104D1000400F00F0A5840D9B0B9953F8042B0D93C5
+:104D20001180FAE49AF800606C2E03BF9AF80160D3
+:104D30004BF0200B0AF1010A4BF0100B10E5002A92
+:104D400040F0A9860D4B14931BF0200F0D9B9DD1B5
+:104D500053F8044B0D931BF0100F40F032831BF0FF
+:104D6000400F00F02E83A4B2002595E7FFFFEF7FF0
+:104D7000841E0208881E0208941E0208A81E02084B
+:104D80000D9C54F8047B00258DF86750002F00F02F
+:104D90003784099A1346013300F0F28429463846D5
+:104DA000FCF746F8002800F04A86C31B0C930995CF
+:104DB0000D94CDF81CB023EAE37308939DF8673097
+:104DC0000F950E9330E0DDF81CB0012B3FF4D8AE08
+:104DD000022B00F093802EAFE20842EA4572E90808
+:104DE00004F007030D461446303354EA05013A46F1
+:104DF00007F8013DF0D11BF0010F00F08F80302B40
+:104E000000F08C803023023A07F8013C2EAB9B1A4D
+:104E1000CDF81CB00C931746099B0C9A9342B8BF6F
+:104E20001346089300230F930E9B002B3FF4B7AD5E
+:104E3000089B01330893B2E5652E40F3FD80DDE960
+:104E400010010022002308F021F8002800F0DF8183
+:104E5000229BCE4AC9F80020013301340122072BDE
+:104E6000CDE92234C9F8042000F36E8409F1080961
+:104E70001B9B129A934280F2B982229B159AC9F821
+:104E80000020139AC9F8042001331444072B2394FB
+:104E9000229300F3A88309F10809129B5E1E002EDD
+:104EA0007FF7CFAD102E229BB94D40F3418419EE10
+:104EB00010BA102705E009F10809103E102E40F342
+:104EC000378401331034072BCDE92234C9E9005768
+:104ED000F1DD21AA5946404605F086FF00287FF4FF
+:104EE00039ADDDE922340DF1B809E6E7012B00F018
+:104EF0004A85022BDDF81CB07FF46DAF14982EAFFD
+:104F0000230904F00F0143EA05732A091C461546DC
+:104F1000435C07F8013D54EA0503F1D12EABDB1BDE
+:104F2000CDF81CB00C9377E70A9B089AA3EB020B11
+:104F3000BBF1000F7FF76AADBBF1100F229A944DC1
+:104F400027DD2146102319EE104A06E0ABF1100BC5
+:104F5000BBF1100F09F108091ADD01321031072ADF
+:104F6000CDE92221C9E90053F0DD21AA21464046BE
+:104F700005F03AFF00287FF4EDACABF1100BBBF16C
+:104F8000100FDDE922210DF1B8094FF01003E4DC28
+:104F90000C4601325C44072ACDE92224C9F80050AE
+:104FA000C9F804B000F3DE8309F108092EE5BBF16E
+:104FB000100F229A764D27DD2146102319EE104A54
+:104FC00006E0ABF1100BBBF1100F09F108091ADD77
+:104FD00001321031072ACDE92221C9E90053F0DD61
+:104FE00021AA2146404605F0FFFE00287FF4B2AC1E
+:104FF000ABF1100BBBF1100FDDE922210DF1B80967
+:105000004FF01003E4DC0C4601325C44072ACDE982
+:105010002224C9F80050C9F804B000F3C48109F192
+:105020000809FBE419EE101A21AA404605F0DCFE3F
+:1050300000283FF41AAD8DE4129B229E012B40F311
+:105040006181013601340123072ECDE92264C9F8BC
+:105050000070C9F8043000F3198309F10809139BA3
+:10506000159A01361C44072ECDE92264C9E90023B4
+:1050700000F3FE8209F108090023DDE91001002296
+:1050800007F004FF129B002840F06381013B0136CA
+:1050900001371C44072ECDE92264C9F80070C9F815
+:1050A000043000F33F8109F10809169A01361444CF
+:1050B0001DAB072ECDE92264C9E900327FF7BFACF2
+:1050C00019EE101A21AA404605F08EFE00287FF442
+:1050D00041AC239C0DF1B809B3E4102DDDE9222188
+:1050E00029DD0E9310244B460846B946374619EE83
+:1050F000106A04E0103D102D03F1080316DD0132A3
+:1051000024491030072ACDE92220C3E90014F1DD3B
+:1051100021AA3146404605F067FE00287FF41AAC0C
+:10512000103D102DDDE922202EABE8DC3E464F4637
+:1051300099460E9B014601321648C9F800006C18CA
+:10514000072ACDE92224C9F8045000F3AD8209F101
+:10515000080936E419EE101A21AA40460E9305F00C
+:1051600043FE00287FF4F6AB239C0E9B0DF1B8099B
+:1051700039E419EE101A21AA404605F035FE002840
+:105180007FF4E8AB239C0DF1B8093BE4C41E020890
+:10519000241F0208141F0208102D229B20DD19EE87
+:1051A000107A102604E0103D102D09F1080917DDD2
+:1051B00001339E4A1034072BCDE92234C9E9002679
+:1051C000F1DD21AA3946404605F00EFE00287FF4A5
+:1051D000C1AB103D102DDDE922340DF1B809E7DC3B
+:1051E0000133924AC9F800202C44072BCDE9223420
+:1051F000C9F804507FF72EAC19EE101A21AA4046C8
+:1052000005F0F2FD00287FF4A5AB239C22E41B9956
+:10521000002940F35982129B0F9A9342A8BF13466C
+:10522000002B1E460DDD229BC9F80070013334446B
+:10523000072B2394C9F80460229300F3E08309F15B
+:1052400008090F9B002EA8BF9B1B002B1E4600F3D6
+:10525000E1811B9A129B9A4280F2B881229B159998
+:10526000C9F800101399C9F8041001330C44072B36
+:105270002394229300F3388309F10809129B0F99B4
+:105280009A1A5B1A9342A8BF1346002B1E460EDDE6
+:10529000229BC9F8046001330F443444072BCDE945
+:1052A0002234C9F8007000F3B78309F10809002E11
+:1052B000ACBF961B1646002E7FF7C3AB102E229B69
+:1052C0005B4D40F3358219EE10BA102705E009F165
+:1052D0000809103E102E40F32B8201331034072BA7
+:1052E000CDE92234C9E90057F1DD21AA59464046EB
+:1052F00005F07AFD00287FF42DABDDE922340DF1B5
+:10530000B809E6E7079BD9073FF59BAE01360134A4
+:105310000123072ECDE92264C9F80070C9F80430D2
+:105320007FF7C1AE19EE101A21AA404605F05CFDC8
+:1053300000287FF40FABDDE922640DF1B809B4E673
+:10534000099B002B40F01F83002309930C932EAF81
+:1053500062E55F1E002F7FF7A8AE102F344D40F39B
+:105360005282CDF824A04FF0100B19EE10AA05E0E0
+:1053700009F10809103F102F40F343820136103421
+:10538000072ECDE92264C9E9005BF1DD21AA51466F
+:10539000404605F029FD00287FF4DCAADDE92264FF
+:1053A0000DF1B809E6E719EE101A21AA404605F0FA
+:1053B0001BFD00287FF4CEAA239C0DF1B809FFF74E
+:1053C0002DBB002568E4E51722460D93002A2B46E5
+:1053D00073F10003BFF6C4AB2D2364428DF8673030
+:1053E0000E9365EB45050123FFF76EBA079BDD07BA
+:1053F0007FF527AB41E59AF800600D93FFF7B0B950
+:105400002EAF09E50D9B53F8041B0D930B9BDD1785
+:105410001A462B46C1E90023FFF77FB91BF0400F66
+:1054200018BFA4B20025FFF74BBA00BF141F020833
+:10543000241F0208DDE9100102460B4607F058FD63
+:10544000002840F05D83099B013326F0200500F021
+:10545000F382472D00F07582DDE910014BF4807274
+:1054600000290792C0F237829DED107B002317932D
+:10547000B0EE47AAF0EE67AA662E00F0D781462E5E
+:1054800000F0D481452D00F08282099C01941FA870
+:105490001CA91BAA0223CDE90310029200934046E7
+:1054A00053EC1A2B00F082FD672E074640F06D8307
+:1054B0001BF0010F40F07F821F9B472DA3EB0703DA
+:1054C000129340F064831B9B0F93DA1C03DB099A51
+:1054D000934240F38582023E0F9A8DF87460531E0A
+:1054E000002B1B93B6BFC2F101032B222D22092BE7
+:1054F0008DF8752040F3FB820DF1830CC74D644697
+:1055000085FB0321DA17C2EBA10202EB8201A3EBB8
+:1055100041019E463031BEF1630F204604F8011C64
+:10552000134604F1FF34EBDC3033821EDBB29445CA
+:10553000214604F8013C40F225830DF1760201E09A
+:1055400011F8013B02F8013B8C45F9D10DF18503BF
+:105550000DF176021B1A13441DAA9B1A1693129A78
+:10556000169B012A13440C9340F3E8820C9B139A78
+:1055700013440C9323EAE373089300230F938BE106
+:10558000002D9DF867300E9308BF0A2CFFF4FDAA8A
+:105590002EAF204629460A22002307F057FD30325D
+:1055A00007F8012D00230A222046294607F04EFD68
+:1055B0002B462246002B08BF0A2A04460D46E8D295
+:1055C0002EABDB1BCDF81CB00C9325E4079BD80752
+:1055D0003FF544AE12990F9B8A1ACB1A9342A8BF8B
+:1055E00013461E4663E619EE101A21AA404605F03E
+:1055F000FBFB00287FF4AEA9239C0DF1B8094CE415
+:10560000099B874F062B28BF0623CDE90C3408934E
+:10561000FFF7C0B9102E229B824D40F349812246EC
+:105620004FF0100B19EE104A05E009F10809103E81
+:10563000102E40F33C8101331032072BCDE922328A
+:10564000C9E9005BF1DD21AA2146404605F0CCFB0B
+:1056500000287FF47FA9DDE922320DF1B809E6E7E1
+:105660000D9B0B9953F8042B11600D93FFF755B860
+:1056700019EE101A21AA404605F0B6FB00287FF467
+:1056800069A9DDE922640DF1B809F5E419EE101AF3
+:1056900021AA404605F0A8FB00287FF45BA9DDE9BC
+:1056A00022640DF1B809DAE419EE101A21AA404675
+:1056B0000E9305F099FB00287FF44CA9239C0E9BC8
+:1056C0000DF1B809FFF77DB9229B574AC9F80020B0
+:1056D000013301340122072BCDE92234C9F804201B
+:1056E00000F3108109F10809002954D1079B129A8F
+:1056F00003F0010313433FF4A4A9229B1399159AC5
+:10570000C9F8002001330A19072B2392C9F80410A5
+:10571000229300F31C8109F10809129901338C18B6
+:10572000072BCDE92234C9E900717FF788A9C7E4C6
+:1057300001333444072BC9F80050CDE92234C9F8AD
+:1057400004607FF77CA9BBE419EE101A21AA404639
+:1057500005F04AFB00287FF4FDA8239C0DF1B80951
+:10576000FFF786BB19EE101A21AA404605F03CFB54
+:1057700000287FF4EFA8239C0DF1B809FFF746B984
+:105780003846FCF7DDFB0995CDE90C04CDF81CB0DB
+:105790000346FFF710BB229B1398159AC9F8002007
+:1057A00001330219072B2392C9F80400229300F356
+:1057B000CE8009F108090029AFDA4E421031194DA7
+:1057C00080F27E8119EE10BA102405E009F1080973
+:1057D000103E102E40F3748101331032072BCDE9B7
+:1057E0002232C9E90054F1DD21AA5946404605F0AC
+:1057F000FBFA00287FF4AEA8DDE922320DF1B809EA
+:10580000E6E7DDF824A001363C44072ECDE922640A
+:10581000C9E900577FF747AC84E500BF6766666655
+:10582000BC1E0208241F0208C41E0208099C019421
+:105830001FA81CA91BAA0323CDE903100292009301
+:10584000404653EC1A2B00F0B1FB074604193B7895
+:10585000302B69D01B9B1C4451EC1A0B00220023F7
+:1058600007F014FB002800F0A8802346DB1B472D1F
+:1058700012933FF428AE662E40F089811B9A0F9256
+:10588000002A0BF0010340F3628109990B4340F0B9
+:105890004D810F9B08930C93179B002B00F0998070
+:1058A0002D238DF8673000230993FFF7C1BA144602
+:1058B00001333444072BCDE92234C9F80050C9F82C
+:1058C000046053DC09F10809C3E42D238DF8673027
+:1058D0000E93FFF703B901F100430AEE903A2D232E
+:1058E0000AEE100A1793C7E519EE101A21AA4046CE
+:1058F00005F07AFA00287FF42DA81B9A239C0DF15D
+:10590000B809BBE419EE101A21AA404605F06CFA5A
+:1059100000287FF41FA81B99239C0DF1B809E3E62A
+:105920008DF86710FFF72BB851EC1A0B00220023FB
+:1059300007F0ACFA00288DD1099BC3F101031B933A
+:1059400089E7099B002B08BF0123099384E519EE21
+:10595000101A21AA404605F047FA00287EF4FAAF53
+:10596000DDE922321B990DF1B80924E719EE101A6E
+:1059700021AA404605F038FA00287EF4EBAF239CBC
+:105980000DF1B80965E4DDF81CB0FFF7FEB8099B1E
+:105990001FA85C1C1CA91BAA0223CDE903100292BC
+:1059A0000093019453EC1A2B404600F0FFFA07468F
+:1059B000472E3FF47DAD3C444EE71F9BA342BFF40E
+:1059C00055AF30215A1C1F9219701F9B9C42F9D869
+:1059D0004CE79DF867300E93179B0993FFF724BAA5
+:1059E000129B19460F9B994236DC1BF0010F40F0C9
+:1059F000948023EAE37208920C9367264CE719EE31
+:105A0000101A21AA404605F0EFF900287EF4A2AF53
+:105A1000239C0DF1B80914E419EE101A21AA40468E
+:105A200005F0E2F900287EF495AF1B9A129B239CA7
+:105A30009A1A0DF1B8093AE4062309930CE5099B7B
+:105A400008930C939DF8673009900D94CDF81CB025
+:105A50000F900E93FFF7E8B9DDE9123213440F9A65
+:105A60000C93002A06DC0F9B0C9AC3F101031A4425
+:105A700013460C9223EAE373089367260CE78DF82C
+:105A80006710FFF7FDB88DF86710FFF738B98DF88C
+:105A90006710FFF753B88DF86710FFF753B98DF80B
+:105AA0006710FEF7EABF00230993FEF75BBE8DF88F
+:105AB0006710FFF7A7B84FF0FF330B93FEF750BF07
+:105AC00001333244072BCDE92232C9E900567FF772
+:105AD00022AE19EE101A21AA404605F085F90028D9
+:105AE0007EF438AFDDE922320DF1B80915E6303326
+:105AF00030228DF8773004238DF8762016932EE52A
+:105B0000119B244F002BB6BF2D239DF867308DF8D5
+:105B100067300E93204BFEF7E3BF0F9B139A13449D
+:105B20000C9323EAE37308936726B5E6139BD31817
+:105B3000194421EAE1730C910893ADE61BF00102D0
+:105B40000F927FF413AD23EAE3730893A4E6099A56
+:105B5000134303D1012308930C939DE6139B013358
+:105B60001A4422EAE2730C92089395E60D9B9AF888
+:105B7000016053F8044B0D93824644EAE4700990A7
+:105B8000FEF7EEBD02231693E9E4099C10E71B9B88
+:105B90000F93A1E48C1E0208901E020830B4044C3E
+:105BA0000D46134601462A46206830BCFEF76CBD00
+:105BB000C8040020F0B50C46ADF26C4D8989666EC4
+:105BC000E589199621F00201666AADF80E500025AC
+:105BD000E769ADF80C10099606951AAE4FF480658A
+:105BE0006946009604960295059507970646FEF7C6
+:105BF0004BFD051E07DB30466946F9F725FF0028F7
+:105C000018BF4FF0FF35BDF80C305B0603D5A389F4
+:105C100043F04003A38128460DF26C4DF0BD00BF58
+:105C200070B5141E9AB005462CDB4FF40272009139
+:105C30000491ADF80C2014D01A46013C1E9B02942E
+:105C40004FF6FF7669460594ADF80E60FCF768FAEA
+:105C5000421C01DA8B232B60009B00221A701AB0C1
+:105C600070BD1A464FF6FF761E9B02946946059456
+:105C7000ADF80E60FCF754FA431C01DA8B232B605D
+:105C80001AB070BD8B2303604FF0FF30F8E700BF00
+:105C900070B5064C82B00E4615460146009320684A
+:105CA00032462B46FFF7BCFF02B070BDC80400208F
+:105CB000F8B50D461446064610B1836B002B43D051
+:105CC000B4F90C20A369A360170790B21BD5236910
+:105CD000CBB1EDB281042F4622D522686169D31A77
+:105CE000994229DD0133A168501C0139A16020606F
+:105CF000157062699A422AD0A389DB0701D50A2D63
+:105D000025D03846F8BD2146304600F047F820BB84
+:105D1000B4F90C20236990B2EDB281042F46DCD493
+:105D2000616E42F4005221F40051A2812268616642
+:105D30006169D31A9942D5DC21463046F9F784FED1
+:105D400058B922680123CEE7F9F77EFFB8E721466C
+:105D50003046F9F779FE0028D3D04FF0FF37D0E76F
+:105D6000024B0A4601461868FFF7A2BFC80400208C
+:105D700070B50C46084D114600261A4603462046CB
+:105D80002E601C46EBF72CFE431C00D070BD2B6828
+:105D9000002BFBD0236070BD00E6002038B5324BED
+:105DA0001B6805460C4613B19A6B002A3CD0B4F927
+:105DB0000C3018079AB20CD52169A9B112F0010074
+:105DC00022D0606900254042A061A56011B3002087
+:105DD00038BDD10640D552072AD4216943F00803C3
+:105DE000A3819AB20029E9D102F42070B0F5007FB6
+:105DF000E4D028462146FAF705FDB4F90C302169B4
+:105E00009AB212F00100DCD1950758BF6069A0601A
+:105E10000029DCD1120658BF0846D9D543F040030B
+:105E2000A3814FF0FF3038BD1846F9F70DFFBEE7EC
+:105E3000216B51B104F14002914204D02846EBF7A6
+:105E400099FCB4F90C300022226321692160002200
+:105E5000626023F02403C1E743F0400309222A6073
+:105E60004FF0FF30A38138BDC804002038B5074D7E
+:105E70000022044608462A60EBF792FD431C00D03E
+:105E800038BD2B68002BFBD0236038BD00E6002016
+:105E90002DE9F04F03690E69B34283B0C0F28280EE
+:105EA000013E01F1140700F1140A57F826305AF8A0
+:105EB000262001338346B00000909A420AEB860008
+:105EC00007EB86090190B2FBF3F836D300252A468A
+:105ED000BC4650465CF8044B03681FFA84FE08FB7E
+:105EE0000E554FEA154E240C08FB04E4ADB2551BC9
+:105EF000A2B2C2EB134215FA83F302EB23429BB228
+:105F000043EA0243E14540F8043B4FEA14454FEAB7
+:105F10002242DFD2009B5AF8033073B9019B043B45
+:105F20009A4504D307E09A4506F1FF3603D253F8A9
+:105F30000429002AF7D0CBF81060584601F0A6FBE0
+:105F400000282BDB08F101085046002357F8041BFA
+:105F500004688AB29A1A0B0C12FA84F2C3EB144347
+:105F600003EB224392B242EA0342B94540F8042BC4
+:105F70004FEA2343EAD25AF826200AEB86036AB98D
+:105F8000043B9A4504D307E09A4506F1FF3603D255
+:105F900053F80429002AF7D0CBF81060404603B02C
+:105FA000BDE8F08F002003B0BDE8F08F2DE9F04F81
+:105FB0002DED048B016C97B090469946CDE906898A
+:105FC000279D044641B1426C4A60012393408B6097
+:105FD00001F0CCF800232364B9F1000AB4BF012317
+:105FE00000232B60764BBCBF2AF0004ACDF81CA0E2
+:105FF00033EA0A0300F0AB809DED067B002251ECF2
+:10600000170B00238DED047B06F040FF074680B19F
+:10601000269A01231360289B002B00F0DC8269483C
+:106020001860431E0393039817B0BDEC048BBDE8C2
+:10603000F08F14AA15ABCDE900322046DDE9042328
+:1060400001F06CFC5FEA1A56054640F09880DDE9E5
+:1060500014763E4406F23240202840F3B183C0F16A
+:10606000400306F212400AFA03FA28FA00F04AEA5C
+:10607000000006F029FC0123013EA1F1F8710E9306
+:10608000514B002206F0E2FA47A3D3E9002306F0C1
+:1060900095FC47A3D3E9002306F0DAFA80463046A0
+:1060A000894606F021FC44A3D3E9002306F086FCD0
+:1060B00002460B464046494606F0CAFA80468946E3
+:1060C00006F02CFF0022834600234046494606F096
+:1060D000E7FE002840F07282BBF1160F00F26182E9
+:1060E0003A4B03EBCB03D3E90023DDE9040106F0CF
+:1060F000D7FE002870D00023BE1B0D93731E0BF13A
+:10610000FF3B089300F1548200230B93BBF1000F77
+:1061100069DA0B9BCDF824B0A3EB0B030B93249B04
+:10612000092BCBF1000A4FF0000B65D8052B40F38B
+:106130004583043B24930026249B023B032B00F25F
+:10614000AA86DFE813F060045D0454043704269A3D
+:1061500042F20F73CAF3130A13605AEA08031CD100
+:10616000289B002B00F09386194B03930833289A41
+:106170000398136017B0BDEC048BBDE8F08FDDE928
+:106180000412C2F31303084643F07F510E97A6F2A0
+:10619000FF36149F41F4401172E7289B002B40F01A
+:1061A000EC830C4B03933EE761436F63A787D23FB9
+:1061B000B3C8608B288AC63FFB799F501344D33FF6
+:1061C0000000F07FC51E02080000F83FE82002082A
+:1061D0003C20020838200208BE1B731E089300F101
+:1061E000E0840D900B90089B5B44CDE9083B249B19
+:1061F000092B4FF0000A99D90023012624932593F7
+:106200004FF0FF330C960A930A9B109300216164B0
+:10621000204600F085FF0390002800F04486039B91
+:1062200023640A9B0E2B00F20181002E00F0FE80F9
+:106230000999002940F37F84C24B01F00F0203EB60
+:10624000C2034FEA2118C905D3E9006740F1188459
+:10625000BD4BDDE90401D3E9082306F0D9FC032393
+:1062600041EC180B08F00F080F93B8F1000F1DD088
+:10627000CDF844B0DFF8D092D346DDF83CA018F05A
+:10628000010F09D030463946D9E9002306F096FBC4
+:106290000AF1010A06460F465FEA680809F1080993
+:1062A000EDD1CDF83CA0DA46DDF844B051EC180B46
+:1062B00032463B4606F0ACFC804689460D9B43B116
+:1062C000A24B00224046494606F0EAFD002840F075
+:1062D00065850F9806F008FB42464B4606F06EFBBC
+:1062E0009B4B002206F0B4F90A9B0646A1F15077B9
+:1062F000002B00F0ED83099B11930A9B0F930C9BDD
+:10630000002B00F0D9840F9A8E4B924903EBC20305
+:1063100053E90223002006F07BFC32463B4606F0A0
+:1063200095F906460F464046494606F0F7FD12909D
+:1063300006F0DAFA02460B464046494606F086F970
+:10634000129BDDF80C8047EC186B303308F8013BEA
+:1063500006460F4602460B4651EC180B06F0BEFDF2
+:10636000002840F067854FF0000909EE105A09EE49
+:10637000904A45464C46CDE912AB59EC188B2AE0C1
+:106380000F9B01349C424BDA734B40464946002236
+:1063900006F014FB704B0022804689463046394691
+:1063A00006F00CFB8B46824606F0B8FD074606F069
+:1063B0009BFA02460B465046594606F047F93037DD
+:1063C00005F8017B42464B4606460F4606F068FD3F
+:1063D000002840F02A8532463B465C49002006F002
+:1063E00035F942464B4606F05BFD0028C8D0119BAC
+:1063F000039A0993A84619EE904A19EE105A02E042
+:10640000904500F0F784C14618F8013D392BF7D0CC
+:106410000133DBB288F80030099B01330993ADE109
+:10642000DDE912AB19EE105A19EE904A159B002BBC
+:10643000C0F29680099A0E2A00F39280414B03EB3A
+:10644000C203D3E900AB259B002B1BDA0A9B002B70
+:1064500018DC40F05683414B50460022594606F066
+:10646000ADFA02460B46DDE9040106F023FDDDF836
+:1064700028A05646002800F0DE82259BDDF80C801F
+:10648000DF43E1E2DDE9046752465B4630463946C8
+:1064900006F0BEFB06F042FD814606F025FA5246A4
+:1064A0005B4606F08BFA0B4602463946304606F04C
+:1064B000CDF8DDF80C804B46303308F8013B0A9BE1
+:1064C000012B00F09F834FF0010908EE105A08EEEF
+:1064D000904A1D464446C8461DE052465B4630463B
+:1064E000394606F095FB06F019FD814606F0FCF9E9
+:1064F00052465B4606F062FA08F101080B46024676
+:106500003946304606F0A2F809F13003454504F853
+:10651000013B00F07283104B002206F04FFA00227C
+:10652000002306460F4606F0B1FC0028D5D0A04651
+:1065300018EE105A18EE904A099B01330993C14690
+:106540001CE100BFE8200208D82102080000F03F4B
+:1065500000001C400000E03F000024400000144008
+:106560000C9A002A3FD0249A012A40F3CE820A9B3B
+:1065700003F1FF38C245C0F27C82AAEB08080A9BEF
+:10658000002BC0F27183089A11460B9A19441746E2
+:106590001A4408910B920121204600F0F1FE0646B4
+:1065A00024E00123BE1B0D93731E08937FF5ACAD51
+:1065B000C6F101030B9300230893A7E5584606F0A4
+:1065C00093F942464B4606F061FC00287FF484AD07
+:1065D0000BF1FF3B80E5CB4B0393039817B0BDEC69
+:1065E000048BBDE8F08FDDE90B76D046002F0CDD83
+:1065F000089A002A09DD0B99BA421346A8BF3B4608
+:10660000C91AFF1AD31A0B910893BAF1000F1BD0C5
+:106610000C9B002B00F0AA81B8F1000F10DD314671
+:106620004246204600F072FF2A46014606462046B2
+:1066300000F0BCFE2946034620461D4600F096FDAC
+:10664000BAEB080240F093810121204600F098FE49
+:10665000BBF1000F824600F3B880249B012B40F36E
+:1066600091814FF000090120BBF1000F40F0B9808B
+:10667000089A104410F01F0000F09780C0F120032A
+:10668000042B40F317840B9BC0F11C00034402440D
+:106690000B93074408920B9B002B05DD29461A46F5
+:1066A000204600F07FFF0546089B002B05DD514684
+:1066B0001A46204600F076FF82460D9B002B40F0E4
+:1066C0003A810A9B002B40F31F810C9B002B40F06A
+:1066D0009F80099B01330993DDF80C80DDF8289039
+:1066E000012707E0294600230A22204600F048FD42
+:1066F0000137054651462846FFF7CAFB4F4500F1D2
+:10670000300008F8010BEDDB0A9A002AC8BF934657
+:10671000039AD8BF4FF0010B034693440027294644
+:1067200001222046049300F03DFF5146054600F04B
+:10673000ADFF002840F3B3811BF8013C039A0BF135
+:10674000FF3B04E05A4500F0EF811BF8013D392B77
+:106750000BF10109F6D001338BF800305146204689
+:1067600000F004FD56B12FB1B74203D039462046A0
+:1067700000F0FCFC3146204600F0F8FC294620469B
+:1067800000F0F4FC002389F80030269B1A46099B90
+:106790001360289B002B3FF446AC0398C3F800908D
+:1067A00017B0BDEC048BBDE8F08F1C200B9B03449D
+:1067B0000B93089B0344074408936CE70126BBE452
+:1067C000C0F1200008FA00F053E401465A46204682
+:1067D00000F09CFE249B012B824640F3E4814FF0A5
+:1067E0000009DAF810300AEB8303186900F078FD2D
+:1067F000C0F120003CE7314600230A22204600F089
+:10680000BFFC109B002B064640F32D83CDE9098386
+:10681000002F00F32781B9F1000F40F00E82B0463F
+:10682000069B2499039F03F001020C920A430B92EA
+:106830000A9A7B1E1A440A9251462846FFF728FB03
+:1068400031468346284600F021FF424651468146A4
+:10685000204600F039FFC26801460BF13003002AE0
+:1068600042D106902846089300F010FF0699049044
+:10687000204600F07BFC049A089B1AB90B9900296A
+:1068800000F0E382B9F1000FC0F29981249941EA46
+:1068900009090C9951EA090100F09181002A00F3DD
+:1068A000E7810A9A3B7007F101099742CB4600F055
+:1068B000F981294600230A22204600F061FC464562
+:1068C000054631464FF000034FF00A02204612D031
+:1068D00000F056FC4146064600230A22204600F0FE
+:1068E0004FFC4F468046A7E72046049300F03EFC4D
+:1068F000049B0122C6E700F043FC4F460646804653
+:106900009AE700BFC41E0208249B022B00F382807A
+:106910000C9B002B7FF47CAF51462846FFF7B8FA5A
+:10692000099ADDF80CB000F1300301320BF8013B9D
+:1069300009920027F3E65146284600F0A7FE0028FA
+:10694000BFF6BFAE294600230A22204600F018FCFD
+:10695000099B03F1FF380C9B0546002B7FF44BAFDE
+:10696000109B002B40F378820A93B5E652462946E5
+:10697000204600F0CBFD054666E6C44B0393033387
+:10698000FFF7F5BBDDE9061200297FF46AAEC2F31A
+:106990001303002B7FF465AEBD4B1340002B00F0BA
+:1069A0003D820B9B01330B93089B013308934FF0FF
+:1069B000010958E601230C93259B099A134410936F
+:1069C0000133012B1F460A93B8BF01270021172F5F
+:1069D00061647FF71DAC012204235B0003F1140006
+:1069E000B842114602F10102F7D9616410E40123B3
+:1069F0000C93259B002B4DDD10930A931F46E5E772
+:106A000000230C93D8E700230C93F2E7109BCDF8FA
+:106A100024800A930A9B002B7FF42FAD5146052258
+:106A2000204600F0ADFB01468246284600F02EFECF
+:106A300000287FF722ADDDF80C80099F4346312204
+:106A400003F8012B013703935146204600F08EFBDB
+:106A50007B1CDDF80C900993CDF80C80002E7FF4A0
+:106A600089AE8BE631463A46204600F09BFD06464D
+:106A7000D1E6A8EB0A039B44C2464FF000087EE52E
+:106A80009DED047B02230F93B0EE478AF0EE678AF8
+:106A9000FFF7EBBB012325930A93FFF7B5BB03D1A7
+:106AA000049BDB073FF548AED9461BF8013D302B70
+:106AB000FAD053E60F9805F017FF42464B4605F013
+:106AC0007DFF744B002205F0C3FD0646A1F150770F
+:106AD000714B40464946002205F0B8FD32463B4620
+:106AE0008046894606F0FAF9002840F09381324644
+:106AF00007F100434046494606F0D2F900283FF42A
+:106B000095AC4FF0000A5646B7E40E9A002A00F002
+:106B1000CF8003F23343089A1A4408920B9A17461F
+:106B20001A440B92D04636E5099A01320992039A2B
+:106B30003123137012E600F05781099B5E42574BD8
+:106B400006F00F0203EBC203D3E90023DDE90401E1
+:106B500005F034FF36118046894600F08D8102220F
+:106B60004F4F49EC188B0023D946D3469246F20783
+:106B700006D5D7E9002305F021FF0AF1010A012318
+:106B8000761007F10807F2D1CDF83CA0DA46CB46E3
+:106B900059EC188B002B3FF491AB80468946FFF7E8
+:106BA0008DBB0D9004E5069B002B7FF418AEDDE94C
+:106BB0000612C2F31303002B3FF4EEAE0FE6002AD9
+:106BC00012DD294601222046049300F0EBFC5146D9
+:106BD000054600F05BFD0028049B40F33081392B13
+:106BE00000F00E810BF13103B946374609F8013B3D
+:106BF000099B013309934646B0E5A04618EE105AAA
+:106C000018EE904A02460B4605F022FD52465B46BE
+:106C100006460F4606F062F960B952465B463046BA
+:106C2000394606F033F900283FF486AC5FEAC971B3
+:106C30007FF582AC039AFFF7E6BB7168204600F04F
+:106C40006FFA0746002800F01B81336902339A006F
+:106C500006F10C010C30FAF73BF9394601222046C7
+:106C600000F0A0FC8046DBE5DDE90A239F1A92E4F0
+:106C7000392B00F0C580B946013309F8013B099B67
+:106C8000013337460993464668E500BF38200208BD
+:106C90000000F07F00001C4000001440E8200208C3
+:106CA000D8210208099A013237460992464636E54C
+:106CB000149BC3F136032EE70F9B864901EBC301FA
+:106CC00032463B4651E9020105F078FE02460B468A
+:106CD0004046494643EC182B06F020F9074605F0DC
+:106CE00003FE0B4602464946404605F0AFFCDDF880
+:106CF0000C8007F1300308F8013B0F9B012B06467F
+:106D00000F4627D00F9B039ACDF83CA01344CDF833
+:106D100048B0C2469B46704B00223046394605F0CB
+:106D20004DFE8946804606F0F9F8074605F0DCFD81
+:106D3000303702460B464046494605F087FC0AF8C4
+:106D4000017BDA4506460F46E5D1D046DDF848B06E
+:106D5000DDF83CA0614B002251EC180B05F078FCEB
+:106D600032463B4606F09CF8002859D153EC182BCC
+:106D70005A49002005F06AFC32463B4606F0AEF860
+:106D800000283FF453ABC14608F1FF3819F8013C25
+:106D9000302BF8D0119B01330993EFE40A9B002BB1
+:106DA0003FF488AE109B002B7FF740AB4A4B00228C
+:106DB0004046494605F002FE80460F98894601305C
+:106DC00005F092FD42464B4605F0F8FD444B00228B
+:106DD00005F03EFC099A109B0F93013A0646A1F17B
+:106DE00050771192FFF78BBA0223DDE904890F93E4
+:106DF000FFF764BA099B013309933123FFF70ABBFC
+:106E0000099ABB463923013237460BF8013B0992F8
+:106E1000464693E44FF0000A56460CE6994622E4B3
+:106E2000119B039A0993FFF7EEBAA84619EE904A10
+:106E300019EE105A119B01330993C1469EE47FF469
+:106E4000D3AEDA077FF5D0AEC9E6392BD8D0B9F189
+:106E5000000F3FF7C7AEC7E6249B022B3FF7D6AD26
+:106E6000CDF8248058E5249B022B3FF7CFAD109B33
+:106E7000CDF824800A93CBE402230F93FFF71EBAC8
+:106E80000246184B184840F2EA2104F0FBFD174B6C
+:106E90000393FFF7C8B8002666643146204600F029
+:106EA0003FF9039058B90F4B0F4800224FF4D571AA
+:106EB00004F0E8FD3FF4EFABC0F13C0076E44FF0A6
+:106EC000FF33039A10930A930123226425960C93AF
+:106ED000FFF7ACBAE8200208000024400000E03FC1
+:106EE00000001C40482002085C2002083C200208E8
+:106EF00030B40B78722B35D0772B06D0612B2BD08A
+:106F00001623036030BC002070474FF4C065012495
+:106F100008204B7801312BB90EE02B2B13D011F840
+:106F2000013F4BB1622B0BD0782BF6D111F8013F0A
+:106F300044F40064002BF5D12C43146030BC70473E
+:106F400044F48034EBE720F01C0024F0030440F00C
+:106F5000100044F00204E2E74FF4027501244FF4FC
+:106F60008470D6E700252C460420D2E738B5074DBB
+:106F70000022044608462A60EAF7B2FD431C00D00E
+:106F800038BD2B68002BFBD0236038BD00E6002005
+:106F9000002100F001B800BFFF289DBF024BC05C7C
+:106FA00000F0080000207047351F020842B110B5FC
+:106FB0000B4910461446FAF7E7FD18B9094810BD09
+:106FC0000848704707492046FAF7DEFD0028F5D04B
+:106FD00005492046FAF7D8FD0028EFD0002010BD63
+:106FE0009420020890200208D0220208014B93F856
+:106FF00028017047080D0020024B0A460146186818
+:10700000FFF7D4BFC8040020F03070470048704735
+:10701000F80D002000487047F80D002070B50C46B0
+:10702000084D114600261A46034620462E601C468F
+:10703000EAF774FD431C00D070BD2B68002BFBD019
+:10704000236070BD00E6002070B582B00646069C45
+:1070500042B10C4D0094D5F8E450A847431C0BD026
+:1070600002B070BD074B0094D3F8E45011460123E1
+:10707000054AA847431CF3D100228A2322603360CB
+:1070800002B070BD080D0020D0220208F0B5114CEE
+:1070900083B026681D4661B10F4F0093D7F8E440D6
+:1070A00013460A4601463046A047431C0BD003B0A6
+:1070B000F0BD094B0095D3F8E440084A012330465F
+:1070C000A047431CF3D100228A232A60336003B017
+:1070D000F0BD00BFC8040020080D0020D022020827
+:1070E00010B4034CD4F8E440A4465DF8044B604768
+:1070F000080D002082B049B15AB16BB113780B6012
+:107100001278101E18BF012002B0704701A9002A92
+:10711000F3D1104602B070476FF00100F4E700BFF2
+:10712000C36C70B505460C464BB153F8240080B1D2
+:10713000026843F824200023C0E9033370BD2122F4
+:107140000421EAF719FB0346E8640028EDD100208A
+:1071500070BD012101FA04F6721D28469200EAF77B
+:107160000BFB0028F3D0C0E90146E4E731B1C36C62
+:107170004A6853F82200086043F82210704700BFA5
+:107180002DE9F8430F69884681461D4601F1140038
+:1071900000210668B4B202FB04531C0C350C02FB40
+:1071A000054501319CB204EB05448F4240F8044B85
+:1071B0004FEA1545EDDC4DB1D8F80830BB4208DD8B
+:1071C00008EB870301375D61C8F810704046BDE8E1
+:1071D000F883D8F8041048460131FFF7A1FF0446B0
+:1071E000D0B1D8F81020023208F10C0192000C3016
+:1071F000F9F76EFED9F84C30D8F8042053F8221075
+:10720000C8F8001043F82280A04608EB8703013736
+:107210005D61C8F81070D9E70246024B0248B521FB
+:1072200004F030FC48200208A02002082DE9F047B5
+:107230001F46284B089D07F1080C83FB0C3E092FC5
+:107240004FEAEC73064689469046C3EB6E0339DD80
+:10725000012400216400A34201F10101FADC30465F
+:10726000FFF75EFF014678B30123B8F1090FC0E9CB
+:10727000043515DC09F10A044FF0090847450CDD17
+:10728000A7EB0805254414F8013B0A22303B3046A1
+:10729000FFF776FFA5420146F5D10846BDE8F08725
+:1072A00009F1090A5546C14415F8013B0A22303B51
+:1072B0003046FFF765FF4D450146F5D1A8F10804BA
+:1072C0005444DBE70021CAE70246034B0348CE21C2
+:1072D00004F0D8FB398EE33848200208A0200208C9
+:1072E000030C1B04D3B90004102310F07F4F04BF1C
+:1072F0000002083310F0704F04BF0001043310F097
+:10730000404F04BF80000233002805DB10F0804F9F
+:1073100003F1010308BF2023184670470023E4E768
+:10732000036813F00702014607D0DA0720D4980754
+:1073300022D55B080B600120704798B2A8B11046B7
+:1073400013F0FF0F04BF1B0A08301A0704BF1B0904
+:1073500004309A0704BF9B080230DA0703D45B08A5
+:1073600000F1010006D00B6070471B0C1020E7E70E
+:1073700000207047202070479B080B600220704758
+:1073800010B50C460121FFF7CBFE024618B10123D0
+:10739000C0E9043410BD034B03484FF4A07104F05E
+:1073A00071FB00BF48200208A02002082DE9F04F21
+:1073B0000D691769BD4285B00E46144605DB3A4695
+:1073C00023462F460C4615461E46D4E9011307EB0B
+:1073D00005084345B8BF0131FFF7A2FE0190002820
+:1073E00000F08880019B03F1140909EB880AD1455C
+:1073F00005D24B46002243F8042B9A45FBD806F1F0
+:10740000140E0EEB850B04F11403DE451A4603EB54
+:1074100087073ED23B1B153B23F00303043315348F
+:10742000A74238BF0423CDE902A89846924603E05C
+:10743000F34509F104092AD95EF8040B86B2002E3F
+:1074400038D1000CF4D0D9F8003054461E464D46D1
+:107450004FF0000C2288360C00FB0266B4449BB24D
+:1074600043EA0C4345F8043B54F8043B2E681B0CDC
+:10747000B2B200FB032303EB1C43A7424FEA134CB9
+:10748000E8D8F34549F8083009F10409D4D8DDE912
+:1074900002A8B8F1000F03DC06E0B8F1010803D040
+:1074A0005AF8043D002BF8D00198C0F8108005B0C0
+:1074B000BDE8F08F55464C46002355F8041B206864
+:1074C0008AB21FFA80FC06FB02C2090C000C1344AE
+:1074D00006FB010202EB13429BB243EA0243AF42B6
+:1074E00044F8043B4FEA1243E7D849F808305EF805
+:1074F000040CA6E70246034B034840F25D1104F07A
+:10750000C1FA00BF48200208A020020812F00303BD
+:107510002DE9F041144607462ED10E46A4101CD08A
+:10752000BD6C95B3E3074FF0000806D4641014D087
+:107530002868A8B10546E307F8D52A4631463846FB
+:10754000FFF734FFB6B17168FB6C641053F821206B
+:10755000326043F821600646EAD13046BDE8F0814A
+:107560002A4629463846FFF721FF2860C0F80080E8
+:107570000546E0E70646D9E7013B094A52F82320D1
+:107580000023FFF7FDFD0646C8E740F271213846AB
+:10759000FFF7F6FE0023B86405460360C2E700BFAC
+:1075A000D82002082DE9F0470F690D46D1E90113F3
+:1075B00007EB62177E1C9E42914680464FEA62149A
+:1075C00004DD5B009E4201F10101FADC4046FFF759
+:1075D000A7FD00284FD0002C00F114010DDD621D25
+:1075E0004FEA820C0B4600EB8202002443F8044B66
+:1075F0009342FBD1ACF1140319442C6905F1140337
+:1076000019F01F0903EB840C2DD0C9F120028E461E
+:107610004FF0000A1C6804FA09F444EA0A044EF820
+:10762000044B53F8044B9C4524FA02FAF2D8ACEB15
+:107630000503153B23F00303043305F115029445BC
+:1076400038BF0423BAF1000F18BF374641F803A032
+:10765000D8F84C306A68076153F82210296043F863
+:107660002250BDE8F087043953F8042B41F8042F69
+:107670009C45F9D8ECE70246024B034840F2D91189
+:1076800004F000FA48200208A020020830B40B6978
+:1076900005460069C01A11D11435143101EB83027B
+:1076A00005EB830301E09D4208D253F8044D52F8E4
+:1076B000041D8C42F7D003D24FF0FF3030BC70472E
+:1076C000012030BC704700BF2DE9F84F0D690C4612
+:1076D00011696D1A002D90467AD104F11407143205
+:1076E00007EB810302EB810201E09F4273D253F862
+:1076F000046D52F8041D8E42F7D064D36168FFF721
+:107700000FFD002871D02769D8F81030C56004F14A
+:10771000140A08F1140500F1140605EB830910346E
+:107720000AEB870EB446002355F804BB54F8042F27
+:107730001FFA8BF113FA82F34FEA1B4B591ACBEB6A
+:10774000124303EB214389B241EA0341A9454CF8B6
+:10775000041B4FEA2343E7D8A9EB0802153A08F1C6
+:107760001508C14522F0030505F1040538BF0425BD
+:10777000AA4422F0030238BF0022D64535441644FD
+:1077800018D92E46524652F8044B13FA84F10B14C2
+:1077900003EB144389B241EA0341964546F8041BC2
+:1077A0004FEA2343EFD80EF1FF36A6EB0A0626F088
+:1077B00003062E4421B956F8043D013F002BFAD0B0
+:1077C0000761BDE8F88F234601254446984695E7B2
+:1077D000F9DB002592E70021FFF7A2FC60B101224E
+:1077E0000023C0E90423BDE8F88F0246064B074892
+:1077F0004FF4107104F046F90246034B034840F27F
+:10780000322104F03FF900BF48200208A0200208FE
+:107810000F4B0B40A3F15073002B02DD00201946E3
+:1078200070475B42B3F1A07F4FEA235205DA4FF471
+:107830000023002043FA02F17047143A1E2ADABFEF
+:107840004FF0004323FA02F2012200211046704754
+:107850000000F07F0269F8B500F1140707EB82021F
+:1078600052F8046C3046FFF73BFDC0F120030A28B4
+:107870000B60A2F1040333DD9F421DD2B0F10B0374
+:1078800052F8081C24D0C3F1200C9E4021FA0CF0C1
+:10789000064346F07F55A2F10806B74245F440156D
+:1078A00037D252F80C2C01FA03F022FA0CF31843E9
+:1078B000044620462946F8BD0B3808D006FA00F3E6
+:1078C00043F07F55002045F440150446F1E701469A
+:1078D00046F07F550C4645F4401520462946F8BD34
+:1078E0009F42C0F10B0138BF52F8082C26FA01FC68
+:1078F00000F1150338BFCA404CF07F5528BF002265
+:1079000006FA03F345F4401543EA020420462946EB
+:10791000F8BD01FA03F00446CBE700BFF0B5012142
+:1079200083B016461F46FFF7FBFB044600284AD0EB
+:10793000C7F30A55C7F313030DB143F48013002EA8
+:10794000019322D068460096FFF7EAFC002836D063
+:10795000DDE90013C0F1200203FA02F20A43C3403A
+:1079600001936261002B14BF02220122A3612261F4
+:10797000ADB1089AA5F2334303441360099BC0F1EB
+:1079800035001860204603B0F0BD01A8FFF7C8FC21
+:10799000019B6361012220302261002DE9D104EBBB
+:1079A00082030899A0F2324008601869FFF798FC3A
+:1079B000099BC0EB42101860204603B0F0BDDDE922
+:1079C00000236261CEE70246024B034840F20A31CF
+:1079D00004F058F848200208A02002082DE9F043DE
+:1079E00083B00F4669460646FFF734FF04460D464E
+:1079F000384601A9FFF72EFF32693E69019BA2EBD1
+:107A0000060C009AD31A03EB4C13002B0F460CDD27
+:107A100005EB035906464D4632463B46204629466D
+:107A200005F0F6F803B0BDE8F083C3EB033301EBD8
+:107A3000035106460F46EFE7172870B506460ADDE4
+:107A40000849094D0020002422462B4604F0B6FFC9
+:107A5000013EF9D170BD054B03EBC006D6E9040128
+:107A600070BD00BF0000F03F00002440D820020895
+:107A700070B41469013902F114034D1103EB840150
+:107A800001358B4200EB85040CD2051F53F8046BC3
+:107A900045F8046F9942F9D88B1A153B23F003037C
+:107AA00004331844844204D9002340F8043B844240
+:107AB000FBD870BC704700BF03694A11934200F1C4
+:107AC000140009DA00EB830302E053F8042DCAB96D
+:107AD0008342FAD80020704711DD11F01F010ED04B
+:107AE00010B450F8224024FA01F303FA01F18C4259
+:107AF00000EB82030CD001205DF8044B704700EBD3
+:107B00008203E5E70120704753F8042D002AF2D1E3
+:107B10008342F9D800205DF8044B704770B50C46DD
+:107B2000084D114600261A46034620462E601C4684
+:107B3000E9F798FF431C00D070BD2B68002BFBD0E9
+:107B4000236070BD00E60020F0B40D785E2D044681
+:107B500021D00022481C1646631E04F1FF0103F8E1
+:107B6000012F8B42FBD19DB186F00102E7436255A4
+:107B7000411C11F8013C2D2B01F1FF3608460FD0B6
+:107B80005D2B03D00BB11D46F1E73046F0BC7047CA
+:107B90000138F0BC704701224D781646881CDBE79F
+:107BA0000E785D2EEFD0B542EDDC05F1010C04EB53
+:107BB0000C0303F8012BF8188642FADCEB4333443C
+:107BC000B542A8BF0023023103EB0C05D1E700BF8B
+:107BD000004870470000C07F2DE9F0410D469046F7
+:107BE000FFF716FE06460F46B8F1000F11D0C5F399
+:107BF0000A53C3F16B03002B0BDD1B0503F17F550B
+:107C0000002405F5401522462B4604F0D7FE064613
+:107C10000F4630463946BDE8F08100BF2DE9F04FF0
+:107C2000B34C2DED028B2468A3B08046002520467E
+:107C30008A46089407921C461E95FAF781F900219E
+:107C400083460020CDE90401CDF874A052461746C2
+:107C500012F8013B2D2B2FD8DFE813F0A0002E00E7
+:107C60002E002E002E002E002E002E002E00B00022
+:107C7000B000B000B000B0002E002E002E002E008C
+:107C80002E002E002E002E002E002E002E002E0084
+:107C90002E002E002E002E002E002E00B0002E00F2
+:107CA0002E002E002E002E002E002E002E002E0064
+:107CB0002E0008042E00FE0300220C92302B7FD0F1
+:107CC000002209922F2B1C4640F30A854FF0000931
+:107CD0004E464D46384612E00130082D1D90C8BF73
+:107CE00009EB89090478C6BF03EB4903A3F1300906
+:107CF000A2F130062F2C05F10105234678DD06EBB5
+:107D00008602392C03EB4202E6DD08995A46FAF75F
+:107D100085F90346002864D11D9A11465A441D92E4
+:107D200011F80B40002D40F0E485302C40F0C88560
+:107D3000C2F10101531801321D921478302CF9D090
+:107D4000A4F13102082A00F23B831D9F03F1010BCD
+:107D50000023A4F1300E08933C46012506EB86066D
+:107D60000EEB46060023621C1D926478A4F13001DC
+:107D7000092906D801338E46002940F087841D9CCE
+:107D8000F1E70122652C0D9200F08780452C3DD152
+:107D9000002D40F08280099A1A437DD1079B13B1D0
+:107DA000079BC3F800A04FF0000A4FF0000B5046AD
+:107DB000594623B0BDEC028BBDE8F08F1D9246E71B
+:107DC0007B7803F0DF03582B00F0418401371D97C7
+:107DD0003B78302BFAD0002B00F0D380012209929F
+:107DE00070E70023652C9B460D930895D0D0CDE716
+:107DF00008995A46FAF712F90346002800F0D7808E
+:107E000008954FF0000BCDF834B05B4600220A9283
+:107E1000002D00F09280304604F056FD089C234669
+:107E2000002C08BF2B4608930A9B102DA3EB0B03D5
+:107E30002C46A8BF1024092DCDE904010D9314DDB3
+:107E40002C4B03EBC40353E9122304F0B7FD0246A5
+:107E500048468A46914604F037FD02460B4648469E
+:107E6000514604F0F5FBCDE904010F2D00F3A88085
+:107E70000D9B002B00F0E8830D9B40F33883162BFD
+:107E800040F321850D9AC5F12503934280F23A858E
+:107E90000D9B2C1B1C4499E00025DDF874A00AF111
+:107EA00001021D929AF801402B2C00F086822D2CA5
+:107EB00000F01F824FF0000EA4F13002092A00F2F8
+:107EC0001382302C05D11D9A01321D921478302C6A
+:107ED000FAD0A4F13102082A98D81D990A914A1CB7
+:107EE0001D92A4F130004C782F2C0DDC00F007BC63
+:107EF00040240208E820020801321D929CF801404B
+:107F00002F2CA1F1300006DD00EB8001392C9446C6
+:107F100004EB4101F0DD0A99521A082A40F3EF837D
+:107F200044F61F620A92BEF1000F3FF471AF0A9A45
+:107F300052420A92002D7FF46EAF099A134320D16A
+:107F40000D9B002B7FF42AAF692C00F0428400F3D4
+:107F5000E682492C00F03D844E2C7FF41FAFB249DD
+:107F60001DA804F06BF900283FF418AF1D9B1B7887
+:107F7000282B00F07385AD4804F04AFA82468B4600
+:107F800003E04FF0000A4FF0000B079A0AB11D9B67
+:107F900013600C9B002B3FF40AAF0BF100439B4690
+:107FA0005046594623B0BDEC028BBDE8F08F1D9AB8
+:107FB000089502EB0B011D9112F80B409B46D5E68C
+:107FC0000D9B2C1B1C44002C40F3CE8214F00F039D
+:107FD0000AD0974901EBC301D1E90001DDE904238F
+:107FE00004F0ECFCCDE9040134F00F0340F06882AA
+:107FF00000230993089A00962B4639464046FFF71E
+:1080000015F91390002800F0FE830A9BABEB0300E8
+:108010000D9B0026002BB4BF0246324623EAE373D1
+:108020000E921293B1460896139C40466168FFF782
+:1080300077F88346002800F0388122699DED047BA3
+:108040000232920004F10C010C308DED0A7BF8F73E
+:108050003FFF20A81FA9CDE90010DDE90A23404613
+:10806000FFF75CFC1E90002800F00E8101214046C5
+:10807000FFF786F98146002800F017811F9B002B2F
+:10808000C0F206810E9A129D9E180999209C694A99
+:108090005B1A2344013B9342C4F1360480F2A3806F
+:1080A000D21A1F2AA4EB020400F317810123934084
+:1080B00010930027099B25443444A6421D443346AF
+:1080C000A8BF2346AB42A8BF2B46002B02DDE41A13
+:1080D000ED1AF61A0E9B002B00F3B680002C00F36D
+:1080E000CA800D9B002B00F3D780002D00F3EB809E
+:1080F000002E08DD494632464046FFF753FA8146D6
+:10810000002800F0D2801E995A464046FFF7DCFA5C
+:108110000890002800F0F183089A0023D1680F919D
+:10812000D3604946FFF7B2FA0028C0F2708400F02D
+:10813000008408984946FFF751FC00224FF0804325
+:1081400006460F4604F0B6FE002850D00F9B002BC9
+:1081500000F0DC809FED307B8DED107B364F059C71
+:108160000026364D364B25409D4200F0F480099B99
+:108170007BB1B5F1D46F0CD829A3D3E90023DDE995
+:10818000100104F097FE002840F0848107F1D663C7
+:108190005F1BDDE90A01FFF73BFB02460B46304659
+:1081A000394604F00BFCDDE90A2304F051FA0346DA
+:1081B0000C46CDE90434099B23B9204B23409D4252
+:1081C00000F007811E994046FEF7D0FF5946404611
+:1081D000FEF7CCFF49464046FEF7C8FF08994046E7
+:1081E000FEF7C4FF20E701230027109362E7154B39
+:1081F00030463946002204F0E1FB0F9BCDE9100127
+:10820000002B7ED101F1004314901593DDE9146732
+:10821000059CA6E7AFF30080000000000000F03FDF
+:108220000000C0FFFFFFDF410C220208D02202083D
+:10823000E820020802FCFFFF0000F03F0000F07F92
+:108240000000E07F0000E03F49461A464046FFF745
+:108250005DF9814648B301461E9A4046FFF7A6F8ED
+:1082600018B30F901E994046FEF780FF0F9B1E9398
+:10827000002C7FF736AF1E9922464046FFF792F951
+:108280001E9000287FF42DAF4F46089ED94610E07F
+:10829000129A0E9ED51AF8E65946129A4046FFF7F2
+:1082A00035F9834600287FF420AF089E4F46D94613
+:1082B0001E98A54B0593002222230492DDE904AB0E
+:1082C000C8F80030B3E059462A464046FFF76AF93D
+:1082D000834600287FF40CAFE7E79C4FFF1A012389
+:1082E00003FA07F71093E5E60022CDF874A00A928E
+:1082F0008EE54FF0010E0AF102021D929AF802403B
+:10830000DAE59DED107B8DED147B7FE7DDE904124E
+:10831000002940F0AE80C2F313031446002B40F056
+:10832000AE808B4B00223046394604F0B9FD002860
+:1083300040F0D682874B00223046394604F03EFB9F
+:108340000A460146CDE9101202F100431A901B9330
+:10835000DDE91A6705E7A4F1547305939DED047BED
+:1083600051EC170BB0EE478AF0EE678AFFF750FA30
+:1083700002460B463046394604F020FB53EC182BDE
+:1083800004F066F9704B744A0B40CDE904010C46C9
+:10839000DDE90A01934206460F46CDE9186775D913
+:1083A0006E4B994203D1B0F1FF3F3FF47EAF6B4972
+:1083B0004FF0FF33CDE9043104E74FF0000E9AE7A8
+:1083C000652C00F0A680452C00F0A38001220D92C0
+:1083D000B3E5DDE910562846314604F04FFE04F0BF
+:1083E000BFFA0B4602463146284604F02FF9049D99
+:1083F0000F9EC4F313072E4356EA070304460D46A7
+:108400006CD049A3D3E9002304F04AFD48B948A33E
+:10841000D3E900232046294604F060FD00283FF4FC
+:10842000D1AE4F46D946DDE904AB089E1E98014601
+:108430004046FEF79BFE49464046FEF797FE39460A
+:108440004046FEF793FE13994046FEF78FFE3146F5
+:108450004046FEF78BFE98E501230C937A1C1D9293
+:108460007B78002B3FF49AAC174627E400230C934B
+:10847000F4E7DDE90412012900F0488114469FED7C
+:108480002E7B374F8DED107B00266AE604F1547485
+:10849000059490E6DDE9100104F068FD012838BF7D
+:1084A000012004F011FA0F9BCDE91001002B40F0E0
+:1084B0003F8101F1004316901793DDE9166765E6E9
+:1084C000B3F59A7F40F339811F4B05930022222395
+:1084D0000492DDE904ABC8F8003056E518A3D3E9EF
+:1084E000002304F0DDFC00283FF46CAE99E716335E
+:1084F000FFF666AD0A9A1B4BABEB020003EBC00321
+:10850000D3E90023DDE9040104F082FB82468B46B7
+:108510003BE500220892934601220D923BE46E2C2B
+:108520003FF41DAD3AE400BF9535A094FFFFDF3F57
+:1085300035E5AF350000E03F000000000000F03FEF
+:108540009535A094FFFFCF3F0000F07FE2FBFFFFD7
+:108550000000F03F0000E03FFFFF9F7CFFFFEF7F48
+:108560000000F0BFE82002083FF442AD644214F07E
+:108570000F020AD0BE4B03EBC203DDE90401D3E9CD
+:10858000002304F045FBCDE9040124113FF430AD94
+:108590001F2C40DC14F010031946DDE9042318BF3A
+:1085A0006A21DFF8EC9209914FF0000C14F0010FF2
+:1085B0001046194607D0D9E9002304F0FFF94FF01F
+:1085C000010C02460B46641009F10809EED1BCF11A
+:1085D000000F01D0CDE90423099B9BB1DDE9041212
+:1085E000C2F30A53C3F16B03002B11460ADD1F2BA4
+:1085F00040F383820022342B049240F389824FF0AF
+:108600005C730593DDE904010022002304F03EFCC5
+:1086100000283FF4EFAC2223C8F800304FF0000AE6
+:108620004FF0000BB1E4DDE920131F9A049102F230
+:10863000334223F4801343EA02530593240742BFD5
+:10864000059B43F000430593DDE904AB9DE40C9AE0
+:1086500002941EABCDE900321DA9864A1FAB4046ED
+:1086600003F034FB10F0070504463FF48AAC062DF6
+:1086700040F0D480079B0137002B3FF494AB1F6080
+:108680004FF0000A4FF0000BFFF791BB012B1D9C30
+:108690009B4405F1010200F052822B4403F1FF3CA0
+:1086A00003E04600944515460CD0082D05F1010263
+:1086B00006EB8600F5DD102ADCBF09EB89094FEADD
+:1086C0004909EFE71D46BCF1080F7FF747AB102DB6
+:1086D000DCBF09EB890901EB49090023FFF743BB24
+:1086E00008995A463846F9F799FC002800F0DE80D0
+:1086F00000231D46089399461E46FFF782BB44F6A9
+:108700001F629042A8BF10460A900CE4DDE90423E2
+:108710001C46002B7FF4B3AE089E4F46D946222359
+:108720001E98C8F800304FF0000A4FF0000B7EE6AC
+:108730009DED107B8DED167BBFE6102B4FEA2314C9
+:108740004D4B40F3A58119460993DDE904234FF011
+:10875000000C8A46E14614F0010F104619464FEA14
+:10876000640409F1010907D0DAE9002304F026F9CD
+:108770004FF0010C02460B46012C0AF1080AEAD11F
+:10878000BCF1000F01D0CDE90423059B3B4CA3F1C4
+:1087900054730593099B03EBC909D9E90001DDE98D
+:1087A000042304F00BF9DFF8ECC001EA040363458D
+:1087B000CDE904010A4600F2068131498B4240F2BC
+:1087C000FB80304B0593002309934FF0FF33049354
+:1087D00010E42D491DA803F031FD00283FF4DEAA66
+:1087E0001D9B2A49013B1DA81D9303F027FD10B9CD
+:1087F0001D9B01331D9321480023CDE90430DDE9A1
+:1088000004ABFFF7C2BB1D4B0593139B04932223BC
+:10881000DDE904ABC8F80030FFF7B7BB1E9A3AB1E8
+:10882000352120A8FFF724F91E994046FEF79EFC4B
+:10883000013D052D3FF602AF01A353F825F000BF1F
+:1088400027860108A3880108998801086188010822
+:1088500027860108598801080023CDE90433EDE695
+:108860004FF0FF336FF00045CDE90435E6E600BF79
+:10887000E820020810220208D82102080000F07F38
+:108880000000907CFFFFEF7F002202080422020814
+:10889000382202080000A07CAF4E0023CDE9043648
+:1088A000CCE6209B0493219B0593C7E61D9A1346B3
+:1088B0005A441D9213F80B4006468146FFF735BA1D
+:1088C0000023FFF73DBAA54901EBC301D1E900013F
+:1088D000DDE9042304F072F882468B46FFF755BBAE
+:1088E0009FED997B8DED1A7B9FED997B8DED107B34
+:1088F0002EE508958346FFF739BA4F460646D94616
+:108900001E98D6E4954CC5F10F0504EBC501DDE9D1
+:108910000423D1E9000104F051F80D9B5D1B04EB29
+:10892000C504D4E9002304F049F882468B46FFF7DA
+:108930002CBB0F9B089EBC464F46D946DDE90AABCF
+:10894000002B4AD0DDE90445854BC5F3130199425C
+:108950002A4600F0B3806346002B00F09380059A0E
+:108960001CEA020F10D00F9B099ADDE90401002BCD
+:1089700000F09280FFF730F902460B465046594608
+:1089800003F066FE82468B46099B9BB1754A002325
+:10899000CDE918325046DDE91823594604F00EF8A7
+:1089A00003460B4382468B4604D122231E98C8F807
+:1089B00000303CE51E983AE502F15473059300231C
+:1089C0000993FFF717BB0023049305942223DDE9E5
+:1089D00004ABC8F80030FFF7D8BADDE90412C2F3DF
+:1089E00013030B431446B6D1099B002B40F098802B
+:1089F000594B2340A3F580136FEA13536FEA0353D7
+:108A000005934FF0FF330493DDE904ABBCE7DDE9E8
+:108A100004010F9B089E03434F46D946DDE90AAB8C
+:108A2000B2D1C1F313030C46002BADD121F00043AA
+:108A30001B0D1B05B3F1D66FA6D9736913B9336942
+:108A4000012BA1DD314601224046FEF7ABFD394640
+:108A50000646FEF71BFE002896DDC5E742491DA825
+:108A600020AA03F003FC05287FF485AA219B43F08C
+:108A7000FF4343F4E0030593209B0493DDE904AB3B
+:108A8000FFF783BA109B049A13423FF47DAF6AE765
+:108A900009934FF0000978E6FFF79EF802460B466F
+:108AA0005046594603F0D2FD0022002382468B46F1
+:108AB00004F0ECF900283FF467AF30E6099B049915
+:108AC0001BB3254B2B40B3F1D46F1ED81B0DC3F144
+:108AD0006B034FF0FF3000FA03F399427FF43BAF92
+:108AE000224B9A4227D01C4B134003F58013059369
+:108AF00000230493DDE904AB46E74FF0FF3202FAAE
+:108B000003F3049A1A4004927CE54FF0FF33E4E744
+:108B1000203B4FF0FF3202FA03F30B40059371E55F
+:108B20000D4B2340B3F1D66F3FF764AFB3F15C7FD9
+:108B30003FF72CAFF3E50131D5D1FFF7B9BBAC4618
+:108B40001546C0E5AFF30080000000000000E0BF64
+:108B5000000000000000E03F0000F07FE820020875
+:108B6000FFFF0F000000503924220208FFFFEF7FB3
+:108B7000014BFFF753B800BF080D002030B4044C80
+:108B80000D46134601462A46206830BCFFF746B81A
+:108B9000C804002010B4044C044B0A460146206867
+:108BA0005DF8044BFFF73AB8C8040020080D002018
+:108BB0002DE9F041DFF8A4800C4613462DED028B21
+:108BC00022460146D8F80000FFF728F802460B4677
+:108BD00004460D4604F08CF950BB2046294604F0AB
+:108BE000E5F908EE100ADFED1A7AB0EEC87AB4EEB5
+:108BF000677AF1EE10FA15DD25F00047154B204697
+:108C000039464FF0FF3204F073F938B9114B204662
+:108C100039464FF0FF3204F04DF918B1D8F8003062
+:108C200022221A6018EE100ABDEC028BBDE8F0811A
+:108C3000002D094806DAFEF7CBFF07EE900AB1EEE9
+:108C4000678AEFE7BDEC028BBDE8F041FEF7C0BFDD
+:108C5000FFFF7F7FFFFFEF7FD0220208C8040020C4
+:108C60002DE9F041DFF8A880254B0A462DED028B57
+:108C70000146D8F80000FEF7D1FF02460B46044635
+:108C80000D4604F035F950BB2046294604F08EF914
+:108C900008EE100ADFED1B7AB0EEC87AB4EE677A00
+:108CA000F1EE10FA15DD25F00047174B2046394646
+:108CB0004FF0FF3204F01CF938B9134B2046394607
+:108CC0004FF0FF3204F0F6F818B1D8F80030222245
+:108CD0001A6018EE100ABDEC028BBDE8F081002D81
+:108CE0000A4806DAFEF774FF07EE900AB1EE678ACB
+:108CF000EFE7BDEC028BBDE8F041FEF769BF00BFB6
+:108D0000080D0020FFFF7F7FFFFFEF7FD0220208CA
+:108D1000C8040020012B2DE9F84F3AD0242B9846A7
+:108D200037D8464F0D46AC4615F8014B3E5D16F060
+:108D30000806F8D12D2C69D02B2C0ABF95F800B06D
+:108D4000A3460CF102056FF00049002B40D0102B18
+:108D500051D0B9FBF8FE0027BC4608FB1E9A07E07D
+:108D6000E64513D32FD008FB0C4C012715F801BBA7
+:108D7000ABF13004092C05D9ABF14104192C0FD803
+:108D8000ABF13704A34213DD002FE9DA4FF0FF37D0
+:108D9000ECE7F6F76FFD162303600020BDE8F88FBF
+:108DA000ABF16104192C03D8ABF15704A342EBDCFF
+:108DB000002F25DB0EB1CCF1000C0AB18FBB116086
+:108DC0006046BDE8F88FA245CDDA4FF0FF37CDE71A
+:108DD000BBF1300F03D04FF00A084346B9E72B78B8
+:108DE00003F0DF03582B1ED14FF0100895F801B0A7
+:108DF00043460235ADE7BBF1300F18D09846A8E7DF
+:108E00002223036052B1691ECC46D8E795F800B022
+:108E10004FF000490CF10205012696E7CC4660466A
+:108E2000CFE7E146EFE74FF00808434691E72C789B
+:108E300004F0DF04582CD7D098468AE7351F020883
+:108E400068E700BF30B4044C0D46134601462A467D
+:108E5000206830BC5EE700BFC804002030B4044C7A
+:108E60000D46134601462A46206830BC52E700BF33
+:108E7000C80400202DE9F04F87B00F465B490590EC
+:108E800001921E463D462A4615F8014B0B5D13F034
+:108E90000803F8D12D2C78D02B2C3DD004934FF023
+:108EA000FF3E6FF00043CDE902E3002E3FD0102ECD
+:108EB00075D0B0464FEAE679DDE9020142464B46FD
+:108EC00004F0C4F8002382468B469446002000211B
+:108ED0000DE04CD000FB09F308FB0133A0FB0801B7
+:108EE0001944801841EBE271012315F8014BA4F1FC
+:108EF0003002092A05D9A4F14102192A1FD8A4F188
+:108F00003702964223DD5C1CEFD08B4508BF8245BB
+:108F1000DFD24FF0FF33E8E704934FF0FF3C6FF0F0
+:108F200000432C78CDE902C3951C002EBFD1302C14
+:108F300049D04FF00A084FF000090A26BCE7A4F117
+:108F40006102192A03D8A4F157029642DBDC5A1CAD
+:108F500012D0049A12B1404261EB4101019A1AB158
+:108F6000002B40D1019B1F6007B0BDE8F08F9445F6
+:108F7000B0DA4FF0FF33B8E7059A22231360019B64
+:108F800063B3DDE902016F1EECE7002302934FF0AB
+:108F9000004801232C78CDE90383951C85E7302C0C
+:108FA00004D12B7803F0DF03582B04D04FF01008C6
+:108FB0004FF0000980E76C784FF010084FF000097F
+:108FC0000235102678E72B7803F0DF03582BF2D018
+:108FD0004FF008084FF0000908266DE7DDE90201AF
+:108FE00007B0BDE8F08FCDE90201CAE7351F0208DE
+:108FF00040E700BF30B4044C0D46134601462A46F4
+:10900000206830BC36E700BFC804002030B4044CF0
+:109010000D46134601462A46206830BC2AE700BFA9
+:10902000C80400202DE9F0474B4D86468C4660462B
+:109030001CF8014B2E5D16F00806F8D12D2C57D0E8
+:109040002B2C0ABF9CF80050254600F1020C5BB1A6
+:10905000102B53D04FF0FF38B8FBF3F803FB08FA9E
+:109060006FEA0A0A994607E0302D5BD00A23DFF841
+:10907000EC8099464FF0050A0027384607E0404546
+:1090800013D826D009FB004001271CF8015BA5F18D
+:109090003004092C05D9A5F14104192C08D8A5F1F3
+:1090A0003704A3420CDD002FE9DA4FF0FF37ECE77D
+:1090B000A5F16104192C03D8A5F15704A342F2DCF1
+:1090C000002F0BDB06B140420AB177B91160BDE851
+:1090D000F0875445D6DD4FF0FF37D6E72223CEF890
+:1090E00000304FF0FF30002AF1D00CF1FF31EDE7F6
+:1090F0009CF80050012600F1020CA8E7302D24D185
+:109100009CF8000000F0DF00582818D14FF010093B
+:109110009CF801504B464FF00F0A0CF1020C6FF017
+:109120007048A9E79CF8003003F0DF03582BEDD01E
+:10913000082399464FF0070A6FF060489CE799466C
+:109140006FF070484FF00F0A96E74FF00F0A6FF07C
+:109150007048994690E700BF351F02089999991900
+:1091600060E700BF30B4044C0D46134601462A4662
+:10917000206830BC56E700BFC804002030B4044C5F
+:109180000D46134601462A46206830BC4AE700BF18
+:10919000C80400202DE9F04F85B08B466949039043
+:1091A00001929A465D462A4615F8014B0B5D13F075
+:1091B0000803F8D12D2C00F08A802B2C09BF2C78C5
+:1091C00002930293951CBAF1000F1AD0BAF1100F56
+:1091D00000F08280D0464FEAEA7942464B464FF093
+:1091E000FF304FF0FF3103F031FF42468C46064618
+:1091F0004B464FF0FF304FF0FF31674603F026FF3C
+:109200000BE0302C7DD0504F05224FF099364FF0B7
+:109210000A084FF000094FF00A0A4FF0000C002036
+:10922000002115E08F4208BF864220D3B94208BF13
+:10923000B0423AD000FB09F408FB0144A0FB08014E
+:109240002144C01841EBE3714FF0010C15F8014BBC
+:10925000A4F13003092B05D9A4F14103192B09D836
+:10926000A4F137039A450DDDBCF1000FDADA4FF0B7
+:10927000FF3CEBE7A4F16103192B03D8A4F15703DA
+:109280009A45F1DCBCF1000F14DB029B13B14042A4
+:1092900061EB4101019B2BB1BCF1000F14D1019B8B
+:1092A000C3F800B005B0BDE8F08F9342C2DD4FF0C7
+:1092B000FF3CCBE7039A22231360019B4FF0FF3062
+:1092C0004FF0FF31002BEDD005F1FF3BE7E7012325
+:1092D0002C780293951C76E7302C28D12B7803F05C
+:1092E000DF03582B1ED16C780F2202354FF0FF366A
+:1092F0006FF070474FF010084FF000094FF0100A60
+:109300008BE72B7803F0DF03582BECD007224FF0CC
+:10931000FF366FF060474FF008084FF000094FF03C
+:10932000080A7AE74FF010084FF0000955E70F22BE
+:109330004FF0FF366FF070474FF010084FF0000904
+:109340006BE700BF351F02089999991922E700BF02
+:1093500030B4044C0D46134601462A46206830BC02
+:1093600018E700BFC804002030B4044C0D46134673
+:1093700001462A46206830BC0CE700BFC804002024
+:109380002DE9F04F936883B09146002B6ED017689B
+:109390008D6880460C460868083744E0A38913F4BA
+:1093A000906F2ED0D4E9041505EB4505A0EB010A1A
+:1093B00005EBD5750AEB06006D100130A8422A4670
+:1093C00084BF05462A465B0537D511464046E8F777
+:1093D000CDF900283BD0524621690190F7F778FD7E
+:1093E000A289019B22F4906242F08002A281A5EB47
+:1093F0000A0203EB0A00656123612060A260354622
+:10940000B24659465246F7F7FDFDA068D9F8081054
+:109410002368451B8E1B03EB0A00A5602060C9F87A
+:1094200008601EB3083757E902B6002EFAD0B542DD
+:10943000AA46B3D93546B246E3E74046E8F798F97D
+:1094400003460028D3D121694046E8F793F90C235D
+:10945000C8F80030A389002243F040034FF0FF30EA
+:10946000A381C9E9012203B0BDE8F08F0020C9F84B
+:10947000040003B0BDE8F08F2DE9F04F2DED028B15
+:109480008A468989A9B00D0608EE100A934604930E
+:1094900004D5DAF81030002B00F094840023CDE9D5
+:1094A0000C330793019318AB0B9398469BF800304D
+:1094B000002B00F029815C4604E014F8013F002BEA
+:1094C00000F04C81252BF8D1B4EB0B0540F049811D
+:1094D0002378002B00F018814FF0000300218DF855
+:1094E00027306378039108460F4604F1010B4FF0D3
+:1094F000FF390BF1010BA3F12002582A00F24F8132
+:10950000DFE812F08C024D014D0187024D014D0143
+:109510004D014D014D014D017C0277024D012701A6
+:109520005E024D0159025900590059005900590075
+:1095300059005900590059004D014D014D014D018F
+:109540004D014D014D014D014D014D0142024D01B5
+:109550004D014D014D014D014D014D014D014D019B
+:109560004D0115014D014D014D014D014D016800A9
+:109570004D014D01FA014D014D014D014D014D01CE
+:109580004D014D014D014D014D01EC0178014D01A1
+:109590004D014D013D0278014D014D0130024D015B
+:1095A0001D0217010E02E7014D01C7014D016A00BE
+:1095B0004D014D01A901A3F1300200241BF8013B2C
+:1095C00004EB840402EB4404A3F13002092AF5D928
+:1095D000039490E747F01007BE0640F10081049B1A
+:1095E000073323F00703F3E80245049301234FF008
+:1095F00000028DF8272000220592B9F1FF3F00F00C
+:10960000278227F08002009254EA050240F01F8270
+:10961000B9F1000F40F0FA83002B40F0128117F0EF
+:109620000103029300F00F8130238DF85F300DF1BC
+:109630005F06029B4B45B8BF4B461D46059B03B1D9
+:109640000135009B13F002030593009B18BF023500
+:1096500013F08403069304D1039B5C1B002C00F3DE
+:10966000C382DDE90C219DF8270068B10132013188
+:109670000DF127040120072ACDE90C21C8E900409B
+:1096800000F3EA8208F10808059B63B10132023158
+:109690000AA80223072ACDE90C21C8E9000300F338
+:1096A000E98208F10808069B802B00F00782029BE4
+:1096B000A9EB0307002F00F33F82029B01321944FC
+:1096C000072ACDE90C21C8E9006300F3768208F18E
+:1096D0000808009B5B0704D5039B5C1B002C00F370
+:1096E000D782019B039AAA42ACBF9B185B190193D6
+:1096F000002940F06F8200230C939BF800300DF19D
+:109700006008002B7FF4D7AE0D9B002B40F09C83AC
+:10971000BAF80C3013F0400F019B18BF4FF0FF3325
+:109720000193019829B0BDEC028BBDE8F08F47F0A2
+:10973000100717F0200344D0049B073323F00703DE
+:10974000F3E802450493002351E7039A5242CDE91E
+:1097500003239BF8003047F00407CAE6B4EB0B057F
+:10976000D2D0DDE90C3201332A44072BCDE90C328B
+:10977000C8F800B0C8F8045006DC08F10808019ADF
+:1097800023782A440192A4E618EE100A0BAA514647
+:10979000FFF7F6FD0028BBD10DF16008EFE70029C7
+:1097A00040F04F83002BAFD001258DF838304FF0BB
+:1097B00000038DF8273002950EAE00974FF0000998
+:1097C0003FE717F0100240D117F040033DD0049955
+:1097D00051F8044B04911346A4B2002507E7049AFC
+:1097E000FD0652F8044B04924FF0010340F1D98278
+:1097F0000025FCE6002940F03B83BC06049B40F1B9
+:10980000CC80073323F007031946F1E802230491C3
+:1098100014461D46002A73F10003C0F28082B9F19C
+:10982000FF3F00F003819DF82730059354EA0503BC
+:1098300027F0800740F0FD80B9F1000F40F0FE8076
+:109840000097CDF8089018AEF3E6049A52F8044B4E
+:1098500004920025CBE6002940F00D83BD4A079213
+:10986000B906049A50D5073222F00702F2E8024501
+:109870000492F8070BD554EA050208D030228DF87F
+:10988000293047F002078DF828200223AFE6022393
+:10989000ADE6049C54F8046B4FF000038DF82730BC
+:1098A000002E00F0C682B9F1FF3F00F07F824A46E9
+:1098B00000213046F7F7BCFA002800F0CC82831B69
+:1098C00002939DF827300494009705934FF0000908
+:1098D000AFE69BF8003047F020070AE6049B01251D
+:1098E00053F8042B8DF838204FF000018DF8271025
+:1098F000049302950EAE60E7002940F0BF82964ABD
+:109900000792B906049AAED452F8044B0492FE06AC
+:1099100000F1FA817D0640F1F781A4B20025A8E7A5
+:10992000049B53F8044B049347F63002894B07938A
+:10993000ADF8282047F002070025022357E600294A
+:1099400040F09F82BA0600F12082FB0600F14882B7
+:109950007F0640F14582049B019953F8042B049340
+:109960001180A3E59BF800306C2B03BF9BF80130FE
+:1099700047F020070BF1010B47F01007B9E59BF802
+:10998000003047F04007B4E5002940F06E8247F010
+:109990001007BC06049B3FF534AFF80653F8044BA0
+:1099A00000F1B481790640F1B18124B2E517049346
+:1099B00022462B462EE79BF8003047F0800798E5BB
+:1099C0005C4614F8013B2A2B00F05E82A3F13002C2
+:1099D000092AA3464FF000093FF68DAD1BF8013B65
+:1099E00009EB890902EB4909A3F13002092AF5D9EB
+:1099F00081E59BF8003001212B207AE5049B53F888
+:109A0000042B0392002AFFF6A0AE04939BF80030CB
+:109A10006FE59BF8003047F001076AE59BF80030DE
+:109A200000287FF466AD0121202062E59DF82730F3
+:109A30000593002D08BF0A2C80F08A813034012361
+:109A40008DF85F40009702930DF15F06F1E5009FEE
+:109A5000012BEED0022B18AE13D10798230904F086
+:109A60000F0143EA05732A091C461546435C06F8B4
+:109A7000013D54EA0503F1D118AB9B1B00970293FB
+:109A8000D7E5E20842EA4572E90804F007030D460B
+:109A90001446303354EA0501324606F8013DF0D150
+:109AA000F907E9D5302BE7D03023023A06F8013C1C
+:109AB00018AB9B1A009702931646BAE5039B5F1BEF
+:109AC000002F7FF7F4AD102F244C24DD40461023E7
+:109AD000A84618EE105A04E0103F102F00F10800BD
+:109AE00017DD01321031072ACDE90C21C0E900430E
+:109AF000F2DD0BAA51462846FFF742FC00287FF40E
+:109B000007AE103F102FDDE90C2118A84FF010030D
+:109B1000E7DC4546804601323944072ACDE90C216D
+:109B2000C8E9004700F37781029BA9EB0307002FE8
+:109B300008F108087FF7C1AD102F084C31DD0595FD
+:109B40004FF0100955460B46B246264618EE104A0D
+:109B50000BE000BFA81E0208941E02087022020833
+:109B6000103F102F08F1080816DD01321033072AC4
+:109B7000CDE90C23C8E90069F2DD0BAA294620468D
+:109B8000FFF7FEFB002840F0E180103F102FDDE9D9
+:109B90000C230DF16008E8DC34465646AA46059DC4
+:109BA000194601323944072ACDE90C21C8E900479A
+:109BB00000F3BE8008F108087FE518EE100A0BAA32
+:109BC0005146FFF7DDFB00287FF4A2AD0D990DF1A2
+:109BD00060087EE518EE100A0BAA5146FFF7D0FB8D
+:109BE00000283FF488AD93E5102CDDE90C21B04F3F
+:109BF00024DD40461023A84618EE105A04E0103C1D
+:109C0000102C00F1080017DD01321031072ACDE9D0
+:109C10000C21C0E90073F2DD0BAA51462846FFF77C
+:109C2000AFFB00287FF474AD103C102CDDE90C2153
+:109C300018A84FF01003E7DC454680460132214466
+:109C4000072ACDE90C21C8F80070C8F8044000F3D9
+:109C5000CF8008F1080806E518EE100A0BAA514655
+:109C6000FFF78EFB00287FF453ADDDE90C210DF1E9
+:109C7000600809E518EE100A0BAA5146FFF780FBB1
+:109C800000287FF445ADDDE90C210DF160080AE5FF
+:109C9000102C0C9B864F21DD18EE109A10260A46D8
+:109CA00004E0103C102C08F1080816DD01331032D6
+:109CB000072BCDE90C32C8E90076F2DD0BAA51463C
+:109CC0004846FFF75DFB00287FF422AD103C102CC6
+:109CD000DDE90C320DF16008E8DC11460133214466
+:109CE000072BCDE90C31C8F80070C8F804407FF7A5
+:109CF000F8AC18EE100A0BAA5146FFF741FB0028FA
+:109D00007FF406AD0D99ECE40025B2E5E517224697
+:109D10000493002A2B4673F10003BFF680AD2D2378
+:109D200064428DF82730059365EB4505012364E413
+:109D300018EE100A0BAA5146FFF722FB00287FF409
+:109D4000E7ACDDE90C210DF16008B6E4AA46DFE4DA
+:109D500018AE204629460A22002303F077F9303254
+:109D600006F8012D00230A222046294603F06EF949
+:109D70002B462246002B08BF0A2A04460D46E8D28D
+:109D800018AB9B1B0097029353E4049B53F8041BEE
+:109D90000493019BDD171A462B46C1E90023FFF708
+:109DA00085BB780648BFA4B2002520E43046F8F70A
+:109DB000C7F89DF8273004940097029005934FF060
+:109DC000000936E44021E7F7D1FCCAF80000CAF8E0
+:109DD0001000002863D04023CAF81430FFF75EBBA0
+:109DE000049B019953F8042B11600493FFF75EBBA9
+:109DF00018EE100A0BAA5146FFF7C2FA00287FF4AA
+:109E000087ACDDE90C210DF160082CE4012B009FEB
+:109E10007FF420AE12E618EE100A0BAA5146FFF7A7
+:109E2000AFFA00287FF474ACDDE90C210DF1600875
+:109E30003DE44D46062D28BF06251E4E029504948E
+:109E4000BBE48DF82700ADE418EE100A0BAA5146CA
+:109E5000FFF796FA5CE49DF82730CDF8089005935B
+:109E6000049400978146FFF7E4BB8DF827008EE548
+:109E70008DF82700C1E48DF82700EFE48DF8270066
+:109E80003DE58DF827005DE5049D9BF8013055F810
+:109E9000042B0495A34642EAE279FFF72ABB18EEA9
+:109EA000102A0C2313604FF0FF33019339E400BFF5
+:109EB00060220208BC1E020838B54B1C1AD09389D8
+:109EC0001446126B23F02003CDB2A381AAB16268BD
+:109ED000636B9A4209DA23685A1E226003F8015C18
+:109EE000636801336360284638BD214600F08EFE6A
+:109EF0000028F0D04FF0FF35F5E7226923682AB13A
+:109F00009A4203D213F8012CAA420FD0A36323462E
+:109F10006068E06304F140010322C4E90C1203F815
+:109F2000425F0122C4E90032284638BD6268013B25
+:109F30000132C4E90032D6E710B50C46096B69B1AD
+:109F400004F14003994201D0E7F714FCE36B63602E
+:109F50000020206313B1A36B236010BDA389226985
+:109F6000226043F020030022A38162604FF0FF30A3
+:109F700010BD00BF2DE9F04F83B002FB03FA0C9C2B
+:109F800001929B46BAF1000F25D0074689465646F6
+:109F90004FF000080FE02168F6F79AFF2268C4F836
+:109FA00004802A44226021463846FFF7C5FFA944B1
+:109FB000721BA0B916466568B54248462A46EAD3E0
+:109FC00021683246F6F784FFD4E900539B1B3544E1
+:109FD000C4E90053DA46504603B0BDE8F08F019B58
+:109FE0005544AD1BB5FBF3FA504603B0BDE8F08F06
+:109FF0002DE9F04F2DED028B8A46B1F90C10DDB042
+:10A0000007468804049309D4DAF8643041F4005117
+:10A0100023F40053AAF80C10CAF86430904618F8DC
+:10A02000013B0D93002B00F0A885DFF8E4B43E4619
+:10A0300047461BF80380002218F00808CDE90522E6
+:10A0400003929146029240F09E80252B7BD13A7874
+:10A050004546A2F12503791C532B6DD8DFE813F098
+:10A0600072006C006C006C006C000B026C006C00E9
+:10A070006C006C006C00BE00BE00BE00BE00BE00E6
+:10A08000BE00BE00BE00BE00BE006C006C006C00D6
+:10A090006C006C006C006C006C006C006C00A70124
+:10A0A0006C006C006C006C006C006C006C00FB01C0
+:10A0B0006C006C0091016C006C006C006C006C001A
+:10A0C0006C006C006C00CA006C006C00E6016C0057
+:10A0D0006C006C006C006C006C006C00D801A90175
+:10A0E0006C006C006C00DD0104026C006C00CC01A3
+:10A0F0006C00B0019301EE016C006C00F1016C008A
+:10A10000F4016C006C00CA0051463046FFF714FFA2
+:10A11000002800F02B833B460A9F002B00F032837F
+:10A12000029A002A00F02785BAF80C3013F0400F8D
+:10A1300018BF4FF0FF32029202985DB0BDEC028B67
+:10A14000BDE8F08F0F46DAF80430002B3FDDDAF877
+:10A15000003017F8012C19789142EDD1DAF804207B
+:10A160000133013ACAF8003009F10109CAF80420A4
+:10A1700017F8013B0D93002BDED01BF8038018F07D
+:10A1800008083FF462AFDAF8042012E0DAF8003091
+:10A190001A781BF8022012F0080F03F10103E7D030
+:10A1A000DAF80420CAF80030013A09F10109CAF8C6
+:10A1B0000420002AEADC51463046FFF7BDFE0028A5
+:10A1C000E4D017F8013B0D93002BD6D1B4E75146EC
+:10A1D0003046FFF7B1FE0028B9D0A1E718F08F0F85
+:10A1E000AAD105EB850502EB4502A2F130057A788C
+:10A1F0000F462EE748F40078C34B059310230F4613
+:10A2000003930324DAF80430002B40F3C88018F0DD
+:10A21000400F34D0022C4DD0032C00F07B81012C58
+:10A2200000F03281012D2C4638BF012418F00105C1
+:10A2300040F0C38318F0100F40F08C80DDF81080E0
+:10A24000234658F8041BCDF800A001223046FFF742
+:10A2500091FE00283FF464AF029BCDF810800133DB
+:10A26000029317F8013B0D938144002B85D163E7DE
+:10A2700051463046FFF760FE00287FF451AFDAF810
+:10A28000002013781BF803301907C3D5DAF804301F
+:10A29000013B002B09F10109CAF8043002F1010267
+:10A2A000E6DDCAF8002013781BF803301907EDD457
+:10A2B000022CB1D1002D08BF4FF0FF3518F0010F6F
+:10A2C00040F0FA81DAF8002018F0100F137800F04F
+:10A2D000B0821BF803301C073FF54AAFDAF80430B0
+:10A2E0000132013B012DCAE9002308BF09F1010930
+:10A2F0003FF43EAF01241A4612E0DAF800301A7833
+:10A300001BF80220100703F1010311D4DAF804202E
+:10A31000CAF800300134013AA542CAF8042028D016
+:10A32000002AEADC51463046FFF706FE0028E4D05A
+:10A33000A14417F8013B0D93002B7FF41EAFFBE601
+:10A340001344CAF800301544A41AFFF7F5FD00289D
+:10A3500040F0F383DAF80420DAF8003094425146F2
+:10A360003046EDDC121B2344CAF804202544CAF809
+:10A370000030A94417F8013B0D93002B7FF4FDAE8C
+:10A38000DAE648F00108604B059308230393DAF8F6
+:10A390000430002B0F464FF003043FF738AF51460F
+:10A3A0003046FFF7C9FD00283FF431AFB8E648F06A
+:10A3B0000108564B05930A230F460393032421E714
+:10A3C00018F0100F40F05C8318F0040F40F07D830C
+:10A3D00018F0010F40F0DA8318F0020F00F0D68376
+:10A3E000DDF810804A4658F8040BCDF81080D317DA
+:10A3F000C0E900230F46BBE618F00F0F7FF49CAEB8
+:10A400007A786C2A00F09E8348F001080F4620E617
+:10A4100048F040080F460024F4E618F00F0F7FF4D0
+:10A420008BAE7A7848F004080F4612E61CA8FDF7B8
+:10A430008BFB48F0400807460124E3E648F408781F
+:10A44000DAE60F460224DDE62F4B05930A230F467A
+:10A4500003930324D6E618F00F0F7FF46DAE7A78DD
+:10A4600048F002080F46F4E5284B059300230F46F9
+:10A4700003930324C6E655EA08057FF45DAE7A78B7
+:10A480004FF010080F46E4E5002D08BF4FF0FF35F0
+:10A4900018F0010F40F00E8218F0100FDAF80020CB
+:10A4A00000F07A811CAB19461378CB5C002B3FF48B
+:10A4B00043AEDAF804300132013B012DCAE9002332
+:10A4C0003FF436AF1A46884613E0DAF800301A78BF
+:10A4D00018F802200133002A3FF42AAFDAF80420EA
+:10A4E000CAF800300134013AA542CAF804203FF40A
+:10A4F0001FAF002AE9DC51463046FFF71DFD00285A
+:10A50000E3D0A14415E700BF61910108418E010825
+:10A51000351F02086B1E262B40F2CB80A5F12703C6
+:10A520000893272500235146BA46039F079348F412
+:10A53000586812AC0A681078A0F12B034D2B37D85D
+:10A54000DFE803F07F367F36368B6E6E6E6E6E6E92
+:10A550006E8585363636363636362727272727271F
+:10A56000363636363636363636363636363636368B
+:10A570003674363636363636363627272727272797
+:10A58000363636363636363636363636363636366B
+:10A5900036740A2F0CDD28F4386804F8010B4B6878
+:10A5A000013B002B4B6066DD01320A60013DC1D1E9
+:10A5B00018F4807F039757468A4607D012AB9C4217
+:10A5C00000F2B38212AB9C423FF4B6AD18F0100219
+:10A5D00063D1039B059D227012A93046A84718F04D
+:10A5E000200F50D118F0040F40F0678218F00102DC
+:10A5F00049D118F0020F46D0059B1946B84B994235
+:10A600003046039B12A900F0FA82FEF7F1FCDDF858
+:10A61000108058F8043BCDF81080C3E9000139E000
+:10A62000B04B28F4386833F91770B6E708F4C06304
+:10A63000B3F5007FBCD128F4007848F4A068102757
+:10A64000ABE718F0800FB3D028F08008A5E7A54B42
+:10A6500033F91770082F9EDCAAE718F4006F9CD01E
+:10A6600017B948F40078082718F4806F00F0FA81D1
+:10A6700028F4B06891E730460391FFF75DFC039939
+:10A68000002893D094E7DDF8108058F8043B186058
+:10A69000CDF81080029B0133029312ABE41A079BA2
+:10A6A0002344994417F8013B0D93002B7FF465ADCB
+:10A6B00042E50023089335E718F01003089340F0B3
+:10A6C000DC81DDF8108058F8043B0793CDF810804A
+:10A6D000DAF800301B781BF8033013F0080351D16F
+:10A6E000CDE909571C460DF14808FCF77FFCA04254
+:10A6F0003FF416ADDAE9002312F8011B08F8041044
+:10A70000013BCAE90023069B032B04F1010710ADAE
+:10A7100002D12B68042B04D0082200212846F6F72A
+:10A72000DDFC4246079900953B463046FCF78CFC21
+:10A73000421C06903FF4F4AC002840F00982079ACE
+:10A740001060FCF725FC002840F02B82B944099BDF
+:10A75000013B0993089F002F40F03482079B04338C
+:10A760000793DAF80430002B7FF7CEACDAF800302C
+:10A770001B781BF803301D0703D4099B0BB13C4623
+:10A78000B3E70A9F089B002B7FF4F2AC079A136093
+:10A79000029B01330293EBE4049C13781CA821462E
+:10A7A000C35C51F8044B0491002B3FF4C5ACDAF8BC
+:10A7B0000430511C013BCAE90013A046137808F885
+:10A7C000013B012D26D02544079434462E460546EC
+:10A7D00011E0DAF800100B78EB5C481C33B3DAF8C0
+:10A7E0000430CAF80000013BCAF804300B7808F8BE
+:10A7F000013BB0451AD0DAF80430002BE9DC5146B1
+:10A800002046FFF799FB0028E3D02646079C4445E5
+:10A810003FF486ACB8EB04043FF48EAC029A0023FC
+:10A8200001320292A14488F80030A1E42646079C38
+:10A83000F0E704991BF8033051F8044B0491190711
+:10A8400000F1DB81DAF80430511C013BCAE9001346
+:10A85000A046137808F8013B012D00F0D381254470
+:10A8600014E0DAF800301A781BF80220120703F11E
+:10A87000010115D4DAF80420CAF80010013ACAF828
+:10A8800004201B7808F8013BA84509D0DAF8043009
+:10A89000002BE6DC51463046FFF74EFB0028E0D0A7
+:10A8A000A8EB0404A144029A00230132029288F822
+:10A8B00000305DE418F010030A9340F0FB80DDF8EF
+:10A8C000108058F8043B0793CDF810800023069CB5
+:10A8D000CDF8209006950B971D46B14639E000BF94
+:10A8E00061910108802202083C60274610AB18469F
+:10A8F000082200210993F6F7F1FBB348099BD0F831
+:10A90000E0003A460CA907464846B847012800F03F
+:10A91000048100221CAB9B5C002B00F05781089B3C
+:10A92000032C4344089300F0FB80069B013B0693F5
+:10A930000A9B002B40F0E880079A043207921D46DC
+:10A94000DAF80430002B40F3CB80069B002B00F09C
+:10A950001781FCF74BFBA8423FF4E2ABDAE9002396
+:10A9600012A812F8011B4155013B032CCAE9002330
+:10A9700005F101080EAE02D13368042B04D0082281
+:10A9800000213046F6F7AAFB079F0096434612AA1D
+:10A9900039464846FCF758FB0446601C3FF4C0AB00
+:10A9A000002CA1D0A11C08BF4546C9D0079B1B683D
+:10A9B0001F4601339AD13A46ACE718F010030793CB
+:10A9C00074D1049B53F8042B049308EE102A0897C3
+:10A9D000069F0025FCF70AFBA8423FF4A1ABDAE989
+:10A9E000000312AA10F8011B5155013B032F05F17A
+:10A9F0000108CAF80000CAF8043010AD02D12A6874
+:10AA0000042A04D0082200212846F6F767FB12AA80
+:10AA100018EE101A009543463046FCF715FB421C11
+:10AA200007463FF47DAB70BB079B13B918EE102AA5
+:10AA30001360C144013C079B23B918EE103A04335C
+:10AA400008EE103ADAF80430002B4FF0000521DD53
+:10AA5000002CBFD10697089F079B002B3FF498AEB0
+:10AA6000FFF786BB089B28F4607813B1013B08937D
+:10AA70000135079B0133079391E50DAB079327E65B
+:10AA80000F46FFF775BB831C40D1DAF8041000298C
+:10AA900045469FDC51463046FFF74EFA0028D7D096
+:10AAA0000697089F002DD7D0FFF73ABB002308EE8A
+:10AAB000103A8CE70DAB079308E7DDF8108058F8E3
+:10AAC000043BCDF810801880E4E5DDF8108058F8DC
+:10AAD000043BCDF810800F46A3F80090FFF748BB69
+:10AAE00051464846FFF728FA00283FF42EAF4E465D
+:10AAF0000B9FDDF820900694002D7FF411AB0A9B8C
+:10AB0000002B7FF435AB41E6002519E70328C1444B
+:10AB100090D12B68042B8DD18DE79DF83020F9E67C
+:10AB20003368042B7FF401AF02E70A46304614F87D
+:10AB3000011CFFF7C1F9013C44E5002D3FF4F0AAE8
+:10AB4000A94417E4BA7848F002080237FFF781BA3F
+:10AB5000069B02333FF405AE079B1868FCF718FA12
+:10AB6000F8B9069B032BB9447FF4F1AD2B68042B95
+:10AB70007FF4EDADEEE54FF0FF330293FFF7DCBA63
+:10AB80004E460B9FDDF820900694B8E7DDF8108064
+:10AB900058F8043B0F46C3F80090CDF81080FFF73B
+:10ABA000E7BA3B460A9F002B3FF4ECAD08EB0405E7
+:10ABB000297852463046FFF77FF9A84505F1FF3561
+:10ABC000F6D1DFE50027CCE5080D00204E460B9FAF
+:10ABD000DDF8209006942B46B8F1000F8FD012AA12
+:10ABE00013441C46217852463046FFF765F912ABF4
+:10ABF0009C4204F1FF34F5D181E7A04653E6FEF70D
+:10AC0000A5FB04E509F101094DE600BF01F1400390
+:10AC10002DE9F0410C46096B994214D0666B770020
+:10AC20003A46E6F7A5FD054640B300EB0608324676
+:10AC300040462946F6F74CF9C4E90C57C4F80080A1
+:10AC40000020BDE8F0814FF48061E6F78FFDA8B1E8
+:10AC500094F842304FF48062C4E90C0280F8FF336C
+:10AC600094F8413080F8FE3394F8403080F8FD339A
+:10AC700000F2FD3020600020BDE8F0814FF0FF3091
+:10AC8000DFE700BF70B54C1C34D00E4614460546B5
+:10AC900010B1836B002B30D0B4F90C309A0405D47A
+:10ACA000626E22F4005243F40053626623F02003E4
+:10ACB0005807A3819AB206D4D1061BD512073CD4FB
+:10ACC00043F00403A381236BF6B2EBB16268636BBC
+:10ACD0009A4209DA23685A1E226003F8016C6368FD
+:10ACE00001336360304670BD28462146FFF78EFF72
+:10ACF0000028EFD04FF0FF36F4E7F4F7A5FFB4F9E2
+:10AD00000C309A04D2D4CBE7226923682AB19A4244
+:10AD100003D213F8012CB2421CD0A363234660680F
+:10AD2000E06304F140010322C4E90C1203F8426F0E
+:10AD30000122C4E90032304670BD21462846F4F7AE
+:10AD400083FE0028D6D1B4F90C30A060A06123F0B6
+:10AD50000803B5E76268013B0132C4E90032C1E78C
+:10AD6000024B0A4601461868FFF78CBFC804002052
+:10AD70002DE9F84F4B6E9C0490462DD593681268D0
+:10AD800043B38B46064602F1080959E9025A5FEAC5
+:10AD90009A0715D0043D002401E0A7420ED055F8D3
+:10ADA000041F5A46304600F007FF431C04F101041B
+:10ADB000F3D10023C8E90133BDE8F88FD8F8083093
+:10ADC0002AF0030AA3EB0A03C8F8083009F10809BE
+:10ADD000002BDAD10020ECE7F5F7CEFA0023C8E922
+:10ADE0000133BDE8F88F00BF10B4946814B15DF86A
+:10ADF000044BBDE7204654605DF8044B704700BF2C
+:10AE00002DE9F04F2DED028BABB008EE100A1C4679
+:10AE10008A469346069318B1836B002B00F021827B
+:10AE2000BAF90C1088048AB20AD4DAF8643041F412
+:10AE3000005223F40053AAF80C20CAF8643092B2EE
+:10AE4000110740F1A980DAF81030002B00F0A4803F
+:10AE500002F01A020A2A00F0AE800023CDE90E3378
+:10AE60000993059318EE109A1AAB0D9398469BF828
+:10AE70000030002B00F014815C4604E014F8013F20
+:10AE8000002B00F0EB80252BF8D1B4EB0B0540F044
+:10AE9000E8802378002B00F003814FF000030021AD
+:10AEA0008DF82F304FF0FF326378049108460F463B
+:10AEB00004F1010B02920BF1010BA3F12002582ABD
+:10AEC00000F20181DFE812F07902FF00FF00740256
+:10AED000FF00FF00FF00FF00FF00FF00D6016F0230
+:10AEE000FF00E1013902FF006A02590059005900D0
+:10AEF000590059005900590059005900FF00FF003E
+:10AF0000FF00FF00FF00FF00FF00FF00FF00FF0049
+:10AF10005302FF00FF00FF00FF00FF00FF00FF00E3
+:10AF2000FF00FF00FF009300FF00FF00FF00FF0095
+:10AF3000FF008500FF00FF008F02FF00FF00FF0001
+:10AF4000FF00FF00FF00FF00FF00FF00FF00810285
+:10AF5000A401FF00FF00FF00C402A401FF00FF00E6
+:10AF6000B702FF00A40295002A022502FF00050295
+:10AF7000FF008700FF00FF00E601A3F1300200247C
+:10AF80001BF8013B04EB840402EB4404A3F1300200
+:10AF9000092AF5D9049490E718EE100A5146FAF7F9
+:10AFA000FDFE002840F0FF84BAF80C2002F01A02DF
+:10AFB0000A2A7FF452AFBAF90E30002BFFF64DAFDC
+:10AFC00018EE100A23465A46514600F00DFD059032
+:10AFD00073E047F01007BB0640F10F81069B073373
+:10AFE00023F00703F3E80245069301230DE047F041
+:10AFF000100717F0200300F0F280069B073323F0C0
+:10B000000703F3E80245069300234FF000028DF892
+:10B010002F2000220792029A1146013100F02F8260
+:10B0200027F08001019154EA050140F02782002AAF
+:10B0300040F06F84002B40F0E88317F00103039386
+:10B0400040F01B841AAEDDE902329342B8BF1346CA
+:10B050001D46079B002B47D0013545E0B4EB0B059F
+:10B060001ED0DDE90E3201332A44072BCDE90E3222
+:10B07000C8F800B0C8F8045006DC08F10808059AC2
+:10B0800023782A44059205E7002A00F0A6830DAA3A
+:10B0900051464846FFF76CFE50B90DF16808EEE7DF
+:10B0A0000F9B2BB118EE100A0DAA5146FFF760FE58
+:10B0B000BAF80C305B0600F1768405982BB0BDEC35
+:10B0C000028BBDE8F08F002940F04184002BE7D0CF
+:10B0D00001258DF840304FF000038DF82F30039597
+:10B0E00010AE002301970293019B13F00203079314
+:10B0F000019B18BF023513F08403089304D1049B0D
+:10B100005C1B002C00F3BF82DDE90E2C511C9DF866
+:10B110002F0078B10CF1010C0DF12F00012207294D
+:10B12000CDE90E1CC8E9000200F38E820A4608F140
+:10B1300008080131079BD3B10CF1020C0CAA0223C1
+:10B140000729CDE90E1CC8E9002340F39782BCF122
+:10B15000000F00F03D830DAA51464846FFF708FE58
+:10B160000028A5D1DDE90E2C0DF16808511C089BC3
+:10B17000802B00F0C581DDE902301F1A002F00F39B
+:10B180001882039A0E91134663440729C8E90062A6
+:10B190000F9340F3B281002B00F0B3820DAA514609
+:10B1A0004846FFF7E5FD002882D10F9B0DF16808A6
+:10B1B000019A520704D5049A541B002C00F3AB8269
+:10B1C000DDE90412A942ACBF521852190592002BB6
+:10B1D00040F02C8200230E930DF1680847E617F02B
+:10B1E000100241D117F040033ED0069951F8044BAC
+:10B1F00006911346A4B2002507E7069AFE0652F808
+:10B20000044B06924FF0010340F14F830025FCE60A
+:10B21000002940F0B583BA06069B40F1B1800733A0
+:10B2200023F007031946F1E80223069114461D4650
+:10B23000002A73F10003C0F2DF82029B013300F0A9
+:10B240000C819DF82F30079354EA050327F08007FF
+:10B2500040F00681029B002B40F007810197039389
+:10B26000F0E6F4F7F1FCDBE5069A52F8044B06929F
+:10B270000025CAE6069B53F8042B0492002A80F2AC
+:10B28000F782049A0693524204929BF8003047F0EA
+:10B29000040710E6002940F068839F4A0992B80627
+:10B2A000069A40F1A980073222F00702F2E802452F
+:10B2B0000692FE070BD554EA050208D030228DF81D
+:10B2C000313047F002078DF8302002239DE602233B
+:10B2D0009BE6069C54F8046B4FF000038DF82F306A
+:10B2E000002E00F01B83029A1346013300F0F08217
+:10B2F00000213046F5F79CFD002800F02C83831BCD
+:10B3000003939DF82F30079300230694019702932F
+:10B3100099E69BF8003047F02007CCE5069B53F8F0
+:10B32000044B069347F630027B4B0993ADF830206F
+:10B3300047F002070025022367E65C4614F8013B4C
+:10B340002A2B00F03583A3F13002092AA34698BFC7
+:10B35000002400F21E831BF8013B04EB840402EB83
+:10B360004404A3F13002092AF5D90294A5E5002985
+:10B3700040F0FE8247F01007BA06069B3FF54FAF3C
+:10B38000FE0653F8044B00F12E827D0640F12B821D
+:10B3900024B2E517069322462B4649E79BF8003076
+:10B3A00047F0800787E59BF8003001212B2082E5DC
+:10B3B0009BF8003047F001077DE59BF8003000283E
+:10B3C0007FF479AD0121202075E5069B012553F816
+:10B3D000042B8DF840204FF000018DF82F100693BC
+:10B3E000039510AE7DE6002940F0CD824B4A0992CC
+:10B3F000B806069A3FF557AF52F8044B0692F90685
+:10B4000000F1EF817A0640F1EC81A4B2002550E70B
+:10B41000002940F0BB82B80600F13B82F90600F13A
+:10B4200070827A0640F16D82069B059953F8042BD1
+:10B43000069311801BE59BF800306C2B03BF9BF833
+:10B44000013047F020070BF1010B47F0100732E500
+:10B450009BF8003047F040072DE59DF82F3007930B
+:10B46000002D08BF0A2C80F0E581303401238DF8CF
+:10B470006740019703930DF16706E4E5019F012BF7
+:10B48000EED0022B1AAE13D10998230904F00F0154
+:10B4900043EA05732A091C461546435C06F8013D3C
+:10B4A00054EA0503F1D11AAB9B1B01970393CAE53C
+:10B4B000E20842EA4572E90804F007030D46144623
+:10B4C000303354EA0501324606F8013DF0D1F80761
+:10B4D000E9D5302BE7D03023023A06F8013C1AAB0D
+:10B4E0009B1A019703931646ADE5039B1B9301221C
+:10B4F0000F931A960E920DF1680808F1080857E6A6
+:10B50000049B5F1B002F7FF736AE102F044C40F3D7
+:10B51000488263460DE000BFA81E0208941E020880
+:10B52000B4220208901C08F108080A46103F102FA8
+:10B530001DDD511C1033102007290F93C8F800405F
+:10B54000C8F804000E91EDDD0DAA51464846002BC7
+:10B5500075D0FFF70DFC00287FF4AAADDDE90E23BE
+:10B56000103F102F02F101000DF16808E1DC9C464C
+:10B57000BC440728C8E90047CDF83CC00E9040F312
+:10B580008381BCF1000F00F0D2810DAA51464846DC
+:10B59000FFF7EEFB00287FF48BADDDE90230DDE93B
+:10B5A0000E2C1F1A002F02F101010DF168087FF720
+:10B5B000E8AD102FC44CC8BF634607DC24E0911CE3
+:10B5C00008F108080246103F102F1CDD501C1033F4
+:10B5D000102107280F93C8F80040C8F804100E90F7
+:10B5E000EDDD0DAA51464846DBB1FFF7C1FB00284F
+:10B5F0007FF45EADDDE90E23103F102F02F1010153
+:10B600000DF16808E2DC9C46BC440729C8E9004704
+:10B61000CDF83CC00E9100F3C68008F10808013156
+:10B62000AFE501211A460DF16808CCE70DAA514695
+:10B630004846FFF79DFB00283FF4CCAD38E50120DC
+:10B640001A460DF1680871E7BCF1000F00F0BD80EB
+:10B650000DAA51464846FFF78BFB00287FF428AD22
+:10B66000DDE90E2C0DF16808511C63E502230CAADC
+:10B67000CDE91A239C4601210DF168080A4608F11C
+:10B680000808511C73E5102C40F37581DDE90E03A9
+:10B690008E4F06E0821C08F108080846103C102C6A
+:10B6A0001CDD411C1033102207290F93C8F80070CD
+:10B6B000C8F804200E91EDDD0DAA51464846DBB1D5
+:10B6C000FFF756FB00287FF4F3ACDDE90E03103CD6
+:10B6D000102C00F101020DF16808E2DC04EB030C10
+:10B6E000072AC8E90074CDF83CC00E9200F391809F
+:10B6F00008F10808511C0AE5184601220DF16808F6
+:10B70000CCE7019A0E93510745D5049A541B002C9F
+:10B7100041DD0DF16808102C40F33F810E996B4F0D
+:10B72000102606E0881C08F108081146103C102C71
+:10B7300019DD4A1C1033072AC8E900760F930E92D0
+:10B74000F0DD0DAA5146484603B3FFF711FB002870
+:10B750007FF4AEACDDE90E13103C102C01F10100BA
+:10B760000DF16808E5DC23440728C8E900740F934D
+:10B770000E907FF725AD73B10DAA51464846FFF7ED
+:10B78000F7FA00287FF494AC0F9B19E501201946C5
+:10B790000DF16808CAE7DDE90423AA42ACBF9B1893
+:10B7A0005B19059316E5BCF1000F3FF49EAE0DAAA0
+:10B7B00051464846FFF7DCFA00287FF479ACDDE912
+:10B7C0000E1C0DF168080131DBE4079B002B72D1E0
+:10B7D000012162460DF16808C9E40E920DF1680876
+:10B7E0004DE4002565E5E51722460693002A2B4621
+:10B7F00073F10003BFF621AD2D2364428DF82F3085
+:10B80000079365EB4505012305E4029B03931AAEFC
+:10B8100019E4BCF1000F68D00DAA51464846FFF765
+:10B82000A7FA00287FF444ACDDE90E2C0DF168087E
+:10B83000511C6CE41AAE204629460A22002301F06E
+:10B8400005FC303206F8012D00230A222046294645
+:10B8500001F0FCFB2B462246002B08BF0A2A0446B7
+:10B860000D46E8D21AAB9B1B01970393FFF7EBBB86
+:10B8700006939BF80030FFF71EBB30238DF867302E
+:10B880000DF16706FFF7DFBB08F10808411C02460F
+:10B8900071E4069B53F8041B0693059BDD171A46BB
+:10B8A0002B46C1E90023FFF7E2BA7D0648BFA4B2E8
+:10B8B0000025FFF7AABB02230CA9CDE91A139C4669
+:10B8C0000DF16808DBE600BFB4220208A4220208DA
+:10B8D0003046F6F735FB9DF82F300793002306948A
+:10B8E000019703900293FFF7AEBB9DF82F201ABB80
+:10B8F000079B002B7FF4BAAE624601210DF1680868
+:10B9000039E4069B059953F8042B11600693FFF761
+:10B91000AEBA012B019F7FF4B4ADA6E5029D2A4E7D
+:10B920000694062D28BF06250395FFF7DABB0121F3
+:10B9300062460DF168081EE401220DF12F00114648
+:10B940001B9294461A900DF16808FFF7EFBB8DF833
+:10B950002F00FFF7BBBB9DF82F300793029B03938B
+:10B96000CDE901700694FFF76EBB8DF82F0094E4CB
+:10B970008DF82F00FEE4DDE90E23144F0132ADE611
+:10B980008DF82F0047E48DF82F002FE58DF82F005C
+:10B9900041E500220292FFF790BA0E980B4F01305A
+:10B9A000E1E60846E4E54FF0FF330593FFF785BB7A
+:10B9B000069A9BF8013052F8045B0692A34645EACA
+:10B9C000E5740294FFF777BABC1E0208A4220208AD
+:10B9D00030B4044C0D46134601462A46206830BC5C
+:10B9E000FFF70EBAC8040020F0B50C46ADF26C4D5E
+:10B9F0008989666EE589199621F00201666AADF8BB
+:10BA00000E500025E769ADF80C10099606951AAEA0
+:10BA10004FF4806569460096049602950595079750
+:10BA20000646FFF7EDF9051E07DB30466946F4F7D9
+:10BA30000BF8002818BF4FF0FF35BDF80C305B063F
+:10BA400003D5A38943F04003A38128460DF26C4D32
+:10BA5000F0BD00BF10B4034CD4F8E040A4465DF83C
+:10BA6000044B6047080D002049B1FF2A02D80A7034
+:10BA7000012070478A2303604FF0FF30704708466B
+:10BA8000704700BF00B50A4C2568144685B01A46B9
+:10BA90000346E86844B1074D0091CDE901540649D9
+:10BAA00000F022F800F0FEFC044D2C46F4E700BF45
+:10BAB000C8040020C4220208D4220208D0220208AE
+:10BAC00008B513460022FFF7DDFF00BF0CB400B538
+:10BAD00083B004AB53F8042B0193FFF791F903B043
+:10BAE0005DF804EB02B070470EB410B583B005AB3F
+:10BAF000064C53F8042B019301462068FFF780F9A8
+:10BB000003B0BDE8104003B0704700BFC804002078
+:10BB10002DE9F04782B0804689461446FBF766FA65
+:10BB2000012803D109F1FF33FE2B36D94A4604F12F
+:10BB30005C0301A9404600F071FC421C064632D06D
+:10BB400030B39DF804C000250DF1040A09E0236814
+:10BB50005A1C226083F800C00135B54218D215F88E
+:10BB60000AC0A368013B002BA360F0DAA769BB42BF
+:10BB700061462246404602DBBCF10A0FE7D1FAF7E4
+:10BB800097F8431CE8D10646304602B0BDE8F0877E
+:10BB90004E46304602B0BDE8F0875FFA89FC0646A3
+:10BBA0008DF804C0CFE7A389304643F04003A3815A
+:10BBB00002B0BDE8F08700BFB2F90C3013F4005FAB
+:10BBC0000BD110B4546E43F4005344F40054546643
+:10BBD00093815DF8044BFFF79BBFFFF799BF00BF50
+:10BBE00030B5104B1D680C4683B001460DB1AB6BF0
+:10BBF0008BB1B4F90C309A0406D4626E43F400534E
+:10BC000042F40052A38162662246284603B0BDE892
+:10BC10003040FFF77DBF01902846F4F715F80199F1
+:10BC2000E7E700BFC80400202DE9F0410469B4EB48
+:10BC3000611F2FDD00F114074E1111F01F0C07EBEF
+:10BC4000840507EB86032BD057F8262004339D424A
+:10BC500022FA0CF1CCF1200818D9BE461A6802FA73
+:10BC600008F20A434EF8042B53F8041B9D4221FAB4
+:10BC70000CF1F3D8A31B9B00053B9B08013307EB9A
+:10BC8000830447F82310C9B1043417E041613C46EE
+:10BC90000029F9D10023036100234361BDE8F0814D
+:10BCA0009D4288BF00F11002F4D953F8041B42F8FA
+:10BCB000041F9D42F9D8A41B07EB8404E31B9B10CF
+:10BCC000BC420361E8D0BDE8F08100BF2DE9F04F30
+:10BCD000C14C2DED028B24688BB08946014620466D
+:10BCE00008EE101A039207930494F6F729F9D9F88D
+:10BCF0000030997802462018302910F801BC40F035
+:10BD0000EC816FF00100C01A033300EB030A1C46FC
+:10BD100013F8011B3029F8D0DFF8C08218F8013081
+:10BD2000002B00F0F9802378002718F803303D46F7
+:10BD300026462BB116F8013F18F80330002BF9D135
+:10BD4000049902923046F6F769F9029A01900028A8
+:10BD500000F09680002D40F096803378019503F036
+:10BD6000DF03502B354600F09880C9F80060002FA3
+:10BD700040F0B3802B1B013B072B394604DD5B10E1
+:10BD8000072B01F10101FADC18EE100A0592FBF70E
+:10BD9000C7F9059A0290002800F03F82029BAC424E
+:10BDA00003F11406069680F0C3810027C2F1010357
+:10BDB000B946059310E0202F00F09A8039460437E9
+:10BDC00015F8013C18F80330554603F00F038B407B
+:10BDD000A54249EA030916D915F8013C5B4505F16E
+:10BDE000FF3AE8D1059B5344A342E4D31846049993
+:10BDF00009920893F6F712F9DDE908320028DAD142
+:10BE00001D46A542E8D846F8049B069BF61A029BFD
+:10BE1000B6101E614846FBF763FA039B76011C6867
+:10BE2000301AA04200F3B780C0F235810027039B8F
+:10BE3000019A9B689342C0F26F810398019A43680C
+:10BE4000934240F386809D1AAC4200F3C980C268D9
+:10BE5000022A00F0A281032A00F09A81012A00F050
+:10BE60007E8118EE100A0299FBF780F95025169A88
+:10BE70000023284613600BB0BDEC028BBDE8F08FA9
+:10BE8000002D00F01881AD1BAB000193337803F057
+:10BE9000DF03502B35467FF468AF6B782B2B00F017
+:10BEA000F7802D2B72D06E1C4FF0000C18F8033069
+:10BEB000591E182968D8717818F80110103B0136FE
+:10BEC00039BBBCF1000F00D05B420199C9F800609A
+:10BED00019440191002F3FF44DAFBAF1000F14BF88
+:10BEE0000025062528460BB0BDEC028BBDE8F08F7F
+:10BEF000002146F8049B0427894661E716F8010FE4
+:10BF000003EB830301EB430318F80010103B0029F7
+:10BF1000D7D01929F2DDD4E7049901922046F6F72B
+:10BF20007DF8019A002879D1A15C18F80130A51894
+:10BF3000002B75D030292C4605D114F8013F302B49
+:10BF4000FBD018F80330B3FA83F77F094FF0010AEA
+:10BF5000EEE6012557B1039BDB68022B68D0032B6B
+:10BF60006AD0012B00F08B8045F01005169B1A4615
+:10BF7000029B1360079B1A46019B136028460BB077
+:10BF8000BDEC028BBDE8F08F2E46EEE64FF0010CC3
+:10BF9000AB78AE1C8AE7DDF80880061B31464046C8
+:10BFA000FBF78AFD074678B1721E069D511102F01B
+:10BFB0001F0355F82110012707FA03F30B4203D0A2
+:10BFC000BA4200F3BF800227DDE901303146334435
+:10BFD0000193FFF729FE2AE74024020840230208C4
+:10BFE0006E1E002F40F0A280002E40F0A58073113D
+:10BFF000069A029852F8232006F01F06012303FA3E
+:10C0000006F61642294618BF47F00207FFF70CFE56
+:10C01000039B5B680193641B02259BE721782546FF
+:10C0200001F0DF01502900F09680C9F8005054E774
+:10C03000179BC3F101031793179B002B94D0029B0E
+:10C04000DDF818C01E6900210CEB8600B7006346BE
+:10C0500003E0984243F8041C43D99E4653F8042B4E
+:10C06000B2F1FF3FF5D00132022DCEF8002000F0F2
+:10C07000998014F01F0440F0B980212576E7BA07B3
+:10C080007FF572AF069B1B681F43FB07D7D46BE796
+:10C090004FF0000C7CE7261A029918EE100A32467F
+:10C0A000FBF780FA019B02909B1B0193034614331C
+:10C0B00006930027BBE6B35C18F80310B0180646D9
+:10C0C00000293FF44CAE16F8013F18F80310002980
+:10C0D000F9D1801B8100019141E69C1C4FF0000AC0
+:10C0E0001AE6029B9B689E4263DA3346029800EB95
+:10C0F000830201210133022D0361516152D09E421E
+:10C10000B7DA02980121FFF78FFD039B019A9B6824
+:10C11000013293420192B0DA029918EE100AFBF74D
+:10C1200025F8169A00231360A325DBE601275EE7B6
+:10C13000069E4FF0000966E602983146FBF7BCFC0C
+:10C14000074654E7B11E4046FBF7B6FC00283FF413
+:10C150003AAF032738E70023019301279DE6AC425D
+:10C160007FF47FAE012C08D00298611EFBF7A4FC7F
+:10C1700000283FF476AE039B5B6807990B60029B37
+:10C18000069901221A610A60169A62251360A9E6CF
+:10C19000179A002A3FF465AEEFE7179A002A7FF45A
+:10C1A00060AEEAE7039B1B68013BA34229D022252E
+:10C1B000DCE6029B596818EE100A0131FAF7B0FF6D
+:10C1C000804680B302990B6902339A000C310C301F
+:10C1D000F4F77EFE029918EE100AFAF7C7FFD8F8B6
+:10C1E0001030CDF8088008F1140C7FE76744C4F1E3
+:10C1F000200457F8040CFBF773F8A042BFF63DAFDC
+:10C200007FE7631104F01F045CF823200123A3409F
+:10C2100013420CBF22252125A8E60246054B0648FD
+:10C22000DE21FFF72FFC0246024B03488421FFF773
+:10C2300029FC00BF482002080423020830B4046827
+:10C2400008E014F8013FA3F14105192D98BF2033F0
+:10C25000934208D111F8012B002AF2D10134046075
+:10C26000012030BC7047002030BC70472DE9F04FF2
+:10C27000096885B04B1111F01F01019002EB830397
+:10C28000039140F08A801D1F00930199086800996E
+:10C29000002341F8043C44780130002C00F0A880D1
+:10C2A000DFF8689102959A461E469846AC462946A4
+:10C2B00096460EE0202C00F29780B24506DA6145E2
+:10C2C00001D2072B7DDD8E455FD3082310F8014F87
+:10C2D00094B119F80450002DECD00133082B06F16D
+:10C2E00001064ADC0A68120105F00F0515430D60CE
+:10C2F00010F8014F002CECD1029D7246002E77D031
+:10C300008C4513D9072B11DCC3F108039B000E6881
+:10C31000C3F1200E0846476807FA0EF4344327FAA3
+:10C3200003F6046040F8046F8445F4D88A4238D29A
+:10C33000101F0B4653F8044B40F8044FAB42F9D999
+:10C340006B1A23F0030301310433681C884238BFA1
+:10C3500004231344002143F8041BAB42FBD9009B88
+:10C3600053F8043C2BB9AA4246D055F8043D002BA3
+:10C37000F9D0052005B0BDE8F08F8E45A6D241F872
+:10C38000048C002204390123AEE7A1F1040C41F82A
+:10C39000048CB2466146002398E7191D00911D46A2
+:10C3A00073E7039B002BDAD0039B009CC3F12001B1
+:10C3B00054F8040C4FF0FF33CB40034044F8043CE6
+:10C3C000D0E7C3F108039B000F68C3F1200B0C46B4
+:10C3D000656805FA0BF23A4325FA03F7226044F840
+:10C3E000047F6445F4D36EE7292C029D724609D080
+:10C3F000042005B0BDE8F08F012305202B6005B0B7
+:10C40000BDE8F08F019C0130206077E740230208EF
+:10C4100001490020704700BF0000F87F70B5064654
+:10C4200084B01D4639B10B4CD4F8E040A047431C02
+:10C430000AD004B070BD0C4606492246D1F8E0404F
+:10C4400001A9A047431CF4D100228A232A6033604B
+:10C4500004B070BD080D002070B5104D104B2D6854
+:10C4600084B0144650B1D3F8E0600A462346014632
+:10C470002846B047431C0AD004B070BDD3F8E06032
+:10C480000246234601A92846B047431CF4D10022A6
+:10C490008A2322602B6004B070BD00BFC804002056
+:10C4A000080D002008B5062000F092F80120E5F7FD
+:10C4B000A3FB00BF10B580210446E5F757F9C4F887
+:10C4C000DC0248B1031F00F17C02002143F8041F85
+:10C4D0009342FBD1002010BD4FF0FF3010BD00BFD4
+:10C4E000D0F8DC320BB100207047E3E71F2970B5AC
+:10C4F000044609D8D0F8DC320D4616464BB153F845
+:10C50000250043F8256070BD162303604FF0FF300F
+:10C5100070BDFFF7CFFF10B9D4F8DC32EFE74FF072
+:10C52000FF3070BD1F2938B5054621D8D0F8DC2270
+:10C530000C466AB152F8213053B1012B16D0591C68
+:10C5400010D00025204642F824509847284638BD90
+:10C55000284600F075F8224601462846BDE83840D6
+:10C5600000F058B816230360012038BD002038BD04
+:10C57000162303604FF0FF3038BD00BF1F2923D8BA
+:10C5800038B5D0F8DC320D46044683B153F8252087
+:10C5900003EB85034AB1511C11D0012A0DD00024B0
+:10C5A00028461C609047204638BD012038BDFFF763
+:10C5B00081FF30B9D4F8DC32E8E7032038BD02202F
+:10C5C00038BD4FF0FF3038BD4FF0FF30704700BF2F
+:10C5D000024B01461868FFF7A5BF00BFC804002042
+:10C5E000024B0A4601461868FFF780BFC8040020C6
+:10C5F000034B1868D0F8DC320BB10020704759E7C4
+:10C60000C8040020024B01461868FFF7B7BF00BFFF
+:10C61000C804002038B50C46084D03461146204694
+:10C6200000221C462A6000F0CBFE431C00D038BD1F
+:10C630002B68002BFBD0236038BD00BF00E6002034
+:10C6400000F0B6BE81F0004102E000BF83F000437D
+:10C6500030B54FEA41044FEA430594EA050F08BF9D
+:10C6600090EA020F1FBF54EA000C55EA020C7FEA61
+:10C67000645C7FEA655C00F0E2804FEA5454D4EBDE
+:10C680005555B8BF6D420CDD2C4480EA020281EAA8
+:10C69000030382EA000083EA010180EA020281EAE0
+:10C6A0000303362D88BF30BD11F0004F4FEA013132
+:10C6B0004FF4801C4CEA113102D0404261EB410141
+:10C6C00013F0004F4FEA03334CEA133302D05242C7
+:10C6D00063EB430394EA050F00F0A780A4F1010483
+:10C6E000D5F1200E0DDB02FA0EFC22FA05F28018BD
+:10C6F00041F1000103FA0EF2801843FA05F35941A3
+:10C700000EE0A5F120050EF1200E012A03FA0EFC21
+:10C7100028BF4CF0020C43FA05F3C01851EBE3714B
+:10C7200001F0004507D54FF0000EDCF1000C7EEB68
+:10C7300000006EEB0101B1F5801F1BD3B1F5001FA6
+:10C740000CD349085FEA30004FEA3C0C04F10104C5
+:10C750004FEA445212F5800F80F09A80BCF1004FEE
+:10C7600008BF5FEA500C50F1000041EB045141EA70
+:10C77000050130BD5FEA4C0C404141EB0101013C39
+:10C7800028BFB1F5801FE9D291F0000F04BF014628
+:10C790000020B1FA81F308BF2033A3F10B03B3F1FA
+:10C7A00020020CDA0C3208DD02F1140CC2F10C028A
+:10C7B00001FA0CF021FA02F10CE002F11402D8BFE8
+:10C7C000C2F1200C01FA02F120FA0CFCDCBF41EAB4
+:10C7D0000C019040E41AA2BF01EB0451294330BD83
+:10C7E0006FEA04041F3C1CDA0C340EDC04F1140460
+:10C7F000C4F1200220FA04F001FA02F340EA030037
+:10C8000021FA04F345EA030130BDC4F10C04C4F17C
+:10C81000200220FA02F001FA04F340EA030029465C
+:10C8200030BD21FA04F0294630BD94F0000F83F4A6
+:10C83000801306BF81F480110134013D4EE77FEA89
+:10C84000645C18BF7FEA655C29D094EA050F08BFD5
+:10C8500090EA020F05D054EA000C04BF19461046B6
+:10C8600030BD91EA030F1EBF0021002030BD5FEAFA
+:10C87000545C05D14000494128BF41F0004130BD22
+:10C8800014F580043CBF01F5801130BD01F0004576
+:10C8900045F0FE4141F470014FF0000030BD7FEAE9
+:10C8A000645C1ABF194610467FEA655C1CBF0B46E4
+:10C8B000024650EA013406BF52EA033591EA030FFB
+:10C8C00041F4002130BD00BF90F0000F04BF0021F3
+:10C8D000704730B54FF4806404F132044FF0000526
+:10C8E0004FF0000150E700BF90F0000F04BF00219F
+:10C8F000704730B54FF4806404F1320410F0004505
+:10C9000048BF40424FF000013EE700BF42004FEAFF
+:10C91000E2014FEA31014FEA02701FBF12F07F437C
+:10C9200093F07F4F81F06051704732F07F4208BF33
+:10C93000704793F07F4F04BF41F40021704730B53A
+:10C940004FF4607401F0004521F000411CE700BF86
+:10C9500050EA010208BF704730B54FF000050AE009
+:10C9600050EA010208BF704730B511F0004502D50A
+:10C97000404261EB41014FF4806404F132045FEA0C
+:10C98000915C3FF4D8AE4FF003025FEADC0C18BFB5
+:10C9900003325FEADC0C18BF033202EBDC02C2F1A7
+:10C9A000200300FA03FC20FA02F001FA03FE40EA39
+:10C9B0000E0021FA02F11444BDE600BF70B54FF03D
+:10C9C000FF0C4CF4E06C1CEA11541DBF1CEA13551B
+:10C9D00094EA0C0F95EA0C0F00F0DEF82C4481EA83
+:10C9E000030621EA4C5123EA4C5350EA013518BFA3
+:10C9F00052EA033541F4801143F4801338D0A0FB90
+:10CA000002CE4FF00005E1FB02E506F00042E0FB3C
+:10CA100003E54FF00006E1FB03569CF0000F18BF42
+:10CA20004EF0010EA4F1FF04B6F5007F64F54074EA
+:10CA300004D25FEA4E0E6D4146EB060642EAC6217D
+:10CA400041EA55514FEAC52040EA5E504FEACE2EEA
+:10CA5000B4F1FD0C88BFBCF5E06F1ED8BEF1004FED
+:10CA600008BF5FEA500E50F1000041EB045170BD69
+:10CA700006F0004646EA010140EA020081EA0301AD
+:10CA8000B4EB5C04C2BFD4EB0C0541EA045170BDA9
+:10CA900041F480114FF0000E013C00F3AB8014F123
+:10CAA000360FDEBF002001F0004170BDC4F100046C
+:10CAB000203C35DA0C341BDC04F11404C4F12005ED
+:10CAC00000FA05F320FA04F001FA05F240EA020048
+:10CAD00001F0004221F0004110EBD37021FA04F67E
+:10CAE00042EB06015EEA430E08BF20EAD37070BD38
+:10CAF000C4F10C04C4F1200500FA04F320FA05F097
+:10CB000001FA04F240EA020001F0004110EBD37098
+:10CB100041F100015EEA430E08BF20EAD37070BD08
+:10CB2000C4F1200500FA05F24EEA020E20FA04F3E1
+:10CB300001FA05F243EA020321FA04F001F0004190
+:10CB400021FA04F220EA020000EBD3705EEA430E01
+:10CB500008BF20EAD37070BD94F0000F0FD101F030
+:10CB60000046400041EB010111F4801F08BF013C69
+:10CB7000F7D041EA060195F0000F18BF704703F0A7
+:10CB80000046520043EB030313F4801F08BF013D2E
+:10CB9000F7D043EA0603704794EA0C0F0CEA1355EA
+:10CBA00018BF95EA0C0F0CD050EA410618BF52EAA4
+:10CBB0004306D1D181EA030101F000414FF00000AA
+:10CBC00070BD50EA410606BF1046194652EA4306B8
+:10CBD00019D094EA0C0F02D150EA013613D195EA2C
+:10CBE0000C0F05D152EA03361CBF104619460AD174
+:10CBF00081EA030101F0004141F0FE4141F470017E
+:10CC00004FF0000070BD41F0FE4141F4780170BD6D
+:10CC100070B54FF0FF0C4CF4E06C1CEA11541DBFD2
+:10CC20001CEA135594EA0C0F95EA0C0F00F0A7F8D4
+:10CC3000A4EB050481EA030E52EA03354FEA013101
+:10CC400000F088804FEA03334FF0805545EA131314
+:10CC500043EA12634FEA022245EA111545EA1065DC
+:10CC60004FEA00260EF000419D4208BF964244F173
+:10CC7000FD0404F5407402D25B084FEA3202B61A92
+:10CC800065EB03055B084FEA32024FF480104FF466
+:10CC9000002CB6EB020E75EB030E22BFB61A7546DA
+:10CCA00040EA0C005B084FEA3202B6EB020E75EB6D
+:10CCB000030E22BFB61A754640EA5C005B084FEAD5
+:10CCC0003202B6EB020E75EB030E22BFB61A7546A2
+:10CCD00040EA9C005B084FEA3202B6EB020E75EBAD
+:10CCE000030E22BFB61A754640EADC0055EA060E6E
+:10CCF00018D04FEA051545EA16754FEA06164FEAB1
+:10CD0000C30343EA52734FEAC2025FEA1C1CC0D15C
+:10CD100011F4801F0BD141EA00014FF000004FF0E9
+:10CD2000004CB6E711F4801F04BF01430020B4F1AA
+:10CD3000FD0C88BFBCF5E06F3FF6AFAEB5EB030C62
+:10CD400004BFB6EB020C5FEA500C50F1000041EB5F
+:10CD5000045170BD0EF0004E4EEA113114EB5C042C
+:10CD6000C2BFD4EB0C0541EA045170BD41F48011FF
+:10CD70004FF0000E013C90E645EA060E8DE60CEA07
+:10CD8000135594EA0C0F08BF95EA0C0F3FF43BAF24
+:10CD900094EA0C0F0AD150EA01347FF434AF95EADB
+:10CDA0000C0F7FF425AF104619462CE795EA0C0FBF
+:10CDB00006D152EA03353FF4FDAE1046194622E78C
+:10CDC00050EA410618BF52EA43067FF4C5AE50EA66
+:10CDD00041047FF40DAF52EA43057FF4EBAE12E756
+:10CDE0004FF0FF3C06E000BF4FF0010C02E000BF37
+:10CDF0004FF0010C4DF804CD4FEA410C7FEA6C5C1A
+:10CE00004FEA430C18BF7FEA6C5C1BD001B050EABC
+:10CE1000410C0CBF52EA430C91EA030F02BF90EAA7
+:10CE2000020F0020704710F1000F91EA030F58BF66
+:10CE3000994208BF90422CBFD8176FEAE37040F0C8
+:10CE4000010070474FEA410C7FEA6C5C02D150EA66
+:10CE5000013C07D14FEA430C7FEA6C5CD6D152EA21
+:10CE6000033CD3D05DF8040B704700BF84461046E6
+:10CE700062468C461946634600E000BF01B5FFF7E5
+:10CE8000B7FF002848BF10F1000F01BD4DF808EDB5
+:10CE9000FFF7F4FF0CBF012000205DF808FB00BF86
+:10CEA0004DF808EDFFF7EAFF34BF012000205DF8E0
+:10CEB00008FB00BF4DF808EDFFF7E0FF94BF01202D
+:10CEC00000205DF808FB00BF4DF808EDFFF7CEFF2E
+:10CED00094BF012000205DF808FB00BF4DF808ED6D
+:10CEE000FFF7C4FF34BF012000205DF808FB00BF3E
+:10CEF0004FEA410C7FEA6C5C02D150EA013C0AD156
+:10CF00004FEA430C7FEA6C5C02D152EA033C02D147
+:10CF10004FF0000070474FF0010070474FEA4102A8
+:10CF200012F5001215D211D56FF47873B3EB62527B
+:10CF300012D94FEAC12343F0004343EA505311F0A2
+:10CF4000004F23FA02F018BF404270474FF0000034
+:10CF5000704750EA013005D111F0004008BF6FF072
+:10CF6000004070474FF00000704700BF4A0011D2E8
+:10CF700012F5001211D20DD56FF47873B3EB625233
+:10CF80000ED44FEAC12343F0004343EA505323FA3F
+:10CF900002F070474FF00000704750EA013002D1B4
+:10CFA0004FF0FF3070474FF0000070474FEA4102EA
+:10CFB000B2F1E04324BFB3F5001CDCF1FE5C0DD9F7
+:10CFC00001F0004C4FEAC0024CEA5070B2F1004F41
+:10CFD00040EB830008BF20F00100704711F0804F44
+:10CFE00021D113F13872BCBF01F00040704741F409
+:10CFF00080114FEA5252C2F11802C2F1200C10FA0D
+:10D000000CF320FA02F018BF40F001004FEAC123F0
+:10D010004FEAD32303FA0CFC40EA0C0023FA02F394
+:10D020004FEA4303CCE77FEA625307D150EA01336A
+:10D030001EBF4FF0FE4040F44000704701F000403A
+:10D0400040F0FE4040F40000704700BF53B94AB9B9
+:10D05000002908BF00281CBF4FF0FF314FF0FF3000
+:10D0600000F0A4B9ADF1080C6DE904CE00F03CF875
+:10D07000DDF804E0DDE9022304B0704738B5002292
+:10D08000002304460D46FFF70BFF28B9204629462A
+:10D09000BDE8384000F00AB8204605F1004100F034
+:10D0A00005F8404261EB410138BD00BFD0B50C4BE3
+:10D0B000002206460F46FFF781FCFFF757FF0446A4
+:10D0C000FFF702FC074B0022FFF778FC02460B46F5
+:10D0D00030463946FFF7BAFAFFF748FF2146D0BD80
+:10D0E0000000F03D0000F0412DE9F047089D0446A6
+:10D0F0008C46002B40F083808A42174647D9B2FA0B
+:10D1000082F242B1C2F1200024FA00F0914097402F
+:10D1100040EA010C94404FEA1748230CBCFBF8F698
+:10D120001FFA87FE08FB16C143EA014306FB0EF116
+:10D13000994209D9FB1806F1FF3080F01981994214
+:10D1400040F21681023E3B445B1AA4B2B3FBF8F0F6
+:10D1500008FB103344EA034400FB0EFEA64509D940
+:10D160003C1900F1FF3380F00581A64540F20281B1
+:10D1700002383C4440EA0640A4EB0E0400261DB1F0
+:10D18000D4400023C5E900433146BDE8F08702B929
+:10D19000FFDEB2FA82F2002A50D1CB1B4FEA174EC3
+:10D1A0001FFA87F80126B3FBFEFC210C0EFB1C3393
+:10D1B00041EA034108FB0CF38B4207D979180CF1C3
+:10D1C000FF3002D28B4200F2E9808446C91AA3B232
+:10D1D000B1FBFEF00EFB101143EA014408FB00F81E
+:10D1E000A04507D93C1900F1FF3302D2A04500F257
+:10D1F000D9801846A4EB080440EA0C40BFE78B42F4
+:10D2000009D9002D00F0B1800026C5E900013046A3
+:10D210003146BDE8F087B3FA83F6002E4AD18B423F
+:10D2200002D3824200F2B880841A61EB030101202C
+:10D230008C46002DA8D0C5E9004CA5E7C2F120031B
+:10D2400020FA03F6974001FA02F04FEA174ED94050
+:10D250003043030CB1FBFEF61FFA87F80EFB1611E4
+:10D2600043EA014306FB08F1994204FA02F409D9A2
+:10D27000FB1806F1FF3C80F08D80994240F28A80D5
+:10D28000023E3B445B1A81B2B3FBFEF00EFB10334F
+:10D2900041EA034100FB08F38B4207D9791800F1FA
+:10D2A000FF3C73D28B4271D902383944CB1A40EA21
+:10D2B000064678E7C6F1200C03FA06F422FA0CF3CE
+:10D2C0001C4320FA0CF701FA06F34FEA144E21FA38
+:10D2D0000CF11F433B0CB1FBFEF91FFA84F80EFB67
+:10D2E000191143EA014109FB08FA8A4502FA06F2DC
+:10D2F00000FA06F308D9611809F1FF3048D28A45CF
+:10D3000046D9A9F102092144A1EB0A01BFB2B1FB40
+:10D31000FEF00EFB101147EA014700FB08F8B84584
+:10D3200007D9E71900F1FF312ED2B8452CD90238C0
+:10D33000274440EA0940A7EB0807A0FB02894F45B4
+:10D34000C64649461AD317D05DB1B3EB0E0267EB60
+:10D35000010707FA0CFCF2404CEA0202F740C5E96B
+:10D36000002700263146BDE8F0872E4628460BE709
+:10D370000646E9E61846FDE64345E5D2B8EB020E5F
+:10D3800069EB04010138DFE70846D2E760468DE724
+:10D390008146B9E7664675E730464AE7ACF1020CCC
+:10D3A000394413E702383C4424E700BF704700BF0C
+:10D3B000024B58221A604FF0FF30704700E6002001
+:10D3C000024B58221A604FF0FF30704700E60020F1
+:10D3D000F8B500BFF8BC08BC9E467047F8B500BF62
+:10D3E000F8BC08BC9E4670472E2E2F2E2F6D62650E
+:10D3F000642D6F732F706C6174666F726D2F53693B
+:10D400006E676C65746F6E5074722E68005F707416
+:10D4100072203D3D202854202A29265F64617461D2
+:10D42000002E2E2F2E2F6D6265642D6F732F706C62
+:10D430006174666F726D2F43616C6C6261636B2EF9
+:10D4400068005F6F707300000000000000000000C3
+:10D4500051050008790500088502000889020008C6
+:10D460008F02000800000000000000006D070008A7
+:10D4700097070008BD060008E90800080109000830
+:10D48000850800089D08000800000000000000005A
+:10D490008309000895090008A5090008E5090008A6
+:10D4A0006B09000877090008B4FFFFFF00000000C7
+:10D4B000D9090008F709000871160008411600088C
+:10D4C000A31600083D1600083D1600083D1600088A
+:10D4D000A7160008AB160008A71600084D0900089B
+:10D4E00053090008590900085F0900086509000888
+:10D4F000690900087B0900086F0900088D09000808
+:10D500009B090008B0FFFFFF00000000DF090008D2
+:10D51000FD09000800000000000000003D0A0008AE
+:10D520003D0A0008E10B0008390C0008000000006B
+:10D5300000000000F50C0008190D00084B0C000855
+:10D540000000000000000000590D00086D0D0008EB
+:10D550002D0D000800000000000000000000000089
+:10D5600000000000AD1B0008636F756C64206E6FD7
+:10D57000742070696E6F75740070696E6D617020D3
+:10D580006D69732D6D617463680070696E6D617093
+:10D59000206E6F7420666F756E6420666F722070E7
+:10D5A00065726970686572616C0070696E6D61703A
+:10D5B000206E6F7420666F756E6420666F722066D1
+:10D5C000756E6374696F6E004465657020736C6579
+:10D5D0006570206C6F636B20776F756C64206F765D
+:10D5E0006572666C6F7720283E2055534852545F11
+:10D5F0004D415829004465657020736C6565702045
+:10D600006C6F636B20776F756C6420756E646572E8
+:10D61000666C6F7720283C203029002E2E2F6D62FB
+:10D6200065642D6F732F68616C2F6D6265645F7424
+:10D6300069636B65725F6170692E63003000000082
+:10D6400048D60108B80F0020FF7A0008017B0008C7
+:10D65000397B00084D7B0008097B0008257B00080A
+:10D66000851C00080000000000000000B114000844
+:10D670000915000800000000000000000000000084
+:10D6800000000000AD1B0008AD1B0008AD1B00082A
+:10D69000AD1B0008691500086D150008D90E0008BB
+:10D6A000E30E0008711500084D0900085309000831
+:10D6B000590900085F0900086509000869090008A0
+:10D6C000772B0053747265616D206F626A2066610A
+:10D6D000696C7572652C206572726E6F3D25640DE4
+:10D6E0000A00000000000000000000000000000030
+:10D6F00000000000AD1B0008AD1B0008AD1B0008BA
+:10D70000AD1B0008691500086D150008D90E00084A
+:10D71000E30E0008711500084D09000853090008C0
+:10D72000590900085F09000865090008690900082F
+:10D73000FCFFFFFF000000000000000000000000F0
+:10D7400000000000000000000000000000000000D9
+:10D750007116000841160008A31600083D160008BF
+:10D760003D1600083D160008A7160008AB16000875
+:10D77000A71600084D0900085309000859090008B8
+:10D780005F0900086509000869090008AD1B000869
+:10D79000AD1B0008391600083B160008FCFFFFFF10
+:10D7A0000000000000000000000000006D626564E1
+:10D7B000206173736572746174696F6E206661694C
+:10D7C0006C65643A2025732C2066696C653A2025C7
+:10D7D000732C206C696E65202564200A002E2E2F84
+:10D7E0006D6265642D6F732F706C6174666F726DFE
+:10D7F0002F6D6265645F637269746963616C2E6327
+:10D8000000696E746572727570745F656E61626CCA
+:10D81000655F636F756E746572203C2055494E5488
+:10D8200033325F4D415800696E7465727275707461
+:10D83000735F64697361626C6564004572726F72D4
+:10D84000202D2077726974696E6720746F206120C3
+:10D8500066696C6520696E20616E20495352206FA5
+:10D860007220637269746963616C207365637469A3
+:10D870006F6E0D0A004572726F72202D2072656105
+:10D8800064696E672066726F6D20612066696C65E1
+:10D8900020696E20616E20495352206F722063729E
+:10D8A00069746963616C2073656374696F6E0D0AD6
+:10D8B0000000000040420F00200000002F7374643D
+:10D8C000657272002F737464696E002F7374646FD5
+:10D8D00075740061706C69636174696F6E5F756EF9
+:10D8E0006E616D65645F6D75746578002E2E2F6DA9
+:10D8F0006265642D6F732F72746F732F4D7574652D
+:10D90000782E637070005F69640073696E676C6580
+:10D91000746F6E5F6D75746578006D616C6C6F63AC
+:10D920005F6D7574657800656E765F6D757465788A
+:10D93000006D61696E5F7468726561640050726544
+:10D94000206D61696E20746872656164206E6F7409
+:10D95000206372656174656400434D5349532D52D1
+:10D96000544F53206572726F723A20537461636B27
+:10D9700020756E646572666C6F77202873746174AD
+:10D9800075733A20307825582C207461736B2049C8
+:10D99000443A20307825582C207461736B206E61D6
+:10D9A0006D653A202573290A0D00434D5349532DC7
+:10D9B00052544F53206572726F723A20495352206D
+:10D9C0005175657565206F766572666C6F77202876
+:10D9D0007374617475733A20307825582C20746103
+:10D9E000736B2049443A20307825582C206F626AA6
+:10D9F0006563742049443A2030782558290A0D007F
+:10DA0000434D5349532D52544F53206572726F72D8
+:10DA10003A20557365722054696D65722043616CBC
+:10DA20006C6261636B205175657565206F766572F8
+:10DA3000666C6F7720287374617475733A20307840
+:10DA400025582C207461736B2049443A2030782586
+:10DA5000582C2074696D65722049443A203078252D
+:10DA600058290A0D00434D5349532D52544F53200A
+:10DA70006572726F723A2053544420432F432B2B0C
+:10DA8000206C696272617279206C69627370616383
+:10DA900065206E6F7420617661696C61626C6520CF
+:10DAA000287374617475733A20307825582C20746B
+:10DAB00061736B2049443A2030782558290A0D00BB
+:10DAC000434D5349532D52544F53206572726F7218
+:10DAD0003A2053544420432F432B2B206C6962720D
+:10DAE000617279206D7574657820696E69746961F9
+:10DAF0006C697A6174696F6E206661696C65642017
+:10DB0000287374617475733A20307825582C20740A
+:10DB100061736B2049443A2030782558290A0D005A
+:10DB2000434D5349532D52544F53206572726F72B7
+:10DB30003A20556E6B6E6F776E2028737461747522
+:10DB4000733A20307825582C207461736B20494437
+:10DB50003A2030782558290A0D00556E6B6E6F7784
+:10DB60006E004B65726E656C206572726F72202557
+:10DB7000693A2025730D0A00546872656164202596
+:10DB800070206572726F722025693A2025730D0A24
+:10DB9000004D75746578202570206572726F722053
+:10DBA00025693A2025730D0A004D65737361676519
+:10DBB000205175657565202570206572726F722021
+:10DBC00025690D0A004E6F7420616C6C6F77656477
+:10DBD00020696E2049535220636F6E74657874001B
+:10DBE00053797374656D206973206F7574206F6647
+:10DBF000206D656D6F727900506172616D6574653D
+:10DC000072206572726F72005265736F7572636510
+:10DC1000206E6F7420617661696C61626C65004F83
+:10DC20007065726174696F6E206E6F7420636F6DC2
+:10DC3000706C657465642077697468696E207468B7
+:10DC4000652074696D656F757420706572696F64A5
+:10DC500000556E7370656369666965642052544F40
+:10DC600053206572726F7200C5DB0108E0DB0108AA
+:10DC7000F8DB010808DC01081FDC010851DC0108A1
+:10DC80005254582056352E312E310000000000002D
+:10DC90000000000000000000000000000000000084
+:10DCA0000000000000000000000000000000000074
+:10DCB0000000000000000000000000000000000064
+:10DCC0000000000003000000E80300000500000061
+:10DCD0008011002010000000000000000000000083
+:10DCE0000000000000000000000000000000000034
+:10DCF0000000000000000000000000000000000024
+:10DD00000000000000000000000000000000000013
+:10DD100000000000000000000010000030DD0108DD
+:10DD20006CDD010854DD0108040000000000000063
+:10DD300000000000000000008C12002048000000DD
+:10DD4000D8150020000200000100000000000000C3
+:10DD5000000000000000000000000000C0110020D2
+:10DD600034000000F411002050000000000000000A
+:10DD7000000000004412002048000000D8120020DB
+:10DD80000003000028000000000000000000000068
+:10DD900000000000000004500350000001000000DB
+:10DDA0000000045003600000030000000000045065
+:10DDB00003800000040000000000045003900000F5
+:10DDC000050000000000045003A000000600000051
+:10DDD0000000045003B000000700000000000450E1
+:10DDE00003C00000100000000000045003F0000019
+:10DDF000FFFF0000FFFFFFFF00000000F000000039
+:10DE00000000045003100100F10000000000045065
+:10DE100003000000F2000000000004500320010095
+:10DE2000FFFF0000FFFFFFFF0000000006000000F2
+:10DE300000300140120500000B00000000300140DE
+:10DE40001205000014000000003C00401206000013
+:10DE5000140100000030014012050000FFFF000027
+:10DE6000FFFFFFFF0000000007000000003001403E
+:10DE7000120500000C0000000030014012050000F7
+:10DE800015000000003C00401206000015010000D3
+:10DE90000030014012050000FFFF0000FFFFFFFF00
+:10DEA00000000000010000000030014012050000E9
+:10DEB00005000000003001401205000013000000C2
+:10DEC000003C004012060000130100000030014039
+:10DED00012050000FFFF0000FFFFFFFF0000000031
+:10DEE00004000000003C0040120600000401000095
+:10DEF0000030014012050000100000000030014019
+:10DF000012050000FFFF0000FFFFFFFF0000000000
+:10DF1000030000000044004012070000030100005D
+:10DF200000800040120800000A0000000038014094
+:10DF3000120700000F000000004400401203000020
+:10DF4000170000000038014012070000FFFF00002A
+:10DF5000FFFFFFFF0000000002000000004400403F
+:10DF600012070000020100000080004012080000BB
+:10DF700009000000003801401207000016000000F0
+:10DF80000038014012070000FFFF0000FFFFFFFF05
+:10DF9000000000002E2E2F6D6265642D6F732F74AC
+:10DFA0006172676574732F5441524745545F5354EF
+:10DFB0004D2F5441524745545F53544D33324C34E6
+:10DFC0002F616E616C6F67696E5F6170692E6300AF
+:10DFD0006F626A2D3E68616E646C652E496E737463
+:10DFE000616E636520213D20284144435F54797070
+:10DFF00065446566202A294E430066756E63746920
+:10E000006F6E20213D202875696E7433325F74294C
+:10E010004E430043616E6E6F7420696E697469616E
+:10E020006C697A65204144430A000402080010101C
+:10E030001004101010021010100800000000000062
+:10E0400000000102030406070809000000000102A5
+:10E0500003040000A0860100400D0300801A0600A2
+:10E0600000350C0040420F0080841E0000093D0076
+:10E0700000127A000024F40000366E010048E80126
+:10E08000006CDC0200000000000000000600000040
+:10E090000000000001000000070000000000000078
+:10E0A0000200000008000000000000000300000063
+:10E0B0000900000000000000040000000A00000049
+:10E0C0000000000005000000170000000100000033
+:10E0D000050000001700000002000000050000001D
+:10E0E00017000000030000000500000017000000FA
+:10E0F0000400000005000000170000000000000000
+:10E1000006000000280000000100000006000000DA
+:10E1100028000000020000000600000028000000A7
+:10E1200003000000060000002800000004000000BA
+:10E1300006000000280000000500000006000000A6
+:10E14000280000002E2E2F6D6265642D6F732F74D2
+:10E150006172676574732F5441524745545F53543D
+:10E160004D2F5441524745545F53544D33324C3434
+:10E170002F73657269616C5F6465766963652E6390
+:10E18000006F626A5F732D3E7561727420213D20BD
+:10E1900028554152544E616D65294E4300434C4B06
+:10E1A0003A2053504920696E7374616E6365206E26
+:10E1B0006F74207365740050696E6D6170206572B4
+:10E1C000726F723A2077726F6E6720706F72742070
+:10E1D0006E756D6265722E002E2E2F6D6265642D38
+:10E1E0006F732F746172676574732F544152474582
+:10E1F000545F53544D2F6770696F5F6170692E6370
+:10E200000070696E20213D202850696E4E616D6559
+:10E21000294E4300556E65787065637465642053BC
+:10E22000707572696F757320696E7465727275703E
+:10E23000742C20696E6465782025640D0A00496E8F
+:10E2400074657272757074496E206572726F723A7D
+:10E250002070696E206E6F7420737570706F7274A9
+:10E2600065642E0A002E2E2F6D6265642D6F732F4C
+:10E27000746172676574732F5441524745545F53FC
+:10E28000544D2F70696E6D61702E630001000000A7
+:10E290000200000004000000080000001000000060
+:10E2A000200000004000000080000000000100008D
+:10E2B0000002000000040000000800000010000040
+:10E2C00000200000004000000080000043616E6EEE
+:10E2D0006F7420696E697469616C697A6520554153
+:10E2E00052540A0043616E6E6F7420696E697469DE
+:10E2F000616C697A6520535049002E2E2F6D62653E
+:10E30000642D6F732F746172676574732F5441525B
+:10E310004745545F53544D2F73746D5F7370695F3D
+:10E320006170692E63007370696F626A2D3E73704D
+:10E330006920213D20285350494E616D65294E4387
+:10E340000000000008001000180020002800300025
+:10E35000380020202025693A737461743A256920B9
+:10E3600049503A0025692E25692E25692E256920F8
+:10E370004D41433A00253032583A0025303258207A
+:10E38000006167653A25697365630D0A00FFFFFF49
+:10E39000FFFFFF0000000000000806000108000663
+:10E3A0000400020000000000000000000000000067
+:10E3B000000000000000000000000000000000FF5E
+:10E3C000FFFFFFFFFF00000000000008060001083B
+:10E3D0000006040001000000000000000000000032
+:10E3E000000000000000000000000000000000002D
+:10E3F0000074656C6E657420636F6E6E6578696F0E
+:10E400006E20636C6F7365640D0A72656164793E9A
+:10E41000200065786974206F6E6C792076616C6974
+:10E420006420666F722074656C6E65740D0A726587
+:10E430006164793E2000257300726164696F206D0C
+:10E44000757374206265206F666620666F72207433
+:10E4500068697320636F6D6D616E640D0A7265612A
+:10E4600064793E20007265636F6E666967757269D4
+:10E470006E6720726164696F2E2E2E0D0A00726124
+:10E4800064696F207472616E736D69742074657352
+:10E4900074202569207365636F6E64732E2E2E0DB4
+:10E4A0000A00434F4E4649473A0D0A202063616CEB
+:10E4B0006C7369676E3A20272573270D0A2020693F
+:10E4C000735F6D61737465723A2025730D0A2020A5
+:10E4D0004D41433A20253032583A253032583A25BA
+:10E4E0003032583A253032583A253032583A2530B1
+:10E4F00032580D0A0020204574685F6D6F64653ADC
+:10E500002025690D0A0020206578745F5352414D23
+:10E510003A2025730D0A0020206672657175656EBC
+:10E5200063793A20252E33664D487A0D0A202066FD
+:10E530007265715F73686966743A20252E33664D83
+:10E54000487A0D0A202052465F706F7765723A2034
+:10E5500025690D0A20206D6F64756C6174696F6E9A
+:10E560003A2025690D0A002020726164696F5F6E90
+:10E570006574775F49443A2025690D0A202072614D
+:10E5800064696F5F6F6E5F61745F73746172743A18
+:10E590002025730D0A00202074656C6E657420615F
+:10E5A00063746976653A2025730D0A202074656CC2
+:10E5B0006E657420726F757465643A2025730D0A58
+:10E5C0000020206D6F64656D5F49503A2025692EEB
+:10E5D00025692E25692E25690D0A20206E65746D2A
+:10E5E00061736B3A2025692E25692E25692E2569D0
+:10E5F0000D0A0020206D61737465725F4644443AD1
+:10E600002025730D0A00202049505F626567696EFE
+:10E610003A2025692E25692E25692E25690D0A20A7
+:10E62000206D61737465725F49505F73697A653AF2
+:10E6300020256C6420284C6173742049503A2025B1
+:10E64000692E25692E25692E2569290D0A002020AD
+:10E650006465665F726F7574655F61637469766522
+:10E660003A2025730D0A20206465665F726F757409
+:10E67000655F76616C3A2025692E25692E25692E05
+:10E6800025690D0A002020444E535F61637469764A
+:10E69000653A2025730D0A2020444E535F76616C45
+:10E6A00075653A2025692E25692E25692E25690D67
+:10E6B0000A0020206D61737465725F646F776E5F0E
+:10E6C00049503A2025692E25692E25692E25690D88
+:10E6D0000A00202049505F626567696E3A2025690B
+:10E6E0002E25692E25692E25690D0A002020636CD0
+:10E6F00069656E745F7265715F73697A653A20252A
+:10E700006C640D0A2020444843505F61637469764D
+:10E71000653A2025730D0A0025692E25692E256985
+:10E720002E2569004F4B0D0A72656164793E200009
+:10E7300062616420495020666F726D61740D0A72C7
+:10E74000656164793E2000796573006E6F007661C3
+:10E750006C7565206D75737420626520277965730B
+:10E7600027206F7220276E6F270D0A72656164790A
+:10E770003E200063616C6C7369676E006E65772084
+:10E7800063616C6C7369676E20272573270D0A72AD
+:10E79000656164793E200069735F6D6173746572B1
+:10E7A0000020287761726E696E672C2044484350C0
+:10E7B00020696E6869626974656420696E206D61A4
+:10E7C00073746572206D6F646529004D61737465A3
+:10E7D00072202725732725730D0A72656164793EBF
+:10E7E000200074656C6E65745F61637469766500A2
+:10E7F00074656C6E65742061637469766520272585
+:10E8000073270D0A72656164793E200074656C6E31
+:10E8100065745F726F757465640074656C6E6574A1
+:10E8200020726F7574656420272573270D0A726541
+:10E830006164793E2000444E535F6163746976657C
+:10E8400000444E5320616374697665202725732741
+:10E850000D0A72656164793E20006465665F726FBF
+:10E860007574655F6163746976650064656661757A
+:10E870006C7420726F7574652061637469766520AD
+:10E88000272573270D0A72656164793E20006D614A
+:10E89000737465725F46444400646F776E007570F0
+:10E8A00000202077726F6E672076616C75650D0AA7
+:10E8B00000726164696F5F6F6E5F61745F73746132
+:10E8C000727400726164696F5F6F6E5F61745F7311
+:10E8D0007461727420272573270D0A72656164794B
+:10E8E0003E2000444843505F61637469766500448C
+:10E8F0004843505F6163746976653A202725732722
+:10E9000025730D0A72656164793E20006D6F646540
+:10E910006D5F4950006E65746D61736B0064656670
+:10E920005F726F7574655F76616C00444E535F76FD
+:10E93000616C75650049505F626567696E006D6165
+:10E94000737465725F646F776E5F4950006D6173B9
+:10E950007465725F49505F73697A6500256C640065
+:10E9600077726F6E672076616C75650D0A726561EE
+:10E9700064793E2000636C69656E745F7265715FD7
+:10E9800073697A65006672657175656E63790025D5
+:10E99000660077726F6E6720667265712076616CB3
+:10E9A00075650D0A72656164793E20006672657155
+:10E9B0005F73686966740052465F706F77657200B6
+:10E9C0006572726F72203A206D61782052465F70D6
+:10E9D0006F7765722076616C7565203132370D0A6C
+:10E9E00072656164793E20004574685F6D6F64658F
+:10E9F000006572726F72203A206D617820457468EC
+:10EA00005F6D6F64652076616C756520370D0A72E5
+:10EA1000656164793E20006D6F64756C6174696F27
+:10EA20006E0077726F6E67206D6F64756C617469CC
+:10EA30006F6E2076616C75650D0A72656164793E52
+:10EA40002000726164696F5F6E6574775F4944008E
+:10EA500077726F6E672076616C75652C203135207A
+:10EA60006D61780D0A72656164793E2000756E6B88
+:10EA70006E6F776E20636F6E66696720706172617A
+:10EA80006D0D0A72656164793E20007365742063C0
+:10EA90006F6D6D616E64207265717569726573204A
+:10EAA0003220706172616D0D0A72656164793E2079
+:10EAB0000025732569204D61737465723A204944BD
+:10EAC0003A3132372043616C6C7369676E3A257353
+:10EAD0000D0A004D453A2043616C6C7369676E3ACC
+:10EAE00025732049443A2569206D6F64656D20497E
+:10EAF000503A25692E25692E25692E25690D0A00B3
+:10EB0000436C69656E74733A0D0A002049443A25D6
+:10EB1000692043616C6C7369676E3A257320004904
+:10EB2000502073746172743A25692E25692E256907
+:10EB30002E25692000495020656E643A25692E25EE
+:10EB4000692E25692E25690D0A002020202020200D
+:10EB500020202020202020202020202020202020B5
+:10EB600020202020202020202020202020202020A5
+:10EB70002020202020202020202020202020202095
+:10EB80002020202020200D0A002573202020256928
+:10EB9000207374617475733A20726164696F204FD9
+:10EBA0004646202020202020202020202020202019
+:10EBB000200D0A00257320202025692073746174BC
+:10EBC00075733A2072656A65637465642062656373
+:10EBD0006175736520746F6F206D616E7920257388
+:10EBE000200D0A002573202020256920737461748C
+:10EBF00075733A2025732054413A252E31666B6D8A
+:10EC00002054656D703A2569646567432020200DA6
+:10EC10000A00202020525820746F70732066726F93
+:10EC20006D206D61737465722046444420646F7773
+:10EC30006E2025690D0A0020202052585F45746817
+:10EC40005F49507634202569203B54585F726164D7
+:10EC5000696F5F49507634202569203B2052585F08
+:10EC6000726164696F5F49507634202569202020E5
+:10EC70000D0A00202020444F574E4C494E4B202D6A
+:10EC80002062616E6477696474683A252E3166206B
+:10EC9000525353493A252E3166204552523A252E79
+:10ECA00032662525202020200D0A00202020444FF8
+:10ECB000574E4C494E4B202D2062616E647769643B
+:10ECC00074683A20252E316620525353493A202049
+:10ECD00020202020204552523A2020202020200DA4
+:10ECE0000A0020202055504C494E4B202D2020203A
+:10ECF00062616E6477696474683A252E31662052C9
+:10ED00005353493A252E3166204552523A252E3228
+:10ED1000662525202020200D0A4354524C2B6320C9
+:10ED2000746F20657869742E2E2E0D0A0020202025
+:10ED300055504C494E4B202D20202062616E647747
+:10ED4000696474683A252E316620525353493A203B
+:10ED5000202020204552523A2020202020200D0A39
+:10ED60004354524C2B6320746F20657869742E2EA7
+:10ED70002E0D0A00726164696F006F666600756E21
+:10ED80006B6E6F776E20726164696F20636F6D6D5B
+:10ED9000616E640D0A72656164793E200054585FAB
+:10EDA000746573740073746174757300646973704F
+:10EDB0006C617900636F6E66696700737461746972
+:10EDC0006300444843505F41525000756E6B6E6F54
+:10EDD000776E20646973706C617920636F6D6D610B
+:10EDE0006E640D0A72656164793E200077686F0079
+:10EDF00077007265626F6F7400736176650073618E
+:10EE000076656420696E6465783A25690D0A7265D5
+:10EE10006164793E200072657365745F746F5F642E
+:10EE2000656661756C7400636C656172696E6720FC
+:10EE3000736176656420636F6E6669672E2E2E0D92
+:10EE40000A00446F6E652E204E6F77207265626FE8
+:10EE50006F74696E672E2E2E0D0A007665727369C7
+:10EE60006F6E003730636D00323032325F30315FA9
+:10EE70003234006669726D776172653A2025730DD0
+:10EE80000A667265712062616E643A2025730D0A0C
+:10EE900072656164793E20006578697400756E6BF7
+:10EEA0006E6F776E20636F6D6D616E640D0A7265B3
+:10EEB0006164793E200068656C700048454C5020C4
+:10EEC000636D643A2068656C702C2073746174758E
+:10EED00073202873292C20646973706C6179206316
+:10EEE0006F6E6669672C20646973706C617920733A
+:10EEF00074617469632C20646973706C6179204457
+:10EF00004843505F4152502C0909090D0A7365743A
+:10EF1000205B706172616D735D2C20726164696F3A
+:10EF20002C2054585F746573742C2077686F2028E8
+:10EF300077292C20736176652C207265626F6F745F
+:10EF40002C2076657273696F6E2C20726573657400
+:10EF50005F746F5F64656661756C742C2065786999
+:10EF6000740909090D0A72656164793E20000D0A71
+:10EF70000D0A6E65772074656C6E657420636F6E24
+:10EF80006E6578696F6E2066726F6D2025692E251B
+:10EF9000692E25692E25690D0A73657269616C20D9
+:10EFA000696E6163746976652E2E2E0D0A004E50CF
+:10EFB00052206D6F64656D0D0A72656164793E2043
+:10EFC000001B5B411B5B411B5B411B5B411B5B41AE
+:10EFD0001B5B411B5B411B5B411B5B411B5B411B83
+:10EFE0005B41000000000000000000000000000085
+:10EFF0000000004552522050726F746F636F6C0DA9
+:10F000000A00464543206572726F720D0A007061F6
+:10F01000727420696E666F3A200066756E6374695B
+:10F020006F6E20696E666F3A20007265636F6E6660
+:10F0300069677572696E6720646F6E653B207374D3
+:10F04000617274696E6720726164696F0D0A0011E4
+:10F050000001031000000000001112021100FF0067
+:10F060000000001112020B3064000000003336393A
+:10F070003C6366696C9396999CC3C6C9CC0000003A
+:10F080000011110103CC000000000000001122015A
+:10F09000017F0000000000080421714B0000DC9596
+:10F0A0000805A62221F0415B2608E22F1CBB0AA816
+:10F0B000942808058767E2581A075B08E1D072D8E0
+:10F0C0008AB85B7D080511EC9E28231B6D08E24F72
+:10F0D0008AB2A92914130805D12E716A514C2C0843
+:10F0E000E5802742A469B07F0805AA812ABD45E8CA
+:10F0F000A808EAE4F024C99FCC3C080508F50504FB
+:10F1000027629808EA6B6284A1F94AE20805E97768
+:10F11000054F84EE3508E243C38DFBAD5425080549
+:10F1200014065E39362F4508EA0C1C74D011FC32E7
+:10F130000805DA38BA0E3CE78B08EAB009E6FF9416
+:10F14000BBA90805D71129FEDC71D508EA7F83A782
+:10F15000609062180805847F6AD191C65208EA2A35
+:10F16000D87B8E4A9F910805BDAA9D1618061508E2
+:10F17000E255AD2D0A141F5D0805D3E07C39CF019F
+:10F18000F008EF3A91726A03BB9608E7836DA49288
+:10F19000FC13A708EFF8FDCF62076F1E08E74CEAE3
+:10F1A0004A754FD6CF08E2F611E4260D4DC6080584
+:10F1B000FBBFE80789C35108EF8227043F96A85890
+:10F1C00008E741293C752A031C08EFAF599836AA75
+:10F1D0000F0608E6F693412DEC0E990805291990C3
+:10F1E000E5AA364008E7FB68107D775DC008E7CBED
+:10F1F000B4DDCE9054BE08E7728AD602F4DDCC08A6
+:10F20000E76A210B0286EC1508E77B7C3D6B8103E6
+:10F21000D008EF7D6136947CA0DF08EFCC853BDA27
+:10F22000E05C1C08E7E375BB39224BA808EFF9CE78
+:10F23000E05EEB1DCB08E7BDE270D5AB4E3F08E7C3
+:10F24000B78D20686B095208EFA11B90CD98006321
+:10F2500008EF54675D9C11FC4508E7D49BC897BE36
+:10F260008A0708EF528D906373D52A08EF03BC6EAE
+:10F270001C76BE4A08E7C2ED67BA5E662108EFE772
+:10F280003F87BEE07A6D08E7C970931D64F56C088E
+:10F29000EFF5280834B3B62C08EF3A0AEC0FDB562A
+:10F2A000CA08EF39A06EED79D02408E76C0BAFA93E
+:10F2B0004E40B508E9B9AFBF2550D13708059EDBF0
+:10F2C000DE3F94E96B08ECC505AA57DC8A5E0805A9
+:10F2D00070DA8484DDCA900702810001C9C3800806
+:10F2E000130020212000000005110001005205112B
+:10F2F000000103200511100104211011200C00034E
+:10F30000000702710005C9C3800000051120010C2F
+:10F31000461011200C18010008038000B0100CE802
+:10F32000004E1011200C24068DB9000002C0080008
+:10F330001200230711200330015CA00511200135C4
+:10F34000E01011200C38111111801A200000280C37
+:10F35000A42309112005450300850100081120049C
+:10F360004B060910400611200250940A0611200293
+:10F37000540307051120015700091120055B4004C3
+:10F380000478201011210C007E641BBA580BDDCECE
+:10F39000D6E6F6001011210C0C030315F03F007E99
+:10F3A000641BBA580B1011210C18DDCED6E6F600FE
+:10F3B000030315F03F0005112201031D0B11230764
+:10F3C000002C0E0B040C73030C11400800370900CD
+:10F3D000000AEC20FE0832000000000000000517C3
+:10F3E0005610CAF005171310CAF0051100010100EC
+:10F3F0000511000103200711010300033301081167
+:10F4000002040004060A090D11100900101400FF7F
+:10F4100031000000000A111106000A45D2CC00009C
+:10F420001011120C00040108FFFF2022002A015ACB
+:10F43000301011120C0C4000011680003F12000029
+:10F4400000001011120C1800000000000000000065
+:10F450000000001011120C24000000000000000049
+:10F460000000000009111205300000000000081122
+:10F47000120436000000001011200C000500070FD8
+:10F48000424009C9C3800006051120010CD41011A7
+:10F49000200C18050008038000202000E8004B1015
+:10F4A00011200C2406D3A006D4020200001281B55C
+:10F4B000071120033001CBA00511200135E0101108
+:10F4C000200C38111010001A155500280CA4230E1A
+:10F4D00011200A450301150100FF0602184006111C
+:10F4E000200250840A06112002540407051120014D
+:10F4F0005700091120055B40040878201011210CE9
+:10F5000000FFC4307FF5B5B8DE0517160C101121C9
+:10F510000C0C030015FF0000FFC4307FF5B510117F
+:10F52000210C18B8DE0517160C030015FF000008A3
+:10F5300011220400087F001D0B112307002C0E0B65
+:10F54000040C73031011300C0000000000000000D8
+:10F5500000000000000C11400800380AAAAA0AECBA
+:10F5600020FE00000000000000000000000000007D
+:10F57000000000000000000000080421714B0000A2
+:10F58000DC950805A62221F0415B2608E22F1CBB72
+:10F590000AA8942808058767E2581A075B08E1D093
+:10F5A00072D88AB85B7D080511EC9E28231B6D0874
+:10F5B000E24F8AB2A92914130805D12E716A514C61
+:10F5C0002C08E5802742A469B07F0805AA812ABDDE
+:10F5D00045E8A808EAE4F024C99FCC3C080508F5F2
+:10F5E000050427629808EA6B6284A1F94AE20805DB
+:10F5F000E977054F84EE3508E243C38DFBAD542512
+:10F60000080514065E39362F4508EA0C1C74D01123
+:10F61000FC320805DA38BA0E3CE78B08EAB009E696
+:10F62000FF94BBA90805D71129FEDC71D508EA7F34
+:10F6300083A7609062180805847F6AD191C652083A
+:10F64000EA2AD87B8E4A9F910805BDAA9D16180606
+:10F650001508E255AD2D0A141F5D0805D3E07C396D
+:10F66000CF01F008EF3A91726A03BB9608E7836D09
+:10F67000A492FC13A708EFF8FDCF62076F1E08E7FE
+:10F680004CEA4A754FD6CF08E2F611E4260D4DC676
+:10F690000805FBBFE80789C35108EF8227043F969E
+:10F6A000A85808E741293C752A031C08EFAF599870
+:10F6B00036AA0F0608E6F693412DEC0E99080529A7
+:10F6C0001990E5AA364008E7FB68107D775DC00811
+:10F6D000E7CBB4DDCE9054BE08E7728AD602F4DDE3
+:10F6E000CC08E76A210B0286EC1508E77B7C3D6BB2
+:10F6F0008103D008EF7D6136947CA0DF08EFCC85D4
+:10F700003BDAE05C1C08E7E375BB39224BA808EF45
+:10F71000F9CEE05EEB1DCB08E7BDE270D5AB4E3F06
+:10F7200008E7B78D20686B095208EFA11B90CD98B0
+:10F73000006308EF54675D9C11FC4508E7D49BC843
+:10F7400097BE8A0708EF528D906373D52A08EF039E
+:10F75000BC6E1C76BE4A08E7C2ED67BA5E66210839
+:10F76000EFE73F87BEE07A6D08E7C970931D64F547
+:10F770006C08EFF5280834B3B62C08EF3A0AEC0F02
+:10F78000DB56CA08EF39A06EED79D02408E76C0B80
+:10F79000AFA94E40B508E9B9AFBF2550D13708052C
+:10F7A0009EDBDE3F94E96B08ECC505AA57DC8A5E58
+:10F7B000080570DA8484DDCA900702810001C9C39C
+:10F7C00080081300202120000000051100010052D4
+:10F7D0000511000103200511100104211011200C56
+:10F7E0000003000702710005C9C380000005112055
+:10F7F000010C461011200C18010008038000B01005
+:10F800000CE8004E1011200C24068DB9000002C037
+:10F8100008001200230711200330015CA00511200D
+:10F820000135E01011200C38111111801A20000050
+:10F83000280CA423091120054503008501000811A7
+:10F8400020044B060910400611200250940A0611AC
+:10F850002002540307051120015700091120055B00
+:10F8600040040478201011210C007E641BBA580B50
+:10F87000DDCED6E6F6001011210C0C030315F03F87
+:10F88000007E641BBA580B1011210C18DDCED6E691
+:10F89000F600030315F03F0005112201031D0B11B3
+:10F8A0002307002C0E0B040C73030C1140080037C7
+:10F8B0000900000AEC20FE083200000000000000F1
+:10F8C00005175610CAF005171310CAF005110001EC
+:10F8D000010005110001032007110103000333019A
+:10F8E000081102040004060A090D11100900101481
+:10F8F00000EF31000000000A111106000245D2CCD1
+:10F9000000001011120C00040108FFFF2002002A61
+:10F91000015A301011120C0C4000010680003F0209
+:10F92000000000001011120C180000000000000080
+:10F9300000000000001011120C2400000000000064
+:10F940000000000000000911120530000000000056
+:10F950000811120436000000001011200C000300F2
+:10F96000071E848009C9C380000D051120010CA762
+:10F970001011200C18010008038000102000E8007E
+:10F980004B1011200C2406D3A006D4020000002343
+:10F9900086D4071120033000D3A00511200135E0E3
+:10F9A0001011200C38111010801A400000280CA4EF
+:10F9B000230E11200A450301150100FF060218401D
+:10F9C0000611200250840A06112002540407051172
+:10F9D00020015700091120055B4004087820101110
+:10F9E000210C00FFC4307FF5B5B8DE0517160C10EA
+:10F9F00011210C0C030015FF0000FFC4307FF5B58A
+:10FA00001011210C18B8DE0517160C030015FF00A5
+:10FA1000000811220400087F001D0B112307003489
+:10FA2000040B040770031011300C000000000000EC
+:10FA3000000000000000000C11400800380AAAAACB
+:10FA40000AEC20FE000000000000000000000000A2
+:10FA50000000000000000000000000080421714BBD
+:10FA60000000DC950805A62221F0415B2608E22F64
+:10FA70001CBB0AA8942808058767E2581A075B0888
+:10FA8000E1D072D88AB85B7D080511EC9E28231B53
+:10FA90006D08E24F8AB2A92914130805D12E716AA4
+:10FAA000514C2C08E5802742A469B07F0805AA8143
+:10FAB0002ABD45E8A808EAE4F024C99FCC3C080523
+:10FAC00008F5050427629808EA6B6284A1F94AE206
+:10FAD0000805E977054F84EE3508E243C38DFBAD99
+:10FAE0005425080514065E39362F4508EA0C1C74A7
+:10FAF000D011FC320805DA38BA0E3CE78B08EAB0C0
+:10FB000009E6FF94BBA90805D71129FEDC71D508C9
+:10FB1000EA7F83A7609062180805847F6AD191C646
+:10FB20005208EA2AD87B8E4A9F910805BDAA9D16E5
+:10FB300018061508E255AD2D0A141F5D0805D3E01F
+:10FB40007C39CF01F008EF3A91726A03BB9608E75F
+:10FB5000836DA492FC13A708EFF8FDCF62076F1E18
+:10FB600008E74CEA4A754FD6CF08E2F611E4260DB5
+:10FB70004DC60805FBBFE80789C35108EF8227047B
+:10FB80003F96A85808E741293C752A031C08EFAFA7
+:10FB9000599836AA0F0608E6F693412DEC0E9908FF
+:10FBA00005291990E5AA364008E7FB68107D775DC6
+:10FBB000C008E7CBB4DDCE9054BE08E7728AD60207
+:10FBC000F4DDCC08E76A210B0286EC1508E77B7CA4
+:10FBD0003D6B8103D008EF7D6136947CA0DF08EF98
+:10FBE000CC853BDAE05C1C08E7E375BB39224BA807
+:10FBF00008EFF9CEE05EEB1DCB08E7BDE270D5ABB8
+:10FC00004E3F08E7B78D20686B095208EFA11B90A3
+:10FC1000CD98006308EF54675D9C11FC4508E7D45C
+:10FC20009BC897BE8A0708EF528D906373D52A0848
+:10FC3000EF03BC6E1C76BE4A08E7C2ED67BA5E668B
+:10FC40002108EFE73F87BEE07A6D08E7C970931D92
+:10FC500064F56C08EFF5280834B3B62C08EF3A0ABF
+:10FC6000EC0FDB56CA08EF39A06EED79D02408E717
+:10FC70006C0BAFA94E40B508E9B9AFBF2550D137DD
+:10FC800008059EDBDE3F94E96B08ECC505AA57DC4E
+:10FC90008A5E080570DA8484DDCA9007028100015B
+:10FCA000C9C38008130020212000000005110001B5
+:10FCB000005205110001032005111001042110114B
+:10FCC000200C0003000702710005C9C38000000575
+:10FCD0001120010C461011200C18010008038000AF
+:10FCE000B0100CE8004E1011200C24068DB9000055
+:10FCF00002C008001200230711200330015CA00598
+:10FD000011200135E01011200C38111111801A203A
+:10FD10000000280CA42309112005450300850100DB
+:10FD2000081120044B060910400611200250940AC5
+:10FD30000611200254030705112001570009112064
+:10FD4000055B40040478201011210C007E641BBA6E
+:10FD5000580BDDCED6E6F6001011210C0C0303156E
+:10FD6000F03F007E641BBA580B1011210C18DDCE39
+:10FD7000D6E6F600030315F03F0005112201031D2E
+:10FD80000B112307002C0E0B040C73030C114008FD
+:10FD900000370900000AEC20FE08320000000000D5
+:10FDA000000005175610CAF005171310CAF0051108
+:10FDB00000010100051100010320071101030003E8
+:10FDC0003301081102040004060A090D111009008C
+:10FDD000101400FF31000000000A111106000A454E
+:10FDE000D2CC00001011120C00040108FFFF2022E9
+:10FDF000002A015A301011120C0C4000011680002C
+:10FE00003F12000000001011120C1800000000004A
+:10FE1000000000000000001011120C24000000007F
+:10FE20000000000000000000091112053000000071
+:10FE300000000811120436000000001011200C0010
+:10FE40000500071E848009C9C380000D051120012B
+:10FE50000CA71011200C18050008038000102000CA
+:10FE6000E8004B1011200C2406D3A006D402020097
+:10FE7000002386D4071120033000D3A005112001F0
+:10FE800035E01011200C38111010001A15550028FB
+:10FE90000CA4230E11200A450301150100FF0602E0
+:10FEA00018400611200250840A061120025404074B
+:10FEB000051120015700091120055B400408782036
+:10FEC0001011210C00FFC4307FF5B5B8DE05171600
+:10FED0000C1011210C0C030015FF0000FFC4307F33
+:10FEE000F5B51011210C18B8DE0517160C03001516
+:10FEF000FF00000811220400087F001D0B112307DA
+:10FF00000034040B040770031011300C00000000D3
+:10FF10000000000000000000000C11400800380A3A
+:10FF2000AAAA0AEC20FE0000000000000000000069
+:10FF30000000000000000000000000000008042194
+:10FF4000714B0000DC950805A62221F0415B2608D4
+:10FF5000E22F1CBB0AA8942808058767E2581A07F5
+:10FF60005B08E1D072D88AB85B7D080511EC9E2849
+:10FF7000231B6D08E24F8AB2A92914130805D12E5C
+:10FF8000716A514C2C08E5802742A469B07F0805AE
+:10FF9000AA812ABD45E8A808EAE4F024C99FCC3C20
+:10FFA000080508F5050427629808EA6B6284A1F940
+:10FFB0004AE20805E977054F84EE3508E243C38D30
+:10FFC000FBAD5425080514065E39362F4508EA0CAA
+:10FFD0001C74D011FC320805DA38BA0E3CE78B08E5
+:10FFE000EAB009E6FF94BBA90805D71129FEDC7128
+:10FFF000D508EA7F83A7609062180805847F6AD1DC
+:020000040802F0
+:1000000091C65208EA2AD87B8E4A9F910805BDAA5C
+:100010009D1618061508E255AD2D0A141F5D08053A
+:10002000D3E07C39CF01F008EF3A91726A03BB96B6
+:1000300008E7836DA492FC13A708EFF8FDCF6207D1
+:100040006F1E08E74CEA4A754FD6CF08E2F611E476
+:10005000260D4DC60805FBBFE80789C35108EF828E
+:1000600027043F96A85808E741293C752A031C0835
+:10007000EFAF599836AA0F0608E6F693412DEC0E1D
+:10008000990805291990E5AA364008E7FB68107D14
+:10009000775DC008E7CBB4DDCE9054BE08E7728A26
+:1000A000D602F4DDCC08E76A210B0286EC1508E7DE
+:1000B0007B7C3D6B8103D008EF7D6136947CA0DFB3
+:1000C00008EFCC853BDAE05C1C08E7E375BB39221E
+:1000D0004BA808EFF9CEE05EEB1DCB08E7BDE27060
+:1000E000D5AB4E3F08E7B78D20686B095208EFA1EA
+:1000F0001B90CD98006308EF54675D9C11FC450888
+:10010000E7D49BC897BE8A0708EF528D906373D5DA
+:100110002A08EF03BC6E1C76BE4A08E7C2ED67BA38
+:100120005E662108EFE73F87BEE07A6D08E7C97099
+:10013000931D64F56C08EFF5280834B3B62C08EF6E
+:100140003A0AEC0FDB56CA08EF39A06EED79D024DD
+:1001500008E76C0BAFA94E40B508E9B9AFBF255011
+:10016000D13708059EDBDE3F94E96B08ECC505AA94
+:1001700057DC8A5E080570DA8484DDCA9007028144
+:100180000001C9C3800813002021200000000511D0
+:100190000001005205110001032005111001042186
+:1001A0001011200C0003000702710005C9C3800074
+:1001B00000051120010C461011200C180100080345
+:1001C0008000B0100CE8004E1011200C24068DB9F0
+:1001D000000002C008001200230711200330015C58
+:1001E000A00511200135E01011200C3811111180EB
+:1001F0001A200000280CA4230911200545030085BE
+:100200000100081120044B0609104006112002507D
+:10021000940A061120025403070511200157000912
+:100220001120055B40040478201011210C007E642D
+:100230001BBA580BDDCED6E6F6001011210C0C03CC
+:100240000315F03F007E641BBA580B1011210C18E7
+:10025000DDCED6E6F600030315F03F0005112201BE
+:10026000031D0B112307002C0E0B040C73030C1140
+:10027000400800370900000AEC20FE0832000000A8
+:100280000000000005175610CAF005171310CAF039
+:1002900005110001010005110001032007110103F0
+:1002A00000033301081102040004060A090D1110AD
+:1002B0000900101400EF31000000000A11110600BF
+:1002C0000245D2CC00001011120C00040108FFFFFF
+:1002D0002002002A015A301011120C0C40000106B5
+:1002E00080003F02000000001011120C18000000F6
+:1002F0000000000000000000001011120C2400009B
+:10030000000000000000000000000911120530008C
+:100310000000000008111204360000000010112037
+:100320000C0003000736EE8009C9C38000180511D0
+:1003300020010C931011200C18010008038000000C
+:100340002000E800531011200C240624DD062B02A7
+:10035000000000238C4A071120033000D3A00511B0
+:10036000200135E01011200C38111212801A4000C3
+:1003700000280CA4230E11200A450300F90100FFF8
+:10038000060218400611200250840A061120025469
+:100390000307051120015700091120055B400407E0
+:1003A00078201011210C00CCA130A021D1B9C9EACC
+:1003B0000512111011210C0C0A0415FC0300CCA12C
+:1003C00030A021D11011210C18B9C9EA0512110A67
+:1003D0000415FC03000811220400087F003D0B11E6
+:1003E00023070039040B050401031011300C000031
+:1003F00000000000000000000000000C1140080098
+:10040000380AAAAA0AEC20FE000000000000000042
+:1004100000000000000000000000000000000008D4
+:100420000421714B0000DC950805A62221F0415BF8
+:100430002608E22F1CBB0AA8942808058767E25803
+:100440001A075B08E1D072D88AB85B7D080511EC09
+:100450009E28231B6D08E24F8AB2A92914130805B0
+:10046000D12E716A514C2C08E5802742A469B07FD7
+:100470000805AA812ABD45E8A808EAE4F024C99F36
+:10048000CC3C080508F5050427629808EA6B6284ED
+:10049000A1F94AE20805E977054F84EE3508E24301
+:1004A000C38DFBAD5425080514065E39362F45086B
+:1004B000EA0C1C74D011FC320805DA38BA0E3CE79D
+:1004C0008B08EAB009E6FF94BBA90805D71129FEFD
+:1004D000DC71D508EA7F83A7609062180805847FE5
+:1004E0006AD191C65208EA2AD87B8E4A9F910805A4
+:1004F000BDAA9D1618061508E255AD2D0A141F5DFC
+:100500000805D3E07C39CF01F008EF3A91726A0315
+:10051000BB9608E7836DA492FC13A708EFF8FDCF04
+:1005200062076F1E08E74CEA4A754FD6CF08E2F61D
+:1005300011E4260D4DC60805FBBFE80789C3510825
+:10054000EF8227043F96A85808E741293C752A0303
+:100550001C08EFAF599836AA0F0608E6F693412D0E
+:10056000EC0E990805291990E5AA364008E7FB68C2
+:10057000107D775DC008E7CBB4DDCE9054BE08E7B0
+:10058000728AD602F4DDCC08E76A210B0286EC15EC
+:1005900008E77B7C3D6B8103D008EF7D6136947C5E
+:1005A000A0DF08EFCC853BDAE05C1C08E7E375BB15
+:1005B00039224BA808EFF9CEE05EEB1DCB08E7BD72
+:1005C000E270D5AB4E3F08E7B78D20686B09520843
+:1005D000EFA11B90CD98006308EF54675D9C11FC60
+:1005E0004508E7D49BC897BE8A0708EF528D9063F1
+:1005F00073D52A08EF03BC6E1C76BE4A08E7C2ED2D
+:1006000067BA5E662108EFE73F87BEE07A6D08E7CC
+:10061000C970931D64F56C08EFF5280834B3B62C47
+:1006200008EF3A0AEC0FDB56CA08EF39A06EED79F5
+:10063000D02408E76C0BAFA94E40B508E9B9AFBFAD
+:100640002550D13708059EDBDE3F94E96B08ECC5E9
+:1006500005AA57DC8A5E080570DA8484DDCA900733
+:1006600002810001C9C3800813002021200000007E
+:1006700005110001005205110001032005111001B0
+:1006800004211011200C0003000702710005C9C3EA
+:10069000800000051120010C461011200C180100EB
+:1006A00008038000B0100CE8004E1011200C240646
+:1006B0008DB9000002C0080012002307112003308A
+:1006C000015CA00511200135E01011200C3811113A
+:1006D00011801A200000280CA423091120054503CD
+:1006E00000850100081120044B0609104006112066
+:1006F0000250940A061120025403070511200157E5
+:1007000000091120055B40040478201011210C0021
+:100710007E641BBA580BDDCED6E6F6001011210C14
+:100720000C030315F03F007E641BBA580B10112117
+:100730000C18DDCED6E6F600030315F03F000511D8
+:100740002201031D0B112307002C0E0B040C730355
+:100750000C11400800370900000AEC20FE083200A6
+:1007600000000000000005175610CAF0051713100E
+:10077000CAF0051100010100051100010320071155
+:10078000010300033301081102040004060A090DE5
+:1007900011100900101400FF31000000000A1111AF
+:1007A00006000A45D2CC00001011120C000401080A
+:1007B000FFFF2022002A015A301011120C0C4000B9
+:1007C000011680003F12000000001011120C1800EA
+:1007D00000000000000000000000001011120C24B6
+:1007E00000000000000000000000000009111205D8
+:1007F0003000000000000811120436000000001054
+:1008000011200C0005000736EE8009C9C3800018CE
+:10081000051120010C931011200C1805000803800D
+:1008200000002000E800531011200C240624DD06EF
+:100830002B02020000238C4A071120033000D3A0B2
+:100840000511200135E01011200C38111212001A88
+:10085000155500280CA4230E11200A450300F901A8
+:1008600000FF060218400611200250840A061120DB
+:1008700002540307051120015700091120055B40B0
+:10088000040778201011210C00CCA130A021D1B98F
+:10089000C9EA0512111011210C0C0A0415FC030001
+:1008A000CCA130A021D11011210C18B9C9EA051230
+:1008B000110A0415FC03000811220400087F001D22
+:1008C0000B1123070039040B050401031011300C30
+:1008D000000000000000000000000000000C1140BB
+:1008E0000800380AAAAA0AEC20FE00000000000056
+:1008F00000000000000000000000000000000000F8
+:1009000000080421714B0000DC950805A62221F0A7
+:10091000415B2608E22F1CBB0AA8942808058767BC
+:10092000E2581A075B08E1D072D88AB85B7D0805E7
+:1009300011EC9E28231B6D08E24F8AB2A9291413DB
+:100940000805D12E716A514C2C08E5802742A46914
+:10095000B07F0805AA812ABD45E8A808EAE4F0248A
+:10096000C99FCC3C080508F5050427629808EA6B86
+:100970006284A1F94AE20805E977054F84EE35085B
+:10098000E243C38DFBAD5425080514065E39362FAE
+:100990004508EA0C1C74D011FC320805DA38BA0E8E
+:1009A0003CE78B08EAB009E6FF94BBA90805D7111C
+:1009B00029FEDC71D508EA7F83A7609062180805DC
+:1009C000847F6AD191C65208EA2AD87B8E4A9F91C9
+:1009D0000805BDAA9D1618061508E255AD2D0A1486
+:1009E0001F5D0805D3E07C39CF01F008EF3A917222
+:1009F0006A03BB9608E7836DA492FC13A708EFF87F
+:100A0000FDCF62076F1E08E74CEA4A754FD6CF0844
+:100A1000E2F611E4260D4DC60805FBBFE80789C3C1
+:100A20005108EF8227043F96A85808E741293C75F2
+:100A30002A031C08EFAF599836AA0F0608E6F6936A
+:100A4000412DEC0E990805291990E5AA364008E7D2
+:100A5000FB68107D775DC008E7CBB4DDCE9054BE57
+:100A600008E7728AD602F4DDCC08E76A210B028619
+:100A7000EC1508E77B7C3D6B8103D008EF7D613688
+:100A8000947CA0DF08EFCC853BDAE05C1C08E7E350
+:100A900075BB39224BA808EFF9CEE05EEB1DCB0801
+:100AA000E7BDE270D5AB4E3F08E7B78D20686B0914
+:100AB0005208EFA11B90CD98006308EF54675D9C2E
+:100AC00011FC4508E7D49BC897BE8A0708EF528DF2
+:100AD000906373D52A08EF03BC6E1C76BE4A08E704
+:100AE000C2ED67BA5E662108EFE73F87BEE07A6D28
+:100AF00008E7C970931D64F56C08EFF5280834B356
+:100B0000B62C08EF3A0AEC0FDB56CA08EF39A06E94
+:100B1000ED79D02408E76C0BAFA94E40B508E9B9D0
+:100B2000AFBF2550D13708059EDBDE3F94E96B0847
+:100B3000ECC505AA57DC8A5E080570DA8484DDCA34
+:100B4000900702810001C9C3800813002021200002
+:100B500000000511000100520511000103200511DC
+:100B6000100104211011200C000300070271000580
+:100B7000C9C3800000051120010C461011200C187B
+:100B8000010008038000B0100CE8004E1011200C8A
+:100B900024068DB9000002C00800120023071120AE
+:100BA0000330015CA00511200135E01011200C3844
+:100BB000111111801A200000280CA423091120050E
+:100BC000450300850100081120044B06091040066A
+:100BD00011200250940A0611200254030705112027
+:100BE000015700091120055B4004047820101121F1
+:100BF0000C007E641BBA580BDDCED6E6F600101151
+:100C0000210C0C030315F03F007E641BBA580B1037
+:100C100011210C18DDCED6E6F600030315F03F00D7
+:100C200005112201031D0B112307002C0E0B040CD0
+:100C300073030C11400800370900000AEC20FE087D
+:100C4000320000000000000005175610CAF005171A
+:100C50001310CAF005110001010005110001032065
+:100C60000711010300033301081102040004060AFE
+:100C7000090D11100900101400EF31000000000AE6
+:100C8000111106000245D2CC00001011120C000414
+:100C90000108FFFF2002002A015A301011120C0C2B
+:100CA0004000010680003F02000000001011120CFD
+:100CB00018000000000000000000000000101112E9
+:100CC0000C240000000000000000000000000911DA
+:100CD0001205300000000000081112043600000068
+:100CE000001011200C000300072DC6C001C9C380ED
+:100CF0000028051120010CF61011200C1801000825
+:100D0000038000003000E800641011200C24051E50
+:100D1000B8051F02000000238A3E0711200330019E
+:100D20009AA00511200135E21011200C38220B0B7E
+:100D3000801A400000280CA4230E11200A4503004D
+:100D4000D00100FF080218400611200250840A0654
+:100D50001120025403070511200157000911200535
+:100D60005B40040678201011210C007E641BBA58E9
+:100D70000BDDCED6E6F6001011210C0C030315F0A6
+:100D80003F007E641BBA580B1011210C18DDCED623
+:100D9000E6F600030315F03F000811220400087F67
+:100DA000005D0B1123070001050B05020003101164
+:100DB000300C000000000000000000000000000CEB
+:100DC00011400800380AAAAA0AEC20FE0000000020
+:100DD0000000000000000000000000000000000013
+:100DE000000000080421714B0000DC950805A622D4
+:100DF00021F0415B2608E22F1CBB0AA894280805B5
+:100E00008767E2581A075B08E1D072D88AB85B7D21
+:100E1000080511EC9E28231B6D08E24F8AB2A92910
+:100E200014130805D12E716A514C2C08E580274215
+:100E3000A469B07F0805AA812ABD45E8A808EAE4AC
+:100E4000F024C99FCC3C080508F5050427629808E2
+:100E5000EA6B6284A1F94AE20805E977054F84EE5E
+:100E60003508E243C38DFBAD5425080514065E39F1
+:100E7000362F4508EA0C1C74D011FC320805DA380C
+:100E8000BA0E3CE78B08EAB009E6FF94BBA9080557
+:100E9000D71129FEDC71D508EA7F83A7609062181C
+:100EA0000805847F6AD191C65208EA2AD87B8E4A07
+:100EB0009F910805BDAA9D1618061508E255AD2D8F
+:100EC0000A141F5D0805D3E07C39CF01F008EF3A22
+:100ED00091726A03BB9608E7836DA492FC13A7087E
+:100EE000EFF8FDCF62076F1E08E74CEA4A754FD650
+:100EF000CF08E2F611E4260D4DC60805FBBFE80752
+:100F000089C35108EF8227043F96A85808E7412972
+:100F10003C752A031C08EFAF599836AA0F0608E65D
+:100F2000F693412DEC0E990805291990E5AA364053
+:100F300008E7FB68107D775DC008E7CBB4DDCE9095
+:100F400054BE08E7728AD602F4DDCC08E76A210BAA
+:100F50000286EC1508E77B7C3D6B8103D008EF7DB2
+:100F60006136947CA0DF08EFCC853BDAE05C1C089E
+:100F7000E7E375BB39224BA808EFF9CEE05EEB1D25
+:100F8000CB08E7BDE270D5AB4E3F08E7B78D2068D0
+:100F90006B095208EFA11B90CD98006308EF5467CE
+:100FA0005D9C11FC4508E7D49BC897BE8A0708EFF3
+:100FB000528D906373D52A08EF03BC6E1C76BE4A2F
+:100FC00008E7C2ED67BA5E662108EFE73F87BEE03B
+:100FD0007A6D08E7C970931D64F56C08EFF5280871
+:100FE00034B3B62C08EF3A0AEC0FDB56CA08EF39D7
+:100FF000A06EED79D02408E76C0BAFA94E40B50880
+:10100000E9B9AFBF2550D13708059EDBDE3F94E933
+:101010006B08ECC505AA57DC8A5E080570DA848483
+:10102000DDCA900702810001C9C380081300202196
+:1010300020000000051100010052051100010320ED
+:101040000511100104211011200C0003000702718A
+:101050000005C9C3800000051120010C46101120B5
+:101060000C18010008038000B0100CE8004E1011AD
+:10107000200C24068DB9000002C0080012002307CE
+:1010800011200330015CA00511200135E010112072
+:101090000C38111111801A200000280CA42309110A
+:1010A0002005450300850100081120044B060910A6
+:1010B000400611200250940A06112002540307052D
+:1010C0001120015700091120055B4004047820100D
+:1010D00011210C007E641BBA580BDDCED6E6F6005B
+:1010E0001011210C0C030315F03F007E641BBA584D
+:1010F0000B1011210C18DDCED6E6F600030315F017
+:101100003F0005112201031D0B112307002C0E0BBC
+:10111000040C73030C11400800370900000AEC208E
+:10112000FE08320000000000000005175610CAF04B
+:1011300005171310CAF00511000101000511000187
+:101140000320071101030003330108110204000406
+:10115000060A090D11100900101400FF31000000EB
+:10116000000A111106000A45D2CC00001011120C21
+:1011700000040108FFFF2022002A015A301011123A
+:101180000C0C4000011680003F12000000001011FE
+:10119000120C180000000000000000000000001009
+:1011A00011120C24000000000000000000000000EC
+:1011B0000911120530000000000008111204360069
+:1011C0000000001011200C000500072DC6C001C949
+:1011D000C3800028051120010CF61011200C180501
+:1011E0000008038000003000E800641011200C2487
+:1011F000051EB8051F02020000238A3E07112003C6
+:101200003001C3A00511200135E21011200C382255
+:101210000B0B001A155500280CA4230E11200A45AB
+:101220000300D00100FF080218400611200250847C
+:101230000A06112002540307051120015700091165
+:1012400020055B40040678201011210C00A28126A5
+:10125000AF3FEEC8C7DBF202081011210C0C0703E8
+:1012600015FC0F00A28126AF3FEE1011210C18C80B
+:10127000C7DBF20208070315FC0F00081122040067
+:10128000087F003D0B1123070001050B0502000339
+:101290001011300C000000000000000000000000F1
+:1012A000000C11400800380AAAAA0AEC20FE00002F
+:1012B000000000000000000000000000000000002E
+:1012C0000000000000080421714B0000DC950805B7
+:1012D000A62221F0415B2608E22F1CBB0AA8942815
+:1012E00008058767E2581A075B08E1D072D88AB808
+:1012F0005B7D080511EC9E28231B6D08E24F8AB226
+:10130000A92914130805D12E716A514C2C08E580C7
+:101310002742A469B07F0805AA812ABD45E8A8082C
+:10132000EAE4F024C99FCC3C080508F505042762CF
+:101330009808EA6B6284A1F94AE20805E977054F4B
+:1013400084EE3508E243C38DFBAD54250805140631
+:101350005E39362F4508EA0C1C74D011FC320805A2
+:10136000DA38BA0E3CE78B08EAB009E6FF94BBA96D
+:101370000805D71129FEDC71D508EA7F83A76090A4
+:1013800062180805847F6AD191C65208EA2AD87B80
+:101390008E4A9F910805BDAA9D1618061508E255AC
+:1013A000AD2D0A141F5D0805D3E07C39CF01F0088C
+:1013B000EF3A91726A03BB9608E7836DA492FC131F
+:1013C000A708EFF8FDCF62076F1E08E74CEA4A75E1
+:1013D0004FD6CF08E2F611E4260D4DC60805FBBF37
+:1013E000E80789C35108EF8227043F96A85808E709
+:1013F00041293C752A031C08EFAF599836AA0F06FD
+:1014000008E6F693412DEC0E990805291990E5AAF6
+:10141000364008E7FB68107D775DC008E7CBB4DD98
+:10142000CE9054BE08E7728AD602F4DDCC08E76A93
+:10143000210B0286EC1508E77B7C3D6B8103D0080D
+:10144000EF7D6136947CA0DF08EFCC853BDAE05C71
+:101450001C08E7E375BB39224BA808EFF9CEE05E24
+:10146000EB1DCB08E7BDE270D5AB4E3F08E7B78D6B
+:1014700020686B095208EFA11B90CD98006308EF1C
+:1014800054675D9C11FC4508E7D49BC897BE8A074A
+:1014900008EF528D906373D52A08EF03BC6E1C765B
+:1014A000BE4A08E7C2ED67BA5E662108EFE73F87EC
+:1014B000BEE07A6D08E7C970931D64F56C08EFF51E
+:1014C000280834B3B62C08EF3A0AEC0FDB56CA08EA
+:1014D000EF39A06EED79D02408E76C0BAFA94E4030
+:1014E000B508E9B9AFBF2550D13708059EDBDE3F0F
+:1014F00094E96B08ECC505AA57DC8A5E080570DA2A
+:101500008484DDCA900702810001C9C380081300EA
+:1015100020212000000005110001005205110001EA
+:1015200003200511100104211011200C00030007F5
+:1015300002710005C9C3800000051120010C46108E
+:1015400011200C18010008038000B0100CE8004EB8
+:101550001011200C24068DB9000002C008001200F2
+:10156000230711200330015CA00511200135E01094
+:1015700011200C38111111801A200000280CA4230E
+:1015800009112005450300850100081120044B06C0
+:101590000910400611200250940A0611200254033B
+:1015A00007051120015700091120055B400404784C
+:1015B000201011210C007E641BBA580BDDCED6E63C
+:1015C000F6001011210C0C030315F03F007E641B84
+:1015D000BA580B1011210C18DDCED6E6F600030325
+:1015E00015F03F0005112201031D0B112307002CEC
+:1015F0000E0B040C73030C11400800370900000A9D
+:10160000EC20FE0832000000000000000517561014
+:10161000CAF005171310CAF00511000101000511E9
+:101620000001032007110103000333010811020424
+:101630000004060A090D11100900101400FF310002
+:101640000000000A111106000245D2CC0000101162
+:10165000120C00040108FFFF2002002A015A30107A
+:1016600011120C0C4000010680003F020000000037
+:101670001011120C18000000000000000000000013
+:10168000001011120C2400000000000000000000F7
+:1016900000000911120530000000000008111204BA
+:1016A00036000000001011200C000300074C4B40D6
+:1016B00001C9C3800044051120010C441011200C05
+:1016C00018010008038000003000E8003C101120E1
+:1016D0000C2408888907FF02000000238FFF0711F0
+:1016E0002003300176A00511200135E21011200CF5
+:1016F00038220707801A400000270CA4230E11206F
+:101700000A4503015A0100FF080218400611200291
+:1017100050840A06112002540407051120015700C5
+:10172000091120055B40040A78201011210C00FFEC
+:10173000C4307FF5B5B8DE0517160C1011210C0C5E
+:10174000030015FF0000FFC4307FF5B51011210C18
+:1017500018B8DE0517160C030015FF00000811224B
+:101760000400087F005D0B1123070001050B050233
+:1017700000031011300C0000000000000000000009
+:101780000000000C11400800380AAAAA0AEC20FE4A
+:101790000000000000000000000000000000000049
+:1017A00000000000000000080421714B0000DC95DF
+:1017B0000805A62221F0415B2608E22F1CBB0AA8DF
+:1017C000942808058767E2581A075B08E1D072D8A9
+:1017D0008AB85B7D080511EC9E28231B6D08E24F3B
+:1017E0008AB2A92914130805D12E716A514C2C080C
+:1017F000E5802742A469B07F0805AA812ABD45E893
+:10180000A808EAE4F024C99FCC3C080508F50504C3
+:1018100027629808EA6B6284A1F94AE20805E97731
+:10182000054F84EE3508E243C38DFBAD5425080512
+:1018300014065E39362F4508EA0C1C74D011FC32B0
+:101840000805DA38BA0E3CE78B08EAB009E6FF94DF
+:10185000BBA90805D71129FEDC71D508EA7F83A74B
+:10186000609062180805847F6AD191C65208EA2AFE
+:10187000D87B8E4A9F910805BDAA9D1618061508AB
+:10188000E255AD2D0A141F5D0805D3E07C39CF0168
+:10189000F008EF3A91726A03BB9608E7836DA49251
+:1018A000FC13A708EFF8FDCF62076F1E08E74CEAAC
+:1018B0004A754FD6CF08E2F611E4260D4DC608054D
+:1018C000FBBFE80789C35108EF8227043F96A85859
+:1018D00008E741293C752A031C08EFAF599836AA3E
+:1018E0000F0608E6F693412DEC0E9908052919908C
+:1018F000E5AA364008E7FB68107D775DC008E7CBB6
+:10190000B4DDCE9054BE08E7728AD602F4DDCC086E
+:10191000E76A210B0286EC1508E77B7C3D6B8103AF
+:10192000D008EF7D6136947CA0DF08EFCC853BDAF0
+:10193000E05C1C08E7E375BB39224BA808EFF9CE41
+:10194000E05EEB1DCB08E7BDE270D5AB4E3F08E78C
+:10195000B78D20686B095208EFA11B90CD980063EA
+:1019600008EF54675D9C11FC4508E7D49BC897BEFF
+:101970008A0708EF528D906373D52A08EF03BC6E77
+:101980001C76BE4A08E7C2ED67BA5E662108EFE73B
+:101990003F87BEE07A6D08E7C970931D64F56C0857
+:1019A000EFF5280834B3B62C08EF3A0AEC0FDB56F3
+:1019B000CA08EF39A06EED79D02408E76C0BAFA907
+:1019C0004E40B508E9B9AFBF2550D13708059EDBB9
+:1019D000DE3F94E96B08ECC505AA57DC8A5E080572
+:1019E00070DA8484DDCA900702810001C9C38008CF
+:1019F00013002021200000000511000100520511F4
+:101A0000000103200511100104211011200C000316
+:101A1000000702710005C9C3800000051120010CF8
+:101A2000461011200C18010008038000B0100CE8CB
+:101A3000004E1011200C24068DB9000002C00800D1
+:101A40001200230711200330015CA005112001358D
+:101A5000E01011200C38111111801A200000280C00
+:101A6000A423091120054503008501000811200465
+:101A70004B060910400611200250940A061120025C
+:101A8000540307051120015700091120055B40048C
+:101A90000478201011210C007E641BBA580BDDCE97
+:101AA000D6E6F6001011210C0C030315F03F007E62
+:101AB000641BBA580B1011210C18DDCED6E6F600C7
+:101AC000030315F03F0005112201031D0B1123072D
+:101AD000002C0E0B040C73030C1140080037090096
+:101AE000000AEC20FE08320000000000000005178C
+:101AF0005610CAF005171310CAF0051100010100B5
+:101B0000051100010320071101030003330108112F
+:101B100002040004060A090D11100900101400FF48
+:101B200031000000000A111106000A45D2CC000065
+:101B30001011120C00040108FFFF2022002A015A94
+:101B4000301011120C0C4000011680003F120000F2
+:101B500000001011120C180000000000000000002E
+:101B60000000001011120C24000000000000000012
+:101B700000000000091112053000000000000811EB
+:101B8000120436000000001011200C000500074C64
+:101B90004B4001C9C3800044051120010C441011C1
+:101BA000200C18050008038000003000E8003C10FD
+:101BB00011200C2408888907FF02020000238FFFF0
+:101BC0000711200330017CA00511200135E210111E
+:101BD000200C38220707001A155500270CA4230EE5
+:101BE00011200A4503015A0100FF0802184006119E
+:101BF000200250840A061120025404070511200116
+:101C00005700091120055B40040A78201011210CAF
+:101C100000FFBA0F51CFA9C9FC1B1E0F01101121E3
+:101C20000C0CFCFD15FF000FFFBA0F51CFA91011CE
+:101C3000210C18C9FC1B1E0F01FCFD15FF000F082D
+:101C400011220400087F005D0B1123070001050B22
+:101C5000050200031011300C00000000000000001D
+:101C600000000000000C11400800380AAAAA0AEC83
+:101C700020FE000000000000000000000000000046
+:101C80000000000000000000001110010020000012
+:101C9000000000000103070F1F0000002E000405D4
+:101CA00006000000000000000000000000000065C9
+:101CB000727261736520736563746F723A25580D93
+:101CC0000A00777269746520737563636573730DB9
+:101CD0000A004552524F52203A206E6F74207965A7
+:101CE0007420636F6E666967757265640D0A000023
+:101CF00000000000000000000000000000000000E4
+:101D0000000000000118AF000000000001012CA835
+:101D100028AAFFFFFF0000000020010101010101CE
+:101D20002CA828AE2CA82841010000007F0000420A
+:101D300068000000002CA828FC070000000000003C
+:101D40000000000000000000000000000000000093
+:101D50000000000000000000000000000000000083
+:101D60000000000000000000000000000000000073
+:101D70000000000000000000000000000000000063
+:101D80000000000000000000000000000000000053
+:101D90000000000000000000000000000000000043
+:101DA0000000000000000000000000000000000033
+:101DB0000000000000000000000000000000000023
+:101DC0000000000000000000000000000000000013
+:101DD0000000000000000000000000000000000003
+:101DE00000000000000000000000000000000000F3
+:101DF0000000000D0A0D0A4E505220465720257350
+:101E00000D0A00636F6E6669672057495448206564
+:101E10007874205352414D0D0A00636F6E666967F6
+:101E200020574954484F55542065787420535241E7
+:101E30004D0D0A0053493434363320636F6E6669A2
+:101E400067757265640D0A00534934343633206572
+:101E500072726F72207768696C6520636F6E666955
+:101E6000677572650D0A00000000000000000000A8
+:101E700027E7000829E7000859EC000845EC0008AE
+:101E8000D0040020494E4600696E66004E414E0067
+:101E90006E616E0030313233343536373839414275
+:101EA0004344454600000000303132333435363784
+:101EB000383961626364656600000000286E756CE5
+:101EC0006C2900003000000020202020202020204D
+:101ED0002020202020202020303030303030303082
+:101EE000303030303030303065256C640000000018
+:101EF0000A000100020003000400050006000700BC
+:101F0000080009000A000B000C000D000E000F0075
+:101F10001000000020202020202020202020202031
+:101F200020202020303030303030303030303030F1
+:101F30003030303000202020202020202020282871
+:101F40002828282020202020202020202020202079
+:101F500020202020208810101010101010101010B9
+:101F600010101010100404040404040404040410E9
+:101F70001010101010104141414141410101010177
+:101F80000101010101010101010101010101010141
+:101F9000101010101010424242424242020202024D
+:101FA0000202020202020202020202020202020211
+:101FB00010101010200000000000000000000000C1
+:101FC0000000000000000000000000000000000011
+:101FD0000000000000000000000000000000000001
+:101FE00000000000000000000000000000000000F1
+:101FF00000000000000000000000000000000000E1
+:1020000000000000000000000000000000000000D0
+:1020100000000000000000000000000000000000C0
+:1020200000000000000000000000000000000000B0
+:1020300000000000000000004E614E00496E66691D
+:102040006E6974790000000042616C6C6F632073EC
+:102050007563636565646564000000002E2E2F2E95
+:102060002E2F2E2E2F2E2E2F2E2E2F2E2E2F2E2E8B
+:102070002F2E2E2F6E65776C69622F6C6962632F2D
+:102080007374646C69622F64746F612E6300000066
+:1020900043000000504F5349580000002E0000003C
+:1020A0002E2E2F2E2E2F2E2E2F2E2E2F2E2E2F2E4B
+:1020B0002E2F2E2E2F2E2E2F6E65776C69622F6C91
+:1020C0006962632F7374646C69622F6D70726563EB
+:1020D0002E63000000000000050000001900000051
+:1020E0007D00000000000000000000000000F03F44
+:1020F00000000000000024400000000000005940E3
+:102100000000000000408F40000000000088C34035
+:1021100000000000006AF8400000000080842E41AA
+:1021200000000000D01263410000000084D79741F6
+:102130000000000065CDCD41000000205FA00242FC
+:10214000000000E876483742000000A2941A6D4271
+:10215000000040E59C30A2420000901EC4BCD64264
+:1021600000003426F56B0C430080E03779C341430F
+:1021700000A0D8855734764300C84E676DC1AB4385
+:10218000003D9160E458E143408CB5781DAF1544A3
+:1021900050EFE2D6E41A4B4492D54D06CFF080447E
+:1021A000F64AE1C7022DB544B49DD9794378EA4493
+:1021B000BC89D897B2D29C3C33A7A8D523F649391D
+:1021C0003DA7F444FD0FA5329D978CCF08BA5B253F
+:1021D000436FAC642806C80A0080E03779C34143E6
+:1021E000176E05B5B5B89346F5F93FE9034F384D7D
+:1021F000321D30F94877825A3CBF737FDD4F157529
+:102200006E660000696E697479000000616E0000FE
+:1022100035000000CEFBFFFFCB03000001000000F3
+:102220000000000034000000CEFBFFFFCB030000E5
+:102230000100000000000000BC89D897B2D29C3C8D
+:1022400033A7A8D523F649393DA7F444FD0FA5329D
+:102250009D978CCF08BA5B25436FAC642806681144
+:10226000202020202020202020202020202020206E
+:10227000303030303030303030303030303030305E
+:102280000A00010002000300040005000600070028
+:10229000080009000A000B000C000D000E000F00E2
+:1022A000100000002020202020202020202020209E
+:1022B000202020203030303030303030303030305E
+:1022C000303030302C2066756E6374696F6E3A2042
+:1022D00000000000617373657274696F6E202225BF
+:1022E0007322206661696C65643A2066696C6520BA
+:1022F000222573222C206C696E65202564257325A8
+:10230000730A00002E2E2F2E2E2F2E2E2F2E2E2F24
+:102310002E2E2F2E2E2F2E2E2F2E2E2F6E65776CDB
+:1023200069622F6C6962632F7374646C69622F67D2
+:1023300064746F612D6765746865782E63000000B2
+:10234000000000000000000000000000000000008D
+:10235000000000000000000000000000000000007D
+:10236000000000000000000000000000000000006D
+:102370001011121314151617181900000000000090
+:10238000001A1B1C1D1E1F000000000000000000A2
+:10239000000000000000000000000000000000003D
+:1023A000001A1B1C1D1E1F00000000000000000082
+:1023B000000000000000000000000000000000001D
+:1023C000000000000000000000000000000000000D
+:1023D00000000000000000000000000000000000FD
+:1023E00000000000000000000000000000000000ED
+:1023F00000000000000000000000000000000000DD
+:1024000000000000000000000000000000000000CC
+:1024100000000000000000000000000000000000BC
+:1024200000000000000000000000000000000000AC
+:10243000000000000000000000000000000000009C
+:102440009C200208D0220208740E00200000000028
+:08245000C4DDFD7F0100000066
+:102458000000000004E600205B21000800000000E6
+:1024680080DC01089117FB0200000000000000005A
+:102478000000000000000000000000000000000054
+:102488000000000000000000000000000000000044
+:102498000000000000000000000000000000000034
+:1024A8000000000000000000000000000000000024
+:1024B8000000000000000000000000000000000014
+:1024C8000000000000000000000000000000000004
+:1024D80000000000000000000000000000000000F4
+:1024E80000000000000000000000000000000000E4
+:1024F80000000000000000000000000000000000D4
+:1025080000000000000000000000000000000000C3
+:1025180000093D006E6F0000796573006E6F000062
+:1025280000646F776E007570000000000100000005
+:1025380077616974696E6720636F6E6E656374692D
+:102548006F6E00000000636F6E6E656374656400F3
+:10255800000000000000000000000000636F6E6EC5
+:10256800656374696F6E2072656A6563746564007B
+:1025780000004950207265717565737465640000C8
+:1025880000636C69656E7473000000000000000051
+:102598000300000000000200000000002C01000001
+:1025A8003200000000080808000000003100500058
+:1025B800000000000000000002000000070000000A
+:1025C800D0070000E8FD0000200D00002C010000ED
+:1025D800F40100001E000000BC020000080000001A
+:1025E80006040000E80300004E0200007F0000001F
+:1025F80080C3C901809698003809000001000000D6
+:102608000100000001FE000080BB00000100000185
+:1026180000010100000101000100000100010100AA
+:10262800010000010100000100010100000101009A
+:10263800010000010100000100010100010000018A
+:10264800000101000001010001000001000101007A
+:10265800010000010100000100010100010000016A
+:10266800000101000001010001000001010000015A
+:10267800000101000001010001000001000101004A
+:10268800010000010100000100010100000101003A
+:10269800010000010100000100010100010000012A
+:1026A800000101000001010001000001010000011A
+:1026B800000101000001010001000001000101000A
+:1026C80001000001010000010001010001000001FA
+:1026D80000010100000101000100000100010100EA
+:1026E80001000001010000010001010000010100DA
+:1026F80001000001010000010001010001000001CA
+:1027080000010100000101000100000100808000BB
+:1027180080000080800000800080800080000080B1
+:1027280000808000008080008000008080000080A1
+:102738000080800000808000800000800080800091
+:102748008000008080000080008080008000008081
+:102758000080800000808000800000800080800071
+:102768008000008080000080008080000080800061
+:102778008000008080000080008080008000008051
+:10278800008080000080800080000080C8AF0000CA
+:10279800D00400200000000000000000BC0700205A
+:1027A800240800208C080020000000000000000021
+:1027B8000000000000000000000000000000000011
+:1027C8000000000000000000000000000000000001
+:1027D80000000000000000000000000000000000F1
+:1027E80000000000000000000000000000000000E1
+:1027F80000000000000000000000000000000000D1
+:1028080000000000000000000000000000000000C0
+:1028180000000000000000000000000000000000B0
+:1028280000000000000000000000000000000000A0
+:102838000000000000000000000000000000000090
+:1028480001000000000000000E33CDAB34126DE62D
+:10285800ECDE05000B000000000000000000000096
+:102868000000000000000000000000000000000060
+:102878000000000000000000000000000000000050
+:102888000000000000000000000000000000000040
+:102898000000000000000000000000000000000030
+:1028A8000000000000000000000000000000000020
+:1028B8000000000000000000000000000000000010
+:1028C8000000000000000000000000000000000000
+:1028D80000000000000000000000000000000000F0
+:1028E80000000000000000000000000000000000E0
+:1028F80000000000000000000000000000000000D0
+:1029080000000000000000000000000000000000BF
+:1029180000000000000000000000000000000000AF
+:10292800000000000000000000000000000000009F
+:10293800000000000000000000000000000000008F
+:10294800000000000000000000000000000000007F
+:10295800000000000000000000000000000000006F
+:10296800000000000000000000000000000000005F
+:10297800000000000000000000000000000000004F
+:10298800000000000000000000000000000000003F
+:10299800000000000000000000000000000000002F
+:1029A800000000000000000000000000000000001F
+:1029B800000000000000000000000000000000000F
+:1029C80000000000000000000000000000000000FF
+:1029D80000000000000000000000000000000000EF
+:1029E80000000000000000000000000000000000DF
+:1029F80000000000000000000000000000000000CF
+:102A080000000000000000000000000000000000BE
+:102A180000000000000000000000000000000000AE
+:102A2800000000000000000000000000000000009E
+:102A3800000000000000000000000000000000008E
+:102A4800000000000000000000000000000000007E
+:102A5800000000000000000000000000000000006E
+:102A6800000000000000000000000000000000005E
+:102A7800000000000000000000000000000000004E
+:102A8800000000000000000000000000000000003E
+:102A9800000000000000000000000000000000002E
+:102AA800000000000000000000000000000000001E
+:102AB800000000000000000000000000000000000E
+:102AC80000000000000000000000000000000000FE
+:102AD80000000000000000000000000000000000EE
+:102AE80000000000000000000000000000000000DE
+:102AF80000000000000000000000000000000000CE
+:102B080000000000000000000000000000000000BD
+:102B180000000000000000000000000000000000AD
+:102B2800000000000000000000000000000000009D
+:102B3800000000000000000000000000000000008D
+:102B4800000000000000000000000000000000007D
+:102B5800000000000000000000000000000000006D
+:102B6800000000000000000000000000000000005D
+:102B7800000000000000000000000000000000004D
+:102B8800000000000000000000000000000000003D
+:102B9800000000000000000000000000000000002D
+:102BA800000000000000000000000000000000001D
+:102BB800000000000000000000000000000000000D
+:102BC8000000000000000000F8080020F8080020BD
+:102BD8000009002000090020080900200809002039
+:102BE80010090020100900201809002018090020E9
+:102BF8002009002020090020280900202809002099
+:102C08003009002030090020380900203809002048
+:102C180040090020400900204809002048090020F8
+:102C280050090020500900205809002058090020A8
+:102C38006009002060090020680900206809002058
+:102C48007009002070090020780900207809002008
+:102C580080090020800900208809002088090020B8
+:102C68009009002090090020980900209809002068
+:102C7800A0090020A0090020A8090020A809002018
+:102C8800B0090020B0090020B8090020B8090020C8
+:102C9800C0090020C0090020C8090020C809002078
+:102CA800D0090020D0090020D8090020D809002028
+:102CB800E0090020E0090020E8090020E8090020D8
+:102CC800F0090020F0090020F8090020F809002088
+:102CD800000A0020000A0020080A0020080A002034
+:102CE800100A0020100A0020180A0020180A0020E4
+:102CF800200A0020200A0020280A0020280A002094
+:102D0800300A0020300A0020380A0020380A002043
+:102D1800400A0020400A0020480A0020480A0020F3
+:102D2800500A0020500A0020580A0020580A0020A3
+:102D3800600A0020600A0020680A0020680A002053
+:102D4800700A0020700A0020780A0020780A002003
+:102D5800800A0020800A0020880A0020880A0020B3
+:102D6800900A0020900A0020980A0020980A002063
+:102D7800A00A0020A00A0020A80A0020A80A002013
+:102D8800B00A0020B00A0020B80A0020B80A0020C3
+:102D9800C00A0020C00A0020C80A0020C80A002073
+:102DA800D00A0020D00A0020D80A0020D80A002023
+:102DB800E00A0020E00A0020E80A0020E80A0020D3
+:102DC800F00A0020F00A0020F80A0020F80A002083
+:102DD800000B0020000B0020080B0020080B00202F
+:102DE800100B0020100B0020180B0020180B0020DF
+:102DF800200B0020200B0020280B0020280B00208F
+:102E0800300B0020300B0020380B0020380B00203E
+:102E1800400B0020400B0020480B0020480B0020EE
+:102E2800500B0020500B0020580B0020580B00209E
+:102E3800600B0020600B0020680B0020680B00204E
+:102E4800700B0020700B0020780B0020780B0020FE
+:102E5800800B0020800B0020880B0020880B0020AE
+:102E6800900B0020900B0020980B0020980B00205E
+:102E7800A00B0020A00B0020A80B0020A80B00200E
+:102E8800B00B0020B00B0020B80B0020B80B0020BE
+:102E9800C00B0020C00B0020C80B0020C80B00206E
+:102EA800D00B0020D00B0020D80B0020D80B00201E
+:102EB800E00B0020E00B0020E80B0020E80B0020CE
+:102EC800F00B0020F00B0020F80B0020F80B00207E
+:102ED800000C0020000C0020080C0020080C00202A
+:102EE800100C0020100C0020180C0020180C0020DA
+:102EF800200C0020200C0020280C0020280C00208A
+:102F0800300C0020300C0020380C0020380C002039
+:102F1800400C0020400C0020480C0020480C0020E9
+:102F2800500C0020500C0020580C0020580C002099
+:102F3800600C0020600C0020680C0020680C002049
+:102F4800700C0020700C0020780C0020780C0020F9
+:102F5800800C0020800C0020880C0020880C0020A9
+:102F6800900C0020900C0020980C0020980C002059
+:102F7800A00C0020A00C0020A80C0020A80C002009
+:102F8800B00C0020B00C0020B80C0020B80C0020B9
+:102F9800C00C0020C00C0020C80C0020C80C002069
+:102FA800D00C0020D00C0020D80C0020D80C002019
+:102FB800E00C0020E00C0020E80C0020E80C0020C9
+:102FC800F00C0020F00C0020FFFFFFFF00000200C3
+:102FD80043000000000000000000000000000000A6
+:102FE80000000000000000000000000000000000D9
+:102FF8004300000000000000000000000000000086
+:1030080000000000000000000000000000000000B8
+:103018004300000000000000000000000000000065
+:103028000000000000000000000000000000000098
+:103038004300000000000000000000000000000045
+:103048000000000000000000000000000000000078
+:103058004300000000000000000000000000000025
+:103068000000000000000000000000000000000058
+:103078004300000000000000000000000000000005
+:103088000000000000000000000000000000000038
+:1030980043000000000000000000000000000000E5
+:1030A8000000000000000000000000000000000018
+:1030B80069BA0108F570010800000000341F020811
+:1030C8009C200208D0220208D0220208D02202083E
+:1030D800D0220208D0220208D0220208D0220208F8
+:1030E800D0220208D0220208FFFFFFFFFFFFFFFFE8
+:1030F800FFFFFFFFFFFF0000010041534349490064
+:1031080000000000000000000000000000000000B7
+:10311800000000000000000000004153434949003E
+:103128000000000000000000000000000000000097
+:10313800000000000000000000000000FF00000088
+:10314800F50100081509000815CE00088DE60008ED
+:0831580071EC0008CD01000834
+:0400000508003EFDB4
+:00000001FF
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.link_script.ld b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.link_script.ld
new file mode 100755
index 0000000..bbdc41f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/NPR_14.link_script.ld
@@ -0,0 +1,92 @@
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+  SRAM1 (rwx) : ORIGIN = 0x20000188, LENGTH = 64k - 0x188
+}
+ENTRY(Reset_Handler)
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+        *(.rodata*)
+        KEEP(*(.eh_frame*))
+    } > FLASH
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+    __etext = .;
+    _sidata = .;
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+        . = ALIGN(4);
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+        . = ALIGN(4);
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+        . = ALIGN(4);
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        __data_end__ = .;
+        _edata = .;
+    } > SRAM1
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > SRAM1
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > SRAM1
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM1
+    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/AnalogIn.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/AnalogIn.d
new file mode 100755
index 0000000..2d807d9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/AnalogIn.d
@@ -0,0 +1,109 @@
+mbed-os/drivers/AnalogIn.o: ../mbed-os/drivers/AnalogIn.cpp \
+ ../mbed_config.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/AnalogIn.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/AnalogIn.o
new file mode 100755
index 0000000..f9eb481
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/AnalogIn.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusIn.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusIn.d
new file mode 100755
index 0000000..b56bf2f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusIn.d
@@ -0,0 +1,110 @@
+mbed-os/drivers/BusIn.o: ../mbed-os/drivers/BusIn.cpp ../mbed_config.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/mbed_assert.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusIn.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusIn.o
new file mode 100755
index 0000000..438bcd2
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusIn.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusInOut.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusInOut.d
new file mode 100755
index 0000000..0298a8c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusInOut.d
@@ -0,0 +1,110 @@
+mbed-os/drivers/BusInOut.o: ../mbed-os/drivers/BusInOut.cpp \
+ ../mbed_config.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/mbed_assert.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusInOut.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusInOut.o
new file mode 100755
index 0000000..6313c46
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusInOut.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusOut.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusOut.d
new file mode 100755
index 0000000..a3e8197
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusOut.d
@@ -0,0 +1,109 @@
+mbed-os/drivers/BusOut.o: ../mbed-os/drivers/BusOut.cpp ../mbed_config.h \
+ .././mbed-os/drivers/BusOut.h .././mbed-os/drivers/DigitalOut.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/mbed_assert.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusOut.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusOut.o
new file mode 100755
index 0000000..9908b10
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/BusOut.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/CAN.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/CAN.d
new file mode 100755
index 0000000..ab6b686
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/CAN.d
@@ -0,0 +1,111 @@
+mbed-os/drivers/CAN.o: ../mbed-os/drivers/CAN.cpp ../mbed_config.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/CAN.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/CAN.o
new file mode 100755
index 0000000..892c2ab
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/CAN.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ethernet.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ethernet.d
new file mode 100755
index 0000000..f357419
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ethernet.d
@@ -0,0 +1,90 @@
+mbed-os/drivers/Ethernet.o: ../mbed-os/drivers/Ethernet.cpp \
+ ../mbed_config.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/NonCopyable.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ethernet.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ethernet.o
new file mode 100755
index 0000000..b629f2e
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ethernet.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/FlashIAP.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/FlashIAP.d
new file mode 100755
index 0000000..66fe7b7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/FlashIAP.d
@@ -0,0 +1,107 @@
+mbed-os/drivers/FlashIAP.o: ../mbed-os/drivers/FlashIAP.cpp \
+ ../mbed_config.h ../mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/SingletonPtr.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/FlashIAP.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/FlashIAP.o
new file mode 100755
index 0000000..7019f9e
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/FlashIAP.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2C.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2C.d
new file mode 100755
index 0000000..1317f64
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2C.d
@@ -0,0 +1,112 @@
+mbed-os/drivers/I2C.o: ../mbed-os/drivers/I2C.cpp ../mbed_config.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/platform/SingletonPtr.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/CThunk.h .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_toolchain.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2C.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2C.o
new file mode 100755
index 0000000..f0084f8
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2C.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2CSlave.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2CSlave.d
new file mode 100755
index 0000000..24e33d6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2CSlave.d
@@ -0,0 +1,90 @@
+mbed-os/drivers/I2CSlave.o: ../mbed-os/drivers/I2CSlave.cpp \
+ ../mbed_config.h .././mbed-os/drivers/I2CSlave.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/dma_api.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2CSlave.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2CSlave.o
new file mode 100755
index 0000000..028d267
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/I2CSlave.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptIn.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptIn.d
new file mode 100755
index 0000000..75acb6a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptIn.d
@@ -0,0 +1,93 @@
+mbed-os/drivers/InterruptIn.o: ../mbed-os/drivers/InterruptIn.cpp \
+ ../mbed_config.h .././mbed-os/drivers/InterruptIn.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/hal/gpio_irq_api.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/NonCopyable.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptIn.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptIn.o
new file mode 100755
index 0000000..fcecbe8
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptIn.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptManager.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptManager.d
new file mode 100755
index 0000000..0985759
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptManager.d
@@ -0,0 +1,100 @@
+mbed-os/drivers/InterruptManager.o: \
+ ../mbed-os/drivers/InterruptManager.cpp ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/drivers/InterruptManager.h \
+ .././mbed-os/platform/CallChain.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptManager.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptManager.o
new file mode 100755
index 0000000..70beb90
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/InterruptManager.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/RawSerial.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/RawSerial.d
new file mode 100755
index 0000000..a297da0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/RawSerial.d
@@ -0,0 +1,95 @@
+mbed-os/drivers/RawSerial.o: ../mbed-os/drivers/RawSerial.cpp \
+ ../mbed_config.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/platform/mbed_wait_api.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/RawSerial.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/RawSerial.o
new file mode 100755
index 0000000..f3ae4ba
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/RawSerial.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPI.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPI.d
new file mode 100755
index 0000000..a0db269
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPI.d
@@ -0,0 +1,115 @@
+mbed-os/drivers/SPI.o: ../mbed-os/drivers/SPI.cpp ../mbed_config.h \
+ .././mbed-os/drivers/SPI.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/FunctionPointer.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_toolchain.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPI.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPI.o
new file mode 100755
index 0000000..968d249
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPI.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPISlave.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPISlave.d
new file mode 100755
index 0000000..67131c1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPISlave.d
@@ -0,0 +1,91 @@
+mbed-os/drivers/SPISlave.o: ../mbed-os/drivers/SPISlave.cpp \
+ ../mbed_config.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/hal/spi_api.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/hal/buffer.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPISlave.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPISlave.o
new file mode 100755
index 0000000..bec9605
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SPISlave.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Serial.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Serial.d
new file mode 100755
index 0000000..159402a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Serial.d
@@ -0,0 +1,117 @@
+mbed-os/drivers/Serial.o: ../mbed-os/drivers/Serial.cpp ../mbed_config.h \
+ .././mbed-os/drivers/Serial.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/FileHandle.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_poll.h .././mbed-os/drivers/SerialBase.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/mbed_wait_api.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Serial.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Serial.o
new file mode 100755
index 0000000..94af54b
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Serial.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SerialBase.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SerialBase.d
new file mode 100755
index 0000000..891c9c8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SerialBase.d
@@ -0,0 +1,96 @@
+mbed-os/drivers/SerialBase.o: ../mbed-os/drivers/SerialBase.cpp \
+ ../mbed_config.h .././mbed-os/drivers/SerialBase.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/platform/mbed_critical.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_toolchain.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SerialBase.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SerialBase.o
new file mode 100755
index 0000000..f527bce
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/SerialBase.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ticker.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ticker.d
new file mode 100755
index 0000000..9b533cf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ticker.d
@@ -0,0 +1,95 @@
+mbed-os/drivers/Ticker.o: ../mbed-os/drivers/Ticker.cpp ../mbed_config.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/TimerEvent.h \
+ .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/us_ticker_api.h .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/hal/lp_ticker_api.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/FunctionPointer.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ticker.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ticker.o
new file mode 100755
index 0000000..1858e04
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Ticker.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timeout.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timeout.d
new file mode 100755
index 0000000..cc32a3e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timeout.d
@@ -0,0 +1,95 @@
+mbed-os/drivers/Timeout.o: ../mbed-os/drivers/Timeout.cpp \
+ ../mbed_config.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/TimerEvent.h \
+ .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/us_ticker_api.h .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/hal/lp_ticker_api.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timeout.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timeout.o
new file mode 100755
index 0000000..084a17b
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timeout.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timer.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timer.d
new file mode 100755
index 0000000..120637d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timer.d
@@ -0,0 +1,93 @@
+mbed-os/drivers/Timer.o: ../mbed-os/drivers/Timer.cpp ../mbed_config.h \
+ .././mbed-os/drivers/Timer.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/platform/mbed_critical.h .././mbed-os/hal/lp_ticker_api.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timer.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timer.o
new file mode 100755
index 0000000..fda63ff
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/Timer.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/TimerEvent.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/TimerEvent.d
new file mode 100755
index 0000000..44148a5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/TimerEvent.d
@@ -0,0 +1,89 @@
+mbed-os/drivers/TimerEvent.o: ../mbed-os/drivers/TimerEvent.cpp \
+ ../mbed_config.h .././mbed-os/drivers/TimerEvent.h \
+ .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/us_ticker_api.h .././mbed-os/platform/NonCopyable.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/TimerEvent.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/TimerEvent.o
new file mode 100755
index 0000000..2bbcf2c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/TimerEvent.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/UARTSerial.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/UARTSerial.d
new file mode 100755
index 0000000..f0f3e4f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/UARTSerial.d
@@ -0,0 +1,116 @@
+mbed-os/drivers/UARTSerial.o: ../mbed-os/drivers/UARTSerial.cpp \
+ ../mbed_config.h ../mbed-os/drivers/UARTSerial.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/FileHandle.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/NonCopyable.h ../mbed-os/drivers/SerialBase.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/platform/mbed_toolchain.h ../mbed-os/drivers/InterruptIn.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/Semaphore.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/UARTSerial.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/UARTSerial.o
new file mode 100755
index 0000000..3fd7d15
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/drivers/UARTSerial.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/EventQueue.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/EventQueue.d
new file mode 100755
index 0000000..75ae089
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/EventQueue.d
@@ -0,0 +1,173 @@
+mbed-os/events/EventQueue.o: ../mbed-os/events/EventQueue.cpp \
+ ../mbed_config.h .././mbed-os/events/EventQueue.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/Event.h .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/Semaphore.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/RtosTimer.h .././mbed-os/rtos/Mail.h \
+ .././mbed-os/rtos/Queue.h .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/Queue.h .././mbed-os/rtos/EventFlags.h \
+ .././mbed-os/events/mbed_events.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/EventQueue.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/EventQueue.o
new file mode 100755
index 0000000..3b8580f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/EventQueue.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue.d
new file mode 100755
index 0000000..8d0cd52
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue.d
@@ -0,0 +1,90 @@
+mbed-os/events/equeue/equeue.o: ../mbed-os/events/equeue/equeue.c \
+ ../mbed_config.h .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue.o
new file mode 100755
index 0000000..85030c4
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_mbed.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_mbed.d
new file mode 100755
index 0000000..369476b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_mbed.d
@@ -0,0 +1,173 @@
+mbed-os/events/equeue/equeue_mbed.o: \
+ ../mbed-os/events/equeue/equeue_mbed.cpp ../mbed_config.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h .././mbed-os/mbed.h \
+ .././mbed-os/rtos/rtos.h .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h .././mbed-os/events/EventQueue.h \
+ .././mbed-os/events/Event.h .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_mbed.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_mbed.o
new file mode 100755
index 0000000..16e2c0c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_mbed.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_posix.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_posix.d
new file mode 100755
index 0000000..30d1808
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_posix.d
@@ -0,0 +1,90 @@
+mbed-os/events/equeue/equeue_posix.o: \
+ ../mbed-os/events/equeue/equeue_posix.c ../mbed_config.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_posix.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_posix.o
new file mode 100755
index 0000000..ba67f78
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/equeue/equeue_posix.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/mbed_shared_queues.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/mbed_shared_queues.d
new file mode 100755
index 0000000..f592b98
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/mbed_shared_queues.d
@@ -0,0 +1,174 @@
+mbed-os/events/mbed_shared_queues.o: \
+ ../mbed-os/events/mbed_shared_queues.cpp ../mbed_config.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/mbed.h \
+ .././mbed-os/rtos/rtos.h .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/Semaphore.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/RtosTimer.h .././mbed-os/rtos/Mail.h \
+ .././mbed-os/rtos/Queue.h .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/Queue.h .././mbed-os/rtos/EventFlags.h \
+ .././mbed-os/events/mbed_events.h .././mbed-os/events/Event.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/mbed_shared_queues.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/mbed_shared_queues.o
new file mode 100755
index 0000000..5700399
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/events/mbed_shared_queues.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_flash_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_flash_api.d
new file mode 100755
index 0000000..38a3457
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_flash_api.d
@@ -0,0 +1,88 @@
+mbed-os/hal/mbed_flash_api.o: ../mbed-os/hal/mbed_flash_api.c \
+ ../mbed_config.h .././mbed-os/hal/flash_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_toolchain.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_flash_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_flash_api.o
new file mode 100755
index 0000000..2ae8d96
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_flash_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_gpio.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_gpio.d
new file mode 100755
index 0000000..5d314b2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_gpio.d
@@ -0,0 +1,87 @@
+mbed-os/hal/mbed_gpio.o: ../mbed-os/hal/mbed_gpio.c ../mbed_config.h \
+ .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_gpio.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_gpio.o
new file mode 100755
index 0000000..180f40a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_gpio.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_lp_ticker_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_lp_ticker_api.d
new file mode 100755
index 0000000..8e85613
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_lp_ticker_api.d
@@ -0,0 +1,88 @@
+mbed-os/hal/mbed_lp_ticker_api.o: ../mbed-os/hal/mbed_lp_ticker_api.c \
+ ../mbed_config.h .././mbed-os/hal/lp_ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/ticker_api.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_lp_ticker_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_lp_ticker_api.o
new file mode 100755
index 0000000..286a257
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_lp_ticker_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_pinmap_common.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_pinmap_common.d
new file mode 100755
index 0000000..354baec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_pinmap_common.d
@@ -0,0 +1,79 @@
+mbed-os/hal/mbed_pinmap_common.o: ../mbed-os/hal/mbed_pinmap_common.c \
+ ../mbed_config.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/platform/mbed_error.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_pinmap_common.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_pinmap_common.o
new file mode 100755
index 0000000..481698a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_pinmap_common.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_sleep_manager.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_sleep_manager.d
new file mode 100755
index 0000000..5a9ace6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_sleep_manager.d
@@ -0,0 +1,91 @@
+mbed-os/hal/mbed_sleep_manager.o: ../mbed-os/hal/mbed_sleep_manager.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_critical.h ../mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_error.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_sleep_manager.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_sleep_manager.o
new file mode 100755
index 0000000..4a679ec
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_sleep_manager.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_ticker_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_ticker_api.d
new file mode 100755
index 0000000..10af6c2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_ticker_api.d
@@ -0,0 +1,88 @@
+mbed-os/hal/mbed_ticker_api.o: ../mbed-os/hal/mbed_ticker_api.c \
+ ../mbed_config.h .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_ticker_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_ticker_api.o
new file mode 100755
index 0000000..213c889
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_ticker_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_us_ticker_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_us_ticker_api.d
new file mode 100755
index 0000000..71755e0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_us_ticker_api.d
@@ -0,0 +1,88 @@
+mbed-os/hal/mbed_us_ticker_api.o: ../mbed-os/hal/mbed_us_ticker_api.c \
+ ../mbed_config.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_us_ticker_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_us_ticker_api.o
new file mode 100755
index 0000000..cd36041
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/hal/mbed_us_ticker_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/ATCmdParser.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/ATCmdParser.d
new file mode 100755
index 0000000..c3f7837
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/ATCmdParser.d
@@ -0,0 +1,176 @@
+mbed-os/platform/ATCmdParser.o: ../mbed-os/platform/ATCmdParser.cpp \
+ ../mbed_config.h ../mbed-os/platform/ATCmdParser.h .././mbed-os/mbed.h \
+ .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../mbed-os/platform/Callback.h \
+ ../mbed-os/platform/mbed_poll.h ../mbed-os/platform/mbed_debug.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/ATCmdParser.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/ATCmdParser.o
new file mode 100755
index 0000000..e69e46e
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/ATCmdParser.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/CallChain.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/CallChain.d
new file mode 100755
index 0000000..e7b031e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/CallChain.d
@@ -0,0 +1,81 @@
+mbed-os/platform/CallChain.o: ../mbed-os/platform/CallChain.cpp \
+ ../mbed_config.h .././mbed-os/platform/CallChain.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/CallChain.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/CallChain.o
new file mode 100755
index 0000000..d431dc6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/CallChain.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileBase.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileBase.d
new file mode 100755
index 0000000..72b4ecb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileBase.d
@@ -0,0 +1,110 @@
+mbed-os/platform/FileBase.o: ../mbed-os/platform/FileBase.cpp \
+ ../mbed_config.h .././mbed-os/platform/FileBase.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/SingletonPtr.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/FileLike.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileBase.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileBase.o
new file mode 100755
index 0000000..91cd366
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileBase.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileHandle.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileHandle.d
new file mode 100755
index 0000000..a5ed1bd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileHandle.d
@@ -0,0 +1,92 @@
+mbed-os/platform/FileHandle.o: ../mbed-os/platform/FileHandle.cpp \
+ ../mbed_config.h ../mbed-os/platform/FileHandle.h \
+ ../mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileHandle.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileHandle.o
new file mode 100755
index 0000000..e741c96
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileHandle.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FilePath.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FilePath.d
new file mode 100755
index 0000000..8c22564
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FilePath.d
@@ -0,0 +1,114 @@
+mbed-os/platform/FilePath.o: ../mbed-os/platform/FilePath.cpp \
+ ../mbed_config.h .././mbed-os/platform/FilePath.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/FileSystemLike.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/FileHandle.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_poll.h .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/FileLike.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FilePath.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FilePath.o
new file mode 100755
index 0000000..65181f6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FilePath.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileSystemHandle.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileSystemHandle.d
new file mode 100755
index 0000000..cd448bf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileSystemHandle.d
@@ -0,0 +1,176 @@
+mbed-os/platform/FileSystemHandle.o: \
+ ../mbed-os/platform/FileSystemHandle.cpp ../mbed_config.h \
+ .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ ../mbed-os/platform/FileSystemHandle.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileSystemHandle.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileSystemHandle.o
new file mode 100755
index 0000000..6db7e2c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/FileSystemHandle.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/LocalFileSystem.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/LocalFileSystem.d
new file mode 100755
index 0000000..ecc8775
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/LocalFileSystem.d
@@ -0,0 +1,90 @@
+mbed-os/platform/LocalFileSystem.o: \
+ ../mbed-os/platform/LocalFileSystem.cpp ../mbed_config.h \
+ .././mbed-os/platform/LocalFileSystem.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/LocalFileSystem.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/LocalFileSystem.o
new file mode 100755
index 0000000..2b734bc
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/LocalFileSystem.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/Stream.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/Stream.d
new file mode 100755
index 0000000..31ba7e6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/Stream.d
@@ -0,0 +1,111 @@
+mbed-os/platform/Stream.o: ../mbed-os/platform/Stream.cpp \
+ ../mbed_config.h .././mbed-os/platform/Stream.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/FileLike.h .././mbed-os/platform/FileBase.h \
+ .././mbed-os/platform/SingletonPtr.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/FileHandle.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_poll.h .././mbed-os/platform/mbed_error.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/Stream.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/Stream.o
new file mode 100755
index 0000000..d901913
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/Stream.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_alloc_wrappers.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_alloc_wrappers.d
new file mode 100755
index 0000000..8d1e4cf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_alloc_wrappers.d
@@ -0,0 +1,99 @@
+mbed-os/platform/mbed_alloc_wrappers.o: \
+ ../mbed-os/platform/mbed_alloc_wrappers.cpp ../mbed_config.h \
+ .././mbed-os/platform/mbed_mem_trace.h \
+ .././mbed-os/platform/mbed_stats.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/SingletonPtr.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_alloc_wrappers.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_alloc_wrappers.o
new file mode 100755
index 0000000..c3f5cdc
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_alloc_wrappers.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_application.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_application.d
new file mode 100755
index 0000000..771d599
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_application.d
@@ -0,0 +1,88 @@
+mbed-os/platform/mbed_application.o: \
+ ../mbed-os/platform/mbed_application.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_application.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_application.o
new file mode 100755
index 0000000..dd83ca6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_application.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_assert.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_assert.d
new file mode 100755
index 0000000..455c8e4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_assert.d
@@ -0,0 +1,89 @@
+mbed-os/platform/mbed_assert.o: ../mbed-os/platform/mbed_assert.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_assert.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_assert.o
new file mode 100755
index 0000000..0194bce
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_assert.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_board.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_board.d
new file mode 100755
index 0000000..a8e2f9b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_board.d
@@ -0,0 +1,92 @@
+mbed-os/platform/mbed_board.o: ../mbed-os/platform/mbed_board.c \
+ ../mbed_config.h .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_critical.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/dma_api.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_board.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_board.o
new file mode 100755
index 0000000..f881ae1
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_board.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_critical.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_critical.d
new file mode 100755
index 0000000..2965569
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_critical.d
@@ -0,0 +1,79 @@
+mbed-os/platform/mbed_critical.o: ../mbed-os/platform/mbed_critical.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_critical.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_critical.o
new file mode 100755
index 0000000..f5ab554
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_critical.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_error.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_error.d
new file mode 100755
index 0000000..dadea99
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_error.d
@@ -0,0 +1,89 @@
+mbed-os/platform/mbed_error.o: ../mbed-os/platform/mbed_error.c \
+ ../mbed_config.h .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_error.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_error.o
new file mode 100755
index 0000000..ea6d212
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_error.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_interface.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_interface.d
new file mode 100755
index 0000000..730c8c3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_interface.d
@@ -0,0 +1,91 @@
+mbed-os/platform/mbed_interface.o: ../mbed-os/platform/mbed_interface.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/platform/mbed_semihost_api.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_error.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_interface.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_interface.o
new file mode 100755
index 0000000..54c6695
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_interface.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mem_trace.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mem_trace.d
new file mode 100755
index 0000000..84bb63d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mem_trace.d
@@ -0,0 +1,3 @@
+mbed-os/platform/mbed_mem_trace.o: ../mbed-os/platform/mbed_mem_trace.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_mem_trace.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mem_trace.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mem_trace.o
new file mode 100755
index 0000000..ef76c16
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mem_trace.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mktime.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mktime.d
new file mode 100755
index 0000000..6347324
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mktime.d
@@ -0,0 +1,2 @@
+mbed-os/platform/mbed_mktime.o: ../mbed-os/platform/mbed_mktime.c \
+ ../mbed_config.h ../mbed-os/platform/mbed_mktime.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mktime.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mktime.o
new file mode 100755
index 0000000..54558b4
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_mktime.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_poll.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_poll.d
new file mode 100755
index 0000000..7a4bedb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_poll.d
@@ -0,0 +1,113 @@
+mbed-os/platform/mbed_poll.o: ../mbed-os/platform/mbed_poll.cpp \
+ ../mbed_config.h ../mbed-os/platform/mbed_poll.h \
+ ../mbed-os/platform/FileHandle.h ../mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/platform.h .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_poll.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_poll.o
new file mode 100755
index 0000000..1643131
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_poll.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_retarget.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_retarget.d
new file mode 100755
index 0000000..ab162d4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_retarget.d
@@ -0,0 +1,121 @@
+mbed-os/platform/mbed_retarget.o: ../mbed-os/platform/mbed_retarget.cpp \
+ ../mbed_config.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/FilePath.h .././mbed-os/platform/FileSystemLike.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/FileHandle.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/mbed_poll.h .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/FileLike.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/hal/us_ticker_api.h .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/platform/mbed_semihost_api.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/platform/mbed_stats.h \
+ .././mbed-os/platform/mbed_critical.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h ../mbed-os/platform/mbed_error.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_retarget.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_retarget.o
new file mode 100755
index 0000000..45db546
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_retarget.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_rtc_time.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_rtc_time.d
new file mode 100755
index 0000000..608a013
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_rtc_time.d
@@ -0,0 +1,108 @@
+mbed-os/platform/mbed_rtc_time.o: ../mbed-os/platform/mbed_rtc_time.cpp \
+ ../mbed_config.h .././mbed-os/hal/rtc_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/platform/mbed_rtc_time.h \
+ .././mbed-os/platform/SingletonPtr.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/PlatformMutex.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_rtc_time.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_rtc_time.o
new file mode 100755
index 0000000..0ebd0c3
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_rtc_time.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_sdk_boot.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_sdk_boot.d
new file mode 100755
index 0000000..c7c0e9d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_sdk_boot.d
@@ -0,0 +1,77 @@
+mbed-os/platform/mbed_sdk_boot.o: ../mbed-os/platform/mbed_sdk_boot.c \
+ ../mbed_config.h ../mbed-os/platform/mbed_toolchain.h \
+ ../mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_sdk_boot.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_sdk_boot.o
new file mode 100755
index 0000000..3c1bd19
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_sdk_boot.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_semihost_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_semihost_api.d
new file mode 100755
index 0000000..6722ac8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_semihost_api.d
@@ -0,0 +1,89 @@
+mbed-os/platform/mbed_semihost_api.o: \
+ ../mbed-os/platform/mbed_semihost_api.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/platform/mbed_semihost_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_toolchain.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_semihost_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_semihost_api.o
new file mode 100755
index 0000000..8ac5e41
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_semihost_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_stats.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_stats.d
new file mode 100755
index 0000000..1d19697
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_stats.d
@@ -0,0 +1,5 @@
+mbed-os/platform/mbed_stats.o: ../mbed-os/platform/mbed_stats.c \
+ ../mbed_config.h ../mbed-os/platform/mbed_stats.h \
+ ../mbed-os/platform/mbed_assert.h \
+ ../mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_stats.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_stats.o
new file mode 100755
index 0000000..d4ea85b
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_stats.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_no_rtos.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_no_rtos.d
new file mode 100755
index 0000000..3630d03
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_no_rtos.d
@@ -0,0 +1,2 @@
+mbed-os/platform/mbed_wait_api_no_rtos.o: \
+ ../mbed-os/platform/mbed_wait_api_no_rtos.c ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_no_rtos.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_no_rtos.o
new file mode 100755
index 0000000..b51744c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_no_rtos.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_rtos.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_rtos.d
new file mode 100755
index 0000000..2626a1d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_rtos.d
@@ -0,0 +1,176 @@
+mbed-os/platform/mbed_wait_api_rtos.o: \
+ ../mbed-os/platform/mbed_wait_api_rtos.cpp ../mbed_config.h \
+ .././mbed-os/platform/mbed_wait_api.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/mbed.h \
+ .././mbed-os/rtos/rtos.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/TimerEvent.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_rtos.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_rtos.o
new file mode 100755
index 0000000..9a48058
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/platform/mbed_wait_api_rtos.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/EventFlags.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/EventFlags.d
new file mode 100755
index 0000000..40f33bc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/EventFlags.d
@@ -0,0 +1,95 @@
+mbed-os/rtos/EventFlags.o: ../mbed-os/rtos/EventFlags.cpp \
+ ../mbed_config.h .././mbed-os/rtos/EventFlags.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/EventFlags.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/EventFlags.o
new file mode 100755
index 0000000..ba89083
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/EventFlags.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Mutex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Mutex.d
new file mode 100755
index 0000000..ee7292f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Mutex.d
@@ -0,0 +1,95 @@
+mbed-os/rtos/Mutex.o: ../mbed-os/rtos/Mutex.cpp ../mbed_config.h \
+ .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Mutex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Mutex.o
new file mode 100755
index 0000000..996d326
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Mutex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/RtosTimer.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/RtosTimer.d
new file mode 100755
index 0000000..3c55aa5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/RtosTimer.d
@@ -0,0 +1,174 @@
+mbed-os/rtos/RtosTimer.o: ../mbed-os/rtos/RtosTimer.cpp ../mbed_config.h \
+ .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h .././mbed-os/mbed.h \
+ .././mbed-os/rtos/rtos.h .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/Semaphore.h .././mbed-os/rtos/Mutex.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/RtosTimer.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/RtosTimer.o
new file mode 100755
index 0000000..011cc93
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/RtosTimer.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Semaphore.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Semaphore.d
new file mode 100755
index 0000000..7d69f07
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Semaphore.d
@@ -0,0 +1,94 @@
+mbed-os/rtos/Semaphore.o: ../mbed-os/rtos/Semaphore.cpp ../mbed_config.h \
+ .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Semaphore.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Semaphore.o
new file mode 100755
index 0000000..6ad669a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Semaphore.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_boot.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_boot.d
new file mode 100755
index 0000000..40baa12
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_boot.d
@@ -0,0 +1,92 @@
+mbed-os/rtos/TARGET_CORTEX/mbed_boot.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/mbed_boot.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ ../mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ ../mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_error.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_boot.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_boot.o
new file mode 100755
index 0000000..f026b43
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_boot.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.d
new file mode 100755
index 0000000..6fd4914
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.d
@@ -0,0 +1,13 @@
+mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.c ../mbed_config.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.o
new file mode 100755
index 0000000..b6bf5b6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.d
new file mode 100755
index 0000000..bf05174
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.d
@@ -0,0 +1,105 @@
+mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp ../mbed_config.h \
+ .././mbed-os/rtos/rtos_idle.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/TimerEvent.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/hal/lp_ticker_api.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.o
new file mode 100755
index 0000000..945b29f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.d
new file mode 100755
index 0000000..d0e5d8a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.d
@@ -0,0 +1,6 @@
+mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.o
new file mode 100755
index 0000000..07901c7
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.d
new file mode 100755
index 0000000..a2ba1f5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.d
@@ -0,0 +1,6 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.c ../mbed_config.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.o
new file mode 100755
index 0000000..313ee85
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.d
new file mode 100755
index 0000000..b07ba28
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.d
@@ -0,0 +1,2 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.o
new file mode 100755
index 0000000..d7c2bea
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.d
new file mode 100755
index 0000000..a1f3ec0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.d
@@ -0,0 +1,3 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.o
new file mode 100755
index 0000000..d39bc27
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.d
new file mode 100755
index 0000000..e86deab
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.o
new file mode 100755
index 0000000..cf4e389
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.d
new file mode 100755
index 0000000..4c2b80c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.o
new file mode 100755
index 0000000..47d2100
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.d
new file mode 100755
index 0000000..3a7b030
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.d
@@ -0,0 +1,10 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.c ../mbed_config.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.o
new file mode 100755
index 0000000..6118804
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.d
new file mode 100755
index 0000000..56ac040
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.d
@@ -0,0 +1,87 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.o
new file mode 100755
index 0000000..78dc119
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.d
new file mode 100755
index 0000000..d3e6656
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.d
@@ -0,0 +1,9 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.c ../mbed_config.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.o
new file mode 100755
index 0000000..c3bf404
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.d
new file mode 100755
index 0000000..36908f5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.o
new file mode 100755
index 0000000..273bdec
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.d
new file mode 100755
index 0000000..8ff575b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.o
new file mode 100755
index 0000000..38b4408
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.d
new file mode 100755
index 0000000..b0f348d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.o
new file mode 100755
index 0000000..8bd4de9
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.d
new file mode 100755
index 0000000..851041f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.o
new file mode 100755
index 0000000..ee468f2
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.d
new file mode 100755
index 0000000..60bf5d8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.o
new file mode 100755
index 0000000..2bb3afd
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.d
new file mode 100755
index 0000000..adb9d9f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.o
new file mode 100755
index 0000000..e36be96
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.d
new file mode 100755
index 0000000..aa5c940
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.d
@@ -0,0 +1,87 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.o
new file mode 100755
index 0000000..9848f52
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.d
new file mode 100755
index 0000000..adefa57
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.d
@@ -0,0 +1,86 @@
+mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.o: \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.c ../mbed_config.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ ../mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.o
new file mode 100755
index 0000000..27519d9
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Thread.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Thread.d
new file mode 100755
index 0000000..09796a8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Thread.d
@@ -0,0 +1,173 @@
+mbed-os/rtos/Thread.o: ../mbed-os/rtos/Thread.cpp ../mbed_config.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/RtosTimer.h .././mbed-os/rtos/Mail.h \
+ .././mbed-os/rtos/Queue.h .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/Queue.h .././mbed-os/rtos/EventFlags.h \
+ .././mbed-os/events/mbed_events.h .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h .././mbed-os/rtos/rtos_idle.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Thread.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Thread.o
new file mode 100755
index 0000000..9931265
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/rtos/Thread.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.d
new file mode 100755
index 0000000..0d16679
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.d
@@ -0,0 +1,81 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c \
+ ../mbed_config.h .././mbed-os/targets/TARGET_STM/PeripheralPins.h \
+ .././mbed-os/hal/pinmap.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.o
new file mode 100755
index 0000000..e48e5af
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.d
new file mode 100755
index 0000000..2c9dfbc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.d
@@ -0,0 +1,77 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c \
+ ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/nvic_addr.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.o
new file mode 100755
index 0000000..c2ee800
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.d
new file mode 100755
index 0000000..3e6e0c5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.d
@@ -0,0 +1,2 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.o
new file mode 100755
index 0000000..d8ade91
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.d
new file mode 100755
index 0000000..b82cf9a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.d
@@ -0,0 +1,91 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/hal/analogin_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_wait_api.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/PeripheralPins.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.o
new file mode 100755
index 0000000..a3dcfb6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.d
new file mode 100755
index 0000000..79e1abf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/PeripheralPins.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.o
new file mode 100755
index 0000000..2d05611
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.d
new file mode 100755
index 0000000..77d7cbc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.o
new file mode 100755
index 0000000..766b606
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.d
new file mode 100755
index 0000000..4c45ac6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.o
new file mode 100755
index 0000000..47b9dba
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.d
new file mode 100755
index 0000000..a734ff6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.o
new file mode 100755
index 0000000..1729701
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.d
new file mode 100755
index 0000000..914315d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.o
new file mode 100755
index 0000000..c7906a8
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.d
new file mode 100755
index 0000000..6151151
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.o
new file mode 100755
index 0000000..970dc53
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.d
new file mode 100755
index 0000000..09391e4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.o
new file mode 100755
index 0000000..f077801
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.d
new file mode 100755
index 0000000..a7a2b5c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.o
new file mode 100755
index 0000000..5970137
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.d
new file mode 100755
index 0000000..86e869e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.o
new file mode 100755
index 0000000..277984a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.d
new file mode 100755
index 0000000..9baceb2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.o
new file mode 100755
index 0000000..e2412f6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.d
new file mode 100755
index 0000000..b8486e4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.o
new file mode 100755
index 0000000..8487c8c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.d
new file mode 100755
index 0000000..0655f13
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.o
new file mode 100755
index 0000000..9fa6d37
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.d
new file mode 100755
index 0000000..9965744
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.o
new file mode 100755
index 0000000..f18d1a0
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.d
new file mode 100755
index 0000000..35cbb61
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.o
new file mode 100755
index 0000000..a9713d3
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.d
new file mode 100755
index 0000000..550295d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.o
new file mode 100755
index 0000000..603640d
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.d
new file mode 100755
index 0000000..1d54d43
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.o
new file mode 100755
index 0000000..26eb00e
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.d
new file mode 100755
index 0000000..e4930d2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.o
new file mode 100755
index 0000000..7eca5ae
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.d
new file mode 100755
index 0000000..2fc1462
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.o
new file mode 100755
index 0000000..5a6a6e3
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.d
new file mode 100755
index 0000000..9471bcd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.o
new file mode 100755
index 0000000..a3b5a71
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.d
new file mode 100755
index 0000000..1a81742
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.o
new file mode 100755
index 0000000..6c88c81
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.d
new file mode 100755
index 0000000..ec88fa1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.o
new file mode 100755
index 0000000..5e61447
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.d
new file mode 100755
index 0000000..b5e0a32
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.o
new file mode 100755
index 0000000..efbcbd3
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.d
new file mode 100755
index 0000000..1e4d219
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.o
new file mode 100755
index 0000000..02335c9
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.d
new file mode 100755
index 0000000..efeb117
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.o
new file mode 100755
index 0000000..85ebaa5
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.d
new file mode 100755
index 0000000..b54f388
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.o
new file mode 100755
index 0000000..e2245ec
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.d
new file mode 100755
index 0000000..42b81a3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.o
new file mode 100755
index 0000000..32c5980
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.d
new file mode 100755
index 0000000..feb817c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.o
new file mode 100755
index 0000000..de13b87
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.d
new file mode 100755
index 0000000..cc1440d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.o
new file mode 100755
index 0000000..d80d765
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.d
new file mode 100755
index 0000000..79824fc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.o
new file mode 100755
index 0000000..7dbc4df
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.d
new file mode 100755
index 0000000..c7a35dc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.o
new file mode 100755
index 0000000..9f0baf8
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.d
new file mode 100755
index 0000000..55b4655
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.o
new file mode 100755
index 0000000..16b574c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.d
new file mode 100755
index 0000000..53ccf54
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.o
new file mode 100755
index 0000000..41e1ffd
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.d
new file mode 100755
index 0000000..a72332e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.o
new file mode 100755
index 0000000..4a70169
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.d
new file mode 100755
index 0000000..77d2a50
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.o
new file mode 100755
index 0000000..177e59c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.d
new file mode 100755
index 0000000..14ca6e3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.o
new file mode 100755
index 0000000..e36c3f2
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.d
new file mode 100755
index 0000000..2df1ea3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.o
new file mode 100755
index 0000000..e7f19f5
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.d
new file mode 100755
index 0000000..9222545
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.o
new file mode 100755
index 0000000..b6bd585
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.d
new file mode 100755
index 0000000..4c34e2a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.o
new file mode 100755
index 0000000..a3106fe
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.d
new file mode 100755
index 0000000..f2d0504
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.o
new file mode 100755
index 0000000..ffb9bfb
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.d
new file mode 100755
index 0000000..baf80e7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.o
new file mode 100755
index 0000000..5ce809c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.d
new file mode 100755
index 0000000..c2afb80
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.o
new file mode 100755
index 0000000..4721147
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.d
new file mode 100755
index 0000000..eaaddf6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.o
new file mode 100755
index 0000000..bef619a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.d
new file mode 100755
index 0000000..cfb75bc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.o
new file mode 100755
index 0000000..acdc428
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.d
new file mode 100755
index 0000000..24e8b3d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.o
new file mode 100755
index 0000000..463261e
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.d
new file mode 100755
index 0000000..f045366
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.o
new file mode 100755
index 0000000..921d048
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.d
new file mode 100755
index 0000000..c9c4a7f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.o
new file mode 100755
index 0000000..2b7ed5a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.d
new file mode 100755
index 0000000..d7014cf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.o
new file mode 100755
index 0000000..a8dc4aa
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.d
new file mode 100755
index 0000000..6fab5c0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.o
new file mode 100755
index 0000000..8e9a092
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.d
new file mode 100755
index 0000000..a0cbb04
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.o
new file mode 100755
index 0000000..bffe082
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.d
new file mode 100755
index 0000000..e822863
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.o
new file mode 100755
index 0000000..050ce5c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.d
new file mode 100755
index 0000000..174dddc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.o
new file mode 100755
index 0000000..6c0b417
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.d
new file mode 100755
index 0000000..d4cd2f6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.o
new file mode 100755
index 0000000..c5b7bec
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.d
new file mode 100755
index 0000000..16398a2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.o
new file mode 100755
index 0000000..28141c6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.d
new file mode 100755
index 0000000..2294589
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.o
new file mode 100755
index 0000000..cfb6f17
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.d
new file mode 100755
index 0000000..4642639
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.o
new file mode 100755
index 0000000..1a444d9
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.d
new file mode 100755
index 0000000..4321625
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.o
new file mode 100755
index 0000000..9052c45
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.d
new file mode 100755
index 0000000..e366bd0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.o
new file mode 100755
index 0000000..4215502
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.d
new file mode 100755
index 0000000..34fcd39
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.o
new file mode 100755
index 0000000..9ce1d00
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.d
new file mode 100755
index 0000000..b4205bd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.o
new file mode 100755
index 0000000..8de8047
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.d
new file mode 100755
index 0000000..3f8ba82
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.o
new file mode 100755
index 0000000..ace6878
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.d
new file mode 100755
index 0000000..03c0db4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.o
new file mode 100755
index 0000000..0673bff
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.d
new file mode 100755
index 0000000..68336a9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.o
new file mode 100755
index 0000000..a549312
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.d
new file mode 100755
index 0000000..1042fef
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.o
new file mode 100755
index 0000000..dcc65d8
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.d
new file mode 100755
index 0000000..cc91303
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.o
new file mode 100755
index 0000000..96e3d74
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.d
new file mode 100755
index 0000000..eb0fd14
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.o
new file mode 100755
index 0000000..e19e9c4
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.d
new file mode 100755
index 0000000..c76a1e6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.o
new file mode 100755
index 0000000..81f56d9
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.d
new file mode 100755
index 0000000..a73eb19
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.o
new file mode 100755
index 0000000..666acd1
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.d
new file mode 100755
index 0000000..f326d3b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.o
new file mode 100755
index 0000000..89d0876
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.d
new file mode 100755
index 0000000..15e2b48
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.o
new file mode 100755
index 0000000..6dcead2
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.d
new file mode 100755
index 0000000..9ab79eb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.o
new file mode 100755
index 0000000..18f6994
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.d
new file mode 100755
index 0000000..a23474e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.o
new file mode 100755
index 0000000..f945739
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.d
new file mode 100755
index 0000000..64455e8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.o
new file mode 100755
index 0000000..bd57e34
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.d
new file mode 100755
index 0000000..f16388b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.o
new file mode 100755
index 0000000..f79df1b
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.d
new file mode 100755
index 0000000..38edb5c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.o
new file mode 100755
index 0000000..80d920a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.d
new file mode 100755
index 0000000..94b5ab5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.o
new file mode 100755
index 0000000..902411a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.d
new file mode 100755
index 0000000..24fcaa4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.o
new file mode 100755
index 0000000..1af5297
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.d
new file mode 100755
index 0000000..fbbce8e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.o
new file mode 100755
index 0000000..bdf4c5c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.d
new file mode 100755
index 0000000..1e2db3e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.o
new file mode 100755
index 0000000..e6c1a18
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.d
new file mode 100755
index 0000000..170b265
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.o
new file mode 100755
index 0000000..868c6c0
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.d
new file mode 100755
index 0000000..0ef1f93
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.o
new file mode 100755
index 0000000..69e9b4a
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.d
new file mode 100755
index 0000000..574ac43
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.o
new file mode 100755
index 0000000..7bca036
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.d
new file mode 100755
index 0000000..464f039
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.o
new file mode 100755
index 0000000..e5528c0
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.d
new file mode 100755
index 0000000..d9adc98
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.o
new file mode 100755
index 0000000..91f4fb4
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.d
new file mode 100755
index 0000000..22932e6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.o
new file mode 100755
index 0000000..ba6e4ab
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.d
new file mode 100755
index 0000000..8e4bdb9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.d
@@ -0,0 +1,3 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c \
+ ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.o
new file mode 100755
index 0000000..49f5c12
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.d
new file mode 100755
index 0000000..689caeb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.d
@@ -0,0 +1,75 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.o
new file mode 100755
index 0000000..02a307c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.d
new file mode 100755
index 0000000..35719c9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.d
@@ -0,0 +1,78 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c \
+ ../mbed_config.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.o
new file mode 100755
index 0000000..50574ab
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.d
new file mode 100755
index 0000000..6143e42
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.d
@@ -0,0 +1,74 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c \
+ ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.o
new file mode 100755
index 0000000..844df03
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.d
new file mode 100755
index 0000000..836aef1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.d
@@ -0,0 +1,89 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.c \
+ ../mbed_config.h .././mbed-os/hal/flash_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.o
new file mode 100755
index 0000000..9e042c2
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.d
new file mode 100755
index 0000000..e0b585b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.d
@@ -0,0 +1,79 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.c \
+ ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.o
new file mode 100755
index 0000000..1fd9ee5
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.d
new file mode 100755
index 0000000..4b29be4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c \
+ ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.o
new file mode 100755
index 0000000..12c7eb9
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.d
new file mode 100755
index 0000000..4dcce50
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.d
@@ -0,0 +1,91 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.c \
+ ../mbed_config.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h \
+ .././mbed-os/targets/TARGET_STM/serial_api_hal.h \
+ .././mbed-os/hal/pinmap.h .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/PeripheralPins.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.o
new file mode 100755
index 0000000..70e8ba2
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.d
new file mode 100755
index 0000000..fa2ca38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.o: \
+ ../mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.c ../mbed_config.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h .././mbed-os/hal/spi_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/PeripheralPins.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.o
new file mode 100755
index 0000000..4e01852
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/analogout_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/analogout_api.d
new file mode 100755
index 0000000..dafb86d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/analogout_api.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/analogout_api.o: \
+ ../mbed-os/targets/TARGET_STM/analogout_api.c ../mbed_config.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/platform/mbed_error.h \
+ ../mbed-os/targets/TARGET_STM/PeripheralPins.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/analogout_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/analogout_api.o
new file mode 100755
index 0000000..7f77420
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/analogout_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/can_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/can_api.d
new file mode 100755
index 0000000..a1ed4a1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/can_api.d
@@ -0,0 +1,92 @@
+mbed-os/targets/TARGET_STM/can_api.o: \
+ ../mbed-os/targets/TARGET_STM/can_api.c ../mbed_config.h \
+ .././mbed-os/hal/can_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/hal/pinmap.h \
+ ../mbed-os/targets/TARGET_STM/PeripheralPins.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/can_device.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/can_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/can_api.o
new file mode 100755
index 0000000..b0f341f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/can_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_api.d
new file mode 100755
index 0000000..cb06339
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_api.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/gpio_api.o: \
+ ../mbed-os/targets/TARGET_STM/gpio_api.c ../mbed_config.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h .././mbed-os/hal/gpio_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/pin_device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_api.o
new file mode 100755
index 0000000..130a4be
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_irq_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_irq_api.d
new file mode 100755
index 0000000..0ea5197
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_irq_api.d
@@ -0,0 +1,91 @@
+mbed-os/targets/TARGET_STM/gpio_irq_api.o: \
+ ../mbed-os/targets/TARGET_STM/gpio_irq_api.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_irq_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_irq_api.o
new file mode 100755
index 0000000..c6d44f5
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/gpio_irq_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_16b.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_16b.d
new file mode 100755
index 0000000..465e4c3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_16b.d
@@ -0,0 +1,77 @@
+mbed-os/targets/TARGET_STM/hal_tick_16b.o: \
+ ../mbed-os/targets/TARGET_STM/hal_tick_16b.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_16b.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_16b.o
new file mode 100755
index 0000000..f96bcfb
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_16b.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_32b.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_32b.d
new file mode 100755
index 0000000..d08c099
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_32b.d
@@ -0,0 +1,77 @@
+mbed-os/targets/TARGET_STM/hal_tick_32b.o: \
+ ../mbed-os/targets/TARGET_STM/hal_tick_32b.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_32b.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_32b.o
new file mode 100755
index 0000000..b3ee4b3
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/hal_tick_32b.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/i2c_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/i2c_api.d
new file mode 100755
index 0000000..9905587
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/i2c_api.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/i2c_api.o: \
+ ../mbed-os/targets/TARGET_STM/i2c_api.c ../mbed_config.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/pinmap.h ../mbed-os/targets/TARGET_STM/PeripheralPins.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/i2c_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/i2c_api.o
new file mode 100755
index 0000000..044a265
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/i2c_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/lp_ticker.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/lp_ticker.d
new file mode 100755
index 0000000..328e759
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/lp_ticker.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/lp_ticker.o: \
+ ../mbed-os/targets/TARGET_STM/lp_ticker.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/hal/lp_ticker_api.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/hal/rtc_api.h \
+ ../mbed-os/targets/TARGET_STM/rtc_api_hal.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/lp_ticker.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/lp_ticker.o
new file mode 100755
index 0000000..a730caa
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/lp_ticker.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/mbed_overrides.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/mbed_overrides.d
new file mode 100755
index 0000000..f0f3c20
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/mbed_overrides.d
@@ -0,0 +1,76 @@
+mbed-os/targets/TARGET_STM/mbed_overrides.o: \
+ ../mbed-os/targets/TARGET_STM/mbed_overrides.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/mbed_overrides.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/mbed_overrides.o
new file mode 100755
index 0000000..1c1d7b6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/mbed_overrides.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pinmap.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pinmap.d
new file mode 100755
index 0000000..3c7378b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pinmap.d
@@ -0,0 +1,84 @@
+mbed-os/targets/TARGET_STM/pinmap.o: \
+ ../mbed-os/targets/TARGET_STM/pinmap.c ../mbed_config.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ ../mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/pin_device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pinmap.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pinmap.o
new file mode 100755
index 0000000..56c6699
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pinmap.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/port_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/port_api.d
new file mode 100755
index 0000000..2c4510c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/port_api.d
@@ -0,0 +1,89 @@
+mbed-os/targets/TARGET_STM/port_api.o: \
+ ../mbed-os/targets/TARGET_STM/port_api.c ../mbed_config.h \
+ .././mbed-os/hal/port_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_error.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/port_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/port_api.o
new file mode 100755
index 0000000..dc7c7dc
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/port_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pwmout_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pwmout_api.d
new file mode 100755
index 0000000..6670972
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pwmout_api.d
@@ -0,0 +1,91 @@
+mbed-os/targets/TARGET_STM/pwmout_api.o: \
+ ../mbed-os/targets/TARGET_STM/pwmout_api.c ../mbed_config.h \
+ .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/pinmap.h \
+ .././mbed-os/platform/mbed_error.h \
+ ../mbed-os/targets/TARGET_STM/PeripheralPins.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pwmout_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pwmout_api.o
new file mode 100755
index 0000000..240c00f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/pwmout_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/rtc_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/rtc_api.d
new file mode 100755
index 0000000..d9a4d73
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/rtc_api.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/rtc_api.o: \
+ ../mbed-os/targets/TARGET_STM/rtc_api.c ../mbed_config.h \
+ .././mbed-os/hal/rtc_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ ../mbed-os/targets/TARGET_STM/rtc_api_hal.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/platform/mbed_mktime.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/rtc_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/rtc_api.o
new file mode 100755
index 0000000..42a5fae
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/rtc_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/serial_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/serial_api.d
new file mode 100755
index 0000000..060948a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/serial_api.d
@@ -0,0 +1,91 @@
+mbed-os/targets/TARGET_STM/serial_api.o: \
+ ../mbed-os/targets/TARGET_STM/serial_api.c ../mbed_config.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h \
+ ../mbed-os/targets/TARGET_STM/serial_api_hal.h \
+ ../mbed-os/targets/TARGET_STM/PeripheralPins.h .././mbed-os/hal/pinmap.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/serial_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/serial_api.o
new file mode 100755
index 0000000..45beaa0
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/serial_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/sleep.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/sleep.d
new file mode 100755
index 0000000..2b0b0e9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/sleep.d
@@ -0,0 +1,92 @@
+mbed-os/targets/TARGET_STM/sleep.o: ../mbed-os/targets/TARGET_STM/sleep.c \
+ ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/hal/us_ticker_api.h .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/sleep_api.h \
+ ../mbed-os/targets/TARGET_STM/rtc_api_hal.h .././mbed-os/hal/rtc_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h \
+ .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/sleep.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/sleep.o
new file mode 100755
index 0000000..f5b866d
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/sleep.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/stm_spi_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/stm_spi_api.d
new file mode 100755
index 0000000..f80e7b5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/stm_spi_api.d
@@ -0,0 +1,92 @@
+mbed-os/targets/TARGET_STM/stm_spi_api.o: \
+ ../mbed-os/targets/TARGET_STM/stm_spi_api.c ../mbed_config.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/hal/spi_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h .././mbed-os/hal/dma_api.h \
+ .././mbed-os/hal/buffer.h .././mbed-os/hal/pinmap.h \
+ ../mbed-os/targets/TARGET_STM/PeripheralPins.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/stm_spi_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/stm_spi_api.o
new file mode 100755
index 0000000..b45e3c5
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/stm_spi_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/trng_api.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/trng_api.d
new file mode 100755
index 0000000..77dae78
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/trng_api.d
@@ -0,0 +1,89 @@
+mbed-os/targets/TARGET_STM/trng_api.o: \
+ ../mbed-os/targets/TARGET_STM/trng_api.c ../mbed_config.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/hal/trng_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/platform/mbed_critical.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/trng_api.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/trng_api.o
new file mode 100755
index 0000000..4a6325d
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/trng_api.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_16b.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_16b.d
new file mode 100755
index 0000000..c8c52ec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_16b.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/us_ticker_16b.o: \
+ ../mbed-os/targets/TARGET_STM/us_ticker_16b.c ../mbed_config.h \
+ .././mbed-os/hal/us_ticker_api.h .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_16b.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_16b.o
new file mode 100755
index 0000000..05df84f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_16b.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_32b.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_32b.d
new file mode 100755
index 0000000..7859a9f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_32b.d
@@ -0,0 +1,90 @@
+mbed-os/targets/TARGET_STM/us_ticker_32b.o: \
+ ../mbed-os/targets/TARGET_STM/us_ticker_32b.c ../mbed_config.h \
+ .././mbed-os/hal/us_ticker_api.h .././mbed-os/hal/ticker_api.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_32b.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_32b.o
new file mode 100755
index 0000000..a0b5c8d
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/mbed-os/targets/TARGET_STM/us_ticker_32b.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/DHCP_ARP.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/DHCP_ARP.d
new file mode 100755
index 0000000..51ac37b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/DHCP_ARP.d
@@ -0,0 +1,176 @@
+source/DHCP_ARP.o: ../source/DHCP_ARP.cpp ../mbed_config.h \
+ ../source/DHCP_ARP.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/W5500.h \
+ ../source/global_variables.h ../source/SI4463.h ../source/ext_SRAM2.h \
+ ../source/Eth_IPv4.h ../source/HMI_telnet.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/DHCP_ARP.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/DHCP_ARP.o
new file mode 100755
index 0000000..bf046e8
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/DHCP_ARP.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Eth_IPv4.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Eth_IPv4.d
new file mode 100755
index 0000000..5126fe9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Eth_IPv4.d
@@ -0,0 +1,176 @@
+source/Eth_IPv4.o: ../source/Eth_IPv4.cpp ../mbed_config.h \
+ ../source/Eth_IPv4.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/W5500.h \
+ ../source/global_variables.h ../source/SI4463.h ../source/ext_SRAM2.h \
+ ../source/L1L2_radio.h ../source/DHCP_ARP.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Eth_IPv4.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Eth_IPv4.o
new file mode 100755
index 0000000..20bd2f3
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Eth_IPv4.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/HMI_telnet.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/HMI_telnet.d
new file mode 100755
index 0000000..d0bd215
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/HMI_telnet.d
@@ -0,0 +1,177 @@
+source/HMI_telnet.o: ../source/HMI_telnet.cpp ../mbed_config.h \
+ ../source/HMI_telnet.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/W5500.h \
+ ../source/global_variables.h ../source/SI4463.h ../source/ext_SRAM2.h \
+ ../source/Eth_IPv4.h ../source/signaling.h ../source/config_flash.h \
+ ../source/TDMA.h ../source/DHCP_ARP.h ../source/L1L2_radio.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/HMI_telnet.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/HMI_telnet.o
new file mode 100755
index 0000000..3352ca7
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/HMI_telnet.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/L1L2_radio.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/L1L2_radio.d
new file mode 100755
index 0000000..a35fdcc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/L1L2_radio.d
@@ -0,0 +1,176 @@
+source/L1L2_radio.o: ../source/L1L2_radio.cpp ../mbed_config.h \
+ ../source/L1L2_radio.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/W5500.h \
+ ../source/global_variables.h ../source/SI4463.h ../source/ext_SRAM2.h \
+ ../source/Eth_IPv4.h ../source/TDMA.h ../source/signaling.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/L1L2_radio.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/L1L2_radio.o
new file mode 100755
index 0000000..8c00db7
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/L1L2_radio.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/SI4463.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/SI4463.d
new file mode 100755
index 0000000..508864a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/SI4463.d
@@ -0,0 +1,185 @@
+source/SI4463.o: ../source/SI4463.cpp ../mbed_config.h ../source/SI4463.h \
+ .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/global_variables.h \
+ ../source/W5500.h ../source/ext_SRAM2.h ../source/TDMA.h \
+ ../source/HMI_telnet.h ../source/L1L2_radio.h \
+ .././source/SI4463/SI4463_config_20.h \
+ .././source/SI4463/SI4463_config_11.h \
+ .././source/SI4463/SI4463_config_21.h \
+ .././source/SI4463/SI4463_config_12.h \
+ .././source/SI4463/SI4463_config_22.h \
+ .././source/SI4463/SI4463_config_13.h \
+ .././source/SI4463/SI4463_config_23.h \
+ .././source/SI4463/SI4463_config_14.h \
+ .././source/SI4463/SI4463_config_24.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/SI4463.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/SI4463.o
new file mode 100755
index 0000000..9909743
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/SI4463.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/TDMA.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/TDMA.d
new file mode 100755
index 0000000..f0e8033
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/TDMA.d
@@ -0,0 +1,176 @@
+source/TDMA.o: ../source/TDMA.cpp ../mbed_config.h ../source/TDMA.h \
+ .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/L1L2_radio.h \
+ ../source/W5500.h ../source/global_variables.h ../source/SI4463.h \
+ ../source/ext_SRAM2.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/TDMA.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/TDMA.o
new file mode 100755
index 0000000..e460bf7
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/TDMA.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Virt_Chan.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Virt_Chan.d
new file mode 100755
index 0000000..87e03b9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Virt_Chan.d
@@ -0,0 +1,174 @@
+source/Virt_Chan.o: ../source/Virt_Chan.cpp ../mbed_config.h \
+ ../source/Virt_Chan.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/W5500.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Virt_Chan.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Virt_Chan.o
new file mode 100755
index 0000000..84cc3c4
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/Virt_Chan.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/W5500.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/W5500.d
new file mode 100755
index 0000000..becc5e9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/W5500.d
@@ -0,0 +1,175 @@
+source/W5500.o: ../source/W5500.cpp ../mbed_config.h ../source/W5500.h \
+ .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/global_variables.h \
+ ../source/SI4463.h ../source/ext_SRAM2.h ../source/Eth_IPv4.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/W5500.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/W5500.o
new file mode 100755
index 0000000..43a3712
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/W5500.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/config_flash.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/config_flash.d
new file mode 100755
index 0000000..429bfc2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/config_flash.d
@@ -0,0 +1,176 @@
+source/config_flash.o: ../source/config_flash.cpp ../mbed_config.h \
+ ../source/config_flash.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/global_variables.h \
+ ../source/SI4463.h ../source/W5500.h ../source/ext_SRAM2.h \
+ ../source/Eth_IPv4.h ../source/HMI_telnet.h ../source/TDMA.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/config_flash.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/config_flash.o
new file mode 100755
index 0000000..851b2bc
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/config_flash.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/ext_SRAM2.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/ext_SRAM2.d
new file mode 100755
index 0000000..105937f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/ext_SRAM2.d
@@ -0,0 +1 @@
+source/ext_SRAM2.o: ../source/ext_SRAM2.cpp ../mbed_config.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/ext_SRAM2.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/ext_SRAM2.o
new file mode 100755
index 0000000..8ddae42
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/ext_SRAM2.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/global_variables.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/global_variables.d
new file mode 100755
index 0000000..5a0478b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/global_variables.d
@@ -0,0 +1,176 @@
+source/global_variables.o: ../source/global_variables.cpp \
+ ../mbed_config.h ../source/SI4463.h .././mbed-os/mbed.h \
+ .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/W5500.h \
+ ../source/global_variables.h ../source/ext_SRAM2.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/global_variables.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/global_variables.o
new file mode 100755
index 0000000..e5faa01
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/global_variables.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/main.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/main.d
new file mode 100755
index 0000000..2408640
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/main.d
@@ -0,0 +1,178 @@
+source/main.o: ../source/main.cpp ../mbed_config.h .././mbed-os/mbed.h \
+ .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/W5500.h \
+ ../source/SI4463.h ../source/HMI_telnet.h ../source/global_variables.h \
+ ../source/ext_SRAM2.h ../source/Eth_IPv4.h ../source/DHCP_ARP.h \
+ ../source/L1L2_radio.h ../source/TDMA.h ../source/signaling.h \
+ ../source/config_flash.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/main.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/main.o
new file mode 100755
index 0000000..c2f3996
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/main.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/signaling.d b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/signaling.d
new file mode 100755
index 0000000..98a7c3a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/signaling.d
@@ -0,0 +1,177 @@
+source/signaling.o: ../source/signaling.cpp ../mbed_config.h \
+ ../source/signaling.h .././mbed-os/mbed.h .././mbed-os/rtos/rtos.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h \
+ .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h \
+ .././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h \
+ .././mbed-os/cmsis/arm_math.h .././mbed-os/cmsis/core_cm4.h \
+ .././mbed-os/cmsis/tz_context.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/targets/TARGET_STM/mbed_rtx.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h \
+ .././mbed-os/rtos/Thread.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h \
+ .././mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h \
+ .././mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/platform/mbed_preprocessor.h \
+ .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/NonCopyable.h .././mbed-os/rtos/Semaphore.h \
+ .././mbed-os/rtos/Mutex.h .././mbed-os/rtos/RtosTimer.h \
+ .././mbed-os/rtos/Mail.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/platform/mbed_error.h .././mbed-os/rtos/MemoryPool.h \
+ .././mbed-os/rtos/MemoryPool.h .././mbed-os/rtos/Queue.h \
+ .././mbed-os/rtos/EventFlags.h .././mbed-os/events/mbed_events.h \
+ .././mbed-os/events/equeue/equeue.h \
+ .././mbed-os/events/equeue/equeue_platform.h \
+ .././mbed-os/events/EventQueue.h .././mbed-os/events/Event.h \
+ .././mbed-os/events/mbed_shared_queues.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/platform/platform.h \
+ .././mbed-os/platform/mbed_retarget.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h \
+ .././mbed-os/targets/TARGET_STM/PinNamesTypes.h \
+ .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h \
+ .././mbed-os/targets/TARGET_STM/gpio_object.h \
+ .././mbed-os/platform/mbed_assert.h \
+ .././mbed-os/targets/TARGET_STM/PortNames.h \
+ .././mbed-os/platform/mbed_application.h \
+ .././mbed-os/platform/mbed_error.h \
+ .././mbed-os/platform/mbed_interface.h \
+ .././mbed-os/platform/mbed_assert.h .././mbed-os/platform/mbed_debug.h \
+ .././mbed-os/drivers/DigitalIn.h .././mbed-os/platform/platform.h \
+ .././mbed-os/hal/gpio_api.h .././mbed-os/platform/mbed_critical.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/DigitalInOut.h \
+ .././mbed-os/drivers/BusIn.h .././mbed-os/drivers/DigitalIn.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/BusOut.h \
+ .././mbed-os/drivers/DigitalOut.h .././mbed-os/drivers/BusInOut.h \
+ .././mbed-os/drivers/DigitalInOut.h .././mbed-os/drivers/PortIn.h \
+ .././mbed-os/hal/port_api.h .././mbed-os/drivers/PortInOut.h \
+ .././mbed-os/drivers/PortOut.h .././mbed-os/drivers/AnalogIn.h \
+ .././mbed-os/hal/analogin_api.h .././mbed-os/platform/SingletonPtr.h \
+ .././mbed-os/drivers/AnalogOut.h .././mbed-os/hal/analogout_api.h \
+ .././mbed-os/drivers/PwmOut.h .././mbed-os/hal/pwmout_api.h \
+ .././mbed-os/platform/mbed_sleep.h .././mbed-os/hal/sleep_api.h \
+ .././mbed-os/platform/mbed_toolchain.h .././mbed-os/drivers/Serial.h \
+ .././mbed-os/platform/Stream.h .././mbed-os/platform/FileLike.h \
+ .././mbed-os/platform/FileBase.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/Callback.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/hal/serial_api.h .././mbed-os/hal/buffer.h \
+ .././mbed-os/hal/dma_api.h .././mbed-os/platform/mbed_toolchain.h \
+ .././mbed-os/platform/PlatformMutex.h .././mbed-os/drivers/SPI.h \
+ .././mbed-os/hal/spi_api.h .././mbed-os/platform/CThunk.h \
+ .././mbed-os/platform/CircularBuffer.h \
+ .././mbed-os/platform/FunctionPointer.h \
+ .././mbed-os/platform/Transaction.h .././mbed-os/drivers/SPISlave.h \
+ .././mbed-os/drivers/I2C.h .././mbed-os/hal/i2c_api.h \
+ .././mbed-os/drivers/I2CSlave.h .././mbed-os/drivers/Ethernet.h \
+ .././mbed-os/drivers/CAN.h .././mbed-os/hal/can_api.h \
+ .././mbed-os/hal/can_helper.h .././mbed-os/drivers/RawSerial.h \
+ .././mbed-os/drivers/SerialBase.h .././mbed-os/hal/serial_api.h \
+ .././mbed-os/drivers/UARTSerial.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/hal/gpio_irq_api.h \
+ .././mbed-os/platform/CircularBuffer.h .././mbed-os/drivers/FlashIAP.h \
+ .././mbed-os/hal/flash_api.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/hal/ticker_api.h .././mbed-os/drivers/Ticker.h \
+ .././mbed-os/drivers/TimerEvent.h .././mbed-os/hal/us_ticker_api.h \
+ .././mbed-os/hal/lp_ticker_api.h .././mbed-os/drivers/Timeout.h \
+ .././mbed-os/drivers/Ticker.h .././mbed-os/drivers/LowPowerTimeout.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTicker.h \
+ .././mbed-os/drivers/LowPowerTimer.h .././mbed-os/drivers/Timer.h \
+ .././mbed-os/platform/LocalFileSystem.h \
+ .././mbed-os/drivers/InterruptIn.h .././mbed-os/platform/mbed_wait_api.h \
+ .././mbed-os/hal/sleep_api.h .././mbed-os/platform/mbed_sleep.h \
+ .././mbed-os/platform/mbed_rtc_time.h .././mbed-os/platform/mbed_poll.h \
+ .././mbed-os/platform/ATCmdParser.h \
+ .././mbed-os/platform/FileSystemHandle.h \
+ .././mbed-os/platform/DirHandle.h .././mbed-os/platform/FileHandle.h \
+ .././mbed-os/platform/DirHandle.h \
+ .././mbed-os/platform/CriticalSectionLock.h \
+ .././mbed-os/platform/DeepSleepLock.h .././mbed-os/platform/Callback.h \
+ .././mbed-os/platform/FunctionPointer.h ../source/Eth_IPv4.h \
+ ../source/W5500.h ../source/global_variables.h ../source/SI4463.h \
+ ../source/ext_SRAM2.h ../source/L1L2_radio.h ../source/DHCP_ARP.h \
+ ../source/TDMA.h ../source/HMI_telnet.h
diff --git a/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/signaling.o b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/signaling.o
new file mode 100755
index 0000000..90b540b
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/BUILD/source/signaling.o differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/Makefile b/NPR_FW_source_2020_06_29/NPR_14/Makefile
new file mode 100755
index 0000000..f875fbb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/Makefile
@@ -0,0 +1,525 @@
+# This file was automagically generated by mbed.org. For more information, 
+# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
+
+###############################################################################
+# Boiler-plate
+
+# cross-platform directory manipulation
+ifeq ($(shell echo $$OS),$$OS)
+    MAKEDIR = if not exist "$(1)" mkdir "$(1)"
+    RM = rmdir /S /Q "$(1)"
+else
+    MAKEDIR = '$(SHELL)' -c "mkdir -p \"$(1)\""
+    RM = '$(SHELL)' -c "rm -rf \"$(1)\""
+endif
+
+OBJDIR := BUILD
+# Move to the build directory
+ifeq (,$(filter $(OBJDIR),$(notdir $(CURDIR))))
+.SUFFIXES:
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
+MAKETARGET = '$(MAKE)' --no-print-directory -C $(OBJDIR) -f '$(mkfile_path)' \
+		'SRCDIR=$(CURDIR)' $(MAKECMDGOALS)
+.PHONY: $(OBJDIR) clean
+all:
+	+@$(call MAKEDIR,$(OBJDIR))
+	+@$(MAKETARGET)
+$(OBJDIR): all
+Makefile : ;
+% :: $(OBJDIR) ; :
+clean :
+	$(call RM,$(OBJDIR))
+
+else
+
+# trick rules into thinking we are in the root, when we are in the bulid dir
+VPATH = ..
+
+# Boiler-plate
+###############################################################################
+# Project settings
+
+PROJECT := NPR_14
+
+
+# Project settings
+###############################################################################
+# Objects and Paths
+
+OBJECTS += ./mbed-os/drivers/AnalogIn.o
+OBJECTS += ./mbed-os/drivers/BusIn.o
+OBJECTS += ./mbed-os/drivers/BusInOut.o
+OBJECTS += ./mbed-os/drivers/BusOut.o
+OBJECTS += ./mbed-os/drivers/CAN.o
+OBJECTS += ./mbed-os/drivers/Ethernet.o
+OBJECTS += ./mbed-os/drivers/FlashIAP.o
+OBJECTS += ./mbed-os/drivers/I2C.o
+OBJECTS += ./mbed-os/drivers/I2CSlave.o
+OBJECTS += ./mbed-os/drivers/InterruptIn.o
+OBJECTS += ./mbed-os/drivers/InterruptManager.o
+OBJECTS += ./mbed-os/drivers/RawSerial.o
+OBJECTS += ./mbed-os/drivers/SPI.o
+OBJECTS += ./mbed-os/drivers/SPISlave.o
+OBJECTS += ./mbed-os/drivers/Serial.o
+OBJECTS += ./mbed-os/drivers/SerialBase.o
+OBJECTS += ./mbed-os/drivers/Ticker.o
+OBJECTS += ./mbed-os/drivers/Timeout.o
+OBJECTS += ./mbed-os/drivers/Timer.o
+OBJECTS += ./mbed-os/drivers/TimerEvent.o
+OBJECTS += ./mbed-os/drivers/UARTSerial.o
+OBJECTS += ./mbed-os/events/EventQueue.o
+OBJECTS += ./mbed-os/events/equeue/equeue.o
+OBJECTS += ./mbed-os/events/equeue/equeue_mbed.o
+OBJECTS += ./mbed-os/events/equeue/equeue_posix.o
+OBJECTS += ./mbed-os/events/mbed_shared_queues.o
+OBJECTS += ./mbed-os/hal/mbed_flash_api.o
+OBJECTS += ./mbed-os/hal/mbed_gpio.o
+OBJECTS += ./mbed-os/hal/mbed_lp_ticker_api.o
+OBJECTS += ./mbed-os/hal/mbed_pinmap_common.o
+OBJECTS += ./mbed-os/hal/mbed_sleep_manager.o
+OBJECTS += ./mbed-os/hal/mbed_ticker_api.o
+OBJECTS += ./mbed-os/hal/mbed_us_ticker_api.o
+OBJECTS += ./mbed-os/platform/ATCmdParser.o
+OBJECTS += ./mbed-os/platform/CallChain.o
+OBJECTS += ./mbed-os/platform/FileBase.o
+OBJECTS += ./mbed-os/platform/FileHandle.o
+OBJECTS += ./mbed-os/platform/FilePath.o
+OBJECTS += ./mbed-os/platform/FileSystemHandle.o
+OBJECTS += ./mbed-os/platform/LocalFileSystem.o
+OBJECTS += ./mbed-os/platform/Stream.o
+OBJECTS += ./mbed-os/platform/mbed_alloc_wrappers.o
+OBJECTS += ./mbed-os/platform/mbed_application.o
+OBJECTS += ./mbed-os/platform/mbed_assert.o
+OBJECTS += ./mbed-os/platform/mbed_board.o
+OBJECTS += ./mbed-os/platform/mbed_critical.o
+OBJECTS += ./mbed-os/platform/mbed_error.o
+OBJECTS += ./mbed-os/platform/mbed_interface.o
+OBJECTS += ./mbed-os/platform/mbed_mem_trace.o
+OBJECTS += ./mbed-os/platform/mbed_mktime.o
+OBJECTS += ./mbed-os/platform/mbed_poll.o
+OBJECTS += ./mbed-os/platform/mbed_retarget.o
+OBJECTS += ./mbed-os/platform/mbed_rtc_time.o
+OBJECTS += ./mbed-os/platform/mbed_sdk_boot.o
+OBJECTS += ./mbed-os/platform/mbed_semihost_api.o
+OBJECTS += ./mbed-os/platform/mbed_stats.o
+OBJECTS += ./mbed-os/platform/mbed_wait_api_no_rtos.o
+OBJECTS += ./mbed-os/platform/mbed_wait_api_rtos.o
+OBJECTS += ./mbed-os/rtos/EventFlags.o
+OBJECTS += ./mbed-os/rtos/Mutex.o
+OBJECTS += ./mbed-os/rtos/RtosTimer.o
+OBJECTS += ./mbed-os/rtos/Semaphore.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/mbed_boot.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.o
+OBJECTS += ./mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.o
+OBJECTS += ./mbed-os/rtos/Thread.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/analogout_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/can_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/gpio_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/gpio_irq_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/hal_tick_16b.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/hal_tick_32b.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/i2c_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/lp_ticker.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/mbed_overrides.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/pinmap.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/port_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/pwmout_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/rtc_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/serial_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/sleep.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/stm_spi_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/trng_api.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/us_ticker_16b.o
+OBJECTS += ./mbed-os/targets/TARGET_STM/us_ticker_32b.o
+OBJECTS += ./source/DHCP_ARP.o
+OBJECTS += ./source/Eth_IPv4.o
+OBJECTS += ./source/HMI_telnet.o
+OBJECTS += ./source/L1L2_radio.o
+OBJECTS += ./source/SI4463.o
+OBJECTS += ./source/TDMA.o
+OBJECTS += ./source/Virt_Chan.o
+OBJECTS += ./source/W5500.o
+OBJECTS += ./source/config_flash.o
+OBJECTS += ./source/ext_SRAM2.o
+OBJECTS += ./source/global_variables.o
+OBJECTS += ./source/main.o
+OBJECTS += ./source/signaling.o
+
+
+INCLUDE_PATHS += -I../
+INCLUDE_PATHS += -I../.
+INCLUDE_PATHS += -I.././mbed-os
+INCLUDE_PATHS += -I.././mbed-os/cmsis
+INCLUDE_PATHS += -I.././mbed-os/cmsis/TARGET_CORTEX_M
+INCLUDE_PATHS += -I.././mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC
+INCLUDE_PATHS += -I.././mbed-os/cmsis/TOOLCHAIN_GCC
+INCLUDE_PATHS += -I.././mbed-os/drivers
+INCLUDE_PATHS += -I.././mbed-os/events
+INCLUDE_PATHS += -I.././mbed-os/events/equeue
+INCLUDE_PATHS += -I.././mbed-os/hal
+INCLUDE_PATHS += -I.././mbed-os/hal/storage_abstraction
+INCLUDE_PATHS += -I.././mbed-os/platform
+INCLUDE_PATHS += -I.././mbed-os/rtos
+INCLUDE_PATHS += -I.././mbed-os/rtos/TARGET_CORTEX
+INCLUDE_PATHS += -I.././mbed-os/rtos/TARGET_CORTEX/rtx4
+INCLUDE_PATHS += -I.././mbed-os/rtos/TARGET_CORTEX/rtx5
+INCLUDE_PATHS += -I.././mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7
+INCLUDE_PATHS += -I.././mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC
+INCLUDE_PATHS += -I.././mbed-os/targets
+INCLUDE_PATHS += -I.././mbed-os/targets/TARGET_STM
+INCLUDE_PATHS += -I.././mbed-os/targets/TARGET_STM/TARGET_STM32L4
+INCLUDE_PATHS += -I.././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC
+INCLUDE_PATHS += -I.././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC
+INCLUDE_PATHS += -I.././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device
+INCLUDE_PATHS += -I.././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM
+INCLUDE_PATHS += -I.././mbed-os/targets/TARGET_STM/TARGET_STM32L4/device
+INCLUDE_PATHS += -I.././source
+INCLUDE_PATHS += -I.././source/SI4463
+INCLUDE_PATHS += -I.././source/drivers
+INCLUDE_PATHS += -I.././source/drivers/radio
+INCLUDE_PATHS += -I.././source/drivers/radio/Si446x
+
+LIBRARY_PATHS :=
+LIBRARIES :=
+LINKER_SCRIPT ?= .././mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld
+
+# Objects and Paths
+###############################################################################
+# Tools and Flags
+
+AS      = 'arm-none-eabi-gcc' '-x' 'assembler-with-cpp' '-c' '-Wall' '-Wextra' '-Wno-unused-parameter' '-Wno-missing-field-initializers' '-fmessage-length=0' '-fno-exceptions' '-fno-builtin' '-ffunction-sections' '-fdata-sections' '-funsigned-char' '-MMD' '-fno-delete-null-pointer-checks' '-fomit-frame-pointer' '-Os' '-g1' '-DMBED_DEBUG' '-DMBED_TRAP_ERRORS_ENABLED=1' '-mcpu=cortex-m4' '-mthumb' '-mfpu=fpv4-sp-d16' '-mfloat-abi=softfp'
+CC      = 'arm-none-eabi-gcc' '-std=gnu99' '-c' '-Wall' '-Wextra' '-Wno-unused-parameter' '-Wno-missing-field-initializers' '-fmessage-length=0' '-fno-exceptions' '-fno-builtin' '-ffunction-sections' '-fdata-sections' '-funsigned-char' '-MMD' '-fno-delete-null-pointer-checks' '-fomit-frame-pointer' '-Os' '-g1' '-DMBED_DEBUG' '-DMBED_TRAP_ERRORS_ENABLED=1' '-mcpu=cortex-m4' '-mthumb' '-mfpu=fpv4-sp-d16' '-mfloat-abi=softfp'
+CPP     = 'arm-none-eabi-g++' '-std=gnu++98' '-fno-rtti' '-Wvla' '-c' '-Wall' '-Wextra' '-Wno-unused-parameter' '-Wno-missing-field-initializers' '-fmessage-length=0' '-fno-exceptions' '-fno-builtin' '-ffunction-sections' '-fdata-sections' '-funsigned-char' '-MMD' '-fno-delete-null-pointer-checks' '-fomit-frame-pointer' '-Os' '-g1' '-DMBED_DEBUG' '-DMBED_TRAP_ERRORS_ENABLED=1' '-mcpu=cortex-m4' '-mthumb' '-mfpu=fpv4-sp-d16' '-mfloat-abi=softfp'
+LD      = 'arm-none-eabi-gcc'
+ELF2BIN = 'arm-none-eabi-objcopy'
+PREPROC = 'arm-none-eabi-cpp' '-E' '-P' '-Wl,--gc-sections' '-Wl,--wrap,main' '-Wl,--wrap,_malloc_r' '-Wl,--wrap,_free_r' '-Wl,--wrap,_realloc_r' '-Wl,--wrap,_memalign_r' '-Wl,--wrap,_calloc_r' '-Wl,--wrap,exit' '-Wl,--wrap,atexit' '-Wl,-n' '-mcpu=cortex-m4' '-mthumb' '-mfpu=fpv4-sp-d16' '-mfloat-abi=softfp'
+
+
+C_FLAGS += -std=gnu99
+C_FLAGS += -D__MBED__=1
+C_FLAGS += -DDEVICE_I2CSLAVE=1
+C_FLAGS += -D__FPU_PRESENT=1
+C_FLAGS += -DDEVICE_PORTOUT=1
+C_FLAGS += -DDEVICE_PORTINOUT=1
+C_FLAGS += -DTARGET_RTOS_M4_M7
+C_FLAGS += -DDEVICE_LOWPOWERTIMER=1
+C_FLAGS += -DDEVICE_RTC=1
+C_FLAGS += -DTOOLCHAIN_object
+C_FLAGS += -D__CMSIS_RTOS
+C_FLAGS += -DTOOLCHAIN_GCC
+C_FLAGS += -DDEVICE_CAN=1
+C_FLAGS += -DTARGET_CORTEX_M
+C_FLAGS += -DTARGET_DEBUG
+C_FLAGS += -DDEVICE_I2C_ASYNCH=1
+C_FLAGS += -DTARGET_LIKE_CORTEX_M4
+C_FLAGS += -DDEVICE_ANALOGOUT=1
+C_FLAGS += -DTARGET_M4
+C_FLAGS += -DTARGET_UVISOR_UNSUPPORTED
+C_FLAGS += -DTARGET_STM32L4
+C_FLAGS += -DDEVICE_SPI_ASYNCH=1
+C_FLAGS += -DDEVICE_PWMOUT=1
+C_FLAGS += -DTARGET_STM32L432xC
+C_FLAGS += -DTARGET_CORTEX
+C_FLAGS += -DDEVICE_I2C=1
+C_FLAGS += -DTRANSACTION_QUEUE_SIZE_SPI=2
+C_FLAGS += -D__CORTEX_M4
+C_FLAGS += -DDEVICE_STDIO_MESSAGES=1
+C_FLAGS += -DTARGET_FAMILY_STM32
+C_FLAGS += -DTARGET_FF_ARDUINO
+C_FLAGS += -DDEVICE_PORTIN=1
+C_FLAGS += -DTARGET_STM
+C_FLAGS += -DTARGET_STM32L432KC
+C_FLAGS += -DDEVICE_SERIAL_FC=1
+C_FLAGS += -DMBED_BUILD_TIMESTAMP=1593423187.67
+C_FLAGS += -DDEVICE_TRNG=1
+C_FLAGS += -DTARGET_LIKE_MBED
+C_FLAGS += -D__MBED_CMSIS_RTOS_CM
+C_FLAGS += -DDEVICE_SLEEP=1
+C_FLAGS += -DTOOLCHAIN_GCC_ARM
+C_FLAGS += -DDEVICE_SPI=1
+C_FLAGS += -DDEVICE_INTERRUPTIN=1
+C_FLAGS += -DDEVICE_SPISLAVE=1
+C_FLAGS += -DDEVICE_ANALOGIN=1
+C_FLAGS += -DDEVICE_SERIAL=1
+C_FLAGS += -DDEVICE_FLASH=1
+C_FLAGS += -DTARGET_NUCLEO_L432KC
+C_FLAGS += -DARM_MATH_CM4
+C_FLAGS += -include
+C_FLAGS += mbed_config.h
+
+CXX_FLAGS += -std=gnu++98
+CXX_FLAGS += -fno-rtti
+CXX_FLAGS += -Wvla
+CXX_FLAGS += -D__MBED__=1
+CXX_FLAGS += -DDEVICE_I2CSLAVE=1
+CXX_FLAGS += -D__FPU_PRESENT=1
+CXX_FLAGS += -DDEVICE_PORTOUT=1
+CXX_FLAGS += -DDEVICE_PORTINOUT=1
+CXX_FLAGS += -DTARGET_RTOS_M4_M7
+CXX_FLAGS += -DDEVICE_LOWPOWERTIMER=1
+CXX_FLAGS += -DDEVICE_RTC=1
+CXX_FLAGS += -DTOOLCHAIN_object
+CXX_FLAGS += -D__CMSIS_RTOS
+CXX_FLAGS += -DTOOLCHAIN_GCC
+CXX_FLAGS += -DDEVICE_CAN=1
+CXX_FLAGS += -DTARGET_CORTEX_M
+CXX_FLAGS += -DTARGET_DEBUG
+CXX_FLAGS += -DDEVICE_I2C_ASYNCH=1
+CXX_FLAGS += -DTARGET_LIKE_CORTEX_M4
+CXX_FLAGS += -DDEVICE_ANALOGOUT=1
+CXX_FLAGS += -DTARGET_M4
+CXX_FLAGS += -DTARGET_UVISOR_UNSUPPORTED
+CXX_FLAGS += -DTARGET_STM32L4
+CXX_FLAGS += -DDEVICE_SPI_ASYNCH=1
+CXX_FLAGS += -DDEVICE_PWMOUT=1
+CXX_FLAGS += -DTARGET_STM32L432xC
+CXX_FLAGS += -DTARGET_CORTEX
+CXX_FLAGS += -DDEVICE_I2C=1
+CXX_FLAGS += -DTRANSACTION_QUEUE_SIZE_SPI=2
+CXX_FLAGS += -D__CORTEX_M4
+CXX_FLAGS += -DDEVICE_STDIO_MESSAGES=1
+CXX_FLAGS += -DTARGET_FAMILY_STM32
+CXX_FLAGS += -DTARGET_FF_ARDUINO
+CXX_FLAGS += -DDEVICE_PORTIN=1
+CXX_FLAGS += -DTARGET_STM
+CXX_FLAGS += -DTARGET_STM32L432KC
+CXX_FLAGS += -DDEVICE_SERIAL_FC=1
+CXX_FLAGS += -DMBED_BUILD_TIMESTAMP=1593423187.67
+CXX_FLAGS += -DDEVICE_TRNG=1
+CXX_FLAGS += -DTARGET_LIKE_MBED
+CXX_FLAGS += -D__MBED_CMSIS_RTOS_CM
+CXX_FLAGS += -DDEVICE_SLEEP=1
+CXX_FLAGS += -DTOOLCHAIN_GCC_ARM
+CXX_FLAGS += -DDEVICE_SPI=1
+CXX_FLAGS += -DDEVICE_INTERRUPTIN=1
+CXX_FLAGS += -DDEVICE_SPISLAVE=1
+CXX_FLAGS += -DDEVICE_ANALOGIN=1
+CXX_FLAGS += -DDEVICE_SERIAL=1
+CXX_FLAGS += -DDEVICE_FLASH=1
+CXX_FLAGS += -DTARGET_NUCLEO_L432KC
+CXX_FLAGS += -DARM_MATH_CM4
+CXX_FLAGS += -include
+CXX_FLAGS += mbed_config.h
+
+ASM_FLAGS += -x
+ASM_FLAGS += assembler-with-cpp
+ASM_FLAGS += -DTRANSACTION_QUEUE_SIZE_SPI=2
+ASM_FLAGS += -D__CORTEX_M4
+ASM_FLAGS += -DARM_MATH_CM4
+ASM_FLAGS += -D__FPU_PRESENT=1
+ASM_FLAGS += -D__MBED_CMSIS_RTOS_CM
+ASM_FLAGS += -D__CMSIS_RTOS
+ASM_FLAGS += -I.
+ASM_FLAGS += -I./mbed-os
+ASM_FLAGS += -I./mbed-os/cmsis
+ASM_FLAGS += -I./mbed-os/cmsis/TARGET_CORTEX_M
+ASM_FLAGS += -I./mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC
+ASM_FLAGS += -I./mbed-os/cmsis/TOOLCHAIN_GCC
+ASM_FLAGS += -I./mbed-os/drivers
+ASM_FLAGS += -I./mbed-os/events
+ASM_FLAGS += -I./mbed-os/events/equeue
+ASM_FLAGS += -I./mbed-os/hal
+ASM_FLAGS += -I./mbed-os/hal/storage_abstraction
+ASM_FLAGS += -I./mbed-os/platform
+ASM_FLAGS += -I./mbed-os/rtos
+ASM_FLAGS += -I./mbed-os/rtos/TARGET_CORTEX
+ASM_FLAGS += -I./mbed-os/rtos/TARGET_CORTEX/rtx4
+ASM_FLAGS += -I./mbed-os/rtos/TARGET_CORTEX/rtx5
+ASM_FLAGS += -I./mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7
+ASM_FLAGS += -I./mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC
+ASM_FLAGS += -I./mbed-os/targets
+ASM_FLAGS += -I./mbed-os/targets/TARGET_STM
+ASM_FLAGS += -I./mbed-os/targets/TARGET_STM/TARGET_STM32L4
+ASM_FLAGS += -I./mbed-os/targets/TARGET_STM/TARGET_STM32L4/device
+ASM_FLAGS += -I./mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC
+ASM_FLAGS += -I./mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device
+ASM_FLAGS += -I./mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM
+ASM_FLAGS += -I./mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC
+ASM_FLAGS += -I./source
+ASM_FLAGS += -I./source/drivers
+ASM_FLAGS += -I./source/drivers/radio
+ASM_FLAGS += -I./source/drivers/radio/Si446x
+ASM_FLAGS += -I./source/SI4463
+
+
+LD_FLAGS :=-Wl,--gc-sections -Wl,--wrap,main -Wl,--wrap,_malloc_r -Wl,--wrap,_free_r -Wl,--wrap,_realloc_r -Wl,--wrap,_memalign_r -Wl,--wrap,_calloc_r -Wl,--wrap,exit -Wl,--wrap,atexit -Wl,-n -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp 
+LD_SYS_LIBS :=-Wl,--start-group -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys  -Wl,--end-group
+
+# Tools and Flags
+###############################################################################
+# Rules
+
+.PHONY: all lst size
+
+
+all: $(PROJECT).bin $(PROJECT).hex size
+
+
+.s.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Assemble: $(notdir $<)"
+  
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+  
+
+
+.S.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Assemble: $(notdir $<)"
+  
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+  
+
+.c.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Compile: $(notdir $<)"
+	@$(CC) $(C_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+
+.cpp.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Compile: $(notdir $<)"
+	@$(CPP) $(CXX_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+
+
+$(PROJECT).link_script.ld: $(LINKER_SCRIPT)
+	@$(PREPROC) $< -o $@
+
+
+
+$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) $(PROJECT).link_script.ld 
+	+@echo "link: $(notdir $@)"
+	@$(LD) $(LD_FLAGS) -T $(filter-out %.o, $^) $(LIBRARY_PATHS) --output $@ $(filter %.o, $^) $(LIBRARIES) $(LD_SYS_LIBS)
+
+
+$(PROJECT).bin: $(PROJECT).elf
+	$(ELF2BIN) -O binary $< $@
+	+@echo "===== bin file ready to flash: $(OBJDIR)/$@ =====" 
+
+$(PROJECT).hex: $(PROJECT).elf
+	$(ELF2BIN) -O ihex $< $@
+
+
+# Rules
+###############################################################################
+# Dependencies
+
+DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
+-include $(DEPS)
+endif
+
+# Dependencies
+###############################################################################
diff --git a/NPR_FW_source_2020_06_29/NPR_14/gpl-3.0.txt b/NPR_FW_source_2020_06_29/NPR_14/gpl-3.0.txt
new file mode 100755
index 0000000..f288702
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/gpl-3.0.txt
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works.  By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users.  We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors.  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+  To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights.  Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received.  You must make sure that they, too, receive
+or can get the source code.  And you must show them these terms so they
+know their rights.
+
+  Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+  For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software.  For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
+authors of previous versions.
+
+  Some devices are designed to deny users access to install or run
+modified versions of the software inside them, although the manufacturer
+can do so.  This is fundamentally incompatible with the aim of
+protecting users' freedom to change the software.  The systematic
+pattern of such abuse occurs in the area of products for individuals to
+use, which is precisely where it is most unacceptable.  Therefore, we
+have designed this version of the GPL to prohibit the practice for those
+products.  If such problems arise substantially in other domains, we
+stand ready to extend this provision to those domains in future versions
+of the GPL, as needed to protect the freedom of users.
+
+  Finally, every program is threatened constantly by software patents.
+States should not allow patents to restrict development and use of
+software on general-purpose computers, but in those that do, we wish to
+avoid the special danger that patents applied to a free program could
+make it effectively proprietary.  To prevent this, the GPL assures that
+patents cannot be used to render the program non-free.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+                       TERMS AND CONDITIONS
+
+  0. Definitions.
+
+  "This License" refers to version 3 of the GNU General Public License.
+
+  "Copyright" also means copyright-like laws that apply to other kinds of
+works, such as semiconductor masks.
+
+  "The Program" refers to any copyrightable work licensed under this
+License.  Each licensee is addressed as "you".  "Licensees" and
+"recipients" may be individuals or organizations.
+
+  To "modify" a work means to copy from or adapt all or part of the work
+in a fashion requiring copyright permission, other than the making of an
+exact copy.  The resulting work is called a "modified version" of the
+earlier work or a work "based on" the earlier work.
+
+  A "covered work" means either the unmodified Program or a work based
+on the Program.
+
+  To "propagate" a work means to do anything with it that, without
+permission, would make you directly or secondarily liable for
+infringement under applicable copyright law, except executing it on a
+computer or modifying a private copy.  Propagation includes copying,
+distribution (with or without modification), making available to the
+public, and in some countries other activities as well.
+
+  To "convey" a work means any kind of propagation that enables other
+parties to make or receive copies.  Mere interaction with a user through
+a computer network, with no transfer of a copy, is not conveying.
+
+  An interactive user interface displays "Appropriate Legal Notices"
+to the extent that it includes a convenient and prominently visible
+feature that (1) displays an appropriate copyright notice, and (2)
+tells the user that there is no warranty for the work (except to the
+extent that warranties are provided), that licensees may convey the
+work under this License, and how to view a copy of this License.  If
+the interface presents a list of user commands or options, such as a
+menu, a prominent item in the list meets this criterion.
+
+  1. Source Code.
+
+  The "source code" for a work means the preferred form of the work
+for making modifications to it.  "Object code" means any non-source
+form of a work.
+
+  A "Standard Interface" means an interface that either is an official
+standard defined by a recognized standards body, or, in the case of
+interfaces specified for a particular programming language, one that
+is widely used among developers working in that language.
+
+  The "System Libraries" of an executable work include anything, other
+than the work as a whole, that (a) is included in the normal form of
+packaging a Major Component, but which is not part of that Major
+Component, and (b) serves only to enable use of the work with that
+Major Component, or to implement a Standard Interface for which an
+implementation is available to the public in source code form.  A
+"Major Component", in this context, means a major essential component
+(kernel, window system, and so on) of the specific operating system
+(if any) on which the executable work runs, or a compiler used to
+produce the work, or an object code interpreter used to run it.
+
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h
new file mode 100755
index 0000000..80f9dd9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.00
+ * @date     22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))
+  #define __ARM_ARCH_7A__           1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                  __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE           static __inline
+#endif
+#ifndef   __STATIC_ASM
+  #define __STATIC_ASM              static __asm
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN               __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+  #define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                  __attribute__((packed))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                     __breakpoint(value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  __regCPSR = cpsr;
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void) {
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
+  MOV  r1, lr
+  MSR  CPSR_C, r0
+  BX   r1
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
+{
+  MOV  sp, r0
+  BX   lr
+}
+
+/** \brief  Set Process Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  ARM
+  PRESERVE8
+
+  BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     SP, R0
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Set User Mode
+ */
+__STATIC_INLINE __ASM void __set_CPS_USR(void)
+{
+  ARM
+
+  CPS  #0x10
+  BX   LR
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+}
+
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_INLINE uint32_t __get_CPACR(void)
+{
+  register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+  return __regCPACR;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Acccess Control value to set
+ */
+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+  register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+  __regCPACR = cpacr;
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_INLINE uint32_t __get_CBAR() {
+  register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
+  return(__regCBAR);
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_INLINE uint32_t __get_TTBR0() {
+  register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+  return(__regTTBR0);
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+  register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+  __regTTBR0 = ttbr0;
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_DACR() {
+  register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+  return(__regDACR);
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+  register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+  __regDACR = dacr;
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+  register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+  __regSCTLR = sctlr;
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_INLINE uint32_t __get_SCTLR() {
+  register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+  return(__regSCTLR);
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_INLINE void __set_ACTRL(uint32_t actrl)
+{
+  register uint32_t __regACTRL         __ASM("cp15:0:c1:c0:1");
+  __regACTRL = actrl;
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_INLINE uint32_t __get_ACTRL(void)
+{
+  register uint32_t __regACTRL         __ASM("cp15:0:c1:c0:1");
+  return(__regACTRL);
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_INLINE uint32_t __get_MPIDR(void)
+{
+  register uint32_t __regMPIDR         __ASM("cp15:0:c0:c0:5");
+  return(__regMPIDR);
+}
+
+ /** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_INLINE uint32_t __get_VBAR(void)
+{
+  register uint32_t __regVBAR         __ASM("cp15:0:c12:c0:0");
+  return(__regVBAR);
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_INLINE void __set_VBAR(uint32_t vbar)
+{
+  register uint32_t __regVBAR          __ASM("cp15:0:c12:c0:0");
+  __regVBAR = vbar;
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
+  register uint32_t __regCNTP_TVAL         __ASM("cp15:0:c14:c2:0");
+  __regCNTP_TVAL = value;
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
+  register uint32_t __regCNTP_TVAL         __ASM("cp15:0:c14:c2:0");
+  return(__regCNTP_TVAL);
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
+  register uint32_t __regCNTP_CTL          __ASM("cp15:0:c14:c2:1");
+  __regCNTP_CTL = value;
+}
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_INLINE void __set_TLBIALL(uint32_t value) {
+  register uint32_t __TLBIALL              __ASM("cp15:0:c8:c7:0");
+  __TLBIALL = value;
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_INLINE void __set_BPIALL(uint32_t value) {
+  register uint32_t __BPIALL            __ASM("cp15:0:c7:c5:6");
+  __BPIALL = value;
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_INLINE void __set_ICIALLU(uint32_t value) {
+  register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
+  __ICIALLU = value;
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
+  register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
+  __DCCMVAC = value;
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
+  register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
+  __DCIMVAC = value;
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
+  register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
+  __DCCIMVAC = value;
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+ */
+#pragma push
+#pragma arm
+__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
+        ARM
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
+        ANDS    R3, R6, #0x07000000        // Extract coherency level
+        MOV     R3, R3, LSR #23            // Total cache levels << 1
+        BEQ     Finished                   // If 0, no need to clean
+
+        MOV     R10, #0                    // R10 holds current cache level << 1
+Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
+        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
+        AND     R1, R1, #7                 // Isolate those lower 3 bits
+        CMP     R1, #2
+        BLT     Skip                       // No cache or only instruction cache at this level
+
+        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
+        ISB                                // ISB to sync the change to the CacheSizeID reg
+        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
+        AND     R2, R1, #7                 // Extract the line length field
+        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
+        CLZ     R5, R4                     // R5 is the bit position of the way size increment
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
+
+Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
+
+Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
+        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
+        B       cont
+Dccsw   CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
+        B       cont
+Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
+cont    SUBS    R9, R9, #1                 // Decrement the Way number
+        BGE     Loop3
+        SUBS    R7, R7, #1                 // Decrement the Set number
+        BGE     Loop2
+Skip    ADD     R10, R10, #2               // Increment the cache number
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished
+        DSB
+        POP    {R4-R11}
+        BX     lr
+}
+#pragma pop
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+#pragma push
+#pragma arm
+__STATIC_INLINE __ASM void __FPU_Enable(void) {
+        ARM
+
+        //Permit access to VFP/NEON, registers by modifying CPACR
+        MRC     p15,0,R1,c1,c0,2
+        ORR     R1,R1,#0x00F00000
+        MCR     p15,0,R1,c1,c0,2
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+        ISB
+
+        //Enable VFP/NEON
+        VMRS    R1,FPEXC
+        ORR     R1,R1,#0x40000000
+        VMSR    FPEXC,R1
+
+        //Initialise VFP/NEON registers to 0
+        MOV     R2,#0
+  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
+        //Initialise D16 registers to 0
+        VMOV    D0, R2,R2
+        VMOV    D1, R2,R2
+        VMOV    D2, R2,R2
+        VMOV    D3, R2,R2
+        VMOV    D4, R2,R2
+        VMOV    D5, R2,R2
+        VMOV    D6, R2,R2
+        VMOV    D7, R2,R2
+        VMOV    D8, R2,R2
+        VMOV    D9, R2,R2
+        VMOV    D10,R2,R2
+        VMOV    D11,R2,R2
+        VMOV    D12,R2,R2
+        VMOV    D13,R2,R2
+        VMOV    D14,R2,R2
+        VMOV    D15,R2,R2
+  ENDIF
+  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+        //Initialise D32 registers to 0
+        VMOV    D16,R2,R2
+        VMOV    D17,R2,R2
+        VMOV    D18,R2,R2
+        VMOV    D19,R2,R2
+        VMOV    D20,R2,R2
+        VMOV    D21,R2,R2
+        VMOV    D22,R2,R2
+        VMOV    D23,R2,R2
+        VMOV    D24,R2,R2
+        VMOV    D25,R2,R2
+        VMOV    D26,R2,R2
+        VMOV    D27,R2,R2
+        VMOV    D28,R2,R2
+        VMOV    D29,R2,R2
+        VMOV    D30,R2,R2
+        VMOV    D31,R2,R2
+  ENDIF
+
+        //Initialise FPSCR to a known state
+        VMRS    R2,FPSCR
+        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        AND     R2,R2,R3
+        VMSR    FPSCR,R2
+
+        BX      LR
+}
+#pragma pop
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h
new file mode 100755
index 0000000..4006983
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h
@@ -0,0 +1,646 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.00
+ * @date     05. Apr 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                  __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE           static __inline
+#endif
+#ifndef   __STATIC_ASM
+  #define __STATIC_ASM              static __asm
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN               __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+  #define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                  __attribute__((packed))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  uint32_t result;
+  __ASM volatile("MRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+  (void)fpscr;
+#endif
+}
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __builtin_arm_wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __builtin_arm_wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __builtin_arm_sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __builtin_bswap32
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  int32_t result;
+  __ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT                            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __builtin_clz
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void) {
+    return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE void __set_mode(uint32_t mode) {
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Set Process Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile(
+    ".preserve8         \n"
+    "BIC     r0, r0, #7 \n" // ensure stack is 8-byte aligned
+    "MRS     r1, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, r0     \n"
+    "MSR     cpsr_c, r1 \n" // no effect in USR mode
+    "ISB"
+   );
+}
+
+/** \brief  Set User Mode
+ */
+__STATIC_INLINE void __set_CPS_USR(void)
+{
+  __ASM volatile("CPS  #0x10");
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("MRS %0, fpexc" : "=r" (result) );
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("MSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_INLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Acccess Control value to set
+ */
+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory");
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_INLINE uint32_t __get_CBAR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_INLINE uint32_t __get_TTBR0() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+  __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory");
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_DACR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+  __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory");
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory");
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_INLINE uint32_t __get_SCTLR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_INLINE void __set_ACTRL(uint32_t actrl)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory");
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_INLINE uint32_t __get_ACTRL(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_INLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result));
+  return result;
+}
+
+ /** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_INLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_INLINE void __set_VBAR(uint32_t vbar)
+{
+  __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory");
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_INLINE void __set_TLBIALL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_INLINE void __set_BPIALL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory");
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_INLINE void __set_ICIALLU(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+ */
+__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
+  __ASM volatile(
+    "        PUSH    {R4-R11}                   \n"
+
+    "        MRC     p15, 1, R6, c0, c0, 1      \n" // Read CLIDR
+    "        ANDS    R3, R6, #0x07000000        \n" // Extract coherency level
+    "        MOV     R3, R3, LSR #23            \n" // Total cache levels << 1
+    "        BEQ     Finished                   \n" // If 0, no need to clean
+
+    "        MOV     R10, #0                    \n" // R10 holds current cache level << 1
+    "Loop1:  ADD     R2, R10, R10, LSR #1       \n" // R2 holds cache "Set" position
+    "        MOV     R1, R6, LSR R2             \n" // Bottom 3 bits are the Cache-type for this level
+    "        AND     R1, R1, #7                 \n" // Isolate those lower 3 bits
+    "        CMP     R1, #2                     \n"
+    "        BLT     Skip                       \n" // No cache or only instruction cache at this level
+
+    "        MCR     p15, 2, R10, c0, c0, 0     \n" // Write the Cache Size selection register
+    "        ISB                                \n" // ISB to sync the change to the CacheSizeID reg
+    "        MRC     p15, 1, R1, c0, c0, 0      \n" // Reads current Cache Size ID register
+    "        AND     R2, R1, #7                 \n" // Extract the line length field
+    "        ADD     R2, R2, #4                 \n" // Add 4 for the line length offset (log2 16 bytes)
+    "        LDR     R4, =0x3FF                 \n"
+    "        ANDS    R4, R4, R1, LSR #3         \n" // R4 is the max number on the way size (right aligned)
+    "        CLZ     R5, R4                     \n" // R5 is the bit position of the way size increment
+    "        LDR     R7, =0x7FFF                \n"
+    "        ANDS    R7, R7, R1, LSR #13        \n" // R7 is the max number of the index size (right aligned)
+
+    "Loop2:  MOV     R9, R4                     \n" // R9 working copy of the max way size (right aligned)
+
+    "Loop3:  ORR     R11, R10, R9, LSL R5       \n" // Factor in the Way number and cache number into R11
+    "        ORR     R11, R11, R7, LSL R2       \n" // Factor in the Set number
+    "        CMP     R0, #0                     \n"
+    "        BNE     Dccsw                      \n"
+    "        MCR     p15, 0, R11, c7, c6, 2     \n" // DCISW. Invalidate by Set/Way
+    "        B       cont                       \n"
+    "Dccsw:  CMP     R0, #1                     \n"
+    "        BNE     Dccisw                     \n"
+    "        MCR     p15, 0, R11, c7, c10, 2    \n" // DCCSW. Clean by Set/Way
+    "        B       cont                       \n"
+    "Dccisw: MCR     p15, 0, R11, c7, c14, 2    \n" // DCCISW. Clean and Invalidate by Set/Way
+    "cont:   SUBS    R9, R9, #1                 \n" // Decrement the Way number
+    "        BGE     Loop3                      \n"
+    "        SUBS    R7, R7, #1                 \n" // Decrement the Set number
+    "        BGE     Loop2                      \n"
+    "Skip:   ADD     R10, R10, #2               \n" // Increment the cache number
+    "        CMP     R3, R10                    \n"
+    "        BGT     Loop1                      \n"
+
+    "Finished:                                  \n"
+    "        DSB                                \n"
+    "        POP    {R4-R11}                      "
+  );
+}
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void) {
+  __ASM volatile(
+        //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+        //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+        //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+#if 0 // TODO: Initialize FPU registers according to available register count
+    ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n"
+        //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+    ".endif                            \n"
+
+    ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n"
+        //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+    ".endif                            \n"
+#endif
+        //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/cmsis_compiler.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/cmsis_compiler.h
new file mode 100755
index 0000000..9fa0e0e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/cmsis_compiler.h
@@ -0,0 +1,211 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.00
+ * @date     22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+
+  #include <cmsis_iar.h>
+
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __noreturn
+  #endif
+  #ifndef   __USED
+    #define __USED                    __root
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __weak
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    __packed struct T_UINT32 { uint32_t v; };
+      #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __packed
+  #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __attribute__((aligned(x)))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __attribute__((packed))
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __packed__
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                     _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __weak
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  @packed
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_ca9.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_ca9.h
new file mode 100755
index 0000000..c7c402d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_ca9.h
@@ -0,0 +1,276 @@
+/**************************************************************************//**
+ * @file     core_ca9.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date     25 March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA9_H_GENERIC
+#define __CORE_CA9_H_GENERIC
+
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_A9
+  @{
+ */
+
+/*  CMSIS CA9 definitions */
+#define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \
+                                    __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+  #define __STATIC_ASM     static __asm
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#include <stdint.h>
+inline uint32_t __get_PSR(void) {
+	__ASM("mrs r0, cpsr");
+}
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /*!< standard types definitions                      */
+#include "core_caInstr.h"                /*!< Core Instruction Access                         */
+#include "core_caFunc.h"                 /*!< Core Function Access                            */
+#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CA9_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA9_H_DEPENDANT
+#define __CORE_CA9_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CA9_REV
+    #define __CA9_REV               0x0000
+    #warning "__CA9_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             1
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    1
+  #endif
+
+  #if __Vendor_SysTickConfig == 0
+    #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_A9 */
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-A processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */ 
+} APSR_Type;
+
+
+/*@} end of group CMSIS_CORE */
+
+/*@} end of CMSIS_Core_FPUFunctions */
+
+
+#endif /* __CORE_CA9_H_GENERIC */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_caFunc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_caFunc.h
new file mode 100755
index 0000000..6e47321
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_caFunc.h
@@ -0,0 +1,1444 @@
+/**************************************************************************//**
+ * @file     core_caFunc.h
+ * @brief    CMSIS Cortex-A Core Function Access Header File
+ * @version  V3.10
+ * @date     30 Oct 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CAFUNC_H__
+#define __CORE_CAFUNC_H__
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_MON 0x16
+#define MODE_ABT 0x17
+#define MODE_HYP 0x1A
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get CPSR Register
+
+    This function returns the content of the CPSR Register.
+
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+/** \brief  Set Stack Pointer
+
+    This function assigns the given value to the current stack pointer.
+
+    \param [in]    topOfStack  Stack Pointer value to set
+ */
+register uint32_t __regSP              __ASM("sp");
+__STATIC_INLINE void __set_SP(uint32_t topOfStack)
+{
+    __regSP = topOfStack;
+}
+
+
+/** \brief  Get link register
+
+    This function returns the value of the link register
+
+    \return    Value of link register
+ */
+register uint32_t __reglr         __ASM("lr");
+__STATIC_INLINE uint32_t __get_LR(void)
+{
+  return(__reglr);
+}
+
+/** \brief  Set link register
+
+    This function sets the value of the link register
+
+    \param [in]    lr  LR value to set
+ */
+__STATIC_INLINE void __set_LR(uint32_t lr)
+{
+  __reglr = lr;
+}
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
+{
+    ARM
+    PRESERVE8
+
+    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
+    MRS     R1, CPSR
+    CPS     #MODE_SYS   ;no effect in USR mode
+    MOV     SP, R0
+    MSR     CPSR_c, R1  ;no effect in USR mode
+    ISB
+    BX      LR
+
+}
+
+/** \brief  Set User Mode
+
+    This function changes the processor state to User Mode
+ */
+__STATIC_ASM void __set_CPS_USR(void)
+{
+    ARM 
+
+    CPS  #MODE_USR  
+    BX   LR
+}
+
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+/** \brief  Get FPEXC
+
+    This function returns the current value of the Floating Point Exception Control register.
+
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPEXC
+
+    This function assigns the given value to the Floating Point Exception Control register.
+
+    \param [in]    fpscr  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+}
+
+/** \brief  Get CPACR
+
+    This function returns the current value of the Coprocessor Access Control register.
+
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_INLINE uint32_t __get_CPACR(void)
+{
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+    return __regCPACR;
+}
+
+/** \brief  Set CPACR
+
+    This function assigns the given value to the Coprocessor Access Control register.
+
+    \param [in]    cpacr  Coprocessor Acccess Control value to set
+ */
+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+    __regCPACR = cpacr;
+    __ISB();
+}
+
+/** \brief  Get CBAR
+
+    This function returns the value of the Configuration Base Address register.
+
+    \return               Configuration Base Address register value
+ */
+__STATIC_INLINE uint32_t __get_CBAR() {
+    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
+    return(__regCBAR);
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_INLINE uint32_t __get_TTBR0() {
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+    return(__regTTBR0);
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+    __regTTBR0 = ttbr0;
+    __ISB();
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_DACR() {
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+    return(__regDACR);
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+    __regDACR = dacr;
+    __ISB();
+}
+
+/******************************** Cache and BTAC enable  ****************************************************/
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+    __regSCTLR = sctlr;
+}
+
+/** \brief  Get SCTLR
+
+    This function returns the value of the System Control Register.
+
+    \return               System Control Register value
+ */
+__STATIC_INLINE uint32_t __get_SCTLR() {
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+    return(__regSCTLR);
+}
+
+/** \brief  Enable Caches
+
+    Enable Caches
+ */
+__STATIC_INLINE void __enable_caches(void) {
+    // Set I bit 12 to enable I Cache
+    // Set C bit  2 to enable D Cache
+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Disable Caches
+
+    Disable Caches
+ */
+__STATIC_INLINE void __disable_caches(void) {
+    // Clear I bit 12 to disable I Cache
+    // Clear C bit  2 to disable D Cache
+    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
+    __ISB();
+}
+
+/** \brief  Enable BTAC
+
+    Enable BTAC
+ */
+__STATIC_INLINE void __enable_btac(void) {
+    // Set Z bit 11 to enable branch prediction
+    __set_SCTLR( __get_SCTLR() | (1 << 11));
+    __ISB();
+}
+
+/** \brief  Disable BTAC
+
+    Disable BTAC
+ */
+__STATIC_INLINE void __disable_btac(void) {
+    // Clear Z bit 11 to disable branch prediction
+    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
+}
+
+
+/** \brief  Enable MMU
+
+    Enable MMU
+ */
+__STATIC_INLINE void __enable_mmu(void) {
+    // Set M bit 0 to enable the MMU
+    // Set AFE bit to enable simplified access permissions model
+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+    __ISB();
+}
+
+/** \brief  Disable MMU
+
+    Disable MMU
+ */
+__STATIC_INLINE void __disable_mmu(void) {
+    // Clear M bit 0 to disable the MMU
+    __set_SCTLR( __get_SCTLR() & ~1);
+    __ISB();
+}
+
+/******************************** TLB maintenance operations ************************************************/
+/** \brief  Invalidate the whole tlb
+
+    TLBIALL. Invalidate the whole tlb
+ */
+
+__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
+    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
+    __TLBIALL = 0;
+    __DSB();
+    __ISB();
+}
+
+/******************************** BTB maintenance operations ************************************************/
+/** \brief  Invalidate entire branch predictor array
+
+    BPIALL. Branch Predictor Invalidate All.
+ */
+
+__STATIC_INLINE void __v7_inv_btac(void) {
+    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
+    __BPIALL  = 0;
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+/******************************** L1 cache operations ******************************************************/
+
+/** \brief  Invalidate the whole I$
+
+    ICIALLU. Instruction Cache Invalidate All to PoU
+ */
+__STATIC_INLINE void __v7_inv_icache_all(void) {
+    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
+    __ICIALLU = 0;
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean D$ by MVA
+
+    DCCMVAC. Data cache clean by MVA to PoC
+ */
+__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
+    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
+    __DCCMVAC = (uint32_t)va;
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate D$ by MVA
+
+    DCIMVAC. Data cache invalidate by MVA to PoC
+ */
+__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
+    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
+    __DCIMVAC = (uint32_t)va;
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate D$ by MVA
+
+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+ */
+__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
+    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
+    __DCCIMVAC = (uint32_t)va;
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+ */
+#pragma push
+#pragma arm
+__STATIC_ASM void __v7_all_cache(uint32_t op) {
+        ARM 
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
+        ANDS    R3, R6, #0x07000000        // Extract coherency level
+        MOV     R3, R3, LSR #23            // Total cache levels << 1
+        BEQ     Finished                   // If 0, no need to clean
+
+        MOV     R10, #0                    // R10 holds current cache level << 1
+Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
+        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
+        AND     R1, R1, #7                 // Isolate those lower 3 bits
+        CMP     R1, #2
+        BLT     Skip                       // No cache or only instruction cache at this level
+
+        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
+        ISB                                // ISB to sync the change to the CacheSizeID reg
+        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
+        AND     R2, R1, #7                 // Extract the line length field
+        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
+        CLZ     R5, R4                     // R5 is the bit position of the way size increment
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
+
+Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
+
+Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
+        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
+        B       cont
+Dccsw   CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
+        B       cont
+Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
+cont    SUBS    R9, R9, #1                 // Decrement the Way number
+        BGE     Loop3
+        SUBS    R7, R7, #1                 // Decrement the Set number
+        BGE     Loop2
+Skip    ADD     R10, R10, #2               // Increment the cache number
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+}
+#pragma pop
+
+
+/** \brief  Invalidate the whole D$
+
+    DCISW. Invalidate by Set/Way
+ */
+
+__STATIC_INLINE void __v7_inv_dcache_all(void) {
+    __v7_all_cache(0);
+}
+
+/** \brief  Clean the whole D$
+
+    DCCSW. Clean by Set/Way
+ */
+
+__STATIC_INLINE void __v7_clean_dcache_all(void) {
+    __v7_all_cache(1);
+}
+
+/** \brief  Clean and invalidate the whole D$
+
+    DCCISW. Clean and Invalidate by Set/Way
+ */
+
+__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
+    __v7_all_cache(2);
+}
+
+#include "core_ca_mmu.h"
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+
+#define __inline inline
+
+inline static uint32_t __disable_irq_iar() {
+  int irq_dis = __get_CPSR() & 0x80;      // 7bit CPSR.I
+  __disable_irq();
+  return irq_dis;
+}
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_MON 0x16
+#define MODE_ABT 0x17
+#define MODE_HYP 0x1A
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+// from rt_CMSIS.c
+__arm static inline void __set_PSP(uint32_t topOfProcStack) {
+__asm(
+  "    ARM\n"
+//  "    PRESERVE8\n"
+
+  "    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned \n"
+  "    MRS     R1, CPSR \n"
+  "    CPS     #0x1F   ;no effect in USR mode \n"        // MODE_SYS
+  "    MOV     SP, R0 \n"
+  "    MSR     CPSR_c, R1  ;no effect in USR mode \n"
+  "    ISB \n"
+  "    BX      LR \n");
+}
+
+/** \brief  Set User Mode
+
+    This function changes the processor state to User Mode
+ */
+// from rt_CMSIS.c
+__arm static inline void __set_CPS_USR(void) {
+__asm(
+  "    ARM \n"
+
+  "    CPS  #0x10  \n"                  // MODE_USR
+  "    BX   LR\n");
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+// from mmu_Renesas_RZ_A1.c
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+    __MCR(15, 0, ttbr0, 2, 0, 0);      // reg to cp15
+    __ISB();
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+// from mmu_Renesas_RZ_A1.c
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+    __MCR(15, 0, dacr, 3, 0, 0);      // reg to cp15
+    __ISB();
+}
+
+
+/******************************** Cache and BTAC enable  ****************************************************/
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+// from __enable_mmu()
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
+    __MCR(15, 0, sctlr, 1, 0, 0);      // reg to cp15
+}
+
+/** \brief  Get SCTLR
+
+    This function returns the value of the System Control Register.
+
+    \return               System Control Register value
+ */
+// from __enable_mmu()
+__STATIC_INLINE uint32_t __get_SCTLR() {
+	uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
+	return __regSCTLR;
+}
+
+/** \brief  Enable Caches
+
+    Enable Caches
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_caches(void) {
+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Enable BTAC
+
+    Enable BTAC
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_btac(void) {
+    __set_SCTLR( __get_SCTLR() | (1 << 11));
+    __ISB();
+}
+
+/** \brief  Enable MMU
+
+    Enable MMU
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_mmu(void) {
+    // Set M bit 0 to enable the MMU
+    // Set AFE bit to enable simplified access permissions model
+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+    __ISB();
+}
+
+/******************************** TLB maintenance operations ************************************************/
+/** \brief  Invalidate the whole tlb
+
+    TLBIALL. Invalidate the whole tlb
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 8, 7, 0);      // reg to cp15
+    __MCR(15, 0, val, 8, 6, 0);      // reg to cp15
+    __MCR(15, 0, val, 8, 5, 0);      // reg to cp15
+    __DSB();
+    __ISB();
+}
+
+/******************************** BTB maintenance operations ************************************************/
+/** \brief  Invalidate entire branch predictor array
+
+    BPIALL. Branch Predictor Invalidate All.
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_btac(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 7, 5, 6);      // reg to cp15
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+/******************************** L1 cache operations ******************************************************/
+
+/** \brief  Invalidate the whole I$
+
+    ICIALLU. Instruction Cache Invalidate All to PoU
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_icache_all(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 7, 5, 0);      // reg to cp15
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+// from __v7_inv_dcache_all()
+__arm static inline void __v7_all_cache(uint32_t op) {
+__asm(
+	"        ARM \n"
+
+	"        PUSH    {R4-R11} \n"
+
+	"        MRC     p15, 1, R6, c0, c0, 1\n"      // Read CLIDR
+	"        ANDS    R3, R6, #0x07000000\n"        // Extract coherency level
+	"        MOV     R3, R3, LSR #23\n"            // Total cache levels << 1
+	"        BEQ     Finished\n"                   // If 0, no need to clean
+
+	"        MOV     R10, #0\n"                    // R10 holds current cache level << 1
+    "Loop1:   ADD     R2, R10, R10, LSR #1\n"       // R2 holds cache "Set" position
+	"        MOV     R1, R6, LSR R2 \n"            // Bottom 3 bits are the Cache-type for this level
+	"        AND     R1, R1, #7 \n"                // Isolate those lower 3 bits
+	"        CMP     R1, #2 \n"
+	"        BLT     Skip \n"                      // No cache or only instruction cache at this level
+
+	"        MCR     p15, 2, R10, c0, c0, 0 \n"    // Write the Cache Size selection register
+	"        ISB \n"                               // ISB to sync the change to the CacheSizeID reg
+	"        MRC     p15, 1, R1, c0, c0, 0 \n"     // Reads current Cache Size ID register
+	"        AND     R2, R1, #7 \n"                // Extract the line length field
+	"        ADD     R2, R2, #4 \n"                // Add 4 for the line length offset (log2 16 bytes)
+	"        movw    R4, #0x3FF \n"
+	"        ANDS    R4, R4, R1, LSR #3 \n"        // R4 is the max number on the way size (right aligned)
+	"        CLZ     R5, R4 \n"                    // R5 is the bit position of the way size increment
+	"        movw    R7, #0x7FFF \n"
+	"        ANDS    R7, R7, R1, LSR #13 \n"       // R7 is the max number of the index size (right aligned)
+
+	"Loop2:   MOV     R9, R4 \n"                    // R9 working copy of the max way size (right aligned)
+
+	"Loop3:   ORR     R11, R10, R9, LSL R5 \n"      // Factor in the Way number and cache number into R11
+	"        ORR     R11, R11, R7, LSL R2 \n"      // Factor in the Set number
+	"        CMP     R0, #0 \n"
+	"        BNE     Dccsw \n"
+	"        MCR     p15, 0, R11, c7, c6, 2 \n"    // DCISW. Invalidate by Set/Way
+	"        B       cont \n"
+	"Dccsw:   CMP     R0, #1 \n"
+	"        BNE     Dccisw \n"
+	"        MCR     p15, 0, R11, c7, c10, 2 \n"   // DCCSW. Clean by Set/Way
+	"        B       cont \n"
+	"Dccisw:  MCR     p15, 0, R11, c7, c14, 2 \n"   // DCCISW, Clean and Invalidate by Set/Way
+	"cont:    SUBS    R9, R9, #1 \n"                // Decrement the Way number
+	"        BGE     Loop3 \n"
+	"        SUBS    R7, R7, #1 \n"                // Decrement the Set number
+	"        BGE     Loop2 \n"
+	"Skip:    ADD     R10, R10, #2 \n"              // increment the cache number
+	"        CMP     R3, R10 \n"
+	"        BGT     Loop1 \n"
+
+	"Finished: \n"
+	"        DSB \n"
+	"        POP    {R4-R11} \n"
+	"        BX     lr \n" );
+}
+
+/** \brief  Invalidate the whole D$
+
+    DCISW. Invalidate by Set/Way
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_dcache_all(void) {
+    __v7_all_cache(0);
+}
+/** \brief  Clean the whole D$
+
+    DCCSW. Clean by Set/Way
+ */
+
+__STATIC_INLINE void __v7_clean_dcache_all(void) {
+    __v7_all_cache(1);
+}
+
+/** \brief  Clean and invalidate the whole D$
+
+    DCCISW. Clean and Invalidate by Set/Way
+ */
+
+__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
+    __v7_all_cache(2);
+}
+/** \brief  Clean and Invalidate D$ by MVA
+
+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+ */
+__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
+    __MCR(15, 0, (uint32_t)va, 7, 14, 1);
+    __DMB();
+}
+
+#include "core_ca_mmu.h"
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_MON 0x16
+#define MODE_ABT 0x17
+#define MODE_HYP 0x1A
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile ("cpsie i");
+}
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("mrs %0, cpsr" : "=r" (result));
+    __ASM volatile ("cpsid i");
+    return(result & 0x80);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+#if 1
+  register uint32_t __regAPSR;
+  __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
+#else
+  register uint32_t __regAPSR          __ASM("apsr");
+#endif
+  return(__regAPSR);
+}
+
+
+/** \brief  Get CPSR Register
+
+    This function returns the content of the CPSR Register.
+
+    \return               CPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
+{
+#if 1
+  register uint32_t __regCPSR;
+  __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
+#else
+  register uint32_t __regCPSR          __ASM("cpsr");
+#endif
+  return(__regCPSR);
+}
+
+#if 0
+/** \brief  Set Stack Pointer
+
+    This function assigns the given value to the current stack pointer.
+
+    \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
+{
+    register uint32_t __regSP       __ASM("sp");
+    __regSP = topOfStack;
+}
+#endif
+
+/** \brief  Get link register
+
+    This function returns the value of the link register
+
+    \return    Value of link register
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
+{
+  register uint32_t __reglr         __ASM("lr");
+  return(__reglr);
+}
+
+#if 0
+/** \brief  Set link register
+
+    This function sets the value of the link register
+
+    \param [in]    lr  LR value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
+{
+  register uint32_t __reglr         __ASM("lr");
+  __reglr = lr;
+}
+#endif
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __asm__ volatile (
+    ".ARM;"
+    ".eabi_attribute Tag_ABI_align8_preserved,1;"
+
+    "BIC     R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
+    "MRS     R1, CPSR;"
+    "CPS     %0;"         /* ;no effect in USR mode */
+    "MOV     SP, R0;"
+    "MSR     CPSR_c, R1;" /* ;no effect in USR mode */
+    "ISB;"
+    //"BX      LR;"
+    :
+    : "i"(MODE_SYS)
+    : "r0", "r1");
+    return;
+}
+
+/** \brief  Set User Mode
+
+    This function changes the processor state to User Mode
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
+{
+    __asm__ volatile (
+    ".ARM;"
+
+    "CPS  %0;"
+    //"BX   LR;"
+    :
+    : "i"(MODE_USR)
+    : );
+    return;
+}
+
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq()                __asm__ volatile ("cpsie f")
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq()               __asm__ volatile ("cpsid f")
+
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+#if 1
+    uint32_t result;
+
+    __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
+    return (result);
+#else
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#endif
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+#if 1
+    __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
+#else
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+#endif
+}
+
+/** \brief  Get FPEXC
+
+    This function returns the current value of the Floating Point Exception Control register.
+
+    \return               Floating Point Exception Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+#if 1
+    uint32_t result;
+
+    __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
+    return (result);
+#else
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#endif
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPEXC
+
+    This function assigns the given value to the Floating Point Exception Control register.
+
+    \param [in]    fpscr  Floating Point Exception Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+#if 1
+    __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
+#else
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+#endif
+}
+
+/** \brief  Get CPACR
+
+    This function returns the current value of the Coprocessor Access Control register.
+
+    \return               Coprocessor Access Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
+{
+#if 1
+    register uint32_t __regCPACR;
+    __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
+#else
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+#endif
+    return __regCPACR;
+}
+
+/** \brief  Set CPACR
+
+    This function assigns the given value to the Coprocessor Access Control register.
+
+    \param [in]    cpacr  Coprocessor Acccess Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
+#else
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+    __regCPACR = cpacr;
+#endif
+    __ISB();
+}
+
+/** \brief  Get CBAR
+
+    This function returns the value of the Configuration Base Address register.
+
+    \return               Configuration Base Address register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
+#if 1
+    register uint32_t __regCBAR;
+    __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
+#else
+    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
+#endif
+    return(__regCBAR);
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
+#if 1
+    register uint32_t __regTTBR0;
+    __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
+#else
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+#endif
+    return(__regTTBR0);
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
+#else
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+    __regTTBR0 = ttbr0;
+#endif
+    __ISB();
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
+#if 1
+    register uint32_t __regDACR;
+    __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
+#else
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+#endif
+    return(__regDACR);
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
+#else
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+    __regDACR = dacr;
+#endif
+    __ISB();
+}
+
+/******************************** Cache and BTAC enable  ****************************************************/
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
+#else
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+    __regSCTLR = sctlr;
+#endif
+}
+
+/** \brief  Get SCTLR
+
+    This function returns the value of the System Control Register.
+
+    \return               System Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
+#if 1
+	register uint32_t __regSCTLR;
+	__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
+#else
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+#endif
+    return(__regSCTLR);
+}
+
+/** \brief  Enable Caches
+
+    Enable Caches
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
+    // Set I bit 12 to enable I Cache
+    // Set C bit  2 to enable D Cache
+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Disable Caches
+
+    Disable Caches
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
+    // Clear I bit 12 to disable I Cache
+    // Clear C bit  2 to disable D Cache
+    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
+    __ISB();
+}
+
+/** \brief  Enable BTAC
+
+    Enable BTAC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
+    // Set Z bit 11 to enable branch prediction
+    __set_SCTLR( __get_SCTLR() | (1 << 11));
+    __ISB();
+}
+
+/** \brief  Disable BTAC
+
+    Disable BTAC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
+    // Clear Z bit 11 to disable branch prediction
+    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
+}
+
+
+/** \brief  Enable MMU
+
+    Enable MMU
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
+    // Set M bit 0 to enable the MMU
+    // Set AFE bit to enable simplified access permissions model
+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+    __ISB();
+}
+
+/** \brief  Disable MMU
+
+    Disable MMU
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
+    // Clear M bit 0 to disable the MMU
+    __set_SCTLR( __get_SCTLR() & ~1);
+    __ISB();
+}
+
+/******************************** TLB maintenance operations ************************************************/
+/** \brief  Invalidate the whole tlb
+
+    TLBIALL. Invalidate the whole tlb
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
+#else
+    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
+    __TLBIALL = 0;
+#endif
+    __DSB();
+    __ISB();
+}
+
+/******************************** BTB maintenance operations ************************************************/
+/** \brief  Invalidate entire branch predictor array
+
+    BPIALL. Branch Predictor Invalidate All.
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
+#else
+    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
+    __BPIALL  = 0;
+#endif
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+/******************************** L1 cache operations ******************************************************/
+
+/** \brief  Invalidate the whole I$
+
+    ICIALLU. Instruction Cache Invalidate All to PoU
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+#else
+    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
+    __ICIALLU = 0;
+#endif
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean D$ by MVA
+
+    DCCMVAC. Data cache clean by MVA to PoC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
+#else
+    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
+    __DCCMVAC = (uint32_t)va;
+#endif
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate D$ by MVA
+
+    DCIMVAC. Data cache invalidate by MVA to PoC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
+#else
+    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
+    __DCIMVAC = (uint32_t)va;
+#endif
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate D$ by MVA
+
+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
+#else
+    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
+    __DCCIMVAC = (uint32_t)va;
+#endif
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+ */
+extern void __v7_all_cache(uint32_t op);
+
+
+/** \brief  Invalidate the whole D$
+
+    DCISW. Invalidate by Set/Way
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
+    __v7_all_cache(0);
+}
+
+/** \brief  Clean the whole D$
+
+    DCCSW. Clean by Set/Way
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
+    __v7_all_cache(1);
+}
+
+/** \brief  Clean and invalidate the whole D$
+
+    DCCISW. Clean and Invalidate by Set/Way
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
+    __v7_all_cache(2);
+}
+
+#include "core_ca_mmu.h"
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+
+#error TASKING Compiler support not implemented for Cortex-A
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CAFUNC_H__ */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_caInstr.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_caInstr.h
new file mode 100755
index 0000000..b1d3435
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_caInstr.h
@@ -0,0 +1,45 @@
+/**************************************************************************//**
+ * @file     core_caInstr.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date     04. December 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef __CORE_CAINSTR_H__
+#define __CORE_CAINSTR_H__
+
+#define __CORTEX_M 0x3
+#include "core_cmInstr.h"
+#undef  __CORTEX_M
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_ca_mmu.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_ca_mmu.h
new file mode 100755
index 0000000..189b073
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_ca_mmu.h
@@ -0,0 +1,847 @@
+;/**************************************************************************//**
+; * @file     core_ca_mmu.h
+; * @brief    MMU Startup File for A9_MP Device Series
+; * @version  V1.01
+; * @date     10 Sept 2014
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2012-2014 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef _MMU_FUNC_H
+#define _MMU_FUNC_H
+
+#define SECTION_DESCRIPTOR      (0x2)
+#define SECTION_MASK            (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
+#define SECTION_B_SHIFT         (2)
+#define SECTION_C_SHIFT         (3)
+#define SECTION_TEX0_SHIFT      (12)
+#define SECTION_TEX1_SHIFT      (13)
+#define SECTION_TEX2_SHIFT      (14)
+
+#define SECTION_XN_MASK         (0xFFFFFFEF)
+#define SECTION_XN_SHIFT        (4)
+
+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT    (5)
+
+#define SECTION_P_MASK          (0xFFFFFDFF)
+#define SECTION_P_SHIFT         (9)
+
+#define SECTION_AP_MASK         (0xFFFF73FF)
+#define SECTION_AP_SHIFT        (10)
+#define SECTION_AP2_SHIFT       (15)
+
+#define SECTION_S_MASK          (0xFFFEFFFF)
+#define SECTION_S_SHIFT         (16)
+
+#define SECTION_NG_MASK         (0xFFFDFFFF)
+#define SECTION_NG_SHIFT        (17)
+
+#define SECTION_NS_MASK         (0xFFF7FFFF)
+#define SECTION_NS_SHIFT        (19)
+
+
+#define PAGE_L1_DESCRIPTOR      (0x1)
+#define PAGE_L1_MASK            (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC         (0x2)
+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC        (0x1)
+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT         (2)
+#define PAGE_4K_C_SHIFT         (3)
+#define PAGE_4K_TEX0_SHIFT      (6)
+#define PAGE_4K_TEX1_SHIFT      (7)
+#define PAGE_4K_TEX2_SHIFT      (8)
+
+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT        (2)
+#define PAGE_64K_C_SHIFT        (3)
+#define PAGE_64K_TEX0_SHIFT     (12)
+#define PAGE_64K_TEX1_SHIFT     (13)
+#define PAGE_64K_TEX2_SHIFT     (14)
+
+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
+#define PAGE_B_SHIFT            (2)
+#define PAGE_C_SHIFT            (3)
+#define PAGE_TEX_SHIFT          (12)
+
+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT        (0)
+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT       (15)
+
+
+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT       (5)
+
+#define PAGE_P_MASK             (0xFFFFFDFF)
+#define PAGE_P_SHIFT            (9)
+
+#define PAGE_AP_MASK            (0xFFFFFDCF)
+#define PAGE_AP_SHIFT           (4)
+#define PAGE_AP2_SHIFT          (9)
+
+#define PAGE_S_MASK             (0xFFFFFBFF)
+#define PAGE_S_SHIFT            (10)
+
+#define PAGE_NG_MASK            (0xFFFFF7FF)
+#define PAGE_NG_SHIFT           (11)
+
+#define PAGE_NS_MASK            (0xFFFFFFF7)
+#define PAGE_NS_SHIFT           (3)
+
+#define OFFSET_1M               (0x00100000)
+#define OFFSET_64K              (0x00010000)
+#define OFFSET_4K               (0x00001000)
+
+#define DESCRIPTOR_FAULT        (0x00000000)
+
+/* ###########################  MMU Function Access  ########################### */
+/** \ingroup  MMU_FunctionInterface
+    \defgroup MMU_Functions MMU Functions Interface
+  @{
+ */
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+   SECTION,
+   PAGE_4k,
+   PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+   NORMAL,
+   DEVICE,
+   SHARED_DEVICE,
+   NON_SHARED_DEVICE,
+   STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+   NON_CACHEABLE,
+   WB_WA,
+   WT,
+   WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+   ECC_DISABLED,
+   ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+   EXECUTE,
+   NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+   GLOBAL,
+   NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+   NON_SHARED,
+   SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+   SECURE,
+   NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+   NO_ACCESS,
+   RW,
+   READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+    mmu_region_size_Type rg_t;
+    mmu_memory_Type mem_t;
+    uint8_t domain;
+    mmu_cacheability_Type inner_norm_t;
+    mmu_cacheability_Type outer_norm_t;
+    mmu_ecc_check_Type e_t;
+    mmu_execute_Type xn_t;
+    mmu_global_Type g_t;
+    mmu_secure_Type sec_t;
+    mmu_access_Type priv_t;
+    mmu_access_Type user_t;
+    mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+/** \brief  Set section execution-never attribute
+
+    The function sets section execution-never attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+    \return          0  
+ */
+__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+    *descriptor_l1 &= SECTION_XN_MASK;
+    *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section domain
+
+    The function sets section domain
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]            domain  Section domain
+
+    \return          0  
+ */
+__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
+{
+    *descriptor_l1 &= SECTION_DOMAIN_MASK;
+    *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section parity check
+
+    The function sets section parity check
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+    \return          0  
+ */
+__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+    *descriptor_l1 &= SECTION_P_MASK;
+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section access privileges
+
+    The function sets section access privileges
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+    \param [in]               afe  Access flag enable
+
+    \return          0  
+ */
+__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
+{
+    uint32_t ap = 0;
+
+    if (afe == 0) { //full access
+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+    }
+
+    else { //Simplified access
+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+    }
+
+    *descriptor_l1 &= SECTION_AP_MASK;
+    *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+    *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+    return 0;
+}
+
+/** \brief  Set section shareability
+
+    The function sets section shareability
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
+
+    \return          0  
+ */
+__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+    *descriptor_l1 &= SECTION_S_MASK;
+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section Global attribute
+
+    The function sets section Global attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
+
+    \return          0  
+ */
+__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+    *descriptor_l1 &= SECTION_NG_MASK;
+    *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section Security attribute
+
+    The function sets section Global attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
+
+    \return          0  
+ */
+__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+    *descriptor_l1 &= SECTION_NS_MASK;
+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+    return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief  Set 4k/64k page execution-never attribute
+
+    The function sets 4k/64k page execution-never attribute
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
+    \param [in]              page  Page size: PAGE_4k, PAGE_64k,
+   
+    \return          0  
+ */
+__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+    if (page == PAGE_4k)
+    {
+        *descriptor_l2 &= PAGE_XN_4K_MASK;
+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+    }
+    else
+    {
+        *descriptor_l2 &= PAGE_XN_64K_MASK;
+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+    }
+    return 0;
+}
+
+/** \brief  Set 4k/64k page domain
+
+    The function sets 4k/64k page domain
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]            domain  Page domain
+
+    \return          0  
+ */
+__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
+{
+    *descriptor_l1 &= PAGE_DOMAIN_MASK;
+    *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page parity check
+
+    The function sets 4k/64k page parity check
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+    \return          0  
+ */
+__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+    *descriptor_l1 &= SECTION_P_MASK;
+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page access privileges
+
+    The function sets 4k/64k page access privileges
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+    \param [in]               afe  Access flag enable
+
+    \return          0  
+ */
+__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
+{
+    uint32_t ap = 0;
+
+    if (afe == 0) { //full access
+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x6; }
+    }
+
+    else { //Simplified access
+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+    }
+
+    *descriptor_l2 &= PAGE_AP_MASK;
+    *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+    *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+    return 0;
+}
+
+/** \brief  Set 4k/64k page shareability
+
+    The function sets 4k/64k page shareability
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
+
+    \return          0  
+ */
+__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+    *descriptor_l2 &= PAGE_S_MASK;
+    *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page Global attribute
+
+    The function sets 4k/64k page Global attribute
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+    \return          0  
+ */
+__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+    *descriptor_l2 &= PAGE_NG_MASK;
+    *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page Security attribute
+
+    The function sets 4k/64k page Global attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
+
+    \return          0  
+ */
+__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+    *descriptor_l1 &= PAGE_NS_MASK;
+    *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+    return 0;
+}
+
+
+/** \brief  Set Section memory attributes
+
+    The function sets section memory attributes
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+    \return          0  
+ */
+__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+    *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+    if (STRONGLY_ORDERED == mem)
+    {
+        return 0;
+    }
+    else if (SHARED_DEVICE == mem)
+    {
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+    }
+    else if (NON_SHARED_DEVICE == mem)
+    {
+        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+    }
+    else if (NORMAL == mem)
+    {
+           *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+           switch(inner)
+           {
+            case NON_CACHEABLE:
+            break;
+            case WB_WA:
+                *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+                break;
+            case WT:
+                *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+                break;
+            case WB_NO_WA:
+                *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+                break;
+        }
+        switch(outer)
+        {
+            case NON_CACHEABLE:
+             break;
+            case WB_WA:
+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+                break;
+            case WT:
+                *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+                break;
+            case WB_NO_WA:
+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+                break;
+        }
+    }
+
+    return 0;
+}
+
+/** \brief  Set 4k/64k page memory attributes
+
+    The function sets 4k/64k page memory attributes
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+    \return          0  
+ */
+__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+    *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+    if (page == PAGE_64k)
+    {
+        //same as section
+        __memory_section(descriptor_l2, mem, outer, inner);
+    }
+    else
+    {
+        if (STRONGLY_ORDERED == mem)
+        {
+            return 0;
+        }
+        else if (SHARED_DEVICE == mem)
+        {
+            *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+        }
+        else if (NON_SHARED_DEVICE == mem)
+        {
+             *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+        }
+        else if (NORMAL == mem)
+        {
+            *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+            switch(inner)
+            {
+                case NON_CACHEABLE:
+                break;
+                case WB_WA:
+                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+                     break;
+                case WT:
+                    *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+                     break;
+                case WB_NO_WA:
+                    *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+                    break;
+            }
+            switch(outer)
+            {
+                case NON_CACHEABLE:
+                break;
+                case WB_WA:
+                      *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+                    break;
+                case WT:
+                     *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+                    break;
+                case WB_NO_WA:
+                    *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+                    break;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/** \brief  Create a L1 section descriptor
+
+    The function creates a section descriptor.
+    
+    Assumptions:
+    - 16MB super sections not supported
+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
+    - Functions always return 0
+
+    \param [out]       descriptor  L1 descriptor
+    \param [out]      descriptor2  L2 descriptor
+    \param [in]               reg  Section attributes
+
+    \return          0  
+ */
+__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+    *descriptor  = 0;
+
+   __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+   __xn_section(descriptor,reg.xn_t);
+   __domain_section(descriptor, reg.domain);
+   __p_section(descriptor, reg.e_t);
+   __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
+   __shared_section(descriptor,reg.sh_t);
+   __global_section(descriptor,reg.g_t);
+   __secure_section(descriptor,reg.sec_t);
+   *descriptor &= SECTION_MASK;
+   *descriptor |= SECTION_DESCRIPTOR;
+
+   return 0;
+
+}
+
+
+/** \brief  Create a L1 and L2 4k/64k page descriptor
+
+    The function creates a 4k/64k page descriptor.
+    Assumptions:
+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
+    - Functions always return 0
+
+    \param [out]       descriptor  L1 descriptor
+    \param [out]      descriptor2  L2 descriptor
+    \param [in]               reg  4k/64k page attributes
+
+    \return          0  
+ */
+__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+    *descriptor  = 0;
+    *descriptor2 = 0;
+
+    switch (reg.rg_t)
+    {
+        case PAGE_4k:
+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+            __xn_page(descriptor2, reg.xn_t, PAGE_4k);
+            __domain_page(descriptor, reg.domain);
+            __p_page(descriptor, reg.e_t);
+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
+            __shared_page(descriptor2,reg.sh_t);
+            __global_page(descriptor2,reg.g_t);
+            __secure_page(descriptor,reg.sec_t);
+            *descriptor &= PAGE_L1_MASK;
+            *descriptor |= PAGE_L1_DESCRIPTOR;
+            *descriptor2 &= PAGE_L2_4K_MASK;
+            *descriptor2 |= PAGE_L2_4K_DESC;
+            break;
+
+        case PAGE_64k:
+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+            __xn_page(descriptor2, reg.xn_t, PAGE_64k);
+            __domain_page(descriptor, reg.domain);
+            __p_page(descriptor, reg.e_t);
+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
+            __shared_page(descriptor2,reg.sh_t);
+            __global_page(descriptor2,reg.g_t);
+            __secure_page(descriptor,reg.sec_t);
+            *descriptor &= PAGE_L1_MASK;
+            *descriptor |= PAGE_L1_DESCRIPTOR;
+            *descriptor2 &= PAGE_L2_64K_MASK;
+            *descriptor2 |= PAGE_L2_64K_DESC;
+            break;
+
+        case SECTION:
+            //error
+            break;    
+
+    }
+
+   return 0;
+
+}
+
+/** \brief  Create a 1MB Section
+
+    \param [in]               ttb  Translation table base address
+    \param [in]      base_address  Section base address
+    \param [in]             count  Number of sections to create
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
+
+ */
+__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+    uint32_t offset;
+    uint32_t entry;
+    uint32_t i;
+
+    offset = base_address >> 20;
+    entry  = (base_address & 0xFFF00000) | descriptor_l1;
+
+    //4 bytes aligned
+    ttb = ttb + offset;
+
+    for (i = 0; i < count; i++ )
+    {
+        //4 bytes aligned
+       *ttb++ = entry;
+       entry += OFFSET_1M;
+    }
+}
+
+/** \brief  Create a 4k page entry
+
+    \param [in]               ttb  L1 table base address
+    \param [in]      base_address  4k base address
+    \param [in]             count  Number of 4k pages to create
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
+    \param [in]            ttb_l2  L2 table base address
+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
+
+ */
+__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+    uint32_t offset, offset2;
+    uint32_t entry, entry2;
+    uint32_t i;
+
+
+    offset = base_address >> 20;
+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+    //4 bytes aligned
+    ttb += offset;
+    //create l1_entry
+    *ttb = entry;
+
+    offset2 = (base_address & 0xff000) >> 12;
+    ttb_l2 += offset2;
+    entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+    for (i = 0; i < count; i++ )
+    {
+        //4 bytes aligned
+       *ttb_l2++ = entry2;
+       entry2 += OFFSET_4K;
+    }
+}
+
+/** \brief  Create a 64k page entry
+
+    \param [in]               ttb  L1 table base address
+    \param [in]      base_address  64k base address
+    \param [in]             count  Number of 64k pages to create
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
+    \param [in]            ttb_l2  L2 table base address
+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
+
+ */
+__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+    uint32_t offset, offset2;
+    uint32_t entry, entry2;
+    uint32_t i,j;
+
+
+    offset = base_address >> 20;
+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+    //4 bytes aligned
+    ttb += offset;
+    //create l1_entry
+    *ttb = entry;
+
+    offset2 = (base_address & 0xff000) >> 12;
+    ttb_l2 += offset2;
+    entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+    for (i = 0; i < count; i++ )
+    {
+        //create 16 entries
+        for (j = 0; j < 16; j++)
+            //4 bytes aligned
+            *ttb_l2++ = entry2;
+        entry2 += OFFSET_64K;
+    }
+}
+
+/*@} end of MMU_Functions */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_cm4_simd.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_cm4_simd.h
new file mode 100755
index 0000000..83db95b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_cmInstr.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_cmInstr.h
new file mode 100755
index 0000000..fca425c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_A/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h
new file mode 100755
index 0000000..7b2a284
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h
@@ -0,0 +1,809 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h
new file mode 100755
index 0000000..7c22d84
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h
@@ -0,0 +1,1795 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.3
+ * @date     27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//lint -esym(9058, IRQn)   disable MISRA 2012 Rule 2.4 for IRQn
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32)  disable MISRA 2012 Rule 2.4 for T_UINT32
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_WRITE)  disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_READ)  disable MISRA 2012 Rule 2.4 for T_UINT16_READ
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32_WRITE)  disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR      __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR      __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          __builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h
new file mode 100755
index 0000000..f023d77
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h
@@ -0,0 +1,1958 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+//  __ASM volatile ("nop");
+//}
+#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+//  __ASM volatile ("wfi");
+//}
+#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+//  __ASM volatile ("wfe");
+//}
+#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+//  __ASM volatile ("sev");
+//}
+#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h
new file mode 100755
index 0000000..9e87cfd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TARGET_CORTEX_M/cmsis_compiler.h
@@ -0,0 +1,315 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+
+  #include <cmsis_iar.h>
+
+  /* CMSIS compiler control architecture macros */
+  #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+    #ifndef __ARM_ARCH_6M__
+      #define __ARM_ARCH_6M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7M__)
+    #ifndef __ARM_ARCH_7M__
+      #define __ARM_ARCH_7M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7EM__)
+    #ifndef __ARM_ARCH_7EM__
+      #define __ARM_ARCH_7EM__                     1
+    #endif
+  #elif (__CORE__ == __ARM8M_BASELINE__)
+    #ifndef __ARM_ARCH_8M_BASE__
+      #define __ARM_ARCH_8M_BASE__                 1
+    #endif
+  #elif (__CORE__ == __ARM8M_MAINLINE__)
+    #ifndef __ARM_ARCH_8M_MAIN__
+      #define __ARM_ARCH_8M_MAIN__                 1
+    #endif
+  #endif
+
+  // IAR version 7.8.1 and earlier do not include __ALIGNED
+  #ifndef __ALIGNED
+  #define __ALIGNED(x) __attribute__((aligned(x)))
+  #endif
+
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __noreturn
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __root
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        __packed struct
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    __packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S
new file mode 100755
index 0000000..d37f889
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S
@@ -0,0 +1,94 @@
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+    .text
+    .global __v7_all_cache
+/*
+ * __STATIC_ASM void __v7_all_cache(uint32_t op) {
+ */
+__v7_all_cache:
+        .arm
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
+        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
+        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
+        BEQ     Finished                   /* If 0, no need to clean */
+
+        MOV     R10, #0                    /* R10 holds current cache level << 1 */
+Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
+        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
+        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
+        CMP     R1, #2
+        BLT     Skip                       /* No cache or only instruction cache at this level */
+
+        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
+        ISB                                /* ISB to sync the change to the CacheSizeID reg */
+        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
+        AND     R2, R1, #7                 /* Extract the line length field */
+        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
+        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
+
+Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
+
+Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
+        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
+        B       cont
+Dccsw:  CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
+        B       cont
+Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
+cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
+        BGE     Loop3
+        SUBS    R7, R7, #1                 /* Decrement the Set number */
+        BGE     Loop2
+Skip:   ADD     R10, R10, #2               /* increment the cache number */
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished:
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+
+    .END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S
new file mode 100755
index 0000000..0035278
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S
@@ -0,0 +1,97 @@
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+    SECTION `.text`:CODE:NOROOT(2)
+    arm 
+    PUBLIC __v7_all_cache
+/*
+ * __STATIC_ASM void __v7_all_cache(uint32_t op) {
+ */
+
+__v7_all_cache:
+
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
+        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
+        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
+        BEQ     Finished                   /* If 0, no need to clean */
+
+        MOV     R10, #0                    /* R10 holds current cache level << 1 */
+Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
+        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
+        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
+        CMP     R1, #2
+        BLT     Skip                       /* No cache or only instruction cache at this level */
+
+        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
+        ISB                                /* ISB to sync the change to the CacheSizeID reg */
+        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
+        AND     R2, R1, #7                 /* Extract the line length field */
+        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
+        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
+
+Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
+
+Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
+        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
+        B       cont
+Dccsw:  CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
+        B       cont
+Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
+cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
+        BGE     Loop3
+        SUBS    R7, R7, #1                 /* Decrement the Set number */
+        BGE     Loop2
+Skip:   ADD     R10, R10, #2               /* increment the cache number */
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished:
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+
+    END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+ 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_IAR/cmain.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_IAR/cmain.S
new file mode 100755
index 0000000..0da5500
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/TOOLCHAIN_IAR/cmain.S
@@ -0,0 +1,101 @@
+/**************************************************
+ *
+ * Part two of the system initialization code, contains C-level
+ * initialization, thumb-2 only variant.
+ *
+ * $Revision: 59783 $
+ *
+ **************************************************/
+/* Copyright 2008-2017, IAR Systems AB.
+   This source code is the property of IAR Systems. The source code may only
+   be used together with the IAR Embedded Workbench. Redistribution and use
+   in source and binary forms, with or without modification, is permitted
+   provided that the following conditions are met:
+   - Redistributions of source code, in whole or in part, must retain the
+     above copyright notice, this list of conditions and the disclaimer below.
+   - IAR Systems name may not be used to endorse or promote products
+     derived from this software without specific prior written permission.
+
+   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+; --------------------------------------------------
+; Module ?cmain, C-level initialization.
+;
+
+
+        SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
+        SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  __cmain
+        ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
+        PUBLIC  ?main
+        EXTWEAK __iar_data_init3
+        EXTWEAK __iar_argc_argv
+        EXTERN  __low_level_init
+        EXTERN  __call_ctors
+        EXTERN  main
+        EXTERN  exit
+        EXTERN  __iar_dynamic_initialization
+        EXTERN mbed_sdk_init
+        EXTERN mbed_main
+        EXTERN SystemInit
+        
+        THUMB
+__cmain:
+?main:
+
+; Initialize segments.
+; __segment_init and __low_level_init are assumed to use the same
+; instruction set and to be reachable by BL from the ICODE segment
+; (it is safest to link them in segment ICODE).
+
+          FUNCALL __cmain, __low_level_init
+        bl      __low_level_init
+        cmp     r0,#0
+        beq     ?l1
+          FUNCALL __cmain, __iar_data_init3
+        bl      __iar_data_init3
+        MOVS    r0,#0             ;  No parameters
+        FUNCALL __cmain, mbed_sdk_init
+        BL      mbed_sdk_init
+        MOVS    r0,#0             ;  No parameters        
+          FUNCALL __cmain, __iar_dynamic_initialization
+        BL      __iar_dynamic_initialization   ; C++ dynamic initialization  
+
+?l1:
+        REQUIRE ?l3
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  _main
+        PUBLIC _call_main
+        THUMB
+
+__iar_init$$done:                 ; Copy initialization is done
+
+?l3:
+_call_main:
+        MOVS    r0,#0             ;  No parameters  
+          FUNCALL __cmain, __iar_argc_argv
+        BL      __iar_argc_argv   ; Maybe setup command line
+
+        MOVS    r0,#0             ;  No parameters  
+          FUNCALL __cmain, mbed_main
+        BL      mbed_main
+
+          FUNCALL __cmain, main
+        BL      main
+_main:
+          FUNCALL __cmain, exit
+        BL      exit
+
+        END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/arm_math.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/arm_math.h
new file mode 100755
index 0000000..6d75401
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/arm_math.h
@@ -0,0 +1,7257 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_math.h
+ * Description:  Public header file for CMSIS DSP Library
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+   * 
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+   * on ARMv8M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+  #include "core_armv8mbl.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+  #include "core_armv8mml.h"
+  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+    #define ARM_MATH_DSP
+  #endif
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+  #define PI               3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if   defined ( __CC_ARM )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+/*
+  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+  #define __CLZ __clz
+  #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+  q31_t data);
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while ((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+  }
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+  CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if (x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if (x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if (x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+  }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+  /*
+   * @brief C custom defined SMMLA for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+  int32_t x,
+  int32_t y,
+  int32_t sum)
+  {
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+  }
+
+#if 0
+  /*
+   * @brief C custom defined PKHBT for unavailable DSP extension
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+  uint32_t x,
+  uint32_t y,
+  uint32_t leftshift)
+  {
+    return ( ((x             ) & 0x0000FFFFUL) |
+             ((y << leftshift) & 0xFFFF0000UL)  );
+  }
+
+  /*
+   * @brief C custom defined PKHTB for unavailable DSP extension
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+  uint32_t x,
+  uint32_t y,
+  uint32_t rightshift)
+  {
+    return ( ((x              ) & 0xFFFF0000UL) |
+             ((y >> rightshift) & 0x0000FFFFUL)  );
+  }
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if (in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+  #define LOW_OPTIMIZATION_ENTER \
+       __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_armv8mbl.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_armv8mbl.h
new file mode 100755
index 0000000..d039352
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_armv8mbl.h
@@ -0,0 +1,1876 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+/*  CMSIS cmGrebe definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_armv8mml.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_armv8mml.h
new file mode 100755
index 0000000..286322f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_armv8mml.h
@@ -0,0 +1,2900 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+/*  CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_ca.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_ca.h
new file mode 100755
index 0000000..6d1e29f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_ca.h
@@ -0,0 +1,2016 @@
+/**************************************************************************//**
+ * @file     core_ca.h
+ * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
+ * @version  V1.00
+ * @date     22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA_H_GENERIC
+#define __CORE_CA_H_GENERIC
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+
+/*  CMSIS CA definitions */
+#define __CA_CMSIS_VERSION_MAIN  (1U)                                      /*!< \brief [31:16] CMSIS HAL main version   */
+#define __CA_CMSIS_VERSION_SUB   (0U)                                      /*!< \brief [15:0]  CMSIS HAL sub version    */
+#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CA_CMSIS_VERSION_SUB          )       /*!< \brief CMSIS HAL version number         */
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA_H_DEPENDANT
+#define __CORE_CA_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ /* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CA_REV
+    #define __CA_REV              0x0000U
+    #warning "__CA_REV not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __GIC_PRESENT
+    #define __GIC_PRESENT             1U
+    #warning "__GIC_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __TIM_PRESENT
+    #define __TIM_PRESENT             1U
+    #warning "__TIM_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __L2C_PRESENT
+    #define __L2C_PRESENT             0U
+    #warning "__L2C_PRESENT not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< \brief Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< \brief Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< \brief Defines 'write only' permissions */
+#define     __IO    volatile             /*!< \brief Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*!< \brief Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*!< \brief Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
+
+
+ /*******************************************************************************
+  *                 Register Abstraction
+   Core Register contain:
+   - CPSR
+   - CP15 Registers
+   - L2C-310 Cache Controller
+   - Generic Interrupt Controller Distributor
+   - Generic Interrupt Controller Interface
+  ******************************************************************************/
+
+/* Core Register CPSR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:5;                        /*!< \brief bit:  0.. 4  Mode field */
+    uint32_t T:1;                        /*!< \brief bit:      5  Thumb execution state bit */
+    uint32_t F:1;                        /*!< \brief bit:      6  FIQ mask bit */
+    uint32_t I:1;                        /*!< \brief bit:      7  IRQ mask bit */
+    uint32_t A:1;                        /*!< \brief bit:      8  Asynchronous abort mask bit */
+    uint32_t E:1;                        /*!< \brief bit:      9  Endianness execution state bit */
+    uint32_t IT1:6;                      /*!< \brief bit: 10..15  If-Then execution state bits 2-7 */
+    uint32_t GE:4;                       /*!< \brief bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved0:4;               /*!< \brief bit: 20..23  Reserved */
+    uint32_t J:1;                        /*!< \brief bit:     24  Jazelle bit */
+    uint32_t IT0:2;                      /*!< \brief bit: 25..26  If-Then execution state bits 0-1 */
+    uint32_t Q:1;                        /*!< \brief bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< \brief bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< \brief bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< \brief bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< \brief bit:     31  Negative condition code flag */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPSR_Type;
+
+/* CPSR Register Definitions */
+#define CPSR_N_Pos                       31U                                    /*!< \brief CPSR: N Position */
+#define CPSR_N_Msk                       (1UL << CPSR_N_Pos)                    /*!< \brief CPSR: N Mask */
+
+#define CPSR_Z_Pos                       30U                                    /*!< \brief CPSR: Z Position */
+#define CPSR_Z_Msk                       (1UL << CPSR_Z_Pos)                    /*!< \brief CPSR: Z Mask */
+
+#define CPSR_C_Pos                       29U                                    /*!< \brief CPSR: C Position */
+#define CPSR_C_Msk                       (1UL << CPSR_C_Pos)                    /*!< \brief CPSR: C Mask */
+
+#define CPSR_V_Pos                       28U                                    /*!< \brief CPSR: V Position */
+#define CPSR_V_Msk                       (1UL << CPSR_V_Pos)                    /*!< \brief CPSR: V Mask */
+
+#define CPSR_Q_Pos                       27U                                    /*!< \brief CPSR: Q Position */
+#define CPSR_Q_Msk                       (1UL << CPSR_Q_Pos)                    /*!< \brief CPSR: Q Mask */
+
+#define CPSR_IT0_Pos                     25U                                    /*!< \brief CPSR: IT0 Position */
+#define CPSR_IT0_Msk                     (3UL << CPSR_IT0_Pos)                  /*!< \brief CPSR: IT0 Mask */
+
+#define CPSR_J_Pos                       24U                                    /*!< \brief CPSR: J Position */
+#define CPSR_J_Msk                       (1UL << CPSR_J_Pos)                    /*!< \brief CPSR: J Mask */
+
+#define CPSR_GE_Pos                      16U                                    /*!< \brief CPSR: GE Position */
+#define CPSR_GE_Msk                      (0xFUL << CPSR_GE_Pos)                 /*!< \brief CPSR: GE Mask */
+
+#define CPSR_IT1_Pos                     10U                                    /*!< \brief CPSR: IT1 Position */
+#define CPSR_IT1_Msk                     (0x3FUL << CPSR_IT1_Pos)               /*!< \brief CPSR: IT1 Mask */
+
+#define CPSR_E_Pos                       9U                                     /*!< \brief CPSR: E Position */
+#define CPSR_E_Msk                       (1UL << CPSR_E_Pos)                    /*!< \brief CPSR: E Mask */
+
+#define CPSR_A_Pos                       8U                                     /*!< \brief CPSR: A Position */
+#define CPSR_A_Msk                       (1UL << CPSR_A_Pos)                    /*!< \brief CPSR: A Mask */
+
+#define CPSR_I_Pos                       7U                                     /*!< \brief CPSR: I Position */
+#define CPSR_I_Msk                       (1UL << CPSR_I_Pos)                    /*!< \brief CPSR: I Mask */
+
+#define CPSR_F_Pos                       6U                                     /*!< \brief CPSR: F Position */
+#define CPSR_F_Msk                       (1UL << CPSR_F_Pos)                    /*!< \brief CPSR: F Mask */
+
+#define CPSR_T_Pos                       5U                                     /*!< \brief CPSR: T Position */
+#define CPSR_T_Msk                       (1UL << CPSR_T_Pos)                    /*!< \brief CPSR: T Mask */
+
+#define CPSR_M_Pos                       0U                                     /*!< \brief CPSR: M Position */
+#define CPSR_M_Msk                       (0x1FUL << CPSR_M_Pos)                 /*!< \brief CPSR: M Mask */
+
+/* CP15 Register SCTLR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:1;                        /*!< \brief bit:     0  MMU enable */
+    uint32_t A:1;                        /*!< \brief bit:     1  Alignment check enable */
+    uint32_t C:1;                        /*!< \brief bit:     2  Cache enable */
+    uint32_t _reserved0:2;               /*!< \brief bit: 3.. 4  Reserved */
+    uint32_t CP15BEN:1;                  /*!< \brief bit:     5  CP15 barrier enable */
+    uint32_t _reserved1:1;               /*!< \brief bit:     6  Reserved */
+    uint32_t B:1;                        /*!< \brief bit:     7  Endianness model */
+    uint32_t _reserved2:2;               /*!< \brief bit: 8.. 9  Reserved */
+    uint32_t SW:1;                       /*!< \brief bit:    10  SWP and SWPB enable */
+    uint32_t Z:1;                        /*!< \brief bit:    11  Branch prediction enable */
+    uint32_t I:1;                        /*!< \brief bit:    12  Instruction cache enable */
+    uint32_t V:1;                        /*!< \brief bit:    13  Vectors bit */
+    uint32_t RR:1;                       /*!< \brief bit:    14  Round Robin select */
+    uint32_t _reserved3:2;               /*!< \brief bit:15..16  Reserved */
+    uint32_t HA:1;                       /*!< \brief bit:    17  Hardware Access flag enable */
+    uint32_t _reserved4:1;               /*!< \brief bit:    18  Reserved */
+    uint32_t WXN:1;                      /*!< \brief bit:    19  Write permission implies XN */
+    uint32_t UWXN:1;                     /*!< \brief bit:    20  Unprivileged write permission implies PL1 XN */
+    uint32_t FI:1;                       /*!< \brief bit:    21  Fast interrupts configuration enable */
+    uint32_t U:1;                        /*!< \brief bit:    22  Alignment model */
+    uint32_t _reserved5:1;               /*!< \brief bit:    23  Reserved */
+    uint32_t VE:1;                       /*!< \brief bit:    24  Interrupt Vectors Enable */
+    uint32_t EE:1;                       /*!< \brief bit:    25  Exception Endianness */
+    uint32_t _reserved6:1;               /*!< \brief bit:    26  Reserved */
+    uint32_t NMFI:1;                     /*!< \brief bit:    27  Non-maskable FIQ (NMFI) support */
+    uint32_t TRE:1;                      /*!< \brief bit:    28  TEX remap enable. */
+    uint32_t AFE:1;                      /*!< \brief bit:    29  Access flag enable */
+    uint32_t TE:1;                       /*!< \brief bit:    30  Thumb Exception enable */
+    uint32_t _reserved7:1;               /*!< \brief bit:    31  Reserved */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} SCTLR_Type;
+
+#define SCTLR_TE_Pos                     30U                                    /*!< \brief SCTLR: TE Position */
+#define SCTLR_TE_Msk                     (1UL << SCTLR_TE_Pos)                  /*!< \brief SCTLR: TE Mask */
+
+#define SCTLR_AFE_Pos                    29U                                    /*!< \brief SCTLR: AFE Position */
+#define SCTLR_AFE_Msk                    (1UL << SCTLR_AFE_Pos)                 /*!< \brief SCTLR: AFE Mask */
+
+#define SCTLR_TRE_Pos                    28U                                    /*!< \brief SCTLR: TRE Position */
+#define SCTLR_TRE_Msk                    (1UL << SCTLR_TRE_Pos)                 /*!< \brief SCTLR: TRE Mask */
+
+#define SCTLR_NMFI_Pos                   27U                                    /*!< \brief SCTLR: NMFI Position */
+#define SCTLR_NMFI_Msk                   (1UL << SCTLR_NMFI_Pos)                /*!< \brief SCTLR: NMFI Mask */
+
+#define SCTLR_EE_Pos                     25U                                    /*!< \brief SCTLR: EE Position */
+#define SCTLR_EE_Msk                     (1UL << SCTLR_EE_Pos)                  /*!< \brief SCTLR: EE Mask */
+
+#define SCTLR_VE_Pos                     24U                                    /*!< \brief SCTLR: VE Position */
+#define SCTLR_VE_Msk                     (1UL << SCTLR_VE_Pos)                  /*!< \brief SCTLR: VE Mask */
+
+#define SCTLR_U_Pos                      22U                                    /*!< \brief SCTLR: U Position */
+#define SCTLR_U_Msk                      (1UL << SCTLR_U_Pos)                   /*!< \brief SCTLR: U Mask */
+
+#define SCTLR_FI_Pos                     21U                                    /*!< \brief SCTLR: FI Position */
+#define SCTLR_FI_Msk                     (1UL << SCTLR_FI_Pos)                  /*!< \brief SCTLR: FI Mask */
+
+#define SCTLR_UWXN_Pos                   20U                                    /*!< \brief SCTLR: UWXN Position */
+#define SCTLR_UWXN_Msk                   (1UL << SCTLR_UWXN_Pos)                /*!< \brief SCTLR: UWXN Mask */
+
+#define SCTLR_WXN_Pos                    19U                                    /*!< \brief SCTLR: WXN Position */
+#define SCTLR_WXN_Msk                    (1UL << SCTLR_WXN_Pos)                 /*!< \brief SCTLR: WXN Mask */
+
+#define SCTLR_HA_Pos                     17U                                    /*!< \brief SCTLR: HA Position */
+#define SCTLR_HA_Msk                     (1UL << SCTLR_HA_Pos)                  /*!< \brief SCTLR: HA Mask */
+
+#define SCTLR_RR_Pos                     14U                                    /*!< \brief SCTLR: RR Position */
+#define SCTLR_RR_Msk                     (1UL << SCTLR_RR_Pos)                  /*!< \brief SCTLR: RR Mask */
+
+#define SCTLR_V_Pos                      13U                                    /*!< \brief SCTLR: V Position */
+#define SCTLR_V_Msk                      (1UL << SCTLR_V_Pos)                   /*!< \brief SCTLR: V Mask */
+
+#define SCTLR_I_Pos                      12U                                    /*!< \brief SCTLR: I Position */
+#define SCTLR_I_Msk                      (1UL << SCTLR_I_Pos)                   /*!< \brief SCTLR: I Mask */
+
+#define SCTLR_Z_Pos                      11U                                    /*!< \brief SCTLR: Z Position */
+#define SCTLR_Z_Msk                      (1UL << SCTLR_Z_Pos)                   /*!< \brief SCTLR: Z Mask */
+
+#define SCTLR_SW_Pos                     10U                                    /*!< \brief SCTLR: SW Position */
+#define SCTLR_SW_Msk                     (1UL << SCTLR_SW_Pos)                  /*!< \brief SCTLR: SW Mask */
+
+#define SCTLR_B_Pos                      7U                                     /*!< \brief SCTLR: B Position */
+#define SCTLR_B_Msk                      (1UL << SCTLR_B_Pos)                   /*!< \brief SCTLR: B Mask */
+
+#define SCTLR_CP15BEN_Pos                5U                                     /*!< \brief SCTLR: CP15BEN Position */
+#define SCTLR_CP15BEN_Msk                (1UL << SCTLR_CP15BEN_Pos)             /*!< \brief SCTLR: CP15BEN Mask */
+
+#define SCTLR_C_Pos                      2U                                     /*!< \brief SCTLR: C Position */
+#define SCTLR_C_Msk                      (1UL << SCTLR_C_Pos)                   /*!< \brief SCTLR: C Mask */
+
+#define SCTLR_A_Pos                      1U                                     /*!< \brief SCTLR: A Position */
+#define SCTLR_A_Msk                      (1UL << SCTLR_A_Pos)                   /*!< \brief SCTLR: A Mask */
+
+#define SCTLR_M_Pos                      0U                                     /*!< \brief SCTLR: M Position */
+#define SCTLR_M_Msk                      (1UL << SCTLR_M_Pos)                   /*!< \brief SCTLR: M Mask */
+
+/* CP15 Register CPACR */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:20;              /*!< \brief bit: 0..19  Reserved */
+    uint32_t cp10:2;                     /*!< \brief bit:20..21  Access rights for coprocessor 10 */
+    uint32_t cp11:2;                     /*!< \brief bit:22..23  Access rights for coprocessor 11 */
+    uint32_t _reserved1:6;               /*!< \brief bit:24..29  Reserved */
+    uint32_t D32DIS:1;                   /*!< \brief bit:    30  Disable use of registers D16-D31 of the VFP register file */
+    uint32_t ASEDIS:1;                   /*!< \brief bit:    31  Disable Advanced SIMD Functionality */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPACR_Type;
+
+#define CPACR_ASEDIS_Pos                 31U                                    /*!< \brief CPACR: ASEDIS Position */
+#define CPACR_ASEDIS_Msk                 (1UL << CPACR_ASEDIS_Pos)              /*!< \brief CPACR: ASEDIS Mask */
+
+#define CPACR_D32DIS_Pos                 30U                                    /*!< \brief CPACR: D32DIS Position */
+#define CPACR_D32DIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_cp11_Pos                   22U                                    /*!< \brief CPACR: cp11 Position */
+#define CPACR_cp11_Msk                   (3UL << CPACR_cp11_Pos)                /*!< \brief CPACR: cp11 Mask */
+
+#define CPACR_cp10_Pos                   20U                                    /*!< \brief CPACR: cp10 Position */
+#define CPACR_cp10_Msk                   (3UL << CPACR_cp10_Pos)                /*!< \brief CPACR: cp10 Mask */
+
+/* CP15 Register DFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    uint32_t Domain:4;                   /*!< \brief bit: 4.. 7  Fault on which domain */
+    uint32_t _reserved0:2;               /*!< \brief bit: 8.. 9  Reserved */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
+    uint32_t _reserved1:18;              /*!< \brief bit:14..31  Reserved */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} DFSR_Type;
+
+#define DFSR_CM_Pos                      13U                                    /*!< \brief DFSR: CM Position */
+#define DFSR_CM_Msk                      (1UL << DFSR_CM_Pos)                   /*!< \brief DFSR: CM Mask */
+
+#define DFSR_Ext_Pos                     12U                                    /*!< \brief DFSR: Ext Position */
+#define DFSR_Ext_Msk                     (1UL << DFSR_Ext_Pos)                  /*!< \brief DFSR: Ext Mask */
+
+#define DFSR_WnR_Pos                     11U                                    /*!< \brief DFSR: WnR Position */
+#define DFSR_WnR_Msk                     (1UL << DFSR_WnR_Pos)                  /*!< \brief DFSR: WnR Mask */
+
+#define DFSR_FS1_Pos                     10U                                    /*!< \brief DFSR: FS1 Position */
+#define DFSR_FS1_Msk                     (1UL << DFSR_FS1_Pos)                  /*!< \brief DFSR: FS1 Mask */
+
+#define DFSR_Domain_Pos                  4U                                     /*!< \brief DFSR: Domain Position */
+#define DFSR_Domain_Msk                  (0xFUL << DFSR_Domain_Pos)             /*!< \brief DFSR: Domain Mask */
+
+#define DFSR_FS0_Pos                     0U                                     /*!< \brief DFSR: FS0 Position */
+#define DFSR_FS0_Msk                     (0xFUL << DFSR_FS0_Pos)                /*!< \brief DFSR: FS0 Mask */
+
+/* CP15 Register IFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    uint32_t _reserved0:6;               /*!< \brief bit: 4.. 9  Reserved */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    uint32_t _reserved1:1;               /*!< \brief bit:    11  Reserved */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t _reserved2:19;              /*!< \brief bit:13..31  Reserved */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} IFSR_Type;
+
+#define IFSR_ExT_Pos                     12U                                    /*!< \brief IFSR: ExT Position */
+#define IFSR_ExT_Msk                     (1UL << IFSR_ExT_Pos)                  /*!< \brief IFSR: ExT Mask */
+
+#define IFSR_FS1_Pos                     10U                                    /*!< \brief IFSR: FS1 Position */
+#define IFSR_FS1_Msk                     (1UL << IFSR_FS1_Pos)                  /*!< \brief IFSR: FS1 Mask */
+
+#define IFSR_FS0_Pos                     0U                                     /*!< \brief IFSR: FS0 Position */
+#define IFSR_FS0_Msk                     (0xFUL << IFSR_FS0_Pos)                /*!< \brief IFSR: FS0 Mask */
+
+/* CP15 Register ISR */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:6;               /*!< \brief bit: 0.. 5  Reserved */
+    uint32_t F:1;                        /*!< \brief bit:     6  FIQ pending bit */
+    uint32_t I:1;                        /*!< \brief bit:     7  IRQ pending bit */
+    uint32_t A:1;                        /*!< \brief bit:     8  External abort pending bit */
+    uint32_t _reserved1:23;              /*!< \brief bit:14..31  Reserved */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} ISR_Type;
+
+#define ISR_A_Pos                        13U                                    /*!< \brief ISR: A Position */
+#define ISR_A_Msk                        (1UL << ISR_A_Pos)                     /*!< \brief ISR: A Mask */
+
+#define ISR_I_Pos                        12U                                    /*!< \brief ISR: I Position */
+#define ISR_I_Msk                        (1UL << ISR_I_Pos)                     /*!< \brief ISR: I Mask */
+
+#define ISR_F_Pos                        11U                                    /*!< \brief ISR: F Position */
+#define ISR_F_Msk                        (1UL << ISR_F_Pos)                     /*!< \brief ISR: F Mask */
+
+
+/**
+ \brief  Union type to access the L2C_310 Cache Controller.
+*/
+#if (__L2C_PRESENT == 1U)
+typedef struct
+{
+  __I  uint32_t CACHE_ID;                   /*!< \brief Offset: 0x0000   Cache ID Register               */
+  __I  uint32_t CACHE_TYPE;                 /*!< \brief Offset: 0x0004   Cache Type Register             */
+       uint32_t RESERVED0[0x3e];
+  __IO uint32_t CONTROL;                    /*!< \brief Offset: 0x0100   Control Register                */
+  __IO uint32_t AUX_CNT;                    /*!< \brief Offset: 0x0104   Auxiliary Control               */
+       uint32_t RESERVED1[0x3e];
+  __IO uint32_t EVENT_CONTROL;              /*!< \brief Offset: 0x0200   Event Counter Control           */
+  __IO uint32_t EVENT_COUNTER1_CONF;        /*!< \brief Offset: 0x0204   Event Counter 1 Configuration   */
+  __IO uint32_t EVENT_COUNTER0_CONF;        /*!< \brief Offset: 0x0208   Event Counter 1 Configuration   */
+       uint32_t RESERVED2[0x2];
+  __IO uint32_t INTERRUPT_MASK;             /*!< \brief Offset: 0x0214   Interrupt Mask                  */
+  __I  uint32_t MASKED_INT_STATUS;          /*!< \brief Offset: 0x0218   Masked Interrupt Status         */
+  __I  uint32_t RAW_INT_STATUS;             /*!< \brief Offset: 0x021c   Raw Interrupt Status            */
+  __O  uint32_t INTERRUPT_CLEAR;            /*!< \brief Offset: 0x0220   Interrupt Clear                 */
+       uint32_t RESERVED3[0x143];
+  __IO uint32_t CACHE_SYNC;                 /*!< \brief Offset: 0x0730   Cache Sync                      */
+       uint32_t RESERVED4[0xf];
+  __IO uint32_t INV_LINE_PA;                /*!< \brief Offset: 0x0770   Invalidate Line By PA           */
+       uint32_t RESERVED6[2];
+  __IO uint32_t INV_WAY;                    /*!< \brief Offset: 0x077c   Invalidate by Way               */
+       uint32_t RESERVED5[0xc];
+  __IO uint32_t CLEAN_LINE_PA;              /*!< \brief Offset: 0x07b0   Clean Line by PA                */
+       uint32_t RESERVED7[1];
+  __IO uint32_t CLEAN_LINE_INDEX_WAY;       /*!< \brief Offset: 0x07b8   Clean Line by Index/Way         */
+  __IO uint32_t CLEAN_WAY;                  /*!< \brief Offset: 0x07bc   Clean by Way                    */
+       uint32_t RESERVED8[0xc];
+  __IO uint32_t CLEAN_INV_LINE_PA;          /*!< \brief Offset: 0x07f0   Clean and Invalidate Line by PA  */
+       uint32_t RESERVED9[1];
+  __IO uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< \brief Offset: 0x07f8   Clean and Invalidate Line by Index/Way  */
+  __IO uint32_t CLEAN_INV_WAY;              /*!< \brief Offset: 0x07fc   Clean and Invalidate by Way     */
+       uint32_t RESERVED10[0x40];
+  __IO uint32_t DATA_LOCK_0_WAY;            /*!< \brief Offset: 0x0900   Data Lockdown 0 by Way          */
+  __IO uint32_t INST_LOCK_0_WAY;            /*!< \brief Offset: 0x0904   Instruction Lockdown 0 by Way   */
+  __IO uint32_t DATA_LOCK_1_WAY;            /*!< \brief Offset: 0x0908   Data Lockdown 1 by Way          */
+  __IO uint32_t INST_LOCK_1_WAY;            /*!< \brief Offset: 0x090c   Instruction Lockdown 1 by Way   */
+  __IO uint32_t DATA_LOCK_2_WAY;            /*!< \brief Offset: 0x0910   Data Lockdown 2 by Way          */
+  __IO uint32_t INST_LOCK_2_WAY;            /*!< \brief Offset: 0x0914   Instruction Lockdown 2 by Way   */
+  __IO uint32_t DATA_LOCK_3_WAY;            /*!< \brief Offset: 0x0918   Data Lockdown 3 by Way          */
+  __IO uint32_t INST_LOCK_3_WAY;            /*!< \brief Offset: 0x091c   Instruction Lockdown 3 by Way   */
+  __IO uint32_t DATA_LOCK_4_WAY;            /*!< \brief Offset: 0x0920   Data Lockdown 4 by Way          */
+  __IO uint32_t INST_LOCK_4_WAY;            /*!< \brief Offset: 0x0924   Instruction Lockdown 4 by Way   */
+  __IO uint32_t DATA_LOCK_5_WAY;            /*!< \brief Offset: 0x0928   Data Lockdown 5 by Way          */
+  __IO uint32_t INST_LOCK_5_WAY;            /*!< \brief Offset: 0x092c   Instruction Lockdown 5 by Way   */
+  __IO uint32_t DATA_LOCK_6_WAY;            /*!< \brief Offset: 0x0930   Data Lockdown 5 by Way          */
+  __IO uint32_t INST_LOCK_6_WAY;            /*!< \brief Offset: 0x0934   Instruction Lockdown 5 by Way   */
+  __IO uint32_t DATA_LOCK_7_WAY;            /*!< \brief Offset: 0x0938   Data Lockdown 6 by Way          */
+  __IO uint32_t INST_LOCK_7_WAY;            /*!< \brief Offset: 0x093c   Instruction Lockdown 6 by Way   */
+       uint32_t RESERVED11[0x4];
+  __IO uint32_t LOCK_LINE_EN;               /*!< \brief Offset: 0x0950   Lockdown by Line Enable         */
+  __IO uint32_t UNLOCK_ALL_BY_WAY;          /*!< \brief Offset: 0x0954   Unlock All Lines by Way         */
+       uint32_t RESERVED12[0xaa];
+  __IO uint32_t ADDRESS_FILTER_START;       /*!< \brief Offset: 0x0c00   Address Filtering Start         */
+  __IO uint32_t ADDRESS_FILTER_END;         /*!< \brief Offset: 0x0c04   Address Filtering End           */
+       uint32_t RESERVED13[0xce];
+  __IO uint32_t DEBUG_CONTROL;              /*!< \brief Offset: 0x0f40   Debug Control Register          */
+} L2C_310_TypeDef;
+
+#define L2C_310           ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 Declaration */
+#endif
+
+#if (__GIC_PRESENT == 1U)
+/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
+*/
+typedef struct
+{
+ __IO uint32_t ICDDCR;
+ __I  uint32_t ICDICTR;
+ __I  uint32_t ICDIIDR;
+      uint32_t RESERVED0[29];
+ __IO uint32_t ICDISR[32];
+ __IO uint32_t ICDISER[32];
+ __IO uint32_t ICDICER[32];
+ __IO uint32_t ICDISPR[32];
+ __IO uint32_t ICDICPR[32];
+ __I  uint32_t ICDABR[32];
+      uint32_t RESERVED1[32];
+ __IO uint32_t ICDIPR[256];
+ __IO uint32_t ICDIPTR[256];
+ __IO uint32_t ICDICFR[64];
+      uint32_t RESERVED2[128];
+ __IO uint32_t ICDSGIR;
+}  GICDistributor_Type;
+
+#define GICDistributor      ((GICDistributor_Type      *)     GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
+
+/** \brief  Structure type to access the Generic Interrupt Controller Interface (GICC)
+*/
+typedef struct
+{
+  __IO uint32_t ICCICR;          //!< \brief  +0x000 - RW - CPU Interface Control Register
+  __IO uint32_t ICCPMR;          //!< \brief  +0x004 - RW - Interrupt Priority Mask Register
+  __IO uint32_t ICCBPR;          //!< \brief  +0x008 - RW - Binary Point Register
+  __I  uint32_t ICCIAR;          //!< \brief  +0x00C - RO - Interrupt Acknowledge Register
+  __IO uint32_t ICCEOIR;         //!< \brief  +0x010 - WO - End of Interrupt Register
+  __I  uint32_t ICCRPR;          //!< \brief  +0x014 - RO - Running Priority Register
+  __I  uint32_t ICCHPIR;         //!< \brief  +0x018 - RO - Highest Pending Interrupt Register
+  __IO uint32_t ICCABPR;         //!< \brief  +0x01C - RW - Aliased Binary Point Register
+  uint32_t RESERVED[55];
+  __I  uint32_t ICCIIDR;         //!< \brief  +0x0FC - RO - CPU Interface Identification Register
+}  GICInterface_Type;
+
+#define GICInterface        ((GICInterface_Type        *)     GIC_INTERFACE_BASE )   /*!< GIC Interface configuration struct */
+#endif
+
+#if (__TIM_PRESENT == 1U)
+#if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
+/** \brief Structure type to access the Private Timer
+*/
+typedef struct
+{
+  __IO uint32_t LOAD;            //!< \brief  +0x000 - RW - Private Timer Load Register
+  __IO uint32_t COUNTER;         //!< \brief  +0x004 - RW - Private Timer Counter Register
+  __IO uint32_t CONTROL;         //!< \brief  +0x008 - RW - Private Timer Control Register
+  __IO uint32_t ISR;             //!< \brief  +0x00C - RO - Private Timer Interrupt Status Register
+  uint32_t RESERVED[8];
+  __IO uint32_t WLOAD;           //!< \brief  +0x020 - RW - Watchdog Load Register
+  __IO uint32_t WCOUNTER;        //!< \brief  +0x024 - RW - Watchdog Counter Register
+  __IO uint32_t WCONTROL;        //!< \brief  +0x028 - RW - Watchdog Control Register
+  __IO uint32_t WISR;            //!< \brief  +0x02C - RW - Watchdog Interrupt Status Register
+  __IO uint32_t WRESET;          //!< \brief  +0x030 - RW - Watchdog Reset Status Register
+  __I  uint32_t WDISABLE;        //!< \brief  +0x0FC - RO - Watchdog Disable Register
+} Timer_Type;
+#define PTIM ((Timer_Type *) TIMER_BASE )   /*!< \brief Timer configuration struct */
+#endif
+#endif
+
+ /*******************************************************************************
+  *                Hardware Abstraction Layer
+   Core Function Interface contains:
+   - L1 Cache Functions
+   - L2C-310 Cache Controller Functions 
+   - PL1 Timer Functions
+   - GIC Functions
+   - MMU Functions
+  ******************************************************************************/
+ 
+/* ##########################  L1 Cache functions  ################################# */
+
+/** \brief  Enable Caches
+
+  Enable Caches
+ */
+__STATIC_INLINE void L1C_EnableCaches(void) {
+  // Set I bit 12 to enable I Cache
+  // Set C bit  2 to enable D Cache
+  __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Disable Caches
+
+  Disable Caches
+ */
+__STATIC_INLINE void L1C_DisableCaches(void) {
+  // Clear I bit 12 to disable I Cache
+  // Clear C bit  2 to disable D Cache
+  __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
+  __ISB();
+}
+
+/** \brief  Enable BTAC
+
+  Enable BTAC
+ */
+__STATIC_INLINE void L1C_EnableBTAC(void) {
+  // Set Z bit 11 to enable branch prediction
+  __set_SCTLR( __get_SCTLR() | (1 << 11));
+  __ISB();
+}
+
+/** \brief  Disable BTAC
+
+  Disable BTAC
+ */
+__STATIC_INLINE void L1C_DisableBTAC(void) {
+  // Clear Z bit 11 to disable branch prediction
+  __set_SCTLR( __get_SCTLR() & ~(1 << 11));
+}
+
+/** \brief  Invalidate entire branch predictor array
+
+  BPIALL. Branch Predictor Invalidate All.
+ */
+
+__STATIC_INLINE void L1C_InvalidateBTAC(void) {
+  __set_BPIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+/** \brief  Invalidate the whole I$
+
+  ICIALLU. Instruction Cache Invalidate All to PoU
+*/
+__STATIC_INLINE void L1C_InvalidateICacheAll(void) {
+  __set_ICIALLU(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean D$ by MVA
+
+  DCCMVAC. Data cache clean by MVA to PoC
+*/
+__STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
+  __set_DCCMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate D$ by MVA
+
+  DCIMVAC. Data cache invalidate by MVA to PoC
+*/
+__STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
+  __set_DCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate D$ by MVA
+
+  DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+*/
+__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
+  __set_DCCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+*/
+__STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
+  __L1C_CleanInvalidateCache(op);  // compiler specific call
+}
+
+
+/** \brief  Invalidate the whole D$
+
+  DCISW. Invalidate by Set/Way
+*/
+
+__STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(0);
+}
+
+/** \brief  Clean the whole D$
+
+    DCCSW. Clean by Set/Way
+ */
+
+__STATIC_INLINE void L1C_CleanDCacheAll(void) {
+  L1C_CleanInvalidateCache(1);
+}
+
+/** \brief  Clean and invalidate the whole D$
+
+    DCCISW. Clean and Invalidate by Set/Way
+ */
+
+__STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(2);
+}
+
+
+/* ##########################  L2 Cache functions  ################################# */
+#if (__L2C_PRESENT == 1U)
+//Cache Sync operation
+__STATIC_INLINE void L2C_Sync(void)
+{
+  L2C_310->CACHE_SYNC = 0x0;
+}
+
+//return Cache controller cache ID
+__STATIC_INLINE int L2C_GetID (void)
+{
+  return L2C_310->CACHE_ID;
+}
+
+//return Cache controller cache Type
+__STATIC_INLINE int L2C_GetType (void)
+{
+  return L2C_310->CACHE_TYPE;
+}
+
+//Invalidate all cache by way
+__STATIC_INLINE void L2C_InvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1<<16))
+    assoc = 16;
+  else
+    assoc =  8;
+
+  L2C_310->INV_WAY = (1 << assoc) - 1;
+  while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+
+  L2C_Sync();
+}
+
+//Clean and Invalidate all cache by way
+__STATIC_INLINE void L2C_CleanInvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1<<16))
+    assoc = 16;
+  else
+    assoc =  8;
+
+  L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
+  while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+
+  L2C_Sync();
+}
+
+//Enable Cache
+__STATIC_INLINE void L2C_Enable(void)
+{
+  L2C_310->CONTROL = 0;
+  L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
+  L2C_310->DEBUG_CONTROL = 0;
+  L2C_310->DATA_LOCK_0_WAY = 0;
+  L2C_310->CACHE_SYNC = 0;
+  L2C_310->CONTROL = 0x01;
+  L2C_Sync();
+}
+//Disable Cache
+__STATIC_INLINE void L2C_Disable(void)
+{
+  L2C_310->CONTROL = 0x00;
+  L2C_Sync();
+}
+
+//Invalidate cache by physical address
+__STATIC_INLINE void L2C_InvPa (void *pa)
+{
+  L2C_310->INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+//Clean cache by physical address
+__STATIC_INLINE void L2C_CleanPa (void *pa)
+{
+  L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+//Clean and invalidate cache by physical address
+__STATIC_INLINE void L2C_CleanInvPa (void *pa)
+{
+  L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+#endif
+
+/* ##########################  GIC functions  ###################################### */
+#if (__GIC_PRESENT == 1U)
+  
+__STATIC_INLINE void GIC_EnableDistributor(void)
+{
+  GICDistributor->ICDDCR |= 1; //enable distributor
+}
+
+__STATIC_INLINE void GIC_DisableDistributor(void)
+{
+  GICDistributor->ICDDCR &=~1; //disable distributor
+}
+
+__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
+{
+  return (uint32_t)(GICDistributor->ICDICTR);
+}
+
+__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
+{
+  return (uint32_t)(GICDistributor->ICDIIDR);
+}
+
+__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+  char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+  field += IRQn % 4;
+  *field = (char)cpu_target & 0xf;
+}
+
+__STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
+{
+  uint32_t i, num_irq;
+
+  //Get the maximum number of interrupts that the GIC supports
+  num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+  for (i = 0; i < (num_irq/16); i++)
+  {
+    GICDistributor->ICDISPR[i] = *ICDICFRn++;
+  }
+}
+
+__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+  char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+  field += IRQn % 4;
+  return ((uint32_t)*field & 0xf);
+}
+
+__STATIC_INLINE void GIC_EnableInterface(void)
+{
+  GICInterface->ICCICR |= 1; //enable interface
+}
+
+__STATIC_INLINE void GIC_DisableInterface(void)
+{
+  GICInterface->ICCICR &=~1; //disable distributor
+}
+
+__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
+{
+  return (IRQn_Type)(GICInterface->ICCIAR);
+}
+
+__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+  GICInterface->ICCEOIR = IRQn;
+}
+
+__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+__STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
+{   
+  // Word-size read/writes must be used to access this register
+  volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
+  unsigned bit_shift = (IRQn % 16)<<1;
+  unsigned int save_word;
+
+  save_word = *field;
+  save_word &= (~(3 << bit_shift));
+
+  *field = (save_word | (((edge_level<<1) | model) << bit_shift));
+}
+
+__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
+  field += IRQn % 4;
+  *field = (char)priority;
+}
+
+__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+  char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
+  field += IRQn % 4;
+  return (uint32_t)*field;
+}
+
+__STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
+{
+  GICInterface->ICCPMR = priority & 0xff; //set priority mask
+}
+
+__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+  GICInterface->ICCBPR = binary_point & 0x07; //set binary point
+}
+
+__STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
+{
+  return (uint32_t)GICInterface->ICCBPR;
+}
+
+__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+  uint32_t pending, active;
+
+  active = ((GICDistributor->ICDABR[IRQn / 32])  >> (IRQn % 32)) & 0x1;
+  pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+
+  return ((active<<1) | pending);
+}
+
+__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+  GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
+}
+
+__STATIC_INLINE void GIC_DistInit(void)
+{
+  IRQn_Type i;
+  uint32_t num_irq = 0;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableDistributor();
+  //Get the maximum number of interrupts that the GIC supports
+  num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an ICDIPR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0, 0xff);
+  priority_field = GIC_GetPriority((IRQn_Type)0);
+
+  for (i = (IRQn_Type)32; i < num_irq; i++)
+  {
+      //Disable the SPI interrupt
+      GIC_DisableIRQ(i);
+      //Set level-sensitive and 1-N model
+      GIC_SetLevelModel(i, 0, 1);
+      //Set priority
+      GIC_SetPriority(i, priority_field/2);
+      //Set target list to CPU0
+      GIC_SetTarget(i, 1);
+  }
+  //Enable distributor
+  GIC_EnableDistributor();
+}
+
+__STATIC_INLINE void GIC_CPUInterfaceInit(void)
+{
+  IRQn_Type i;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableInterface();
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an ICDIPR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0, 0xff);
+  priority_field = GIC_GetPriority((IRQn_Type)0);
+
+  //SGI and PPI
+  for (i = (IRQn_Type)0; i < 32; i++)
+  {
+      //Set level-sensitive and 1-N model for PPI
+    if(i > 15)
+          GIC_SetLevelModel(i, 0, 1);
+      //Disable SGI and PPI interrupts
+      GIC_DisableIRQ(i);
+      //Set priority
+      GIC_SetPriority(i, priority_field/2);
+  }
+  //Enable interface
+  GIC_EnableInterface();
+  //Set binary point to 0
+  GIC_SetBinaryPoint(0);
+  //Set priority mask
+  GIC_InterfacePriorityMask(0xff);
+}
+
+__STATIC_INLINE void GIC_Enable(void)
+{
+  GIC_DistInit();
+  GIC_CPUInterfaceInit(); //per CPU
+}
+#endif
+
+/* ##########################  Generic Timer functions  ############################ */
+#if (__TIM_PRESENT == 1U)
+  
+/* PL1 Physical Timer */
+#if (__CORTEX_A == 7U)
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
+  __set_CNTP_TVAL(value);
+  __ISB();
+}
+
+__STATIC_INLINE uint32_t PL1_GetCurrentValue() {
+  return(__get_CNTP_TVAL());
+}
+
+__STATIC_INLINE void PL1_SetControl(uint32_t value) {
+  __set_CNTP_CTL(value);
+  __ISB();
+}
+
+/* Private Timer */
+#elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
+__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
+  PTIM->LOAD = value;
+}
+
+__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
+  return(PTIM->LOAD);
+}
+
+__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
+  return(PTIM->COUNTER);
+}
+
+__STATIC_INLINE void PTIM_SetControl(uint32_t value) {
+  PTIM->CONTROL = value;
+}
+
+__STATIC_INLINE uint32_t PTIM_GetControl(void) {
+  return(PTIM->CONTROL);
+}
+
+__STATIC_INLINE void PTIM_ClearEventFlag(void) {
+  PTIM->ISR = 1;
+}
+#endif
+#endif
+
+/* ##########################  MMU functions  ###################################### */
+
+#define SECTION_DESCRIPTOR      (0x2)
+#define SECTION_MASK            (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
+#define SECTION_B_SHIFT         (2)
+#define SECTION_C_SHIFT         (3)
+#define SECTION_TEX0_SHIFT      (12)
+#define SECTION_TEX1_SHIFT      (13)
+#define SECTION_TEX2_SHIFT      (14)
+
+#define SECTION_XN_MASK         (0xFFFFFFEF)
+#define SECTION_XN_SHIFT        (4)
+
+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT    (5)
+
+#define SECTION_P_MASK          (0xFFFFFDFF)
+#define SECTION_P_SHIFT         (9)
+
+#define SECTION_AP_MASK         (0xFFFF73FF)
+#define SECTION_AP_SHIFT        (10)
+#define SECTION_AP2_SHIFT       (15)
+
+#define SECTION_S_MASK          (0xFFFEFFFF)
+#define SECTION_S_SHIFT         (16)
+
+#define SECTION_NG_MASK         (0xFFFDFFFF)
+#define SECTION_NG_SHIFT        (17)
+
+#define SECTION_NS_MASK         (0xFFF7FFFF)
+#define SECTION_NS_SHIFT        (19)
+
+#define PAGE_L1_DESCRIPTOR      (0x1)
+#define PAGE_L1_MASK            (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC         (0x2)
+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC        (0x1)
+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT         (2)
+#define PAGE_4K_C_SHIFT         (3)
+#define PAGE_4K_TEX0_SHIFT      (6)
+#define PAGE_4K_TEX1_SHIFT      (7)
+#define PAGE_4K_TEX2_SHIFT      (8)
+
+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT        (2)
+#define PAGE_64K_C_SHIFT        (3)
+#define PAGE_64K_TEX0_SHIFT     (12)
+#define PAGE_64K_TEX1_SHIFT     (13)
+#define PAGE_64K_TEX2_SHIFT     (14)
+
+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
+#define PAGE_B_SHIFT            (2)
+#define PAGE_C_SHIFT            (3)
+#define PAGE_TEX_SHIFT          (12)
+
+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT        (0)
+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT       (15)
+
+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT       (5)
+
+#define PAGE_P_MASK             (0xFFFFFDFF)
+#define PAGE_P_SHIFT            (9)
+
+#define PAGE_AP_MASK            (0xFFFFFDCF)
+#define PAGE_AP_SHIFT           (4)
+#define PAGE_AP2_SHIFT          (9)
+
+#define PAGE_S_MASK             (0xFFFFFBFF)
+#define PAGE_S_SHIFT            (10)
+
+#define PAGE_NG_MASK            (0xFFFFF7FF)
+#define PAGE_NG_SHIFT           (11)
+
+#define PAGE_NS_MASK            (0xFFFFFFF7)
+#define PAGE_NS_SHIFT           (3)
+
+#define OFFSET_1M               (0x00100000)
+#define OFFSET_64K              (0x00010000)
+#define OFFSET_4K               (0x00001000)
+
+#define DESCRIPTOR_FAULT        (0x00000000)
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+   SECTION,
+   PAGE_4k,
+   PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+   NORMAL,
+   DEVICE,
+   SHARED_DEVICE,
+   NON_SHARED_DEVICE,
+   STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+   NON_CACHEABLE,
+   WB_WA,
+   WT,
+   WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+   ECC_DISABLED,
+   ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+   EXECUTE,
+   NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+   GLOBAL,
+   NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+   NON_SHARED,
+   SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+   SECURE,
+   NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+   NO_ACCESS,
+   RW,
+   READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+    mmu_region_size_Type rg_t;
+    mmu_memory_Type mem_t;
+    uint8_t domain;
+    mmu_cacheability_Type inner_norm_t;
+    mmu_cacheability_Type outer_norm_t;
+    mmu_ecc_check_Type e_t;
+    mmu_execute_Type xn_t;
+    mmu_global_Type g_t;
+    mmu_secure_Type sec_t;
+    mmu_access_Type priv_t;
+    mmu_access_Type user_t;
+    mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+//Following macros define the descriptors and attributes
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
+#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+/** \brief  Set section execution-never attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+  *descriptor_l1 &= SECTION_XN_MASK;
+  *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Section domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= SECTION_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section access privileges
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l1 &= SECTION_AP_MASK;
+  *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+  *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set section shareability
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_S_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Global attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+  *descriptor_l1 &= SECTION_NG_MASK;
+  *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+  return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief  Set 4k/64k page execution-never attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
+  \param [in]              page  Page size: PAGE_4k, PAGE_64k,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+  if (page == PAGE_4k)
+  {
+      *descriptor_l2 &= PAGE_XN_4K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+  }
+  else
+  {
+      *descriptor_l2 &= PAGE_XN_64K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Page domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= PAGE_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page access privileges
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x6; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l2 &= PAGE_AP_MASK;
+  *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+  *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set 4k/64k page shareability
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+  *descriptor_l2 &= PAGE_S_MASK;
+  *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Global attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+  *descriptor_l2 &= PAGE_NG_MASK;
+  *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= PAGE_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+  return 0;
+}
+
+/** \brief  Set Section memory attributes
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+  *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+  if (STRONGLY_ORDERED == mem)
+  {
+    return 0;
+  }
+  else if (SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+  }
+  else if (NON_SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+  }
+  else if (NORMAL == mem)
+  {
+   *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+   switch(inner)
+   {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+        break;
+    }
+    switch(outer)
+    {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+        break;
+    }
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page memory attributes
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]              page  Page size
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+  *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+  if (page == PAGE_64k)
+  {
+    //same as section
+    MMU_MemorySection(descriptor_l2, mem, outer, inner);
+  }
+  else
+  {
+    if (STRONGLY_ORDERED == mem)
+    {
+      return 0;
+    }
+    else if (SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+    }
+    else if (NON_SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+    }
+    else if (NORMAL == mem)
+    {
+      *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+      switch(inner)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+          break;
+      }
+      switch(outer)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+      }
+    }
+  }
+
+  return 0;
+}
+
+/** \brief  Create a L1 section descriptor
+
+  \param [out]     descriptor  L1 descriptor
+  \param [in]      reg  Section attributes
+  
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+
+  MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+  MMU_XNSection(descriptor,reg.xn_t);
+  MMU_DomainSection(descriptor, reg.domain);
+  MMU_PSection(descriptor, reg.e_t);
+  MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
+  MMU_SharedSection(descriptor,reg.sh_t);
+  MMU_GlobalSection(descriptor,reg.g_t);
+  MMU_SecureSection(descriptor,reg.sec_t);
+  *descriptor &= SECTION_MASK;
+  *descriptor |= SECTION_DESCRIPTOR;
+ 
+  return 0;
+}
+
+
+/** \brief  Create a L1 and L2 4k/64k page descriptor
+
+  \param [out]       descriptor  L1 descriptor
+  \param [out]      descriptor2  L2 descriptor
+  \param [in]               reg  4k/64k page attributes
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+  *descriptor2 = 0;
+
+  switch (reg.rg_t)
+  {
+    case PAGE_4k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_4K_MASK;
+      *descriptor2 |= PAGE_L2_4K_DESC;
+      break;
+
+    case PAGE_64k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_64K_MASK;
+      *descriptor2 |= PAGE_L2_64K_DESC;
+      break;
+
+    case SECTION:
+      //error
+      break;
+  }
+  
+  return 0;
+}
+
+/** \brief  Create a 1MB Section
+
+  \param [in]               ttb  Translation table base address
+  \param [in]      base_address  Section base address
+  \param [in]             count  Number of sections to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+  uint32_t offset;
+  uint32_t entry;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = (base_address & 0xFFF00000) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb = ttb + offset;
+
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb++ = entry;
+    entry += OFFSET_1M;
+  }
+}
+
+/** \brief  Create a 4k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  4k base address
+  \param [in]             count  Number of 4k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb_l2++ = entry2;
+    entry2 += OFFSET_4K;
+  }
+}
+
+/** \brief  Create a 64k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  64k base address
+  \param [in]             count  Number of 64k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i,j;
+
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //create 16 entries
+    for (j = 0; j < 16; j++)
+    {
+      //4 bytes aligned
+      *ttb_l2++ = entry2;
+    }
+    entry2 += OFFSET_64K;
+  }
+}
+
+/** \brief  Enable MMU
+
+  Enable MMU
+*/
+__STATIC_INLINE void MMU_Enable(void) {
+  // Set M bit 0 to enable the MMU
+  // Set AFE bit to enable simplified access permissions model
+  // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+  __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+  __ISB();
+}
+
+/** \brief  Disable MMU
+
+  Disable MMU
+*/
+__STATIC_INLINE void MMU_Disable(void) {
+  // Clear M bit 0 to disable the MMU
+  __set_SCTLR( __get_SCTLR() & ~1);
+  __ISB();
+}
+
+/** \brief  Invalidate entire unified TLB
+
+  TLBIALL. Invalidate entire unified TLB
+*/
+
+__STATIC_INLINE void MMU_InvalidateTLB(void) {
+  __set_TLBIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm0.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm0.h
new file mode 100755
index 0000000..f1fbbe9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm0.h
@@ -0,0 +1,886 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm0plus.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm0plus.h
new file mode 100755
index 0000000..2dca31a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm0plus.h
@@ -0,0 +1,1012 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm23.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm23.h
new file mode 100755
index 0000000..378c69b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm23.h
@@ -0,0 +1,1876 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+/*  CMSIS cmGrebe definitions */
+#define __CM23_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm3.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm3.h
new file mode 100755
index 0000000..cfeb58b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm3.h
@@ -0,0 +1,1919 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm33.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm33.h
new file mode 100755
index 0000000..9e880ae
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm33.h
@@ -0,0 +1,2896 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )     /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm4.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm4.h
new file mode 100755
index 0000000..bdaedcf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm4.h
@@ -0,0 +1,2103 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm7.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm7.h
new file mode 100755
index 0000000..fee3d0c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cm7.h
@@ -0,0 +1,2646 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    register uint32_t ccsidr;
+    register uint32_t sets;
+    register uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cmSecureAccess.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cmSecureAccess.h
new file mode 100755
index 0000000..4903efd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_cmSecureAccess.h
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file     core_cmSecureAccess.h
+ * @brief    CMSIS Cortex-M Core Secure Access Header File
+ * @version  XXX
+ * @date     10. June 2016
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2016 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CM_SECURE_ACCESS_H
+#define __CORE_CM_SECURE_ACCESS_H
+
+
+/* ###########################  Core Secure Access  ########################### */
+
+#ifdef FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+
+/* Secure uVisor implementation. */
+
+/** Set the value at the target address.
+ *
+ * Equivalent to: `*address = value`.
+ * @param address[in]  Target address
+ * @param value[in]    Value to write at the address location.
+ */
+#define SECURE_WRITE(address, value) \
+    uvisor_write(public_box, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
+
+/** Get the value at the target address.
+ *
+ * @param address[in]  Target address
+ * @returns The value `*address`.
+ */
+#define SECURE_READ(address) \
+    uvisor_read(public_box, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
+
+/** Get the selected bits at the target address.
+ *
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `*address & mask`.
+ */
+#define SECURE_BITS_GET(address, mask) \
+    UVISOR_BITS_GET(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Check the selected bits at the target address.
+ *
+ * @param address[in]  Address at which to check the bits
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `((*address & mask) == mask)`.
+ */
+#define SECURE_BITS_CHECK(address, mask) \
+    UVISOR_BITS_CHECK(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Set the selected bits to 1 at the target address.
+ *
+ * Equivalent to: `*address |= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_SET(address, mask) \
+    UVISOR_BITS_SET(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Clear the selected bits at the target address.
+ *
+ * Equivalent to: `*address &= ~mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_CLEAR(address, mask) \
+    UVISOR_BITS_CLEAR(public_box, UVISOR_RGW_SHARED, address, mask)
+
+/** Set the selected bits at the target address to the given value.
+ *
+ * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @param value[in]    Value to write at the address location. Note: The value
+ *                     must be already shifted to the correct bit position
+ */
+#define SECURE_BITS_SET_VALUE(address, mask, value) \
+    UVISOR_BITS_SET_VALUE(public_box, UVISOR_RGW_SHARED, address, mask, value)
+
+/** Toggle the selected bits at the target address.
+ *
+ * Equivalent to: `*address ^= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_TOGGLE(address, mask) \
+    UVISOR_BITS_TOGGLE(public_box, UVISOR_RGW_SHARED, address, mask)
+
+#else
+
+/* Insecure fallback implementation. */
+
+/** Set the value at the target address.
+ *
+ * Equivalent to: `*address = value`.
+ * @param address[in]  Target address
+ * @param value[in]    Value to write at the address location.
+ */
+#define SECURE_WRITE(address, value) \
+    *(address) = (value)
+
+/** Get the value at the target address.
+ *
+ * @param address[in]  Target address
+ * @returns The value `*address`.
+ */
+#define SECURE_READ(address) \
+    (*(address))
+
+/** Get the selected bits at the target address.
+ *
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `*address & mask`.
+ */
+#define SECURE_BITS_GET(address, mask) \
+    (*(address) & (mask))
+
+/** Check the selected bits at the target address.
+ *
+ * @param address[in]  Address at which to check the bits
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `((*address & mask) == mask)`.
+ */
+#define SECURE_BITS_CHECK(address, mask) \
+    ((*(address) & (mask)) == (mask))
+
+/** Set the selected bits to 1 at the target address.
+ *
+ * Equivalent to: `*address |= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_SET(address, mask) \
+    *(address) |= (mask)
+
+/** Clear the selected bits at the target address.
+ *
+ * Equivalent to: `*address &= ~mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_CLEAR(address, mask) \
+    *(address) &= ~(mask)
+
+/** Set the selected bits at the target address to the given value.
+ *
+ * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @param value[in]    Value to write at the address location. Note: The value
+ *                     must be already shifted to the correct bit position
+ */
+#define SECURE_BITS_SET_VALUE(address, mask, value) \
+    *(address) = (*(address) & ~(mask)) | ((value) & (mask))
+
+/** Toggle the selected bits at the target address.
+ *
+ * Equivalent to: `*address ^= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_TOGGLE(address, mask) \
+    *(address) ^= (mask)
+
+#endif
+
+#endif /* __CORE_CM_SECURE_ACCESS_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_sc000.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_sc000.h
new file mode 100755
index 0000000..53dfaad
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_sc000.h
@@ -0,0 +1,1014 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_sc300.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_sc300.h
new file mode 100755
index 0000000..78450e0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/core_sc300.h
@@ -0,0 +1,1901 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/tz_context.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/tz_context.h
new file mode 100755
index 0000000..0784d26
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/cmsis/tz_context.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date:        21. September 2016
+ * $Revision:    V1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+  
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogIn.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogIn.cpp
new file mode 100755
index 0000000..86fd7be
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogIn.cpp
@@ -0,0 +1,27 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "drivers/AnalogIn.h"
+
+#if DEVICE_ANALOGIN
+
+namespace mbed {
+
+SingletonPtr<PlatformMutex> AnalogIn::_mutex;
+
+};
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogIn.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogIn.h
new file mode 100755
index 0000000..e81428f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogIn.h
@@ -0,0 +1,130 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_ANALOGIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/analogin_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(temperature > 0.5) {
+ *             printf("Too hot! (%f)", temperature.read());
+ *         }
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class AnalogIn {
+
+public:
+
+    /** Create an AnalogIn, connected to the specified pin
+     *
+     * @param pin AnalogIn pin to connect to
+     */
+    AnalogIn(PinName pin) {
+        lock();
+        analogin_init(&_adc, pin);
+        unlock();
+    }
+
+    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+     *
+     * @returns A floating-point value representing the current input voltage, measured as a percentage
+     */
+    float read() {
+        lock();
+        float ret = analogin_read(&_adc);
+        unlock();
+        return ret;
+    }
+
+    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     * @returns
+     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+     */
+    unsigned short read_u16() {
+        lock();
+        unsigned short ret = analogin_read_u16(&_adc);
+        unlock();
+        return ret;
+    }
+
+    /** An operator shorthand for read()
+     *
+     * The float() operator can be used as a shorthand for read() to simplify common code sequences
+     *
+     * Example:
+     * @code
+     * float x = volume.read();
+     * float x = volume;
+     *
+     * if(volume.read() > 0.25) { ... }
+     * if(volume > 0.25) { ... }
+     * @endcode
+     */
+    operator float() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+    virtual ~AnalogIn() {
+        // Do nothing
+    }
+
+protected:
+
+    virtual void lock() {
+        _mutex->lock();
+    }
+
+    virtual void unlock() {
+        _mutex->unlock();
+    }
+
+    analogin_t _adc;
+    static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogOut.h
new file mode 100755
index 0000000..5038f0f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/AnalogOut.h
@@ -0,0 +1,153 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_ANALOGOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/analogout_api.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ *     while(1) {
+ *         tri = tri + 0.01;
+ *         wait_us(1);
+ *         if(tri == 1) {
+ *             tri = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class AnalogOut {
+
+public:
+
+    /** Create an AnalogOut connected to the specified pin
+     *
+     * @param pin AnalogOut pin to connect to
+     */
+    AnalogOut(PinName pin) {
+        analogout_init(&_dac, pin);
+    }
+
+    /** Set the output voltage, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output voltage,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        lock();
+        analogout_write(&_dac, value);
+        unlock();
+    }
+
+    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     *  @param value 16-bit unsigned short representing the output voltage,
+     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+     */
+    void write_u16(unsigned short value) {
+        lock();
+        analogout_write_u16(&_dac, value);
+        unlock();
+    }
+
+    /** Return the current output voltage setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current voltage being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *
+     *  @note
+     *    This value may not match exactly the value set by a previous write().
+     */
+    float read() {
+        lock();
+        float ret = analogout_read(&_dac);
+        unlock();
+        return ret;
+    }
+
+    /** An operator shorthand for write()
+     * \sa AnalogOut::write()
+     */
+    AnalogOut& operator= (float percent) {
+        // Underlying write call is thread safe
+        write(percent);
+        return *this;
+    }
+
+    /** An operator shorthand for write()
+     * \sa AnalogOut::write()
+     */
+    AnalogOut& operator= (AnalogOut& rhs) {
+        // Underlying write call is thread safe
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     * \sa AnalogOut::read()
+     */
+    operator float() {
+        // Underlying read call is thread safe
+        return read();
+    }
+
+    virtual ~AnalogOut() {
+        // Do nothing
+    }
+
+protected:
+
+    virtual void lock() {
+        _mutex.lock();
+    }
+
+    virtual void unlock() {
+        _mutex.unlock();
+    }
+
+    dac_t _dac;
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusIn.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusIn.cpp
new file mode 100755
index 0000000..1fd0528
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusIn.cpp
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusIn.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusIn::~BusIn() {
+    // No lock needed in the destructor
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+int BusIn::read() {
+    int v = 0;
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    unlock();
+    return v;
+}
+
+void BusIn::mode(PinMode pull) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+    unlock();
+}
+
+void BusIn::lock() {
+    _mutex.lock();
+}
+
+void BusIn::unlock() {
+    _mutex.unlock();
+}
+
+BusIn::operator int() {
+    // Underlying read is thread safe
+    return read();
+}
+
+DigitalIn& BusIn::operator[] (int index) {
+    // No lock needed since _pin is not modified outside the constructor
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusIn.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusIn.h
new file mode 100755
index 0000000..d015529
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusIn.h
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform/platform.h"
+#include "drivers/DigitalIn.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input bus, used for reading the state of a collection of pins
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class BusIn : private NonCopyable<BusIn> {
+
+public:
+    /* Group: Configuration Methods */
+
+    /** Create an BusIn, connected to the specified pins
+     *
+     * @param p0 DigitalIn pin to connect to bus bit
+     * @param p1 DigitalIn pin to connect to bus bit
+     * @param p2 DigitalIn pin to connect to bus bit
+     * @param p3 DigitalIn pin to connect to bus bit
+     * @param p4 DigitalIn pin to connect to bus bit
+     * @param p5 DigitalIn pin to connect to bus bit
+     * @param p6 DigitalIn pin to connect to bus bit
+     * @param p7 DigitalIn pin to connect to bus bit
+     * @param p8 DigitalIn pin to connect to bus bit
+     * @param p9 DigitalIn pin to connect to bus bit
+     * @param p10 DigitalIn pin to connect to bus bit
+     * @param p11 DigitalIn pin to connect to bus bit
+     * @param p12 DigitalIn pin to connect to bus bit
+     * @param p13 DigitalIn pin to connect to bus bit
+     * @param p14 DigitalIn pin to connect to bus bit
+     * @param p15 DigitalIn pin to connect to bus bit
+     *
+     * @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    
+    /** Create an BusIn, connected to the specified pins
+     *
+     * @param pins An array of pins to connect to bus bit
+     */
+     BusIn(PinName pins[16]);
+
+    virtual ~BusIn();
+
+    /** Read the value of the input bus
+     *
+     *  @returns
+     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
+     */
+    int read();
+
+    /** Set the input pin mode
+     *
+     *  @param pull PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        // No lock needed since _nc_mask is not modified outside the constructor
+        return _nc_mask;
+    }
+
+    /** A shorthand for read()
+     *  \sa DigitalIn::read()
+     */
+    operator int();
+
+    /** Access to particular bit in random-iterator fashion
+     * @param index  Position of bit
+     */
+    DigitalIn & operator[] (int index);
+
+protected:
+    DigitalIn* _pin[16];
+
+    /* Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    PlatformMutex _mutex;
+
+private:
+    virtual void lock();
+    virtual void unlock();
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusInOut.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusInOut.cpp
new file mode 100755
index 0000000..ff244fa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusInOut.cpp
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusInOut.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusInOut::~BusInOut() {
+    // No lock needed in the destructor
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusInOut::write(int value) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+    unlock();
+}
+
+int BusInOut::read() {
+    lock();
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    unlock();
+    return v;
+}
+
+void BusInOut::output() {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->output();
+        }
+    }
+    unlock();
+}
+
+void BusInOut::input() {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->input();
+        }
+    }
+    unlock();
+}
+
+void BusInOut::mode(PinMode pull) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+    unlock();
+}
+
+BusInOut& BusInOut::operator= (int v) {
+    // Underlying write is thread safe
+    write(v);
+    return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+    // Underlying read is thread safe
+    write(rhs.read());
+    return *this;
+}
+
+DigitalInOut& BusInOut::operator[] (int index) {
+    // No lock needed since _pin is not modified outside the constructor
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+BusInOut::operator int() {
+    // Underlying read is thread safe
+    return read();
+}
+
+void BusInOut::lock() {
+    _mutex.lock();
+}
+
+void BusInOut::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusInOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusInOut.h
new file mode 100755
index 0000000..0be52ca
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusInOut.h
@@ -0,0 +1,143 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "drivers/DigitalInOut.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class BusInOut : private NonCopyable<BusInOut> {
+
+public:
+
+    /** Create an BusInOut, connected to the specified pins
+     *
+     *  @param p0 DigitalInOut pin to connect to bus bit
+     *  @param p1 DigitalInOut pin to connect to bus bit
+     *  @param p2 DigitalInOut pin to connect to bus bit
+     *  @param p3 DigitalInOut pin to connect to bus bit
+     *  @param p4 DigitalInOut pin to connect to bus bit
+     *  @param p5 DigitalInOut pin to connect to bus bit
+     *  @param p6 DigitalInOut pin to connect to bus bit
+     *  @param p7 DigitalInOut pin to connect to bus bit
+     *  @param p8 DigitalInOut pin to connect to bus bit
+     *  @param p9 DigitalInOut pin to connect to bus bit
+     *  @param p10 DigitalInOut pin to connect to bus bit
+     *  @param p11 DigitalInOut pin to connect to bus bit
+     *  @param p12 DigitalInOut pin to connect to bus bit
+     *  @param p13 DigitalInOut pin to connect to bus bit
+     *  @param p14 DigitalInOut pin to connect to bus bit
+     *  @param p15 DigitalInOut pin to connect to bus bit
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    /** Create an BusInOut, connected to the specified pins
+     *
+     *  @param pins An array of pins to construct a BusInOut from
+     */
+    BusInOut(PinName pins[16]);
+
+    virtual ~BusInOut();
+
+    /* Group: Access Methods */
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalInOut pin setting
+     */
+    int read();
+
+    /** Set as an output
+     */
+    void output();
+
+    /** Set as an input
+     */
+    void input();
+
+    /** Set the input pin mode
+     *
+     *  @param pull PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        // No lock needed since _nc_mask is not modified outside the constructor
+        return _nc_mask;
+    }
+
+     /** A shorthand for write()
+    * \sa BusInOut::write()
+      */
+    BusInOut& operator= (int v);
+    BusInOut& operator= (BusInOut& rhs);
+
+    /** Access to particular bit in random-iterator fashion
+     * @param index  Bit Position
+     */
+    DigitalInOut& operator[] (int index);
+
+    /** A shorthand for read()
+     * \sa BusInOut::read()
+     */
+    operator int();
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    DigitalInOut* _pin[16];
+
+    /* Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusOut.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusOut.cpp
new file mode 100755
index 0000000..9019552
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusOut.cpp
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusOut.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusOut::~BusOut() {
+    // No lock needed in the destructor
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusOut::write(int value) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+    unlock();
+}
+
+int BusOut::read() {
+    lock();
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    unlock();
+    return v;
+}
+
+BusOut& BusOut::operator= (int v) {
+    // Underlying write is thread safe
+    write(v);
+    return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+    // Underlying write is thread safe
+    write(rhs.read());
+    return *this;
+}
+
+DigitalOut& BusOut::operator[] (int index) {
+    // No lock needed since _pin is not modified outside the constructor
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+BusOut::operator int() {
+    // Underlying read is thread safe
+    return read();
+}
+
+void BusOut::lock() {
+    _mutex.lock();
+}
+
+void BusOut::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusOut.h
new file mode 100755
index 0000000..d7612d4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/BusOut.h
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "drivers/DigitalOut.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital output bus, used for setting the state of a collection of pins
+ * @ingroup drivers
+ */
+class BusOut : private NonCopyable<BusOut> {
+
+public:
+
+    /** Create an BusOut, connected to the specified pins
+     *
+     *  @param p0 DigitalOut pin to connect to bus bit
+     *  @param p1 DigitalOut pin to connect to bus bit
+     *  @param p2 DigitalOut pin to connect to bus bit
+     *  @param p3 DigitalOut pin to connect to bus bit
+     *  @param p4 DigitalOut pin to connect to bus bit
+     *  @param p5 DigitalOut pin to connect to bus bit
+     *  @param p6 DigitalOut pin to connect to bus bit
+     *  @param p7 DigitalOut pin to connect to bus bit
+     *  @param p8 DigitalOut pin to connect to bus bit
+     *  @param p9 DigitalOut pin to connect to bus bit
+     *  @param p10 DigitalOut pin to connect to bus bit
+     *  @param p11 DigitalOut pin to connect to bus bit
+     *  @param p12 DigitalOut pin to connect to bus bit
+     *  @param p13 DigitalOut pin to connect to bus bit
+     *  @param p14 DigitalOut pin to connect to bus bit
+     *  @param p15 DigitalOut pin to connect to bus bit
+     *
+     *  @note Synchronization level: Thread safe
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    /** Create an BusOut, connected to the specified pins
+     *
+     *  @param pins An array of pins to connect to bus the bit
+     */
+    BusOut(PinName pins[16]);
+
+    virtual ~BusOut();
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalOut pin setting
+     */
+    int read();
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        // No lock needed since _nc_mask is not modified outside the constructor
+        return _nc_mask;
+    }
+
+    /** A shorthand for write()
+     * \sa BusOut::write()
+     */
+    BusOut& operator= (int v);
+    BusOut& operator= (BusOut& rhs);
+
+    /** Access to particular bit in random-iterator fashion
+     * @param index  Bit Position
+     */
+    DigitalOut& operator[] (int index);
+
+    /** A shorthand for read()
+     * \sa BusOut::read()
+     */
+    operator int();
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    DigitalOut* _pin[16];
+
+    /* Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/CAN.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/CAN.cpp
new file mode 100755
index 0000000..b84d608
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/CAN.cpp
@@ -0,0 +1,156 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+#include "platform/mbed_sleep.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
+    // No lock needed in constructor
+
+    for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+        _irq[i] = NULL;
+    }
+
+    can_init(&_can, rd, td);
+    can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::CAN(PinName rd, PinName td, int hz) : _can(), _irq() {
+    // No lock needed in constructor
+
+    for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+        _irq[i] = NULL;
+    }
+
+    can_init_freq(&_can, rd, td, hz);
+    can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN() {
+    // No lock needed in destructor
+
+    // Detaching interrupts releases the sleep lock if it was locked
+    for (int irq = 0; irq < IrqCnt; irq++) {
+        attach(NULL, (IrqType)irq);
+    }
+    can_irq_free(&_can);
+    can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+    lock();
+    int ret = can_frequency(&_can, f);
+    unlock();
+    return ret;
+}
+
+int CAN::write(CANMessage msg) {
+    lock();
+    int ret = can_write(&_can, msg, 0);
+    unlock();
+    return ret;
+}
+
+int CAN::read(CANMessage &msg, int handle) {
+    lock();
+    int ret = can_read(&_can, &msg, handle);
+    unlock();
+    return ret;
+}
+
+void CAN::reset() {
+    lock();
+    can_reset(&_can);
+    unlock();
+}
+
+unsigned char CAN::rderror() {
+    lock();
+    int ret = can_rderror(&_can);
+    unlock();
+    return ret;
+}
+
+unsigned char CAN::tderror() {
+    lock();
+    int ret = can_tderror(&_can);
+    unlock();
+    return ret;
+}
+
+void CAN::monitor(bool silent) {
+    lock();
+    can_monitor(&_can, (silent) ? 1 : 0);
+    unlock();
+}
+
+int CAN::mode(Mode mode) {
+    lock();
+    int ret = can_mode(&_can, (CanMode)mode);
+    unlock();
+    return ret;
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
+    lock();
+    int ret = can_filter(&_can, id, mask, format, handle);
+    unlock();
+    return ret;
+}
+
+void CAN::attach(Callback<void()> func, IrqType type) {
+    lock();
+    if (func) {
+        // lock deep sleep only the first time
+        if (!_irq[(CanIrqType)type]) {
+            sleep_manager_lock_deep_sleep();
+        }
+        _irq[(CanIrqType)type] = func;
+        can_irq_set(&_can, (CanIrqType)type, 1);
+    } else {
+        // unlock deep sleep only the first time
+        if (_irq[(CanIrqType)type]) {
+            sleep_manager_unlock_deep_sleep();
+        }
+        _irq[(CanIrqType)type] = NULL;
+        can_irq_set(&_can, (CanIrqType)type, 0);
+    }
+    unlock();
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+    CAN *handler = (CAN*)id;
+    if (handler->_irq[type]) {
+        handler->_irq[type].call();
+    }
+}
+
+void CAN::lock() {
+    _mutex.lock();
+}
+
+void CAN::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/CAN.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/CAN.h
new file mode 100755
index 0000000..668e32c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/CAN.h
@@ -0,0 +1,299 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_CAN) || defined(DOXYGEN_ONLY)
+
+#include "hal/can_api.h"
+#include "platform/Callback.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** CANMessage class
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class CANMessage : public CAN_Message {
+
+public:
+    /** Creates empty CAN message.
+     */
+    CANMessage() : CAN_Message() {
+        len    = 8;
+        type   = CANData;
+        format = CANStandard;
+        id     = 0;
+        memset(data, 0, 8);
+    }
+
+    /** Creates CAN message with specific content.
+     *
+     *  @param _id      Message ID
+     *  @param _data    Mesaage Data
+     *  @param _len     Message Data length
+     *  @param _type    Type of Data: Use enum CANType for valid parameter values
+     *  @param _format  Data Format: Use enum CANFormat for valid parameter values
+     */
+    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+      len    = _len & 0xF;
+      type   = _type;
+      format = _format;
+      id     = _id;
+      memcpy(data, _data, _len);
+    }
+
+    /** Creates CAN remote message.
+     *
+     *  @param _id      Message ID
+     *  @param _format  Data Format: Use enum CANType for valid parameter values
+     */
+    CANMessage(int _id, CANFormat _format = CANStandard) {
+      len    = 0;
+      type   = CANRemote;
+      format = _format;
+      id     = _id;
+      memset(data, 0, 8);
+    }
+};
+
+/** A can bus client, used for communicating with can devices
+ * @ingroup drivers
+ */
+class CAN : private NonCopyable<CAN> {
+
+public:
+    /** Creates an CAN interface connected to specific pins.
+     *
+     *  @param rd read from transmitter
+     *  @param td transmit to transmitter
+     *
+     * Example:
+     * @code
+     * #include "mbed.h"
+     *
+     * Ticker ticker;
+     * DigitalOut led1(LED1);
+     * DigitalOut led2(LED2);
+     * CAN can1(p9, p10);
+     * CAN can2(p30, p29);
+     *
+     * char counter = 0;
+     *
+     * void send() {
+     *     if(can1.write(CANMessage(1337, &counter, 1))) {
+     *         printf("Message sent: %d\n", counter);
+     *         counter++;
+     *     }
+     *     led1 = !led1;
+     * }
+     *
+     * int main() {
+     *     ticker.attach(&send, 1);
+     *    CANMessage msg;
+     *     while(1) {
+     *         if(can2.read(msg)) {
+     *             printf("Message received: %d\n\n", msg.data[0]);
+     *             led2 = !led2;
+     *         }
+     *         wait(0.2);
+     *     }
+     * }
+     * @endcode
+     */
+    CAN(PinName rd, PinName td);
+
+    /** Initialize CAN interface and set the frequency
+      *
+      * @param rd the rd pin
+      * @param td the td pin
+      * @param hz the bus frequency in hertz
+      */
+    CAN(PinName rd, PinName td, int hz);
+
+    virtual ~CAN();
+
+    /** Set the frequency of the CAN interface
+     *
+     *  @param hz The bus frequency in hertz
+     *
+     *  @returns
+     *    1 if successful,
+     *    0 otherwise
+     */
+    int frequency(int hz);
+
+    /** Write a CANMessage to the bus.
+     *
+     *  @param msg The CANMessage to write.
+     *
+     *  @returns
+     *    0 if write failed,
+     *    1 if write was successful
+     */
+    int write(CANMessage msg);
+
+    /** Read a CANMessage from the bus.
+     *
+     *  @param msg A CANMessage to read to.
+     *  @param handle message filter handle (0 for any message)
+     *
+     *  @returns
+     *    0 if no message arrived,
+     *    1 if message arrived
+     */
+    int read(CANMessage &msg, int handle = 0);
+
+    /** Reset CAN interface.
+     *
+     * To use after error overflow.
+     */
+    void reset();
+
+    /** Puts or removes the CAN interface into silent monitoring mode
+     *
+     *  @param silent boolean indicating whether to go into silent mode or not
+     */
+    void monitor(bool silent);
+
+    enum Mode {
+        Reset = 0,
+        Normal,
+        Silent,
+        LocalTest,
+        GlobalTest,
+        SilentTest
+    };
+
+    /** Change CAN operation to the specified mode
+     *
+     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+     *
+     *  @returns
+     *    0 if mode change failed or unsupported,
+     *    1 if mode change was successful
+     */
+    int mode(Mode mode);
+
+    /** Filter out incomming messages
+     *
+     *  @param id the id to filter on
+     *  @param mask the mask applied to the id
+     *  @param format format to filter on (Default CANAny)
+     *  @param handle message filter handle (Optional)
+     *
+     *  @returns
+     *    0 if filter change failed or unsupported,
+     *    new filter handle if successful
+     */
+    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+    /**  Detects read errors - Used to detect read overflow errors.
+     *
+     *  @returns number of read errors
+     */
+    unsigned char rderror();
+
+    /** Detects write errors - Used to detect write overflow errors.
+     *
+     *  @returns number of write errors
+     */
+    unsigned char tderror();
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq,
+        EwIrq,
+        DoIrq,
+        WuIrq,
+        EpIrq,
+        AlIrq,
+        BeIrq,
+        IdIrq,
+
+        IrqCnt
+    };
+
+    /** Attach a function to call whenever a CAN frame received interrupt is
+     *  generated.
+     *  
+     *  This function locks the deep sleep while a callback is attached
+     *  
+     *  @param func A pointer to a void function, or 0 to set as none
+     *  @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+     */
+    void attach(Callback<void()> func, IrqType type=RxIrq);
+
+   /** Attach a member function to call whenever a CAN frame received interrupt
+    *  is generated.
+    *
+    *  @param obj pointer to the object to call the member function on
+    *  @param method pointer to the member function to be called
+    *  @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+    *  @deprecated
+    *      The attach function does not support cv-qualifiers. Replaced by
+    *      attach(callback(obj, method), type).
+    */
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The attach function does not support cv-qualifiers. Replaced by "
+        "attach(callback(obj, method), type).")
+    void attach(T* obj, void (T::*method)(), IrqType type=RxIrq) {
+        // Underlying call thread safe
+        attach(callback(obj, method), type);
+    }
+
+   /** Attach a member function to call whenever a CAN frame received interrupt
+    *  is generated.
+    *
+    *  @param obj pointer to the object to call the member function on
+    *  @param method pointer to the member function to be called
+    *  @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+    *  @deprecated
+    *      The attach function does not support cv-qualifiers. Replaced by
+    *      attach(callback(obj, method), type).
+    */
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The attach function does not support cv-qualifiers. Replaced by "
+        "attach(callback(obj, method), type).")
+    void attach(T* obj, void (*method)(T*), IrqType type=RxIrq) {
+        // Underlying call thread safe
+        attach(callback(obj, method), type);
+    }
+
+    static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    can_t               _can;
+    Callback<void()>    _irq[IrqCnt];
+    PlatformMutex       _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif    // MBED_CAN_H
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalIn.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalIn.h
new file mode 100755
index 0000000..d35476c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalIn.h
@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform/platform.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input, used for reading the state of a pin
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(enable) {
+ *             led = !led;
+ *         }
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class DigitalIn {
+
+public:
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     */
+    DigitalIn(PinName pin) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     *  @param mode the initial mode of the pin
+     */
+    DigitalIn(PinName pin, PinMode mode) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_in_ex(&gpio, pin, mode);
+    }
+    /** Read the input, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    An integer representing the state of the input pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        // Thread safe / atomic HAL call
+        return gpio_read(&gpio);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param pull PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        core_util_critical_section_enter();
+        gpio_mode(&gpio, pull);
+        core_util_critical_section_exit();
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        // Thread safe / atomic HAL call
+        return gpio_is_connected(&gpio);
+    }
+
+    /** An operator shorthand for read()
+     * \sa DigitalIn::read()
+     */
+    operator int() {
+        // Underlying read is thread safe
+        return read();
+    }
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalInOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalInOut.h
new file mode 100755
index 0000000..cc524ff
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalInOut.h
@@ -0,0 +1,147 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform/platform.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class DigitalInOut {
+
+public:
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     */
+    DigitalInOut(PinName pin) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     *  @param direction the initial direction of the pin
+     *  @param mode the initial mode of the pin
+     *  @param value the initial value of the pin if is an output
+     */
+    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_inout(&gpio, pin, direction, mode, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        // Thread safe / atomic HAL call
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin if it is an output,
+     *    or read the input if set as an input
+     */
+    int read() {
+        // Thread safe / atomic HAL call
+        return gpio_read(&gpio);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        core_util_critical_section_enter();
+        gpio_dir(&gpio, PIN_OUTPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        core_util_critical_section_enter();
+        gpio_dir(&gpio, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param pull PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        core_util_critical_section_enter();
+        gpio_mode(&gpio, pull);
+        core_util_critical_section_exit();
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        // Thread safe / atomic HAL call
+        return gpio_is_connected(&gpio);
+    }
+
+    /** A shorthand for write()
+     * \sa DigitalInOut::write()
+     */
+    DigitalInOut& operator= (int value) {
+        // Underlying write is thread safe
+        write(value);
+        return *this;
+    }
+
+    /** A shorthand for write()
+     * \sa DigitalInOut::write()
+     */
+    DigitalInOut& operator= (DigitalInOut& rhs) {
+        core_util_critical_section_enter();
+        write(rhs.read());
+        core_util_critical_section_exit();
+        return *this;
+    }
+
+    /** A shorthand for read()
+     * \sa DigitalInOut::read()
+     */
+    operator int() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalOut.h
new file mode 100755
index 0000000..06c5735
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/DigitalOut.h
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform/platform.h"
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital output, used for setting the state of a pin
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class DigitalOut {
+
+public:
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     */
+    DigitalOut(PinName pin) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_out(&gpio, pin);
+    }
+
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     *  @param value the initial pin value
+     */
+    DigitalOut(PinName pin, int value) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_out_ex(&gpio, pin, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        // Thread safe / atomic HAL call
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        // Thread safe / atomic HAL call
+        return gpio_read(&gpio);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        // Thread safe / atomic HAL call
+        return gpio_is_connected(&gpio);
+    }
+
+    /** A shorthand for write()
+     * \sa DigitalOut::write()
+     */
+    DigitalOut& operator= (int value) {
+        // Underlying write is thread safe
+        write(value);
+        return *this;
+    }
+
+    /** A shorthand for write()
+     * \sa DigitalOut::write()
+     */
+    DigitalOut& operator= (DigitalOut& rhs) {
+        core_util_critical_section_enter();
+        write(rhs.read());
+        core_util_critical_section_exit();
+        return *this;
+    }
+
+    /** A shorthand for read()
+     * \sa DigitalOut::read()
+     */
+    operator int() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ethernet.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ethernet.cpp
new file mode 100755
index 0000000..c275f4a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ethernet.cpp
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "hal/ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+    ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+    ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+    return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+    return ethernet_send();
+}
+
+int Ethernet::receive() {
+    return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+    return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+    return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+    return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+    int speed = -1;
+    int duplex = 0;
+
+    switch(mode) {
+        case AutoNegotiate : speed = -1; duplex = 0; break;
+        case HalfDuplex10  : speed = 0;  duplex = 0; break;
+        case FullDuplex10  : speed = 0;  duplex = 1; break;
+        case HalfDuplex100 : speed = 1;  duplex = 0; break;
+        case FullDuplex100 : speed = 1;  duplex = 1; break;
+    }
+
+    ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ethernet.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ethernet.h
new file mode 100755
index 0000000..ae4e999
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ethernet.h
@@ -0,0 +1,176 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform/platform.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_ETHERNET) || defined(DOXYGEN_ONLY)
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ *     char buf[0x600];
+ *
+ *     while(1) {
+ *         int size = eth.receive();
+ *         if(size > 0) {
+ *             eth.read(buf, size);
+ *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ *         }
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Ethernet : private NonCopyable<Ethernet> {
+
+public:
+
+    /** Initialise the ethernet interface.
+     */
+    Ethernet();
+
+    /** Powers the hardware down.
+     */
+    virtual ~Ethernet();
+
+    enum Mode {
+        AutoNegotiate,
+        HalfDuplex10,
+        FullDuplex10,
+        HalfDuplex100,
+        FullDuplex100
+    };
+
+    /** Writes into an outgoing ethernet packet.
+     *
+     *  It will append size bytes of data to the previously written bytes.
+     *
+     *  @param data An array to write.
+     *  @param size The size of data.
+     *
+     *  @returns
+     *   The number of written bytes.
+     */
+    int write(const char *data, int size);
+
+    /** Send an outgoing ethernet packet.
+     *
+     *  After filling in the data in an ethernet packet it must be send.
+     *  Send will provide a new packet to write to.
+     *
+     *  @returns
+     *    0 if the sending was failed,
+     *    or the size of the packet successfully sent.
+     */
+    int send();
+
+    /** Recevies an arrived ethernet packet.
+     *
+     *  Receiving an ethernet packet will drop the last received ethernet packet
+     *  and make a new ethernet packet ready to read.
+     *  If no ethernet packet is arrived it will return 0.
+     *
+     *  @returns
+     *    0 if no ethernet packet is arrived,
+     *    or the size of the arrived packet.
+     */
+    int receive();
+
+    /** Read from an recevied ethernet packet.
+     *
+     *  After receive returned a number bigger than 0 it is
+     *  possible to read bytes from this packet.
+     *
+     *  @param data      Pointer to data packet
+     *  @param size      Size of data to be read.
+     *  @returns         The number of byte read.
+     *
+     *  @note It is possible to use read multiple times.
+     *  Each time read will start reading after the last read byte before.
+     *
+     */
+    int read(char *data, int size);
+
+    /** Gives the ethernet address of the mbed.
+     *
+     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+     */
+    void address(char *mac);
+
+    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+     *
+     *  @returns
+     *   0 if no ethernet link is pressent,
+     *   1 if an ethernet link is pressent.
+     *
+     * Example:
+     * @code
+     * // Using the Ethernet link function
+     * #include "mbed.h"
+     *
+     * Ethernet eth;
+     *
+     * int main() {
+     *     wait(1); // Needed after startup.
+     *     if (eth.link()) {
+     *          printf("online\n");
+     *     } else {
+     *          printf("offline\n");
+     *     }
+     * }
+     * @endcode
+     */
+    int link();
+
+    /** Sets the speed and duplex parameters of an ethernet link
+     *
+     * - AutoNegotiate      Auto negotiate speed and duplex
+     * - HalfDuplex10       10 Mbit, half duplex
+     * - FullDuplex10       10 Mbit, full duplex
+     * - HalfDuplex100      100 Mbit, half duplex
+     * - FullDuplex100      100 Mbit, full duplex
+     *
+     *  @param mode the speed and duplex mode to set the link to:
+     */
+    void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/FlashIAP.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/FlashIAP.cpp
new file mode 100755
index 0000000..9677e38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/FlashIAP.cpp
@@ -0,0 +1,168 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <string.h>
+#include "FlashIAP.h"
+#include "mbed_assert.h"
+
+
+#ifdef DEVICE_FLASH
+
+namespace mbed {
+
+SingletonPtr<PlatformMutex> FlashIAP::_mutex;
+
+static inline bool is_aligned(uint32_t number, uint32_t alignment)
+{
+    if ((number % alignment) != 0) {
+        return false;
+    } else {
+        return true;
+    }
+}
+
+FlashIAP::FlashIAP()
+{
+
+}
+
+FlashIAP::~FlashIAP()
+{
+
+}
+
+int FlashIAP::init()
+{
+    int ret = 0;
+    _mutex->lock();
+    if (flash_init(&_flash)) {
+        ret = -1;
+    }
+    _mutex->unlock();
+    return ret;
+}
+
+int FlashIAP::deinit()
+{
+    int ret = 0;
+    _mutex->lock();
+    if (flash_free(&_flash)) {
+        ret = -1;
+    }
+    _mutex->unlock();
+    return ret;
+}
+
+
+int FlashIAP::read(void *buffer, uint32_t addr, uint32_t size)
+{
+    int32_t ret = -1;
+    _mutex->lock();
+    ret = flash_read(&_flash, addr, (uint8_t *) buffer, size);
+    _mutex->unlock();
+    return ret;
+}
+
+int FlashIAP::program(const void *buffer, uint32_t addr, uint32_t size)
+{
+    uint32_t page_size = get_page_size();
+    uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
+    // addr and size should be aligned to page size, and multiple of page size
+    // page program should not cross sector boundaries
+    if (!is_aligned(addr, page_size) ||
+        !is_aligned(size, page_size) ||
+        (size < page_size) ||
+        (((addr % current_sector_size) + size) > current_sector_size)) {
+        return -1;
+    }
+
+    int ret = 0;
+    _mutex->lock();
+    if (flash_program_page(&_flash, addr, (const uint8_t *)buffer, size)) {
+        ret = -1;
+    }
+    _mutex->unlock();
+    return ret;
+}
+
+bool FlashIAP::is_aligned_to_sector(uint32_t addr, uint32_t size)
+{
+    uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
+    if (!is_aligned(size, current_sector_size) ||
+        !is_aligned(addr, current_sector_size)) {
+        return false;
+    } else {
+        return true;
+    }
+}
+
+int FlashIAP::erase(uint32_t addr, uint32_t size)
+{
+    uint32_t current_sector_size = 0UL;
+
+    if (!is_aligned_to_sector(addr, size)) {
+        return -1;
+    }
+
+    int32_t ret = 0;
+    _mutex->lock();
+    while (size) {
+        ret = flash_erase_sector(&_flash, addr);
+        if (ret != 0) {
+            ret = -1;
+            break;
+        }
+        current_sector_size = flash_get_sector_size(&_flash, addr);
+        if (!is_aligned_to_sector(addr, size)) {
+            ret = -1;
+            break;
+        }
+        size -= current_sector_size;
+        addr += current_sector_size;
+    }
+    _mutex->unlock();
+    return ret;
+}
+
+uint32_t FlashIAP::get_page_size() const
+{
+    return flash_get_page_size(&_flash);
+}
+
+uint32_t FlashIAP::get_sector_size(uint32_t addr) const
+{
+    return flash_get_sector_size(&_flash, addr);
+}
+
+uint32_t FlashIAP::get_flash_start() const
+{
+    return flash_get_start_address(&_flash);
+}
+
+uint32_t FlashIAP::get_flash_size() const
+{
+    return flash_get_size(&_flash);
+}
+
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/FlashIAP.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/FlashIAP.h
new file mode 100755
index 0000000..a6acc1b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/FlashIAP.h
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FLASHIAP_H
+#define MBED_FLASHIAP_H
+
+#if defined (DEVICE_FLASH) || defined(DOXYGEN_ONLY)
+
+#include "flash_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+
+/** \addtogroup drivers */
+
+/** Flash IAP driver. It invokes flash HAL functions.
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class FlashIAP : private NonCopyable<FlashIAP> {
+public:
+    FlashIAP();
+    ~FlashIAP();
+
+    /** Initialize a flash IAP device
+     *
+     *  Should be called once per lifetime of the object.
+     *  @return 0 on success or a negative error code on failure
+     */
+    int init();
+
+    /** Deinitialize a flash IAP device
+     *
+     *  @return 0 on success or a negative error code on failure
+     */
+    int deinit();
+
+    /** Read data from a flash device. 
+     *
+     *  This method invokes memcpy - reads number of bytes from the address
+     *
+     *  @param buffer Buffer to write to
+     *  @param addr   Flash address to begin reading from
+     *  @param size   Size to read in bytes
+     *  @return       0 on success, negative error code on failure
+     */
+    int read(void *buffer, uint32_t addr, uint32_t size);
+
+    /** Program data to pages
+     *
+     *  The sectors must have been erased prior to being programmed
+     *
+     *  @param buffer Buffer of data to be written
+     *  @param addr   Address of a page to begin writing to, must be a multiple of program and sector sizes
+     *  @param size   Size to write in bytes, must be a multiple of program and sector sizes
+     *  @return       0 on success, negative error code on failure
+     */
+    int program(const void *buffer, uint32_t addr, uint32_t size);
+
+    /** Erase sectors
+     *
+     *  The state of an erased sector is undefined until it has been programmed
+     *
+     *  @param addr Address of a sector to begin erasing, must be a multiple of the sector size
+     *  @param size Size to erase in bytes, must be a multiple of the sector size
+     *  @return     0 on success, negative error code on failure
+     */
+    int erase(uint32_t addr, uint32_t size);
+
+    /** Get the sector size at the defined address
+     *
+     *  Sector size might differ at address ranges. 
+     *  An example <0-0x1000, sector size=1024; 0x10000-0x20000, size=2048>
+     *
+     *  @param addr Address of or inside the sector to query
+     *  @return Size of a sector in bytes or MBED_FLASH_INVALID_SIZE if not mapped
+     */
+    uint32_t get_sector_size(uint32_t addr) const;
+
+    /** Get the flash start address 
+     *
+     *  @return Flash start address 
+     */
+    uint32_t get_flash_start() const;
+
+    /** Get the flash size
+     *
+     *  @return Flash size 
+     */
+    uint32_t get_flash_size() const;
+
+    /** Get the program page size
+     *
+     *  The page size defines the writable page size
+     *  @return Size of a program page in bytes
+     */
+    uint32_t get_page_size() const;
+
+private:
+
+    /* Check if address and size are aligned to a sector
+     *
+     *  @param addr Address of block to check for alignment
+     *  @param size Size of block to check for alignment
+     *  @return true if the block is sector aligned, false otherwise
+     */
+    bool is_aligned_to_sector(uint32_t addr, uint32_t size);
+
+    flash_t _flash;
+    static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} /* namespace mbed */
+
+#endif  /* DEVICE_FLASH */
+
+#endif  /* MBED_FLASHIAP_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2C.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2C.cpp
new file mode 100755
index 0000000..31d8532
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2C.cpp
@@ -0,0 +1,172 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/I2C.h"
+
+#if DEVICE_I2C
+
+#if DEVICE_I2C_ASYNCH
+#include "platform/mbed_sleep.h"
+#endif
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+SingletonPtr<PlatformMutex> I2C::_mutex;
+
+I2C::I2C(PinName sda, PinName scl) :
+#if DEVICE_I2C_ASYNCH
+                                     _irq(this), _usage(DMA_USAGE_NEVER),
+#endif
+                                      _i2c(), _hz(100000) {
+    // No lock needed in the constructor
+
+    // The init function also set the frequency to 100000
+    i2c_init(&_i2c, sda, scl);
+
+    // Used to avoid unnecessary frequency updates
+    _owner = this;
+}
+
+void I2C::frequency(int hz) {
+    lock();
+    _hz = hz;
+
+    // We want to update the frequency even if we are already the bus owners
+    i2c_frequency(&_i2c, _hz);
+
+    // Updating the frequency of the bus we become the owners of it
+    _owner = this;
+    unlock();
+}
+
+void I2C::aquire() {
+    lock();
+    if (_owner != this) {
+        i2c_frequency(&_i2c, _hz);
+        _owner = this;
+    }
+    unlock();
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char* data, int length, bool repeated) {
+    lock();
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int written = i2c_write(&_i2c, address, data, length, stop);
+
+    unlock();
+    return length != written;
+}
+
+int I2C::write(int data) {
+    lock();
+    int ret = i2c_byte_write(&_i2c, data);
+    unlock();
+    return ret;
+}
+
+// read - Master Reciever Mode
+int I2C::read(int address, char* data, int length, bool repeated) {
+    lock();
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int read = i2c_read(&_i2c, address, data, length, stop);
+
+    unlock();
+    return length != read;
+}
+
+int I2C::read(int ack) {
+    lock();
+    int ret;
+    if (ack) {
+        ret = i2c_byte_read(&_i2c, 0);
+    } else {
+        ret = i2c_byte_read(&_i2c, 1);
+    }
+    unlock();
+    return ret;
+}
+
+void I2C::start(void) {
+    lock();
+    i2c_start(&_i2c);
+    unlock();
+}
+
+void I2C::stop(void) {
+    lock();
+    i2c_stop(&_i2c);
+    unlock();
+}
+
+void I2C::lock() {
+    _mutex->lock();
+}
+
+void I2C::unlock() {
+    _mutex->unlock();
+}
+
+#if DEVICE_I2C_ASYNCH
+
+int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event, bool repeated)
+{
+    lock();
+    if (i2c_active(&_i2c)) {
+        unlock();
+        return -1; // transaction ongoing
+    }
+    sleep_manager_lock_deep_sleep();
+    aquire();
+
+    _callback = callback;
+    int stop = (repeated) ? 0 : 1;
+    _irq.callback(&I2C::irq_handler_asynch);
+    i2c_transfer_asynch(&_i2c, (void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length, address, stop, _irq.entry(), event, _usage);
+    unlock();
+    return 0;
+}
+
+void I2C::abort_transfer(void)
+{
+    lock();
+    i2c_abort_asynch(&_i2c);
+    sleep_manager_unlock_deep_sleep();
+    unlock();
+}
+
+void I2C::irq_handler_asynch(void)
+{
+    int event = i2c_irq_handler_asynch(&_i2c);
+    if (_callback && event) {
+        _callback.call(event);
+    }
+    if (event) {
+        sleep_manager_unlock_deep_sleep();
+    }
+
+}
+
+
+#endif
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2C.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2C.h
new file mode 100755
index 0000000..b4fbc2f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2C.h
@@ -0,0 +1,199 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_I2C) || defined(DOXYGEN_ONLY)
+
+#include "hal/i2c_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "platform/CThunk.h"
+#include "hal/dma_api.h"
+#include "platform/FunctionPointer.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ *     int address = 0x62;
+ *     char data[2];
+ *     i2c.read(address, data, 2);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class I2C : private NonCopyable<I2C> {
+
+public:
+    enum RxStatus {
+        NoData,
+        MasterGeneralCall,
+        MasterWrite,
+        MasterRead
+    };
+
+    enum Acknowledge {
+        NoACK = 0,
+        ACK   = 1
+    };
+
+    /** Create an I2C Master interface, connected to the specified pins
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2C(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Read from an I2C slave
+     *
+     * Performs a complete read transaction. The bottom bit of
+     * the address is forced to 1 to indicate a read.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 1 ]
+     *  @param data Pointer to the byte-array to read data in to
+     *  @param length Number of bytes to read
+     *  @param repeated Repeated start, true - don't send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int read(int address, char *data, int length, bool repeated = false);
+
+    /** Read a single byte from the I2C bus
+     *
+     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(int ack);
+
+    /** Write to an I2C slave
+     *
+     * Performs a complete write transaction. The bottom bit of
+     * the address is forced to 0 to indicate a write.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 0 ]
+     *  @param data Pointer to the byte-array data to send
+     *  @param length Number of bytes to send
+     *  @param repeated Repeated start, true - do not send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int write(int address, const char *data, int length, bool repeated = false);
+
+    /** Write single byte out on the I2C bus
+     *
+     *  @param data data to write out on bus
+     *
+     *  @returns
+     *    '0' - NAK was received
+     *    '1' - ACK was received,
+     *    '2' - timeout
+     */
+    int write(int data);
+
+    /** Creates a start condition on the I2C bus
+     */
+
+    void start(void);
+
+    /** Creates a stop condition on the I2C bus
+     */
+    void stop(void);
+
+    /** Acquire exclusive access to this I2C bus
+     */
+    virtual void lock(void);
+
+    /** Release exclusive access to this I2C bus
+     */
+    virtual void unlock(void);
+
+    virtual ~I2C() {
+        // Do nothing
+    }
+
+#if DEVICE_I2C_ASYNCH
+
+    /** Start non-blocking I2C transfer.
+     *
+     * This function locks the deep sleep until any event has occured
+     * 
+     * @param address   8/10 bit I2c slave address
+     * @param tx_buffer The TX buffer with data to be transfered
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data
+     * @param rx_length The length of RX buffer in bytes
+     * @param event     The logical OR of events to modify
+     * @param callback  The event callback function
+     * @param repeated Repeated start, true - do not send stop at end
+     * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
+     */
+    int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
+
+    /** Abort the on-going I2C transfer
+     */
+    void abort_transfer();
+protected:
+    void irq_handler_asynch(void);
+    event_callback_t _callback;
+    CThunk<I2C> _irq;
+    DMAUsage _usage;
+#endif
+
+protected:
+    void aquire();
+
+    i2c_t _i2c;
+    static I2C  *_owner;
+    int         _hz;
+    static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2CSlave.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2CSlave.cpp
new file mode 100755
index 0000000..f168c2a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2CSlave.cpp
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
+    i2c_init(&_i2c, sda, scl);
+    i2c_frequency(&_i2c, 100000);
+    i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz) {
+    i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address) {
+    int addr = (address & 0xFF) | 1;
+    i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void) {
+    return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length) {
+    return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void) {
+    return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length) {
+    return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data) {
+    return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void) {
+    i2c_stop(&_i2c);
+}
+
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2CSlave.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2CSlave.h
new file mode 100755
index 0000000..047ef77
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/I2CSlave.h
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_I2CSLAVE) || defined(DOXYGEN_ONLY)
+
+#include "hal/i2c_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ *     char buf[10];
+ *     char msg[] = "Slave!";
+ *
+ *     slave.address(0xA0);
+ *     while (1) {
+ *         int i = slave.receive();
+ *         switch (i) {
+ *             case I2CSlave::ReadAddressed:
+ *                 slave.write(msg, strlen(msg) + 1); // Includes null char
+ *                 break;
+ *             case I2CSlave::WriteGeneral:
+ *                 slave.read(buf, 10);
+ *                 printf("Read G: %s\n", buf);
+ *                 break;
+ *             case I2CSlave::WriteAddressed:
+ *                 slave.read(buf, 10);
+ *                 printf("Read A: %s\n", buf);
+ *                 break;
+ *         }
+ *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class I2CSlave {
+
+public:
+    enum RxStatus {
+        NoData         = 0,
+        ReadAddressed  = 1,
+        WriteGeneral   = 2,
+        WriteAddressed = 3
+    };
+
+    /** Create an I2C Slave interface, connected to the specified pins.
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2CSlave(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Checks to see if this I2C Slave has been addressed.
+     *
+     *  @returns
+     *  A status indicating if the device has been addressed, and how
+     *  - NoData            - the slave has not been addressed
+     *  - ReadAddressed     - the master has requested a read from this slave
+     *  - WriteAddressed    - the master is writing to this slave
+     *  - WriteGeneral      - the master is writing to all slave
+     */
+    int receive(void);
+
+    /** Read from an I2C master.
+     *
+     *  @param data pointer to the byte array to read data in to
+     *  @param length maximum number of bytes to read
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int read(char *data, int length);
+
+    /** Read a single byte from an I2C master.
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(void);
+
+    /** Write to an I2C master.
+     *
+     *  @param data pointer to the byte array to be transmitted
+     *  @param length the number of bytes to transmite
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int write(const char *data, int length);
+
+    /** Write a single byte to an I2C master.
+     *
+     *  @param data the byte to write
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Sets the I2C slave address.
+     *
+     *  @param address The address to set for the slave (ignoring the least
+     *  signifcant bit). If set to 0, the slave will only respond to the
+     *  general call address.
+     */
+    void address(int address);
+
+    /** Reset the I2C slave back into the known ready receiving state.
+     */
+    void stop(void);
+
+protected:
+    i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptIn.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptIn.cpp
new file mode 100755
index 0000000..34f3210
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptIn.cpp
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+                                        gpio_irq(),
+                                        _rise(NULL),
+                                        _fall(NULL) {
+    // No lock needed in the constructor
+
+    gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+    gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::~InterruptIn() {
+    // No lock needed in the destructor
+    gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+    // Read only
+    return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+    core_util_critical_section_enter();
+    gpio_mode(&gpio, pull);
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::rise(Callback<void()> func) {
+    core_util_critical_section_enter();
+    if (func) {
+        _rise = func;
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    } else {
+        _rise = NULL;
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+    }
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::fall(Callback<void()> func) {
+    core_util_critical_section_enter();
+    if (func) {
+        _fall = func;
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    } else {
+        _fall = NULL;
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+    }
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+    InterruptIn *handler = (InterruptIn*)id;
+    switch (event) {
+        case IRQ_RISE: 
+            if (handler->_rise) {
+                handler->_rise();
+            }
+            break;
+        case IRQ_FALL: 
+            if (handler->_fall) {
+                handler->_fall(); 
+            }
+            break;
+        case IRQ_NONE: break;
+    }
+}
+
+void InterruptIn::enable_irq() {
+    core_util_critical_section_enter();
+    gpio_irq_enable(&gpio_irq);
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::disable_irq() {
+    core_util_critical_section_enter();
+    gpio_irq_disable(&gpio_irq);
+    core_util_critical_section_exit();
+}
+
+InterruptIn::operator int() {
+    // Underlying call is atomic
+    return read();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptIn.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptIn.h
new file mode 100755
index 0000000..0a122bd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptIn.h
@@ -0,0 +1,162 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/gpio_api.h"
+#include "hal/gpio_irq_api.h"
+#include "platform/Callback.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ *     printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ *     event.rise(&trigger);
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class InterruptIn : private NonCopyable<InterruptIn> {
+
+public:
+
+    /** Create an InterruptIn connected to the specified pin
+     *
+     *  @param pin InterruptIn pin to connect to
+     */
+    InterruptIn(PinName pin);
+    virtual ~InterruptIn();
+
+    /** Read the input, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    An integer representing the state of the input pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read();
+
+    /** An operator shorthand for read()
+     */
+    operator int();
+
+
+    /** Attach a function to call when a rising edge occurs on the input
+     *
+     *  @param func A pointer to a void function, or 0 to set as none
+     */
+    void rise(Callback<void()> func);
+
+    /** Attach a member function to call when a rising edge occurs on the input
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @deprecated
+     *      The rise function does not support cv-qualifiers. Replaced by
+     *      rise(callback(obj, method)).
+     */
+    template<typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The rise function does not support cv-qualifiers. Replaced by "
+        "rise(callback(obj, method)).")
+    void rise(T *obj, M method) {
+        core_util_critical_section_enter();
+        rise(callback(obj, method));
+        core_util_critical_section_exit();
+    }
+
+    /** Attach a function to call when a falling edge occurs on the input
+     *
+     *  @param func A pointer to a void function, or 0 to set as none
+     */
+    void fall(Callback<void()> func);
+
+    /** Attach a member function to call when a falling edge occurs on the input
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @deprecated
+     *      The rise function does not support cv-qualifiers. Replaced by
+     *      rise(callback(obj, method)).
+     */
+    template<typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The fall function does not support cv-qualifiers. Replaced by "
+        "fall(callback(obj, method)).")
+    void fall(T *obj, M method) {
+        core_util_critical_section_enter();
+        fall(callback(obj, method));
+        core_util_critical_section_exit();
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param pull PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Enable IRQ. This method depends on hw implementation, might enable one
+     *  port interrupts. For further information, check gpio_irq_enable().
+     */
+    void enable_irq();
+
+    /** Disable IRQ. This method depends on hw implementation, might disable one
+     *  port interrupts. For further information, check gpio_irq_disable().
+     */
+    void disable_irq();
+
+    static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+    gpio_t gpio;
+    gpio_irq_t gpio_irq;
+
+    Callback<void()> _rise;
+    Callback<void()> _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptManager.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptManager.cpp
new file mode 100755
index 0000000..ac8c83d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptManager.cpp
@@ -0,0 +1,137 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#if defined(NVIC_NUM_VECTORS)
+
+#include "drivers/InterruptManager.h"
+#include "platform/mbed_critical.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE    4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
+
+InterruptManager* InterruptManager::get() {
+
+    if (NULL == _instance) {
+        InterruptManager* temp = new InterruptManager();
+
+        // Atomically set _instance
+        core_util_critical_section_enter();
+        if (NULL == _instance) {
+            _instance = temp;
+        }
+        core_util_critical_section_exit();
+
+        // Another thread got there first so delete ours
+        if (temp != _instance) {
+            delete temp;
+        }
+
+    }
+    return _instance;
+}
+
+InterruptManager::InterruptManager() {
+    // No mutex needed in constructor
+    memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+    // Not a good idea to call this unless NO interrupt at all
+    // is under the control of the handler; otherwise, a system crash
+    // is very likely to occur
+    if (NULL != _instance) {
+        delete _instance;
+        _instance = (InterruptManager*)NULL;
+    }
+}
+
+InterruptManager::~InterruptManager() {
+    for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+        if (NULL != _chains[i])
+            delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+    lock();
+
+    int ret = false;
+    int irq_pos = get_irq_index(irq);
+    if (NULL == _chains[irq_pos]) {
+        _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+        _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+        ret = true;
+    }
+    unlock();
+    return ret;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+    lock();
+    int irq_pos = get_irq_index(irq);
+    bool change = must_replace_vector(irq);
+
+    pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+    if (change)
+        NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+    unlock();
+    return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+    int irq_pos = get_irq_index(irq);
+    bool ret = false;
+
+    lock();
+    if (_chains[irq_pos] != NULL) {
+        if (_chains[irq_pos]->remove(handler)) {
+            ret = true;
+        }
+    }
+    unlock();
+
+    return ret;
+}
+
+void InterruptManager::irq_helper() {
+    _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+    // Pure function - no lock needed
+    return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+    InterruptManager::get()->irq_helper();
+}
+
+void InterruptManager::lock() {
+    _mutex.lock();
+}
+
+void InterruptManager::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptManager.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptManager.h
new file mode 100755
index 0000000..8060738
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/InterruptManager.h
@@ -0,0 +1,169 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "platform/CallChain.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+#include <string.h>
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ *     led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ *     led2 = !led1;
+ * }
+ *
+ * int main() {
+ *     led1 = led2 = 0;
+ *     flipper.attach(&flip, 1.0);
+ *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class InterruptManager : private NonCopyable<InterruptManager> {
+public:
+    /** Get the instance of InterruptManager Class
+     *
+     *  @return the only instance of this class
+     */
+    static InterruptManager* get();
+
+    /** Destroy the current instance of the interrupt manager
+     */
+    static void destroy();
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(function, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(function, irq, true);
+    }
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(tptr, mptr, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(tptr, mptr, irq, true);
+    }
+
+    /** Remove a handler from an interrupt
+     *
+     *  @param handler the function object for the handler to remove
+     *  @param irq the interrupt number
+     *
+     *  @returns
+     *  true if the handler was found and removed, false otherwise
+     */
+    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+    InterruptManager();
+    ~InterruptManager();
+
+    void lock();
+    void unlock();
+
+    template<typename T>
+    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+        _mutex.lock();
+        int irq_pos = get_irq_index(irq);
+        bool change = must_replace_vector(irq);
+
+        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+        if (change)
+            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+        _mutex.unlock();
+        return pf;
+    }
+
+    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+    bool must_replace_vector(IRQn_Type irq);
+    int get_irq_index(IRQn_Type irq);
+    void irq_helper();
+    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+    static void static_irq_helper();
+
+    CallChain* _chains[NVIC_NUM_VECTORS];
+    static InterruptManager* _instance;
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTicker.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTicker.h
new file mode 100755
index 0000000..2df8ef3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTicker.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTICKER_H
+#define MBED_LOWPOWERTICKER_H
+
+#include "platform/platform.h"
+#include "drivers/Ticker.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_LOWPOWERTIMER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low Power Ticker
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTicker : public Ticker, private NonCopyable<LowPowerTicker> {
+
+public:
+    LowPowerTicker() : Ticker(get_lp_ticker_data()) {
+    }
+
+    virtual ~LowPowerTicker() {
+    }
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTimeout.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTimeout.h
new file mode 100755
index 0000000..6aaefe2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTimeout.h
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMEOUT_H
+#define MBED_LOWPOWERTIMEOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_LOWPOWERTIMER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+#include "drivers/LowPowerTicker.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low Power Timout
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTimeout : public LowPowerTicker, private NonCopyable<LowPowerTimeout> {
+
+private:
+    virtual void handler(void) {
+        _function.call();
+    }
+};
+
+}
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTimer.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTimer.h
new file mode 100755
index 0000000..e7e0037
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/LowPowerTimer.h
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMER_H
+#define MBED_LOWPOWERTIMER_H
+
+#include "platform/platform.h"
+#include "drivers/Timer.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_LOWPOWERTIMER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low power timer
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTimer : public Timer, private NonCopyable<LowPowerTimer> {
+
+public:
+    LowPowerTimer() : Timer(get_lp_ticker_data()) {
+    }
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortIn.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortIn.h
new file mode 100755
index 0000000..2796916
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortIn.h
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A multiple pin digital input
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ *  Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn     p(Port2, 0x0000003F);   // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ *     while(1) {
+ *         int pins = p.read();
+ *         if(pins) {
+ *             ind = 1;
+ *         } else {
+ *             ind = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PortIn {
+public:
+
+    /** Create an PortIn, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+        */
+    PortIn(PortName port, int mask = 0xFFFFFFFF) {
+        core_util_critical_section_enter();
+        port_init(&_port, port, mask, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        core_util_critical_section_enter();
+        port_mode(&_port, mode);
+        core_util_critical_section_exit();
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortInOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortInOut.h
new file mode 100755
index 0000000..4eb9ecb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortInOut.h
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTINOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class PortInOut {
+public:
+
+    /** Create an PortInOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+        core_util_critical_section_enter();
+        port_init(&_port, port, mask, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding port pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        core_util_critical_section_enter();
+        port_dir(&_port, PIN_OUTPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        core_util_critical_section_enter();
+        port_dir(&_port, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        core_util_critical_section_enter();
+        port_mode(&_port, mode);
+        core_util_critical_section_exit();
+    }
+
+    /** A shorthand for write()
+     * \sa PortInOut::write()
+     */
+    PortInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    /** A shorthand for write()
+     * \sa PortInOut::write()
+     */
+    PortInOut& operator= (PortInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     * \sa PortInOut::read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortOut.h
new file mode 100755
index 0000000..9b8a76b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PortOut.h
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+/** A multiple pin digital out
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ *     while(1) {
+ *         ledport = LED_MASK;
+ *         wait(1);
+ *         ledport = 0;
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PortOut {
+public:
+
+    /** Create an PortOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortOut(PortName port, int mask = 0xFFFFFFFF) {
+        core_util_critical_section_enter();
+        port_init(&_port, port, mask, PIN_OUTPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated PortOut pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** A shorthand for write()
+     * \sa PortOut::write()
+     */
+    PortOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    /** A shorthand for read()
+     * \sa PortOut::read()
+     */
+    PortOut& operator= (PortOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     * \sa PortOut::read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PwmOut.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PwmOut.h
new file mode 100755
index 0000000..c94b858
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/PwmOut.h
@@ -0,0 +1,212 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY)
+#include "hal/pwmout_api.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A pulse-width modulation digital output
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = led + 0.01;
+ *         wait(0.2);
+ *         if(led == 1.0) {
+ *             led = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PwmOut {
+
+public:
+
+    /** Create a PwmOut connected to the specified pin
+     *
+     *  @param pin PwmOut pin to connect to
+     */
+    PwmOut(PinName pin) : _deep_sleep_locked(false) {
+        core_util_critical_section_enter();
+        pwmout_init(&_pwm, pin);
+        core_util_critical_section_exit();
+    }
+
+    ~PwmOut() {
+        core_util_critical_section_enter();
+        unlock_deep_sleep();
+        core_util_critical_section_exit();
+    }
+
+    /** Set the ouput duty-cycle, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output duty-cycle,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        core_util_critical_section_enter();
+        lock_deep_sleep();
+        pwmout_write(&_pwm, value);
+        core_util_critical_section_exit();
+    }
+
+    /** Return the current output duty-cycle setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current duty-cycle being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *
+     *  @note
+     *  This value may not match exactly the value set by a previous write().
+     */
+    float read() {
+        core_util_critical_section_enter();
+        float val = pwmout_read(&_pwm);
+        core_util_critical_section_exit();
+        return val;
+    }
+
+    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+     *
+     *  @param seconds Change the period of a PWM signal in seconds (float) without modifying the duty cycle
+     *  @note
+     *   The resolution is currently in microseconds; periods smaller than this
+     *   will be set to zero.
+     */
+    void period(float seconds) {
+        core_util_critical_section_enter();
+        pwmout_period(&_pwm, seconds);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+     *  @param ms Change the period of a PWM signal in milli-seconds without modifying the duty cycle
+     */
+    void period_ms(int ms) {
+        core_util_critical_section_enter();
+        pwmout_period_ms(&_pwm, ms);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+     *  @param us Change the period of a PWM signal in micro-seconds without modifying the duty cycle
+     */
+    void period_us(int us) {
+        core_util_critical_section_enter();
+        pwmout_period_us(&_pwm, us);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+     *  @param seconds Change the pulse width of a PWM signal specified in seconds (float)
+     */
+    void pulsewidth(float seconds) {
+        core_util_critical_section_enter();
+        pwmout_pulsewidth(&_pwm, seconds);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+     *  @param ms Change the pulse width of a PWM signal specified in milli-seconds
+     */
+    void pulsewidth_ms(int ms) {
+        core_util_critical_section_enter();
+        pwmout_pulsewidth_ms(&_pwm, ms);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+     *  @param us Change the pulse width of a PWM signal specified in micro-seconds  
+     */
+    void pulsewidth_us(int us) {
+        core_util_critical_section_enter();
+        pwmout_pulsewidth_us(&_pwm, us);
+        core_util_critical_section_exit();
+    }
+
+    /** A operator shorthand for write()
+     *  \sa PwmOut::write()
+     */
+    PwmOut& operator= (float value) {
+        // Underlying call is thread safe
+        write(value);
+        return *this;
+    }
+
+    /** A operator shorthand for write()
+     * \sa PwmOut::write()
+     */    
+    PwmOut& operator= (PwmOut& rhs) {
+        // Underlying call is thread safe
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     * \sa PwmOut::read()
+     */
+    operator float() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+protected:
+    /** Lock deep sleep only if it is not yet locked */
+    void lock_deep_sleep() {
+        if (_deep_sleep_locked == false) {
+            sleep_manager_lock_deep_sleep();
+            _deep_sleep_locked = true;
+        }
+    }
+
+    /** Unlock deep sleep in case it is locked */
+    void unlock_deep_sleep() {
+        if (_deep_sleep_locked == true) {
+            sleep_manager_unlock_deep_sleep();
+            _deep_sleep_locked = false;
+        }
+    }
+
+    pwmout_t _pwm;
+    bool _deep_sleep_locked;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/RawSerial.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/RawSerial.cpp
new file mode 100755
index 0000000..6395868
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/RawSerial.cpp
@@ -0,0 +1,95 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/RawSerial.h"
+#include "platform/mbed_wait_api.h"
+#include <stdio.h>
+#include <cstdarg>
+
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT    120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx, int baud) : SerialBase(tx, rx, baud) {
+    // No lock needed in the constructor
+}
+
+int RawSerial::getc() {
+    lock();
+    int ret = _base_getc();
+    unlock();
+    return ret;
+}
+
+int RawSerial::putc(int c) {
+    lock();
+    int ret = _base_putc(c);
+    unlock();
+    return ret;
+}
+
+int RawSerial::puts(const char *str) {
+    lock();
+    while (*str)
+        putc(*str ++);
+    unlock();
+    return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...) {
+    lock();
+    std::va_list arg;
+    va_start(arg, format);
+    // ARMCC microlib does not properly handle a size of 0.
+    // As a workaround supply a dummy buffer with a size of 1.
+    char dummy_buf[1];
+    int len = vsnprintf(dummy_buf, sizeof(dummy_buf), format, arg);
+    if (len < STRING_STACK_LIMIT) {
+        char temp[STRING_STACK_LIMIT];
+        vsprintf(temp, format, arg);
+        puts(temp);
+    } else {
+        char *temp = new char[len + 1];
+        vsprintf(temp, format, arg);
+        puts(temp);
+        delete[] temp;
+    }
+    va_end(arg);
+    unlock();
+    return len;
+}
+
+/** Acquire exclusive access to this serial port
+ */
+void RawSerial::lock() {
+    // No lock used - external synchronization required
+}
+
+/** Release exclusive access to this serial port
+ */
+void RawSerial::unlock() {
+    // No lock used - external synchronization required
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/RawSerial.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/RawSerial.h
new file mode 100755
index 0000000..b39fac7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/RawSerial.h
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "drivers/SerialBase.h"
+#include "hal/serial_api.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.putc('A');
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class RawSerial: public SerialBase, private NonCopyable<RawSerial> {
+
+public:
+    /** Create a RawSerial port, connected to the specified transmit and receive pins, with the specified baud.
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *  @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    RawSerial(PinName tx, PinName rx, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+
+    /** Write a char to the serial port
+     *
+     * @param c The char to write
+     *
+     * @returns The written char or -1 if an error occured
+     */
+    int putc(int c);
+
+    /** Read a char from the serial port
+     *
+     * @returns The char read from the serial port
+     */
+    int getc();
+
+    /** Write a string to the serial port
+     *
+     * @param str The string to write
+     *
+     * @returns 0 if the write succeeds, EOF for error
+     */
+    int puts(const char *str);
+
+    int printf(const char *format, ...);
+
+protected:
+
+    /* Acquire exclusive access to this serial port
+     */
+    virtual void lock(void);
+
+    /* Release exclusive access to this serial port
+     */
+    virtual void unlock(void);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPI.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPI.cpp
new file mode 100755
index 0000000..884f3a1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPI.cpp
@@ -0,0 +1,258 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SPI.h"
+#include "platform/mbed_critical.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "platform/mbed_sleep.h"
+#endif
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
+CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
+#endif
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+        _spi(),
+#if DEVICE_SPI_ASYNCH
+        _irq(this),
+        _usage(DMA_USAGE_NEVER),
+#endif
+        _bits(8),
+        _mode(0),
+        _hz(1000000),
+        _write_fill(SPI_FILL_CHAR) {
+    // No lock needed in the constructor
+
+    spi_init(&_spi, mosi, miso, sclk, ssel);
+    _acquire();
+}
+
+void SPI::format(int bits, int mode) {
+    lock();
+    _bits = bits;
+    _mode = mode;
+    // If changing format while you are the owner than just
+    // update format, but if owner is changed than even frequency should be
+    // updated which is done by acquire.
+    if (_owner == this) {
+        spi_format(&_spi, _bits, _mode, 0);
+    } else {
+        _acquire();
+    }
+    unlock();
+}
+
+void SPI::frequency(int hz) {
+    lock();
+    _hz = hz;
+    // If changing format while you are the owner than just
+    // update frequency, but if owner is changed than even frequency should be
+    // updated which is done by acquire.
+    if (_owner == this) {
+        spi_frequency(&_spi, _hz);
+    } else {
+        _acquire();
+    }
+    unlock();
+}
+
+SPI* SPI::_owner = NULL;
+SingletonPtr<PlatformMutex> SPI::_mutex;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+    lock();
+     if (_owner != this) {
+        spi_format(&_spi, _bits, _mode, 0);
+        spi_frequency(&_spi, _hz);
+        _owner = this;
+    }
+    unlock();
+}
+
+// Note: Private function with no locking
+void SPI::_acquire() {
+     if (_owner != this) {
+        spi_format(&_spi, _bits, _mode, 0);
+        spi_frequency(&_spi, _hz);
+        _owner = this;
+    }
+}
+
+int SPI::write(int value) {
+    lock();
+    _acquire();
+    int ret = spi_master_write(&_spi, value);
+    unlock();
+    return ret;
+}
+
+int SPI::write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+    lock();
+    _acquire();
+    int ret = spi_master_block_write(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, _write_fill);
+    unlock();
+    return ret;
+}
+
+// NEW FUNCTION F4HDK !!!
+ int SPI::transfer_2(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length) {
+    //lock();
+    //aquire();
+    //int ret = spi_master_write(&_spi, value);
+	int ret = spi_master_transfer_2 (&_spi, tx_buffer, tx_length, rx_buffer, rx_length);
+    //unlock();
+    return ret;
+}
+
+void SPI::lock() {
+    _mutex->lock();
+}
+
+void SPI::unlock() {
+    _mutex->unlock();
+}
+
+void SPI::set_default_write_value(char data) {
+    lock();
+    _write_fill = data;
+    unlock();
+}
+
+#if DEVICE_SPI_ASYNCH
+
+int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+    if (spi_active(&_spi)) {
+        return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+    }
+    start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+    return 0;
+}
+
+void SPI::abort_transfer()
+{
+    spi_abort_asynch(&_spi);
+    sleep_manager_unlock_deep_sleep();
+#if TRANSACTION_QUEUE_SIZE_SPI
+    dequeue_transaction();
+#endif
+}
+
+
+void SPI::clear_transfer_buffer()
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+    _transaction_buffer.reset();
+#endif
+}
+
+void SPI::abort_all_transfers()
+{
+    clear_transfer_buffer();
+    abort_transfer();
+}
+
+int SPI::set_dma_usage(DMAUsage usage)
+{
+    if (spi_active(&_spi)) {
+        return -1;
+    }
+    _usage = usage;
+    return  0;
+}
+
+int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+    transaction_t t;
+
+    t.tx_buffer = const_cast<void *>(tx_buffer);
+    t.tx_length = tx_length;
+    t.rx_buffer = rx_buffer;
+    t.rx_length = rx_length;
+    t.event = event;
+    t.callback = callback;
+    t.width = bit_width;
+    Transaction<SPI> transaction(this, t);
+    if (_transaction_buffer.full()) {
+        return -1; // the buffer is full
+    } else {
+        core_util_critical_section_enter();
+        _transaction_buffer.push(transaction);
+        if (!spi_active(&_spi)) {
+            dequeue_transaction();
+        }
+        core_util_critical_section_exit();
+        return 0;
+    }
+#else
+    return -1;
+#endif
+}
+
+void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+    sleep_manager_lock_deep_sleep();
+    _acquire();
+    _callback = callback;
+    _irq.callback(&SPI::irq_handler_asynch);
+    spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
+}
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+void SPI::start_transaction(transaction_t *data)
+{
+    start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
+}
+
+void SPI::dequeue_transaction()
+{
+    Transaction<SPI> t;
+    if (_transaction_buffer.pop(t)) {
+        SPI* obj = t.get_object();
+        transaction_t* data = t.get_transaction();
+        obj->start_transaction(data);
+    }
+}
+
+#endif
+
+void SPI::irq_handler_asynch(void)
+{
+    int event = spi_irq_handler_asynch(&_spi);
+    if (_callback && (event & SPI_EVENT_ALL)) {
+        sleep_manager_unlock_deep_sleep();
+        _callback.call(event & SPI_EVENT_ALL);
+    }
+#if TRANSACTION_QUEUE_SIZE_SPI
+    if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
+        // SPI peripheral is free (event happend), dequeue transaction
+        dequeue_transaction();
+    }
+#endif
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPI.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPI.h
new file mode 100755
index 0000000..df2f1ca
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPI.h
@@ -0,0 +1,301 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SPI) || defined(DOXYGEN_ONLY)
+
+#include "platform/PlatformMutex.h"
+#include "hal/spi_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/NonCopyable.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "platform/CThunk.h"
+#include "hal/dma_api.h"
+#include "platform/CircularBuffer.h"
+#include "platform/FunctionPointer.h"
+#include "platform/Transaction.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using DigitalOut pins
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * // hardware ssel (where applicable)
+ * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * // software ssel
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ * DigitalOut cs(p8); // ssel
+ *
+ * int main() {
+ *     // hardware ssel (where applicable)
+ *     //int response = device.write(0xFF);
+ *
+ *     device.lock();
+ *     // software ssel
+ *     cs = 0;
+ *     int response = device.write(0xFF);
+ *     cs = 1;
+ *     device.unlock();
+ *
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class SPI : private NonCopyable<SPI> {
+
+public:
+
+    /** Create a SPI master connected to the specified pins
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     */
+    SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Write to the SPI Slave and return the response
+     *
+     *  @param value Data to be sent to the SPI slave
+     *
+     *  @returns
+     *    Response from the SPI slave
+     */
+    virtual int write(int value);
+
+    /** Write to the SPI Slave and obtain the response
+     *
+     *  The total number of bytes sent and recieved will be the maximum of
+     *  tx_length and rx_length. The bytes written will be padded with the
+     *  value 0xff.
+     *
+     *  @param tx_buffer Pointer to the byte-array of data to write to the device
+     *  @param tx_length Number of bytes to write, may be zero
+     *  @param rx_buffer Pointer to the byte-array of data to read from the device
+     *  @param rx_length Number of bytes to read, may be zero
+     *  @returns
+     *      The number of bytes written and read from the device. This is
+     *      maximum of tx_length and rx_length.
+     */
+    virtual int write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length);
+
+	// NEW FUNCTION F4HDK !!!
+	virtual int transfer_2(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length);
+	
+    /** Acquire exclusive access to this SPI bus
+     */
+    virtual void lock(void);
+
+    /** Release exclusive access to this SPI bus
+     */
+    virtual void unlock(void);
+
+    /** Set default write data
+      * SPI requires the master to send some data during a read operation.
+      * Different devices may require different default byte values.
+      * For example: A SD Card requires default bytes to be 0xFF.
+      *
+      * @param data    Default character to be transmitted while read operation
+      */
+    void set_default_write_value(char data);
+
+#if DEVICE_SPI_ASYNCH
+
+    /** Start non-blocking SPI transfer using 8bit buffers.
+     *
+     * This function locks the deep sleep until any event has occured
+     * 
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify. Look at spi hal header file for SPI events.
+     * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
+     */
+    template<typename Type>
+    int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
+        if (spi_active(&_spi)) {
+            return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+        }
+        start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+        return 0;
+    }
+
+    /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
+     */
+    void abort_transfer();
+
+    /** Clear the transaction buffer
+     */
+    void clear_transfer_buffer();
+
+    /** Clear the transaction buffer and abort on-going transfer.
+     */
+    void abort_all_transfers();
+
+    /** Configure DMA usage suggestion for non-blocking transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+    */
+    int set_dma_usage(DMAUsage usage);
+
+protected:
+    /** SPI IRQ handler
+     *
+    */
+    void irq_handler_asynch(void);
+
+    /** Common transfer method
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+     * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
+    */
+    int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+    /**
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+     * @return Zero if a transfer was added to the queue, or -1 if the queue is full
+    */
+    int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+    /** Configures a callback, spi peripheral and initiate a new transfer
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+    */
+    void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+    /** Start a new transaction
+     *
+     *  @param data Transaction data
+    */
+    void start_transaction(transaction_t *data);
+
+    /** Dequeue a transaction
+     *
+    */
+    void dequeue_transaction();
+    static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
+#endif
+
+#endif
+
+public:
+    virtual ~SPI() {
+    }
+
+protected:
+    spi_t _spi;
+
+#if DEVICE_SPI_ASYNCH
+    CThunk<SPI> _irq;
+    event_callback_t _callback;
+    DMAUsage _usage;
+#endif
+
+    void aquire(void);
+    static SPI *_owner;
+    static SingletonPtr<PlatformMutex> _mutex;
+    int _bits;
+    int _mode;
+    int _hz;
+    char _write_fill;
+
+private:
+    /* Private acquire function without locking/unlocking
+     * Implemented in order to avoid duplicate locking and boost performance
+     */
+    void _acquire(void);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPISlave.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPISlave.cpp
new file mode 100755
index 0000000..8ae263e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPISlave.cpp
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+    _spi(),
+    _bits(8),
+    _mode(0),
+    _hz(1000000)
+ {
+    spi_init(&_spi, mosi, miso, sclk, ssel);
+    spi_format(&_spi, _bits, _mode, 1);
+    spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode) {
+    _bits = bits;
+    _mode = mode;
+    spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz) {
+    _hz = hz;
+    spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void) {
+    return(spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void) {
+    return(spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value) {
+    spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPISlave.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPISlave.h
new file mode 100755
index 0000000..c6226b2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SPISlave.h
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform/platform.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_SPISLAVE) || defined(DOXYGEN_ONLY)
+
+#include "hal/spi_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ *     device.reply(0x00);              // Prime SPI with first reply
+ *     while(1) {
+ *         if(device.receive()) {
+ *             int v = device.read();   // Read byte from master
+ *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
+ *             device.reply(v);         // Make this the next reply
+ *         }
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class SPISlave : private NonCopyable<SPISlave> {
+
+public:
+
+    /** Create a SPI slave connected to the specified pins
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     */
+    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Polls the SPI to see if data has been received
+     *
+     *  @returns
+     *    0 if no data,
+     *    1 otherwise
+     */
+    int receive(void);
+
+    /** Retrieve  data from receive buffer as slave
+     *
+     *  @returns
+     *    the data in the receive buffer
+     */
+    int read(void);
+
+    /** Fill the transmission buffer with the value to be written out
+     *  as slave on the next received message from the master.
+     *
+     *  @param value the data to be transmitted next
+     */
+    void reply(int value);
+
+protected:
+    spi_t _spi;
+
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Serial.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Serial.cpp
new file mode 100755
index 0000000..8e3ce51
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Serial.cpp
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Serial.h"
+#include "platform/mbed_wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name, int baud) : SerialBase(tx, rx, baud), Stream(name) {
+}
+
+Serial::Serial(PinName tx, PinName rx, int baud): SerialBase(tx, rx, baud), Stream(NULL) {
+}
+
+int Serial::_getc() {
+    // Mutex is already held
+    return _base_getc();
+}
+
+int Serial::_putc(int c) {
+    // Mutex is already held
+    return _base_putc(c);
+}
+
+void Serial::lock() {
+    _mutex.lock();
+}
+
+void Serial::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Serial.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Serial.h
new file mode 100755
index 0000000..549943a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Serial.h
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "PlatformMutex.h"
+#include "serial_api.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.printf("Hello World\n");
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Serial : public SerialBase, public Stream, private NonCopyable<Serial> {
+
+public:
+#if DEVICE_SERIAL_ASYNCH
+    using SerialBase::read;
+    using SerialBase::write;
+#endif
+
+    /** Create a Serial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *  @param name The name of the stream associated with this serial port (optional)
+     *  @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    Serial(PinName tx, PinName rx, const char *name=NULL, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+
+
+    /** Create a Serial port, connected to the specified transmit and receive pins, with the specified baud
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *  @param baud The baud rate of the serial port
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    Serial(PinName tx, PinName rx, int baud);
+
+    /* Stream gives us a FileHandle with non-functional poll()/readable()/writable. Pass through
+     * the calls from the SerialBase instead for backwards compatibility. This problem is
+     * part of why Stream and Serial should be deprecated.
+     */
+    bool readable()
+    {
+        return SerialBase::readable();
+    }
+    bool writable()
+    {
+        return SerialBase::writeable();
+    }
+    bool writeable()
+    {
+        return SerialBase::writeable();
+    }
+
+protected:
+    virtual int _getc();
+    virtual int _putc(int c);
+    virtual void lock();
+    virtual void unlock();
+
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SerialBase.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SerialBase.cpp
new file mode 100755
index 0000000..5ec47ff
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SerialBase.cpp
@@ -0,0 +1,292 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SerialBase.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+SerialBase::SerialBase(PinName tx, PinName rx, int baud) :
+#if DEVICE_SERIAL_ASYNCH
+                                                 _thunk_irq(this), _tx_usage(DMA_USAGE_NEVER),
+                                                 _rx_usage(DMA_USAGE_NEVER), _tx_callback(NULL),
+                                                 _rx_callback(NULL),
+#endif
+                                                _serial(), _baud(baud) {
+    // No lock needed in the constructor
+
+    for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+        _irq[i] = NULL;
+    }
+
+    serial_init(&_serial, tx, rx);
+    serial_baud(&_serial, _baud);
+    serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate) {
+    lock();
+    serial_baud(&_serial, baudrate);
+    _baud = baudrate;
+    unlock();
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits) {
+    lock();
+    serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+    unlock();
+}
+
+int SerialBase::readable() {
+    lock();
+    int ret = serial_readable(&_serial);
+    unlock();
+    return ret;
+}
+
+
+int SerialBase::writeable() {
+    lock();
+    int ret = serial_writable(&_serial);
+    unlock();
+    return ret;
+}
+
+void SerialBase::attach(Callback<void()> func, IrqType type) {
+    lock();
+    // Disable interrupts when attaching interrupt handler
+    core_util_critical_section_enter();
+    if (func) {
+        // lock deep sleep only the first time
+        if (!_irq[type]) {
+            sleep_manager_lock_deep_sleep();
+        } 
+        _irq[type] = func;
+        serial_irq_set(&_serial, (SerialIrq)type, 1);
+    } else {
+        // unlock deep sleep only the first time
+        if (_irq[type]) {
+            sleep_manager_unlock_deep_sleep();
+        } 
+        _irq[type] = NULL;
+        serial_irq_set(&_serial, (SerialIrq)type, 0);
+    }
+    core_util_critical_section_exit();
+    unlock();
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
+    SerialBase *handler = (SerialBase*)id;
+    if (handler->_irq[irq_type]) {
+        handler->_irq[irq_type]();
+    }
+}
+
+int SerialBase::_base_getc() {
+    // Mutex is already held
+    return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c) {
+    // Mutex is already held
+    serial_putc(&_serial, c);
+    return c;
+}
+
+void SerialBase::send_break() {
+    lock();
+  // Wait for 1.5 frames before clearing the break condition
+  // This will have different effects on our platforms, but should
+  // ensure that we keep the break active for at least one frame.
+  // We consider a full frame (1 start bit + 8 data bits bits +
+  // 1 parity bit + 2 stop bits = 12 bits) for computation.
+  // One bit time (in us) = 1000000/_baud
+  // Twelve bits: 12000000/baud delay
+  // 1.5 frames: 18000000/baud delay
+  serial_break_set(&_serial);
+  wait_us(18000000/_baud);
+  serial_break_clear(&_serial);
+  unlock();
+}
+
+void SerialBase::lock() {
+    // Stub
+}
+
+void SerialBase:: unlock() {
+    // Stub
+}
+
+SerialBase::~SerialBase()
+{
+    // No lock needed in destructor
+
+    // Detaching interrupts releases the sleep lock if it was locked
+    for (int irq = 0; irq < IrqCnt; irq++) {
+        attach(NULL, (IrqType)irq);
+    }
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
+    lock();
+    FlowControl flow_type = (FlowControl)type;
+    switch(type) {
+        case RTS:
+            serial_set_flow_control(&_serial, flow_type, flow1, NC);
+            break;
+
+        case CTS:
+            serial_set_flow_control(&_serial, flow_type, NC, flow1);
+            break;
+
+        case RTSCTS:
+        case Disabled:
+            serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+            break;
+
+        default:
+            break;
+    }
+    unlock();
+}
+#endif
+
+#if DEVICE_SERIAL_ASYNCH
+
+int SerialBase::write(const uint8_t *buffer, int length, const event_callback_t& callback, int event)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_write((void *)buffer, length, 8, callback, event);
+    return 0;
+}
+
+int SerialBase::write(const uint16_t *buffer, int length, const event_callback_t& callback, int event)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_write((void *)buffer, length, 16, callback, event);
+    return 0;
+}
+
+void SerialBase::start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event)
+{
+    _tx_callback = callback;
+
+    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+    sleep_manager_lock_deep_sleep();
+    serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage);
+}
+
+void SerialBase::abort_write(void)
+{
+    // rx might still be active
+    if (_rx_callback) {
+        sleep_manager_unlock_deep_sleep();
+    }
+    _tx_callback = NULL;
+    serial_tx_abort_asynch(&_serial);
+}
+
+void SerialBase::abort_read(void)
+{
+    // tx might still be active
+    if (_tx_callback) {
+        sleep_manager_unlock_deep_sleep();
+    }
+    _rx_callback = NULL;
+    serial_rx_abort_asynch(&_serial);
+}
+
+int SerialBase::set_dma_usage_tx(DMAUsage usage)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1;
+    }
+    _tx_usage = usage;
+    return 0;
+}
+
+int SerialBase::set_dma_usage_rx(DMAUsage usage)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1;
+    }
+    _rx_usage = usage;
+    return 0;
+}
+
+int SerialBase::read(uint8_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    if (serial_rx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_read((void*)buffer, length, 8, callback, event, char_match);
+    return 0;
+}
+
+
+int SerialBase::read(uint16_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    if (serial_rx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_read((void*)buffer, length, 16, callback, event, char_match);
+    return 0;
+}
+
+
+void SerialBase::start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    _rx_callback = callback;
+    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+    sleep_manager_lock_deep_sleep();
+    serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage);
+}
+
+void SerialBase::interrupt_handler_asynch(void)
+{
+    int event = serial_irq_handler_asynch(&_serial);
+    int rx_event = event & SERIAL_EVENT_RX_MASK;
+    bool unlock_deepsleep = false;
+
+    if (_rx_callback && rx_event) {
+        unlock_deepsleep = true;
+        _rx_callback.call(rx_event);
+    }
+
+    int tx_event = event & SERIAL_EVENT_TX_MASK;
+    if (_tx_callback && tx_event) {
+        unlock_deepsleep = true;
+        _tx_callback.call(tx_event);
+    }
+    // unlock if tx or rx events are generated
+    if (unlock_deepsleep) {
+        sleep_manager_unlock_deep_sleep();
+    }
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SerialBase.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SerialBase.h
new file mode 100755
index 0000000..faf29a0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/SerialBase.h
@@ -0,0 +1,267 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "Callback.h"
+#include "serial_api.h"
+#include "mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ *
+ * @note Synchronization level: Set by subclass
+ * @ingroup drivers
+ */
+class SerialBase : private NonCopyable<SerialBase> {
+
+public:
+    /** Set the baud rate of the serial port
+     *
+     *  @param baudrate The baudrate of the serial port (default = 9600).
+     */
+    void baud(int baudrate);
+
+    enum Parity {
+        None = 0,
+        Odd,
+        Even,
+        Forced1,
+        Forced0
+    };
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq,
+
+        IrqCnt
+    };
+
+    enum Flow {
+        Disabled = 0,
+        RTS,
+        CTS,
+        RTSCTS
+    };
+
+    /** Set the transmission format used by the serial port
+     *
+     *  @param bits The number of bits in a word (5-8; default = 8)
+     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+     *  @param stop_bits The number of stop bits (1 or 2; default = 1)
+     */
+    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+    /** Determine if there is a character available to read
+     *
+     *  @returns
+     *    1 if there is a character available to read,
+     *    0 otherwise
+     */
+    int readable();
+
+    /** Determine if there is space available to write a character
+     *
+     *  @returns
+     *    1 if there is space to write a character,
+     *    0 otherwise
+     */
+    int writeable();
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     *  @param func A pointer to a void function, or 0 to set as none
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    void attach(Callback<void()> func, IrqType type=RxIrq);
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     *  @deprecated
+     *      The attach function does not support cv-qualifiers. Replaced by
+     *      attach(callback(obj, method), type).
+     */
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The attach function does not support cv-qualifiers. Replaced by "
+        "attach(callback(obj, method), type).")
+    void attach(T *obj, void (T::*method)(), IrqType type=RxIrq) {
+        attach(callback(obj, method), type);
+    }
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     *  @deprecated
+     *      The attach function does not support cv-qualifiers. Replaced by
+     *      attach(callback(obj, method), type).
+     */
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The attach function does not support cv-qualifiers. Replaced by "
+        "attach(callback(obj, method), type).")
+    void attach(T *obj, void (*method)(T*), IrqType type=RxIrq) {
+        attach(callback(obj, method), type);
+    }
+
+    /** Generate a break condition on the serial line
+     */
+    void send_break();
+
+protected:
+
+    /** Acquire exclusive access to this serial port
+     */
+    virtual void lock(void);
+
+    /** Release exclusive access to this serial port
+     */
+    virtual void unlock(void);
+
+public:
+
+#if DEVICE_SERIAL_FC
+    /** Set the flow control type on the serial port
+     *
+     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+     *  @param flow2 the second flow control pin (CTS for RTSCTS)
+     */
+    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+    static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+#if DEVICE_SERIAL_ASYNCH
+
+    /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
+     *
+     *  This function locks the deep sleep until any event has occured
+     * 
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
+     *
+     *  This function locks the deep sleep until any event has occured
+     * 
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Abort the on-going write transfer
+     */
+    void abort_write();
+
+    /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
+     *
+     *  This function locks the deep sleep until any event has occured
+     * 
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
+     *
+     *  This function locks the deep sleep until any event has occured
+     * 
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Abort the on-going read transfer
+     */
+    void abort_read();
+
+    /** Configure DMA usage suggestion for non-blocking TX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_tx(DMAUsage usage);
+
+    /** Configure DMA usage suggestion for non-blocking RX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_rx(DMAUsage usage);
+
+protected:
+    void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
+    void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
+    void interrupt_handler_asynch(void);
+#endif
+
+protected:
+    SerialBase(PinName tx, PinName rx, int baud);
+    virtual ~SerialBase();
+
+    int _base_getc();
+    int _base_putc(int c);
+
+#if DEVICE_SERIAL_ASYNCH
+    CThunk<SerialBase> _thunk_irq;
+    DMAUsage _tx_usage;
+    DMAUsage _rx_usage;
+    event_callback_t _tx_callback;
+    event_callback_t _rx_callback;
+#endif
+
+    serial_t         _serial;
+    Callback<void()> _irq[IrqCnt];
+    int              _baud;
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ticker.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ticker.cpp
new file mode 100755
index 0000000..c2589c0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ticker.cpp
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Ticker.h"
+
+#include "drivers/TimerEvent.h"
+#include "platform/FunctionPointer.h"
+#include "hal/ticker_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+    core_util_critical_section_enter();
+    remove();
+    // unlocked only if we were attached (we locked it) and this is not low power ticker
+    if(_function && _lock_deepsleep) {
+        sleep_manager_unlock_deep_sleep();
+    }
+
+    _function = 0;
+    core_util_critical_section_exit();
+}
+
+void Ticker::setup(us_timestamp_t t) {
+    core_util_critical_section_enter();
+    remove();
+    _delay = t;
+    insert_absolute(_delay + ticker_read_us(_ticker_data));
+    core_util_critical_section_exit();
+}
+
+void Ticker::handler() {
+    insert_absolute(event.timestamp + _delay);
+    if (_function) {
+        _function();
+    }
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ticker.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ticker.h
new file mode 100755
index 0000000..c8f1f9d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Ticker.h
@@ -0,0 +1,164 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "drivers/TimerEvent.h"
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+#include "platform/mbed_sleep.h"
+#include "hal/lp_ticker_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ *  You can use as many separate Ticker objects as you require.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ *     flip = !flip;
+ * }
+ *
+ * int main() {
+ *     timer.attach(&attime, 5);
+ *     while(1) {
+ *         if(flip == 0) {
+ *             led1 = !led1;
+ *         } else {
+ *             led2 = !led2;
+ *         }
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Ticker : public TimerEvent, private NonCopyable<Ticker> {
+
+public:
+    Ticker() : TimerEvent(), _function(0), _lock_deepsleep(true) {
+    }
+
+    // When low power ticker is in use, then do not disable deep-sleep.
+    Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(true)  {
+        data->interface->init();
+#if DEVICE_LOWPOWERTIMER
+        _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
+    }
+
+    /** Attach a function to be called by the Ticker, specifying the interval in seconds
+     *
+     *  @param func pointer to the function to be called
+     *  @param t the time between calls in seconds
+     */
+    void attach(Callback<void()> func, float t) {
+        attach_us(func, t * 1000000.0f);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifying the interval in seconds
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @param t the time between calls in seconds
+     *  @deprecated
+     *      The attach function does not support cv-qualifiers. Replaced by
+     *      attach(callback(obj, method), t).
+     */
+    template<typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The attach function does not support cv-qualifiers. Replaced by "
+        "attach(callback(obj, method), t).")
+    void attach(T *obj, M method, float t) {
+        attach(callback(obj, method), t);
+    }
+
+    /** Attach a function to be called by the Ticker, specifying the interval in micro-seconds
+     *
+     *  @param func pointer to the function to be called
+     *  @param t the time between calls in micro-seconds
+     *
+     *  @note setting @a t to a value shorter that it takes to process the ticker callback
+     *  will cause the system to hang. Ticker callback will be called constantly with no time
+     *  for threads scheduling.
+     *
+     */
+    void attach_us(Callback<void()> func, us_timestamp_t t) {
+        core_util_critical_section_enter();
+        // lock only for the initial callback setup and this is not low power ticker
+        if(!_function && _lock_deepsleep) {
+            sleep_manager_lock_deep_sleep();
+        }
+        _function = func;
+        setup(t);
+        core_util_critical_section_exit();
+    }
+
+    /** Attach a member function to be called by the Ticker, specifying the interval in micro-seconds
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @param t the time between calls in micro-seconds
+     *  @deprecated
+     *      The attach_us function does not support cv-qualifiers. Replaced by
+     *      attach_us(callback(obj, method), t).
+     */
+    template<typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The attach_us function does not support cv-qualifiers. Replaced by "
+        "attach_us(callback(obj, method), t).")
+    void attach_us(T *obj, M method, us_timestamp_t t) {
+        attach_us(Callback<void()>(obj, method), t);
+    }
+
+    virtual ~Ticker() {
+        detach();
+    }
+
+    /** Detach the function
+     */
+    void detach();
+
+protected:
+    void setup(us_timestamp_t t);
+    virtual void handler();
+
+protected:
+    us_timestamp_t         _delay;  /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+    Callback<void()>    _function;  /**< Callback. */
+    bool          _lock_deepsleep;  /**< Flag which indicates if deep-sleep should be disabled. */
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timeout.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timeout.cpp
new file mode 100755
index 0000000..40c7d9f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timeout.cpp
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+    _function.call();
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timeout.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timeout.h
new file mode 100755
index 0000000..8d9a193
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timeout.h
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "drivers/Ticker.h"
+#include "platform/NonCopyable.h"
+#include "platform/mbed_sleep.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ *     on = 0;
+ * }
+ *
+ * int main() {
+ *     timeout.attach(&attimeout, 5);
+ *     while(on) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Timeout : public Ticker, private NonCopyable<Timeout> {
+
+protected:
+    virtual void handler();
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timer.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timer.cpp
new file mode 100755
index 0000000..f523974
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timer.cpp
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Timer.h"
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+#include "platform/mbed_critical.h"
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()), _lock_deepsleep(true) {
+    reset();
+}
+
+Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data), _lock_deepsleep(true) {
+    reset();
+#if DEVICE_LOWPOWERTIMER
+    _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
+}
+
+Timer::~Timer() {
+    core_util_critical_section_enter();
+    if (_running) {
+        if(_lock_deepsleep) {
+            sleep_manager_unlock_deep_sleep();
+        }
+    }
+    _running = 0;
+    core_util_critical_section_exit();
+}
+
+void Timer::start() {
+    core_util_critical_section_enter();
+    if (!_running) {
+        if(_lock_deepsleep) {
+            sleep_manager_lock_deep_sleep();
+        }
+        _start = ticker_read_us(_ticker_data);
+        _running = 1;
+    }
+    core_util_critical_section_exit();
+}
+
+void Timer::stop() {
+    core_util_critical_section_enter();
+    _time += slicetime();
+    if (_running) {
+        if(_lock_deepsleep) {
+            sleep_manager_unlock_deep_sleep();
+        }
+    }
+    _running = 0;
+    core_util_critical_section_exit();
+}
+
+int Timer::read_us() {
+    return read_high_resolution_us();
+}
+
+float Timer::read() {
+    return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+    return read_high_resolution_us() / 1000;
+}
+
+us_timestamp_t Timer::read_high_resolution_us() {
+    core_util_critical_section_enter();
+    us_timestamp_t time = _time + slicetime();
+    core_util_critical_section_exit();
+    return time;
+}
+
+us_timestamp_t Timer::slicetime() {
+    us_timestamp_t ret = 0;
+    core_util_critical_section_enter();
+    if (_running) {
+        ret = ticker_read_us(_ticker_data) - _start;
+    }
+    core_util_critical_section_exit();
+    return ret;
+}
+
+void Timer::reset() {
+    core_util_critical_section_enter();
+    _start = ticker_read_us(_ticker_data);
+    _time = 0;
+    core_util_critical_section_exit();
+}
+
+Timer::operator float() {
+    return read();
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timer.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timer.h
new file mode 100755
index 0000000..a875800
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/Timer.h
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform/platform.h"
+#include "hal/ticker_api.h"
+#include "platform/NonCopyable.h"
+#include "platform/mbed_sleep.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A general purpose timer
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ *     timer.start();
+ *     begin = timer.read_us();
+ *     led = !led;
+ *     end = timer.read_us();
+ *     printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Timer : private NonCopyable<Timer> {
+
+public:
+    Timer();
+    Timer(const ticker_data_t *data);
+    ~Timer();
+
+    /** Start the timer
+     */
+    void start();
+
+    /** Stop the timer
+     */
+    void stop();
+
+    /** Reset the timer to 0.
+     *
+     * If it was already counting, it will continue
+     */
+    void reset();
+
+    /** Get the time passed in seconds
+     *
+     *  @returns    Time passed in seconds
+     */
+    float read();
+
+    /** Get the time passed in milli-seconds
+     *
+     *  @returns    Time passed in milli seconds
+     */
+    int read_ms();
+
+    /** Get the time passed in micro-seconds
+     *
+     *  @returns    Time passed in micro seconds
+     */
+    int read_us();
+
+    /** An operator shorthand for read()
+     */
+    operator float();
+
+    /** Get in a high resolution type the time passed in micro-seconds.
+     */
+    us_timestamp_t read_high_resolution_us();
+
+protected:
+    us_timestamp_t slicetime();
+    int _running;            // whether the timer is running
+    us_timestamp_t _start;   // the start time of the latest slice
+    us_timestamp_t _time;    // any accumulated time from previous slices
+    const ticker_data_t *_ticker_data;
+    bool _lock_deepsleep;    // flag which indicates if deep-sleep should be disabled
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/TimerEvent.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/TimerEvent.cpp
new file mode 100755
index 0000000..d7a7c1c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/TimerEvent.cpp
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event(), _ticker_data(get_us_ticker_data()) {
+    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) {
+    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+    TimerEvent *timer_event = (TimerEvent*)id;
+    timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+    remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(timestamp_t timestamp) {
+    ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::insert_absolute(us_timestamp_t timestamp) {
+    ticker_insert_event_us(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+    ticker_remove_event(_ticker_data, &event);
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/TimerEvent.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/TimerEvent.h
new file mode 100755
index 0000000..45c3c14
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/TimerEvent.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Base abstraction for timer interrupts
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class TimerEvent : private NonCopyable<TimerEvent> {
+public:
+    TimerEvent();
+    TimerEvent(const ticker_data_t *data);
+
+    /** The handler registered with the underlying timer interrupt
+     *
+     *  @param id       Timer Event ID
+     */
+    static void irq(uint32_t id);
+
+    /** Destruction removes it...
+     */
+    virtual ~TimerEvent();
+
+protected:
+    // The handler called to service the timer event of the derived class
+    virtual void handler() = 0;
+
+    // insert relative timestamp in to linked list
+    void insert(timestamp_t timestamp);
+
+    // insert absolute timestamp into linked list
+    void insert_absolute(us_timestamp_t timestamp);
+
+    // remove from linked list, if in it
+    void remove();
+
+    ticker_event_t event;
+
+    const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/UARTSerial.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/UARTSerial.cpp
new file mode 100755
index 0000000..5cad4ff
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/UARTSerial.cpp
@@ -0,0 +1,298 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if (DEVICE_SERIAL && DEVICE_INTERRUPTIN)
+
+#include <errno.h>
+#include "UARTSerial.h"
+#include "platform/mbed_poll.h"
+
+#if MBED_CONF_RTOS_PRESENT
+#include "rtos/Thread.h"
+#else
+#include "platform/mbed_wait_api.h"
+#endif
+
+namespace mbed {
+
+UARTSerial::UARTSerial(PinName tx, PinName rx, int baud) :
+        SerialBase(tx, rx, baud),
+        _blocking(true),
+        _tx_irq_enabled(false),
+        _dcd_irq(NULL)
+{
+    /* Attatch IRQ routines to the serial device. */
+    SerialBase::attach(callback(this, &UARTSerial::rx_irq), RxIrq);
+}
+
+UARTSerial::~UARTSerial()
+{
+    delete _dcd_irq;
+}
+
+void UARTSerial::dcd_irq()
+{
+    wake();
+}
+
+void UARTSerial::set_baud(int baud)
+{
+    SerialBase::baud(baud);
+}
+
+void UARTSerial::set_data_carrier_detect(PinName dcd_pin, bool active_high)
+{
+     delete _dcd_irq;
+    _dcd_irq = NULL;
+
+    if (dcd_pin != NC) {
+        _dcd_irq = new InterruptIn(dcd_pin);
+        if (active_high) {
+            _dcd_irq->fall(callback(this, &UARTSerial::dcd_irq));
+        } else {
+            _dcd_irq->rise(callback(this, &UARTSerial::dcd_irq));
+        }
+    }
+}
+
+int UARTSerial::close()
+{
+    /* Does not let us pass a file descriptor. So how to close ?
+     * Also, does it make sense to close a device type file descriptor*/
+    return 0;
+}
+
+int UARTSerial::isatty()
+{
+    return 1;
+
+}
+
+off_t UARTSerial::seek(off_t offset, int whence)
+{
+    /*XXX lseek can be done theoratically, but is it sane to mark positions on a dynamically growing/shrinking
+     * buffer system (from an interrupt context) */
+    return -ESPIPE;
+}
+
+int UARTSerial::sync()
+{
+    api_lock();
+
+    while (!_txbuf.empty()) {
+        api_unlock();
+        // Doing better than wait would require TxIRQ to also do wake() when becoming empty. Worth it?
+        wait_ms(1);
+        api_lock();
+    }
+
+    api_unlock();
+
+    return 0;
+}
+
+void UARTSerial::sigio(Callback<void()> func) {
+    core_util_critical_section_enter();
+    _sigio_cb = func;
+    if (_sigio_cb) {
+        short current_events = poll(0x7FFF);
+        if (current_events) {
+            _sigio_cb();
+        }
+    }
+    core_util_critical_section_exit();
+}
+
+ssize_t UARTSerial::write(const void* buffer, size_t length)
+{
+    size_t data_written = 0;
+    const char *buf_ptr = static_cast<const char *>(buffer);
+
+    api_lock();
+
+    while (_txbuf.full()) {
+        if (!_blocking) {
+            api_unlock();
+            return -EAGAIN;
+        }
+        api_unlock();
+        wait_ms(1); // XXX todo - proper wait, WFE for non-rtos ?
+        api_lock();
+    }
+
+    while (data_written < length && !_txbuf.full()) {
+        _txbuf.push(*buf_ptr++);
+        data_written++;
+    }
+
+    core_util_critical_section_enter();
+    if (!_tx_irq_enabled) {
+        UARTSerial::tx_irq();                // only write to hardware in one place
+        if (!_txbuf.empty()) {
+            SerialBase::attach(callback(this, &UARTSerial::tx_irq), TxIrq);
+            _tx_irq_enabled = true;
+        }
+    }
+    core_util_critical_section_exit();
+
+    api_unlock();
+
+    return data_written;
+}
+
+ssize_t UARTSerial::read(void* buffer, size_t length)
+{
+    size_t data_read = 0;
+
+    char *ptr = static_cast<char *>(buffer);
+
+    api_lock();
+
+    while (_rxbuf.empty()) {
+        if (!_blocking) {
+            api_unlock();
+            return -EAGAIN;
+        }
+        api_unlock();
+        wait_ms(1);  // XXX todo - proper wait, WFE for non-rtos ?
+        api_lock();
+    }
+
+    while (data_read < length && !_rxbuf.empty()) {
+        _rxbuf.pop(*ptr++);
+        data_read++;
+    }
+
+    api_unlock();
+
+    return data_read;
+}
+
+bool UARTSerial::hup() const
+{
+    return _dcd_irq && _dcd_irq->read() != 0;
+}
+
+void UARTSerial::wake()
+{
+    if (_sigio_cb) {
+        _sigio_cb();
+    }
+}
+
+short UARTSerial::poll(short events) const {
+
+    short revents = 0;
+    /* Check the Circular Buffer if space available for writing out */
+
+
+    if (!_rxbuf.empty()) {
+        revents |= POLLIN;
+    }
+
+    /* POLLHUP and POLLOUT are mutually exclusive */
+    if (hup()) {
+        revents |= POLLHUP;
+    } else if (!_txbuf.full()) {
+        revents |= POLLOUT;
+    }
+
+    /*TODO Handle other event types */
+
+    return revents;
+}
+
+void UARTSerial::lock()
+{
+    // This is the override for SerialBase.
+    // No lock required as we only use SerialBase from interrupt or from
+    // inside our own critical section.
+}
+
+void UARTSerial::unlock()
+{
+    // This is the override for SerialBase.
+}
+
+void UARTSerial::api_lock(void)
+{
+    _mutex.lock();
+}
+
+void UARTSerial::api_unlock(void)
+{
+    _mutex.unlock();
+}
+
+void UARTSerial::rx_irq(void)
+{
+    bool was_empty = _rxbuf.empty();
+
+    /* Fill in the receive buffer if the peripheral is readable
+     * and receive buffer is not full. */
+    while (SerialBase::readable()) {
+        char data = SerialBase::_base_getc();
+        if (!_rxbuf.full()) {
+            _rxbuf.push(data);
+        } else {
+            /* Drop - can we report in some way? */
+        }
+    }
+
+    /* Report the File handler that data is ready to be read from the buffer. */
+    if (was_empty && !_rxbuf.empty()) {
+        wake();
+    }
+}
+
+// Also called from write to start transfer
+void UARTSerial::tx_irq(void)
+{
+    bool was_full = _txbuf.full();
+
+    /* Write to the peripheral if there is something to write
+     * and if the peripheral is available to write. */
+    while (!_txbuf.empty() && SerialBase::writeable()) {
+        char data;
+        _txbuf.pop(data);
+        SerialBase::_base_putc(data);
+    }
+
+    if (_tx_irq_enabled && _txbuf.empty()) {
+        SerialBase::attach(NULL, TxIrq);
+        _tx_irq_enabled = false;
+    }
+
+    /* Report the File handler that data can be written to peripheral. */
+    if (was_full && !_txbuf.full() && !hup()) {
+        wake();
+    }
+}
+
+void UARTSerial::wait_ms(uint32_t millisec)
+{
+    /* wait_ms implementation for RTOS spins until exact microseconds - we
+     * want to just sleep until next tick.
+     */
+#if MBED_CONF_RTOS_PRESENT
+    rtos::Thread::wait(millisec);
+#else
+    ::wait_ms(millisec);
+#endif
+}
+} //namespace mbed
+
+#endif //(DEVICE_SERIAL && DEVICE_INTERRUPTIN)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/UARTSerial.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/UARTSerial.h
new file mode 100755
index 0000000..c0069ad
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/UARTSerial.h
@@ -0,0 +1,220 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_UARTSERIAL_H
+#define MBED_UARTSERIAL_H
+
+#include "platform/platform.h"
+
+#if (DEVICE_SERIAL && DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
+
+#include "FileHandle.h"
+#include "SerialBase.h"
+#include "InterruptIn.h"
+#include "PlatformMutex.h"
+#include "serial_api.h"
+#include "CircularBuffer.h"
+#include "platform/NonCopyable.h"
+
+#ifndef MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE
+#define MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE  256
+#endif
+
+#ifndef MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE
+#define MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE  256
+#endif
+
+namespace mbed {
+
+class UARTSerial : private SerialBase, public FileHandle, private NonCopyable<UARTSerial> {
+
+public:
+
+    /** Create a UARTSerial port, connected to the specified transmit and receive pins, with a particular baud rate.
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *  @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+     */
+    UARTSerial(PinName tx, PinName rx, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+    virtual ~UARTSerial();
+
+    /** Equivalent to POSIX poll(). Derived from FileHandle.
+     *  Provides a mechanism to multiplex input/output over a set of file handles.
+     */
+    virtual short poll(short events) const;
+
+    /* Resolve ambiguities versus our private SerialBase
+     * (for writable, spelling differs, but just in case)
+     */
+    using FileHandle::readable;
+    using FileHandle::writable;
+
+    /** Write the contents of a buffer to a file
+     *
+     *  @param buffer   The buffer to write from
+     *  @param length   The number of bytes to write
+     *  @return         The number of bytes written, negative error on failure
+     */
+    virtual ssize_t write(const void* buffer, size_t length);
+
+    /** Read the contents of a file into a buffer
+     *
+     *  Follows POSIX semantics:
+     *
+     *  * if no data is available, and non-blocking set return -EAGAIN
+     *  * if no data is available, and blocking set, wait until data is available
+     *  * If any data is available, call returns immediately
+     *
+     *  @param buffer   The buffer to read in to
+     *  @param length   The number of bytes to read
+     *  @return         The number of bytes read, 0 at end of file, negative error on failure
+     */
+    virtual ssize_t read(void* buffer, size_t length);
+
+    /** Close a file
+     *
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int close();
+
+    /** Check if the file in an interactive terminal device
+     *
+     *  @return         True if the file is a terminal
+     *  @return         False if the file is not a terminal
+     *  @return         Negative error code on failure
+     */
+    virtual int isatty();
+
+    /** Move the file position to a given offset from from a given location
+     *
+     * Not valid for a device type FileHandle like UARTSerial.
+     * In case of UARTSerial, returns ESPIPE
+     *
+     *  @param offset   The offset from whence to move to
+     *  @param whence   The start of where to seek
+     *      SEEK_SET to start from beginning of file,
+     *      SEEK_CUR to start from current position in file,
+     *      SEEK_END to start from end of file
+     *  @return         The new offset of the file, negative error code on failure
+     */
+    virtual off_t seek(off_t offset, int whence);
+
+    /** Flush any buffers associated with the file
+     *
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int sync();
+
+    /** Set blocking or non-blocking mode
+     *  The default is blocking.
+     *
+     *  @param blocking true for blocking mode, false for non-blocking mode.
+     */
+    virtual int set_blocking(bool blocking)
+    {
+        _blocking = blocking;
+        return 0;
+    }
+
+    /** Register a callback on state change of the file.
+     *
+     *  The specified callback will be called on state changes such as when
+     *  the file can be written to or read from.
+     *
+     *  The callback may be called in an interrupt context and should not
+     *  perform expensive operations.
+     *
+     *  Note! This is not intended as an attach-like asynchronous api, but rather
+     *  as a building block for constructing  such functionality.
+     *
+     *  The exact timing of when the registered function
+     *  is called is not guaranteed and susceptible to change. It should be used
+     *  as a cue to make read/write/poll calls to find the current state.
+     *
+     *  @param func     Function to call on state change
+     */
+    virtual void sigio(Callback<void()> func);
+
+    /** Setup interrupt handler for DCD line
+     *
+     *  If DCD line is connected, an IRQ handler will be setup.
+     *  Does nothing if DCD is NC, i.e., not connected.
+     *
+     *  @param dcd_pin         Pin-name for DCD
+     *  @param active_high     a boolean set to true if DCD polarity is active low
+     */
+    void set_data_carrier_detect(PinName dcd_pin, bool active_high = false);
+
+    /** Set the baud rate
+     *
+     *  @param baud   The baud rate
+     */
+    void set_baud(int baud);
+
+private:
+
+    void wait_ms(uint32_t millisec);
+
+    /** SerialBase lock override */
+    virtual void lock(void);
+
+    /** SerialBase unlock override */
+    virtual void unlock(void);
+
+    /** Acquire mutex */
+    virtual void api_lock(void);
+
+    /** Release mutex */
+    virtual void api_unlock(void);
+
+    /** Software serial buffers
+     *  By default buffer size is 256 for TX and 256 for RX. Configurable through mbed_app.json
+     */
+    CircularBuffer<char, MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE> _rxbuf;
+    CircularBuffer<char, MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE> _txbuf;
+
+    PlatformMutex _mutex;
+
+    Callback<void()> _sigio_cb;
+
+    bool _blocking;
+    bool _tx_irq_enabled;
+    InterruptIn *_dcd_irq;
+
+    /** Device Hanged up
+     *  Determines if the device hanged up on us.
+     *
+     *  @return True, if hanged up
+     */
+    bool hup() const;
+
+    /** ISRs for serial
+     *  Routines to handle interrupts on serial pins.
+     *  Copies data into Circular Buffer.
+     *  Reports the state change to File handle.
+     */
+    void tx_irq(void);
+    void rx_irq(void);
+
+    void wake(void);
+
+    void dcd_irq(void);
+
+};
+} //namespace mbed
+
+#endif //(DEVICE_SERIAL && DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
+#endif //MBED_UARTSERIAL_H
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/mbed_lib.json
new file mode 100755
index 0000000..c268b63
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/drivers/mbed_lib.json
@@ -0,0 +1,13 @@
+{
+    "name": "drivers",
+    "config": {
+        "uart-serial-txbuf-size": {
+            "help": "Default TX buffer size for a UARTSerial instance (unit Bytes))",
+            "value": 256
+        },
+        "uart-serial-rxbuf-size": {
+            "help": "Default RX buffer size for a UARTSerial instance (unit Bytes))",
+            "value": 256
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/Event.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/Event.h
new file mode 100755
index 0000000..2e2d8f6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/Event.h
@@ -0,0 +1,3627 @@
+/* events
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef EVENT_H
+#define EVENT_H
+
+#include "events/EventQueue.h"
+#include "platform/mbed_assert.h"
+
+namespace events {
+/** \addtogroup events */
+
+/** Event
+ *
+ *  Representation of an event for fine-grain dispatch control
+ * @ingroup events
+ */
+template <typename F>
+class Event;
+
+/** Event
+ *
+ *  Representation of an event for fine-grain dispatch control
+ * @ingroup events
+ */
+template <>
+class Event<void()> {
+public:
+    /** Create an event
+     *
+     *  Constructs an event bound to the specified event queue. The specified
+     *  callback acts as the target for the event and is executed in the
+     *  context of the event queue's dispatch loop once posted.
+     *
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     */
+    template <typename F>
+    Event(EventQueue *q, F f) {
+        _event = static_cast<struct event *>(
+                equeue_alloc(&q->_equeue, sizeof(struct event) + sizeof(F)));
+
+        if (_event) {
+            _event->equeue = &q->_equeue;
+            _event->id = 0;
+            _event->delay = 0;
+            _event->period = -1;
+
+            _event->post = &Event::event_post<F>;
+            _event->dtor = &Event::event_dtor<F>;
+
+            new (_event+1) F(f);
+
+            _event->ref = 1;
+        }
+    }
+
+    /** Copy constructor for events
+     */
+    Event(const Event &e) {
+        _event = 0;
+        if (e._event) {
+            _event = e._event;
+            _event->ref += 1;
+        }
+    }
+
+    /** Assignment operator for events
+     */
+    Event &operator=(const Event &that) {
+        if (this != &that) {
+            this->~Event();
+            new (this) Event(that);
+        }
+
+        return *this;
+    }
+
+    /** Destructor for events
+     */
+    ~Event() {
+        if (_event) {
+            _event->ref -= 1;
+            if (_event->ref == 0) {
+                _event->dtor(_event);
+                equeue_dealloc(_event->equeue, _event);
+            }
+        }
+    }
+
+    /** Configure the delay of an event
+     *
+     *  @param delay    Millisecond delay before dispatching the event
+     */
+    void delay(int delay) {
+        if (_event) {
+            _event->delay = delay;
+        }
+    }
+
+    /** Configure the period of an event
+     *
+     *  @param period   Millisecond period for repeatedly dispatching an event
+     */
+    void period(int period) {
+        if (_event) {
+            _event->period = period;
+        }
+    }
+
+    /** Posts an event onto the underlying event queue
+     *
+     *  The event is posted to the underlying queue and is executed in the
+     *  context of the event queue's dispatch loop.
+     *
+     *  The post function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @return         A unique id that represents the posted event and can
+     *                  be passed to EventQueue::cancel, or an id of 0 if
+     *                  there is not enough memory to allocate the event.
+     */
+    int post() const {
+        if (!_event) {
+            return 0;
+        }
+
+        _event->id = _event->post(_event);
+        return _event->id;
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     */
+    void call() const {
+        MBED_UNUSED int id = post();
+        MBED_ASSERT(id);
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     */
+    void operator()() const {
+        return call();
+    }
+
+    /** Static thunk for passing as C-style function
+     *
+     *  @param func     Event to call passed as a void pointer
+     */
+    static void thunk(void *func) {
+        return static_cast<Event*>(func)->call();
+    }
+
+    /** Cancels the most recently posted event
+     *
+     *  Attempts to cancel the most recently posted event. It is safe to call
+     *  cancel after an event has already been dispatched.
+     *
+     *  The cancel function is irq safe.
+     *
+     *  If called while the event queue's dispatch loop is active, the cancel
+     *  function does not garuntee that the event will not execute after it
+     *  returns, as the event may have already begun executing.
+     */
+    void cancel() const {
+        if (_event) {
+            equeue_cancel(_event->equeue, _event->id);
+        }
+    }
+
+private:
+    struct event {
+        unsigned ref;
+        equeue_t *equeue;
+        int id;
+
+        int delay;
+        int period;
+
+        int (*post)(struct event *);
+        void (*dtor)(struct event *);
+
+        // F follows
+    } *_event;
+
+    // Event attributes
+    template <typename F>
+    static int event_post(struct event *e) {
+        typedef EventQueue::context00<F> C;
+        void *p = equeue_alloc(e->equeue, sizeof(C));
+        if (!p) {
+            return 0;
+        }
+
+        new (p) C(*(F*)(e + 1));
+        equeue_event_delay(p, e->delay);
+        equeue_event_period(p, e->period);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
+    }
+
+    template <typename F>
+    static void event_dtor(struct event *e) {
+        ((F*)(e + 1))->~F();
+    }
+
+public:
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0               Argument to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0>
+    Event(EventQueue *q, F f, C0 c0) {
+        new (this) Event(q, EventQueue::context10<F, C0>(f, c0));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1            Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b1, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1>
+    Event(EventQueue *q, F f, C0 c0, C1 c1) {
+        new (this) Event(q, EventQueue::context20<F, C0, C1>(f, c0, c1));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2         Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b2, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2) {
+        new (this) Event(q, EventQueue::context30<F, C0, C1, C2>(f, c0, c1, c2));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3      Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b3, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3) {
+        new (this) Event(q, EventQueue::context40<F, C0, C1, C2, C3>(f, c0, c1, c2, c3));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3,c4   Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b4, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+        new (this) Event(q, EventQueue::context50<F, C0, C1, C2, C3, C4>(f, c0, c1, c2, c3, c4));
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0), B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0) const, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0) volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0) const volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1), B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1) const, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1) volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1) const volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2), B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2) const, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2) volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2) const volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3), B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3) const, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3) volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3) const volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, B4), B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, B4) const, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4) volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4) const volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+};
+
+/** Event
+ *
+ *  Representation of an event for fine-grain dispatch control
+ * @ingroup events
+ */
+template <typename A0>
+class Event<void(A0)> {
+public:
+    /** Create an event
+     *
+     *  Constructs an event bound to the specified event queue. The specified
+     *  callback acts as the target for the event and is executed in the
+     *  context of the event queue's dispatch loop once posted.
+     *
+     *  @param q        Event queue to dispatch on
+     *  @param f        Function to execute when the event is dispatched
+     */
+    template <typename F>
+    Event(EventQueue *q, F f) {
+        _event = static_cast<struct event *>(
+                equeue_alloc(&q->_equeue, sizeof(struct event) + sizeof(F)));
+
+        if (_event) {
+            _event->equeue = &q->_equeue;
+            _event->id = 0;
+            _event->delay = 0;
+            _event->period = -1;
+
+            _event->post = &Event::event_post<F>;
+            _event->dtor = &Event::event_dtor<F>;
+
+            new (_event+1) F(f);
+
+            _event->ref = 1;
+        }
+    }
+
+    /** Copy constructor for events
+     */
+    Event(const Event &e) {
+        _event = 0;
+        if (e._event) {
+            _event = e._event;
+            _event->ref += 1;
+        }
+    }
+
+    /** Assignment operator for events
+     */
+    Event &operator=(const Event &that) {
+        if (this != &that) {
+            this->~Event();
+            new (this) Event(that);
+        }
+
+        return *this;
+    }
+
+    /** Destructor for events
+     */
+    ~Event() {
+        if (_event) {
+            _event->ref -= 1;
+            if (_event->ref == 0) {
+                _event->dtor(_event);
+                equeue_dealloc(_event->equeue, _event);
+            }
+        }
+    }
+
+    /** Configure the delay of an event
+     *
+     *  @param delay    Millisecond delay before dispatching the event
+     */
+    void delay(int delay) {
+        if (_event) {
+            _event->delay = delay;
+        }
+    }
+
+    /** Configure the period of an event
+     *
+     *  @param period   Millisecond period for repeatedly dispatching an event
+     */
+    void period(int period) {
+        if (_event) {
+            _event->period = period;
+        }
+    }
+
+    /** Posts an event onto the underlying event queue
+     *
+     *  The event is posted to the underlying queue and is executed in the
+     *  context of the event queue's dispatch loop.
+     *
+     *  The post function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @param a0       Argument to pass to the event
+     *  @return         A unique id that represents the posted event and can
+     *                  be passed to EventQueue::cancel, or an id of 0 if
+     *                  there is not enough memory to allocate the event.
+     */
+    int post(A0 a0) const {
+        if (!_event) {
+            return 0;
+        }
+
+        _event->id = _event->post(_event, a0);
+        return _event->id;
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0       Argument to pass to the event
+     */
+    void call(A0 a0) const {
+        MBED_UNUSED int id = post(a0);
+        MBED_ASSERT(id);
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0      Argument to pass to the event
+     */
+    void operator()(A0 a0) const {
+        return call(a0);
+    }
+
+    /** Static thunk for passing as C-style function
+     *
+     *  @param func     Event to call passed as a void pointer
+     *  @param a0       Argument to pass to the event
+     */
+    static void thunk(void *func, A0 a0) {
+        return static_cast<Event*>(func)->call(a0);
+    }
+
+    /** Cancels the most recently posted event
+     *
+     *  Attempts to cancel the most recently posted event. It is safe to call
+     *  cancel after an event has already been dispatched.
+     *
+     *  The cancel function is irq safe.
+     *
+     *  If called while the event queue's dispatch loop is active, the cancel
+     *  function does not garuntee that the event will not execute after it
+     *  returns, as the event may have already begun executing.
+     */
+    void cancel() const {
+        if (_event) {
+            equeue_cancel(_event->equeue, _event->id);
+        }
+    }
+
+private:
+    struct event {
+        unsigned ref;
+        equeue_t *equeue;
+        int id;
+
+        int delay;
+        int period;
+
+        int (*post)(struct event *, A0 a0);
+        void (*dtor)(struct event *);
+
+        // F follows
+    } *_event;
+
+    // Event attributes
+    template <typename F>
+    static int event_post(struct event *e, A0 a0) {
+        typedef EventQueue::context10<F, A0> C;
+        void *p = equeue_alloc(e->equeue, sizeof(C));
+        if (!p) {
+            return 0;
+        }
+
+        new (p) C(*(F*)(e + 1), a0);
+        equeue_event_delay(p, e->delay);
+        equeue_event_period(p, e->period);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
+    }
+
+    template <typename F>
+    static void event_dtor(struct event *e) {
+        ((F*)(e + 1))->~F();
+    }
+
+public:
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0               Argument to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0>
+    Event(EventQueue *q, F f, C0 c0) {
+        new (this) Event(q, EventQueue::context11<F, C0, A0>(f, c0));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1            Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b1, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1>
+    Event(EventQueue *q, F f, C0 c0, C1 c1) {
+        new (this) Event(q, EventQueue::context21<F, C0, C1, A0>(f, c0, c1));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2         Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b2, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2) {
+        new (this) Event(q, EventQueue::context31<F, C0, C1, C2, A0>(f, c0, c1, c2));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3      Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b3, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3) {
+        new (this) Event(q, EventQueue::context41<F, C0, C1, C2, C3, A0>(f, c0, c1, c2, c3));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3,c4   Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b4, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+        new (this) Event(q, EventQueue::context51<F, C0, C1, C2, C3, C4, A0>(f, c0, c1, c2, c3, c4));
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, A0), B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, A0) const, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, A0) volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, A0) const volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, A0), B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, A0) const, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, A0) volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, A0) const volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, A0), B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, A0) const, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, A0) volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, A0) const volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, A0), B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, A0) const, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0) volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0) const volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0), B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) const, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) const volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+};
+
+/** Event
+ *
+ *  Representation of an event for fine-grain dispatch control
+ * @ingroup events
+ */
+template <typename A0, typename A1>
+class Event<void(A0, A1)> {
+public:
+    /** Create an event
+     *
+     *  Constructs an event bound to the specified event queue. The specified
+     *  callback acts as the target for the event and is executed in the
+     *  context of the event queue's dispatch loop once posted.
+     *
+     *  @param q        Event queue to dispatch on
+     *  @param f        Function to execute when the event is dispatched
+     */
+    template <typename F>
+    Event(EventQueue *q, F f) {
+        _event = static_cast<struct event *>(
+                equeue_alloc(&q->_equeue, sizeof(struct event) + sizeof(F)));
+
+        if (_event) {
+            _event->equeue = &q->_equeue;
+            _event->id = 0;
+            _event->delay = 0;
+            _event->period = -1;
+
+            _event->post = &Event::event_post<F>;
+            _event->dtor = &Event::event_dtor<F>;
+
+            new (_event+1) F(f);
+
+            _event->ref = 1;
+        }
+    }
+
+    /** Copy constructor for events
+     */
+    Event(const Event &e) {
+        _event = 0;
+        if (e._event) {
+            _event = e._event;
+            _event->ref += 1;
+        }
+    }
+
+    /** Assignment operator for events
+     */
+    Event &operator=(const Event &that) {
+        if (this != &that) {
+            this->~Event();
+            new (this) Event(that);
+        }
+
+        return *this;
+    }
+
+    /** Destructor for events
+     */
+    ~Event() {
+        if (_event) {
+            _event->ref -= 1;
+            if (_event->ref == 0) {
+                _event->dtor(_event);
+                equeue_dealloc(_event->equeue, _event);
+            }
+        }
+    }
+
+    /** Configure the delay of an event
+     *
+     *  @param delay    Millisecond delay before dispatching the event
+     */
+    void delay(int delay) {
+        if (_event) {
+            _event->delay = delay;
+        }
+    }
+
+    /** Configure the period of an event
+     *
+     *  @param period   Millisecond period for repeatedly dispatching an event
+     */
+    void period(int period) {
+        if (_event) {
+            _event->period = period;
+        }
+    }
+
+    /** Posts an event onto the underlying event queue
+     *
+     *  The event is posted to the underlying queue and is executed in the
+     *  context of the event queue's dispatch loop.
+     *
+     *  The post function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @param a0,a1    Arguments to pass to the event
+     *  @return         A unique id that represents the posted event and can
+     *                  be passed to EventQueue::cancel, or an id of 0 if
+     *                  there is not enough memory to allocate the event.
+     */
+    int post(A0 a0, A1 a1) const {
+        if (!_event) {
+            return 0;
+        }
+
+        _event->id = _event->post(_event, a0, a1);
+        return _event->id;
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1    Arguments to pass to the event
+     */
+    void call(A0 a0, A1 a1) const {
+        MBED_UNUSED int id = post(a0, a1);
+        MBED_ASSERT(id);
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1    Arguments to pass to the event
+     */
+    void operator()(A0 a0, A1 a1) const {
+        return call(a0, a1);
+    }
+
+    /** Static thunk for passing as C-style function
+     *
+     *  @param func     Event to call passed as a void pointer
+     *  @param a0,a1    Arguments to pass to the event
+     */
+    static void thunk(void *func, A0 a0, A1 a1) {
+        return static_cast<Event*>(func)->call(a0, a1);
+    }
+
+    /** Cancels the most recently posted event
+     *
+     *  Attempts to cancel the most recently posted event. It is safe to call
+     *  cancel after an event has already been dispatched.
+     *
+     *  The cancel function is irq safe.
+     *
+     *  If called while the event queue's dispatch loop is active, the cancel
+     *  function does not garuntee that the event will not execute after it
+     *  returns, as the event may have already begun executing.
+     */
+    void cancel() const {
+        if (_event) {
+            equeue_cancel(_event->equeue, _event->id);
+        }
+    }
+
+private:
+    struct event {
+        unsigned ref;
+        equeue_t *equeue;
+        int id;
+
+        int delay;
+        int period;
+
+        int (*post)(struct event *, A0 a0, A1 a1);
+        void (*dtor)(struct event *);
+
+        // F follows
+    } *_event;
+
+    // Event attributes
+    template <typename F>
+    static int event_post(struct event *e, A0 a0, A1 a1) {
+        typedef EventQueue::context20<F, A0, A1> C;
+        void *p = equeue_alloc(e->equeue, sizeof(C));
+        if (!p) {
+            return 0;
+        }
+
+        new (p) C(*(F*)(e + 1), a0, a1);
+        equeue_event_delay(p, e->delay);
+        equeue_event_period(p, e->period);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
+    }
+
+    template <typename F>
+    static void event_dtor(struct event *e) {
+        ((F*)(e + 1))->~F();
+    }
+
+public:
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0               Argument to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0>
+    Event(EventQueue *q, F f, C0 c0) {
+        new (this) Event(q, EventQueue::context12<F, C0, A0, A1>(f, c0));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1            Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b1, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1>
+    Event(EventQueue *q, F f, C0 c0, C1 c1) {
+        new (this) Event(q, EventQueue::context22<F, C0, C1, A0, A1>(f, c0, c1));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2         Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b2, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2) {
+        new (this) Event(q, EventQueue::context32<F, C0, C1, C2, A0, A1>(f, c0, c1, c2));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3      Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b3, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3) {
+        new (this) Event(q, EventQueue::context42<F, C0, C1, C2, C3, A0, A1>(f, c0, c1, c2, c3));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3,c4   Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b4, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+        new (this) Event(q, EventQueue::context52<F, C0, C1, C2, C3, C4, A0, A1>(f, c0, c1, c2, c3, c4));
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, A0, A1), B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, A0, A1) const, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, A0, A1) volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, A0, A1) const volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, A0, A1), B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, A0, A1) const, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, A0, A1) volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, A0, A1) const volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, A0, A1), B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, A0, A1) const, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1) volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1) const volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1), B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) const, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) const volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1), B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) const, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) const volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+};
+
+/** Event
+ *
+ *  Representation of an event for fine-grain dispatch control
+ * @ingroup events
+ */
+template <typename A0, typename A1, typename A2>
+class Event<void(A0, A1, A2)> {
+public:
+    /** Create an event
+     *
+     *  Constructs an event bound to the specified event queue. The specified
+     *  callback acts as the target for the event and is executed in the
+     *  context of the event queue's dispatch loop once posted.
+     *
+     *  @param q        Event queue to dispatch on
+     *  @param f        Function to execute when the event is dispatched
+     */
+    template <typename F>
+    Event(EventQueue *q, F f) {
+        _event = static_cast<struct event *>(
+                equeue_alloc(&q->_equeue, sizeof(struct event) + sizeof(F)));
+
+        if (_event) {
+            _event->equeue = &q->_equeue;
+            _event->id = 0;
+            _event->delay = 0;
+            _event->period = -1;
+
+            _event->post = &Event::event_post<F>;
+            _event->dtor = &Event::event_dtor<F>;
+
+            new (_event+1) F(f);
+
+            _event->ref = 1;
+        }
+    }
+
+    /** Copy constructor for events
+     */
+    Event(const Event &e) {
+        _event = 0;
+        if (e._event) {
+            _event = e._event;
+            _event->ref += 1;
+        }
+    }
+
+    /** Assignment operator for events
+     */
+    Event &operator=(const Event &that) {
+        if (this != &that) {
+            this->~Event();
+            new (this) Event(that);
+        }
+
+        return *this;
+    }
+
+    /** Destructor for events
+     */
+    ~Event() {
+        if (_event) {
+            _event->ref -= 1;
+            if (_event->ref == 0) {
+                _event->dtor(_event);
+                equeue_dealloc(_event->equeue, _event);
+            }
+        }
+    }
+
+    /** Configure the delay of an event
+     *
+     *  @param delay    Millisecond delay before dispatching the event
+     */
+    void delay(int delay) {
+        if (_event) {
+            _event->delay = delay;
+        }
+    }
+
+    /** Configure the period of an event
+     *
+     *  @param period   Millisecond period for repeatedly dispatching an event
+     */
+    void period(int period) {
+        if (_event) {
+            _event->period = period;
+        }
+    }
+
+    /** Posts an event onto the underlying event queue
+     *
+     *  The event is posted to the underlying queue and is executed in the
+     *  context of the event queue's dispatch loop.
+     *
+     *  The post function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @param a0,a1,a2     Arguments to pass to the event
+     *  @return             A unique id that represents the posted event and can
+     *                      be passed to EventQueue::cancel, or an id of 0 if
+     *                      there is not enough memory to allocate the event.
+     */
+    int post(A0 a0, A1 a1, A2 a2) const {
+        if (!_event) {
+            return 0;
+        }
+
+        _event->id = _event->post(_event, a0, a1, a2);
+        return _event->id;
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1,a2     Arguments to pass to the event
+     */
+    void call(A0 a0, A1 a1, A2 a2) const {
+        MBED_UNUSED int id = post(a0, a1, a2);
+        MBED_ASSERT(id);
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1,a2     Arguments to pass to the event
+     */
+    void operator()(A0 a0, A1 a1, A2 a2) const {
+        return call(a0, a1, a2);
+    }
+
+    /** Static thunk for passing as C-style function
+     *
+     *  @param func         Event to call passed as a void pointer
+     *  @param a0,a1,a2     Arguments to pass to the event
+     */
+    static void thunk(void *func, A0 a0, A1 a1, A2 a2) {
+        return static_cast<Event*>(func)->call(a0, a1, a2);
+    }
+
+    /** Cancels the most recently posted event
+     *
+     *  Attempts to cancel the most recently posted event. It is safe to call
+     *  cancel after an event has already been dispatched.
+     *
+     *  The cancel function is irq safe.
+     *
+     *  If called while the event queue's dispatch loop is active, the cancel
+     *  function does not garuntee that the event will not execute after it
+     *  returns, as the event may have already begun executing.
+     */
+    void cancel() const {
+        if (_event) {
+            equeue_cancel(_event->equeue, _event->id);
+        }
+    }
+
+private:
+    struct event {
+        unsigned ref;
+        equeue_t *equeue;
+        int id;
+
+        int delay;
+        int period;
+
+        int (*post)(struct event *, A0 a0, A1 a1, A2 a2);
+        void (*dtor)(struct event *);
+
+        // F follows
+    } *_event;
+
+    // Event attributes
+    template <typename F>
+    static int event_post(struct event *e, A0 a0, A1 a1, A2 a2) {
+        typedef EventQueue::context30<F, A0, A1, A2> C;
+        void *p = equeue_alloc(e->equeue, sizeof(C));
+        if (!p) {
+            return 0;
+        }
+
+        new (p) C(*(F*)(e + 1), a0, a1, a2);
+        equeue_event_delay(p, e->delay);
+        equeue_event_period(p, e->period);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
+    }
+
+    template <typename F>
+    static void event_dtor(struct event *e) {
+        ((F*)(e + 1))->~F();
+    }
+
+public:
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0               Argument to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0>
+    Event(EventQueue *q, F f, C0 c0) {
+        new (this) Event(q, EventQueue::context13<F, C0, A0, A1, A2>(f, c0));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1            Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b1, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1>
+    Event(EventQueue *q, F f, C0 c0, C1 c1) {
+        new (this) Event(q, EventQueue::context23<F, C0, C1, A0, A1, A2>(f, c0, c1));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2         Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b2, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2) {
+        new (this) Event(q, EventQueue::context33<F, C0, C1, C2, A0, A1, A2>(f, c0, c1, c2));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3      Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b3, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3) {
+        new (this) Event(q, EventQueue::context43<F, C0, C1, C2, C3, A0, A1, A2>(f, c0, c1, c2, c3));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3,c4   Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b4, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+        new (this) Event(q, EventQueue::context53<F, C0, C1, C2, C3, C4, A0, A1, A2>(f, c0, c1, c2, c3, c4));
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, A0, A1, A2), B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, A0, A1, A2) const, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, A0, A1, A2) volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, A0, A1, A2) const volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, A0, A1, A2), B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, A0, A1, A2) const, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2) volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2) const volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2), B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) const, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) const volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2), B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) const, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) const volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2), B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) const, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) const volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+};
+
+/** Event
+ *
+ *  Representation of an event for fine-grain dispatch control
+ * @ingroup events
+ */
+template <typename A0, typename A1, typename A2, typename A3>
+class Event<void(A0, A1, A2, A3)> {
+public:
+    /** Create an event
+     *
+     *  Constructs an event bound to the specified event queue. The specified
+     *  callback acts as the target for the event and is executed in the
+     *  context of the event queue's dispatch loop once posted.
+     *
+     *  @param q        Event queue to dispatch on
+     *  @param f        Function to execute when the event is dispatched
+     */
+    template <typename F>
+    Event(EventQueue *q, F f) {
+        _event = static_cast<struct event *>(
+                equeue_alloc(&q->_equeue, sizeof(struct event) + sizeof(F)));
+
+        if (_event) {
+            _event->equeue = &q->_equeue;
+            _event->id = 0;
+            _event->delay = 0;
+            _event->period = -1;
+
+            _event->post = &Event::event_post<F>;
+            _event->dtor = &Event::event_dtor<F>;
+
+            new (_event+1) F(f);
+
+            _event->ref = 1;
+        }
+    }
+
+    /** Copy constructor for events
+     */
+    Event(const Event &e) {
+        _event = 0;
+        if (e._event) {
+            _event = e._event;
+            _event->ref += 1;
+        }
+    }
+
+    /** Assignment operator for events
+     */
+    Event &operator=(const Event &that) {
+        if (this != &that) {
+            this->~Event();
+            new (this) Event(that);
+        }
+
+        return *this;
+    }
+
+    /** Destructor for events
+     */
+    ~Event() {
+        if (_event) {
+            _event->ref -= 1;
+            if (_event->ref == 0) {
+                _event->dtor(_event);
+                equeue_dealloc(_event->equeue, _event);
+            }
+        }
+    }
+
+    /** Configure the delay of an event
+     *
+     *  @param delay    Millisecond delay before dispatching the event
+     */
+    void delay(int delay) {
+        if (_event) {
+            _event->delay = delay;
+        }
+    }
+
+    /** Configure the period of an event
+     *
+     *  @param period   Millisecond period for repeatedly dispatching an event
+     */
+    void period(int period) {
+        if (_event) {
+            _event->period = period;
+        }
+    }
+
+    /** Posts an event onto the underlying event queue
+     *
+     *  The event is posted to the underlying queue and is executed in the
+     *  context of the event queue's dispatch loop.
+     *
+     *  The post function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @param a0,a1,a2,a3   Arguments to pass to the event
+     *  @return              A unique id that represents the posted event and can
+     *                       be passed to EventQueue::cancel, or an id of 0 if
+     *                       there is not enough memory to allocate the event.
+     */
+    int post(A0 a0, A1 a1, A2 a2, A3 a3) const {
+        if (!_event) {
+            return 0;
+        }
+
+        _event->id = _event->post(_event, a0, a1, a2, a3);
+        return _event->id;
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1,a2,a3   Arguments to pass to the event
+     */
+    void call(A0 a0, A1 a1, A2 a2, A3 a3) const {
+        MBED_UNUSED int id = post(a0, a1, a2, a3);
+        MBED_ASSERT(id);
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1,a2,a3   Arguments to pass to the event
+     */
+    void operator()(A0 a0, A1 a1, A2 a2, A3 a3) const {
+        return call(a0, a1, a2, a3);
+    }
+
+    /** Static thunk for passing as C-style function
+     *
+     *  @param func          Event to call passed as a void pointer
+     *  @param a0,a1,a2,a3   Arguments to pass to the event
+     */
+    static void thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return static_cast<Event*>(func)->call(a0, a1, a2, a3);
+    }
+
+    /** Cancels the most recently posted event
+     *
+     *  Attempts to cancel the most recently posted event. It is safe to call
+     *  cancel after an event has already been dispatched.
+     *
+     *  The cancel function is irq safe.
+     *
+     *  If called while the event queue's dispatch loop is active, the cancel
+     *  function does not garuntee that the event will not execute after it
+     *  returns, as the event may have already begun executing.
+     */
+    void cancel() const {
+        if (_event) {
+            equeue_cancel(_event->equeue, _event->id);
+        }
+    }
+
+private:
+    struct event {
+        unsigned ref;
+        equeue_t *equeue;
+        int id;
+
+        int delay;
+        int period;
+
+        int (*post)(struct event *, A0 a0, A1 a1, A2 a2, A3 a3);
+        void (*dtor)(struct event *);
+
+        // F follows
+    } *_event;
+
+    // Event attributes
+    template <typename F>
+    static int event_post(struct event *e, A0 a0, A1 a1, A2 a2, A3 a3) {
+        typedef EventQueue::context40<F, A0, A1, A2, A3> C;
+        void *p = equeue_alloc(e->equeue, sizeof(C));
+        if (!p) {
+            return 0;
+        }
+
+        new (p) C(*(F*)(e + 1), a0, a1, a2, a3);
+        equeue_event_delay(p, e->delay);
+        equeue_event_period(p, e->period);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
+    }
+
+    template <typename F>
+    static void event_dtor(struct event *e) {
+        ((F*)(e + 1))->~F();
+    }
+
+public:
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0               Argument to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0>
+    Event(EventQueue *q, F f, C0 c0) {
+        new (this) Event(q, EventQueue::context14<F, C0, A0, A1, A2, A3>(f, c0));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1            Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b1, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1>
+    Event(EventQueue *q, F f, C0 c0, C1 c1) {
+        new (this) Event(q, EventQueue::context24<F, C0, C1, A0, A1, A2, A3>(f, c0, c1));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2         Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b2, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2) {
+        new (this) Event(q, EventQueue::context34<F, C0, C1, C2, A0, A1, A2, A3>(f, c0, c1, c2));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3      Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b3, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3) {
+        new (this) Event(q, EventQueue::context44<F, C0, C1, C2, C3, A0, A1, A2, A3>(f, c0, c1, c2, c3));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3,c4   Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b4, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+        new (this) Event(q, EventQueue::context54<F, C0, C1, C2, C3, C4, A0, A1, A2, A3>(f, c0, c1, c2, c3, c4));
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, A0, A1, A2, A3), B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, A0, A1, A2, A3) const, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3) volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3) const volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3), B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) const, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) const volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3), B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) const, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) const volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3), B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) const, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) const volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3), B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) const, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) const volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+};
+
+/** Event
+ *
+ *  Representation of an event for fine-grain dispatch control
+ * @ingroup events
+ */
+template <typename A0, typename A1, typename A2, typename A3, typename A4>
+class Event<void(A0, A1, A2, A3, A4)> {
+public:
+    /** Create an event
+     *
+     *  Constructs an event bound to the specified event queue. The specified
+     *  callback acts as the target for the event and is executed in the
+     *  context of the event queue's dispatch loop once posted.
+     *
+     *  @param q        Event queue to dispatch on
+     *  @param f        Function to execute when the event is dispatched
+     */
+    template <typename F>
+    Event(EventQueue *q, F f) {
+        _event = static_cast<struct event *>(
+                equeue_alloc(&q->_equeue, sizeof(struct event) + sizeof(F)));
+
+        if (_event) {
+            _event->equeue = &q->_equeue;
+            _event->id = 0;
+            _event->delay = 0;
+            _event->period = -1;
+
+            _event->post = &Event::event_post<F>;
+            _event->dtor = &Event::event_dtor<F>;
+
+            new (_event+1) F(f);
+
+            _event->ref = 1;
+        }
+    }
+
+    /** Copy constructor for events
+     */
+    Event(const Event &e) {
+        _event = 0;
+        if (e._event) {
+            _event = e._event;
+            _event->ref += 1;
+        }
+    }
+
+    /** Assignment operator for events
+     */
+    Event &operator=(const Event &that) {
+        if (this != &that) {
+            this->~Event();
+            new (this) Event(that);
+        }
+
+        return *this;
+    }
+
+    /** Destructor for events
+     */
+    ~Event() {
+        if (_event) {
+            _event->ref -= 1;
+            if (_event->ref == 0) {
+                _event->dtor(_event);
+                equeue_dealloc(_event->equeue, _event);
+            }
+        }
+    }
+
+    /** Configure the delay of an event
+     *
+     *  @param delay    Millisecond delay before dispatching the event
+     */
+    void delay(int delay) {
+        if (_event) {
+            _event->delay = delay;
+        }
+    }
+
+    /** Configure the period of an event
+     *
+     *  @param period   Millisecond period for repeatedly dispatching an event
+     */
+    void period(int period) {
+        if (_event) {
+            _event->period = period;
+        }
+    }
+
+    /** Posts an event onto the underlying event queue
+     *
+     *  The event is posted to the underlying queue and is executed in the
+     *  context of the event queue's dispatch loop.
+     *
+     *  The post function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @param a0,a1,a2,a3,a4   Arguments to pass to the event
+     *  @return                 A unique id that represents the posted event and can
+     *                          be passed to EventQueue::cancel, or an id of 0 if
+     *                          there is not enough memory to allocate the event.
+     */
+    int post(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+        if (!_event) {
+            return 0;
+        }
+
+        _event->id = _event->post(_event, a0, a1, a2, a3, a4);
+        return _event->id;
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1,a2,a3,a4   Arguments to pass to the event
+     */
+    void call(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+        MBED_UNUSED int id = post(a0, a1, a2, a3, a4);
+        MBED_ASSERT(id);
+    }
+
+    /** Posts an event onto the underlying event queue, returning void
+     *
+     *  @param a0,a1,a2,a3,a4   Arguments to pass to the event
+     */
+    void operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+        return call(a0, a1, a2, a3, a4);
+    }
+
+    /** Static thunk for passing as C-style function
+     *
+     *  @param func             Event to call passed as a void pointer
+     *  @param a0,a1,a2,a3,a4   Arguments to pass to the event
+     */
+    static void thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return static_cast<Event*>(func)->call(a0, a1, a2, a3, a4);
+    }
+
+    /** Cancels the most recently posted event
+     *
+     *  Attempts to cancel the most recently posted event. It is safe to call
+     *  cancel after an event has already been dispatched.
+     *
+     *  The cancel function is irq safe.
+     *
+     *  If called while the event queue's dispatch loop is active, the cancel
+     *  function does not garuntee that the event will not execute after it
+     *  returns, as the event may have already begun executing.
+     */
+    void cancel() const {
+        if (_event) {
+            equeue_cancel(_event->equeue, _event->id);
+        }
+    }
+
+private:
+    struct event {
+        unsigned ref;
+        equeue_t *equeue;
+        int id;
+
+        int delay;
+        int period;
+
+        int (*post)(struct event *, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4);
+        void (*dtor)(struct event *);
+
+        // F follows
+    } *_event;
+
+    // Event attributes
+    template <typename F>
+    static int event_post(struct event *e, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        typedef EventQueue::context50<F, A0, A1, A2, A3, A4> C;
+        void *p = equeue_alloc(e->equeue, sizeof(C));
+        if (!p) {
+            return 0;
+        }
+
+        new (p) C(*(F*)(e + 1), a0, a1, a2, a3, a4);
+        equeue_event_delay(p, e->delay);
+        equeue_event_period(p, e->period);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
+    }
+
+    template <typename F>
+    static void event_dtor(struct event *e) {
+        ((F*)(e + 1))->~F();
+    }
+
+public:
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0               Argument to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0>
+    Event(EventQueue *q, F f, C0 c0) {
+        new (this) Event(q, EventQueue::context15<F, C0, A0, A1, A2, A3, A4>(f, c0));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1            Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b1, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1>
+    Event(EventQueue *q, F f, C0 c0, C1 c1) {
+        new (this) Event(q, EventQueue::context25<F, C0, C1, A0, A1, A2, A3, A4>(f, c0, c1));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2         Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b2, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2) {
+        new (this) Event(q, EventQueue::context35<F, C0, C1, C2, A0, A1, A2, A3, A4>(f, c0, c1, c2));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3      Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b3, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3) {
+        new (this) Event(q, EventQueue::context45<F, C0, C1, C2, C3, A0, A1, A2, A3, A4>(f, c0, c1, c2, c3));
+    }
+
+    /** Create an event
+     *  @param q                Event queue to dispatch on
+     *  @param f                Function to execute when the event is dispatched
+     *  @param c0,c1,c2,c3,c4   Arguments to bind to the callback, these arguments are
+     *                          allocated on an irq-safe allocator from the event queue's
+     *                          memory pool. Must be type-compatible with b0..b4, the
+     *                          arguments to the underlying callback.
+     */
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event(EventQueue *q, F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+        new (this) Event(q, EventQueue::context55<F, C0, C1, C2, C3, C4, A0, A1, A2, A3, A4>(f, c0, c1, c2, c3, c4));
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4), B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) const, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) const volatile, B0 b0) {
+        new (this) Event(q, mbed::callback(obj, method), b0);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4), B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) const, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) const volatile, B0 b0, B1 b1) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4), B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) const, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) const volatile, B0 b0, B1 b1, B2 b2) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4), B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) const, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) const volatile, B0 b0, B1 b1, B2 b2, B3 b3) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4), B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) const, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+
+    /** Create an event
+     *  @see Event::Event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4>
+    Event(EventQueue *q, const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) const volatile, B0 b0, B1 b1, B2 b2, B3 b3, B4 b4) {
+        new (this) Event(q, mbed::callback(obj, method), b0, b1, b2, b3, b4);
+    }
+};
+
+
+/** \addtogroup events */
+/** @{ */
+
+// Convenience functions declared here to avoid cyclic
+// dependency between Event and EventQueue
+template <typename R>
+Event<void()> EventQueue::event(R (*func)()) {
+    return Event<void()>(this, func);
+}
+
+template <typename T, typename R>
+Event<void()> EventQueue::event(T *obj, R (T::*method)()) {
+    return Event<void()>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R>
+Event<void()> EventQueue::event(const T *obj, R (T::*method)() const) {
+    return Event<void()>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R>
+Event<void()> EventQueue::event(volatile T *obj, R (T::*method)() volatile) {
+    return Event<void()>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R>
+Event<void()> EventQueue::event(const volatile T *obj, R (T::*method)() const volatile) {
+    return Event<void()>(this, mbed::callback(obj, method));
+}
+
+template <typename R>
+Event<void()> EventQueue::event(mbed::Callback<R()> cb) {
+    return Event<void()>(this, cb);
+}
+
+template <typename R, typename B0, typename C0>
+Event<void()> EventQueue::event(R (*func)(B0), C0 c0) {
+    return Event<void()>(this, func, c0);
+}
+
+template <typename T, typename R, typename B0, typename C0>
+Event<void()> EventQueue::event(T *obj, R (T::*method)(B0), C0 c0) {
+    return Event<void()>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0>
+Event<void()> EventQueue::event(const T *obj, R (T::*method)(B0) const, C0 c0) {
+    return Event<void()>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0>
+Event<void()> EventQueue::event(volatile T *obj, R (T::*method)(B0) volatile, C0 c0) {
+    return Event<void()>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0>
+Event<void()> EventQueue::event(const volatile T *obj, R (T::*method)(B0) const volatile, C0 c0) {
+    return Event<void()>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename R, typename B0, typename C0>
+Event<void()> EventQueue::event(mbed::Callback<R(B0)> cb, C0 c0) {
+    return Event<void()>(this, cb, c0);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1>
+Event<void()> EventQueue::event(R (*func)(B0, B1), C0 c0, C1 c1) {
+    return Event<void()>(this, func, c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+Event<void()> EventQueue::event(T *obj, R (T::*method)(B0, B1), C0 c0, C1 c1) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+Event<void()> EventQueue::event(const T *obj, R (T::*method)(B0, B1) const, C0 c0, C1 c1) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+Event<void()> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1) volatile, C0 c0, C1 c1) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+Event<void()> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1) const volatile, C0 c0, C1 c1) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1>
+Event<void()> EventQueue::event(mbed::Callback<R(B0, B1)> cb, C0 c0, C1 c1) {
+    return Event<void()>(this, cb, c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+Event<void()> EventQueue::event(R (*func)(B0, B1, B2), C0 c0, C1 c1, C2 c2) {
+    return Event<void()>(this, func, c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+Event<void()> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2), C0 c0, C1 c1, C2 c2) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+Event<void()> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2) const, C0 c0, C1 c1, C2 c2) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+Event<void()> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2) volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+Event<void()> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2) const volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+Event<void()> EventQueue::event(mbed::Callback<R(B0, B1, B2)> cb, C0 c0, C1 c1, C2 c2) {
+    return Event<void()>(this, cb, c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+Event<void()> EventQueue::event(R (*func)(B0, B1, B2, B3), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void()>(this, func, c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+Event<void()> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+Event<void()> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3) const, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+Event<void()> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3) volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+Event<void()> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3) const volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+Event<void()> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3)> cb, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void()>(this, cb, c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+Event<void()> EventQueue::event(R (*func)(B0, B1, B2, B3, B4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void()>(this, func, c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+Event<void()> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, B4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+Event<void()> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+Event<void()> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+Event<void()> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void()>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+Event<void()> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, B4)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void()>(this, cb, c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename A0>
+Event<void(A0)> EventQueue::event(R (*func)(A0)) {
+    return Event<void(A0)>(this, func);
+}
+
+template <typename T, typename R, typename A0>
+Event<void(A0)> EventQueue::event(T *obj, R (T::*method)(A0)) {
+    return Event<void(A0)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0>
+Event<void(A0)> EventQueue::event(const T *obj, R (T::*method)(A0) const) {
+    return Event<void(A0)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0>
+Event<void(A0)> EventQueue::event(volatile T *obj, R (T::*method)(A0) volatile) {
+    return Event<void(A0)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0>
+Event<void(A0)> EventQueue::event(const volatile T *obj, R (T::*method)(A0) const volatile) {
+    return Event<void(A0)>(this, mbed::callback(obj, method));
+}
+
+template <typename R, typename A0>
+Event<void(A0)> EventQueue::event(mbed::Callback<R(A0)> cb) {
+    return Event<void(A0)>(this, cb);
+}
+
+template <typename R, typename B0, typename C0, typename A0>
+Event<void(A0)> EventQueue::event(R (*func)(B0, A0), C0 c0) {
+    return Event<void(A0)>(this, func, c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0>
+Event<void(A0)> EventQueue::event(T *obj, R (T::*method)(B0, A0), C0 c0) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0>
+Event<void(A0)> EventQueue::event(const T *obj, R (T::*method)(B0, A0) const, C0 c0) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0>
+Event<void(A0)> EventQueue::event(volatile T *obj, R (T::*method)(B0, A0) volatile, C0 c0) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0>
+Event<void(A0)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, A0) const volatile, C0 c0) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename R, typename B0, typename C0, typename A0>
+Event<void(A0)> EventQueue::event(mbed::Callback<R(B0, A0)> cb, C0 c0) {
+    return Event<void(A0)>(this, cb, c0);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+Event<void(A0)> EventQueue::event(R (*func)(B0, B1, A0), C0 c0, C1 c1) {
+    return Event<void(A0)>(this, func, c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+Event<void(A0)> EventQueue::event(T *obj, R (T::*method)(B0, B1, A0), C0 c0, C1 c1) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+Event<void(A0)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, A0) const, C0 c0, C1 c1) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+Event<void(A0)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, A0) volatile, C0 c0, C1 c1) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+Event<void(A0)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, A0) const volatile, C0 c0, C1 c1) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+Event<void(A0)> EventQueue::event(mbed::Callback<R(B0, B1, A0)> cb, C0 c0, C1 c1) {
+    return Event<void(A0)>(this, cb, c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+Event<void(A0)> EventQueue::event(R (*func)(B0, B1, B2, A0), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0)>(this, func, c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+Event<void(A0)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, A0), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+Event<void(A0)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, A0) const, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+Event<void(A0)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, A0) volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+Event<void(A0)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0) const volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+Event<void(A0)> EventQueue::event(mbed::Callback<R(B0, B1, B2, A0)> cb, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0)>(this, cb, c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+Event<void(A0)> EventQueue::event(R (*func)(B0, B1, B2, B3, A0), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0)>(this, func, c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+Event<void(A0)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, A0), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+Event<void(A0)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0) const, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+Event<void(A0)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0) volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+Event<void(A0)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0) const volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+Event<void(A0)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, A0)> cb, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0)>(this, cb, c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+Event<void(A0)> EventQueue::event(R (*func)(B0, B1, B2, B3, B4, A0), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0)>(this, func, c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+Event<void(A0)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+Event<void(A0)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+Event<void(A0)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+Event<void(A0)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+Event<void(A0)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, B4, A0)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0)>(this, cb, c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(R (*func)(A0, A1)) {
+    return Event<void(A0, A1)>(this, func);
+}
+
+template <typename T, typename R, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(T *obj, R (T::*method)(A0, A1)) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const T *obj, R (T::*method)(A0, A1) const) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(volatile T *obj, R (T::*method)(A0, A1) volatile) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const volatile T *obj, R (T::*method)(A0, A1) const volatile) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method));
+}
+
+template <typename R, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(mbed::Callback<R(A0, A1)> cb) {
+    return Event<void(A0, A1)>(this, cb);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(R (*func)(B0, A0, A1), C0 c0) {
+    return Event<void(A0, A1)>(this, func, c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(T *obj, R (T::*method)(B0, A0, A1), C0 c0) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const T *obj, R (T::*method)(B0, A0, A1) const, C0 c0) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(volatile T *obj, R (T::*method)(B0, A0, A1) volatile, C0 c0) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, A0, A1) const volatile, C0 c0) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(mbed::Callback<R(B0, A0, A1)> cb, C0 c0) {
+    return Event<void(A0, A1)>(this, cb, c0);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(R (*func)(B0, B1, A0, A1), C0 c0, C1 c1) {
+    return Event<void(A0, A1)>(this, func, c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(T *obj, R (T::*method)(B0, B1, A0, A1), C0 c0, C1 c1) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, A0, A1) const, C0 c0, C1 c1) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, A0, A1) volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1) const volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(mbed::Callback<R(B0, B1, A0, A1)> cb, C0 c0, C1 c1) {
+    return Event<void(A0, A1)>(this, cb, c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(R (*func)(B0, B1, B2, A0, A1), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1)>(this, func, c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, A0, A1), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1) const, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1) volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1) const volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(mbed::Callback<R(B0, B1, B2, A0, A1)> cb, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1)>(this, cb, c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(R (*func)(B0, B1, B2, B3, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1)>(this, func, c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) const, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) const volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, A0, A1)> cb, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1)>(this, cb, c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(R (*func)(B0, B1, B2, B3, B4, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1)>(this, func, c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+Event<void(A0, A1)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1)>(this, cb, c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(R (*func)(A0, A1, A2)) {
+    return Event<void(A0, A1, A2)>(this, func);
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(T *obj, R (T::*method)(A0, A1, A2)) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const T *obj, R (T::*method)(A0, A1, A2) const) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(volatile T *obj, R (T::*method)(A0, A1, A2) volatile) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const volatile T *obj, R (T::*method)(A0, A1, A2) const volatile) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method));
+}
+
+template <typename R, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(mbed::Callback<R(A0, A1, A2)> cb) {
+    return Event<void(A0, A1, A2)>(this, cb);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(R (*func)(B0, A0, A1, A2), C0 c0) {
+    return Event<void(A0, A1, A2)>(this, func, c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(T *obj, R (T::*method)(B0, A0, A1, A2), C0 c0) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const T *obj, R (T::*method)(B0, A0, A1, A2) const, C0 c0) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(volatile T *obj, R (T::*method)(B0, A0, A1, A2) volatile, C0 c0) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, A0, A1, A2) const volatile, C0 c0) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(mbed::Callback<R(B0, A0, A1, A2)> cb, C0 c0) {
+    return Event<void(A0, A1, A2)>(this, cb, c0);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(R (*func)(B0, B1, A0, A1, A2), C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2)>(this, func, c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(T *obj, R (T::*method)(B0, B1, A0, A1, A2), C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, A0, A1, A2) const, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2) volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2) const volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(mbed::Callback<R(B0, B1, A0, A1, A2)> cb, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2)>(this, cb, c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(R (*func)(B0, B1, B2, A0, A1, A2), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2)>(this, func, c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) const, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) const volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(mbed::Callback<R(B0, B1, B2, A0, A1, A2)> cb, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2)>(this, cb, c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(R (*func)(B0, B1, B2, B3, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2)>(this, func, c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) const, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) const volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, A0, A1, A2)> cb, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2)>(this, cb, c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(R (*func)(B0, B1, B2, B3, B4, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2)>(this, func, c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+Event<void(A0, A1, A2)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1, A2)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2)>(this, cb, c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(R (*func)(A0, A1, A2, A3)) {
+    return Event<void(A0, A1, A2, A3)>(this, func);
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(T *obj, R (T::*method)(A0, A1, A2, A3)) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const T *obj, R (T::*method)(A0, A1, A2, A3) const) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(volatile T *obj, R (T::*method)(A0, A1, A2, A3) volatile) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const volatile T *obj, R (T::*method)(A0, A1, A2, A3) const volatile) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method));
+}
+
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(mbed::Callback<R(A0, A1, A2, A3)> cb) {
+    return Event<void(A0, A1, A2, A3)>(this, cb);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(R (*func)(B0, A0, A1, A2, A3), C0 c0) {
+    return Event<void(A0, A1, A2, A3)>(this, func, c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(T *obj, R (T::*method)(B0, A0, A1, A2, A3), C0 c0) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const T *obj, R (T::*method)(B0, A0, A1, A2, A3) const, C0 c0) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3) volatile, C0 c0) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3) const volatile, C0 c0) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(mbed::Callback<R(B0, A0, A1, A2, A3)> cb, C0 c0) {
+    return Event<void(A0, A1, A2, A3)>(this, cb, c0);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(R (*func)(B0, B1, A0, A1, A2, A3), C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3)>(this, func, c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3), C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) const, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) const volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(mbed::Callback<R(B0, B1, A0, A1, A2, A3)> cb, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3)>(this, cb, c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(R (*func)(B0, B1, B2, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3)>(this, func, c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) const, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) const volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(mbed::Callback<R(B0, B1, B2, A0, A1, A2, A3)> cb, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3)>(this, cb, c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(R (*func)(B0, B1, B2, B3, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3)>(this, func, c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) const, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) const volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, A0, A1, A2, A3)> cb, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3)>(this, cb, c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(R (*func)(B0, B1, B2, B3, B4, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3)>(this, func, c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+Event<void(A0, A1, A2, A3)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1, A2, A3)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3)>(this, cb, c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(R (*func)(A0, A1, A2, A3, A4)) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, func);
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(T *obj, R (T::*method)(A0, A1, A2, A3, A4)) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const T *obj, R (T::*method)(A0, A1, A2, A3, A4) const) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method));
+}
+
+template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method));
+}
+
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(mbed::Callback<R(A0, A1, A2, A3, A4)> cb) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, cb);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(R (*func)(B0, A0, A1, A2, A3, A4), C0 c0) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, func, c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4), C0 c0) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) const, C0 c0) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) volatile, C0 c0) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) const volatile, C0 c0) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0);
+}
+
+template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(mbed::Callback<R(B0, A0, A1, A2, A3, A4)> cb, C0 c0) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, cb, c0);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(R (*func)(B0, B1, A0, A1, A2, A3, A4), C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, func, c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4), C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) const, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(mbed::Callback<R(B0, B1, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, cb, c0, c1);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(R (*func)(B0, B1, B2, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, func, c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) const, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(mbed::Callback<R(B0, B1, B2, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1, C2 c2) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, cb, c0, c1, c2);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(R (*func)(B0, B1, B2, B3, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, func, c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) const, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1, C2 c2, C3 c3) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, cb, c0, c1, c2, c3);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(R (*func)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, func, c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, mbed::callback(obj, method), c0, c1, c2, c3, c4);
+}
+
+template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+Event<void(A0, A1, A2, A3, A4)> EventQueue::event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4) {
+    return Event<void(A0, A1, A2, A3, A4)>(this, cb, c0, c1, c2, c3, c4);
+}
+
+}
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/EventQueue.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/EventQueue.cpp
new file mode 100755
index 0000000..420f31b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/EventQueue.cpp
@@ -0,0 +1,66 @@
+/* events
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "events/EventQueue.h"
+
+#include "events/mbed_events.h"
+#include "mbed.h"
+
+
+EventQueue::EventQueue(unsigned event_size, unsigned char *event_pointer) {
+    if (!event_pointer) {
+        equeue_create(&_equeue, event_size);
+    } else {
+        equeue_create_inplace(&_equeue, event_size, event_pointer);
+    }
+}
+
+EventQueue::~EventQueue() {
+    equeue_destroy(&_equeue);
+}
+
+void EventQueue::dispatch(int ms) {
+    return equeue_dispatch(&_equeue, ms);
+}
+
+void EventQueue::break_dispatch() {
+    return equeue_break(&_equeue);
+}
+
+unsigned EventQueue::tick() {
+    return equeue_tick();
+}
+
+void EventQueue::cancel(int id) {
+    return equeue_cancel(&_equeue, id);
+}
+
+void EventQueue::background(Callback<void(int)> update) {
+    _update = update;
+
+    if (_update) {
+        equeue_background(&_equeue, &Callback<void(int)>::thunk, &_update);
+    } else {
+        equeue_background(&_equeue, 0, 0);
+    }
+}
+
+void EventQueue::chain(EventQueue *target) {
+    if (target) {
+        equeue_chain(&_equeue, &target->_equeue);
+    } else {
+        equeue_chain(&_equeue, 0);
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/EventQueue.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/EventQueue.h
new file mode 100755
index 0000000..9b15edb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/EventQueue.h
@@ -0,0 +1,2734 @@
+/* events
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef EVENT_QUEUE_H
+#define EVENT_QUEUE_H
+
+#include "equeue/equeue.h"
+#include "platform/Callback.h"
+#include "platform/NonCopyable.h"
+#include <cstddef>
+#include <new>
+
+namespace events {
+/** \addtogroup events */
+
+/** EVENTS_EVENT_SIZE
+ *  Minimum size of an event
+ *  This size fits a Callback<void()> at minimum
+ */
+#define EVENTS_EVENT_SIZE \
+    (EQUEUE_EVENT_SIZE - 2*sizeof(void*) + sizeof(mbed::Callback<void()>))
+
+/** EVENTS_QUEUE_SIZE
+ *  Default size of buffer for events
+ */
+#define EVENTS_QUEUE_SIZE (32*EVENTS_EVENT_SIZE)
+
+// Predeclared classes
+template <typename F>
+class Event;
+
+
+/** EventQueue
+ *
+ *  Flexible event queue for dispatching events
+ * @ingroup events
+ */
+class EventQueue : private mbed::NonCopyable<EventQueue> {
+public:
+    /** Create an EventQueue
+     *
+     *  Create an event queue. The event queue either allocates a buffer of
+     *  the specified size with malloc or uses the user provided buffer.
+     *
+     *  @param size     Size of buffer to use for events in bytes
+     *                  (default to EVENTS_QUEUE_SIZE)
+     *  @param buffer   Pointer to buffer to use for events
+     *                  (default to NULL)
+     */
+    EventQueue(unsigned size=EVENTS_QUEUE_SIZE, unsigned char *buffer=NULL);
+
+    /** Destroy an EventQueue
+     */
+    ~EventQueue();
+
+    /** Dispatch events
+     *
+     *  Executes events until the specified milliseconds have passed.
+     *  If ms is negative, the dispatch function will dispatch events
+     *  indefinitely or until break_dispatch is called on this queue.
+     *
+     *  When called with a finite timeout, the dispatch function is guaranteed
+     *  to terminate. When called with a timeout of 0, the dispatch function
+     *  does not wait and is irq safe.
+     *
+     *  @param ms       Time to wait for events in milliseconds, a negative
+     *                  value will dispatch events indefinitely
+     *                  (default to -1)
+     */
+    void dispatch(int ms=-1);
+
+    /** Dispatch events without a timeout
+     *
+     *  This is equivalent to EventQueue::dispatch with no arguments, but 
+     *  avoids overload ambiguities when passed as a callback.
+     *
+     *  @see EventQueue::dispatch
+     */
+    void dispatch_forever() { dispatch(); }
+
+    /** Break out of a running event loop
+     *
+     *  Forces the specified event queue's dispatch loop to terminate. Pending
+     *  events may finish executing, but no new events will be executed.
+     */
+    void break_dispatch();
+
+    /** Millisecond counter
+     *
+     *  Returns the underlying tick of the event queue represented as the 
+     *  number of milliseconds that have passed since an arbitrary point in
+     *  time. Intentionally overflows to 0 after 2^32-1.
+     *
+     *  @return         The underlying tick of the event queue in milliseconds
+     */
+    unsigned tick();
+
+    /** Cancel an in-flight event
+     *
+     *  Attempts to cancel an event referenced by the unique id returned from
+     *  one of the call functions. It is safe to call cancel after an event
+     *  has already been dispatched.
+     *
+     *  The cancel function is irq safe.
+     *
+     *  If called while the event queue's dispatch loop is active, the cancel
+     *  function does not garuntee that the event will not execute after it
+     *  returns, as the event may have already begun executing.
+     *
+     *  @param id       Unique id of the event
+     */
+    void cancel(int id);
+
+    /** Background an event queue onto a single-shot timer-interrupt
+     *
+     *  When updated, the event queue will call the provided update function
+     *  with a timeout indicating when the queue should be dispatched. A
+     *  negative timeout will be passed to the update function when the
+     *  timer-interrupt is no longer needed.
+     *
+     *  Passing a null function disables the existing update function.
+     *
+     *  The background function allows an event queue to take advantage of
+     *  hardware timers or other event loops, allowing an event queue to be
+     *  ran in the background without consuming the foreground thread.
+     *
+     *  @param update   Function called to indicate when the queue should be
+     *                  dispatched
+     */
+    void background(mbed::Callback<void(int)> update);
+
+    /** Chain an event queue onto another event queue
+     *
+     *  After chaining a queue to a target, calling dispatch on the target
+     *  queue will also dispatch events from this queue. The queues use
+     *  their own buffers and events must be handled independently.
+     *
+     *  A null queue as the target will unchain the existing queue.
+     *
+     *  The chain function allows multiple event queues to be composed,
+     *  sharing the context of a dispatch loop while still being managed
+     *  independently
+     *
+     *  @param target   Queue that will dispatch this queue's events as a
+     *                  part of its dispatch loop
+     */
+    void chain(EventQueue *target);
+
+    /** Calls an event on the queue
+     *
+     *  The specified callback will be executed in the context of the event
+     *  queue's dispatch loop.
+     *
+     *  The call function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @param f        Function to execute in the context of the dispatch loop
+     *  @return         A unique id that represents the posted event and can
+     *                  be passed to cancel, or an id of 0 if there is not
+     *                  enough memory to allocate the event.
+     */
+    template <typename F>
+    int call(F f) {
+        void *p = equeue_alloc(&_equeue, sizeof(F));
+        if (!p) {
+            return 0;
+        }
+
+        F *e = new (p) F(f);
+        equeue_event_dtor(e, &EventQueue::function_dtor<F>);
+        return equeue_post(&_equeue, &EventQueue::function_call<F>, e);
+    }
+
+    /** Calls an event on the queue
+     *  @see                    EventQueue::call
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0               Argument to pass to the callback
+     */
+    template <typename F, typename A0>
+    int call(F f, A0 a0) {
+        return call(context10<F, A0>(f, a0));
+    }
+
+    /** Calls an event on the queue
+     *  @see                    EventQueue::call
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0,a1            Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1>
+    int call(F f, A0 a0, A1 a1) {
+        return call(context20<F, A0, A1>(f, a0, a1));
+    }
+
+    /** Calls an event on the queue
+     *  @see                    EventQueue::call
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2         Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1, typename A2>
+    int call(F f, A0 a0, A1 a1, A2 a2) {
+        return call(context30<F, A0, A1, A2>(f, a0, a1, a2));
+    }
+
+    /** Calls an event on the queue
+     *  @see                     EventQueue::call
+     *  @param f                 Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2,a3       Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1, typename A2, typename A3>
+    int call(F f, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call(context40<F, A0, A1, A2, A3>(f, a0, a1, a2, a3));
+    }
+
+    /** Calls an event on the queue
+     *  @see                    EventQueue::call
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2,a3,a4   Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call(F f, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call(context50<F, A0, A1, A2, A3, A4>(f, a0, a1, a2, a3, a4));
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R>
+    int call(T *obj, R (T::*method)()) {
+        return call(mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R>
+    int call(const T *obj, R (T::*method)() const) {
+        return call(mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R>
+    int call(volatile T *obj, R (T::*method)() volatile) {
+        return call(mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R>
+    int call(const volatile T *obj, R (T::*method)() const volatile) {
+        return call(mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0>
+    int call(T *obj, R (T::*method)(A0), A0 a0) {
+        return call(mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0>
+    int call(const T *obj, R (T::*method)(A0) const, A0 a0) {
+        return call(mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0>
+    int call(volatile T *obj, R (T::*method)(A0) volatile, A0 a0) {
+        return call(mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0>
+    int call(const volatile T *obj, R (T::*method)(A0) const volatile, A0 a0) {
+        return call(mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call(T *obj, R (T::*method)(A0, A1), A0 a0, A1 a1) {
+        return call(mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call(const T *obj, R (T::*method)(A0, A1) const, A0 a0, A1 a1) {
+        return call(mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call(volatile T *obj, R (T::*method)(A0, A1) volatile, A0 a0, A1 a1) {
+        return call(mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call(const volatile T *obj, R (T::*method)(A0, A1) const volatile, A0 a0, A1 a1) {
+        return call(mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call(T *obj, R (T::*method)(A0, A1, A2), A0 a0, A1 a1, A2 a2) {
+        return call(mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call(const T *obj, R (T::*method)(A0, A1, A2) const, A0 a0, A1 a1, A2 a2) {
+        return call(mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call(volatile T *obj, R (T::*method)(A0, A1, A2) volatile, A0 a0, A1 a1, A2 a2) {
+        return call(mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call(const volatile T *obj, R (T::*method)(A0, A1, A2) const volatile, A0 a0, A1 a1, A2 a2) {
+        return call(mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call(T *obj, R (T::*method)(A0, A1, A2, A3), A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call(const T *obj, R (T::*method)(A0, A1, A2, A3) const, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call(volatile T *obj, R (T::*method)(A0, A1, A2, A3) volatile, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call(const volatile T *obj, R (T::*method)(A0, A1, A2, A3) const volatile, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call(T *obj, R (T::*method)(A0, A1, A2, A3, A4), A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call(const T *obj, R (T::*method)(A0, A1, A2, A3, A4) const, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call(volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue
+     *  @see EventQueue::call
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call(const volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call(mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *
+     *  The specified callback will be executed in the context of the event
+     *  queue's dispatch loop.
+     *
+     *  The call_in function is irq safe and can act as a mechanism for moving
+     *  events out of irq contexts.
+     *
+     *  @param f        Function to execute in the context of the dispatch loop
+     *  @param ms       Time to delay in milliseconds
+     *  @return         A unique id that represents the posted event and can
+     *                  be passed to cancel, or an id of 0 if there is not
+     *                  enough memory to allocate the event.
+     */
+    template <typename F>
+    int call_in(int ms, F f) {
+        void *p = equeue_alloc(&_equeue, sizeof(F));
+        if (!p) {
+            return 0;
+        }
+
+        F *e = new (p) F(f);
+        equeue_event_delay(e, ms);
+        equeue_event_dtor(e, &EventQueue::function_dtor<F>);
+        return equeue_post(&_equeue, &EventQueue::function_call<F>, e);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see                        EventQueue::call_in
+     *  @param ms                   Time to delay in milliseconds
+     *  @param f                    Function to execute in the context of the dispatch loop
+     *  @param a0                   Argument to pass to the callback
+     */
+    template <typename F, typename A0>
+    int call_in(int ms, F f, A0 a0) {
+        return call_in(ms, context10<F, A0>(f, a0));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see                        EventQueue::call_in
+     *  @param ms                   Time to delay in milliseconds
+     *  @param f                    Function to execute in the context of the dispatch loop
+     *  @param a0,a1                Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1>
+    int call_in(int ms, F f, A0 a0, A1 a1) {
+        return call_in(ms, context20<F, A0, A1>(f, a0, a1));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see                        EventQueue::call_in
+     *  @param ms                   Time to delay in milliseconds
+     *  @param f                    Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2             Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1, typename A2>
+    int call_in(int ms, F f, A0 a0, A1 a1, A2 a2) {
+        return call_in(ms, context30<F, A0, A1, A2>(f, a0, a1, a2));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see                        EventQueue::call_in
+     *  @param ms                   Time to delay in milliseconds
+     *  @param f                    Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2,a3          Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1, typename A2, typename A3>
+    int call_in(int ms, F f, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_in(ms, context40<F, A0, A1, A2, A3>(f, a0, a1, a2, a3));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see                        EventQueue::call_in
+     *  @param ms                   Time to delay in milliseconds
+     *  @param f                    Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2,a3,a4       Arguments to pass to the callback
+     */
+    template <typename F, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_in(int ms, F f, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_in(ms, context50<F, A0, A1, A2, A3, A4>(f, a0, a1, a2, a3, a4));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R>
+    int call_in(int ms, T *obj, R (T::*method)()) {
+        return call_in(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R>
+    int call_in(int ms, const T *obj, R (T::*method)() const) {
+        return call_in(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R>
+    int call_in(int ms, volatile T *obj, R (T::*method)() volatile) {
+        return call_in(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R>
+    int call_in(int ms, const volatile T *obj, R (T::*method)() const volatile) {
+        return call_in(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0>
+    int call_in(int ms, T *obj, R (T::*method)(A0), A0 a0) {
+        return call_in(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0>
+    int call_in(int ms, const T *obj, R (T::*method)(A0) const, A0 a0) {
+        return call_in(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0>
+    int call_in(int ms, volatile T *obj, R (T::*method)(A0) volatile, A0 a0) {
+        return call_in(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0>
+    int call_in(int ms, const volatile T *obj, R (T::*method)(A0) const volatile, A0 a0) {
+        return call_in(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_in(int ms, T *obj, R (T::*method)(A0, A1), A0 a0, A1 a1) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_in(int ms, const T *obj, R (T::*method)(A0, A1) const, A0 a0, A1 a1) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_in(int ms, volatile T *obj, R (T::*method)(A0, A1) volatile, A0 a0, A1 a1) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_in(int ms, const volatile T *obj, R (T::*method)(A0, A1) const volatile, A0 a0, A1 a1) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_in(int ms, T *obj, R (T::*method)(A0, A1, A2), A0 a0, A1 a1, A2 a2) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_in(int ms, const T *obj, R (T::*method)(A0, A1, A2) const, A0 a0, A1 a1, A2 a2) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_in(int ms, volatile T *obj, R (T::*method)(A0, A1, A2) volatile, A0 a0, A1 a1, A2 a2) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_in(int ms, const volatile T *obj, R (T::*method)(A0, A1, A2) const volatile, A0 a0, A1 a1, A2 a2) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_in(int ms, T *obj, R (T::*method)(A0, A1, A2, A3), A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_in(int ms, const T *obj, R (T::*method)(A0, A1, A2, A3) const, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_in(int ms, volatile T *obj, R (T::*method)(A0, A1, A2, A3) volatile, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_in(int ms, const volatile T *obj, R (T::*method)(A0, A1, A2, A3) const volatile, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_in(int ms, T *obj, R (T::*method)(A0, A1, A2, A3, A4), A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_in(int ms, const T *obj, R (T::*method)(A0, A1, A2, A3, A4) const, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_in(int ms, volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue after a specified delay
+     *  @see EventQueue::call_in
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_in(int ms, const volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_in(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue periodically
+     *
+     *  The specified callback will be executed in the context of the event
+     *  queue's dispatch loop.
+     *
+     *  The call_every function is irq safe and can act as a mechanism for
+     *  moving events out of irq contexts.
+     *
+     *  @param f        Function to execute in the context of the dispatch loop
+     *  @param ms       Period of the event in milliseconds
+     *  @return         A unique id that represents the posted event and can
+     *                  be passed to cancel, or an id of 0 if there is not
+     *                  enough memory to allocate the event.
+     */
+    template <typename F>
+    int call_every(int ms, F f) {
+        void *p = equeue_alloc(&_equeue, sizeof(F));
+        if (!p) {
+            return 0;
+        }
+
+        F *e = new (p) F(f);
+        equeue_event_delay(e, ms);
+        equeue_event_period(e, ms);
+        equeue_event_dtor(e, &EventQueue::function_dtor<F>);
+        return equeue_post(&_equeue, &EventQueue::function_call<F>, e);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see                    EventQueue::call_every
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0               Argument to pass to the callback
+     *  @param ms               Period of the event in milliseconds
+     */
+    template <typename F, typename A0>
+    int call_every(int ms, F f, A0 a0) {
+        return call_every(ms, context10<F, A0>(f, a0));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see                    EventQueue::call_every
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0,a1            Arguments to pass to the callback
+     *  @param ms               Period of the event in milliseconds
+     */
+    template <typename F, typename A0, typename A1>
+    int call_every(int ms, F f, A0 a0, A1 a1) {
+        return call_every(ms, context20<F, A0, A1>(f, a0, a1));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see                    EventQueue::call_every
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2         Arguments to pass to the callback
+     *  @param ms               Period of the event in milliseconds
+     */
+    template <typename F, typename A0, typename A1, typename A2>
+    int call_every(int ms, F f, A0 a0, A1 a1, A2 a2) {
+        return call_every(ms, context30<F, A0, A1, A2>(f, a0, a1, a2));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see                    EventQueue::call_every
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2,a3      Arguments to pass to the callback
+     *  @param ms               Period of the event in milliseconds
+     */
+    template <typename F, typename A0, typename A1, typename A2, typename A3>
+    int call_every(int ms, F f, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_every(ms, context40<F, A0, A1, A2, A3>(f, a0, a1, a2, a3));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see                    EventQueue::call_every
+     *  @param f                Function to execute in the context of the dispatch loop
+     *  @param a0,a1,a2,a3,a4   Arguments to pass to the callback
+     *  @param ms               Period of the event in milliseconds
+     */
+    template <typename F, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_every(int ms, F f, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_every(ms, context50<F, A0, A1, A2, A3, A4>(f, a0, a1, a2, a3, a4));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R>
+    int call_every(int ms, T *obj, R (T::*method)()) {
+        return call_every(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R>
+    int call_every(int ms, const T *obj, R (T::*method)() const) {
+        return call_every(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R>
+    int call_every(int ms, volatile T *obj, R (T::*method)() volatile) {
+        return call_every(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R>
+    int call_every(int ms, const volatile T *obj, R (T::*method)() const volatile) {
+        return call_every(ms, mbed::callback(obj, method));
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0>
+    int call_every(int ms, T *obj, R (T::*method)(A0), A0 a0) {
+        return call_every(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0>
+    int call_every(int ms, const T *obj, R (T::*method)(A0) const, A0 a0) {
+        return call_every(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0>
+    int call_every(int ms, volatile T *obj, R (T::*method)(A0) volatile, A0 a0) {
+        return call_every(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0>
+    int call_every(int ms, const volatile T *obj, R (T::*method)(A0) const volatile, A0 a0) {
+        return call_every(ms, mbed::callback(obj, method), a0);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_every(int ms, T *obj, R (T::*method)(A0, A1), A0 a0, A1 a1) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_every(int ms, const T *obj, R (T::*method)(A0, A1) const, A0 a0, A1 a1) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_every(int ms, volatile T *obj, R (T::*method)(A0, A1) volatile, A0 a0, A1 a1) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    int call_every(int ms, const volatile T *obj, R (T::*method)(A0, A1) const volatile, A0 a0, A1 a1) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_every(int ms, T *obj, R (T::*method)(A0, A1, A2), A0 a0, A1 a1, A2 a2) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_every(int ms, const T *obj, R (T::*method)(A0, A1, A2) const, A0 a0, A1 a1, A2 a2) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_every(int ms, volatile T *obj, R (T::*method)(A0, A1, A2) volatile, A0 a0, A1 a1, A2 a2) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    int call_every(int ms, const volatile T *obj, R (T::*method)(A0, A1, A2) const volatile, A0 a0, A1 a1, A2 a2) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_every(int ms, T *obj, R (T::*method)(A0, A1, A2, A3), A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_every(int ms, const T *obj, R (T::*method)(A0, A1, A2, A3) const, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_every(int ms, volatile T *obj, R (T::*method)(A0, A1, A2, A3) volatile, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    int call_every(int ms, const volatile T *obj, R (T::*method)(A0, A1, A2, A3) const volatile, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_every(int ms, T *obj, R (T::*method)(A0, A1, A2, A3, A4), A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_every(int ms, const T *obj, R (T::*method)(A0, A1, A2, A3, A4) const, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_every(int ms, volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Calls an event on the queue periodically
+     *  @see EventQueue::call_every
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    int call_every(int ms, const volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call_every(ms, mbed::callback(obj, method), a0, a1, a2, a3, a4);
+    }
+
+    /** Creates an event bound to the event queue
+     *
+     *  Constructs an event bound to the specified event queue. The specified
+     *  callback acts as the target for the event and is executed in the
+     *  context of the event queue's dispatch loop once posted.
+     *
+     *  @param func        Function to execute when the event is dispatched
+     *  @return            Event that will dispatch on the specific queue
+     */
+    template <typename R>
+    Event<void()> event(R (*func)());
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R>
+    Event<void()> event(T *obj, R (T::*method)());
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R>
+    Event<void()> event(const T *obj, R (T::*method)() const);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R>
+    Event<void()> event(volatile T *obj, R (T::*method)() volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R>
+    Event<void()> event(const volatile T *obj, R (T::*method)() const volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R>
+    Event<void()> event(mbed::Callback<R()> cb);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0>
+    Event<void()> event(R (*func)(B0), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0>
+    Event<void()> event(T *obj, R (T::*method)(B0), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0>
+    Event<void()> event(const T *obj, R (T::*method)(B0) const, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0>
+    Event<void()> event(volatile T *obj, R (T::*method)(B0) volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0>
+    Event<void()> event(const volatile T *obj, R (T::*method)(B0) const volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0>
+    Event<void()> event(mbed::Callback<R(B0)> cb, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1>
+    Event<void()> event(R (*func)(B0, B1), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+    Event<void()> event(T *obj, R (T::*method)(B0, B1), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+    Event<void()> event(const T *obj, R (T::*method)(B0, B1) const, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+    Event<void()> event(volatile T *obj, R (T::*method)(B0, B1) volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1>
+    Event<void()> event(const volatile T *obj, R (T::*method)(B0, B1) const volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1>
+    Event<void()> event(mbed::Callback<R(B0, B1)> cb, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+    Event<void()> event(R (*func)(B0, B1, B2), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+    Event<void()> event(T *obj, R (T::*method)(B0, B1, B2), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+    Event<void()> event(const T *obj, R (T::*method)(B0, B1, B2) const, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+    Event<void()> event(volatile T *obj, R (T::*method)(B0, B1, B2) volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+    Event<void()> event(const volatile T *obj, R (T::*method)(B0, B1, B2) const volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2>
+    Event<void()> event(mbed::Callback<R(B0, B1, B2)> cb, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+    Event<void()> event(R (*func)(B0, B1, B2, B3), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+    Event<void()> event(T *obj, R (T::*method)(B0, B1, B2, B3), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+    Event<void()> event(const T *obj, R (T::*method)(B0, B1, B2, B3) const, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+    Event<void()> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3) volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+    Event<void()> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3) const volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3>
+    Event<void()> event(mbed::Callback<R(B0, B1, B2, B3)> cb, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event<void()> event(R (*func)(B0, B1, B2, B3, B4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event<void()> event(T *obj, R (T::*method)(B0, B1, B2, B3, B4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event<void()> event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event<void()> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event<void()> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4>
+    Event<void()> event(mbed::Callback<R(B0, B1, B2, B3, B4)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0>
+    Event<void(A0)> event(R (*func)(A0));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0>
+    Event<void(A0)> event(T *obj, R (T::*method)(A0));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0>
+    Event<void(A0)> event(const T *obj, R (T::*method)(A0) const);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0>
+    Event<void(A0)> event(volatile T *obj, R (T::*method)(A0) volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0>
+    Event<void(A0)> event(const volatile T *obj, R (T::*method)(A0) const volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0>
+    Event<void(A0)> event(mbed::Callback<R(A0)> cb);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0>
+    Event<void(A0)> event(R (*func)(B0, A0), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0>
+    Event<void(A0)> event(T *obj, R (T::*method)(B0, A0), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0>
+    Event<void(A0)> event(const T *obj, R (T::*method)(B0, A0) const, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0>
+    Event<void(A0)> event(volatile T *obj, R (T::*method)(B0, A0) volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0>
+    Event<void(A0)> event(const volatile T *obj, R (T::*method)(B0, A0) const volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0>
+    Event<void(A0)> event(mbed::Callback<R(B0, A0)> cb, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+    Event<void(A0)> event(R (*func)(B0, B1, A0), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+    Event<void(A0)> event(T *obj, R (T::*method)(B0, B1, A0), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+    Event<void(A0)> event(const T *obj, R (T::*method)(B0, B1, A0) const, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+    Event<void(A0)> event(volatile T *obj, R (T::*method)(B0, B1, A0) volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+    Event<void(A0)> event(const volatile T *obj, R (T::*method)(B0, B1, A0) const volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0>
+    Event<void(A0)> event(mbed::Callback<R(B0, B1, A0)> cb, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+    Event<void(A0)> event(R (*func)(B0, B1, B2, A0), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+    Event<void(A0)> event(T *obj, R (T::*method)(B0, B1, B2, A0), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+    Event<void(A0)> event(const T *obj, R (T::*method)(B0, B1, B2, A0) const, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+    Event<void(A0)> event(volatile T *obj, R (T::*method)(B0, B1, B2, A0) volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+    Event<void(A0)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0) const volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0>
+    Event<void(A0)> event(mbed::Callback<R(B0, B1, B2, A0)> cb, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+    Event<void(A0)> event(R (*func)(B0, B1, B2, B3, A0), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+    Event<void(A0)> event(T *obj, R (T::*method)(B0, B1, B2, B3, A0), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+    Event<void(A0)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0) const, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+    Event<void(A0)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0) volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+    Event<void(A0)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0) const volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0>
+    Event<void(A0)> event(mbed::Callback<R(B0, B1, B2, B3, A0)> cb, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+    Event<void(A0)> event(R (*func)(B0, B1, B2, B3, B4, A0), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+    Event<void(A0)> event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+    Event<void(A0)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+    Event<void(A0)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+    Event<void(A0)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+    Event<void(A0)> event(mbed::Callback<R(B0, B1, B2, B3, B4, A0)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1>
+    Event<void(A0, A1)> event(R (*func)(A0, A1));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    Event<void(A0, A1)> event(T *obj, R (T::*method)(A0, A1));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    Event<void(A0, A1)> event(const T *obj, R (T::*method)(A0, A1) const);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    Event<void(A0, A1)> event(volatile T *obj, R (T::*method)(A0, A1) volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1>
+    Event<void(A0, A1)> event(const volatile T *obj, R (T::*method)(A0, A1) const volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1>
+    Event<void(A0, A1)> event(mbed::Callback<R(A0, A1)> cb);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1>
+    Event<void(A0, A1)> event(R (*func)(B0, A0, A1), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+    Event<void(A0, A1)> event(T *obj, R (T::*method)(B0, A0, A1), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+    Event<void(A0, A1)> event(const T *obj, R (T::*method)(B0, A0, A1) const, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+    Event<void(A0, A1)> event(volatile T *obj, R (T::*method)(B0, A0, A1) volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1>
+    Event<void(A0, A1)> event(const volatile T *obj, R (T::*method)(B0, A0, A1) const volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1>
+    Event<void(A0, A1)> event(mbed::Callback<R(B0, A0, A1)> cb, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+    Event<void(A0, A1)> event(R (*func)(B0, B1, A0, A1), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+    Event<void(A0, A1)> event(T *obj, R (T::*method)(B0, B1, A0, A1), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+    Event<void(A0, A1)> event(const T *obj, R (T::*method)(B0, B1, A0, A1) const, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+    Event<void(A0, A1)> event(volatile T *obj, R (T::*method)(B0, B1, A0, A1) volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+    Event<void(A0, A1)> event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1) const volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1>
+    Event<void(A0, A1)> event(mbed::Callback<R(B0, B1, A0, A1)> cb, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+    Event<void(A0, A1)> event(R (*func)(B0, B1, B2, A0, A1), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+    Event<void(A0, A1)> event(T *obj, R (T::*method)(B0, B1, B2, A0, A1), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+    Event<void(A0, A1)> event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1) const, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+    Event<void(A0, A1)> event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1) volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+    Event<void(A0, A1)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1) const volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1>
+    Event<void(A0, A1)> event(mbed::Callback<R(B0, B1, B2, A0, A1)> cb, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+    Event<void(A0, A1)> event(R (*func)(B0, B1, B2, B3, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+    Event<void(A0, A1)> event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+    Event<void(A0, A1)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) const, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+    Event<void(A0, A1)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+    Event<void(A0, A1)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1) const volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+    Event<void(A0, A1)> event(mbed::Callback<R(B0, B1, B2, B3, A0, A1)> cb, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+    Event<void(A0, A1)> event(R (*func)(B0, B1, B2, B3, B4, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+    Event<void(A0, A1)> event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+    Event<void(A0, A1)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+    Event<void(A0, A1)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+    Event<void(A0, A1)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+    Event<void(A0, A1)> event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(R (*func)(A0, A1, A2));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(T *obj, R (T::*method)(A0, A1, A2));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const T *obj, R (T::*method)(A0, A1, A2) const);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(volatile T *obj, R (T::*method)(A0, A1, A2) volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const volatile T *obj, R (T::*method)(A0, A1, A2) const volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(mbed::Callback<R(A0, A1, A2)> cb);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(R (*func)(B0, A0, A1, A2), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(T *obj, R (T::*method)(B0, A0, A1, A2), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const T *obj, R (T::*method)(B0, A0, A1, A2) const, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(volatile T *obj, R (T::*method)(B0, A0, A1, A2) volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const volatile T *obj, R (T::*method)(B0, A0, A1, A2) const volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(mbed::Callback<R(B0, A0, A1, A2)> cb, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(R (*func)(B0, B1, A0, A1, A2), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(T *obj, R (T::*method)(B0, B1, A0, A1, A2), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const T *obj, R (T::*method)(B0, B1, A0, A1, A2) const, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2) volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2) const volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(mbed::Callback<R(B0, B1, A0, A1, A2)> cb, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(R (*func)(B0, B1, B2, A0, A1, A2), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) const, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2) const volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(mbed::Callback<R(B0, B1, B2, A0, A1, A2)> cb, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(R (*func)(B0, B1, B2, B3, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) const, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2) const volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(mbed::Callback<R(B0, B1, B2, B3, A0, A1, A2)> cb, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(R (*func)(B0, B1, B2, B3, B4, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+    Event<void(A0, A1, A2)> event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1, A2)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(R (*func)(A0, A1, A2, A3));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(T *obj, R (T::*method)(A0, A1, A2, A3));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const T *obj, R (T::*method)(A0, A1, A2, A3) const);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(volatile T *obj, R (T::*method)(A0, A1, A2, A3) volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const volatile T *obj, R (T::*method)(A0, A1, A2, A3) const volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(mbed::Callback<R(A0, A1, A2, A3)> cb);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(R (*func)(B0, A0, A1, A2, A3), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(T *obj, R (T::*method)(B0, A0, A1, A2, A3), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const T *obj, R (T::*method)(B0, A0, A1, A2, A3) const, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3) volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3) const volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(mbed::Callback<R(B0, A0, A1, A2, A3)> cb, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(R (*func)(B0, B1, A0, A1, A2, A3), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) const, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3) const volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(mbed::Callback<R(B0, B1, A0, A1, A2, A3)> cb, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(R (*func)(B0, B1, B2, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) const, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3) const volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(mbed::Callback<R(B0, B1, B2, A0, A1, A2, A3)> cb, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(R (*func)(B0, B1, B2, B3, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) const, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3) const volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(mbed::Callback<R(B0, B1, B2, B3, A0, A1, A2, A3)> cb, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(R (*func)(B0, B1, B2, B3, B4, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+    Event<void(A0, A1, A2, A3)> event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1, A2, A3)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(R (*func)(A0, A1, A2, A3, A4));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(T *obj, R (T::*method)(A0, A1, A2, A3, A4));
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const T *obj, R (T::*method)(A0, A1, A2, A3, A4) const);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const volatile T *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(mbed::Callback<R(A0, A1, A2, A3, A4)> cb);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(R (*func)(B0, A0, A1, A2, A3, A4), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4), C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) const, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const volatile T *obj, R (T::*method)(B0, A0, A1, A2, A3, A4) const volatile, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(mbed::Callback<R(B0, A0, A1, A2, A3, A4)> cb, C0 c0);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(R (*func)(B0, B1, A0, A1, A2, A3, A4), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4), C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) const, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const volatile T *obj, R (T::*method)(B0, B1, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(mbed::Callback<R(B0, B1, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(R (*func)(B0, B1, B2, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) const, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(mbed::Callback<R(B0, B1, B2, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1, C2 c2);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(R (*func)(B0, B1, B2, B3, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) const, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(mbed::Callback<R(B0, B1, B2, B3, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1, C2 c2, C3 c3);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(R (*func)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4), C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) const, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename T, typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(const volatile T *obj, R (T::*method)(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4) const volatile, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+    /** Creates an event bound to the event queue
+     *  @see EventQueue::event
+     */
+    template <typename R, typename B0, typename B1, typename B2, typename B3, typename B4, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+    Event<void(A0, A1, A2, A3, A4)> event(mbed::Callback<R(B0, B1, B2, B3, B4, A0, A1, A2, A3, A4)> cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4);
+
+protected:
+    template <typename F>
+    friend class Event;
+    struct equeue _equeue;
+    mbed::Callback<void(int)> _update;
+
+    // Function attributes
+    template <typename F>
+    static void function_call(void *p) {
+        (*(F*)p)();
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Context structures
+    template <typename F>
+    struct context00 {
+        F f;
+
+        context00(F f)
+            : f(f) {}
+
+        void operator()() {
+            f();
+        }
+    };
+
+    template <typename F, typename C0>
+    struct context10 {
+        F f; C0 c0;
+
+        context10(F f, C0 c0)
+            : f(f), c0(c0) {}
+
+        void operator()() {
+            f(c0);
+        }
+    };
+
+    template <typename F, typename C0, typename C1>
+    struct context20 {
+        F f; C0 c0; C1 c1;
+
+        context20(F f, C0 c0, C1 c1)
+            : f(f), c0(c0), c1(c1) {}
+
+        void operator()() {
+            f(c0, c1);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2>
+    struct context30 {
+        F f; C0 c0; C1 c1; C2 c2;
+
+        context30(F f, C0 c0, C1 c1, C2 c2)
+            : f(f), c0(c0), c1(c1), c2(c2) {}
+
+        void operator()() {
+            f(c0, c1, c2);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3>
+    struct context40 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3;
+
+        context40(F f, C0 c0, C1 c1, C2 c2, C3 c3)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3) {}
+
+        void operator()() {
+            f(c0, c1, c2, c3);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4>
+    struct context50 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3; C4 c4;
+
+        context50(F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3), c4(c4) {}
+
+        void operator()() {
+            f(c0, c1, c2, c3, c4);
+        }
+    };
+
+    template <typename F, typename A0>
+    struct context01 {
+        F f;
+
+        context01(F f)
+            : f(f) {}
+
+        void operator()(A0 a0) {
+            f(a0);
+        }
+    };
+
+    template <typename F, typename C0, typename A0>
+    struct context11 {
+        F f; C0 c0;
+
+        context11(F f, C0 c0)
+            : f(f), c0(c0) {}
+
+        void operator()(A0 a0) {
+            f(c0, a0);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename A0>
+    struct context21 {
+        F f; C0 c0; C1 c1;
+
+        context21(F f, C0 c0, C1 c1)
+            : f(f), c0(c0), c1(c1) {}
+
+        void operator()(A0 a0) {
+            f(c0, c1, a0);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename A0>
+    struct context31 {
+        F f; C0 c0; C1 c1; C2 c2;
+
+        context31(F f, C0 c0, C1 c1, C2 c2)
+            : f(f), c0(c0), c1(c1), c2(c2) {}
+
+        void operator()(A0 a0) {
+            f(c0, c1, c2, a0);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename A0>
+    struct context41 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3;
+
+        context41(F f, C0 c0, C1 c1, C2 c2, C3 c3)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3) {}
+
+        void operator()(A0 a0) {
+            f(c0, c1, c2, c3, a0);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0>
+    struct context51 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3; C4 c4;
+
+        context51(F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3), c4(c4) {}
+
+        void operator()(A0 a0) {
+            f(c0, c1, c2, c3, c4, a0);
+        }
+    };
+
+    template <typename F, typename A0, typename A1>
+    struct context02 {
+        F f;
+
+        context02(F f)
+            : f(f) {}
+
+        void operator()(A0 a0, A1 a1) {
+            f(a0, a1);
+        }
+    };
+
+    template <typename F, typename C0, typename A0, typename A1>
+    struct context12 {
+        F f; C0 c0;
+
+        context12(F f, C0 c0)
+            : f(f), c0(c0) {}
+
+        void operator()(A0 a0, A1 a1) {
+            f(c0, a0, a1);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename A0, typename A1>
+    struct context22 {
+        F f; C0 c0; C1 c1;
+
+        context22(F f, C0 c0, C1 c1)
+            : f(f), c0(c0), c1(c1) {}
+
+        void operator()(A0 a0, A1 a1) {
+            f(c0, c1, a0, a1);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename A0, typename A1>
+    struct context32 {
+        F f; C0 c0; C1 c1; C2 c2;
+
+        context32(F f, C0 c0, C1 c1, C2 c2)
+            : f(f), c0(c0), c1(c1), c2(c2) {}
+
+        void operator()(A0 a0, A1 a1) {
+            f(c0, c1, c2, a0, a1);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1>
+    struct context42 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3;
+
+        context42(F f, C0 c0, C1 c1, C2 c2, C3 c3)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3) {}
+
+        void operator()(A0 a0, A1 a1) {
+            f(c0, c1, c2, c3, a0, a1);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1>
+    struct context52 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3; C4 c4;
+
+        context52(F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3), c4(c4) {}
+
+        void operator()(A0 a0, A1 a1) {
+            f(c0, c1, c2, c3, c4, a0, a1);
+        }
+    };
+
+    template <typename F, typename A0, typename A1, typename A2>
+    struct context03 {
+        F f;
+
+        context03(F f)
+            : f(f) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2) {
+            f(a0, a1, a2);
+        }
+    };
+
+    template <typename F, typename C0, typename A0, typename A1, typename A2>
+    struct context13 {
+        F f; C0 c0;
+
+        context13(F f, C0 c0)
+            : f(f), c0(c0) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2) {
+            f(c0, a0, a1, a2);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename A0, typename A1, typename A2>
+    struct context23 {
+        F f; C0 c0; C1 c1;
+
+        context23(F f, C0 c0, C1 c1)
+            : f(f), c0(c0), c1(c1) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2) {
+            f(c0, c1, a0, a1, a2);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2>
+    struct context33 {
+        F f; C0 c0; C1 c1; C2 c2;
+
+        context33(F f, C0 c0, C1 c1, C2 c2)
+            : f(f), c0(c0), c1(c1), c2(c2) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2) {
+            f(c0, c1, c2, a0, a1, a2);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2>
+    struct context43 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3;
+
+        context43(F f, C0 c0, C1 c1, C2 c2, C3 c3)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2) {
+            f(c0, c1, c2, c3, a0, a1, a2);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2>
+    struct context53 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3; C4 c4;
+
+        context53(F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3), c4(c4) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2) {
+            f(c0, c1, c2, c3, c4, a0, a1, a2);
+        }
+    };
+
+    template <typename F, typename A0, typename A1, typename A2, typename A3>
+    struct context04 {
+        F f;
+
+        context04(F f)
+            : f(f) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
+            f(a0, a1, a2, a3);
+        }
+    };
+
+    template <typename F, typename C0, typename A0, typename A1, typename A2, typename A3>
+    struct context14 {
+        F f; C0 c0;
+
+        context14(F f, C0 c0)
+            : f(f), c0(c0) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
+            f(c0, a0, a1, a2, a3);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3>
+    struct context24 {
+        F f; C0 c0; C1 c1;
+
+        context24(F f, C0 c0, C1 c1)
+            : f(f), c0(c0), c1(c1) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
+            f(c0, c1, a0, a1, a2, a3);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3>
+    struct context34 {
+        F f; C0 c0; C1 c1; C2 c2;
+
+        context34(F f, C0 c0, C1 c1, C2 c2)
+            : f(f), c0(c0), c1(c1), c2(c2) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
+            f(c0, c1, c2, a0, a1, a2, a3);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3>
+    struct context44 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3;
+
+        context44(F f, C0 c0, C1 c1, C2 c2, C3 c3)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
+            f(c0, c1, c2, c3, a0, a1, a2, a3);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3>
+    struct context54 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3; C4 c4;
+
+        context54(F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3), c4(c4) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
+            f(c0, c1, c2, c3, c4, a0, a1, a2, a3);
+        }
+    };
+
+    template <typename F, typename A0, typename A1, typename A2, typename A3, typename A4>
+    struct context05 {
+        F f;
+
+        context05(F f)
+            : f(f) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+            f(a0, a1, a2, a3, a4);
+        }
+    };
+
+    template <typename F, typename C0, typename A0, typename A1, typename A2, typename A3, typename A4>
+    struct context15 {
+        F f; C0 c0;
+
+        context15(F f, C0 c0)
+            : f(f), c0(c0) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+            f(c0, a0, a1, a2, a3, a4);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename A0, typename A1, typename A2, typename A3, typename A4>
+    struct context25 {
+        F f; C0 c0; C1 c1;
+
+        context25(F f, C0 c0, C1 c1)
+            : f(f), c0(c0), c1(c1) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+            f(c0, c1, a0, a1, a2, a3, a4);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename A0, typename A1, typename A2, typename A3, typename A4>
+    struct context35 {
+        F f; C0 c0; C1 c1; C2 c2;
+
+        context35(F f, C0 c0, C1 c1, C2 c2)
+            : f(f), c0(c0), c1(c1), c2(c2) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+            f(c0, c1, c2, a0, a1, a2, a3, a4);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename A0, typename A1, typename A2, typename A3, typename A4>
+    struct context45 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3;
+
+        context45(F f, C0 c0, C1 c1, C2 c2, C3 c3)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+            f(c0, c1, c2, c3, a0, a1, a2, a3, a4);
+        }
+    };
+
+    template <typename F, typename C0, typename C1, typename C2, typename C3, typename C4, typename A0, typename A1, typename A2, typename A3, typename A4>
+    struct context55 {
+        F f; C0 c0; C1 c1; C2 c2; C3 c3; C4 c4;
+
+        context55(F f, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4)
+            : f(f), c0(c0), c1(c1), c2(c2), c3(c3), c4(c4) {}
+
+        void operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+            f(c0, c1, c2, c3, c4, a0, a1, a2, a3, a4);
+        }
+    };
+};
+
+}
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/LICENSE b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/LICENSE
new file mode 100755
index 0000000..59cd3f8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/LICENSE
@@ -0,0 +1,165 @@
+Apache License
+Version 2.0, January 2004
+http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and
+distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the copyright owner or entity authorized by the copyright
+owner that is granting the License.
+
+"Legal Entity" shall mean the union of the acting entity and all other entities
+that control, are controlled by, or are under common control with that entity.
+For the purposes of this definition, "control" means (i) the power, direct or
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+contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the
+outstanding shares, or (iii) beneficial ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising
+permissions granted by this License.
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+but not limited to software source code, documentation source, and configuration
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+
+"Work" shall mean the work of authorship, whether in Source or Object form, made
+available under the License, as indicated by a copyright notice that is included
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+
+"Derivative Works" shall mean any work, whether in Source or Object form, that
+is based on (or derived from) the Work and for which the editorial revisions,
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+shall not include works that remain separable from, or merely link (or bind by
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+"Contribution" shall mean any work of authorship, including the original version
+of the Work and any modifications or additions to that Work or Derivative Works
+thereof, that is intentionally submitted to Licensor for inclusion in the Work
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+
+"Contributor" shall mean Licensor and any individual or Legal Entity on behalf
+of whom a Contribution has been received by Licensor and subsequently
+incorporated within the Work.
+
+2. Grant of Copyright License.
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+Subject to the terms and conditions of this License, each Contributor hereby
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+3. Grant of Patent License.
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/README.md b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/README.md
new file mode 100755
index 0000000..9e0263c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/README.md
@@ -0,0 +1,153 @@
+## The mbed-events library ##
+
+The mbed-events library provides a flexible queue for scheduling events.
+
+``` cpp
+#include "mbed_events.h"
+#include <stdio.h>
+
+int main() {
+    // creates a queue with the default size
+    EventQueue queue;
+
+    // events are simple callbacks
+    queue.call(printf, "called immediately\n");
+    queue.call_in(2000, printf, "called in 2 seconds\n");
+    queue.call_every(1000, printf, "called every 1 seconds\n");
+
+    // events are executed by the dispatch method
+    queue.dispatch();
+}
+```
+
+The mbed-events library can be used as a normal event loop, or it can be
+backgrounded on a single hardware timer or even another event loop. It is
+both thread and irq safe, and provides functions for easily composing 
+independent event queues.
+
+The mbed-events library can act as a drop-in scheduler, provide synchronization
+between multiple threads, or just act as a mechanism for moving events out of 
+interrupt contexts.
+
+### Usage ###
+
+The core of the mbed-events library is the [EventQueue](EventQueue.h) class,
+which represents a single event queue. The `EventQueue::dispatch` function
+runs the queue, providing the context for executing events.
+
+``` cpp
+// Creates an event queue enough buffer space for 32 Callbacks. This
+// is the default if no argument was provided. Alternatively the size
+// can just be specified in bytes.
+EventQueue queue(32*EVENTS_EVENT_SIZE);
+
+// Events can be posted to the underlying event queue with dynamic
+// context allocated from the specified buffer
+queue.call(printf, "hello %d %d %d %d\n", 1, 2, 3, 4);
+queue.call(&serial, &Serial::printf, "hi\n");
+
+// The dispatch function provides the context for the running the queue
+// and can take a millisecond timeout to run for a fixed time or to just
+// dispatch any pending events
+queue.dispatch();
+```
+
+The EventQueue class provides several call functions for posting events
+to the underlying event queue. The call functions are thread and irq safe,
+don't need the underlying loop to be running, and provide an easy mechanism
+for moving events out of interrupt contexts.
+
+``` cpp
+// Simple call function registers events to be called as soon as possible
+queue.call(doit);
+queue.call(printf, "called immediately\n");
+
+// The call_in function registers events to be called after a delay
+// specified in milliseconds
+queue.call_in(2000, doit_in_two_seconds);
+queue.call_in(300, printf, "called in 0.3 seconds\n");
+
+// The call_every function registers events to be called repeatedly
+// with a period specified in milliseconds
+queue.call_every(2000, doit_every_two_seconds);
+queue.call_every(400, printf, "called every 0.4 seconds\n");
+```
+
+The call functions return an id that uniquely represents the event in the 
+the event queue. This id can be passed to `EventQueue::cancel` to cancel
+an in-flight event.
+
+``` cpp
+// The event id uniquely represents the event in the queue
+int id = queue.call_in(100, printf, "will this work?\n");
+
+// If there was not enough memory necessary to allocate the event,
+// an id of 0 is returned from the call functions
+if (id) {
+    error("oh no!");
+}
+
+// Events can be cancelled as long as they have not been dispatched. If the
+// event has already expired, cancel has no side-effects.
+queue.cancel(id);
+```
+
+For a more fine-grain control of event dispatch, the `Event` class can be
+manually instantiated and configured. An `Event` represents an event as
+a C++ style function object and can be directly passed to other APIs that
+expect a callback.
+
+``` cpp
+// Creates an event bound to the specified event queue
+EventQueue queue;
+Event<void()> event(&queue, doit);
+
+// The event can be manually configured for special timing requirements
+// specified in milliseconds
+event.delay(10);
+event.period(10000);
+
+// Posted events are dispatched in the context of the queue's
+// dispatch function
+queue.dispatch();
+
+// Events can also pass arguments to the underlying callback when both
+// initially constructed and posted.
+Event<void(int, int)> event(&queue, printf, "recieved %d and %d\n");
+
+// Events can be posted multiple times and enqueue gracefully until
+// the dispatch function is called.
+event.post(1, 2);
+event.post(3, 4);
+event.post(5, 6);
+
+queue.dispatch();
+```
+
+Event queues easily align with module boundaries, where internal state can
+be implicitly synchronized through event dispatch. Multiple modules can
+use independent event queues, but still be composed through the
+`EventQueue::chain` function.
+
+``` cpp
+// Create some event queues with pending events
+EventQueue a;
+a.call(printf, "hello from a!\n");
+
+EventQueue b;
+b.call(printf, "hello from b!\n");
+
+EventQueue c;
+c.call(printf, "hello from c!\n");
+
+// Chain c and b onto a's event queue. Both c and b will be dispatched
+// in the context of a's dispatch function.
+c.chain(&a);
+b.chain(&a);
+
+// Dispatching a will in turn dispatch b and c, printing hello from
+// all three queues
+a.dispatch();
+```
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/.mbedignore b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/.mbedignore
new file mode 100755
index 0000000..e7e1fb0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/.mbedignore
@@ -0,0 +1 @@
+tests/*
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/Makefile b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/Makefile
new file mode 100755
index 0000000..1323c96
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/Makefile
@@ -0,0 +1,60 @@
+TARGET = libequeue.a
+
+CC = gcc
+AR = ar
+SIZE = size
+
+SRC += $(wildcard *.c)
+OBJ := $(SRC:.c=.o)
+DEP := $(SRC:.c=.d)
+ASM := $(SRC:.c=.s)
+
+ifdef DEBUG
+CFLAGS += -O0 -g3
+else
+CFLAGS += -O2
+endif
+ifdef WORD
+CFLAGS += -m$(WORD)
+endif
+CFLAGS += -I. -I..
+CFLAGS += -std=c99
+CFLAGS += -Wall
+CFLAGS += -D_XOPEN_SOURCE=600
+
+LFLAGS += -pthread
+
+
+all: $(TARGET)
+
+test: tests/tests.o $(OBJ)
+	$(CC) $(CFLAGS) $^ $(LFLAGS) -o tests/tests
+	tests/tests
+
+prof: tests/prof.o $(OBJ)
+	$(CC) $(CFLAGS) $^ $(LFLAGS) -o tests/prof
+	tests/prof
+
+asm: $(ASM)
+
+size: $(OBJ)
+	$(SIZE) -t $^
+
+-include $(DEP)
+
+%.a: $(OBJ)
+	$(AR) rcs $@ $^
+
+%.o: %.c
+	$(CC) -c -MMD $(CFLAGS) $< -o $@
+
+%.s: %.c
+	$(CC) -S $(CFLAGS) $< -o $@
+
+clean:
+	rm -f $(TARGET)
+	rm -f tests/tests tests/tests.o tests/tests.d
+	rm -f tests/prof tests/prof.o tests/prof.d
+	rm -f $(OBJ)
+	rm -f $(DEP)
+	rm -f $(ASM)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/README.md b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/README.md
new file mode 100755
index 0000000..10f500c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/README.md
@@ -0,0 +1,210 @@
+## The equeue library ##
+
+The equeue library is designed as a simple but powerful library for scheduling
+events on composable queues.
+
+``` c
+#include "equeue.h"
+#include <stdio.h>
+
+int main() {
+    // creates a queue with space for 32 basic events
+    equeue_t queue;
+    equeue_create(&queue, 32*EQUEUE_EVENT_SIZE);
+
+    // events can be simple callbacks
+    equeue_call(&queue, print, "called immediately");
+    equeue_call_in(&queue, 2000, print, "called in 2 seconds");
+    equeue_call_every(&queue, 1000, print, "called every 1 seconds");
+
+    // events are executed in equeue_dispatch
+    equeue_dispatch(&queue, 3000);
+
+    print("called after 3 seconds");
+
+    equeue_destroy(&queue);
+}
+```
+
+The equeue library can be used as a normal event loop, or it can be
+backgrounded on a single hardware timer or even another event loop. It
+is both thread and irq safe, and provides functions for easily composing
+multiple queues.
+
+The equeue library can act as a drop-in scheduler, provide synchronization
+between multiple threads, or just act as a mechanism for moving events
+out of interrupt contexts.
+
+## Documentation ##
+
+The in-depth documentation on specific functions can be found in
+[equeue.h](equeue.h).
+
+The core of the equeue library is the `equeue_t` type which represents a
+single event queue, and the `equeue_dispatch` function which runs the equeue,
+providing the context for executing events.
+
+On top of this, `equeue_call`, `equeue_call_in`, and `equeue_call_every`
+provide easy methods for posting events to execute in the context of the
+`equeue_dispatch` function.
+
+``` c
+#include "equeue.h"
+#include "game.h"
+
+equeue_t queue;
+struct game game;
+
+// button_isr may be in interrupt context
+void button_isr(void) {
+    equeue_call(&queue, game_button_update, &game);
+}
+
+// a simple user-interface framework
+int main() {
+    equeue_create(&queue, 4096);
+    game_create(&game);
+
+    // call game_screen_udpate at 60 Hz
+    equeue_call_every(&queue, 1000/60, game_screen_update, &game);
+
+    // dispatch forever
+    equeue_dispatch(&queue, -1);
+}
+```
+
+In addition to simple callbacks, an event can be manually allocated with
+`equeue_alloc` and posted with `equeue_post` to allow passing an arbitrary
+amount of context to the execution of the event. This memory is allocated out
+of the equeue's buffer, and dynamic memory can be completely avoided.
+
+The equeue allocator is designed to minimize jitter in interrupt contexts as
+well as avoid memory fragmentation on small devices. The allocator achieves
+both constant-runtime and zero-fragmentation for fixed-size events, however
+grows linearly as the quantity of differently-sized allocations increases.
+
+``` c
+#include "equeue.h"
+
+equeue_t queue;
+
+// arbitrary data can be moved to a different context
+int enet_consume(void *buffer, int size) {
+    if (size > 512) {
+        size = 512;
+    }
+
+    void *data = equeue_alloc(&queue, 512);
+    memcpy(data, buffer, size);
+    equeue_post(&queue, handle_data_elsewhere, data);
+
+    return size;
+}
+```
+
+Additionally, in-flight events can be cancelled with `equeue_cancel`. Events
+are given unique ids on post, allowing safe cancellation of expired events.
+
+``` c
+#include "equeue.h"
+
+equeue_t queue;
+int sonar_value;
+int sonar_timeout_id;
+
+void sonar_isr(int value) {
+    equeue_cancel(&queue, sonar_timeout_id);
+    sonar_value = value;
+}
+
+void sonar_timeout(void *) {
+    sonar_value = -1;
+}
+
+void sonar_read(void) {
+    sonar_timeout_id = equeue_call_in(&queue, 300, sonar_timeout, 0);
+    sonar_start();
+}
+```
+
+From an architectural standpoint, event queues easily align with module
+boundaries, where internal state can be implicitly synchronized through
+event dispatch.
+
+On platforms where multiple threads are unavailable, multiple modules
+can use independent event queues and still be composed through the
+`equeue_chain` function.
+
+``` c
+#include "equeue.h"
+
+// run a simultaneous localization and mapping loop in one queue
+struct slam {
+    equeue_t queue;
+};
+
+void slam_create(struct slam *s, equeue_t *target) {
+    equeue_create(&s->queue, 4096);
+    equeue_chain(&s->queue, target);
+    equeue_call_every(&s->queue, 100, slam_filter);
+}
+
+// run a sonar with it's own queue
+struct sonar {
+    equeue_t equeue;
+    struct slam *slam;
+};
+
+void sonar_create(struct sonar *s, equeue_t *target) {
+    equeue_create(&s->queue, 64);
+    equeue_chain(&s->queue, target);
+    equeue_call_in(&s->queue, 5, sonar_update, s);
+}
+
+// all of the above queues can be combined into a single thread of execution
+int main() {
+    equeue_t queue;
+    equeue_create(&queue, 1024);
+
+    struct sonar s1, s2, s3;
+    sonar_create(&s1, &queue);
+    sonar_create(&s2, &queue);
+    sonar_create(&s3, &queue);
+
+    struct slam slam;
+    slam_create(&slam, &queue);
+
+    // dispatches events from all of the modules
+    equeue_dispatch(&queue, -1);
+}
+```
+
+## Platform ##
+
+The equeue library has a minimal porting layer that is flexible depending
+on the requirements of the underlying platform. Platform specific declarations
+and more information can be found in [equeue_platform.h](equeue_platform.h).
+
+## Tests ##
+
+The equeue library uses a set of local tests based on the posix implementation.
+
+Runtime tests are located in [tests.c](tests/tests.c):
+
+``` bash
+make test
+```
+
+Profiling tests based on rdtsc are located in [prof.c](tests/prof.c):
+
+``` bash
+make prof
+```
+
+To make profiling results more tangible, the profiler also supports percentage
+comparison with previous runs:
+``` bash
+make prof | tee results.txt
+cat results.txt | make prof
+```
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue.c
new file mode 100755
index 0000000..e9fe444
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue.c
@@ -0,0 +1,574 @@
+/*
+ * Flexible event queue for dispatching events
+ *
+ * Copyright (c) 2016 Christopher Haster
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "equeue/equeue.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+
+// calculate the relative-difference between absolute times while
+// correctly handling overflow conditions
+static inline int equeue_tickdiff(unsigned a, unsigned b) {
+    return (int)(unsigned)(a - b);
+}
+
+// calculate the relative-difference between absolute times, but
+// also clamp to zero, resulting in only non-zero values.
+static inline int equeue_clampdiff(unsigned a, unsigned b) {
+    int diff = equeue_tickdiff(a, b);
+    return ~(diff >> (8*sizeof(int)-1)) & diff;
+}
+
+// Increment the unique id in an event, hiding the event from cancel
+static inline void equeue_incid(equeue_t *q, struct equeue_event *e) {
+    e->id += 1;
+    if (!(e->id < q->npw2)) {
+        e->id = 1;
+    }
+}
+
+
+// equeue lifetime management
+int equeue_create(equeue_t *q, size_t size) {
+    // dynamically allocate the specified buffer
+    void *buffer = malloc(size);
+    if (!buffer) {
+        return -1;
+    }
+
+    int err = equeue_create_inplace(q, size, buffer);
+    q->allocated = buffer;
+    return err;
+}
+
+int equeue_create_inplace(equeue_t *q, size_t size, void *buffer) {
+    // setup queue around provided buffer
+    q->buffer = buffer;
+    q->allocated = 0;
+
+    q->npw2 = 0;
+    for (unsigned s = size; s; s >>= 1) {
+        q->npw2++;
+    }
+
+    q->chunks = 0;
+    q->slab.size = size;
+    q->slab.data = buffer;
+
+    q->queue = 0;
+    q->tick = equeue_tick();
+    q->generation = 0;
+    q->breaks = 0;
+
+    q->background.active = false;
+    q->background.update = 0;
+    q->background.timer = 0;
+
+    // initialize platform resources
+    int err;
+    err = equeue_sema_create(&q->eventsema);
+    if (err < 0) {
+        return err;
+    }
+
+    err = equeue_mutex_create(&q->queuelock);
+    if (err < 0) {
+        return err;
+    }
+
+    err = equeue_mutex_create(&q->memlock);
+    if (err < 0) {
+        return err;
+    }
+
+    return 0;
+}
+
+void equeue_destroy(equeue_t *q) {
+    // call destructors on pending events
+    for (struct equeue_event *es = q->queue; es; es = es->next) {
+        for (struct equeue_event *e = q->queue; e; e = e->sibling) {
+            if (e->dtor) {
+                e->dtor(e + 1);
+            }
+        }
+    }
+
+    // notify background timer
+    if (q->background.update) {
+        q->background.update(q->background.timer, -1);
+    }
+
+    // clean up platform resources + memory
+    equeue_mutex_destroy(&q->memlock);
+    equeue_mutex_destroy(&q->queuelock);
+    equeue_sema_destroy(&q->eventsema);
+    free(q->allocated);
+}
+
+
+// equeue chunk allocation functions
+static struct equeue_event *equeue_mem_alloc(equeue_t *q, size_t size) {
+    // add event overhead
+    size += sizeof(struct equeue_event);
+    size = (size + sizeof(void*)-1) & ~(sizeof(void*)-1);
+
+    equeue_mutex_lock(&q->memlock);
+
+    // check if a good chunk is available
+    for (struct equeue_event **p = &q->chunks; *p; p = &(*p)->next) {
+        if ((*p)->size >= size) {
+            struct equeue_event *e = *p;
+            if (e->sibling) {
+                *p = e->sibling;
+                (*p)->next = e->next;
+            } else {
+                *p = e->next;
+            }
+
+            equeue_mutex_unlock(&q->memlock);
+            return e;
+        }
+    }
+
+    // otherwise allocate a new chunk out of the slab
+    if (q->slab.size >= size) {
+        struct equeue_event *e = (struct equeue_event *)q->slab.data;
+        q->slab.data += size;
+        q->slab.size -= size;
+        e->size = size;
+        e->id = 1;
+
+        equeue_mutex_unlock(&q->memlock);
+        return e;
+    }
+
+    equeue_mutex_unlock(&q->memlock);
+    return 0;
+}
+
+static void equeue_mem_dealloc(equeue_t *q, struct equeue_event *e) {
+    equeue_mutex_lock(&q->memlock);
+
+    // stick chunk into list of chunks
+    struct equeue_event **p = &q->chunks;
+    while (*p && (*p)->size < e->size) {
+        p = &(*p)->next;
+    }
+
+    if (*p && (*p)->size == e->size) {
+        e->sibling = *p;
+        e->next = (*p)->next;
+    } else {
+        e->sibling = 0;
+        e->next = *p;
+    }
+    *p = e;
+
+    equeue_mutex_unlock(&q->memlock);
+}
+
+void *equeue_alloc(equeue_t *q, size_t size) {
+    struct equeue_event *e = equeue_mem_alloc(q, size);
+    if (!e) {
+        return 0;
+    }
+
+    e->target = 0;
+    e->period = -1;
+    e->dtor = 0;
+
+    return e + 1;
+}
+
+void equeue_dealloc(equeue_t *q, void *p) {
+    struct equeue_event *e = (struct equeue_event*)p - 1;
+
+    if (e->dtor) {
+        e->dtor(e+1);
+    }
+
+    equeue_mem_dealloc(q, e);
+}
+
+
+// equeue scheduling functions
+static int equeue_enqueue(equeue_t *q, struct equeue_event *e, unsigned tick) {
+    // setup event and hash local id with buffer offset for unique id
+    int id = (e->id << q->npw2) | ((unsigned char *)e - q->buffer);
+    e->target = tick + equeue_clampdiff(e->target, tick);
+    e->generation = q->generation;
+
+    equeue_mutex_lock(&q->queuelock);
+
+    // find the event slot
+    struct equeue_event **p = &q->queue;
+    while (*p && equeue_tickdiff((*p)->target, e->target) < 0) {
+        p = &(*p)->next;
+    }
+
+    // insert at head in slot
+    if (*p && (*p)->target == e->target) {
+        e->next = (*p)->next;
+        if (e->next) {
+            e->next->ref = &e->next;
+        }
+
+        e->sibling = *p;
+        e->sibling->ref = &e->sibling;
+    } else {
+        e->next = *p;
+        if (e->next) {
+            e->next->ref = &e->next;
+        }
+
+        e->sibling = 0;
+    }
+
+    *p = e;
+    e->ref = p;
+
+    // notify background timer
+    if ((q->background.update && q->background.active) &&
+        (q->queue == e && !e->sibling)) {
+        q->background.update(q->background.timer,
+                equeue_clampdiff(e->target, tick));
+    }
+
+    equeue_mutex_unlock(&q->queuelock);
+
+    return id;
+}
+
+static struct equeue_event *equeue_unqueue(equeue_t *q, int id) {
+    // decode event from unique id and check that the local id matches
+    struct equeue_event *e = (struct equeue_event *)
+            &q->buffer[id & ((1 << q->npw2)-1)];
+
+    equeue_mutex_lock(&q->queuelock);
+    if (e->id != id >> q->npw2) {
+        equeue_mutex_unlock(&q->queuelock);
+        return 0;
+    }
+
+    // clear the event and check if already in-flight
+    e->cb = 0;
+    e->period = -1;
+
+    int diff = equeue_tickdiff(e->target, q->tick);
+    if (diff < 0 || (diff == 0 && e->generation != q->generation)) {
+        equeue_mutex_unlock(&q->queuelock);
+        return 0;
+    }
+
+    // disentangle from queue
+    if (e->sibling) {
+        e->sibling->next = e->next;
+        if (e->sibling->next) {
+            e->sibling->next->ref = &e->sibling->next;
+        }
+
+        *e->ref = e->sibling;
+        e->sibling->ref = e->ref;
+    } else {
+        *e->ref = e->next;
+        if (e->next) {
+            e->next->ref = e->ref;
+        }
+    }
+
+    equeue_incid(q, e);
+    equeue_mutex_unlock(&q->queuelock);
+
+    return e;
+}
+
+static struct equeue_event *equeue_dequeue(equeue_t *q, unsigned target) {
+    equeue_mutex_lock(&q->queuelock);
+
+    // find all expired events and mark a new generation
+    q->generation += 1;
+    if (equeue_tickdiff(q->tick, target) <= 0) {
+        q->tick = target;
+    }
+
+    struct equeue_event *head = q->queue;
+    struct equeue_event **p = &head;
+    while (*p && equeue_tickdiff((*p)->target, target) <= 0) {
+        p = &(*p)->next;
+    }
+
+    q->queue = *p;
+    if (q->queue) {
+        q->queue->ref = &q->queue;
+    }
+
+    *p = 0;
+
+    equeue_mutex_unlock(&q->queuelock);
+
+    // reverse and flatten each slot to match insertion order
+    struct equeue_event **tail = &head;
+    struct equeue_event *ess = head;
+    while (ess) {
+        struct equeue_event *es = ess;
+        ess = es->next;
+
+        struct equeue_event *prev = 0;
+        for (struct equeue_event *e = es; e; e = e->sibling) {
+            e->next = prev;
+            prev = e;
+        }
+
+        *tail = prev;
+        tail = &es->next;
+    }
+
+    return head;
+}
+
+int equeue_post(equeue_t *q, void (*cb)(void*), void *p) {
+    struct equeue_event *e = (struct equeue_event*)p - 1;
+    unsigned tick = equeue_tick();
+    e->cb = cb;
+    e->target = tick + e->target;
+
+    int id = equeue_enqueue(q, e, tick);
+    equeue_sema_signal(&q->eventsema);
+    return id;
+}
+
+void equeue_cancel(equeue_t *q, int id) {
+    if (!id) {
+        return;
+    }
+
+    struct equeue_event *e = equeue_unqueue(q, id);
+    if (e) {
+        equeue_dealloc(q, e + 1);
+    }
+}
+
+void equeue_break(equeue_t *q) {
+    equeue_mutex_lock(&q->queuelock);
+    q->breaks++;
+    equeue_mutex_unlock(&q->queuelock);
+    equeue_sema_signal(&q->eventsema);
+}
+
+void equeue_dispatch(equeue_t *q, int ms) {
+    unsigned tick = equeue_tick();
+    unsigned timeout = tick + ms;
+    q->background.active = false;
+
+    while (1) {
+        // collect all the available events and next deadline
+        struct equeue_event *es = equeue_dequeue(q, tick);
+
+        // dispatch events
+        while (es) {
+            struct equeue_event *e = es;
+            es = e->next;
+
+            // actually dispatch the callbacks
+            void (*cb)(void *) = e->cb;
+            if (cb) {
+                cb(e + 1);
+            }
+
+            // reenqueue periodic events or deallocate
+            if (e->period >= 0) {
+                e->target += e->period;
+                equeue_enqueue(q, e, equeue_tick());
+            } else {
+                equeue_incid(q, e);
+                equeue_dealloc(q, e+1);
+            }
+        }
+
+        int deadline = -1;
+        tick = equeue_tick();
+
+        // check if we should stop dispatching soon
+        if (ms >= 0) {
+            deadline = equeue_tickdiff(timeout, tick);
+            if (deadline <= 0) {
+                // update background timer if necessary
+                if (q->background.update) {
+                    equeue_mutex_lock(&q->queuelock);
+                    if (q->background.update && q->queue) {
+                        q->background.update(q->background.timer,
+                                equeue_clampdiff(q->queue->target, tick));
+                    }
+                    q->background.active = true;
+                    equeue_mutex_unlock(&q->queuelock);
+                }
+                return;
+            }
+        }
+
+        // find closest deadline
+        equeue_mutex_lock(&q->queuelock);
+        if (q->queue) {
+            int diff = equeue_clampdiff(q->queue->target, tick);
+            if ((unsigned)diff < (unsigned)deadline) {
+                deadline = diff;
+            }
+        }
+        equeue_mutex_unlock(&q->queuelock);
+
+        // wait for events
+        equeue_sema_wait(&q->eventsema, deadline);
+
+        // check if we were notified to break out of dispatch
+        if (q->breaks) {
+            equeue_mutex_lock(&q->queuelock);
+            if (q->breaks > 0) {
+                q->breaks--;
+                equeue_mutex_unlock(&q->queuelock);
+                return;
+            }
+            equeue_mutex_unlock(&q->queuelock);
+        }
+
+        // update tick for next iteration
+        tick = equeue_tick();
+    }
+}
+
+
+// event functions
+void equeue_event_delay(void *p, int ms) {
+    struct equeue_event *e = (struct equeue_event*)p - 1;
+    e->target = ms;
+}
+
+void equeue_event_period(void *p, int ms) {
+    struct equeue_event *e = (struct equeue_event*)p - 1;
+    e->period = ms;
+}
+
+void equeue_event_dtor(void *p, void (*dtor)(void *)) {
+    struct equeue_event *e = (struct equeue_event*)p - 1;
+    e->dtor = dtor;
+}
+
+
+// simple callbacks 
+struct ecallback {
+    void (*cb)(void*);
+    void *data;
+};
+
+static void ecallback_dispatch(void *p) {
+    struct ecallback *e = (struct ecallback*)p;
+    e->cb(e->data);
+}
+
+int equeue_call(equeue_t *q, void (*cb)(void*), void *data) {
+    struct ecallback *e = equeue_alloc(q, sizeof(struct ecallback));
+    if (!e) {
+        return 0;
+    }
+
+    e->cb = cb;
+    e->data = data;
+    return equeue_post(q, ecallback_dispatch, e);
+}
+
+int equeue_call_in(equeue_t *q, int ms, void (*cb)(void*), void *data) {
+    struct ecallback *e = equeue_alloc(q, sizeof(struct ecallback));
+    if (!e) {
+        return 0;
+    }
+
+    equeue_event_delay(e, ms);
+    e->cb = cb;
+    e->data = data;
+    return equeue_post(q, ecallback_dispatch, e);
+}
+
+int equeue_call_every(equeue_t *q, int ms, void (*cb)(void*), void *data) {
+    struct ecallback *e = equeue_alloc(q, sizeof(struct ecallback));
+    if (!e) {
+        return 0;
+    }
+
+    equeue_event_delay(e, ms);
+    equeue_event_period(e, ms);
+    e->cb = cb;
+    e->data = data;
+    return equeue_post(q, ecallback_dispatch, e);
+}
+
+
+// backgrounding
+void equeue_background(equeue_t *q,
+        void (*update)(void *timer, int ms), void *timer) {
+    equeue_mutex_lock(&q->queuelock);
+    if (q->background.update) {
+        q->background.update(q->background.timer, -1);
+    }
+
+    q->background.update = update;
+    q->background.timer = timer;
+
+    if (q->background.update && q->queue) {
+        q->background.update(q->background.timer,
+                equeue_clampdiff(q->queue->target, equeue_tick()));
+    }
+    q->background.active = true;
+    equeue_mutex_unlock(&q->queuelock);
+}
+
+struct equeue_chain_context {
+    equeue_t *q;
+    equeue_t *target;
+    int id;
+};
+
+static void equeue_chain_dispatch(void *p) {
+    equeue_dispatch((equeue_t *)p, 0);
+}
+
+static void equeue_chain_update(void *p, int ms) {
+    struct equeue_chain_context *c = (struct equeue_chain_context *)p;
+    equeue_cancel(c->target, c->id);
+
+    if (ms >= 0) {
+        c->id = equeue_call_in(c->target, ms, equeue_chain_dispatch, c->q);
+    } else {
+        equeue_dealloc(c->target, c);
+    }
+}
+
+void equeue_chain(equeue_t *q, equeue_t *target) {
+    if (!target) {
+        equeue_background(q, 0, 0);
+        return;
+    }
+
+    struct equeue_chain_context *c = equeue_alloc(q,
+            sizeof(struct equeue_chain_context));
+
+    c->q = q;
+    c->target = target;
+    c->id = 0;
+
+    equeue_background(q, equeue_chain_update, c);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue.h
new file mode 100755
index 0000000..80ee9c7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue.h
@@ -0,0 +1,223 @@
+
+/** \addtogroup events */
+/** @{*/
+/*
+ * Flexible event queue for dispatching events
+ *
+ * Copyright (c) 2016 Christopher Haster
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef EQUEUE_H
+#define EQUEUE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Platform specific files
+#include "equeue/equeue_platform.h"
+
+#include <stddef.h>
+#include <stdint.h>
+
+
+// The minimum size of an event
+// This size is guaranteed to fit events created by event_call
+#define EQUEUE_EVENT_SIZE (sizeof(struct equeue_event) + 2*sizeof(void*))
+
+// Internal event structure
+struct equeue_event {
+    unsigned size;
+    uint8_t id;
+    uint8_t generation;
+
+    struct equeue_event *next;
+    struct equeue_event *sibling;
+    struct equeue_event **ref;
+
+    unsigned target;
+    int period;
+    void (*dtor)(void *);
+
+    void (*cb)(void *);
+    // data follows
+};
+
+// Event queue structure
+typedef struct equeue {
+    struct equeue_event *queue;
+    unsigned tick;
+    unsigned breaks;
+    uint8_t generation;
+
+    unsigned char *buffer;
+    unsigned npw2;
+    void *allocated;
+
+    struct equeue_event *chunks;
+    struct equeue_slab {
+        size_t size;
+        unsigned char *data;
+    } slab;
+
+    struct equeue_background {
+        bool active;
+        void (*update)(void *timer, int ms);
+        void *timer;
+    } background;
+
+    equeue_sema_t eventsema;
+    equeue_mutex_t queuelock;
+    equeue_mutex_t memlock;
+} equeue_t;
+
+
+// Queue lifetime operations
+//
+// Creates and destroys an event queue. The event queue either allocates a
+// buffer of the specified size with malloc or uses a user provided buffer
+// if constructed with equeue_create_inplace.
+//
+// If the event queue creation fails, equeue_create returns a negative,
+// platform-specific error code.
+int equeue_create(equeue_t *queue, size_t size);
+int equeue_create_inplace(equeue_t *queue, size_t size, void *buffer);
+void equeue_destroy(equeue_t *queue);
+
+// Dispatch events
+//
+// Executes events until the specified milliseconds have passed. If ms is
+// negative, equeue_dispatch will dispatch events indefinitely or until
+// equeue_break is called on this queue.
+//
+// When called with a finite timeout, the equeue_dispatch function is
+// guaranteed to terminate. When called with a timeout of 0, the
+// equeue_dispatch does not wait and is irq safe.
+void equeue_dispatch(equeue_t *queue, int ms);
+
+// Break out of a running event loop
+//
+// Forces the specified event queue's dispatch loop to terminate. Pending
+// events may finish executing, but no new events will be executed.
+void equeue_break(equeue_t *queue);
+
+// Simple event calls
+//
+// The specified callback will be executed in the context of the event queue's
+// dispatch loop. When the callback is executed depends on the call function.
+//
+// equeue_call       - Immediately post an event to the queue
+// equeue_call_in    - Post an event after a specified time in milliseconds
+// equeue_call_every - Post an event periodically every milliseconds
+//
+// All equeue_call functions are irq safe and can act as a mechanism for
+// moving events out of irq contexts.
+//
+// The return value is a unique id that represents the posted event and can
+// be passed to equeue_cancel. If there is not enough memory to allocate the
+// event, equeue_call returns an id of 0.
+int equeue_call(equeue_t *queue, void (*cb)(void *), void *data);
+int equeue_call_in(equeue_t *queue, int ms, void (*cb)(void *), void *data);
+int equeue_call_every(equeue_t *queue, int ms, void (*cb)(void *), void *data);
+
+// Allocate memory for events
+//
+// The equeue_alloc function allocates an event that can be manually dispatched
+// with equeue_post. The equeue_dealloc function may be used to free an event
+// that has not been posted. Once posted, an event's memory is managed by the
+// event queue and should not be deallocated.
+//
+// Both equeue_alloc and equeue_dealloc are irq safe.
+//
+// The equeue allocator is designed to minimize jitter in interrupt contexts as
+// well as avoid memory fragmentation on small devices. The allocator achieves
+// both constant-runtime and zero-fragmentation for fixed-size events, however
+// grows linearly as the quantity of different sized allocations increases.
+//
+// The equeue_alloc function returns a pointer to the event's allocated memory
+// and acts as a handle to the underlying event. If there is not enough memory
+// to allocate the event, equeue_alloc returns null.
+void *equeue_alloc(equeue_t *queue, size_t size);
+void equeue_dealloc(equeue_t *queue, void *event);
+
+// Configure an allocated event
+//
+// equeue_event_delay  - Millisecond delay before dispatching an event
+// equeue_event_period - Millisecond period for repeating dispatching an event
+// equeue_event_dtor   - Destructor to run when the event is deallocated
+void equeue_event_delay(void *event, int ms);
+void equeue_event_period(void *event, int ms);
+void equeue_event_dtor(void *event, void (*dtor)(void *));
+
+// Post an event onto the event queue
+//
+// The equeue_post function takes a callback and a pointer to an event
+// allocated by equeue_alloc. The specified callback will be executed in the
+// context of the event queue's dispatch loop with the allocated event
+// as its argument.
+//
+// The equeue_post function is irq safe and can act as a mechanism for
+// moving events out of irq contexts.
+//
+// The return value is a unique id that represents the posted event and can
+// be passed to equeue_cancel.
+int equeue_post(equeue_t *queue, void (*cb)(void *), void *event);
+
+// Cancel an in-flight event
+//
+// Attempts to cancel an event referenced by the unique id returned from
+// equeue_call or equeue_post. It is safe to call equeue_cancel after an event
+// has already been dispatched.
+//
+// The equeue_cancel function is irq safe.
+//
+// If called while the event queue's dispatch loop is active, equeue_cancel
+// does not guarantee that the event will not not execute after it returns as
+// the event may have already begun executing.
+void equeue_cancel(equeue_t *queue, int id);
+
+// Background an event queue onto a single-shot timer
+//
+// The provided update function will be called to indicate when the queue
+// should be dispatched. A negative timeout will be passed to the update
+// function when the timer is no longer needed.
+//
+// Passing a null update function disables the existing timer.
+//
+// The equeue_background function allows an event queue to take advantage
+// of hardware timers or even other event loops, allowing an event queue to
+// be effectively backgrounded.
+void equeue_background(equeue_t *queue,
+        void (*update)(void *timer, int ms), void *timer);
+
+// Chain an event queue onto another event queue
+//
+// After chaining a queue to a target, calling equeue_dispatch on the
+// target queue will also dispatch events from this queue. The queues
+// use their own buffers and events must be managed independently.
+//
+// Passing a null queue as the target will unchain the existing queue.
+//
+// The equeue_chain function allows multiple equeues to be composed, sharing
+// the context of a dispatch loop while still being managed independently.
+void equeue_chain(equeue_t *queue, equeue_t *target);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_mbed.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_mbed.cpp
new file mode 100755
index 0000000..db8af73
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_mbed.cpp
@@ -0,0 +1,158 @@
+/*
+ * Implementation for the mbed library
+ * https://github.com/mbedmicro/mbed
+ *
+ * Copyright (c) 2016 Christopher Haster
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "equeue/equeue_platform.h"
+
+#if defined(EQUEUE_PLATFORM_MBED)
+
+#include <stdbool.h>
+#include "mbed.h"
+
+
+// Ticker operations
+static bool equeue_tick_inited = false;
+static volatile unsigned equeue_minutes = 0;
+static unsigned equeue_timer[
+        (sizeof(Timer)+sizeof(unsigned)-1)/sizeof(unsigned)];
+static unsigned equeue_ticker[
+        (sizeof(Ticker)+sizeof(unsigned)-1)/sizeof(unsigned)];
+
+static void equeue_tick_update() {
+    equeue_minutes += reinterpret_cast<Timer*>(equeue_timer)->read_ms();
+    reinterpret_cast<Timer*>(equeue_timer)->reset();
+}
+
+static void equeue_tick_init() {
+    MBED_STATIC_ASSERT(sizeof(equeue_timer) >= sizeof(Timer),
+            "The equeue_timer buffer must fit the class Timer");
+    MBED_STATIC_ASSERT(sizeof(equeue_ticker) >= sizeof(Ticker),
+            "The equeue_ticker buffer must fit the class Ticker");
+    Timer *timer = new (equeue_timer) Timer;
+    Ticker *ticker = new (equeue_ticker) Ticker;
+
+    equeue_minutes = 0;
+    timer->start();
+    ticker->attach_us(equeue_tick_update, 1000 << 16);
+
+    equeue_tick_inited = true;
+}
+
+unsigned equeue_tick() {
+    if (!equeue_tick_inited) {
+        equeue_tick_init();
+    }
+
+    unsigned minutes;
+    unsigned ms;
+
+    do {
+        minutes = equeue_minutes;
+        ms = reinterpret_cast<Timer*>(equeue_timer)->read_ms();
+    } while (minutes != equeue_minutes);
+
+    return minutes + ms;
+}
+
+
+// Mutex operations
+int equeue_mutex_create(equeue_mutex_t *m) { return 0; }
+void equeue_mutex_destroy(equeue_mutex_t *m) { }
+
+void equeue_mutex_lock(equeue_mutex_t *m) {
+    core_util_critical_section_enter();
+}
+
+void equeue_mutex_unlock(equeue_mutex_t *m) {
+    core_util_critical_section_exit();
+}
+
+
+// Semaphore operations
+#ifdef MBED_CONF_RTOS_PRESENT
+
+int equeue_sema_create(equeue_sema_t *s) {
+    osEventFlagsAttr_t attr;
+    memset(&attr, 0, sizeof(attr));
+    attr.cb_mem = &s->mem;
+    attr.cb_size = sizeof(s->mem);
+
+    s->id = osEventFlagsNew(&attr);
+    return !s->id ? -1 : 0;
+}
+
+void equeue_sema_destroy(equeue_sema_t *s) {
+    osEventFlagsDelete(s->id);
+}
+
+void equeue_sema_signal(equeue_sema_t *s) {
+    osEventFlagsSet(s->id, 1);
+}
+
+bool equeue_sema_wait(equeue_sema_t *s, int ms) {
+    if (ms < 0) {
+        ms = osWaitForever;
+    }
+
+    return (osEventFlagsWait(s->id, 1, osFlagsWaitAny, ms) == 1);
+}
+
+#else
+
+// Semaphore operations
+int equeue_sema_create(equeue_sema_t *s) {
+    *s = false;
+    return 0;
+}
+
+void equeue_sema_destroy(equeue_sema_t *s) {
+}
+
+void equeue_sema_signal(equeue_sema_t *s) {
+    *s = 1;
+}
+
+static void equeue_sema_timeout(equeue_sema_t *s) {
+    *s = -1;
+}
+
+bool equeue_sema_wait(equeue_sema_t *s, int ms) {
+    int signal = 0;
+    Timeout timeout;
+    if (ms == 0) {
+        return false;
+    } else if (ms > 0) {
+        timeout.attach_us(callback(equeue_sema_timeout, s), ms*1000);
+    }
+
+    core_util_critical_section_enter();
+    while (!*s) {
+        sleep();
+        core_util_critical_section_exit();
+        core_util_critical_section_enter();
+    }
+
+    signal = *s;
+    *s = false;
+    core_util_critical_section_exit();
+
+    return (signal > 0);
+}
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_platform.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_platform.h
new file mode 100755
index 0000000..9c5bec2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_platform.h
@@ -0,0 +1,152 @@
+
+/** \addtogroup events */
+/** @{*/
+/*
+ * System specific implementation
+ *
+ * Copyright (c) 2016 Christopher Haster
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef EQUEUE_PLATFORM_H
+#define EQUEUE_PLATFORM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+
+// Currently supported platforms
+//
+// Uncomment to select a supported platform or reimplement this file
+// for a specific target.
+//#define EQUEUE_PLATFORM_POSIX
+//#define EQUEUE_PLATFORM_MBED
+
+// Try to infer a platform if none was manually selected
+#if !defined(EQUEUE_PLATFORM_POSIX)     \
+ && !defined(EQUEUE_PLATFORM_MBED)
+#if defined(__unix__)
+#define EQUEUE_PLATFORM_POSIX
+#elif defined(__MBED__)
+#define EQUEUE_PLATFORM_MBED
+#else
+#warning "Unknown platform! Please update equeue_platform.h"
+#endif
+#endif
+
+// Platform includes
+#if defined(EQUEUE_PLATFORM_POSIX)
+#include <pthread.h>
+#elif defined(EQUEUE_PLATFORM_MBED)
+#include "cmsis_os2.h"
+#include "mbed_rtos_storage.h"
+#endif
+
+
+// Platform millisecond counter
+//
+// Return a tick that represents the number of milliseconds that have passed
+// since an arbitrary point in time. The granularity does not need to be at
+// the millisecond level, however the accuracy of the equeue library is
+// limited by the accuracy of this tick.
+//
+// Must intentionally overflow to 0 after 2^32-1
+unsigned equeue_tick(void);
+
+
+// Platform mutex type
+//
+// The equeue library requires at minimum a non-recursive mutex that is
+// safe in interrupt contexts. The mutex section is help for a bounded
+// amount of time, so simply disabling interrupts is acceptable
+//
+// If irq safety is not required, a regular blocking mutex can be used.
+#if defined(EQUEUE_PLATFORM_POSIX)
+typedef pthread_mutex_t equeue_mutex_t;
+#elif defined(EQUEUE_PLATFORM_WINDOWS)
+typedef CRITICAL_SECTION equeue_mutex_t;
+#elif defined(EQUEUE_PLATFORM_MBED)
+typedef unsigned equeue_mutex_t;
+#elif defined(EQUEUE_PLATFORM_FREERTOS)
+typedef UBaseType_t equeue_mutex_t;
+#endif
+
+// Platform mutex operations
+//
+// The equeue_mutex_create and equeue_mutex_destroy manage the lifetime
+// of the mutex. On error, equeue_mutex_create should return a negative
+// error code.
+//
+// The equeue_mutex_lock and equeue_mutex_unlock lock and unlock the
+// underlying mutex.
+int equeue_mutex_create(equeue_mutex_t *mutex);
+void equeue_mutex_destroy(equeue_mutex_t *mutex);
+void equeue_mutex_lock(equeue_mutex_t *mutex);
+void equeue_mutex_unlock(equeue_mutex_t *mutex);
+
+
+// Platform semaphore type
+//
+// The equeue library requires a binary semaphore type that can be safely
+// signaled from interrupt contexts and from inside a equeue_mutex section.
+//
+// The equeue_signal_wait is relied upon by the equeue library to sleep the
+// processor between events. Spurious wakeups have no negative-effects.
+//
+// A counting semaphore will also work, however may cause the event queue
+// dispatch loop to run unnecessarily. For that matter, equeue_signal_wait
+// may even be implemented as a single return statement.
+#if defined(EQUEUE_PLATFORM_POSIX)
+typedef struct equeue_sema {
+    pthread_mutex_t mutex;
+    pthread_cond_t cond;
+    bool signal;
+} equeue_sema_t;
+#elif defined(EQUEUE_PLATFORM_MBED) && defined(MBED_CONF_RTOS_PRESENT)
+typedef struct equeue_sema {
+    osEventFlagsId_t id;
+    mbed_rtos_storage_event_flags_t mem;
+} equeue_sema_t;
+#elif defined(EQUEUE_PLATFORM_MBED)
+typedef volatile int equeue_sema_t;
+#endif
+
+// Platform semaphore operations
+//
+// The equeue_sema_create and equeue_sema_destroy manage the lifetime
+// of the semaphore. On error, equeue_sema_create should return a negative
+// error code.
+//
+// The equeue_sema_signal marks a semaphore as signalled such that the next
+// equeue_sema_wait will return true.
+//
+// The equeue_sema_wait waits for a semaphore to be signalled or returns
+// immediately if equeue_sema_signal had been called since the last
+// equeue_sema_wait. The equeue_sema_wait returns true if it detected that
+// equeue_sema_signal had been called. If ms is negative, equeue_sema_wait
+// will wait for a signal indefinitely.
+int equeue_sema_create(equeue_sema_t *sema);
+void equeue_sema_destroy(equeue_sema_t *sema);
+void equeue_sema_signal(equeue_sema_t *sema);
+bool equeue_sema_wait(equeue_sema_t *sema, int ms);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_posix.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_posix.c
new file mode 100755
index 0000000..5d0c930
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/equeue_posix.c
@@ -0,0 +1,106 @@
+/*
+ * Implementation for Posix compliant platforms
+ *
+ * Copyright (c) 2016 Christopher Haster
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "equeue/equeue_platform.h"
+
+#if defined(EQUEUE_PLATFORM_POSIX)
+
+#include <time.h>
+#include <sys/time.h>
+#include <errno.h>
+
+
+// Tick operations
+unsigned equeue_tick(void) {
+    struct timeval tv;
+    gettimeofday(&tv, 0);
+    return (unsigned)(tv.tv_sec*1000 + tv.tv_usec/1000);
+}
+
+
+// Mutex operations
+int equeue_mutex_create(equeue_mutex_t *m) {
+    return pthread_mutex_init(m, 0);
+}
+
+void equeue_mutex_destroy(equeue_mutex_t *m) {
+    pthread_mutex_destroy(m);
+}
+
+void equeue_mutex_lock(equeue_mutex_t *m) {
+    pthread_mutex_lock(m);
+}
+
+void equeue_mutex_unlock(equeue_mutex_t *m) {
+    pthread_mutex_unlock(m);
+}
+
+
+// Semaphore operations
+int equeue_sema_create(equeue_sema_t *s) {
+    int err = pthread_mutex_init(&s->mutex, 0);
+    if (err) {
+        return err;
+    }
+
+    err = pthread_cond_init(&s->cond, 0);
+    if (err) {
+        return err;
+    }
+
+    s->signal = false;
+    return 0;
+}
+
+void equeue_sema_destroy(equeue_sema_t *s) {
+    pthread_cond_destroy(&s->cond);
+    pthread_mutex_destroy(&s->mutex);
+}
+
+void equeue_sema_signal(equeue_sema_t *s) {
+    pthread_mutex_lock(&s->mutex);
+    s->signal = true;
+    pthread_cond_signal(&s->cond);
+    pthread_mutex_unlock(&s->mutex);
+}
+
+bool equeue_sema_wait(equeue_sema_t *s, int ms) {
+    pthread_mutex_lock(&s->mutex);
+    if (!s->signal) {
+        if (ms < 0) {
+            pthread_cond_wait(&s->cond, &s->mutex);
+        } else {
+            struct timeval tv;
+            gettimeofday(&tv, 0);
+
+            struct timespec ts = {
+                .tv_sec = ms/1000 + tv.tv_sec,
+                .tv_nsec = ms*1000000 + tv.tv_usec*1000,
+            };
+
+            pthread_cond_timedwait(&s->cond, &s->mutex, &ts);
+        }
+    }
+
+    bool signal = s->signal;
+    s->signal = false;
+    pthread_mutex_unlock(&s->mutex);
+
+    return signal;
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/tests/prof.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/tests/prof.c
new file mode 100755
index 0000000..20d5ac5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/tests/prof.c
@@ -0,0 +1,407 @@
+/*
+ * Profiling framework for the events library
+ *
+ * Copyright (c) 2016 Christopher Haster
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "equeue.h"
+#include <unistd.h>
+#include <stdio.h>
+#include <setjmp.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <sys/time.h>
+
+
+// Performance measurement utils
+#define PROF_RUNS 5
+#define PROF_INTERVAL 100000000
+
+#define prof_volatile(t) __attribute__((unused)) volatile t
+
+typedef uint64_t prof_cycle_t;
+
+static volatile prof_cycle_t prof_start_cycle;
+static volatile prof_cycle_t prof_stop_cycle;
+static prof_cycle_t prof_accum_cycle;
+static prof_cycle_t prof_baseline_cycle;
+static prof_cycle_t prof_iterations;
+static const char *prof_units;
+
+#define prof_cycle() ({                                                     \
+    uint32_t a, b;                                                          \
+    __asm__ volatile ("rdtsc" : "=a" (a), "=d" (b));                        \
+    ((uint64_t)b << 32) | (uint64_t)a;                                      \
+})
+
+#define prof_loop()                                                         \
+    for (prof_iterations = 0;                                               \
+         prof_accum_cycle < PROF_INTERVAL;                                  \
+         prof_iterations++)
+
+#define prof_start() ({                                                     \
+    prof_start_cycle = prof_cycle();                                        \
+})
+
+#define prof_stop() ({                                                      \
+    prof_stop_cycle = prof_cycle();                                         \
+    prof_accum_cycle += prof_stop_cycle - prof_start_cycle;                 \
+})
+
+#define prof_result(value, units) ({                                        \
+    prof_accum_cycle = value+prof_baseline_cycle;                           \
+    prof_iterations = 1;                                                    \
+    prof_units = units;                                                     \
+})
+
+#define prof_measure(func, ...) ({                                          \
+    printf("%s: ...", #func);                                               \
+    fflush(stdout);                                                         \
+                                                                            \
+    prof_units = "cycles";                                                  \
+    prof_cycle_t runs[PROF_RUNS];                                           \
+    for (int i = 0; i < PROF_RUNS; i++) {                                   \
+        prof_accum_cycle = 0;                                               \
+        prof_iterations = 0;                                                \
+        func(__VA_ARGS__);                                                  \
+        runs[i] = prof_accum_cycle / prof_iterations;                       \
+    }                                                                       \
+                                                                            \
+    prof_cycle_t res = runs[0];                                             \
+    for (int i = 0; i < PROF_RUNS; i++) {                                   \
+        if (runs[i] < res) {                                                \
+            res = runs[i];                                                  \
+        }                                                                   \
+    }                                                                       \
+    res -= prof_baseline_cycle;                                             \
+    printf("\r%s: %"PRIu64" %s", #func, res, prof_units);                   \
+                                                                            \
+    if (!isatty(0)) {                                                       \
+        prof_cycle_t prev;                                                  \
+        while (scanf("%*[^0-9]%"PRIu64, &prev) == 0);                       \
+        int64_t perc = 100*((int64_t)prev - (int64_t)res) / (int64_t)prev;  \
+                                                                            \
+        if (perc > 10) {                                                    \
+            printf(" (\e[32m%+"PRId64"%%\e[0m)", perc);                     \
+        } else if (perc < -10) {                                            \
+            printf(" (\e[31m%+"PRId64"%%\e[0m)", perc);                     \
+        } else {                                                            \
+            printf(" (%+"PRId64"%%)", perc);                                \
+        }                                                                   \
+    }                                                                       \
+                                                                            \
+    printf("\n");                                                           \
+    res;                                                                    \
+})
+
+#define prof_baseline(func, ...) ({                                         \
+    prof_baseline_cycle = 0;                                                \
+    prof_baseline_cycle = prof_measure(func, __VA_ARGS__);                  \
+})
+
+
+// Various test functions
+void no_func(void *eh) {
+}
+
+
+// Actual performance tests
+void baseline_prof(void) {
+    prof_loop() {
+        prof_start();
+        __asm__ volatile ("");
+        prof_stop();
+    }
+}
+
+void equeue_tick_prof(void) {
+    prof_volatile(unsigned) res;
+    prof_loop() {
+        prof_start();
+        res = equeue_tick();
+        prof_stop();
+    }
+}
+
+void equeue_alloc_prof(void) {
+    struct equeue q;
+    equeue_create(&q, 32*EQUEUE_EVENT_SIZE);
+
+    prof_loop() {
+        prof_start();
+        void *e = equeue_alloc(&q, 8 * sizeof(int));
+        prof_stop();
+
+        equeue_dealloc(&q, e);
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_alloc_many_prof(int count) {
+    struct equeue q;
+    equeue_create(&q, count*EQUEUE_EVENT_SIZE);
+
+    void *es[count];
+
+    for (int i = 0; i < count; i++) {
+        es[i] = equeue_alloc(&q, (i % 4) * sizeof(int));
+    }
+
+    for (int i = 0; i < count; i++) {
+        equeue_dealloc(&q, es[i]);
+    }
+
+    prof_loop() {
+        prof_start();
+        void *e = equeue_alloc(&q, 8 * sizeof(int));
+        prof_stop();
+
+        equeue_dealloc(&q, e);
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_post_prof(void) {
+    struct equeue q;
+    equeue_create(&q, EQUEUE_EVENT_SIZE);
+
+    prof_loop() {
+        void *e = equeue_alloc(&q, 0);
+
+        prof_start();
+        int id = equeue_post(&q, no_func, e);
+        prof_stop();
+
+        equeue_cancel(&q, id);
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_post_many_prof(int count) {
+    struct equeue q;
+    equeue_create(&q, count*EQUEUE_EVENT_SIZE);
+
+    for (int i = 0; i < count-1; i++) {
+        equeue_call(&q, no_func, 0);
+    }
+
+    prof_loop() {
+        void *e = equeue_alloc(&q, 0);
+
+        prof_start();
+        int id = equeue_post(&q, no_func, e);
+        prof_stop();
+
+        equeue_cancel(&q, id);
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_post_future_prof(void) {
+    struct equeue q;
+    equeue_create(&q, EQUEUE_EVENT_SIZE);
+
+    prof_loop() {
+        void *e = equeue_alloc(&q, 0);
+        equeue_event_delay(e, 1000);
+
+        prof_start();
+        int id = equeue_post(&q, no_func, e);
+        prof_stop();
+
+        equeue_cancel(&q, id);
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_post_future_many_prof(int count) {
+    struct equeue q;
+    equeue_create(&q, count*EQUEUE_EVENT_SIZE);
+
+    for (int i = 0; i < count-1; i++) {
+        equeue_call(&q, no_func, 0);
+    }
+
+    prof_loop() {
+        void *e = equeue_alloc(&q, 0);
+        equeue_event_delay(e, 1000);
+
+        prof_start();
+        int id = equeue_post(&q, no_func, e);
+        prof_stop();
+
+        equeue_cancel(&q, id);
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_dispatch_prof(void) {
+    struct equeue q;
+    equeue_create(&q, EQUEUE_EVENT_SIZE);
+
+    prof_loop() {
+        equeue_call(&q, no_func, 0);
+
+        prof_start();
+        equeue_dispatch(&q, 0);
+        prof_stop();
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_dispatch_many_prof(int count) {
+    struct equeue q;
+    equeue_create(&q, count*EQUEUE_EVENT_SIZE);
+
+    prof_loop() {
+        for (int i = 0; i < count; i++) {
+            equeue_call(&q, no_func, 0);
+        }
+
+        prof_start();
+        equeue_dispatch(&q, 0);
+        prof_stop();
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_cancel_prof(void) {
+    struct equeue q;
+    equeue_create(&q, EQUEUE_EVENT_SIZE);
+
+    prof_loop() {
+        int id = equeue_call(&q, no_func, 0);
+
+        prof_start();
+        equeue_cancel(&q, id);
+        prof_stop();
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_cancel_many_prof(int count) {
+    struct equeue q;
+    equeue_create(&q, count*EQUEUE_EVENT_SIZE);
+
+    for (int i = 0; i < count-1; i++) {
+        equeue_call(&q, no_func, 0);
+    }
+
+    prof_loop() {
+        int id = equeue_call(&q, no_func, 0);
+
+        prof_start();
+        equeue_cancel(&q, id);
+        prof_stop();
+    }
+
+    equeue_destroy(&q);
+}
+
+void equeue_alloc_size_prof(void) {
+    size_t size = 32*EQUEUE_EVENT_SIZE;
+
+    struct equeue q;
+    equeue_create(&q, size);
+    equeue_alloc(&q, 0);
+
+    prof_result(size - q.slab.size, "bytes");
+
+    equeue_destroy(&q);
+}
+
+void equeue_alloc_many_size_prof(int count) {
+    size_t size = count*EQUEUE_EVENT_SIZE;
+
+    struct equeue q;
+    equeue_create(&q, size);
+
+    for (int i = 0; i < count; i++) {
+        equeue_alloc(&q, (i % 4) * sizeof(int));
+    }
+
+    prof_result(size - q.slab.size, "bytes");
+
+    equeue_destroy(&q);
+}
+
+void equeue_alloc_fragmented_size_prof(int count) {
+    size_t size = count*EQUEUE_EVENT_SIZE;
+
+    struct equeue q;
+    equeue_create(&q, size);
+
+    void *es[count];
+
+    for (int i = 0; i < count; i++) {
+        es[i] = equeue_alloc(&q, (i % 4) * sizeof(int));
+    }
+
+    for (int i = 0; i < count; i++) {
+        equeue_dealloc(&q, es[i]);
+    }
+
+    for (int i = count-1; i >= 0; i--) {
+        es[i] = equeue_alloc(&q, (i % 4) * sizeof(int));
+    }
+
+    for (int i = count-1; i >= 0; i--) {
+        equeue_dealloc(&q, es[i]);
+    }
+
+    for (int i = 0; i < count; i++) {
+        equeue_alloc(&q, (i % 4) * sizeof(int));
+    }
+
+    prof_result(size - q.slab.size, "bytes");
+
+    equeue_destroy(&q);
+}
+
+
+// Entry point
+int main() {
+    printf("beginning profiling...\n");
+
+    prof_baseline(baseline_prof);
+
+    prof_measure(equeue_tick_prof);
+    prof_measure(equeue_alloc_prof);
+    prof_measure(equeue_post_prof);
+    prof_measure(equeue_post_future_prof);
+    prof_measure(equeue_dispatch_prof);
+    prof_measure(equeue_cancel_prof);
+
+    prof_measure(equeue_alloc_many_prof, 1000);
+    prof_measure(equeue_post_many_prof, 1000);
+    prof_measure(equeue_post_future_many_prof, 1000);
+    prof_measure(equeue_dispatch_many_prof, 100);
+    prof_measure(equeue_cancel_many_prof, 100);
+
+    prof_measure(equeue_alloc_size_prof);
+    prof_measure(equeue_alloc_many_size_prof, 1000);
+    prof_measure(equeue_alloc_fragmented_size_prof, 1000);
+
+    printf("done!\n");
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/tests/tests.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/tests/tests.c
new file mode 100755
index 0000000..57212de
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/equeue/tests/tests.c
@@ -0,0 +1,718 @@
+/*
+ * Testing framework for the events library
+ *
+ * Copyright (c) 2016 Christopher Haster
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "equeue.h"
+#include <unistd.h>
+#include <stdio.h>
+#include <setjmp.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <pthread.h>
+
+
+// Testing setup
+static jmp_buf test_buf;
+static int test_line;
+static int test_failure;
+
+#define test_assert(test) ({                                                \
+    if (!(test)) {                                                          \
+        test_line = __LINE__;                                               \
+        longjmp(test_buf, 1);                                               \
+    }                                                                       \
+})
+
+#define test_run(func, ...) ({                                              \
+    printf("%s: ...", #func);                                               \
+    fflush(stdout);                                                         \
+                                                                            \
+    if (!setjmp(test_buf)) {                                                \
+        func(__VA_ARGS__);                                                  \
+        printf("\r%s: \e[32mpassed\e[0m\n", #func);                         \
+    } else {                                                                \
+        printf("\r%s: \e[31mfailed\e[0m at line %d\n", #func, test_line);   \
+        test_failure = true;                                                \
+    }                                                                       \
+})
+
+
+// Test functions
+void pass_func(void *eh) {
+}
+
+void simple_func(void *p) {
+    (*(int *)p)++;
+}
+
+void sloth_func(void *p) {
+    usleep(10000);
+    (*(int *)p)++;
+}
+
+struct indirect {
+    int *touched;
+    uint8_t buffer[7];
+};
+
+void indirect_func(void *p) {
+    struct indirect *i = (struct indirect*)p;
+    (*i->touched)++;
+}
+
+struct timing {
+    unsigned tick;
+    unsigned delay;
+};
+
+void timing_func(void *p) {
+    struct timing *timing = (struct timing*)p;
+    unsigned tick = equeue_tick();
+
+    unsigned t1 = timing->delay;
+    unsigned t2 = tick - timing->tick;
+    test_assert(t1 > t2 - 10 && t1 < t2 + 10);
+
+    timing->tick = tick;
+}
+
+struct fragment {
+    equeue_t *q;
+    size_t size;
+    struct timing timing;
+};
+
+void fragment_func(void *p) {
+    struct fragment *fragment = (struct fragment*)p;
+    timing_func(&fragment->timing);
+
+    struct fragment *nfragment = equeue_alloc(fragment->q, fragment->size);
+    test_assert(nfragment);
+
+    *nfragment = *fragment;
+    equeue_event_delay(nfragment, fragment->timing.delay);
+
+    int id = equeue_post(nfragment->q, fragment_func, nfragment);
+    test_assert(id);
+}
+
+struct cancel {
+    equeue_t *q;
+    int id;
+};
+
+void cancel_func(void *p) {
+    struct cancel *cancel = (struct cancel *)p;
+    equeue_cancel(cancel->q, cancel->id);
+}
+
+struct nest {
+    equeue_t *q;
+    void (*cb)(void *);
+    void *data;
+};
+
+void nest_func(void *p) {
+    struct nest *nest = (struct nest *)p;
+    equeue_call(nest->q, nest->cb, nest->data);
+
+    usleep(10000);
+}
+
+
+// Simple call tests
+void simple_call_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    bool touched = false;
+    equeue_call(&q, simple_func, &touched);
+    equeue_dispatch(&q, 0);
+    test_assert(touched);
+
+    equeue_destroy(&q);
+}
+
+void simple_call_in_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    bool touched = false;
+    int id = equeue_call_in(&q, 10, simple_func, &touched);
+    test_assert(id);
+
+    equeue_dispatch(&q, 15);
+    test_assert(touched);
+
+    equeue_destroy(&q);
+}
+
+void simple_call_every_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    bool touched = false;
+    int id = equeue_call_every(&q, 10, simple_func, &touched);
+    test_assert(id);
+
+    equeue_dispatch(&q, 15);
+    test_assert(touched);
+
+    equeue_destroy(&q);
+}
+
+void simple_post_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int touched = false;
+    struct indirect *i = equeue_alloc(&q, sizeof(struct indirect));
+    test_assert(i);
+
+    i->touched = &touched;
+    int id = equeue_post(&q, indirect_func, i);
+    test_assert(id);
+
+    equeue_dispatch(&q, 0);
+    test_assert(*i->touched);
+
+    equeue_destroy(&q);
+}
+
+// Misc tests
+void destructor_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int touched;
+    struct indirect *e;
+    int ids[3];
+
+    touched = 0;
+    for (int i = 0; i < 3; i++) {
+        e = equeue_alloc(&q, sizeof(struct indirect));
+        test_assert(e);
+
+        e->touched = &touched;
+        equeue_event_dtor(e, indirect_func);
+        int id = equeue_post(&q, pass_func, e);
+        test_assert(id);
+    }
+
+    equeue_dispatch(&q, 0);
+    test_assert(touched == 3);
+
+    touched = 0;
+    for (int i = 0; i < 3; i++) {
+        e = equeue_alloc(&q, sizeof(struct indirect));
+        test_assert(e);
+
+        e->touched = &touched;
+        equeue_event_dtor(e, indirect_func);
+        ids[i] = equeue_post(&q, pass_func, e);
+        test_assert(ids[i]);
+    }
+
+    for (int i = 0; i < 3; i++) {
+        equeue_cancel(&q, ids[i]);
+    }
+
+    equeue_dispatch(&q, 0);
+    test_assert(touched == 3);
+
+    touched = 0;
+    for (int i = 0; i < 3; i++) {
+        e = equeue_alloc(&q, sizeof(struct indirect));
+        test_assert(e);
+
+        e->touched = &touched;
+        equeue_event_dtor(e, indirect_func);
+        int id = equeue_post(&q, pass_func, e);
+        test_assert(id);
+    }
+
+    equeue_destroy(&q);
+    test_assert(touched == 3);
+}
+
+void allocation_failure_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    void *p = equeue_alloc(&q, 4096);
+    test_assert(!p);
+
+    for (int i = 0; i < 100; i++) {
+        p = equeue_alloc(&q, 0);
+    }
+    test_assert(!p);
+
+    equeue_destroy(&q);
+}
+
+void cancel_test(int N) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    bool touched = false;
+    int *ids = malloc(N*sizeof(int));
+
+    for (int i = 0; i < N; i++) {
+        ids[i] = equeue_call(&q, simple_func, &touched);
+    }
+
+    for (int i = N-1; i >= 0; i--) {
+        equeue_cancel(&q, ids[i]);
+    }
+
+    free(ids);
+
+    equeue_dispatch(&q, 0);
+    test_assert(!touched);
+
+    equeue_destroy(&q);
+}
+
+void cancel_inflight_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    bool touched = false;
+
+    int id = equeue_call(&q, simple_func, &touched);
+    equeue_cancel(&q, id);
+
+    equeue_dispatch(&q, 0);
+    test_assert(!touched);
+
+    id = equeue_call(&q, simple_func, &touched);
+    equeue_cancel(&q, id);
+
+    equeue_dispatch(&q, 0);
+    test_assert(!touched);
+
+    struct cancel *cancel = equeue_alloc(&q, sizeof(struct cancel));
+    test_assert(cancel);
+    cancel->q = &q;
+    cancel->id = 0;
+
+    id = equeue_post(&q, cancel_func, cancel);
+    test_assert(id);
+
+    cancel->id = equeue_call(&q, simple_func, &touched);
+
+    equeue_dispatch(&q, 0);
+    test_assert(!touched);
+
+    equeue_destroy(&q);
+}
+
+void cancel_unnecessarily_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int id = equeue_call(&q, pass_func, 0);
+    for (int i = 0; i < 5; i++) {
+        equeue_cancel(&q, id);
+    }
+
+    id = equeue_call(&q, pass_func, 0);
+    equeue_dispatch(&q, 0);
+    for (int i = 0; i < 5; i++) {
+        equeue_cancel(&q, id);
+    }
+
+    bool touched = false;
+    equeue_call(&q, simple_func, &touched);
+    for (int i = 0; i < 5; i++) {
+        equeue_cancel(&q, id);
+    }
+
+    equeue_dispatch(&q, 0);
+    test_assert(touched);
+
+    equeue_destroy(&q);
+}
+
+void loop_protect_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    bool touched = false;
+    equeue_call_every(&q, 0, simple_func, &touched);
+
+    equeue_dispatch(&q, 0);
+    test_assert(touched);
+
+    touched = false;
+    equeue_call_every(&q, 1, simple_func, &touched);
+
+    equeue_dispatch(&q, 0);
+    test_assert(touched);
+
+    equeue_destroy(&q);
+}
+
+void break_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    bool touched = false;
+    equeue_call_every(&q, 0, simple_func, &touched);
+
+    equeue_break(&q);
+    equeue_dispatch(&q, -1);
+    test_assert(touched);
+
+    equeue_destroy(&q);
+}
+
+void period_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int count = 0;
+    equeue_call_every(&q, 10, simple_func, &count);
+
+    equeue_dispatch(&q, 55);
+    test_assert(count == 5);
+
+    equeue_destroy(&q);
+}
+
+void nested_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int touched = 0;
+    struct nest *nest = equeue_alloc(&q, sizeof(struct nest));
+    test_assert(nest);
+    nest->q = &q;
+    nest->cb = simple_func;
+    nest->data = &touched;
+
+    int id = equeue_post(&q, nest_func, nest);
+    test_assert(id);
+
+    equeue_dispatch(&q, 5);
+    test_assert(touched == 0);
+
+    equeue_dispatch(&q, 5);
+    test_assert(touched == 1);
+
+    touched = 0;
+    nest = equeue_alloc(&q, sizeof(struct nest));
+    test_assert(nest);
+    nest->q = &q;
+    nest->cb = simple_func;
+    nest->data = &touched;
+
+    id = equeue_post(&q, nest_func, nest);
+    test_assert(id);
+
+    equeue_dispatch(&q, 20);
+    test_assert(touched == 1);
+
+    equeue_destroy(&q);
+}
+
+void sloth_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int touched = 0;
+    int id = equeue_call(&q, sloth_func, &touched);
+    test_assert(id);
+
+    id = equeue_call_in(&q, 5, simple_func, &touched);
+    test_assert(id);
+
+    id = equeue_call_in(&q, 15, simple_func, &touched);
+    test_assert(id);
+
+    equeue_dispatch(&q, 20);
+    test_assert(touched == 3);
+
+    equeue_destroy(&q);
+}
+
+void *multithread_thread(void *p) {
+    equeue_t *q = (equeue_t *)p;
+    equeue_dispatch(q, -1);
+    return 0;
+}
+
+void multithread_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int touched = 0;
+    equeue_call_every(&q, 1, simple_func, &touched);
+
+    pthread_t thread;
+    err = pthread_create(&thread, 0, multithread_thread, &q);
+    test_assert(!err);
+
+    usleep(10000);
+    equeue_break(&q);
+    err = pthread_join(thread, 0);
+    test_assert(!err);
+
+    test_assert(touched);
+
+    equeue_destroy(&q);
+}
+
+void background_func(void *p, int ms) {
+    *(unsigned *)p = ms;
+}
+
+void background_test(void) {
+    equeue_t q;
+    int err = equeue_create(&q, 2048);
+    test_assert(!err);
+
+    int id = equeue_call_in(&q, 20, pass_func, 0);
+    test_assert(id);
+
+    unsigned ms;
+    equeue_background(&q, background_func, &ms);
+    test_assert(ms == 20);
+
+    id = equeue_call_in(&q, 10, pass_func, 0);
+    test_assert(id);
+    test_assert(ms == 10);
+
+    id = equeue_call(&q, pass_func, 0);
+    test_assert(id);
+    test_assert(ms == 0);
+
+    equeue_dispatch(&q, 0);
+    test_assert(ms == 10);
+
+    equeue_destroy(&q);
+    test_assert(ms == -1);
+}
+
+void chain_test(void) {
+    equeue_t q1;
+    int err = equeue_create(&q1, 2048);
+    test_assert(!err);
+
+    equeue_t q2;
+    err = equeue_create(&q2, 2048);
+    test_assert(!err);
+
+    equeue_chain(&q2, &q1);
+
+    int touched = 0;
+
+    int id1 = equeue_call_in(&q1, 20, simple_func, &touched);
+    int id2 = equeue_call_in(&q2, 20, simple_func, &touched);
+    test_assert(id1 && id2);
+
+    id1 = equeue_call(&q1, simple_func, &touched);
+    id2 = equeue_call(&q2, simple_func, &touched);
+    test_assert(id1 && id2);
+
+    id1 = equeue_call_in(&q1, 5, simple_func, &touched);
+    id2 = equeue_call_in(&q2, 5, simple_func, &touched);
+    test_assert(id1 && id2);
+
+    equeue_cancel(&q1, id1);
+    equeue_cancel(&q2, id2);
+
+    id1 = equeue_call_in(&q1, 10, simple_func, &touched);
+    id2 = equeue_call_in(&q2, 10, simple_func, &touched);
+    test_assert(id1 && id2);
+
+    equeue_dispatch(&q1, 30);
+
+    test_assert(touched == 6);
+
+    equeue_destroy(&q1);
+    equeue_destroy(&q2);
+}
+
+void unchain_test(void) {
+    equeue_t q1;
+    int err = equeue_create(&q1, 2048);
+    test_assert(!err);
+
+    equeue_t q2;
+    err = equeue_create(&q2, 2048);
+    test_assert(!err);
+
+    equeue_chain(&q2, &q1);
+
+    int touched = 0;
+    int id1 = equeue_call(&q1, simple_func, &touched);
+    int id2 = equeue_call(&q2, simple_func, &touched);
+    test_assert(id1 && id2);
+
+    equeue_dispatch(&q1, 0);
+    test_assert(touched == 2);
+
+    equeue_chain(&q2, 0);
+    equeue_chain(&q1, &q2);
+
+    id1 = equeue_call(&q1, simple_func, &touched);
+    id2 = equeue_call(&q2, simple_func, &touched);
+    test_assert(id1 && id2);
+
+    equeue_dispatch(&q2, 0);
+    test_assert(touched == 4);
+
+    equeue_destroy(&q1);
+    equeue_destroy(&q2);
+}
+
+// Barrage tests
+void simple_barrage_test(int N) {
+    equeue_t q;
+    int err = equeue_create(&q, N*(EQUEUE_EVENT_SIZE+sizeof(struct timing)));
+    test_assert(!err);
+
+    for (int i = 0; i < N; i++) {
+        struct timing *timing = equeue_alloc(&q, sizeof(struct timing));
+        test_assert(timing);
+
+        timing->tick = equeue_tick();
+        timing->delay = (i+1)*100;
+        equeue_event_delay(timing, timing->delay);
+        equeue_event_period(timing, timing->delay);
+
+        int id = equeue_post(&q, timing_func, timing);
+        test_assert(id);
+    }
+
+    equeue_dispatch(&q, N*100);
+
+    equeue_destroy(&q);
+}
+
+void fragmenting_barrage_test(int N) {
+    equeue_t q;
+    int err = equeue_create(&q,
+            2*N*(EQUEUE_EVENT_SIZE+sizeof(struct fragment)+N*sizeof(int)));
+    test_assert(!err);
+
+    for (int i = 0; i < N; i++) {
+        size_t size = sizeof(struct fragment) + i*sizeof(int);
+        struct fragment *fragment = equeue_alloc(&q, size);
+        test_assert(fragment);
+
+        fragment->q = &q;
+        fragment->size = size;
+        fragment->timing.tick = equeue_tick();
+        fragment->timing.delay = (i+1)*100;
+        equeue_event_delay(fragment, fragment->timing.delay);
+
+        int id = equeue_post(&q, fragment_func, fragment);
+        test_assert(id);
+    }
+
+    equeue_dispatch(&q, N*100);
+
+    equeue_destroy(&q);
+}
+
+struct ethread {
+    pthread_t thread;
+    equeue_t *q;
+    int ms;
+};
+
+static void *ethread_dispatch(void *p) {
+    struct ethread *t = (struct ethread*)p;
+    equeue_dispatch(t->q, t->ms);
+    return 0;
+}
+
+void multithreaded_barrage_test(int N) {
+    equeue_t q;
+    int err = equeue_create(&q, N*(EQUEUE_EVENT_SIZE+sizeof(struct timing)));
+    test_assert(!err);
+
+    struct ethread t;
+    t.q = &q;
+    t.ms = N*100;
+    err = pthread_create(&t.thread, 0, ethread_dispatch, &t);
+    test_assert(!err);
+
+    for (int i = 0; i < N; i++) {
+        struct timing *timing = equeue_alloc(&q, sizeof(struct timing));
+        test_assert(timing);
+
+        timing->tick = equeue_tick();
+        timing->delay = (i+1)*100;
+        equeue_event_delay(timing, timing->delay);
+        equeue_event_period(timing, timing->delay);
+
+        int id = equeue_post(&q, timing_func, timing);
+        test_assert(id);
+    }
+
+    err = pthread_join(t.thread, 0);
+    test_assert(!err);
+
+    equeue_destroy(&q);
+}
+
+
+int main() {
+    printf("beginning tests...\n");
+
+    test_run(simple_call_test);
+    test_run(simple_call_in_test);
+    test_run(simple_call_every_test);
+    test_run(simple_post_test);
+    test_run(destructor_test);
+    test_run(allocation_failure_test);
+    test_run(cancel_test, 20);
+    test_run(cancel_inflight_test);
+    test_run(cancel_unnecessarily_test);
+    test_run(loop_protect_test);
+    test_run(break_test);
+    test_run(period_test);
+    test_run(nested_test);
+    test_run(sloth_test);
+    test_run(background_test);
+    test_run(chain_test);
+    test_run(unchain_test);
+    test_run(multithread_test);
+    test_run(simple_barrage_test, 20);
+    test_run(fragmenting_barrage_test, 20);
+    test_run(multithreaded_barrage_test, 20);
+
+    printf("done!\n");
+    return test_failure;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_events.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_events.h
new file mode 100755
index 0000000..b313cd2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_events.h
@@ -0,0 +1,40 @@
+
+/** \addtogroup events */
+/** @{*/
+/* events
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_EVENTS_H
+#define MBED_EVENTS_H
+
+
+#include "equeue/equeue.h"
+
+
+#ifdef __cplusplus
+
+#include "events/EventQueue.h"
+#include "events/Event.h"
+
+#include "events/mbed_shared_queues.h"
+
+using namespace events;
+
+#endif
+
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_lib.json
new file mode 100755
index 0000000..0f786f6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_lib.json
@@ -0,0 +1,26 @@
+{
+    "name": "events",
+    "config": {
+        "present": 1,
+        "shared-stacksize": {
+            "help": "Stack size (bytes) for shared event queue thread",
+            "value": 1024
+        },
+        "shared-eventsize": {
+            "help": "Event buffer size (bytes) for shared event queue",
+            "value": 256
+        },
+        "shared-dispatch-from-application": {
+            "help": "No thread created for shared event queue - application will call dispatch from another thread (eg dispatch_forever at end of main)",
+            "value": false
+        },
+        "shared-highprio-stacksize": {
+            "help": "Stack size (bytes) for shared high-priority event queue thread",
+            "value": 1024
+        },
+        "shared-highprio-eventsize": {
+            "help": "Event buffer size (bytes) for shared high-priority event queue",
+            "value": 256
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_shared_queues.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_shared_queues.cpp
new file mode 100755
index 0000000..b227d8d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_shared_queues.cpp
@@ -0,0 +1,72 @@
+/* events
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "events/mbed_shared_queues.h"
+#include "mbed.h"
+
+using namespace events;
+
+namespace mbed {
+
+#ifdef MBED_CONF_RTOS_PRESENT
+/* Create an event queue, and start the thread that dispatches it. Static
+ * variables mean this happens once the first time each template instantiation
+ * is called. This is currently instantiated no more than twice.
+ */
+template
+<osPriority Priority, size_t QueueSize, size_t StackSize>
+EventQueue *do_shared_event_queue_with_thread()
+{
+    static uint64_t queue_buffer[QueueSize / sizeof(uint64_t)];
+    static EventQueue queue(sizeof queue_buffer, (unsigned char *) queue_buffer);
+
+    static uint64_t stack[StackSize / sizeof(uint64_t)];
+    static Thread thread(Priority, StackSize, (unsigned char *) stack);
+
+    Thread::State state = thread.get_state();
+    if (state == Thread::Inactive || state == Thread::Deleted) {
+        osStatus status = thread.start(callback(&queue, &EventQueue::dispatch_forever));
+        MBED_ASSERT(status == osOK);
+        if (status != osOK) {
+            return NULL;
+        }
+    }
+
+    return &queue;
+}
+#endif
+
+EventQueue *mbed_event_queue()
+{
+#if MBED_CONF_EVENTS_SHARED_DISPATCH_FROM_APPLICATION || !defined MBED_CONF_RTOS_PRESENT
+    /* Only create the EventQueue, but no dispatching thread */
+    static unsigned char queue_buffer[MBED_CONF_EVENTS_SHARED_EVENTSIZE];
+    static EventQueue queue(sizeof queue_buffer, queue_buffer);
+
+    return &queue;
+#else
+    return do_shared_event_queue_with_thread<osPriorityNormal, MBED_CONF_EVENTS_SHARED_EVENTSIZE, MBED_CONF_EVENTS_SHARED_STACKSIZE>();
+#endif
+}
+
+#ifdef MBED_CONF_RTOS_PRESENT
+EventQueue *mbed_highprio_event_queue()
+{
+    return do_shared_event_queue_with_thread<osPriorityHigh, MBED_CONF_EVENTS_SHARED_HIGHPRIO_EVENTSIZE, MBED_CONF_EVENTS_SHARED_HIGHPRIO_STACKSIZE>();
+}
+#endif
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_shared_queues.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_shared_queues.h
new file mode 100755
index 0000000..e56f6bf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/events/mbed_shared_queues.h
@@ -0,0 +1,81 @@
+
+/** \addtogroup events */
+/** @{*/
+/* events
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SHARED_QUEUES_H
+#define MBED_SHARED_QUEUES_H
+
+#include "events/EventQueue.h"
+
+namespace mbed {
+
+/**
+ * Return a pointer to an EventQueue, on which normal tasks can be queued.
+ *
+ * All calls to this return the same EventQueue - it and its dispatch thread
+ * are created on the first call to this function. The dispatch thread
+ * runs at default priority (currently osPriorityNormal).
+ *
+ * The EventQueue returned may be used to call() Events, or to chain() other
+ * EventQueues so that they are run in the same context.
+ *
+ * Events (or chained EventQueues) executing on the normal event queue should
+ * normally take less than 10ms to execute, to avoid starving other users. As
+ * such, users can expect that event latency will typically be 10ms or less,
+ * but could occasionally be significantly higher if many events are queued.
+ *
+ * If an RTOS is not present or the configuration option
+ * `events.shared-dispatch-from-application` is set to true, then this
+ * does not create a dedicated dispatch thread - instead the application is
+ * expected to run the EventQueue's dispatch, eg from main. This is necessary
+ * for the event loop to work without an RTOS, or an RTOS system can can save
+ * memory by reusing the main stack.
+ *
+ * @return pointer to event queue
+ */
+events::EventQueue *mbed_event_queue();
+
+#ifdef MBED_CONF_RTOS_PRESENT
+/**
+ * Return a pointer to an EventQueue, on which small high-priority tasks can
+ * be queues, such as simple deferrals from interrupt.
+ *
+ * All calls to this return the same EventQueue - it and its thread are
+ * created on the first call to this function. The dispatch thread
+ * runs at a high priority (currently osPriorityHigh).
+ *
+ * The EventQueue returned may be used to call() Events, or to chain() other
+ * EventQueues so that they are run in the same context.
+ *
+ * Events (or chained EventQueues) executing on the high-priority event queue
+ * should normally take less than 100us to execute, to avoid starving other
+ * users. As such, users can expect that event latency will typically be 100us
+ * or less, but could occasionally be significantly higher if many events are
+ * queued.
+ *
+ * @return pointer to high-priority event queue
+ */
+
+events::EventQueue *mbed_highprio_event_queue();
+
+#endif // MBED_CONF_RTOS_PRESENT
+
+};
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c
new file mode 100755
index 0000000..6bb9b4f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c
@@ -0,0 +1,169 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+
+#define MBED_FLASH_ALGO_ERASE   1UL
+#define MBED_FLASH_ALGO_PROGRAM 2UL
+
+extern uint32_t SystemCoreClock;
+
+/*
+    This binary blob (thumb code) sets r9 (static base) as the code we are jumping to
+    is PIC (position independent code).
+
+    These are the instructions (r0 is a pointer to arg_t):
+        push {r5, lr, r4}
+        mov r5, r9
+        push {r5}
+        ldr r5, [r0, #20]
+        ldr r3, [r0, #16]
+        mov r9, r3
+        ldr r3, [r0, #12]
+        ldr r2, [r0, #8]
+        ldr r1, [r0, #4]
+        ldr r0, [r0, #0]
+        blx r5
+        pop {r5}
+        mov r9, r5
+        pop {r4-r5, pc}
+        bx r14
+*/
+static uint32_t jump_to_flash_algo[] = {
+    0x464DB530,
+    0x6945B420,
+    0x46996903,
+    0x688268C3,
+    0x68006841,
+    0xBC2047A8,
+    0xBD3046A9
+};
+
+// should be called within critical section
+static int32_t flash_algo_init(flash_t *obj, uint32_t address, uint32_t function)
+{
+    args_t arguments = {
+        .r0 = address,
+        .r1 = SystemCoreClock,
+        .r2 = function,
+        .r3 = 0,
+        .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+        .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->init
+    };
+    return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+}
+
+// should be called within critical section
+static int32_t flash_algo_uninit(flash_t *obj, uint32_t address, uint32_t function)
+{
+    args_t arguments = {
+        .r0 = address,
+        .r1 = SystemCoreClock,
+        .r2 = function,
+        .r3 = 0,
+        .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+        .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->uninit
+    };
+    return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+}
+
+
+int32_t flash_init(flash_t *obj)
+{
+    flash_set_target_config(obj);
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    core_util_critical_section_enter();
+    flash_algo_init(obj, address, MBED_FLASH_ALGO_ERASE);
+
+    args_t arguments = {
+        .r0 = address,
+        .r1 = 0,
+        .r2 = 0,
+        .r3 = 0,
+        .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+        .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->erase_sector
+    };
+    int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+
+    flash_algo_uninit(obj, address, MBED_FLASH_ALGO_ERASE);
+    core_util_critical_section_exit();
+    return ret ? -1 : 0;
+}
+
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    core_util_critical_section_enter();
+    flash_algo_init(obj, address, MBED_FLASH_ALGO_PROGRAM);
+
+    args_t arguments = {
+        .r0 = address,
+        .r1 = size,
+        .r2 = (uint32_t)data,
+        .r3 = 0,
+        .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+        .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->program_page
+    };
+    int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+
+    flash_algo_uninit(obj, address, MBED_FLASH_ALGO_PROGRAM);
+    core_util_critical_section_exit();
+    return ret ? -1 : 0;
+}
+
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    const sector_info_t *sectors = obj->target_config->sectors;
+
+    if (address >= obj->target_config->flash_start + obj->target_config->flash_size) {
+        return MBED_FLASH_INVALID_SIZE;
+    }
+
+    int sector_index = obj->target_config->sector_info_count - 1;
+    for (; sector_index >= 0; sector_index--) {
+        if (address >= sectors[sector_index].start) {
+            return sectors[sector_index].size;
+        }
+    }
+    return MBED_FLASH_INVALID_SIZE;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return obj->target_config->page_size;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return obj->target_config->flash_start;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return obj->target_config->flash_size;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h
new file mode 100755
index 0000000..e905ad2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FLASH_DATA_H
+#define MBED_FLASH_DATA_H
+
+#include <stdint.h>
+
+// Target flash algorithm structure
+typedef struct {
+    const uint32_t init;
+    const uint32_t uninit;
+    const uint32_t erase_sector;
+    const uint32_t program_page;
+    const uint32_t static_base;
+    uint32_t *algo_blob;
+} flash_algo_t;
+
+typedef struct {
+    const uint32_t start;
+    const uint32_t size;
+} sector_info_t;
+
+typedef struct {
+    const uint32_t page_size;
+    const uint32_t flash_start;
+    const uint32_t flash_size;
+    const sector_info_t *sectors;
+    const uint32_t sector_info_count;
+} flash_target_config_t;
+
+// Target flash configuration
+struct flash_s {
+    const flash_target_config_t *target_config;
+    const flash_algo_t *flash_algo;
+};
+
+typedef struct {
+    uint32_t r0;
+    uint32_t r1;
+    uint32_t r2;
+    uint32_t r3;
+    uint32_t r9;
+    uint32_t pc;
+} args_t;
+
+typedef int32_t (*flash_algo_jump_t)(args_t*);
+
+// prototypes for flash algo CMSIS API
+
+typedef int (*CMSIS_Algo_Function_Init)(unsigned long adr, unsigned long clk, unsigned long fnc);
+typedef int (*CMSIS_Algo_Function_UnInit)(unsigned long fnc);
+typedef int (*CMSIS_Algo_Function_EraseSector)(unsigned long adr);
+typedef int (*CMSIS_Algo_Function_EraseChip)(void);
+typedef int (*CMSIS_Algo_Function_ProgramPage)(unsigned long adr, unsigned long sz, unsigned char *buf);
+typedef unsigned long (*CMSIS_Algo_Function_Verify)(unsigned long adr, unsigned long sz, unsigned char *buf);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set target configuration
+ */
+void flash_set_target_config(flash_t *obj);
+
+#ifdef __cplusplus
+};
+#endif
+
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/analogin_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/analogin_api.h
new file mode 100755
index 0000000..674e1af
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/analogin_api.h
@@ -0,0 +1,71 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogin hal structure. analogin_s is declared in the target's hal
+ */
+typedef struct analogin_s analogin_t;
+
+/**
+ * \defgroup hal_analogin Analogin hal functions
+ * @{
+ */
+
+/** Initialize the analogin peripheral
+ *
+ * Configures the pin used by analogin.
+ * @param obj The analogin object to initialize
+ * @param pin The analogin pin name
+ */
+void analogin_init(analogin_t *obj, PinName pin);
+
+/** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @param obj The analogin object
+ * @return A floating value representing the current input voltage
+ */
+float analogin_read(analogin_t *obj);
+
+/** Read the value from analogin pin, represented as an unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16bit value representing the current input voltage
+ */
+uint16_t analogin_read_u16(analogin_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/analogout_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/analogout_api.h
new file mode 100755
index 0000000..6875b77
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/analogout_api.h
@@ -0,0 +1,93 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogout hal structure. dac_s is declared in the target's hal
+ */
+typedef struct dac_s dac_t;
+
+/**
+ * \defgroup hal_analogout Analogout hal functions
+ * @{
+ */
+
+/** Initialize the analogout peripheral
+ *
+ * Configures the pin used by analogout.
+ * @param obj The analogout object to initialize
+ * @param pin The analogout pin name
+ */
+void analogout_init(dac_t *obj, PinName pin);
+
+/** Release the analogout object
+ *
+ * Note: This is not currently used in the mbed-drivers
+ * @param obj The analogout object
+ */
+void analogout_free(dac_t *obj);
+
+/** Set the output voltage, specified as a percentage (float)
+ *
+ * @param obj The analogin object
+ * @param value The floating-point output voltage to be set
+ */
+void analogout_write(dac_t *obj, float value);
+
+/** Set the output voltage, specified as unsigned 16-bit
+ *
+ * @param obj The analogin object
+ * @param value The unsigned 16-bit output voltage to be set
+ */
+void analogout_write_u16(dac_t *obj, uint16_t value);
+
+/** Read the current voltage value on the pin
+ *
+ * @param obj The analogin object
+ * @return A floating-point value representing the current voltage on the pin,
+ *     measured as a percentage
+ */
+float analogout_read(dac_t *obj);
+
+/** Read the current voltage value on the pin, as a normalized unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16-bit value representing the current voltage on the pin
+ */
+uint16_t analogout_read_u16(dac_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/buffer.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/buffer.h
new file mode 100755
index 0000000..bf01cd6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/buffer.h
@@ -0,0 +1,35 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUFFER_H
+#define MBED_BUFFER_H
+
+#include <stddef.h>
+
+/** Generic buffer structure
+ */
+typedef struct buffer_s {
+    void    *buffer; /**< the pointer to a buffer */
+    size_t   length; /**< the buffer length */
+    size_t   pos;    /**< actual buffer position */
+    uint8_t  width;  /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
+} buffer_t;
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/can_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/can_api.h
new file mode 100755
index 0000000..723342f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/can_api.h
@@ -0,0 +1,86 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "hal/can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    IRQ_RX,
+    IRQ_TX,
+    IRQ_ERROR,
+    IRQ_OVERRUN,
+    IRQ_WAKEUP,
+    IRQ_PASSIVE,
+    IRQ_ARB,
+    IRQ_BUS,
+    IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+    MODE_RESET,
+    MODE_NORMAL,
+    MODE_SILENT,
+    MODE_TEST_LOCAL,
+    MODE_TEST_GLOBAL,
+    MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void          can_init      (can_t *obj, PinName rd, PinName td);
+void          can_init_freq (can_t *obj, PinName rd, PinName td, int hz);
+void          can_free      (can_t *obj);
+int           can_frequency (can_t *obj, int hz);
+
+void          can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void          can_irq_free (can_t *obj);
+void          can_irq_set  (can_t *obj, CanIrqType irq, uint32_t enable);
+
+int           can_write    (can_t *obj, CAN_Message, int cc);
+int           can_read     (can_t *obj, CAN_Message *msg, int handle);
+int           can_mode     (can_t *obj, CanMode mode);
+int           can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
+void          can_reset    (can_t *obj);
+unsigned char can_rderror  (can_t *obj);
+unsigned char can_tderror  (can_t *obj);
+void          can_monitor  (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif    // MBED_CAN_API_H
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/can_helper.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/can_helper.h
new file mode 100755
index 0000000..bf04f4c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/can_helper.h
@@ -0,0 +1,77 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *
+ * \enum    CANFormat
+ *
+ * \brief   Values that represent CAN Format
+**/
+enum CANFormat {
+    CANStandard = 0,
+    CANExtended = 1,
+    CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+/**
+ *
+ * \enum    CANType
+ *
+ * \brief   Values that represent CAN Type
+**/
+enum CANType {
+    CANData   = 0,
+    CANRemote = 1
+};
+typedef enum CANType CANType;
+
+/**
+ *
+ * \struct  CAN_Message
+ *
+ * \brief   Holder for single CAN message.
+ *
+**/
+struct CAN_Message {
+    unsigned int   id;                 // 29 bit identifier
+    unsigned char  data[8];            // Data field
+    unsigned char  len;                // Length of data field in bytes
+    CANFormat      format;             // Format ::CANFormat
+    CANType        type;               // Type ::CANType
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/dma_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/dma_api.h
new file mode 100755
index 0000000..1c9755d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/dma_api.h
@@ -0,0 +1,50 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DMA_API_H
+#define MBED_DMA_API_H
+
+#include <stdint.h>
+
+#define DMA_ERROR_OUT_OF_CHANNELS (-1)
+
+typedef enum {
+    DMA_USAGE_NEVER,
+    DMA_USAGE_OPPORTUNISTIC,
+    DMA_USAGE_ALWAYS,
+    DMA_USAGE_TEMPORARY_ALLOCATED,
+    DMA_USAGE_ALLOCATED
+} DMAUsage;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void dma_init(void);
+
+int dma_channel_allocate(uint32_t capabilities);
+
+int dma_channel_free(int channelid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/emac_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/emac_api.h
new file mode 100755
index 0000000..e5fbd1a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/emac_api.h
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_EMAC_API_H
+#define MBED_EMAC_API_H
+
+#if DEVICE_EMAC
+
+#include <stdbool.h>
+#include "emac_stack_mem.h"
+
+typedef struct emac_interface emac_interface_t;
+
+/**
+ * EmacInterface
+ *
+ * This interface should be used to abstract low level access to networking hardware
+ */
+
+/**
+ * Callback to be register with Emac interface and to be called fore received packets
+ *
+ * @param data Arbitrary user data (IP stack)
+ * @param buf  Received data
+ */
+typedef void (*emac_link_input_fn)(void *data, emac_stack_mem_chain_t *buf);
+
+/**
+ * Callback to be register with Emac interface and to be called for link status changes
+ *
+ * @param  data Arbitrary user data (IP stack)
+ * @param  up   Link status
+ */
+typedef void (*emac_link_state_change_fn)(void *data, bool up);
+
+/**
+ * Return maximum transmission unit
+ *
+ * @param emac Emac interface
+ * @return     MTU in bytes
+ */
+typedef uint32_t (*emac_get_mtu_size_fn)(emac_interface_t *emac);
+
+/**
+ * Return interface name
+ *
+ * @param emac Emac interface
+ * @param name Pointer to where the name should be written
+ * @param size Maximum number of character to copy
+ */
+typedef void (*emac_get_ifname_fn)(emac_interface_t *emac, char *name, uint8_t size);
+
+/**
+ * Returns size of the underlying interface HW address size
+ *
+ * @param emac Emac interface
+ * @return     HW address size in bytes
+ */
+typedef uint8_t (*emac_get_hwaddr_size_fn)(emac_interface_t *emac);
+
+/**
+ * Return interface hw address
+ *
+ * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size
+ *
+ * @param emac Emac interface
+ * @param addr HW address for underlying interface
+ */
+typedef void (*emac_get_hwaddr_fn)(emac_interface_t *emac, uint8_t *addr);
+
+/**
+ * Set HW address for interface
+ *
+ * Provided address has to be of correct size, see @a get_hwaddr_size
+ *
+ * @param emac Emac interface
+ * @param addr Address to be set
+ */
+typedef void (*emac_set_hwaddr_fn)(emac_interface_t *emac, uint8_t *addr);
+
+/**
+ * Sends the packet over the link
+ *
+ * That can not be called from an interrupt context.
+ *
+ * @param emac Emac interface
+ * @param buf  Packet to be send
+ * @return     True if the packet was send successfully, False otherwise
+ */
+typedef bool (*emac_link_out_fn)(emac_interface_t *emac, emac_stack_mem_t *buf);
+
+/**
+ * Initializes the HW
+ *
+ * @return True on success, False in case of an error.
+ */
+typedef bool (*emac_power_up_fn)(emac_interface_t *emac);
+
+/**
+ * Deinitializes the HW
+ *
+ * @param emac Emac interface
+ */
+typedef void (*emac_power_down_fn)(emac_interface_t *emac);
+
+/**
+ * Sets a callback that needs to be called for packets received for that interface
+ *
+ * @param emac     Emac interface
+ * @param input_cb Function to be register as a callback
+ * @param data     Arbitrary user data to be passed to the callback
+ */
+typedef void (*emac_set_link_input_cb_fn)(emac_interface_t *emac, emac_link_input_fn input_cb, void *data);
+
+/**
+ * Sets a callback that needs to be called on link status changes for given interface
+ *
+ * @param emac     Emac interface
+ * @param state_cb Function to be register as a callback
+ * @param data Arbitrary user data to be passed to the callback
+ */
+typedef void (*emac_set_link_state_cb_fn)(emac_interface_t *emac, emac_link_state_change_fn state_cb, void *data);
+
+typedef struct emac_interface_ops {
+    emac_get_mtu_size_fn        get_mtu_size;
+    emac_get_ifname_fn          get_ifname;
+    emac_get_hwaddr_size_fn     get_hwaddr_size;
+    emac_get_hwaddr_fn          get_hwaddr;
+    emac_set_hwaddr_fn          set_hwaddr;
+    emac_link_out_fn            link_out;
+    emac_power_up_fn            power_up;
+    emac_power_down_fn          power_down;
+    emac_set_link_input_cb_fn   set_link_input_cb;
+    emac_set_link_state_cb_fn   set_link_state_cb;
+} emac_interface_ops_t;
+
+typedef struct emac_interface {
+    const emac_interface_ops_t ops;
+    void *hw;
+} emac_interface_t;
+
+#else
+
+typedef void *emac_interface_t;
+
+#endif /* DEVICE_EMAC */
+#endif  /* MBED_EMAC_API_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/ethernet_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/ethernet_api.h
new file mode 100755
index 0000000..817f1f2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/ethernet_api.h
@@ -0,0 +1,68 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/flash_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/flash_api.h
new file mode 100755
index 0000000..4231c08
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/flash_api.h
@@ -0,0 +1,130 @@
+/** \addtogroup hal */
+/** @{*/
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FLASH_API_H
+#define MBED_FLASH_API_H
+
+#include "device.h"
+#include <stdint.h>
+
+#if DEVICE_FLASH
+
+#define MBED_FLASH_INVALID_SIZE     0xFFFFFFFF
+
+typedef struct flash_s flash_t;
+
+#if TARGET_FLASH_CMSIS_ALGO
+#include "flash_data.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup flash_hal Flash HAL API
+ * @{
+ */
+
+/** Initialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_init(flash_t *obj);
+
+/** Uninitialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_free(flash_t *obj);
+
+/** Erase one sector starting at defined address
+ *
+ * The address should be at sector boundary. This function does not do any check for address alignments
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_erase_sector(flash_t *obj, uint32_t address);
+
+/** Read data starting at defined address
+ *
+ * This function has a WEAK implementation using memcpy for backwards compatibility.
+ * @param obj The flash object
+ * @param address Address to begin reading from
+ * @param data The buffer to read data into
+ * @param size The number of bytes to read
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size);
+
+/** Program pages starting at defined address
+ *
+ * The pages should not cross multiple sectors.
+ * This function does not do any check for address alignments or if size is aligned to a page size.
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @param data The data buffer to be programmed
+ * @param size The number of bytes to program
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size);
+
+/** Get sector size
+ *
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return The size of a sector
+ */
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
+
+/** Get page size
+ *
+ * The page size defines the writable page size
+ * @param obj The flash object
+ * @return The size of a page
+ */
+uint32_t flash_get_page_size(const flash_t *obj);
+
+/** Get start address for the flash region
+ *
+ * @param obj The flash object
+ * @return The start address for the flash region
+ */
+uint32_t flash_get_start_address(const flash_t *obj);
+
+/** Get the flash region size
+ *
+ * @param obj The flash object
+ * @return The flash region size
+ */
+uint32_t flash_get_size(const flash_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/gpio_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/gpio_api.h
new file mode 100755
index 0000000..a99fdec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/gpio_api.h
@@ -0,0 +1,133 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include <stdint.h>
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_gpio GPIO HAL functions
+ * @{
+ */
+
+/** Set the given pin as GPIO
+ *
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
+/** Initialize the GPIO pin
+ *
+ * @param obj The GPIO object to initialize
+ * @param pin The GPIO pin to initialize
+ */
+void gpio_init(gpio_t *obj, PinName pin);
+
+/** Set the input pin mode
+ *
+ * @param obj  The GPIO object
+ * @param mode The pin mode to be set
+ */
+void gpio_mode(gpio_t *obj, PinMode mode);
+
+/** Set the pin direction
+ *
+ * @param obj       The GPIO object
+ * @param direction The pin direction to be set
+ */
+void gpio_dir(gpio_t *obj, PinDirection direction);
+
+/** Set the output value
+ *
+ * @param obj   The GPIO object
+ * @param value The value to be set
+ */
+void gpio_write(gpio_t *obj, int value);
+
+/** Read the input value
+ *
+ * @param obj The GPIO object
+ * @return An integer value 1 or 0
+ */
+int gpio_read(gpio_t *obj);
+
+// the following functions are generic and implemented in the common gpio.c file
+// TODO: fix, will be moved to the common gpio header file
+
+/** Init the input pin and set mode to PullDefault
+ *
+ * @param gpio The GPIO object
+ * @param pin  The pin name
+ */
+void gpio_init_in(gpio_t* gpio, PinName pin);
+
+/** Init the input pin and set the mode
+ *
+ * @param gpio  The GPIO object
+ * @param pin   The pin name
+ * @param mode  The pin mode to be set
+ */
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
+
+/** Init the output pin as an output, with predefined output value 0
+ *
+ * @param gpio The GPIO object
+ * @param pin  The pin name
+ * @return     An integer value 1 or 0
+ */
+void gpio_init_out(gpio_t* gpio, PinName pin);
+
+/** Init the pin as an output and set the output value
+ *
+ * @param gpio  The GPIO object
+ * @param pin   The pin name
+ * @param value The value to be set
+ */
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
+
+/** Init the pin to be in/out
+ *
+ * @param gpio      The GPIO object
+ * @param pin       The pin name
+ * @param direction The pin direction to be set
+ * @param mode      The pin mode to be set
+ * @param value     The value to be set for an output pin
+ */
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/gpio_irq_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/gpio_irq_api.h
new file mode 100755
index 0000000..eb63171
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/gpio_irq_api.h
@@ -0,0 +1,97 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO IRQ events
+ */
+typedef enum {
+    IRQ_NONE,
+    IRQ_RISE,
+    IRQ_FALL
+} gpio_irq_event;
+
+/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
+ */
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+/**
+ * \defgroup hal_gpioirq GPIO IRQ HAL functions
+ * @{
+ */
+
+/** Initialize the GPIO IRQ pin
+ *
+ * @param obj     The GPIO object to initialize
+ * @param pin     The GPIO pin name
+ * @param handler The handler to be attached to GPIO IRQ
+ * @param id      The object ID (id != 0, 0 is reserved)
+ * @return -1 if pin is NC, 0 otherwise
+ */
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+
+/** Release the GPIO IRQ PIN
+ *
+ * @param obj The gpio object
+ */
+void gpio_irq_free(gpio_irq_t *obj);
+
+/** Enable/disable pin IRQ event
+ *
+ * @param obj    The GPIO object
+ * @param event  The GPIO IRQ event
+ * @param enable The enable flag
+ */
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+
+/** Enable GPIO IRQ
+ *
+ * This is target dependent, as it might enable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_enable(gpio_irq_t *obj);
+
+/** Disable GPIO IRQ
+ *
+ * This is target dependent, as it might disable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_disable(gpio_irq_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/i2c_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/i2c_api.h
new file mode 100755
index 0000000..7012193
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/i2c_api.h
@@ -0,0 +1,254 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+#include "hal/buffer.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "hal/dma_api.h"
+#endif
+
+#if DEVICE_I2C
+
+/**
+ * @defgroup hal_I2CEvents I2C Events Macros
+ *
+ * @{
+ */
+#define I2C_EVENT_ERROR               (1 << 1)
+#define I2C_EVENT_ERROR_NO_SLAVE      (1 << 2)
+#define I2C_EVENT_TRANSFER_COMPLETE   (1 << 3)
+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
+#define I2C_EVENT_ALL                 (I2C_EVENT_ERROR |  I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+/** Asynch I2C HAL structure
+ */
+typedef struct {
+    struct i2c_s    i2c;     /**< Target specific I2C structure */
+    struct buffer_s tx_buff; /**< Tx buffer */
+    struct buffer_s rx_buff; /**< Rx buffer */
+} i2c_t;
+
+#else
+/** Non-asynch I2C HAL structure
+ */
+typedef struct i2c_s i2c_t;
+
+#endif
+
+enum {
+  I2C_ERROR_NO_SLAVE = -1,
+  I2C_ERROR_BUS_BUSY = -2
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralI2C I2C Configuration Functions
+ * @{
+ */
+
+/** Initialize the I2C peripheral. It sets the default parameters for I2C
+ *  peripheral, and configures its specifieds pins.
+ *  
+ *  @param obj  The I2C object
+ *  @param sda  The sda pin
+ *  @param scl  The scl pin
+ */
+void i2c_init(i2c_t *obj, PinName sda, PinName scl);
+
+/** Configure the I2C frequency
+ *
+ *  @param obj The I2C object
+ *  @param hz  Frequency in Hz
+ */
+void i2c_frequency(i2c_t *obj, int hz);
+
+/** Send START command
+ *
+ *  @param obj The I2C object
+ */
+int  i2c_start(i2c_t *obj);
+
+/** Send STOP command
+ *
+ *  @param obj The I2C object
+ */
+int  i2c_stop(i2c_t *obj);
+
+/** Blocking reading data
+ *
+ *  @param obj     The I2C object
+ *  @param address 7-bit address (last bit is 1)
+ *  @param data    The buffer for receiving
+ *  @param length  Number of bytes to read
+ *  @param stop    Stop to be generated after the transfer is done
+ *  @return Number of read bytes
+ */
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
+
+/** Blocking sending data
+ *
+ *  @param obj     The I2C object
+ *  @param address 7-bit address (last bit is 0)
+ *  @param data    The buffer for sending
+ *  @param length  Number of bytes to write
+ *  @param stop    Stop to be generated after the transfer is done
+ *  @return 
+ *      zero or non-zero - Number of written bytes
+ *      negative - I2C_ERROR_XXX status
+ */
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
+
+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
+ *
+ *  @param obj The I2C object
+ */
+void i2c_reset(i2c_t *obj);
+
+/** Read one byte
+ *
+ *  @param obj The I2C object
+ *  @param last Acknoledge
+ *  @return The read byte
+ */
+int i2c_byte_read(i2c_t *obj, int last);
+
+/** Write one byte
+ *
+ *  @param obj The I2C object
+ *  @param data Byte to be written
+ *  @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
+ */
+int i2c_byte_write(i2c_t *obj, int data);
+
+/**@}*/
+
+#if DEVICE_I2CSLAVE
+
+/**
+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
+ * @{
+ */
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive
+ *  @return non-zero if a value is available
+ */
+void i2c_slave_mode(i2c_t *obj, int enable_slave);
+
+/** Check to see if the I2C slave has been addressed.
+ *  @param obj The I2C object
+ *  @return The status - 1 - read addresses, 2 - write to all slaves,
+ *         3 write addressed, 0 - the slave has not been addressed
+ */
+int  i2c_slave_receive(i2c_t *obj);
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @param data    The buffer for receiving
+ *  @param length  Number of bytes to read
+ *  @return non-zero if a value is available
+ */
+int  i2c_slave_read(i2c_t *obj, char *data, int length);
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @param data    The buffer for sending
+ *  @param length  Number of bytes to write
+ *  @return non-zero if a value is available
+ */
+int  i2c_slave_write(i2c_t *obj, const char *data, int length);
+
+/** Configure I2C address.
+ *  @param obj     The I2C object
+ *  @param idx     Currently not used
+ *  @param address The address to be set
+ *  @param mask    Currently not used
+ */
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+
+#endif
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+
+/**
+ * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
+ * @{
+ */
+
+/** Start I2C asynchronous transfer
+ *
+ *  @param obj       The I2C object
+ *  @param tx        The transmit buffer
+ *  @param tx_length The number of bytes to transmit
+ *  @param rx        The receive buffer
+ *  @param rx_length The number of bytes to receive
+ *  @param address   The address to be set - 7bit or 9bit
+ *  @param stop      If true, stop will be generated after the transfer is done
+ *  @param handler   The I2C IRQ handler to be set
+ *  @param event     Event mask for the transfer. See \ref hal_I2CEvents
+ *  @param hint      DMA hint usage
+ */
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ *  @param obj The I2C object which holds the transfer information
+ *  @return Event flags if a transfer termination condition was met, otherwise return 0.
+ */
+uint32_t i2c_irq_handler_asynch(i2c_t *obj);
+
+/** Attempts to determine if the I2C peripheral is already in use
+ *
+ *  @param obj The I2C object
+ *  @return Non-zero if the I2C module is active or zero if it is not
+ */
+uint8_t i2c_active(i2c_t *obj);
+
+/** Abort asynchronous transfer
+ *
+ *  This function does not perform any check - that should happen in upper layers.
+ *  @param obj The I2C object
+ */
+void i2c_abort_asynch(i2c_t *obj);
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/lp_ticker_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/lp_ticker_api.h
new file mode 100755
index 0000000..39d396e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/lp_ticker_api.h
@@ -0,0 +1,98 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LPTICKER_API_H
+#define MBED_LPTICKER_API_H
+
+#include "device.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_LpTicker Low Power Ticker Functions
+ * @{
+ */
+
+/** Get low power ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_lp_ticker_data(void);
+
+/** The wrapper for ticker_irq_handler, to pass lp ticker's data
+ *
+ */
+void lp_ticker_irq_handler(void);
+
+/* HAL lp ticker */
+
+/** Initialize the low power ticker
+ *
+ */
+void lp_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t lp_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void lp_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable low power ticker interrupt
+ *
+ */
+void lp_ticker_disable_interrupt(void);
+
+/** Clear the low power ticker interrupt
+ *
+ */
+void lp_ticker_clear_interrupt(void);
+
+/** Set pending interrupt that should be fired right away.
+ * 
+ * The ticker should be initialized prior calling this function.
+ */
+void lp_ticker_fire_interrupt(void);
+
+/** Get frequency and counter bits of this ticker.
+ *
+ */
+const ticker_info_t* lp_ticker_get_info(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_flash_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_flash_api.c
new file mode 100755
index 0000000..83fa7f1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_flash_api.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "hal/flash_api.h"
+
+#if DEVICE_FLASH
+
+#include "platform/mbed_toolchain.h"
+#include <string.h>
+
+MBED_WEAK int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
+{
+    memcpy(data, (const void *)address, size);
+    return 0;
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_gpio.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_gpio.c
new file mode 100755
index 0000000..b9dda3f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_gpio.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_dir(gpio, PIN_INPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_write(gpio, value);
+        gpio_dir(gpio, PIN_OUTPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+void gpio_init_in(gpio_t* gpio, PinName pin) {
+    gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+    _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t* gpio, PinName pin) {
+    gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+    _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+    if (direction == PIN_INPUT) {
+        _gpio_init_in(gpio, pin, mode);
+        if (pin != NC)
+            gpio_write(gpio, value); // we prepare the value in case it is switched later
+    } else {
+        _gpio_init_out(gpio, pin, mode, value);
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_lp_ticker_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_lp_ticker_api.c
new file mode 100755
index 0000000..0809f6f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_lp_ticker_api.c
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+static ticker_event_queue_t events = { 0 };
+
+static const ticker_interface_t lp_interface = {
+    .init = lp_ticker_init,
+    .read = lp_ticker_read,
+    .disable_interrupt = lp_ticker_disable_interrupt,
+    .clear_interrupt = lp_ticker_clear_interrupt,
+    .set_interrupt = lp_ticker_set_interrupt,
+    .fire_interrupt = lp_ticker_fire_interrupt,
+    .get_info = lp_ticker_get_info,
+};
+
+static const ticker_data_t lp_data = {
+    .interface = &lp_interface,
+    .queue = &events,
+};
+
+const ticker_data_t* get_lp_ticker_data(void)
+{
+    return &lp_data;
+}
+
+void lp_ticker_irq_handler(void)
+{
+    ticker_irq_handler(&lp_data);
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_pinmap_common.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_pinmap_common.c
new file mode 100755
index 0000000..93658b2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_pinmap_common.c
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/pinmap.h"
+#include "platform/mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map) {
+    if (pin == NC)
+        return;
+
+    while (map->pin != NC) {
+        if (map->pin == pin) {
+            pin_function(pin, map->function);
+
+            pin_mode(pin, PullNone);
+            return;
+        }
+        map++;
+    }
+    error("could not pinout");
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+    // both are the same (inc both NC)
+    if (a == b)
+        return a;
+
+    // one (or both) is not connected
+    if (a == (uint32_t)NC)
+        return b;
+    if (b == (uint32_t)NC)
+        return a;
+
+    // mis-match error case
+    error("pinmap mis-match");
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+    while (map->pin != NC) {
+        if (map->pin == pin)
+            return map->peripheral;
+        map++;
+    }
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+    uint32_t peripheral = (uint32_t)NC;
+
+    if (pin == (PinName)NC)
+        return (uint32_t)NC;
+    peripheral = pinmap_find_peripheral(pin, map);
+    if ((uint32_t)NC == peripheral) // no mapping available
+        error("pinmap not found for peripheral");
+    return peripheral;
+}
+
+uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
+    while (map->pin != NC) {
+        if (map->pin == pin)
+            return map->function;
+        map++;
+    }
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_function(PinName pin, const PinMap* map) {
+    uint32_t function = (uint32_t)NC;
+
+    if (pin == (PinName)NC)
+        return (uint32_t)NC;
+    function = pinmap_find_function(pin, map);
+    if ((uint32_t)NC == function) // no mapping available
+        error("pinmap not found for function");
+    return function;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_sleep_manager.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_sleep_manager.c
new file mode 100755
index 0000000..58cf23a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_sleep_manager.c
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_sleep.h"
+#include "mbed_critical.h"
+#include "sleep_api.h"
+#include "mbed_error.h"
+#include <limits.h>
+
+#if DEVICE_SLEEP
+
+// deep sleep locking counter. A target is allowed to deep sleep if counter == 0
+static uint16_t deep_sleep_lock = 0U;
+
+void sleep_manager_lock_deep_sleep(void)
+{
+    core_util_critical_section_enter();
+    if (deep_sleep_lock == USHRT_MAX) {
+        core_util_critical_section_exit();
+        error("Deep sleep lock would overflow (> USHRT_MAX)");
+    }
+    core_util_atomic_incr_u16(&deep_sleep_lock, 1);
+    core_util_critical_section_exit();
+}
+
+void sleep_manager_unlock_deep_sleep(void)
+{
+    core_util_critical_section_enter();
+    if (deep_sleep_lock == 0) {
+        core_util_critical_section_exit();
+        error("Deep sleep lock would underflow (< 0)");
+    }
+    core_util_atomic_decr_u16(&deep_sleep_lock, 1);
+    core_util_critical_section_exit();
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+    return deep_sleep_lock == 0 ? true : false;
+}
+
+void sleep_manager_sleep_auto(void)
+{
+    core_util_critical_section_enter();
+// debug profile should keep debuggers attached, no deep sleep allowed
+#ifdef MBED_DEBUG
+    hal_sleep();
+#else
+    if (sleep_manager_can_deep_sleep()) {
+        hal_deepsleep();
+    } else {
+        hal_sleep();
+    }
+#endif
+    core_util_critical_section_exit();
+}
+
+#else
+
+// locking is valid only if DEVICE_SLEEP is defined
+// we provide empty implementation
+
+void sleep_manager_lock_deep_sleep(void)
+{
+
+}
+
+void sleep_manager_unlock_deep_sleep(void)
+{
+
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+    // no sleep implemented
+    return false;
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_ticker_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_ticker_api.c
new file mode 100755
index 0000000..114a5a4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_ticker_api.c
@@ -0,0 +1,397 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include <stddef.h>
+#include "hal/ticker_api.h"
+#include "platform/mbed_critical.h"
+#include "mbed_assert.h"
+
+static void schedule_interrupt(const ticker_data_t *const ticker);
+static void update_present_time(const ticker_data_t *const ticker);
+
+/*
+ * Initialize a ticker instance.  
+ */
+static void initialize(const ticker_data_t *ticker)
+{
+    // return if the queue has already been initialized, in that case the 
+    // interface used by the queue is already initialized.
+    if (ticker->queue->initialized) { 
+        return;
+    }
+
+    ticker->interface->init();
+
+    const ticker_info_t *info = ticker->interface->get_info();
+    uint32_t frequency = info->frequency;
+    if (info->frequency == 0) {
+        MBED_ASSERT(0);
+        frequency = 1000000;
+    }
+
+    uint32_t bits = info->bits;
+    if ((info->bits > 32) || (info->bits < 4)) {
+        MBED_ASSERT(0);
+        bits = 32;
+    }
+    uint32_t max_delta = 0x7 << (bits - 4); // 7/16th
+    uint64_t max_delta_us =
+            ((uint64_t)max_delta * 1000000 + frequency - 1) / frequency;
+
+    ticker->queue->event_handler = NULL;
+    ticker->queue->head = NULL;
+    ticker->queue->tick_last_read = ticker->interface->read();
+    ticker->queue->tick_remainder = 0;
+    ticker->queue->frequency = frequency;
+    ticker->queue->bitmask = ((uint64_t)1 << bits) - 1;
+    ticker->queue->max_delta = max_delta;
+    ticker->queue->max_delta_us = max_delta_us;
+    ticker->queue->present_time = 0;
+    ticker->queue->initialized = true;
+    
+    update_present_time(ticker);
+    schedule_interrupt(ticker);
+}
+
+/**
+ * Set the event handler function of a ticker instance. 
+ */
+static void set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+    ticker->queue->event_handler = handler;
+}
+
+/*
+ * Convert a 32 bit timestamp into a 64 bit timestamp.
+ *
+ * A 64 bit timestamp is used as the point of time of reference while the 
+ * timestamp to convert is relative to this point of time. 
+ *
+ * The lower 32 bits of the timestamp returned will be equal to the timestamp to 
+ * convert. 
+ * 
+ * If the timestamp to convert is less than the lower 32 bits of the time 
+ * reference then the timestamp to convert is seen as an overflowed value and 
+ * the upper 32 bit of the timestamp returned will be equal to the upper 32 bit 
+ * of the reference point + 1. 
+ * Otherwise, the upper 32 bit returned will be equal to the upper 32 bit of the 
+ * reference point. 
+ *
+ * @param ref: The 64 bit timestamp of reference.
+ * @param timestamp: The timestamp to convert.
+ */
+static us_timestamp_t convert_timestamp(us_timestamp_t ref, timestamp_t timestamp)
+{
+    bool overflow = timestamp < ((timestamp_t) ref) ? true : false;
+
+    us_timestamp_t result = (ref & ~((us_timestamp_t)UINT32_MAX)) | timestamp;
+    if (overflow) { 
+        result += (1ULL<<32);
+    }
+
+    return result;
+}
+
+/**
+ * Update the present timestamp value of a ticker.
+ */
+static void update_present_time(const ticker_data_t *const ticker)
+{
+
+    ticker_event_queue_t *queue = ticker->queue;
+    uint32_t ticker_time = ticker->interface->read();
+    if (ticker_time == ticker->queue->tick_last_read) {
+        // No work to do
+        return;
+    }
+
+    uint64_t elapsed_ticks = (ticker_time - queue->tick_last_read) & queue->bitmask;
+    queue->tick_last_read = ticker_time;
+
+    uint64_t elapsed_us;
+    if (1000000 == queue->frequency) {
+        // Optimized for 1MHz
+
+        elapsed_us = elapsed_ticks;
+    } else if (32768 == queue->frequency) {
+        // Optimized for 32KHz
+
+        uint64_t us_x_ticks = elapsed_ticks * 1000000;
+        elapsed_us = us_x_ticks >> 15;
+
+        // Update remainder
+        queue->tick_remainder += us_x_ticks - (elapsed_us << 15);
+        if (queue->tick_remainder >= queue->frequency) {
+            elapsed_us += 1;
+            queue->tick_remainder -= queue->frequency;
+        }
+    } else {
+        // General case
+
+        uint64_t us_x_ticks = elapsed_ticks * 1000000;
+        elapsed_us = us_x_ticks / queue->frequency;
+
+        // Update remainder
+        queue->tick_remainder += us_x_ticks - elapsed_us * queue->frequency;
+        if (queue->tick_remainder >= queue->frequency) {
+            elapsed_us += 1;
+            queue->tick_remainder -= queue->frequency;
+        }
+    }
+
+    // Update current time
+    queue->present_time += elapsed_us;
+}
+
+/**
+ * Given the absolute timestamp compute the hal tick timestamp.
+ */
+static timestamp_t compute_tick(const ticker_data_t *const ticker, us_timestamp_t timestamp)
+{
+    ticker_event_queue_t *queue = ticker->queue;
+    us_timestamp_t delta_us = timestamp - queue->present_time;
+
+    timestamp_t delta = ticker->queue->max_delta;
+    if (delta_us <=  ticker->queue->max_delta_us) {
+        // Checking max_delta_us ensures the operation will not overflow
+
+        if (1000000 == queue->frequency) {
+            // Optimized for 1MHz
+
+            delta = delta_us;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        } else if (32768 == queue->frequency) {
+            // Optimized for 32KHz
+
+            delta = (delta_us << 15) / 1000000;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        } else {
+            // General case
+
+            delta = delta_us * queue->frequency / 1000000;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        }
+    }
+    return (queue->tick_last_read + delta) & queue->bitmask;
+}
+
+/**
+ * Return 1 if the tick has incremented to or past match_tick, otherwise 0.
+ */
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick)
+{
+    if (match_tick > prev_tick) {
+        return (cur_tick >= match_tick) || (cur_tick < prev_tick);
+    } else {
+        return (cur_tick < prev_tick) && (cur_tick >= match_tick);
+    }
+}
+
+/**
+ * Compute the time when the interrupt has to be triggered and schedule it.  
+ * 
+ * If there is no event in the queue or the next event to execute is in more 
+ * than ticker.queue.max_delta ticks from now then the ticker irq will be
+ * scheduled in ticker.queue.max_delta ticks. Otherwise the irq will be
+ * scheduled to happen when the running counter reach the timestamp of the
+ * first event in the queue.
+ * 
+ * @note If there is no event in the queue then the interrupt is scheduled to 
+ * in ticker.queue.max_delta. This is necessary to keep track
+ * of the timer overflow.
+ */
+static void schedule_interrupt(const ticker_data_t *const ticker)
+{
+    ticker_event_queue_t *queue = ticker->queue;
+    update_present_time(ticker);
+
+    if (ticker->queue->head) {
+        us_timestamp_t present = ticker->queue->present_time;
+        us_timestamp_t match_time = ticker->queue->head->timestamp;
+
+        // if the event at the head of the queue is in the past then schedule
+        // it immediately.
+        if (match_time <= present) {
+            ticker->interface->fire_interrupt();
+            return;
+        }
+
+        timestamp_t match_tick = compute_tick(ticker, match_time);
+        ticker->interface->set_interrupt(match_tick);
+        timestamp_t cur_tick = ticker->interface->read();
+
+        if (_ticker_match_interval_passed(queue->tick_last_read, cur_tick, match_tick)) {
+            ticker->interface->fire_interrupt();
+        }
+    } else {
+        uint32_t match_tick =
+                (queue->tick_last_read + queue->max_delta) & queue->bitmask;
+        ticker->interface->set_interrupt(match_tick);
+    }
+}
+
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+    initialize(ticker);
+    set_handler(ticker, handler);
+}
+
+void ticker_irq_handler(const ticker_data_t *const ticker)
+{
+    ticker->interface->clear_interrupt();
+
+    /* Go through all the pending TimerEvents */
+    while (1) {
+        if (ticker->queue->head == NULL) {
+            break;
+        }
+
+        // update the current timestamp used by the queue 
+        update_present_time(ticker);
+
+        if (ticker->queue->head->timestamp <= ticker->queue->present_time) { 
+            // This event was in the past:
+            //      point to the following one and execute its handler
+            ticker_event_t *p = ticker->queue->head;
+            ticker->queue->head = ticker->queue->head->next;
+            if (ticker->queue->event_handler != NULL) {
+                (*ticker->queue->event_handler)(p->id); // NOTE: the handler can set new events
+            }
+            /* Note: We continue back to examining the head because calling the
+             * event handler may have altered the chain of pending events. */
+        } else {
+            break;
+        } 
+    }
+
+    schedule_interrupt(ticker);
+}
+
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id)
+{
+    core_util_critical_section_enter();
+
+    // update the current timestamp
+    update_present_time(ticker);
+    us_timestamp_t absolute_timestamp = convert_timestamp(
+        ticker->queue->present_time, 
+        timestamp
+    );
+    core_util_critical_section_exit();
+
+    // defer to ticker_insert_event_us
+    ticker_insert_event_us(
+        ticker, 
+        obj, absolute_timestamp, id
+    );
+}
+
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id)
+{
+    core_util_critical_section_enter();
+
+    // update the current timestamp
+    update_present_time(ticker);
+
+    // initialise our data
+    obj->timestamp = timestamp;
+    obj->id = id;
+
+    /* Go through the list until we either reach the end, or find
+       an element this should come before (which is possibly the
+       head). */
+    ticker_event_t *prev = NULL, *p = ticker->queue->head;
+    while (p != NULL) {
+        /* check if we come before p */
+        if (timestamp < p->timestamp) {
+            break;
+        }
+        /* go to the next element */
+        prev = p;
+        p = p->next;
+    }
+    
+    /* if we're at the end p will be NULL, which is correct */
+    obj->next = p;
+
+    /* if prev is NULL we're at the head */
+    if (prev == NULL) {
+        ticker->queue->head = obj;
+    } else {
+        prev->next = obj;
+    }
+
+    schedule_interrupt(ticker);
+
+    core_util_critical_section_exit();
+}
+
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj)
+{
+    core_util_critical_section_enter();
+
+    // remove this object from the list
+    if (ticker->queue->head == obj) {
+        // first in the list, so just drop me
+        ticker->queue->head = obj->next;
+        schedule_interrupt(ticker);
+    } else {
+        // find the object before me, then drop me
+        ticker_event_t* p = ticker->queue->head;
+        while (p != NULL) {
+            if (p->next == obj) {
+                p->next = obj->next;
+                break;
+            }
+            p = p->next;
+        }
+    }
+
+    core_util_critical_section_exit();
+}
+
+timestamp_t ticker_read(const ticker_data_t *const ticker)
+{
+    return ticker_read_us(ticker);
+}
+
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker)
+{
+    initialize(ticker);
+    update_present_time(ticker);
+    return ticker->queue->present_time;
+}
+
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp)
+{
+    int ret = 0;
+
+    /* if head is NULL, there are no pending events */
+    core_util_critical_section_enter();
+    if (data->queue->head != NULL) {
+        *timestamp = data->queue->head->timestamp;
+        ret = 1;
+    }
+    core_util_critical_section_exit();
+
+    return ret;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_us_ticker_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_us_ticker_api.c
new file mode 100755
index 0000000..17cf6f8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/mbed_us_ticker_api.c
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/us_ticker_api.h"
+
+static ticker_event_queue_t events = { 0 };
+
+static const ticker_interface_t us_interface = {
+    .init = us_ticker_init,
+    .read = us_ticker_read,
+    .disable_interrupt = us_ticker_disable_interrupt,
+    .clear_interrupt = us_ticker_clear_interrupt,
+    .set_interrupt = us_ticker_set_interrupt,
+    .fire_interrupt = us_ticker_fire_interrupt,
+    .get_info = us_ticker_get_info,
+};
+
+static const ticker_data_t us_data = {
+    .interface = &us_interface,
+    .queue = &events
+};
+
+const ticker_data_t* get_us_ticker_data(void)
+{
+    return &us_data;
+}
+
+void us_ticker_irq_handler(void)
+{
+    ticker_irq_handler(&us_data);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/pinmap.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/pinmap.h
new file mode 100755
index 0000000..844a4cb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/pinmap.h
@@ -0,0 +1,50 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+    int peripheral;
+    int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode    (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_function(PinName pin, const PinMap* map);
+uint32_t pinmap_merge     (uint32_t a, uint32_t b);
+void     pinmap_pinout    (PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_find_function(PinName pin, const PinMap* map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/port_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/port_api.h
new file mode 100755
index 0000000..6e718c5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/port_api.h
@@ -0,0 +1,93 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Port HAL structure. port_s is declared in the target's HAL
+ */
+typedef struct port_s port_t;
+
+/**
+ * \defgroup hal_port Port HAL functions
+ * @{
+ */
+
+/** Get the pin name from the port's pin number
+ *
+ * @param port  The port name
+ * @param pin_n The pin number within the specified port
+ * @return The pin name for the port's pin number
+ */
+PinName port_pin(PortName port, int pin_n);
+
+/** Initilize the port
+ *
+ * @param obj  The port object to initialize
+ * @param port The port name
+ * @param mask The bitmask to identify which bits in the port should be included (0 - ignore)
+ * @param dir  The port direction
+ */
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir);
+
+/** Set the input port mode
+ *
+ * @param obj  The port object
+ * @param mode THe port mode to be set
+ */
+void port_mode(port_t *obj, PinMode mode);
+
+/** Set port direction (in/out)
+ *
+ * @param obj The port object
+ * @param dir The port direction to be set
+ */
+void port_dir(port_t *obj, PinDirection dir);
+
+/** Write value to the port
+ *
+ * @param obj   The port object
+ * @param value The value to be set
+ */
+void port_write(port_t *obj, int value);
+
+/** Read the current value on the port
+ *
+ * @param obj The port object
+ * @return An integer with each bit corresponding to an associated port pin setting
+ */
+int port_read(port_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/pwmout_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/pwmout_api.h
new file mode 100755
index 0000000..00588c0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/pwmout_api.h
@@ -0,0 +1,120 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Pwmout hal structure. pwmout_s is declared in the target's hal
+ */
+typedef struct pwmout_s pwmout_t;
+
+/**
+ * \defgroup hal_pwmout Pwmout hal functions
+ * @{
+ */
+
+/** Initialize the pwm out peripheral and configure the pin
+ *
+ * @param obj The pwmout object to initialize
+ * @param pin The pwmout pin to initialize
+ */
+void pwmout_init(pwmout_t *obj, PinName pin);
+
+/** Deinitialize the pwmout object
+ *
+ * @param obj The pwmout object
+ */
+void pwmout_free(pwmout_t *obj);
+
+/** Set the output duty-cycle in range <0.0f, 1.0f>
+ *
+ * Value 0.0f represents 0 percentage, 1.0f represents 100 percent.
+ * @param obj     The pwmout object
+ * @param percent The floating-point percentage number
+ */
+void pwmout_write(pwmout_t *obj, float percent);
+
+/** Read the current float-point output duty-cycle
+ *
+ * @param obj The pwmout object
+ * @return A floating-point output duty-cycle
+ */
+float pwmout_read(pwmout_t *obj);
+
+/** Set the PWM period specified in seconds, keeping the duty cycle the same
+ *
+ * Periods smaller than microseconds (the lowest resolution) are set to zero.
+ * @param obj     The pwmout object
+ * @param seconds The floating-point seconds period
+ */
+void pwmout_period(pwmout_t *obj, float seconds);
+
+/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param ms  The milisecond period
+ */
+void pwmout_period_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM period specified in microseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param us  The microsecond period
+ */
+void pwmout_period_us(pwmout_t *obj, int us);
+
+/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
+ *
+ * @param obj     The pwmout object
+ * @param seconds The floating-point pulsewidth in seconds
+ */
+void pwmout_pulsewidth(pwmout_t *obj, float seconds);
+
+/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param ms  The floating-point pulsewidth in miliseconds
+ */
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param us  The floating-point pulsewidth in microseconds
+ */
+void pwmout_pulsewidth_us(pwmout_t *obj, int us);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/rtc_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/rtc_api.h
new file mode 100755
index 0000000..5dc87eb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/rtc_api.h
@@ -0,0 +1,77 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_rtc RTC hal functions
+ * @{
+ */
+
+/** Initialize the RTC peripheral
+ *
+ */
+void rtc_init(void);
+
+/** Deinitialize RTC
+ *
+ * TODO: The function is not used by rtc api in mbed-drivers.
+ */
+void rtc_free(void);
+
+/** Get the RTC enable status
+ *
+ * @retval 0 disabled
+ * @retval 1 enabled
+ */
+int rtc_isenabled(void);
+
+/** Get the current time from the RTC peripheral
+ *
+ * @return The current time
+ */
+time_t rtc_read(void);
+
+/** Set the current time to the RTC peripheral
+ *
+ * @param t The current time to be set
+ */
+void rtc_write(time_t t);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/serial_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/serial_api.h
new file mode 100755
index 0000000..30f100f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/serial_api.h
@@ -0,0 +1,307 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+#include "hal/buffer.h"
+#include "hal/dma_api.h"
+
+#if DEVICE_SERIAL
+
+#define SERIAL_EVENT_TX_SHIFT (2)
+#define SERIAL_EVENT_RX_SHIFT (8)
+
+#define SERIAL_EVENT_TX_MASK (0x00FC)
+#define SERIAL_EVENT_RX_MASK (0x3F00)
+
+#define SERIAL_EVENT_ERROR (1 << 1)
+
+/**
+ * @defgroup SerialTXEvents Serial TX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
+#define SERIAL_EVENT_TX_ALL      (SERIAL_EVENT_TX_COMPLETE)
+/**@}*/
+
+/**
+ * @defgroup SerialRXEvents Serial RX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_RX_COMPLETE        (1 << (SERIAL_EVENT_RX_SHIFT + 0))
+#define SERIAL_EVENT_RX_OVERRUN_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 1))
+#define SERIAL_EVENT_RX_FRAMING_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 2))
+#define SERIAL_EVENT_RX_PARITY_ERROR    (1 << (SERIAL_EVENT_RX_SHIFT + 3))
+#define SERIAL_EVENT_RX_OVERFLOW        (1 << (SERIAL_EVENT_RX_SHIFT + 4))
+#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
+#define SERIAL_EVENT_RX_ALL             (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
+                                         SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
+                                         SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
+/**@}*/
+
+#define SERIAL_RESERVED_CHAR_MATCH (255)
+
+typedef enum {
+    ParityNone = 0,
+    ParityOdd = 1,
+    ParityEven = 2,
+    ParityForced1 = 3,
+    ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+    RxIrq,
+    TxIrq
+} SerialIrq;
+
+typedef enum {
+    FlowControlNone,
+    FlowControlRTS,
+    FlowControlCTS,
+    FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+#if DEVICE_SERIAL_ASYNCH
+/** Asynch serial HAL structure
+ */
+typedef struct {
+    struct serial_s serial;  /**< Target specific serial structure */
+    struct buffer_s tx_buff; /**< TX buffer */
+    struct buffer_s rx_buff; /**< RX buffer */
+    uint8_t char_match;      /**< Character to be matched */
+    uint8_t char_found;      /**< State of the matched character */
+} serial_t;
+
+#else
+/** Non-asynch serial HAL structure
+ */
+typedef struct serial_s serial_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSerial Serial Configuration Functions
+ * @{
+ */
+
+/** Initialize the serial peripheral. It sets the default parameters for serial
+ *  peripheral, and configures its specifieds pins.
+ *
+ * @param obj The serial object
+ * @param tx  The TX pin name
+ * @param rx  The RX pin name
+ */
+void serial_init(serial_t *obj, PinName tx, PinName rx);
+
+/** Release the serial peripheral, not currently invoked. It requires further
+ *  resource management.
+ *
+ * @param obj The serial object
+ */
+void serial_free(serial_t *obj);
+
+/** Configure the baud rate
+ *
+ * @param obj      The serial object
+ * @param baudrate The baud rate to be configured
+ */
+void serial_baud(serial_t *obj, int baudrate);
+
+/** Configure the format. Set the number of bits, parity and the number of stop bits
+ *
+ * @param obj       The serial object
+ * @param data_bits The number of data bits
+ * @param parity    The parity
+ * @param stop_bits The number of stop bits
+ */
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+/** The serial interrupt handler registration
+ *
+ * @param obj     The serial object
+ * @param handler The interrupt handler which will be invoked when the interrupt fires
+ * @param id      The SerialBase object
+ */
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+
+/** Configure serial interrupt. This function is used for word-approach
+ *
+ * @param obj    The serial object
+ * @param irq    The serial IRQ type (RX or TX)
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
+
+/** Get character. This is a blocking call, waiting for a character
+ *
+ * @param obj The serial object
+ */
+int  serial_getc(serial_t *obj);
+
+/** Send a character. This is a blocking call, waiting for a peripheral to be available
+ *  for writing
+ *
+ * @param obj The serial object
+ * @param c   The character to be sent
+ */
+void serial_putc(serial_t *obj, int c);
+
+/** Check if the serial peripheral is readable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be read, 0 if nothing to read
+ */
+int  serial_readable(serial_t *obj);
+
+/** Check if the serial peripheral is writable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be written, 0 otherwise.
+ */
+int  serial_writable(serial_t *obj);
+
+/** Clear the serial peripheral
+ *
+ * @param obj The serial object
+ */
+void serial_clear(serial_t *obj);
+
+/** Set the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_set(serial_t *obj);
+
+/** Clear the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_clear(serial_t *obj);
+
+/** Configure the TX pin for UART function.
+ *
+ * @param tx The pin name used for TX
+ */
+void serial_pinout_tx(PinName tx);
+
+/** Configure the serial for the flow control. It sets flow control in the hardware
+ *  if a serial peripheral supports it, otherwise software emulation is used.
+ *
+ * @param obj    The serial object
+ * @param type   The type of the flow control. Look at the available FlowControl types.
+ * @param rxflow The TX pin name
+ * @param txflow The RX pin name
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#if DEVICE_SERIAL_ASYNCH
+
+/**@}*/
+
+/**
+ * \defgroup hal_AsynchSerial Asynchronous Serial Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
+ *  tx_buff
+ *
+ * @param obj       The serial object
+ * @param tx        The transmit buffer
+ * @param tx_length The number of bytes to transmit
+ * @param tx_width  Deprecated argument
+ * @param handler   The serial handler
+ * @param event     The logical OR of events to be registered
+ * @param hint      A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, otherwise returns 0
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** Begin asynchronous RX transfer (enable interrupt for data collecting)
+ *  The used buffer is specified in the serial object - rx_buff
+ *
+ * @param obj        The serial object
+ * @param rx         The receive buffer
+ * @param rx_length  The number of bytes to receive
+ * @param rx_width   Deprecated argument
+ * @param handler    The serial handler
+ * @param event      The logical OR of events to be registered
+ * @param handler    The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint       A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
+
+/** Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj);
+
+/** Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj);
+
+/** The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0
+ */
+int serial_irq_handler_asynch(serial_t *obj);
+
+/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ *  flushes the TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj);
+
+/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
+ *  flushes the RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj);
+
+/**@}*/
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/sleep_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/sleep_api.h
new file mode 100755
index 0000000..8747459
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/sleep_api.h
@@ -0,0 +1,69 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void hal_sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void hal_deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/spi_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/spi_api.h
new file mode 100755
index 0000000..cf619e0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/spi_api.h
@@ -0,0 +1,241 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+#include "hal/dma_api.h"
+#include "hal/buffer.h"
+
+#if DEVICE_SPI
+
+#define SPI_EVENT_ERROR       (1 << 1)
+#define SPI_EVENT_COMPLETE    (1 << 2)
+#define SPI_EVENT_RX_OVERFLOW (1 << 3)
+#define SPI_EVENT_ALL         (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
+
+#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
+
+#define SPI_FILL_WORD         (0xFFFF)
+#define SPI_FILL_CHAR         (0xFF)
+
+#if DEVICE_SPI_ASYNCH
+/** Asynch SPI HAL structure
+ */
+typedef struct {
+    struct spi_s spi;        /**< Target specific SPI structure */
+    struct buffer_s tx_buff; /**< Tx buffer */
+    struct buffer_s rx_buff; /**< Rx buffer */
+} spi_t;
+
+#else
+/** Non-asynch SPI HAL structure
+ */
+typedef struct spi_s spi_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSPI SPI Configuration Functions
+ * @{
+ */
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj  The SPI object to initialize
+ * @param[in]  mosi The pin to use for MOSI
+ * @param[in]  miso The pin to use for MISO
+ * @param[in]  sclk The pin to use for SCLK
+ * @param[in]  ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj);
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
+ * The default bit order is MSB.
+ * @param[in,out] obj   The SPI object to configure
+ * @param[in]     bits  The number of bits per frame
+ * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in]     slave Zero for master mode or non-zero for slave mode
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave);
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in]     hz  The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz);
+
+/**@}*/
+/**
+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj   The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int  spi_master_write(spi_t *obj, int value);
+
+// New function F4HDK
+int spi_master_transfer_2 (spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
+
+/** Write a block out in master mode and receive a value
+ *
+ *  The total number of bytes sent and recieved will be the maximum of
+ *  tx_length and rx_length. The bytes written will be padded with the
+ *  value 0xff.
+ *
+ * @param[in] obj        The SPI peripheral to use for sending
+ * @param[in] tx_buffer  Pointer to the byte-array of data to write to the device
+ * @param[in] tx_length  Number of bytes to write, may be zero
+ * @param[in] rx_buffer  Pointer to the byte-array of data to read from the device
+ * @param[in] rx_length  Number of bytes to read, may be zero
+ * @param[in] write_fill Default data transmitted while performing a read
+ * @returns
+ *      The number of bytes written and read from the device. This is
+ *      maximum of tx_length and rx_length.
+ */
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
+
+/** Check if a value is available to read
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if a value is available
+ */
+int  spi_slave_receive(spi_t *obj);
+
+/** Get a received value out of the SPI receive buffer in slave mode
+ *
+ * Blocks until a value is available
+ * @param[in] obj The SPI peripheral to read
+ * @return The value received
+ */
+int  spi_slave_read(spi_t *obj);
+
+/** Write a value to the SPI peripheral in slave mode
+ *
+ * Blocks until the SPI peripheral can be written to
+ * @param[in] obj   The SPI peripheral to write
+ * @param[in] value The value to write
+ */
+void spi_slave_write(spi_t *obj, int value);
+
+/** Checks if the specified SPI peripheral is in use
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if the peripheral is currently transmitting
+ */
+int  spi_busy(spi_t *obj);
+
+/** Get the module number
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return The module number
+ */
+uint8_t spi_get_module(spi_t *obj);
+
+/**@}*/
+
+#if DEVICE_SPI_ASYNCH
+/**
+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
+ *
+ * @param[in] obj       The SPI object that holds the transfer information
+ * @param[in] tx        The transmit buffer
+ * @param[in] tx_length The number of bytes to transmit
+ * @param[in] rx        The receive buffer
+ * @param[in] rx_length The number of bytes to receive
+ * @param[in] bit_width The bit width of buffer words
+ * @param[in] event     The logical OR of events to be registered
+ * @param[in] handler   SPI interrupt handler
+ * @param[in] hint      A suggestion for how to use DMA with this transfer
+ */
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
+ * conditions, such as buffer overflows or transfer complete.
+ * @param[in] obj     The SPI object that holds the transfer information
+ * @return Event flags if a transfer termination condition was met; otherwise 0.
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj);
+
+/** Attempts to determine if the SPI peripheral is already in use
+ *
+ * If a temporary DMA channel has been allocated, peripheral is in use.
+ * If a permanent DMA channel has been allocated, check if the DMA channel is in use.  If not, proceed as though no DMA
+ * channel were allocated.
+ * If no DMA channel is allocated, check whether tx and rx buffers have been assigned.  For each assigned buffer, check
+ * if the corresponding buffer position is less than the buffer length.  If buffers do not indicate activity, check if
+ * there are any bytes in the FIFOs.
+ * @param[in] obj The SPI object to check for activity
+ * @return Non-zero if the SPI port is active or zero if it is not.
+ */
+uint8_t spi_active(spi_t *obj);
+
+/** Abort an SPI transfer
+ *
+ * @param obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj);
+
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // SPI_DEVICE
+
+#endif // MBED_SPI_API_H
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/storage_abstraction/Driver_Common.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/storage_abstraction/Driver_Common.h
new file mode 100755
index 0000000..f61ff2c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/storage_abstraction/Driver_Common.h
@@ -0,0 +1,60 @@
+
+/** \addtogroup hal */
+/** @{*/
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_COMMON_H
+#define __DRIVER_COMMON_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/****** This file has been deprecated since mbed-os-5.5 *****/
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* __DRIVER_COMMON_H */
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/storage_abstraction/Driver_Storage.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/storage_abstraction/Driver_Storage.h
new file mode 100755
index 0000000..363a265
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/storage_abstraction/Driver_Storage.h
@@ -0,0 +1,775 @@
+
+/** \addtogroup hal */
+/** @{*/
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_STORAGE_H
+#define __DRIVER_STORAGE_H
+
+#include <stdint.h>
+
+/****** This file has been deprecated since mbed-os-5.5 *****/
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "Driver_Common.h"
+
+#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00)  /* API version */
+
+
+#define _ARM_Driver_Storage_(n)      Driver_Storage##n
+#define  ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
+
+#define ARM_STORAGE_INVALID_OFFSET  (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
+                                                            ///< address space). A storage block may never start at this address.
+
+#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL)          ///< Invalid address within the processor's memory address space.
+                                                            ///< Refer to memory-mapped storage, i.e. < \ref ARM_DRIVER_STORAGE::ResolveAddress().
+
+/****** Storage specific error codes *****/
+#define ARM_STORAGE_ERROR_NOT_ERASABLE      (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
+#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE  (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
+#define ARM_STORAGE_ERROR_PROTECTED         (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
+#define ARM_STORAGE_ERROR_RUNTIME_OR_INTEGRITY_FAILURE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Runtime or sanity-check failure.
+
+/**
+ * \brief Attributes of the storage range within a storage block.
+ */
+typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
+  uint32_t erasable      :  1;   ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
+                                 ///<   @note: if 'erasable' is 0--i.e. the 'erase' operation isn't available--then
+                                 ///<   'erase_unit' (see below) is immaterial and should be 0.
+  uint32_t programmable  :  1;   ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
+                                 ///<   Writes are typically achieved through the ProgramData operation (following an erase);
+                                 ///<   if storage isn't erasable (see 'erasable' above) but is memory-mapped
+                                 ///<   (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
+  uint32_t executable    :  1;   ///< This storage block can hold program data; the processor can fetch and execute code
+                                 ///<   sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
+  uint32_t protectable   :  1;   ///< The entire block can be protected from program and erase operations. Once protection
+                                 ///<   is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
+  uint32_t reserved      : 28;
+  uint32_t erase_unit;           ///< Minimum erase size in bytes.
+                                 ///<   The offset of the start of the erase-range should also be aligned with this value.
+                                 ///<   Applicable if the 'erasable' attribute is set for the block.
+                                 ///<   @note: if 'erasable' (see above) is 0--i.e. the 'erase' operation isn't available--then
+                                 ///<   'erase_unit' is immaterial and should be 0.
+  uint32_t protection_unit;      ///< Minimum protectable size in bytes. Applicable if the 'protectable'
+                                 ///<   attribute is set for the block. This should be a divisor of the block's size. A
+                                 ///<   block can be considered to be made up of consecutive, individually-protectable fragments.
+} ARM_STORAGE_BLOCK_ATTRIBUTES;
+
+/**
+ * \brief A storage block is a range of memory with uniform attributes. Storage blocks
+ * combine to make up the address map of a storage controller.
+ */
+typedef struct _ARM_STORAGE_BLOCK {
+  uint64_t                     addr;       ///< This is the start address of the storage block. It is
+                                           ///<   expressed as an offset from the start of the storage map
+                                           ///<   maintained by the owning storage controller.
+  uint64_t                     size;       ///< This is the size of the storage block, in units of bytes.
+                                           ///<   Together with addr, it describes a range [addr, addr+size).
+  ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
+} ARM_STORAGE_BLOCK;
+
+/**
+ * The check for a valid ARM_STORAGE_BLOCK.
+ */
+#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
+
+/**
+ * \brief Values for encoding storage memory-types with respect to programmability.
+ *
+ * Please ensure that the maximum of the following memory types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
+ */
+#define ARM_STORAGE_PROGRAMMABILITY_RAM       (0x0)
+#define ARM_STORAGE_PROGRAMMABILITY_ROM       (0x1) ///< Read-only memory.
+#define ARM_STORAGE_PROGRAMMABILITY_WORM      (0x2) ///< write-once-read-only-memory (WORM).
+#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE  (0x3) ///< re-programmable based on erase. Supports multiple writes.
+
+/**
+ * Values for encoding data-retention levels for storage blocks.
+ *
+ * Please ensure that the maximum of the following retention types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
+ */
+#define ARM_RETENTION_WHILE_DEVICE_ACTIVE     (0x0) ///< Data is retained only during device activity.
+#define ARM_RETENTION_ACROSS_SLEEP            (0x1) ///< Data is retained across processor sleep.
+#define ARM_RETENTION_ACROSS_DEEP_SLEEP       (0x2) ///< Data is retained across processor deep-sleep.
+#define ARM_RETENTION_BATTERY_BACKED          (0x3) ///< Data is battery-backed. Device can be powered off.
+#define ARM_RETENTION_NVM                     (0x4) ///< Data is retained in non-volatile memory.
+
+/**
+ * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
+ */
+typedef struct _ARM_STORAGE_SECURITY_FEATURES {
+  uint32_t acls                :  1; ///< Protection against internal software attacks using ACLs.
+  uint32_t rollback_protection :  1; ///< Roll-back protection. Set to true if the creator of the storage
+                                     ///<   can ensure that an external attacker can't force an
+                                     ///<   older firmware to run or to revert back to a previous state.
+  uint32_t tamper_proof        :  1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
+  uint32_t internal_flash      :  1; ///< Internal flash.
+  uint32_t reserved1           : 12;
+
+  /**
+   * Encode support for hardening against various classes of attacks.
+   */
+  uint32_t software_attacks     :  1; ///< device software (malware running on the device).
+  uint32_t board_level_attacks  :  1; ///< board level attacks (debug probes, copy protection fuses.)
+  uint32_t chip_level_attacks   :  1; ///< chip level attacks (tamper-protection).
+  uint32_t side_channel_attacks :  1; ///< side channel attacks.
+  uint32_t reserved2            : 12;
+} ARM_STORAGE_SECURITY_FEATURES;
+
+#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
+
+/**
+ * \brief Storage information. This contains device-metadata. It is the return
+ *     value from calling GetInfo() on the storage driver.
+ *
+ * \details These fields serve a different purpose than the ones contained in
+ *     \ref ARM_STORAGE_CAPABILITIES, which is another structure containing
+ *     device-level metadata. ARM_STORAGE_CAPABILITIES describes the API
+ *     capabilities, whereas ARM_STORAGE_INFO describes the device. Furthermore
+ *     ARM_STORAGE_CAPABILITIES fits within a single word, and is designed to be
+ *     passed around by value; ARM_STORAGE_INFO, on the other hand, contains
+ *     metadata which doesn't fit into a single word and requires the use of
+ *     pointers to be moved around.
+ */
+typedef struct _ARM_STORAGE_INFO {
+  uint64_t                      total_storage;        ///< Total available storage, in bytes.
+  uint32_t                      program_unit;         ///< Minimum programming size in bytes.
+                                                      ///<   The offset of the start of the program-range should also be aligned with this value.
+                                                      ///<   Applicable only if the 'programmable' attribute is set for a block.
+                                                      ///<   @note: setting program_unit to 0 has the effect of disabling the size and alignment
+                                                      ///<   restrictions (setting it to 1 also has the same effect).
+  uint32_t                      optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
+                                                      ///<   have internal buffers into which to receive data. Writing in chunks of
+                                                      ///<   'optimal_program_unit' would achieve maximum programming speed.
+                                                      ///<   Applicable only if the 'programmable' attribute is set for the underlying block(s).
+  uint32_t                      program_cycles;       ///< A measure of endurance for reprogramming.
+                                                      ///<   Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
+  uint32_t                      erased_value    :  1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
+  uint32_t                      memory_mapped   :  1; ///< This storage device has a mapping onto the processor's memory address space.
+                                                      ///<   @note: For a memory-mapped block which isn't erasable but is programmable (i.e. if
+                                                      ///<   'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
+                                                      ///<   the memory-mapped storage without going through the ProgramData operation.
+  uint32_t                      programmability :  4; ///< A value to indicate storage programmability.
+  uint32_t                      retention_level :  4;
+  uint32_t                      reserved        : 22;
+  ARM_STORAGE_SECURITY_FEATURES security;             ///< \ref ARM_STORAGE_SECURITY_FEATURES
+} ARM_STORAGE_INFO;
+
+/**
+\brief Operating status of the storage controller.
+*/
+typedef struct _ARM_STORAGE_STATUS {
+  uint32_t busy  : 1;                   ///< Controller busy flag
+  uint32_t error : 1;                   ///< Read/Program/Erase error flag (cleared on start of next operation)
+} ARM_STORAGE_STATUS;
+
+/**
+ * \brief Storage Driver API Capabilities.
+ *
+ * This data structure is designed to fit within a single word so that it can be
+ * fetched cheaply using a call to driver->GetCapabilities().
+ */
+typedef struct _ARM_STORAGE_CAPABILITIES {
+  uint32_t asynchronous_ops :  1; ///< Used to indicate if APIs like initialize,
+                                  ///<   read, erase, program, etc. can operate in asynchronous mode.
+                                  ///<   Setting this bit to 1 means that the driver is capable
+                                  ///<   of launching asynchronous operations; command completion is
+                                  ///<   signaled by the invocation of a completion callback. If
+                                  ///<   set to 1, drivers may still complete asynchronous
+                                  ///<   operations synchronously as necessary--in which case they
+                                  ///<   return a positive error code to indicate synchronous completion.
+  uint32_t erase_all        :  1; ///< Supports EraseAll operation.
+  uint32_t reserved         : 30;
+} ARM_STORAGE_CAPABILITIES;
+
+/**
+ * Command opcodes for Storage. Completion callbacks use these codes to refer to
+ * completing commands. Refer to \ref ARM_Storage_Callback_t.
+ */
+typedef enum _ARM_STORAGE_OPERATION {
+  ARM_STORAGE_OPERATION_GET_VERSION,
+  ARM_STORAGE_OPERATION_GET_CAPABILITIES,
+  ARM_STORAGE_OPERATION_INITIALIZE,
+  ARM_STORAGE_OPERATION_UNINITIALIZE,
+  ARM_STORAGE_OPERATION_POWER_CONTROL,
+  ARM_STORAGE_OPERATION_READ_DATA,
+  ARM_STORAGE_OPERATION_PROGRAM_DATA,
+  ARM_STORAGE_OPERATION_ERASE,
+  ARM_STORAGE_OPERATION_ERASE_ALL,
+  ARM_STORAGE_OPERATION_GET_STATUS,
+  ARM_STORAGE_OPERATION_GET_INFO,
+  ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
+  ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
+  ARM_STORAGE_OPERATION_GET_BLOCK
+} ARM_STORAGE_OPERATION;
+
+/**
+ * Declaration of the callback-type for command completion.
+ *
+ * @param [in] status
+ *               A code to indicate the status of the completed operation. For data
+ *               transfer operations, the status field is overloaded in case of
+ *               success to return the count of items successfully transferred; this
+ *               can be done safely because error codes are negative values.
+ *
+ * @param [in] operation
+ *               The command op-code. This value isn't essential for the callback in
+ *               the presence of the command instance-id, but it is expected that
+ *               this information could be a quick and useful filter.
+ */
+typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
+
+/**
+ * This is the set of operations constituting the Storage driver. Their
+ * implementation is platform-specific, and needs to be supplied by the
+ * porting effort.
+ *
+ * Some APIs within `ARM_DRIVER_STORAGE` will always operate synchronously:
+ * GetVersion, GetCapabilities, GetStatus, GetInfo, ResolveAddress,
+ * GetNextBlock, and GetBlock. This means that control returns to the caller
+ * with a relevant status code only after the completion of the operation (or
+ * the discovery of a failure condition).
+ *
+ * The remainder of the APIs: Initialize, Uninitialize, PowerControl, ReadData,
+ * ProgramData, Erase, EraseAll, can function asynchronously if the underlying
+ * controller supports it--i.e. if ARM_STORAGE_CAPABILITIES::asynchronous_ops is
+ * set. In the case of asynchronous operation, the invocation returns early
+ * (with ARM_DRIVER_OK) and results in a completion callback later. If
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is not set, then all such APIs
+ * execute synchronously, and control returns to the caller with a status code
+ * only after the completion of the operation (or the discovery of a failure
+ * condition).
+ *
+ * If ARM_STORAGE_CAPABILITIES::asynchronous_ops is set, a storage driver may
+ * still choose to execute asynchronous operations in a synchronous manner. If
+ * so, the driver returns a positive value to indicate successful synchronous
+ * completion (or an error code in case of failure) and no further invocation of
+ * completion callback should be expected. The expected return value for
+ * synchronous completion of such asynchronous operations varies depending on
+ * the operation. For operations involving data access, it often equals the
+ * amount of data transferred or affected. For non data-transfer operations,
+ * such as EraseAll or Initialize, it is usually 1.
+ *
+ * Here's a code snippet to suggest how asynchronous APIs might be used by
+ * callers to handle both synchronous and asynchronous execution by the
+ * underlying storage driver:
+ * \code
+ *     ASSERT(ARM_DRIVER_OK == 0); // this is a precondition; it doesn't need to be put in code
+ *     int32_t returnValue = drv->asynchronousAPI(...);
+ *     if (returnValue < ARM_DRIVER_OK) {
+ *         // handle error.
+ *     } else if (returnValue == ARM_DRIVER_OK) {
+ *         ASSERT(drv->GetCapabilities().asynchronous_ops == 1);
+ *         // handle early return from asynchronous execution; remainder of the work is done in the callback handler.
+ *     } else {
+ *         ASSERT(returnValue == EXPECTED_RETURN_VALUE_FOR_SYNCHRONOUS_COMPLETION);
+ *         // handle synchronous completion.
+ *     }
+ * \endcode
+ */
+typedef struct _ARM_DRIVER_STORAGE {
+  /**
+   * \brief Get driver version.
+   *
+   * The function GetVersion() returns version information of the driver implementation in ARM_DRIVER_VERSION.
+   *
+   *    - API version is the version of the CMSIS-Driver specification used to implement this driver.
+   *    - Driver version is source code version of the actual driver implementation.
+   *
+   * Example:
+   * \code
+   *     extern ARM_DRIVER_STORAGE *drv_info;
+   *
+   *     void read_version (void)  {
+   *       ARM_DRIVER_VERSION  version;
+   *
+   *       version = drv_info->GetVersion ();
+   *       if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher
+   *         // error handling
+   *         return;
+   *       }
+   *     }
+   * \endcode
+   *
+   * @return \ref ARM_DRIVER_VERSION.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   *
+   * @note The function GetVersion() can be called any time to obtain the
+   *     required information from the driver (even before initialization). It
+   *     always returns the same information.
+   */
+  ARM_DRIVER_VERSION (*GetVersion)(void);
+
+  /**
+   * \brief Get driver capabilities.
+   *
+   * \details The function GetCapabilities() returns information about
+   * capabilities in this driver implementation. The data fields of the struct
+   * ARM_STORAGE_CAPABILITIES encode various capabilities, for example if the device
+   * is able to execute operations asynchronously.
+   *
+   * Example:
+   * \code
+   *     extern ARM_DRIVER_STORAGE *drv_info;
+   *
+   *     void read_capabilities (void)  {
+   *       ARM_STORAGE_CAPABILITIES drv_capabilities;
+   *
+   *       drv_capabilities = drv_info->GetCapabilities ();
+   *       // interrogate capabilities
+   *
+   *     }
+   * \endcode
+   *
+   * @return \ref ARM_STORAGE_CAPABILITIES.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   *
+   * @note The function GetCapabilities() can be called any time to obtain the
+   *     required information from the driver (even before initialization). It
+   *     always returns the same information.
+   */
+  ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);
+
+  /**
+   * \brief Initialize the Storage Interface.
+   *
+   * The function Initialize is called when the middleware component starts
+   * operation. In addition to bringing the controller to a ready state,
+   * Initialize() receives a callback handler to be invoked upon completion of
+   * asynchronous operations.
+   *
+   * Initialize() needs to be called explicitly before
+   * powering the peripheral using PowerControl(), and before initiating other
+   * accesses to the storage controller.
+   *
+   * The function performs the following operations:
+   *   - Initializes the resources needed for the Storage interface.
+   *   - Registers the \ref ARM_Storage_Callback_t callback function.
+   *
+   * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+   *     drv->Initialize (...); // Allocate I/O pins
+   *     drv->PowerControl (ARM_POWER_FULL);        // Power up peripheral, setup IRQ/DMA
+   *
+   * - Initialize() typically allocates the I/O resources (pins) for the
+   *   peripheral. The function can be called multiple times; if the I/O resources
+   *   are already initialized it performs no operation and just returns with
+   *   ARM_DRIVER_OK.
+   *
+   * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+   *   interrupt (NVIC) and optionally DMA. The function can be called multiple
+   *   times; if the registers are already set it performs no operation and just
+   *   returns with ARM_DRIVER_OK.
+   *
+   * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+   *     drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+   *     drv->Uninitialize (...);               // Release I/O pins
+   *
+   * The functions PowerControl and Uninitialize always execute and can be used
+   * to put the peripheral into a Safe State, for example after any data
+   * transmission errors. To restart the peripheral in an error condition,
+   * you should first execute the Stop Sequence and then the Start Sequence.
+   *
+   * @param [in] callback
+   *               Caller-defined callback to be invoked upon command completion
+   *               for asynchronous APIs (including the completion of
+   *               initialization). Use a NULL pointer when no callback
+   *               signals are required.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*Initialize)(ARM_Storage_Callback_t callback);
+
+  /**
+   * \brief De-initialize the Storage Interface.
+   *
+   * The function Uninitialize() de-initializes the resources of Storage interface.
+   *
+   * It is called when the middleware component stops operation, and wishes to
+   * release the software resources used by the interface.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*Uninitialize)(void);
+
+  /**
+   * \brief Control the Storage interface power.
+   *
+   * The function \b ARM_Storage_PowerControl operates the power modes of the Storage interface.
+   *
+   * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+   *     drv->Initialize (...);                 // Allocate I/O pins
+   *     drv->PowerControl (ARM_POWER_FULL);    // Power up peripheral, setup IRQ/DMA
+   *
+   * - Initialize() typically allocates the I/O resources (pins) for the
+   *   peripheral. The function can be called multiple times; if the I/O resources
+   *   are already initialized it performs no operation and just returns with
+   *   ARM_DRIVER_OK.
+   *
+   * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+   *   interrupt (NVIC) and optionally DMA. The function can be called multiple
+   *   times; if the registers are already set it performs no operation and just
+   *   returns with ARM_DRIVER_OK.
+   *
+   * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+   *
+   *     drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+   *     drv->Uninitialize (...);               // Release I/O pins
+   *
+   * The functions PowerControl and Uninitialize always execute and can be used
+   * to put the peripheral into a Safe State, for example after any data
+   * transmission errors. To restart the peripheral in an error condition,
+   * you should first execute the Stop Sequence and then the Start Sequence.
+   *
+   * @param state
+   *          \ref ARM_POWER_STATE. The target power-state for the storage controller.
+   *          The parameter state can have the following values:
+   *              - ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts
+   *                                 (NVIC) and optionally DMA. Can be called multiple times. If the peripheral
+   *                                 is already in this mode, then the function performs no operation and returns
+   *                                 with ARM_DRIVER_OK.
+   *              - ARM_POWER_LOW : may use power saving. Returns ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.
+   *              - ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*PowerControl)(ARM_POWER_STATE state);
+
+  /**
+   * \brief read the contents of a given address range from the storage device.
+   *
+   * \details Read the contents of a range of storage memory into a buffer
+   *   supplied by the caller. The buffer is owned by the caller and should
+   *   remain accessible for the lifetime of this command.
+   *
+   * @param  [in] addr
+   *                This specifies the address from where to read data.
+   *
+   * @param [out] data
+   *                The destination of the read operation. The buffer
+   *                is owned by the caller and should remain accessible for the
+   *                lifetime of this command.
+   *
+   * @param  [in] size
+   *                The number of bytes requested to read. The data buffer
+   *                should be at least as large as this size.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with the number of successfully transferred bytes passed in as
+   *     the 'status' parameter. In the case of synchronous execution, control
+   *     returns after completion with a positive transfer-count. Return values
+   *     less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*ReadData)(uint64_t addr, void *data, uint32_t size);
+
+  /**
+   * \brief program (write into) the contents of a given address range of the storage device.
+   *
+   * \details Write the contents of a given memory buffer into a range of
+   *   storage memory. In the case of flash memory, the destination range in
+   *   storage memory typically has its contents in an erased state from a
+   *   preceding erase operation. The source memory buffer is owned by the
+   *   caller and should remain accessible for the lifetime of this command.
+   *
+   * @param [in] addr
+   *               This is the start address of the range to be written into. It
+   *               needs to be aligned to the device's \em program_unit
+   *               specified in \ref ARM_STORAGE_INFO.
+   *
+   * @param [in] data
+   *               The source of the write operation. The buffer is owned by the
+   *               caller and should remain accessible for the lifetime of this
+   *               command.
+   *
+   * @param [in] size
+   *               The number of bytes requested to be written. The buffer
+   *               should be at least as large as this size. \note 'size' should
+   *               be a multiple of the device's 'program_unit' (see \ref
+   *               ARM_STORAGE_INFO).
+   *
+   * @note It is best for the middleware to write in units of
+   *     'optimal_program_unit' (\ref ARM_STORAGE_INFO) of the device.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with the number of successfully transferred bytes passed in as
+   *     the 'status' parameter. In the case of synchronous execution, control
+   *     returns after completion with a positive transfer-count. Return values
+   *     less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*ProgramData)(uint64_t addr, const void *data, uint32_t size);
+
+  /**
+   * @brief Erase Storage range.
+   *
+   * @details This function erases a range of storage specified by [addr, addr +
+   *     size). Both 'addr' and 'addr + size' should align with the
+   *     'erase_unit'(s) of the respective owning storage block(s) (see \ref
+   *     ARM_STORAGE_BLOCK and \ref ARM_STORAGE_BLOCK_ATTRIBUTES). The range to
+   *     be erased will have its contents returned to the un-programmed state--
+   *     i.e. to 'erased_value' (see \ref ARM_STORAGE_BLOCK_ATTRIBUTES), which
+   *     is usually 1 to indicate the pattern of all ones: 0xFF.
+   *
+   * @param [in] addr
+   *               This is the start-address of the range to be erased. It must
+   *               start at an 'erase_unit' boundary of the underlying block.
+   *
+   * @param [in] size
+   *               Size (in bytes) of the range to be erased. 'addr + size'
+   *               must be aligned with the 'erase_unit' of the underlying
+   *               block.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return
+   *   If the range to be erased doesn't align with the erase_units of the
+   *   respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is returned.
+   *   If any part of the range is protected, ARM_STORAGE_ERROR_PROTECTED is
+   *   returned. If any part of the range is not erasable,
+   *   ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All such sanity-check
+   *   failures result in the error code being returned synchronously and the
+   *   storage bytes within the range remain unaffected.
+   *   Otherwise the function executes in the following ways:
+   *     If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with the number of successfully erased bytes passed in as
+   *     the 'status' parameter. In the case of synchronous execution, control
+   *     returns after completion with a positive erase-count. Return values
+   *     less than ARM_DRIVER_OK (0) signify errors.
+   *
+   * @note Erase() may return a smaller (positive) value than the size of the
+   *     requested range. The returned value indicates the actual number of bytes
+   *     erased. It is the caller's responsibility to follow up with an appropriate
+   *     request to complete the operation.
+   *
+   * @note in the case of a failed erase (except when
+   *     ARM_DRIVER_ERROR_PARAMETER, ARM_STORAGE_ERROR_PROTECTED, or
+   *     ARM_STORAGE_ERROR_NOT_ERASABLE is returned synchronously), the
+   *     requested range should be assumed to be in an unknown state. The
+   *     previous contents may not be retained.
+   */
+  int32_t (*Erase)(uint64_t addr, uint32_t size);
+
+  /**
+   * @brief Erase complete storage. Optional function for faster erase of the complete device.
+   *
+   * This optional function erases the complete device. If the device does not
+   *    support global erase then the function returns the error value \ref
+   *    ARM_DRIVER_ERROR_UNSUPPORTED. The data field \em 'erase_all' = 1
+   *    of the structure \ref ARM_STORAGE_CAPABILITIES encodes that
+   *    ARM_STORAGE_EraseAll is supported.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return
+   *   If any part of the storage range is protected,
+   *   ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the storage
+   *   range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
+   *   such sanity-check failures result in the error code being returned
+   *   synchronously and the storage bytes within the range remain unaffected.
+   *   Otherwise the function executes in the following ways:
+   *     If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with ARM_DRIVER_OK passed in as the 'status' parameter. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*EraseAll)(void);
+
+  /**
+   * @brief Get the status of the current (or previous) command executed by the
+   *     storage controller; stored in the structure \ref ARM_STORAGE_STATUS.
+   *
+   * @return
+   *          The status of the underlying controller.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+  ARM_STORAGE_STATUS (*GetStatus)(void);
+
+  /**
+   * @brief Get information about the Storage device; stored in the structure \ref ARM_STORAGE_INFO.
+   *
+   * @param [out] info
+   *                A caller-supplied buffer capable of being filled in with an
+   *                \ref ARM_STORAGE_INFO.
+   *
+   * @return ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
+   *         metadata about the storage controller is filled into the supplied
+   *         buffer, else an appropriate error value.
+   *
+   * @note It is the caller's responsibility to ensure that the buffer passed in
+   *         is able to be initialized with a \ref ARM_STORAGE_INFO.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+  int32_t (*GetInfo)(ARM_STORAGE_INFO *info);
+
+  /**
+   * \brief For memory-mapped storage, resolve an address relative to
+   *     the storage controller into a memory address.
+   *
+   * @param addr
+   *          This is the address for which we want a resolution to the
+   *          processor's physical address space. It is an offset from the
+   *          start of the storage map maintained by the owning storage
+   *          controller.
+   *
+   * @return
+   *          The resolved address in the processor's address space; else
+   *          ARM_STORAGE_INVALID_ADDRESS, if no resolution is possible.
+   *
+   * @note This API returns synchronously. The invocation should return quickly,
+   *     and result in a resolved address.
+   */
+  uint32_t (*ResolveAddress)(uint64_t addr);
+
+  /**
+   * @brief Advance to the successor of the current block (iterator), or fetch
+   *     the first block (if 'prev_block' is passed in as NULL).
+   *
+   * @details This helper function fetches (an iterator to) the next block (or
+   *     the first block if 'prev_block' is passed in as NULL). In the failure
+   *     case, a terminating, invalid block iterator is filled into the out
+   *     parameter: 'next_block'. In combination with \ref
+   *     ARM_STORAGE_VALID_BLOCK(), it can be used to iterate over the sequence
+   *     of blocks within the storage map:
+   *
+   * \code
+   *   ARM_STORAGE_BLOCK block;
+   *   for (drv->GetNextBlock(NULL, &block); ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
+   *       // make use of block
+   *   }
+   * \endcode
+   *
+   * @param[in]  prev_block
+   *               An existing block (iterator) within the same storage
+   *               controller. The memory buffer holding this block is owned
+   *               by the caller. This pointer may be NULL; if so, the
+   *               invocation fills in the first block into the out parameter:
+   *               'next_block'.
+   *
+   * @param[out] next_block
+   *               A caller-owned buffer large enough to be filled in with
+   *               the following ARM_STORAGE_BLOCK. It is legal to provide the
+   *               same buffer using 'next_block' as was passed in with 'prev_block'. It
+   *               is also legal to pass a NULL into this parameter if the
+   *               caller isn't interested in populating a buffer with the next
+   *               block--i.e. if the caller only wishes to establish the
+   *               presence of a next block.
+   *
+   * @return ARM_DRIVER_OK if a valid next block is found (or first block, if
+   *     prev_block is passed as NULL); upon successful operation, the contents
+   *     of the next (or first) block are filled into the buffer pointed to by
+   *     the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
+   *     guaranteed to be true. Upon reaching the end of the sequence of blocks
+   *     (iterators), or in case the driver is unable to fetch information about
+   *     the next (or first) block, an error (negative) value is returned and an
+   *     invalid StorageBlock is populated into the supplied buffer. If
+   *     prev_block is NULL, the first block is returned.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+   int32_t (*GetNextBlock)(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
+
+  /**
+   * @brief Find the storage block (iterator) encompassing a given storage address.
+   *
+   * @param[in]  addr
+   *               Storage address in bytes.
+   *
+   * @param[out] block
+   *               A caller-owned buffer large enough to be filled in with the
+   *               ARM_STORAGE_BLOCK encapsulating the given address. This value
+   *               can also be passed in as NULL if the caller isn't interested
+   *               in populating a buffer with the block--if the caller only
+   *               wishes to establish the presence of a containing storage
+   *               block.
+   *
+   * @return ARM_DRIVER_OK if a containing storage-block is found. In this case,
+   *     if block is non-NULL, the buffer pointed to by it is populated with
+   *     the contents of the storage block--i.e. if block is valid and a block is
+   *     found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
+   *     call. If there is no storage block containing the given offset, or in
+   *     case the driver is unable to resolve an address to a storage-block, an
+   *     error (negative) value is returned and an invalid StorageBlock is
+   *     populated into the supplied buffer.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+  int32_t (*GetBlock)(uint64_t addr, ARM_STORAGE_BLOCK *block);
+} const ARM_DRIVER_STORAGE;
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif /* __DRIVER_STORAGE_H */
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/ticker_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/ticker_api.h
new file mode 100755
index 0000000..605fa23
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/ticker_api.h
@@ -0,0 +1,205 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_API_H
+#define MBED_TICKER_API_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "device.h"
+
+/**
+ * Legacy format representing a timestamp in us.
+ * Given it is modeled as a 32 bit integer, this type can represent timestamp
+ * up to 4294 seconds (71 minutes).
+ * Prefer using us_timestamp_t which store timestamp as 64 bits integer.
+ */
+typedef uint32_t timestamp_t;
+
+/**
+ * A us timestamp stored in a 64 bit integer.
+ * Can store timestamp up to 584810 years.
+ */
+typedef uint64_t us_timestamp_t;
+
+/** Ticker's event structure
+ */
+typedef struct ticker_event_s {
+    us_timestamp_t         timestamp; /**< Event's timestamp */
+    uint32_t               id;        /**< TimerEvent object */
+    struct ticker_event_s *next;      /**< Next event in the queue */
+} ticker_event_t;
+
+typedef void (*ticker_event_handler)(uint32_t id);
+
+/** Information about the ticker implementation
+ */
+typedef struct {
+    uint32_t frequency;                           /**< Frequency in Hz this ticker runs at */
+    uint32_t bits;                                /**< Number of bits this ticker supports */
+} ticker_info_t;
+
+
+/** Ticker's interface structure - required API for a ticker
+ */
+typedef struct {
+    void (*init)(void);                           /**< Init function */
+    uint32_t (*read)(void);                       /**< Read function */
+    void (*disable_interrupt)(void);              /**< Disable interrupt function */
+    void (*clear_interrupt)(void);                /**< Clear interrupt function */
+    void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+    void (*fire_interrupt)(void);                 /**< Fire interrupt right-away */
+    const ticker_info_t *(*get_info)(void);       /**< Return info about this ticker's implementation */
+} ticker_interface_t;
+
+/** Ticker's event queue structure
+ */
+typedef struct {
+    ticker_event_handler event_handler; /**< Event handler */
+    ticker_event_t *head;               /**< A pointer to head */
+    uint32_t frequency;                 /**< Frequency of the timer in Hz */
+    uint32_t bitmask;                   /**< Mask to be applied to time values read */
+    uint32_t max_delta;                 /**< Largest delta in ticks that can be used when scheduling */
+    uint64_t max_delta_us;              /**< Largest delta in us that can be used when scheduling */
+    uint32_t tick_last_read;            /**< Last tick read */
+    uint64_t tick_remainder;            /**< Ticks that have not been added to base_time */
+    us_timestamp_t present_time;        /**< Store the timestamp used for present time */
+    bool initialized;                   /**< Indicate if the instance is initialized */
+} ticker_event_queue_t;
+
+/** Ticker's data structure
+ */
+typedef struct {
+    const ticker_interface_t *interface; /**< Ticker's interface */
+    ticker_event_queue_t *queue;         /**< Ticker's event queue */
+} ticker_data_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_ticker Ticker HAL functions
+ * @{
+ */
+
+/** Initialize a ticker and set the event handler
+ *
+ * @param ticker The ticker object.
+ * @param handler A handler to be set
+ */
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler);
+
+/** IRQ handler that goes through the events to trigger overdue events.
+ *
+ * @param ticker The ticker object.
+ */
+void ticker_irq_handler(const ticker_data_t *const ticker);
+
+/** Remove an event from the queue
+ *
+ * @param ticker The ticker object.
+ * @param obj  The event object to be removed from the queue
+ */
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj);
+
+/** Insert an event to the queue
+ *
+ * The event will be executed in timestamp - ticker_read().
+ *
+ * @warning This function does not consider timestamp in the past. If an event
+ * is inserted with a timestamp less than the current timestamp then the event
+ * will be executed in timestamp - ticker_read() us.
+ * The internal counter wrap very quickly it is hard to decide weither an
+ * event is in the past or in 1 hour.
+ *
+ * @note prefer the use of ticker_insert_event_us which allows registration of
+ * absolute timestamp.
+ *
+ * @param ticker    The ticker object.
+ * @param obj       The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id        The event object
+ */
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+
+/** Insert an event to the queue
+ *
+ * The event will be executed in timestamp - ticker_read_us() us.
+ *
+ * @note If an event is inserted with a timestamp less than the current
+ * timestamp then the event will be scheduled immediately resulting in
+ * an instant call to event handler.
+ *
+ * @param ticker    The ticker object.
+ * @param obj       The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id        The event object
+ */
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id);
+
+/** Read the current (relative) ticker's timestamp
+ *
+ * @warning Return a relative timestamp because the counter wrap every 4294
+ * seconds.
+ *
+ * @param ticker The ticker object.
+ * @return The current timestamp
+ */
+timestamp_t ticker_read(const ticker_data_t *const ticker);
+
+/** Read the current (absolute) ticker's timestamp
+ *
+ * @warning Return an absolute timestamp counting from the initialization of the
+ * ticker.
+ *
+ * @param ticker The ticker object.
+ * @return The current timestamp
+ */
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker);
+
+/** Read the next event's timestamp
+ *
+ * @param ticker        The ticker object.
+ * @param timestamp     The timestamp object.
+ * @return 1 if timestamp is pending event, 0 if there's no event pending
+ */
+int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp);
+
+/* Private functions
+ *
+ * @cond PRIVATE
+ *
+ */
+
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick);
+
+/*
+ * @endcond PRIVATE
+ *
+ */
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/trng_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/trng_api.h
new file mode 100755
index 0000000..946c253
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/trng_api.h
@@ -0,0 +1,72 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRNG_API_H
+#define MBED_TRNG_API_H
+
+#include <stddef.h>
+#include "device.h"
+
+#if DEVICE_TRNG
+
+/** TRNG HAL structure. trng_s is declared in the target's HAL
+ */
+typedef struct trng_s trng_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_trng TRNG hal functions
+ * @{
+ */
+
+/** Initialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_init(trng_t *obj);
+
+/** Deinitialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_free(trng_t *obj);
+
+/** Get random data from TRNG peripheral
+ *
+ * @param obj The TRNG object
+ * @param output The pointer to an output array
+ * @param length The size of output data, to avoid buffer overwrite
+ * @param output_length The length of generated data
+ * @return 0 success, -1 fail
+ */
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/us_ticker_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/us_ticker_api.h
new file mode 100755
index 0000000..07288d2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/hal/us_ticker_api.h
@@ -0,0 +1,94 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_UsTicker Microseconds Ticker Functions
+ * @{
+ */
+
+/** Get ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_us_ticker_data(void);
+
+
+/** The wrapper for ticker_irq_handler, to pass us ticker's data
+ *
+ */
+void us_ticker_irq_handler(void);
+
+/* HAL us ticker */
+
+/** Initialize the ticker
+ *
+ */
+void us_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t us_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void us_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable us ticker interrupt
+ *
+ */
+void us_ticker_disable_interrupt(void);
+
+/** Clear us ticker interrupt
+ *
+ */
+void us_ticker_clear_interrupt(void);
+
+/** Set pending interrupt that should be fired right away.
+ * 
+ * The ticker should be initialized prior calling this function.
+ */
+void us_ticker_fire_interrupt(void);
+
+/** Get frequency and counter bits of this ticker.
+ *
+ */
+const ticker_info_t* us_ticker_get_info(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/mbed.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/mbed.h
new file mode 100755
index 0000000..1e56e63
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/mbed.h
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_H
+#define MBED_H
+
+#if MBED_CONF_RTOS_PRESENT
+#include "rtos/rtos.h"
+#endif
+
+#if MBED_CONF_NSAPI_PRESENT
+#include "netsocket/nsapi.h"
+#include "netsocket/nsapi_ppp.h"
+#endif
+
+#if MBED_CONF_EVENTS_PRESENT
+#include "events/mbed_events.h"
+#endif
+
+#if MBED_CONF_FILESYSTEM_PRESENT
+#include "filesystem/mbed_filesystem.h"
+#endif
+
+#include "platform/mbed_toolchain.h"
+#include "platform/platform.h"
+#include "platform/mbed_application.h"
+
+// Useful C libraries
+#include <math.h>
+#include <time.h>
+
+// mbed Debug libraries
+#include "platform/mbed_error.h"
+#include "platform/mbed_interface.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_debug.h"
+
+// mbed Peripheral components
+#include "drivers/DigitalIn.h"
+#include "drivers/DigitalOut.h"
+#include "drivers/DigitalInOut.h"
+#include "drivers/BusIn.h"
+#include "drivers/BusOut.h"
+#include "drivers/BusInOut.h"
+#include "drivers/PortIn.h"
+#include "drivers/PortInOut.h"
+#include "drivers/PortOut.h"
+#include "drivers/AnalogIn.h"
+#include "drivers/AnalogOut.h"
+#include "drivers/PwmOut.h"
+#include "drivers/Serial.h"
+#include "drivers/SPI.h"
+#include "drivers/SPISlave.h"
+#include "drivers/I2C.h"
+#include "drivers/I2CSlave.h"
+#include "drivers/Ethernet.h"
+#include "drivers/CAN.h"
+#include "drivers/RawSerial.h"
+#include "drivers/UARTSerial.h"
+#include "drivers/FlashIAP.h"
+
+// mbed Internal components
+#include "drivers/Timer.h"
+#include "drivers/Ticker.h"
+#include "drivers/Timeout.h"
+#include "drivers/LowPowerTimeout.h"
+#include "drivers/LowPowerTicker.h"
+#include "drivers/LowPowerTimer.h"
+#include "platform/LocalFileSystem.h"
+#include "drivers/InterruptIn.h"
+#include "platform/mbed_wait_api.h"
+#include "hal/sleep_api.h"
+#include "platform/mbed_sleep.h"
+#include "platform/mbed_rtc_time.h"
+#include "platform/mbed_poll.h"
+#include "platform/ATCmdParser.h"
+#include "platform/FileSystemHandle.h"
+#include "platform/FileHandle.h"
+#include "platform/DirHandle.h"
+#include "platform/CriticalSectionLock.h"
+#include "platform/DeepSleepLock.h"
+
+// mbed Non-hardware components
+#include "platform/Callback.h"
+#include "platform/FunctionPointer.h"
+
+using namespace mbed;
+using namespace std;
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/ATCmdParser.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/ATCmdParser.cpp
new file mode 100755
index 0000000..a787b58
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/ATCmdParser.cpp
@@ -0,0 +1,423 @@
+/* Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * @section DESCRIPTION
+ *
+ * Parser for the AT command syntax
+ *
+ */
+
+#include "ATCmdParser.h"
+#include "mbed_poll.h"
+#include "mbed_debug.h"
+
+#ifdef LF
+#undef LF
+#define LF  10
+#else
+#define LF  10
+#endif
+
+#ifdef CR
+#undef CR
+#define CR  13
+#else
+#define CR  13
+#endif
+
+// getc/putc handling with timeouts
+int ATCmdParser::putc(char c)
+{
+    pollfh fhs;
+    fhs.fh = _fh;
+    fhs.events = POLLOUT;
+
+    int count = poll(&fhs, 1, _timeout);
+    if (count > 0 && (fhs.revents & POLLOUT)) {
+        return _fh->write(&c, 1) == 1 ? 0 : -1;
+    } else {
+        return -1;
+    }
+}
+
+int ATCmdParser::getc()
+{
+    pollfh fhs;
+    fhs.fh = _fh;
+    fhs.events = POLLIN;
+
+    int count = poll(&fhs, 1, _timeout);
+    if (count > 0 && (fhs.revents & POLLIN)) {
+        unsigned char ch;
+        return _fh->read(&ch, 1) == 1 ? ch : -1;
+    } else {
+        return -1;
+    }
+}
+
+void ATCmdParser::flush()
+{
+    while (_fh->readable()) {
+        unsigned char ch;
+        _fh->read(&ch, 1);
+    }
+}
+
+
+// read/write handling with timeouts
+int ATCmdParser::write(const char *data, int size)
+{
+    int i = 0;
+    for ( ; i < size; i++) {
+        if (putc(data[i]) < 0) {
+            return -1;
+        }
+    }
+    return i;
+}
+
+int ATCmdParser::read(char *data, int size)
+{
+    int i = 0;
+    for ( ; i < size; i++) {
+        int c = getc();
+        if (c < 0) {
+            return -1;
+        }
+        data[i] = c;
+    }
+    return i;
+}
+
+
+// printf/scanf handling
+int ATCmdParser::vprintf(const char *format, va_list args)
+{
+
+    if (vsprintf(_buffer, format, args) < 0) {
+        return false;
+    }
+
+    int i = 0;
+    for ( ; _buffer[i]; i++) {
+        if (putc(_buffer[i]) < 0) {
+            return -1;
+        }
+    }
+    return i;
+}
+
+int ATCmdParser::vscanf(const char *format, va_list args)
+{
+    // Since format is const, we need to copy it into our buffer to
+    // add the line's null terminator and clobber value-matches with asterisks.
+    //
+    // We just use the beginning of the buffer to avoid unnecessary allocations.
+    int i = 0;
+    int offset = 0;
+
+    while (format[i]) {
+        if (format[i] == '%' && format[i+1] != '%' && format[i+1] != '*') {
+            _buffer[offset++] = '%';
+            _buffer[offset++] = '*';
+            i++;
+        } else {
+            _buffer[offset++] = format[i++];
+        }
+    }
+
+    // Scanf has very poor support for catching errors
+    // fortunately, we can abuse the %n specifier to determine
+    // if the entire string was matched.
+    _buffer[offset++] = '%';
+    _buffer[offset++] = 'n';
+    _buffer[offset++] = 0;
+
+    // To workaround scanf's lack of error reporting, we actually
+    // make two passes. One checks the validity with the modified
+    // format string that only stores the matched characters (%n).
+    // The other reads in the actual matched values.
+    //
+    // We keep trying the match until we succeed or some other error
+    // derails us.
+    int j = 0;
+
+    while (true) {
+        // Ran out of space
+        if (j+1 >= _buffer_size - offset) {
+            return false;
+        }
+        // Recieve next character
+        int c = getc();
+        if (c < 0) {
+            return -1;
+        }
+        _buffer[offset + j++] = c;
+        _buffer[offset + j] = 0;
+
+        // Check for match
+        int count = -1;
+        sscanf(_buffer+offset, _buffer, &count);
+
+        // We only succeed if all characters in the response are matched
+        if (count == j) {
+            // Store the found results
+            vsscanf(_buffer+offset, format, args);
+            return j;
+        }
+    }
+}
+
+
+// Command parsing with line handling
+bool ATCmdParser::vsend(const char *command, va_list args)
+{
+    // Create and send command
+    if (vsprintf(_buffer, command, args) < 0) {
+        return false;
+    }
+
+    for (int i = 0; _buffer[i]; i++) {
+        if (putc(_buffer[i]) < 0) {
+            return false;
+        }
+    }
+
+    // Finish with newline
+    for (size_t i = 0; _output_delimiter[i]; i++) {
+        if (putc(_output_delimiter[i]) < 0) {
+            return false;
+        }
+    }
+
+    debug_if(_dbg_on, "AT> %s\n", _buffer);
+    return true;
+}
+
+bool ATCmdParser::vrecv(const char *response, va_list args)
+{
+restart:
+    _aborted = false;
+    // Iterate through each line in the expected response
+    while (response[0]) {
+        // Since response is const, we need to copy it into our buffer to
+        // add the line's null terminator and clobber value-matches with asterisks.
+        //
+        // We just use the beginning of the buffer to avoid unnecessary allocations.
+        int i = 0;
+        int offset = 0;
+        bool whole_line_wanted = false;
+
+        while (response[i]) {
+            if (response[i] == '%' && response[i+1] != '%' && response[i+1] != '*') {
+                _buffer[offset++] = '%';
+                _buffer[offset++] = '*';
+                i++;
+            } else {
+                _buffer[offset++] = response[i++];
+                // Find linebreaks, taking care not to be fooled if they're in a %[^\n] conversion specification
+                if (response[i - 1] == '\n' && !(i >= 3 && response[i-3] == '[' && response[i-2] == '^')) {
+                    whole_line_wanted = true;
+                    break;
+                }
+            }
+        }
+
+        // Scanf has very poor support for catching errors
+        // fortunately, we can abuse the %n specifier to determine
+        // if the entire string was matched.
+        _buffer[offset++] = '%';
+        _buffer[offset++] = 'n';
+        _buffer[offset++] = 0;
+
+        debug_if(_dbg_on, "AT? %s\n", _buffer);
+        // To workaround scanf's lack of error reporting, we actually
+        // make two passes. One checks the validity with the modified
+        // format string that only stores the matched characters (%n).
+        // The other reads in the actual matched values.
+        //
+        // We keep trying the match until we succeed or some other error
+        // derails us.
+        int j = 0;
+
+        while (true) {
+            // Receive next character
+            int c = getc();
+            if (c < 0) {
+                debug_if(_dbg_on, "AT(Timeout)\n");
+                return false;
+            }
+            // Simplify newlines (borrowed from retarget.cpp)
+            if ((c == CR && _in_prev != LF) ||
+                (c == LF && _in_prev != CR)) {
+                _in_prev = c;
+                c = '\n';
+            } else if ((c == CR && _in_prev == LF) ||
+                       (c == LF && _in_prev == CR)) {
+                _in_prev = c;
+                // onto next character
+                continue;
+            } else {
+                _in_prev = c;
+            }
+            _buffer[offset + j++] = c;
+            _buffer[offset + j] = 0;
+
+            // Check for oob data
+            for (struct oob *oob = _oobs; oob; oob = oob->next) {
+                if ((unsigned)j == oob->len && memcmp(
+                        oob->prefix, _buffer+offset, oob->len) == 0) {
+                    debug_if(_dbg_on, "AT! %s\n", oob->prefix);
+                    oob->cb();
+
+                    if (_aborted) {
+                        debug_if(_dbg_on, "AT(Aborted)\n");
+                        return false;
+                    }
+                    // oob may have corrupted non-reentrant buffer,
+                    // so we need to set it up again
+                    goto restart;
+                }
+            }
+
+            // Check for match
+            int count = -1;
+            if (whole_line_wanted && c != '\n') {
+                // Don't attempt scanning until we get delimiter if they included it in format
+                // This allows recv("Foo: %s\n") to work, and not match with just the first character of a string
+                // (scanf does not itself match whitespace in its format string, so \n is not significant to it)
+            } else {
+                sscanf(_buffer+offset, _buffer, &count);
+            }
+
+            // We only succeed if all characters in the response are matched
+            if (count == j) {
+                debug_if(_dbg_on, "AT= %s\n", _buffer+offset);
+                // Reuse the front end of the buffer
+                memcpy(_buffer, response, i);
+                _buffer[i] = 0;
+
+                // Store the found results
+                vsscanf(_buffer+offset, _buffer, args);
+
+                // Jump to next line and continue parsing
+                response += i;
+                break;
+            }
+
+            // Clear the buffer when we hit a newline or ran out of space
+            // running out of space usually means we ran into binary data
+            if (c == '\n' || j+1 >= _buffer_size - offset) {
+                debug_if(_dbg_on, "AT< %s", _buffer+offset);
+                j = 0;
+            }
+        }
+    }
+
+    return true;
+}
+
+// Mapping to vararg functions
+int ATCmdParser::printf(const char *format, ...)
+{
+    va_list args;
+    va_start(args, format);
+    int res = vprintf(format, args);
+    va_end(args);
+    return res;
+}
+
+int ATCmdParser::scanf(const char *format, ...)
+{
+    va_list args;
+    va_start(args, format);
+    int res = vscanf(format, args);
+    va_end(args);
+    return res;
+}
+
+bool ATCmdParser::send(const char *command, ...)
+{
+    va_list args;
+    va_start(args, command);
+    bool res = vsend(command, args);
+    va_end(args);
+    return res;
+}
+
+bool ATCmdParser::recv(const char *response, ...)
+{
+    va_list args;
+    va_start(args, response);
+    bool res = vrecv(response, args);
+    va_end(args);
+    return res;
+}
+
+// oob registration
+void ATCmdParser::oob(const char *prefix, Callback<void()> cb)
+{
+    struct oob *oob = new struct oob;
+    oob->len = strlen(prefix);
+    oob->prefix = prefix;
+    oob->cb = cb;
+    oob->next = _oobs;
+    _oobs = oob;
+}
+
+void ATCmdParser::abort()
+{
+    _aborted = true;
+}
+
+bool ATCmdParser::process_oob()
+{
+    if (!_fh->readable()) {
+        return false;
+    }
+
+    int i = 0;
+    while (true) {
+        // Receive next character
+        int c = getc();
+        if (c < 0) {
+            return false;
+        }
+        _buffer[i++] = c;
+        _buffer[i] = 0;
+
+        // Check for oob data
+        struct oob *oob = _oobs;
+        while (oob) {
+            if (i == (int)oob->len && memcmp(
+                    oob->prefix, _buffer, oob->len) == 0) {
+                debug_if(_dbg_on, "AT! %s\r\n", oob->prefix);
+                oob->cb();
+                return true;
+            }
+            oob = oob->next;
+        }
+        
+        // Clear the buffer when we hit a newline or ran out of space
+        // running out of space usually means we ran into binary data
+        if (i+1 >= _buffer_size ||
+            strcmp(&_buffer[i-_output_delim_size], _output_delimiter) == 0) {
+
+            debug_if(_dbg_on, "AT< %s", _buffer);
+            i = 0;
+        }
+    }
+}
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/ATCmdParser.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/ATCmdParser.h
new file mode 100755
index 0000000..1201a60
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/ATCmdParser.h
@@ -0,0 +1,304 @@
+/* Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * @section DESCRIPTION
+ *
+ * Parser for the AT command syntax
+ *
+ */
+#ifndef MBED_ATCMDPARSER_H
+#define MBED_ATCMDPARSER_H
+
+#include "mbed.h"
+#include <cstdarg>
+#include "Callback.h"
+
+/**
+ * Parser class for parsing AT commands
+ *
+ * Here are some examples:
+ * @code
+ * UARTSerial serial = UARTSerial(D1, D0);
+ * ATCmdParser at = ATCmdParser(&serial, "\r\n");
+ * int value;
+ * char buffer[100];
+ *
+ * at.send("AT") && at.recv("OK");
+ * at.send("AT+CWMODE=%d", 3) && at.recv("OK");
+ * at.send("AT+CWMODE?") && at.recv("+CWMODE:%d\r\nOK", &value);
+ * at.recv("+IPD,%d:", &value);
+ * at.read(buffer, value);
+ * at.recv("OK");
+ * @endcode
+ */
+
+namespace mbed {
+
+class ATCmdParser : private NonCopyable<ATCmdParser>
+{
+private:
+    // File handle
+    // Not owned by ATCmdParser
+    FileHandle *_fh;
+
+    int _buffer_size;
+    char *_buffer;
+    int _timeout;
+
+    // Parsing information
+    const char *_output_delimiter;
+    int _output_delim_size;
+    char _in_prev;
+    bool _dbg_on;
+    bool _aborted;
+
+    struct oob {
+        unsigned len;
+        const char *prefix;
+        mbed::Callback<void()> cb;
+        oob *next;
+    };
+    oob *_oobs;
+
+public:
+
+    /**
+     * Constructor
+     *
+     * @param fh A FileHandle to a digital interface to use for AT commands
+     * @param output_delimiter end of command line termination
+     * @param buffer_size size of internal buffer for transaction
+     * @param timeout timeout of the connection
+     * @param debug turns on/off debug output for AT commands
+     */
+    ATCmdParser(FileHandle *fh, const char *output_delimiter = "\r",
+             int buffer_size = 256, int timeout = 8000, bool debug = false)
+            : _fh(fh), _buffer_size(buffer_size), _in_prev(0), _oobs(NULL)
+    {
+        _buffer = new char[buffer_size];
+        set_timeout(timeout);
+        set_delimiter(output_delimiter);
+        debug_on(debug);
+    }
+
+    /**
+     * Destructor
+     */
+    ~ATCmdParser()
+    {
+        while (_oobs) {
+            struct oob *oob = _oobs;
+            _oobs = oob->next;
+            delete oob;
+        }
+        delete[] _buffer;
+    }
+
+    /**
+     * Allows timeout to be changed between commands
+     *
+     * @param timeout timeout of the connection
+     */
+    void set_timeout(int timeout)
+    {
+        _timeout = timeout;
+    }
+
+    /**
+     * For backwards compatibility.
+     *
+     * Please use set_timeout(int) API only from now on.
+     * Allows timeout to be changed between commands
+     *
+     * @param timeout timeout of the connection
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with set_timeout for consistency")
+    void setTimeout(int timeout)
+    {
+        set_timeout(timeout);
+    }
+
+    /**
+     * Sets string of characters to use as line delimiters
+     *
+     * @param output_delimiter string of characters to use as line delimiters
+     */
+    void set_delimiter(const char *output_delimiter)
+    {
+        _output_delimiter = output_delimiter;
+        _output_delim_size = strlen(output_delimiter);
+    }
+
+    /**
+     * For backwards compatibility.
+     *
+     * Please use set_delimiter(const char *) API only from now on.
+     * Sets string of characters to use as line delimiters
+     *
+     * @param output_delimiter string of characters to use as line delimiters
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with set_delimiter for consistency")
+    void setDelimiter(const char *output_delimiter)
+    {
+        set_delimiter(output_delimiter);
+    }
+
+    /**
+     * Allows traces from modem to be turned on or off
+     *
+     * @param on set as 1 to turn on traces and vice versa.
+     */
+    void debug_on(uint8_t on)
+    {
+        _dbg_on = (on) ? 1 : 0;
+    }
+
+    /**
+     * For backwards compatibility.
+     *
+     * Allows traces from modem to be turned on or off
+     *
+     * @param on set as 1 to turn on traces and vice versa.
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with debug_on for consistency")
+    void debugOn(uint8_t on)
+    {
+        debug_on(on);
+    }
+
+    /**
+     * Sends an AT command
+     *
+     * Sends a formatted command using printf style formatting
+     * @see printf
+     *
+     * @param command printf-like format string of command to send which
+     *                is appended with a newline
+     * @param ... all printf-like arguments to insert into command
+     * @return true only if command is successfully sent
+     */
+    bool send(const char *command, ...) MBED_PRINTF_METHOD(1,2);
+
+    bool vsend(const char *command, va_list args);
+
+    /**
+     * Receive an AT response
+     *
+     * Receives a formatted response using scanf style formatting
+     * @see scanf
+     *
+     * Responses are parsed line at a time.
+     * Any received data that does not match the response is ignored until
+     * a timeout occurs.
+     *
+     * @param response scanf-like format string of response to expect
+     * @param ... all scanf-like arguments to extract from response
+     * @return true only if response is successfully matched
+     */
+    bool recv(const char *response, ...) MBED_SCANF_METHOD(1,2);
+
+    bool vrecv(const char *response, va_list args);
+
+    /**
+     * Write a single byte to the underlying stream
+     *
+     * @param c The byte to write
+     * @return The byte that was written or -1 during a timeout
+     */
+    int putc(char c);
+
+    /**
+     * Get a single byte from the underlying stream
+     *
+     * @return The byte that was read or -1 during a timeout
+     */
+    int getc();
+
+    /**
+     * Write an array of bytes to the underlying stream
+     *
+     * @param data the array of bytes to write
+     * @param size number of bytes to write
+     * @return number of bytes written or -1 on failure
+     */
+    int write(const char *data, int size);
+
+    /**
+     * Read an array of bytes from the underlying stream
+     *
+     * @param data the destination for the read bytes
+     * @param size number of bytes to read
+     * @return number of bytes read or -1 on failure
+     */
+    int read(char *data, int size);
+
+    /**
+     * Direct printf to underlying stream
+     * @see printf
+     *
+     * @param format format string to pass to printf
+     * @param ... arguments to printf
+     * @return number of bytes written or -1 on failure
+     */
+    int printf(const char *format, ...) MBED_PRINTF_METHOD(1,2);
+
+    int vprintf(const char *format, va_list args);
+
+    /**
+     * Direct scanf on underlying stream
+     * @see scanf
+     *
+     * @param format format string to pass to scanf
+     * @param ... arguments to scanf
+     * @return number of bytes read or -1 on failure
+     */
+    int scanf(const char *format, ...) MBED_SCANF_METHOD(1,2);
+
+    int vscanf(const char *format, va_list args);
+
+    /**
+     * Attach a callback for out-of-band data
+     *
+     * @param prefix string on when to initiate callback
+     * @param func callback to call when string is read
+     * @note out-of-band data is only processed during a scanf call
+     */
+    void oob(const char *prefix, mbed::Callback<void()> func);
+
+    /**
+     * Flushes the underlying stream
+     */
+    void flush();
+
+    /**
+     * Abort current recv
+     *
+     * Can be called from oob handler to interrupt the current
+     * recv operation.
+     */
+    void abort();
+    
+    /**
+    * Process out-of-band data
+    *
+    * Process out-of-band data in the receive buffer. This function
+    * returns immediately if there is no data to process.
+    *
+    * @return true if oob data processed, false otherwise
+    */
+    bool process_oob(void);
+};
+} //namespace mbed
+
+#endif //MBED_ATCMDPARSER_H
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CThunk.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CThunk.h
new file mode 100755
index 0000000..90e150b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CThunk.h
@@ -0,0 +1,247 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ *
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ */
+
+#ifndef __CTHUNK_H__
+#define __CTHUNK_H__
+
+#define CTHUNK_ADDRESS 1
+#define CTHUNK_VARIABLES volatile uint32_t code[2]
+
+#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7) || defined(__CORTEX_A9) \
+    || defined(__CORTEX_M23) || defined(__CORTEX_M33))
+/**
+* CTHUNK disassembly for Cortex-M3/M4/M7/A9 (thumb2):
+* * adr  r0, #4
+* * ldm  r0, {r0, r1, r2, pc}
+*
+* This instruction loads the arguments for the static thunking function to r0-r2, and
+* branches to that function by loading its address into PC.
+*
+* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
+* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
+*/
+#define CTHUNK_ASSIGMENT do {                              \
+                             m_thunk.code[0] = 0xE890A001; \
+                             m_thunk.code[1] = 0x00008007; \
+                         } while (0)
+
+#elif (defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0))
+/*
+* CTHUNK disassembly for Cortex M0/M0+ (thumb):
+* * adr  r0, #4
+* * ldm  r0, {r0, r1, r2, r3}
+* * bx   r3
+*/
+#define CTHUNK_ASSIGMENT do {                              \
+                             m_thunk.code[0] = 0xC80FA001; \
+                             m_thunk.code[1] = 0x00004718; \
+                         } while (0)
+
+#else
+#error "Target is not currently suported."
+#endif
+
+/* IRQ/Exception compatible thunk entry function */
+typedef void (*CThunkEntry)(void);
+/** @}*/
+
+/**
+ * Class for created a pointer with data bound to it
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template<class T>
+class CThunk
+{
+    public:
+        typedef void (T::*CCallbackSimple)(void);
+        typedef void (T::*CCallback)(void* context);
+
+        inline CThunk(T *instance)
+        {
+            init(instance, NULL, NULL);
+        }
+
+        inline CThunk(T *instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        ~CThunk() {
+
+        }
+
+        inline CThunk(T *instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback, void* context)
+        {
+            init(instance, callback, context);
+        }
+
+        inline void callback(CCallback callback)
+        {
+            m_callback = callback;
+        }
+
+        inline void callback(CCallbackSimple callback)
+        {
+            m_callback = (CCallback)callback;
+        }
+
+        inline void context(void* context)
+        {
+            m_thunk.context = (uint32_t)context;
+        }
+
+        inline void context(uint32_t context)
+        {
+            m_thunk.context = context;
+        }
+        
+        inline uint32_t entry(void)
+        {
+            return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator CThunkEntry(void)
+        {
+            return (CThunkEntry)entry();
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator uint32_t(void)
+        {
+            return entry();
+        }
+
+        /* simple test function */
+        inline void call(void)
+        {
+            (((CThunkEntry)(entry()))());
+        }
+
+    private:
+        T* m_instance;
+        volatile CCallback m_callback;
+
+// TODO: this needs proper fix, to refactor toolchain header file and all its use
+// PACKED there is not defined properly for IAR
+#if defined (__ICCARM__)
+        typedef __packed struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        }  CThunkTrampoline;
+#else
+        typedef struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        } __attribute__((__packed__)) CThunkTrampoline;
+#endif
+
+        static void trampoline(T* instance, void* context, CCallback* callback)
+        {
+            if(instance && *callback) {
+                (static_cast<T*>(instance)->**callback)(context);
+            }
+        }
+
+        volatile CThunkTrampoline m_thunk;
+
+        inline void init(T *instance, CCallback callback, void* context)
+        {
+            /* remember callback - need to add this level of redirection
+               as pointer size for member functions differs between platforms */
+            m_callback = callback;
+
+            /* populate thunking trampoline */
+            CTHUNK_ASSIGMENT;
+            m_thunk.context = (uint32_t)context;
+            m_thunk.instance = (uint32_t)instance;
+            m_thunk.callback = (uint32_t)&m_callback;
+            m_thunk.trampoline = (uint32_t)&trampoline;
+
+#if defined(__CORTEX_A9)
+            /* Data cache clean */
+            /* Cache control */
+            {
+                uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0;
+                uint32_t end_addr   = (uint32_t)&m_thunk + sizeof(m_thunk);
+                uint32_t addr;
+                
+                /* Data cache clean and invalid */
+                for (addr = start_addr; addr < end_addr; addr += 0x20) {
+                    __v7_clean_inv_dcache_mva((void *)addr);
+                }
+                /* Instruction cache invalid */
+                __v7_inv_icache_all();
+                __ca9u_inv_tlb_all();
+                __v7_inv_btac();
+            }
+#endif
+#if defined(__CORTEX_M7)
+            /* Data cache clean and invalid */
+            SCB_CleanInvalidateDCache();
+
+            /* Instruction cache invalid */
+            SCB_InvalidateICache();
+#endif
+            __ISB();
+            __DSB();
+        }
+};
+
+#endif/*__CTHUNK_H__*/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CallChain.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CallChain.cpp
new file mode 100755
index 0000000..c9ee38c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CallChain.cpp
@@ -0,0 +1,116 @@
+#include "platform/CallChain.h"
+#include "cmsis.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+class CallChainLink {
+public:
+    CallChainLink(): cb(), next(NULL) {
+        // No work to do
+    }
+
+    CallChainLink(Callback<void()> &callback): cb(callback), next(NULL) {
+        // No work to do
+    }
+    Callback<void()> cb;
+    CallChainLink * next;
+};
+
+CallChain::CallChain(int size) : _chain(NULL) {
+    // No work to do
+}
+
+CallChain::~CallChain() {
+    clear();
+}
+
+pFunctionPointer_t CallChain::add(Callback<void()> func) {
+    CallChainLink *new_link = new CallChainLink(func);
+    if (NULL == _chain) {
+        _chain = new_link;
+        return &new_link->cb;
+    }
+
+    CallChainLink *link = _chain;
+    while (true) {
+        if (NULL == link->next) {
+            link->next = new_link;
+            return &new_link->cb;
+        }
+        link = link->next;
+    }
+}
+
+pFunctionPointer_t CallChain::add_front(Callback<void()> func) {
+    CallChainLink *link = new CallChainLink(func);
+    link->next = _chain;
+    _chain = link;
+    return &link->cb;
+}
+
+int CallChain::size() const {
+    CallChainLink *link = _chain;
+    int elements = 0;
+    while (link != NULL) {
+        elements++;
+        link = link->next;
+    }
+    return elements;
+}
+
+pFunctionPointer_t CallChain::get(int idx) const {
+    CallChainLink *link = _chain;
+    for (int i = 0; i < idx; i++) {
+        if (NULL == link) {
+            break;
+        }
+        link = link->next;
+    }
+    return &link->cb;
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+    CallChainLink *link = _chain;
+    int i = 0;
+    while (link != NULL) {
+        if (f == &link->cb) {
+            return i;
+        }
+        i++;
+        link = link->next;
+    }
+    return -1;
+}
+
+void CallChain::clear() {
+    CallChainLink *link = _chain;
+    _chain = NULL;
+    while (link != NULL) {
+        CallChainLink *temp = link->next;
+        delete link;
+        link = temp;
+    }
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+    CallChainLink *link = _chain;
+    while (link != NULL) {
+        if (f == &link->cb) {
+            delete link;
+            return true;
+        }
+        link = link->next;
+    }
+    return false;
+}
+
+void CallChain::call() {
+    CallChainLink *link = _chain;
+    while (link != NULL) {
+        link->cb.call();
+        link = link->next;
+    }
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CallChain.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CallChain.h
new file mode 100755
index 0000000..42e97e6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CallChain.h
@@ -0,0 +1,189 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+#include <string.h>
+
+namespace mbed {
+/** \addtogroup platform */
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ *     printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ *     printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ *     void f(void) {
+ *         printf("A::f (class member).\n");
+ *     }
+ * };
+ *
+ * int main() {
+ *     Test test;
+ *
+ *     chain.add(second);
+ *     chain.add_front(first);
+ *     chain.add(&test, &Test::f);
+ *     chain.call();
+ * }
+ * @endcode
+ * @ingroup platform
+ */
+
+typedef Callback<void()> *pFunctionPointer_t;
+class CallChainLink;
+
+class CallChain : private NonCopyable<CallChain> {
+public:
+    /** Create an empty chain
+     *
+     *  @param size (optional) Initial size of the chain
+     */
+    CallChain(int size = 4);
+    virtual ~CallChain();
+
+    /** Add a function at the end of the chain
+     *
+     *  @param func A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'func'
+     */
+    pFunctionPointer_t add(Callback<void()> func);
+
+    /** Add a function at the end of the chain
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'obj' and 'method'
+     *
+     *  @deprecated
+     *  The add function does not support cv-qualifiers. Replaced by
+     *  add(callback(obj, method)).
+     */
+    template<typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The add function does not support cv-qualifiers. Replaced by "
+        "add(callback(obj, method)).")
+    pFunctionPointer_t add(T *obj, M method) {
+        return add(callback(obj, method));
+    }
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param func A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'func'
+     */
+    pFunctionPointer_t add_front(Callback<void()> func);
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     *
+     *  @deprecated
+     *  The add_front function does not support cv-qualifiers. Replaced by
+     *  add_front(callback(obj, method)).
+     */
+    template<typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The add_front function does not support cv-qualifiers. Replaced by "
+        "add_front(callback(obj, method)).")
+    pFunctionPointer_t add_front(T *obj, M method) {
+        return add_front(callback(obj, method));
+    }
+
+    /** Get the number of functions in the chain
+     */
+    int size() const;
+
+    /** Get a function object from the chain
+     *
+     *  @param i function object index
+     *
+     *  @returns
+     *  The function object at position 'i' in the chain
+     */
+    pFunctionPointer_t get(int i) const;
+
+    /** Look for a function object in the call chain
+     *
+     *  @param f the function object to search
+     *
+     *  @returns
+     *  The index of the function object if found, -1 otherwise.
+     */
+    int find(pFunctionPointer_t f) const;
+
+    /** Clear the call chain (remove all functions in the chain).
+     */
+    void clear();
+
+    /** Remove a function object from the chain
+     *
+     *  @arg f the function object to remove
+     *
+     *  @returns
+     *  true if the function object was found and removed, false otherwise.
+     */
+    bool remove(pFunctionPointer_t f);
+
+    /** Call all the functions in the chain in sequence
+     */
+    void call();
+
+    void operator ()(void) {
+        call();
+    }
+    pFunctionPointer_t operator [](int i) const {
+        return get(i);
+    }
+
+private:
+    CallChainLink *_chain;
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Callback.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Callback.h
new file mode 100755
index 0000000..cb2c5a9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Callback.h
@@ -0,0 +1,4552 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLBACK_H
+#define MBED_CALLBACK_H
+
+#include <string.h>
+#include <stdint.h>
+#include <new>
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename F>
+class Callback;
+
+// Internal sfinae declarations
+//
+// These are used to eliminate overloads based on type attributes
+// 1. Does a function object have a call operator
+// 2. Does a function object fit in the available storage
+//
+// These eliminations are handled cleanly by the compiler and avoid
+// massive and misleading error messages when confronted with an
+// invalid type (or worse, runtime failures)
+namespace detail {
+    struct nil {};
+
+    template <bool B, typename R = nil>
+    struct enable_if { typedef R type; };
+
+    template <typename R>
+    struct enable_if<false, R> {};
+
+    template <typename M, M>
+    struct is_type {
+        static const bool value = true;
+    };
+}
+
+#define MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)                            \
+    typename detail::enable_if<                                             \
+            detail::is_type<M, &F::operator()>::value &&                    \
+            sizeof(F) <= sizeof(uintptr_t)                                  \
+        >::type = detail::nil()
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R>
+class Callback<R()> {
+public:
+    /** Create a Callback with a static function
+     *  @param func     Static function to attach
+     */
+    Callback(R (*func)() = 0) {
+        if (!func) {
+            memset(this, 0, sizeof(Callback));
+        } else {
+            generate(func);
+        }
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     */
+    Callback(const Callback<R()> &func) {
+        if (func._ops) {
+            func._ops->move(this, &func);
+        }
+        _ops = func._ops;
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(U *obj, R (T::*method)()) {
+        generate(method_context<T, R (T::*)()>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const U *obj, R (T::*method)() const) {
+        generate(method_context<const T, R (T::*)() const>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(volatile U *obj, R (T::*method)() volatile) {
+        generate(method_context<volatile T, R (T::*)() volatile>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const volatile U *obj, R (T::*method)() const volatile) {
+        generate(method_context<const volatile T, R (T::*)() const volatile>(obj, method));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(T*), U *arg) {
+        generate(function_context<R (*)(T*), T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const T*), const U *arg) {
+        generate(function_context<R (*)(const T*), const T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(volatile T*), volatile U *arg) {
+        generate(function_context<R (*)(volatile T*), volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const volatile T*), const volatile U *arg) {
+        generate(function_context<R (*)(const volatile T*), const volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)())) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(U *obj, R (*func)(T*)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const U *obj, R (*func)(const T*)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(volatile U *obj, R (*func)(volatile T*)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const volatile U *obj, R (*func)(const volatile T*)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Destroy a callback
+     */
+    ~Callback() {
+        if (_ops) {
+            _ops->dtor(this);
+        }
+    }
+
+    /** Attach a static function
+     *  @param func     Static function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)()) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const Callback<R()> &func) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(U *obj, R (T::*method)()) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const U *obj, R (T::*method)() const) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile U *obj, R (T::*method)() volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile U *obj, R (T::*method)() const volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(T*), U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const T*), const U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(volatile T*), volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const volatile T*), const volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a function object
+     *  @param f     Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)())) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f     Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(U *obj, R (*func)(T*)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const U *obj, R (*func)(const T*)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(volatile U *obj, R (*func)(volatile T*)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const volatile U *obj, R (*func)(const volatile T*)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Assign a callback
+     */
+    Callback &operator=(const Callback &that) {
+        if (this != &that) {
+            this->~Callback();
+            new (this) Callback(that);
+        }
+
+        return *this;
+    }
+
+    /** Call the attached function
+     */
+    R call() const {
+        MBED_ASSERT(_ops);
+        return _ops->call(this);
+    }
+
+    /** Call the attached function
+     */
+    R operator()() const {
+        return call();
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _ops;
+    }
+
+    /** Test for equality
+     */
+    friend bool operator==(const Callback &l, const Callback &r) {
+        return memcmp(&l, &r, sizeof(Callback)) == 0;
+    }
+
+    /** Test for inequality
+     */
+    friend bool operator!=(const Callback &l, const Callback &r) {
+        return !(l == r);
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     *  @return the value as determined by func which is of 
+     *      type and determined by the signiture of func
+     */
+    static R thunk(void *func) {
+        return static_cast<Callback*>(func)->call();
+    }
+
+private:
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)();
+        void (*_boundfunc)(_class*);
+        void (_class::*_methodfunc)();
+    } _func;
+    void *_obj;
+
+    // Dynamically dispatched operations
+    const struct ops {
+        R (*call)(const void*);
+        void (*move)(void*, const void*);
+        void (*dtor)(void*);
+    } *_ops;
+
+    // Generate operations for function object
+    template <typename F>
+    void generate(const F &f) {
+        static const ops ops = {
+            &Callback::function_call<F>,
+            &Callback::function_move<F>,
+            &Callback::function_dtor<F>,
+        };
+
+        MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+                "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
+        new (this) F(f);
+        _ops = &ops;
+    }
+
+    // Function attributes
+    template <typename F>
+    static R function_call(const void *p) {
+        return (*(F*)p)();
+    }
+
+    template <typename F>
+    static void function_move(void *d, const void *p) {
+        new (d) F(*(F*)p);
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Wrappers for functions with context
+    template <typename O, typename M>
+    struct method_context {
+        M method;
+        O *obj;
+
+        method_context(O *obj, M method)
+            : method(method), obj(obj) {}
+
+        R operator()() const {
+            return (obj->*method)();
+        }
+    };
+
+    template <typename F, typename A>
+    struct function_context {
+        F func;
+        A *arg;
+
+        function_context(F func, A *arg)
+            : func(func), arg(arg) {}
+
+        R operator()() const {
+            return func(arg);
+        }
+    };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0>
+class Callback<R(A0)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func     Static function to attach
+     */
+    Callback(R (*func)(A0) = 0) {
+        if (!func) {
+            memset(this, 0, sizeof(Callback));
+        } else {
+            generate(func);
+        }
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     */
+    Callback(const Callback<R(A0)> &func) {
+        if (func._ops) {
+            func._ops->move(this, &func);
+        }
+        _ops = func._ops;
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(U *obj, R (T::*method)(A0)) {
+        generate(method_context<T, R (T::*)(A0)>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const U *obj, R (T::*method)(A0) const) {
+        generate(method_context<const T, R (T::*)(A0) const>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(volatile U *obj, R (T::*method)(A0) volatile) {
+        generate(method_context<volatile T, R (T::*)(A0) volatile>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const volatile U *obj, R (T::*method)(A0) const volatile) {
+        generate(method_context<const volatile T, R (T::*)(A0) const volatile>(obj, method));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(T*, A0), U *arg) {
+        generate(function_context<R (*)(T*, A0), T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const T*, A0), const U *arg) {
+        generate(function_context<R (*)(const T*, A0), const T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(volatile T*, A0), volatile U *arg) {
+        generate(function_context<R (*)(volatile T*, A0), volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const volatile T*, A0), const volatile U *arg) {
+        generate(function_context<R (*)(const volatile T*, A0), const volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0))) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(U *obj, R (*func)(T*, A0)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const U *obj, R (*func)(const T*, A0)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(volatile U *obj, R (*func)(volatile T*, A0)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const volatile U *obj, R (*func)(const volatile T*, A0)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Destroy a callback
+     */
+    ~Callback() {
+        if (_ops) {
+            _ops->dtor(this);
+        }
+    }
+
+    /** Attach a static function
+     *  @param func     Static function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(A0)) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const Callback<R(A0)> &func) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(U *obj, R (T::*method)(A0)) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const U *obj, R (T::*method)(A0) const) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile U *obj, R (T::*method)(A0) volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile U *obj, R (T::*method)(A0) const volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(T*, A0), U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const T*, A0), const U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(volatile T*, A0), volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const volatile T*, A0), const volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0))) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(U *obj, R (*func)(T*, A0)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const U *obj, R (*func)(const T*, A0)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(volatile U *obj, R (*func)(volatile T*, A0)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const volatile U *obj, R (*func)(const volatile T*, A0)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Assign a callback
+     */
+    Callback &operator=(const Callback &that) {
+        if (this != &that) {
+            this->~Callback();
+            new (this) Callback(that);
+        }
+
+        return *this;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0) const {
+        MBED_ASSERT(_ops);
+        return _ops->call(this, a0);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0) const {
+        return call(a0);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _ops;
+    }
+
+    /** Test for equality
+     */
+    friend bool operator==(const Callback &l, const Callback &r) {
+        return memcmp(&l, &r, sizeof(Callback)) == 0;
+    }
+
+    /** Test for inequality
+     */
+    friend bool operator!=(const Callback &l, const Callback &r) {
+        return !(l == r);
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     *  @param a0 An argument to be called with function func
+     *  @return the value as determined by func which is of 
+     *      type and determined by the signiture of func
+     */
+    static R thunk(void *func, A0 a0) {
+        return static_cast<Callback*>(func)->call(a0);
+    }
+
+private:
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)(A0);
+        void (*_boundfunc)(_class*, A0);
+        void (_class::*_methodfunc)(A0);
+    } _func;
+    void *_obj;
+
+    // Dynamically dispatched operations
+    const struct ops {
+        R (*call)(const void*, A0);
+        void (*move)(void*, const void*);
+        void (*dtor)(void*);
+    } *_ops;
+
+    // Generate operations for function object
+    template <typename F>
+    void generate(const F &f) {
+        static const ops ops = {
+            &Callback::function_call<F>,
+            &Callback::function_move<F>,
+            &Callback::function_dtor<F>,
+        };
+
+        MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+                "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
+        new (this) F(f);
+        _ops = &ops;
+    }
+
+    // Function attributes
+    template <typename F>
+    static R function_call(const void *p, A0 a0) {
+        return (*(F*)p)(a0);
+    }
+
+    template <typename F>
+    static void function_move(void *d, const void *p) {
+        new (d) F(*(F*)p);
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Wrappers for functions with context
+    template <typename O, typename M>
+    struct method_context {
+        M method;
+        O *obj;
+
+        method_context(O *obj, M method)
+            : method(method), obj(obj) {}
+
+        R operator()(A0 a0) const {
+            return (obj->*method)(a0);
+        }
+    };
+
+    template <typename F, typename A>
+    struct function_context {
+        F func;
+        A *arg;
+
+        function_context(F func, A *arg)
+            : func(func), arg(arg) {}
+
+        R operator()(A0 a0) const {
+            return func(arg, a0);
+        }
+    };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1>
+class Callback<R(A0, A1)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func     Static function to attach
+     */
+    Callback(R (*func)(A0, A1) = 0) {
+        if (!func) {
+            memset(this, 0, sizeof(Callback));
+        } else {
+            generate(func);
+        }
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     */
+    Callback(const Callback<R(A0, A1)> &func) {
+        if (func._ops) {
+            func._ops->move(this, &func);
+        }
+        _ops = func._ops;
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(U *obj, R (T::*method)(A0, A1)) {
+        generate(method_context<T, R (T::*)(A0, A1)>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const U *obj, R (T::*method)(A0, A1) const) {
+        generate(method_context<const T, R (T::*)(A0, A1) const>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(volatile U *obj, R (T::*method)(A0, A1) volatile) {
+        generate(method_context<volatile T, R (T::*)(A0, A1) volatile>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const volatile U *obj, R (T::*method)(A0, A1) const volatile) {
+        generate(method_context<const volatile T, R (T::*)(A0, A1) const volatile>(obj, method));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(T*, A0, A1), U *arg) {
+        generate(function_context<R (*)(T*, A0, A1), T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const T*, A0, A1), const U *arg) {
+        generate(function_context<R (*)(const T*, A0, A1), const T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(volatile T*, A0, A1), volatile U *arg) {
+        generate(function_context<R (*)(volatile T*, A0, A1), volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const volatile T*, A0, A1), const volatile U *arg) {
+        generate(function_context<R (*)(const volatile T*, A0, A1), const volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1))) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(U *obj, R (*func)(T*, A0, A1)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const U *obj, R (*func)(const T*, A0, A1)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(volatile U *obj, R (*func)(volatile T*, A0, A1)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Destroy a callback
+     */
+    ~Callback() {
+        if (_ops) {
+            _ops->dtor(this);
+        }
+    }
+
+    /** Attach a static function
+     *  @param func     Static function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(A0, A1)) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const Callback<R(A0, A1)> &func) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(U *obj, R (T::*method)(A0, A1)) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const U *obj, R (T::*method)(A0, A1) const) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile U *obj, R (T::*method)(A0, A1) volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile U *obj, R (T::*method)(A0, A1) const volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(T*, A0, A1), U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const T*, A0, A1), const U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(volatile T*, A0, A1), volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const volatile T*, A0, A1), const volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1))) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(U *obj, R (*func)(T*, A0, A1)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const U *obj, R (*func)(const T*, A0, A1)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(volatile U *obj, R (*func)(volatile T*, A0, A1)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Assign a callback
+     */
+    Callback &operator=(const Callback &that) {
+        if (this != &that) {
+            this->~Callback();
+            new (this) Callback(that);
+        }
+
+        return *this;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1) const {
+        MBED_ASSERT(_ops);
+        return _ops->call(this, a0, a1);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1) const {
+        return call(a0, a1);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _ops;
+    }
+
+    /** Test for equality
+     */
+    friend bool operator==(const Callback &l, const Callback &r) {
+        return memcmp(&l, &r, sizeof(Callback)) == 0;
+    }
+
+    /** Test for inequality
+     */
+    friend bool operator!=(const Callback &l, const Callback &r) {
+        return !(l == r);
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     *  @param a0 An argument to be called with function func
+     *  @param a1 An argument to be called with function func
+     *  @return the value as determined by func which is of 
+     *      type and determined by the signiture of func
+     */
+    static R thunk(void *func, A0 a0, A1 a1) {
+        return static_cast<Callback*>(func)->call(a0, a1);
+    }
+
+private:
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)(A0, A1);
+        void (*_boundfunc)(_class*, A0, A1);
+        void (_class::*_methodfunc)(A0, A1);
+    } _func;
+    void *_obj;
+
+    // Dynamically dispatched operations
+    const struct ops {
+        R (*call)(const void*, A0, A1);
+        void (*move)(void*, const void*);
+        void (*dtor)(void*);
+    } *_ops;
+
+    // Generate operations for function object
+    template <typename F>
+    void generate(const F &f) {
+        static const ops ops = {
+            &Callback::function_call<F>,
+            &Callback::function_move<F>,
+            &Callback::function_dtor<F>,
+        };
+
+        MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+                "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
+        new (this) F(f);
+        _ops = &ops;
+    }
+
+    // Function attributes
+    template <typename F>
+    static R function_call(const void *p, A0 a0, A1 a1) {
+        return (*(F*)p)(a0, a1);
+    }
+
+    template <typename F>
+    static void function_move(void *d, const void *p) {
+        new (d) F(*(F*)p);
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Wrappers for functions with context
+    template <typename O, typename M>
+    struct method_context {
+        M method;
+        O *obj;
+
+        method_context(O *obj, M method)
+            : method(method), obj(obj) {}
+
+        R operator()(A0 a0, A1 a1) const {
+            return (obj->*method)(a0, a1);
+        }
+    };
+
+    template <typename F, typename A>
+    struct function_context {
+        F func;
+        A *arg;
+
+        function_context(F func, A *arg)
+            : func(func), arg(arg) {}
+
+        R operator()(A0 a0, A1 a1) const {
+            return func(arg, a0, a1);
+        }
+    };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1, typename A2>
+class Callback<R(A0, A1, A2)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func     Static function to attach
+     */
+    Callback(R (*func)(A0, A1, A2) = 0) {
+        if (!func) {
+            memset(this, 0, sizeof(Callback));
+        } else {
+            generate(func);
+        }
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     */
+    Callback(const Callback<R(A0, A1, A2)> &func) {
+        if (func._ops) {
+            func._ops->move(this, &func);
+        }
+        _ops = func._ops;
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(U *obj, R (T::*method)(A0, A1, A2)) {
+        generate(method_context<T, R (T::*)(A0, A1, A2)>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const U *obj, R (T::*method)(A0, A1, A2) const) {
+        generate(method_context<const T, R (T::*)(A0, A1, A2) const>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(volatile U *obj, R (T::*method)(A0, A1, A2) volatile) {
+        generate(method_context<volatile T, R (T::*)(A0, A1, A2) volatile>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const volatile U *obj, R (T::*method)(A0, A1, A2) const volatile) {
+        generate(method_context<const volatile T, R (T::*)(A0, A1, A2) const volatile>(obj, method));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(T*, A0, A1, A2), U *arg) {
+        generate(function_context<R (*)(T*, A0, A1, A2), T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const T*, A0, A1, A2), const U *arg) {
+        generate(function_context<R (*)(const T*, A0, A1, A2), const T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(volatile T*, A0, A1, A2), volatile U *arg) {
+        generate(function_context<R (*)(volatile T*, A0, A1, A2), volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const volatile T*, A0, A1, A2), const volatile U *arg) {
+        generate(function_context<R (*)(const volatile T*, A0, A1, A2), const volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2))) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(U *obj, R (*func)(T*, A0, A1, A2)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const U *obj, R (*func)(const T*, A0, A1, A2)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Destroy a callback
+     */
+    ~Callback() {
+        if (_ops) {
+            _ops->dtor(this);
+        }
+    }
+
+    /** Attach a static function
+     *  @param func     Static function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(A0, A1, A2)) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const Callback<R(A0, A1, A2)> &func) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(U *obj, R (T::*method)(A0, A1, A2)) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const U *obj, R (T::*method)(A0, A1, A2) const) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile U *obj, R (T::*method)(A0, A1, A2) volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile U *obj, R (T::*method)(A0, A1, A2) const volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(T*, A0, A1, A2), U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const T*, A0, A1, A2), const U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(volatile T*, A0, A1, A2), volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const volatile T*, A0, A1, A2), const volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2))) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(U *obj, R (*func)(T*, A0, A1, A2)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const U *obj, R (*func)(const T*, A0, A1, A2)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(volatile U *obj, R (*func)(volatile T*, A0, A1, A2)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Assign a callback
+     */
+    Callback &operator=(const Callback &that) {
+        if (this != &that) {
+            this->~Callback();
+            new (this) Callback(that);
+        }
+
+        return *this;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1, A2 a2) const {
+        MBED_ASSERT(_ops);
+        return _ops->call(this, a0, a1, a2);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1, A2 a2) const {
+        return call(a0, a1, a2);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _ops;
+    }
+
+    /** Test for equality
+     */
+    friend bool operator==(const Callback &l, const Callback &r) {
+        return memcmp(&l, &r, sizeof(Callback)) == 0;
+    }
+
+    /** Test for inequality
+     */
+    friend bool operator!=(const Callback &l, const Callback &r) {
+        return !(l == r);
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     *  @param a0 An argument to be called with function func
+     *  @param a1 An argument to be called with function func
+     *  @param a2 An argument to be called with function func
+     *  @return the value as determined by func which is of 
+     *      type and determined by the signiture of func
+     */
+    static R thunk(void *func, A0 a0, A1 a1, A2 a2) {
+        return static_cast<Callback*>(func)->call(a0, a1, a2);
+    }
+
+private:
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)(A0, A1, A2);
+        void (*_boundfunc)(_class*, A0, A1, A2);
+        void (_class::*_methodfunc)(A0, A1, A2);
+    } _func;
+    void *_obj;
+
+    // Dynamically dispatched operations
+    const struct ops {
+        R (*call)(const void*, A0, A1, A2);
+        void (*move)(void*, const void*);
+        void (*dtor)(void*);
+    } *_ops;
+
+    // Generate operations for function object
+    template <typename F>
+    void generate(const F &f) {
+        static const ops ops = {
+            &Callback::function_call<F>,
+            &Callback::function_move<F>,
+            &Callback::function_dtor<F>,
+        };
+
+        MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+                "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
+        new (this) F(f);
+        _ops = &ops;
+    }
+
+    // Function attributes
+    template <typename F>
+    static R function_call(const void *p, A0 a0, A1 a1, A2 a2) {
+        return (*(F*)p)(a0, a1, a2);
+    }
+
+    template <typename F>
+    static void function_move(void *d, const void *p) {
+        new (d) F(*(F*)p);
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Wrappers for functions with context
+    template <typename O, typename M>
+    struct method_context {
+        M method;
+        O *obj;
+
+        method_context(O *obj, M method)
+            : method(method), obj(obj) {}
+
+        R operator()(A0 a0, A1 a1, A2 a2) const {
+            return (obj->*method)(a0, a1, a2);
+        }
+    };
+
+    template <typename F, typename A>
+    struct function_context {
+        F func;
+        A *arg;
+
+        function_context(F func, A *arg)
+            : func(func), arg(arg) {}
+
+        R operator()(A0 a0, A1 a1, A2 a2) const {
+            return func(arg, a0, a1, a2);
+        }
+    };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+class Callback<R(A0, A1, A2, A3)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func     Static function to attach
+     */
+    Callback(R (*func)(A0, A1, A2, A3) = 0) {
+        if (!func) {
+            memset(this, 0, sizeof(Callback));
+        } else {
+            generate(func);
+        }
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     */
+    Callback(const Callback<R(A0, A1, A2, A3)> &func) {
+        if (func._ops) {
+            func._ops->move(this, &func);
+        }
+        _ops = func._ops;
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(U *obj, R (T::*method)(A0, A1, A2, A3)) {
+        generate(method_context<T, R (T::*)(A0, A1, A2, A3)>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const U *obj, R (T::*method)(A0, A1, A2, A3) const) {
+        generate(method_context<const T, R (T::*)(A0, A1, A2, A3) const>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3) volatile) {
+        generate(method_context<volatile T, R (T::*)(A0, A1, A2, A3) volatile>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3) const volatile) {
+        generate(method_context<const volatile T, R (T::*)(A0, A1, A2, A3) const volatile>(obj, method));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(T*, A0, A1, A2, A3), U *arg) {
+        generate(function_context<R (*)(T*, A0, A1, A2, A3), T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const T*, A0, A1, A2, A3), const U *arg) {
+        generate(function_context<R (*)(const T*, A0, A1, A2, A3), const T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(volatile T*, A0, A1, A2, A3), volatile U *arg) {
+        generate(function_context<R (*)(volatile T*, A0, A1, A2, A3), volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const volatile T*, A0, A1, A2, A3), const volatile U *arg) {
+        generate(function_context<R (*)(const volatile T*, A0, A1, A2, A3), const volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3))) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(U *obj, R (*func)(T*, A0, A1, A2, A3)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Destroy a callback
+     */
+    ~Callback() {
+        if (_ops) {
+            _ops->dtor(this);
+        }
+    }
+
+    /** Attach a static function
+     *  @param func     Static function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(A0, A1, A2, A3)) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const Callback<R(A0, A1, A2, A3)> &func) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(U *obj, R (T::*method)(A0, A1, A2, A3)) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const U *obj, R (T::*method)(A0, A1, A2, A3) const) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile U *obj, R (T::*method)(A0, A1, A2, A3) volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile U *obj, R (T::*method)(A0, A1, A2, A3) const volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(T*, A0, A1, A2, A3), U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const T*, A0, A1, A2, A3), const U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(volatile T*, A0, A1, A2, A3), volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const volatile T*, A0, A1, A2, A3), const volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3))) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(U *obj, R (*func)(T*, A0, A1, A2, A3)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const U *obj, R (*func)(const T*, A0, A1, A2, A3)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Assign a callback
+     */
+    Callback &operator=(const Callback &that) {
+        if (this != &that) {
+            this->~Callback();
+            new (this) Callback(that);
+        }
+
+        return *this;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1, A2 a2, A3 a3) const {
+        MBED_ASSERT(_ops);
+        return _ops->call(this, a0, a1, a2, a3);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const {
+        return call(a0, a1, a2, a3);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _ops;
+    }
+
+    /** Test for equality
+     */
+    friend bool operator==(const Callback &l, const Callback &r) {
+        return memcmp(&l, &r, sizeof(Callback)) == 0;
+    }
+
+    /** Test for inequality
+     */
+    friend bool operator!=(const Callback &l, const Callback &r) {
+        return !(l == r);
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     *  @param a0 An argument to be called with function func
+     *  @param a1 An argument to be called with function func
+     *  @param a2 An argument to be called with function func
+     *  @param a3 An argument to be called with function func
+     *  @return the value as determined by func which is of 
+     *      type and determined by the signiture of func
+     */
+    static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return static_cast<Callback*>(func)->call(a0, a1, a2, a3);
+    }
+
+private:
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)(A0, A1, A2, A3);
+        void (*_boundfunc)(_class*, A0, A1, A2, A3);
+        void (_class::*_methodfunc)(A0, A1, A2, A3);
+    } _func;
+    void *_obj;
+
+    // Dynamically dispatched operations
+    const struct ops {
+        R (*call)(const void*, A0, A1, A2, A3);
+        void (*move)(void*, const void*);
+        void (*dtor)(void*);
+    } *_ops;
+
+    // Generate operations for function object
+    template <typename F>
+    void generate(const F &f) {
+        static const ops ops = {
+            &Callback::function_call<F>,
+            &Callback::function_move<F>,
+            &Callback::function_dtor<F>,
+        };
+
+        MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+                "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
+        new (this) F(f);
+        _ops = &ops;
+    }
+
+    // Function attributes
+    template <typename F>
+    static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return (*(F*)p)(a0, a1, a2, a3);
+    }
+
+    template <typename F>
+    static void function_move(void *d, const void *p) {
+        new (d) F(*(F*)p);
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Wrappers for functions with context
+    template <typename O, typename M>
+    struct method_context {
+        M method;
+        O *obj;
+
+        method_context(O *obj, M method)
+            : method(method), obj(obj) {}
+
+        R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const {
+            return (obj->*method)(a0, a1, a2, a3);
+        }
+    };
+
+    template <typename F, typename A>
+    struct function_context {
+        F func;
+        A *arg;
+
+        function_context(F func, A *arg)
+            : func(func), arg(arg) {}
+
+        R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const {
+            return func(arg, a0, a1, a2, a3);
+        }
+    };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+class Callback<R(A0, A1, A2, A3, A4)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func     Static function to attach
+     */
+    Callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
+        if (!func) {
+            memset(this, 0, sizeof(Callback));
+        } else {
+            generate(func);
+        }
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     */
+    Callback(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+        if (func._ops) {
+            func._ops->move(this, &func);
+        }
+        _ops = func._ops;
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(U *obj, R (T::*method)(A0, A1, A2, A3, A4)) {
+        generate(method_context<T, R (T::*)(A0, A1, A2, A3, A4)>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const U *obj, R (T::*method)(A0, A1, A2, A3, A4) const) {
+        generate(method_context<const T, R (T::*)(A0, A1, A2, A3, A4) const>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile) {
+        generate(method_context<volatile T, R (T::*)(A0, A1, A2, A3, A4) volatile>(obj, method));
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     */
+    template<typename T, typename U>
+    Callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile) {
+        generate(method_context<const volatile T, R (T::*)(A0, A1, A2, A3, A4) const volatile>(obj, method));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(T*, A0, A1, A2, A3, A4), U *arg) {
+        generate(function_context<R (*)(T*, A0, A1, A2, A3, A4), T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const T*, A0, A1, A2, A3, A4), const U *arg) {
+        generate(function_context<R (*)(const T*, A0, A1, A2, A3, A4), const T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(volatile T*, A0, A1, A2, A3, A4), volatile U *arg) {
+        generate(function_context<R (*)(volatile T*, A0, A1, A2, A3, A4), volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function 
+     */
+    template<typename T, typename U>
+    Callback(R (*func)(const volatile T*, A0, A1, A2, A3, A4), const volatile U *arg) {
+        generate(function_context<R (*)(const volatile T*, A0, A1, A2, A3, A4), const volatile T>(func, arg));
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4))) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     */
+    template <typename F>
+    Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const volatile)) {
+        generate(f);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(U *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3, A4)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3, A4)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to Callback(func, arg)
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to Callback(func, arg)")
+    Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3, A4)) {
+        new (this) Callback(func, obj);
+    }
+
+    /** Destroy a callback
+     */
+    ~Callback() {
+        if (_ops) {
+            _ops->dtor(this);
+        }
+    }
+
+    /** Attach a static function
+     *  @param func     Static function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(A0, A1, A2, A3, A4)) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a Callback
+     *  @param func     The Callback to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+        this->~Callback();
+        new (this) Callback(func);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(U *obj, R (T::*method)(A0, A1, A2, A3, A4)) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const U *obj, R (T::*method)(A0, A1, A2, A3, A4) const) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a member function
+     *  @param obj      Pointer to object to invoke member function on
+     *  @param method   Member function to attach
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template<typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile) {
+        this->~Callback();
+        new (this) Callback(obj, method);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(T*, A0, A1, A2, A3, A4), U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const T*, A0, A1, A2, A3, A4), const U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(volatile T*, A0, A1, A2, A3, A4), volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param func     Static function to attach
+     *  @param arg      Pointer argument to function
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(R (*func)(const volatile T*, A0, A1, A2, A3, A4), const volatile U *arg) {
+        this->~Callback();
+        new (this) Callback(func, arg);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4))) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a function object
+     *  @param f Function object to attach
+     *  @note The function object is limited to a single word of storage
+     *  @deprecated
+     *      Replaced by simple assignment 'Callback cb = func'
+     */
+    template <typename F>
+    MBED_DEPRECATED_SINCE("mbed-os-5.4",
+        "Replaced by simple assignment 'Callback cb = func")
+    void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const volatile)) {
+        this->~Callback();
+        new (this) Callback(f);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(U *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const U *obj, R (*func)(const T*, A0, A1, A2, A3, A4)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3, A4)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     *  @deprecated
+     *      Arguments to callback have been reordered to attach(func, arg)
+     */
+    template <typename T, typename U>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Arguments to callback have been reordered to attach(func, arg)")
+    void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3, A4)) {
+        this->~Callback();
+        new (this) Callback(func, obj);
+    }
+
+    /** Assign a callback
+     */
+    Callback &operator=(const Callback &that) {
+        if (this != &that) {
+            this->~Callback();
+            new (this) Callback(that);
+        }
+
+        return *this;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+        MBED_ASSERT(_ops);
+        return _ops->call(this, a0, a1, a2, a3, a4);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+        return call(a0, a1, a2, a3, a4);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _ops;
+    }
+
+    /** Test for equality
+     */
+    friend bool operator==(const Callback &l, const Callback &r) {
+        return memcmp(&l, &r, sizeof(Callback)) == 0;
+    }
+
+    /** Test for inequality
+     */
+    friend bool operator!=(const Callback &l, const Callback &r) {
+        return !(l == r);
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     *  @param a0 An argument to be called with function func
+     *  @param a1 An argument to be called with function func
+     *  @param a2 An argument to be called with function func
+     *  @param a3 An argument to be called with function func
+     *  @param a4 An argument to be called with function func
+     *  @return the value as determined by func which is of 
+     *      type and determined by the signiture of func
+     */
+    static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return static_cast<Callback*>(func)->call(a0, a1, a2, a3, a4);
+    }
+
+private:
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)(A0, A1, A2, A3, A4);
+        void (*_boundfunc)(_class*, A0, A1, A2, A3, A4);
+        void (_class::*_methodfunc)(A0, A1, A2, A3, A4);
+    } _func;
+    void *_obj;
+
+    // Dynamically dispatched operations
+    const struct ops {
+        R (*call)(const void*, A0, A1, A2, A3, A4);
+        void (*move)(void*, const void*);
+        void (*dtor)(void*);
+    } *_ops;
+
+    // Generate operations for function object
+    template <typename F>
+    void generate(const F &f) {
+        static const ops ops = {
+            &Callback::function_call<F>,
+            &Callback::function_move<F>,
+            &Callback::function_dtor<F>,
+        };
+
+        MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+                "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
+        new (this) F(f);
+        _ops = &ops;
+    }
+
+    // Function attributes
+    template <typename F>
+    static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return (*(F*)p)(a0, a1, a2, a3, a4);
+    }
+
+    template <typename F>
+    static void function_move(void *d, const void *p) {
+        new (d) F(*(F*)p);
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Wrappers for functions with context
+    template <typename O, typename M>
+    struct method_context {
+        M method;
+        O *obj;
+
+        method_context(O *obj, M method)
+            : method(method), obj(obj) {}
+
+        R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+            return (obj->*method)(a0, a1, a2, a3, a4);
+        }
+    };
+
+    template <typename F, typename A>
+    struct function_context {
+        F func;
+        A *arg;
+
+        function_context(F func, A *arg)
+            : func(func), arg(arg) {}
+
+        R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+            return func(arg, a0, a1, a2, a3, a4);
+        }
+    };
+};
+
+// Internally used event type
+typedef Callback<void(int)> event_callback_t;
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R>
+Callback<R()> callback(R (*func)() = 0) {
+    return Callback<R()>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R>
+Callback<R()> callback(const Callback<R()> &func) {
+    return Callback<R()>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(U *obj, R (T::*method)()) {
+    return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(const U *obj, R (T::*method)() const) {
+    return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(volatile U *obj, R (T::*method)() volatile) {
+    return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(const volatile U *obj, R (T::*method)() const volatile) {
+    return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(T*), U *arg) {
+    return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(const T*), const U *arg) {
+    return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(volatile T*), volatile U *arg) {
+    return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(const volatile T*), const volatile U *arg) {
+    return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(U *obj, R (*func)(T*)) {
+    return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(const U *obj, R (*func)(const T*)) {
+    return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(volatile U *obj, R (*func)(volatile T*)) {
+    return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(const volatile U *obj, R (*func)(const volatile T*)) {
+    return Callback<R()>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(A0) = 0) {
+    return Callback<R(A0)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0>
+Callback<R(A0)> callback(const Callback<R(A0)> &func) {
+    return Callback<R(A0)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(U *obj, R (T::*method)(A0)) {
+    return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(const U *obj, R (T::*method)(A0) const) {
+    return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(volatile U *obj, R (T::*method)(A0) volatile) {
+    return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(const volatile U *obj, R (T::*method)(A0) const volatile) {
+    return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(T*, A0), U *arg) {
+    return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(const T*, A0), const U *arg) {
+    return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(volatile T*, A0), volatile U *arg) {
+    return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(const volatile T*, A0), const volatile U *arg) {
+    return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(U *obj, R (*func)(T*, A0)) {
+    return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(const U *obj, R (*func)(const T*, A0)) {
+    return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(volatile U *obj, R (*func)(volatile T*, A0)) {
+    return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(const volatile U *obj, R (*func)(const volatile T*, A0)) {
+    return Callback<R(A0)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(A0, A1) = 0) {
+    return Callback<R(A0, A1)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const Callback<R(A0, A1)> &func) {
+    return Callback<R(A0, A1)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(U *obj, R (T::*method)(A0, A1)) {
+    return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const U *obj, R (T::*method)(A0, A1) const) {
+    return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(volatile U *obj, R (T::*method)(A0, A1) volatile) {
+    return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const volatile U *obj, R (T::*method)(A0, A1) const volatile) {
+    return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(T*, A0, A1), U *arg) {
+    return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(const T*, A0, A1), const U *arg) {
+    return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(volatile T*, A0, A1), volatile U *arg) {
+    return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(const volatile T*, A0, A1), const volatile U *arg) {
+    return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(U *obj, R (*func)(T*, A0, A1)) {
+    return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(const U *obj, R (*func)(const T*, A0, A1)) {
+    return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1)) {
+    return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1)) {
+    return Callback<R(A0, A1)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(A0, A1, A2) = 0) {
+    return Callback<R(A0, A1, A2)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const Callback<R(A0, A1, A2)> &func) {
+    return Callback<R(A0, A1, A2)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(U *obj, R (T::*method)(A0, A1, A2)) {
+    return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const U *obj, R (T::*method)(A0, A1, A2) const) {
+    return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(volatile U *obj, R (T::*method)(A0, A1, A2) volatile) {
+    return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const volatile U *obj, R (T::*method)(A0, A1, A2) const volatile) {
+    return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(T*, A0, A1, A2), U *arg) {
+    return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(const T*, A0, A1, A2), const U *arg) {
+    return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(volatile T*, A0, A1, A2), volatile U *arg) {
+    return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(const volatile T*, A0, A1, A2), const volatile U *arg) {
+    return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(U *obj, R (*func)(T*, A0, A1, A2)) {
+    return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(const U *obj, R (*func)(const T*, A0, A1, A2)) {
+    return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2)) {
+    return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2)) {
+    return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(A0, A1, A2, A3) = 0) {
+    return Callback<R(A0, A1, A2, A3)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const Callback<R(A0, A1, A2, A3)> &func) {
+    return Callback<R(A0, A1, A2, A3)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(U *obj, R (T::*method)(A0, A1, A2, A3)) {
+    return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const U *obj, R (T::*method)(A0, A1, A2, A3) const) {
+    return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3) volatile) {
+    return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3) const volatile) {
+    return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(T*, A0, A1, A2, A3), U *arg) {
+    return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(const T*, A0, A1, A2, A3), const U *arg) {
+    return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(volatile T*, A0, A1, A2, A3), volatile U *arg) {
+    return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(const volatile T*, A0, A1, A2, A3), const volatile U *arg) {
+    return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(U *obj, R (*func)(T*, A0, A1, A2, A3)) {
+    return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3)) {
+    return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3)) {
+    return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3)) {
+    return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @return         Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R (T::*method)(A0, A1, A2, A3, A4)) {
+    return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R (T::*method)(A0, A1, A2, A3, A4) const) {
+    return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile) {
+    return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj      Optional pointer to object to bind to function
+ *  @param method   Member function to attach
+ *  @return         Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile) {
+    return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(T*, A0, A1, A2, A3, A4), U *arg) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(const T*, A0, A1, A2, A3, A4), const U *arg) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(volatile T*, A0, A1, A2, A3, A4), volatile U *arg) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param func     Static function to attach
+ *  @param arg      Pointer argument to function
+ *  @return         Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(const volatile T*, A0, A1, A2, A3, A4), const volatile U *arg) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3, A4)) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3, A4)) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ *  @param obj  Optional pointer to object to bind to function
+ *  @param func Static function to attach
+ *  @return     Callback with infered type
+ *  @deprecated
+ *      Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+    "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3, A4)) {
+    return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CircularBuffer.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CircularBuffer.h
new file mode 100755
index 0000000..bb7fd38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CircularBuffer.h
@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CIRCULARBUFFER_H
+#define MBED_CIRCULARBUFFER_H
+
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+/** Templated Circular buffer class
+ *
+ *  @note Synchronization level: Interrupt safe
+ *  @ingroup platform
+ */
+template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
+class CircularBuffer {
+public:
+    CircularBuffer() : _head(0), _tail(0), _full(false) {
+    }
+
+    ~CircularBuffer() {
+    }
+
+    /** Push the transaction to the buffer. This overwrites the buffer if it's
+     *  full
+     *
+     * @param data Data to be pushed to the buffer
+     */
+    void push(const T& data) {
+        core_util_critical_section_enter();
+        if (full()) {
+            _tail++;
+            _tail %= BufferSize;
+        }
+        _pool[_head++] = data;
+        _head %= BufferSize;
+        if (_head == _tail) {
+            _full = true;
+        }
+        core_util_critical_section_exit();
+    }
+
+    /** Pop the transaction from the buffer
+     *
+     * @param data Data to be pushed to the buffer
+     * @return True if the buffer is not empty and data contains a transaction, false otherwise
+     */
+    bool pop(T& data) {
+        bool data_popped = false;
+        core_util_critical_section_enter();
+        if (!empty()) {
+            data = _pool[_tail++];
+            _tail %= BufferSize;
+            _full = false;
+            data_popped = true;
+        }
+        core_util_critical_section_exit();
+        return data_popped;
+    }
+
+    /** Check if the buffer is empty
+     *
+     * @return True if the buffer is empty, false if not
+     */
+    bool empty() const {
+        core_util_critical_section_enter();
+        bool is_empty = (_head == _tail) && !_full;
+        core_util_critical_section_exit();
+        return is_empty;
+    }
+
+    /** Check if the buffer is full
+     *
+     * @return True if the buffer is full, false if not
+     */
+    bool full() const {
+        core_util_critical_section_enter();
+        bool full = _full;
+        core_util_critical_section_exit();
+        return full;
+    }
+
+    /** Reset the buffer
+     *
+     */
+    void reset() {
+        core_util_critical_section_enter();
+        _head = 0;
+        _tail = 0;
+        _full = false;
+        core_util_critical_section_exit();
+    }
+
+private:
+    T _pool[BufferSize];
+    volatile CounterType _head;
+    volatile CounterType _tail;
+    volatile bool _full;
+};
+
+}
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CriticalSectionLock.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CriticalSectionLock.h
new file mode 100755
index 0000000..5199fba
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/CriticalSectionLock.h
@@ -0,0 +1,71 @@
+/*
+ * PackageLicenseDeclared: Apache-2.0
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CRITICALSECTIONLOCK_H
+#define MBED_CRITICALSECTIONLOCK_H
+
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+/** RAII object for disabling, then restoring, interrupt state
+  * Usage:
+  * @code
+  *
+  * void f() {
+  *     // some code here
+  *     {
+  *         CriticalSectionLock lock;
+  *         // Code in this block will run with interrupts disabled
+  *     }
+  *     // interrupts will be restored to their previous state
+  * }
+  * @endcode
+  */
+class CriticalSectionLock {
+public:
+    CriticalSectionLock() 
+    {
+        core_util_critical_section_enter();
+    }
+
+    ~CriticalSectionLock() 
+    {
+        core_util_critical_section_exit();
+    }
+
+    /** Mark the start of a critical section
+     *     
+     */
+    void lock()
+    {
+        core_util_critical_section_enter();
+    }
+
+    /** Mark the end of a critical section
+     *     
+     */
+    void unlock()
+    {
+        core_util_critical_section_exit();
+    }
+};
+
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/DeepSleepLock.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/DeepSleepLock.h
new file mode 100755
index 0000000..17abe15
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/DeepSleepLock.h
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEEPSLEEPLOCK_H
+#define MBED_DEEPSLEEPLOCK_H
+
+#include <limits.h>
+#include "platform/mbed_sleep.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+
+/** RAII object for disabling, then restoring the deep sleep mode
+  * Usage:
+  * @code
+  *
+  * void f() {
+  *     // some code here
+  *     {
+  *         DeepSleepLock lock;
+  *         // Code in this block will run with the deep sleep mode locked
+  *     }
+  *     // deep sleep mode will be restored to their previous state
+  * }
+  * @endcode
+  */
+class DeepSleepLock {
+private:
+    uint16_t _lock_count;
+
+public:
+    DeepSleepLock(): _lock_count(1)
+    {
+        sleep_manager_lock_deep_sleep();
+    }
+
+    ~DeepSleepLock()
+    {
+        if (_lock_count) {
+            sleep_manager_unlock_deep_sleep();
+        }
+    }
+
+    /** Mark the start of a locked deep sleep section
+     */
+    void lock()
+    {
+        uint16_t count = core_util_atomic_incr_u16(&_lock_count, 1);
+        if (1 == count) {
+            sleep_manager_lock_deep_sleep();
+        }
+        if (0 == count) {
+            error("DeepSleepLock overflow (> USHRT_MAX)");
+        }
+    }
+
+    /** Mark the end of a locked deep sleep section
+     */
+    void unlock()
+    {
+        uint16_t count = core_util_atomic_decr_u16(&_lock_count, 1);
+        if (count == 0) {
+            sleep_manager_unlock_deep_sleep();
+        }
+        if (count == USHRT_MAX) {
+            core_util_critical_section_exit();
+            error("DeepSleepLock underflow (< 0)");
+        }
+    }
+};
+
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/DirHandle.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/DirHandle.h
new file mode 100755
index 0000000..b1dcfe2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/DirHandle.h
@@ -0,0 +1,148 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#include <stdint.h>
+#include "platform/platform.h"
+#include "platform/FileHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+/** Represents a directory stream. Objects of this type are returned
+ *  by an opendir function. The core functions are read and seek,
+ *  but only a subset needs to be provided.
+ *
+ *  If a FileSystemLike class defines the opendir method, then the
+ *  directories of an object of that type can be accessed by
+ *  DIR *d = opendir("/example/directory") (or opendir("/example")
+ *  to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ *  The root directory is considered to contain all FileHandle and
+ *  FileSystem objects, so the DIR* returned by opendir("/") will
+ *  reflect this.
+ *
+ *  @note to create a directory, @see Dir
+ *  @note Synchronization level: Set by subclass
+ *  @ingroup platform
+ */
+class DirHandle : private NonCopyable<DirHandle> {
+public:
+    virtual ~DirHandle() {}
+
+    /** Read the next directory entry
+     *
+     *  @param ent      The directory entry to fill out
+     *  @return         1 on reading a filename, 0 at end of directory, negative error on failure
+     */
+    virtual ssize_t read(struct dirent *ent) = 0;
+
+    /** Close a directory
+     *
+     *  @return          0 on success, negative error code on failure
+     */
+    virtual int close() = 0;
+
+    /** Set the current position of the directory
+     *
+     *  @param offset   Offset of the location to seek to,
+     *                  must be a value returned from tell
+     */
+    virtual void seek(off_t offset) = 0;
+
+    /** Get the current position of the directory
+     *
+     *  @return         Position of the directory that can be passed to rewind
+     */
+    virtual off_t tell() = 0;
+
+    /** Rewind the current position to the beginning of the directory
+     */
+    virtual void rewind() = 0;
+
+    /** Get the sizeof the directory 
+     *
+     *  @return         Number of files in the directory
+     */
+    virtual size_t size()
+    {
+        off_t off = tell();
+        size_t size = 0;
+        struct dirent *ent = new struct dirent;
+
+        rewind();
+        while (read(ent) > 0) {
+            size += 1;
+        }
+        seek(off);
+
+        delete ent;
+        return size;
+    }
+
+    /** Closes the directory.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on error.
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::close")
+    virtual int closedir() { return close(); };
+
+    /** Return the directory entry at the current position, and
+     *  advances the position to the next entry.
+     *
+     * @returns
+     *  A pointer to a dirent structure representing the
+     *  directory entry at the current position, or NULL on reaching
+     *  end of directory or error.
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::read")
+    virtual struct dirent *readdir()
+    {
+        static struct dirent ent;
+        return (read(&ent) > 0) ? &ent : NULL;
+    }
+
+    /** Resets the position to the beginning of the directory.
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::rewind")
+    virtual void rewinddir() { rewind(); }
+
+    /** Returns the current position of the DirHandle.
+     *
+     * @returns
+     *   the current position,
+     *  -1 on error.
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::tell")
+    virtual off_t telldir() { return tell(); }
+
+    /** Sets the position of the DirHandle.
+     *
+     *  @param location The location to seek to. Must be a value returned by telldir.
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::seek")
+    virtual void seekdir(off_t location) { seek(location); }
+};
+
+
+} // namespace mbed
+
+#endif /* MBED_DIRHANDLE_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileBase.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileBase.cpp
new file mode 100755
index 0000000..4458f58
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileBase.cpp
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/FileBase.h"
+#include "platform/FileLike.h"
+#include "platform/FileHandle.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+SingletonPtr<PlatformMutex> FileBase::_mutex;
+
+FileBase::FileBase(const char *name, PathType t) : _next(NULL),
+                                                   _name(name),
+                                                   _path_type(t) {
+    _mutex->lock();
+    if (name != NULL) {
+        // put this object at head of the list
+        _next = _head;
+        _head = this;
+    } else {
+        _next = NULL;
+    }
+    _mutex->unlock();
+}
+
+FileBase::~FileBase() {
+    _mutex->lock();
+    if (_name != NULL) {
+        // remove this object from the list
+        if (_head == this) { // first in the list, so just drop me
+            _head = _next;
+        } else {             // find the object before me, then drop me
+            FileBase *p = _head;
+            while (p->_next != this) {
+                p = p->_next;
+            }
+            p->_next = _next;
+        }
+    }
+    _mutex->unlock();
+
+    if (getPathType() == FilePathType) {
+        extern void remove_filehandle(FileHandle *file);
+        remove_filehandle(static_cast<FileHandle*>(static_cast<FileLike*>(this)));
+    }
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len) {
+    _mutex->lock();
+    FileBase *p = _head;
+    while (p != NULL) {
+        /* Check that p->_name matches name and is the correct length */
+        if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+            _mutex->unlock();
+            return p;
+        }
+        p = p->_next;
+    }
+    _mutex->unlock();
+    return NULL;
+}
+
+FileBase *FileBase::get(int n) {
+    _mutex->lock();
+    FileBase *p = _head;
+    int m = 0;
+    while (p != NULL) {
+        if (m == n) {
+            _mutex->unlock();
+            return p;
+        }
+
+        m++;
+        p = p->_next;
+    }
+    _mutex->unlock();
+    return NULL;
+}
+
+const char* FileBase::getName(void) {
+    // Constant read so no lock needed
+    return _name;
+}
+
+PathType FileBase::getPathType(void) {
+    // Constant read so no lock needed
+    return _path_type;
+}
+
+} // namespace mbed
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileBase.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileBase.h
new file mode 100755
index 0000000..5df9ef8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileBase.h
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <cstdio>
+#include <cstring>
+
+#include "platform/platform.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+
+typedef enum {
+    FilePathType,
+    FileSystemPathType
+} PathType;
+/** @}*/
+
+/**
+ * @class FileBase
+ * @ingroup platform
+ */
+class FileBase : private NonCopyable<FileBase> {
+public:
+    FileBase(const char *name, PathType t);
+    virtual ~FileBase();
+
+    const char* getName(void);
+    PathType    getPathType(void);
+
+    static FileBase *lookup(const char *name, unsigned int len);
+
+    static FileBase *get(int n);
+
+    /* disallow copy constructor and assignment operators */
+private:
+    static FileBase *_head;
+    static SingletonPtr<PlatformMutex> _mutex;
+
+    FileBase   *_next;
+    const char * const _name;
+    const PathType _path_type;
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileHandle.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileHandle.cpp
new file mode 100755
index 0000000..026b11d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileHandle.cpp
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileHandle.h"
+#include "platform/mbed_retarget.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+off_t FileHandle::size()
+{
+    /* remember our current position */
+    off_t off = seek(0, SEEK_CUR);
+    if (off < 0) {
+        return off;
+    }
+    /* seek to the end to get the file length */
+    off_t size = seek(0, SEEK_END);
+    /* return to our old position */
+    seek(off, SEEK_SET);
+    return size;
+}
+
+std::FILE *fdopen(FileHandle *fh, const char *mode)
+{
+    return mbed_fdopen(fh, mode);
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileHandle.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileHandle.h
new file mode 100755
index 0000000..a6b306b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileHandle.h
@@ -0,0 +1,259 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <cstdio>
+#include "Callback.h"
+#include "platform/mbed_poll.h"
+#include "platform/platform.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+/** Class FileHandle
+ *
+ *  An abstract interface that represents operations on a file-like
+ *  object. The core functions are read, write, and seek, but only
+ *  a subset of these operations can be provided.
+ *
+ *  @note to create a file, @see File
+ *  @note Synchronization level: Set by subclass
+ *  @ingroup platform
+ */
+class FileHandle : private NonCopyable<FileHandle> {
+public:
+    virtual ~FileHandle() {}
+
+    /** Read the contents of a file into a buffer
+     *
+     *  Devices acting as FileHandles should follow POSIX semantics:
+     *
+     *  * if no data is available, and non-blocking set return -EAGAIN
+     *  * if no data is available, and blocking set, wait until data is available
+     *  * If any data is available, call returns immediately
+     *
+     *  @param buffer   The buffer to read in to
+     *  @param size     The number of bytes to read
+     *  @return         The number of bytes read, 0 at end of file, negative error on failure
+     */
+    virtual ssize_t read(void *buffer, size_t size) = 0;
+
+    /** Write the contents of a buffer to a file
+     *
+     *  @param buffer   The buffer to write from
+     *  @param size     The number of bytes to write 
+     *  @return         The number of bytes written, negative error on failure
+     */
+    virtual ssize_t write(const void *buffer, size_t size) = 0;
+
+    /** Move the file position to a given offset from from a given location
+     *
+     *  @param offset   The offset from whence to move to
+     *  @param whence   The start of where to seek
+     *      SEEK_SET to start from beginning of file,
+     *      SEEK_CUR to start from current position in file,
+     *      SEEK_END to start from end of file
+     *  @return         The new offset of the file, negative error code on failure
+     */
+    virtual off_t seek(off_t offset, int whence = SEEK_SET) = 0;
+
+    /** Close a file
+     *
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int close() = 0;
+
+    /** Flush any buffers associated with the file
+     *
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int sync()
+    {
+        return 0;
+    }
+
+    /** Check if the file in an interactive terminal device
+     *
+     *  @return         True if the file is a terminal
+     *  @return         False if the file is not a terminal
+     *  @return         Negative error code on failure
+     */
+    virtual int isatty()
+    {
+        return false;
+    }
+
+    /** Get the file position of the file
+     *
+     *  @note This is equivalent to seek(0, SEEK_CUR)
+     *
+     *  @return         The current offset in the file, negative error code on failure
+     */
+    virtual off_t tell()
+    {
+        return seek(0, SEEK_CUR);
+    }
+
+    /** Rewind the file position to the beginning of the file
+     *
+     *  @note This is equivalent to seek(0, SEEK_SET)
+     */
+    virtual void rewind()
+    {
+        seek(0, SEEK_SET);
+    }
+
+    /** Get the size of the file
+     *
+     *  @return         Size of the file in bytes
+     */
+    virtual off_t size();
+
+    /** Move the file position to a given offset from a given location.
+     *
+     *  @param offset The offset from whence to move to
+     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+     *   current file position, or SEEK_END for the end of the file.
+     *
+     *  @returns
+     *    new file position on success,
+     *    -1 on failure or unsupported
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::seek")
+    virtual off_t lseek(off_t offset, int whence)
+    {
+        return seek(offset, whence);
+    }
+
+    /** Flush any buffers associated with the FileHandle, ensuring it
+     *  is up to date on disk
+     *
+     *  @returns
+     *    0 on success or un-needed,
+     *   -1 on error
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::sync")
+    virtual int fsync()
+    {
+        return sync();
+    }
+
+    /** Find the length of the file
+     *
+     *  @returns
+     *   Length of the file
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::size")
+    virtual off_t flen()
+    {
+        return size();
+    }
+
+    /** Set blocking or non-blocking mode of the file operation like read/write.
+     *  Definition depends upon the subclass implementing FileHandle.
+     *  The default is blocking.
+     *
+     *  @param blocking     true for blocking mode, false for non-blocking mode.
+     *
+     *  @return             0 on success
+     *  @return             Negative error code on failure
+     */
+    virtual int set_blocking(bool blocking)
+    {
+        return -1;
+    }
+
+    /** Check for poll event flags
+     * The input parameter can be used or ignored - the could always return all events,
+     * or could check just the events listed in events.
+     * Call is non-blocking - returns instantaneous state of events.
+     * Whenever an event occurs, the derived class should call the sigio() callback).
+     *
+     * @param events        bitmask of poll events we're interested in - POLLIN/POLLOUT etc.
+     *
+     * @returns             bitmask of poll events that have occurred.
+     */
+    virtual short poll(short events) const
+    {
+        // Possible default for real files
+        return POLLIN | POLLOUT;
+    }
+
+    /** Definition depends upon the subclass implementing FileHandle.
+     *  For example, if the FileHandle is of type Stream, writable() could return
+     *  true when there is ample buffer space available for write() calls.
+     *
+     * @returns             true if the FileHandle is writable.
+     */
+    bool writable() const
+    {
+        return poll(POLLOUT) & POLLOUT;
+    }
+
+    /** Definition depends upon the subclass implementing FileHandle.
+     *  For example, if the FileHandle is of type Stream, readable() could return
+     *  true when there is something available to read.
+     *
+     *  @returns            true when there is something available to read.
+     */
+    bool readable() const
+    {
+        return poll(POLLIN) & POLLIN;
+    }
+
+    /** Register a callback on state change of the file.
+     *
+     *  The specified callback will be called on state changes such as when
+     *  the file can be written to or read from.
+     *
+     *  The callback may be called in an interrupt context and should not
+     *  perform expensive operations.
+     *
+     *  Note! This is not intended as an attach-like asynchronous api, but rather
+     *  as a building block for constructing  such functionality.
+     *
+     *  The exact timing of when the registered function
+     *  is called is not guaranteed and susceptible to change. It should be used
+     *  as a cue to make read/write/poll calls to find the current state.
+     *
+     *  @param func     Function to call on state change
+     */
+    virtual void sigio(Callback<void()> func)
+    {
+        //Default for real files. Do nothing for real files.
+    }
+};
+
+/** Not a member function
+ *  This call is equivalent to posix fdopen().
+ *  It associates a Stream to an already opened file descriptor (FileHandle)
+ *
+ *  @param fh       a pointer to an opened file descriptor
+ *  @param mode     operation upon the file descriptor, e.g., 'wb+'
+ *
+ *  @returns        a pointer to std::FILE
+*/
+
+std::FILE *fdopen(FileHandle *fh, const char *mode);
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileLike.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileLike.h
new file mode 100755
index 0000000..91a3f30
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileLike.h
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "platform/mbed_toolchain.h"
+#include "platform/FileBase.h"
+#include "platform/FileHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+/* Class FileLike
+ *  A file-like object is one that can be opened with fopen by
+ *  fopen("/name", mode).
+ *
+ *  @note Synchronization level: Set by subclass
+ *  @ingroup platform
+ */
+class FileLike : public FileHandle, public FileBase, private NonCopyable<FileLike> {
+public:
+    /** Constructor FileLike
+     *
+     *  @param name     The name to use to open the file.
+     */
+    FileLike(const char *name = NULL) : FileBase(name, FilePathType) {}
+    virtual ~FileLike() {}
+};
+
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FilePath.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FilePath.cpp
new file mode 100755
index 0000000..0260986
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FilePath.cpp
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
+    if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+
+    const char* file_system = &file_path[1];
+    file_name = file_system;
+    int len = 0;
+    while (true) {
+        char c = *file_name;
+        if (c == '/') { // end of object name
+            file_name++; // point to one char after the '/'
+            break;
+        }
+        if (c == 0) { // end of object name, with no filename
+            break;
+        }
+        len++;
+        file_name++;
+    }
+
+    fb = FileBase::lookup(file_system, len);
+}
+
+const char* FilePath::fileName(void) {
+    return file_name;
+}
+
+bool FilePath::isFileSystem(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike* FilePath::fileSystem(void) {
+    if (isFileSystem()) {
+        return static_cast<FileSystemLike*>(fb);
+    }
+    return NULL;
+}
+
+bool FilePath::isFile(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FilePathType);
+}
+
+FileLike* FilePath::file(void) {
+    if (isFile()) {
+        return (FileLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::exists(void) {
+    return fb != NULL;
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FilePath.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FilePath.h
new file mode 100755
index 0000000..4c4dc65
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FilePath.h
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform/platform.h"
+
+#include "platform/FileSystemLike.h"
+#include "platform/FileLike.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+/**
+ * @class FileSystem
+ * @ingroup platform
+ */
+class FileSystem;
+
+class FilePath {
+public:
+    FilePath(const char* file_path);
+
+    const char* fileName(void);
+
+    bool          isFileSystem(void);
+    FileSystemLike* fileSystem(void);
+
+    bool    isFile(void);
+    FileLike* file(void);
+    bool    exists(void);
+
+private:
+    const char* file_name;
+    FileBase* fb;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemHandle.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemHandle.cpp
new file mode 100755
index 0000000..3028d40
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemHandle.cpp
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "FileSystemHandle.h"
+#include <errno.h>
+
+int FileSystemHandle::open(DirHandle **dir, const char *path)
+{
+    return -ENOSYS;
+}
+
+int FileSystemHandle::remove(const char *path)
+{
+    return -ENOSYS;
+}
+
+int FileSystemHandle::rename(const char *path, const char *newpath)
+{
+    return -ENOSYS;
+}
+
+int FileSystemHandle::stat(const char *path, struct stat *st)
+{
+    return -ENOSYS;
+}
+
+int FileSystemHandle::mkdir(const char *path, mode_t mode)
+{
+    return -ENOSYS;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemHandle.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemHandle.h
new file mode 100755
index 0000000..bf2c335
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemHandle.h
@@ -0,0 +1,100 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMHANDLE_H
+#define MBED_FILESYSTEMHANDLE_H
+
+#include "platform/platform.h"
+
+#include "platform/FileBase.h"
+#include "platform/FileHandle.h"
+#include "platform/DirHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+
+
+/** A filesystem-like object is one that can be used to open file-like
+ *  objects though it by fopen("/name/filename", mode)
+ *
+ *  Implementations must define at least open (the default definitions
+ *  of the rest of the functions just return error values).
+ *
+ * @note Synchronization level: Set by subclass
+ */
+class FileSystemHandle : private NonCopyable<FileSystemHandle> {
+public:
+    /** FileSystemHandle lifetime
+     */
+    virtual ~FileSystemHandle() {}
+
+    /** Open a file on the filesystem
+     *
+     *  @param file     Destination for the handle to a newly created file
+     *  @param filename The name of the file to open
+     *  @param flags    The flags to open the file in, one of O_RDONLY, O_WRONLY, O_RDWR,
+     *                  bitwise or'd with one of O_CREAT, O_TRUNC, O_APPEND
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int open(FileHandle **file, const char *filename, int flags) = 0;
+
+    /** Open a directory on the filesystem
+     *
+     *  @param dir      Destination for the handle to the directory
+     *  @param path     Name of the directory to open
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int open(DirHandle **dir, const char *path);
+
+    /** Remove a file from the filesystem.
+     *
+     *  @param path     The name of the file to remove.
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int remove(const char *path);
+
+    /** Rename a file in the filesystem.
+     *
+     *  @param path     The name of the file to rename.
+     *  @param newpath  The name to rename it to
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int rename(const char *path, const char *newpath);
+
+    /** Store information about the file in a stat structure
+     *
+     *  @param path     The name of the file to find information about
+     *  @param st       The stat buffer to write to
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int stat(const char *path, struct stat *st);
+
+    /** Create a directory in the filesystem.
+     *
+     *  @param path     The name of the directory to create.
+     *  @param mode     The permissions with which to create the directory
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int mkdir(const char *path, mode_t mode);
+};
+
+
+} // namespace mbed
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemLike.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemLike.h
new file mode 100755
index 0000000..d892339
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FileSystemLike.h
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform/platform.h"
+
+#include "platform/FileSystemHandle.h"
+#include "platform/FileHandle.h"
+#include "platform/DirHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+/** A filesystem-like object is one that can be used to open file-like
+ *  objects though it by fopen("/name/filename", mode)
+ *
+ *  Implementations must define at least open (the default definitions
+ *  of the rest of the functions just return error values).
+ *
+ * @note Synchronization level: Set by subclass
+ * @ingroup platform
+ */
+class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopyable<FileSystemLike> {
+public:
+    /** FileSystemLike lifetime
+     */
+    FileSystemLike(const char *name = NULL) : FileBase(name, FileSystemPathType) {}
+    virtual ~FileSystemLike() {}
+
+    // Inherited functions with name conflicts
+    using FileSystemHandle::open;
+
+    /** Open a file on the filesystem
+     *
+     *  @param path     The name of the file to open
+     *  @param flags    The flags to open the file in, one of O_RDONLY, O_WRONLY, O_RDWR,
+     *                  bitwise or'd with one of O_CREAT, O_TRUNC, O_APPEND
+     *  @return         A file handle on success, NULL on failure
+     *  @deprecated Replaced by `int open(FileHandle **, ...)` for propagating error codes
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.5",
+        "Replaced by `int open(FileHandle **, ...)` for propagating error codes")
+    FileHandle *open(const char *path, int flags)
+    {
+        FileHandle *file;
+        int err = open(&file, path, flags);
+        return err ? NULL : file;
+    }
+
+    /** Open a directory on the filesystem
+     *
+     *  @param path     Name of the directory to open
+     *  @return         A directory handle on success, NULL on failure
+     *  @deprecated Replaced by `int open(DirHandle **, ...)` for propagating error codes
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.5",
+        "Replaced by `int open(DirHandle **, ...)` for propagating error codes")
+    DirHandle *opendir(const char *path)
+    {
+        DirHandle *dir;
+        int err = open(&dir, path);
+        return err ? NULL : dir;
+    }
+};
+
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FunctionPointer.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FunctionPointer.h
new file mode 100755
index 0000000..a57195f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/FunctionPointer.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include <string.h>
+#include <stdint.h>
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+// Declarations for backwards compatibility
+// To be foward compatible, code should adopt the Callback class
+/**
+ * @ingroup platform
+ */
+template <typename R, typename A1>
+class FunctionPointerArg1 : public Callback<R(A1)> {
+public:
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+    FunctionPointerArg1(R (*function)(A1) = 0)
+        : Callback<R(A1)>(function) {}
+
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+    FunctionPointerArg1(T *object, R (T::*member)(A1))
+        : Callback<R(A1)>(object, member) {}
+
+    R (*get_function())(A1) {
+        return *reinterpret_cast<R (**)(A1)>(this);
+    }
+
+    R call(A1 a1) const {
+        if (!Callback<R(A1)>::operator bool()) {
+            return (R)0;
+        }
+
+        return Callback<R(A1)>::call(a1);
+    }
+
+    R operator()(A1 a1) const {
+        return Callback<R(A1)>::call(a1);
+    }
+};
+
+/**
+ * @ingroup platform
+ */
+template <typename R>
+class FunctionPointerArg1<R, void> : public Callback<R()> {
+public:
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointer has been replaced by Callback<void()>")
+    FunctionPointerArg1(R (*function)() = 0)
+        : Callback<R()>(function) {}
+
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointer has been replaced by Callback<void()>")
+    FunctionPointerArg1(T *object, R (T::*member)())
+        : Callback<R()>(object, member) {}
+
+    R (*get_function())() {
+        return *reinterpret_cast<R (**)()>(this);
+    }
+
+    R call() const {
+        if (!Callback<R()>::operator bool()) {
+            return (R)0;
+        }
+
+        return Callback<R()>::call();
+    }
+
+    R operator()() const {
+        return Callback<R()>::call();
+    }
+};
+
+typedef FunctionPointerArg1<void, void> FunctionPointer;
+
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/LocalFileSystem.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/LocalFileSystem.cpp
new file mode 100755
index 0000000..13daee3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/LocalFileSystem.cpp
@@ -0,0 +1,278 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "platform/mbed_semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+#include <errno.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+    unsigned char  hr;   /* Hours    [0..23]                  */
+    unsigned char  min;  /* Minutes  [0..59]                  */
+    unsigned char  sec;  /* Seconds  [0..59]                  */
+    unsigned char  day;  /* Day      [1..31]                  */
+    unsigned char  mon;  /* Month    [1..12]                  */
+    unsigned short year; /* Year     [1980..2107]             */
+} FTIME;
+
+typedef struct {         /* File Search info record           */
+    char  name[32];      /* File name                         */
+    long  size;          /* File size in bytes                */
+    int   fileID;        /* System File Identification        */
+    FTIME create_time;   /* Date & time file was created      */
+    FTIME write_time;    /* Date & time of last write         */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind (const char *pattern, XFINFO *info) {
+    unsigned param[4];
+
+    param[0] = (unsigned long)pattern;
+    param[1] = (unsigned long)strlen(pattern);
+    param[2] = (unsigned long)info;
+    param[3] = (unsigned long)sizeof(XFINFO);
+
+    return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R          0
+#define OPEN_B          1
+#define OPEN_PLUS       2
+#define OPEN_W          4
+#define OPEN_A          8
+#define OPEN_INVALID   -1
+
+int posix_to_semihost_open_flags(int flags) {
+    /* POSIX flags -> semihosting open mode */
+    int openmode;
+    if (flags & O_RDWR) {
+        /* a plus mode */
+        openmode = OPEN_PLUS;
+        if (flags & O_APPEND) {
+            openmode |= OPEN_A;
+        } else if (flags & O_TRUNC) {
+            openmode |= OPEN_W;
+        } else {
+            openmode |= OPEN_R;
+        }
+    } else if (flags & O_WRONLY) {
+        /* write or append */
+        if (flags & O_APPEND) {
+            openmode = OPEN_A;
+        } else {
+            openmode = OPEN_W;
+        }
+    } else if (flags == O_RDONLY) {
+        /* read mode */
+        openmode = OPEN_R;
+    } else {
+        /* invalid flags */
+        openmode = OPEN_INVALID;
+    }
+
+    return openmode;
+}
+
+FILEHANDLE local_file_open(const char* name, int flags) {
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return (FILEHANDLE)NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return (FILEHANDLE)NULL;
+    }
+
+    return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
+    // No lock needed in constructor
+}
+
+int LocalFileHandle::close() {
+    int retval = semihost_close(_fh);
+    delete this;
+    return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
+    lock();
+    ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
+    n = length - n; // number of characters written
+    pos += n;
+    unlock();
+    return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length) {
+    lock();
+    ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
+    n = length - n; // number of characters read
+    pos += n;
+    unlock();
+    return n;
+}
+
+int LocalFileHandle::isatty() {
+    lock();
+    int ret = semihost_istty(_fh);
+    unlock();
+    return ret;
+}
+
+off_t LocalFileHandle::seek(off_t position, int whence) {
+    lock();
+    if (whence == SEEK_CUR) {
+        position += pos;
+    } else if (whence == SEEK_END) {
+        position += semihost_flen(_fh);
+    } /* otherwise SEEK_SET, so position is fine */
+
+    /* Always seems to return -1, so just ignore for now. */
+    semihost_seek(_fh, position);
+    pos = position;
+    unlock();
+    return position;
+}
+
+int LocalFileHandle::sync() {
+    lock();
+    int ret = semihost_ensure(_fh);
+    unlock();
+    return ret;
+}
+
+off_t LocalFileHandle::size() {
+    lock();
+    off_t off = semihost_flen(_fh);
+    unlock();
+    return off;
+}
+
+void LocalFileHandle::lock() {
+    _mutex.lock();
+}
+
+void LocalFileHandle::unlock() {
+    _mutex.unlock();
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+    XFINFO info;
+
+    LocalDirHandle() : info() {
+    }
+
+    virtual int close() {
+        // No lock can be used in destructor
+        delete this;
+        return 0;
+    }
+
+    virtual int read(struct dirent *ent) {
+        lock();
+        if (xffind("*", &info)!=0) {
+            unlock();
+            return 0;
+        }
+        memcpy(ent->d_name, info.name, sizeof(info.name));
+        unlock();
+        return 1;
+    }
+
+    virtual void rewind() {
+        lock();
+        info.fileID = 0;
+        unlock();
+    }
+
+    virtual off_t tell() {
+        lock();
+        int fileId = info.fileID;
+        unlock();
+        return fileId;
+    }
+
+    virtual void seek(off_t offset) {
+        lock();
+        info.fileID = offset;
+        unlock();
+    }
+
+protected:
+    PlatformMutex _mutex;
+
+    virtual void lock() {
+        _mutex.lock();
+    }
+
+    virtual void unlock() {
+        _mutex.unlock();
+    }
+};
+
+int LocalFileSystem::open(FileHandle **file, const char* name, int flags) {
+    // No global state modified so function is thread safe
+
+    /* reject filenames with / in them */
+    for (const char *tmp = name; *tmp; tmp++) {
+        if (*tmp == '/') {
+            return -EINVAL;
+        }
+    }
+
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return -EINVAL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return -EIO;
+    }
+
+    *file = new LocalFileHandle(fh);
+    return 0;
+}
+
+int LocalFileSystem::remove(const char *filename) {
+    // No global state modified so function is thread safe
+
+    return semihost_remove(filename);
+}
+
+int LocalFileSystem::open(DirHandle **dir, const char *name) {
+    // No global state modified so function is thread safe
+
+    *dir = new LocalDirHandle();
+    return 0;
+}
+
+} // namespace mbed
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/LocalFileSystem.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/LocalFileSystem.h
new file mode 100755
index 0000000..3bd64d8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/LocalFileSystem.h
@@ -0,0 +1,120 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform/platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "platform/FileSystemLike.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+
+FILEHANDLE local_file_open(const char* name, int flags);
+/** @}*/
+
+/**
+ * @class LocalFileHandle
+ * @ingroup platform
+ */
+class LocalFileHandle : public FileHandle, private NonCopyable<LocalFileHandle> {
+
+public:
+    LocalFileHandle(FILEHANDLE fh);
+
+    virtual int close();
+
+    virtual ssize_t write(const void *buffer, size_t length);
+
+    virtual ssize_t read(void *buffer, size_t length);
+
+    virtual int isatty();
+
+    virtual off_t seek(off_t position, int whence);
+
+    virtual int sync();
+
+    virtual off_t size();
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    FILEHANDLE _fh;
+    int pos;
+    PlatformMutex _mutex;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ *  This allows programs to read and write files on the same disk drive that is used to program the
+ *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ *  read and write files.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
+ *     fprintf(fp, "Hello World!");
+ *     fclose(fp);
+ *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
+ *
+ *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
+ *     struct dirent *p;
+ *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
+ *       printf("%s\n", p->d_name);              // to stdout.
+ *     }
+ *     closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ *  on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ * @ingroup platform
+ */
+class LocalFileSystem : public FileSystemLike, private NonCopyable<LocalFileSystem> {
+    // No modifiable state
+
+public:
+    LocalFileSystem(const char* n) : FileSystemLike(n) {
+
+    }
+
+    virtual int open(FileHandle **file, const char *path, int flags);
+    virtual int open(DirHandle **dir, const char *name);
+    virtual int remove(const char *filename);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/NonCopyable.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/NonCopyable.h
new file mode 100755
index 0000000..c8cc092
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/NonCopyable.h
@@ -0,0 +1,168 @@
+/* Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_NONCOPYABLE_H_
+#define MBED_NONCOPYABLE_H_
+
+namespace mbed { 
+
+/**
+ * Inheriting from this class autogeneration of copy construction and copy 
+ * assignement operations. 
+ * 
+ * Classes which are not value type should inherit privately from this class 
+ * to avoid generation of invalid copy constructor or copy assignement operator
+ * which can lead to unoticeable programming errors. 
+ * 
+ * As an example consider the following signature: 
+ * 
+ * @code
+ * class Resource; 
+ *
+ * class Foo { 
+ * public:     
+ *   Foo() : _resource(new Resource()) { }
+ *   ~Foo() { delete _resource; } 
+ * private:
+ *   Resource* _resource;
+ * }
+ * 
+ * Foo get_foo();
+ * 
+ * Foo foo = get_foo();
+ * @endcode 
+ * 
+ * There is a bug in this function, it returns a temporary value which will be 
+ * byte copied into foo then destroyed. Unfortunately, internaly the Foo class 
+ * manage a pointer to a Resource object. This pointer will be released when the 
+ * temporary is destroyed and foo will manage a pointer to an already released 
+ * Resource.
+ * 
+ * Two issues has to be fixed in the example above: 
+ *   - Function signature has to be changed to reflect the fact that Foo 
+ *     instances cannot be copied. In that case accessor should return a 
+ *     reference to give access to objects already existing and managed. 
+ *     Generator on the other hand should return a pointer to the created object.
+ * 
+ * @code 
+ * // return a reference to an already managed Foo instance
+ * Foo& get_foo(); 
+ * Foo& foo = get_foo();
+ * 
+ * // create a new Foo instance
+ * Foo* make_foo();
+ * Foo* m = make_foo();
+ * @endcode
+ * 
+ *   - Copy constructor and copy assignement operator has to be made private 
+ *     in the Foo class. It prevents unwanted copy of Foo objects. This can be 
+ *     done by declaring copy constructor and copy assignement in the private 
+ *     section of the Foo class.
+ *     
+ * @code 
+ * class Foo { 
+ * public:     
+ *   Foo() : _resource(new Resource()) { }
+ *   ~Foo() { delete _resource; } 
+ * private:
+ *   // disallow copy operations 
+ *   Foo(const Foo&);
+ *   Foo& operator=(const Foo&);
+ *   // data members 
+ *   Resource* _resource;
+ * }
+ * @endcode
+ * 
+ * Another solution is to inherit privately from the NonCopyable class. 
+ * It reduces the boiler plate needed to avoid copy operations but more 
+ * importantly it clarifies the programer intent and the object semantic.
+ *
+ * class Foo : private NonCopyable<Foo> { 
+ * public:     
+ *   Foo() : _resource(new Resource()) { }
+ *   ~Foo() { delete _resource; } 
+ * private:
+ *   Resource* _resource;
+ * }
+ * 
+ * @tparam T The type that should be made non copyable. It prevent cases where 
+ * the empty base optimization cannot be applied and therefore ensure that the 
+ * cost of this semantic sugar is null. 
+ * 
+ * As an example, the empty base optimization is prohibited if one of the empty 
+ * base class is also a base type of the first non static data member: 
+ * 
+ * @code 
+ * struct A { };
+ * struct B : A { 
+ *    int foo;
+ * };
+ * // thanks to empty base optimization, sizeof(B) == sizeof(int)
+ * 
+ * struct C : A { 
+ *   B b;
+ * };
+ * 
+ * // empty base optimization cannot be applied here because A from C and A from
+ * // B shall have a different address. In that case, with the alignement 
+ * // sizeof(C) == 2* sizeof(int)
+ * @endcode
+ * 
+ * The solution to that problem is to templatize the empty class to makes it 
+ * unique to the type it is applied to: 
+ * 
+ * @code 
+ * template<typename T>
+ * struct A<T> { };
+ * struct B : A<B> { 
+ *    int foo;
+ * };
+ * struct C : A<C> { 
+ *   B b;
+ * };
+ * 
+ * // empty base optimization can be applied B and C does not refer to the same 
+ * // kind of A. sizeof(C) == sizeof(B) == sizeof(int).
+ * @endcode
+ */
+template<typename T>
+class NonCopyable { 
+protected:
+    /** 
+     * Disalow construction of NonCopyable objects from outside of its hierarchy.
+     */
+    NonCopyable() { }
+    /** 
+     * Disalow destruction of NonCopyable objects from outside of its hierarchy.
+     */
+    ~NonCopyable() { }
+
+private: 
+    /**
+     * Declare copy constructor as private, any attempt to copy construct 
+     * a NonCopyable will fail at compile time.
+     */
+    NonCopyable(const NonCopyable&);
+
+    /**
+     * Declare copy assignement operator as private, any attempt to copy assign 
+     * a NonCopyable will fail at compile time.
+     */
+    NonCopyable& operator=(const NonCopyable&);
+};
+
+} // namespace mbed 
+
+#endif /* MBED_NONCOPYABLE_H_ */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/PlatformMutex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/PlatformMutex.h
new file mode 100755
index 0000000..517fd3a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/PlatformMutex.h
@@ -0,0 +1,52 @@
+
+/** \addtogroup platform */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef PLATFORM_MUTEX_H
+#define PLATFORM_MUTEX_H
+
+#include "platform/NonCopyable.h"
+
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "rtos/Mutex.h"
+typedef rtos::Mutex PlatformMutex;
+#else
+/** A stub mutex for when an RTOS is not present
+ * @ingroup platform
+*/
+class PlatformMutex : private mbed::NonCopyable<PlatformMutex> {
+public:
+    PlatformMutex() {
+        // Stub
+
+    }
+    ~PlatformMutex() {
+        // Stub
+    }
+
+    void lock() {
+        // Do nothing
+    }
+
+    void unlock() {
+        // Do nothing
+    }
+};
+
+#endif
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/SingletonPtr.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/SingletonPtr.h
new file mode 100755
index 0000000..369d6db
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/SingletonPtr.h
@@ -0,0 +1,111 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef SINGLETONPTR_H
+#define SINGLETONPTR_H
+
+#include <stdint.h>
+#include <new>
+#include "platform/mbed_assert.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "cmsis_os2.h"
+#endif
+
+#ifdef MBED_CONF_RTOS_PRESENT
+extern osMutexId_t singleton_mutex_id;
+#endif
+
+/** Lock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_lock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+    osMutexAcquire(singleton_mutex_id, osWaitForever);
+#endif
+}
+
+/** Unlock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_unlock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+    osMutexRelease (singleton_mutex_id);
+#endif
+}
+/** @}*/
+
+/** Utility class for creating an using a singleton
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @note: This class must only be used in a static context -
+ * this class must never be allocated or created on the
+ * stack.
+ *
+ * @note: This class is lazily initialized on first use.
+ * This class is a POD type so if it is not used it will
+ * be garbage collected.
+ * @ingroup platform
+ */
+template <class T>
+struct SingletonPtr {
+
+    /** Get a pointer to the underlying singleton
+     *
+     * @returns
+     *   A pointer to the singleton
+     */
+    T* get() {
+        if (NULL == _ptr) {
+            singleton_lock();
+            if (NULL == _ptr) {
+                _ptr = new (_data) T();
+            }
+            singleton_unlock();
+        }
+        // _ptr was not zero initialized or was
+        // corrupted if this assert is hit
+        MBED_ASSERT(_ptr == (T *)&_data);
+        return _ptr;
+    }
+
+    /** Get a pointer to the underlying singleton
+     *
+     * @returns
+     *   A pointer to the singleton
+     */
+    T* operator->() {
+        return get();
+    }
+
+    // This is zero initialized when in global scope
+    T *_ptr;
+    // Force data to be 4 byte aligned
+    uint32_t _data[(sizeof(T) + sizeof(uint32_t) - 1) / sizeof(uint32_t)];
+};
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Stream.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Stream.cpp
new file mode 100755
index 0000000..61054d6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Stream.cpp
@@ -0,0 +1,165 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/Stream.h"
+#include "platform/mbed_error.h"
+#include <errno.h>
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
+    // No lock needed in constructor
+    /* open ourselves */
+    _file = fdopen(this, "w+");
+    // fdopen() will make us buffered because Stream::isatty()
+    // wrongly returns zero which is not being changed for
+    // backward compatibility 
+    if (_file) {
+        mbed_set_unbuffered_stream(_file);
+    } else {
+        error("Stream obj failure, errno=%d\r\n", errno);
+    }
+}
+
+Stream::~Stream() {
+    // No lock can be used in destructor
+    fclose(_file);
+}
+
+int Stream::putc(int c) {
+    lock();
+    fflush(_file);
+    int ret = std::fputc(c, _file);
+    unlock();
+    return ret;
+}
+int Stream::puts(const char *s) {
+    lock();
+    fflush(_file);
+    int ret = std::fputs(s, _file);
+    unlock();
+    return ret;
+}
+int Stream::getc() {
+    lock();
+    fflush(_file);
+    int ret = mbed_getc(_file);
+    unlock();
+    return ret;
+}
+char* Stream::gets(char *s, int size) {
+    lock();
+    fflush(_file);
+    char *ret = mbed_gets(s,size,_file);
+    unlock();
+    return ret;
+}
+
+int Stream::close() {
+    return 0;
+}
+
+ssize_t Stream::write(const void* buffer, size_t length) {
+    const char* ptr = (const char*)buffer;
+    const char* end = ptr + length;
+
+    lock();
+    while (ptr != end) {
+        if (_putc(*ptr++) == EOF) {
+            break;
+        }
+    }
+    unlock();
+
+    return ptr - (const char*)buffer;
+}
+
+ssize_t Stream::read(void* buffer, size_t length) {
+    char* ptr = (char*)buffer;
+    char* end = ptr + length;
+
+    lock();
+    while (ptr != end) {
+        int c = _getc();
+        if (c==EOF) break;
+        *ptr++ = c;
+    }
+    unlock();
+
+    return ptr - (const char*)buffer;
+}
+
+off_t Stream::seek(off_t offset, int whence) {
+    return 0;
+}
+
+off_t Stream::tell() {
+    return 0;
+}
+
+void Stream::rewind() {
+}
+
+int Stream::isatty() {
+    return 0;
+}
+
+int Stream::sync() {
+    return 0;
+}
+
+off_t Stream::size() {
+    return 0;
+}
+
+int Stream::printf(const char* format, ...) {
+    lock();
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfprintf(_file, format, arg);
+    va_end(arg);
+    unlock();
+    return r;
+}
+
+int Stream::scanf(const char* format, ...) {
+    lock();
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfscanf(_file, format, arg);
+    va_end(arg);
+    unlock();
+    return r;
+}
+
+int Stream::vprintf(const char* format, std::va_list args) {
+    lock();
+    fflush(_file);
+    int r = vfprintf(_file, format, args);
+    unlock();
+    return r;
+}
+
+int Stream::vscanf(const char* format, std::va_list args) {
+    lock();
+    fflush(_file);
+    int r = vfscanf(_file, format, args);
+    unlock();
+    return r;
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Stream.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Stream.h
new file mode 100755
index 0000000..fd74b05
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Stream.h
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform/platform.h"
+#include "platform/FileLike.h"
+#include "platform/FileHandle.h"
+#include "platform/NonCopyable.h"
+#include <cstdio>
+#include <cstdarg>
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+
+extern void mbed_set_unbuffered_stream(std::FILE *_file);
+extern int mbed_getc(std::FILE *_file);
+extern char* mbed_gets(char *s, int size, std::FILE *_file);
+/** @}*/
+
+/** File stream
+ *
+ * @note Synchronization level: Set by subclass
+ * @ingroup platform
+ */
+class Stream : public FileLike, private NonCopyable<Stream> {
+
+public:
+    Stream(const char *name=NULL);
+    virtual ~Stream();
+
+    int putc(int c);
+    int puts(const char *s);
+    int getc();
+    char *gets(char *s, int size);
+    int printf(const char* format, ...);
+    int scanf(const char* format, ...);
+    int vprintf(const char* format, std::va_list args);
+    int vscanf(const char* format, std::va_list args);
+
+    operator std::FILE*() {return _file;}
+
+protected:
+    virtual int close();
+    virtual ssize_t write(const void* buffer, size_t length);
+    virtual ssize_t read(void* buffer, size_t length);
+    virtual off_t seek(off_t offset, int whence);
+    virtual off_t tell();
+    virtual void rewind();
+    virtual int isatty();
+    virtual int sync();
+    virtual off_t size();
+
+    virtual int _putc(int c) = 0;
+    virtual int _getc() = 0;
+
+    std::FILE *_file;
+
+    /** Acquire exclusive access to this object.
+     */
+    virtual void lock() {
+        // Stub
+    }
+
+    /** Release exclusive access to this object.
+     */
+    virtual void unlock() {
+        // Stub
+    }
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Transaction.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Transaction.h
new file mode 100755
index 0000000..8e26236
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/Transaction.h
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRANSACTION_H
+#define MBED_TRANSACTION_H
+
+#include "platform/platform.h"
+#include "platform/FunctionPointer.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+/** Transaction structure
+ * @ingroup platform
+ */
+typedef struct {
+    void *tx_buffer;           /**< Tx buffer */
+    size_t tx_length;          /**< Length of Tx buffer*/
+    void *rx_buffer;           /**< Rx buffer */
+    size_t rx_length;          /**< Length of Rx buffer */
+    uint32_t event;            /**< Event for a transaction */
+    event_callback_t callback; /**< User's callback */
+    uint8_t width;             /**< Buffer's word width (8, 16, 32, 64) */
+} transaction_t;
+
+/** Transaction class defines a transaction.
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template<typename Class>
+class Transaction {
+public:
+    Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
+    }
+
+    Transaction() : _obj(), _data() {
+    }
+
+    ~Transaction() {
+    }
+
+    /** Get object's instance for the transaction
+     *
+     * @return The object which was stored
+     */
+    Class* get_object() {
+        return _obj;
+    }
+
+    /** Get the transaction
+     *
+     * @return The transaction which was stored
+     */
+    transaction_t* get_transaction() {
+        return &_data;
+    }
+
+private:
+    Class* _obj;
+    transaction_t _data;
+};
+
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/critical.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/critical.h
new file mode 100755
index 0000000..c790e83
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/critical.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_CRITICAL_H
+#define MBED_OLD_CRITICAL_H
+
+#warning critical.h has been replaced by mbed_critical.h, please update to mbed_critical.h [since mbed-os-5.3]
+#include "platform/mbed_critical.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_alloc_wrappers.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_alloc_wrappers.cpp
new file mode 100755
index 0000000..9431811
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_alloc_wrappers.cpp
@@ -0,0 +1,365 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/mbed_mem_trace.h"
+#include "platform/mbed_stats.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* There are two memory tracers in mbed OS:
+
+- the first can be used to detect the maximum heap usage at runtime. It is
+  activated by defining the MBED_HEAP_STATS_ENABLED macro.
+- the second can be used to trace each memory call by automatically invoking
+  a callback on each memory operation (see hal/api/mbed_mem_trace.h). It is
+  activated by defining the MBED_MEM_TRACING_ENABLED macro.
+
+Both tracers can be activated and deactivated in any combination. If both tracers
+are active, the second one (MBED_MEM_TRACING_ENABLED) will trace the first one's
+(MBED_HEAP_STATS_ENABLED) memory calls.*/
+
+/******************************************************************************/
+/* Implementation of the runtime max heap usage checker                       */
+/******************************************************************************/
+
+/* Size must be a multiple of 8 to keep alignment */
+typedef struct {
+    uint32_t size;
+    uint32_t pad;
+} alloc_info_t;
+
+#ifdef MBED_MEM_TRACING_ENABLED
+static SingletonPtr<PlatformMutex> mem_trace_mutex;
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+static SingletonPtr<PlatformMutex> malloc_stats_mutex;
+static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0};
+#endif
+
+void mbed_stats_heap_get(mbed_stats_heap_t *stats)
+{
+#ifdef MBED_HEAP_STATS_ENABLED
+    extern uint32_t mbed_heap_size;
+    heap_stats.reserved_size = mbed_heap_size;
+
+    malloc_stats_mutex->lock();
+    memcpy(stats, &heap_stats, sizeof(mbed_stats_heap_t));
+    malloc_stats_mutex->unlock();
+#else
+    memset(stats, 0, sizeof(mbed_stats_heap_t));
+#endif
+}
+
+/******************************************************************************/
+/* GCC memory allocation wrappers                                             */
+/******************************************************************************/
+
+#if defined(TOOLCHAIN_GCC)
+
+#ifdef   FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+#endif/* FEATURE_UVISOR */
+
+extern "C" {
+    void * __real__malloc_r(struct _reent * r, size_t size);
+    void * __real__memalign_r(struct _reent * r, size_t alignment, size_t bytes);
+    void * __real__realloc_r(struct _reent * r, void * ptr, size_t size);
+    void __real__free_r(struct _reent * r, void * ptr);
+    void* __real__calloc_r(struct _reent * r, size_t nmemb, size_t size);
+}
+
+// TODO: memory tracing doesn't work with uVisor enabled.
+#if !defined(FEATURE_UVISOR)
+
+extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = (alloc_info_t*)__real__malloc_r(r, size + sizeof(alloc_info_t));
+    if (alloc_info != NULL) {
+        alloc_info->size = size;
+        ptr = (void*)(alloc_info + 1);
+        heap_stats.current_size += size;
+        heap_stats.total_size += size;
+        heap_stats.alloc_cnt += 1;
+        if (heap_stats.current_size > heap_stats.max_size) {
+            heap_stats.max_size = heap_stats.current_size;
+        }
+    } else {
+        heap_stats.alloc_fail_cnt += 1;
+    }
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = __real__malloc_r(r, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) {
+    void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Implement realloc_r with malloc and free.
+    // The function realloc_r can't be used here directly since
+    // it can call into __wrap__malloc_r (returns ptr + 4) or
+    // resize memory directly (returns ptr + 0).
+
+    // Note - no lock needed since malloc and free are thread safe
+
+    // Get old size
+    uint32_t old_size = 0;
+    if (ptr != NULL) {
+        alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+        old_size = alloc_info->size;
+    }
+
+    // Allocate space
+    if (size != 0) {
+        new_ptr = malloc(size);
+    }
+
+    // If the new buffer has been allocated copy the data to it
+    // and free the old buffer
+    if (new_ptr != NULL) {
+        uint32_t copy_size = (old_size < size) ? old_size : size;
+        memcpy(new_ptr, (void*)ptr, copy_size);
+        free(ptr);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    new_ptr = __real__realloc_r(r, ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return new_ptr;
+}
+
+extern "C" void __wrap__free_r(struct _reent * r, void * ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = NULL;
+    if (ptr != NULL) {
+        alloc_info = ((alloc_info_t*)ptr) - 1;
+        heap_stats.current_size -= alloc_info->size;
+        heap_stats.alloc_cnt -= 1;
+    }
+    __real__free_r(r, (void*)alloc_info);
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    __real__free_r(r, ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc is thread safe
+
+    ptr = malloc(nmemb * size);
+    if (ptr != NULL) {
+        memset(ptr, 0, nmemb * size);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = __real__calloc_r(r, nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void * __wrap__memalign_r(struct _reent * r, size_t alignment, size_t bytes) {
+    return __real__memalign_r(r, alignment, bytes);
+}
+
+#endif // if !defined(FEATURE_UVISOR)
+
+
+/******************************************************************************/
+/* ARMCC / IAR memory allocation wrappers                                     */
+/******************************************************************************/
+
+#elif defined(TOOLCHAIN_ARM) || defined(__ICCARM__)
+
+#if defined(TOOLCHAIN_ARM)
+#define SUPER_MALLOC    $Super$$malloc
+#define SUB_MALLOC      $Sub$$malloc
+#define SUPER_REALLOC   $Super$$realloc
+#define SUB_REALLOC     $Sub$$realloc
+#define SUPER_CALLOC    $Super$$calloc
+#define SUB_CALLOC      $Sub$$calloc
+#define SUPER_FREE      $Super$$free
+#define SUB_FREE        $Sub$$free
+#elif defined(__ICCARM__)
+#define SUPER_MALLOC    $Super$$__iar_dlmalloc
+#define SUB_MALLOC      $Sub$$__iar_dlmalloc
+#define SUPER_REALLOC   $Super$$__iar_dlrealloc
+#define SUB_REALLOC     $Sub$$__iar_dlrealloc
+#define SUPER_CALLOC    $Super$$__iar_dlcalloc
+#define SUB_CALLOC      $Sub$$__iar_dlcalloc
+#define SUPER_FREE      $Super$$__iar_dlfree
+#define SUB_FREE        $Sub$$__iar_dlfree
+#endif
+
+/* Enable hooking of memory function only if tracing is also enabled */
+#if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+extern "C" {
+    void *SUPER_MALLOC(size_t size);
+    void *SUPER_REALLOC(void *ptr, size_t size);
+    void *SUPER_CALLOC(size_t nmemb, size_t size);
+    void SUPER_FREE(void *ptr);
+}
+
+extern "C" void* SUB_MALLOC(size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = (alloc_info_t*)SUPER_MALLOC(size + sizeof(alloc_info_t));
+    if (alloc_info != NULL) {
+        alloc_info->size = size;
+        ptr = (void*)(alloc_info + 1);
+        heap_stats.current_size += size;
+        heap_stats.total_size += size;
+        heap_stats.alloc_cnt += 1;
+        if (heap_stats.current_size > heap_stats.max_size) {
+            heap_stats.max_size = heap_stats.current_size;
+        }
+    } else {
+        heap_stats.alloc_fail_cnt += 1;
+    }
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = SUPER_MALLOC(size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void* SUB_REALLOC(void *ptr, size_t size) {
+    void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc and free are thread safe
+
+    // Get old size
+    uint32_t old_size = 0;
+    if (ptr != NULL) {
+        alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+        old_size = alloc_info->size;
+    }
+
+    // Allocate space
+    if (size != 0) {
+        new_ptr = malloc(size);
+    }
+
+    // If the new buffer has been allocated copy the data to it
+    // and free the old buffer
+    if (new_ptr != NULL) {
+        uint32_t copy_size = (old_size < size) ? old_size : size;
+        memcpy(new_ptr, (void*)ptr, copy_size);
+        free(ptr);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    new_ptr = SUPER_REALLOC(ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return new_ptr;
+}
+
+extern "C" void *SUB_CALLOC(size_t nmemb, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc is thread safe
+    ptr = malloc(nmemb * size);
+    if (ptr != NULL) {
+        memset(ptr, 0, nmemb * size);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = SUPER_CALLOC(nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void SUB_FREE(void *ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = NULL;
+    if (ptr != NULL) {
+        alloc_info = ((alloc_info_t*)ptr) - 1;
+        heap_stats.current_size -= alloc_info->size;
+        heap_stats.alloc_cnt -= 1;
+    }
+    SUPER_FREE((void*)alloc_info);
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    SUPER_FREE(ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+#endif // #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+/******************************************************************************/
+/* Allocation wrappers for other toolchains are not supported yet             */
+/******************************************************************************/
+
+#else
+
+#ifdef MBED_MEM_TRACING_ENABLED
+#error Memory tracing is not supported with the current toolchain.
+#endif
+
+#ifdef MBED_HEAP_STATS_ENABLED
+#error Heap statistics are not supported with the current toolchain.
+#endif
+
+#endif // #if defined(TOOLCHAIN_GCC)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_application.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_application.c
new file mode 100755
index 0000000..75657f6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_application.c
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "platform/mbed_application.h"
+
+#if MBED_APPLICATION_SUPPORT
+
+static void powerdown_nvic(void);
+static void powerdown_scb(uint32_t vtor);
+static void start_new_application(void *sp, void *pc);
+
+void mbed_start_application(uintptr_t address)
+{
+    void *sp;
+    void *pc;
+
+    // Interrupts are re-enabled in start_new_application
+    __disable_irq();
+
+    SysTick->CTRL = 0x00000000;
+    powerdown_nvic();
+    powerdown_scb(address);
+
+    sp = *((void**)address + 0);
+    pc = *((void**)address + 1);
+    start_new_application(sp, pc);
+}
+
+static void powerdown_nvic()
+{
+    int isr_groups_32;
+    int i;
+    int j;
+
+    isr_groups_32 = ((SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos) + 1;
+    for (i = 0; i < isr_groups_32; i++) {
+        NVIC->ICER[i] = 0xFFFFFFFF;
+        NVIC->ICPR[i] = 0xFFFFFFFF;
+        for (j = 0; j < 8; j++) {
+            NVIC->IP[i * 8 + j] = 0x00000000;
+        }
+    }
+}
+
+static void powerdown_scb(uint32_t vtor)
+{
+    int i;
+
+    // SCB->CPUID   - Read only CPU ID register
+    SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk;
+    SCB->VTOR = vtor;
+    SCB->AIRCR = 0x05FA | 0x0000;
+    SCB->SCR = 0x00000000;
+    // SCB->CCR     - Implementation defined value
+    for (i = 0; i < 12; i++) {
+#if defined(__CORTEX_M7)
+        SCB->SHPR[i] = 0x00;
+#else
+        SCB->SHP[i] = 0x00;
+#endif
+    }
+    SCB->SHCSR = 0x00000000;
+    SCB->CFSR = 0xFFFFFFFF;
+    SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk;
+    SCB->DFSR = SCB_DFSR_EXTERNAL_Msk | SCB_DFSR_VCATCH_Msk |
+                SCB_DFSR_DWTTRAP_Msk | SCB_DFSR_BKPT_Msk | SCB_DFSR_HALTED_Msk;
+    // SCB->MMFAR   - Implementation defined value
+    // SCB->BFAR    - Implementation defined value
+    // SCB->AFSR    - Implementation defined value
+    // SCB->PFR     - Read only processor feature register
+    // SCB->DFR     - Read only debug feature registers
+    // SCB->ADR     - Read only auxiliary feature registers
+    // SCB->MMFR    - Read only memory model feature registers
+    // SCB->ISAR    - Read only instruction set attribute registers
+    // SCB->CPACR   - Implementation defined value
+}
+
+#if defined (__CC_ARM)
+
+__asm static void start_new_application(void *sp, void *pc)
+{
+    MOV R2, #0
+    MSR CONTROL, R2         // Switch to main stack
+    MOV SP, R0
+    MSR PRIMASK, R2         // Enable interrupts
+    BX R1
+}
+
+#elif defined (__GNUC__) || defined (__ICCARM__)
+
+void start_new_application(void *sp, void *pc)
+{
+    __asm volatile (
+        "mov    r2, #0      \n"
+        "msr    control, r2 \n" // Switch to main stack
+        "mov    sp, %0      \n"
+        "msr    primask, r2 \n" // Enable interrupts
+        "bx     %1          \n"
+        :
+        : "l" (sp), "l" (pc)
+        : "r2", "cc", "memory"
+    );
+}
+
+#else
+
+#error "Unsupported toolchain"
+
+#endif
+
+#endif /* MBED_APPLICATION_SUPPORT */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_application.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_application.h
new file mode 100755
index 0000000..633b6a8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_application.h
@@ -0,0 +1,55 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_APPLICATION_H
+#define MBED_APPLICATION_H
+
+#include<stdint.h>
+
+#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7)
+#define MBED_APPLICATION_SUPPORT 1
+#else
+#define MBED_APPLICATION_SUPPORT 0
+#endif
+
+#if MBED_APPLICATION_SUPPORT
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  Start the application at the given address. This function does
+ *  not return. It is the applications responsibility for flushing to
+ *  or powering down external components such as filesystems or
+ *  socket connections before calling this function. For Cortex-M
+ *  devices this function powers down generic system components such as
+ *  the NVIC and set the vector table to that of the new image followed
+ *  by jumping to the reset handler of the new image.
+ *
+ *  @param address    Starting address of next application to run
+ */
+void mbed_start_application(uintptr_t address);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_assert.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_assert.c
new file mode 100755
index 0000000..8a698ab
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_assert.c
@@ -0,0 +1,27 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/mbed_assert.h"
+#include "device.h"
+
+#include "platform/mbed_interface.h"
+#include "platform/mbed_critical.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+    core_util_critical_section_enter();
+    mbed_error_printf("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+    mbed_die();
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_assert.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_assert.h
new file mode 100755
index 0000000..bd86983
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_assert.h
@@ -0,0 +1,113 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#include "mbed_preprocessor.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ *  This function is active only if NDEBUG is not defined prior to including this
+ *  assert header file.
+ *  In case of MBED_ASSERT failing condition, error() is called with the assertation message.
+ *  @param expr Expresion to be checked.
+ *  @param file File where assertation failed.
+ *  @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr)                                \
+do {                                                     \
+    if (!(expr)) {                                       \
+        mbed_assert_internal(#expr, __FILE__, __LINE__); \
+    }                                                    \
+} while (0)
+#endif
+
+
+/** MBED_STATIC_ASSERT
+ *  Declare compile-time assertions, results in compile-time error if condition is false
+ *
+ *  The assertion acts as a declaration that can be placed at file scope, in a
+ *  code block (except after a label), or as a member of a C++ class/struct/union.
+ *
+ *  @note
+ *  Use of MBED_STATIC_ASSERT as a member of a struct/union is limited:
+ *  - In C++, MBED_STATIC_ASSERT is valid in class/struct/union scope.
+ *  - In C, MBED_STATIC_ASSERT is not valid in struct/union scope, and
+ *    MBED_STRUCT_STATIC_ASSERT is provided as an alternative that is valid
+ *    in C and C++ class/struct/union scope.
+ *
+ *  @code
+ *  MBED_STATIC_ASSERT(MBED_LIBRARY_VERSION >= 120,
+ *          "The mbed library must be at least version 120");
+ *
+ *  int main() {
+ *      MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
+ *              "An int must be larger than a char");
+ *  }
+ *  @endcode
+ */
+#if defined(__cplusplus) && (__cplusplus >= 201103L || __cpp_static_assert >= 200410L)
+#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
+#elif !defined(__cplusplus) && __STDC_VERSION__ >= 201112L
+#define MBED_STATIC_ASSERT(expr, msg) _Static_assert(expr, msg)
+#elif defined(__cplusplus) && defined(__GNUC__) && defined(__GXX_EXPERIMENTAL_CXX0X__) \
+    && (__GNUC__*100 + __GNUC_MINOR__) > 403L
+#define MBED_STATIC_ASSERT(expr, msg) __extension__ static_assert(expr, msg)
+#elif !defined(__cplusplus) && defined(__GNUC__) && !defined(__CC_ARM) \
+    && (__GNUC__*100 + __GNUC_MINOR__) > 406L
+#define MBED_STATIC_ASSERT(expr, msg) __extension__ _Static_assert(expr, msg)
+#elif defined(__ICCARM__)
+#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
+#else
+#define MBED_STATIC_ASSERT(expr, msg) \
+    enum {MBED_CONCAT(MBED_ASSERTION_AT_, __LINE__) = sizeof(char[(expr) ? 1 : -1])}
+#endif
+
+/** MBED_STRUCT_STATIC_ASSERT
+ *  Declare compile-time assertions, results in compile-time error if condition is false
+ *
+ *  Unlike MBED_STATIC_ASSERT, MBED_STRUCT_STATIC_ASSERT can and must be used
+ *  as a member of a C/C++ class/struct/union.
+ *
+ *  @code
+ *  struct thing {
+ *      MBED_STATIC_ASSERT(2 + 2 == 4,
+ *              "Hopefully the universe is mathematically consistent");
+ *  };
+ *  @endcode
+ */
+#define MBED_STRUCT_STATIC_ASSERT(expr, msg) int : (expr) ? 0 : -1
+
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_board.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_board.c
new file mode 100755
index 0000000..227c774
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_board.c
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "hal/gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_interface.h"
+#include "platform/mbed_critical.h"
+#include "hal/serial_api.h"
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+WEAK void mbed_die(void) {
+#if !defined (NRF51_H) && !defined(TARGET_EFM32)
+    core_util_critical_section_enter();
+#endif
+    gpio_t led_err; gpio_init_out(&led_err, LED1);
+
+    while (1) {
+        for (int i = 0; i < 4; ++i) {
+            gpio_write(&led_err, 1);
+            wait_ms(150);
+            gpio_write(&led_err, 0);
+            wait_ms(150);
+        }
+
+        for (int i = 0; i < 4; ++i) {
+            gpio_write(&led_err, 1);
+            wait_ms(400);
+            gpio_write(&led_err, 0);
+            wait_ms(400);
+        }
+    }
+}
+
+void mbed_error_printf(const char* format, ...) {
+    va_list arg;
+    va_start(arg, format);
+    mbed_error_vfprintf(format, arg);
+    va_end(arg);
+}
+
+void mbed_error_vfprintf(const char * format, va_list arg) {
+#if DEVICE_SERIAL
+#define ERROR_BUF_SIZE      (128)
+    core_util_critical_section_enter();
+    char buffer[ERROR_BUF_SIZE];
+    int size = vsnprintf(buffer, ERROR_BUF_SIZE, format, arg);
+    if (size > 0) {
+        if (!stdio_uart_inited) {
+            serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+        }
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+        char stdio_out_prev = '\0';
+        for (int i = 0; i < size; i++) {
+            if (buffer[i] == '\n' && stdio_out_prev != '\r') {
+                 serial_putc(&stdio_uart, '\r');
+            }
+            serial_putc(&stdio_uart, buffer[i]);
+            stdio_out_prev = buffer[i];
+        }
+#else
+        for (int i = 0; i < size; i++) {
+            serial_putc(&stdio_uart, buffer[i]);
+        }
+#endif
+    }
+    core_util_critical_section_exit();
+#endif
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_critical.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_critical.c
new file mode 100755
index 0000000..6afb48e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_critical.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Declare __STDC_LIMIT_MACROS so stdint.h defines UINT32_MAX when using C++ */
+#define __STDC_LIMIT_MACROS
+#include "platform/mbed_critical.h"
+
+#include "cmsis.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+static volatile uint32_t interrupt_enable_counter = 0;
+static volatile bool critical_interrupts_disabled = false;
+
+bool core_util_are_interrupts_enabled(void)
+{
+#if defined(__CORTEX_A9)
+    return ((__get_CPSR() & 0x80) == 0);
+#else
+    return ((__get_PRIMASK() & 0x1) == 0);
+#endif
+}
+
+bool core_util_is_isr_active(void)
+{
+#if defined(__CORTEX_A9)
+    switch(__get_CPSR() & 0x1FU) {
+        case MODE_USR:
+        case MODE_SYS:
+            return false;
+        case MODE_SVC:
+        default:
+            return true;
+    }
+#else
+    return (__get_IPSR() != 0U);
+#endif
+}
+
+MBED_WEAK void core_util_critical_section_enter(void)
+{
+    bool interrupts_disabled = !core_util_are_interrupts_enabled();
+    __disable_irq();
+
+    /* Save the interrupt disabled state as it was prior to any nested critical section lock use */
+    if (!interrupt_enable_counter) {
+        critical_interrupts_disabled = interrupts_disabled;
+    }
+
+    /* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
+       are enabled, then something has gone badly wrong thus assert an error.
+    */
+    MBED_ASSERT(interrupt_enable_counter < UINT32_MAX); 
+// FIXME
+#ifndef   FEATURE_UVISOR
+    if (interrupt_enable_counter > 0) {
+        MBED_ASSERT(interrupts_disabled);
+    }
+#else
+#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+    interrupt_enable_counter++;
+}
+
+MBED_WEAK void core_util_critical_section_exit(void)
+{
+    /* If critical_section_enter has not previously been called, do nothing */
+    if (interrupt_enable_counter) {
+
+// FIXME
+#ifndef   FEATURE_UVISOR
+        bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
+
+        MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
+#else
+#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+
+        interrupt_enable_counter--;
+
+        /* Only re-enable interrupts if we are exiting the last of the nested critical sections and
+           interrupts were enabled on entry to the first critical section.
+        */
+        if (!interrupt_enable_counter && !critical_interrupts_disabled) {
+            __enable_irq();
+        }
+    }
+}
+
+#if __EXCLUSIVE_ACCESS
+
+/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
+#if defined (__CC_ARM) 
+#pragma diag_suppress 3731
+#endif
+
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+    uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
+    if (currentValue != *expectedCurrentValue) {
+        *expectedCurrentValue = currentValue;
+        __CLREX();
+        return false;
+    }
+
+    return !__STREXB(desiredValue, (volatile uint8_t*)ptr);
+}
+
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+    uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
+    if (currentValue != *expectedCurrentValue) {
+        *expectedCurrentValue = currentValue;
+        __CLREX();
+        return false;
+    }
+
+    return !__STREXH(desiredValue, (volatile uint16_t*)ptr);
+}
+
+
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+    uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
+    if (currentValue != *expectedCurrentValue) {
+        *expectedCurrentValue = currentValue;
+        __CLREX();
+        return false;
+    }
+
+    return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
+}
+
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    do {
+        newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta;
+    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+    return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    do {
+        newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta;
+    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+    return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    do {
+        newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta;
+    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+    return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    do {
+        newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta;
+    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+    return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    do {
+        newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta;
+    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+    return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    do {
+        newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta;
+    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+    return newValue;
+}
+
+#else
+
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+    bool success;
+    uint8_t currentValue;
+    core_util_critical_section_enter();
+    currentValue = *ptr;
+    if (currentValue == *expectedCurrentValue) {
+        *ptr = desiredValue;
+        success = true;
+    } else {
+        *expectedCurrentValue = currentValue;
+        success = false;
+    }
+    core_util_critical_section_exit();
+    return success;
+}
+
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+    bool success;
+    uint16_t currentValue;
+    core_util_critical_section_enter();
+    currentValue = *ptr;
+    if (currentValue == *expectedCurrentValue) {
+        *ptr = desiredValue;
+        success = true;
+    } else {
+        *expectedCurrentValue = currentValue;
+        success = false;
+    }
+    core_util_critical_section_exit();
+    return success;
+}
+
+
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+    bool success;
+    uint32_t currentValue;
+    core_util_critical_section_enter();
+    currentValue = *ptr;
+    if (currentValue == *expectedCurrentValue) {
+        *ptr = desiredValue;
+        success = true;
+    } else {
+        *expectedCurrentValue = currentValue;
+        success = false;
+    }
+    core_util_critical_section_exit();
+    return success;
+}
+
+
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr + delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr + delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr + delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr - delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr - delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr - delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+#endif
+
+
+bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
+    return core_util_atomic_cas_u32(
+            (uint32_t *)ptr,
+            (uint32_t *)expectedCurrentValue,
+            (uint32_t)desiredValue);
+}
+
+void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
+    return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+}
+
+void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
+    return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_critical.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_critical.h
new file mode 100755
index 0000000..8aa314a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_critical.h
@@ -0,0 +1,370 @@
+
+/** \addtogroup platform */
+/** @{*/
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_UTIL_CRITICAL_H__
+#define __MBED_UTIL_CRITICAL_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** Determine the current interrupts enabled state
+  *
+  * This function can be called to determine whether or not interrupts are currently enabled.
+  * @note
+  * NOTE:
+  * This function works for both cortex-A and cortex-M, although the underlyng implementation
+  * differs.
+  * @return true if interrupts are enabled, false otherwise
+  */
+bool core_util_are_interrupts_enabled(void);
+
+/** Determine if this code is executing from an interrupt
+  *
+  * This function can be called to determine if the code is running on interrupt context.
+  * @note
+  * NOTE:
+  * This function works for both cortex-A and cortex-M, although the underlyng implementation
+  * differs.
+  * @return true if in an isr, false otherwise
+  */
+bool core_util_is_isr_active(void);
+
+/** Mark the start of a critical section
+  *
+  * This function should be called to mark the start of a critical section of code.
+  * @note
+  * NOTES:
+  * 1) The use of this style of critical section is targetted at C based implementations.
+  * 2) These critical sections can be nested.
+  * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+  *    section) will be preserved on exit from the section.
+  * 4) This implementation will currently only work on code running in privileged mode.
+  */
+void core_util_critical_section_enter(void);
+
+/** Mark the end of a critical section
+  *
+  * This function should be called to mark the end of a critical section of code.
+  * @note
+  * NOTES:
+  * 1) The use of this style of critical section is targetted at C based implementations.
+  * 2) These critical sections can be nested.
+  * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+  *    section) will be preserved on exit from the section.
+  * 4) This implementation will currently only work on code running in privileged mode.
+  */
+void core_util_critical_section_exit(void);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented.
+ * @return          The new incremented value.
+ */
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented.
+ * @return          The new incremented value.
+ */
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented.
+ * @return          The new incremented value.
+ */
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented in bytes.
+ * @return          The new incremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ *       and the pointer is incremented by bytes.
+ */
+void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented.
+ * @return          The new decremented value.
+ */
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented.
+ * @return          The new decremented value.
+ */
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented.
+ * @return          The new decremented value.
+ */
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented in bytes.
+ * @return          The new decremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ *       and the pointer is decremented by bytes
+ */
+void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+
+#endif // __MBED_UTIL_CRITICAL_H__
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_debug.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_debug.h
new file mode 100755
index 0000000..761c1eb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_debug.h
@@ -0,0 +1,71 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+    va_list args;
+    va_start(args, format);
+    vfprintf(stderr, format, args);
+    va_end(args);
+#endif
+}
+
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (== 0) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (!= 0)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+    if (condition) {
+        va_list args;
+        va_start(args, format);
+        vfprintf(stderr, format, args);
+        va_end(args);
+    }
+#endif
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_error.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_error.c
new file mode 100755
index 0000000..3742203
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_error.c
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+static uint8_t error_in_progress = 0;
+
+WEAK void error(const char* format, ...) {
+
+    // Prevent recursion if error is called again
+    if (error_in_progress) {
+        return;
+    }
+    error_in_progress = 1;
+
+#ifndef NDEBUG
+    va_list arg;
+    va_start(arg, format);
+    mbed_error_vfprintf(format, arg);
+    va_end(arg);
+#endif
+    exit(1);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_error.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_error.h
new file mode 100755
index 0000000..1da5513
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_error.h
@@ -0,0 +1,77 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @param format    C string that contains data stream to be printed.
+ *                  Code snippets below show valid format.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ *     #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ *     error("expected x to be less than 5, but got %d", x);
+ * }
+ * @endcode
+ *
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void error(const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_interface.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_interface.c
new file mode 100755
index 0000000..84ab20c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_interface.c
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "platform/mbed_interface.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_semihost_api.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+    return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+    if (mbed_interface_connected()) {
+        semihost_reset();
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+WEAK int mbed_interface_uid(char *uid) {
+    if (mbed_interface_connected()) {
+        return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+    } else {
+        uid[0] = 0;
+        return -1;
+    }
+}
+
+int mbed_interface_disconnect(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_disabledebug()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+int mbed_interface_powerdown(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_powerdown()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+    mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid) {
+    return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+    char uid[DEVICE_ID_LENGTH + 1];
+    int i;
+
+    // if we have a UID, extract the MAC
+    if (mbed_interface_uid(uid) == 0) {
+        char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+        p += DEVICE_MAC_OFFSET;
+#endif
+        for (i=0; i<6; i++) {
+            int byte;
+            sscanf(p, "%2x", &byte);
+            mac[i] = byte;
+            p += 2;
+        }
+        mac[0] &= ~0x01;    // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
+    } else {  // else return a default MAC
+#endif
+        mac[0] = 0x00;
+        mac[1] = 0x02;
+        mac[2] = 0xF7;
+        mac[3] = 0xF0;
+        mac[4] = 0x00;
+        mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+    }
+#endif
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_interface.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_interface.h
new file mode 100755
index 0000000..538a6a7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_interface.h
@@ -0,0 +1,147 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include <stdarg.h>
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ *  @returns
+ *    1 if interface is connected,
+ *    0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ *  @returns
+ *    1 if successful,
+ *    0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ *  This is a weak function that can be overwritten if required
+ *
+ *  @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ *  @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+/** Print out an error message.  This is typically called when
+ * handling a crash.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * @param format    C string that contains data stream to be printed.
+ *                  Code snippets below show valid format.
+ *
+ * @code
+ * mbed_error_printf("Failed: %s, file: %s, line %d \n", expr, file, line);
+ * @endcode
+ *
+ */
+void mbed_error_printf(const char* format, ...);
+
+/** Print out an error message.  Similar to mbed_error_printf
+ * but uses a va_list.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * @param format    C string that contains data stream to be printed.
+ * @param arg       Variable arguments list
+ *
+ */
+void mbed_error_vfprintf(const char * format, va_list arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_lib.json
new file mode 100755
index 0000000..3185ed1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_lib.json
@@ -0,0 +1,32 @@
+{
+    "name": "platform",
+    "config": {
+        "stdio-convert-newlines": {
+            "help": "Enable conversion to standard newlines on stdin/stdout",
+            "value": false
+        },
+
+        "stdio-baud-rate": {
+            "help": "Baud rate for stdio",
+            "value": 9600
+        },
+
+        "stdio-flush-at-exit": {
+            "help": "Enable or disable the flush of standard I/O's at exit.",
+            "value": true
+        },
+
+        "default-serial-baud-rate": {
+            "help": "Default baud rate for a Serial or RawSerial instance (if not specified in the constructor)",
+            "value": 9600
+        }
+    },
+    "target_overrides": {
+        "EFM32": {
+            "stdio-baud-rate": 115200
+        },
+        "EFR32": {
+            "stdio-baud-rate": 115200
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mem_trace.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mem_trace.c
new file mode 100755
index 0000000..ee00760
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mem_trace.c
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "platform/mbed_mem_trace.h"
+#include "platform/mbed_critical.h"
+
+/******************************************************************************
+ * Internal variables, functions and helpers
+ *****************************************************************************/
+
+/* The callback function that will be called after a traced memory operations finishes. */
+static mbed_mem_trace_cb_t mem_trace_cb;
+/* 'trave_level' guards "trace inside trace" situations (for example, the implementation
+ * of realloc() might call malloc() internally, and since malloc() is also traced, this could
+ * result in two calls to the callback function instead of one. */
+static uint8_t trace_level;
+
+/******************************************************************************
+ * Public interface
+ *****************************************************************************/
+
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) {
+    mem_trace_cb = cb;
+}
+
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void mbed_mem_trace_free(void *ptr, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+}
+
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...) {
+    va_list va;
+    size_t temp_s1, temp_s2;
+    void *temp_ptr;
+
+    va_start(va, caller);
+    switch(op) {
+        case MBED_MEM_TRACE_MALLOC:
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_REALLOC:
+            temp_ptr = va_arg(va, void*);
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_CALLOC:
+            temp_s1 = va_arg(va, size_t);
+            temp_s2 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2);
+            break;
+
+        case MBED_MEM_TRACE_FREE:
+            temp_ptr = va_arg(va, void*);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr);
+            break;
+
+        default:
+            printf("?\n");
+    }
+    va_end(va);
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mem_trace.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mem_trace.h
new file mode 100755
index 0000000..0267255
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mem_trace.h
@@ -0,0 +1,143 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_MEM_TRACE_H__
+#define __MBED_MEM_TRACE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/* Operation types for tracer */
+enum {
+    MBED_MEM_TRACE_MALLOC,
+    MBED_MEM_TRACE_REALLOC,
+    MBED_MEM_TRACE_CALLOC,
+    MBED_MEM_TRACE_FREE
+};
+
+/* Prefix for the output of the default tracer */
+#define MBED_MEM_DEFAULT_TRACER_PREFIX  "#"
+
+/**
+ * Type of the callback used by the memory tracer. This callback is called when a memory
+ * allocation operation (malloc, realloc, calloc, free) is called and tracing is enabled
+ * for that memory allocation function.
+ *
+ * @param op the ID of the operation (MBED_MEM_TRACE_MALLOC, MBED_MEM_TRACE_REALLOC,
+ *           MBED_MEM_TRACE_CALLOC or MBED_MEM_TRACE_FREE).
+ * @param res the result that the memory operation returned (NULL for 'free').
+ * @param caller the caller of the memory operation. Note that the value of 'caller' might be
+ *               unreliable.
+ *
+ * The rest of the parameters passed 'mbed_mem_trace_cb_t' are the same as the memory operations
+ * that triggered its call (see 'man malloc' for details):
+ *
+ * - for malloc: cb(MBED_MEM_TRACE_MALLOC, res, caller, size).
+ * - for realloc: cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size).
+ * - for calloc: cb(MBED_MEM_TRACE_CALLOC, res, caller, nmemb, size).
+ * - for free: cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr).
+ */
+typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void* caller, ...);
+
+/**
+ * Set the callback used by the memory tracer (use NULL for disable tracing).
+ *
+ * @param cb the callback to call on each memory operation.
+ */
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb);
+
+/**
+ * Trace a call to 'malloc'.
+ * @param res the result of running 'malloc'.
+ * @param size the 'size' argument given to 'malloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller);
+
+/**
+ * Trace a call to 'realloc'.
+ * @param res the result of running 'realloc'.
+ * @param ptr the 'ptr' argument given to 'realloc'.
+ * @param size the 'size' argument given to 'realloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller);
+
+/**
+ * Trace a call to 'calloc'.
+ * @param res the result of running 'calloc'.
+ * @param num the 'nmemb' argument given to 'calloc'.
+ * @param size the 'size' argument given to 'calloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller);
+
+/**
+ * Trace a call to 'free'.
+ * @param ptr the 'ptr' argument given to 'free'.
+ * @param caller the caller of the memory operation.
+ */
+void mbed_mem_trace_free(void *ptr, void *caller);
+
+/**
+ * Default memory trace callback. DO NOT CALL DIRECTLY. It is meant to be used
+ * as the second argument of 'mbed_mem_trace_setup'.
+ *
+ * The default callback outputs trace data using 'printf', in a format that's
+ * easily parsable by an external tool. For each memory operation, the callback
+ * outputs a line that begins with "#<op>:<0xresult>;<0xcaller>-":
+ *
+ * @param op        identifies the memory operation ('m' for 'malloc', 'r' for 'realloc',
+ *                  'c' for 'calloc' and 'f' for 'free').
+ * @param res       (base 16) is the result of the memor operation. This is always NULL
+ *                  for 'free', since 'free' doesn't return anything.
+ * @param caller    (base 16) is the caller of the memory operation. Note that the value
+ *                  of 'caller' might be unreliable.
+ *
+ * The rest of the output depends on the operation being traced:
+ *
+ * - for 'malloc': 'size', where 'size' is the original argument to 'malloc'.
+ * - for 'realloc': '0xptr;size', where 'ptr' (base 16) and 'size' are the original arguments to 'realloc'.
+ * - for 'calloc': 'nmemb;size', where 'nmemb' and 'size' are the original arguments to 'calloc'.
+ * - for 'free': '0xptr', where 'ptr' (base 16) is the original argument to 'free'.
+ *
+ * Examples:
+ *
+ * - "#m:0x20003240;0x600d-50" encodes a 'malloc' that returned 0x20003240, was called
+ *   by the instruction at 0x600D with a the 'size' argument equal to 50.
+ * - "#f:0x0;0x602f-0x20003240" encodes a 'free' that was called by the instruction at
+ *   0x602f with the 'ptr' argument equal to 0x20003240.
+ */
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif// #ifndef __MBED_MEM_TRACE_H__
+
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mktime.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mktime.c
new file mode 100755
index 0000000..6954e72
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mktime.c
@@ -0,0 +1,165 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_mktime.h"
+
+/*
+ * time constants 
+ */
+#define SECONDS_BY_MINUTES 60
+#define MINUTES_BY_HOUR 60
+#define SECONDS_BY_HOUR (SECONDS_BY_MINUTES * MINUTES_BY_HOUR)
+#define HOURS_BY_DAY 24 
+#define SECONDS_BY_DAY (SECONDS_BY_HOUR * HOURS_BY_DAY)
+
+/*
+ * 2 dimensional array containing the number of seconds elapsed before a given 
+ * month.
+ * The second index map to the month while the first map to the type of year:
+ *   - 0: non leap year 
+ *   - 1: leap year
+ */
+static const uint32_t seconds_before_month[2][12] = {
+    {
+        0,
+        31 * SECONDS_BY_DAY,
+        (31 + 28) * SECONDS_BY_DAY,
+        (31 + 28 + 31) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31) * SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30) * SECONDS_BY_DAY,
+    },
+    {
+        0,
+        31 * SECONDS_BY_DAY,
+        (31 + 29) * SECONDS_BY_DAY,
+        (31 + 29 + 31) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31) * SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30) * SECONDS_BY_DAY,
+    }
+};
+
+bool _rtc_is_leap_year(int year) {
+    /* 
+     * since in practice, the value manipulated by this algorithm lie in the 
+     * range [70 : 138], the algorith can be reduced to: year % 4.
+     * The algorithm valid over the full range of value is: 
+
+        year = 1900 + year;
+        if (year % 4) {
+            return false;
+        } else if (year % 100) {
+            return true;
+        } else if (year % 400) {
+            return false;
+        }
+        return true;
+
+     */ 
+    return (year) % 4 ? false : true;
+}
+
+time_t _rtc_mktime(const struct tm* time) {
+    // partial check for the upper bound of the range
+    // normalization might happen at the end of the function 
+    // this solution is faster than checking if the input is after the 19th of 
+    // january 2038 at 03:14:07.  
+    if ((time->tm_year < 70) || (time->tm_year > 138)) { 
+        return ((time_t) -1);
+    }
+
+    uint32_t result = time->tm_sec;
+    result += time->tm_min * SECONDS_BY_MINUTES;
+    result += time->tm_hour * SECONDS_BY_HOUR;
+    result += (time->tm_mday - 1) * SECONDS_BY_DAY;
+    result += seconds_before_month[_rtc_is_leap_year(time->tm_year)][time->tm_mon];
+
+    if (time->tm_year > 70) { 
+        // valid in the range [70:138] 
+        uint32_t count_of_leap_days = ((time->tm_year - 1) / 4) - (70 / 4);
+        result += (((time->tm_year - 70) * 365) + count_of_leap_days) * SECONDS_BY_DAY;
+    }
+
+    if (result > INT32_MAX) { 
+        return (time_t) -1;
+    }
+
+    return result;
+}
+
+bool _rtc_localtime(time_t timestamp, struct tm* time_info) {
+    if (((int32_t) timestamp) < 0) { 
+        return false;
+    } 
+
+    time_info->tm_sec = timestamp % 60;
+    timestamp = timestamp / 60;   // timestamp in minutes
+    time_info->tm_min = timestamp % 60;
+    timestamp = timestamp / 60;  // timestamp in hours
+    time_info->tm_hour = timestamp % 24;
+    timestamp = timestamp / 24;  // timestamp in days;
+
+    // compute the weekday
+    // The 1st of January 1970 was a Thursday which is equal to 4 in the weekday
+    // representation ranging from [0:6]
+    time_info->tm_wday = (timestamp + 4) % 7;
+
+    // years start at 70
+    time_info->tm_year = 70;
+    while (true) { 
+        if (_rtc_is_leap_year(time_info->tm_year) && timestamp >= 366) {
+            ++time_info->tm_year;
+            timestamp -= 366;
+        } else if (!_rtc_is_leap_year(time_info->tm_year) && timestamp >= 365) {
+            ++time_info->tm_year;
+            timestamp -= 365;
+        } else {
+            // the remaining days are less than a years
+            break;
+        }
+    }
+
+    time_info->tm_yday = timestamp;
+
+    // convert days into seconds and find the current month
+    timestamp *= SECONDS_BY_DAY;
+    time_info->tm_mon = 11;
+    bool leap = _rtc_is_leap_year(time_info->tm_year);
+    for (uint32_t i = 0; i < 12; ++i) {
+        if ((uint32_t) timestamp < seconds_before_month[leap][i]) {
+            time_info->tm_mon = i - 1;
+            break;
+        }
+    }
+
+    // remove month from timestamp and compute the number of days.
+    // note: unlike other fields, days are not 0 indexed.
+    timestamp -= seconds_before_month[leap][time_info->tm_mon];
+    time_info->tm_mday = (timestamp / SECONDS_BY_DAY) + 1;
+
+    return true;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mktime.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mktime.h
new file mode 100755
index 0000000..b285252
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_mktime.h
@@ -0,0 +1,98 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_MKTIME_H
+#define MBED_MKTIME_H
+
+#include <time.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Compute if a year is a leap year or not.
+ *
+ * @param year The year to test it shall be in the range [70:138]. Year 0 is
+ * translated into year 1900 CE.
+ * @return true if the year in input is a leap year and false otherwise.
+ * @note - For use by the HAL only
+ */
+bool _rtc_is_leap_year(int year);
+
+/* Convert a calendar time into time since UNIX epoch as a time_t.
+ *
+ * This function is a thread safe (partial) replacement for mktime. It is
+ * tailored around RTC peripherals needs and is not by any mean a complete
+ * replacement of mktime.
+ *
+ * @param calendar_time The calendar time to convert into a time_t since epoch.
+ * The fields from tm used for the computation are:
+ *   - tm_sec
+ *   - tm_min
+ *   - tm_hour
+ *   - tm_mday
+ *   - tm_mon
+ *   - tm_year
+ * Other fields are ignored and won't be renormalized by a call to this function.
+ * A valid calendar time is comprised between the 1st january of 1970 at
+ * 00:00:00 and the 19th of january 2038 at 03:14:07.
+ *
+ * @return The calendar time as seconds since UNIX epoch if the input is in the
+ * valid range. Otherwise ((time_t) -1).
+ *
+ * @note Leap seconds are not supported.
+ * @note Values in output range from 0 to INT_MAX.
+ * @note - For use by the HAL only
+ */
+time_t _rtc_mktime(const struct tm* calendar_time);
+
+/* Convert a given time in seconds since epoch into calendar time.
+ *
+ * This function is a thread safe (partial) replacement for localtime. It is
+ * tailored around RTC peripherals specification and is not by any means a
+ * complete of localtime.
+ *
+ * @param timestamp The time (in seconds) to convert into calendar time. Valid
+ * input are in the range [0 : INT32_MAX].
+ * @param calendar_time Pointer to the object which will contain the result of
+ * the conversion. The tm fields filled by this function are:
+ *   - tm_sec
+ *   - tm_min
+ *   - tm_hour
+ *   - tm_mday
+ *   - tm_mon
+ *   - tm_year
+ *   - tm_wday
+ *   - tm_yday
+ * The object remains untouched if the time in input is invalid.
+ * @return true if the conversion was successful, false otherwise.
+ *
+ * @note - For use by the HAL only
+ */
+bool _rtc_localtime(time_t timestamp, struct tm* calendar_time);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_MKTIME_H */
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_poll.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_poll.cpp
new file mode 100755
index 0000000..c2a08fa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_poll.cpp
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_poll.h"
+#include "FileHandle.h"
+#include "Timer.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "rtos/Thread.h"
+#endif
+
+namespace mbed {
+
+// timeout -1 forever, or milliseconds
+int poll(pollfh fhs[], unsigned nfhs, int timeout)
+{
+    /**
+     * TODO Proper wake-up mechanism.
+     * In order to correctly detect availability of read/write a FileHandle, we needed
+     * a select or poll mechanisms. We opted for poll as POSIX defines in
+     * http://pubs.opengroup.org/onlinepubs/009695399/functions/poll.html Currently,
+     * mbed::poll() just spins and scans filehandles looking for any events we are
+     * interested in. In future, his spinning behaviour will be replaced with
+     * condition variables.
+     */
+    Timer timer;
+    if (timeout > 0) {
+        timer.start();
+    }
+
+    int count = 0;
+    for (;;) {
+        /* Scan the file handles */
+        for (unsigned n = 0; n < nfhs; n++) {
+            FileHandle *fh = fhs[n].fh;
+            short mask = fhs[n].events | POLLERR | POLLHUP | POLLNVAL;
+            if (fh) {
+                fhs[n].revents = fh->poll(mask) & mask;
+            } else {
+                fhs[n].revents = POLLNVAL;
+            }
+            if (fhs[n].revents) {
+                count++;
+            }
+        }
+
+        if (count) {
+            break;
+        }
+
+        /* Nothing selected - this is where timeout handling would be needed */
+        if (timeout == 0 || (timeout > 0 && timer.read_ms() > timeout)) {
+            break;
+        }
+#ifdef MBED_CONF_RTOS_PRESENT
+        // TODO - proper blocking
+        // wait for condition variable, wait queue whatever here
+        rtos::Thread::wait(1);
+#endif
+    }
+    return count;
+}
+
+} // namespace mbed
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_poll.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_poll.h
new file mode 100755
index 0000000..635733b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_poll.h
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_POLL_H
+#define MBED_POLL_H
+
+#define POLLIN         0x0001 ///< Data may be read without blocking
+#define POLLOUT        0x0010 ///< Data may be written without blocking
+#define POLLERR        0x1000 ///< An error has occurred on the device or stream
+#define POLLHUP        0x2000 ///< The device has been disconnected
+#define POLLNVAL       0x4000 ///< The specified file handle value is invalid
+
+namespace mbed {
+
+class FileHandle;
+
+/** \addtogroup platform */
+
+
+struct pollfh {
+    FileHandle *fh;
+    short events;
+    short revents;
+};
+
+/** A mechanism to multiplex input/output over a set of file handles(file descriptors).
+ * For every file handle provided, poll() examines it for any events registered for that particular
+ * file handle.
+ *
+ * @param fhs     an array of PollFh struct carrying a FileHandle and bitmasks of events
+ * @param nfhs    number of file handles
+ * @param timeout timer value to timeout or -1 for loop forever
+ *
+ * @return number of file handles selected (for which revents is non-zero). 0 if timed out with nothing selected. -1 for error.
+ */
+int poll(pollfh fhs[], unsigned nfhs, int timeout);
+
+} // namespace mbed
+
+#endif //MBED_POLL_H
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_preprocessor.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_preprocessor.h
new file mode 100755
index 0000000..5e72d99
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_preprocessor.h
@@ -0,0 +1,53 @@
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PREPROCESSOR_H
+#define MBED_PREPROCESSOR_H
+
+
+/** MBED_CONCAT
+ *  Concatenate tokens together
+ *
+ *  @note
+ *  Expands tokens before concatenation
+ *
+ *  @code
+ *  // Creates a unique label based on the line number
+ *  int MBED_CONCAT(UNIQUE_LABEL_, __LINE__) = 1;
+ *  @endcode
+ */
+#define MBED_CONCAT(a, b) MBED_CONCAT_(a, b)
+#define MBED_CONCAT_(a, b) a##b
+
+/** MBED_STRINGIFY
+ *  Converts tokens into strings
+ *
+ *  @note
+ *  Expands tokens before stringification
+ *
+ *  @code
+ *  // Creates a string based on the parameters
+ *  const char *c = MBED_STRINGIFY(This is a ridiculous way to create a string)
+ *  @endcode
+ */
+#define MBED_STRINGIFY(a) MBED_STRINGIFY_(a)
+#define MBED_STRINGIFY_(a) #a
+
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_retarget.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_retarget.cpp
new file mode 100755
index 0000000..6c5f120
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_retarget.cpp
@@ -0,0 +1,1087 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <time.h>
+#include "platform/platform.h"
+#include "platform/FilePath.h"
+#include "hal/serial_api.h"
+#include "hal/us_ticker_api.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_semihost_api.h"
+#include "platform/mbed_interface.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_stats.h"
+#include "platform/mbed_critical.h"
+#include "platform/PlatformMutex.h"
+#include "us_ticker_api.h"
+#include "lp_ticker_api.h"
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+#include <errno.h>
+#include "platform/mbed_retarget.h"
+
+static SingletonPtr<PlatformMutex> _mutex;
+
+#if defined(__ARMCC_VERSION)
+#   if __ARMCC_VERSION >= 6010050
+#      include <arm_compat.h>
+#   endif
+#   include <rt_sys.h>
+#   include <rt_misc.h>
+#   include <stdint.h>
+#   define PREFIX(x)    _sys##x
+#   define OPEN_MAX     _SYS_OPEN
+#   ifdef __MICROLIB
+#       pragma import(__use_full_stdio)
+#   endif
+
+#elif defined(__ICCARM__)
+#   include <yfuns.h>
+#   define PREFIX(x)        _##x
+#   define OPEN_MAX         16
+
+#   define STDIN_FILENO     0
+#   define STDOUT_FILENO    1
+#   define STDERR_FILENO    2
+
+#else
+#   include <sys/stat.h>
+#   include <sys/syslimits.h>
+#   define PREFIX(x)    x
+#endif
+
+#define FILE_HANDLE_RESERVED    0xFFFFFFFF
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[]  = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[]  = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+unsigned char *mbed_heap_start = 0;
+uint32_t mbed_heap_size = 0;
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+static SingletonPtr<PlatformMutex> filehandle_mutex;
+
+namespace mbed {
+void remove_filehandle(FileHandle *file) {
+    filehandle_mutex->lock();
+    /* Remove all open filehandles for this */
+    for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == file) {
+            filehandles[fh_i] = NULL;
+        }
+    }
+    filehandle_mutex->unlock();
+}
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+static char stdio_in_prev;
+static char stdio_out_prev;
+#endif
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+    if (stdio_uart_inited) return;
+    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
+    serial_baud(&stdio_uart, MBED_CONF_PLATFORM_STDIO_BAUD_RATE);
+#endif
+#endif
+}
+
+/**
+ * Sets errno when file opening fails.
+ * Wipes out the filehandle too.
+ *
+ * @param error is a negative error code returned from an mbed function and
+ *              will be negated to store a positive error code in errno
+ */
+static int handle_open_errors(int error, unsigned filehandle_idx) {
+    errno = -error;
+    // Free file handle
+    filehandles[filehandle_idx] = NULL;
+    return -1;
+}
+
+static inline int openmode_to_posix(int openmode) {
+    int posix = openmode;
+#ifdef __ARMCC_VERSION
+    if (openmode & OPEN_PLUS) {
+        posix = O_RDWR;
+    } else if(openmode & OPEN_W) {
+        posix = O_WRONLY;
+    } else if(openmode & OPEN_A) {
+        posix = O_WRONLY|O_APPEND;
+    } else {
+        posix = O_RDONLY;
+    }
+    /* a, w, a+, w+ all create if file does not already exist */
+    if (openmode & (OPEN_A|OPEN_W)) {
+        posix |= O_CREAT;
+    }
+    /* w and w+ truncate */
+    if (openmode & OPEN_W) {
+        posix |= O_TRUNC;
+    }
+#elif defined(__ICCARM__)
+    switch (openmode & _LLIO_RDWRMASK) {
+        case _LLIO_RDONLY: posix = O_RDONLY; break;
+        case _LLIO_WRONLY: posix = O_WRONLY; break;
+        case _LLIO_RDWR  : posix = O_RDWR  ; break;
+    }
+    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#elif defined(TOOLCHAIN_GCC)
+    posix &= ~O_BINARY;
+#endif
+    return posix;
+}
+
+/* @brief 	standard c library fopen() retargeting function.
+ *
+ * This function is invoked by the standard c library retargeting to handle fopen()
+ *
+ * @return
+ *  On success, a valid FILEHANDLE is returned.
+ *  On failure, -1 is returned and errno is set to an appropriate value e.g.
+ *   ENOENT	    file not found (default errno setting)
+ *	 EMFILE		the maximum number of open files was exceeded.
+ *
+ * */
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+    #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+#if !defined(MBED_CONF_RTOS_PRESENT)
+    // valid only for mbed 2
+    // for ulib, this is invoked after RAM init, prior c++
+    // used as hook, as post stack/heap is not active there
+    extern void mbed_copy_nvic(void);
+    extern void mbed_sdk_init(void);
+
+    static int mbed_sdk_inited = 0;
+    if (!mbed_sdk_inited) {
+        mbed_copy_nvic();
+        mbed_sdk_init();
+        mbed_sdk_inited = 1;
+    }
+#endif
+    // Before version 5.03, we were using a patched version of microlib with proper names
+    // This is the workaround that the microlib author suggested us
+    static int n = 0;
+    if (!std::strcmp(name, ":tt")) return n++;
+    #else
+    /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+     */
+    if (std::strcmp(name, __stdin_name) == 0) {
+        init_serial();
+        return 0;
+    } else if (std::strcmp(name, __stdout_name) == 0) {
+        init_serial();
+        return 1;
+    } else if (std::strcmp(name, __stderr_name) == 0) {
+        init_serial();
+        return 2;
+    }
+    #endif
+
+    // find the first empty slot in filehandles
+    filehandle_mutex->lock();
+    unsigned int fh_i;
+    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+    	/* Take a next free filehandle slot available. */
+        if (filehandles[fh_i] == NULL) break;
+    }
+    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+        /* Too many file handles have been opened */
+        errno = EMFILE;
+        filehandle_mutex->unlock();
+        return -1;
+    }
+    filehandles[fh_i] = (FileHandle*)FILE_HANDLE_RESERVED;
+    filehandle_mutex->unlock();
+
+    FileHandle *res = NULL;
+
+    /* FILENAME: ":(pointer)" describes a FileHandle* */
+    if (name[0] == ':') {
+        void *p;
+        memcpy(&p, name + 1, sizeof(p));
+        res = (FileHandle*)p;
+
+    /* FILENAME: "/file_system/file_name" */
+    } else {
+        FilePath path(name);
+
+        if (!path.exists()) {
+            /* The first part of the filename (between first 2 '/') is not a
+             * registered mount point in the namespace.
+             */
+            return handle_open_errors(-ENOENT, fh_i);
+        }
+
+        if (path.isFile()) {
+            res = path.file();
+        } else {
+            FileSystemHandle *fs = path.fileSystem();
+            if (fs == NULL) {
+                return handle_open_errors(-ENOENT, fh_i);
+            }
+            int posix_mode = openmode_to_posix(openmode);
+            int err = fs->open(&res, path.fileName(), posix_mode);
+            if (err) {
+                return handle_open_errors(err, fh_i);
+            }
+        }
+    }
+
+    filehandles[fh_i] = res;
+
+    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    filehandles[fh-3] = NULL;
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    int err = fhc->close();
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes written
+
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED && defined(MBED_CONF_RTOS_PRESENT)
+    if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+        error("Error - writing to a file in an ISR or critical section\r\n");
+    }
+#endif
+
+    if (fh < 3) {
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+        for (unsigned int i = 0; i < length; i++) {
+            if (buffer[i] == '\n' && stdio_out_prev != '\r') {
+                 serial_putc(&stdio_uart, '\r');
+            }
+            serial_putc(&stdio_uart, buffer[i]);
+            stdio_out_prev = buffer[i];
+        }
+#else
+        for (unsigned int i = 0; i < length; i++) {
+            serial_putc(&stdio_uart, buffer[i]);
+        }
+#endif
+#endif
+        n = length;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) {
+            errno = EBADF;
+            return -1;
+        }
+
+        n = fhc->write(buffer, length);
+        if (n < 0) {
+            errno = -n;
+        }
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+extern "C" void PREFIX(_exit)(int return_code) {
+    while(1) {}
+}
+
+extern "C" void _ttywrch(int ch) {
+    serial_putc(&stdio_uart, ch);
+}
+#endif
+
+#if defined(__ICCARM__)
+extern "C" size_t    __read (int        fh, unsigned char *buffer, size_t       length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes read
+
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED && defined(MBED_CONF_RTOS_PRESENT)
+    if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+        error("Error - reading from a file in an ISR or critical section\r\n");
+    }
+#endif
+
+    if (fh < 3) {
+        // only read a character at a time from stdin
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+        while (true) {
+            char c = serial_getc(&stdio_uart);
+            if ((c == '\r' && stdio_in_prev != '\n') ||
+                (c == '\n' && stdio_in_prev != '\r')) {
+                stdio_in_prev = c;
+                *buffer = '\n';
+                break;
+            } else if ((c == '\r' && stdio_in_prev == '\n') ||
+                       (c == '\n' && stdio_in_prev == '\r')) {
+                stdio_in_prev = c;
+                // onto next character
+                continue;
+            } else {
+                stdio_in_prev = c;
+                *buffer = c;
+                break;
+            }
+        }
+#else
+        *buffer = serial_getc(&stdio_uart);
+#endif
+#endif
+        n = 1;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) {
+            errno = EBADF;
+            return -1;
+        }
+
+        n = fhc->read(buffer, length);
+        if (n < 0) {
+            errno = -n;
+        }
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+    /* stdin, stdout and stderr should be tty */
+    if (fh < 3) return 1;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) {
+        errno = EBADF;
+        return 0;
+    }
+
+    int tty = fhc->isatty();
+    if (tty < 0) {
+        errno = -tty;
+        return 0;
+    } else {
+        return tty;
+    }
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long offset)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+#if defined(__ARMCC_VERSION)
+    int whence = SEEK_SET;
+#endif
+
+    if (fh < 3) {
+        errno = ESPIPE;
+        return -1;
+    }
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    off_t off = fhc->seek(offset, whence);
+    if (off < 0) {
+        errno = -off;
+        return -1;
+    }
+    // Assuming INT_MAX = LONG_MAX, so we don't care about prototype difference
+    if (off > INT_MAX) {
+        errno = EOVERFLOW;
+        return -1;
+    }
+    return off;
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    int err = fhc->sync();
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+    if (fh < 3) {
+        errno = EINVAL;
+        return -1;
+    }
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    off_t size = fhc->size();
+    if (size < 0) {
+        errno = -size;
+        return -1;
+    }
+    if (size > LONG_MAX) {
+        errno = EOVERFLOW;
+        return -1;
+    }
+    return size;
+}
+
+extern "C" char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern "C" MBED_WEAK __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+extern "C" __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    return _mbed_user_setup_stackheap(R0, R1, R2, R3);
+}
+
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fh, struct stat *st) {
+    if (fh < 3) {
+        st->st_mode = S_IFCHR;
+        return  0;
+    }
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    st->st_mode = fhc->isatty() ? S_IFCHR : S_IFREG;
+    st->st_size = fhc->size();
+    return 0;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+    FilePath fp(path);
+    FileSystemHandle *fs = fp.fileSystem();
+    if (fs == NULL) {
+        errno = ENOENT;
+        return -1;
+    }
+
+    int err = fs->remove(fp.fileName());
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+    FilePath fpOld(oldname);
+    FilePath fpNew(newname);
+    FileSystemHandle *fsOld = fpOld.fileSystem();
+    FileSystemHandle *fsNew = fpNew.fileSystem();
+
+    if (fsOld == NULL) {
+        errno = ENOENT;
+        return -1;
+    }
+
+    /* rename only if both files are on the same FS */
+    if (fsOld != fsNew) {
+        errno = EXDEV;
+        return -1;
+    }
+
+    int err = fsOld->rename(fpOld.fileName(), fpNew.fileName());
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+extern "C" char *tmpnam(char *s) {
+    errno = EBADF;
+    return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+    errno = EBADF;
+    return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+    return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+    FilePath fp(path);
+    FileSystemHandle* fs = fp.fileSystem();
+    if (fs == NULL) {
+        errno = ENOENT;
+        return NULL;
+    }
+
+    DirHandle *dir;
+    int err = fs->open(&dir, fp.fileName());
+    if (err < 0) {
+        errno = -err;
+        return NULL;
+    }
+
+    return dir;
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+    static struct dirent ent;
+    int err = dir->read(&ent);
+    if (err < 1) {
+        if (err < 0) {
+            errno = -err;
+        }
+        return NULL;
+    }
+
+    return &ent;
+}
+
+extern "C" int closedir(DIR *dir) {
+    int err = dir->close();
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+extern "C" void rewinddir(DIR *dir) {
+    dir->rewind();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+    return dir->tell();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+    dir->seek(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+    FilePath fp(path);
+    FileSystemHandle *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    int err = fs->mkdir(fp.fileName(), mode);
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+extern "C" int stat(const char *path, struct stat *st) {
+    FilePath fp(path);
+    FileSystemHandle *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    int err = fs->stat(fp.fileName(), st);
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+    void __verbose_terminate_handler() {
+        error("Exception");
+    }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+    exit(1);
+}
+
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP.  This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+
+#if defined(TARGET_CORTEX_A)
+extern "C" uint32_t  __HeapLimit;
+#endif
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// Dynamic memory allocation related syscall.
+#if defined(TARGET_NUVOTON)
+// Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
+// __wrap__sbrk() is implemented in:
+// TARGET_NUMAKER_PFM_NUC472    targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/nuc472_retarget.c
+// TARGET_NUMAKER_PFM_M453      targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/m451_retarget.c
+extern "C" void *__wrap__sbrk(int incr);
+extern "C" caddr_t _sbrk(int incr) {
+    return (caddr_t) __wrap__sbrk(incr);
+}
+#else
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" uint32_t __end__;
+extern "C" caddr_t _sbrk(int incr) {
+    static unsigned char* heap = (unsigned char*)&__end__;
+    unsigned char*        prev_heap = heap;
+    unsigned char*        new_heap = heap + incr;
+
+#if defined(TARGET_CORTEX_A)
+    if (new_heap >= (unsigned char*)&__HeapLimit) {     /* __HeapLimit is end of heap section */
+#else
+    if (new_heap >= (unsigned char*)__get_MSP()) {
+#endif
+        errno = ENOMEM;
+        return (caddr_t)-1;
+    }
+
+    // Additional heap checking if set
+    if (mbed_heap_size && (new_heap >= mbed_heap_start + mbed_heap_size)) {
+        errno = ENOMEM;
+        return (caddr_t)-1;
+    }
+
+    heap = new_heap;
+    return (caddr_t) prev_heap;
+}
+#endif
+#endif
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+extern "C" void _exit(int return_code) {
+#else
+namespace std {
+extern "C" void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#if MBED_CONF_PLATFORM_STDIO_FLUSH_AT_EXIT
+    fflush(stdout);
+    fflush(stderr);
+#endif
+#endif
+
+#if DEVICE_SEMIHOST
+    if (mbed_interface_connected()) {
+        semihost_exit();
+    }
+#endif
+    if (return_code) {
+        mbed_die();
+    }
+
+    while (1);
+}
+
+#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CR)
+} //namespace std
+#endif
+
+#if defined(TOOLCHAIN_ARM) || defined(TOOLCHAIN_GCC)
+
+// This series of function disable the registration of global destructors
+// in a dynamic table which will be called when the application exit.
+// In mbed, program never exit properly, it dies.
+// More informations about this topic for ARMCC here:
+// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/6449.html
+extern "C" {
+int __aeabi_atexit(void *object, void (*dtor)(void* /*this*/), void *handle) {
+    return 1;
+}
+
+int __cxa_atexit(void (*dtor)(void* /*this*/), void *object, void *handle) {
+    return 1;
+}
+
+void __cxa_finalize(void *handle) {
+}
+
+} // end of extern "C"
+
+#endif
+
+
+#if defined(TOOLCHAIN_GCC)
+
+/*
+ * Depending on how newlib is  configured, it is often not enough to define
+ * __aeabi_atexit, __cxa_atexit and __cxa_finalize in order to override the
+ * behavior regarding the registration of handlers with atexit.
+ *
+ * To overcome this limitation, exit and atexit are overriden here.
+ */
+extern "C"{
+
+/**
+ * @brief Retarget of exit for GCC.
+ * @details Unlike the standard version, this function doesn't call any function
+ * registered with atexit before calling _exit.
+ */
+void __wrap_exit(int return_code) {
+    _exit(return_code);
+}
+
+/**
+ * @brief Retarget atexit from GCC.
+ * @details This function will always fail and never register any handler to be
+ * called at exit.
+ */
+int __wrap_atexit(void (*func)()) {
+    return 1;
+}
+
+}
+
+#endif
+
+
+
+namespace mbed {
+
+void mbed_set_unbuffered_stream(std::FILE *_file) {
+#if defined (__ICCARM__)
+    char buf[2];
+    std::setvbuf(_file,buf,_IONBF,NULL);
+#else
+    setbuf(_file, NULL);
+#endif
+}
+
+/* Applications are expected to use fdopen()
+ * not this function directly. This code had to live here because FILE and FileHandle
+ * processes are all linked together here.
+ */
+std::FILE *mbed_fdopen(FileHandle *fh, const char *mode)
+{
+    // This is to avoid scanf(buf, ":%.4s", fh) and the bloat it brings.
+    char buf[1 + sizeof(fh)]; /* :(pointer) */
+    MBED_STATIC_ASSERT(sizeof(buf) == 5, "Pointers should be 4 bytes.");
+    buf[0] = ':';
+    memcpy(buf + 1, &fh, sizeof(fh));
+
+    std::FILE *stream = std::fopen(buf, mode);
+    /* newlib-nano doesn't appear to ever call _isatty itself, so
+     * happily fully buffers an interactive stream. Deal with that here.
+     */
+    if (stream && fh->isatty()) {
+        mbed_set_unbuffered_stream(stream);
+    }
+    return stream;
+}
+
+int mbed_getc(std::FILE *_file){
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ < 8000000)
+    /*This is only valid for unbuffered streams*/
+    int res = std::fgetc(_file);
+    if (res>=0){
+        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+        _file->_Rend = _file->_Wend;
+        _file->_Next = _file->_Wend;
+    }
+    return res;
+#else
+    return std::fgetc(_file);
+#endif
+}
+
+char* mbed_gets(char*s, int size, std::FILE *_file){
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ < 8000000)
+    /*This is only valid for unbuffered streams*/
+    char *str = fgets(s,size,_file);
+    if (str!=NULL){
+        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+        _file->_Rend = _file->_Wend;
+        _file->_Next = _file->_Wend;
+    }
+    return str;
+#else
+    return std::fgets(s,size,_file);
+#endif
+}
+
+} // namespace mbed
+
+#if defined (__ICCARM__)
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __iar_system_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxunlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {}
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
+extern "C" WEAK void *__aeabi_read_tp (void) { return NULL ;}
+#endif
+#elif defined(__CC_ARM)
+// Do nothing
+#elif defined (__GNUC__)
+struct _reent;
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __rtos_malloc_lock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_malloc_unlock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_env_lock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_env_unlock( struct _reent *_r ) {}
+
+extern "C" void __malloc_lock( struct _reent *_r )
+{
+    __rtos_malloc_lock(_r);
+}
+
+extern "C" void __malloc_unlock( struct _reent *_r )
+{
+    __rtos_malloc_unlock(_r);
+}
+
+extern "C" void __env_lock( struct _reent *_r )
+{
+    __rtos_env_lock(_r);
+}
+
+extern "C" void __env_unlock( struct _reent *_r )
+{
+    __rtos_env_unlock(_r);
+}
+
+#define CXA_GUARD_INIT_DONE             (1 << 0)
+#define CXA_GUARD_INIT_IN_PROGRESS      (1 << 1)
+#define CXA_GUARD_MASK                  (CXA_GUARD_INIT_DONE | CXA_GUARD_INIT_IN_PROGRESS)
+
+extern "C" int __cxa_guard_acquire(int *guard_object_p)
+{
+    uint8_t *guard_object = (uint8_t *)guard_object_p;
+    if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+        return 0;
+    }
+    singleton_lock();
+    if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+        singleton_unlock();
+        return 0;
+    }
+    MBED_ASSERT(0 == (*guard_object & CXA_GUARD_MASK));
+    *guard_object = *guard_object | CXA_GUARD_INIT_IN_PROGRESS;
+    return 1;
+}
+
+extern "C" void __cxa_guard_release(int *guard_object_p)
+{
+    uint8_t *guard_object = (uint8_t *)guard_object_p;
+    MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+    *guard_object = (*guard_object & ~CXA_GUARD_MASK) | CXA_GUARD_INIT_DONE;
+    singleton_unlock();
+}
+
+extern "C" void __cxa_guard_abort(int *guard_object_p)
+{
+    uint8_t *guard_object = (uint8_t *)guard_object_p;
+    MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+    *guard_object = *guard_object & ~CXA_GUARD_INIT_IN_PROGRESS;
+    singleton_unlock();
+}
+
+#endif
+
+void *operator new(std::size_t count)
+{
+    void *buffer = malloc(count);
+    if (NULL == buffer) {
+        error("Operator new out of memory\r\n");
+    }
+    return buffer;
+}
+
+void *operator new[](std::size_t count)
+{
+    void *buffer = malloc(count);
+    if (NULL == buffer) {
+        error("Operator new[] out of memory\r\n");
+    }
+    return buffer;
+}
+
+void *operator new(std::size_t count, const std::nothrow_t& tag)
+{
+    return malloc(count);
+}
+
+void *operator new[](std::size_t count, const std::nothrow_t& tag)
+{
+    return malloc(count);
+}
+
+void operator delete(void *ptr)
+{
+    if (ptr != NULL) {
+        free(ptr);
+    }
+}
+void operator delete[](void *ptr)
+{
+    if (ptr != NULL) {
+        free(ptr);
+    }
+}
+
+/* @brief   standard c library clock() function.
+ *
+ * This function returns the number of clock ticks elapsed since the start of the program.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @return
+ *  the number of clock ticks elapsed since the start of the program.
+ *
+ * */
+extern "C" clock_t clock()
+{
+    _mutex->lock();
+    clock_t t = ticker_read(get_us_ticker_data());
+    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+    _mutex->unlock();
+    return t;
+}
+
+// temporary - Default to 1MHz at 32 bits if target does not have us_ticker_get_info
+MBED_WEAK const ticker_info_t* us_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        1000000,
+        32
+    };
+    return &info;
+}
+
+// temporary - Default to 1MHz at 32 bits if target does not have lp_ticker_get_info
+MBED_WEAK const ticker_info_t* lp_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        1000000,
+        32
+    };
+    return &info;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_retarget.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_retarget.h
new file mode 100755
index 0000000..a12abc2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_retarget.h
@@ -0,0 +1,441 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef RETARGET_H
+#define RETARGET_H
+
+#if __cplusplus
+#include <cstdio>
+#endif //__cplusplus
+#include <stdint.h>
+#include <stddef.h>
+
+/* We can get the following standard types from sys/types for gcc, but we
+ * need to define the types ourselves for the other compilers that normally
+ * target embedded systems */
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef signed   int  ssize_t;  ///< Signed size type, usually encodes negative errors
+typedef signed   long off_t;    ///< Offset in a data stream
+typedef unsigned int  mode_t;   ///< Mode for opening files
+typedef unsigned int  dev_t;    ///< Device ID type
+typedef unsigned long ino_t;    ///< File serial number
+typedef unsigned int  nlink_t;  ///< Number of links to a file
+typedef unsigned int  uid_t;    ///< User ID
+typedef unsigned int  gid_t;    ///< Group ID
+
+#define O_RDONLY 0      ///< Open for reading
+#define O_WRONLY 1      ///< Open for writing
+#define O_RDWR   2      ///< Open for reading and writing
+#define O_CREAT  0x0200 ///< Create file if it does not exist
+#define O_TRUNC  0x0400 ///< Truncate file to zero length
+#define O_EXCL   0x0800 ///< Fail if file exists
+#define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write
+
+#define NAME_MAX 255    ///< Maximum size of a name in a file path
+
+#include <time.h>
+
+#else
+
+#include <sys/fcntl.h>
+#include <sys/types.h>
+#include <sys/syslimits.h>
+
+#endif
+
+
+/* DIR declarations must also be here */
+#if __cplusplus
+namespace mbed {
+class FileHandle;
+class DirHandle;
+std::FILE *mbed_fdopen(FileHandle *fh, const char *mode);
+}
+typedef mbed::DirHandle DIR;
+#else
+typedef struct Dir DIR;
+#endif
+
+#if __cplusplus
+extern "C" {
+#endif
+    DIR *opendir(const char*);
+    struct dirent *readdir(DIR *);
+    int closedir(DIR*);
+    void rewinddir(DIR*);
+    long telldir(DIR*);
+    void seekdir(DIR*, long);
+    int mkdir(const char *name, mode_t n);
+#if __cplusplus
+};
+#endif
+
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+/* The intent of this section is to unify the errno error values to match
+ * the POSIX definitions for the GCC_ARM, ARMCC and IAR compilers. This is
+ * necessary because the ARMCC/IAR errno.h, or sys/stat.h are missing some
+ * symbol definitions used by the POSIX filesystem API to return errno codes.
+ * Note also that ARMCC errno.h defines some symbol values differently from
+ * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against
+ * this and future changes by changing the symbol definition as shown below.
+ */
+#undef  EPERM
+#define EPERM           1       /* Operation not permitted */
+#undef  ENOENT
+#define ENOENT          2       /* No such file or directory */
+#undef  ESRCH
+#define ESRCH           3       /* No such process */
+#undef  EINTR
+#define EINTR           4       /* Interrupted system call */
+#undef  EIO
+#define EIO             5       /* I/O error */
+#undef  ENXIO
+#define ENXIO           6       /* No such device or address */
+#undef  E2BIG
+#define E2BIG           7       /* Argument list too long */
+#undef  ENOEXEC
+#define ENOEXEC         8       /* Exec format error */
+#undef  EBADF
+#define EBADF           9       /* Bad file number */
+#undef  ECHILD
+#define ECHILD          10      /* No child processes */
+#undef  EAGAIN
+#define EAGAIN          11      /* Try again */
+#undef  ENOMEM
+#define ENOMEM          12      /* Out of memory */
+#undef  EACCES
+#define EACCES          13      /* Permission denied */
+#undef  EFAULT
+#define EFAULT          14      /* Bad address */
+#undef  ENOTBLK
+#define ENOTBLK         15      /* Block device required */
+#undef  EBUSY
+#define EBUSY           16      /* Device or resource busy */
+#undef  EEXIST
+#define EEXIST          17      /* File exists */
+#undef  EXDEV
+#define EXDEV           18      /* Cross-device link */
+#undef  ENODEV
+#define ENODEV          19      /* No such device */
+#undef  ENOTDIR
+#define ENOTDIR         20      /* Not a directory */
+#undef  EISDIR
+#define EISDIR          21      /* Is a directory */
+#undef  EINVAL
+#define EINVAL          22      /* Invalid argument */
+#undef  ENFILE
+#define ENFILE          23      /* File table overflow */
+#undef  EMFILE
+#define EMFILE          24      /* Too many open files */
+#undef  ENOTTY
+#define ENOTTY          25      /* Not a typewriter */
+#undef  ETXTBSY
+#define ETXTBSY         26      /* Text file busy */
+#undef  EFBIG
+#define EFBIG           27      /* File too large */
+#undef  ENOSPC
+#define ENOSPC          28      /* No space left on device */
+#undef  ESPIPE
+#define ESPIPE          29      /* Illegal seek */
+#undef  EROFS
+#define EROFS           30      /* Read-only file system */
+#undef  EMLINK
+#define EMLINK          31      /* Too many links */
+#undef  EPIPE
+#define EPIPE           32      /* Broken pipe */
+#undef  EDOM
+#define EDOM            33      /* Math argument out of domain of func */
+#undef  ERANGE
+#define ERANGE          34      /* Math result not representable */
+#undef  EDEADLK
+#define EDEADLK         35      /* Resource deadlock would occur */
+#undef  ENAMETOOLONG
+#define ENAMETOOLONG    36      /* File name too long */
+#undef  ENOLCK
+#define ENOLCK          37      /* No record locks available */
+#undef  ENOSYS
+#define ENOSYS          38      /* Function not implemented */
+#undef  ENOTEMPTY
+#define ENOTEMPTY       39      /* Directory not empty */
+#undef  ELOOP
+#define ELOOP           40      /* Too many symbolic links encountered */
+#undef  EWOULDBLOCK
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#undef  ENOMSG
+#define ENOMSG          42      /* No message of desired type */
+#undef  EIDRM
+#define EIDRM           43      /* Identifier removed */
+#undef  ECHRNG
+#define ECHRNG          44      /* Channel number out of range */
+#undef  EL2NSYNC
+#define EL2NSYNC        45      /* Level 2 not synchronized */
+#undef  EL3HLT
+#define EL3HLT          46      /* Level 3 halted */
+#undef  EL3RST
+#define EL3RST          47      /* Level 3 reset */
+#undef  ELNRNG
+#define ELNRNG          48      /* Link number out of range */
+#undef  EUNATCH
+#define EUNATCH         49      /* Protocol driver not attached */
+#undef  ENOCSI
+#define ENOCSI          50      /* No CSI structure available */
+#undef  EL2HLT
+#define EL2HLT          51      /* Level 2 halted */
+#undef  EBADE
+#define EBADE           52      /* Invalid exchange */
+#undef  EBADR
+#define EBADR           53      /* Invalid request descriptor */
+#undef  EXFULL
+#define EXFULL          54      /* Exchange full */
+#undef  ENOANO
+#define ENOANO          55      /* No anode */
+#undef  EBADRQC
+#define EBADRQC         56      /* Invalid request code */
+#undef  EBADSLT
+#define EBADSLT         57      /* Invalid slot */
+#undef  EDEADLOCK
+#define EDEADLOCK       EDEADLK /* Resource deadlock would occur */
+#undef  EBFONT
+#define EBFONT          59      /* Bad font file format */
+#undef  ENOSTR
+#define ENOSTR          60      /* Device not a stream */
+#undef  ENODATA
+#define ENODATA         61      /* No data available */
+#undef  ETIME
+#define ETIME           62      /* Timer expired */
+#undef  ENOSR
+#define ENOSR           63      /* Out of streams resources */
+#undef  ENONET
+#define ENONET          64      /* Machine is not on the network */
+#undef  ENOPKG
+#define ENOPKG          65      /* Package not installed */
+#undef  EREMOTE
+#define EREMOTE         66      /* Object is remote */
+#undef  ENOLINK
+#define ENOLINK         67      /* Link has been severed */
+#undef  EADV
+#define EADV            68      /* Advertise error */
+#undef  ESRMNT
+#define ESRMNT          69      /* Srmount error */
+#undef  ECOMM
+#define ECOMM           70      /* Communication error on send */
+#undef  EPROTO
+#define EPROTO          71      /* Protocol error */
+#undef  EMULTIHOP
+#define EMULTIHOP       72      /* Multihop attempted */
+#undef  EDOTDOT
+#define EDOTDOT         73      /* RFS specific error */
+#undef  EBADMSG
+#define EBADMSG         74      /* Not a data message */
+#undef  EOVERFLOW
+#define EOVERFLOW       75      /* Value too large for defined data type */
+#undef  ENOTUNIQ
+#define ENOTUNIQ        76      /* Name not unique on network */
+#undef  EBADFD
+#define EBADFD          77      /* File descriptor in bad state */
+#undef  EREMCHG
+#define EREMCHG         78      /* Remote address changed */
+#undef  ELIBACC
+#define ELIBACC         79      /* Can not access a needed shared library */
+#undef  ELIBBAD
+#define ELIBBAD         80      /* Accessing a corrupted shared library */
+#undef  ELIBSCN
+#define ELIBSCN         81      /* .lib section in a.out corrupted */
+#undef  ELIBMAX
+#define ELIBMAX         82      /* Attempting to link in too many shared libraries */
+#undef  ELIBEXEC
+#define ELIBEXEC        83      /* Cannot exec a shared library directly */
+#undef  EILSEQ
+#define EILSEQ          84      /* Illegal byte sequence */
+#undef  ERESTART
+#define ERESTART        85      /* Interrupted system call should be restarted */
+#undef  ESTRPIPE
+#define ESTRPIPE        86      /* Streams pipe error */
+#undef  EUSERS
+#define EUSERS          87      /* Too many users */
+#undef  ENOTSOCK
+#define ENOTSOCK        88      /* Socket operation on non-socket */
+#undef  EDESTADDRREQ
+#define EDESTADDRREQ    89      /* Destination address required */
+#undef  EMSGSIZE
+#define EMSGSIZE        90      /* Message too long */
+#undef  EPROTOTYPE
+#define EPROTOTYPE      91      /* Protocol wrong type for socket */
+#undef  ENOPROTOOPT
+#define ENOPROTOOPT     92      /* Protocol not available */
+#undef  EPROTONOSUPPORT
+#define EPROTONOSUPPORT 93      /* Protocol not supported */
+#undef  ESOCKTNOSUPPORT
+#define ESOCKTNOSUPPORT 94      /* Socket type not supported */
+#undef  EOPNOTSUPP
+#define EOPNOTSUPP      95      /* Operation not supported on transport endpoint */
+#undef  EPFNOSUPPORT
+#define EPFNOSUPPORT    96      /* Protocol family not supported */
+#undef  EAFNOSUPPORT
+#define EAFNOSUPPORT    97      /* Address family not supported by protocol */
+#undef  EADDRINUSE
+#define EADDRINUSE      98      /* Address already in use */
+#undef  EADDRNOTAVAIL
+#define EADDRNOTAVAIL   99      /* Cannot assign requested address */
+#undef  ENETDOWN
+#define ENETDOWN        100     /* Network is down */
+#undef  ENETUNREACH
+#define ENETUNREACH     101     /* Network is unreachable */
+#undef  ENETRESET
+#define ENETRESET       102     /* Network dropped connection because of reset */
+#undef  ECONNABORTED
+#define ECONNABORTED    103     /* Software caused connection abort */
+#undef  ECONNRESET
+#define ECONNRESET      104     /* Connection reset by peer */
+#undef  ENOBUFS
+#define ENOBUFS         105     /* No buffer space available */
+#undef  EISCONN
+#define EISCONN         106     /* Transport endpoint is already connected */
+#undef  ENOTCONN
+#define ENOTCONN        107     /* Transport endpoint is not connected */
+#undef  ESHUTDOWN
+#define ESHUTDOWN       108     /* Cannot send after transport endpoint shutdown */
+#undef  ETOOMANYREFS
+#define ETOOMANYREFS    109     /* Too many references: cannot splice */
+#undef  ETIMEDOUT
+#define ETIMEDOUT       110     /* Connection timed out */
+#undef  ECONNREFUSED
+#define ECONNREFUSED    111     /* Connection refused */
+#undef  EHOSTDOWN
+#define EHOSTDOWN       112     /* Host is down */
+#undef  EHOSTUNREACH
+#define EHOSTUNREACH    113     /* No route to host */
+#undef  EALREADY
+#define EALREADY        114     /* Operation already in progress */
+#undef  EINPROGRESS
+#define EINPROGRESS     115     /* Operation now in progress */
+#undef  ESTALE
+#define ESTALE          116     /* Stale NFS file handle */
+#undef  EUCLEAN
+#define EUCLEAN         117     /* Structure needs cleaning */
+#undef  ENOTNAM
+#define ENOTNAM         118     /* Not a XENIX named type file */
+#undef  ENAVAIL
+#define ENAVAIL         119     /* No XENIX semaphores available */
+#undef  EISNAM
+#define EISNAM          120     /* Is a named type file */
+#undef  EREMOTEIO
+#define EREMOTEIO       121     /* Remote I/O error */
+#undef  EDQUOT
+#define EDQUOT          122     /* Quota exceeded */
+#undef  ENOMEDIUM
+#define ENOMEDIUM       123     /* No medium found */
+#undef  EMEDIUMTYPE
+#define EMEDIUMTYPE     124     /* Wrong medium type */
+#undef  ECANCELED
+#define ECANCELED       125     /* Operation Canceled */
+#undef  ENOKEY
+#define ENOKEY          126     /* Required key not available */
+#undef  EKEYEXPIRED
+#define EKEYEXPIRED     127     /* Key has expired */
+#undef  EKEYREVOKED
+#define EKEYREVOKED     128     /* Key has been revoked */
+#undef  EKEYREJECTED
+#define EKEYREJECTED    129     /* Key was rejected by service */
+#undef  EOWNERDEAD
+#define EOWNERDEAD      130     /* Owner died */
+#undef  ENOTRECOVERABLE
+#define ENOTRECOVERABLE 131     /* State not recoverable */
+#endif
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+/* Missing stat.h defines.
+ * The following are sys/stat.h definitions not currently present in the ARMCC
+ * errno.h. Note, ARMCC errno.h defines some symbol values differing from
+ * GCC_ARM/IAR/standard POSIX definitions. Guard against this and future
+ * changes by changing the symbol definition for filesystem use.
+ */
+#define     _IFMT   0170000 //< type of file
+#define     _IFSOCK 0140000 //< socket
+#define     _IFLNK  0120000 //< symbolic link
+#define     _IFREG  0100000 //< regular
+#define     _IFBLK  0060000 //< block special
+#define     _IFDIR  0040000 //< directory
+#define     _IFCHR  0020000 //< character special
+#define     _IFIFO  0010000 //< fifo special
+
+#define S_IFMT      _IFMT   //< type of file
+#define S_IFSOCK    _IFSOCK //< socket
+#define S_IFLNK     _IFLNK  //< symbolic link
+#define S_IFREG     _IFREG  //< regular
+#define S_IFBLK     _IFBLK  //< block special
+#define S_IFDIR     _IFDIR  //< directory
+#define S_IFCHR     _IFCHR  //< character special
+#define S_IFIFO     _IFIFO  //< fifo special
+
+#define S_IRWXU     (S_IRUSR | S_IWUSR | S_IXUSR)
+#define     S_IRUSR 0000400 ///< read permission, owner
+#define     S_IWUSR 0000200 ///< write permission, owner
+#define     S_IXUSR 0000100 ///< execute/search permission, owner
+#define S_IRWXG     (S_IRGRP | S_IWGRP | S_IXGRP)
+#define     S_IRGRP 0000040 ///< read permission, group
+#define     S_IWGRP 0000020 ///< write permission, grougroup
+#define     S_IXGRP 0000010 ///< execute/search permission, group
+#define S_IRWXO     (S_IROTH | S_IWOTH | S_IXOTH)
+#define     S_IROTH 0000004 ///< read permission, other
+#define     S_IWOTH 0000002 ///< write permission, other
+#define     S_IXOTH 0000001 ///< execute/search permission, other
+
+/* Refer to sys/stat standard
+ * Note: Not all fields may be supported by the underlying filesystem
+ */
+struct stat {
+    dev_t     st_dev;     ///< Device ID containing file
+    ino_t     st_ino;     ///< File serial number
+    mode_t    st_mode;    ///< Mode of file
+    nlink_t   st_nlink;   ///< Number of links to file
+
+    uid_t     st_uid;     ///< User ID
+    gid_t     st_gid;     ///< Group ID
+
+    off_t     st_size;    ///< Size of file in bytes
+
+    time_t    st_atime;   ///< Time of last access
+    time_t    st_mtime;   ///< Time of last data modification
+    time_t    st_ctime;   ///< Time of last status change
+};
+
+#endif /* defined(__ARMCC_VERSION) || defined(__ICCARM__) */
+
+
+/* The following are dirent.h definitions are declared here to garuntee
+ * consistency where structure may be different with different toolchains
+ */
+struct dirent {
+    char d_name[NAME_MAX+1]; ///< Name of file
+    uint8_t d_type;          ///< Type of file
+};
+
+enum {
+    DT_UNKNOWN, ///< The file type could not be determined.
+    DT_FIFO,    ///< This is a named pipe (FIFO).
+    DT_CHR,     ///< This is a character device.
+    DT_DIR,     ///< This is a directory.
+    DT_BLK,     ///< This is a block device.
+    DT_REG,     ///< This is a regular file.
+    DT_LNK,     ///< This is a symbolic link.
+    DT_SOCK,    ///< This is a UNIX domain socket.
+};
+
+#endif /* RETARGET_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_rtc_time.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_rtc_time.cpp
new file mode 100755
index 0000000..b77e2ef
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_rtc_time.cpp
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/rtc_api.h"
+
+#include "platform/mbed_critical.h"
+#include "platform/mbed_rtc_time.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+static SingletonPtr<PlatformMutex> _mutex;
+
+#if DEVICE_RTC
+static void (*_rtc_init)(void) = rtc_init;
+static int (*_rtc_isenabled)(void) = rtc_isenabled;
+static time_t (*_rtc_read)(void) = rtc_read;
+static void (*_rtc_write)(time_t t) = rtc_write;
+#else
+static void (*_rtc_init)(void) = NULL;
+static int (*_rtc_isenabled)(void) = NULL;
+static time_t (*_rtc_read)(void) = NULL;
+static void (*_rtc_write)(time_t t) = NULL;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+    _mutex->lock();
+    if (_rtc_isenabled != NULL) {
+        if (!(_rtc_isenabled())) {
+            set_time(0);
+        }
+    }
+    
+    time_t t = (time_t)-1;
+    if (_rtc_read != NULL) {
+        t = _rtc_read();
+    }
+
+    if (timer != NULL) {
+        *timer = t;
+    }
+    _mutex->unlock();
+    return t;
+}
+
+void set_time(time_t t) {
+    _mutex->lock();
+    if (_rtc_init != NULL) {
+        _rtc_init();
+    }
+    if (_rtc_write != NULL) {
+        _rtc_write(t);
+    }
+    _mutex->unlock();
+}
+
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
+    _mutex->lock();
+    _rtc_read = read_rtc;
+    _rtc_write = write_rtc;
+    _rtc_init = init_rtc;
+    _rtc_isenabled = isenabled_rtc;
+    _mutex->unlock();
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_rtc_time.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_rtc_time.h
new file mode 100755
index 0000000..84a3739
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_rtc_time.h
@@ -0,0 +1,92 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ *     while(1) {
+ *         time_t seconds = time(NULL);
+ *
+ *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ *         printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ *         char buffer[32];
+ *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ *         printf("Time as a custom formatted string = %s", buffer);
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+/** Attach an external RTC to be used for the C time functions
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @param read_rtc pointer to function which returns current UNIX timestamp
+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ */
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_sdk_boot.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_sdk_boot.c
new file mode 100755
index 0000000..4799e2c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_sdk_boot.c
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_toolchain.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include "cmsis.h"
+
+/* This startup is for mbed 2 baremetal. There is no config for RTOS for mbed 2,
+ * therefore we protect this file with MBED_CONF_RTOS_PRESENT
+ * Note: The new consolidated started for mbed OS is in rtos/mbed_boot code file.
+ */
+#if !defined(MBED_CONF_RTOS_PRESENT)
+
+/* mbed_main is a function that is called before main()
+ * mbed_sdk_init() is also a function that is called before main(), but unlike
+ * mbed_main(), it is not meant for user code, but for the SDK itself to perform
+ * initializations before main() is called.
+ */
+MBED_WEAK void mbed_main(void) 
+{
+
+}
+
+/* This function can be implemented by the target to perform higher level target initialization
+ */
+MBED_WEAK void mbed_sdk_init(void) 
+{
+
+}
+
+MBED_WEAK void software_init_hook_rtos()
+{
+    // Nothing by default
+}
+
+void mbed_copy_nvic(void)
+{
+    /* If vector address in RAM is defined, copy and switch to dynamic vectors. Exceptions for M0 which doesn't have
+    VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
+    responsible for correctly handling the vectors.
+    */
+#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9)
+#ifdef NVIC_RAM_VECTOR_ADDRESS
+    uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
+    uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+    for (int i = 0; i < NVIC_NUM_VECTORS; i++) {
+        vectors[i] = old_vectors[i];
+    }
+    SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+#endif /* NVIC_RAM_VECTOR_ADDRESS */
+#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */
+}
+
+/* Toolchain specific main code */
+
+#if defined (__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 5010060))
+
+int $Super$$main(void);
+
+int $Sub$$main(void) 
+{
+    mbed_main();
+    return $Super$$main();
+}
+
+void _platform_post_stackheap_init(void) 
+{
+    mbed_copy_nvic();
+    mbed_sdk_init();
+}
+
+#elif defined (__GNUC__) 
+
+extern int __real_main(void);
+
+void software_init_hook(void)
+{
+    mbed_copy_nvic();
+    mbed_sdk_init();
+    software_init_hook_rtos();
+}
+
+
+int __wrap_main(void) 
+{
+    mbed_main();
+    return __real_main();
+}
+
+#elif defined (__ICCARM__)
+
+int __low_level_init(void)
+{
+  mbed_copy_nvic();
+  return 1;
+}
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_semihost_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_semihost_api.c
new file mode 100755
index 0000000..06c6777
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_semihost_api.c
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "platform/mbed_semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN   (0x1)
+#define SYS_CLOSE  (0x2)
+#define SYS_WRITE  (0x5)
+#define SYS_READ   (0x6)
+#define SYS_ISTTY  (0x9)
+#define SYS_SEEK   (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN   (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT   (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND      (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID      (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET     (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS     (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN     (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)openmode;
+    args[2] = (uint32_t)strlen(name);
+    return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh) {
+    return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
+    if (length == 0) return 0;
+
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh) {
+    return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position) {
+    uint32_t args[2];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)position;
+    return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh) {
+    return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh) {
+    return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name) {
+    uint32_t args[2];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)strlen(name);
+    return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name) {
+    uint32_t args[4];
+    args[0] = (uint32_t)old_name;
+    args[1] = (uint32_t)strlen(old_name);
+    args[0] = (uint32_t)new_name;
+    args[1] = (uint32_t)strlen(new_name);
+    return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void) {
+    uint32_t args[4];
+    return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid) {
+    uint32_t args[2];
+    args[0] = (uint32_t)uid;
+    args[1] = DEVICE_ID_LENGTH + 1;
+    return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void) {
+    // Does not normally return, however if used with older firmware versions
+    // that do not support this call it will return -1.
+    return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void) {
+    return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void) {
+    return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void) {
+    return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void) {
+    return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void) {
+    uint32_t args[1];
+#if !(DEVICE_DEBUG_AWARENESS)
+    is_debugger_attached = 0;
+#endif
+    return __semihost(USR_DISABLEDEBUG, &args);
+}
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_semihost_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_semihost_api.h
new file mode 100755
index 0000000..9127c5f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_semihost_api.h
@@ -0,0 +1,98 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "platform/mbed_toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#if !defined(__CC_ARM) && !defined(__ARMCC_VERSION)
+
+#if defined(__ICCARM__)
+static inline int __semihost(int reason, const void *arg) {
+    return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+#   define AngelSWI            0xAB
+#   define AngelSWIInsn        "bkpt"
+#   define AngelSWIAsm          bkpt
+#else
+#   define AngelSWI            0x123456
+#   define AngelSWIInsn        "swi"
+#   define AngelSWIAsm          swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+    int value;
+
+    asm volatile (
+       "mov r0, %1"          "\n\t"
+       "mov r1, %2"          "\n\t"
+       AngelSWIInsn " %a3"   "\n\t"
+       "mov %0, r0"
+       : "=r" (value)                                         /* output operands             */
+       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
+       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
+    );
+
+    return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek  (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_sleep.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_sleep.h
new file mode 100755
index 0000000..4f635d4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_sleep.h
@@ -0,0 +1,171 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_H
+#define MBED_SLEEP_H
+
+#include "sleep_api.h"
+#include "mbed_toolchain.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Sleep manager API
+ * The sleep manager provides API to automatically select sleep mode.
+ *
+ * There are two sleep modes:
+ * - sleep
+ * - deepsleep
+ *
+ * Use locking/unlocking deepsleep for drivers that depend on features that
+ * are not allowed (=disabled) during the deepsleep. For instance, high frequency
+ * clocks.
+ *
+ * Example:
+ * @code
+ *
+ * void driver::handler()
+ * {
+ *     if (_sensor.get_event()) {
+ *         // any event - we are finished, unlock the deepsleep
+ *         sleep_manager_unlock_deep_sleep();
+ *         _callback();
+ *     }
+ * }
+ *
+ * int driver::measure(event_t event, callback_t& callback)
+ * {
+ *      _callback = callback;
+ *      sleep_manager_lock_deep_sleep();
+ *      // start async transaction, we are waiting for an event
+ *      return _sensor.start(event, callback);
+ * }
+ * @endcode
+ */
+
+/** Lock the deep sleep mode
+ *
+ * This locks the automatic deep mode selection.
+ * sleep_manager_sleep_auto() will ignore deepsleep mode if
+ * this function is invoked at least once (the internal counter is non-zero)
+ *
+ * Use this locking mechanism for interrupt driven API that are
+ * running in the background and deepsleep could affect their functionality
+ *
+ * The lock is a counter, can be locked up to USHRT_MAX
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_lock_deep_sleep(void);
+
+/** Unlock the deep sleep mode
+ *
+ * Use unlocking in pair with sleep_manager_lock_deep_sleep().
+ *
+ * The lock is a counter, should be equally unlocked as locked
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_unlock_deep_sleep(void);
+
+/** Get the status of deep sleep allowance for a target
+ *
+ * @return true if a target can go to deepsleep, false otherwise
+ */
+bool sleep_manager_can_deep_sleep(void);
+
+/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based
+ *  on the deepsleep locking counter
+ *
+ * This function is IRQ and thread safe
+ *
+ * @note
+ * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
+ * to be active for debug modes.
+ *
+ */
+void sleep_manager_sleep_auto(void);
+
+/** Send the microcontroller to sleep
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
+ * @note This function will be a noop while uVisor is in use.
+ * @note This function will be a noop if the following conditions are met:
+ *   - The RTOS is present
+ *   - The processor turn off the Systick clock during sleep
+ *   - The target does not implement tickless mode
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+__INLINE static void sleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#if DEVICE_SLEEP
+#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
+    sleep_manager_sleep_auto();
+#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
+#endif /* DEVICE_SLEEP */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+/** Send the microcontroller to deep sleep
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
+ * @note This function will be a noop while uVisor is in use.
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep. This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+
+MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
+__INLINE static void deepsleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#if DEVICE_SLEEP
+    sleep_manager_sleep_auto();
+#endif /* DEVICE_SLEEP */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_stats.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_stats.c
new file mode 100755
index 0000000..106394b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_stats.c
@@ -0,0 +1,70 @@
+#include "mbed_stats.h"
+#include <string.h>
+#include <stdlib.h>
+#include "mbed_assert.h"
+
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os2.h"
+#endif
+
+// note: mbed_stats_heap_get defined in mbed_alloc_wrappers.cpp
+
+void mbed_stats_stack_get(mbed_stats_stack_t *stats)
+{
+    memset(stats, 0, sizeof(mbed_stats_stack_t));
+
+#if MBED_STACK_STATS_ENABLED && MBED_CONF_RTOS_PRESENT
+    uint32_t thread_n = osThreadGetCount();
+    unsigned i;
+    osThreadId_t *threads;
+
+    threads = malloc(sizeof(osThreadId_t) * thread_n);
+    MBED_ASSERT(threads != NULL);
+
+    osKernelLock();
+    thread_n = osThreadEnumerate(threads, thread_n);
+
+    for(i = 0; i < thread_n; i++) {
+        uint32_t stack_size = osThreadGetStackSize(threads[i]);
+        stats->max_size += stack_size - osThreadGetStackSpace(threads[i]);
+        stats->reserved_size += stack_size;
+        stats->stack_cnt++;
+    }
+    osKernelUnlock();
+
+    free(threads);
+#endif
+}
+
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count)
+{
+    memset(stats, 0, count*sizeof(mbed_stats_stack_t));
+    size_t i = 0;
+
+#if MBED_STACK_STATS_ENABLED && MBED_CONF_RTOS_PRESENT
+    osThreadId_t *threads;
+
+    threads = malloc(sizeof(osThreadId_t) * count);
+    MBED_ASSERT(threads != NULL);
+
+    osKernelLock();
+    count = osThreadEnumerate(threads, count);
+
+    for(i = 0; i < count; i++) {
+        uint32_t stack_size = osThreadGetStackSize(threads[i]);
+        stats[i].max_size = stack_size - osThreadGetStackSpace(threads[i]);
+        stats[i].reserved_size = stack_size;
+        stats[i].thread_id = (uint32_t)threads[i];
+        stats[i].stack_cnt = 1;
+    }
+    osKernelUnlock();
+
+    free(threads);
+#endif
+
+    return i;
+}
+
+#if MBED_STACK_STATS_ENABLED && !MBED_CONF_RTOS_PRESENT
+#warning Stack statistics are currently not supported without the rtos.
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_stats.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_stats.h
new file mode 100755
index 0000000..99662af
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_stats.h
@@ -0,0 +1,75 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STATS_H
+#define MBED_STATS_H
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t current_size;      /**< Bytes allocated currently. */
+    uint32_t max_size;          /**< Max bytes allocated at a given time. */
+    uint32_t total_size;        /**< Cumulative sum of bytes ever allocated. */
+    uint32_t reserved_size;     /**< Current number of bytes allocated for the heap. */
+    uint32_t alloc_cnt;         /**< Current number of allocations. */
+    uint32_t alloc_fail_cnt;    /**< Number of failed allocations. */
+} mbed_stats_heap_t;
+
+/**
+ *  Fill the passed in heap stat structure with heap stats.
+ *
+ *  @param stats    A pointer to the mbed_stats_heap_t structure to fill
+ */
+void mbed_stats_heap_get(mbed_stats_heap_t *stats);
+
+typedef struct {
+    uint32_t thread_id;         /**< Identifier for thread that owns the stack or 0 if multiple threads. */
+    uint32_t max_size;          /**< Maximum number of bytes used on the stack. */
+    uint32_t reserved_size;     /**< Current number of bytes allocated for the stack. */
+    uint32_t stack_cnt;         /**< Number of stacks stats accumulated in the structure. */
+} mbed_stats_stack_t;
+
+/**
+ *  Fill the passed in structure with stack stats accumulated for all threads. The thread_id will be 0
+ *  and stack_cnt will represent number of threads.
+ *
+ *  @param stats    A pointer to the mbed_stats_stack_t structure to fill
+ */
+void mbed_stats_stack_get(mbed_stats_stack_t *stats);
+
+/**
+ *  Fill the passed array of stat structures with the stack stats for each available thread.
+ *
+ *  @param stats    A pointer to an array of mbed_stats_stack_t structures to fill
+ *  @param count    The number of mbed_stats_stack_t structures in the provided array
+ *  @return         The number of mbed_stats_stack_t structures that have been filled,
+ *                  this is equal to the number of stacks on the system.
+ */
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_toolchain.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_toolchain.h
new file mode 100755
index 0000000..f5d5e79
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_toolchain.h
@@ -0,0 +1,384 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#include "mbed_preprocessor.h"
+
+
+// Warning for unsupported compilers
+#if !defined(__GNUC__)   /* GCC        */ \
+ && !defined(__CC_ARM)   /* ARMCC      */ \
+ && !defined(__clang__)  /* LLVM/Clang */ \
+ && !defined(__ICCARM__) /* IAR        */
+#warning "This compiler is not yet supported."
+#endif
+
+
+// Attributes
+
+/** MBED_PACKED
+ *  Pack a structure, preventing any padding from being added between fields.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_PACKED(struct) foo {
+ *      char x;
+ *      int y;
+ *  };
+ *  @endcode
+ */
+#ifndef MBED_PACKED
+#if defined(__ICCARM__)
+#define MBED_PACKED(struct) __packed struct
+#else
+#define MBED_PACKED(struct) struct __attribute__((packed))
+#endif
+#endif
+
+/** MBED_ALIGN(N)
+ *  Declare a variable to be aligned on an N-byte boundary.
+ *
+ *  @note
+ *  IAR does not support alignment greater than word size on the stack
+ *  
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_ALIGN(16) char a;
+ *  @endcode
+ */
+#ifndef MBED_ALIGN
+#if defined(__ICCARM__)
+#define MBED_ALIGN(N) _Pragma(MBED_STRINGIFY(data_alignment=N))
+#else
+#define MBED_ALIGN(N) __attribute__((aligned(N)))
+#endif
+#endif
+
+/** MBED_UNUSED
+ *  Declare a function argument to be unused, suppressing compiler warnings
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  void foo(MBED_UNUSED int arg) {
+ *
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_UNUSED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_UNUSED __attribute__((__unused__))
+#else
+#define MBED_UNUSED
+#endif
+#endif
+
+/** MBED_USED
+ *  Inform the compiler that a static variable is to be retained in the object file, even if it is unreferenced.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_USED int foo;
+ *
+ *  @endcode
+ */
+#ifndef MBED_USED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_USED __attribute__((used))
+#elif defined(__ICCARM__)
+#define MBED_USED __root
+#else
+#define MBED_USED
+#endif
+#endif
+
+/** MBED_WEAK
+ *  Mark a function as being weak.
+ *
+ *  @note
+ *  Functions should only be marked as weak in the source file. The header file
+ *  should contain a regular function declaration to insure the function is emitted.
+ *  A function marked weak will not be emitted if an alternative non-weak
+ *  implementation is defined.
+ *  
+ *  @note
+ *  Weak functions are not friendly to making code re-usable, as they can only
+ *  be overridden once (and if they are multiply overridden the linker will emit
+ *  no warning). You should not normally use weak symbols as part of the API to
+ *  re-usable modules.
+ *  
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *  
+ *  MBED_WEAK void foo() {
+ *      // a weak implementation of foo that can be overriden by a definition
+ *      // without  __weak
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_WEAK
+#if defined(__ICCARM__)
+#define MBED_WEAK __weak
+#else
+#define MBED_WEAK __attribute__((weak))
+#endif
+#endif
+
+/** MBED_PURE
+ *  Hint to the compiler that a function depends only on parameters
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_PURE int foo(int arg){
+ *      // no access to global variables
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_PURE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_PURE __attribute__((const))
+#else
+#define MBED_PURE
+#endif
+#endif
+
+/** MBED_NOINLINE
+ *  Declare a function that must not be inlined.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *  
+ *  MBED_NOINLINE void foo() {
+ *  
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_NOINLINE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_NOINLINE __attribute__((noinline))
+#elif defined(__ICCARM__)
+#define MBED_NOINLINE _Pragma("inline=never")
+#else
+#define MBED_NOINLINE
+#endif
+#endif
+
+/** MBED_FORCEINLINE
+ *  Declare a function that must always be inlined. Failure to inline
+ *  such a function will result in an error.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *  
+ *  MBED_FORCEINLINE void foo() {
+ *  
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_FORCEINLINE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_FORCEINLINE static inline __attribute__((always_inline))
+#elif defined(__ICCARM__)
+#define MBED_FORCEINLINE _Pragma("inline=forced") static
+#else
+#define MBED_FORCEINLINE static inline
+#endif
+#endif
+
+/** MBED_NORETURN
+ *  Declare a function that will never return.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *  
+ *  MBED_NORETURN void foo() {
+ *      // must never return
+ *      while (1) {}
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_NORETURN
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_NORETURN __attribute__((noreturn))
+#elif defined(__ICCARM__)
+#define MBED_NORETURN __noreturn
+#else
+#define MBED_NORETURN
+#endif
+#endif
+
+/** MBED_UNREACHABLE
+ *  An unreachable statement. If the statement is reached,
+ *  behaviour is undefined. Useful in situations where the compiler
+ *  cannot deduce the unreachability of code.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  void foo(int arg) {
+ *      switch (arg) {
+ *          case 1: return 1;
+ *          case 2: return 2;
+ *          ...
+ *      }
+ *      MBED_UNREACHABLE;
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_UNREACHABLE
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_UNREACHABLE __builtin_unreachable()
+#else
+#define MBED_UNREACHABLE while (1)
+#endif
+#endif
+
+/** MBED_DEPRECATED("message string")
+ *  Mark a function declaration as deprecated, if it used then a warning will be
+ *  issued by the compiler possibly including the provided message. Note that not
+ *  all compilers are able to display the message.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *  
+ *  MBED_DEPRECATED("don't foo any more, bar instead")
+ *  void foo(int arg);
+ *  @endcode
+ */
+#ifndef MBED_DEPRECATED
+#if defined(__CC_ARM)
+#define MBED_DEPRECATED(M) __attribute__((deprecated))
+#elif defined(__GNUC__) || defined(__clang__)
+#define MBED_DEPRECATED(M) __attribute__((deprecated(M)))
+#else
+#define MBED_DEPRECATED(M)
+#endif
+#endif
+
+/** MBED_DEPRECATED_SINCE("version", "message string")
+ *  Mark a function declaration as deprecated, noting that the declaration was
+ *  deprecated on the specified version. If the function is used then a warning
+ *  will be issued by the compiler possibly including the provided message.
+ *  Note that not all compilers are able to display this message.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_DEPRECATED_SINCE("mbed-os-5.1", "don't foo any more, bar instead")
+ *  void foo(int arg);
+ *  @endcode
+ */
+#define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]")
+
+/** MBED_CALLER_ADDR()
+ * Returns the caller of the current function.
+ *
+ * @note
+ * This macro is only implemented for GCC and ARMCC.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * printf("This function was called from %p", MBED_CALLER_ADDR());
+ * @endcode
+ *
+ * @return Address of the calling function
+ */
+#ifndef MBED_CALLER_ADDR
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_extract_return_addr(__builtin_return_address(0))
+#elif defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_return_address(0)
+#else
+#define MBED_CALLER_ADDR() (NULL)
+#endif
+#endif
+
+#ifndef MBED_SECTION
+#if (defined(__GNUC__) || defined(__clang__)) || defined(__CC_ARM)
+#define MBED_SECTION(name) __attribute__ ((section (name)))
+#elif defined(__ICCARM__)
+#define MBED_SECTION(name) _Pragma(MBED_STRINGIFY(location=name))
+#else
+#error "Missing MBED_SECTION directive"
+#endif
+#endif
+
+#ifndef MBED_PRINTF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx)))
+#else
+#define MBED_PRINTF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_PRINTF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx, first_param_idx)))
+#else
+#define MBED_SCANF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_SCANF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+// FILEHANDLE declaration
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+// Backwards compatibility
+#ifndef WEAK
+#define WEAK MBED_WEAK
+#endif
+
+#ifndef PACKED
+#define PACKED MBED_PACKED()
+#endif
+
+#ifndef EXTERN
+#define EXTERN extern
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api.h
new file mode 100755
index 0000000..91619de
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api.h
@@ -0,0 +1,72 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ *     while (1) {
+ *         heartbeat = 1;
+ *         wait(0.5);
+ *         heartbeat = 0;
+ *         wait(0.5);
+ *     }
+ * }
+ * @endcode
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ *  the accuracy of single precision floating point).
+ *
+ *  @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ *  @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ *  @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api_no_rtos.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api_no_rtos.c
new file mode 100755
index 0000000..a78dd8b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api_no_rtos.c
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is not present.
+#ifndef MBED_CONF_RTOS_PRESENT
+
+#include "platform/mbed_wait_api.h"
+#include "hal/us_ticker_api.h"
+
+void wait(float s) {
+    wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+    wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+    const ticker_data_t *const ticker = get_us_ticker_data();
+    uint32_t start = ticker_read(ticker);
+    while ((ticker_read(ticker) - start) < (uint32_t)us);
+}
+
+#endif // #ifndef MBED_CONF_RTOS_PRESENT
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api_rtos.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api_rtos.cpp
new file mode 100755
index 0000000..d89b139
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/mbed_wait_api_rtos.cpp
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is present.
+#ifdef MBED_CONF_RTOS_PRESENT
+
+#include "platform/mbed_wait_api.h"
+#include "hal/us_ticker_api.h"
+#include "rtos/rtos.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
+
+void wait(float s) {
+    wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+    wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+    const ticker_data_t *const ticker = get_us_ticker_data();
+
+    uint32_t start = ticker_read(ticker);
+    // Use the RTOS to wait for millisecond delays if possible
+    int ms = us / 1000;
+    if ((ms > 0) && core_util_are_interrupts_enabled()) {
+        sleep_manager_lock_deep_sleep();
+        Thread::wait((uint32_t)ms);
+        sleep_manager_unlock_deep_sleep();
+    }
+    // Use busy waiting for sub-millisecond delays, or for the whole
+    // interval if interrupts are not enabled
+    while ((ticker_read(ticker) - start) < (uint32_t)us);
+}
+
+#endif // #if MBED_CONF_RTOS_PRESENT
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/platform.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/platform.h
new file mode 100755
index 0000000..a5802ff
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/platform.h
@@ -0,0 +1,35 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#include "platform/mbed_retarget.h"
+#include "platform/mbed_toolchain.h"
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/rtc_time.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/rtc_time.h
new file mode 100755
index 0000000..a13f1bd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/rtc_time.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_RTC_TIME_H
+#define MBED_OLD_RTC_TIME_H
+
+#warning rtc_time.h has been replaced by mbed_rtc_time.h, please update to mbed_rtc_time.h [since mbed-os-5.3]
+#include "platform/mbed_rtc_time.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/semihost_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/semihost_api.h
new file mode 100755
index 0000000..41811a3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/semihost_api.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_SEMIHOST_API_H
+#define MBED_OLD_SEMIHOST_API_H
+
+#warning semihost_api.h has been replaced by mbed_semihost_api.h, please update to mbed_semihost_api.h [since mbed-os-5.3]
+#include "platform/mbed_semihost_api.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/sleep.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/sleep.h
new file mode 100755
index 0000000..ac3e84b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/sleep.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_SLEEP_H
+#define MBED_OLD_SLEEP_H
+
+#warning sleep.h has been replaced by mbed_sleep.h, please update to mbed_sleep.h [since mbed-os-5.3]
+#include "platform/mbed_sleep.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/toolchain.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/toolchain.h
new file mode 100755
index 0000000..6fbef80
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/toolchain.h
@@ -0,0 +1,28 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_TOOLCHAIN_H
+#define MBED_OLD_TOOLCHAIN_H
+
+#warning toolchain.h has been replaced by mbed_toolchain.h, please update to mbed_toolchain.h [since mbed-os-5.3]
+#include "platform/mbed_toolchain.h"
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/wait_api.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/wait_api.h
new file mode 100755
index 0000000..d725b5f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/platform/wait_api.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_WAIT_API_H
+#define MBED_OLD_WAIT_API_H
+
+#warning wait_api.h has been replaced by mbed_wait_api.h, please update to mbed_wait_api.h [since mbed-os-5.3]
+#include "platform/mbed_wait_api.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/EventFlags.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/EventFlags.cpp
new file mode 100755
index 0000000..abd88a1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/EventFlags.cpp
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "rtos/EventFlags.h"
+#include <string.h>
+#include "mbed_error.h"
+#include "mbed_assert.h"
+
+namespace rtos {
+
+EventFlags::EventFlags()
+{
+    constructor();
+}
+
+EventFlags::EventFlags(const char *name)
+{
+    constructor(name);
+}
+
+void EventFlags::constructor(const char *name)
+{
+    memset(&_obj_mem, 0, sizeof(_obj_mem));
+    memset(&_attr, 0, sizeof(_attr));
+    _attr.name = name ? name : "application_unnamed_event_flags";
+    _attr.cb_mem = &_obj_mem;
+    _attr.cb_size = sizeof(_obj_mem);
+    _id = osEventFlagsNew(&_attr);
+    MBED_ASSERT(_id);
+}
+
+uint32_t EventFlags::set(uint32_t flags)
+{
+    return osEventFlagsSet(_id, flags);
+}
+
+uint32_t EventFlags::clear(uint32_t flags)
+{
+    return osEventFlagsClear(_id, flags);
+}
+
+uint32_t EventFlags::get() const
+{
+    return osEventFlagsGet(_id);
+}
+
+uint32_t EventFlags::wait_all(uint32_t flags, uint32_t timeout, bool clear)
+{
+    return wait(flags, osFlagsWaitAll, timeout, clear);
+}
+
+uint32_t EventFlags::wait_any(uint32_t flags, uint32_t timeout, bool clear)
+{
+    return wait(flags, osFlagsWaitAny, timeout, clear);
+}
+
+EventFlags::~EventFlags()
+{
+    osEventFlagsDelete(_id);
+}
+
+uint32_t EventFlags::wait(uint32_t flags, uint32_t opt, uint32_t timeout, bool clear)
+{
+    if (clear == false) {
+        opt |= osFlagsNoClear;
+    }
+
+    return osEventFlagsWait(_id, flags, opt, timeout);
+}
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/EventFlags.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/EventFlags.h
new file mode 100755
index 0000000..8f0e2b2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/EventFlags.h
@@ -0,0 +1,100 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef EVENT_FLAG_H
+#define EVENT_FLAG_H
+
+#include <stdint.h>
+#include "cmsis_os2.h"
+#include "mbed_rtos1_types.h"
+#include "mbed_rtos_storage.h"
+
+#include "platform/NonCopyable.h"
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** The EventFlags class is used to signal or wait for an arbitrary event or events.
+ @note 
+ EventFlags support 31 flags so the MSB flag is ignored, it is used to return an error code (@a osFlagsError)
+ @note
+ Memory considerations: The EventFlags control structures will be created on current thread's stack, both for the mbed OS
+ and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+*/
+class EventFlags : private mbed::NonCopyable<EventFlags> {
+public:
+    /** Create and Initialize a EventFlags object */
+    EventFlags();
+
+    /** Create and Initialize a EventFlags object
+
+     @param name name to be used for this EventFlags. It has to stay allocated for the lifetime of the thread.
+    */
+    EventFlags(const char *name);
+
+    /** Set the specified Event Flags.
+      @param   flags  specifies the flags that shall be set.
+      @return  event flags after setting or error code if highest bit set (@a osFlagsError).
+     */
+    uint32_t set(uint32_t flags);
+
+    /** Clear the specified Event Flags.
+      @param   flags  specifies the flags that shall be cleared. (default: 0x7fffffff - all flags)
+      @return  event flags before clearing or error code if highest bit set (@a osFlagsError).
+     */
+    uint32_t clear(uint32_t flags = 0x7fffffff);
+
+    /** Get the currently set Event Flags.
+      @return  set event flags.
+     */
+    uint32_t get() const;
+
+    /** Wait for all of the specified event flags to become signaled.
+      @param   flags    specifies the flags to wait for.
+      @param   timeout  timeout value or 0 in case of no time-out. (default: osWaitForever)
+      @param   clear    specifies wether to clear the flags after waiting for them. (default: true)
+      @return  event flags before clearing or error code if highest bit set (@a osFlagsError).
+     */
+    uint32_t wait_all(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true);
+
+    /** Wait for any of the specified event flags to become signaled.
+      @param   flags    specifies the flags to wait for. (default: 0)
+      @param   timeout  timeout value or 0 in case of no time-out. (default: osWaitForever)
+      @param   clear    specifies wether to clear the flags after waiting for them. (default: true)
+      @return  event flags before clearing or error code if highest bit set (@a osFlagsError).
+     */
+    uint32_t wait_any(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true);
+
+    ~EventFlags();
+
+private:
+    void constructor(const char *name = NULL);
+    uint32_t wait(uint32_t flags, uint32_t opt, uint32_t timeout, bool clear);
+    osEventFlagsId_t                _id;
+    osEventFlagsAttr_t              _attr;
+    mbed_rtos_storage_event_flags_t _obj_mem;
+};
+
+}
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mail.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mail.h
new file mode 100755
index 0000000..602907e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mail.h
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MAIL_H
+#define MAIL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "Queue.h"
+#include "MemoryPool.h"
+#include "cmsis_os2.h"
+#include "mbed_rtos_storage.h"
+#include "mbed_rtos1_types.h"
+
+#include "platform/NonCopyable.h"
+
+using namespace rtos;
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** The Mail class allow to control, send, receive, or wait for mail.
+ A mail is a memory block that is send to a thread or interrupt service routine.
+  @tparam  T         data type of a single message element.
+  @tparam  queue_sz  maximum number of messages in queue.
+
+ @note
+ Memory considerations: The mail data store and control structures will be created on current thread's stack,
+ both for the mbed OS and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+*/
+template<typename T, uint32_t queue_sz>
+class Mail : private mbed::NonCopyable<Mail<T, queue_sz> > {
+public:
+    /** Create and Initialise Mail queue. */
+    Mail() { };
+
+    /** Allocate a memory block of type T
+      @param   millisec  timeout value or 0 in case of no time-out. (default: 0).
+      @return  pointer to memory block that can be filled with mail or NULL in case error.
+    */
+    T* alloc(uint32_t millisec=0) {
+        return _pool.alloc();
+    }
+
+    /** Allocate a memory block of type T and set memory block to zero.
+      @param   millisec  timeout value or 0 in case of no time-out.  (default: 0).
+      @return  pointer to memory block that can be filled with mail or NULL in case error.
+    */
+    T* calloc(uint32_t millisec=0) {
+        return _pool.calloc();
+    }
+
+    /** Put a mail in the queue.
+      @param   mptr  memory block previously allocated with Mail::alloc or Mail::calloc.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus put(T *mptr) {
+        return _queue.put(mptr);
+    }
+
+    /** Get a mail from a queue.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event that contains mail information or error code.
+    */
+    osEvent get(uint32_t millisec=osWaitForever) {
+        osEvent evt = _queue.get(millisec);
+        if (evt.status == osEventMessage) {
+            evt.status = osEventMail;
+        }
+        return evt;
+    }
+
+    /** Free a memory block from a mail.
+      @param   mptr  pointer to the memory block that was obtained with Mail::get.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus free(T *mptr) {
+        return _pool.free(mptr);
+    }
+
+private:
+    Queue<T, queue_sz> _queue;
+    MemoryPool<T, queue_sz> _pool;
+};
+
+}
+
+#endif
+
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/MemoryPool.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/MemoryPool.h
new file mode 100755
index 0000000..361ae65
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/MemoryPool.h
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MEMORYPOOL_H
+#define MEMORYPOOL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os2.h"
+#include "mbed_rtos1_types.h"
+#include "mbed_rtos_storage.h"
+#include "platform/NonCopyable.h"
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** Define and manage fixed-size memory pools of objects of a given type.
+  @tparam  T         data type of a single object (element).
+  @tparam  queue_sz  maximum number of objects (elements) in the memory pool.
+
+ @note
+ Memory considerations: The memory pool data store and control structures will be created on current thread's stack,
+ both for the mbed OS and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+*/
+template<typename T, uint32_t pool_sz>
+class MemoryPool : private mbed::NonCopyable<MemoryPool<T, pool_sz> > {
+	MBED_STATIC_ASSERT(pool_sz > 0, "Invalid memory pool size. Must be greater than 0.");
+public:
+    /** Create and Initialize a memory pool. */
+    MemoryPool() {
+        memset(_pool_mem, 0, sizeof(_pool_mem));
+        memset(&_obj_mem, 0, sizeof(_obj_mem));
+        memset(&_attr, 0, sizeof(_attr));
+        _attr.mp_mem = _pool_mem;
+        _attr.mp_size = sizeof(_pool_mem);
+        _attr.cb_mem = &_obj_mem;
+        _attr.cb_size = sizeof(_obj_mem);
+        _id = osMemoryPoolNew(pool_sz, sizeof(T), &_attr);
+        MBED_ASSERT(_id);
+    }
+
+    /** Destroy a memory pool */
+    ~MemoryPool() {
+        osMemoryPoolDelete(_id);
+    }
+
+    /** Allocate a memory block of type T from a memory pool.
+      @return  address of the allocated memory block or NULL in case of no memory available.
+    */
+    T* alloc(void) {
+        return (T*)osMemoryPoolAlloc(_id, 0);
+    }
+
+    /** Allocate a memory block of type T from a memory pool and set memory block to zero.
+      @return  address of the allocated memory block or NULL in case of no memory available.
+    */
+    T* calloc(void) {
+        T *item = (T*)osMemoryPoolAlloc(_id, 0);
+        if (item != NULL) {
+            memset(item, 0, sizeof(T));
+        }
+        return item;
+    }
+
+    /** Free a memory block.
+      @param   block  address of the allocated memory block to be freed.
+      @return         osOK on successful deallocation, osErrorParameter if given memory block id
+                      is NULL or invalid, or osErrorResource if given memory block is in an
+                      invalid memory pool state.
+
+    */
+    osStatus free(T *block) {
+        return osMemoryPoolFree(_id, (void*)block);
+    }
+
+private:
+    osMemoryPoolId_t             _id;
+    osMemoryPoolAttr_t           _attr;
+    /* osMemoryPoolNew requires that pool block size is a multiple of 4 bytes. */
+    char                         _pool_mem[((sizeof(T) + 3) & ~3) * pool_sz];
+    mbed_rtos_storage_mem_pool_t _obj_mem;
+};
+
+}
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mutex.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mutex.cpp
new file mode 100755
index 0000000..359af10
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mutex.cpp
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "rtos/Mutex.h"
+
+#include <string.h>
+#include "mbed_error.h"
+#include "mbed_assert.h"
+
+namespace rtos {
+
+Mutex::Mutex()
+{
+    constructor();
+}
+
+Mutex::Mutex(const char *name)
+{
+    constructor(name);
+}
+
+void Mutex::constructor(const char *name)
+{
+    memset(&_obj_mem, 0, sizeof(_obj_mem));
+    memset(&_attr, 0, sizeof(_attr));
+    _attr.name = name ? name : "aplication_unnamed_mutex";
+    _attr.cb_mem = &_obj_mem;
+    _attr.cb_size = sizeof(_obj_mem);
+    _attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    _id = osMutexNew(&_attr);
+    MBED_ASSERT(_id);
+}
+
+osStatus Mutex::lock(uint32_t millisec) {
+    return osMutexAcquire(_id, millisec);
+}
+
+bool Mutex::trylock() {
+    return (osMutexAcquire(_id, 0) == osOK);
+}
+
+osStatus Mutex::unlock() {
+    return osMutexRelease(_id);
+}
+
+Mutex::~Mutex() {
+    osMutexDelete(_id);
+}
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mutex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mutex.h
new file mode 100755
index 0000000..4f1ed8a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Mutex.h
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MUTEX_H
+#define MUTEX_H
+
+#include <stdint.h>
+#include "cmsis_os2.h"
+#include "mbed_rtos1_types.h"
+#include "mbed_rtos_storage.h"
+
+#include "platform/NonCopyable.h"
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** The Mutex class is used to synchronize the execution of threads.
+ This is for example used to protect access to a shared resource.
+
+ @note
+ Memory considerations: The mutex control structures will be created on current thread's stack, both for the mbed OS
+ and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+*/
+class Mutex : private mbed::NonCopyable<Mutex> {
+public:
+    /** Create and Initialize a Mutex object */
+    Mutex();
+
+    /** Create and Initialize a Mutex object
+
+     @param name name to be used for this mutex. It has to stay allocated for the lifetime of the thread.
+    */
+    Mutex(const char *name);
+
+    /** Wait until a Mutex becomes available.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever)
+      @return  status code that indicates the execution status of the function:
+               @a osOK the mutex has been obtained.
+               @a osErrorTimeout the mutex could not be obtained in the given time.
+               @a osErrorParameter internal error.
+               @a osErrorResource the mutex could not be obtained when no timeout was specified.
+               @a osErrorISR this function cannot be called from the interrupt service routine.
+     */
+    osStatus lock(uint32_t millisec=osWaitForever);
+
+    /** Try to lock the mutex, and return immediately
+      @return true if the mutex was acquired, false otherwise.
+     */
+    bool trylock();
+
+    /** Unlock the mutex that has previously been locked by the same thread
+      @return status code that indicates the execution status of the function:
+              @a osOK the mutex has been released.
+              @a osErrorParameter internal error.
+              @a osErrorResource the mutex was not locked or the current thread wasn't the owner.
+              @a osErrorISR this function cannot be called from the interrupt service routine.
+     */
+    osStatus unlock();
+
+    ~Mutex();
+
+private:
+    void constructor(const char *name = NULL);
+
+    osMutexId_t               _id;
+    osMutexAttr_t             _attr;
+    mbed_rtos_storage_mutex_t _obj_mem;
+};
+
+}
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Queue.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Queue.h
new file mode 100755
index 0000000..5673952
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Queue.h
@@ -0,0 +1,126 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os2.h"
+#include "mbed_rtos_storage.h"
+#include "platform/mbed_error.h"
+#include "platform/NonCopyable.h"
+#include "mbed_rtos1_types.h"
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** The Queue class allow to control, send, receive, or wait for messages.
+ A message can be a integer or pointer value  to a certain type T that is send
+ to a thread or interrupt service routine.
+  @tparam  T         data type of a single message element.
+  @tparam  queue_sz  maximum number of messages in queue.
+
+ @note
+ Memory considerations: The queue control structures will be created on current thread's stack, both for the mbed OS
+ and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+*/
+template<typename T, uint32_t queue_sz>
+class Queue : private mbed::NonCopyable<Queue<T, queue_sz> > {
+public:
+    /** Create and initialize a message Queue. */
+    Queue() {
+        memset(&_obj_mem, 0, sizeof(_obj_mem));
+        memset(&_attr, 0, sizeof(_attr));
+        _attr.mq_mem = _queue_mem;
+        _attr.mq_size = sizeof(_queue_mem);
+        _attr.cb_mem = &_obj_mem;
+        _attr.cb_size = sizeof(_obj_mem);
+        _id = osMessageQueueNew(queue_sz, sizeof(T*), &_attr);
+        MBED_ASSERT(_id);
+    }
+
+    ~Queue() {
+        osMessageQueueDelete(_id);
+    }
+
+    /** Put a message in a Queue.
+      @param   data      message pointer.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: 0)
+      @param   prio      priority value or 0 in case of default. (default: 0)
+      @return  status code that indicates the execution status of the function:
+               @a osOK the message has been put into the queue.
+               @a osErrorTimeout the message could not be put into the queue in the given time.
+               @a osErrorResource not enough space in the queue.
+               @a osErrorParameter internal error or non-zero timeout specified in an ISR.
+    */
+    osStatus put(T* data, uint32_t millisec=0, uint8_t prio=0) {
+        return osMessageQueuePut(_id, &data, prio, millisec);
+    }
+
+    /** Get a message or Wait for a message from a Queue. Messages are retrieved in a descending priority order or
+        first in first out when the priorities are the same.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event information that includes the message in event.value and the status code in event.status:
+               @a osEventMessage message received.
+               @a osOK no message is available in the queue and no timeout was specified.
+               @a osEventTimeout no message has arrived during the given timeout period.
+               @a osErrorParameter a parameter is invalid or outside of a permitted range.
+    */
+    osEvent get(uint32_t millisec=osWaitForever) {
+        osEvent event;
+        T *data = NULL;
+        osStatus_t res = osMessageQueueGet(_id, &data, NULL, millisec);
+
+        switch (res) {
+            case osOK:
+                event.status = (osStatus)osEventMessage;
+                event.value.p = data;
+                break;
+            case osErrorResource:
+                event.status = osOK;
+                break;
+            case osErrorTimeout:
+                event.status = (osStatus)osEventTimeout;
+                break;
+            case osErrorParameter:
+            default:
+                event.status = osErrorParameter;
+                break;
+        }
+        event.def.message_id = _id;
+
+        return event;
+    }
+
+private:
+    osMessageQueueId_t            _id;
+    osMessageQueueAttr_t          _attr;
+    char                          _queue_mem[queue_sz * (sizeof(T*) + sizeof(mbed_rtos_storage_message_t))];
+    mbed_rtos_storage_msg_queue_t _obj_mem;
+};
+
+}
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/RtosTimer.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/RtosTimer.cpp
new file mode 100755
index 0000000..acec84e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/RtosTimer.cpp
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "rtos/RtosTimer.h"
+
+#include <string.h>
+
+#include "mbed.h"
+#include "platform/mbed_error.h"
+
+namespace rtos {
+
+void RtosTimer::constructor(mbed::Callback<void()> func, os_timer_type type) {
+    _function = func;
+    memset(&_obj_mem, 0, sizeof(_obj_mem));
+    memset(&_attr, 0, sizeof(_attr));
+    _attr.cb_mem = &_obj_mem;
+    _attr.cb_size = sizeof(_obj_mem);
+    _id = osTimerNew((void (*)(void *))Callback<void()>::thunk, type, &_function, &_attr);
+    MBED_ASSERT(_id);
+}
+
+osStatus RtosTimer::start(uint32_t millisec) {
+    return osTimerStart(_id, millisec);
+}
+
+osStatus RtosTimer::stop(void) {
+    return osTimerStop(_id);
+}
+
+RtosTimer::~RtosTimer() {
+    osTimerDelete(_id);
+}
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/RtosTimer.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/RtosTimer.h
new file mode 100755
index 0000000..d96de82
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/RtosTimer.h
@@ -0,0 +1,169 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_TIMER_H
+#define RTOS_TIMER_H
+
+#include <stdint.h>
+#include "cmsis_os2.h"
+#include "mbed_rtos_storage.h"
+#include "platform/Callback.h"
+#include "platform/NonCopyable.h"
+#include "platform/mbed_toolchain.h"
+#include "mbed_rtos1_types.h"
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** The RtosTimer class allow creating and and controlling of timer functions in the system.
+ A timer function is called when a time period expires whereby both on-shot and
+ periodic timers are possible. A timer can be started, restarted, or stopped.
+
+ Timers are handled in the thread osTimerThread.
+ Callback functions run under control of this thread and may use CMSIS-RTOS API calls.
+
+ @deprecated
+ The RtosTimer has been superseded by the EventQueue. The RtosTimer and EventQueue duplicate
+ the functionality of timing events outside of interrupt context, however the EventQueue
+ has additional features to handle deferring other events to multiple contexts.
+
+ For an example, the following code shows a simple use of the RtosTimer:
+ @code
+ DigitalOut led(LED1);
+ void blink() {
+     led = !led;
+ }
+
+ RtosTimer timer(&blink);
+ int main() {
+     timer.start(1000); // call blink every 1s
+     wait_ms(5000);
+     timer.stop(); // stop after 5s
+ }
+ @endcode
+
+ This is the above example rewritten to use the EventQueue:
+ @code
+ DigitalOut led(LED1);
+ void blink() {
+     led = !led;
+ }
+
+ EventQueue queue(4*EVENTS_EVENT_SIZE);
+ int main() {
+    int blink_id = queue.call_every(1000, &blink); // call blink every 1s
+    queue.dispatch(5000);
+    queue.cancel(blink_id); // stop after 5s
+ }
+ @endcode
+
+ @note
+ Memory considerations: The timer control structures will be created on current thread's stack, both for the mbed OS
+ and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+*/
+class RtosTimer : private mbed::NonCopyable<RtosTimer> {
+public:
+    /** Create timer.
+      @param   func      function to be executed by this timer.
+      @param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+      @param   argument  argument to the timer call back function. (default: NULL)
+      @deprecated Replaced with RtosTimer(Callback<void()>, os_timer_type)
+      @deprecated
+          The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Replaced with RtosTimer(Callback<void()>, os_timer_type)")
+    MBED_DEPRECATED_SINCE("mbed-os-5.2",
+        "The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details")
+    RtosTimer(void (*func)(void const *argument), os_timer_type type=osTimerPeriodic, void *argument=NULL) {
+        constructor(mbed::callback((void (*)(void *))func, argument), type);
+    }
+    
+    /** Create timer.
+      @param   func      function to be executed by this timer.
+      @param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+      @deprecated
+          The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details
+    */
+    MBED_DEPRECATED_SINCE("mbed-os-5.2",
+        "The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details")
+    RtosTimer(mbed::Callback<void()> func, os_timer_type type=osTimerPeriodic) {
+        constructor(func, type);
+    }
+    
+    /** Create timer.
+      @param   obj       pointer to the object to call the member function on.
+      @param   method    member function to be executed by this timer.
+      @param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+      @deprecated
+          The RtosTimer constructor does not support cv-qualifiers. Replaced by
+          RtosTimer(callback(obj, method), os_timer_type).
+      @deprecated
+          The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details
+    */
+    template <typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The RtosTimer constructor does not support cv-qualifiers. Replaced by "
+        "RtosTimer(callback(obj, method), os_timer_type).")
+    MBED_DEPRECATED_SINCE("mbed-os-5.2",
+        "The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details")
+    RtosTimer(T *obj, M method, os_timer_type type=osTimerPeriodic) {
+        constructor(mbed::callback(obj, method), type);
+    }
+
+    /** Stop the timer.
+      @return  status code that indicates the execution status of the function:
+          @a osOK the timer has been stopped.
+          @a osErrorISR @a stop cannot be called from interrupt service routines.
+          @a osErrorParameter internal error.
+          @a osErrorResource the timer is not running.
+    */
+    osStatus stop(void);
+
+    /** Start or restart the timer.
+      @param   millisec  non-zero value of the timer.
+      @return  status code that indicates the execution status of the function:
+          @a osOK the timer has been started or restarted.
+          @a osErrorISR @a start cannot be called from interrupt service routines.
+          @a osErrorParameter internal error or incorrect parameter value.
+          @a osErrorResource internal error (the timer is in an invalid timer state).
+    */
+    osStatus start(uint32_t millisec);
+
+    ~RtosTimer();
+
+private:
+    // Required to share definitions without
+    // delegated constructors
+    void constructor(mbed::Callback<void()> func, os_timer_type type);
+
+    osTimerId_t _id;
+    osTimerAttr_t _attr;
+    mbed_rtos_storage_timer_t _obj_mem;
+    mbed::Callback<void()> _function;
+};
+
+}
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Semaphore.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Semaphore.cpp
new file mode 100755
index 0000000..107dccb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Semaphore.cpp
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "rtos/Semaphore.h"
+#include "platform/mbed_assert.h"
+
+#include <string.h>
+
+namespace rtos {
+
+Semaphore::Semaphore(int32_t count) {
+    constructor(count, 0xffff);
+}
+
+Semaphore::Semaphore(int32_t count, uint16_t max_count) {
+    constructor(count, max_count);
+}
+
+void Semaphore::constructor(int32_t count, uint16_t max_count) {
+    memset(&_obj_mem, 0, sizeof(_obj_mem));
+    memset(&_attr, 0, sizeof(_attr));
+    _attr.cb_mem = &_obj_mem;
+    _attr.cb_size = sizeof(_obj_mem);
+    _id = osSemaphoreNew(max_count, count, &_attr);
+    MBED_ASSERT(_id != NULL);
+}
+
+int32_t Semaphore::wait(uint32_t millisec) {
+    osStatus_t stat = osSemaphoreAcquire(_id, millisec);
+    switch (stat) {
+        case osOK:
+            return osSemaphoreGetCount(_id) + 1;
+        case osErrorTimeout:
+        case osErrorResource:
+            return 0;
+        case osErrorParameter:
+        default:
+            return -1;
+    }
+}
+
+osStatus Semaphore::release(void) {
+    return osSemaphoreRelease(_id);
+}
+
+Semaphore::~Semaphore() {
+    osSemaphoreDelete(_id);
+}
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Semaphore.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Semaphore.h
new file mode 100755
index 0000000..80dc928
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Semaphore.h
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#include <stdint.h>
+#include "cmsis_os2.h"
+#include "mbed_rtos1_types.h"
+#include "mbed_rtos_storage.h"
+#include "platform/NonCopyable.h"
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** The Semaphore class is used to manage and protect access to a set of shared resources.
+ *
+ * @note
+ * Memory considerations: The semaphore control structures will be created on current thread's stack, both for the mbed OS
+ * and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+ */
+class Semaphore : private mbed::NonCopyable<Semaphore> {
+public:
+    /** Create and Initialize a Semaphore object used for managing resources.
+      @param count      number of available resources; maximum index value is (count-1). (default: 0).
+    */
+    Semaphore(int32_t count=0);
+
+    /** Create and Initialize a Semaphore object used for managing resources.
+      @param  count     number of available resources
+      @param  max_count maximum number of available resources
+    */
+    Semaphore(int32_t count, uint16_t max_count);
+
+    /** Wait until a Semaphore resource becomes available.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  number of available tokens, before taking one; or -1 in case of incorrect parameters
+    */
+    int32_t wait(uint32_t millisec=osWaitForever);
+
+    /** Release a Semaphore resource that was obtain with Semaphore::wait.
+      @return status code that indicates the execution status of the function:
+              @a osOK the token has been correctly released.
+              @a osErrorResource the maximum token count has been reached.
+              @a osErrorParameter internal error.
+    */
+    osStatus release(void);
+
+    ~Semaphore();
+
+private:
+    void constructor(int32_t count, uint16_t max_count);
+
+    osSemaphoreId_t               _id;
+    osSemaphoreAttr_t             _attr;
+    mbed_rtos_storage_semaphore_t _obj_mem;
+};
+
+}
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_boot.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_boot.c
new file mode 100755
index 0000000..646f307
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_boot.c
@@ -0,0 +1,703 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* mbed OS boot sequence
+ *
+ * Most of mbed supported targets use default ARM Cortex M boot approach, where the core starts executing reset vector
+ * after power up. Reset ISR is defined for each target by the vendor (basing on CMSIS template). Reset vector is
+ * responsible for low level platform init and then calling in libc (__main). Depending on compiler and version of C
+ * library, predefined function will be called which is implemented by mbed OS.
+ *
+ * There's number of functions, vendor and users can provide to setup the platform and/or inject a code to be executed
+ *  before main():
+ *      * Reset vector and SystemInit: Reset vector should do low level core and board initialization.
+ *      * mbed_sdk_init: Higher level board init and making sure the board is ready for the mbed OS.
+ *      * mbed_main: User's code to be executed before main().
+ *      * main: Standard application code.
+ *
+ * Detailed boot procedures:
+ *
+ * For ARMCC:
+ * ==========
+ *
+ * Reset (TARGET)
+ *     -> SystemInit (TARGET)
+ *     -> __main (LIBC)
+ *         -> __rt_entry (MBED: rtos/mbed_boot.c)
+ *             -> __user_setup_stackheap (LIBC)
+ *             -> mbed_set_stack_heap (MBED: rtos/mbed_boot.c)
+ *             -> mbed_cpy_nvic (MBED: rtos/mbed_boot.c)
+ *             -> mbed_sdk_init (TARGET)
+ *             -> _platform_post_stackheap_init (RTX)
+ *                 -> osKernelInitialize (RTX)
+ *             -> mbed_start_main (MBED: rtos/mbed_boot.c)
+ *                 -> osThreadNew (RTX)
+ *                     -> pre_main(MBED: rtos/mbed_boot.c)
+ *                         -> __rt_lib_init (LIBC)
+ *                         -> $Sub$$main (MBED: rtos/mbed_boot.c)
+ *                             -> mbed_main (MBED: rtos/mbed_boot.c)
+ *                             -> main (APP)
+ *                 -> osKernelStart (RTX)
+ *
+ * In addition to the above, libc will use functions defined by RTX: __user_perthread_libspace, _mutex_initialize,
+ * _mutex_acquire, _mutex_release, _mutex_free for details consult: ARM C and C++ Libraries and Floating-Point
+ * Support User Guide.
+ *
+ * For MICROLIB:
+ * ==========
+ *
+ * Reset (TARGET)
+ *     -> SystemInit (TARGET)
+ *     -> __main (LIBC)
+ *         -> _main_init (MBED: rtos/mbed_boot.c)
+ *             -> mbed_set_stack_heap (MBED: rtos/mbed_boot.c)
+ *             -> mbed_cpy_nvic (MBED: rtos/mbed_boot.c)
+ *             -> mbed_sdk_init (TARGET)
+ *             -> osKernelInitialize (RTX)
+ *             -> mbed_start_main (MBED: rtos/mbed_boot.c)
+ *                 -> osThreadNew (RTX)
+ *                     -> pre_main(MBED: rtos/mbed_boot.c)
+ *                         -> __cpp_initialize__aeabi_ (LIBC)
+ *                         -> $Sub$$main (MBED: rtos/mbed_boot.c)
+ *                             -> mbed_main (MBED: rtos/mbed_boot.c)
+ *                             -> main (APP)
+ *                 -> osKernelStart (RTX)
+ *
+ * For GCC:
+ * ========
+ *
+ * Reset (TARGET)
+ *     -> SystemInit (TARGET)
+ *     -> __main (LIBC)
+ *         -> software_init_hook (MBED: rtos/mbed_boot.c)
+ *             -> mbed_set_stack_heap (MBED: rtos/mbed_boot.c)
+ *             -> mbed_cpy_nvic (MBED: rtos/mbed_boot.c)
+ *             -> mbed_sdk_init (TARGET)
+ *             -> osKernelInitialize (RTX)
+ *             -> mbed_start_main (MBED: rtos/mbed_boot.c)
+ *                 -> osThreadNew (RTX)
+ *                     -> pre_main(MBED: rtos/mbed_boot.c)
+ *                     -> __libc_init_array (LIBC)
+ *                         -> __wrap_main (MBED: rtos/mbed_boot.c)
+ *                             -> mbed_main (MBED: rtos/mbed_boot.c)
+ *                             -> __real_main (APP)
+ *                 -> osKernelStart (RTX)
+ *
+ * For IAR:
+ * ========
+ *
+ * Reset (TARGET)
+ *     -> SystemInit (TARGET)
+ *     -> __iar_program_start
+ *         -> __iar_init_core
+ *         -> __iar_init_core
+ *         -> __iar_init_vfp
+ *         -> __low_level_init
+ *         -> __iar_data_init3
+ *         -> mbed_cpy_nvic (MBED: rtos/mbed_boot.c)
+ *         -> mbed_sdk_init (TARGET)
+ *         -> mbed_set_stack_heap (MBED: rtos/mbed_boot.c)
+ *         -> osKernelInitialize (RTX)
+ *         -> mbed_start_main (MBED: rtos/mbed_boot.c)
+ *             -> osThreadNew (RTX)
+ *             -> pre_main(MBED: rtos/mbed_boot.c)
+ *                 -> __iar_dynamic_initialization
+*                  -> main
+ *             -> osKernelStart (RTX)
+ *
+ * Other notes:
+ *
+ *    * In addition to the above, libc will use functions defined in mbed_boot.c: __rtos_malloc_lock/unlock,
+ *      __rtos_env_lock/unlock.
+ *
+ *    * First step after the execution is passed to mbed, software_init_hook for GCC and __rt_entry for ARMC is to
+ *      initialize heap.
+ *
+ * Memory layout notes:
+ * ====================
+ *
+ * IAR Default Memory layout notes:
+ * -Heap defined by "HEAP" region in .icf file
+ * -Interrupt stack defined by "CSTACK" region in .icf file
+ * -Value INITIAL_SP is ignored
+ *
+ * IAR Custom Memory layout notes:
+ * -There is no custom layout available for IAR - everything must be defined in
+ *      the .icf file and use the default layout
+ *
+ *
+ * GCC Default Memory layout notes:
+ * -Block of memory from symbol __end__ to define INITIAL_SP used to setup interrupt
+ *      stack and heap in the function set_stack_heap()
+ * -ISR_STACK_SIZE can be overridden to be larger or smaller
+ *
+ * GCC Custom Memory layout notes:
+ * -Heap can be explicitly placed by defining both HEAP_START and HEAP_SIZE
+ * -Interrupt stack can be explicitly placed by defining both ISR_STACK_START and ISR_STACK_SIZE
+ *
+ *
+ * ARM Memory layout
+ * -Block of memory from end of region "RW_IRAM1" to define INITIAL_SP used to setup interrupt
+ *      stack and heap in the function set_stack_heap()
+ * -ISR_STACK_SIZE can be overridden to be larger or smaller
+ *
+ * ARM Custom Memory layout notes:
+ * -Heap can be explicitly placed by defining both HEAP_START and HEAP_SIZE
+ * -Interrupt stack can be explicitly placed by defining both ISR_STACK_START and ISR_STACK_SIZE
+ *
+ */
+
+#include <stdlib.h>
+
+#include "cmsis.h"
+#include "mbed_rtx.h"
+#include "mbed_rtos_storage.h"
+#include "cmsis_os2.h"
+#include "mbed_toolchain.h"
+#include "mbed_error.h"
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
+#include <DLib_Threads.h>
+#endif
+/* Heap limits - only used if set */
+extern unsigned char *mbed_heap_start;
+extern uint32_t mbed_heap_size;
+
+unsigned char *mbed_stack_isr_start = 0;
+uint32_t mbed_stack_isr_size = 0;
+
+WEAK void mbed_main(void);
+void pre_main (void);
+
+osThreadAttr_t _main_thread_attr;
+
+/** The main thread's stack size can be configured by the application, if not explicitly specified it'll default to 4K */
+#ifndef MBED_CONF_APP_MAIN_STACK_SIZE
+#define MBED_CONF_APP_MAIN_STACK_SIZE 4096
+#endif
+MBED_ALIGN(8) char _main_stack[MBED_CONF_APP_MAIN_STACK_SIZE];
+mbed_rtos_storage_thread_t _main_obj;
+
+osMutexId_t               singleton_mutex_id;
+mbed_rtos_storage_mutex_t singleton_mutex_obj;
+osMutexAttr_t             singleton_mutex_attr;
+
+/*
+ * Sanity check values
+ */
+#if defined(__ICCARM__) &&                                  \
+    (defined(HEAP_START) || defined(HEAP_SIZE) ||           \
+     defined(ISR_STACK_START) && defined(ISR_STACK_SIZE))
+    #error "No custom layout allowed for IAR. Use .icf file instead"
+#endif
+#if defined(HEAP_START) && !defined(HEAP_SIZE)
+    #error "HEAP_SIZE must be defined if HEAP_START is defined"
+#endif
+#if defined(ISR_STACK_START) && !defined(ISR_STACK_SIZE)
+    #error "ISR_STACK_SIZE must be defined if ISR_STACK_START is defined"
+#endif
+#if defined(HEAP_SIZE) && !defined(HEAP_START)
+    #error "HEAP_START must be defined if HEAP_SIZE is defined"
+#endif
+
+/* IAR - INITIAL_SP and HEAP_START ignored as described in Memory layout notes above
+ */
+#if !defined(__ICCARM__) && !defined(INITIAL_SP) && !defined(HEAP_START)
+    #error "no target defined"
+#endif
+
+/* Interrupt stack and heap always defined for IAR
+ * Main thread defined here
+ */
+#if defined(__ICCARM__)
+    #pragma section="CSTACK"
+    #pragma section="HEAP"
+    #define HEAP_START          ((unsigned char*)__section_begin("HEAP"))
+    #define HEAP_SIZE           ((uint32_t)__section_size("HEAP"))
+    #define ISR_STACK_START     ((unsigned char*)__section_begin("CSTACK"))
+    #define ISR_STACK_SIZE      ((uint32_t)__section_size("CSTACK"))
+#endif
+
+/* Define heap region if it has not been defined already */
+#if !defined(HEAP_START)
+    #if defined(__ICCARM__)
+        #error "Heap should already be defined for IAR"
+    #elif defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+        extern uint32_t          Image$$RW_IRAM1$$ZI$$Limit[];
+        #define HEAP_START      ((unsigned char*)Image$$RW_IRAM1$$ZI$$Limit)
+        #define HEAP_SIZE       ((uint32_t)((uint32_t)INITIAL_SP - (uint32_t)HEAP_START))
+    #elif defined(__GNUC__)
+        extern uint32_t         __end__[];
+        #define HEAP_START      ((unsigned char*)__end__)
+        #define HEAP_SIZE       ((uint32_t)((uint32_t)INITIAL_SP - (uint32_t)HEAP_START))
+    #endif
+#endif
+
+/* Define stack sizes if they haven't been set already */
+#if !defined(ISR_STACK_SIZE)
+    #define ISR_STACK_SIZE ((uint32_t)1024)
+#endif
+
+/*
+ * mbed_set_stack_heap purpose is to set the following variables:
+ * -mbed_heap_start
+ * -mbed_heap_size
+ * -mbed_stack_isr_start
+ * -mbed_stack_isr_size
+ */
+void mbed_set_stack_heap(void) {
+
+    unsigned char *free_start = HEAP_START;
+    uint32_t free_size = HEAP_SIZE;
+
+#ifdef ISR_STACK_START
+    /* Interrupt stack explicitly specified */
+    mbed_stack_isr_size = ISR_STACK_SIZE;
+    mbed_stack_isr_start = ISR_STACK_START;
+#else
+    /* Interrupt stack -  reserve space at the end of the free block */
+    mbed_stack_isr_size = ISR_STACK_SIZE < free_size ? ISR_STACK_SIZE : free_size;
+    mbed_stack_isr_start = free_start + free_size - mbed_stack_isr_size;
+    free_size -= mbed_stack_isr_size;
+#endif
+
+    /* Heap - everything else */
+    mbed_heap_size = free_size;
+    mbed_heap_start = free_start;
+}
+
+static void mbed_cpy_nvic(void)
+{
+    /* If vector address in RAM is defined, copy and switch to dynamic vectors. Exceptions for M0 which doesn't have
+    VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
+    responsible for correctly handling the vectors.
+    */
+#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9)
+#ifdef NVIC_RAM_VECTOR_ADDRESS
+    uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
+    uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+    for (int i = 0; i < NVIC_NUM_VECTORS; i++) {
+        vectors[i] = old_vectors[i];
+    }
+    SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+#endif /* NVIC_RAM_VECTOR_ADDRESS */
+#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */
+}
+
+/* mbed_main is a function that is called before main()
+ * mbed_sdk_init() is also a function that is called before main(), but unlike
+ * mbed_main(), it is not meant for user code, but for the SDK itself to perform
+ * initializations before main() is called.
+ */
+WEAK void mbed_main(void) {
+
+}
+
+/* This function can be implemented by the target to perform higher level target initialization, before the mbed OS or
+ * RTX is started.
+ */
+void mbed_sdk_init(void);
+WEAK void mbed_sdk_init(void) {
+}
+
+void mbed_start_main(void)
+{
+    _main_thread_attr.stack_mem = _main_stack;
+    _main_thread_attr.stack_size = sizeof(_main_stack);
+    _main_thread_attr.cb_size = sizeof(_main_obj);
+    _main_thread_attr.cb_mem = &_main_obj;
+    _main_thread_attr.priority = osPriorityNormal;
+    _main_thread_attr.name = "main_thread";
+    osThreadId_t result = osThreadNew((osThreadFunc_t)pre_main, NULL, &_main_thread_attr);
+    if ((void *)result == NULL) {
+        error("Pre main thread not created");
+    }
+
+    osKernelStart();
+}
+
+/******************** Toolchain specific code ********************/
+
+#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+
+/* Common for both ARMC and MICROLIB */
+int $Super$$main(void);
+int $Sub$$main(void) {
+    mbed_main();
+    return $Super$$main();
+}
+
+#if defined (__MICROLIB)  /******************** MICROLIB ********************/
+
+int main(void);
+void _main_init (void) __attribute__((section(".ARM.Collect$$$$000000FF")));
+void $Super$$__cpp_initialize__aeabi_(void);
+
+void _main_init (void) {
+    mbed_set_stack_heap();
+    /* Copy the vector table to RAM only if uVisor is not in use. */
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+    mbed_cpy_nvic();
+#endif
+    mbed_sdk_init();
+    osKernelInitialize();
+    mbed_start_main();
+    for (;;);
+}
+
+void $Sub$$__cpp_initialize__aeabi_(void)
+{
+    /* This should invoke C++ initializers prior _main_init, we keep this empty and
+     * invoke them after _main_init, when the RTX is already initilized.
+     */
+}
+
+void pre_main()
+{
+    singleton_mutex_attr.name = "singleton_mutex";
+    singleton_mutex_attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    singleton_mutex_attr.cb_size = sizeof(singleton_mutex_obj);
+    singleton_mutex_attr.cb_mem = &singleton_mutex_obj;
+    singleton_mutex_id = osMutexNew(&singleton_mutex_attr);
+
+    $Super$$__cpp_initialize__aeabi_();
+    main();
+}
+
+#else /******************** ARMC ********************/
+
+#include <rt_misc.h>
+extern __value_in_regs struct __argc_argv __rt_lib_init(unsigned heapbase, unsigned heaptop);
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(void);
+extern void _platform_post_stackheap_init (void);
+extern int main(int argc, char* argv[]);
+
+void pre_main (void)
+{
+    singleton_mutex_attr.name = "singleton_mutex";
+    singleton_mutex_attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    singleton_mutex_attr.cb_size = sizeof(singleton_mutex_obj);
+    singleton_mutex_attr.cb_mem = &singleton_mutex_obj;
+    singleton_mutex_id = osMutexNew(&singleton_mutex_attr);
+
+    __rt_lib_init((unsigned)mbed_heap_start, (unsigned)(mbed_heap_start + mbed_heap_size));
+
+    main(0, NULL);
+}
+
+/* The single memory model is checking for stack collision at run time, verifing
+   that the heap pointer is underneath the stack pointer.
+   With the RTOS there is not only one stack above the heap, there are multiple
+   stacks and some of them are underneath the heap pointer.
+*/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+__asm(".global __use_two_region_memory\n\t");
+__asm(".global __use_no_semihosting\n\t");
+#else
+#pragma import(__use_two_region_memory)
+#endif
+
+/* Called by the C library */
+void __rt_entry (void) {
+    __user_setup_stackheap();
+    mbed_set_stack_heap();
+    /* Copy the vector table to RAM only if uVisor is not in use. */
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+    mbed_cpy_nvic();
+#endif
+    mbed_sdk_init();
+    _platform_post_stackheap_init();
+    mbed_start_main();
+}
+
+typedef void *mutex;
+
+/* ARM toolchain requires dynamically created mutexes to enforce thread safety. There's
+   up to 8 static mutexes, protecting atexit, signalinit, stdin, stdout, stderr, stream_list,
+   fp_trap_init and the heap. Additionally for each call to fopen one extra mutex will be
+   created.
+   mbed OS provides a RTX pool for 8 mutexes, to satisfy the static requirements. All
+   additional mutexes will be allocated on the heap. We can't use the heap allocation for
+   all the required mutexes, as the heap operations also require a mutex. We don't need to
+   worry about freeing the allocated memory as library mutexes are only freed when the
+   application finishes executing.
+ */
+int _mutex_initialize(mutex *m)
+{
+    osMutexAttr_t attr;
+    memset(&attr, 0, sizeof(attr));
+    attr.name = "ARM toolchain mutex";
+    attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+
+    *m = osMutexNew(&attr);
+    if (*m != NULL) {
+        return 1;
+    }
+
+    /* Mutex pool exhausted, try using HEAP */
+    attr.cb_size = sizeof(mbed_rtos_storage_mutex_t);
+    attr.cb_mem = (void*)malloc(attr.cb_size);
+    if (attr.cb_mem == NULL) {
+        osRtxErrorNotify(osRtxErrorClibSpace, m);
+        return 0;
+    }
+
+    *m = osMutexNew(&attr);
+    if (*m == NULL) {
+        osRtxErrorNotify(osRtxErrorClibMutex, m);
+        return 0;
+    }
+
+    return 1;
+}
+
+#endif /* ARMC */
+#elif defined (__GNUC__) /******************** GCC ********************/
+
+extern int main(int argc, char* argv[]);
+extern void __libc_init_array (void);
+extern int __real_main(void);
+
+osMutexId_t               malloc_mutex_id;
+mbed_rtos_storage_mutex_t malloc_mutex_obj;
+osMutexAttr_t             malloc_mutex_attr;
+
+osMutexId_t               env_mutex_id;
+mbed_rtos_storage_mutex_t env_mutex_obj;
+osMutexAttr_t             env_mutex_attr;
+
+#ifdef  FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+#endif/* FEATURE_UVISOR */
+
+int __wrap_main(void) {
+    mbed_main();
+    return __real_main();
+}
+
+void pre_main(void)
+{
+    singleton_mutex_attr.name = "singleton_mutex";
+    singleton_mutex_attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    singleton_mutex_attr.cb_size = sizeof(singleton_mutex_obj);
+    singleton_mutex_attr.cb_mem = &singleton_mutex_obj;
+    singleton_mutex_id = osMutexNew(&singleton_mutex_attr);
+
+    malloc_mutex_attr.name = "malloc_mutex";
+    malloc_mutex_attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    malloc_mutex_attr.cb_size = sizeof(malloc_mutex_obj);
+    malloc_mutex_attr.cb_mem = &malloc_mutex_obj;
+    malloc_mutex_id = osMutexNew(&malloc_mutex_attr);
+
+    env_mutex_attr.name = "env_mutex";
+    env_mutex_attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    env_mutex_attr.cb_size = sizeof(env_mutex_obj);
+    env_mutex_attr.cb_mem = &env_mutex_obj;
+    env_mutex_id = osMutexNew(&env_mutex_attr);
+
+    __libc_init_array();
+
+    main(0, NULL);
+}
+
+void software_init_hook(void)
+{
+    mbed_set_stack_heap();
+    /* Copy the vector table to RAM only if uVisor is not in use. */
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+    mbed_cpy_nvic();
+#endif
+    mbed_sdk_init();
+    osKernelInitialize();
+    /* uvisor_lib_init calls RTOS functions, so must be called after the RTOS has
+     * been initialized. */
+#ifdef   FEATURE_UVISOR
+    int return_code;
+
+    return_code = uvisor_lib_init();
+    if (return_code) {
+        mbed_die();
+    }
+#endif/* FEATURE_UVISOR */
+    mbed_start_main();
+}
+
+/* Opaque declaration of _reent structure */
+struct _reent;
+
+void __rtos_malloc_lock( struct _reent *_r )
+{
+    osMutexAcquire(malloc_mutex_id, osWaitForever);
+}
+
+void __rtos_malloc_unlock( struct _reent *_r )
+{
+    osMutexRelease(malloc_mutex_id);
+}
+
+void __rtos_env_lock( struct _reent *_r )
+{
+    osMutexAcquire(env_mutex_id, osWaitForever);
+}
+
+void __rtos_env_unlock( struct _reent *_r )
+{
+    osMutexRelease(env_mutex_id);
+}
+
+#endif
+
+#if defined(__ICCARM__) /******************** IAR ********************/
+
+extern void* __vector_table;
+extern int  __low_level_init(void);
+extern void __iar_data_init3(void);
+extern __weak void __iar_init_core( void );
+extern __weak void __iar_init_vfp( void );
+extern void __iar_dynamic_initialization(void);
+extern void mbed_sdk_init(void);
+extern int main(void);
+extern void exit(int arg);
+
+static uint8_t low_level_init_needed;
+
+void pre_main(void)
+{
+    singleton_mutex_attr.name = "singleton_mutex";
+    singleton_mutex_attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    singleton_mutex_attr.cb_size = sizeof(singleton_mutex_obj);
+    singleton_mutex_attr.cb_mem = &singleton_mutex_obj;
+    singleton_mutex_id = osMutexNew(&singleton_mutex_attr);
+
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
+    __iar_Initlocks();
+#endif
+
+    if (low_level_init_needed) {
+        __iar_dynamic_initialization();
+    }
+
+    mbed_main();
+    main();
+}
+
+#pragma required=__vector_table
+void __iar_program_start( void )
+{
+    __iar_init_core();
+    __iar_init_vfp();
+
+    uint8_t low_level_init_needed_local;
+
+    low_level_init_needed_local = __low_level_init();
+    if (low_level_init_needed_local) {
+        __iar_data_init3();
+
+    /* Copy the vector table to RAM only if uVisor is not in use. */
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+    mbed_cpy_nvic();
+#endif
+    mbed_sdk_init();
+  }
+
+  mbed_set_stack_heap();
+
+  /* Store in a global variable after RAM has been initialized */
+  low_level_init_needed = low_level_init_needed_local;
+
+  osKernelInitialize();
+
+  mbed_start_main();
+}
+
+/* Thread safety */
+static osMutexId_t               std_mutex_id_sys[_MAX_LOCK] = {0};
+static mbed_rtos_storage_mutex_t std_mutex_sys[_MAX_LOCK] = {0};
+#define _FOPEN_MAX 10
+static osMutexId_t               std_mutex_id_file[_FOPEN_MAX] = {0};
+static mbed_rtos_storage_mutex_t std_mutex_file[_FOPEN_MAX] = {0};
+
+void __iar_system_Mtxinit(__iar_Rmtx *mutex) /* Initialize a system lock */
+{
+    osMutexAttr_t attr;
+    uint32_t index;
+    for (index = 0; index < _MAX_LOCK; index++) {
+        if (0 == std_mutex_id_sys[index]) {
+            attr.name = "system_mutex";
+            attr.cb_mem = &std_mutex_sys[index];
+            attr.cb_size = sizeof(std_mutex_sys[index]);
+            attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+            std_mutex_id_sys[index] = osMutexNew(&attr);
+            *mutex = (__iar_Rmtx*)&std_mutex_id_sys[index];
+            return;
+        }
+    }
+
+    /* This should never happen */
+    error("Not enough mutexes\n");
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *mutex) /* Destroy a system lock */
+{
+    osMutexDelete(*(osMutexId_t*)*mutex);
+    *mutex = 0;
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *mutex) /* Lock a system lock */
+{
+    osMutexAcquire(*(osMutexId_t*)*mutex, osWaitForever);
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *mutex) /* Unlock a system lock */
+{
+    osMutexRelease(*(osMutexId_t*)*mutex);
+}
+
+void __iar_file_Mtxinit(__iar_Rmtx *mutex) /* Initialize a file lock */
+{
+    osMutexAttr_t attr;
+    uint32_t index;
+    for (index = 0; index < _FOPEN_MAX; index++) {
+        if (0 == std_mutex_id_file[index]) {
+            attr.name = "file_mutex";
+            attr.cb_mem = &std_mutex_file[index];
+            attr.cb_size = sizeof(std_mutex_file[index]);
+            attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+            std_mutex_id_file[index] = osMutexNew(&attr);
+            *mutex = (__iar_Rmtx*)&std_mutex_id_file[index];
+            return;
+        }
+    }
+    /* The variable _FOPEN_MAX needs to be increased */
+    error("Not enough mutexes\n");
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *mutex) /* Destroy a file lock */
+{
+    osMutexDelete(*(osMutexId_t*)*mutex);
+    *mutex = 0;
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *mutex) /* Lock a file lock */
+{
+    osMutexAcquire(*(osMutexId_t*)*mutex, osWaitForever);
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *mutex) /* Unlock a file lock */
+{
+    osMutexRelease(*(osMutexId_t*)*mutex);
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h
new file mode 100755
index 0000000..73df37f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtos1_types.h
@@ -0,0 +1,27 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_RTOS_RTX1_TYPES_H
+#define MBED_RTOS_RTX1_TYPES_H
+
+#include "rtx4/cmsis_os.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h
new file mode 100755
index 0000000..11ebc43
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtos_storage.h
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_RTOS_STORAGE_H
+#define MBED_RTOS_STORAGE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \addtogroup rtos */
+/** @{*/
+
+/** @brief RTOS primitives storage types for RTX
+
+ Types defined in this file should be utilized, when the direct RTOS C API usage is required, to provide backing memory
+ for internal RTX data. Allocated object should be wrapped in attribute struct and passed to os*New call, for details
+ see CMSIS-RTOS2 documentation.
+
+ @note
+ This file breaks abstraction layers and uses RTX internal types, but it limits the contamination to single, RTOS
+ implementation specific, header file, therefore limiting scope of possible changes.
+ */
+
+#include "rtx_lib.h"
+#include "mbed_rtx_conf.h"
+
+typedef os_mutex_t mbed_rtos_storage_mutex_t;
+typedef os_semaphore_t mbed_rtos_storage_semaphore_t;
+typedef os_thread_t mbed_rtos_storage_thread_t;
+typedef os_memory_pool_t mbed_rtos_storage_mem_pool_t;
+typedef os_message_queue_t mbed_rtos_storage_msg_queue_t;
+typedef os_event_flags_t mbed_rtos_storage_event_flags_t;
+typedef os_message_t mbed_rtos_storage_message_t;
+typedef os_timer_t mbed_rtos_storage_timer_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
new file mode 100755
index 0000000..a6cd655
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_conf.h
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_RTX_CONF_H
+#define MBED_RTX_CONF_H
+
+#include "mbed_rtx.h"
+
+/** Any access to RTX5 specific data structures used in common code should be wrapped in ifdef MBED_OS_BACKEND_RTX5 */
+#define MBED_OS_BACKEND_RTX5
+
+/** The thread's stack size can be configured by the application, if not explicitly specified it'll default to 4K */
+#ifndef MBED_CONF_APP_THREAD_STACK_SIZE
+#define MBED_CONF_APP_THREAD_STACK_SIZE 4096
+#endif
+
+#define OS_STACK_SIZE               MBED_CONF_APP_THREAD_STACK_SIZE
+
+#define OS_TIMER_THREAD_STACK_SIZE 768
+#ifndef OS_IDLE_THREAD_STACK_SIZE
+#define OS_IDLE_THREAD_STACK_SIZE  512
+#endif
+
+#define OS_DYNAMIC_MEM_SIZE         0
+
+#if defined(OS_TICK_FREQ) && (OS_TICK_FREQ != 1000)
+#error "OS Tickrate must be 1000 for system timing"
+#endif
+
+#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM toolchain uses up to 8 static mutexes, any further mutexes will be allocated on the heap. */
+#define OS_MUTEX_OBJ_MEM            1
+#define OS_MUTEX_NUM                8
+#endif
+
+#if !defined(OS_STACK_WATERMARK) && (defined(MBED_STACK_STATS_ENABLED) && MBED_STACK_STATS_ENABLED)
+#define OS_STACK_WATERMARK          1
+#endif
+
+/* Run threads unprivileged when uVisor is enabled. */
+#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
+# define OS_PRIVILEGE_MODE           0
+#endif
+
+#endif /* MBED_RTX_CONF_H */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.c
new file mode 100755
index 0000000..882d463
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_handlers.c
@@ -0,0 +1,165 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_compiler.h"
+#include "rtx_os.h"
+#include "rtx_evr.h"
+#include "mbed_rtx.h"
+#include "mbed_error.h"
+#include "RTX_Config.h"
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"              // Keil::Compiler:Event Recorder
+// Used from rtx_evr.c
+#define EvtRtxThreadExit               EventID(EventLevelAPI, 0xF2U, 0x19U)
+#define EvtRtxThreadTerminate          EventID(EventLevelAPI, 0xF2U, 0x1AU)
+#endif
+
+extern void rtos_idle_loop(void);
+extern void thread_terminate_hook(osThreadId_t id);
+
+__NO_RETURN void osRtxIdleThread (void *argument)
+{
+    for (;;) {
+      rtos_idle_loop();
+    }
+}
+
+__NO_RETURN uint32_t osRtxErrorNotify (uint32_t code, void *object_id)
+{
+    osThreadId_t tid = osThreadGetId();
+
+    switch (code) {
+      case osRtxErrorStackUnderflow:
+        // Stack underflow detected for thread (thread_id=object_id)
+        error("CMSIS-RTOS error: Stack underflow (status: 0x%X, task ID: 0x%X, task name: %s)\n\r",
+                code, object_id, osThreadGetName(object_id));
+        break;
+      case osRtxErrorISRQueueOverflow:
+        // ISR Queue overflow detected when inserting object (object_id)
+        error("CMSIS-RTOS error: ISR Queue overflow (status: 0x%X, task ID: 0x%X, object ID: 0x%X)\n\r",
+                code, tid, object_id);
+        break;
+      case osRtxErrorTimerQueueOverflow:
+        // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
+        error("CMSIS-RTOS error: User Timer Callback Queue overflow (status: 0x%X, task ID: 0x%X, timer ID: 0x%X)\n\r",
+                code, tid, object_id);
+        break;
+      case osRtxErrorClibSpace:
+        // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
+        error("CMSIS-RTOS error: STD C/C++ library libspace not available (status: 0x%X, task ID: 0x%X)\n\r",
+                code, tid);
+        break;
+      case osRtxErrorClibMutex:
+        // Standard C/C++ library mutex initialization failed
+        error("CMSIS-RTOS error: STD C/C++ library mutex initialization failed (status: 0x%X, task ID: 0x%X)\n\r",
+                code, tid);
+        break;
+      default:
+        error("CMSIS-RTOS error: Unknown (status: 0x%X, task ID: 0x%X)\n\r", code, tid);
+        break;
+    }
+
+    /* That shouldn't be reached */
+    for (;;) {}
+}
+
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED
+
+static const char* error_msg(int32_t status)
+{
+    switch (status) {
+    case osError:
+        return "Unspecified RTOS error";
+    case osErrorTimeout:
+        return "Operation not completed within the timeout period";
+    case osErrorResource:
+        return "Resource not available";
+    case osErrorParameter:
+        return "Parameter error";
+    case osErrorNoMemory:
+        return "System is out of memory";
+    case osErrorISR:
+        return "Not allowed in ISR context";
+    default:
+        return "Unknown";
+    }
+}
+
+void EvrRtxKernelError (int32_t status)
+{
+    error("Kernel error %i: %s\r\n", status, error_msg(status));
+}
+
+void EvrRtxThreadError (osThreadId_t thread_id, int32_t status)
+{
+    error("Thread %p error %i: %s\r\n", thread_id, status, error_msg(status));
+}
+
+void EvrRtxTimerError (osTimerId_t timer_id, int32_t status)
+{
+    error("Timer %p error %i: %s\r\n", timer_id, status, error_msg(status));
+}
+
+void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status)
+{
+    error("Event %p error %i: %s\r\n", ef_id, status, error_msg(status));
+}
+
+void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status)
+{
+    error("Mutex %p error %i: %s\r\n", mutex_id, status, error_msg(status));
+}
+
+void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status)
+{
+    // Ignore semaphore overflow, the count will saturate with a returned error
+    if (status == osRtxErrorSemaphoreCountLimit) {
+        return;
+    }
+
+    error("Semaphore %p error %i\r\n", semaphore_id, status);
+}
+
+void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status)
+{
+    error("Memory Pool %p error %i\r\n", mp_id, status);
+}
+
+void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status)
+{
+    error("Message Queue %p error %i\r\n", mq_id, status);
+}
+
+#endif
+
+// RTX hook which gets called when a thread terminates, using the event function to call hook
+void EvrRtxThreadExit (void)
+{
+    osThreadId_t thread_id = osThreadGetId();
+    thread_terminate_hook(thread_id);
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE) && defined(RTE_Compiler_EventRecorder))
+    EventRecord2(EvtRtxThreadExit, 0U, 0U);
+#endif
+}
+
+void EvrRtxThreadTerminate (osThreadId_t thread_id)
+{
+    thread_terminate_hook(thread_id);
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE) && defined(RTE_Compiler_EventRecorder))
+    EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U);
+#endif
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp
new file mode 100755
index 0000000..1ea59c5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp
@@ -0,0 +1,238 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "rtos/rtos_idle.h"
+#include "platform/mbed_sleep.h"
+#include "TimerEvent.h"
+#include "lp_ticker_api.h"
+#include "core_cm.h"
+#include "mbed_critical.h"
+#include "mbed_assert.h"
+#include <new>
+#include "rtx_os.h"
+extern "C" {
+#include "rtx_lib.h"
+}
+
+using namespace mbed;
+
+#ifdef MBED_TICKLESS
+
+#if (defined(NO_SYSTICK))
+/**
+ * Return an IRQ number that can be used in the absence of SysTick
+ *
+ * @return Free IRQ number that can be used
+ */
+extern "C" IRQn_Type mbed_get_m0_tick_irqn(void);
+#endif
+
+class RtosTimer : private TimerEvent {
+public:
+    RtosTimer(): TimerEvent(get_lp_ticker_data()), _start_time(0), _tick(0) {
+        _start_time = ticker_read_us(_ticker_data);
+#if (defined(NO_SYSTICK))
+        NVIC_SetVector(mbed_get_m0_tick_irqn(), (uint32_t)SysTick_Handler);
+        NVIC_SetPriority(mbed_get_m0_tick_irqn(), 0xFF); /* RTOS requires lowest priority */
+        NVIC_EnableIRQ(mbed_get_m0_tick_irqn());
+#else
+        // Ensure SysTick has the correct priority as it is still used
+        // to trigger software interrupts on each tick. The period does
+        // not matter since it will never start counting.
+        SysTick_Setup(16);
+#endif
+    };
+
+    /**
+     * Schedule an os tick to fire
+     *
+     * @param delta Tick to fire at relative to current tick
+     */
+    void schedule_tick(uint32_t delta=1) {
+        insert_absolute(_start_time + (_tick + delta) * 1000000 /  OS_TICK_FREQ);
+    }
+
+
+    /**
+     * Prevent any scheduled ticks from triggering
+     */
+    void cancel_tick() {
+        remove();
+    }
+
+    /**
+     * Get the current tick count
+     *
+     * @return The number of ticks since boot. This should match RTX's tick count
+     */
+    uint32_t get_tick() {
+        return _tick & 0xFFFFFFFF;
+    }
+
+    /**
+     * Update the internal tick count
+     *
+     * @return The number of ticks incremented
+     */
+    uint32_t update_tick() {
+        uint64_t new_tick = ticker_read_us(_ticker_data) * OS_TICK_FREQ / 1000000;
+        if (new_tick > _tick) {
+            // Don't update to the current tick. Instead, update to the
+            // previous tick and let the SysTick handler increment it
+            // to the current value. This allows scheduling restart
+            // successfully after the OS is resumed.
+            new_tick--;
+        }
+        uint32_t elapsed_ticks = new_tick - _tick;
+        _tick = new_tick;
+        return elapsed_ticks;
+    }
+
+    /**
+     * Get the time
+     *
+     * @return Current time in microseconds
+     */
+    us_timestamp_t get_time() {
+        return ticker_read_us(_ticker_data);
+    }
+
+    ~RtosTimer() {
+
+    };
+
+protected:
+
+    void handler() {
+#if (defined(NO_SYSTICK))
+        NVIC_SetPendingIRQ(mbed_get_m0_tick_irqn());
+#else
+        SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+#endif
+        _tick++;
+    }
+
+    us_timestamp_t _start_time;
+    uint64_t _tick;
+};
+
+static RtosTimer *os_timer;
+static uint64_t os_timer_data[sizeof(RtosTimer) / 8];
+
+/// Setup System Timer.
+int32_t osRtxSysTimerSetup (void)
+{
+    // Do not use SingletonPtr since this relies on the RTOS
+    if (NULL == os_timer) {
+        os_timer = new (os_timer_data) RtosTimer();
+    }
+    return -1;
+}
+
+/// Enable System Timer.
+void osRtxSysTimerEnable (void)
+{
+    // set to fire interrupt on next tick
+    os_timer->schedule_tick();
+}
+
+/// Disable System Timer.
+void osRtxSysTimerDisable (void)
+{
+    os_timer->cancel_tick();
+}
+
+/// Acknowledge System Timer IRQ.
+void osRtxSysTimerAckIRQ (void)
+{
+    os_timer->schedule_tick();
+}
+
+/// Get System Timer count.
+uint32_t osRtxSysTimerGetCount (void)
+{
+    return os_timer->get_time() & 0xFFFFFFFF;
+}
+
+static void default_idle_hook(void)
+{
+    uint32_t elapsed_ticks = 0;
+
+    core_util_critical_section_enter();
+    uint32_t ticks_to_sleep = svcRtxKernelSuspend();
+    MBED_ASSERT(os_timer->get_tick() == svcRtxKernelGetTickCount());
+    if (ticks_to_sleep) {
+        os_timer->schedule_tick(ticks_to_sleep);
+
+        sleep_manager_lock_deep_sleep();
+        sleep();
+        sleep_manager_unlock_deep_sleep();
+
+        os_timer->cancel_tick();
+        // calculate how long we slept
+        elapsed_ticks = os_timer->update_tick();
+    }
+    svcRtxKernelResume(elapsed_ticks);
+    core_util_critical_section_exit();
+}
+
+#elif defined(FEATURE_UVISOR)
+
+static void default_idle_hook(void)
+{
+    /* uVisor can't sleep. See <https://github.com/ARMmbed/uvisor/issues/420>
+     * for details. */
+}
+
+#else
+
+static void default_idle_hook(void)
+{
+    // critical section to complete sleep with locked deepsleep
+    core_util_critical_section_enter();
+    sleep_manager_lock_deep_sleep();
+    sleep();
+    sleep_manager_unlock_deep_sleep();
+    core_util_critical_section_exit();
+}
+
+#endif // MBED_TICKLESS
+
+static void (*idle_hook_fptr)(void) = &default_idle_hook;
+
+void rtos_attach_idle_hook(void (*fptr)(void))
+{
+    //Attach the specified idle hook, or the default idle hook in case of a NULL pointer
+    if (fptr != NULL) {
+        idle_hook_fptr = fptr;
+    } else {
+        idle_hook_fptr = default_idle_hook;
+    }
+}
+
+extern "C" void rtos_idle_loop(void)
+{
+    //Continuously call the idle hook function pointer
+    while (1) {
+        idle_hook_fptr();
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h
new file mode 100755
index 0000000..4f7ba11
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os.h
@@ -0,0 +1,898 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        10. January 2017
+ * $Revision:    V2.1.0
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h RTX header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedefs
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ * Version 2.0.0
+ *    OS objects creation without macros (dynamic creation and resource allocation):
+ *     - added: osXxxxNew functions which replace osXxxxCreate
+ *     - added: osXxxxAttr_t structures
+ *     - deprecated: osXxxxCreate functions, osXxxxDef_t structures
+ *     - deprecated: osXxxxDef and osXxxx macros
+ *    osStatus codes simplified and renamed to osStatus_t
+ *    osEvent return structure deprecated
+ *    Kernel:
+ *     - added: osKernelInfo_t and osKernelGetInfo
+ *     - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
+ *     - added: osKernelLock, osKernelUnlock
+ *     - added: osKernelSuspend, osKernelResume
+ *     - added: osKernelGetTickCount, osKernelGetTickFreq
+ *     - renamed osKernelSysTick to osKernelGetSysTimerCount
+ *     - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
+ *     - deprecated osKernelSysTickMicroSec
+ *    Thread:
+ *     - extended number of thread priorities
+ *     - renamed osPrioriry to osPrioriry_t
+ *     - replaced osThreadCreate with osThreadNew
+ *     - added: osThreadGetName
+ *     - added: osThreadState_t and osThreadGetState
+ *     - added: osThreadGetStackSize, osThreadGetStackSpace
+ *     - added: osThreadSuspend, osThreadResume
+ *     - added: osThreadJoin, osThreadDetach, osThreadExit
+ *     - added: osThreadGetCount, osThreadEnumerate
+ *     - added: Thread Flags (moved from Signals) 
+ *    Signals:
+ *     - renamed osSignals to osThreadFlags (moved to Thread Flags)
+ *     - changed return value of Set/Clear/Wait functions
+ *     - Clear function limited to current running thread
+ *     - extended Wait function (options)
+ *     - added: osThreadFlagsGet
+ *    Event Flags:
+ *     - added new independent object for handling Event Flags
+ *    Delay and Wait functions:
+ *     - added: osDelayUntil
+ *     - deprecated: osWait
+ *    Timer:
+ *     - replaced osTimerCreate with osTimerNew
+ *     - added: osTimerGetName, osTimerIsRunning
+ *    Mutex:
+ *     - extended: attributes (Recursive, Priority Inherit, Robust)
+ *     - replaced osMutexCreate with osMutexNew
+ *     - renamed osMutexWait to osMutexAcquire
+ *     - added: osMutexGetName, osMutexGetOwner
+ *    Semaphore:
+ *     - extended: maximum and initial token count
+ *     - replaced osSemaphoreCreate with osSemaphoreNew
+ *     - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
+ *     - added: osSemaphoreGetName, osSemaphoreGetCount
+ *    Memory Pool:
+ *     - using osMemoryPool prefix instead of osPool
+ *     - replaced osPoolCreate with osMemoryPoolNew
+ *     - extended osMemoryPoolAlloc (timeout)
+ *     - added: osMemoryPoolGetName
+ *     - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
+ *     - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
+ *     - added: osMemoryPoolDelete
+ *     - deprecated: osPoolCAlloc
+ *    Message Queue:
+ *     - extended: fixed size message instead of a single 32-bit value
+ *     - using osMessageQueue prefix instead of osMessage
+ *     - replaced osMessageCreate with osMessageQueueNew
+ *     - updated: osMessageQueuePut, osMessageQueueGet
+ *     - added: osMessageQueueGetName
+ *     - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
+ *     - added: osMessageQueueGetCount, osMessageQueueGetSpace
+ *     - added: osMessageQueueReset, osMessageQueueDelete
+ *    Mail Queue: 
+ *     - deprecated (superseded by extended Message Queue functionality)
+ * Version 2.1.0
+ *    Support for critical and uncritical sections (nesting safe):
+ *    - updated: osKernelLock, osKernelUnlock
+ *    - added: osKernelRestoreLock
+ *    Updated Thread and Event Flags:
+ *    - changed flags parameter and return type from int32_t to uint32_t
+ *---------------------------------------------------------------------------*/
+ 
+#ifndef CMSIS_OS_H_
+#define CMSIS_OS_H_
+ 
+#define osCMSIS             0x20001U    ///< API version (main[31:16].sub[15:0])
+ 
+#define osCMSIS_RTX         0x50001U    ///< RTOS identification and version (main[31:16].sub[15:0])
+ 
+#define osKernelSystemId   "RTX V5.1"   ///< RTOS identification string
+ 
+#define osFeature_MainThread  0         ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Signals     31U       ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore   65535U    ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait        0         ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick     1         ///< osKernelSysTick functions: 1=available, 0=not available
+#define osFeature_Pool        1         ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MessageQ    1         ///< Message Queues:  1=available, 0=not available
+#define osFeature_MailQ       1         ///< Mail Queues:     1=available, 0=not available
+ 
+#if   defined(__CC_ARM)
+#define os_InRegs __value_in_regs
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define os_InRegs __attribute__((value_in_regs))
+#else
+#define os_InRegs
+#endif
+ 
+#if (osCMSIS >= 0x20000U)
+#include "cmsis_os2.h"
+#else
+#include <stdint.h>
+#include <stddef.h>
+#endif
+#include "rtx_os.h"
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+// ==== Enumerations, structures, defines ====
+ 
+/// Priority values.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osPriorityIdle          = -3,         ///< Priority: idle (lowest)
+  osPriorityLow           = -2,         ///< Priority: low
+  osPriorityBelowNormal   = -1,         ///< Priority: below normal
+  osPriorityNormal        =  0,         ///< Priority: normal (default)
+  osPriorityAboveNormal   = +1,         ///< Priority: above normal
+  osPriorityHigh          = +2,         ///< Priority: high
+  osPriorityRealtime      = +3,         ///< Priority: realtime (highest)
+  osPriorityError         = 0x84,       ///< System cannot determine priority or illegal priority.
+  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osPriority;
+#else
+#define osPriority osPriority_t
+#endif
+
+/// Entry point of a thread.
+typedef void (*os_pthread) (void const *argument);
+ 
+/// Entry point of a timer call back function.
+typedef void (*os_ptimer) (void const *argument);
+ 
+/// Timer type.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osTimerOnce             = 0,          ///< One-shot timer.
+  osTimerPeriodic         = 1           ///< Repeating timer.
+} os_timer_type;
+#else
+#define os_timer_type osTimerType_t
+#endif
+ 
+/// Timeout value.
+#define osWaitForever       0xFFFFFFFFU ///< Wait forever timeout value.
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osOK                    =    0,       ///< Function completed; no error or event occurred.
+  osEventSignal           = 0x08,       ///< Function completed; signal event occurred.
+  osEventMessage          = 0x10,       ///< Function completed; message event occurred.
+  osEventMail             = 0x20,       ///< Function completed; mail event occurred.
+  osEventTimeout          = 0x40,       ///< Function completed; timeout occurred.
+  osErrorParameter        = 0x80,       ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         = 0x81,       ///< Resource not available: a specified resource was not available.
+  osErrorTimeoutResource  = 0xC1,       ///< Resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              = 0x82,       ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     = 0x83,       ///< Function called multiple times from ISR with same object.
+  osErrorPriority         = 0x84,       ///< System cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         = 0x85,       ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            = 0x86,       ///< Value of a parameter is out of range.
+  osErrorOS               = 0xFF,       ///< Unspecified RTOS error: run-time error but no other error message fits.
+  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osStatus;
+#else
+typedef int32_t                  osStatus;
+#define osEventSignal           (0x08)
+#define osEventMessage          (0x10)
+#define osEventMail             (0x20)
+#define osEventTimeout          (0x40)
+#define osErrorOS               osError
+#define osErrorTimeoutResource  osErrorTimeout
+#define osErrorISRRecursive     (-126)
+#define osErrorValue            (-127)
+#define osErrorPriority         (-128)
+#endif
+ 
+ 
+// >>> the following data type definitions may be adapted towards a specific RTOS
+ 
+/// Thread ID identifies the thread.
+#if (osCMSIS < 0x20000U)
+typedef void *osThreadId;
+#else
+#define osThreadId osThreadId_t
+#endif
+ 
+/// Timer ID identifies the timer.
+#if (osCMSIS < 0x20000U)
+typedef void *osTimerId;
+#else
+#define osTimerId osTimerId_t
+#endif
+ 
+/// Mutex ID identifies the mutex.
+#if (osCMSIS < 0x20000U)
+typedef void *osMutexId;
+#else
+#define osMutexId osMutexId_t
+#endif
+ 
+/// Semaphore ID identifies the semaphore.
+#if (osCMSIS < 0x20000U)
+typedef void *osSemaphoreId;
+#else
+#define osSemaphoreId osSemaphoreId_t
+#endif
+ 
+/// Pool ID identifies the memory pool.
+typedef void *osPoolId;
+ 
+/// Message ID identifies the message queue.
+typedef void *osMessageQId;
+ 
+/// Mail ID identifies the mail queue.
+typedef void *osMailQId;
+ 
+ 
+/// Thread Definition structure contains startup information of a thread.
+#if (osCMSIS < 0x20000U)
+typedef struct os_thread_def {
+  os_pthread                 pthread;   ///< start address of thread function
+  osPriority               tpriority;   ///< initial thread priority
+  uint32_t                 instances;   ///< maximum number of instances of that thread function
+  uint32_t                 stacksize;   ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+#else
+typedef struct os_thread_def {
+  os_pthread                 pthread;   ///< start address of thread function
+  osThreadAttr_t                attr;   ///< thread attributes
+} osThreadDef_t;
+#endif
+ 
+/// Timer Definition structure contains timer parameters.
+#if (osCMSIS < 0x20000U)
+typedef struct os_timer_def {
+  os_ptimer                   ptimer;   ///< start address of a timer function
+} osTimerDef_t;
+#else
+typedef struct os_timer_def {
+  os_ptimer                   ptimer;   ///< start address of a timer function
+  osTimerAttr_t                 attr;   ///< timer attributes
+} osTimerDef_t;
+#endif
+ 
+/// Mutex Definition structure contains setup information for a mutex.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mutex_def {
+  uint32_t                     dummy;   ///< dummy value
+} osMutexDef_t;
+#else
+#define osMutexDef_t osMutexAttr_t
+#endif
+ 
+/// Semaphore Definition structure contains setup information for a semaphore.
+#if (osCMSIS < 0x20000U)
+typedef struct os_semaphore_def {
+  uint32_t                     dummy;   ///< dummy value
+} osSemaphoreDef_t;
+#else
+#define osSemaphoreDef_t osSemaphoreAttr_t
+#endif
+ 
+/// Definition structure for memory block allocation.
+#if (osCMSIS < 0x20000U)
+typedef struct os_pool_def {
+  uint32_t                   pool_sz;   ///< number of items (elements) in the pool
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *pool;   ///< pointer to memory for pool
+} osPoolDef_t;
+#else
+typedef struct os_pool_def {
+  uint32_t                   pool_sz;   ///< number of items (elements) in the pool
+  uint32_t                   item_sz;   ///< size of an item
+  osMemoryPoolAttr_t            attr;   ///< memory pool attributes
+} osPoolDef_t;
+#endif
+ 
+/// Definition structure for message queue.
+#if (osCMSIS < 0x20000U)
+typedef struct os_messageQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  void                         *pool;   ///< memory array for messages
+} osMessageQDef_t;
+#else
+typedef struct os_messageQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  osMessageQueueAttr_t          attr;   ///< message queue attributes
+} osMessageQDef_t;
+#endif
+ 
+/// Definition structure for mail queue.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mailQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *pool;   ///< memory array for mail
+} osMailQDef_t;
+#else
+typedef struct os_mailQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *mail;   ///< pointer to mail
+  osMemoryPoolAttr_t         mp_attr;   ///< memory pool attributes
+  osMessageQueueAttr_t       mq_attr;   ///< message queue attributes
+} osMailQDef_t;
+#endif
+ 
+ 
+/// Event structure contains detailed information about an event.
+typedef struct {
+  osStatus                    status;   ///< status code: event or error information
+  union {
+    uint32_t                       v;   ///< message as 32-bit value
+    void                          *p;   ///< message or mail as void pointer
+    int32_t                  signals;   ///< signal flags
+  } value;                              ///< event value
+  union {
+    osMailQId                mail_id;   ///< mail id obtained by \ref osMailCreate
+    osMessageQId          message_id;   ///< message id obtained by \ref osMessageCreate
+  } def;                                ///< event definition
+} osEvent;
+ 
+ 
+//  ==== Kernel Management Functions ====
+ 
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelInitialize (void);
+#endif
+ 
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelStart (void);
+#endif
+ 
+/// Check if the RTOS kernel is already started.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+#if (osCMSIS < 0x20000U)
+int32_t osKernelRunning(void);
+#endif
+ 
+#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0))  // System Timer available
+ 
+/// Get the RTOS kernel system timer counter.
+/// \return RTOS kernel system timer as 32-bit value 
+#if (osCMSIS < 0x20000U)
+uint32_t osKernelSysTick (void);
+#else
+#define  osKernelSysTick osKernelGetSysTimerCount
+#endif
+ 
+/// The RTOS kernel system timer frequency in Hz.
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickFrequency 100000000
+#endif
+ 
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param         microsec     time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+#else
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec *  osKernelGetSysTimerFreq()) / 1000000)
+#endif
+ 
+#endif  // System Timer available
+ 
+ 
+//  ==== Thread Management Functions ====
+ 
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name          name of the thread function.
+/// \param         priority      initial priority of the thread function.
+/// \param         instances     number of possible thread instances.
+/// \param         stacksz       stack size (in bytes) requirements for the thread function.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, stacksz) \
+extern const osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osThreadDef(name, priority, stacksz) \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (1), (stacksz) }
+#else
+#define osThreadDef(name, priority, stacksz) \
+uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(".bss.os.thread.stack"))); \
+static osRtxThread_t os_thread_cb_##name __attribute__((section(".bss.os.thread.cb"))); \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), \
+  { NULL, osThreadDetached, \
+    (&os_thread_cb_##name),\
+    osRtxThreadCbSize, \
+    (stacksz) ? (&os_thread_stack##name) : NULL, \
+    8*((stacksz+7)/8), \
+    (priority), 0U, 0U } }
+#endif
+#endif
+ 
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+#define osThread(name) \
+&os_thread_def_##name
+ 
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+#if (osCMSIS < 0x20000U)
+osThreadId osThreadGetId (void);
+#endif
+ 
+/// Change priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+#endif
+ 
+/// Get current priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+#if (osCMSIS < 0x20000U)
+osPriority osThreadGetPriority (osThreadId thread_id);
+#endif
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadYield (void);
+#endif
+ 
+/// Terminate execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadTerminate (osThreadId thread_id);
+#endif
+ 
+ 
+//  ==== Signal Management ====
+ 
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+ 
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+ 
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flag information or error code.
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osDelay (uint32_t millisec);
+#endif
+ 
+#if (defined (osFeature_Wait) && (osFeature_Wait != 0))  // Generic Wait available
+ 
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+os_InRegs osEvent osWait (uint32_t millisec);
+ 
+#endif  // Generic Wait available
+ 
+ 
+//  ==== Timer Management Functions ====
+ 
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function) \
+extern const osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osTimerDef(name, function) \
+const osTimerDef_t os_timer_def_##name = { (function) }
+#else
+#define osTimerDef(name, function) \
+static osRtxTimer_t os_timer_cb_##name __attribute__((section(".bss.os.timer.cb"))); \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), { NULL, 0U, (&os_timer_cb_##name), osRtxTimerCbSize } }
+#endif
+#endif
+ 
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+#define osTimer(name) \
+&os_timer_def_##name
+ 
+/// Create and Initialize a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+#endif
+ 
+/// Stop a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStop (osTimerId timer_id);
+#endif
+ 
+/// Delete a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerDelete (osTimerId timer_id);
+#endif
+ 
+ 
+//  ==== Mutex Management Functions ====
+ 
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name) \
+extern const osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osMutexDef(name) \
+const osMutexDef_t os_mutex_def_##name = { 0 }
+#else
+#define osMutexDef(name) \
+static osRtxMutex_t os_mutex_cb_##name __attribute__((section(".bss.os.mutex.cb"))); \
+const osMutexDef_t os_mutex_def_##name = \
+{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, (&os_mutex_cb_##name), osRtxMutexCbSize }
+#endif
+#endif
+ 
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+#define osMutex(name) \
+&os_mutex_def_##name
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+ 
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+#else
+#define  osMutexWait osMutexAcquire
+#endif
+ 
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexRelease (osMutexId mutex_id);
+#endif
+ 
+/// Delete a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexDelete (osMutexId mutex_id);
+#endif
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))  // Semaphore available
+ 
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name) \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osSemaphoreDef(name) \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#else
+#define osSemaphoreDef(name) \
+static osRtxSemaphore_t os_semaphore_cb_##name __attribute__((section(".bss.os.semaphore.cb"))); \
+const osSemaphoreDef_t os_semaphore_def_##name = \
+{ NULL, 0U, (&os_semaphore_cb_##name), osRtxSemaphoreCbSize }
+#endif
+#endif
+ 
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+#define osSemaphore(name) \
+&os_semaphore_def_##name
+ 
+/// Create and Initialize a Semaphore object.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         maximum and initial number of available tokens.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+ 
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+ 
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+#endif
+ 
+/// Delete a Semaphore object.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+#endif
+ 
+#endif  // Semaphore available
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+ 
+#if (defined(osFeature_Pool) && (osFeature_Pool != 0))  // Memory Pool available
+ 
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type) \
+extern const osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osPoolDef(name, no, type) \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#else
+#define osPoolDef(name, no, type) \
+static osRtxMemoryPool_t os_mp_cb_##name __attribute__((section(".bss.os.mempool.cb"))); \
+static uint32_t os_mp_data_##name[osRtxMemoryPoolMemSize((no),sizeof(type))/4] __attribute__((section(".bss.os.mempool.mem"))); \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), \
+  { NULL, 0U, (&os_mp_cb_##name), osRtxMemoryPoolCbSize, \
+              (&os_mp_data_##name), sizeof(os_mp_data_##name) } }
+#endif
+#endif
+ 
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+#define osPool(name) \
+&os_pool_def_##name
+ 
+/// Create and Initialize a Memory Pool object.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+ 
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolAlloc (osPoolId pool_id);
+ 
+/// Allocate a memory block from a Memory Pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolCAlloc (osPoolId pool_id);
+ 
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+ 
+#endif  // Memory Pool available
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))  // Message Queue available
+  
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type) \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osMessageQDef(name, queue_sz, type) \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), NULL }
+#else
+#define osMessageQDef(name, queue_sz, type) \
+static osRtxMessageQueue_t os_mq_cb_##name __attribute__((section(".bss.os.msgqueue.cb"))); \
+static uint32_t os_mq_data_##name[osRtxMessageQueueMemSize((queue_sz),sizeof(uint32_t))/4] __attribute__((section(".bss.os.msgqueue.mem"))); \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), \
+  { NULL, 0U, (&os_mq_cb_##name), osRtxMessageQueueCbSize, \
+              (&os_mq_data_##name), sizeof(os_mq_data_##name) } }
+#endif
+#endif
+ 
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+ 
+/// Create and Initialize a Message Queue object.
+/// \param[in]     queue_def     message queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+ 
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+ 
+#endif  // Message Queue available
+ 
+ 
+//  ==== Mail Queue Management Functions ====
+ 
+#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))  // Mail Queue available
+ 
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of mails in the queue.
+/// \param         type          data type of a single mail element.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osMailQDef(name, queue_sz, type) \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof(type), NULL }
+#else
+#define osMailQDef(name, queue_sz, type) \
+static void              *os_mail_p_##name[2]  __attribute__((section(".bss.os"))); \
+static osRtxMemoryPool_t   os_mail_mp_cb_##name __attribute__((section(".bss.os.mempool.cb"))); \
+static osRtxMessageQueue_t os_mail_mq_cb_##name __attribute__((section(".bss.os.msgqueue.cb"))); \
+static uint32_t os_mail_mp_data_##name[osRtxMemoryPoolMemSize  ((queue_sz),sizeof(type) )/4] __attribute__((section(".bss.os.mempool.mem"))); \
+static uint32_t os_mail_mq_data_##name[osRtxMessageQueueMemSize((queue_sz),sizeof(void*))/4] __attribute__((section(".bss.os.msgqueue.mem"))); \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof(type), (&os_mail_p_##name), \
+  { NULL, 0U, (&os_mail_mp_cb_##name), osRtxMemoryPoolCbSize, \
+              (&os_mail_mp_data_##name), sizeof(os_mail_mp_data_##name) }, \
+  { NULL, 0U, (&os_mail_mq_cb_##name), osRtxMessageQueueCbSize, \
+              (&os_mail_mq_data_##name), sizeof(os_mail_mq_data_##name) } }
+#endif
+#endif
+ 
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+#define osMailQ(name) \
+&os_mailQ_def_##name
+ 
+/// Create and Initialize a Mail Queue object.
+/// \param[in]     queue_def     mail queue definition referenced with \ref osMailQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Allocate a memory block for mail from a mail memory pool.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Put a Mail into a Queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to memory with mail to put into a queue.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailPut (osMailQId queue_id, const void *mail);
+ 
+/// Get a Mail from a Queue or timeout if Queue is empty.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+ 
+/// Free a memory block by returning it to a mail memory pool.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+ 
+#endif  // Mail Queue available
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // CMSIS_OS_H_
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.c
new file mode 100755
index 0000000..a68eb0a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx4/cmsis_os1.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        10. January 2017
+ * $Revision:    V1.2
+ *
+ * Project:      CMSIS-RTOS API V1
+ * Title:        cmsis_os_v1.c V1 module file
+ *---------------------------------------------------------------------------*/
+
+#include <string.h>
+#include "cmsis_os.h"
+
+#if (osCMSIS >= 0x20000U) && !defined(os1_Disable)
+
+
+// Thread
+#if !defined(os1_Disable_Thread)
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
+
+  if (thread_def == NULL) {
+    return NULL;
+  }
+  return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);
+}
+#endif
+
+
+// Signals
+
+#if !defined(os1_Disable_Signal)
+
+#define SignalMask ((1U<<osFeature_Signals)-1U)
+
+int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
+  uint32_t flags;
+
+  flags = osThreadFlagsSet(thread_id, (uint32_t)signals);
+  if ((flags & 0x80000000U) != 0U) {
+    return ((int32_t)0x80000000U);
+  }
+  return ((int32_t)(flags & ~((uint32_t)signals)));
+}
+
+int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
+  uint32_t flags;
+
+  if (thread_id != osThreadGetId()) {
+    return ((int32_t)0x80000000U);
+  }
+  flags = osThreadFlagsClear((uint32_t)signals);
+  if ((flags & 0x80000000U) != 0U) {
+    return ((int32_t)0x80000000U);
+  }
+  return ((int32_t)flags);
+}
+
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {
+  osEvent  event;
+  uint32_t flags;
+
+  if (signals != 0) {
+    flags = osThreadFlagsWait((uint32_t)signals, osFlagsWaitAll, millisec);
+  } else {
+    flags = osThreadFlagsWait(SignalMask,        osFlagsWaitAny, millisec);
+  }
+  if ((flags > 0U) && (flags < 0x80000000U)) {
+    event.status = osEventSignal;
+    event.value.signals = (int32_t)flags;
+  } else {
+    switch ((int32_t)flags) {
+      case osErrorResource:
+        event.status = osOK;
+        break;
+      case osErrorTimeout:
+        event.status = osEventTimeout;
+        break;
+      case osErrorParameter:
+        event.status = osErrorValue;
+        break;
+      default:
+        event.status = (osStatus)flags;
+        break;
+    }
+  }
+  return event;
+}
+
+#endif  // Signal
+
+
+// Timer
+#if !defined(os1_Disable_Timer)
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+
+  if (timer_def == NULL) {
+    return NULL;
+  }
+  return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);
+}
+#endif
+
+
+// Mutex
+#if !defined(os1_Disable_Mutex)
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
+
+  if (mutex_def == NULL) {
+    return NULL;
+  }
+  return osMutexNew(mutex_def);
+}
+#endif
+
+
+// Semaphore
+
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) && !defined(os1_Disable_Semaphore)
+
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
+
+  if (semaphore_def == NULL) {
+    return NULL;
+  }
+  return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);
+}
+
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+  osStatus_t status;
+  uint32_t   count;
+
+  status = osSemaphoreAcquire(semaphore_id, millisec);
+  switch (status) {
+    case osOK:
+      count = osSemaphoreGetCount(semaphore_id);
+      return ((int32_t)count + 1);
+    case osErrorResource:
+    case osErrorTimeout:
+      return 0;
+    default:
+      break;
+  }
+  return -1;
+}
+
+#endif  // Semaphore
+
+
+// Memory Pool
+
+#if (defined(osFeature_Pool) && (osFeature_Pool != 0))&& !defined(os1_Disable_Pool)
+
+osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
+
+  if (pool_def == NULL) {
+    return NULL;
+  }
+  return osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr);
+}
+
+void *osPoolAlloc (osPoolId pool_id) {
+  return osMemoryPoolAlloc(pool_id, 0U);
+}
+
+void *osPoolCAlloc (osPoolId pool_id) {
+  void    *block;
+  uint32_t block_size;
+
+  block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);
+  if (block_size == 0U) {
+    return NULL;
+  }
+  block = osMemoryPoolAlloc(pool_id, 0U);
+  if (block != NULL) {
+    memset(block, 0, block_size);
+  }
+  return block;
+}
+
+osStatus osPoolFree (osPoolId pool_id, void *block) {
+  return osMemoryPoolFree(pool_id, block);
+}
+
+#endif  // Memory Pool
+
+
+// Message Queue
+
+#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) && !defined(os1_Disable_MessageQ)
+
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
+  (void)thread_id;
+
+  if (queue_def == NULL) {
+    return NULL;
+  }
+  return osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr);
+}
+
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+  return osMessageQueuePut(queue_id, &info, 0U, millisec);
+}
+
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  osStatus_t status;
+  osEvent    event;
+  uint32_t   message;
+
+  status = osMessageQueueGet(queue_id, &message, NULL, millisec);
+  switch (status) {
+    case osOK:
+      event.status = osEventMessage;
+      event.value.v = message;
+      break;
+    case osErrorResource:
+      event.status = osOK;
+      break;
+    case osErrorTimeout:
+      event.status = osEventTimeout;
+      break;
+    default:
+      event.status = status;
+      break;
+  }
+  return event;
+}
+
+#endif  // Message Queue
+
+
+// Mail Queue
+
+#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) && !defined(os1_Disable_MailQ)
+
+typedef struct os_mail_queue_s {
+  osMemoryPoolId_t   mp_id;
+  osMessageQueueId_t mq_id;
+} os_mail_queue_t;
+
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
+  os_mail_queue_t *ptr;
+  (void)thread_id;
+
+  if (queue_def == NULL) {
+    return NULL;
+  }
+
+  ptr = queue_def->mail;
+  if (ptr == NULL) {
+    return NULL;
+  }
+
+  ptr->mp_id = osMemoryPoolNew  (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);
+  ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);
+  if ((ptr->mp_id == NULL) || (ptr->mq_id == NULL)) {
+    if (ptr->mp_id != NULL) {
+      osMemoryPoolDelete(ptr->mp_id);
+    }
+    if (ptr->mq_id != NULL) {
+      osMessageQueueDelete(ptr->mq_id);
+    }
+    return NULL;
+  }
+
+  return ptr;
+}
+
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+
+  if (ptr == NULL) {
+    return NULL;
+  }
+  return osMemoryPoolAlloc(ptr->mp_id, millisec);
+}
+
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+  void            *block;
+  uint32_t         block_size;
+
+  if (ptr == NULL) {
+    return NULL;
+  }
+  block_size = osMemoryPoolGetBlockSize(ptr->mp_id);
+  if (block_size == 0U) {
+    return NULL;
+  }
+  block = osMemoryPoolAlloc(ptr->mp_id, millisec);
+  if (block != NULL) {
+    memset(block, 0, block_size);
+  }
+
+  return block;
+
+}
+
+osStatus osMailPut (osMailQId queue_id, const void *mail) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+
+  if (ptr == NULL) {
+    return osErrorParameter;
+  }
+  if (mail == NULL) {
+    return osErrorValue;
+  }
+  return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);
+}
+
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+  osStatus_t       status;
+  osEvent          event;
+  void            *mail;
+
+  if (ptr == NULL) {
+    event.status = osErrorParameter;
+    return event;
+  }
+
+  status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);
+  switch (status) {
+    case osOK:
+      event.status = osEventMail;
+      event.value.p = mail;
+      break;
+    case osErrorResource:
+      event.status = osOK;
+      break;
+    case osErrorTimeout:
+      event.status = osEventTimeout;
+      break;
+    default:
+      event.status = status;
+      break;
+  }
+  return event;
+}
+
+osStatus osMailFree (osMailQId queue_id, void *mail) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+
+  if (ptr == NULL) {
+    return osErrorParameter;
+  }
+  if (mail == NULL) {
+    return osErrorValue;
+  }
+  return osMemoryPoolFree(ptr->mp_id, mail);
+}
+
+#endif  // Mail Queue
+
+
+#endif  // osCMSIS
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.c
new file mode 100755
index 0000000..6572cf0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.1.0
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "cmsis_compiler.h"
+#include "rtx_os.h"
+ 
+// OS Idle Thread
+__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
+  (void)argument;
+
+  for (;;) {}
+}
+ 
+// OS Error Callback function
+__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
+  (void)object_id;
+
+  switch (code) {
+    case osRtxErrorStackUnderflow:
+      // Stack underflow detected for thread (thread_id=object_id)
+      break;
+    case osRtxErrorISRQueueOverflow:
+      // ISR Queue overflow detected when inserting object (object_id)
+      break;
+    case osRtxErrorTimerQueueOverflow:
+      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
+      break;
+    case osRtxErrorClibSpace:
+      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
+      break;
+    case osRtxErrorClibMutex:
+      // Standard C/C++ library mutex initialization failed
+      break;
+    default:
+      break;
+  }
+  for (;;) {}
+//return 0U;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h
new file mode 100755
index 0000000..1a0ea44
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/RTX_Config.h
@@ -0,0 +1,384 @@
+/** \addtogroup rtos */
+/** @{*/
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.1.0
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+
+#include "mbed_rtx_conf.h"
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+ 
+// <h>System Configuration
+// =======================
+ 
+//     <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined global dynamic memory size.
+//     <i> Default: 4096
+#ifndef OS_DYNAMIC_MEM_SIZE
+#define OS_DYNAMIC_MEM_SIZE         4096
+#endif
+ 
+//   <o>Kernel Tick Frequency [Hz] <1-1000000>
+//   <i> Defines base time unit for delays and timeouts.
+//   <i> Default: 1000 (1ms tick)
+#ifndef OS_TICK_FREQ
+#define OS_TICK_FREQ                1000
+#endif
+ 
+//   <e>Round-Robin Thread switching
+//   <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN_ENABLE
+#define OS_ROBIN_ENABLE             1
+#endif
+ 
+//     <o>Round-Robin Timeout <1-1000>
+//     <i> Defines how many ticks a thread will execute before a thread switch.
+//     <i> Default: 5
+#ifndef OS_ROBIN_TIMEOUT
+#define OS_ROBIN_TIMEOUT            5
+#endif
+ 
+//   </e>
+ 
+//   <h>Event Recording
+ 
+//     <q>Memory Management
+//     <i> Enables Memory Management events recording.
+#ifndef OS_EVR_MEMORY
+#define OS_EVR_MEMORY               1
+#endif
+ 
+//     <q>Kernel
+//     <i> Enables Kernel events recording.
+#ifndef OS_EVR_KERNEL
+#define OS_EVR_KERNEL               1
+#endif
+ 
+//     <q>Thread
+//     <i> Enables Thread events recording.
+#ifndef OS_EVR_THREAD
+#define OS_EVR_THREAD               1
+#endif
+ 
+//     <q>Timer
+//     <i> Enables Timer events recording.
+#ifndef OS_EVR_TIMER
+#define OS_EVR_TIMER                1
+#endif
+ 
+//     <q>Event Flags
+//     <i> Enables Event Flags events recording.
+#ifndef OS_EVR_EVFLAGS
+#define OS_EVR_EVFLAGS              1
+#endif
+ 
+//     <q>Mutex
+//     <i> Enables Mutex events recording.
+#ifndef OS_EVR_MUTEX
+#define OS_EVR_MUTEX                1
+#endif
+ 
+//     <q>Semaphore
+//     <i> Enables Semaphore events recording.
+#ifndef OS_EVR_SEMAPHORE
+#define OS_EVR_SEMAPHORE            1
+#endif
+ 
+//     <q>Memory Pool
+//     <i> Enables Memory Pool events recording.
+#ifndef OS_EVR_MEMPOOL
+#define OS_EVR_MEMPOOL              1
+#endif
+ 
+//     <q>Message Queue
+//     <i> Enables Message Queue events recording.
+#ifndef OS_EVR_MSGQUEUE
+#define OS_EVR_MSGQUEUE             1
+#endif
+ 
+//   </h>
+ 
+//   <o>ISR FIFO Queue 
+//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
+//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
+//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
+//   <i> RTOS Functions called from ISR store requests to this buffer.
+//   <i> Default: 16 entries
+#ifndef OS_ISR_FIFO_QUEUE
+#define OS_ISR_FIFO_QUEUE           16
+#endif
+ 
+// </h>
+ 
+// <h>Thread Configuration
+// =======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_THREAD_OBJ_MEM
+#define OS_THREAD_OBJ_MEM           0
+#endif
+ 
+//     <o>Number of user Threads <1-1000>
+//     <i> Defines maximum number of user threads that can be active at the same time.
+//     <i> Applies to user threads with system provided memory for control blocks.
+#ifndef OS_THREAD_NUM
+#define OS_THREAD_NUM               1
+#endif
+ 
+//     <o>Number of user Threads with default Stack size <0-1000>
+//     <i> Defines maximum number of user threads with default stack size.
+//     <i> Applies to user threads with zero stack size specified.
+#ifndef OS_THREAD_DEF_STACK_NUM
+#define OS_THREAD_DEF_STACK_NUM     0
+#endif
+ 
+//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
+//     <i> Defines the combined stack size for user threads with user-provided stack size.
+//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.
+//     <i> Default: 0
+#ifndef OS_THREAD_USER_STACK_SIZE
+#define OS_THREAD_USER_STACK_SIZE   0
+#endif
+ 
+//   </e>
+ 
+//   <o>Default Thread Stack size [bytes] <96-1073741824:8>
+//   <i> Defines stack size for threads with zero stack size specified.
+//   <i> Default: 200
+#ifndef OS_STACK_SIZE
+#define OS_STACK_SIZE               200
+#endif
+ 
+//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>
+//   <i> Defines stack size for Idle thread.
+//   <i> Default: 200
+#ifndef OS_IDLE_THREAD_STACK_SIZE
+#define OS_IDLE_THREAD_STACK_SIZE   200
+#endif
+ 
+//   <q>Stack overrun checking
+//   <i> Enable stack overrun checks at thread switch.
+//   <i> Enabling this option increases slightly the execution time of a thread switch.
+#ifndef OS_STACK_CHECK
+#define OS_STACK_CHECK              1
+#endif
+ 
+//   <q>Stack usage watermark
+//   <i> Initialize thread stack with watermark pattern for analyzing stack usage.
+//   <i> Enabling this option increases significantly the execution time of thread creation.
+#ifndef OS_STACK_WATERMARK
+#define OS_STACK_WATERMARK          0
+#endif
+ 
+//   <o>Processor mode for Thread execution 
+//     <0=> Unprivileged mode 
+//     <1=> Privileged mode
+//   <i> Default: Privileged mode
+#ifndef OS_PRIVILEGE_MODE
+#define OS_PRIVILEGE_MODE           1
+#endif
+ 
+// </h>
+ 
+// <h>Timer Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_TIMER_OBJ_MEM
+#define OS_TIMER_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Timer objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_TIMER_NUM
+#define OS_TIMER_NUM                1
+#endif
+ 
+//   </e>
+ 
+//   <o>Timer Thread Priority
+//      <8=> Low
+//     <16=> Below Normal  <24=> Normal  <32=> Above Normal
+//     <40=> High
+//     <48=> Realtime
+//   <i> Defines priority for timer thread
+//   <i> Default: High
+#ifndef OS_TIMER_THREAD_PRIO
+#define OS_TIMER_THREAD_PRIO        40
+#endif
+ 
+//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>
+//   <i> Defines stack size for Timer thread.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 200
+#ifndef OS_TIMER_THREAD_STACK_SIZE
+#define OS_TIMER_THREAD_STACK_SIZE  200
+#endif
+ 
+//   <o>Timer Callback Queue entries <0-256>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 4
+#ifndef OS_TIMER_CB_QUEUE
+#define OS_TIMER_CB_QUEUE           4
+#endif
+ 
+// </h>
+ 
+// <h>Event Flags Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_EVFLAGS_OBJ_MEM
+#define OS_EVFLAGS_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Event Flags objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_EVFLAGS_NUM
+#define OS_EVFLAGS_NUM              1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Mutex Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MUTEX_OBJ_MEM
+#define OS_MUTEX_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Mutex objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MUTEX_NUM
+#define OS_MUTEX_NUM                1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Semaphore Configuration
+// ==========================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_SEMAPHORE_OBJ_MEM
+#define OS_SEMAPHORE_OBJ_MEM        0
+#endif
+ 
+//     <o>Number of Semaphore objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_SEMAPHORE_NUM
+#define OS_SEMAPHORE_NUM            1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Memory Pool Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MEMPOOL_OBJ_MEM
+#define OS_MEMPOOL_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Memory Pool objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MEMPOOL_NUM
+#define OS_MEMPOOL_NUM              1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MEMPOOL_DATA_SIZE
+#define OS_MEMPOOL_DATA_SIZE        0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Message Queue Configuration
+// ==============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MSGQUEUE_OBJ_MEM
+#define OS_MSGQUEUE_OBJ_MEM         0
+#endif
+ 
+//     <o>Number of Message Queue objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MSGQUEUE_NUM
+#define OS_MSGQUEUE_NUM             1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MSGQUEUE_DATA_SIZE
+#define OS_MSGQUEUE_DATA_SIZE       0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// Number of Threads which use standard C/C++ library libspace
+// (when thread specific memory allocation is not used).
+#if (OS_THREAD_OBJ_MEM == 0)
+#define OS_THREAD_LIBSPACE_NUM      4
+#else
+#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM
+#endif
+ 
+//------------- <<< end of configuration section >>> ---------------------------
+ 
+#endif  // RTX_CONFIG_H_
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.S
new file mode 100755
index 0000000..74c8a84
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.S
@@ -0,0 +1,155 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M0 Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CMP      R1,#0
+                BEQ      SVC_ContextSwitch      ; Branch if running thread is deleted
+
+SVC_ContextSave
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+                MOVS     R0,#~0xFFFFFFFD
+                MVNS     R0,R0                  ; Set EXC_RETURN value
+                BX       R0                     ; Exit from handler
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STMIA    R4!,{R0-R3}            ; Store function return values
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_GCC/irq_cm0.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_GCC/irq_cm0.S
new file mode 100755
index 0000000..5362c19
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_GCC/irq_cm0.S
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Cortex-M0 Exception handlers
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+
+        .file    "irq_cm0.S"
+        .syntax  unified
+
+        .equ     I_T_RUN_OFS, 28        // osRtxInfo.thread.run offset
+        .equ     TCB_SP_OFS,  56        // TCB.SP offset
+
+        .section ".rodata"
+        .global  irqRtxLib              // Non weak library reference
+irqRtxLib:
+        .byte    0
+
+
+        .thumb
+        .section ".text"
+        .align   2
+
+
+        .thumb_func
+        .type    SVC_Handler, %function
+        .global  SVC_Handler
+        .fnstart
+        .cantunwind
+SVC_Handler:
+
+        MRS      R0,PSP                 // Get PSP
+        LDR      R1,[R0,#24]            // Load saved PC from stack
+        SUBS     R1,R1,#2               // Point to SVC instruction
+        LDRB     R1,[R1]                // Load SVC number
+        CMP      R1,#0
+        BNE      SVC_User               // Branch if not SVC 0
+
+        PUSH     {R0,LR}                // Save PSP and EXC_RETURN
+        LDMIA    R0,{R0-R3}             // Load function parameters from stack
+        BLX      R7                     // Call service function
+        POP      {R2,R3}                // Restore PSP and EXC_RETURN
+        STMIA    R2!,{R0-R1}            // Store function return values
+        MOV      LR,R3                  // Set EXC_RETURN
+
+SVC_Context:
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDMIA    R3!,{R1,R2}            // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        BEQ      SVC_Exit               // Branch when threads are the same
+
+        CMP      R1,#0
+        BEQ      SVC_ContextSwitch      // Branch if running thread is deleted
+
+SVC_ContextSave:
+        MRS      R0,PSP                 // Get PSP
+        SUBS     R0,R0,#32              // Adjust address
+        STR      R0,[R1,#TCB_SP_OFS];   // Store SP
+        STMIA    R0!,{R4-R7}            // Save R4..R7
+        MOV      R4,R8
+        MOV      R5,R9
+        MOV      R6,R10
+        MOV      R7,R11
+        STMIA    R0!,{R4-R7}            // Save R8..R11
+
+SVC_ContextSwitch:
+        SUBS     R3,R3,#8
+        STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore:
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        ADDS     R0,R0,#16              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R8..R11
+        MOV      R8,R4
+        MOV      R9,R5
+        MOV      R10,R6
+        MOV      R11,R7
+        MSR      PSP,R0                 // Set PSP
+        SUBS     R0,R0,#32              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R4..R7
+
+        MOVS     R0,#~0xFFFFFFFD
+        MVNS     R0,R0                  // Set EXC_RETURN value
+        BX       R0                     // Exit from handler
+
+SVC_Exit:
+        BX       LR                     // Exit from handler
+
+SVC_User:
+        PUSH     {R4,LR}                // Save registers
+        LDR      R2,=osRtxUserSVC       // Load address of SVC table
+        LDR      R3,[R2]                // Load SVC maximum number
+        CMP      R1,R3                  // Check SVC number range
+        BHI      SVC_Done               // Branch if out of range
+
+        LSLS     R1,R1,#2
+        LDR      R4,[R2,R1]             // Load address of SVC function
+
+        LDMIA    R0,{R0-R3}             // Load function parameters from stack
+        BLX      R4                     // Call service function
+        MRS      R4,PSP                 // Get PSP
+        STMIA    R4!,{R0-R3}            // Store function return values
+
+SVC_Done:
+        POP      {R4,PC}                // Return from handler
+
+        .fnend
+        .size    SVC_Handler, .-SVC_Handler
+
+
+        .thumb_func
+        .type    PendSV_Handler, %function
+        .global  PendSV_Handler
+        .fnstart
+        .cantunwind
+PendSV_Handler:
+
+        PUSH     {R0,LR}                // Save EXC_RETURN
+        BL       osRtxPendSV_Handler    // Call osRtxPendSV_Handler
+        POP      {R0,R1}                // Restore EXC_RETURN
+        MOV      LR,R1                  // Set EXC_RETURN
+        B        SVC_Context
+
+        .fnend
+        .size    PendSV_Handler, .-PendSV_Handler
+
+
+        .thumb_func
+        .type    SysTick_Handler, %function
+        .global  SysTick_Handler
+        .fnstart
+        .cantunwind
+SysTick_Handler:
+
+        PUSH     {R0,LR}                // Save EXC_RETURN
+        BL       osRtxTick_Handler      // Call osRtxTick_Handler
+        POP      {R0,R1}                // Restore EXC_RETURN
+        MOV      LR,R1                  // Set EXC_RETURN
+        B        SVC_Context
+
+        .fnend
+        .size    SysTick_Handler, .-SysTick_Handler
+
+
+        .end
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.S
new file mode 100755
index 0000000..023aae3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.S
@@ -0,0 +1,149 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M0 Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+                NAME    irq_cm0.s
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+
+
+                PRESERVE8
+                SECTION .rodata:DATA:NOROOT(2)
+
+
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                THUMB
+                SECTION .text:CODE:NOROOT(2)
+
+
+SVC_Handler     
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CMP      R1,#0
+                BEQ      SVC_ContextSwitch      ; Branch if running thread is deleted
+
+SVC_ContextSave
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+                MOVS     R0,#~0xFFFFFFFD
+                MVNS     R0,R0                  ; Set EXC_RETURN value
+                BX       R0                     ; Exit from handler
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STMIA    R4!,{R0-R3}            ; Store function return values
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+
+PendSV_Handler  
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+
+SysTick_Handler 
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.S
new file mode 100755
index 0000000..74c8a84
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.S
@@ -0,0 +1,155 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M0 Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CMP      R1,#0
+                BEQ      SVC_ContextSwitch      ; Branch if running thread is deleted
+
+SVC_ContextSave
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+                MOVS     R0,#~0xFFFFFFFD
+                MVNS     R0,R0                  ; Set EXC_RETURN value
+                BX       R0                     ; Exit from handler
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STMIA    R4!,{R0-R3}            ; Store function return values
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_GCC/irq_cm0.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_GCC/irq_cm0.S
new file mode 100755
index 0000000..5362c19
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_GCC/irq_cm0.S
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Cortex-M0 Exception handlers
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+
+        .file    "irq_cm0.S"
+        .syntax  unified
+
+        .equ     I_T_RUN_OFS, 28        // osRtxInfo.thread.run offset
+        .equ     TCB_SP_OFS,  56        // TCB.SP offset
+
+        .section ".rodata"
+        .global  irqRtxLib              // Non weak library reference
+irqRtxLib:
+        .byte    0
+
+
+        .thumb
+        .section ".text"
+        .align   2
+
+
+        .thumb_func
+        .type    SVC_Handler, %function
+        .global  SVC_Handler
+        .fnstart
+        .cantunwind
+SVC_Handler:
+
+        MRS      R0,PSP                 // Get PSP
+        LDR      R1,[R0,#24]            // Load saved PC from stack
+        SUBS     R1,R1,#2               // Point to SVC instruction
+        LDRB     R1,[R1]                // Load SVC number
+        CMP      R1,#0
+        BNE      SVC_User               // Branch if not SVC 0
+
+        PUSH     {R0,LR}                // Save PSP and EXC_RETURN
+        LDMIA    R0,{R0-R3}             // Load function parameters from stack
+        BLX      R7                     // Call service function
+        POP      {R2,R3}                // Restore PSP and EXC_RETURN
+        STMIA    R2!,{R0-R1}            // Store function return values
+        MOV      LR,R3                  // Set EXC_RETURN
+
+SVC_Context:
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDMIA    R3!,{R1,R2}            // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        BEQ      SVC_Exit               // Branch when threads are the same
+
+        CMP      R1,#0
+        BEQ      SVC_ContextSwitch      // Branch if running thread is deleted
+
+SVC_ContextSave:
+        MRS      R0,PSP                 // Get PSP
+        SUBS     R0,R0,#32              // Adjust address
+        STR      R0,[R1,#TCB_SP_OFS];   // Store SP
+        STMIA    R0!,{R4-R7}            // Save R4..R7
+        MOV      R4,R8
+        MOV      R5,R9
+        MOV      R6,R10
+        MOV      R7,R11
+        STMIA    R0!,{R4-R7}            // Save R8..R11
+
+SVC_ContextSwitch:
+        SUBS     R3,R3,#8
+        STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore:
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        ADDS     R0,R0,#16              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R8..R11
+        MOV      R8,R4
+        MOV      R9,R5
+        MOV      R10,R6
+        MOV      R11,R7
+        MSR      PSP,R0                 // Set PSP
+        SUBS     R0,R0,#32              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R4..R7
+
+        MOVS     R0,#~0xFFFFFFFD
+        MVNS     R0,R0                  // Set EXC_RETURN value
+        BX       R0                     // Exit from handler
+
+SVC_Exit:
+        BX       LR                     // Exit from handler
+
+SVC_User:
+        PUSH     {R4,LR}                // Save registers
+        LDR      R2,=osRtxUserSVC       // Load address of SVC table
+        LDR      R3,[R2]                // Load SVC maximum number
+        CMP      R1,R3                  // Check SVC number range
+        BHI      SVC_Done               // Branch if out of range
+
+        LSLS     R1,R1,#2
+        LDR      R4,[R2,R1]             // Load address of SVC function
+
+        LDMIA    R0,{R0-R3}             // Load function parameters from stack
+        BLX      R4                     // Call service function
+        MRS      R4,PSP                 // Get PSP
+        STMIA    R4!,{R0-R3}            // Store function return values
+
+SVC_Done:
+        POP      {R4,PC}                // Return from handler
+
+        .fnend
+        .size    SVC_Handler, .-SVC_Handler
+
+
+        .thumb_func
+        .type    PendSV_Handler, %function
+        .global  PendSV_Handler
+        .fnstart
+        .cantunwind
+PendSV_Handler:
+
+        PUSH     {R0,LR}                // Save EXC_RETURN
+        BL       osRtxPendSV_Handler    // Call osRtxPendSV_Handler
+        POP      {R0,R1}                // Restore EXC_RETURN
+        MOV      LR,R1                  // Set EXC_RETURN
+        B        SVC_Context
+
+        .fnend
+        .size    PendSV_Handler, .-PendSV_Handler
+
+
+        .thumb_func
+        .type    SysTick_Handler, %function
+        .global  SysTick_Handler
+        .fnstart
+        .cantunwind
+SysTick_Handler:
+
+        PUSH     {R0,LR}                // Save EXC_RETURN
+        BL       osRtxTick_Handler      // Call osRtxTick_Handler
+        POP      {R0,R1}                // Restore EXC_RETURN
+        MOV      LR,R1                  // Set EXC_RETURN
+        B        SVC_Context
+
+        .fnend
+        .size    SysTick_Handler, .-SysTick_Handler
+
+
+        .end
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.S
new file mode 100755
index 0000000..023aae3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.S
@@ -0,0 +1,149 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M0 Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+                NAME    irq_cm0.s
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+
+
+                PRESERVE8
+                SECTION .rodata:DATA:NOROOT(2)
+
+
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                THUMB
+                SECTION .text:CODE:NOROOT(2)
+
+
+SVC_Handler     
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CMP      R1,#0
+                BEQ      SVC_ContextSwitch      ; Branch if running thread is deleted
+
+SVC_ContextSave
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+                MOVS     R0,#~0xFFFFFFFD
+                MVNS     R0,R0                  ; Set EXC_RETURN value
+                BX       R0                     ; Exit from handler
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDMIA    R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STMIA    R4!,{R0-R3}            ; Store function return values
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+
+PendSV_Handler  
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+
+SysTick_Handler 
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        SVC_Context
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S
new file mode 100755
index 0000000..41e4beb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S
@@ -0,0 +1,298 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Baseline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+I_T_RUN_OFS     EQU      28                     ; osInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      SVC_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+SVC_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+Sys_Context     PROC
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      Sys_ContextExit        ; Branch when threads are the same
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+                LSLS     R7,R7,#25              ; Check domain of interrupted thread
+                BMI      Sys_ContextSave1       ; Branch if secure
+                MRS      R0,PSP                 ; Get PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                B        Sys_ContextSave2
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+Sys_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+Sys_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust offset
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      Sys_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+Sys_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                ALIGN
+                ENDP
+
+
+                END
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_GCC/irq_armv8mbl.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_GCC/irq_armv8mbl.S
new file mode 100755
index 0000000..1b6b119
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_GCC/irq_armv8mbl.S
@@ -0,0 +1,302 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Baseline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+        .file    "irq_armv8mbl.S"
+        .syntax  unified
+
+        .equ     I_T_RUN_OFS, 28        // osRtxInfo.thread.run offset
+        .equ     TCB_SM_OFS,  48        // TCB.stack_mem offset
+        .equ     TCB_SP_OFS,  56        // TCB.SP offset
+        .equ     TCB_SF_OFS,  34        // TCB.stack_frame offset
+        .equ     TCB_TZM_OFS, 64        // TCB.tz_memory offset
+
+        .section ".rodata"
+        .global  irqRtxLib              // Non weak library reference
+irqRtxLib:
+        .byte    0
+
+
+        .thumb
+        .section ".text"
+        .align   2
+
+
+        .thumb_func
+        .type    SVC_Handler, %function
+        .global  SVC_Handler
+        .fnstart
+        .cantunwind
+SVC_Handler:
+        MRS      R0,PSP                 // Get PSP
+        LDR      R1,[R0,#24]            // Load saved PC from stack
+        SUBS     R1,R1,#2               // Point to SVC instruction
+        LDRB     R1,[R1]                // Load SVC number
+        CMP      R1,#0
+        BNE      SVC_User               // Branch if not SVC 0
+
+        PUSH     {R0,LR}                // Save PSP and EXC_RETURN
+        LDM      R0,{R0-R3}             // Load function parameters from stack
+        BLX      R7                     // Call service function
+        POP      {R2,R3}                // Restore PSP and EXC_RETURN
+        STMIA    R2!,{R0-R1}            // Store function return values
+        MOV      LR,R3                  // Set EXC_RETURN
+
+SVC_Context:
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDMIA    R3!,{R1,R2}            // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        BEQ      SVC_Exit               // Branch when threads are the same
+
+        CBZ      R1,SVC_ContextSwitch   // Branch if running thread is deleted
+
+SVC_ContextSave:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,SVC_ContextSave1    // Branch if there is no secure context
+        PUSH     {R1,R2,R3,R7}          // Save registers
+        MOV      R7,LR                  // Get EXC_RETURN
+        BL       TZ_StoreContext_S      // Store secure context
+        MOV      LR,R7                  // Set EXC_RETURN
+        POP      {R1,R2,R3,R7}          // Restore registers
+#endif
+
+SVC_ContextSave1:
+        MRS      R0,PSP                 // Get PSP
+        SUBS     R0,R0,#32              // Adjust PSP
+        STR      R0,[R1,#TCB_SP_OFS]    // Store SP
+        STMIA    R0!,{R4-R7}            // Save R4..R7
+        MOV      R4,R8
+        MOV      R5,R9
+        MOV      R6,R10
+        MOV      R7,R11
+        STMIA    R0!,{R4-R7}            // Save R8..R11
+
+SVC_ContextSave2:
+        MOV      R0,LR                  // Get EXC_RETURN
+        ADDS     R1,R1,#TCB_SF_OFS      // Adjust address
+        STRB     R0,[R1]                // Store stack frame information
+
+SVC_ContextSwitch:
+        SUBS     R3,R3,#8               // Adjust address
+        STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,SVC_ContextRestore1 // Branch if there is no secure context
+        PUSH     {R2,R3}                // Save registers
+        BL       TZ_LoadContext_S       // Load secure context
+        POP      {R2,R3}                // Restore registers
+#endif
+
+SVC_ContextRestore1:
+        MOV      R1,R2
+        ADDS     R1,R1,#TCB_SF_OFS      // Adjust address
+        LDRB     R0,[R1]                // Load stack frame information
+        MOVS     R1,#0xFF
+        MVNS     R1,R1                  // R1=0xFFFFFF00
+        ORRS     R0,R1
+        MOV      LR,R0                  // Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+        LSLS     R0,R0,#25              // Check domain of interrupted thread
+        BPL      SVC_ContextRestore2    // Branch if non-secure
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        MSR      PSP,R0                 // Set PSP
+        BX       LR                     // Exit from handler
+#else
+        LDR      R0,[R2,#TCB_SM_OFS]    // Load stack memory base
+        MSR      PSPLIM,R0              // Set PSPLIM
+#endif
+
+SVC_ContextRestore2:
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        ADDS     R0,R0,#16              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R8..R11
+        MOV      R8,R4
+        MOV      R9,R5
+        MOV      R10,R6
+        MOV      R11,R7
+        MSR      PSP,R0                 // Set PSP
+        SUBS     R0,R0,#32              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R4..R7
+
+SVC_Exit:
+        BX       LR                     // Exit from handler
+
+SVC_User:
+        PUSH     {R4,LR}                // Save registers
+        LDR      R2,=osRtxUserSVC       // Load address of SVC table
+        LDR      R3,[R2]                // Load SVC maximum number
+        CMP      R1,R3                  // Check SVC number range
+        BHI      SVC_Done               // Branch if out of range
+
+        LSLS     R1,R1,#2
+        LDR      R4,[R2,R1]             // Load address of SVC function
+
+        LDM      R0,{R0-R3}             // Load function parameters from stack
+        BLX      R4                     // Call service function
+        MRS      R4,PSP                 // Get PSP
+        STR      R0,[R4]                // Store function return value
+
+SVC_Done:
+        POP      {R4,PC}                // Return from handler
+
+        .fnend
+        .size    SVC_Handler, .-SVC_Handler
+
+
+        .thumb_func
+        .type    PendSV_Handler, %function
+        .global  PendSV_Handler
+        .fnstart
+        .cantunwind
+PendSV_Handler:
+
+        PUSH     {R0,LR}                // Save EXC_RETURN
+        BL       osRtxPendSV_Handler    // Call osRtxPendSV_Handler
+        POP      {R0,R1}                // Restore EXC_RETURN
+        MOV      LR,R1                  // Set EXC_RETURN
+        B        Sys_Context
+
+        .fnend
+        .size    PendSV_Handler, .-PendSV_Handler
+
+
+        .thumb_func
+        .type    SysTick_Handler, %function
+        .global  SysTick_Handler
+        .fnstart
+        .cantunwind
+SysTick_Handler:
+
+        PUSH     {R0,LR}                // Save EXC_RETURN
+        BL       osRtxTick_Handler      // Call osRtxTick_Handler
+        POP      {R0,R1}                // Restore EXC_RETURN
+        MOV      LR,R1                  // Set EXC_RETURN
+        B        Sys_Context
+
+        .fnend
+        .size   SysTick_Handler, .-SysTick_Handler
+
+
+        .thumb_func
+        .type    Sys_Context, %function
+        .global  Sys_Context
+        .fnstart
+        .cantunwind
+Sys_Context:
+
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDM      R3!,{R1,R2}            // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        BEQ      Sys_ContextExit        // Branch when threads are the same
+
+Sys_ContextSave:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,Sys_ContextSave1    // Branch if there is no secure context
+        PUSH     {R1,R2,R3,R7}          // Save registers
+        MOV      R7,LR                  // Get EXC_RETURN
+        BL       TZ_StoreContext_S      // Store secure context
+        MOV      LR,R7                  // Set EXC_RETURN
+        POP      {R1,R2,R3,R7}          // Restore registers
+        LSLS     R7,R7,#25              // Check domain of interrupted thread
+        BMI      Sys_ContextSave1       // Branch if secure
+        MRS      R0,PSP                 // Get PSP
+        STR      R0,[R1,#TCB_SP_OFS]    // Store SP
+        B        Sys_ContextSave2
+#endif
+
+Sys_ContextSave1:
+        MRS      R0,PSP                 // Get PSP
+        SUBS     R0,R0,#32              // Adjust address
+        STR      R0,[R1,#TCB_SP_OFS]    // Store SP
+        STMIA    R0!,{R4-R7}            // Save R4..R7
+        MOV      R4,R8
+        MOV      R5,R9
+        MOV      R6,R10
+        MOV      R7,R11
+        STMIA    R0!,{R4-R7}            // Save R8..R11
+
+Sys_ContextSave2:
+        MOV      R0,LR                  // Get EXC_RETURN
+        ADDS     R1,R1,#TCB_SF_OFS      // Adjust address
+        STRB     R0,[R1]                // Store stack frame information
+
+Sys_ContextSwitch:
+        SUBS     R3,R3,#8               // Adjust address
+        STR      R2,[R3]                // osRtxInfo.run: curr = next
+
+Sys_ContextRestore:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,Sys_ContextRestore1 // Branch if there is no secure context
+        PUSH     {R2,R3}                // Save registers
+        BL       TZ_LoadContext_S       // Load secure context
+        POP      {R2,R3}                // Restore registers
+#endif
+
+Sys_ContextRestore1:
+        MOV      R1,R2
+        ADDS     R1,R1,#TCB_SF_OFS      // Adjust offset
+        LDRB     R0,[R1]                // Load stack frame information
+        MOVS     R1,#0xFF
+        MVNS     R1,R1                  // R1=0xFFFFFF00
+        ORRS     R0,R1
+        MOV      LR,R0                  // Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+        LSLS     R0,R0,#25              // Check domain of interrupted thread
+        BPL      Sys_ContextRestore2    // Branch if non-secure
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        MSR      PSP,R0                 // Set PSP
+        BX       LR                     // Exit from handler
+#else
+        LDR      R0,[R2,#TCB_SM_OFS]    // Load stack memory base
+        MSR      PSPLIM,R0              // Set PSPLIM
+#endif
+
+Sys_ContextRestore2:
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        ADDS     R0,R0,#16              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R8..R11
+        MOV      R8,R4
+        MOV      R9,R5
+        MOV      R10,R6
+        MOV      R11,R7
+        MSR      PSP,R0                 // Set PSP
+        SUBS     R0,R0,#32              // Adjust address
+        LDMIA    R0!,{R4-R7}            // Restore R4..R7
+
+Sys_ContextExit:
+        BX       LR                     // Exit from handler
+
+        .fnend
+        .size    Sys_Context, .-Sys_Context
+
+
+        .end
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_IAR/irq_armv8mbl.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_IAR/irq_armv8mbl.S
new file mode 100755
index 0000000..080814f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_IAR/irq_armv8mbl.S
@@ -0,0 +1,288 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Baseline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+                NAME    irq_armv8mbl.s
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                SECTION .rodata:DATA:NOROOT(2)
+
+
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+                THUMB
+                SECTION .text:CODE:NOROOT(2)
+
+
+SVC_Handler
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      SVC_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+SVC_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+
+PendSV_Handler
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+
+SysTick_Handler
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+
+Sys_Context
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      Sys_ContextExit        ; Branch when threads are the same
+
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+                LSLS     R7,R7,#25              ; Check domain of interrupted thread
+                BMI      Sys_ContextSave1       ; Branch if secure
+                MRS      R0,PSP                 ; Get PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                B        Sys_ContextSave2
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+Sys_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+Sys_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust offset
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      Sys_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+Sys_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_ARM/irq_cm3.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_ARM/irq_cm3.S
new file mode 100755
index 0000000..b951538
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_ARM/irq_cm3.S
@@ -0,0 +1,133 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M3 Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CBNZ     R1,SVC_User            ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+
+SVC_ContextSave
+                STMDB    R12!,{R4-R11}          ; Save R4..R11
+                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+                MSR      PSP,R0                 ; Set PSP
+
+                MVN      LR,#~0xFFFFFFFD        ; Set EXC_RETURN value
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_GCC/irq_cm3.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_GCC/irq_cm3.S
new file mode 100755
index 0000000..f8684da
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_GCC/irq_cm3.S
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Cortex-M3 Exception handlers
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+
+        .file    "irq_cm3.S"
+        .syntax  unified
+
+        .equ     I_T_RUN_OFS, 28        // osRtxInfo.thread.run offset
+        .equ     TCB_SP_OFS,  56        // TCB.SP offset
+
+        .section ".rodata"
+        .global  irqRtxLib              // Non weak library reference
+irqRtxLib:
+        .byte    0
+
+
+        .thumb
+        .section ".text"
+        .align   2
+
+
+        .thumb_func
+        .type    SVC_Handler, %function
+        .global  SVC_Handler
+        .fnstart
+        .cantunwind
+SVC_Handler:
+
+        MRS      R0,PSP                 // Get PSP
+        LDR      R1,[R0,#24]            // Load saved PC from stack
+        LDRB     R1,[R1,#-2]            // Load SVC number
+        CBNZ     R1,SVC_User            // Branch if not SVC 0
+
+        PUSH     {R0,LR}                // Save PSP and EXC_RETURN
+        LDM      R0,{R0-R3,R12}         // Load function parameters and address from stack
+        BLX      R12                    // Call service function
+        POP      {R12,LR}               // Restore PSP and EXC_RETURN
+        STM      R12,{R0-R1}            // Store function return values
+
+SVC_Context:
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDM      R3,{R1,R2}             // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        IT       EQ
+        BXEQ     LR                     // Exit when threads are the same
+
+        CBZ      R1,SVC_ContextSwitch   // Branch if running thread is deleted
+
+SVC_ContextSave:
+        STMDB    R12!,{R4-R11}          // Save R4..R11
+        STR      R12,[R1,#TCB_SP_OFS]   // Store SP
+
+SVC_ContextSwitch:
+#ifdef FEATURE_UVISOR
+        CPSID I // The call to the thread switch helper and PSP loading must be atomic.
+#endif
+        /* The call to thread_switch_helper can clobber R2 and R3, but we don't
+         * want to clobber R2 or R3. We can't save R2 and R3 to the stack (as
+         * the stack we save them onto is likely to be inaccessible after the
+         * call to thread_switch_helper). So, we just re-obtain the values from
+         * osRtxInfo again. */
+        BL       thread_switch_helper
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDM      R3,{R1,R2}             // Load osRtxInfo.thread.run: curr & next
+
+        STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore:
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        LDMIA    R0!,{R4-R11}           // Restore R4..R11
+        MSR      PSP,R0                 // Set PSP
+#ifdef FEATURE_UVISOR
+        CPSIE I                         // The PSP has been set. Re-enable interrupts.
+#endif
+        MVN      LR,#~0xFFFFFFFD        // Set EXC_RETURN value
+
+SVC_Exit:
+        BX       LR                     // Exit from handler
+
+SVC_User:
+        PUSH     {R4,LR}                // Save registers
+        LDR      R2,=osRtxUserSVC       // Load address of SVC table
+        LDR      R3,[R2]                // Load SVC maximum number
+        CMP      R1,R3                  // Check SVC number range
+        BHI      SVC_Done               // Branch if out of range
+
+        LDR      R4,[R2,R1,LSL #2]      // Load address of SVC function
+
+        LDM      R0,{R0-R3}             // Load function parameters from stack
+        BLX      R4                     // Call service function
+        MRS      R4,PSP                 // Get PSP
+        STR      R0,[R4]                // Store function return value
+
+SVC_Done:
+        POP      {R4,PC}                // Return from handler
+
+        .fnend
+        .size    SVC_Handler, .-SVC_Handler
+
+
+        .thumb_func
+        .type    PendSV_Handler, %function
+        .global  PendSV_Handler
+        .fnstart
+        .cantunwind
+PendSV_Handler:
+
+        PUSH     {R4,LR}                // Save EXC_RETURN
+        BL       osRtxPendSV_Handler    // Call osRtxPendSV_Handler
+        POP      {R4,LR}                // Restore EXC_RETURN
+        MRS      R12,PSP
+        B        SVC_Context
+
+        .fnend
+        .size    PendSV_Handler, .-PendSV_Handler
+
+
+        .thumb_func
+        .type    SysTick_Handler, %function
+        .global  SysTick_Handler
+        .fnstart
+        .cantunwind
+SysTick_Handler:
+
+        PUSH     {R4,LR}                // Save EXC_RETURN
+        BL       osRtxTick_Handler      // Call osRtxTick_Handler
+        POP      {R4,LR}                // Restore EXC_RETURN
+        MRS      R12,PSP
+        B        SVC_Context
+
+        .fnend
+        .size    SysTick_Handler, .-SysTick_Handler
+
+
+        .end
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_IAR/irq_cm3.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_IAR/irq_cm3.S
new file mode 100755
index 0000000..bfc3b33
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_IAR/irq_cm3.S
@@ -0,0 +1,128 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M3 Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+                NAME    irq_cm3.s
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+
+
+                PRESERVE8
+                SECTION .rodata:DATA:NOROOT(2)
+
+
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                THUMB
+                SECTION .text:CODE:NOROOT(2)
+
+
+SVC_Handler     
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CBNZ     R1,SVC_User            ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                IT       EQ
+                BXEQ     LR                     ; Exit when threads are the same
+
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+
+SVC_ContextSave
+                STMDB    R12!,{R4-R11}          ; Save R4..R11
+                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+                MSR      PSP,R0                 ; Set PSP
+
+                MVN      LR,#~0xFFFFFFFD        ; Set EXC_RETURN value
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+
+PendSV_Handler  
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+
+SysTick_Handler 
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_ARM/irq_armv8mml.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_ARM/irq_armv8mml.S
new file mode 100755
index 0000000..1adeffa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_ARM/irq_armv8mml.S
@@ -0,0 +1,267 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Mainline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+#ifdef __FPU_USED
+                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
+                TST      LR,#0x10               ; Check if extended stack frame
+                BNE      SVC_ContextSwitch
+                LDR      R1,=0xE000EF34         ; FPCCR Address
+                LDR      R0,[R1]                ; Load FPCCR
+                BIC      R0,#1                  ; Clear LSPACT (Lazy state)
+                STR      R0,[R1]                ; Store FPCCR
+                B        SVC_ContextSwitch
+#else
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+#endif
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+SVC_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      SVC_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+SVC_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+Sys_Context     PROC
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                MRSNE    R0,PSP                 ; Get PSP
+                BNE      Sys_ContextSave2       ; Branch if secure
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+Sys_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+Sys_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      Sys_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+Sys_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                ALIGN
+                ENDP
+
+
+                END
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S
new file mode 100755
index 0000000..49f80cf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       ARMv8M Mainline Exception handlers
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+
+        .file    "irq_armv8mml.S"
+        .syntax  unified
+
+        .equ     I_T_RUN_OFS, 28        // osRtxInfo.thread.run offset
+        .equ     TCB_SM_OFS,  48        // TCB.stack_mem offset
+        .equ     TCB_SP_OFS,  56        // TCB.SP offset
+        .equ     TCB_SF_OFS,  34        // TCB.stack_frame offset
+        .equ     TCB_TZM_OFS, 64        // TCB.tz_memory offset
+
+        .section ".rodata"
+        .global  irqRtxLib              // Non weak library reference
+irqRtxLib:
+        .byte    0
+
+
+        .thumb
+        .section ".text"
+        .align   2
+
+
+        .thumb_func
+        .type    SVC_Handler, %function
+        .global  SVC_Handler
+        .fnstart
+        .cantunwind
+SVC_Handler:
+
+        MRS      R0,PSP                 // Get PSP
+        LDR      R1,[R0,#24]            // Load saved PC from stack
+        LDRB     R1,[R1,#-2]            // Load SVC number
+        CMP      R1,#0
+        BNE      SVC_User               // Branch if not SVC 0
+
+        PUSH     {R0,LR}                // Save PSP and EXC_RETURN
+        LDM      R0,{R0-R3,R12}         // Load function parameters and address from stack
+        BLX      R12                    // Call service function
+        POP      {R12,LR}               // Restore PSP and EXC_RETURN
+        STM      R12,{R0-R1}            // Store function return values
+
+SVC_Context:
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDM      R3,{R1,R2}             // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        IT       EQ
+        BXEQ     LR                     // Exit when threads are the same
+
+#ifdef __FPU_USED
+        CBNZ     R1,SVC_ContextSave     // Branch if running thread is not deleted
+        TST      LR,#0x10               // Check if extended stack frame
+        BNE      SVC_ContextSwitch
+        LDR      R1,=0xE000EF34         // FPCCR Address
+        LDR      R0,[R1]                // Load FPCCR
+        BIC      R0,#1                  // Clear LSPACT (Lazy state)
+        STR      R0,[R1]                // Store FPCCR
+        B        SVC_ContextSwitch
+#else
+        CBZ      R1,SVC_ContextSwitch   // Branch if running thread is deleted
+#endif
+
+SVC_ContextSave:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,SVC_ContextSave1    // Branch if there is no secure context
+        PUSH     {R1,R2,R3,LR}          // Save registers and EXC_RETURN
+        BL       TZ_StoreContext_S      // Store secure context
+        POP      {R1,R2,R3,LR}          // Restore registers and EXC_RETURN
+#endif
+
+SVC_ContextSave1:
+        MRS      R0,PSP                 // Get PSP
+        STMDB    R0!,{R4-R11}           // Save R4..R11
+#ifdef __FPU_USED
+        TST      LR,#0x10               // Check if extended stack frame
+        IT       EQ
+        VSTMDBEQ R0!,{S16-S31}          //  Save VFP S16.S31
+#endif
+
+SVC_ContextSave2:
+        STR      R0,[R1,#TCB_SP_OFS]    // Store SP
+        STRB     LR,[R1,#TCB_SF_OFS]    // Store stack frame information
+
+SVC_ContextSwitch:
+        STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,SVC_ContextRestore1 // Branch if there is no secure context
+        PUSH     {R2,R3}                // Save registers
+        BL       TZ_LoadContext_S       // Load secure context
+        POP      {R2,R3}                // Restore registers
+#endif
+
+SVC_ContextRestore1:
+        LDR      R0,[R2,#TCB_SM_OFS]    // Load stack memory base
+        LDRB     R1,[R2,#TCB_SF_OFS]    // Load stack frame information
+        MSR      PSPLIM,R0              // Set PSPLIM
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+        TST      LR,#0x40               // Check domain of interrupted thread
+        BNE      SVC_ContextRestore2    // Branch if secure
+#endif
+
+#ifdef __FPU_USED
+        TST      LR,#0x10               // Check if extended stack frame
+        IT       EQ
+        VLDMIAEQ R0!,{S16-S31}          //  Restore VFP S16..S31
+#endif
+        LDMIA    R0!,{R4-R11}           // Restore R4..R11
+
+SVC_ContextRestore2:
+        MSR      PSP,R0                 // Set PSP
+
+SVC_Exit:
+        BX       LR                     // Exit from handler
+
+SVC_User:
+        PUSH     {R4,LR}                // Save registers
+        LDR      R2,=osRtxUserSVC       // Load address of SVC table
+        LDR      R3,[R2]                // Load SVC maximum number
+        CMP      R1,R3                  // Check SVC number range
+        BHI      SVC_Done               // Branch if out of range
+
+        LDR      R4,[R2,R1,LSL #2]      // Load address of SVC function
+
+        LDM      R0,{R0-R3}             // Load function parameters from stack
+        BLX      R4                     // Call service function
+        MRS      R4,PSP                 // Get PSP
+        STR      R0,[R4]                // Store function return value
+
+SVC_Done:
+        POP      {R4,PC}                // Return from handler
+
+        .fnend
+        .size    SVC_Handler, .-SVC_Handler
+
+
+        .thumb_func
+        .type    PendSV_Handler, %function
+        .global  PendSV_Handler
+        .fnstart
+        .cantunwind
+PendSV_Handler:
+
+        PUSH     {R4,LR}                // Save EXC_RETURN
+        BL       osRtxPendSV_Handler    // Call osRtxPendSV_Handler
+        POP      {R4,LR}                // Restore EXC_RETURN
+        B        Sys_Context
+
+        .fnend
+        .size    PendSV_Handler, .-PendSV_Handler
+
+
+        .thumb_func
+        .type    SysTick_Handler, %function
+        .global  SysTick_Handler
+        .fnstart
+        .cantunwind
+SysTick_Handler:
+
+        PUSH     {R4,LR}                // Save EXC_RETURN
+        BL       osRtxTick_Handler      // Call osRtxTick_Handler
+        POP      {R4,LR}                // Restore EXC_RETURN
+        B        Sys_Context
+
+        .fnend
+        .size   SysTick_Handler, .-SysTick_Handler
+
+
+        .thumb_func
+        .type    Sys_Context, %function
+        .global  Sys_Context
+        .fnstart
+        .cantunwind
+Sys_Context:
+
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDM      R3,{R1,R2}             // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        IT       EQ
+        BXEQ     LR                     // Exit when threads are the same
+
+Sys_ContextSave:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,Sys_ContextSave1    // Branch if there is no secure context
+        PUSH     {R1,R2,R3,LR}          // Save registers and EXC_RETURN
+        BL       TZ_StoreContext_S      // Store secure context
+        POP      {R1,R2,R3,LR}          // Restore registers and EXC_RETURN
+        TST      LR,#0x40               // Check domain of interrupted thread
+        IT       NE
+        MRSNE    R0,PSP                 // Get PSP
+        BNE      Sys_ContextSave2       // Branch if secure
+#endif
+
+Sys_ContextSave1:
+        MRS      R0,PSP                 // Get PSP
+        STMDB    R0!,{R4-R11}           // Save R4..R11
+#ifdef __FPU_USED
+        TST      LR,#0x10               // Check if extended stack frame
+        IT       EQ
+        VSTMDBEQ R0!,{S16-S31}          //  Save VFP S16.S31
+#endif
+
+Sys_ContextSave2:
+        STR      R0,[R1,#TCB_SP_OFS]    // Store SP
+        STRB     LR,[R1,#TCB_SF_OFS]    // Store stack frame information
+
+Sys_ContextSwitch:
+        STR      R2,[R3]                // osRtxInfo.run: curr = next
+
+Sys_ContextRestore:
+#ifdef __DOMAIN_NS
+        LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
+        CBZ      R0,Sys_ContextRestore1 // Branch if there is no secure context
+        PUSH     {R2,R3}                // Save registers
+        BL       TZ_LoadContext_S       // Load secure context
+        POP      {R2,R3}                // Restore registers
+#endif
+
+Sys_ContextRestore1:
+        LDR      R0,[R2,#TCB_SM_OFS]    // Load stack memory base
+        LDRB     R1,[R2,#TCB_SF_OFS]    // Load stack frame information
+        MSR      PSPLIM,R0              // Set PSPLIM
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+        TST      LR,#0x40               // Check domain of interrupted thread
+        BNE      Sys_ContextRestore2    // Branch if secure
+#endif
+
+#ifdef __FPU_USED
+        TST      LR,#0x10               // Check if extended stack frame
+        IT       EQ
+        VLDMIAEQ R0!,{S16-S31}          //  Restore VFP S16..S31
+#endif
+        LDMIA    R0!,{R4-R11}           // Restore R4..R11
+
+Sys_ContextRestore2:
+        MSR      PSP,R0                 // Set PSP
+
+Sys_ContextExit:
+        BX       LR                     // Exit from handler
+
+        .fnend
+        .size    Sys_Context, .-Sys_Context
+
+
+        .end
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_IAR/irq_armv8mml.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_IAR/irq_armv8mml.S
new file mode 100755
index 0000000..20c0411
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_IAR/irq_armv8mml.S
@@ -0,0 +1,253 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Mainline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+                NAME    irq_armv8mml.S
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                SECTION .rodata:DATA:NOROOT(2)
+
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+                THUMB
+                SECTION .text:CODE:NOROOT(2)
+
+
+SVC_Handler
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+#ifdef __FPU_USED
+                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
+                TST      LR,#0x10               ; Check if extended stack frame
+                BNE      SVC_ContextSwitch
+                LDR      R1,=0xE000EF34         ; FPCCR Address
+                LDR      R0,[R1]                ; Load FPCCR
+                BIC      R0,#1                  ; Clear LSPACT (Lazy state)
+                STR      R0,[R1]                ; Store FPCCR
+                B        SVC_ContextSwitch
+#else
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+#endif
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+SVC_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      SVC_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+SVC_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+
+PendSV_Handler
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+
+SysTick_Handler
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+
+Sys_Context
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                MRSNE    R0,PSP                 ; Get PSP
+                BNE      Sys_ContextSave2       ; Branch if secure
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+Sys_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+Sys_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      Sys_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+Sys_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                END
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.S
new file mode 100755
index 0000000..84ad0b5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.S
@@ -0,0 +1,154 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M4F Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CBNZ     R1,SVC_User            ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
+                TST      LR,#0x10               ; Check if extended stack frame
+                BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
+                LDR      R1,=0xE000EF34         ; FPCCR Address
+                LDR      R0,[R1]                ; Load FPCCR
+                BIC      R0,#1                  ; Clear LSPACT (Lazy state)
+                STR      R0,[R1]                ; Store FPCCR
+                B        SVC_ContextSwitch
+#endif
+
+SVC_ContextSave
+                STMDB    R12!,{R4-R11}          ; Save R4..R11
+#ifdef __FPU_PRESENT
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31
+#endif
+
+                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
+                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __FPU_PRESENT
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+                MSR      PSP,R0                 ; Set PSP
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+                ALIGN
+                ENDP
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S
new file mode 100755
index 0000000..fd57b7f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Cortex-M4F Exception handlers
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+
+        .file    "irq_cm4f.S"
+        .syntax  unified
+
+        .equ     I_T_RUN_OFS, 28        // osRtxInfo.thread.run offset
+        .equ     TCB_SP_OFS,  56        // TCB.SP offset
+        .equ     TCB_SF_OFS,  34        // TCB.stack_frame offset
+
+        .section ".rodata"
+        .global  irqRtxLib              // Non weak library reference
+irqRtxLib:
+        .byte    0
+
+
+        .thumb
+        .section ".text"
+        .align   2
+
+
+        .thumb_func
+        .type    SVC_Handler, %function
+        .global  SVC_Handler
+        .fnstart
+        .cantunwind
+SVC_Handler:
+
+        MRS      R0,PSP                 // Get PSP
+        LDR      R1,[R0,#24]            // Load saved PC from stack
+        LDRB     R1,[R1,#-2]            // Load SVC number
+        CBNZ     R1,SVC_User            // Branch if not SVC 0
+
+        PUSH     {R0,LR}                // Save PSP and EXC_RETURN
+        LDM      R0,{R0-R3,R12}         // Load function parameters and address from stack
+        BLX      R12                    // Call service function
+        POP      {R12,LR}               // Restore PSP and EXC_RETURN
+        STM      R12,{R0-R1}            // Store function return values
+
+SVC_Context:
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDM      R3,{R1,R2}             // Load osRtxInfo.thread.run: curr & next
+        CMP      R1,R2                  // Check if thread switch is required
+        IT       EQ
+        BXEQ     LR                     // Exit when threads are the same
+
+        CBNZ     R1,SVC_ContextSave     // Branch if running thread is not deleted
+        TST      LR,#0x10               // Check if extended stack frame
+        BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
+        LDR      R1,=0xE000EF34         // FPCCR Address
+        LDR      R0,[R1]                // Load FPCCR
+        BIC      R0,#1                  // Clear LSPACT (Lazy state)
+        STR      R0,[R1]                // Store FPCCR
+        B        SVC_ContextSwitch
+#endif
+
+SVC_ContextSave:
+        STMDB    R12!,{R4-R11}          // Save R4..R11
+
+#ifdef __FPU_PRESENT
+        TST      LR,#0x10               // Check if extended stack frame
+        IT       EQ
+        VSTMDBEQ R12!,{S16-S31}         //  Save VFP S16.S31
+#endif
+
+        STR      R12,[R1,#TCB_SP_OFS]   // Store SP
+        STRB     LR, [R1,#TCB_SF_OFS]   // Store stack frame information
+
+SVC_ContextSwitch:
+#ifdef FEATURE_UVISOR
+        CPSID I // The call to the thread switch helper and PSP loading must be atomic.
+#endif
+        /* The call to thread_switch_helper can clobber R2 and R3, but we don't
+         * want to clobber R2 or R3. We can't save R2 and R3 to the stack (as
+         * the stack we save them onto is likely to be inaccessible after the
+         * call to thread_switch_helper). So, we just re-obtain the values from
+         * osRtxInfo again. */
+        BL       thread_switch_helper
+        LDR      R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+        LDM      R3,{R1,R2}             // Load osRtxInfo.thread.run: curr & next
+
+        STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore:
+        LDRB     R1,[R2,#TCB_SF_OFS]    // Load stack frame information
+        LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
+        ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
+
+#ifdef __FPU_PRESENT
+        TST      LR,#0x10               // Check if extended stack frame
+        IT       EQ
+        VLDMIAEQ R0!,{S16-S31}          //  Restore VFP S16..S31
+#endif
+        LDMIA    R0!,{R4-R11}           // Restore R4..R11
+        MSR      PSP,R0                 // Set PSP
+#ifdef FEATURE_UVISOR
+        CPSIE I                         // The PSP has been set. Re-enable interrupts.
+#endif
+
+SVC_Exit:
+        BX       LR                     // Exit from handler
+
+SVC_User:
+        PUSH     {R4,LR}                // Save registers
+        LDR      R2,=osRtxUserSVC       // Load address of SVC table
+        LDR      R3,[R2]                // Load SVC maximum number
+        CMP      R1,R3                  // Check SVC number range
+        BHI      SVC_Done               // Branch if out of range
+
+        LDR      R4,[R2,R1,LSL #2]      // Load address of SVC function
+
+        LDM      R0,{R0-R3}             // Load function parameters from stack
+        BLX      R4                     // Call service function
+        MRS      R4,PSP                 // Get PSP
+        STR      R0,[R4]                // Store function return value
+
+SVC_Done:
+        POP     {R4,PC}                 // Return from handler
+
+        .fnend
+        .size    SVC_Handler, .-SVC_Handler
+
+
+        .thumb_func
+        .type    PendSV_Handler, %function
+        .global  PendSV_Handler
+        .fnstart
+        .cantunwind
+PendSV_Handler:
+
+        PUSH     {R4,LR}                // Save EXC_RETURN
+        BL       osRtxPendSV_Handler    // Call osRtxPendSV_Handler
+        POP      {R4,LR}                // Restore EXC_RETURN
+        MRS      R12,PSP
+        B        SVC_Context
+
+        .fnend
+        .size    PendSV_Handler, .-PendSV_Handler
+
+
+        .thumb_func
+        .type    SysTick_Handler, %function
+        .global  SysTick_Handler
+        .fnstart
+        .cantunwind
+SysTick_Handler:
+
+        PUSH     {R4,LR}                // Save EXC_RETURN
+        BL       osRtxTick_Handler      // Call osRtxTick_Handler
+        POP      {R4,LR}                // Restore EXC_RETURN
+        MRS      R12,PSP
+        B        SVC_Context
+
+        .fnend
+        .size    SysTick_Handler, .-SysTick_Handler
+
+
+        .end
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.S
new file mode 100755
index 0000000..e194af1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.S
@@ -0,0 +1,150 @@
+;/*
+; * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       Cortex-M4F Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+                NAME    irq_cm4f.s
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+
+
+                PRESERVE8
+                SECTION .rodata:DATA:NOROOT(2)
+
+
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                THUMB
+                SECTION .text:CODE:NOROOT(2)
+
+SVC_Handler
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CBNZ     R1,SVC_User            ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                IT       EQ
+                BXEQ     LR                     ; Exit when threads are the same
+
+                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
+                TST      LR,#0x10               ; Check if extended stack frame
+                BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
+                LDR      R1,=0xE000EF34         ; FPCCR Address
+                LDR      R0,[R1]                ; Load FPCCR
+                BIC      R0,R0,#1               ; Clear LSPACT (Lazy state)
+                STR      R0,[R1]                ; Store FPCCR
+                B        SVC_ContextSwitch
+#endif
+
+SVC_ContextSave
+                STMDB    R12!,{R4-R11}          ; Save R4..R11
+#ifdef __FPU_PRESENT
+                TST      LR,#0x10               ; Check if extended stack frame
+                IT       EQ
+                VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31
+#endif
+
+                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
+                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __FPU_PRESENT
+                TST      LR,#0x10               ; Check if extended stack frame
+                IT       EQ
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+                MSR      PSP,R0                 ; Set PSP
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+
+PendSV_Handler  
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+
+SysTick_Handler 
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                MRS      R12,PSP
+                B        SVC_Context
+
+
+                END
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h
new file mode 100755
index 0000000..6ae6513
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h
@@ -0,0 +1,750 @@
+/** \addtogroup rtos */
+/** @{*/
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        10. January 2017
+ * $Revision:    V2.1.0
+ *
+ * Project:      CMSIS-RTOS2 API
+ * Title:        cmsis_os2.h header file
+ *
+ * Version 2.1.0
+ *    Support for critical and uncritical sections (nesting safe):
+ *    - updated: osKernelLock, osKernelUnlock
+ *    - added: osKernelRestoreLock
+ *    Updated Thread and Event Flags:
+ *    - changed flags parameter and return type from int32_t to uint32_t
+ * Version 2.0.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+ 
+#ifndef CMSIS_OS2_H_
+#define CMSIS_OS2_H_
+ 
+#ifndef __NO_RETURN
+#if   defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((noreturn))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((noreturn))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+#endif
+ 
+#include <stdint.h>
+#include <stddef.h>
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+//  ==== Enumerations, structures, defines ====
+ 
+/// Version information.
+typedef struct {
+  uint32_t                       api;   ///< API version (major.minor.rev: mmnnnrrrr dec).
+  uint32_t                    kernel;   ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
+} osVersion_t;
+ 
+/// Kernel state.
+typedef enum {
+  osKernelInactive        =  0,         ///< Inactive.
+  osKernelReady           =  1,         ///< Ready.
+  osKernelRunning         =  2,         ///< Running.
+  osKernelLocked          =  3,         ///< Locked.
+  osKernelSuspended       =  4,         ///< Suspended.
+  osKernelError           = -1,         ///< Error.
+  osKernelReserved        = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
+} osKernelState_t;
+ 
+/// Thread state.
+typedef enum {
+  osThreadInactive        =  0,         ///< Inactive.
+  osThreadReady           =  1,         ///< Ready.
+  osThreadRunning         =  2,         ///< Running.
+  osThreadBlocked         =  3,         ///< Blocked.
+  osThreadTerminated      =  4,         ///< Terminated.
+  osThreadError           = -1,         ///< Error.
+  osThreadReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osThreadState_t;
+ 
+/// Priority values.
+typedef enum {
+  osPriorityNone          =  0,         ///< No priority (not initialized).
+  osPriorityIdle          =  1,         ///< Reserved for Idle thread.
+  osPriorityLow           =  8,         ///< Priority: low
+  osPriorityLow1          =  8+1,       ///< Priority: low + 1
+  osPriorityLow2          =  8+2,       ///< Priority: low + 2
+  osPriorityLow3          =  8+3,       ///< Priority: low + 3
+  osPriorityLow4          =  8+4,       ///< Priority: low + 4
+  osPriorityLow5          =  8+5,       ///< Priority: low + 5
+  osPriorityLow6          =  8+6,       ///< Priority: low + 6
+  osPriorityLow7          =  8+7,       ///< Priority: low + 7
+  osPriorityBelowNormal   = 16,         ///< Priority: below normal
+  osPriorityBelowNormal1  = 16+1,       ///< Priority: below normal + 1
+  osPriorityBelowNormal2  = 16+2,       ///< Priority: below normal + 2
+  osPriorityBelowNormal3  = 16+3,       ///< Priority: below normal + 3
+  osPriorityBelowNormal4  = 16+4,       ///< Priority: below normal + 4
+  osPriorityBelowNormal5  = 16+5,       ///< Priority: below normal + 5
+  osPriorityBelowNormal6  = 16+6,       ///< Priority: below normal + 6
+  osPriorityBelowNormal7  = 16+7,       ///< Priority: below normal + 7
+  osPriorityNormal        = 24,         ///< Priority: normal
+  osPriorityNormal1       = 24+1,       ///< Priority: normal + 1
+  osPriorityNormal2       = 24+2,       ///< Priority: normal + 2
+  osPriorityNormal3       = 24+3,       ///< Priority: normal + 3
+  osPriorityNormal4       = 24+4,       ///< Priority: normal + 4
+  osPriorityNormal5       = 24+5,       ///< Priority: normal + 5
+  osPriorityNormal6       = 24+6,       ///< Priority: normal + 6
+  osPriorityNormal7       = 24+7,       ///< Priority: normal + 7
+  osPriorityAboveNormal   = 32,         ///< Priority: above normal
+  osPriorityAboveNormal1  = 32+1,       ///< Priority: above normal + 1
+  osPriorityAboveNormal2  = 32+2,       ///< Priority: above normal + 2
+  osPriorityAboveNormal3  = 32+3,       ///< Priority: above normal + 3
+  osPriorityAboveNormal4  = 32+4,       ///< Priority: above normal + 4
+  osPriorityAboveNormal5  = 32+5,       ///< Priority: above normal + 5
+  osPriorityAboveNormal6  = 32+6,       ///< Priority: above normal + 6
+  osPriorityAboveNormal7  = 32+7,       ///< Priority: above normal + 7
+  osPriorityHigh          = 40,         ///< Priority: high
+  osPriorityHigh1         = 40+1,       ///< Priority: high + 1
+  osPriorityHigh2         = 40+2,       ///< Priority: high + 2
+  osPriorityHigh3         = 40+3,       ///< Priority: high + 3
+  osPriorityHigh4         = 40+4,       ///< Priority: high + 4
+  osPriorityHigh5         = 40+5,       ///< Priority: high + 5
+  osPriorityHigh6         = 40+6,       ///< Priority: high + 6
+  osPriorityHigh7         = 40+7,       ///< Priority: high + 7
+  osPriorityRealtime      = 48,         ///< Priority: realtime
+  osPriorityRealtime1     = 48+1,       ///< Priority: realtime + 1
+  osPriorityRealtime2     = 48+2,       ///< Priority: realtime + 2
+  osPriorityRealtime3     = 48+3,       ///< Priority: realtime + 3
+  osPriorityRealtime4     = 48+4,       ///< Priority: realtime + 4
+  osPriorityRealtime5     = 48+5,       ///< Priority: realtime + 5
+  osPriorityRealtime6     = 48+6,       ///< Priority: realtime + 6
+  osPriorityRealtime7     = 48+7,       ///< Priority: realtime + 7
+  osPriorityISR           = 56,         ///< Reserved for ISR deferred thread.
+  osPriorityError         = -1,         ///< System cannot determine priority or illegal priority.
+  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osPriority_t;
+ 
+/// Entry point of a thread.
+typedef void (*osThreadFunc_t) (void *argument);
+ 
+/// Entry point of a timer call back function.
+typedef void (*osTimerFunc_t) (void *argument);
+ 
+/// Timer type.
+typedef enum {
+  osTimerOnce               = 0,          ///< One-shot timer.
+  osTimerPeriodic           = 1           ///< Repeating timer.
+} osTimerType_t;
+ 
+/// Timeout value.
+#define osWaitForever         0xFFFFFFFFU ///< Wait forever timeout value.
+ 
+/// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
+#define osFlagsWaitAny        0x00000000U ///< Wait for any flag (default).
+#define osFlagsWaitAll        0x00000001U ///< Wait for all flags.
+#define osFlagsNoClear        0x00000002U ///< Do not clear flags which have been specified to wait for.
+ 
+/// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
+#define osFlagsError          0x80000000U ///< Error indicator.
+#define osFlagsErrorUnknown   0xFFFFFFFFU ///< osError (-1).
+#define osFlagsErrorTimeout   0xFFFFFFFEU ///< osErrorTimeout (-2).
+#define osFlagsErrorResource  0xFFFFFFFDU ///< osErrorResource (-3).
+#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
+#define osFlagsErrorISR       0xFFFFFFFAU ///< osErrorISR (-6).
+ 
+/// Thread attributes (attr_bits in \ref osThreadAttr_t).
+#define osThreadDetached      0x00000000U ///< Thread created in detached state (default)
+#define osThreadJoinable      0x00000001U ///< Thread created in joinable state
+ 
+/// Mutex attributes (attr_bits in \ref osMutexAttr_t).
+#define osMutexRecursive      0x00000001U ///< Recursive mutex.
+#define osMutexPrioInherit    0x00000002U ///< Priority inherit protocol.
+#define osMutexRobust         0x00000008U ///< Robust mutex.
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+  osOK                      =  0,         ///< Operation completed successfully.
+  osError                   = -1,         ///< Unspecified RTOS error: run-time error but no other error message fits.
+  osErrorTimeout            = -2,         ///< Operation not completed within the timeout period.
+  osErrorResource           = -3,         ///< Resource not available.
+  osErrorParameter          = -4,         ///< Parameter error.
+  osErrorNoMemory           = -5,         ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorISR                = -6,         ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osStatusReserved          = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osStatus_t;
+ 
+ 
+/// \details Thread ID identifies the thread.
+typedef void *osThreadId_t;
+ 
+/// \details Timer ID identifies the timer.
+typedef void *osTimerId_t;
+ 
+/// \details Event Flags ID identifies the event flags.
+typedef void *osEventFlagsId_t;
+ 
+/// \details Mutex ID identifies the mutex.
+typedef void *osMutexId_t;
+ 
+/// \details Semaphore ID identifies the semaphore.
+typedef void *osSemaphoreId_t;
+ 
+/// \details Memory Pool ID identifies the memory pool.
+typedef void *osMemoryPoolId_t;
+ 
+/// \details Message Queue ID identifies the message queue.
+typedef void *osMessageQueueId_t;
+ 
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+ 
+/// Attributes structure for thread.
+typedef struct {
+  const char                   *name;   ///< name of the thread
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                   *stack_mem;    ///< memory for stack
+  uint32_t                stack_size;   ///< size of stack
+  osPriority_t              priority;   ///< initial thread priority (default: osPriorityNormal)
+  TZ_ModuleId_t            tz_module;   ///< TrustZone module identifier
+  uint32_t                  reserved;   ///< reserved (must be 0)
+} osThreadAttr_t;
+ 
+/// Attributes structure for timer.
+typedef struct {
+  const char                   *name;   ///< name of the timer
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osTimerAttr_t;
+ 
+/// Attributes structure for event flags.
+typedef struct {
+  const char                   *name;   ///< name of the event flags
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osEventFlagsAttr_t;
+ 
+/// Attributes structure for mutex.
+typedef struct {
+  const char                   *name;   ///< name of the mutex
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osMutexAttr_t;
+ 
+/// Attributes structure for semaphore.
+typedef struct {
+  const char                   *name;   ///< name of the semaphore
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osSemaphoreAttr_t;
+ 
+/// Attributes structure for memory pool.
+typedef struct {
+  const char                   *name;   ///< name of the memory pool
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mp_mem;    ///< memory for data storage
+  uint32_t                   mp_size;   ///< size of provided memory for data storage 
+} osMemoryPoolAttr_t;
+ 
+/// Attributes structure for message queue.
+typedef struct {
+  const char                   *name;   ///< name of the message queue
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mq_mem;    ///< memory for data storage
+  uint32_t                   mq_size;   ///< size of provided memory for data storage 
+} osMessageQueueAttr_t;
+ 
+ 
+//  ==== Kernel Management Functions ====
+ 
+/// Initialize the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelInitialize (void);
+ 
+///  Get RTOS Kernel Information.
+/// \param[out]    version       pointer to buffer for retrieving version information.
+/// \param[out]    id_buf        pointer to buffer for retrieving kernel identification string.
+/// \param[in]     id_size       size of buffer for kernel identification string.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+ 
+/// Get the current RTOS Kernel state.
+/// \return current RTOS Kernel state.
+osKernelState_t osKernelGetState (void);
+ 
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelStart (void);
+ 
+/// Lock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelLock (void);
+ 
+/// Unlock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelUnlock (void);
+ 
+/// Restore the RTOS Kernel scheduler lock state.
+/// \param[in]     lock          lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelRestoreLock (int32_t lock);
+ 
+/// Suspend the RTOS Kernel scheduler.
+/// \return time in ticks, for how long the system can sleep or power-down.
+uint32_t osKernelSuspend (void);
+ 
+/// Resume the RTOS Kernel scheduler.
+/// \param[in]     sleep_ticks   time in ticks for how long the system was in sleep or power-down mode.
+void osKernelResume (uint32_t sleep_ticks);
+ 
+/// Get the RTOS kernel tick count.
+/// \return RTOS kernel current tick count.
+uint64_t osKernelGetTickCount (void);
+ 
+/// Get the RTOS kernel tick frequency.
+/// \return frequency of the kernel tick.
+uint32_t osKernelGetTickFreq (void);
+ 
+/// Get the RTOS kernel system timer count.
+/// \return RTOS kernel current system timer count as 32-bit value.
+uint32_t osKernelGetSysTimerCount (void);
+ 
+/// Get the RTOS kernel system timer frequency.
+/// \return frequency of the system timer.
+uint32_t osKernelGetSysTimerFreq (void);
+ 
+ 
+//  ==== Thread Management Functions ====
+ 
+/// Create a thread and add it to Active Threads.
+/// \param[in]     func          thread function.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \param[in]     attr          thread attributes; NULL: default values.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+osThreadId_t osThreadContextNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context);
+ 
+/// Get name of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return name as NULL terminated string.
+const char *osThreadGetName (osThreadId_t thread_id);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadGetId (void);
+ 
+/// Get current thread state of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current thread state of the specified thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id);
+ 
+/// Get stack size of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return stack size in bytes.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id);
+ 
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return remaining stack space in bytes.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
+ 
+/// Change priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+ 
+/// Get current priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id);
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadYield (void);
+ 
+/// Suspend execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSuspend (osThreadId_t thread_id);
+ 
+/// Resume execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadResume (osThreadId_t thread_id);
+ 
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadDetach (osThreadId_t thread_id);
+ 
+/// Wait for specified thread to terminate.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadJoin (osThreadId_t thread_id);
+ 
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void);
+ 
+/// Terminate execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadTerminate (osThreadId_t thread_id);
+ 
+/// Get number of active threads.
+/// \return number of active threads.
+uint32_t osThreadGetCount (void);
+ 
+/// Enumerate active threads.
+/// \param[out]    thread_array  pointer to array for retrieving thread IDs.
+/// \param[in]     array_items   maximum number of items in array for retrieving thread IDs.
+/// \return number of enumerated threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
+ 
+ 
+//  ==== Thread Flags Functions ====
+ 
+/// Set the specified Thread Flags of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     flags         specifies the flags of the thread that shall be set.
+/// \return thread flags after setting or error code if highest bit set.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+ 
+/// Clear the specified Thread Flags of current running thread.
+/// \param[in]     flags         specifies the flags of the thread that shall be cleared.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsClear (uint32_t flags);
+ 
+/// Get the current Thread Flags of current running thread.
+/// \return current thread flags.
+uint32_t osThreadFlagsGet (void);
+ 
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelay (uint32_t ticks);
+ 
+/// Wait until specified time.
+/// \param[in]     ticks         absolute time in ticks
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelayUntil (uint64_t ticks);
+ 
+ 
+//  ==== Timer Management Functions ====
+ 
+/// Create and Initialize a timer.
+/// \param[in]     func          start address of a timer call back function.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \param[in]     attr          timer attributes; NULL: default values.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+ 
+/// Get name of a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return name as NULL terminated string.
+const char *osTimerGetName (osTimerId_t timer_id);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
+ 
+/// Stop a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStop (osTimerId_t timer_id);
+ 
+/// Check if a timer is running.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return 0 not running, 1 running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id);
+ 
+/// Delete a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerDelete (osTimerId_t timer_id);
+ 
+ 
+//  ==== Event Flags Management Functions ====
+ 
+/// Create and Initialize an Event Flags object.
+/// \param[in]     attr          event flags attributes; NULL: default values.
+/// \return event flags ID for reference by other functions or NULL in case of error.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
+ 
+/// Get name of an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return name as NULL terminated string.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
+ 
+/// Set the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be set.
+/// \return event flags after setting or error code if highest bit set.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+ 
+/// Clear the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be cleared.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+ 
+/// Get the current Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return current event flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
+ 
+/// Wait for one or more Event Flags to become signaled.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+ 
+/// Delete an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
+ 
+ 
+//  ==== Mutex Management Functions ====
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     attr          mutex attributes; NULL: default values.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr);
+ 
+/// Get name of a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return name as NULL terminated string.
+const char *osMutexGetName (osMutexId_t mutex_id);
+ 
+/// Acquire a Mutex or timeout if it is locked.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+ 
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexRelease (osMutexId_t mutex_id);
+ 
+/// Get Thread which owns a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return thread ID of owner thread or NULL when mutex was not acquired.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
+ 
+/// Delete a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexDelete (osMutexId_t mutex_id);
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+/// Create and Initialize a Semaphore object.
+/// \param[in]     max_count     maximum number of available tokens.
+/// \param[in]     initial_count initial number of available tokens.
+/// \param[in]     attr          semaphore attributes; NULL: default values.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+ 
+/// Get name of a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return name as NULL terminated string.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
+ 
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+ 
+/// Release a Semaphore token that was acquired by \ref osSemaphoreAcquire.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
+ 
+/// Get current Semaphore token count.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return number of tokens available.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
+ 
+/// Delete a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+ 
+/// Create and Initialize a Memory Pool object.
+/// \param[in]     block_count   maximum number of memory blocks in memory pool.
+/// \param[in]     block_size    memory block size in bytes.
+/// \param[in]     attr          memory pool attributes; NULL: default values.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+ 
+/// Get name of a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return name as NULL terminated string.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
+ 
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+ 
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     block         address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+ 
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return maximum number of memory blocks.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
+ 
+/// Get memory block size in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return memory block size in bytes.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+ 
+/// Get number of memory blocks used in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks used.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
+ 
+/// Get number of memory blocks available in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks available.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
+ 
+/// Delete a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+/// Create and Initialize a Message Queue object.
+/// \param[in]     msg_count     maximum number of messages in queue.
+/// \param[in]     msg_size      maximum message size in bytes.
+/// \param[in]     attr          message queue attributes; NULL: default values.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+ 
+/// Get name of a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return name as NULL terminated string.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
+ 
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[in]     msg_ptr       pointer to buffer with message to put into a queue.
+/// \param[in]     msg_prio      message priority.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+ 
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[out]    msg_ptr       pointer to buffer for message to get from a queue.
+/// \param[out]    msg_prio      pointer to buffer for message priority or NULL.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+ 
+/// Get maximum number of messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum number of messages.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+ 
+/// Get maximum message size in a Memory Pool.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum message size in bytes.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
+ 
+/// Get number of queued messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of queued messages.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
+ 
+/// Get number of available slots for messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of available slots for messages.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
+ 
+/// Reset a Message Queue to initial empty state.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
+ 
+/// Delete a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // CMSIS_OS2_H_
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h
new file mode 100755
index 0000000..1590bd6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/core_cm.h
@@ -0,0 +1,1534 @@
+/** \addtogroup rtos */
+/** @{*/
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Cortex-M Core definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#ifndef CORE_CM_H_
+#define CORE_CM_H_
+
+#include <stdint.h>
+#include "cmsis.h"
+#include "cmsis_compiler.h"
+#include "arm_math.h"
+
+#ifndef __ARM_ARCH_6M__
+#define __ARM_ARCH_6M__         0U
+#endif
+#ifndef __ARM_ARCH_7M__
+#define __ARM_ARCH_7M__         0U
+#endif
+#ifndef __ARM_ARCH_7EM__
+#define __ARM_ARCH_7EM__        0U
+#endif
+#ifndef __ARM_ARCH_8M_BASE__
+#define __ARM_ARCH_8M_BASE__    0U
+#endif
+#ifndef __ARM_ARCH_8M_MAIN__
+#define __ARM_ARCH_8M_MAIN__    0U
+#endif
+
+#if   ((__ARM_ARCH_6M__      + \
+        __ARM_ARCH_7M__      + \
+        __ARM_ARCH_7EM__     + \
+        __ARM_ARCH_8M_BASE__ + \
+        __ARM_ARCH_8M_MAIN__) != 1U)
+#error "Unknown ARM Architecture!"
+#endif
+
+#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS
+#define __DOMAIN_NS             1U
+#endif
+
+#ifndef __DOMAIN_NS
+#define __DOMAIN_NS             0U
+#elif ((__DOMAIN_NS          == 1U) && \
+      ((__ARM_ARCH_6M__      == 1U) || \
+       (__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U)))
+#error "Non-secure domain requires ARMv8-M Architecture!"
+#endif
+
+#ifndef __EXCLUSIVE_ACCESS
+#if   ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U) || \
+       (__ARM_ARCH_8M_BASE__ == 1U) || \
+       (__ARM_ARCH_8M_MAIN__ == 1U))
+#define __EXCLUSIVE_ACCESS      1U
+#else
+#define __EXCLUSIVE_ACCESS      0U
+#endif
+#endif
+
+
+#define IS_PRIVILEGED()         ((__get_CONTROL() & 1U) == 0U)
+
+#define IS_IRQ_MODE()            (__get_IPSR() != 0U)
+
+#if   ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U) || \
+       (__ARM_ARCH_8M_MAIN__ == 1U))
+#define IS_IRQ_MASKED()         ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))
+#else
+#define IS_IRQ_MASKED()          (__get_PRIMASK() != 0U) 
+#endif
+
+#define XPSR_INITIAL_VALUE      0x01000000U
+
+#if    (__DOMAIN_NS == 1U)
+#define STACK_FRAME_INIT        0xBCU
+#else
+#define STACK_FRAME_INIT        0xFDU
+#endif
+
+#define IS_EXTENDED_STACK_FRAME(n) (((n) & 0x10U) == 0U)
+
+
+//  ==== Service Calls definitions ====
+
+#if defined(__CC_ARM)
+
+#if   ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U) || \
+       (__ARM_ARCH_8M_MAIN__ == 1U))
+#define __SVC_INDIRECT(n) __svc_indirect(n)
+#elif ((__ARM_ARCH_6M__      == 1U) || \
+       (__ARM_ARCH_8M_BASE__ == 1U))
+#define __SVC_INDIRECT(n) __svc_indirect_r7(n)
+#endif
+
+#if    (__FPU_USED == 1U)
+#define SVC_SETUP_PSP                                                          \
+  uint32_t control = __get_CONTROL();                                          \
+  if ((control & 2U) == 0U) {                                                  \
+    __set_PSP((__get_MSP() - ((control & 4U) ? 104U : 32U)) & ~7U);            \
+  }
+#else
+#define SVC_SETUP_PSP                                                          \
+  uint32_t control = __get_CONTROL();                                          \
+  if ((control & 2U) == 0U) {                                                  \
+    __set_PSP((__get_MSP() -                          32U)  & ~7U);            \
+  }
+#endif
+
+#define SVC0_0N(f,t)                                                           \
+__SVC_INDIRECT(0) t    svc##f (t(*)());                                        \
+                  t svcRtx##f (void);                                          \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (void) {                                         \
+  svc##f(svcRtx##f);                                                           \
+}
+
+#define SVC0_0(f,t)                                                            \
+__SVC_INDIRECT(0) t    svc##f (t(*)());                                        \
+                  t svcRtx##f (void);                                          \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (void) {                                         \
+  return svc##f(svcRtx##f);                                                    \
+}
+
+#define SVC0_0M(f,t)                                                           \
+__SVC_INDIRECT(0) t    svc##f (t(*)());                                        \
+                  t svcRtx##f (void);                                          \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (void) {                                         \
+  SVC_SETUP_PSP                                                                \
+  return svc##f(svcRtx##f);                                                    \
+}
+
+#define SVC0_0D SVC0_0
+
+#define SVC0_1N(f,t,t1)                                                        \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1),t1);                                   \
+                  t svcRtx##f (t1 a1);                                         \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1) {                                        \
+  svc##f(svcRtx##f,a1);                                                        \
+}
+
+#define SVC0_1(f,t,t1)                                                         \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1),t1);                                   \
+                  t svcRtx##f (t1 a1);                                         \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1) {                                        \
+  return svc##f(svcRtx##f,a1);                                                 \
+}
+
+#define SVC0_1M(f,t,t1)                                                        \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1),t1);                                   \
+                  t svcRtx##f (t1 a1);                                         \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1) {                                        \
+  SVC_SETUP_PSP                                                                \
+  return svc##f(svcRtx##f,a1);                                                 \
+}
+
+#define SVC0_2(f,t,t1,t2)                                                      \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1,t2),t1,t2);                             \
+                  t svcRtx##f (t1 a1, t2 a2);                                  \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2) {                                 \
+  return svc##f(svcRtx##f,a1,a2);                                              \
+}
+
+#define SVC0_2M(f,t,t1,t2)                                                     \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1,t2),t1,t2);                             \
+                  t svcRtx##f (t1 a1, t2 a2);                                  \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2) {                                 \
+  SVC_SETUP_PSP                                                                \
+  return svc##f(svcRtx##f,a1,a2);                                              \
+}
+
+#define SVC0_3(f,t,t1,t2,t3)                                                   \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3),t1,t2,t3);                       \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3);                           \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3) {                          \
+  return svc##f(svcRtx##f,a1,a2,a3);                                           \
+}
+
+#define SVC0_3M(f,t,t1,t2,t3)                                                  \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3),t1,t2,t3);                       \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3);                           \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3) {                          \
+  SVC_SETUP_PSP                                                                \
+  return svc##f(svcRtx##f,a1,a2,a3);                                           \
+}
+
+#define SVC0_4(f,t,t1,t2,t3,t4)                                                \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4);                 \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4);                    \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                   \
+  return svc##f(svcRtx##f,a1,a2,a3,a4);                                        \
+}
+
+#define SVC0_4M(f,t,t1,t2,t3,t4)                                               \
+__SVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4);                 \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4);                    \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                   \
+  SVC_SETUP_PSP                                                                \
+  return svc##f(svcRtx##f,a1,a2,a3,a4);                                        \
+}
+
+#elif defined(__ICCARM__)
+
+#if   ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U) || \
+       (__ARM_ARCH_8M_MAIN__ == 1U))
+#define SVC_Setup(f)                                                           \
+  __asm(                                                                       \
+    "mov r12,%0\n"                                                             \
+    :: "r"(&f): "r12"                                                          \
+  );
+#elif ((__ARM_ARCH_6M__      == 1U) || \
+       (__ARM_ARCH_8M_BASE__ == 1U))
+#define SVC_Setup(f)                                                           \
+  __asm(                                                                       \
+    "mov r7,%0\n"                                                              \
+    :: "r"(&f): "r7"                                                           \
+  );
+#endif
+
+#define STRINGIFY(a) #a
+#define __SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi
+
+#if    (__FPU_USED == 1U)
+#define SVC_SETUP_PSP                                                          \
+  uint32_t control = __get_CONTROL();                                          \
+  if ((control & 2U) == 0U) {                                                  \
+    __set_PSP((__get_MSP() - ((control & 4U) ? 104U : 32U)) & ~7U);            \
+  }
+#else
+#define SVC_SETUP_PSP                                                          \
+  uint32_t control = __get_CONTROL();                                          \
+  if ((control & 2U) == 0U) {                                                  \
+    __set_PSP((__get_MSP() -                          32U)  & ~7U);            \
+  }
+#endif
+
+#define SVC0_0N(f,t)                                                           \
+__SVC_INDIRECT(0) t    svc##f ();                                              \
+                  t svcRtx##f (void);                                          \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (void) {                                         \
+  SVC_Setup(svcRtx##f);                                                        \
+  svc##f();                                                                    \
+}
+
+#define SVC0_0(f,t)                                                            \
+__SVC_INDIRECT(0) t    svc##f ();                                              \
+                  t svcRtx##f (void);                                          \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (void) {                                         \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f();                                                             \
+}
+
+#define SVC0_0M(f,t)                                                           \
+__SVC_INDIRECT(0) t    svc##f ();                                              \
+                  t svcRtx##f (void);                                          \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (void) {                                         \
+  SVC_SETUP_PSP                                                                \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f();                                                             \
+}
+
+#define SVC0_0D SVC0_0
+
+#define SVC0_1N(f,t,t1)                                                        \
+__SVC_INDIRECT(0) t    svc##f (t1 a1);                                         \
+                  t svcRtx##f (t1 a1);                                         \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1) {                                        \
+  SVC_Setup(svcRtx##f);                                                        \
+  svc##f(a1);                                                                  \
+}
+
+#define SVC0_1(f,t,t1)                                                         \
+__SVC_INDIRECT(0) t    svc##f (t1 a1);                                         \
+                  t svcRtx##f (t1 a1);                                         \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1) {                                        \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1);                                                           \
+}
+
+#define SVC0_1M(f,t,t1)                                                        \
+__SVC_INDIRECT(0) t    svc##f (t1 a1);                                         \
+                  t svcRtx##f (t1 a1);                                         \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1) {                                        \
+  SVC_SETUP_PSP                                                                \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1);                                                           \
+}
+
+#define SVC0_2(f,t,t1,t2)                                                      \
+__SVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2);                                  \
+                  t svcRtx##f (t1 a1, t2 a2);                                  \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2) {                                 \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1,a2);                                                        \
+}
+
+#define SVC0_2M(f,t,t1,t2)                                                     \
+__SVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2);                                  \
+                  t svcRtx##f (t1 a1, t2 a2);                                  \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2) {                                 \
+  SVC_SETUP_PSP                                                                \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1,a2);                                                        \
+}
+
+#define SVC0_3(f,t,t1,t2,t3)                                                   \
+__SVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3);                           \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3);                           \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3) {                          \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1,a2,a3);                                                     \
+}
+
+#define SVC0_3M(f,t,t1,t2,t3)                                                  \
+__SVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3);                           \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3);                           \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3) {                          \
+  SVC_SETUP_PSP                                                                \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1,a2,a3);                                                     \
+}
+
+#define SVC0_4(f,t,t1,t2,t3,t4)                                                \
+__SVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3, t4 a4);                    \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4);                    \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                   \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1,a2,a3,a4);                                                  \
+}
+
+#define SVC0_4M(f,t,t1,t2,t3,t4)                                               \
+__SVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3, t4 a4);                    \
+                  t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4);                    \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                   \
+  SVC_SETUP_PSP                                                                \
+  SVC_Setup(svcRtx##f);                                                        \
+  return svc##f(a1,a2,a3,a4);                                                  \
+}
+
+#else   // !(defined(__CC_ARM) || defined(__ICCARM__))
+
+#if   ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U) || \
+       (__ARM_ARCH_8M_MAIN__ == 1U))
+#define SVC_RegF "r12"
+#elif ((__ARM_ARCH_6M__      == 1U) || \
+       (__ARM_ARCH_8M_BASE__ == 1U))
+#define SVC_RegF "r7"
+#endif
+
+#define SVC_ArgN(n) \
+register uint32_t __r##n __ASM("r"#n)
+
+#define SVC_ArgR(n,a) \
+register uint32_t __r##n __ASM("r"#n) = (uint32_t)a
+
+#define SVC_ArgF(f) \
+register uint32_t __rf   __ASM(SVC_RegF) = (uint32_t)f
+
+#define SVC_In0 "r"(__rf)
+#define SVC_In1 "r"(__rf),"r"(__r0)
+#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1)
+#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2)
+#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3)
+
+#define SVC_Out0
+#define SVC_Out1 "=r"(__r0)
+#define SVC_Out2 "=r"(__r0),"=r"(__r1)
+
+#define SVC_CL0
+#define SVC_CL1 "r1"
+#define SVC_CL2 "r0","r1"
+
+#define SVC_Call0(in, out, cl)                                                 \
+  __ASM volatile ("svc 0" : out : in : cl)
+
+#if   ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U) || \
+       (__ARM_ARCH_8M_MAIN__ == 1U))
+#if    (__FPU_USED == 1U)
+#define SVC_Call0M(in, out, cl)                                                \
+  register uint32_t val;                                                       \
+  __ASM volatile (                                                             \
+  ".syntax unified\n\t"                                                        \
+    "mrs   %[val],control\n\t"                                                 \
+    "tst   %[val],#2\n\t"                                                      \
+    "bne   0f\n\t"                                                             \
+    "tst   %[val],#4\n\t"                                                      \
+    "mrs   %[val],msp\n\t"                                                     \
+    "ite   eq\n\t"                                                             \
+    "subeq %[val],#32\n\t"                                                     \
+    "subne %[val],#104\n\t"                                                    \
+    "bic   %[val],#7\n\t"                                                      \
+    "msr   psp,%[val]\n\t"                                                     \
+  "0:\n\t"                                                                     \
+    "svc 0"                                                                    \
+  : out, [val] "=&l" (val) : in : cl)
+#else
+#define SVC_Call0M(in, out, cl)                                                \
+  register uint32_t val;                                                       \
+  __ASM volatile (                                                             \
+  ".syntax unified\n\t"                                                        \
+    "mrs   %[val],control\n\t"                                                 \
+    "tst   %[val],#2\n\t"                                                      \
+    "bne   0f\n\t"                                                             \
+    "mrs   %[val],msp\n\t"                                                     \
+    "subs  %[val],#32\n\t"                                                     \
+    "bic   %[val],#7\n\t"                                                      \
+    "msr   psp,%[val]\n\t"                                                     \
+  "0:\n\t"                                                                     \
+    "svc 0"                                                                    \
+  : out, [val] "=&l" (val) : in : cl)
+#endif
+#elif ((__ARM_ARCH_6M__      == 1U) || \
+       (__ARM_ARCH_8M_BASE__ == 1U))
+#define SVC_Call0M(in, out, cl)                                                \
+  register uint32_t val;                                                       \
+  __ASM volatile (                                                             \
+  ".syntax unified\n\t"                                                        \
+    "mrs   %[val],control\n\t"                                                 \
+    "lsls  %[val],#30\n\t"                                                     \
+    "bmi   0f\n\t"                                                             \
+    "mrs   %[val],msp\n\t"                                                     \
+    "subs  %[val],#32\n\t"                                                     \
+    "lsrs  %[val],#3\n\t"                                                      \
+    "lsls  %[val],#3\n\t"                                                      \
+    "msr   psp,%[val]\n\t"                                                     \
+  "0:\n\t"                                                                     \
+    "svc 0"                                                                    \
+  : out, [val] "=&l" (val) : in : cl)
+#endif
+
+#define SVC0_0N(f,t)                                                           \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (void) {                                            \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2);                                       \
+}
+
+#define SVC0_0(f,t)                                                            \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (void) {                                            \
+  SVC_ArgN(0);                                                                 \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1);                                       \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_0M(f,t)                                                           \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (void) {                                            \
+  SVC_ArgN(0);                                                                 \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0M(SVC_In0, SVC_Out1, SVC_CL1);                                      \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_0D(f,t)                                                           \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (void) {                                            \
+  SVC_ArgN(0);                                                                 \
+  SVC_ArgN(1);                                                                 \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In0, SVC_Out2, SVC_CL0);                                       \
+  return (((t) __r0) | (((t) __r1) << 32));                                    \
+}
+
+#define SVC0_1N(f,t,t1)                                                        \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1) {                                           \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1);                                       \
+}
+
+#define SVC0_1(f,t,t1)                                                         \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1) {                                           \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1);                                       \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_1M(f,t,t1)                                                        \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1) {                                           \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0M(SVC_In1, SVC_Out1, SVC_CL1);                                      \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_2(f,t,t1,t2)                                                      \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1, t2 a2) {                                    \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgR(1,a2);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0);                                       \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_2M(f,t,t1,t2)                                                     \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1, t2 a2) {                                    \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgR(1,a2);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0M(SVC_In2, SVC_Out1, SVC_CL0);                                      \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_3(f,t,t1,t2,t3)                                                   \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) {                             \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgR(1,a2);                                                              \
+  SVC_ArgR(2,a3);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0);                                       \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_3M(f,t,t1,t2,t3)                                                  \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) {                             \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgR(1,a2);                                                              \
+  SVC_ArgR(2,a3);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0M(SVC_In3, SVC_Out1, SVC_CL0);                                      \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_4(f,t,t1,t2,t3,t4)                                                \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                      \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgR(1,a2);                                                              \
+  SVC_ArgR(2,a3);                                                              \
+  SVC_ArgR(3,a4);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0);                                       \
+  return (t) __r0;                                                             \
+}
+
+#define SVC0_4M(f,t,t1,t2,t3,t4)                                               \
+__attribute__((always_inline))                                                 \
+__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                      \
+  SVC_ArgR(0,a1);                                                              \
+  SVC_ArgR(1,a2);                                                              \
+  SVC_ArgR(2,a3);                                                              \
+  SVC_ArgR(3,a4);                                                              \
+  SVC_ArgF(svcRtx##f);                                                         \
+  SVC_Call0M(SVC_In4, SVC_Out1, SVC_CL0);                                      \
+  return (t) __r0;                                                             \
+}
+
+#endif
+
+
+//  ==== Core Peripherals functions ====
+
+extern uint32_t SystemCoreClock;        // System Clock Frequency (Core Clock)
+
+
+/// Initialize SVC and PendSV System Service Calls
+__STATIC_INLINE void SVC_Initialize (void) {
+#if   ((__ARM_ARCH_8M_MAIN__ == 1U) || (defined(__CORTEX_M) && (__CORTEX_M == 7U)))
+  uint32_t p, n;
+
+  SCB->SHPR[10] = 0xFFU;
+  n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U));
+  p = NVIC_GetPriorityGrouping();
+  if (p >= n) {
+    n = p + 1U;
+  }
+  SCB->SHPR[7] = (uint8_t)(0xFEU << n);
+#elif  (__ARM_ARCH_8M_BASE__ == 1U)
+  SCB->SHPR[1] |= 0x00FF0000U;
+  SCB->SHPR[0] |= (SCB->SHPR[1] << (8+1)) & 0xFC000000U;
+#elif ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U))
+  uint32_t p, n;
+
+  SCB->SHP[10] = 0xFFU;
+  n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U));
+  p = NVIC_GetPriorityGrouping();
+  if (p >= n) {
+    n = p + 1U;
+  }
+
+/* Only change the SVCall priority if uVisor is not present. */
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+  SCB->SHP[7] = (uint8_t)(0xFEU << n);
+#endif
+#elif  (__ARM_ARCH_6M__      == 1U)
+  SCB->SHP[1] |= 0x00FF0000U;
+  SCB->SHP[0] |= (SCB->SHP[1] << (8+1)) & 0xFC000000U;
+#endif
+}
+
+/// Setup SysTick Timer
+/// \param[in] period  Timer Load value
+__STATIC_INLINE void SysTick_Setup (uint32_t period) {
+  SysTick->LOAD = period - 1U;
+  SysTick->VAL  = 0U;
+#if   ((__ARM_ARCH_8M_MAIN__ == 1U) || (defined(__CORTEX_M) && (__CORTEX_M == 7U)))
+  SCB->SHPR[11] = 0xFFU;
+#elif  (__ARM_ARCH_8M_BASE__ == 1U)
+  SCB->SHPR[1] |= 0xFF000000U;
+#elif ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U))
+  SCB->SHP[11]  = 0xFFU;
+#elif  (__ARM_ARCH_6M__      == 1U)
+  SCB->SHP[1]  |= 0xFF000000U;
+#endif
+}
+
+/// Get SysTick Period
+/// \return    SysTick Period
+__STATIC_INLINE uint32_t SysTick_GetPeriod (void) {
+  return (SysTick->LOAD + 1U);
+}
+
+/// Get SysTick Value
+/// \return    SysTick Value
+__STATIC_INLINE uint32_t SysTick_GetVal (void) {
+  uint32_t load = SysTick->LOAD;
+  return  (load - SysTick->VAL);
+}
+
+/// Get SysTick Overflow (Auto Clear)
+/// \return    SysTick Overflow flag
+__STATIC_INLINE uint32_t SysTick_GetOvf (void) {
+  return ((SysTick->CTRL >> 16) & 1U);
+}
+
+/// Enable SysTick Timer
+__STATIC_INLINE void SysTick_Enable (void) {
+  SysTick->CTRL = SysTick_CTRL_ENABLE_Msk     |
+                  SysTick_CTRL_TICKINT_Msk    |
+                  SysTick_CTRL_CLKSOURCE_Msk;
+}
+
+/// Disable SysTick Timer
+__STATIC_INLINE void SysTick_Disable (void) {
+  SysTick->CTRL = 0U;
+}
+
+/// Setup External Tick Timer Interrupt
+/// \param[in] irqn  Interrupt number
+__STATIC_INLINE void ExtTick_SetupIRQ (int32_t irqn) {
+#if    (__ARM_ARCH_8M_MAIN__ == 1U)
+  NVIC->IPR[irqn] = 0xFFU;
+#elif  (__ARM_ARCH_8M_BASE__ == 1U)
+  NVIC->IPR[irqn >> 2] = (NVIC->IPR[irqn >> 2]  & ~(0xFFU << ((irqn & 3) << 3))) |
+                                                   (0xFFU << ((irqn & 3) << 3));
+#elif ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U))
+  NVIC->IP[irqn] = 0xFFU;
+#elif  (__ARM_ARCH_6M__      == 1U)
+  NVIC->IP[irqn >> 2] = (NVIC->IP[irqn >> 2]  & ~(0xFFU << ((irqn & 3) << 3))) |
+                                                 (0xFFU << ((irqn & 3) << 3));
+#endif
+}
+
+/// Enable External Tick Timer Interrupt
+/// \param[in] irqn  Interrupt number
+__STATIC_INLINE void ExtTick_EnableIRQ (int32_t irqn) {
+  NVIC->ISER[irqn >> 5] = 1U << (irqn & 0x1F);
+}
+
+/// Disable External Tick Timer Interrupt
+/// \param[in] irqn  Interrupt number
+__STATIC_INLINE void ExtTick_DisableIRQ (int32_t irqn) {
+  NVIC->ICER[irqn >> 5] = 1U << (irqn & 0x1F);
+}
+
+/// Get Pending SV (Service Call) and ST (SysTick) Flags
+/// \return    Pending SV&ST Flags
+__STATIC_INLINE uint8_t GetPendSV_ST (void) {
+  return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk | SCB_ICSR_PENDSTSET_Msk)) >> 24));
+}
+
+/// Get Pending SV (Service Call) Flag
+/// \return    Pending SV Flag
+__STATIC_INLINE uint8_t GetPendSV (void) {
+  return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24));
+}
+
+/// Clear Pending SV (Service Call) and ST (SysTick) Flags
+__STATIC_INLINE void ClrPendSV_ST (void) {
+  SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk;
+}
+
+/// Clear Pending SV (Service Call) Flag
+__STATIC_INLINE void ClrPendSV (void) {
+  SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
+}
+
+/// Set Pending SV (Service Call) Flag
+__STATIC_INLINE void SetPendSV (void) {
+  SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
+}
+
+/// Set Pending Flags
+/// \param[in] flags  Flags to set
+__STATIC_INLINE void SetPendFlags (uint8_t flags) {
+  SCB->ICSR = ((uint32_t)flags << 24);
+}
+
+
+//  ==== Exclusive Access Operation ====
+
+#if (__EXCLUSIVE_ACCESS == 1U)
+
+/// Atomic Access Operation: Write (8-bit)
+/// \param[in]  mem             Memory address
+/// \param[in]  val             Value to write
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
+  mov    r2,r0
+1
+  ldrexb r0,[r2]
+  strexb r3,r1,[r2]
+  cbz    r3,%F2
+  b      %B1
+2
+  bx     lr
+}
+#else
+__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint8_t  ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrexb %[ret],[%[mem]]\n\t"
+    "strexb %[res],%[val],[%[mem]]\n\t"
+    "cbz    %[res],2f\n\t"
+    "b       1b\n"
+  "2:"
+  : [ret] "=&l" (ret),
+    [res] "=&l" (res)
+  : [mem] "l"   (mem),
+    [val] "l"   (val)
+  : "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Set bits (32-bit)
+/// \param[in]  mem             Memory address
+/// \param[in]  bits            Bit mask
+/// \return                     New value
+#if defined(__CC_ARM)
+static __asm    uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  orr   r0,r0,r1
+  strex r3,r0,[r2]
+  cbz   r3,%F2
+  b     %B1
+2
+  bx     lr
+}
+#else
+__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint32_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[val],[%[mem]]\n\t"
+#if (__ARM_ARCH_8M_BASE__ == 1U)
+    "mov   %[ret],%[val]\n\t"
+    "orrs  %[ret],%[bits]\n\t"
+#else
+    "orr   %[ret],%[val],%[bits]\n\t"
+#endif
+    "strex %[res],%[ret],[%[mem]]\n\t"
+    "cbz   %[res],2f\n\t"
+    "b     1b\n"
+  "2:"
+  : [ret]  "=&l" (ret),
+    [val]  "=&l" (val),
+    [res]  "=&l" (res)
+  : [mem]  "l"   (mem),
+    [bits] "l"   (bits)
+#if (__ARM_ARCH_8M_BASE__ == 1U)
+  : "memory", "cc"
+#else
+  : "memory"
+#endif
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Clear bits (32-bit)
+/// \param[in]  mem             Memory address
+/// \param[in]  bits            Bit mask
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
+  push  {r4,lr}
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  bic   r4,r0,r1
+  strex r3,r4,[r2]
+  cbz   r3,%F2
+  b     %B1
+2
+  pop   {r4,pc}
+}
+#else
+__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint32_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[ret],[%[mem]]\n\t"
+#if (__ARM_ARCH_8M_BASE__ == 1U)
+    "mov   %[val],%[ret]\n\t"
+    "bics  %[val],%[bits]\n\t"
+#else
+    "bic   %[val],%[ret],%[bits]\n\t"
+#endif
+    "strex %[res],%[val],[%[mem]]\n\t"
+    "cbz   %[res],2f\n\t"
+    "b     1b\n"
+  "2:"
+  : [ret]  "=&l" (ret),
+    [val]  "=&l" (val),
+    [res]  "=&l" (res)
+  : [mem]  "l"   (mem),
+    [bits] "l"   (bits)
+#if (__ARM_ARCH_8M_BASE__ == 1U)
+  : "memory", "cc"
+#else
+  : "memory"
+#endif
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them
+/// \param[in]  mem             Memory address
+/// \param[in]  bits            Bit mask
+/// \return                     Active bits before clearing or 0 if not active
+#if defined(__CC_ARM)
+static __asm    uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
+  push  {r4,lr}
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  and   r4,r0,r1
+  cmp   r4,r1
+  beq   %F2
+  clrex
+  movs  r0,#0
+  pop   {r4,pc}
+2
+  bic   r4,r0,r1
+  strex r3,r4,[r2]
+  cbz   r3,%F3
+  b     %B1
+3
+  pop   {r4,pc}
+}
+#else
+__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint32_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[ret],[%[mem]]\n\t"
+#if (__ARM_ARCH_8M_BASE__ == 1U)
+    "mov   %[val],%[ret]\n\t"
+    "ands  %[val],%[bits]\n\t"
+#else
+    "and   %[val],%[ret],%[bits]\n\t"
+#endif
+    "cmp   %[val],%[bits]\n\t"
+    "beq   2f\n\t"
+    "clrex\n\t"
+    "movs  %[ret],#0\n\t"
+    "b     3f\n"
+  "2:\n\t"
+#if (__ARM_ARCH_8M_BASE__ == 1U)
+    "mov   %[val],%[ret]\n\t"
+    "bics  %[val],%[bits]\n\t"
+#else
+    "bic   %[val],%[ret],%[bits]\n\t"
+#endif
+    "strex %[res],%[val],[%[mem]]\n\t"
+    "cbz   %[res],3f\n\t"
+    "b     1b\n"
+  "3:"
+  : [ret]  "=&l" (ret),
+    [val]  "=&l" (val),
+    [res]  "=&l" (res)
+  : [mem]  "l"   (mem),
+    [bits] "l"   (bits)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them
+/// \param[in]  mem             Memory address
+/// \param[in]  bits            Bit mask
+/// \return                     Active bits before clearing or 0 if not active
+#if defined(__CC_ARM)
+static __asm    uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
+  push  {r4,lr}
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  tst   r0,r1
+  bne   %F2
+  clrex
+  movs  r0,#0
+  pop   {r4,pc}
+2
+  bic   r4,r0,r1
+  strex r3,r4,[r2]
+  cbz   r3,%F3
+  b     %B1
+3
+  pop   {r4,pc}
+}
+#else
+__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint32_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[ret],[%[mem]]\n\t"
+    "tst   %[ret],%[bits]\n\t"
+    "bne   2f\n\t"
+    "clrex\n\t"
+    "movs  %[ret],#0\n\t"
+    "b     3f\n"
+  "2:\n\t"
+#if (__ARM_ARCH_8M_BASE__ == 1U)
+    "mov   %[val],%[ret]\n\t"
+    "bics  %[val],%[bits]\n\t"
+#else
+    "bic   %[val],%[ret],%[bits]\n\t"
+#endif
+    "strex %[res],%[val],[%[mem]]\n\t"
+    "cbz   %[res],3f\n\t"
+    "b     1b\n"
+  "3:"
+  : [ret]  "=&l" (ret),
+    [val]  "=&l" (val),
+    [res]  "=&l" (res)
+  : [mem]  "l"   (mem),
+    [bits] "l"   (bits)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Increment (32-bit)
+/// \param[in]  mem             Memory address
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint32_t atomic_inc32 (uint32_t *mem) {
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  adds  r1,r0,#1
+  strex r3,r1,[r2]
+  cbz   r3,%F2
+  b     %B1
+2
+  bx     lr
+}
+#else
+__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint32_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[ret],[%[mem]]\n\t"
+    "adds  %[val],%[ret],#1\n\t"
+    "strex %[res],%[val],[%[mem]]\n\t"
+    "cbz   %[res],2f\n\t"
+    "b     1b\n"
+  "2:"
+  : [ret] "=&l" (ret),
+    [val] "=&l" (val),
+    [res] "=&l" (res)
+  : [mem] "l"   (mem)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// atomic Access Operation: Increment (32-bit) if Less Than
+/// \param[in]  mem             Memory address
+/// \param[in]  max             Maximum value
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) {
+  push  {r4,lr}
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  cmp   r1,r0
+  bhi   %F2
+  clrex
+  pop   {r4,pc}
+2
+  adds  r4,r0,#1
+  strex r3,r4,[r2]
+  cbz   r3,%F3
+  b     %B1
+3
+  pop   {r4,pc}
+}
+#else
+__STATIC_INLINE uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint32_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[ret],[%[mem]]\n\t"
+    "cmp   %[max],%[ret]\n\t"
+    "bhi    2f\n\t"
+    "clrex\n\t"
+    "b      3f\n"
+  "2:\n\t"
+    "adds  %[val],%[ret],#1\n\t"
+    "strex %[res],%[val],[%[mem]]\n\t"
+    "cbz   %[res],3f\n\t"
+    "b     1b\n"
+  "3:"
+  : [ret] "=&l" (ret),
+    [val] "=&l" (val),
+    [res] "=&l" (res)
+  : [mem] "l"   (mem),
+    [max] "l"   (max)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Increment (16-bit) if Less Than
+/// \param[in]  mem             Memory address
+/// \param[in]  max             Maximum value
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
+  push   {r4,lr}
+  mov    r2,r0
+1
+  ldrexh r0,[r2]
+  cmp    r1,r0
+  bhi    %F2
+  clrex
+  pop    {r4,pc}
+2
+  adds   r4,r0,#1
+  strexh r3,r4,[r2]
+  cbz    r3,%F3
+  b      %B1
+3
+  pop    {r4,pc}
+}
+#else
+__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint16_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrexh %[ret],[%[mem]]\n\t"
+    "cmp    %[max],%[ret]\n\t"
+    "bhi    2f\n\t"
+    "clrex\n\t"
+    "b      3f\n"
+  "2:\n\t"
+    "adds   %[val],%[ret],#1\n\t"
+    "strexh %[res],%[val],[%[mem]]\n\t"
+    "cbz    %[res],3f\n\t"
+    "b      1b\n"
+  "3:"
+  : [ret] "=&l" (ret),
+    [val] "=&l" (val),
+    [res] "=&l" (res)
+  : [mem] "l"   (mem),
+    [max] "l"   (max)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Increment (16-bit) and clear on Limit
+/// \param[in]  mem             Memory address
+/// \param[in]  max             Maximum value
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
+  push   {r4,lr}
+  mov    r2,r0
+1
+  ldrexh r0,[r2]
+  adds   r4,r0,#1
+  cmp    r1,r4
+  bhi    %F2
+  movs   r4,#0
+2
+  strexh r3,r4,[r2]
+  cbz    r3,%F3
+  b      %B1
+3
+  pop    {r4,pc}
+}
+#else
+__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint16_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrexh %[ret],[%[mem]]\n\t"
+    "adds   %[val],%[ret],#1\n\t"
+    "cmp    %[lim],%[val]\n\t"
+    "bhi    2f\n\t"
+    "movs   %[val],#0\n"
+  "2:\n\t"
+    "strexh %[res],%[val],[%[mem]]\n\t"
+    "cbz    %[res],3f\n\t"
+    "b      1b\n"
+  "3:"
+  : [ret] "=&l" (ret),
+    [val] "=&l" (val),
+    [res] "=&l" (res)
+  : [mem] "l"   (mem),
+    [lim] "l"   (lim)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Decrement (32-bit) if Not Zero
+/// \param[in]  mem             Memory address
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint32_t atomic_dec32_nz (uint32_t *mem) {
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  cbnz  r0,%F2
+  clrex
+  bx    lr
+2
+  subs  r1,r0,#1
+  strex r3,r1,[r2]
+  cbz   r3,%F3
+  b     %B1
+3
+  bx     lr
+}
+#else
+__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint32_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[ret],[%[mem]]\n\t"
+    "cbnz  %[ret],2f\n\t"
+    "clrex\n\t"
+    "b     3f\n"
+  "2:\n\t"
+    "subs  %[val],%[ret],#1\n\t"
+    "strex %[res],%[val],[%[mem]]\n\t"
+    "cbz   %[res],3f\n\t"
+    "b     1b\n"
+  "3:"
+  : [ret] "=&l" (ret),
+    [val] "=&l" (val),
+    [res] "=&l" (res)
+  : [mem] "l"   (mem)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Decrement (16-bit) if Not Zero
+/// \param[in]  mem             Memory address
+/// \return                     Previous value
+#if defined(__CC_ARM)
+static __asm    uint16_t atomic_dec16_nz (uint16_t *mem) {
+  mov    r2,r0
+1
+  ldrexh r0,[r2]
+  cbnz   r0,%F2
+  clrex
+  bx     lr
+2
+  subs   r1,r0,#1
+  strexh r3,r1,[r2]
+  cbz    r3,%F3
+  b      %B1
+3
+  bx      lr
+}
+#else
+__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register uint16_t ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrexh %[ret],[%[mem]]\n\t"
+    "cbnz   %[ret],2f\n\t"
+    "clrex\n\t"
+    "b      3f\n"
+  "2:\n\t"
+    "subs   %[val],%[ret],#1\n\t"
+    "strexh %[res],%[val],[%[mem]]\n\t"
+    "cbz    %[res],3f\n\t"
+    "b      1b\n"
+  "3:"
+  : [ret] "=&l" (ret),
+    [val] "=&l" (val),
+    [res] "=&l" (res)
+  : [mem] "l"   (mem)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Link Get
+/// \param[in]  root            Root address
+/// \return                     Link
+#if defined(__CC_ARM)
+static __asm    void *atomic_link_get (void **root) {
+  mov   r2,r0
+1
+  ldrex r0,[r2]
+  cbnz  r0,%F2
+  clrex
+  bx    lr
+2
+  ldr   r1,[r0]
+  strex r3,r1,[r2]
+  cbz   r3,%F3
+  b     %B1
+3
+  bx     lr
+}
+#else
+__STATIC_INLINE void *atomic_link_get (void **root) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+  register void    *ret;
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldrex %[ret],[%[root]]\n\t"
+    "cbnz  %[ret],2f\n\t"
+    "clrex\n\t"
+    "b     3f\n"
+  "2:\n\t"
+    "ldr   %[val],[%[ret]]\n\t"
+    "strex %[res],%[val],[%[root]]\n\t"
+    "cbz   %[res],3f\n\t"
+    "b     1b\n"
+  "3:"
+  : [ret]  "=&l" (ret),
+    [val]  "=&l" (val),
+    [res]  "=&l" (res)
+  : [root] "l"   (root)
+  : "cc", "memory"
+  );
+
+  return ret;
+}
+#endif
+
+/// Atomic Access Operation: Link Put
+/// \param[in]  root            Root address
+/// \param[in]  lnk             Link
+#if defined(__CC_ARM)
+static __asm    void atomic_link_put (void **root, void *link) {
+1
+  ldr   r2,[r0]
+  str   r2,[r1]
+  dmb
+  ldrex r2,[r0]
+  ldr   r3,[r1]
+  cmp   r3,r2
+  bne   %B1
+  strex r3,r1,[r0]
+  cbz   r3,%F2
+  b     %B1
+2
+  bx    lr
+}
+#else
+__STATIC_INLINE void atomic_link_put (void **root, void *link) {
+#ifdef  __ICCARM__
+#pragma diag_suppress=Pe550
+#endif
+  register uint32_t val1, val2, res;
+#ifdef  __ICCARM__
+#pragma diag_default=Pe550
+#endif
+
+  __ASM volatile (
+#ifndef __ICCARM__
+  ".syntax unified\n\t"
+#endif
+  "1:\n\t"
+    "ldr   %[val1],[%[root]]\n\t"
+    "str   %[val1],[%[link]]\n\t"
+    "dmb\n\t"
+    "ldrex %[val1],[%[root]]\n\t"
+    "ldr   %[val2],[%[link]]\n\t"
+    "cmp   %[val2],%[val1]\n\t"
+    "bne   1b\n\t"
+    "strex %[res],%[link],[%[root]]\n\t"
+    "cbz   %[res],2f\n\t"
+    "b     1b\n"
+  "2:"
+  : [val1] "=&l" (val1),
+    [val2] "=&l" (val2),
+    [res]  "=&l" (res)
+  : [root] "l"   (root),
+    [link] "l"   (link)
+  : "cc", "memory"
+  );
+}
+#endif
+
+#endif  // (__EXCLUSIVE_ACCESS == 1U)
+
+
+#endif  // CORE_CM_H_
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.c
new file mode 100755
index 0000000..5fee0aa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       OS Event Observer
+ *
+ * -----------------------------------------------------------------------------
+ */
+#include "rt_OsEventObserver.h"
+
+/*
+ *  _____ _____  ____  __ _____
+ * |  ___|_ _\ \/ /  \/  | ____|
+ * | |_   | | \  /| |\/| |  _|
+ * |  _|  | | /  \| |  | | |___
+ * |_|   |___/_/\_\_|  |_|_____|
+ *
+ * FIXME:
+ * The osEventObs variable must be in protected memory. If not every box
+ * and box 0 can modify osEventObs to point to any handler to run code
+ * privileged. This issue is tracked at
+ * <https://github.com/ARMmbed/uvisor/issues/235>.
+ */
+const OsEventObserver *osEventObs;
+
+void osRegisterForOsEvents(const OsEventObserver *observer)
+{
+    static uint8_t has_been_called = 0;
+    if (has_been_called) {
+        return;
+    }
+    has_been_called = 1;
+
+    osEventObs = observer;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h
new file mode 100755
index 0000000..899f319
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       OS Event Observer
+ *
+ * -----------------------------------------------------------------------------
+ */
+#ifndef _RT_OS_EVENT_OBSERVER_H
+#define _RT_OS_EVENT_OBSERVER_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t version;
+    void (*pre_start)(void);
+    void *(*thread_create)(int thread_id, void *context);
+    void (*thread_destroy)(void *context);
+    void (*thread_switch)(void *context);
+} OsEventObserver;
+extern const OsEventObserver *osEventObs;
+
+void osRegisterForOsEvents(const OsEventObserver *observer);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.c
new file mode 100755
index 0000000..a7e71b7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_delay.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Delay functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_1(Delay,      osStatus_t, uint32_t)
+SVC0_2(DelayUntil, osStatus_t, uint32_t, uint32_t)
+
+/// Wait for Timeout (Time Delay).
+/// \note API identical to osDelay
+osStatus_t svcRtxDelay (uint32_t ticks) {
+
+  if (ticks == 0U) {
+    return osOK;
+  }
+
+  osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks);
+
+  return osOK;
+}
+
+/// Wait until specified time.
+/// \note API identical to osDelayUntil
+osStatus_t svcRtxDelayUntil (uint32_t ticks_l, uint32_t ticks_h) {
+  uint64_t ticks = ((uint64_t)ticks_l) | ((uint64_t)ticks_h << 32);
+
+  ticks -= osRtxInfo.kernel.tick;
+  if (ticks >= 0xFFFFFFFFU) {
+    EvrRtxThreadError(NULL, osErrorParameter);
+    return osErrorParameter;
+  }
+  if (ticks == 0U) {
+    return osOK;
+  }
+
+  osRtxThreadWaitEnter(osRtxThreadWaitingDelay, (uint32_t)ticks);
+
+  return osOK;
+}
+
+
+//  ==== Public API ====
+
+/// Wait for Timeout (Time Delay).
+osStatus_t osDelay (uint32_t ticks) {
+  EvrRtxThreadDelay(ticks);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(NULL, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcDelay(ticks);
+}
+
+/// Wait until specified time.
+osStatus_t osDelayUntil (uint64_t ticks) {
+  EvrRtxThreadDelayUntil(ticks);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(NULL, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcDelayUntil((uint32_t)ticks, (uint32_t)(ticks >> 32));
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.c
new file mode 100755
index 0000000..1c534d5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evflags.c
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Event Flags functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Helper functions ====
+
+/// Set Event Flags.
+/// \param[in]  ef              event flags object.
+/// \param[in]  flags           specifies the flags to set.
+/// \return event flags after setting.
+static uint32_t EventFlagsSet (os_event_flags_t *ef, uint32_t flags) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  uint32_t event_flags;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  ef->event_flags |= flags;
+  event_flags = ef->event_flags;
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  event_flags = atomic_set32(&ef->event_flags, flags);
+#endif
+
+  return event_flags;
+}
+
+/// Clear Event Flags.
+/// \param[in]  ef              event flags object.
+/// \param[in]  flags           specifies the flags to clear.
+/// \return event flags before clearing.
+static uint32_t EventFlagsClear (os_event_flags_t *ef, uint32_t flags) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  uint32_t event_flags;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  event_flags = ef->event_flags;
+  ef->event_flags &= ~flags;
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  event_flags = atomic_clr32(&ef->event_flags, flags);
+#endif
+
+  return event_flags;
+}
+
+/// Check Event Flags.
+/// \param[in]  ef              event flags object.
+/// \param[in]  flags           specifies the flags to check.
+/// \param[in]  options         specifies flags options (osFlagsXxxx).
+/// \return event flags before clearing or 0 if specified flags have not been set.
+static uint32_t EventFlagsCheck (os_event_flags_t *ef, uint32_t flags, uint32_t options) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask;
+#endif
+  uint32_t event_flags;
+
+  if ((options & osFlagsNoClear) == 0U) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+    primask = __get_PRIMASK();
+    __disable_irq();
+
+    event_flags = ef->event_flags;
+    if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) ||
+        (((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) {
+      event_flags = 0U;
+    } else {
+      ef->event_flags &= ~flags;
+    }
+
+    if (primask == 0U) {
+      __enable_irq();
+    }
+#else
+    if ((options & osFlagsWaitAll) != 0U) {
+      event_flags = atomic_chk32_all(&ef->event_flags, flags);
+    } else {
+      event_flags = atomic_chk32_any(&ef->event_flags, flags);
+    }
+#endif
+  } else {
+    event_flags = ef->event_flags;
+    if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) ||
+        (((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) {
+      event_flags = 0U;
+    }
+  }
+
+  return event_flags;
+}
+
+
+//  ==== Library functions ====
+
+/// Event Flags post ISR processing.
+/// \param[in]  ef              event flags object.
+void osRtxEventFlagsPostProcess (os_event_flags_t *ef) {
+  os_thread_t *thread;
+  os_thread_t *thread_next;
+  uint32_t     event_flags;
+
+  if (ef->state == osRtxObjectInactive) {
+    return;
+  }
+
+  // Check if Threads are waiting for Event Flags
+  thread = ef->thread_list;
+  while (thread != NULL) {
+    thread_next = thread->thread_next;
+    event_flags = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options);
+    if (event_flags != 0U) {
+      osRtxThreadListRemove(thread);
+      osRtxThreadWaitExit(thread, event_flags, false);
+      EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags);
+    }
+    thread = thread_next;
+  }
+}
+
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_1M(EventFlagsNew,     osEventFlagsId_t, const osEventFlagsAttr_t *)
+SVC0_1 (EventFlagsGetName, const char *,     osEventFlagsId_t)
+SVC0_2 (EventFlagsSet,     uint32_t,         osEventFlagsId_t, uint32_t)
+SVC0_2 (EventFlagsClear,   uint32_t,         osEventFlagsId_t, uint32_t)
+SVC0_1 (EventFlagsGet,     uint32_t,         osEventFlagsId_t)
+SVC0_4 (EventFlagsWait,    uint32_t,         osEventFlagsId_t, uint32_t, uint32_t, uint32_t)
+SVC0_1 (EventFlagsDelete,  osStatus_t,       osEventFlagsId_t)
+
+/// Create and Initialize an Event Flags object.
+/// \note API identical to osEventFlagsNew
+osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr) {
+  os_event_flags_t *ef;
+  uint8_t           flags;
+  const char       *name;
+
+  // Process attributes
+  if (attr != NULL) {
+    name = attr->name;
+    ef   = attr->cb_mem;
+    if (ef != NULL) {
+      if (((uint32_t)ef & 3U) || (attr->cb_size < sizeof(os_event_flags_t))) {
+        EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    } else {
+      if (attr->cb_size != 0U) {
+        EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    }
+  } else {
+    name = NULL;
+    ef   = NULL;
+  }
+
+  // Allocate object memory if not provided
+  if (ef == NULL) {
+    if (osRtxInfo.mpi.event_flags != NULL) {
+      ef = osRtxMemoryPoolAlloc(osRtxInfo.mpi.event_flags);
+    } else {
+      ef = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_event_flags_t), 1U);
+    }
+    if (ef == NULL) {
+      EvrRtxEventFlagsError(NULL, osErrorNoMemory);
+      return NULL;
+    }
+    flags = osRtxFlagSystemObject;
+  } else {
+    flags = 0U;
+  }
+
+  // Initialize control block
+  ef->id          = osRtxIdEventFlags;
+  ef->state       = osRtxObjectActive;
+  ef->flags       = flags;
+  ef->name        = name;
+  ef->thread_list = NULL;
+  ef->event_flags = 0U;
+
+  // Register post ISR processing function
+  osRtxInfo.post_process.event_flags = osRtxEventFlagsPostProcess;
+
+  EvrRtxEventFlagsCreated(ef);
+
+  return ef;
+}
+
+/// Get name of an Event Flags object.
+/// \note API identical to osEventFlagsGetName
+const char *svcRtxEventFlagsGetName (osEventFlagsId_t ef_id) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) {
+    EvrRtxEventFlagsGetName(ef, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsGetName(ef, NULL);
+    return NULL;
+  }
+
+  EvrRtxEventFlagsGetName(ef, ef->name);
+
+  return ef->name;
+}
+
+/// Set the specified Event Flags.
+/// \note API identical to osEventFlagsSet
+uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+  os_thread_t      *thread;
+  os_thread_t      *thread_next;
+  uint32_t          event_flags;
+  uint32_t          event_flags0;
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags) ||
+      (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) {
+    EvrRtxEventFlagsError(ef, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsError(ef, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Set Event Flags
+  event_flags = EventFlagsSet(ef, flags);
+
+  // Check if Threads are waiting for Event Flags
+  thread = ef->thread_list;
+  while (thread != NULL) {
+    thread_next = thread->thread_next;
+    event_flags0 = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options);
+    if (event_flags0 != 0U) {
+      if ((thread->flags_options & osFlagsNoClear) == 0U) {
+        event_flags = event_flags0 & ~thread->wait_flags;
+      } else {
+        event_flags = event_flags0;
+      }
+      osRtxThreadListRemove(thread);
+      osRtxThreadWaitExit(thread, event_flags0, false);
+      EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags0);
+    }
+    thread = thread_next;
+  }
+  osRtxThreadDispatch(NULL);
+
+  EvrRtxEventFlagsSetDone(ef, event_flags);
+
+  return event_flags;
+}
+
+/// Clear the specified Event Flags.
+/// \note API identical to osEventFlagsClear
+uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+  uint32_t          event_flags;
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags) ||
+      (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) {
+    EvrRtxEventFlagsError(ef, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsError(ef, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Clear Event Flags
+  event_flags = EventFlagsClear(ef, flags);
+
+  EvrRtxEventFlagsClearDone(ef, event_flags);
+  
+  return event_flags;
+}
+
+/// Get the current Event Flags.
+/// \note API identical to osEventFlagsGet
+uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) {
+    EvrRtxEventFlagsGet(ef, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsGet(ef, 0U);
+    return 0U;
+  }
+
+  EvrRtxEventFlagsGet(ef, ef->event_flags);
+
+  return ef->event_flags;
+}
+
+/// Wait for one or more Event Flags to become signaled.
+/// \note API identical to osEventFlagsWait
+uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+  os_thread_t      *running_thread;
+  uint32_t          event_flags;
+
+  running_thread = osRtxThreadGetRunning();
+  if (running_thread == NULL) {
+    EvrRtxEventFlagsError(ef, osRtxErrorKernelNotRunning);
+    return ((uint32_t)osError);
+  }
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags) ||
+      (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) {
+    EvrRtxEventFlagsError(ef, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsError(ef, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Check Event Flags
+  event_flags = EventFlagsCheck(ef, flags, options);
+  if (event_flags != 0U) {
+    EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags);
+    return event_flags;
+  }
+
+  // Check if timeout is specified
+  if (timeout != 0U) {
+    EvrRtxEventFlagsWaitPending(ef, flags, options, timeout);
+    // Store waiting flags and options
+    running_thread->wait_flags = flags;
+    running_thread->flags_options = (uint8_t)options;
+    // Suspend current Thread
+    osRtxThreadListPut((os_object_t*)ef, running_thread);
+    osRtxThreadWaitEnter(osRtxThreadWaitingEventFlags, timeout);
+    return ((uint32_t)osErrorTimeout);
+  }
+
+  EvrRtxEventFlagsWaitNotCompleted(ef, flags, options);
+
+  return ((uint32_t)osErrorResource);
+}
+
+/// Delete an Event Flags object.
+/// \note API identical to osEventFlagsDelete
+osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+  os_thread_t      *thread;
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) {
+    EvrRtxEventFlagsError(ef, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsError(ef, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Mark object as inactive
+  ef->state = osRtxObjectInactive;
+
+  // Unblock waiting threads
+  if (ef->thread_list != NULL) {
+    do {
+      thread = osRtxThreadListGet((os_object_t*)ef);
+      osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false);
+    } while (ef->thread_list != NULL);
+    osRtxThreadDispatch(NULL);
+  }
+
+  // Free object memory
+  if (ef->flags & osRtxFlagSystemObject) {
+    if (osRtxInfo.mpi.event_flags != NULL) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.common, ef);
+    }
+  }
+
+  EvrRtxEventFlagsDestroyed(ef);
+
+  return osOK;
+}
+
+
+//  ==== ISR Calls ====
+
+/// Set the specified Event Flags.
+/// \note API identical to osEventFlagsSet
+__STATIC_INLINE
+uint32_t isrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+  uint32_t          event_flags;
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags) ||
+      (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) {
+    EvrRtxEventFlagsError(ef, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsError(ef, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Set Event Flags
+  event_flags = EventFlagsSet(ef, flags);
+
+  // Register post ISR processing
+  osRtxPostProcess((os_object_t *)ef);
+
+  EvrRtxEventFlagsSetDone(ef, event_flags);
+
+  return event_flags;
+}
+
+/// Wait for one or more Event Flags to become signaled.
+/// \note API identical to osEventFlagsWait
+__STATIC_INLINE
+uint32_t isrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
+  os_event_flags_t *ef = (os_event_flags_t *)ef_id;
+  uint32_t          event_flags;
+
+  // Check parameters
+  if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || (timeout != 0U) ||
+      (flags & ~((1U << osRtxEventFlagsLimit) - 1U))) {
+    EvrRtxEventFlagsError(ef, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if (ef->state == osRtxObjectInactive) {
+    EvrRtxEventFlagsError(ef, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Check Event Flags
+  event_flags = EventFlagsCheck(ef, flags, options);
+  if (event_flags != 0U) {
+    EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags);
+    return ((uint32_t)event_flags);
+  }
+
+  EvrRtxEventFlagsWaitNotCompleted(ef, flags, options);
+
+  return ((uint32_t)osErrorResource);
+}
+
+
+//  ==== Public API ====
+
+/// Create and Initialize an Event Flags object.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {
+  EvrRtxEventFlagsNew(attr);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxEventFlagsError(NULL, osErrorISR);
+    return NULL;
+  }
+  return __svcEventFlagsNew(attr);
+}
+
+/// Get name of an Event Flags object.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxEventFlagsGetName(ef_id, NULL);
+    return NULL;
+  }
+  return __svcEventFlagsGetName(ef_id);
+}
+
+/// Set the specified Event Flags.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
+  EvrRtxEventFlagsSet(ef_id, flags);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxEventFlagsSet(ef_id, flags);
+  } else {
+    return  __svcEventFlagsSet(ef_id, flags);
+  }
+}
+
+/// Clear the specified Event Flags.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
+  EvrRtxEventFlagsClear(ef_id, flags);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxEventFlagsClear(ef_id, flags);
+  } else {
+    return  __svcEventFlagsClear(ef_id, flags);
+  }
+}
+
+/// Get the current Event Flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxEventFlagsGet(ef_id);
+  } else {
+    return  __svcEventFlagsGet(ef_id);
+  }
+}
+
+/// Wait for one or more Event Flags to become signaled.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
+  EvrRtxEventFlagsWait(ef_id, flags, options, timeout);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxEventFlagsWait(ef_id, flags, options, timeout);
+  } else {
+    return  __svcEventFlagsWait(ef_id, flags, options, timeout);
+  }
+}
+
+/// Delete an Event Flags object.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {
+  EvrRtxEventFlagsDelete(ef_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxEventFlagsError(ef_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcEventFlagsDelete(ef_id);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.c
new file mode 100755
index 0000000..f368df8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.c
@@ -0,0 +1,2077 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Event Recorder
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include <string.h>
+#include "cmsis_compiler.h"
+#include "rtx_evr.h"                    // RTX Event Recorder definitions
+
+#ifdef RTE_Compiler_EventRecorder
+
+#include "EventRecorder.h"              // Keil::Compiler:Event Recorder
+
+/// RTOS component number
+#define EvtRtxMemoryNo                  (0xF0U)
+#define EvtRtxKernelNo                  (0xF1U)
+#define EvtRtxThreadNo                  (0xF2U)
+#define EvtRtxTimerNo                   (0xF3U)
+#define EvtRtxEventFlagsNo              (0xF4U)
+#define EvtRtxMutexNo                   (0xF5U)
+#define EvtRtxSemaphoreNo               (0xF6U)
+#define EvtRtxMemoryPoolNo              (0xF7U)
+#define EvtRtxMessageQueueNo            (0xF8U)
+
+/// Event IDs for "RTX Memory Management"
+#define EvtRtxMemoryInit                    EventID(EventLevelOp,     EvtRtxMemoryNo, 0x00U)
+#define EvtRtxMemoryAlloc                   EventID(EventLevelOp,     EvtRtxMemoryNo, 0x01U)
+#define EvtRtxMemoryFree                    EventID(EventLevelOp,     EvtRtxMemoryNo, 0x02U)
+#define EvtRtxMemoryBlockInit               EventID(EventLevelOp,     EvtRtxMemoryNo, 0x03U)
+#define EvtRtxMemoryBlockAlloc              EventID(EventLevelOp,     EvtRtxMemoryNo, 0x04U)
+#define EvtRtxMemoryBlockFree               EventID(EventLevelOp,     EvtRtxMemoryNo, 0x05U)
+
+/// Event IDs for "RTX Kernel"
+#define EvtRtxKernelError                   EventID(EventLevelError,  EvtRtxKernelNo, 0x00U)
+#define EvtRtxKernelInitialize              EventID(EventLevelAPI,    EvtRtxKernelNo, 0x01U)
+#define EvtRtxKernelInitializeCompleted     EventID(EventLevelOp,     EvtRtxKernelNo, 0x02U)
+#define EvtRtxKernelGetInfo                 EventID(EventLevelAPI,    EvtRtxKernelNo, 0x03U)
+#define EvtRtxKernelInfoRetrieved           EventID(EventLevelOp,     EvtRtxKernelNo, 0x04U)
+#define EvtRtxKernelInfoRetrieved_Detail    EventID(EventLevelDetail, EvtRtxKernelNo, 0x05U)
+#define EvtRtxKernelGetState                EventID(EventLevelAPI,    EvtRtxKernelNo, 0x06U)
+#define EvtRtxKernelStart                   EventID(EventLevelAPI,    EvtRtxKernelNo, 0x07U)
+#define EvtRtxKernelStarted                 EventID(EventLevelOp,     EvtRtxKernelNo, 0x08U)
+#define EvtRtxKernelLock                    EventID(EventLevelAPI,    EvtRtxKernelNo, 0x09U)
+#define EvtRtxKernelLocked                  EventID(EventLevelOp,     EvtRtxKernelNo, 0x0AU)
+#define EvtRtxKernelUnlock                  EventID(EventLevelAPI,    EvtRtxKernelNo, 0x0BU)
+#define EvtRtxKernelUnlocked                EventID(EventLevelOp,     EvtRtxKernelNo, 0x0CU)
+#define EvtRtxKernelRestoreLock             EventID(EventLevelAPI,    EvtRtxKernelNo, 0x0DU)
+#define EvtRtxKernelLockRestored            EventID(EventLevelOp,     EvtRtxKernelNo, 0x0EU)
+#define EvtRtxKernelSuspend                 EventID(EventLevelAPI,    EvtRtxKernelNo, 0x0FU)
+#define EvtRtxKernelSuspended               EventID(EventLevelOp,     EvtRtxKernelNo, 0x10U)
+#define EvtRtxKernelResume                  EventID(EventLevelAPI,    EvtRtxKernelNo, 0x11U)
+#define EvtRtxKernelResumed                 EventID(EventLevelOp,     EvtRtxKernelNo, 0x12U)
+#define EvtRtxKernelGetTickCount            EventID(EventLevelAPI,    EvtRtxKernelNo, 0x13U)
+#define EvtRtxKernelGetTickFreq             EventID(EventLevelAPI,    EvtRtxKernelNo, 0x14U)
+#define EvtRtxKernelGetSysTimerCount        EventID(EventLevelAPI,    EvtRtxKernelNo, 0x15U)
+#define EvtRtxKernelGetSysTimerFreq         EventID(EventLevelAPI,    EvtRtxKernelNo, 0x16U)
+
+/// Event IDs for "RTX Thread"
+#define EvtRtxThreadError                   EventID(EventLevelError,  EvtRtxThreadNo, 0x00U)
+#define EvtRtxThreadNew                     EventID(EventLevelAPI,    EvtRtxThreadNo, 0x01U)
+#define EvtRtxThreadNew_Detail              EventID(EventLevelDetail, EvtRtxThreadNo, 0x02U)
+#define EvtRtxThreadCreated                 EventID(EventLevelOp,     EvtRtxThreadNo, 0x03U)
+#define EvtRtxThreadGetName                 EventID(EventLevelAPI,    EvtRtxThreadNo, 0x04U)
+#define EvtRtxThreadGetName_Detail          EventID(EventLevelDetail, EvtRtxThreadNo, 0x05U)
+#define EvtRtxThreadGetId                   EventID(EventLevelAPI,    EvtRtxThreadNo, 0x06U)
+#define EvtRtxThreadGetState                EventID(EventLevelAPI,    EvtRtxThreadNo, 0x07U)
+#define EvtRtxThreadGetStackSize            EventID(EventLevelAPI,    EvtRtxThreadNo, 0x08U)
+#define EvtRtxThreadGetStackSpace           EventID(EventLevelAPI,    EvtRtxThreadNo, 0x09U)
+#define EvtRtxThreadSetPriority             EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0AU)
+#define EvtRtxThreadGetPriority             EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0BU)
+#define EvtRtxThreadYield                   EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0CU)
+#define EvtRtxThreadSuspend                 EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0DU)
+#define EvtRtxThreadSuspended               EventID(EventLevelOp,     EvtRtxThreadNo, 0x0EU)
+#define EvtRtxThreadResume                  EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0FU)
+#define EvtRtxThreadResumed                 EventID(EventLevelOp,     EvtRtxThreadNo, 0x10U)
+#define EvtRtxThreadDetach                  EventID(EventLevelAPI,    EvtRtxThreadNo, 0x11U)
+#define EvtRtxThreadDetached                EventID(EventLevelOp,     EvtRtxThreadNo, 0x12U)
+#define EvtRtxThreadJoin                    EventID(EventLevelAPI,    EvtRtxThreadNo, 0x13U)
+#define EvtRtxThreadJoinPending             EventID(EventLevelOp,     EvtRtxThreadNo, 0x14U)
+#define EvtRtxThreadJoined                  EventID(EventLevelOp,     EvtRtxThreadNo, 0x15U)
+#define EvtRtxThreadBlocked                 EventID(EventLevelOp,     EvtRtxThreadNo, 0x16U)
+#define EvtRtxThreadUnblocked               EventID(EventLevelOp,     EvtRtxThreadNo, 0x17U)
+#define EvtRtxThreadSwitch                  EventID(EventLevelOp,     EvtRtxThreadNo, 0x18U)
+#define EvtRtxThreadExit                    EventID(EventLevelAPI,    EvtRtxThreadNo, 0x19U)
+#define EvtRtxThreadTerminate               EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1AU)
+#define EvtRtxThreadDestroyed               EventID(EventLevelOp,     EvtRtxThreadNo, 0x1BU)
+#define EvtRtxThreadGetCount                EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1CU)
+#define EvtRtxThreadEnumerate               EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1DU)
+#define EvtRtxThreadFlagsSet                EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1EU)
+#define EvtRtxThreadFlagsSetDone            EventID(EventLevelOp,     EvtRtxThreadNo, 0x1FU)
+#define EvtRtxThreadFlagsClear              EventID(EventLevelAPI,    EvtRtxThreadNo, 0x20U)
+#define EvtRtxThreadFlagsClearDone          EventID(EventLevelOp,     EvtRtxThreadNo, 0x21U)
+#define EvtRtxThreadFlagsGet                EventID(EventLevelAPI,    EvtRtxThreadNo, 0x22U)
+#define EvtRtxThreadFlagsWait               EventID(EventLevelAPI,    EvtRtxThreadNo, 0x23U)
+#define EvtRtxThreadFlagsWaitPending        EventID(EventLevelOp,     EvtRtxThreadNo, 0x24U)
+#define EvtRtxThreadFlagsWaitTimeout        EventID(EventLevelOp,     EvtRtxThreadNo, 0x25U)
+#define EvtRtxThreadFlagsWaitCompleted      EventID(EventLevelOp,     EvtRtxThreadNo, 0x26U)
+#define EvtRtxThreadFlagsWaitNotCompleted   EventID(EventLevelOp,     EvtRtxThreadNo, 0x27U)
+#define EvtRtxThreadDelay                   EventID(EventLevelAPI,    EvtRtxThreadNo, 0x28U)
+#define EvtRtxThreadDelayUntil              EventID(EventLevelAPI,    EvtRtxThreadNo, 0x29U)
+#define EvtRtxThreadDelayCompleted          EventID(EventLevelOp,     EvtRtxThreadNo, 0x2AU)
+
+/// Event IDs for "RTX Timer"
+#define EvtRtxTimerError                    EventID(EventLevelError,  EvtRtxTimerNo, 0x00U)
+#define EvtRtxTimerCallback                 EventID(EventLevelOp,     EvtRtxTimerNo, 0x01U)
+#define EvtRtxTimerNew                      EventID(EventLevelAPI,    EvtRtxTimerNo, 0x02U)
+#define EvtRtxTimerNew_Detail               EventID(EventLevelDetail, EvtRtxTimerNo, 0x03U)
+#define EvtRtxTimerCreated                  EventID(EventLevelOp,     EvtRtxTimerNo, 0x04U)
+#define EvtRtxTimerGetName                  EventID(EventLevelAPI,    EvtRtxTimerNo, 0x05U)
+#define EvtRtxTimerGetName_Detail           EventID(EventLevelDetail, EvtRtxTimerNo, 0x06U)
+#define EvtRtxTimerStart                    EventID(EventLevelAPI,    EvtRtxTimerNo, 0x07U)
+#define EvtRtxTimerStarted                  EventID(EventLevelOp,     EvtRtxTimerNo, 0x08U)
+#define EvtRtxTimerStop                     EventID(EventLevelAPI,    EvtRtxTimerNo, 0x09U)
+#define EvtRtxTimerStopped                  EventID(EventLevelOp,     EvtRtxTimerNo, 0x0AU)
+#define EvtRtxTimerIsRunning                EventID(EventLevelAPI,    EvtRtxTimerNo, 0x0BU)
+#define EvtRtxTimerDelete                   EventID(EventLevelAPI,    EvtRtxTimerNo, 0x0CU)
+#define EvtRtxTimerDestroyed                EventID(EventLevelOp,     EvtRtxTimerNo, 0x0DU)
+
+/// Event IDs for "RTX Event Flags"
+#define EvtRtxEventFlagsError               EventID(EventLevelError,  EvtRtxEventFlagsNo, 0x00U)
+#define EvtRtxEventFlagsNew                 EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x01U)
+#define EvtRtxEventFlagsNew_Detail          EventID(EventLevelDetail, EvtRtxEventFlagsNo, 0x02U)
+#define EvtRtxEventFlagsCreated             EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x03U)
+#define EvtRtxEventFlagsGetName             EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x04U)
+#define EvtRtxEventFlagsGetName_Detail      EventID(EventLevelDetail, EvtRtxEventFlagsNo, 0x05U)
+#define EvtRtxEventFlagsSet                 EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x06U)
+#define EvtRtxEventFlagsSetDone             EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x07U)
+#define EvtRtxEventFlagsClear               EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x08U)
+#define EvtRtxEventFlagsClearDone           EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x09U)
+#define EvtRtxEventFlagsGet                 EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x0AU)
+#define EvtRtxEventFlagsWait                EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x0BU)
+#define EvtRtxEventFlagsWaitPending         EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0CU)
+#define EvtRtxEventFlagsWaitTimeout         EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0DU)
+#define EvtRtxEventFlagsWaitCompleted       EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0EU)
+#define EvtRtxEventFlagsWaitNotCompleted    EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0FU)
+#define EvtRtxEventFlagsDelete              EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x10U)
+#define EvtRtxEventFlagsDestroyed           EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x11U)
+
+/// Event IDs for "RTX Mutex"
+#define EvtRtxMutexError                    EventID(EventLevelError,  EvtRtxMutexNo, 0x00U)
+#define EvtRtxMutexNew                      EventID(EventLevelAPI,    EvtRtxMutexNo, 0x01U)
+#define EvtRtxMutexNew_Detail               EventID(EventLevelDetail, EvtRtxMutexNo, 0x02U)
+#define EvtRtxMutexCreated                  EventID(EventLevelOp,     EvtRtxMutexNo, 0x03U)
+#define EvtRtxMutexGetName                  EventID(EventLevelAPI,    EvtRtxMutexNo, 0x04U)
+#define EvtRtxMutexGetName_Detail           EventID(EventLevelDetail, EvtRtxMutexNo, 0x05U)
+#define EvtRtxMutexAcquire                  EventID(EventLevelAPI,    EvtRtxMutexNo, 0x06U)
+#define EvtRtxMutexAcquirePending           EventID(EventLevelError,  EvtRtxMutexNo, 0x07U)
+#define EvtRtxMutexAcquireTimeout           EventID(EventLevelError,  EvtRtxMutexNo, 0x08U)
+#define EvtRtxMutexAcquired                 EventID(EventLevelOp,     EvtRtxMutexNo, 0x09U)
+#define EvtRtxMutexNotAcquired              EventID(EventLevelOp,     EvtRtxMutexNo, 0x0AU)
+#define EvtRtxMutexRelease                  EventID(EventLevelAPI,    EvtRtxMutexNo, 0x0BU)
+#define EvtRtxMutexReleased                 EventID(EventLevelOp,     EvtRtxMutexNo, 0x0CU)
+#define EvtRtxMutexGetOwner                 EventID(EventLevelAPI,    EvtRtxMutexNo, 0x0DU)
+#define EvtRtxMutexDelete                   EventID(EventLevelAPI,    EvtRtxMutexNo, 0x0EU)
+#define EvtRtxMutexDestroyed                EventID(EventLevelOp,     EvtRtxMutexNo, 0x0FU)
+
+/// Event IDs for "RTX Semaphore"
+#define EvtRtxSemaphoreError                EventID(EventLevelError,  EvtRtxSemaphoreNo, 0x00U)
+#define EvtRtxSemaphoreNew                  EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x01U)
+#define EvtRtxSemaphoreNew_Detail           EventID(EventLevelDetail, EvtRtxSemaphoreNo, 0x02U)
+#define EvtRtxSemaphoreCreated              EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x03U)
+#define EvtRtxSemaphoreGetName              EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x04U)
+#define EvtRtxSemaphoreGetName_Detail       EventID(EventLevelDetail, EvtRtxSemaphoreNo, 0x05U)
+#define EvtRtxSemaphoreAcquire              EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x06U)
+#define EvtRtxSemaphoreAcquirePending       EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x07U)
+#define EvtRtxSemaphoreAcquireTimeout       EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x08U)
+#define EvtRtxSemaphoreAcquired             EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x09U)
+#define EvtRtxSemaphoreNotAcquired          EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x0AU)
+#define EvtRtxSemaphoreRelease              EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x0BU)
+#define EvtRtxSemaphoreReleased             EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x0CU)
+#define EvtRtxSemaphoreGetCount             EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x0DU)
+#define EvtRtxSemaphoreDelete               EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x0EU)
+#define EvtRtxSemaphoreDestroyed            EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x0FU)
+
+/// Event IDs for "RTX Memory Pool"
+#define EvtRtxMemoryPoolError               EventID(EventLevelError,  EvtRtxMemoryPoolNo, 0x00U)
+#define EvtRtxMemoryPoolNew                 EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x01U)
+#define EvtRtxMemoryPoolNew_Detail          EventID(EventLevelDetail, EvtRtxMemoryPoolNo, 0x02U)
+#define EvtRtxMemoryPoolCreated             EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x03U)
+#define EvtRtxMemoryPoolGetName             EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x04U)
+#define EvtRtxMemoryPoolGetName_Detail      EventID(EventLevelDetail, EvtRtxMemoryPoolNo, 0x05U)
+#define EvtRtxMemoryPoolAlloc               EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x06U)
+#define EvtRtxMemoryPoolAllocPending        EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x07U)
+#define EvtRtxMemoryPoolAllocTimeout        EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x08U)
+#define EvtRtxMemoryPoolAllocated           EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x09U)
+#define EvtRtxMemoryPoolAllocFailed         EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x0AU)
+#define EvtRtxMemoryPoolFree                EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x0BU)
+#define EvtRtxMemoryPoolDeallocated         EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x0CU)
+#define EvtRtxMemoryPoolFreeFailed          EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x0DU)
+#define EvtRtxMemoryPoolGetCapacity         EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x0EU)
+#define EvtRtxMemoryPoolGetBlockSize        EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x0FU)
+#define EvtRtxMemoryPoolGetCount            EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x10U)
+#define EvtRtxMemoryPoolGetSpace            EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x11U)
+#define EvtRtxMemoryPoolDelete              EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x12U)
+#define EvtRtxMemoryPoolDestroyed           EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x13U)
+
+/// Event IDs for "RTX Message Queue"
+#define EvtRtxMessageQueueError             EventID(EventLevelError,  EvtRtxMessageQueueNo, 0x00U)
+#define EvtRtxMessageQueueNew               EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x01U)
+#define EvtRtxMessageQueueNew_Detail        EventID(EventLevelDetail, EvtRtxMessageQueueNo, 0x02U)
+#define EvtRtxMessageQueueCreated           EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x03U)
+#define EvtRtxMessageQueueGetName           EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x04U)
+#define EvtRtxMessageQueueGetName_Detail    EventID(EventLevelDetail, EvtRtxMessageQueueNo, 0x05U)
+#define EvtRtxMessageQueuePut               EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x06U)
+#define EvtRtxMessageQueuePutPending        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x07U)
+#define EvtRtxMessageQueuePutTimeout        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x08U)
+#define EvtRtxMessageQueueInsertPending     EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x09U)
+#define EvtRtxMessageQueueInserted          EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0AU)
+#define EvtRtxMessageQueueNotInserted       EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0BU)
+#define EvtRtxMessageQueueGet               EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x0CU)
+#define EvtRtxMessageQueueGetPending        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0DU)
+#define EvtRtxMessageQueueGetTimeout        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0EU)
+#define EvtRtxMessageQueueRetrieved         EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0FU)
+#define EvtRtxMessageQueueNotRetrieved      EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x10U)
+#define EvtRtxMessageQueueGetCapacity       EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x11U)
+#define EvtRtxMessageQueueGetMsgSize        EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x12U)
+#define EvtRtxMessageQueueGetCount          EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x13U)
+#define EvtRtxMessageQueueGetSpace          EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x14U)
+#define EvtRtxMessageQueueReset             EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x15U)
+#define EvtRtxMessageQueueResetDone         EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x16U)
+#define EvtRtxMessageQueueDelete            EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x17U)
+#define EvtRtxMessageQueueDestroyed         EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x18U)
+
+#endif  // RTE_Compiler_EventRecorder
+
+
+//  ==== Memory Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE))
+__WEAK void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMemoryInit, (uint32_t)mem, size, result, 0U);
+#else
+  (void)mem;
+  (void)size;
+  (void)result;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE))
+__WEAK void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMemoryAlloc, (uint32_t)mem, size, type, (uint32_t)block);
+#else
+  (void)mem;
+  (void)size;
+  (void)type;
+  (void)block;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE))
+__WEAK void EvrRtxMemoryFree (void *mem, void *block, uint32_t result) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMemoryFree, (uint32_t)mem, (uint32_t)block, result, 0U);
+#else
+  (void)mem;
+  (void)block;
+  (void)result;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE))
+__WEAK void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMemoryBlockInit, (uint32_t)mp_info, block_count, block_size, (uint32_t)block_mem);
+#else
+  (void)mp_info;
+  (void)block_count;
+  (void)block_size;
+  (void)block_mem;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE))
+__WEAK void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryBlockAlloc, (uint32_t)mp_info, (uint32_t)block);
+#else
+  (void)mp_info;
+  (void)block;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE))
+__WEAK void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMemoryBlockFree, (uint32_t)mp_info, (uint32_t)block, (uint32_t)status, 0U);
+#else
+  (void)mp_info;
+  (void)block;
+  (void)status;
+#endif
+}
+#endif
+
+
+//  ==== Kernel Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE))
+__WEAK void EvrRtxKernelError (int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelError, (uint32_t)status, 0U); 
+#else
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE))
+__WEAK void EvrRtxKernelInitialize (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelInitialize, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_COMPLETED_DISABLE))
+__WEAK void EvrRtxKernelInitializeCompleted (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelInitializeCompleted, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE))
+__WEAK void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxKernelGetInfo, (uint32_t)version, (uint32_t)id_buf, id_size, 0U);
+#else
+  (void)version;
+  (void)id_buf;
+  (void)id_size;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE))
+__WEAK void EvrRtxKernelInfoRetrieved (osVersion_t *version, char *id_buf) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelInfoRetrieved, (uint32_t)version, (uint32_t)id_buf);
+  if (id_buf != NULL) {
+    EventRecordData(EvtRtxKernelInfoRetrieved_Detail, id_buf, strlen(id_buf));
+  }
+#else
+  (void)version;
+  (void)id_buf;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE))
+__WEAK void EvrRtxKernelGetState (osKernelState_t state) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelGetState, (uint32_t)state, 0U);
+#else
+  (void)state;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE))
+__WEAK void EvrRtxKernelStart (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelStart, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE))
+__WEAK void EvrRtxKernelStarted (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelStarted, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE))
+__WEAK void EvrRtxKernelLock (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelLock, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE))
+__WEAK void EvrRtxKernelLocked (int32_t lock) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelLocked, (uint32_t)lock, 0U);
+#else
+  (void)lock;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE))
+__WEAK void EvrRtxKernelUnlock (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelUnlock, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE))
+__WEAK void EvrRtxKernelUnlocked (int32_t lock) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelUnlocked, (uint32_t)lock, 0U);
+#else
+  (void)lock;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE))
+__WEAK void EvrRtxKernelRestoreLock (int32_t lock) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelRestoreLock, (uint32_t)lock, 0U);
+#else
+  (void)lock;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE))
+__WEAK void EvrRtxKernelLockRestored (int32_t lock) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelLockRestored, (uint32_t)lock, 0U);
+#else
+  (void)lock;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE))
+__WEAK void EvrRtxKernelSuspend (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelSuspend, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE))
+__WEAK void EvrRtxKernelSuspended (uint32_t sleep_ticks) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelSuspended, sleep_ticks, 0U);
+#else
+  (void)sleep_ticks;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE))
+__WEAK void EvrRtxKernelResume (uint32_t sleep_ticks) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelResume, sleep_ticks, 0U);
+#else
+  (void)sleep_ticks;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE))
+__WEAK void EvrRtxKernelResumed (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelResumed, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE))
+__WEAK void EvrRtxKernelGetTickCount (uint64_t count) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelGetTickCount, (uint32_t)count, (uint32_t)(count>>32));
+#else
+  (void)count;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE))
+__WEAK void EvrRtxKernelGetTickFreq (uint32_t freq) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelGetTickFreq, freq, 0U);
+#else
+  (void)freq;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE))
+__WEAK void EvrRtxKernelGetSysTimerCount (uint32_t count) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelGetSysTimerCount, count, 0U);
+#else
+  (void)count;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE))
+__WEAK void EvrRtxKernelGetSysTimerFreq (uint32_t freq) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxKernelGetSysTimerFreq, freq, 0U);
+#else
+  (void)freq;
+#endif
+}
+#endif
+
+
+//  ==== Thread Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE))
+__WEAK void EvrRtxThreadError (osThreadId_t thread_id, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadError, (uint32_t)thread_id, (uint32_t)status);
+#else
+  (void)thread_id;
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE))
+__WEAK void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxThreadNew, (uint32_t)func, (uint32_t)argument, (uint32_t)attr, 0U);
+  if (attr != NULL) {
+    EventRecordData(EvtRtxThreadNew_Detail, attr, sizeof (osThreadAttr_t));
+  }
+#else
+  (void)func;
+  (void)argument;
+  (void)attr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE))
+__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadCreated, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE))
+__WEAK void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadGetName, (uint32_t)thread_id, (uint32_t)name);
+  if (name != NULL) {
+    EventRecordData(EvtRtxThreadGetName_Detail, name, strlen(name));
+  }
+#else
+  (void)thread_id;
+  (void)name;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE))
+__WEAK void EvrRtxThreadGetId (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadGetId, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE))
+__WEAK void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadGetState, (uint32_t)thread_id, (uint32_t)state);
+#else
+  (void)thread_id;
+  (void)state;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE))
+__WEAK void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadGetStackSize, (uint32_t)thread_id, stack_size);
+#else
+  (void)thread_id;
+  (void)stack_size;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE))
+__WEAK void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadGetStackSpace, (uint32_t)thread_id, stack_space);
+#else
+  (void)thread_id;
+  (void)stack_space;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE))
+__WEAK void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadSetPriority, (uint32_t)thread_id, (uint32_t)priority);
+#else
+  (void)thread_id;
+  (void)priority;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE))
+__WEAK void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadGetPriority, (uint32_t)thread_id, (uint32_t)priority);
+#else
+  (void)thread_id;
+  (void)priority;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE))
+__WEAK void EvrRtxThreadYield (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadYield, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE))
+__WEAK void EvrRtxThreadSuspend (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadSuspend, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE))
+__WEAK void EvrRtxThreadSuspended (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadSuspended, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE))
+__WEAK void EvrRtxThreadResume (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadResume, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE))
+__WEAK void EvrRtxThreadResumed (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadResumed, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE))
+__WEAK void EvrRtxThreadDetach (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadDetach, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE))
+__WEAK void EvrRtxThreadDetached (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadDetached, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE))
+__WEAK void EvrRtxThreadJoin (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadJoin, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE))
+__WEAK void EvrRtxThreadJoinPending (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadJoinPending, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE))
+__WEAK void EvrRtxThreadJoined (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadJoined, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE))
+__WEAK void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadBlocked, (uint32_t)thread_id, timeout);
+#else
+  (void)thread_id;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE))
+__WEAK void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadUnblocked, (uint32_t)thread_id, ret_val);
+#else
+  (void)thread_id;
+  (void)ret_val;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCH_DISABLE))
+__WEAK void EvrRtxThreadSwitch (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadSwitch, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE))
+__WEAK void EvrRtxThreadExit (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadExit, 0U, 0U);
+#else
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE))
+__WEAK void EvrRtxThreadTerminate (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE))
+__WEAK void EvrRtxThreadDestroyed (osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadDestroyed, (uint32_t)thread_id, 0U);
+#else
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE))
+__WEAK void EvrRtxThreadGetCount (uint32_t count) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadGetCount, count, 0U);
+#else
+  (void)count;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE))
+__WEAK void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxThreadEnumerate, (uint32_t)thread_array, array_items, count, 0U);
+#else
+  (void)thread_array;
+  (void)array_items;
+  (void)count;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE))
+__WEAK void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadFlagsSet, (uint32_t)thread_id, flags);
+#else
+  (void)thread_id;
+  (void)flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE))
+__WEAK void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadFlagsSetDone, (uint32_t)thread_id, thread_flags);
+#else
+  (void)thread_id;
+  (void)thread_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE))
+__WEAK void EvrRtxThreadFlagsClear (uint32_t flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadFlagsClear, flags, 0U);
+#else
+  (void)flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE))
+__WEAK void EvrRtxThreadFlagsClearDone (uint32_t thread_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadFlagsClearDone, thread_flags, 0U);
+#else
+  (void)thread_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE))
+__WEAK void EvrRtxThreadFlagsGet (uint32_t thread_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadFlagsGet, thread_flags, 0U);
+#else
+  (void)thread_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE))
+__WEAK void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxThreadFlagsWait, flags, options, timeout, 0U);
+#else
+  (void)flags;
+  (void)options;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE))
+__WEAK void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxThreadFlagsWaitPending, flags, options, timeout, 0U);
+#else
+  (void)flags;
+  (void)options;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE))
+__WEAK void EvrRtxThreadFlagsWaitTimeout (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadFlagsWaitTimeout, 0U, 0U);
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE))
+__WEAK void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxThreadFlagsWaitCompleted, flags, options, thread_flags, 0U);
+#else
+  (void)flags;
+  (void)options;
+  (void)thread_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
+__WEAK void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadFlagsWaitNotCompleted, flags, options);
+#else
+  (void)flags;
+  (void)options;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_DISABLE))
+__WEAK void EvrRtxThreadDelay (uint32_t ticks) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadDelay, ticks, 0U);
+#else
+  (void)ticks;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_UNTIL_DISABLE))
+__WEAK void EvrRtxThreadDelayUntil (uint64_t ticks) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadDelayUntil, (uint32_t)ticks, (uint32_t)(ticks >> 32));
+#else
+  (void)ticks;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_COMPLETED_DISABLE))
+__WEAK void EvrRtxThreadDelayCompleted (void) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxThreadDelayCompleted, 0U, 0U);
+#endif
+}
+#endif
+
+
+//  ==== Timer Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE))
+__WEAK void EvrRtxTimerError (osTimerId_t timer_id, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerError, (uint32_t)timer_id, (uint32_t)status);
+#else
+  (void)timer_id;
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE))
+__WEAK void EvrRtxTimerCallback (osTimerFunc_t func, void *argument) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerCallback, (uint32_t)func, (uint32_t)argument);
+#else
+  (void)func;
+  (void)argument;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE))
+__WEAK void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxTimerNew, (uint32_t)func, (uint32_t)type, (uint32_t)argument, (uint32_t)attr);
+  if (attr != NULL) {
+    EventRecordData(EvtRtxTimerNew_Detail, attr, sizeof (osTimerAttr_t));
+  }
+#else
+  (void)func;
+  (void)type;
+  (void)argument;
+  (void)attr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE))
+__WEAK void EvrRtxTimerCreated (osTimerId_t timer_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerCreated, (uint32_t)timer_id, 0U);
+#else
+  (void)timer_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE))
+__WEAK void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerGetName, (uint32_t)timer_id, (uint32_t)name);
+  if (name != NULL) {
+    EventRecordData(EvtRtxTimerGetName_Detail, name, strlen(name));
+  }
+#else
+  (void)timer_id;
+  (void)name;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE))
+__WEAK void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerStart, (uint32_t)timer_id, ticks);
+#else
+  (void)timer_id;
+  (void)ticks;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE))
+__WEAK void EvrRtxTimerStarted (osTimerId_t timer_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerStarted, (uint32_t)timer_id, 0U);
+#else
+  (void)timer_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE))
+__WEAK void EvrRtxTimerStop (osTimerId_t timer_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerStop, (uint32_t)timer_id, 0U);
+#else
+  (void)timer_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE))
+__WEAK void EvrRtxTimerStopped (osTimerId_t timer_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerStopped, (uint32_t)timer_id, 0U);
+#else
+  (void)timer_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE))
+__WEAK void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerIsRunning, (uint32_t)timer_id, running);
+#else
+  (void)timer_id;
+  (void)running;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE))
+__WEAK void EvrRtxTimerDelete (osTimerId_t timer_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerDelete, (uint32_t)timer_id, 0U);
+#else
+  (void)timer_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE))
+__WEAK void EvrRtxTimerDestroyed (osTimerId_t timer_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxTimerDestroyed, (uint32_t)timer_id, 0U);
+#else
+  (void)timer_id;
+#endif
+}
+#endif
+
+
+//  ==== Event Flags Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE))
+__WEAK void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsError, (uint32_t)ef_id, (uint32_t)status);
+#else
+  (void)ef_id;
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE))
+__WEAK void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsNew, (uint32_t)attr, 0U);
+  if (attr != NULL) {
+    EventRecordData(EvtRtxEventFlagsNew_Detail, attr, sizeof (osEventFlagsAttr_t));
+  }
+#else
+  (void)attr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE))
+__WEAK void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsCreated, (uint32_t)ef_id, 0U);
+#else
+  (void)ef_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE))
+__WEAK void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsGetName, (uint32_t)ef_id, (uint32_t)name);
+  if (name != NULL) {
+    EventRecordData(EvtRtxEventFlagsGetName_Detail, name, strlen(name));
+  }
+#else
+  (void)ef_id;
+  (void)name;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE))
+__WEAK void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsSet, (uint32_t)ef_id, flags);
+#else
+  (void)ef_id;
+  (void)flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE))
+__WEAK void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsSetDone, (uint32_t)ef_id, event_flags);
+#else
+  (void)ef_id;
+  (void)event_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE))
+__WEAK void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsClear, (uint32_t)ef_id, flags);
+#else
+  (void)ef_id;
+  (void)flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE))
+__WEAK void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsClearDone, (uint32_t)ef_id, event_flags);
+#else
+  (void)ef_id;
+  (void)event_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE))
+__WEAK void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsGet, (uint32_t)ef_id, event_flags);
+#else
+  (void)ef_id;
+  (void)event_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE))
+__WEAK void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxEventFlagsWait, (uint32_t)ef_id, flags, options, timeout);
+#else
+  (void)ef_id;
+  (void)flags;
+  (void)options;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE))
+__WEAK void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxEventFlagsWaitPending, (uint32_t)ef_id, flags, options, timeout);
+#else
+  (void)ef_id;
+  (void)flags;
+  (void)options;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE))
+__WEAK void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsWaitTimeout, (uint32_t)ef_id, 0U);
+#else
+  (void)ef_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE))
+__WEAK void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxEventFlagsWaitCompleted, (uint32_t)ef_id, flags, options, event_flags);
+#else
+  (void)ef_id;
+  (void)flags;
+  (void)options;
+  (void)event_flags;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
+__WEAK void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxEventFlagsWaitNotCompleted, (uint32_t)ef_id, flags, options, 0U);
+#else
+  (void)ef_id;
+  (void)flags;
+  (void)options;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE))
+__WEAK void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsDelete, (uint32_t)ef_id, 0U);
+#else
+  (void)ef_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE))
+__WEAK void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxEventFlagsDestroyed, (uint32_t)ef_id, 0U);
+#else
+  (void)ef_id;
+#endif
+}
+#endif
+
+
+//  ==== Mutex Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE))
+__WEAK void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexError, (uint32_t)mutex_id, (uint32_t)status);
+#else
+  (void)mutex_id;
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE))
+__WEAK void EvrRtxMutexNew (const osMutexAttr_t *attr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexNew, (uint32_t)attr, 0U);
+  if (attr != NULL) {
+    EventRecordData(EvtRtxMutexNew_Detail, attr, sizeof (osMutexAttr_t));
+  }
+#else
+  (void)attr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE))
+__WEAK void EvrRtxMutexCreated (osMutexId_t mutex_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexCreated, (uint32_t)mutex_id, 0U);
+#else
+  (void)mutex_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE))
+__WEAK void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexGetName, (uint32_t)mutex_id, (uint32_t)name);
+  if (name != NULL) {
+    EventRecordData(EvtRtxMutexGetName_Detail, name, strlen(name));
+  }
+#else
+  (void)mutex_id;
+  (void)name;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE))
+__WEAK void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexAcquire, (uint32_t)mutex_id, timeout);
+#else
+  (void)mutex_id;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE))
+__WEAK void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexAcquirePending, (uint32_t)mutex_id, timeout);
+#else
+  (void)mutex_id;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE))
+__WEAK void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexAcquireTimeout, (uint32_t)mutex_id, 0U);
+#else
+  (void)mutex_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE))
+__WEAK void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexAcquired, (uint32_t)mutex_id, lock);
+#else
+  (void)mutex_id;
+  (void)lock;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE))
+__WEAK void EvrRtxMutexNotAcquired (osMutexId_t mutex_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexNotAcquired, (uint32_t)mutex_id, 0U);
+#else
+  (void)mutex_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE))
+__WEAK void EvrRtxMutexRelease (osMutexId_t mutex_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexRelease, (uint32_t)mutex_id, 0U);
+#else
+  (void)mutex_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE))
+__WEAK void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexReleased, (uint32_t)mutex_id, lock);
+#else
+  (void)mutex_id;
+  (void)lock;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE))
+__WEAK void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexGetOwner, (uint32_t)mutex_id, (uint32_t)thread_id);
+#else
+  (void)mutex_id;
+  (void)thread_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE))
+__WEAK void EvrRtxMutexDelete (osMutexId_t mutex_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexDelete, (uint32_t)mutex_id, 0U);
+#else
+  (void)mutex_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE))
+__WEAK void EvrRtxMutexDestroyed (osMutexId_t mutex_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMutexDestroyed, (uint32_t)mutex_id, 0U);
+#else
+  (void)mutex_id;
+#endif
+}
+#endif
+
+
+//  ==== Semaphore Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE))
+__WEAK void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreError, (uint32_t)semaphore_id, (uint32_t)status);
+#else
+  (void)semaphore_id;
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE))
+__WEAK void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxSemaphoreNew, max_count, initial_count, (uint32_t)attr, 0U);
+  if (attr != NULL) {
+    EventRecordData(EvtRtxSemaphoreNew_Detail, attr, sizeof (osSemaphoreAttr_t));
+  }
+#else
+  (void)max_count;
+  (void)initial_count;
+  (void)attr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE))
+__WEAK void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreCreated, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE))
+__WEAK void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreGetName, (uint32_t)semaphore_id, (uint32_t)name);
+  if (name != NULL) {
+    EventRecordData(EvtRtxSemaphoreGetName_Detail, name, strlen(name));
+  }
+#else
+#endif
+  (void)semaphore_id;
+  (void)name;
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE))
+__WEAK void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreAcquire, (uint32_t)semaphore_id, timeout);
+#else
+  (void)semaphore_id;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE))
+__WEAK void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreAcquirePending, (uint32_t)semaphore_id, (uint32_t)timeout);
+#else
+  (void)semaphore_id;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE))
+__WEAK void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreAcquireTimeout, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE))
+__WEAK void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE))
+__WEAK void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreNotAcquired, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE))
+__WEAK void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreRelease, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE))
+__WEAK void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE))
+__WEAK void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreGetCount, (uint32_t)semaphore_id, count);
+#else
+  (void)semaphore_id;
+  (void)count;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE))
+__WEAK void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreDelete, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE))
+__WEAK void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxSemaphoreDestroyed, (uint32_t)semaphore_id, 0U);
+#else
+  (void)semaphore_id;
+#endif
+}
+#endif
+
+
+//  ==== Memory Pool Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE))
+__WEAK void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolError, (uint32_t)mp_id, (uint32_t)status);
+#else
+  (void)mp_id;
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE))
+__WEAK void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMemoryPoolNew, block_count, block_size, (uint32_t)attr, 0U);
+  if (attr != NULL) {
+    EventRecordData(EvtRtxMemoryPoolNew_Detail, attr, sizeof (osMemoryPoolAttr_t));
+  }
+#else
+  (void)block_count;
+  (void)block_size;
+  (void)attr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE))
+__WEAK void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolCreated, (uint32_t)mp_id, 0U);
+#else
+  (void)mp_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE))
+__WEAK void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolGetName, (uint32_t)mp_id, (uint32_t)name);
+  if (name != NULL) {
+    EventRecordData(EvtRtxMemoryPoolGetName_Detail, name, strlen(name));
+  }
+#else
+  (void)mp_id;
+  (void)name;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE))
+__WEAK void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolAlloc, (uint32_t)mp_id, timeout);
+#else
+  (void)mp_id;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE))
+__WEAK void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolAllocPending, (uint32_t)mp_id, timeout);
+#else
+  (void)mp_id;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE))
+__WEAK void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolAllocTimeout, (uint32_t)mp_id, 0U);
+#else
+  (void)mp_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE))
+__WEAK void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolAllocated, (uint32_t)mp_id, (uint32_t)block);
+#else
+  (void)mp_id;
+  (void)block;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE))
+__WEAK void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolAllocFailed, (uint32_t)mp_id, 0U);
+#else
+  (void)mp_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE))
+__WEAK void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolFree, (uint32_t)mp_id, (uint32_t)block);
+#else
+  (void)mp_id;
+  (void)block;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE))
+__WEAK void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolDeallocated, (uint32_t)mp_id, (uint32_t)block);
+#else
+  (void)mp_id;
+  (void)block;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE))
+__WEAK void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolFreeFailed, (uint32_t)mp_id, (uint32_t)block);
+#else
+  (void)mp_id;
+  (void)block;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE))
+__WEAK void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolGetCapacity, (uint32_t)mp_id, capacity);
+#else
+  (void)mp_id;
+  (void)capacity;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE))
+__WEAK void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolGetBlockSize, (uint32_t)mp_id, block_size);
+#else
+  (void)mp_id;
+  (void)block_size;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE))
+__WEAK void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolGetCount, (uint32_t)mp_id, count);
+#else
+  (void)mp_id;
+  (void)count;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE))
+__WEAK void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolGetSpace, (uint32_t)mp_id, space);
+#else
+  (void)mp_id;
+  (void)space;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE))
+__WEAK void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolDelete, (uint32_t)mp_id, 0U);
+#else
+  (void)mp_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE))
+__WEAK void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMemoryPoolDestroyed, (uint32_t)mp_id, 0U);
+#else
+  (void)mp_id;
+#endif
+}
+#endif
+
+
+//  ==== Message Queue Events ====
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE))
+__WEAK void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2 (EvtRtxMessageQueueError, (uint32_t)mq_id, (uint32_t)status);
+#else
+  (void)mq_id;
+  (void)status;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE))
+__WEAK void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMessageQueueNew, msg_count, msg_size, (uint32_t)attr, 0U);
+  if (attr != NULL) {
+    EventRecordData(EvtRtxMessageQueueNew_Detail, attr, sizeof (osMemoryPoolAttr_t));
+  }
+#else
+  (void)msg_count;
+  (void)msg_size;
+  (void)attr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE))
+__WEAK void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueCreated, (uint32_t)mq_id, 0U);
+#else
+  (void)mq_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE))
+__WEAK void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueGetName, (uint32_t)mq_id, (uint32_t)name);
+  if (name != NULL) {
+    EventRecordData(EvtRtxMessageQueueGetName_Detail, name, strlen(name));
+  }
+#else
+  (void)mq_id;
+  (void)name;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE))
+__WEAK void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMessageQueuePut, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+  (void)msg_prio;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE))
+__WEAK void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMessageQueuePutPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE))
+__WEAK void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueuePutTimeout, (uint32_t)mq_id, 0U);
+#else
+  (void)mq_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE))
+__WEAK void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueInsertPending, (uint32_t)mq_id, (uint32_t)msg_ptr);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE))
+__WEAK void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueInserted, (uint32_t)mq_id, (uint32_t)msg_ptr);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE))
+__WEAK void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueNotInserted, (uint32_t)mq_id, (uint32_t)msg_ptr);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE))
+__WEAK void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMessageQueueGet, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+  (void)msg_prio;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE))
+__WEAK void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord4(EvtRtxMessageQueueGetPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+  (void)timeout;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE))
+__WEAK void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueGetTimeout, (uint32_t)mq_id, 0U);
+#else
+  (void)mq_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE))
+__WEAK void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE))
+__WEAK void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueNotRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr);
+#else
+  (void)mq_id;
+  (void)msg_ptr;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE))
+__WEAK void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueGetCapacity, (uint32_t)mq_id, capacity);
+#else
+  (void)mq_id;
+  (void)capacity;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE))
+__WEAK void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueGetMsgSize, (uint32_t)mq_id, msg_size);
+#else
+  (void)mq_id;
+  (void)msg_size;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE))
+__WEAK void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueGetCount, (uint32_t)mq_id, count);
+#else
+  (void)mq_id;
+  (void)count;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE))
+__WEAK void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueGetSpace, (uint32_t)mq_id, space);
+#else
+  (void)mq_id;
+  (void)space;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE))
+__WEAK void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueReset, (uint32_t)mq_id, 0U);
+#else
+  (void)mq_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE))
+__WEAK void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueResetDone, (uint32_t)mq_id, 0U);
+#else
+  (void)mq_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE))
+__WEAK void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueDelete, (uint32_t)mq_id, 0U);
+#else
+  (void)mq_id;
+#endif
+}
+#endif
+
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE))
+__WEAK void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id) {
+#if defined(RTE_Compiler_EventRecorder)
+  EventRecord2(EvtRtxMessageQueueDestroyed, (uint32_t)mq_id, 0U);
+#else
+  (void)mq_id;
+#endif
+}
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h
new file mode 100755
index 0000000..5bc4baa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_evr.h
@@ -0,0 +1,1847 @@
+/** \addtogroup rtos */
+/** @{*/
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Event Recorder definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#ifndef RTX_EVR_H_
+#define RTX_EVR_H_
+
+#include "cmsis_os2.h"                  // CMSIS RTOS API
+#include "rtx_os.h"                     // RTX OS definitions
+#include "RTX_Config.h"
+
+
+/// Extended Status codes
+#define osRtxErrorKernelNotReady        (-7)
+#define osRtxErrorKernelNotRunning      (-8)
+#define osRtxErrorInvalidControlBlock   (-9)
+#define osRtxErrorInvalidDataMemory     (-10)
+#define osRtxErrorInvalidThreadStack    (-11)
+#define osRtxErrorInvalidPriority       (-12)
+#define osRtxErrorThreadNotJoinable     (-13)
+#define osRtxErrorMutexNotOwned         (-14)
+#define osRtxErrorMutexNotLocked        (-15)
+#define osRtxErrorMutexLockLimit        (-16)
+#define osRtxErrorSemaphoreCountLimit   (-17)
+#define osRtxErrorTZ_InitContext_S      (-18)
+#define osRtxErrorTZ_AllocContext_S     (-19)
+#define osRtxErrorTZ_FreeContext_S      (-20)
+#define osRtxErrorTZ_LoadContext_S      (-21)
+#define osRtxErrorTZ_SaveContext_S      (-22)
+
+
+//  ==== Memory Events ====
+
+/**
+  \brief  Event on memory initialization (Op)
+  \param[in]  mem           pointer to memory pool.
+  \param[in]  size          size of a memory pool in bytes.
+  \param[in]  result        execution status: 1 - success, 0 - failure.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE))
+extern void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result);
+#else
+#define EvrRtxMemoryInit(mem, size, result)
+#endif
+
+/**
+  \brief  Event on memory allocate (Op)
+  \param[in]  mem           pointer to memory pool.
+  \param[in]  size          size of a memory block in bytes.
+  \param[in]  type          memory block type: 0 - generic, 1 - control block
+  \param[in]  block         pointer to allocated memory block or NULL in case of no memory is available.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE))
+extern void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block);
+#else
+#define EvrRtxMemoryAlloc(mem, size, type, block)
+#endif
+
+/**
+  \brief  Event on memory free (Op)
+  \param[in]  mem           pointer to memory pool.
+  \param[in]  block         memory block to be returned to the memory pool.
+  \param[in]  result        execution status: 1 - success, 0 - failure.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE))
+extern void EvrRtxMemoryFree (void *mem, void *block, uint32_t result);
+#else
+#define EvrRtxMemoryFree(mem, block, result)
+#endif
+
+/**
+  \brief  Event on memory block initialization (Op)
+  \param[in]  mp_info       memory pool info.
+  \param[in]  block_count   maximum number of memory blocks in memory pool.
+  \param[in]  block_size    size of a memory block in bytes.
+  \param[in]  block_mem     pointer to memory for block storage.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE))
+extern void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem);
+#else
+#define EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem)
+#endif
+
+/**
+  \brief  Event on memory block alloc (Op)
+  \param[in]  mp_info       memory pool info.
+  \param[in]  block         address of the allocated memory block or NULL in case of no memory is available.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE))
+extern void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block);
+#else
+#define EvrRtxMemoryBlockAlloc(mp_info, block)
+#endif
+
+/**
+  \brief  Event on memory block free (Op)
+  \param[in]  mp_info       memory pool info.
+  \param[in]  block         address of the allocated memory block to be returned to the memory pool.
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE))
+extern void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status);
+#else
+#define EvrRtxMemoryBlockFree(mp_info, block, status)
+#endif
+
+
+//  ==== Kernel Events ====
+
+/**
+  \brief  Event on RTOS kernel error (Error)
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE))
+extern void EvrRtxKernelError (int32_t status);
+#else
+#define EvrRtxKernelError(status)
+#endif
+
+/**
+  \brief  Event on RTOS kernel initialize (API)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE))
+extern void EvrRtxKernelInitialize (void);
+#else
+#define EvrRtxKernelInitialize()
+#endif
+
+/**
+  \brief  Event on successful RTOS kernel initialize (Op)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_COMPLETED_DISABLE))
+extern void EvrRtxKernelInitializeCompleted (void);
+#else
+#define EvrRtxKernelInitializeCompleted()
+#endif
+
+/**
+  \brief  Event on RTOS kernel information retrieve (API)
+  \param[in]  version       pointer to buffer for retrieving version information.
+  \param[in]  id_buf        pointer to buffer for retrieving kernel identification string.
+  \param[in]  id_size       size of buffer for kernel identification string.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE))
+extern void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+#else
+#define EvrRtxKernelGetInfo(version, id_buf, id_size)
+#endif
+
+/**
+  \brief  Event on successful RTOS kernel information retrieve (Op)
+  \param[in]  version       pointer to buffer for retrieving version information.
+  \param[in]  id_buf        pointer to buffer for retrieving kernel identification string.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE))
+extern void EvrRtxKernelInfoRetrieved (osVersion_t *version, char *id_buf);
+#else
+#define EvrRtxKernelInfoRetrieved(version, id_buf)
+#endif
+
+/**
+  \brief  Event on current RTOS Kernel state retrieve (API)
+  \param[in]  state         current RTOS Kernel state.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE))
+extern void EvrRtxKernelGetState (osKernelState_t state);
+#else
+#define EvrRtxKernelGetState(state)
+#endif
+
+/**
+  \brief  Event on RTOS Kernel scheduler start (API)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE))
+extern void EvrRtxKernelStart (void);
+#else
+#define EvrRtxKernelStart()
+#endif
+
+/**
+  \brief  Event on successful RTOS Kernel scheduler start (Op)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE))
+extern void EvrRtxKernelStarted (void);
+#else
+#define EvrRtxKernelStarted()
+#endif
+
+/**
+  \brief  Event on RTOS Kernel scheduler lock (API)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE))
+extern void EvrRtxKernelLock (void);
+#else
+#define EvrRtxKernelLock()
+#endif
+
+/**
+  \brief  Event on successful RTOS Kernel scheduler lock (Op)
+  \param[in]  lock          previous lock state (1 - locked, 0 - not locked).
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE))
+extern void EvrRtxKernelLocked (int32_t lock);
+#else
+#define EvrRtxKernelLocked(lock)
+#endif
+
+/**
+  \brief  Event on RTOS Kernel scheduler unlock (API)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE))
+extern void EvrRtxKernelUnlock (void);
+#else
+#define EvrRtxKernelUnlock()
+#endif
+
+/**
+  \brief  Event on successful RTOS Kernel scheduler unlock (Op)
+  \param[in]  lock          previous lock state (1 - locked, 0 - not locked).
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE))
+extern void EvrRtxKernelUnlocked (int32_t lock);
+#else
+#define EvrRtxKernelUnlocked(lock)
+#endif
+
+/**
+  \brief  Event on RTOS Kernel scheduler lock state restore (API)
+  \param[in]  lock          lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE))
+extern void EvrRtxKernelRestoreLock (int32_t lock);
+#else
+#define EvrRtxKernelRestoreLock(lock)
+#endif
+
+/**
+  \brief  Event on successful RTOS Kernel scheduler lock state restore (Op)
+  \param[in]  lock          new lock state (1 - locked, 0 - not locked).
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE))
+extern void EvrRtxKernelLockRestored (int32_t lock);
+#else
+#define EvrRtxKernelLockRestored(lock)
+#endif
+
+/**
+  \brief  Event on RTOS Kernel scheduler suspend (API)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE))
+extern void EvrRtxKernelSuspend (void);
+#else
+#define EvrRtxKernelSuspend()
+#endif
+
+/**
+  \brief  Event on successful RTOS Kernel scheduler suspend (Op)
+  \param[in]  sleep_ticks   time in ticks, for how long the system can sleep or power-down.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE))
+extern void EvrRtxKernelSuspended (uint32_t sleep_ticks);
+#else
+#define EvrRtxKernelSuspended(sleep_ticks)
+#endif
+
+/**
+  \brief  Event on RTOS Kernel scheduler resume (API)
+  \param[in]  sleep_ticks   time in ticks, for how long the system was in sleep or power-down mode.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE))
+extern void EvrRtxKernelResume (uint32_t sleep_ticks);
+#else
+#define EvrRtxKernelResume(sleep_ticks)
+#endif
+
+/**
+  \brief  Event on successful RTOS Kernel scheduler resume (Op)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE))
+extern void EvrRtxKernelResumed (void);
+#else
+#define EvrRtxKernelResumed()
+#endif
+
+/**
+  \brief  Event on RTOS kernel tick count retrieve (API)
+  \param[in]  count         RTOS kernel current tick count.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE))
+extern void EvrRtxKernelGetTickCount (uint64_t count);
+#else
+#define EvrRtxKernelGetTickCount(count)
+#endif
+
+/**
+  \brief  Event on RTOS kernel tick frequency retrieve (API)
+  \param[in]  freq          frequency of the kernel tick.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE))
+extern void EvrRtxKernelGetTickFreq (uint32_t freq);
+#else
+#define EvrRtxKernelGetTickFreq(freq)
+#endif
+
+/**
+  \brief  Event on RTOS kernel system timer count retrieve (API)
+  \param[in]  count         RTOS kernel current system timer count as 32-bit value.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE))
+extern void EvrRtxKernelGetSysTimerCount (uint32_t count);
+#else
+#define EvrRtxKernelGetSysTimerCount(count)
+#endif
+
+/**
+  \brief  Event on RTOS kernel system timer frequency retrieve (API)
+  \param[in]  freq          frequency of the system timer.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE))
+extern void EvrRtxKernelGetSysTimerFreq (uint32_t freq);
+#else
+#define EvrRtxKernelGetSysTimerFreq(freq)
+#endif
+
+
+//  ==== Thread Events ====
+
+/**
+  \brief  Event on thread error (Error)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId or NULL when ID is unknown.
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE))
+extern void EvrRtxThreadError (osThreadId_t thread_id, int32_t status);
+#else
+#define EvrRtxThreadError(thread_id, status)
+#endif
+
+/**
+  \brief  Event on thread create and intialize (API)
+  \param[in]  func          thread function.
+  \param[in]  argument      pointer that is passed to the thread function as start argument.
+  \param[in]  attr          thread attributes.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE))
+extern void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+#else
+#define EvrRtxThreadNew(func, argument, attr)
+#endif
+
+/**
+  \brief  Event on successful thread create (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE))
+extern void EvrRtxThreadCreated (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadCreated(thread_id)
+#endif
+
+/**
+  \brief  Event on thread name retrieve (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  name          pointer to thread object name
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE))
+extern void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name);
+#else
+#define EvrRtxThreadGetName(thread_id, name)
+#endif
+
+/**
+  \brief  Event on current running thread ID retrieve (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE))
+extern void EvrRtxThreadGetId (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadGetId(thread_id)
+#endif
+
+/**
+  \brief  Event on thread state retrieve (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  state         current thread state of the specified thread.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE))
+extern void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state);
+#else
+#define EvrRtxThreadGetState(thread_id, state)
+#endif
+
+/**
+  \brief  Event on thread stack size retrieve (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  stack_size    stack size in bytes.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE))
+extern void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size);
+#else
+#define EvrRtxThreadGetStackSize(thread_id, stack_size)
+#endif
+
+/**
+  \brief  Event on available stack space retrieve (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  stack_space   remaining stack space in bytes.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE))
+extern void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space);
+#else
+#define EvrRtxThreadGetStackSpace(thread_id, stack_space)
+#endif
+
+/**
+  \brief  Event on thread priority set (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  priority      new priority value for the thread function.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE))
+extern void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+#else
+#define EvrRtxThreadSetPriority(thread_id, priority)
+#endif
+
+/**
+  \brief  Event on thread priority retrieve (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  priority      current priority value of the specified thread.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE))
+extern void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority);
+#else
+#define EvrRtxThreadGetPriority(thread_id, priority)
+#endif
+
+/**
+  \brief  Event on thread yield (API)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE))
+extern void EvrRtxThreadYield (void);
+#else
+#define EvrRtxThreadYield()
+#endif
+
+/**
+  \brief  Event on thread suspend (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE))
+extern void EvrRtxThreadSuspend (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadSuspend(thread_id)
+#endif
+
+/**
+  \brief  Event on successful thread suspend (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE))
+extern void EvrRtxThreadSuspended (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadSuspended(thread_id)
+#endif
+
+/**
+  \brief  Event on thread resume (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE))
+extern void EvrRtxThreadResume (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadResume(thread_id)
+#endif
+
+/**
+  \brief  Event on successful thread resume (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE))
+extern void EvrRtxThreadResumed (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadResumed(thread_id)
+#endif
+
+/**
+  \brief  Event on thread detach (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE))
+extern void EvrRtxThreadDetach (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadDetach(thread_id)
+#endif
+
+/**
+  \brief  Event on successful thread detach (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE))
+extern void EvrRtxThreadDetached (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadDetached(thread_id)
+#endif
+
+/**
+  \brief  Event on thread join (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE))
+extern void EvrRtxThreadJoin (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadJoin(thread_id)
+#endif
+
+/**
+  \brief  Event on pending thread join (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE))
+extern void EvrRtxThreadJoinPending (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadJoinPending(thread_id)
+#endif
+
+/**
+  \brief  Event on successful thread join (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE))
+extern void EvrRtxThreadJoined (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadJoined(thread_id)
+#endif
+
+/**
+  \brief  Event on thread execution block (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE))
+extern void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout);
+#else
+#define EvrRtxThreadBlocked(thread_id, timeout)
+#endif
+
+/**
+  \brief  Event on blocked thread release (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  ret_val       extended execution status of the thread.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE))
+extern void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val);
+#else
+#define EvrRtxThreadUnblocked(thread_id, ret_val)
+#endif
+
+/**
+  \brief  Event on current running thread switch (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCH_DISABLE))
+extern void EvrRtxThreadSwitch (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadSwitch(thread_id)
+#endif
+
+/**
+  \brief  Event on thread exit (API)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE))
+extern void EvrRtxThreadExit (void);
+#else
+#define EvrRtxThreadExit()
+#endif
+
+/**
+  \brief  Event on thread terminate (API)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE))
+extern void EvrRtxThreadTerminate (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadTerminate(thread_id)
+#endif
+
+/**
+  \brief  Event on successful thread terminate (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE))
+extern void EvrRtxThreadDestroyed (osThreadId_t thread_id);
+#else
+#define EvrRtxThreadDestroyed(thread_id)
+#endif
+
+/**
+  \brief  Event on active thread count retrieve (API)
+  \param[in]  count         number of active threads.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE))
+extern void EvrRtxThreadGetCount (uint32_t count);
+#else
+#define EvrRtxThreadGetCount(count)
+#endif
+
+/**
+  \brief  Event on active threads enumerate (API)
+  \param[in]  thread_array  pointer to array for retrieving thread IDs.
+  \param[in]  array_items   maximum number of items in array for retrieving thread IDs.
+  \param[in]  count         number of enumerated threads.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE))
+extern void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count);
+#else
+#define EvrRtxThreadEnumerate(thread_array, array_items, count)
+#endif
+
+/**
+  \brief  Event on thread flags set (API)
+  \param[in]   thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]   flags         flags of the thread that shall be set.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE))
+extern void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+#else
+#define EvrRtxThreadFlagsSet(thread_id, flags)
+#endif
+
+/**
+  \brief  Event on successful thread flags set (Op)
+  \param[in]  thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+  \param[in]  thread_flags  thread flags after setting
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE))
+extern void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags);
+#else
+#define EvrRtxThreadFlagsSetDone(thread_id, thread_flags)
+#endif
+
+/**
+  \brief  Event on thread flags clear (API)
+  \param[in]  flags         flags of the thread that shall be cleared.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE))
+extern void EvrRtxThreadFlagsClear (uint32_t flags);
+#else
+#define EvrRtxThreadFlagsClear(flags)
+#endif
+
+/**
+  \brief  Event on successful thread flags clear (Op)
+  \param[in]  thread_flags  thread flags before clearing
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE))
+extern void EvrRtxThreadFlagsClearDone (uint32_t thread_flags);
+#else
+#define EvrRtxThreadFlagsClearDone(thread_flags)
+#endif
+
+/**
+  \brief  Event on thread flags retrieve (API)
+  \param[in]  thread_flags  current thread flags.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE))
+extern void EvrRtxThreadFlagsGet (uint32_t thread_flags);
+#else
+#define EvrRtxThreadFlagsGet(thread_flags)
+#endif
+
+/**
+  \brief  Event on wait for thread flags (API)
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE))
+extern void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+#else
+#define EvrRtxThreadFlagsWait(flags, options, timeout)
+#endif
+
+/**
+  \brief  Event on pending wait for thread flags (Op)
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE))
+extern void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout);
+#else
+#define EvrRtxThreadFlagsWaitPending(flags, options, timeout)
+#endif
+
+/**
+  \brief  Event on wait timeout for thread flags (Op)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE))
+extern void EvrRtxThreadFlagsWaitTimeout (void);
+#else
+#define EvrRtxThreadFlagsWaitTimeout()
+#endif
+
+/**
+  \brief  Event on successful wait for thread flags (Op)
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+  \param[in]  thread_flags  thread flags before clearing
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE))
+extern void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags);
+#else
+#define EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags)
+#endif
+
+/**
+  \brief  Event on unsuccessful wait for thread flags (Op)
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
+extern void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options);
+#else
+#define EvrRtxThreadFlagsWaitNotCompleted(flags, options)
+#endif
+
+/**
+  \brief  Event on wait for timeout (API)
+  \param[in]  ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_DISABLE))
+extern void EvrRtxThreadDelay (uint32_t ticks);
+#else
+#define EvrRtxThreadDelay(ticks)
+#endif
+
+/**
+  \brief  Event on wait until specified time (API)
+  \param[in]  ticks         absolute time in ticks
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_UNTIL_DISABLE))
+extern void EvrRtxThreadDelayUntil (uint64_t ticks);
+#else
+#define EvrRtxThreadDelayUntil(ticks)
+#endif
+
+/**
+  \brief  Event on completed wait (Op)
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_COMPLETED_DISABLE))
+extern void EvrRtxThreadDelayCompleted (void);
+#else
+#define EvrRtxThreadDelayCompleted()
+#endif
+
+
+
+//  ==== Timer Events ====
+
+/**
+  \brief  Event on timer error (Error)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew or NULL when ID is unknown.
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE))
+extern void EvrRtxTimerError (osTimerId_t timer_id, int32_t status);
+#else
+#define EvrRtxTimerError(timer_id, status);
+#endif
+
+/**
+  \brief  Event on timer callback call (Op)
+  \param[in]  func          start address of a timer call back function.
+  \param[in]  argument      argument to the timer call back function.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE))
+extern void EvrRtxTimerCallback (osTimerFunc_t func, void *argument);
+#else
+#define EvrRtxTimerCallback(func, argument);
+#endif
+
+/**
+  \brief  Event on timer create and initialize (API)
+  \param[in]  func          start address of a timer call back function.
+  \param[in]  type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+  \param[in]  argument      argument to the timer call back function.
+  \param[in]  attr          timer attributes.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE))
+extern void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+#else
+#define EvrRtxTimerNew(func, type, argument, attr);
+#endif
+
+/**
+  \brief  Event on successful timer create (Op)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE))
+extern void EvrRtxTimerCreated (osTimerId_t timer_id);
+#else
+#define EvrRtxTimerCreated(timer_id);
+#endif
+
+/**
+  \brief  Event on timer name retrieve (API)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+  \param[in]  name          pointer to timer object name.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE))
+extern void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name);
+#else
+#define EvrRtxTimerGetName(timer_id, name);
+#endif
+
+/**
+  \brief  Event on timer start (API)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+  \param[in]  ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE))
+extern void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks);
+#else
+#define EvrRtxTimerStart(timer_id, ticks);
+#endif
+
+/**
+  \brief  Event on successful timer start (Op)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE))
+extern void EvrRtxTimerStarted (osTimerId_t timer_id);
+#else
+#define EvrRtxTimerStarted(timer_id);
+#endif
+
+/**
+  \brief  Event on timer stop (API)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE))
+extern void EvrRtxTimerStop (osTimerId_t timer_id);
+#else
+#define EvrRtxTimerStop(timer_id);
+#endif
+
+/**
+  \brief  Event on successful timer stop (Op)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE))
+extern void EvrRtxTimerStopped (osTimerId_t timer_id);
+#else
+#define EvrRtxTimerStopped(timer_id);
+#endif
+
+/**
+  \brief  Event on timer running state check (API)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+  \param[in]  running       running state: 0 not running, 1 running
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE))
+extern void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running);
+#else
+#define EvrRtxTimerIsRunning(timer_id, running);
+#endif
+
+/**
+  \brief  Event on timer delete (API)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE))
+extern void EvrRtxTimerDelete (osTimerId_t timer_id);
+#else
+#define EvrRtxTimerDelete(timer_id);
+#endif
+
+/**
+  \brief  Event on successful timer delete (Op)
+  \param[in]  timer_id      timer ID obtained by \ref osTimerNew
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE))
+extern void EvrRtxTimerDestroyed (osTimerId_t timer_id);
+#else
+#define EvrRtxTimerDestroyed(timer_id);
+#endif
+
+
+//  ==== Event Flags Events ====
+
+/**
+  \brief  Event on event flags error (Error)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew or NULL when ID is unknown.
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE))
+extern void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status);
+#else
+#define EvrRtxEventFlagsError(ef_id, status)
+#endif
+
+/**
+  \brief  Event on event flags create and initialize (API)
+  \param[in]  attr          event flags attributes
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE))
+extern void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr);
+#else
+#define EvrRtxEventFlagsNew(attr)
+#endif
+
+/**
+  \brief  Event on successful event flags create (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE))
+extern void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id);
+#else
+#define EvrRtxEventFlagsCreated(ef_id)
+#endif
+
+/**
+  \brief  Event on event flags name retrieve (API)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  name          pointer to event flags object name.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE))
+extern void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name);
+#else
+#define EvrRtxEventFlagsGetName(ef_id, name)
+#endif
+
+/**
+  \brief  Event on event flags set (API)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  flags         flags that shall be set.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE))
+extern void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+#else
+#define EvrRtxEventFlagsSet(ef_id, flags)
+#endif
+
+/**
+  \brief  Event on successful event flags set (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  event_flags   event flags after setting
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE))
+extern void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags);
+#else
+#define EvrRtxEventFlagsSetDone(ef_id, event_flags)
+#endif
+
+/**
+  \brief  Event on event flags clear (API)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  flags         flags that shall be cleared.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE))
+extern void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+#else
+#define EvrRtxEventFlagsClear(ef_id, flags)
+#endif
+
+/**
+  \brief  Event on successful event flags clear (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  event_flags   event flags before clearing
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE))
+extern void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags);
+#else
+#define EvrRtxEventFlagsClearDone(ef_id, event_flags)
+#endif
+
+/**
+  \brief  Event on event flags retrieve (API)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  event_flags   current event flags.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE))
+extern void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags);
+#else
+#define EvrRtxEventFlagsGet(ef_id, event_flags)
+#endif
+
+/**
+  \brief  Event on wait for event flags (API)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE))
+extern void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+#else
+#define EvrRtxEventFlagsWait(ef_id, flags, options, timeout)
+#endif
+
+/**
+  \brief  Event on pending wait for event flags (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE))
+extern void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+#else
+#define EvrRtxEventFlagsWaitPending(ef_id, flags, options, timeout)
+#endif
+
+/**
+  \brief  Event on wait timeout for event flags (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE))
+extern void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id);
+#else
+#define EvrRtxEventFlagsWaitTimeout(ef_id)
+#endif
+
+/**
+  \brief  Event on successful wait for event flags (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+  \param[in]  event_flags   event flags before clearing or 0 if specified flags have not been set.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE))
+extern void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags);
+#else
+#define EvrRtxEventFlagsWaitCompleted(ef_id, flags, options, event_flags)
+#endif
+
+/**
+  \brief  Event on unsuccessful wait for event flags (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+  \param[in]  flags         flags to wait for.
+  \param[in]  options       flags options (osFlagsXxxx).
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
+extern void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options);
+#else
+#define EvrRtxEventFlagsWaitNotCompleted(ef_id, flags, options)
+#endif
+
+/**
+  \brief  Event on event flags delete (API)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE))
+extern void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id);
+#else
+#define EvrRtxEventFlagsDelete(ef_id)
+#endif
+
+/**
+  \brief  Event on successful event flags delete (Op)
+  \param[in]  ef_id         event flags ID obtained by \ref osEventFlagsNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE))
+extern void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id);
+#else
+#define EvrRtxEventFlagsDestroyed(ef_id)
+#endif
+
+
+//  ==== Mutex Events ====
+
+/**
+  \brief  Event on mutex error (Error)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew or NULL when ID is unknown.
+  \param[in]  status    extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE))
+extern void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status);
+#else
+#define EvrRtxMutexError(mutex_id, status)
+#endif
+
+/**
+  \brief  Event on mutex create and initialize (API)
+  \param[in]  attr      mutex attributes
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE))
+extern void EvrRtxMutexNew (const osMutexAttr_t *attr);
+#else
+#define EvrRtxMutexNew(attr)
+#endif
+
+/**
+  \brief  Event on successful mutex create (Op)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE))
+extern void EvrRtxMutexCreated (osMutexId_t mutex_id);
+#else
+#define EvrRtxMutexCreated(mutex_id)
+#endif
+
+/**
+  \brief  Event on mutex name retrieve (API)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+  \param[in]  name      pointer to mutex object name
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE))
+extern void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name);
+#else
+#define EvrRtxMutexGetName(mutex_id, name)
+#endif
+
+/**
+  \brief  Event on mutex acquire (API)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+  \param[in]  timeout   \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE))
+extern void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+#else
+#define EvrRtxMutexAcquire(mutex_id, timeout)
+#endif
+
+/**
+  \brief  Event on pending mutex acquire (Op)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+  \param[in]  timeout   \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE))
+extern void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout);
+#else
+#define EvrRtxMutexAcquirePending(mutex_id, timeout);
+#endif
+
+/**
+  \brief  Event on mutex acquire timeout (Op)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE))
+extern void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id);
+#else
+#define EvrRtxMutexAcquireTimeout(mutex_id)
+#endif
+
+/**
+  \brief  Event on successful mutex acquire (Op)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+  \param[in]  lock      current number of times mutex object is locked
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE))
+extern void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock);
+#else
+#define EvrRtxMutexAcquired(mutex_id, lock)
+#endif
+
+/**
+  \brief  Event on unsuccessful mutex acquire (Op)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE))
+extern void EvrRtxMutexNotAcquired (osMutexId_t mutex_id);
+#else
+#define EvrRtxMutexNotAcquired(mutex_id)
+#endif
+
+/**
+  \brief  Event on mutex release (API)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE))
+extern void EvrRtxMutexRelease (osMutexId_t mutex_id);
+#else
+#define EvrRtxMutexRelease(mutex_id)
+#endif
+
+/**
+  \brief  Event on successful mutex release (Op)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+  \param[in]  lock      current number of times mutex object is locked
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE))
+extern void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock);
+#else
+#define EvrRtxMutexReleased(mutex_id, lock)
+#endif
+
+/**
+  \brief  Event on mutex owner retrieve (API)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+  \param[in]  thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE))
+extern void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id);
+#else
+#define EvrRtxMutexGetOwner(mutex_id, thread_id)
+#endif
+
+/**
+  \brief  Event on mutex delete (API)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE))
+extern void EvrRtxMutexDelete (osMutexId_t mutex_id);
+#else
+#define EvrRtxMutexDelete(mutex_id)
+#endif
+
+/**
+  \brief  Event on successful mutex delete (Op)
+  \param[in]  mutex_id  mutex ID obtained by \ref osMutexNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE))
+extern void EvrRtxMutexDestroyed (osMutexId_t mutex_id);
+#else
+#define EvrRtxMutexDestroyed(mutex_id)
+#endif
+
+
+//  ==== Semaphore Events ====
+
+/**
+  \brief  Event on semaphore error (Error)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew or NULL when ID is unknown.
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE))
+extern void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status);
+#else
+#define EvrRtxSemaphoreError(semaphore_id, status)
+#endif
+
+/**
+  \brief  Event on semaphore create and initialize (API)
+  \param[in]  max_count     maximum number of available tokens.
+  \param[in]  initial_count initial number of available tokens.
+  \param[in]  attr          semaphore attributes.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE))
+extern void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+#else
+#define EvrRtxSemaphoreNew(max_count, initial_count, attr)
+#endif
+
+/**
+  \brief  Event on successful semaphore create (Op)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE))
+extern void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreCreated(semaphore_id)
+#endif
+
+/**
+  \brief  Event on semaphore name retrieve (API)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+  \param[in]  name          pointer to semaphore object name.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE))
+extern void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name);
+#else
+#define EvrRtxSemaphoreGetName(semaphore_id, name)
+#endif
+
+/**
+  \brief  Event on semaphore acquire (API)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE))
+extern void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+#else
+#define EvrRtxSemaphoreAcquire(semaphore_id, timeout)
+#endif
+
+/**
+  \brief  Event on pending semaphore acquire (Op)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE))
+extern void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout);
+#else
+#define EvrRtxSemaphoreAcquirePending(semaphore_id, timeout);
+#endif
+
+/**
+  \brief  Event on semaphore acquire timeout (Op)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE))
+extern void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreAcquireTimeout(semaphore_id)
+#endif
+
+/**
+  \brief  Event on successful semaphore acquire (Op)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE))
+extern void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreAcquired(semaphore_id)
+#endif
+
+/**
+  \brief  Event on unsuccessful semaphore acquire (Op)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE))
+extern void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreNotAcquired(semaphore_id)
+#endif
+
+/**
+  \brief  Event on semaphore release (API)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE))
+extern void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreRelease(semaphore_id)
+#endif
+
+/**
+  \brief  Event on successful semaphore release (Op)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE))
+extern void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreReleased(semaphore_id)
+#endif
+
+/**
+  \brief  Event on semaphore token count retrieval (API)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+  \param[in]  count         current number of available tokens.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE))
+extern void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count);
+#else
+#define EvrRtxSemaphoreGetCount(semaphore_id, count)
+#endif
+
+/**
+  \brief  Event on semaphore delete (API)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE))
+extern void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreDelete(semaphore_id)
+#endif
+
+/**
+  \brief  Event on successful semaphore delete (Op)
+  \param[in]  semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE))
+extern void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id);
+#else
+#define EvrRtxSemaphoreDestroyed(semaphore_id)
+#endif
+
+
+//  ==== Memory Pool Events ====
+
+/**
+  \brief  Event on memory pool error (Error)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew or NULL when ID is unknown.
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE))
+extern void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status);
+#else
+#define EvrRtxMemoryPoolError(mp_id, status)
+#endif
+
+/**
+  \brief  Event on memory pool create and initialize (API)
+  \param[in]  block_count   maximum number of memory blocks in memory pool.
+  \param[in]  block_size    memory block size in bytes.
+  \param[in]  attr          memory pool attributes; NULL: default values.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE))
+extern void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+#else
+#define EvrRtxMemoryPoolNew(block_count, block_size, attr)
+#endif
+
+/**
+  \brief  Event on successful memory pool create (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE))
+extern void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id);
+#else
+#define EvrRtxMemoryPoolCreated(mp_id)
+#endif
+
+/**
+  \brief  Event on memory pool name retrieve (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  name          pointer to memory pool object name.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE))
+extern void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name);
+#else
+#define EvrRtxMemoryPoolGetName(mp_id, name)
+#endif
+
+/**
+  \brief  Event on memory pool allocation (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE))
+extern void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+#else
+#define EvrRtxMemoryPoolAlloc(mp_id, timeout)
+#endif
+
+/**
+  \brief  Event on pending memory pool allocation (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE))
+extern void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout);
+#else
+#define EvrRtxMemoryPoolAllocPending(mp_id, timeout)
+#endif
+
+/**
+  \brief  Event on memory pool allocation timeout (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE))
+extern void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id);
+#else
+#define EvrRtxMemoryPoolAllocTimeout(mp_id)
+#endif
+
+/**
+  \brief  Event on successful memory pool allocation (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  block         address of the allocated memory block.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE))
+extern void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block);
+#else
+#define EvrRtxMemoryPoolAllocated(mp_id, block)
+#endif
+
+/**
+  \brief  Event on unsuccessful memory pool allocation (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE))
+extern void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id);
+#else
+#define EvrRtxMemoryPoolAllocFailed(mp_id)
+#endif
+
+/**
+  \brief  Event on memory pool free (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  block         address of the allocated memory block to be returned to the memory pool.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE))
+extern void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+#else
+#define EvrRtxMemoryPoolFree(mp_id, block)
+#endif
+
+/**
+  \brief  Event on successful memory pool free (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  block         address of the allocated memory block to be returned to the memory pool.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE))
+extern void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block);
+#else
+#define EvrRtxMemoryPoolDeallocated(mp_id, block)
+#endif
+
+/**
+  \brief  Event on unsuccessful memory pool free (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  block         address of the allocated memory block to be returned to the memory pool.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE))
+extern void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block);
+#else
+#define EvrRtxMemoryPoolFreeFailed(mp_id, block)
+#endif
+
+/**
+  \brief  Event on memory pool capacity retrieve (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  capacity      maximum number of memory blocks.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE))
+extern void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity);
+#else
+#define EvrRtxMemoryPoolGetCapacity(mp_id, capacity)
+#endif
+
+/**
+  \brief  Event on memory pool block size retrieve (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  block_size    memory block size in bytes.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE))
+extern void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size);
+#else
+#define EvrRtxMemoryPoolGetBlockSize(mp_id, block_size)
+#endif
+
+/**
+  \brief  Event on used memory pool blocks retrieve (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  count         number of memory blocks used.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE))
+extern void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count);
+#else
+#define EvrRtxMemoryPoolGetCount(mp_id, count)
+#endif
+
+/**
+  \brief  Event on available memory pool blocks retrieve (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+  \param[in]  space         number of memory blocks available.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE))
+extern void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space);
+#else
+#define EvrRtxMemoryPoolGetSpace(mp_id, space)
+#endif
+
+/**
+  \brief  Event on memory pool delete (API)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE))
+extern void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id);
+#else
+#define EvrRtxMemoryPoolDelete(mp_id)
+#endif
+
+/**
+  \brief  Event on successful memory pool delete (Op)
+  \param[in]  mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE))
+extern void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id);
+#else
+#define EvrRtxMemoryPoolDestroyed(mp_id)
+#endif
+
+
+//  ==== Message Queue Events ====
+
+/**
+  \brief  Event on message queue error (Error)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew or NULL when ID is unknown.
+  \param[in]  status        extended execution status.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE))
+extern void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status);
+#else
+#define EvrRtxMessageQueueError(mq_id, status)
+#endif
+
+/**
+  \brief  Event on message queue create and initialization (API)
+  \param[in]  msg_count     maximum number of messages in queue.
+  \param[in]  msg_size      maximum message size in bytes.
+  \param[in]  attr          message queue attributes; NULL: default values.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE))
+extern void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+#else
+#define EvrRtxMessageQueueNew(msg_count, msg_size, attr)
+#endif
+
+/**
+  \brief  Event on successful message queue create (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE))
+extern void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id);
+#else
+#define EvrRtxMessageQueueCreated(mq_id)
+#endif
+
+/**
+  \brief  Event on message queue name retrieve(API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  name          pointer to message queue object name.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE))
+extern void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name);
+#else
+#define EvrRtxMessageQueueGetName(mq_id, name)
+#endif
+
+/**
+  \brief  Event on message put (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer with message to put into a queue.
+  \param[in]  msg_prio      message priority.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE))
+extern void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+#else
+#define EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout)
+#endif
+
+/**
+  \brief  Event on pending message put (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer with message to put into a queue.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE))
+extern void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout);
+#else
+#define EvrRtxMessageQueuePutPending(mq_id, msg_ptr, timeout)
+#endif
+
+/**
+  \brief  Event on message put timeout (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE))
+extern void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id);
+#else
+#define EvrRtxMessageQueuePutTimeout(mq_id)
+#endif
+
+/**
+  \brief  Event on pending message insert (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer with message to put into a queue.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE))
+extern void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr);
+#else
+#define EvrRtxMessageQueueInsertPending(mq_id, msg_ptr)
+#endif
+
+/**
+  \brief  Event on successful message insert (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer with message to put into a queue.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE))
+extern void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr);
+#else
+#define EvrRtxMessageQueueInserted(mq_id, msg_ptr)
+#endif
+
+/**
+  \brief  Event on unsuccessful message insert (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer with message to put into a queue.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE))
+extern void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr);
+#else
+#define EvrRtxMessageQueueNotInserted(mq_id, msg_ptr)
+#endif
+
+/**
+  \brief  Event on message get (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer for message to get from a queue.
+  \param[in]  msg_prio      message priority.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE))
+extern void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+#else
+#define EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout)
+#endif
+
+/**
+  \brief  Event on pending message get (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer for message to get from a queue.
+  \param[in]  timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE))
+extern void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout);
+#else
+#define EvrRtxMessageQueueGetPending(mq_id, msg_ptr, timeout)
+#endif
+
+/**
+  \brief  Event on message get timeout (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE))
+extern void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id);
+#else
+#define EvrRtxMessageQueueGetTimeout(mq_id)
+#endif
+
+/**
+  \brief  Event on successful message get (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer for message to get from a queue.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE))
+extern void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr);
+#else
+#define EvrRtxMessageQueueRetrieved(mq_id, msg_ptr)
+#endif
+
+/**
+  \brief  Event on unsuccessful message get (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_ptr       pointer to buffer for message to get from a queue.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE))
+extern void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr);
+#else
+#define EvrRtxMessageQueueNotRetrieved(mq_id, msg_ptr)
+#endif
+
+/**
+  \brief  Event on message queue capacity retrieve (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  capacity      maximum number of messages.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE))
+extern void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity);
+#else
+#define EvrRtxMessageQueueGetCapacity(mq_id, capacity)
+#endif
+
+/**
+  \brief  Event on message queue message size retrieve (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  msg_size      maximum message size in bytes.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE))
+extern void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size);
+#else
+#define EvrRtxMessageQueueGetMsgSize(mq_id, msg_size)
+#endif
+
+/**
+  \brief  Event on message queue message count retrieve (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  count         number of queued messages.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE))
+extern void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count);
+#else
+#define EvrRtxMessageQueueGetCount(mq_id, count)
+#endif
+
+/**
+  \brief  Event on message queue message slots retrieve (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+  \param[in]  space         number of available slots for messages.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE))
+extern void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space);
+#else
+#define EvrRtxMessageQueueGetSpace(mq_id, space)
+#endif
+
+/**
+  \brief  Event on message queue reset (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE))
+extern void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id);
+#else
+#define EvrRtxMessageQueueReset(mq_id)
+#endif
+
+/**
+  \brief  Event on successful message queue reset (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE))
+extern void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id);
+#else
+#define EvrRtxMessageQueueResetDone(mq_id)
+#endif
+
+/**
+  \brief  Event on message queue delete (API)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE))
+extern void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id);
+#else
+#define EvrRtxMessageQueueDelete(mq_id)
+#endif
+
+/**
+  \brief  Event on successful message queue delete (Op)
+  \param[in]  mq_id         message queue ID obtained by \ref osMessageQueueNew.
+*/
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE))
+extern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id);
+#else
+#define EvrRtxMessageQueueDestroyed(mq_id)
+#endif
+
+
+#endif  // RTX_EVR_H_
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c
new file mode 100755
index 0000000..1f9a91f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c
@@ -0,0 +1,641 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Kernel functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+#include "rt_OsEventObserver.h"
+
+
+//  OS Runtime Information
+osRtxInfo_t osRtxInfo __attribute__((section(".data.os"))) =
+{ .os_id = osRtxKernelId, .version = osRtxVersionKernel, .kernel.state = osRtxKernelInactive };
+
+
+//  ==== Helper functions ====
+
+/// Block Kernel (disable: thread switching, time tick, post ISR processing).
+static void KernelBlock (void) {
+
+  if (osRtxInfo.tick_irqn >= 0) {
+    ExtTick_DisableIRQ(osRtxInfo.tick_irqn);
+  }
+  osRtxSysTimerDisable();
+  osRtxInfo.kernel.blocked = 1U;
+  __DSB();
+  if (osRtxInfo.tick_irqn < 0) {
+    osRtxInfo.kernel.pendISR = GetPendSV_ST();
+    ClrPendSV_ST();
+  } else {
+    osRtxInfo.kernel.pendISR = GetPendSV();
+    ClrPendSV();
+  }
+}
+
+/// Unblock Kernel
+static void KernelUnblock (void) {
+
+  osRtxInfo.kernel.blocked = 0U;
+  __DSB();
+  if (osRtxInfo.kernel.pendSV != 0U) {
+    osRtxInfo.kernel.pendSV = 0U;
+    SetPendSV();
+  }
+  if (osRtxInfo.kernel.pendISR != 0U) {
+    SetPendFlags(osRtxInfo.kernel.pendISR);
+  }
+  if (osRtxInfo.tick_irqn >= 0) {
+    ExtTick_EnableIRQ(osRtxInfo.tick_irqn);
+  }
+  osRtxSysTimerEnable();
+}
+
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_0M(KernelInitialize,       osStatus_t)
+SVC0_3 (KernelGetInfo,          osStatus_t, osVersion_t *, char *, uint32_t)
+SVC0_0M(KernelStart,            osStatus_t)
+SVC0_0 (KernelLock,             int32_t)
+SVC0_0 (KernelUnlock,           int32_t)
+SVC0_1 (KernelRestoreLock,      int32_t, int32_t)
+SVC0_0 (KernelSuspend,          uint32_t)
+SVC0_1N(KernelResume,           void, uint32_t)
+SVC0_0 (KernelGetState,         osKernelState_t)
+SVC0_0D(KernelGetTickCount,     uint64_t)
+SVC0_0 (KernelGetTickFreq,      uint32_t)
+SVC0_0 (KernelGetSysTimerCount, uint32_t)
+SVC0_0 (KernelGetSysTimerFreq,  uint32_t)
+
+/// Initialize the RTOS Kernel.
+/// \note API identical to osKernelInitialize
+osStatus_t svcRtxKernelInitialize (void) {
+
+  if (osRtxInfo.kernel.state == osRtxKernelReady) {
+    EvrRtxKernelInitializeCompleted();
+    return osOK;
+  }
+  if (osRtxInfo.kernel.state != osKernelInactive) {
+    EvrRtxKernelError(osError);
+    return osError;
+  }
+
+  // Initialize osRtxInfo
+  memset(&osRtxInfo.kernel, 0, sizeof(osRtxInfo) - offsetof(osRtxInfo_t, kernel));
+
+  if (osRtxConfig.thread_stack_size < (64U + 8U)) {
+    EvrRtxKernelError(osRtxErrorInvalidThreadStack);
+    return osError;
+  }
+
+  if ((osRtxConfig.isr_queue.data == NULL) || (osRtxConfig.isr_queue.max == 0U)) {
+    EvrRtxKernelError(osError);
+    return osError;
+  }
+  osRtxInfo.isr_queue.data = osRtxConfig.isr_queue.data;
+  osRtxInfo.isr_queue.max  = osRtxConfig.isr_queue.max;
+
+  osRtxInfo.thread.robin.timeout = osRtxConfig.robin_timeout;
+
+  // Initialize Memory Pools (Variable Block Size)
+  if (osRtxMemoryInit(osRtxConfig.mem.common_addr, osRtxConfig.mem.common_size) != 0U) {
+    osRtxInfo.mem.common = osRtxConfig.mem.common_addr;
+  }
+  if (osRtxMemoryInit(osRtxConfig.mem.stack_addr, osRtxConfig.mem.stack_size) != 0U) {
+    osRtxInfo.mem.stack = osRtxConfig.mem.stack_addr;
+  } else {
+    osRtxInfo.mem.stack = osRtxInfo.mem.common;
+  }
+  if (osRtxMemoryInit(osRtxConfig.mem.mp_data_addr, osRtxConfig.mem.mp_data_size) != 0U) {
+    osRtxInfo.mem.mp_data = osRtxConfig.mem.mp_data_addr;
+  } else {
+    osRtxInfo.mem.mp_data = osRtxInfo.mem.common;
+  }
+  if (osRtxMemoryInit(osRtxConfig.mem.mq_data_addr, osRtxConfig.mem.mq_data_size) != 0U) {
+    osRtxInfo.mem.mq_data = osRtxConfig.mem.mq_data_addr;
+  } else {
+    osRtxInfo.mem.mq_data = osRtxInfo.mem.common;
+  }
+
+  // Initialize Memory Pools (Fixed Block Size)
+  if ((osRtxConfig.mpi.stack != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.stack,
+                           osRtxConfig.mpi.stack->max_blocks,
+                           osRtxConfig.mpi.stack->block_size,
+                           osRtxConfig.mpi.stack->block_base) != 0U)) {
+    osRtxInfo.mpi.stack = osRtxConfig.mpi.stack;
+  }
+  if ((osRtxConfig.mpi.thread != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.thread,
+                           osRtxConfig.mpi.thread->max_blocks,
+                           osRtxConfig.mpi.thread->block_size,
+                           osRtxConfig.mpi.thread->block_base) != 0U)) {
+    osRtxInfo.mpi.thread = osRtxConfig.mpi.thread;
+  }
+  if ((osRtxConfig.mpi.timer != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.timer,
+                           osRtxConfig.mpi.timer->max_blocks,
+                           osRtxConfig.mpi.timer->block_size,
+                           osRtxConfig.mpi.timer->block_base) != 0U)) {
+    osRtxInfo.mpi.timer = osRtxConfig.mpi.timer;
+  }
+  if ((osRtxConfig.mpi.event_flags != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.event_flags,
+                           osRtxConfig.mpi.event_flags->max_blocks,
+                           osRtxConfig.mpi.event_flags->block_size,
+                           osRtxConfig.mpi.event_flags->block_base) != 0U)) {
+    osRtxInfo.mpi.event_flags = osRtxConfig.mpi.event_flags;
+  }
+  if ((osRtxConfig.mpi.mutex != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.mutex,
+                           osRtxConfig.mpi.mutex->max_blocks,
+                           osRtxConfig.mpi.mutex->block_size,
+                           osRtxConfig.mpi.mutex->block_base) != 0U)) {
+    osRtxInfo.mpi.mutex = osRtxConfig.mpi.mutex;
+  }
+  if ((osRtxConfig.mpi.semaphore != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.semaphore,
+                           osRtxConfig.mpi.semaphore->max_blocks,
+                           osRtxConfig.mpi.semaphore->block_size,
+                           osRtxConfig.mpi.semaphore->block_base) != 0U)) {
+    osRtxInfo.mpi.semaphore = osRtxConfig.mpi.semaphore;
+  }
+  if ((osRtxConfig.mpi.memory_pool != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.memory_pool,
+                           osRtxConfig.mpi.memory_pool->max_blocks,
+                           osRtxConfig.mpi.memory_pool->block_size,
+                           osRtxConfig.mpi.memory_pool->block_base) != 0U)) {
+    osRtxInfo.mpi.memory_pool = osRtxConfig.mpi.memory_pool;
+  }
+  if ((osRtxConfig.mpi.message_queue != NULL) &&
+      (osRtxMemoryPoolInit(osRtxConfig.mpi.message_queue,
+                           osRtxConfig.mpi.message_queue->max_blocks,
+                           osRtxConfig.mpi.message_queue->block_size,
+                           osRtxConfig.mpi.message_queue->block_base) != 0U)) {
+    osRtxInfo.mpi.message_queue = osRtxConfig.mpi.message_queue;
+  }
+
+#if (__DOMAIN_NS == 1U)
+  // Initialize Secure Process Stack
+  if (TZ_InitContextSystem_S() == 0U) {
+    EvrRtxKernelError(osRtxErrorTZ_InitContext_S);
+    return osError;
+  }
+#endif
+
+  // Initialize SVC and PendSV System Service Calls
+  SVC_Initialize();
+
+  osRtxInfo.kernel.state = osRtxKernelReady;
+
+  EvrRtxKernelInitializeCompleted();
+
+  return osOK;
+}
+
+///  Get RTOS Kernel Information.
+/// \note API identical to osKernelGetInfo
+osStatus_t svcRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
+
+  if (version != NULL) {
+    version->api    = osRtxVersionAPI;
+    version->kernel = osRtxVersionKernel;
+  }
+
+  if ((id_buf != NULL) && (id_size != 0U)) {
+    if (id_size > sizeof(osRtxKernelId)) {
+      id_size = sizeof(osRtxKernelId);
+    }
+    memcpy(id_buf, osRtxKernelId, id_size);
+  }
+
+  EvrRtxKernelInfoRetrieved(version, id_buf);
+
+  return osOK;
+}
+
+/// Get the current RTOS Kernel state.
+/// \note API identical to osKernelGetState
+osKernelState_t svcRtxKernelGetState (void) {
+  EvrRtxKernelGetState((osKernelState_t)(osRtxInfo.kernel.state));
+  return ((osKernelState_t)(osRtxInfo.kernel.state));
+}
+
+/// Start the RTOS Kernel scheduler.
+/// \note API identical to osKernelStart
+osStatus_t svcRtxKernelStart (void) {
+  os_thread_t *thread;
+
+  if (osRtxInfo.kernel.state != osRtxKernelReady) {
+    EvrRtxKernelError(osRtxErrorKernelNotReady);
+    return osError;
+  }
+
+  // Create Idle Thread
+  if (osRtxInfo.thread.idle == NULL) {
+    osRtxInfo.thread.idle = svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr, NULL);
+    if (osRtxInfo.thread.idle == NULL) {
+      EvrRtxKernelError(osError);
+      return osError;
+    }
+  }
+
+  // Create Timer Thread
+  if (osRtxConfig.timer_mq_mcnt != 0U) {
+    if (osRtxInfo.timer.thread == NULL) {
+      osRtxInfo.timer.thread = svcRtxThreadNew(osRtxTimerThread, NULL, osRtxConfig.timer_thread_attr, NULL);
+      if (osRtxInfo.timer.thread == NULL) {
+        EvrRtxKernelError(osError);
+        return osError;
+      }
+    }
+  }
+
+  // Switch to Ready Thread with highest Priority
+  thread = osRtxThreadListGet(&osRtxInfo.thread.ready);
+  if (thread == NULL) {
+    EvrRtxKernelError(osError);
+    return osError;
+  }
+  osRtxThreadSwitch(thread);
+
+  if ((osRtxConfig.flags & osRtxConfigPrivilegedMode) != 0U) {
+    // Privileged Thread mode & PSP
+    __set_CONTROL(0x02U);
+  } else {
+    // Unprivileged Thread mode & PSP
+    __set_CONTROL(0x03U);
+  }
+
+  osRtxInfo.kernel.sys_freq = SystemCoreClock;
+
+  // Setup and Enable System Timer
+  osRtxInfo.tick_irqn = osRtxSysTimerSetup();
+  if (osRtxInfo.tick_irqn >= 0) {
+    ExtTick_SetupIRQ (osRtxInfo.tick_irqn);
+    ExtTick_EnableIRQ(osRtxInfo.tick_irqn);
+  }
+  osRtxSysTimerEnable();
+
+  osRtxInfo.kernel.state = osRtxKernelRunning;
+
+  EvrRtxKernelStarted();
+
+  return osOK;
+}
+
+/// Lock the RTOS Kernel scheduler.
+/// \note API identical to osKernelLock
+int32_t svcRtxKernelLock (void) {
+
+  if (osRtxInfo.kernel.state == osRtxKernelLocked) {
+    EvrRtxKernelLocked(1);
+    return 1;
+  }
+  if (osRtxInfo.kernel.state == osRtxKernelRunning) {
+    osRtxInfo.kernel.state = osRtxKernelLocked;
+    EvrRtxKernelLocked(0);
+    return 0;
+  }
+
+  EvrRtxKernelError(osError);
+  return osError;
+}
+ 
+/// Unlock the RTOS Kernel scheduler.
+/// \note API identical to osKernelUnlock
+int32_t svcRtxKernelUnlock (void) {
+
+  if (osRtxInfo.kernel.state == osRtxKernelLocked) {
+    osRtxInfo.kernel.state = osRtxKernelRunning;
+    EvrRtxKernelUnlocked(1);
+    return 1;
+  }
+  if (osRtxInfo.kernel.state == osRtxKernelRunning) {
+    EvrRtxKernelUnlocked(0);
+    return 0;
+  }
+
+  EvrRtxKernelError(osError);
+  return osError;
+}
+
+/// Restore the RTOS Kernel scheduler lock state.
+/// \note API identical to osKernelRestoreLock
+int32_t svcRtxKernelRestoreLock (int32_t lock) {
+
+  if ((osRtxInfo.kernel.state == osRtxKernelRunning) || 
+      (osRtxInfo.kernel.state == osRtxKernelLocked)) {
+    switch (lock) {
+      case 1:
+        osRtxInfo.kernel.state = osRtxKernelLocked;
+        EvrRtxKernelLockRestored(1);
+        return 1;
+      case 0:
+        osRtxInfo.kernel.state = osRtxKernelRunning;
+        EvrRtxKernelLockRestored(0);
+        return 0;
+      default:
+        break;
+    }
+  }
+
+  EvrRtxKernelError(osError);
+  return osError;
+}
+
+/// Suspend the RTOS Kernel scheduler.
+/// \note API identical to osKernelSuspend
+uint32_t svcRtxKernelSuspend (void) {
+  os_thread_t *thread;
+  os_timer_t  *timer;
+  uint32_t     delay;
+
+  if (osRtxInfo.kernel.state != osRtxKernelRunning) {
+    EvrRtxKernelError(osRtxErrorKernelNotRunning);
+    return 0U;
+  }
+
+  KernelBlock();
+
+  delay = osWaitForever;
+
+  // Check Thread Delay list
+  thread = osRtxInfo.thread.delay_list;
+  if (thread != NULL) {
+    delay = thread->delay;
+  }
+
+  // Check Active Timer list
+  timer = osRtxInfo.timer.list;
+  if (timer != NULL) {
+    if (timer->tick < delay) {
+      delay = timer->tick;
+    }
+  }
+
+  osRtxInfo.kernel.state = osRtxKernelSuspended;
+
+  EvrRtxKernelSuspended(delay);
+
+  return delay;
+}
+
+/// Resume the RTOS Kernel scheduler.
+/// \note API identical to osKernelResume
+void svcRtxKernelResume (uint32_t sleep_ticks) {
+  os_thread_t *thread;
+  os_timer_t  *timer;
+  uint32_t     delay;
+
+  if (osRtxInfo.kernel.state != osRtxKernelSuspended) {
+    EvrRtxKernelResumed();
+    return;
+  }
+
+  // Process Thread Delay list
+  thread = osRtxInfo.thread.delay_list;
+  if (thread != NULL) {
+    delay = sleep_ticks;
+    if (delay >= thread->delay) {
+        delay -= thread->delay;
+      osRtxInfo.kernel.tick += thread->delay;
+      thread->delay = 1U;
+      do {
+        osRtxThreadDelayTick();
+        if (delay == 0U) { 
+          break;
+        }
+        delay--;
+        osRtxInfo.kernel.tick++;
+      } while (osRtxInfo.thread.delay_list != NULL);
+    } else {
+      thread->delay -= delay;
+      osRtxInfo.kernel.tick += delay;
+    }
+  } else {
+    osRtxInfo.kernel.tick += sleep_ticks;
+  }
+
+  // Process Active Timer list
+  timer = osRtxInfo.timer.list;
+  if (timer != NULL) {
+    if (sleep_ticks >= timer->tick) {
+        sleep_ticks -= timer->tick;
+      timer->tick = 1U;
+      do {
+        osRtxInfo.timer.tick();
+        if (sleep_ticks == 0U) {
+          break;
+        }
+        sleep_ticks--;
+      } while (osRtxInfo.timer.list != NULL);
+    } else {
+      timer->tick -= sleep_ticks;
+    }
+  }
+
+  osRtxInfo.kernel.state = osRtxKernelRunning;
+
+  osRtxThreadDispatch(NULL);
+
+  KernelUnblock();
+
+  EvrRtxKernelResumed();
+}
+
+/// Get the RTOS kernel tick count.
+/// \note API identical to osKernelGetTickCount
+uint64_t svcRtxKernelGetTickCount (void) {
+  EvrRtxKernelGetTickCount(osRtxInfo.kernel.tick);
+  return osRtxInfo.kernel.tick;
+}
+
+/// Get the RTOS kernel tick frequency.
+/// \note API identical to osKernelGetTickFreq
+uint32_t svcRtxKernelGetTickFreq (void) {
+  EvrRtxKernelGetTickFreq(osRtxConfig.tick_freq);
+  return osRtxConfig.tick_freq;
+}
+
+/// Get the RTOS kernel system timer count.
+/// \note API identical to osKernelGetSysTimerCount
+uint32_t svcRtxKernelGetSysTimerCount (void) {
+  uint32_t count = osRtxSysTimerGetCount();
+  EvrRtxKernelGetSysTimerCount(count);
+  return count;
+}
+
+/// Get the RTOS kernel system timer frequency.
+/// \note API identical to osKernelGetSysTimerFreq
+uint32_t svcRtxKernelGetSysTimerFreq (void) {
+  uint32_t freq = osRtxSysTimerGetFreq();
+  EvrRtxKernelGetSysTimerFreq(freq);
+  return freq;
+}
+
+
+//  ==== Public API ====
+
+/// Initialize the RTOS Kernel.
+osStatus_t osKernelInitialize (void) {
+  EvrRtxKernelInitialize();
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return osErrorISR;
+  }
+  return __svcKernelInitialize();
+}
+
+///  Get RTOS Kernel Information.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
+  EvrRtxKernelGetInfo(version, id_buf, id_size);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return osErrorISR;
+  }
+  if (IS_PRIVILEGED()) {
+    return svcRtxKernelGetInfo(version, id_buf, id_size);
+  } else {
+    return  __svcKernelGetInfo(version, id_buf, id_size);
+  }
+}
+
+/// Get the current RTOS Kernel state.
+osKernelState_t osKernelGetState (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelGetState(osKernelError);
+    return osKernelError;
+  }
+  if (IS_PRIVILEGED()) {
+    return svcRtxKernelGetState();
+  } else {
+    return  __svcKernelGetState();
+  }
+}
+
+/// Start the RTOS Kernel scheduler.
+osStatus_t osKernelStart (void) {
+  EvrRtxKernelStart();
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return osErrorISR;
+  }
+
+  /* Call the pre-start event (from unprivileged mode) if the handler exists
+   * and the kernel is not running. */
+  /* FIXME osEventObs needs to be readable but not writable from unprivileged
+   * code. */
+  if (osKernelGetState() != osKernelRunning && osEventObs && osEventObs->pre_start) {
+    osEventObs->pre_start();
+  }
+
+  return __svcKernelStart();
+}
+
+/// Lock the RTOS Kernel scheduler.
+int32_t osKernelLock (void) {
+  EvrRtxKernelLock();
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return osErrorISR;
+  }
+  return __svcKernelLock();
+}
+ 
+/// Unlock the RTOS Kernel scheduler.
+int32_t osKernelUnlock (void) {
+  EvrRtxKernelUnlock();
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return osErrorISR;
+  }
+  return __svcKernelUnlock();
+}
+
+/// Restore the RTOS Kernel scheduler lock state.
+int32_t osKernelRestoreLock (int32_t lock) {
+  EvrRtxKernelRestoreLock(lock);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return osErrorISR;
+  }
+  return __svcKernelRestoreLock(lock);
+}
+
+/// Suspend the RTOS Kernel scheduler.
+uint32_t osKernelSuspend (void) {
+  EvrRtxKernelSuspend();
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return 0U;
+  }
+  return __svcKernelSuspend();
+}
+
+/// Resume the RTOS Kernel scheduler.
+void osKernelResume (uint32_t sleep_ticks) {
+  EvrRtxKernelResume(sleep_ticks);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxKernelError(osErrorISR);
+    return;
+  }
+  __svcKernelResume(sleep_ticks);
+}
+
+/// Get the RTOS kernel tick count.
+uint64_t osKernelGetTickCount (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxKernelGetTickCount();
+  } else {
+    return  __svcKernelGetTickCount();
+  }
+}
+
+/// Get the RTOS kernel tick frequency.
+uint32_t osKernelGetTickFreq (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxKernelGetTickFreq();
+  } else {
+    return  __svcKernelGetTickFreq();
+  }
+}
+
+/// Get the RTOS kernel system timer count.
+uint32_t osKernelGetSysTimerCount (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxKernelGetSysTimerCount();
+  } else {
+    return  __svcKernelGetSysTimerCount();
+  }
+}
+
+/// Get the RTOS kernel system timer frequency.
+uint32_t osKernelGetSysTimerFreq (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxKernelGetSysTimerFreq();
+  } else {
+    return  __svcKernelGetSysTimerFreq();
+  }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.c
new file mode 100755
index 0000000..70b18e9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.c
@@ -0,0 +1,642 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Library Configuration
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "cmsis_compiler.h"
+#include "rtx_os.h"
+#include "RTX_Config.h"
+
+
+// System Configuration
+// ====================
+
+// Dynamic Memory
+#if (OS_DYNAMIC_MEM_SIZE != 0)
+#if ((OS_DYNAMIC_MEM_SIZE & 7) != 0)
+#error "Invalid Dynamic Memory size!"
+#endif
+static uint64_t os_mem[OS_DYNAMIC_MEM_SIZE/8] \
+__attribute__((section(".bss.os")));
+#endif
+
+// Kernel Tick Frequency
+#if (OS_TICK_FREQ < 1)
+#error "Invalid Kernel Tick Frequency!"
+#endif
+
+// ISR FIFO Queue
+static void *os_isr_queue[OS_ISR_FIFO_QUEUE] \
+__attribute__((section(".bss.os")));
+
+
+// Thread Configuration
+// ====================
+
+#if (((OS_STACK_SIZE & 7) != 0) || (OS_STACK_SIZE < 72))
+#error "Invalid default Thread Stack size!"
+#endif
+
+#if (((OS_IDLE_THREAD_STACK_SIZE & 7) != 0) || (OS_IDLE_THREAD_STACK_SIZE < 72))
+#error "Invalid Idle Thread Stack size!"
+#endif
+
+
+#if (OS_THREAD_OBJ_MEM != 0)
+
+#if (OS_THREAD_NUM == 0)
+#error "Invalid number of user Threads!"
+#endif
+
+#if ((OS_THREAD_USER_STACK_SIZE != 0) && ((OS_THREAD_USER_STACK_SIZE & 7) != 0))
+#error "Invalid total Stack size!"
+#endif
+
+// Thread Control Blocks
+static osRtxThread_t os_thread_cb[OS_THREAD_NUM] \
+__attribute__((section(".bss.os.thread.cb")));
+
+// Thread Default Stack
+#if (OS_THREAD_DEF_STACK_NUM != 0)
+static uint64_t os_thread_def_stack[OS_THREAD_DEF_STACK_NUM*(OS_STACK_SIZE/8)] \
+__attribute__((section(".bss.os.thread.stack")));
+#endif
+
+// Memory Pool for Thread Control Blocks
+static osRtxMpInfo_t os_mpi_thread \
+__attribute__((section(".data.os.thread.mpi"))) =
+{ (uint32_t)OS_THREAD_NUM, 0U, (uint32_t)osRtxThreadCbSize, &os_thread_cb, NULL, NULL };
+
+// Memory Pool for Thread Default Stack
+#if (OS_THREAD_DEF_STACK_NUM != 0)
+static osRtxMpInfo_t os_mpi_def_stack \
+__attribute__((section(".data.os.thread.mpi"))) =
+{ (uint32_t)OS_THREAD_DEF_STACK_NUM, 0U, (uint32_t)OS_STACK_SIZE, &os_thread_def_stack, NULL, NULL };
+#endif
+
+// Memory Pool for Thread Stack
+#if (OS_THREAD_USER_STACK_SIZE != 0)
+static uint64_t os_thread_stack[OS_THREAD_USER_STACK_SIZE/8] \
+__attribute__((section(".bss.os.thread.stack")));
+#endif
+
+#endif  // (OS_THREAD_OBJ_MEM != 0)
+
+
+// Stack overrun checking
+#if (OS_STACK_CHECK == 0)
+// Override library function
+void osRtxThreadStackCheck (void);
+void osRtxThreadStackCheck (void) {}
+#endif
+
+
+// Idle Thread Control Block
+static osRtxThread_t os_idle_thread_cb \
+__attribute__((section(".bss.os.thread.cb")));
+
+// Idle Thread Stack
+static uint64_t os_idle_thread_stack[OS_IDLE_THREAD_STACK_SIZE/8] \
+__attribute__((section(".bss.os.thread.stack")));
+
+// Idle Thread Attributes
+static const osThreadAttr_t os_idle_thread_attr = {
+  NULL,
+  osThreadDetached,
+  &os_idle_thread_cb,
+  (uint32_t)sizeof(os_idle_thread_cb),
+  &os_idle_thread_stack,
+  (uint32_t)sizeof(os_idle_thread_stack),
+  osPriorityIdle,
+  0U, 0U
+};
+
+
+// Timer Configuration
+// ===================
+
+#if (OS_TIMER_OBJ_MEM != 0)
+
+#if (OS_TIMER_NUM == 0)
+#error "Invalid number of Timer objects!"
+#endif
+
+// Timer Control Blocks
+static osRtxTimer_t os_timer_cb[OS_TIMER_NUM] \
+__attribute__((section(".bss.os.timer.cb")));
+
+// Memory Pool for Timer Control Blocks
+static osRtxMpInfo_t os_mpi_timer \
+__attribute__((section(".data.os.timer.mpi"))) =
+{ (uint32_t)OS_TIMER_NUM, 0U, (uint32_t)osRtxTimerCbSize, &os_timer_cb, NULL, NULL };
+
+#endif  // (OS_TIMER_OBJ_MEM != 0)
+
+
+#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))
+
+#if (((OS_TIMER_THREAD_STACK_SIZE & 7) != 0) || (OS_TIMER_THREAD_STACK_SIZE < 96))
+#error "Invalid Timer Thread Stack size!"
+#endif
+
+// Timer Thread Control Block
+static osRtxThread_t os_timer_thread_cb \
+__attribute__((section(".bss.os.thread.cb")));
+
+// Timer Thread Stack
+static uint64_t os_timer_thread_stack[OS_TIMER_THREAD_STACK_SIZE/8] \
+__attribute__((section(".bss.os.thread.stack")));
+
+// Timer Thread Attributes
+static const osThreadAttr_t os_timer_thread_attr = {
+  NULL,
+  osThreadDetached,
+  &os_timer_thread_cb,
+  (uint32_t)sizeof(os_timer_thread_cb),
+  &os_timer_thread_stack,
+  (uint32_t)sizeof(os_timer_thread_stack),
+  (osPriority_t)OS_TIMER_THREAD_PRIO,
+  0U, 0U
+};
+
+// Timer Message Queue Control Block
+static osRtxMessageQueue_t os_timer_mq_cb \
+__attribute__((section(".bss.os.msgqueue.cb")));
+
+// Timer Message Queue Data
+static uint32_t os_timer_mq_data[osRtxMessageQueueMemSize(OS_TIMER_CB_QUEUE,8)/4] \
+__attribute__((section(".bss.os.msgqueue.mem")));
+
+// Timer Message Queue Attributes
+static const osMessageQueueAttr_t os_timer_mq_attr = {
+  NULL,
+  0U,
+  &os_timer_mq_cb,
+  (uint32_t)sizeof(os_timer_mq_cb),
+  &os_timer_mq_data,
+  (uint32_t)sizeof(os_timer_mq_data)
+};
+
+#else
+
+extern void osRtxTimerThread (void *argument);
+       void osRtxTimerThread (void *argument) {}
+
+#endif  // ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))
+
+
+// Event Flags Configuration
+// =========================
+
+#if (OS_EVFLAGS_OBJ_MEM != 0)
+
+#if (OS_EVFLAGS_NUM == 0)
+#error "Invalid number of Event Flags objects!"
+#endif
+
+// Event Flags Control Blocks
+static osRtxEventFlags_t os_ef_cb[OS_EVFLAGS_NUM] \
+__attribute__((section(".bss.os.evflags.cb")));
+
+// Memory Pool for Event Flags Control Blocks
+static osRtxMpInfo_t os_mpi_ef \
+__attribute__((section(".data.os.evflags.mpi"))) =
+{ (uint32_t)OS_EVFLAGS_NUM, 0U, (uint32_t)osRtxEventFlagsCbSize, &os_ef_cb, NULL, NULL };
+
+#endif  // (OS_EVFLAGS_OBJ_MEM != 0)
+
+
+// Mutex Configuration
+// ===================
+
+#if (OS_MUTEX_OBJ_MEM != 0)
+
+#if (OS_MUTEX_NUM == 0)
+#error "Invalid number of Mutex objects!"
+#endif
+
+// Mutex Control Blocks
+static osRtxMutex_t os_mutex_cb[OS_MUTEX_NUM] \
+__attribute__((section(".bss.os.mutex.cb")));
+
+// Memory Pool for Mutex Control Blocks
+static osRtxMpInfo_t os_mpi_mutex \
+__attribute__((section(".data.os.mutex.mpi"))) =
+{ (uint32_t)OS_MUTEX_NUM, 0U, (uint32_t)osRtxMutexCbSize, &os_mutex_cb, NULL, NULL };
+
+#endif  // (OS_MUTEX_OBJ_MEM != 0)
+
+
+// Semaphore Configuration
+// =======================
+
+#if (OS_SEMAPHORE_OBJ_MEM != 0)
+
+#if (OS_SEMAPHORE_NUM == 0)
+#error "Invalid number of Semaphore objects!"
+#endif
+
+// Semaphore Control Blocks
+static osRtxSemaphore_t os_semaphore_cb[OS_SEMAPHORE_NUM] \
+__attribute__((section(".bss.os.semaphore.cb")));
+
+// Memory Pool for Semaphore Control Blocks
+static osRtxMpInfo_t os_mpi_semaphore \
+__attribute__((section(".data.os.semaphore.mpi"))) =
+{ (uint32_t)OS_SEMAPHORE_NUM, 0U, (uint32_t)osRtxSemaphoreCbSize, &os_semaphore_cb, NULL, NULL };
+
+#endif  // (OS_SEMAPHORE_OBJ_MEM != 0)
+
+
+// Memory Pool Configuration
+// =========================
+
+#if (OS_MEMPOOL_OBJ_MEM != 0)
+
+#if (OS_MEMPOOL_NUM == 0)
+#error "Invalid number of Memory Pool objects!"
+#endif
+
+// Memory Pool Control Blocks
+static osRtxMemoryPool_t os_mp_cb[OS_MEMPOOL_NUM] \
+__attribute__((section(".bss.os.mempool.cb")));
+
+// Memory Pool for Memory Pool Control Blocks
+static osRtxMpInfo_t os_mpi_mp \
+__attribute__((section(".data.os.mempool.mpi"))) =
+{ (uint32_t)OS_MEMPOOL_NUM, 0U, (uint32_t)osRtxMemoryPoolCbSize, &os_mp_cb, NULL, NULL };
+
+// Memory Pool for Memory Pool Data Storage
+#if (OS_MEMPOOL_DATA_SIZE != 0)
+#if ((OS_MEMPOOL_DATA_SIZE & 7) != 0)
+#error "Invalid Data Memory size for Memory Pools!"
+#endif
+static uint64_t os_mp_data[OS_MEMPOOL_DATA_SIZE/8] \
+__attribute__((section(".bss.os.mempool.mem")));
+#endif
+
+#endif  // (OS_MEMPOOL_OBJ_MEM != 0)
+
+
+// Message Queue Configuration
+// ===========================
+
+#if (OS_MSGQUEUE_OBJ_MEM != 0)
+
+#if (OS_MSGQUEUE_NUM == 0)
+#error "Invalid number of Message Queue objects!"
+#endif
+
+// Message Queue Control Blocks
+static osRtxMessageQueue_t os_mq_cb[OS_MSGQUEUE_NUM] \
+__attribute__((section(".bss.os.msgqueue.cb")));
+
+// Memory Pool for Message Queue Control Blocks
+static osRtxMpInfo_t os_mpi_mq \
+__attribute__((section(".data.os.msgqueue.mpi"))) =
+{ (uint32_t)OS_MSGQUEUE_NUM, 0U, (uint32_t)osRtxMessageQueueCbSize, &os_mq_cb, NULL, NULL };
+
+// Memory Pool for Message Queue Data Storage
+#if (OS_MSGQUEUE_DATA_SIZE != 0)
+#if ((OS_MSGQUEUE_DATA_SIZE & 7) != 0)
+#error "Invalid Data Memory size for Message Queues!"
+#endif
+static uint64_t os_mq_data[OS_MSGQUEUE_DATA_SIZE/8] \
+__attribute__((section(".bss.os.msgqueue.mem")));
+#endif
+
+#endif  // (OS_MSGQUEUE_OBJ_MEM != 0)
+
+
+// OS Configuration
+// ================
+
+__USED
+__attribute__((section(".rodata")))
+const osRtxConfig_t osRtxConfig = {
+  0U   // Flags
+#if (OS_PRIVILEGE_MODE != 0)
+  | osRtxConfigPrivilegedMode
+#endif
+#if (OS_STACK_CHECK != 0)
+  | osRtxConfigStackCheck
+#endif
+#if (OS_STACK_WATERMARK != 0)
+  | osRtxConfigStackWatermark
+#endif
+  ,
+  (uint32_t)OS_TICK_FREQ,
+#if (OS_ROBIN_ENABLE != 0)
+  (uint32_t)OS_ROBIN_TIMEOUT,
+#else
+  0U,
+#endif
+  { &os_isr_queue[0], sizeof(os_isr_queue)/sizeof(void *), 0U },
+  { 
+    // Memory Pools (Variable Block Size)
+#if ((OS_THREAD_OBJ_MEM != 0) && (OS_THREAD_USER_STACK_SIZE != 0))
+    &os_thread_stack, (uint32_t)OS_THREAD_USER_STACK_SIZE,
+#else
+    NULL, 0U,
+#endif
+#if ((OS_MEMPOOL_OBJ_MEM != 0) && (OS_MEMPOOL_DATA_SIZE != 0))
+    &os_mp_data, (uint32_t)OS_MEMPOOL_DATA_SIZE,
+#else
+    NULL, 0U,
+#endif
+#if ((OS_MSGQUEUE_OBJ_MEM != 0) && (OS_MSGQUEUE_DATA_SIZE != 0))
+    &os_mq_data, (uint32_t)OS_MSGQUEUE_DATA_SIZE,
+#else
+    NULL, 0U,
+#endif
+#if (OS_DYNAMIC_MEM_SIZE != 0)
+    &os_mem, (uint32_t)OS_DYNAMIC_MEM_SIZE,
+#else
+    NULL, 0U
+#endif
+  },
+  {
+    // Memory Pools (Fixed Block Size)
+#if (OS_THREAD_OBJ_MEM != 0)
+#if (OS_THREAD_DEF_STACK_NUM != 0)
+    &os_mpi_def_stack,
+#else
+    NULL,
+#endif
+    &os_mpi_thread,
+#else
+    NULL, 
+    NULL,
+#endif
+#if (OS_TIMER_OBJ_MEM != 0)
+    &os_mpi_timer,
+#else
+    NULL,
+#endif
+#if (OS_EVFLAGS_OBJ_MEM != 0)
+    &os_mpi_ef,
+#else
+    NULL,
+#endif
+#if (OS_MUTEX_OBJ_MEM != 0)
+    &os_mpi_mutex,
+#else
+    NULL,
+#endif
+#if (OS_SEMAPHORE_OBJ_MEM != 0)
+    &os_mpi_semaphore,
+#else
+    NULL,
+#endif
+#if (OS_MEMPOOL_OBJ_MEM != 0)
+    &os_mpi_mp,
+#else
+    NULL,
+#endif
+#if (OS_MSGQUEUE_OBJ_MEM != 0)
+    &os_mpi_mq,
+#else
+    NULL,
+#endif
+  },
+  (uint32_t)OS_STACK_SIZE,
+  &os_idle_thread_attr,
+#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))
+  &os_timer_thread_attr,
+  &os_timer_mq_attr,
+  (uint32_t)OS_TIMER_CB_QUEUE
+#else
+  NULL,
+  NULL,
+  0U
+#endif
+};
+
+
+// Non weak reference to library irq module
+extern       uint8_t  irqRtxLib;
+extern const uint8_t *irqRtxLibRef;
+       const uint8_t *irqRtxLibRef = &irqRtxLib;
+
+// Default User SVC Table
+extern void * const osRtxUserSVC[];
+__WEAK void * const osRtxUserSVC[1] = { (void *)0 };
+
+
+// OS Sections
+// ===========
+
+#if (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+__asm (
+  ".weakref __os_thread_cb_start__,    .bss.os.thread.cb$$Base\n\t"
+  ".weakref __os_thread_cb_end__,      .bss.os.thread.cb$$Limit\n\t"
+  ".weakref __os_timer_cb_start__,     .bss.os.timer.cb$$Base\n\t"
+  ".weakref __os_timer_cb_end__,       .bss.os.timer.cb$$Limit\n\t"
+  ".weakref __os_evflags_cb_start__,   .bss.os.evflags.cb$$Base\n\t"
+  ".weakref __os_evflags_cb_end__,     .bss.os.evflags.cb$$Limit\n\t"
+  ".weakref __os_mutex_cb_start__,     .bss.os.mutex.cb$$Base\n\t"
+  ".weakref __os_mutex_cb_end__,       .bss.os.mutex.cb$$Limit\n\t"
+  ".weakref __os_semaphore_cb_start__, .bss.os.semaphore.cb$$Base\n\t"
+  ".weakref __os_semaphore_cb_end__,   .bss.os.semaphore.cb$$Limit\n\t"
+  ".weakref __os_mempool_cb_start__,   .bss.os.mempool.cb$$Base\n\t"
+  ".weakref __os_mempool_cb_end__,     .bss.os.mempool.cb$$Limit\n\t"
+  ".weakref __os_msgqueue_cb_start__,  .bss.os.msgqueue.cb$$Base\n\t"
+  ".weakref __os_msgqueue_cb_end__,    .bss.os.msgqueue.cb$$Limit\n\t"
+);
+#endif
+
+#if (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
+    (defined(__GNUC__) && !defined(__CC_ARM))
+
+extern __attribute__((weak)) uint32_t __os_thread_cb_start__;
+extern __attribute__((weak)) uint32_t __os_thread_cb_end__;
+extern __attribute__((weak)) uint32_t __os_timer_cb_start__;
+extern __attribute__((weak)) uint32_t __os_timer_cb_end__;
+extern __attribute__((weak)) uint32_t __os_evflags_cb_start__;
+extern __attribute__((weak)) uint32_t __os_evflags_cb_end__;
+extern __attribute__((weak)) uint32_t __os_mutex_cb_start__;
+extern __attribute__((weak)) uint32_t __os_mutex_cb_end__;
+extern __attribute__((weak)) uint32_t __os_semaphore_cb_start__;
+extern __attribute__((weak)) uint32_t __os_semaphore_cb_end__;
+extern __attribute__((weak)) uint32_t __os_mempool_cb_start__;
+extern __attribute__((weak)) uint32_t __os_mempool_cb_end__;
+extern __attribute__((weak)) uint32_t __os_msgqueue_cb_start__;
+extern __attribute__((weak)) uint32_t __os_msgqueue_cb_end__;
+
+__asm (".global os_cb_sections");
+
+extern const uint32_t os_cb_sections[];
+
+__attribute__((section(".rodata")))
+const uint32_t os_cb_sections[] = {
+  (uint32_t)&__os_thread_cb_start__,
+  (uint32_t)&__os_thread_cb_end__,
+  (uint32_t)&__os_timer_cb_start__,
+  (uint32_t)&__os_timer_cb_end__,
+  (uint32_t)&__os_evflags_cb_start__,
+  (uint32_t)&__os_evflags_cb_end__,
+  (uint32_t)&__os_mutex_cb_start__,
+  (uint32_t)&__os_mutex_cb_end__,
+  (uint32_t)&__os_semaphore_cb_start__,
+  (uint32_t)&__os_semaphore_cb_end__,
+  (uint32_t)&__os_mempool_cb_start__,
+  (uint32_t)&__os_mempool_cb_end__,
+  (uint32_t)&__os_msgqueue_cb_start__,
+  (uint32_t)&__os_msgqueue_cb_end__
+};
+
+#endif
+
+
+// OS Initialization
+// =================
+
+#if  defined(__CC_ARM) || \
+    (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+
+#ifndef __MICROLIB
+extern void _platform_post_stackheap_init (void);
+__WEAK void _platform_post_stackheap_init (void) {
+  osKernelInitialize();
+}
+#endif
+
+#elif defined(__GNUC__)
+
+extern void software_init_hook (void);
+__WEAK void software_init_hook (void) {
+  osKernelInitialize();
+}
+
+#endif
+
+
+// C/C++ Standard Library Multithreading Interface
+// ===============================================
+
+#if (( defined(__CC_ARM) || \
+      (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \
+      !defined(__MICROLIB))
+
+#define LIBSPACE_SIZE 96
+
+// Memory for libspace
+static uint32_t os_libspace[OS_THREAD_LIBSPACE_NUM+1][LIBSPACE_SIZE/sizeof(uint32_t)] \
+__attribute__((section(".bss.os")));
+
+// Thread IDs for libspace
+static osThreadId_t os_libspace_id[OS_THREAD_LIBSPACE_NUM] \
+__attribute__((section(".bss.os")));
+
+// Check if Kernel has been started
+static uint32_t os_kernel_is_active (void) {
+  static uint8_t os_kernel_active = 0U;
+
+  if (os_kernel_active == 0U) {
+    if (osKernelGetState() > osKernelReady) {
+      os_kernel_active = 1U;
+      return 1U;
+    }
+    return 0U;
+  } else {
+    return 1U;
+  }
+}
+
+// Provide libspace for current thread
+void *__user_perthread_libspace (void);
+void *__user_perthread_libspace (void) {
+  osThreadId_t id;
+  uint32_t     n;
+
+  if (!os_kernel_is_active()) {
+    return (void *)&os_libspace[OS_THREAD_LIBSPACE_NUM][0];
+  }
+
+  id = osThreadGetId();
+  for (n = 0U; n < OS_THREAD_LIBSPACE_NUM; n++) {
+    if (os_libspace_id[n] == NULL) {
+      os_libspace_id[n] = id;
+      return (void *)&os_libspace[n][0];
+    }
+    if (os_libspace_id[n] == id) {
+      return (void *)&os_libspace[n][0];
+    }
+  }
+
+  if (n == OS_THREAD_LIBSPACE_NUM) {
+    osRtxErrorNotify(osRtxErrorClibSpace, id);
+  }
+
+  return (void *)&os_libspace[n][0];
+}
+
+// Mutex identifier
+typedef void *mutex;
+
+// Initialize mutex
+#if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050
+__USED
+#endif
+int _mutex_initialize(mutex *m);
+__WEAK int _mutex_initialize(mutex *m) {
+  *m = osMutexNew(NULL);
+  if (*m == NULL) {
+    osRtxErrorNotify(osRtxErrorClibMutex, m);
+    return 0;
+  }
+  return 1;
+}
+
+// Acquire mutex
+#if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050
+__USED
+#endif
+void _mutex_acquire(mutex *m);
+__WEAK void _mutex_acquire(mutex *m) {
+  if (os_kernel_is_active()) {
+    osMutexAcquire(*m, osWaitForever);
+  }
+}
+
+// Release mutex
+#if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050
+__USED
+#endif
+void _mutex_release(mutex *m);
+__WEAK void _mutex_release(mutex *m) {
+  if (os_kernel_is_active()) {
+    osMutexRelease(*m);
+  }
+}
+
+// Free mutex
+#if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050
+__USED
+#endif
+void _mutex_free(mutex *m);
+__WEAK void _mutex_free(mutex *m) {
+  osMutexDelete(*m);
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h
new file mode 100755
index 0000000..fb7423d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_lib.h
@@ -0,0 +1,216 @@
+/** \addtogroup rtos */
+/** @{*/
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Library definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#ifndef RTX_LIB_H_
+#define RTX_LIB_H_
+
+#include <string.h>
+#include <stdbool.h>
+#include "core_cm.h"                    // Cortex-M definitions
+#include "tz_context.h"                 // TrustZone Context API
+#include "cmsis_os2.h"                  // CMSIS RTOS API
+#include "rtx_os.h"                     // RTX OS definitions
+#include "rtx_evr.h"                    // RTX Event Recorder definitions
+
+
+//  ==== Library defines ====
+
+#define os_thread_t         osRtxThread_t
+#define os_timer_t          osRtxTimer_t
+#define os_timer_finfo_t    osRtxTimerFinfo_t
+#define os_event_flags_t    osRtxEventFlags_t
+#define os_mutex_t          osRtxMutex_t
+#define os_semaphore_t      osRtxSemaphore_t
+#define os_mp_info_t        osRtxMpInfo_t
+#define os_memory_pool_t    osRtxMemoryPool_t
+#define os_message_t        osRtxMessage_t
+#define os_message_queue_t  osRtxMessageQueue_t
+#define os_object_t         osRtxObject_t
+
+//  ==== Inline functions ====
+
+// Kernel Inline functions
+__STATIC_INLINE uint8_t      osRtxKernelGetState   (void) { return osRtxInfo.kernel.state; }
+
+// Thread Inline functions
+__STATIC_INLINE os_thread_t *osRtxThreadGetRunning (void) { return osRtxInfo.thread.run.curr; }
+__STATIC_INLINE void         osRtxThreadSetRunning (os_thread_t *thread) { osRtxInfo.thread.run.curr = thread; }
+
+
+//  ==== Library functions ====
+
+// Thread Library functions
+extern void         osRtxThreadListPut     (volatile os_object_t *object, os_thread_t *thread);
+extern os_thread_t *osRtxThreadListGet     (volatile os_object_t *object);
+extern void        *osRtxThreadListRoot    (os_thread_t  *thread);
+extern void         osRtxThreadListSort    (os_thread_t  *thread);
+extern void         osRtxThreadListRemove  (os_thread_t  *thread);
+extern void         osRtxThreadListUnlink  (os_thread_t **thread_list, os_thread_t *thread);
+extern void         osRtxThreadReadyPut    (os_thread_t  *thread);
+extern void         osRtxThreadDelayInsert (os_thread_t  *thread, uint32_t delay);
+extern void         osRtxThreadDelayRemove (os_thread_t  *thread);
+extern void         osRtxThreadDelayTick   (void);
+extern uint32_t    *osRtxThreadRegPtr      (os_thread_t  *thread);
+extern void         osRtxThreadBlock       (os_thread_t  *thread);
+extern void         osRtxThreadSwitch      (os_thread_t  *thread);
+extern void         osRtxThreadDispatch    (os_thread_t  *thread);
+extern void         osRtxThreadWaitExit    (os_thread_t  *thread, uint32_t ret_val, bool dispatch);
+extern bool         osRtxThreadWaitEnter   (uint8_t state, uint32_t timeout);
+extern void         osRtxThreadStackCheck  (void);
+
+// Timer Library functions
+extern void osRtxTimerTick   (void);
+extern void osRtxTimerThread (void *argument);
+
+// Mutex Library functions
+extern void osRtxMutexOwnerRelease (os_mutex_t *mutex_list);
+
+// Memory Heap Library functions
+extern uint32_t osRtxMemoryInit (void *mem, uint32_t size);
+extern void    *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type);
+extern uint32_t osRtxMemoryFree (void *mem, void *block);
+
+// Memory Pool Library functions
+extern uint32_t   osRtxMemoryPoolInit  (os_mp_info_t *mp_info, uint32_t blocks, uint32_t block_size, void *block_mem);
+extern void      *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info);
+extern osStatus_t osRtxMemoryPoolFree  (os_mp_info_t *mp_info, void *block);
+
+// System Library functions
+extern void osRtxTick_Handler   (void);
+extern void osRtxPendSV_Handler (void);
+extern void osRtxPostProcess    (os_object_t *object);
+
+// Post ISR processing functions
+extern void osRtxThreadPostProcess       (os_thread_t      *thread);
+extern void osRtxEventFlagsPostProcess   (os_event_flags_t *ef);
+extern void osRtxSemaphorePostProcess    (os_semaphore_t   *semaphore);
+extern void osRtxMemoryPoolPostProcess   (os_memory_pool_t *mp);
+extern void osRtxMessageQueuePostProcess (os_message_t     *msg);
+
+
+//  ==== Service Calls ====
+
+// Kernel Service Calls
+extern osStatus_t       svcRtxKernelInitialize       (void);
+extern osStatus_t       svcRtxKernelGetInfo          (osVersion_t *version, char *id_buf, uint32_t id_size);
+extern osKernelState_t  svcRtxKernelGetState         (void);
+extern osStatus_t       svcRtxKernelStart            (void);
+extern int32_t          svcRtxKernelLock             (void);
+extern int32_t          svcRtxKernelUnlock           (void);
+extern int32_t          svcRtxKernelRestoreLock      (int32_t lock);
+extern uint32_t         svcRtxKernelSuspend          (void);
+extern void             svcRtxKernelResume           (uint32_t sleep_ticks);
+extern uint64_t         svcRtxKernelGetTickCount     (void);
+extern uint32_t         svcRtxKernelGetTickFreq      (void);
+extern uint32_t         svcRtxKernelGetSysTimerCount (void);
+extern uint32_t         svcRtxKernelGetSysTimerFreq  (void);
+
+// Thread Service Calls
+extern osThreadId_t     svcRtxThreadNew          (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context);
+extern const char *     svcRtxThreadGetName      (osThreadId_t thread_id);
+extern osThreadId_t     svcRtxThreadGetId        (void);
+extern osThreadState_t  svcRtxThreadGetState     (osThreadId_t thread_id);
+extern uint32_t         svcRtxThreadGetStackSize (osThreadId_t thread_id);
+extern uint32_t         svcRtxThreadGetStackSpace(osThreadId_t thread_id);
+extern osStatus_t       svcRtxThreadSetPriority  (osThreadId_t thread_id, osPriority_t priority);
+extern osPriority_t     svcRtxThreadGetPriority  (osThreadId_t thread_id);
+extern osStatus_t       svcRtxThreadYield        (void);
+extern osStatus_t       svcRtxThreadSuspend      (osThreadId_t thread_id);
+extern osStatus_t       svcRtxThreadResume       (osThreadId_t thread_id);
+extern osStatus_t       svcRtxThreadDetach       (osThreadId_t thread_id);
+extern osStatus_t       svcRtxThreadJoin         (osThreadId_t thread_id);
+extern void             svcRtxThreadExit         (void);
+extern osStatus_t       svcRtxThreadTerminate    (osThreadId_t thread_id);
+extern uint32_t         svcRtxThreadGetCount     (void);
+extern uint32_t         svcRtxThreadEnumerate    (osThreadId_t *thread_array, uint32_t array_items);
+extern uint32_t         svcRtxThreadFlagsSet     (osThreadId_t thread_id, uint32_t flags);
+extern uint32_t         svcRtxThreadFlagsClear   (uint32_t flags);
+extern uint32_t         svcRtxThreadFlagsGet     (void);
+extern uint32_t         svcRtxThreadFlagsWait    (uint32_t flags, uint32_t options, uint32_t timeout);
+
+// Delay Service Calls
+extern osStatus_t       svcRtxDelay      (uint32_t ticks);
+extern osStatus_t       svcRtxDelayUntil (uint32_t ticks_l, uint32_t ticks_h);
+
+// Timer Service Calls
+extern osTimerId_t      svcRtxTimerNew       (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+extern const char *     svcRtxTimerGetName   (osTimerId_t timer_id);
+extern osStatus_t       svcRtxTimerStart     (osTimerId_t timer_id, uint32_t ticks);
+extern osStatus_t       svcRtxTimerStop      (osTimerId_t timer_id);
+extern uint32_t         svcRtxTimerIsRunning (osTimerId_t timer_id);
+extern osStatus_t       svcRtxTimerDelete    (osTimerId_t timer_id);
+
+// Event Flags Service Calls
+extern osEventFlagsId_t svcRtxEventFlagsNew     (const osEventFlagsAttr_t *attr);
+extern const char *     svcRtxEventFlagsGetName (osEventFlagsId_t ef_id);
+extern uint32_t         svcRtxEventFlagsSet     (osEventFlagsId_t ef_id, uint32_t flags);
+extern uint32_t         svcRtxEventFlagsClear   (osEventFlagsId_t ef_id, uint32_t flags);
+extern uint32_t         svcRtxEventFlagsGet     (osEventFlagsId_t ef_id);
+extern uint32_t         svcRtxEventFlagsWait    (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+extern osStatus_t       svcRtxEventFlagsDelete  (osEventFlagsId_t ef_id);
+
+// Mutex Service Calls
+extern osMutexId_t      svcRtxMutexNew      (const osMutexAttr_t *attr);
+extern const char *     svcRtxMutexGetName  (osMutexId_t mutex_id);
+extern osStatus_t       svcRtxMutexAcquire  (osMutexId_t mutex_id, uint32_t timeout);
+extern osStatus_t       svcRtxMutexRelease  (osMutexId_t mutex_id);
+extern osThreadId_t     svcRtxMutexGetOwner (osMutexId_t mutex_id);
+extern osStatus_t       svcRtxMutexDelete   (osMutexId_t mutex_id);
+
+// Semaphore Service Calls
+extern osSemaphoreId_t  svcRtxSemaphoreNew     (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+extern const char *     svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id);
+extern osStatus_t       svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id);
+extern osStatus_t       svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+extern uint32_t         svcRtxSemaphoreGetCount(osSemaphoreId_t semaphore_id);
+extern osStatus_t       svcRtxSemaphoreDelete  (osSemaphoreId_t semaphore_id);
+
+// Memory Pool Service Calls
+extern osMemoryPoolId_t svcRtxMemoryPoolNew          (uint32_t blocks, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+extern const char *     svcRtxMemoryPoolGetName      (osMemoryPoolId_t mp_id);
+extern void *           svcRtxMemoryPoolAlloc        (osMemoryPoolId_t mp_id, uint32_t timeout);
+extern osStatus_t       svcRtxMemoryPoolFree         (osMemoryPoolId_t mp_id, void *block);
+extern uint32_t         svcRtxMemoryPoolGetCapacity  (osMemoryPoolId_t mp_id);
+extern uint32_t         svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+extern uint32_t         svcRtxMemoryPoolGetCount     (osMemoryPoolId_t mp_id);
+extern uint32_t         svcRtxMemoryPoolGetSpace     (osMemoryPoolId_t mp_id);
+extern osStatus_t       svcRtxMemoryPoolDelete       (osMemoryPoolId_t mp_id);
+
+// Message Queue Service Calls
+extern osMessageQueueId_t svcRtxMessageQueueNew         (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+extern const char *       svcRtxMessageQueueGetName     (osMessageQueueId_t mq_id);
+extern osStatus_t         svcRtxMessageQueuePut         (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t  msg_prio, uint32_t timeout);
+extern osStatus_t         svcRtxMessageQueueGet         (osMessageQueueId_t mq_id,       void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+extern uint32_t           svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+extern uint32_t           svcRtxMessageQueueGetMsgSize  (osMessageQueueId_t mq_id);
+extern uint32_t           svcRtxMessageQueueGetCount    (osMessageQueueId_t mq_id);
+extern uint32_t           svcRtxMessageQueueGetSpace    (osMessageQueueId_t mq_id);
+extern osStatus_t         svcRtxMessageQueueReset       (osMessageQueueId_t mq_id);
+extern osStatus_t         svcRtxMessageQueueDelete      (osMessageQueueId_t mq_id);
+
+#endif  // RTX_LIB_H_
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.c
new file mode 100755
index 0000000..f86e802
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_memory.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Memory functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  Memory Pool Header structure
+typedef struct mem_head_s {
+  uint32_t size;                // Memory Pool size
+  uint32_t used;                // Used Memory
+} mem_head_t;
+
+//  Memory Block Header structure
+typedef struct mem_block_s {
+  struct mem_block_s *next;     // Next Memory Block in list
+  uint32_t            info;     // Info: length = <31:2>:'00', type = <1:0>
+} mem_block_t;
+
+#define MB_INFO_LEN_MASK        0xFFFFFFFCU
+#define MB_INFO_TYPE_MASK       0x00000003U
+
+
+//  ==== Library functions ====
+
+/// Initialize Memory Pool with variable block size.
+/// \param[in]  mem             pointer to memory pool.
+/// \param[in]  size            size of a memory pool in bytes.
+/// \return 1 - success, 0 - failure.
+__WEAK uint32_t osRtxMemoryInit (void *mem, uint32_t size) {
+  mem_head_t  *head;
+  mem_block_t *ptr;
+
+  if ((mem == NULL) || ((uint32_t)mem & 7U) || (size & 7U) ||
+      (size < (sizeof(mem_head_t) + 2*sizeof(mem_block_t)))) {
+    EvrRtxMemoryInit(mem, size, 0U);
+    return 0U;
+  }
+
+  head = (mem_head_t *)mem;
+  head->size = size;
+  head->used = sizeof(mem_head_t) + sizeof(mem_block_t);
+
+  ptr = (mem_block_t *)((uint32_t)mem + sizeof(mem_head_t));
+  ptr->next = (mem_block_t *)((uint32_t)mem + size - sizeof(mem_block_t));
+  ptr->next->next = NULL;
+  ptr->info = 0U;
+
+  EvrRtxMemoryInit(mem, size, 1U);
+
+  return 1U;
+}
+
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]  mem             pointer to memory pool.
+/// \param[in]  size            size of a memory block in bytes.
+/// \param[in]  type            memory block type: 0 - generic, 1 - control block
+/// \return allocated memory block or NULL in case of no memory is available.
+__WEAK void *osRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type) {
+  mem_block_t *p, *p_new, *ptr;
+  uint32_t     hole_size;
+
+  if ((mem == NULL) || (size == 0U) || (type & ~MB_INFO_TYPE_MASK)) {
+    EvrRtxMemoryAlloc(mem, size, type, NULL);
+    return NULL;
+  }
+
+  // Add header to size
+  size += sizeof(mem_block_t);
+  // Make sure that block is 8-byte aligned
+  size = (size + 7U) & ~((uint32_t)7U);
+
+  // Search for hole big enough
+  p = (mem_block_t *)((uint32_t)mem + sizeof(mem_head_t));
+  for (;;) {
+    hole_size  = (uint32_t)p->next - (uint32_t)p;
+    hole_size -= p->info & MB_INFO_LEN_MASK;
+    if (hole_size >= size) {
+      // Hole found
+      break;
+    }
+    p = p->next;
+    if (p->next == NULL) {
+      // Failed (end of list)
+      EvrRtxMemoryAlloc(mem, size, type, NULL);
+      return NULL;
+    }
+  }
+
+  ((mem_head_t *)mem)->used += size;
+
+  if (p->info == 0U) {
+    // No block allocated, set info of first element
+    p->info = size | type;
+    ptr = (mem_block_t *)((uint32_t)p + sizeof(mem_block_t));
+  } else {
+    // Insert new element into the list
+    p_new = (mem_block_t *)((uint32_t)p + (p->info & MB_INFO_LEN_MASK));
+    p_new->next = p->next;
+    p_new->info = size | type;
+    p->next = p_new;
+    ptr = (mem_block_t *)((uint32_t)p_new + sizeof(mem_block_t));
+  }
+
+  EvrRtxMemoryAlloc(mem, size, type, ptr);
+
+  return ptr;
+}
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]  mem             pointer to memory pool.
+/// \param[in]  block           memory block to be returned to the memory pool.
+/// \return 1 - success, 0 - failure.
+__WEAK uint32_t osRtxMemoryFree (void *mem, void *block) {
+  mem_block_t *p, *p_prev, *ptr;
+
+  if ((mem == NULL) || (block == NULL)) {
+    EvrRtxMemoryFree(mem, block, 0U);
+    return 0U;
+  }
+
+  ptr = (mem_block_t *)((uint32_t)block - sizeof(mem_block_t));
+
+  // Search for header
+  p_prev = NULL;
+  p = (mem_block_t *)((uint32_t)mem + sizeof(mem_head_t));
+  while (p != ptr) {
+    p_prev = p;
+    p = p->next;
+    if (p == NULL) {
+      // Not found
+      EvrRtxMemoryFree(mem, block, 0U);
+      return 0U;
+    }
+  }
+
+  ((mem_head_t *)mem)->used -= p->info & MB_INFO_LEN_MASK;
+
+  if (p_prev == NULL) {
+    // Release first block, only set info to 0
+    p->info = 0U;
+  } else {
+    // Discard block from chained list
+    p_prev->next = p->next;
+  }
+
+  EvrRtxMemoryFree(mem, block, 1U);
+
+  return 1U;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.c
new file mode 100755
index 0000000..63bb32a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mempool.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Memory Pool functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Library functions ====
+
+/// Initialize Memory Pool.
+/// \param[in]  mp_info         memory pool info.
+/// \param[in]  block_count     maximum number of memory blocks in memory pool.
+/// \param[in]  block_size      size of a memory block in bytes.
+/// \param[in]  block_mem       pointer to memory for block storage.
+/// \return 1 - success, 0 - failure.
+uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) {
+  void *block;
+
+  // Check parameters
+  if ((mp_info == NULL) || (block_count == 0U) || (block_size  == 0U) || (block_mem   == NULL)) {
+    return 0U;
+  }
+
+  // Initialize information structure
+  mp_info->max_blocks  = block_count;
+  mp_info->used_blocks = 0U;
+  mp_info->block_size  = block_size;
+  mp_info->block_base  = block_mem;
+  mp_info->block_free  = block_mem;
+  mp_info->block_lim   = (uint8_t *)block_mem + (block_count * block_size);
+
+  EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem);
+
+  // Link all free blocks
+  while (--block_count) {
+    block = (uint8_t *)block_mem + block_size;
+    *((void **)block_mem) = block;
+    block_mem = block;
+  }
+  *((void **)block_mem) = NULL;
+
+  return 1U;
+}
+
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]  mp_info         memory pool info.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  void *block;
+
+  if (mp_info == NULL) {
+    EvrRtxMemoryBlockAlloc(NULL, NULL);
+    return NULL;
+  }
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  if (mp_info->used_blocks < mp_info->max_blocks) {
+    mp_info->used_blocks++;
+    block = mp_info->block_free;
+    if (block != NULL) {
+      mp_info->block_free = *((void **)block);
+    }
+  } else {
+    block = NULL;
+  }
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  if (atomic_inc32_lt(&mp_info->used_blocks, mp_info->max_blocks) < mp_info->max_blocks) {
+    block = atomic_link_get(&mp_info->block_free);
+  } else {
+    block = NULL;
+  }
+#endif
+
+  EvrRtxMemoryBlockAlloc(mp_info, block);
+
+  return block;
+}
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]  mp_info         memory pool info.
+/// \param[in]  block           address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  osStatus_t status;
+
+  if ((mp_info == NULL) || (block < mp_info->block_base) || (block >= mp_info->block_lim)) {
+    EvrRtxMemoryBlockFree(mp_info, block, osErrorParameter);
+    return osErrorParameter;
+  }
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  if (mp_info->used_blocks != 0U) {
+    mp_info->used_blocks--;
+    *((void **)block) = mp_info->block_free;
+    mp_info->block_free = block;
+    status = osOK;
+  } else {
+    status = osErrorResource;
+  }
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  if (atomic_dec32_nz(&mp_info->used_blocks) != 0U) {
+    atomic_link_put(&mp_info->block_free, block);
+    status = osOK;
+  } else {
+    status = osErrorResource;
+  }
+#endif
+
+  EvrRtxMemoryBlockFree(mp_info, block, status);
+
+  return status;
+}
+
+/// Memory Pool post ISR processing.
+/// \param[in]  mp              memory pool object.
+void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp) {
+  void        *block;
+  os_thread_t *thread;
+
+  if (mp->state == osRtxObjectInactive) {
+    return;
+  }
+
+  // Check if Thread is waiting to allocate memory
+  if (mp->thread_list != NULL) {
+    // Allocate memory
+    block = osRtxMemoryPoolAlloc(&mp->mp_info);
+    if (block != NULL) {
+      // Wakeup waiting Thread with highest Priority
+      thread = osRtxThreadListGet((os_object_t*)mp);
+      osRtxThreadWaitExit(thread, (uint32_t)block, false);
+      EvrRtxMemoryPoolAllocated(mp, block);
+    }
+  }
+}
+
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_3M(MemoryPoolNew,          osMemoryPoolId_t, uint32_t, uint32_t, const osMemoryPoolAttr_t *)
+SVC0_1 (MemoryPoolGetName,      const char *,     osMemoryPoolId_t)
+SVC0_2 (MemoryPoolAlloc,        void *,           osMemoryPoolId_t, uint32_t)
+SVC0_2 (MemoryPoolFree,         osStatus_t,       osMemoryPoolId_t, void *)
+SVC0_1 (MemoryPoolGetCapacity,  uint32_t,         osMemoryPoolId_t)
+SVC0_1 (MemoryPoolGetBlockSize, uint32_t,         osMemoryPoolId_t)
+SVC0_1 (MemoryPoolGetCount,     uint32_t,         osMemoryPoolId_t)
+SVC0_1 (MemoryPoolGetSpace,     uint32_t,         osMemoryPoolId_t)
+SVC0_1 (MemoryPoolDelete,       osStatus_t,       osMemoryPoolId_t)
+
+/// Create and Initialize a Memory Pool object.
+/// \note API identical to osMemoryPoolNew
+osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
+  os_memory_pool_t *mp;
+  void             *mp_mem;
+  uint32_t          mp_size;
+  uint32_t          size;
+  uint8_t           flags;
+  const char       *name;
+
+  // Check parameters
+  if ((block_count == 0U) || (block_size  == 0U)) {
+    EvrRtxMemoryPoolError(NULL, osErrorParameter);
+    return NULL;
+  }
+  block_size = (block_size + 3U) & ~3UL;
+  if ((__CLZ(block_count) + __CLZ(block_size)) < 32) {
+    EvrRtxMemoryPoolError(NULL, osErrorParameter);
+    return NULL;
+  }
+
+  size = block_count * block_size;
+
+  // Process attributes
+  if (attr != NULL) {
+    name    = attr->name;
+    mp      = attr->cb_mem;
+    mp_mem  = attr->mp_mem;
+    mp_size = attr->mp_size;
+    if (mp != NULL) {
+      if (((uint32_t)mp & 3U) || (attr->cb_size < sizeof(os_memory_pool_t))) {
+        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    } else {
+      if (attr->cb_size != 0U) {
+        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    }
+    if (mp_mem != NULL) {
+      if (((uint32_t)mp_mem & 3U) || (mp_size < size)) {
+        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory);
+        return NULL;
+      }
+    } else {
+      if (mp_size != 0U) {
+        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory);
+        return NULL;
+      }
+    }
+  } else {
+    name   = NULL;
+    mp     = NULL;
+    mp_mem = NULL;
+  }
+
+  // Allocate object memory if not provided
+  if (mp == NULL) {
+    if (osRtxInfo.mpi.memory_pool != NULL) {
+      mp = osRtxMemoryPoolAlloc(osRtxInfo.mpi.memory_pool);
+    } else {
+      mp = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_memory_pool_t), 1U);
+    }
+    if (mp == NULL) {
+      EvrRtxMemoryPoolError(NULL, osErrorNoMemory);
+      return NULL;
+    }
+    flags = osRtxFlagSystemObject;
+  } else {
+    flags = 0U;
+  }
+
+  // Allocate data memory if not provided
+  if (mp_mem == NULL) {
+    mp_mem = osRtxMemoryAlloc(osRtxInfo.mem.mp_data, size, 0U);
+    if (mp_mem == NULL) {
+      EvrRtxMemoryPoolError(NULL, osErrorNoMemory);
+      if (flags & osRtxFlagSystemObject) {
+        if (osRtxInfo.mpi.memory_pool != NULL) {
+          osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);
+        } else {
+          osRtxMemoryFree(osRtxInfo.mem.common, mp);
+        }
+      }
+      return NULL;
+    }
+    memset(mp_mem, 0, size);
+    flags |= osRtxFlagSystemMemory;
+  }
+
+  // Initialize control block
+  mp->id          = osRtxIdMemoryPool;
+  mp->state       = osRtxObjectActive;
+  mp->flags       = flags;
+  mp->name        = name;
+  mp->thread_list = NULL;
+  osRtxMemoryPoolInit(&mp->mp_info, block_count, block_size, mp_mem);
+
+  // Register post ISR processing function
+  osRtxInfo.post_process.memory_pool = osRtxMemoryPoolPostProcess;
+
+  EvrRtxMemoryPoolCreated(mp);
+
+  return mp;
+}
+
+/// Get name of a Memory Pool object.
+/// \note API identical to osMemoryPoolGetName
+const char *svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolGetName(mp, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolGetName(mp, NULL);
+    return NULL;
+  }
+
+  EvrRtxMemoryPoolGetName(mp, mp->name);
+
+  return mp->name;
+}
+
+/// Allocate a memory block from a Memory Pool.
+/// \note API identical to osMemoryPoolAlloc
+void *svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+  void             *block;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolError(mp, osErrorParameter);
+    return NULL;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolError(mp, osErrorResource);
+    return NULL;
+  }
+
+  // Allocate memory
+  block = osRtxMemoryPoolAlloc(&mp->mp_info);
+  if (block == NULL) {
+    // No memory available
+    if (timeout != 0U) {
+      EvrRtxMemoryPoolAllocPending(mp, timeout);
+      // Suspend current Thread
+      osRtxThreadListPut((os_object_t*)mp, osRtxThreadGetRunning());
+      osRtxThreadWaitEnter(osRtxThreadWaitingMemoryPool, timeout);
+    } else {
+      EvrRtxMemoryPoolAllocFailed(mp);
+    }
+  } else {
+    EvrRtxMemoryPoolAllocated(mp, block);
+  }
+
+  return block;
+}
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \note API identical to osMemoryPoolFree
+osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+  os_thread_t      *thread;
+  osStatus_t        status;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolError(mp, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolError(mp, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Free memory
+  status = osRtxMemoryPoolFree(&mp->mp_info, block);
+  if (status == osOK) {
+    EvrRtxMemoryPoolDeallocated(mp, block);
+    // Check if Thread is waiting to allocate memory
+    if (mp->thread_list != NULL) {
+      // Allocate memory
+      block = osRtxMemoryPoolAlloc(&mp->mp_info);
+      if (block != NULL) {
+        // Wakeup waiting Thread with highest Priority
+        thread = osRtxThreadListGet((os_object_t*)mp);
+        osRtxThreadWaitExit(thread, (uint32_t)block, true);
+        EvrRtxMemoryPoolAllocated(mp, block);
+      }
+    }
+  } else {
+    EvrRtxMemoryPoolFreeFailed(mp, block);
+  }
+
+  return status;
+}
+
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \note API identical to osMemoryPoolGetCapacity
+uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolGetCapacity(mp, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolGetCapacity(mp, 0U);
+    return 0U;
+  }
+
+  EvrRtxMemoryPoolGetCapacity(mp, mp->mp_info.max_blocks);
+
+  return mp->mp_info.max_blocks;
+}
+
+/// Get memory block size in a Memory Pool.
+/// \note API identical to osMemoryPoolGetBlockSize
+uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolGetBlockSize(mp, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolGetBlockSize(mp, 0U);
+    return 0U;
+  }
+
+  EvrRtxMemoryPoolGetBlockSize(mp, mp->mp_info.block_size);
+
+  return mp->mp_info.block_size;
+}
+
+/// Get number of memory blocks used in a Memory Pool.
+/// \note API identical to osMemoryPoolGetCount
+uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolGetCount(mp, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolGetCount(mp, 0U);
+    return 0U;
+  }
+
+  EvrRtxMemoryPoolGetCount(mp, mp->mp_info.used_blocks);
+
+  return mp->mp_info.used_blocks;
+}
+
+/// Get number of memory blocks available in a Memory Pool.
+/// \note API identical to osMemoryPoolGetSpace
+uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolGetSpace(mp, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolGetSpace(mp, 0U);
+    return 0U;
+  }
+
+  EvrRtxMemoryPoolGetSpace(mp, mp->mp_info.max_blocks - mp->mp_info.used_blocks);
+
+  return (mp->mp_info.max_blocks - mp->mp_info.used_blocks);
+}
+
+/// Delete a Memory Pool object.
+/// \note API identical to osMemoryPoolDelete
+osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+  os_thread_t      *thread;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolError(mp, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolError(mp, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Mark object as inactive
+  mp->state = osRtxObjectInactive;
+
+  // Unblock waiting threads
+  if (mp->thread_list != NULL) {
+    do {
+      thread = osRtxThreadListGet((os_object_t*)mp);
+      osRtxThreadWaitExit(thread, 0U, false);
+    } while (mp->thread_list != NULL);
+    osRtxThreadDispatch(NULL);
+  }
+
+  // Free data memory
+  if (mp->flags & osRtxFlagSystemMemory) {
+    osRtxMemoryFree(osRtxInfo.mem.mp_data, mp->mp_info.block_base);
+  }
+
+  // Free object memory
+  if (mp->flags & osRtxFlagSystemObject) {
+    if (osRtxInfo.mpi.memory_pool != NULL) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.common, mp);
+    }
+  }
+
+  EvrRtxMemoryPoolDestroyed(mp);
+
+  return osOK;
+}
+
+
+//  ==== ISR Calls ====
+
+/// Allocate a memory block from a Memory Pool.
+/// \note API identical to osMemoryPoolAlloc
+__STATIC_INLINE
+void *isrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+  void             *block;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool) || (timeout != 0U)) {
+    EvrRtxMemoryPoolError(mp, osErrorParameter);
+    return NULL;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolError(mp, osErrorResource);
+    return NULL;
+  }
+
+  // Allocate memory
+  block = osRtxMemoryPoolAlloc(&mp->mp_info);
+  if (block == NULL) {
+    EvrRtxMemoryPoolAllocFailed(mp);
+  } else {
+    EvrRtxMemoryPoolAllocated(mp, block);
+  }
+
+  return block;
+}
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \note API identical to osMemoryPoolFree
+__STATIC_INLINE
+osStatus_t isrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
+  os_memory_pool_t *mp = (os_memory_pool_t *)mp_id;
+  osStatus_t        status;
+
+  // Check parameters
+  if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) {
+    EvrRtxMemoryPoolError(mp, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mp->state == osRtxObjectInactive) {
+    EvrRtxMemoryPoolError(mp, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Free memory
+  status = osRtxMemoryPoolFree(&mp->mp_info, block);
+  if (status == osOK) {
+    // Register post ISR processing
+    osRtxPostProcess((os_object_t *)mp);
+    EvrRtxMemoryPoolDeallocated(mp, block);
+  } else {
+    EvrRtxMemoryPoolFreeFailed(mp, block);
+  }
+
+  return status;
+}
+
+
+//  ==== Public API ====
+
+/// Create and Initialize a Memory Pool object.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
+  EvrRtxMemoryPoolNew(block_count, block_size, attr);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMemoryPoolError(NULL, osErrorISR);
+    return NULL;
+  }
+  return __svcMemoryPoolNew(block_count, block_size, attr);
+}
+
+/// Get name of a Memory Pool object.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMemoryPoolGetName(mp_id, NULL);
+    return NULL;
+  }
+  return __svcMemoryPoolGetName(mp_id);
+}
+
+/// Allocate a memory block from a Memory Pool.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
+  EvrRtxMemoryPoolAlloc(mp_id, timeout);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxMemoryPoolAlloc(mp_id, timeout);
+  } else {
+    return  __svcMemoryPoolAlloc(mp_id, timeout);
+  }
+}
+
+/// Return an allocated memory block back to a Memory Pool.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
+  EvrRtxMemoryPoolFree(mp_id, block);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxMemoryPoolFree(mp_id, block);
+  } else {
+    return  __svcMemoryPoolFree(mp_id, block);
+  }
+}
+
+/// Get maximum number of memory blocks in a Memory Pool.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMemoryPoolGetCapacity(mp_id);
+  } else {
+    return  __svcMemoryPoolGetCapacity(mp_id);
+  }
+}
+
+/// Get memory block size in a Memory Pool.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMemoryPoolGetBlockSize(mp_id);
+  } else {
+    return  __svcMemoryPoolGetBlockSize(mp_id);
+  }
+}
+
+/// Get number of memory blocks used in a Memory Pool.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMemoryPoolGetCount(mp_id);
+  } else {
+    return  __svcMemoryPoolGetCount(mp_id);
+  }
+}
+
+/// Get number of memory blocks available in a Memory Pool.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMemoryPoolGetSpace(mp_id);
+  } else {
+    return  __svcMemoryPoolGetSpace(mp_id);
+  }
+}
+
+/// Delete a Memory Pool object.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) {
+  EvrRtxMemoryPoolDelete(mp_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMemoryPoolError(mp_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcMemoryPoolDelete(mp_id);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.c
new file mode 100755
index 0000000..d147e81
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.c
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Message Queue functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Helper functions ====
+
+/// Put a Message into Queue sorted by Priority (Highest at Head).
+/// \param[in]  mq              message queue object.
+/// \param[in]  msg             message object.
+static void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t      primask = __get_PRIMASK();
+#endif
+  os_message_t *prev, *next;
+
+  if (mq->msg_last != NULL) {
+    prev = mq->msg_last;
+    next = NULL;
+    while ((prev != NULL) && (prev->priority < msg->priority)) {
+      next = prev;
+      prev = prev->prev;
+    }
+    msg->prev = prev;
+    msg->next = next;
+    if (prev != NULL) {
+      prev->next = msg;
+    } else {
+      mq->msg_first = msg;
+    }
+    if (next != NULL) {
+      next->prev = msg;
+    } else {
+      mq->msg_last = msg;
+    }
+  } else {
+    msg->prev = NULL;
+    msg->next = NULL;
+    mq->msg_first= msg;
+    mq->msg_last = msg;
+  }
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  mq->msg_count++;
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  atomic_inc32(&mq->msg_count);
+#endif
+}
+
+/// Get a Message from Queue with Highest Priority.
+/// \param[in]  mq              message queue object.
+/// \return message object or NULL.
+static os_message_t *MessageQueueGet (os_message_queue_t *mq) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t      primask = __get_PRIMASK();
+#endif
+  os_message_t *msg;
+  uint32_t      count;
+  uint8_t       flags;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  count = mq->msg_count;
+  if (count != 0U) {
+    mq->msg_count--;
+  }
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  count = atomic_dec32_nz(&mq->msg_count);
+#endif
+
+  if (count == 0U) {
+    return NULL;
+  }
+
+  msg = mq->msg_first;
+
+  while (msg != NULL) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+    __disable_irq();
+
+    flags = msg->flags;
+    msg->flags = 1U;
+
+    if (primask == 0U) {
+      __enable_irq();
+    }
+#else
+    flags = atomic_wr8(&msg->flags, 1U);
+#endif
+    if (flags == 0U) {
+      break;
+    }
+    msg = msg->next;
+  }
+
+  return msg;
+}
+
+/// Remove a Message from Queue
+/// \param[in]  mq              message queue object.
+/// \param[in]  msg             message object.
+static void MessageQueueRemove (os_message_queue_t *mq, os_message_t *msg) {
+
+  if (msg->prev != NULL) {
+    msg->prev->next = msg->next;
+  } else {
+    mq->msg_first = msg->next;
+  }
+  if (msg->next != NULL) {
+    msg->next->prev = msg->prev;
+  } else {
+    mq->msg_last = msg->prev;
+  }
+}
+
+
+//  ==== Library functions ====
+
+/// Message Queue post ISR processing.
+/// \param[in]  msg             message object.
+void osRtxMessageQueuePostProcess (os_message_t *msg) {
+  os_message_queue_t *mq;
+  os_thread_t        *thread;
+  uint32_t           *reg;
+  void              **ptr;
+
+  if (msg->state == osRtxObjectInactive) {
+    return;
+  }
+
+  if (msg->flags != 0U) {
+    // Remove Message
+    ptr = (void *)((uint8_t *)msg + sizeof(os_message_t));
+    mq = *ptr;
+    if (mq->state == osRtxObjectInactive) {
+      return;
+    }
+    MessageQueueRemove(mq, msg);
+    // Free memory
+    msg->state = osRtxObjectInactive;
+    osRtxMemoryPoolFree(&mq->mp_info, msg);
+    // Check if Thread is waiting to send a Message
+    if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) {
+      // Try to allocate memory
+      msg = osRtxMemoryPoolAlloc(&mq->mp_info);
+      if (msg != NULL) {
+        // Wakeup waiting Thread with highest Priority
+        thread = osRtxThreadListGet((os_object_t*)mq);
+        osRtxThreadWaitExit(thread, (uint32_t)osOK, false);
+        // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio)
+        reg = osRtxThreadRegPtr(thread);
+        memcpy((uint8_t *)msg + sizeof(os_message_t), (void *)reg[2], mq->msg_size);
+        // Store Message into Queue
+        msg->id       = osRtxIdMessage;
+        msg->state    = osRtxObjectActive;
+        msg->flags    = 0U;
+        msg->priority = (uint8_t)reg[3];
+        MessageQueuePut(mq, msg);
+        EvrRtxMessageQueueInserted(mq, (void *)reg[2]);
+      }
+    }
+  } else {
+    // New Message
+    mq = (void *)msg->next;
+    if (mq->state == osRtxObjectInactive) {
+      return;
+    }
+    // Check if Thread is waiting to receive a Message
+    if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) {
+      EvrRtxMessageQueueInserted(mq, (void *)msg->prev);
+      // Wakeup waiting Thread with highest Priority
+      thread = osRtxThreadListGet((os_object_t*)mq);
+      osRtxThreadWaitExit(thread, (uint32_t)osOK, false);
+      // Copy Message (R2: void *msg_ptr, R3: uint8_t *msg_prio)
+      reg = osRtxThreadRegPtr(thread);
+      memcpy((void *)reg[2], (uint8_t *)msg + sizeof(os_message_t), mq->msg_size);
+      if (reg[3] != 0U) {
+        *((uint8_t *)reg[3]) = msg->priority;
+      }
+      EvrRtxMessageQueueRetrieved(mq, (void *)reg[2]);
+      // Free memory
+      msg->state = osRtxObjectInactive;
+      osRtxMemoryPoolFree(&mq->mp_info, msg);
+    } else {
+      EvrRtxMessageQueueInserted(mq, (void *)msg->prev);
+      MessageQueuePut(mq, msg);
+    }
+  }
+}
+
+
+//  ==== Service Calls ====
+
+SVC0_3M(MessageQueueNew,         osMessageQueueId_t, uint32_t, uint32_t, const osMessageQueueAttr_t *)
+SVC0_1 (MessageQueueGetName,     const char *,       osMessageQueueId_t)
+SVC0_4 (MessageQueuePut,         osStatus_t,         osMessageQueueId_t, const void *, uint8_t,   uint32_t)
+SVC0_4 (MessageQueueGet,         osStatus_t,         osMessageQueueId_t,       void *, uint8_t *, uint32_t)
+SVC0_1 (MessageQueueGetCapacity, uint32_t,           osMessageQueueId_t)
+SVC0_1 (MessageQueueGetMsgSize,  uint32_t,           osMessageQueueId_t)
+SVC0_1 (MessageQueueGetCount,    uint32_t,           osMessageQueueId_t)
+SVC0_1 (MessageQueueGetSpace,    uint32_t,           osMessageQueueId_t)
+SVC0_1 (MessageQueueReset,       osStatus_t,         osMessageQueueId_t)
+SVC0_1 (MessageQueueDelete,      osStatus_t,         osMessageQueueId_t)
+
+/// Create and Initialize a Message Queue object.
+/// \note API identical to osMessageQueueNew
+osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
+  os_message_queue_t *mq;
+  void               *mq_mem;
+  uint32_t            mq_size;
+  uint32_t            block_size;
+  uint32_t            size;
+  uint8_t             flags;
+  const char         *name;
+
+  // Check parameters
+  if ((msg_count == 0U) || (msg_size  == 0U)) {
+    EvrRtxMessageQueueError(NULL, osErrorParameter);
+    return NULL;
+  }
+  msg_size = (msg_size + 3U) & ~3UL;
+  block_size = msg_size + sizeof(os_message_t);
+  if ((__CLZ(msg_count) + __CLZ(block_size)) < 32) {
+    EvrRtxMessageQueueError(NULL, osErrorParameter);
+    return NULL;
+  }
+
+  size = msg_count * block_size;
+
+  // Process attributes
+  if (attr != NULL) {
+    name    = attr->name;
+    mq      = attr->cb_mem;
+    mq_mem  = attr->mq_mem;
+    mq_size = attr->mq_size;
+    if (mq != NULL) {
+      if (((uint32_t)mq & 3U) || (attr->cb_size < sizeof(os_message_queue_t))) {
+        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    } else {
+      if (attr->cb_size != 0U) {
+        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    }
+    if (mq_mem != NULL) {
+      if (((uint32_t)mq_mem & 3U) || (mq_size < size)) {
+        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory);
+        return NULL;
+      }
+    } else {
+      if (mq_size != 0U) {
+        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory);
+        return NULL;
+      }
+    }
+  } else {
+    name   = NULL;
+    mq     = NULL;
+    mq_mem = NULL;
+  }
+
+  // Allocate object memory if not provided
+  if (mq == NULL) {
+    if (osRtxInfo.mpi.message_queue != NULL) {
+      mq = osRtxMemoryPoolAlloc(osRtxInfo.mpi.message_queue);
+    } else {
+      mq = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_message_queue_t), 1U);
+    }
+    if (mq == NULL) {
+      EvrRtxMessageQueueError(NULL, osErrorNoMemory);
+      return NULL;
+    }
+    flags = osRtxFlagSystemObject;
+  } else {
+    flags = 0U;
+  }
+
+  // Allocate data memory if not provided
+  if (mq_mem == NULL) {
+    mq_mem = osRtxMemoryAlloc(osRtxInfo.mem.mq_data, size, 0U);
+    if (mq_mem == NULL) {
+      EvrRtxMessageQueueError(NULL, osErrorNoMemory);
+      if (flags & osRtxFlagSystemObject) {
+        if (osRtxInfo.mpi.message_queue != NULL) {
+          osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);
+        } else {
+          osRtxMemoryFree(osRtxInfo.mem.common, mq);
+        }
+      }
+      return NULL;
+    }
+    memset(mq_mem, 0, size);
+    flags |= osRtxFlagSystemMemory;
+  }
+
+  // Initialize control block
+  mq->id          = osRtxIdMessageQueue;
+  mq->state       = osRtxObjectActive;
+  mq->flags       = flags;
+  mq->name        = name;
+  mq->thread_list = NULL;
+  mq->msg_size    = msg_size;
+  mq->msg_count   = 0U;
+  mq->msg_first   = NULL;
+  mq->msg_last    = NULL;
+  osRtxMemoryPoolInit(&mq->mp_info, msg_count, block_size, mq_mem);
+
+  // Register post ISR processing function
+  osRtxInfo.post_process.message_queue = osRtxMessageQueuePostProcess;
+
+  EvrRtxMessageQueueCreated(mq);
+
+  return mq;
+}
+
+/// Get name of a Message Queue object.
+/// \note API identical to osMessageQueueGetName
+const char *svcRtxMessageQueueGetName (osMessageQueueId_t mq_id) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) {
+    EvrRtxMessageQueueGetName(mq, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueGetName(mq, NULL);
+    return NULL;
+  }
+
+  EvrRtxMessageQueueGetName(mq, mq->name);
+
+  return mq->name;
+}
+
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \note API identical to osMessageQueuePut
+osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+  os_message_t       *msg;
+  os_thread_t        *thread;
+  uint32_t           *reg;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) {
+    EvrRtxMessageQueueError(mq, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueError(mq, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Check if Thread is waiting to receive a Message
+  if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) {
+    EvrRtxMessageQueueInserted(mq, msg_ptr);
+    // Wakeup waiting Thread with highest Priority
+    thread = osRtxThreadListGet((os_object_t*)mq);
+    osRtxThreadWaitExit(thread, (uint32_t)osOK, true);
+    // Copy Message (R2: void *msg_ptr, R3: uint8_t *msg_prio)
+    reg = osRtxThreadRegPtr(thread);
+    memcpy((void *)reg[2], msg_ptr, mq->msg_size);
+    if (reg[3] != 0U) {
+      *((uint8_t *)reg[3]) = msg_prio;
+    }
+    EvrRtxMessageQueueRetrieved(mq, (void *)reg[2]);
+    return osOK;
+  }
+
+  // Try to allocate memory
+  msg = osRtxMemoryPoolAlloc(&mq->mp_info);
+  if (msg != NULL) {
+    // Copy Message
+    memcpy((uint8_t *)msg + sizeof(os_message_t), msg_ptr, mq->msg_size);
+    // Put Message into Queue
+    msg->id       = osRtxIdMessage;
+    msg->state    = osRtxObjectActive;
+    msg->flags    = 0U;
+    msg->priority = msg_prio;
+    MessageQueuePut(mq, msg);
+  } else {
+    // No memory available
+    if (timeout != 0U) {
+      EvrRtxMessageQueuePutPending(mq, msg_ptr, timeout);
+      // Suspend current Thread
+      osRtxThreadListPut((os_object_t*)mq, osRtxThreadGetRunning());
+      osRtxThreadWaitEnter(osRtxThreadWaitingMessagePut, timeout);
+      // Save arguments (R2: const void *msg_ptr, R3: uint8_t msg_prio)
+      reg = (uint32_t *)(__get_PSP());
+      reg[2] = (uint32_t)msg_ptr;
+      reg[3] = (uint32_t)msg_prio;
+      return osErrorTimeout;
+    } else {
+      EvrRtxMessageQueueNotInserted(mq, msg_ptr);
+      return osErrorResource;
+    }
+  }
+
+  EvrRtxMessageQueueInserted(mq, msg_ptr);
+
+  return osOK;
+}
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \note API identical to osMessageQueueGet
+osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+  os_message_t       *msg;
+  os_thread_t        *thread;
+  uint32_t           *reg;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) {
+    EvrRtxMessageQueueError(mq, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueError(mq, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Get Message from Queue
+  msg = MessageQueueGet(mq);
+  if (msg != NULL) {
+    MessageQueueRemove(mq, msg);
+    // Copy Message
+    memcpy(msg_ptr, (uint8_t *)msg + sizeof(os_message_t), mq->msg_size);
+    if (msg_prio != NULL) {
+      *msg_prio = msg->priority;
+    }
+    EvrRtxMessageQueueRetrieved(mq, msg_ptr);
+    // Free memory
+    msg->state = osRtxObjectInactive;
+    osRtxMemoryPoolFree(&mq->mp_info, msg);
+  } else {
+    // No Message available
+    if (timeout != 0U) {
+      EvrRtxMessageQueueGetPending(mq, msg_ptr, timeout);
+      // Suspend current Thread
+      osRtxThreadListPut((os_object_t*)mq, osRtxThreadGetRunning());
+      osRtxThreadWaitEnter(osRtxThreadWaitingMessageGet, timeout);
+      // Save arguments (R2: void *msg_ptr, R3: uint8_t *msg_prio)
+      reg = (uint32_t *)(__get_PSP());
+      reg[2] = (uint32_t)msg_ptr;
+      reg[3] = (uint32_t)msg_prio;
+      return osErrorTimeout;
+    } else {
+      EvrRtxMessageQueueNotRetrieved(mq, msg_ptr);
+      return osErrorResource;
+    }
+  }
+
+  // Check if Thread is waiting to send a Message
+  if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) {
+    // Try to allocate memory
+    msg = osRtxMemoryPoolAlloc(&mq->mp_info);
+    if (msg != NULL) {
+      // Wakeup waiting Thread with highest Priority
+      thread = osRtxThreadListGet((os_object_t*)mq);
+      osRtxThreadWaitExit(thread, (uint32_t)osOK, true);
+      // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio)
+      reg = osRtxThreadRegPtr(thread);
+      memcpy((uint8_t *)msg + sizeof(os_message_t), (void *)reg[2], mq->msg_size);
+      // Store Message into Queue
+      msg->id       = osRtxIdMessage;
+      msg->state    = osRtxObjectActive;
+      msg->flags    = 0U;
+      msg->priority = (uint8_t)reg[3];
+      MessageQueuePut(mq, msg);
+      EvrRtxMessageQueueInserted(mq, (void *)reg[2]);
+    }
+  }
+
+  return osOK;
+}
+
+/// Get maximum number of messages in a Message Queue.
+/// \note API identical to osMessageGetCapacity
+uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) {
+    EvrRtxMessageQueueGetCapacity(mq, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueGetCapacity(mq, 0U);
+    return 0U;
+  }
+
+  EvrRtxMessageQueueGetCapacity(mq, mq->mp_info.max_blocks);
+
+  return mq->mp_info.max_blocks;
+}
+
+/// Get maximum message size in a Memory Pool.
+/// \note API identical to osMessageGetMsgSize
+uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) {
+    EvrRtxMessageQueueGetMsgSize(mq, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueGetMsgSize(mq, 0U);
+    return 0U;
+  }
+
+  EvrRtxMessageQueueGetMsgSize(mq, mq->msg_size);
+
+  return mq->msg_size;
+}
+
+/// Get number of queued messages in a Message Queue.
+/// \note API identical to osMessageGetCount
+uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) {
+    EvrRtxMessageQueueGetCount(mq, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueGetCount(mq, 0U);
+    return 0U;
+  }
+
+  EvrRtxMessageQueueGetCount(mq, mq->msg_count);
+
+  return mq->msg_count;
+}
+
+/// Get number of available slots for messages in a Message Queue.
+/// \note API identical to osMessageGetSpace
+uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) {
+    EvrRtxMessageQueueGetSpace(mq, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueGetSpace(mq, 0U);
+    return 0U;
+  }
+
+  EvrRtxMessageQueueGetSpace(mq, mq->mp_info.max_blocks - mq->msg_count);
+
+  return (mq->mp_info.max_blocks - mq->msg_count);
+}
+
+/// Reset a Message Queue to initial empty state.
+/// \note API identical to osMessageQueueReset
+osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+  os_message_t       *msg;
+  os_thread_t        *thread;
+  uint32_t           *reg;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) {
+    EvrRtxMessageQueueError(mq, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueError(mq, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Remove Messages from Queue
+  for (;;) {
+    // Get Message from Queue
+    msg = MessageQueueGet(mq);
+    if (msg == NULL) {
+      break;
+    }
+    MessageQueueRemove(mq, msg);
+    EvrRtxMessageQueueRetrieved(mq, NULL);
+    // Free memory
+    msg->state = osRtxObjectInactive;
+    osRtxMemoryPoolFree(&mq->mp_info, msg);
+  }
+
+  // Check if Threads are waiting to send Messages
+  if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) {
+    do {
+      // Try to allocate memory
+      msg = osRtxMemoryPoolAlloc(&mq->mp_info);
+      if (msg != NULL) {
+        // Wakeup waiting Thread with highest Priority
+        thread = osRtxThreadListGet((os_object_t*)mq);
+        osRtxThreadWaitExit(thread, (uint32_t)osOK, false);
+        // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio)
+        reg = osRtxThreadRegPtr(thread);
+        memcpy((uint8_t *)msg + sizeof(os_message_t), (void *)reg[2], mq->msg_size);
+        // Store Message into Queue
+        msg->id       = osRtxIdMessage;
+        msg->state    = osRtxObjectActive;
+        msg->flags    = 0U;
+        msg->priority = (uint8_t)reg[3];
+        MessageQueuePut(mq, msg);
+        EvrRtxMessageQueueInserted(mq, (void *)reg[2]);
+      }
+    } while ((msg != NULL) && (mq->thread_list != NULL));
+    osRtxThreadDispatch(NULL);
+  }
+
+  EvrRtxMessageQueueResetDone(mq);
+
+  return osOK;
+}
+
+/// Delete a Message Queue object.
+/// \note API identical to osMessageQueueDelete
+osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+  os_thread_t        *thread;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) {
+    EvrRtxMessageQueueError(mq, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueError(mq, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Mark object as inactive
+  mq->state = osRtxObjectInactive;
+
+  // Unblock waiting threads
+  if (mq->thread_list != NULL) {
+    do {
+      thread = osRtxThreadListGet((os_object_t*)mq);
+      osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false);
+    } while (mq->thread_list != NULL);
+    osRtxThreadDispatch(NULL);
+  }
+
+  // Free data memory
+  if (mq->flags & osRtxFlagSystemMemory) {
+    osRtxMemoryFree(osRtxInfo.mem.mq_data, mq->mp_info.block_base);
+  }
+
+  // Free object memory
+  if (mq->flags & osRtxFlagSystemObject) {
+    if (osRtxInfo.mpi.message_queue != NULL) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.common, mq);
+    }
+  }
+
+  EvrRtxMessageQueueDestroyed(mq);
+
+  return osOK;
+}
+
+
+//  ==== ISR Calls ====
+
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \note API identical to osMessageQueuePut
+__STATIC_INLINE
+osStatus_t isrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+  os_message_t       *msg;
+  const void        **ptr;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) {
+    EvrRtxMessageQueueError(mq, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueError(mq, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Try to allocate memory
+  msg = osRtxMemoryPoolAlloc(&mq->mp_info);
+  if (msg != NULL) {
+    // Copy Message
+    memcpy((uint8_t *)msg + sizeof(os_message_t), msg_ptr, mq->msg_size);
+    msg->id       = osRtxIdMessage;
+    msg->state    = osRtxObjectActive;
+    msg->flags    = 0U;
+    msg->priority = msg_prio;
+    // Register post ISR processing
+     ptr = (void *)&msg->prev;
+    *ptr = msg_ptr;
+     ptr = (void *)&msg->next;
+    *ptr = mq;
+    osRtxPostProcess((os_object_t *)msg);
+  } else {
+    // No memory available
+    EvrRtxMessageQueueNotInserted(mq, msg_ptr);
+    return osErrorResource;
+  }
+
+  EvrRtxMessageQueueInsertPending(mq, msg_ptr);
+
+  return osOK;
+}
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \note API identical to osMessageQueueGet
+__STATIC_INLINE
+osStatus_t isrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
+  os_message_queue_t *mq = (os_message_queue_t *)mq_id;
+  os_message_t       *msg;
+  void              **ptr;
+
+  // Check parameters
+  if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) {
+    EvrRtxMessageQueueError(mq, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mq->state == osRtxObjectInactive) {
+    EvrRtxMessageQueueError(mq, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Get Message from Queue
+  msg = MessageQueueGet(mq);
+  if (msg != NULL) {
+    // Copy Message
+    memcpy(msg_ptr, (uint8_t *)msg + sizeof(os_message_t), mq->msg_size);
+    if (msg_prio != NULL) {
+      *msg_prio = msg->priority;
+    }
+    EvrRtxMessageQueueRetrieved(mq, msg_ptr);
+    // Register post ISR processing
+     ptr = (void *)((uint8_t *)msg + sizeof(os_message_t));
+    *ptr = mq;
+    osRtxPostProcess((os_object_t *)msg);
+  } else {
+    // No Message available
+    EvrRtxMessageQueueNotRetrieved(mq, msg_ptr);
+    return osErrorResource;
+  }
+
+  return osOK;
+}
+
+
+//  ==== Public API ====
+
+/// Create and Initialize a Message Queue object.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
+  EvrRtxMessageQueueNew(msg_count, msg_size, attr);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMessageQueueError(NULL, osErrorISR);
+    return NULL;
+  }
+  return __svcMessageQueueNew(msg_count, msg_size, attr);
+}
+
+/// Get name of a Message Queue object.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMessageQueueGetName(mq_id, NULL);
+    return NULL;
+  }
+  return __svcMessageQueueGetName(mq_id);
+}
+
+/// Put a Message into a Queue or timeout if Queue is full.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
+  EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
+  } else {
+    return  __svcMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
+  }
+}
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
+  EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
+  } else {
+    return  __svcMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
+  }
+}
+
+/// Get maximum number of messages in a Message Queue.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMessageQueueGetCapacity(mq_id);
+  } else {
+    return  __svcMessageQueueGetCapacity(mq_id);
+  }
+}
+
+/// Get maximum message size in a Memory Pool.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMessageQueueGetMsgSize(mq_id);
+  } else {
+    return  __svcMessageQueueGetMsgSize(mq_id);
+  }
+}
+
+/// Get number of queued messages in a Message Queue.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMessageQueueGetCount(mq_id);
+  } else {
+    return  __svcMessageQueueGetCount(mq_id);
+  }
+}
+
+/// Get number of available slots for messages in a Message Queue.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxMessageQueueGetSpace(mq_id);
+  } else {
+    return  __svcMessageQueueGetSpace(mq_id);
+  }
+}
+
+/// Reset a Message Queue to initial empty state.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {
+  EvrRtxMessageQueueReset(mq_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMessageQueueError(mq_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcMessageQueueReset(mq_id);
+}
+
+/// Delete a Message Queue object.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {
+  EvrRtxMessageQueueDelete(mq_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMessageQueueError(mq_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcMessageQueueDelete(mq_id);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.c
new file mode 100755
index 0000000..4a274f8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_mutex.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Mutex functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Library functions ====
+
+/// Release Mutex list when owner Thread terminates.
+/// \param[in]  mutex           mutex object.
+/// \return 1 - success, 0 - failure.
+void osRtxMutexOwnerRelease (os_mutex_t *mutex_list) {
+  os_mutex_t  *mutex;
+  os_thread_t *thread;
+
+  mutex = mutex_list;
+  while (mutex) {
+    mutex_list = mutex->owner_next;
+    // Check if Mutex is Robust
+    if (mutex->attr & osMutexRobust) {
+      // Clear Lock counter
+      mutex->lock = 0U;
+      EvrRtxMutexReleased(mutex, 0U);
+      // Check if Thread is waiting for a Mutex
+      if (mutex->thread_list != NULL) {
+        // Wakeup waiting Thread with highest Priority
+        thread = osRtxThreadListGet((os_object_t*)mutex);
+        osRtxThreadWaitExit(thread, (uint32_t)osOK, false);
+        // Thread is the new Mutex owner
+        mutex->owner_thread = thread;
+        mutex->owner_next   = thread->mutex_list;
+        mutex->owner_prev   = NULL;
+        thread->mutex_list  = mutex;
+        mutex->lock = 1U;
+        EvrRtxMutexAcquired(mutex, 1U);
+      }
+    }
+    mutex = mutex_list;
+  }
+}
+
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_1M(MutexNew,      osMutexId_t,  const osMutexAttr_t *)
+SVC0_1 (MutexGetName,  const char *, osMutexId_t)
+SVC0_2 (MutexAcquire,  osStatus_t,   osMutexId_t, uint32_t)
+SVC0_1 (MutexRelease,  osStatus_t,   osMutexId_t)
+SVC0_1 (MutexGetOwner, osThreadId_t, osMutexId_t)
+SVC0_1 (MutexDelete,   osStatus_t,   osMutexId_t)
+
+/// Create and Initialize a Mutex object.
+/// \note API identical to osMutexNew
+osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr) {
+  os_mutex_t *mutex;
+  uint32_t    attr_bits;
+  uint8_t     flags;
+  const char *name;
+
+  // Process attributes
+  if (attr != NULL) {
+    name      = attr->name;
+    attr_bits = attr->attr_bits;
+    mutex     = attr->cb_mem;
+    if (mutex != NULL) {
+      if (((uint32_t)mutex & 3U) || (attr->cb_size < sizeof(os_mutex_t))) {
+        EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    } else {
+      if (attr->cb_size != 0U) {
+        EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    }
+  } else {
+    name      = NULL;
+    attr_bits = 0U;
+    mutex     = NULL;
+  }
+
+  // Allocate object memory if not provided
+  if (mutex == NULL) {
+    if (osRtxInfo.mpi.mutex != NULL) {
+      mutex = osRtxMemoryPoolAlloc(osRtxInfo.mpi.mutex);
+    } else {
+      mutex = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_mutex_t), 1U);
+    }
+    if (mutex == NULL) {
+      EvrRtxMutexError(NULL, osErrorNoMemory);
+      return NULL;
+    }
+    flags = osRtxFlagSystemObject;
+  } else {
+    flags = 0U;
+  }
+
+  // Initialize control block
+  mutex->id           = osRtxIdMutex;
+  mutex->state        = osRtxObjectActive;
+  mutex->flags        = flags;
+  mutex->attr         = (uint8_t)attr_bits;
+  mutex->name         = name;
+  mutex->thread_list  = NULL;
+  mutex->owner_thread = NULL;
+  mutex->owner_prev   = NULL;
+  mutex->owner_next   = NULL;
+  mutex->lock         = 0U;
+
+  EvrRtxMutexCreated(mutex);
+
+  return mutex;
+}
+
+/// Get name of a Mutex object.
+/// \note API identical to osMutexGetName
+const char *svcRtxMutexGetName (osMutexId_t mutex_id) {
+  os_mutex_t *mutex = (os_mutex_t *)mutex_id;
+
+  // Check parameters
+  if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) {
+    EvrRtxMutexGetName(mutex, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (mutex->state == osRtxObjectInactive) {
+    EvrRtxMutexGetName(mutex, NULL);
+    return NULL;
+  }
+
+  EvrRtxMutexGetName(mutex, mutex->name);
+
+  return mutex->name;
+}
+
+/// Acquire a Mutex or timeout if it is locked.
+/// \note API identical to osMutexAcquire
+osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
+  os_mutex_t  *mutex = (os_mutex_t *)mutex_id;
+  os_thread_t *running_thread;
+
+  running_thread = osRtxThreadGetRunning();
+  if (running_thread == NULL) {
+    EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning);
+    return osError;
+  }
+
+  // Check parameters
+  if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) {
+    EvrRtxMutexError(mutex, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mutex->state == osRtxObjectInactive) {
+    EvrRtxMutexError(mutex, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Check if Mutex is not locked
+  if (mutex->lock == 0U) {
+    // Acquire Mutex
+    mutex->owner_thread = running_thread;
+    mutex->owner_next   = running_thread->mutex_list;
+    mutex->owner_prev   = NULL;
+    if (running_thread->mutex_list != NULL) {
+        running_thread->mutex_list->owner_prev = mutex;
+    }
+    running_thread->mutex_list = mutex;
+    mutex->lock = 1U;
+    EvrRtxMutexAcquired(mutex, mutex->lock);
+    return osOK;
+  }
+
+  // Check if Mutex is recursive and running Thread is the owner
+  if ((mutex->attr & osMutexRecursive) && (mutex->owner_thread == running_thread)) {
+    // Increment lock counter
+    if (mutex->lock == osRtxMutexLockLimit) {
+      EvrRtxMutexError(mutex, osRtxErrorMutexLockLimit);
+      return osErrorResource;
+    }
+    mutex->lock++;
+    EvrRtxMutexAcquired(mutex, mutex->lock);
+    return osOK;
+  }
+
+  // Check if timeout is specified
+  if (timeout != 0U) {
+    // Check if Priority inheritance protocol is enabled
+    if (mutex->attr & osMutexPrioInherit) {
+      // Raise priority of owner Thread if lower than priority of running Thread
+      if (mutex->owner_thread->priority < running_thread->priority) {
+        mutex->owner_thread->priority = running_thread->priority;
+        osRtxThreadListSort(mutex->owner_thread);
+      }
+    }
+    EvrRtxMutexAcquirePending(mutex, timeout);
+    // Suspend current Thread
+    osRtxThreadListPut((os_object_t*)mutex, running_thread);
+    osRtxThreadWaitEnter(osRtxThreadWaitingMutex, timeout);
+    return osErrorTimeout;
+  }
+
+  // Mutex was not acquired
+  EvrRtxMutexNotAcquired(mutex);
+
+  return osErrorResource;
+}
+
+/// Release a Mutex that was acquired by osMutexAcquire.
+/// \note API identical to osMutexRelease
+osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) {
+  os_mutex_t  *mutex = (os_mutex_t *)mutex_id;
+  os_mutex_t  *mutex0;
+  os_thread_t *thread;
+  os_thread_t *running_thread;
+  int8_t       priority;
+
+  running_thread = osRtxThreadGetRunning();
+  if (running_thread == NULL) {
+    EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning);
+    return osError;
+  }
+
+  // Check parameters
+  if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) {
+    EvrRtxMutexError(mutex, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mutex->state == osRtxObjectInactive) {
+    EvrRtxMutexError(mutex, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Check if running Thread is not the owner
+  if (mutex->owner_thread != running_thread) {
+    EvrRtxMutexError(mutex, osRtxErrorMutexNotOwned);
+    return osErrorResource;
+  }
+
+  // Check if Mutex is not locked
+  if (mutex->lock == 0U) {
+    EvrRtxMutexError(mutex, osRtxErrorMutexNotLocked);
+    return osErrorResource;
+  }
+
+  // Decrement Lock counter
+  mutex->lock--;
+  EvrRtxMutexReleased(mutex, mutex->lock);
+
+  // Check Lock counter
+  if (mutex->lock != 0U) {
+    return osOK;
+  }
+
+  // Remove Mutex from Thread owner list
+  if (mutex->owner_next != NULL) {
+    mutex->owner_next->owner_prev = mutex->owner_prev;
+  }
+  if (mutex->owner_prev != NULL) {
+    mutex->owner_prev->owner_next = mutex->owner_next;
+  } else {
+    running_thread->mutex_list = mutex->owner_next;
+  }
+
+  // Restore running Thread priority
+  if (mutex->attr & osMutexPrioInherit) {
+    priority = running_thread->priority_base;
+    mutex0   = running_thread->mutex_list;
+    while (mutex0) {
+      // Mutexes owned by running Thread
+      if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) {
+        // Higher priority Thread is waiting for Mutex
+        priority = mutex0->thread_list->priority;
+      }
+      mutex0 = mutex0->owner_next;
+    }
+    running_thread->priority = priority;
+  }
+
+  // Check if Thread is waiting for a Mutex
+  if (mutex->thread_list != NULL) {
+    // Wakeup waiting Thread with highest Priority
+    thread = osRtxThreadListGet((os_object_t*)mutex);
+    osRtxThreadWaitExit(thread, (uint32_t)osOK, false);
+    // Thread is the new Mutex owner
+    mutex->owner_thread = thread;
+    mutex->owner_next   = thread->mutex_list;
+    mutex->owner_prev   = NULL;
+    thread->mutex_list  = mutex;
+    mutex->lock = 1U;
+    EvrRtxMutexAcquired(mutex, 1U);
+  }
+
+  osRtxThreadDispatch(NULL);
+
+  return osOK;
+}
+
+/// Get Thread which owns a Mutex object.
+/// \note API identical to osMutexGetOwner
+osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id) {
+  os_mutex_t *mutex = (os_mutex_t *)mutex_id;
+
+  // Check parameters
+  if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) {
+    EvrRtxMutexGetOwner(mutex, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (mutex->state == osRtxObjectInactive) {
+    EvrRtxMutexGetOwner(mutex, NULL);
+    return NULL;
+  }
+
+  // Check if Mutex is not locked
+  if (mutex->lock == 0U) {
+    EvrRtxMutexGetOwner(mutex, NULL);
+    return NULL;
+  }
+
+  EvrRtxMutexGetOwner(mutex, mutex->owner_thread);
+
+  return mutex->owner_thread;
+}
+
+/// Delete a Mutex object.
+/// \note API identical to osMutexDelete
+osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) {
+  os_mutex_t  *mutex = (os_mutex_t *)mutex_id;
+  os_mutex_t  *mutex0;
+  os_thread_t *thread;
+  int8_t       priority;
+
+  // Check parameters
+  if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) {
+    EvrRtxMutexError(mutex, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (mutex->state == osRtxObjectInactive) {
+    EvrRtxMutexError(mutex, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Mark object as inactive
+  mutex->state = osRtxObjectInactive;
+
+  // Check if Mutex is locked
+  if (mutex->lock != 0U) {
+
+    thread = mutex->owner_thread;
+
+    // Remove Mutex from Thread owner list
+    if (mutex->owner_next != NULL) {
+      mutex->owner_next->owner_prev = mutex->owner_prev;
+    }
+    if (mutex->owner_prev != NULL) {
+      mutex->owner_prev->owner_next = mutex->owner_next;
+    } else {
+      thread->mutex_list = mutex->owner_next;
+    }
+
+    // Restore owner Thread priority
+    if (mutex->attr & osMutexPrioInherit) {
+      priority = thread->priority_base;
+      mutex0   = thread->mutex_list;
+      while (mutex0) {
+        // Mutexes owned by running Thread
+        if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) {
+          // Higher priority Thread is waiting for Mutex
+          priority = mutex0->thread_list->priority;
+        }
+        mutex0 = mutex0->owner_next;
+      }
+      if (thread->priority != priority) {
+        thread->priority = priority;
+        osRtxThreadListSort(thread);
+      }
+    }
+
+    // Unblock waiting threads
+    if (mutex->thread_list != NULL) {
+      do {
+        thread = osRtxThreadListGet((os_object_t*)mutex);
+        osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false);
+      } while (mutex->thread_list != NULL);
+    }
+
+    osRtxThreadDispatch(NULL);
+  }
+
+  // Free object memory
+  if (mutex->flags & osRtxFlagSystemObject) {
+    if (osRtxInfo.mpi.mutex != NULL) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.common, mutex);
+    }
+  }
+
+  EvrRtxMutexDestroyed(mutex);
+
+  return osOK;
+}
+
+
+//  ==== Public API ====
+
+/// Create and Initialize a Mutex object.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
+  EvrRtxMutexNew(attr);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMutexError(NULL, osErrorISR);
+    return NULL;
+  }
+  return __svcMutexNew(attr);
+}
+
+/// Get name of a Mutex object.
+const char *osMutexGetName (osMutexId_t mutex_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMutexGetName(mutex_id, NULL);
+    return NULL;
+  }
+  return __svcMutexGetName(mutex_id);
+}
+
+/// Acquire a Mutex or timeout if it is locked.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
+  EvrRtxMutexAcquire(mutex_id, timeout);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMutexError(mutex_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcMutexAcquire(mutex_id, timeout);
+}
+
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+osStatus_t osMutexRelease (osMutexId_t mutex_id) {
+  EvrRtxMutexRelease(mutex_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMutexError(mutex_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcMutexRelease(mutex_id);
+}
+
+/// Get Thread which owns a Mutex object.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMutexGetOwner(mutex_id, NULL);
+    return NULL;
+  }
+  return __svcMutexGetOwner(mutex_id);
+}
+
+/// Delete a Mutex object.
+osStatus_t osMutexDelete (osMutexId_t mutex_id) {
+  EvrRtxMutexDelete(mutex_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxMutexError(mutex_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcMutexDelete(mutex_id);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h
new file mode 100755
index 0000000..fbc243c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_os.h
@@ -0,0 +1,479 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX OS definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#ifndef RTX_OS_H_
+#define RTX_OS_H_
+ 
+#include <stdint.h>
+#include <stddef.h>
+#include "cmsis_os2.h"
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+/// Kernel Information
+#define osRtxVersionAPI      20010000   ///< API version (2.1.0)
+#define osRtxVersionKernel   50010001   ///< Kernel version (5.1.1)
+#define osRtxKernelId     "RTX V5.1.1"  ///< Kernel identification string
+ 
+ 
+//  ==== Common definitions ====
+ 
+/// Object Identifier definitions
+#define osRtxIdInvalid          0x00U
+#define osRtxIdThread           0x01U
+#define osRtxIdTimer            0x02U
+#define osRtxIdEventFlags       0x03U
+#define osRtxIdMutex            0x04U
+#define osRtxIdSemaphore        0x05U
+#define osRtxIdMemoryPool       0x06U
+#define osRtxIdMessage          0x07U
+#define osRtxIdMessageQueue     0x08U
+ 
+/// Object State definitions (except for Threads and Timers)
+#define osRtxObjectInactive     0x00U
+#define osRtxObjectActive       0x01U
+ 
+/// Object Flags definitions
+#define osRtxFlagSystemObject   0x01U
+#define osRtxFlagSystemMemory   0x02U
+ 
+ 
+//  ==== Kernel definitions ====
+ 
+/// Kernel State definitions
+#define osRtxKernelInactive             ((uint8_t)osKernelInactive)
+#define osRtxKernelReady                ((uint8_t)osKernelReady)
+#define osRtxKernelRunning              ((uint8_t)osKernelRunning)
+#define osRtxKernelLocked               ((uint8_t)osKernelLocked)
+#define osRtxKernelSuspended            ((uint8_t)osKernelSuspended)
+ 
+ 
+//  ==== Thread definitions ====
+ 
+/// Thread State definitions (extending osThreadState)
+#define osRtxThreadStateMask            0x0FU
+ 
+#define osRtxThreadInactive             ((uint8_t)osThreadInactive)
+#define osRtxThreadReady                ((uint8_t)osThreadReady)
+#define osRtxThreadRunning              ((uint8_t)osThreadRunning)
+#define osRtxThreadBlocked              ((uint8_t)osThreadBlocked)
+#define osRtxThreadTerminated           ((uint8_t)osThreadTerminated)
+ 
+#define osRtxThreadWaitingDelay         (osRtxThreadBlocked | 0x10U)
+#define osRtxThreadWaitingJoin          (osRtxThreadBlocked | 0x20U)
+#define osRtxThreadWaitingThreadFlags   (osRtxThreadBlocked | 0x30U) 
+#define osRtxThreadWaitingEventFlags    (osRtxThreadBlocked | 0x40U) 
+#define osRtxThreadWaitingMutex         (osRtxThreadBlocked | 0x50U)
+#define osRtxThreadWaitingSemaphore     (osRtxThreadBlocked | 0x60U)
+#define osRtxThreadWaitingMemoryPool    (osRtxThreadBlocked | 0x70U)
+#define osRtxThreadWaitingMessageGet    (osRtxThreadBlocked | 0x80U)
+#define osRtxThreadWaitingMessagePut    (osRtxThreadBlocked | 0x90U)
+ 
+/// Thread Flags definitions
+#define osRtxThreadFlagDefStack 0x10U   ///< Default Stack flag
+ 
+/// Stack Marker definitions
+#define osRtxStackMagicWord     0xE25A2EA5U ///< Stack Magic Word (Stack Base)
+#define osRtxStackFillPattern   0xCCCCCCCCU ///< Stack Fill Pattern 
+ 
+/// Thread Control Block
+typedef struct osRtxThread_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                        attr;  ///< Object Attributes
+  const char                    *name;  ///< Object Name
+  struct osRtxThread_s   *thread_next;  ///< Link pointer to next Thread in Object list
+  struct osRtxThread_s   *thread_prev;  ///< Link pointer to previous Thread in Object list
+  struct osRtxThread_s    *delay_next;  ///< Link pointer to next Thread in Delay list
+  struct osRtxThread_s    *delay_prev;  ///< Link pointer to previous Thread in Delay list
+  struct osRtxThread_s   *thread_join;  ///< Thread waiting to Join
+  uint32_t                      delay;  ///< Delay Time
+  int8_t                     priority;  ///< Thread Priority
+  int8_t                priority_base;  ///< Base Priority
+  uint8_t                 stack_frame;  ///< Stack Frame (EXC_RETURN[7..0])
+  uint8_t               flags_options;  ///< Thread/Event Flags Options
+  uint32_t                 wait_flags;  ///< Waiting Thread/Event Flags
+  uint32_t               thread_flags;  ///< Thread Flags
+  struct osRtxMutex_s     *mutex_list;  ///< Link pointer to list of owned Mutexes
+  void                     *stack_mem;  ///< Stack Memory
+  uint32_t                 stack_size;  ///< Stack Size
+  uint32_t                         sp;  ///< Current Stack Pointer
+  uint32_t                thread_addr;  ///< Thread entry address
+  uint32_t                  tz_memory;  ///< TrustZone Memory Identifier
+  void                       *context;  ///< Context for OsEventObserver objects
+} osRtxThread_t;
+ 
+ 
+//  ==== Timer definitions ====
+ 
+/// Timer State definitions
+#define osRtxTimerInactive      0x00U   ///< Timer Inactive
+#define osRtxTimerStopped       0x01U   ///< Timer Stopped
+#define osRtxTimerRunning       0x02U   ///< Timer Running
+ 
+/// Timer Type definitions
+#define osRtxTimerPeriodic      ((uint8_t)osTimerPeriodic)
+ 
+/// Timer Function Information
+typedef struct {
+  void                            *fp;  ///< Function Pointer
+  void                           *arg;  ///< Function Argument
+} osRtxTimerFinfo_t;
+ 
+/// Timer Control Block
+typedef struct osRtxTimer_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                        type;  ///< Timer Type (Periodic/One-shot)
+  const char                    *name;  ///< Object Name
+  struct osRtxTimer_s           *prev;  ///< Pointer to previous active Timer
+  struct osRtxTimer_s           *next;  ///< Pointer to next active Timer
+  uint32_t                       tick;  ///< Timer current Tick
+  uint32_t                       load;  ///< Timer Load value
+  osRtxTimerFinfo_t             finfo;  ///< Timer Function Info
+} osRtxTimer_t;
+ 
+ 
+//  ==== Event Flags definitions ====
+ 
+/// Event Flags Control Block
+typedef struct osRtxEventFlags_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                    reserved;
+  const char                    *name;  ///< Object Name
+  osRtxThread_t          *thread_list;  ///< Waiting Threads List
+  uint32_t                event_flags;  ///< Event Flags
+} osRtxEventFlags_t;
+ 
+ 
+//  ==== Mutex definitions ====
+ 
+/// Mutex Control Block
+typedef struct osRtxMutex_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                        attr;  ///< Object Attributes
+  const char                    *name;  ///< Object Name
+  osRtxThread_t          *thread_list;  ///< Waiting Threads List
+  osRtxThread_t         *owner_thread;  ///< Owner Thread
+  struct osRtxMutex_s     *owner_prev;  ///< Pointer to previous owned Mutex
+  struct osRtxMutex_s     *owner_next;  ///< Pointer to next owned Mutex
+  uint8_t                        lock;  ///< Lock counter
+  uint8_t                  padding[3];
+} osRtxMutex_t;
+ 
+ 
+//  ==== Semaphore definitions ====
+ 
+/// Semaphore Control Block
+typedef struct osRtxSemaphore_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                    reserved;
+  const char                    *name;  ///< Object Name
+  osRtxThread_t          *thread_list;  ///< Waiting Threads List
+  uint16_t                     tokens;  ///< Current number of tokens
+  uint16_t                 max_tokens;  ///< Maximum number of tokens
+} osRtxSemaphore_t;
+ 
+ 
+//  ==== Memory Pool definitions ====
+ 
+/// Memory Pool Information
+typedef struct osRtxMpInfo_s {
+  uint32_t                 max_blocks;  ///< Maximum number of Blocks
+  uint32_t                used_blocks;  ///< Number of used Blocks
+  uint32_t                 block_size;  ///< Block Size
+  void                    *block_base;  ///< Block Memory Base Address
+  void                     *block_lim;  ///< Block Memory Limit Address
+  void                    *block_free;  ///< First free Block Address
+} osRtxMpInfo_t;
+ 
+/// Memory Pool Control Block
+typedef struct osRtxMemoryPool_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                    reserved;
+  const char                    *name;  ///< Object Name
+  osRtxThread_t          *thread_list;  ///< Waiting Threads List
+  osRtxMpInfo_t               mp_info;  ///< Memory Pool Info
+} osRtxMemoryPool_t;
+ 
+ 
+//  ==== Message Queue definitions ====
+ 
+/// Message Control Block
+typedef struct osRtxMessage_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                    priority;  ///< Message Priority
+  struct osRtxMessage_s         *prev;  ///< Pointer to previous Message
+  struct osRtxMessage_s         *next;  ///< Pointer to next Message
+} osRtxMessage_t;
+ 
+/// Message Queue Control Block
+typedef struct osRtxMessageQueue_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                    reserved;
+  const char                    *name;  ///< Object Name
+  osRtxThread_t          *thread_list;  ///< Waiting Threads List
+  osRtxMpInfo_t               mp_info;  ///< Memory Pool Info
+  uint32_t                   msg_size;  ///< Message Size
+  uint32_t                  msg_count;  ///< Number of queued Messages
+  osRtxMessage_t           *msg_first;  ///< Pointer to first Message
+  osRtxMessage_t            *msg_last;  ///< Pointer to last Message
+} osRtxMessageQueue_t;
+ 
+ 
+//  ==== Generic Object definitions ====
+ 
+/// Generic Object Control Block
+typedef struct osRtxObject_s {
+  uint8_t                          id;  ///< Object Identifier
+  uint8_t                       state;  ///< Object State
+  uint8_t                       flags;  ///< Object Flags
+  uint8_t                    reserved;
+  const char                    *name;  ///< Object Name
+  osRtxThread_t          *thread_list;  ///< Threads List
+} osRtxObject_t;
+ 
+ 
+//  ==== OS Runtime Information definitions ====
+ 
+/// OS Runtime Information structure
+typedef struct {
+  const char                   *os_id;  ///< OS Identification
+  uint32_t                    version;  ///< OS Version
+  struct {                              ///< Kernel Info
+    uint8_t                     state;  ///< State
+    volatile uint8_t          blocked;  ///< Blocked
+    uint8_t                   pendISR;  ///< Pending ISR (SV and SysTick)
+    uint8_t                    pendSV;  ///< Pending SV
+    uint32_t                 sys_freq;  ///< System Frequency
+    uint64_t                     tick;  ///< Tick counter
+  } kernel;
+  int32_t                   tick_irqn;  ///< Tick Timer IRQ Number
+  struct {                              ///< Thread Info
+    struct {                            ///< Thread Run Info
+      osRtxThread_t             *curr;  ///< Current running Thread
+      osRtxThread_t             *next;  ///< Next Thread to Run
+    } run;
+    volatile osRtxObject_t      ready;  ///< Ready List Object
+    osRtxThread_t               *idle;  ///< Idle Thread
+    osRtxThread_t         *delay_list;  ///< Delay List
+    osRtxThread_t          *wait_list;  ///< Wait List (no Timeout)
+    osRtxThread_t     *terminate_list;  ///< Terminate Thread List
+    struct {                            ///< Thread Round Robin Info
+      osRtxThread_t           *thread;  ///< Round Robin Thread
+      uint32_t                   tick;  ///< Round Robin Time Tick
+      uint32_t                timeout;  ///< Round Robin Timeout
+    } robin;
+  } thread;
+  struct {                              ///< Timer Info
+    osRtxTimer_t                *list;  ///< Active Timer List
+    osRtxThread_t             *thread;  ///< Timer Thread
+    osRtxMessageQueue_t           *mq;  ///< Timer Message Queue
+    void                (*tick)(void);  ///< Timer Tick Function
+  } timer;
+  struct {                              ///< ISR Post Processing Queue
+    uint16_t                      max;  ///< Maximum Items
+    uint16_t                      cnt;  ///< Item Count
+    uint16_t                       in;  ///< Incoming Item Index
+    uint16_t                      out;  ///< Outgoing Item Index
+    void                       **data;  ///< Queue Data
+  } isr_queue;
+  struct {                                      ///< ISR Post Processing functions
+    void          (*thread)(osRtxThread_t*);    ///< Thread Post Processing function
+    void (*event_flags)(osRtxEventFlags_t*);    ///< Event Flags Post Processing function
+    void    (*semaphore)(osRtxSemaphore_t*);    ///< Semaphore Post Processing function
+    void (*memory_pool)(osRtxMemoryPool_t*);    ///< Memory Pool Post Processing function
+    void  (*message_queue)(osRtxMessage_t*);    ///< Message Queue Post Processing function
+  } post_process;
+  struct {                              ///< Memory Pools (Variable Block Size)
+    void                       *stack;  ///< Stack Memory
+    void                     *mp_data;  ///< Memory Pool Data Memory
+    void                     *mq_data;  ///< Message Queue Data Memory
+    void                      *common;  ///< Common Memory
+  } mem;
+  struct {                              ///< Memory Pools (Fixed Block Size)
+    osRtxMpInfo_t              *stack;  ///< Stack for Threads
+    osRtxMpInfo_t             *thread;  ///< Thread Control Blocks
+    osRtxMpInfo_t              *timer;  ///< Timer Control Blocks
+    osRtxMpInfo_t        *event_flags;  ///< Event Flags Control Blocks
+    osRtxMpInfo_t              *mutex;  ///< Mutex Control Blocks
+    osRtxMpInfo_t          *semaphore;  ///< Semaphore Control Blocks
+    osRtxMpInfo_t        *memory_pool;  ///< Memory Pool Control Blocks
+    osRtxMpInfo_t      *message_queue;  ///< Message Queue Control Blocks
+  } mpi;
+  uint32_t                    padding;
+} osRtxInfo_t;
+ 
+extern osRtxInfo_t osRtxInfo;           ///< OS Runtime Information
+ 
+ 
+//  ==== OS API definitions ====
+ 
+/// Object Limits definitions
+#define osRtxThreadFlagsLimit    31U    ///< number of Thread Flags available per thread
+#define osRtxEventFlagsLimit     31U    ///< number of Event Flags available per object
+#define osRtxMutexLockLimit      255U   ///< maximum number of recursive mutex locks
+#define osRtxSemaphoreTokenLimit 65535U ///< maximum number of tokens per semaphore
+ 
+/// Control Block sizes
+#define osRtxThreadCbSize        sizeof(osRtxThread_t)
+#define osRtxTimerCbSize         sizeof(osRtxTimer_t)
+#define osRtxEventFlagsCbSize    sizeof(osRtxEventFlags_t)
+#define osRtxMutexCbSize         sizeof(osRtxMutex_t)
+#define osRtxSemaphoreCbSize     sizeof(osRtxSemaphore_t)
+#define osRtxMemoryPoolCbSize    sizeof(osRtxMemoryPool_t)
+#define osRtxMessageQueueCbSize  sizeof(osRtxMessageQueue_t)
+ 
+/// Memory size in bytes for Memory Pool storage.
+/// \param         block_count   maximum number of memory blocks in memory pool.
+/// \param         block_size    memory block size in bytes.
+#define osRtxMemoryPoolMemSize(block_count, block_size) \
+  (4*(block_count)*(((block_size)+3)/4))
+ 
+/// Memory size in bytes for Message Queue storage.
+/// \param         msg_count     maximum number of messages in queue.
+/// \param         msg_size      maximum message size in bytes.
+#define osRtxMessageQueueMemSize(msg_count, msg_size) \
+  (4*(msg_count)*(3+(((msg_size)+3)/4)))
+ 
+ 
+//  ==== OS External Functions ====
+ 
+/// OS Error Codes
+#define osRtxErrorStackUnderflow        1U
+#define osRtxErrorISRQueueOverflow      2U
+#define osRtxErrorTimerQueueOverflow    3U
+#define osRtxErrorClibSpace             4U
+#define osRtxErrorClibMutex             5U
+ 
+/// OS Error Callback function
+extern uint32_t osRtxErrorNotify (uint32_t code, void *object_id);
+ 
+/// OS Idle Thread
+extern void osRtxIdleThread (void *argument);
+ 
+/// OS Exception handlers
+extern void SVC_Handler     (void);
+extern void PendSV_Handler  (void);
+extern void SysTick_Handler (void);
+ 
+ 
+/// OS System Timer functions (default implementation uses SysTick)
+ 
+/// Setup System Timer.
+/// \return system timer IRQ number.
+extern int32_t osRtxSysTimerSetup (void);
+ 
+/// Enable System Timer.
+extern void osRtxSysTimerEnable (void);
+ 
+/// Disable System Timer.
+extern void osRtxSysTimerDisable (void);
+ 
+/// Acknowledge System Timer IRQ.
+extern void osRtxSysTimerAckIRQ (void);
+ 
+/// Get System Timer count.
+/// \return system timer count.
+extern uint32_t osRtxSysTimerGetCount (void);
+ 
+/// Get System Timer frequency.
+/// \return system timer frequency.
+extern uint32_t osRtxSysTimerGetFreq (void);
+ 
+ 
+//  ==== OS External Configuration ====
+ 
+/// OS Configuration flags
+#define osRtxConfigPrivilegedMode   (1UL<<0)    ///< Threads in Privileged mode
+#define osRtxConfigStackCheck       (1UL<<1)    ///< Stack overrun checking
+#define osRtxConfigStackWatermark   (1UL<<2)    ///< Stack usage Watermark
+ 
+/// OS Configuration structure
+typedef struct {
+  uint32_t                             flags;   ///< OS Configuration Flags
+  uint32_t                         tick_freq;   ///< Kernel Tick Frequency
+  uint32_t                     robin_timeout;   ///< Round Robin Timeout Tick
+  struct {                                      ///< ISR Post Processing Queue
+    void                              **data;   ///< Queue Data
+    uint16_t                             max;   ///< Maximum Items
+    uint16_t                         padding;
+  } isr_queue;
+  struct {                                      ///< Memory Pools (Variable Block Size)
+    void                         *stack_addr;   ///< Stack Memory Address
+    uint32_t                      stack_size;   ///< Stack Memory Size
+    void                       *mp_data_addr;   ///< Memory Pool Memory Address
+    uint32_t                    mp_data_size;   ///< Memory Pool Memory Size
+    void                       *mq_data_addr;   ///< Message Queue Data Memory Address
+    uint32_t                    mq_data_size;   ///< Message Queue Data Memory Size
+    void                        *common_addr;   ///< Common Memory Address
+    uint32_t                     common_size;   ///< Common Memory Size
+  } mem;
+  struct {                                      ///< Memory Pools (Fixed Block Size)
+    osRtxMpInfo_t                     *stack;   ///< Stack for Threads
+    osRtxMpInfo_t                    *thread;   ///< Thread Control Blocks
+    osRtxMpInfo_t                     *timer;   ///< Timer Control Blocks
+    osRtxMpInfo_t               *event_flags;   ///< Event Flags Control Blocks
+    osRtxMpInfo_t                     *mutex;   ///< Mutex Control Blocks
+    osRtxMpInfo_t                 *semaphore;   ///< Semaphore Control Blocks
+    osRtxMpInfo_t               *memory_pool;   ///< Memory Pool Control Blocks
+    osRtxMpInfo_t             *message_queue;   ///< Message Queue Control Blocks
+  } mpi;
+  uint32_t                 thread_stack_size;   ///< Default Thread Stack Size
+  const 
+  osThreadAttr_t           *idle_thread_attr;   ///< Idle Thread Attributes
+  const
+  osThreadAttr_t          *timer_thread_attr;   ///< Timer Thread Attributes
+  const
+  osMessageQueueAttr_t        *timer_mq_attr;   ///< Timer Message Queue Attributes
+  uint32_t                     timer_mq_mcnt;   ///< Timer Message Queue maximum Messages
+} osRtxConfig_t;
+ 
+extern const osRtxConfig_t osRtxConfig;         ///< OS Configuration
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // RTX_OS_H_
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.c
new file mode 100755
index 0000000..f0a3c40
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.c
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Semaphore functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Helper functions ====
+
+/// Decrement Semaphore tokens.
+/// \param[in]  semaphore       semaphore object.
+/// \return 1 - success, 0 - failure.
+static uint32_t SemaphoreTokenDecrement (os_semaphore_t *semaphore) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  uint32_t ret;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  if (semaphore->tokens != 0U) {
+    semaphore->tokens--;
+    ret = 1U;
+  } else {
+    ret = 0U;
+  }
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  if (atomic_dec16_nz(&semaphore->tokens) != 0U) {
+    ret = 1U;
+  } else {
+    ret = 0U;
+  }
+#endif
+
+  return ret;
+}
+
+/// Increment Semaphore tokens.
+/// \param[in]  semaphore       semaphore object.
+/// \return 1 - success, 0 - failure.
+static uint32_t SemaphoreTokenIncrement (os_semaphore_t *semaphore) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  uint32_t ret;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  if (semaphore->tokens < semaphore->max_tokens) {
+    semaphore->tokens++;
+    ret = 1U;
+  } else {
+    ret = 0U;
+  }
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  if (atomic_inc16_lt(&semaphore->tokens, semaphore->max_tokens) < semaphore->max_tokens) {
+    ret = 1U;
+  } else {
+    ret = 0U;
+  }
+#endif
+
+  return ret;
+}
+
+
+//  ==== Library functions ====
+
+/// Semaphore post ISR processing.
+/// \param[in]  semaphore       semaphore object.
+void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) {
+  os_thread_t *thread;
+
+  if (semaphore->state == osRtxObjectInactive) {
+    return;
+  }
+
+  // Check if Thread is waiting for a token
+  if (semaphore->thread_list != NULL) {
+    // Try to acquire token
+    if (SemaphoreTokenDecrement(semaphore) != 0U) {
+      // Wakeup waiting Thread with highest Priority
+      thread = osRtxThreadListGet((os_object_t*)semaphore);
+      osRtxThreadWaitExit(thread, (uint32_t)osOK, false);
+      EvrRtxSemaphoreAcquired(semaphore);
+    }
+  }
+}
+
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_3M(SemaphoreNew,      osSemaphoreId_t, uint32_t, uint32_t, const osSemaphoreAttr_t *)
+SVC0_1 (SemaphoreGetName,  const char *,    osSemaphoreId_t)
+SVC0_2 (SemaphoreAcquire,  osStatus_t,      osSemaphoreId_t, uint32_t)
+SVC0_1 (SemaphoreRelease,  osStatus_t,      osSemaphoreId_t)
+SVC0_1 (SemaphoreGetCount, uint32_t,        osSemaphoreId_t)
+SVC0_1 (SemaphoreDelete,   osStatus_t,      osSemaphoreId_t)
+
+/// Create and Initialize a Semaphore object.
+/// \note API identical to osSemaphoreNew
+osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
+  os_semaphore_t *semaphore;
+  uint8_t         flags;
+  const char     *name;
+
+  // Check parameters
+  if ((max_count == 0U) || (max_count > osRtxSemaphoreTokenLimit) || (initial_count > max_count)) {
+    EvrRtxSemaphoreError(NULL, osErrorParameter);
+    return NULL;
+  }
+
+  // Process attributes
+  if (attr != NULL) {
+    name      = attr->name;
+    semaphore = attr->cb_mem;
+    if (semaphore != NULL) {
+      if (((uint32_t)semaphore & 3U) || (attr->cb_size < sizeof(os_semaphore_t))) {
+        EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    } else {
+      if (attr->cb_size != 0U) {
+        EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    }
+  } else {
+    name      = NULL;
+    semaphore = NULL;
+  }
+
+  // Allocate object memory if not provided
+  if (semaphore == NULL) {
+    if (osRtxInfo.mpi.semaphore != NULL) {
+      semaphore = osRtxMemoryPoolAlloc(osRtxInfo.mpi.semaphore);
+    } else {
+      semaphore = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_semaphore_t), 1U);
+    }
+    if (semaphore == NULL) {
+      EvrRtxSemaphoreError(NULL, osErrorNoMemory);
+      return NULL;
+    }
+    flags = osRtxFlagSystemObject;
+  } else {
+    flags = 0U;
+  }
+
+  // Initialize control block
+  semaphore->id          = osRtxIdSemaphore;
+  semaphore->state       = osRtxObjectActive;
+  semaphore->flags       = flags;
+  semaphore->name        = name;
+  semaphore->thread_list = NULL;
+  semaphore->tokens      = (uint16_t)initial_count;
+  semaphore->max_tokens  = (uint16_t)max_count;
+
+  // Register post ISR processing function
+  osRtxInfo.post_process.semaphore = osRtxSemaphorePostProcess;
+
+  EvrRtxSemaphoreCreated(semaphore);
+
+  return semaphore;
+}
+
+/// Get name of a Semaphore object.
+/// \note API identical to osSemaphoreGetName
+const char *svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id) {
+  os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id;
+
+  // Check parameters
+  if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) {
+    EvrRtxSemaphoreGetName(semaphore, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (semaphore->state == osRtxObjectInactive) {
+    EvrRtxSemaphoreGetName(semaphore, NULL);
+    return NULL;
+  }
+
+  EvrRtxSemaphoreGetName(semaphore, semaphore->name);
+
+  return semaphore->name;
+}
+
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \note API identical to osSemaphoreAcquire
+osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
+  os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id;
+
+  // Check parameters
+  if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) {
+    EvrRtxSemaphoreError(semaphore, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (semaphore->state == osRtxObjectInactive) {
+    EvrRtxSemaphoreError(semaphore, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Try to acquire token
+  if (SemaphoreTokenDecrement(semaphore) == 0U) {
+    // No token available
+    if (timeout != 0U) {
+      EvrRtxSemaphoreAcquirePending(semaphore, timeout);
+      // Suspend current Thread
+      osRtxThreadListPut((os_object_t*)semaphore, osRtxThreadGetRunning());
+      osRtxThreadWaitEnter(osRtxThreadWaitingSemaphore, timeout);
+      return osErrorTimeout;
+    } else {
+      EvrRtxSemaphoreNotAcquired(semaphore);
+      return osErrorResource;
+    }
+  }
+
+  EvrRtxSemaphoreAcquired(semaphore);
+
+  return osOK;
+}
+
+/// Release a Semaphore token that was acquired by osSemaphoreAcquire.
+/// \note API identical to osSemaphoreRelease
+osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {
+  os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id;
+  os_thread_t    *thread;
+
+  // Check parameters
+  if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) {
+    EvrRtxSemaphoreError(semaphore, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (semaphore->state == osRtxObjectInactive) {
+    EvrRtxSemaphoreError(semaphore, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Check if Thread is waiting for a token
+  if (semaphore->thread_list != NULL) {
+    EvrRtxSemaphoreReleased(semaphore);
+    // Wakeup waiting Thread with highest Priority
+    thread = osRtxThreadListGet((os_object_t*)semaphore);
+    osRtxThreadWaitExit(thread, (uint32_t)osOK, true);
+    EvrRtxSemaphoreAcquired(semaphore);
+  } else {
+    // Try to release token
+    if (SemaphoreTokenIncrement(semaphore) == 0U) {
+      EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit);
+      return osErrorResource;
+    }
+    EvrRtxSemaphoreReleased(semaphore);
+  }
+
+  return osOK;
+}
+
+/// Get current Semaphore token count.
+/// \note API identical to osSemaphoreGetCount
+uint32_t svcRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
+  os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id;
+
+  // Check parameters
+  if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) {
+    EvrRtxSemaphoreGetCount(semaphore, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (semaphore->state == osRtxObjectInactive) {
+    EvrRtxSemaphoreGetCount(semaphore, 0U);
+    return 0U;
+  }
+
+  EvrRtxSemaphoreGetCount(semaphore, semaphore->tokens);
+
+  return semaphore->tokens;
+}
+
+/// Delete a Semaphore object.
+/// \note API identical to osSemaphoreDelete
+osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) {
+  os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id;
+  os_thread_t    *thread;
+
+  // Check parameters
+  if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) {
+    EvrRtxSemaphoreError(semaphore, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (semaphore->state == osRtxObjectInactive) {
+    EvrRtxSemaphoreError(semaphore, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Mark object as inactive
+  semaphore->state = osRtxObjectInactive;
+
+  // Unblock waiting threads
+  if (semaphore->thread_list != NULL) {
+    do {
+      thread = osRtxThreadListGet((os_object_t*)semaphore);
+      osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, false);
+    } while (semaphore->thread_list != NULL);
+    osRtxThreadDispatch(NULL);
+  }
+
+  // Free object memory
+  if (semaphore->flags & osRtxFlagSystemObject) {
+    if (osRtxInfo.mpi.semaphore != NULL) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.common, semaphore);
+    }
+  }
+
+  EvrRtxSemaphoreDestroyed(semaphore);
+
+  return osOK;
+}
+
+
+//  ==== ISR Calls ====
+
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \note API identical to osSemaphoreAcquire
+__STATIC_INLINE
+osStatus_t isrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
+  os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id;
+
+  // Check parameters
+  if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore) || (timeout != 0U)) {
+    EvrRtxSemaphoreError(semaphore, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (semaphore->state == osRtxObjectInactive) {
+    EvrRtxSemaphoreError(semaphore, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Try to acquire token
+  if (SemaphoreTokenDecrement(semaphore) == 0U) {
+    // No token available
+    EvrRtxSemaphoreNotAcquired(semaphore);
+    return osErrorResource;
+  }
+
+  EvrRtxSemaphoreAcquired(semaphore);
+
+  return osOK;
+}
+
+/// Release a Semaphore token that was acquired by osSemaphoreAcquire.
+/// \note API identical to osSemaphoreRelease
+__STATIC_INLINE
+osStatus_t isrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {
+  os_semaphore_t *semaphore = (os_semaphore_t *)semaphore_id;
+
+  // Check parameters
+  if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) {
+    EvrRtxSemaphoreError(semaphore, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (semaphore->state == osRtxObjectInactive) {
+    EvrRtxSemaphoreError(semaphore, osErrorResource);
+    return osErrorResource;
+  }
+
+  // Try to release token
+  if (SemaphoreTokenIncrement(semaphore) != 0U) {
+    // Register post ISR processing
+    osRtxPostProcess((os_object_t *)semaphore);
+  } else {
+    EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit);
+    return osErrorResource;
+  }
+
+  EvrRtxSemaphoreReleased(semaphore);
+
+  return osOK;
+}
+
+
+//  ==== Public API ====
+
+/// Create and Initialize a Semaphore object.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
+  EvrRtxSemaphoreNew(max_count, initial_count, attr);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxSemaphoreError(NULL, osErrorISR);
+    return NULL;
+  }
+  return __svcSemaphoreNew(max_count, initial_count, attr);
+}
+
+/// Get name of a Semaphore object.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxSemaphoreGetName(semaphore_id, NULL);
+    return NULL;
+  }
+  return __svcSemaphoreGetName(semaphore_id);
+}
+
+/// Acquire a Semaphore token or timeout if no tokens are available.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
+  EvrRtxSemaphoreAcquire(semaphore_id, timeout);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxSemaphoreAcquire(semaphore_id, timeout);
+  } else {
+    return  __svcSemaphoreAcquire(semaphore_id, timeout);
+  }
+}
+
+/// Release a Semaphore token that was acquired by osSemaphoreAcquire.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
+  EvrRtxSemaphoreRelease(semaphore_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxSemaphoreRelease(semaphore_id);
+  } else {
+    return  __svcSemaphoreRelease(semaphore_id);
+  }
+}
+
+/// Get current Semaphore token count.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return svcRtxSemaphoreGetCount(semaphore_id);
+  } else {
+    return  __svcSemaphoreGetCount(semaphore_id);
+  }
+}
+
+/// Delete a Semaphore object.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {
+  EvrRtxSemaphoreDelete(semaphore_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxSemaphoreError(semaphore_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcSemaphoreDelete(semaphore_id);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.c
new file mode 100755
index 0000000..c8715cd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_system.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       System functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Helper functions ====
+
+/// Put Object into ISR Queue.
+/// \param[in]  object          object.
+/// \return 1 - success, 0 - failure.
+static uint32_t isr_queue_put (void *object) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#else
+  uint32_t n;
+#endif
+  uint16_t max;
+  uint32_t ret;
+
+  max = osRtxInfo.isr_queue.max;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  if (osRtxInfo.isr_queue.cnt < max) {
+    osRtxInfo.isr_queue.cnt++;
+    osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.in] = object;
+    if (++osRtxInfo.isr_queue.in == max) {
+      osRtxInfo.isr_queue.in = 0U;
+    }
+    ret = 1U;
+  } else {
+    ret = 0U;
+  }
+  
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  if (atomic_inc16_lt(&osRtxInfo.isr_queue.cnt, max) < max) {
+    n = atomic_inc16_lim(&osRtxInfo.isr_queue.in, max);
+    osRtxInfo.isr_queue.data[n] = object;
+    ret = 1U;
+  } else {
+    ret = 0U;
+  }
+#endif
+
+  return ret;
+}
+
+/// Get Object from ISR Queue.
+/// \return object or NULL.
+static void *isr_queue_get (void) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#else
+  uint32_t n;
+#endif
+  uint16_t max;
+  void    *ret;
+
+  max = osRtxInfo.isr_queue.max;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  if (osRtxInfo.isr_queue.cnt != 0U) {
+    osRtxInfo.isr_queue.cnt--;
+    ret = osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.out];
+    if (++osRtxInfo.isr_queue.out == max) {
+      osRtxInfo.isr_queue.out = 0U;
+    }
+  } else {
+    ret = NULL;
+  }
+  
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  if (atomic_dec16_nz(&osRtxInfo.isr_queue.cnt) != 0U) {
+    n = atomic_inc16_lim(&osRtxInfo.isr_queue.out, max);
+    ret = osRtxInfo.isr_queue.data[n];
+  } else {
+    ret = NULL;
+  }
+#endif
+
+  return ret;
+}
+
+
+//  ==== Library Functions ====
+
+/// Tick Handler.
+void osRtxTick_Handler (void) {
+  os_thread_t *thread;
+
+  osRtxSysTimerAckIRQ();
+  osRtxInfo.kernel.tick++;
+
+  // Process Timers
+  if (osRtxInfo.timer.tick != NULL) {
+    osRtxInfo.timer.tick();
+  }
+
+  // Process Thread Delays
+  osRtxThreadDelayTick();
+
+  osRtxThreadDispatch(NULL);
+
+  // Check Round Robin timeout
+  if (osRtxInfo.thread.robin.timeout != 0U) {
+    if (osRtxInfo.thread.robin.thread != osRtxInfo.thread.run.next) {
+      // Reset Round Robin
+      osRtxInfo.thread.robin.thread = osRtxInfo.thread.run.next;
+      osRtxInfo.thread.robin.tick   = osRtxInfo.thread.robin.timeout;
+    } else {
+      if (osRtxInfo.thread.robin.tick != 0U) {
+        osRtxInfo.thread.robin.tick--;
+      }
+      if (osRtxInfo.thread.robin.tick == 0U) {
+        // Round Robin Timeout
+        if (osRtxKernelGetState() == osRtxKernelRunning) {
+          thread = osRtxInfo.thread.ready.thread_list;
+          if ((thread != NULL) && (thread->priority == osRtxInfo.thread.robin.thread->priority)) {
+            osRtxThreadListRemove(thread);
+            osRtxThreadReadyPut(osRtxInfo.thread.robin.thread);
+            osRtxThreadSwitch(thread);
+            osRtxInfo.thread.robin.thread = thread;
+            osRtxInfo.thread.robin.tick   = osRtxInfo.thread.robin.timeout;
+          }
+        }
+      }
+    }
+  }
+}
+
+/// Pending Service Call Handler.
+void osRtxPendSV_Handler (void) {
+  os_object_t *object;
+
+  for (;;) {
+    object = isr_queue_get();
+    if (object == NULL) {
+      break;
+    }
+    switch (object->id) {
+      case osRtxIdThread:
+        osRtxInfo.post_process.thread((os_thread_t *)object);
+        break;
+      case osRtxIdEventFlags:
+        osRtxInfo.post_process.event_flags((os_event_flags_t *)object);
+        break;
+      case osRtxIdSemaphore:
+        osRtxInfo.post_process.semaphore((os_semaphore_t *)object);
+        break;
+      case osRtxIdMemoryPool:
+        osRtxInfo.post_process.memory_pool((os_memory_pool_t *)object);
+        break;
+      case osRtxIdMessage:
+        osRtxInfo.post_process.message_queue((os_message_t *)object);
+        break;
+      default:
+        break;
+    }
+  }
+
+  osRtxThreadDispatch(NULL);
+}
+
+/// Register post ISR processing.
+/// \param[in]  object          generic object.
+void osRtxPostProcess (os_object_t *object) {
+
+  if (isr_queue_put(object) != 0U) {
+    if (osRtxInfo.kernel.blocked == 0U) {
+      SetPendSV();
+    } else {
+      osRtxInfo.kernel.pendSV = 1U;
+    }
+  } else {
+    osRtxErrorNotify(osRtxErrorISRQueueOverflow, object);
+  }
+}
+
+
+//  ==== Public API ====
+
+/// Setup System Timer.
+__WEAK int32_t osRtxSysTimerSetup (void) {
+
+  // Setup SysTick Timer
+  SysTick_Setup(osRtxInfo.kernel.sys_freq / osRtxConfig.tick_freq);
+
+  return SysTick_IRQn;                  // Return IRQ number of SysTick
+}
+
+/// Enable System Timer.
+__WEAK void osRtxSysTimerEnable (void) {
+  SysTick_Enable();
+}
+
+/// Disable System Timer.
+__WEAK void osRtxSysTimerDisable (void) {
+  SysTick_Disable();
+}
+
+/// Acknowledge System Timer IRQ.
+__WEAK void osRtxSysTimerAckIRQ (void) {
+  SysTick_GetOvf();
+}
+
+/// Get System Timer count.
+__WEAK uint32_t osRtxSysTimerGetCount (void) {
+  uint32_t tick;
+  uint32_t val;
+
+  tick = (uint32_t)osRtxInfo.kernel.tick;
+  val  = SysTick_GetVal();
+  if (SysTick_GetOvf()) {
+    val = SysTick_GetVal();
+    tick++;
+  }
+  val += tick * SysTick_GetPeriod();
+
+  return val;
+}
+
+/// Get System Timer frequency.
+__WEAK uint32_t osRtxSysTimerGetFreq (void) {
+  return osRtxInfo.kernel.sys_freq;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.c
new file mode 100755
index 0000000..aae22a0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_thread.c
@@ -0,0 +1,1722 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Thread functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+#include "rt_OsEventObserver.h"
+
+
+//  ==== Helper functions ====
+
+/// Set Thread Flags.
+/// \param[in]  thread          thread object.
+/// \param[in]  flags           specifies the flags to set.
+/// \return thread flags after setting.
+static uint32_t ThreadFlagsSet (os_thread_t *thread, uint32_t flags) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  uint32_t thread_flags;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  thread->thread_flags |= flags;
+  thread_flags = thread->thread_flags;
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  thread_flags = atomic_set32(&thread->thread_flags, flags);
+#endif
+
+  return thread_flags;
+}
+
+/// Clear Thread Flags.
+/// \param[in]  thread          thread object.
+/// \param[in]  flags           specifies the flags to clear.
+/// \return thread flags before clearing.
+static uint32_t ThreadFlagsClear (os_thread_t *thread, uint32_t flags) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask = __get_PRIMASK();
+#endif
+  uint32_t thread_flags;
+
+#if (__EXCLUSIVE_ACCESS == 0U)
+  __disable_irq();
+
+  thread_flags = thread->thread_flags;
+  thread->thread_flags &= ~flags;
+
+  if (primask == 0U) {
+    __enable_irq();
+  }
+#else
+  thread_flags = atomic_clr32(&thread->thread_flags, flags);
+#endif
+
+  return thread_flags;
+}
+
+/// Check Thread Flags.
+/// \param[in]  thread          thread object.
+/// \param[in]  flags           specifies the flags to check.
+/// \param[in]  options         specifies flags options (osFlagsXxxx).
+/// \return thread flags before clearing or 0 if specified flags have not been set.
+static uint32_t ThreadFlagsCheck (os_thread_t *thread, uint32_t flags, uint32_t options) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+  uint32_t primask;
+#endif
+  uint32_t thread_flags;
+
+  if ((options & osFlagsNoClear) == 0U) {
+#if (__EXCLUSIVE_ACCESS == 0U)
+    primask = __get_PRIMASK();
+    __disable_irq();
+
+    thread_flags = thread->thread_flags;
+    if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) ||
+        (((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) {
+      thread_flags = 0U;
+    } else {
+      thread->thread_flags &= ~flags;
+    }
+
+    if (primask == 0U) {
+      __enable_irq();
+    }
+#else
+    if ((options & osFlagsWaitAll) != 0U) {
+      thread_flags = atomic_chk32_all(&thread->thread_flags, flags);
+    } else {
+      thread_flags = atomic_chk32_any(&thread->thread_flags, flags);
+    }
+#endif
+  } else {
+    thread_flags = thread->thread_flags;
+    if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) ||
+        (((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) {
+      thread_flags = 0U;
+    }
+  }
+
+  return thread_flags;
+}
+
+
+//  ==== Library functions ====
+
+/// Put a Thread into specified Object list sorted by Priority (Highest at Head).
+/// \param[in]  object          generic object.
+/// \param[in]  thread          thread object.
+void osRtxThreadListPut (volatile os_object_t *object, os_thread_t *thread) {
+  os_thread_t *prev, *next;
+  int32_t      priority;
+
+  if (thread == NULL) {
+    return;
+  }
+
+  priority = thread->priority;
+
+  prev = (os_thread_t *)(uint32_t)object;
+  next = object->thread_list;
+  while ((next != NULL) && (next->priority >= priority)) {
+    prev = next;
+    next = next->thread_next;
+  }
+  thread->thread_prev = prev;
+  thread->thread_next = next;
+  prev->thread_next = thread;
+  if (next != NULL) {
+    next->thread_prev = thread;
+  }
+}
+
+/// Get a Thread with Highest Priority from specified Object list and remove it.
+/// \param[in]  object          generic object.
+/// \return thread object. 
+os_thread_t *osRtxThreadListGet (volatile os_object_t *object) {
+  os_thread_t *thread;
+
+  thread = object->thread_list;
+  if (thread != NULL) {
+    object->thread_list = thread->thread_next;
+    if (thread->thread_next != NULL) {
+      thread->thread_next->thread_prev = (os_thread_t *)(uint32_t)object;
+    }
+    thread->thread_prev = NULL;
+  }
+
+  return thread;
+}
+
+/// Retrieve Thread list root.
+/// \param[in]  thread          thread object.
+void *osRtxThreadListRoot (os_thread_t *thread) {
+
+  while ((thread != NULL) && (thread->id == osRtxIdThread)) {
+    thread = thread->thread_prev;
+  }
+  return ((void *)thread);
+}
+
+/// Re-sort a Thread in linked Object list by Priority (Highest at Head).
+/// \param[in]  thread          thread object.
+void osRtxThreadListSort (os_thread_t *thread) {
+  os_object_t *object;
+  os_thread_t *thread0;
+
+  // Search for object
+  thread0 = thread;
+  while (thread0->id == osRtxIdThread) {
+    thread0 = thread0->thread_prev;
+    if (thread0 == NULL) { 
+      return;
+    }
+  }
+  object = (os_object_t *)thread0;
+
+  osRtxThreadListRemove(thread);
+  osRtxThreadListPut(object, thread);
+}
+
+/// Remove a Thread from linked Object list.
+/// \param[in]  thread          thread object.
+void osRtxThreadListRemove (os_thread_t *thread) {
+
+  if (thread->thread_prev != NULL) {
+    thread->thread_prev->thread_next = thread->thread_next;
+    if (thread->thread_next != NULL) {
+      thread->thread_next->thread_prev = thread->thread_prev;
+    }
+    thread->thread_prev = NULL;
+  }
+}
+
+/// Unlink a Thread from specified linked list.
+/// \param[in]  thread          thread object.
+void osRtxThreadListUnlink (os_thread_t **thread_list, os_thread_t *thread) {
+
+  if (thread->thread_next != NULL) {
+    thread->thread_next->thread_prev = thread->thread_prev;
+  }
+  if (thread->thread_prev != NULL) {
+    thread->thread_prev->thread_next = thread->thread_next;
+    thread->thread_prev = NULL;
+  } else {
+    *thread_list = thread->thread_next;
+  }
+}
+
+/// Mark a Thread as Ready and put it into Ready list (sorted by Priority).
+/// \param[in]  thread          thread object.
+void osRtxThreadReadyPut (os_thread_t *thread) {
+
+  thread->state = osRtxThreadReady;
+  osRtxThreadListPut(&osRtxInfo.thread.ready, thread);
+}
+
+/// Insert a Thread into the Delay list sorted by Delay (Lowest at Head).
+/// \param[in]  thread          thread object.
+/// \param[in]  delay           delay value.
+void osRtxThreadDelayInsert (os_thread_t *thread, uint32_t delay) {
+  os_thread_t *prev, *next;
+
+  if (delay == osWaitForever) {
+    prev = NULL;
+    next = osRtxInfo.thread.wait_list;
+    while (next != NULL)  {
+      prev = next;
+      next = next->delay_next;
+    }
+    thread->delay = delay;
+    thread->delay_prev = prev;
+    thread->delay_next = next;
+    if (prev != NULL) {
+      prev->delay_next = thread;
+    } else {
+      osRtxInfo.thread.wait_list = thread;
+    }
+    if (next != NULL) {
+      next->delay_prev = thread;
+    }
+  } else {
+    prev = NULL;
+    next = osRtxInfo.thread.delay_list;
+    while ((next != NULL) && (next->delay <= delay)) {
+      delay -= next->delay;
+      prev = next;
+      next = next->delay_next;
+    }
+    thread->delay = delay;
+    thread->delay_prev = prev;
+    thread->delay_next = next;
+    if (prev != NULL) {
+      prev->delay_next = thread;
+    } else {
+      osRtxInfo.thread.delay_list = thread;
+    }
+    if (next != NULL) {
+      next->delay -= delay;
+      next->delay_prev = thread;
+    }
+  }
+}
+
+/// Remove a Thread from the Delay list.
+/// \param[in]  thread          thread object.
+void osRtxThreadDelayRemove (os_thread_t *thread) {
+
+  if (thread->delay == osWaitForever) {
+    if ((thread->delay_prev == NULL) && (osRtxInfo.thread.wait_list != thread)) {
+      return;
+    }
+    if (thread->delay_next != NULL) {
+      thread->delay_next->delay_prev = thread->delay_prev;
+    }
+    if (thread->delay_prev != NULL) {
+      thread->delay_prev->delay_next = thread->delay_next;
+      thread->delay_prev = NULL;
+    } else {
+      osRtxInfo.thread.wait_list = thread->delay_next;
+    }
+  } else {
+    if ((thread->delay_prev == NULL) && (osRtxInfo.thread.delay_list != thread)) {
+      return;
+    }
+    if (thread->delay_next != NULL) {
+      thread->delay_next->delay += thread->delay;
+      thread->delay_next->delay_prev = thread->delay_prev;
+    }
+    if (thread->delay_prev != NULL) {
+      thread->delay_prev->delay_next = thread->delay_next;
+      thread->delay_prev = NULL;
+    } else {
+      osRtxInfo.thread.delay_list = thread->delay_next;
+    }
+  }
+}
+
+/// Process Thread Delay Tick (executed each System Tick).
+void osRtxThreadDelayTick (void) {
+  os_thread_t *thread;
+
+  thread = osRtxInfo.thread.delay_list;
+  if (thread == NULL) {
+    return;
+  }
+
+  thread->delay--;
+
+  if (thread->delay == 0U) {
+    do {
+      switch (thread->state) {
+        case osRtxThreadWaitingDelay:
+          EvrRtxThreadDelayCompleted();
+          break;
+        case osRtxThreadWaitingThreadFlags:
+          EvrRtxThreadFlagsWaitTimeout();
+          break;
+        case osRtxThreadWaitingEventFlags:
+          EvrRtxEventFlagsWaitTimeout((osEventFlagsId_t)osRtxThreadListRoot(thread));
+          break;
+        case osRtxThreadWaitingMutex:
+          EvrRtxMutexAcquireTimeout((osMutexId_t)osRtxThreadListRoot(thread));
+          break;
+        case osRtxThreadWaitingSemaphore:
+          EvrRtxSemaphoreAcquireTimeout((osSemaphoreId_t)osRtxThreadListRoot(thread));
+          break;
+        case osRtxThreadWaitingMemoryPool:
+          EvrRtxMemoryPoolAllocTimeout((osMemoryPoolId_t)osRtxThreadListRoot(thread));
+          break;
+        case osRtxThreadWaitingMessageGet:
+          EvrRtxMessageQueueGetTimeout((osMessageQueueId_t)osRtxThreadListRoot(thread));
+          break;
+        case osRtxThreadWaitingMessagePut:
+          EvrRtxMessageQueuePutTimeout((osMessageQueueId_t)osRtxThreadListRoot(thread));
+          break;
+        default:
+          break;
+      }
+      EvrRtxThreadUnblocked(thread, (osRtxThreadRegPtr(thread))[0]);
+      osRtxThreadListRemove(thread);
+      osRtxThreadReadyPut(thread);
+      thread = thread->delay_next;
+    } while ((thread != NULL) && (thread->delay == 0U));
+    if (thread != NULL) {
+      thread->delay_prev = NULL;
+    }
+    osRtxInfo.thread.delay_list = thread;
+  }
+}
+
+/// Get pointer to Thread registers (R0..R3)
+/// \param[in]  thread          thread object.
+/// \return pointer to registers R0-R3.
+uint32_t *osRtxThreadRegPtr (os_thread_t *thread) {
+
+#if (__FPU_USED == 1U)
+  if (IS_EXTENDED_STACK_FRAME(thread->stack_frame)) {
+    // Extended Stack Frame: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR
+    return ((uint32_t *)(thread->sp + (16U+8U)*4U));
+  } else {
+    // Basic Stack Frame:             R4-R11, R0-R3, R12, LR, PC, xPSR
+    return ((uint32_t *)(thread->sp +      8U *4U));
+  }
+#else
+  // Stack Frame: R4-R11, R0-R3, R12, LR, PC, xPSR
+  return ((uint32_t *)(thread->sp + 8U*4U));
+#endif
+}
+
+/// Block running Thread execution and register it as Ready to Run.
+/// \param[in]  thread          running thread object.
+void osRtxThreadBlock (os_thread_t *thread) {
+  os_thread_t *prev, *next;
+  int32_t      priority;
+
+  thread->state = osRtxThreadReady;
+
+  priority = thread->priority;
+
+  prev = (os_thread_t *)(uint32_t)&osRtxInfo.thread.ready;
+  next = prev->thread_next;
+
+  while ((next != NULL) && (next->priority > priority)) {
+    prev = next;
+    next = next->thread_next;
+  }
+  thread->thread_prev = prev;
+  thread->thread_next = next;
+  prev->thread_next = thread;
+  if (next != NULL) {
+    next->thread_prev = thread;
+  }
+}
+
+/// Switch to specified Thread.
+/// \param[in]  thread          thread object.
+void osRtxThreadSwitch (os_thread_t *thread) {
+
+  thread->state = osRtxThreadRunning;
+  osRtxInfo.thread.run.next = thread;
+  osRtxThreadStackCheck();
+  EvrRtxThreadSwitch(thread);
+}
+
+/// Notify the OS event observer of an imminent thread switch.
+void thread_switch_helper(void) {
+  if (osEventObs && osEventObs->thread_switch) {
+    osEventObs->thread_switch(osRtxInfo.thread.run.next->context);
+  }
+}
+
+/// Dispatch specified Thread or Ready Thread with Highest Priority.
+/// \param[in]  thread          thread object or NULL.
+void osRtxThreadDispatch (os_thread_t *thread) {
+  uint8_t      kernel_state;
+  os_thread_t *thread_running;
+
+  kernel_state   = osRtxKernelGetState();
+  thread_running = osRtxThreadGetRunning();
+
+  if (thread == NULL) {
+    thread = osRtxInfo.thread.ready.thread_list;
+    if ((kernel_state == osRtxKernelRunning) &&
+        (thread_running != NULL) && (thread != NULL) && 
+        (thread->priority > thread_running->priority)) {
+      // Preempt running Thread
+      osRtxThreadListRemove(thread);
+      osRtxThreadBlock(thread_running);
+      osRtxThreadSwitch(thread);
+    }
+  } else {
+    if ((kernel_state == osRtxKernelRunning) &&
+        (thread_running != NULL) &&
+        (thread->priority > thread_running->priority)) {
+      // Preempt running Thread
+      osRtxThreadBlock(thread_running);
+      osRtxThreadSwitch(thread);
+    } else {
+      // Put Thread into Ready list
+      osRtxThreadReadyPut(thread);
+    }
+  }
+}
+
+/// Exit Thread wait state.
+/// \param[in]  thread          thread object.
+/// \param[in]  ret_val         return value.
+/// \param[in]  dispatch        dispatch flag.
+void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool dispatch) {
+  uint32_t *reg;
+
+  EvrRtxThreadUnblocked(thread, ret_val);
+
+  reg = osRtxThreadRegPtr(thread);
+  reg[0] = ret_val;
+
+  osRtxThreadDelayRemove(thread);
+  if (dispatch) {
+    osRtxThreadDispatch(thread);
+  } else {
+    osRtxThreadReadyPut(thread);
+  }
+}
+
+/// Enter Thread wait state.
+/// \param[in]  state           new thread state.
+/// \param[in]  timeout         timeout.
+/// \return true - success, false - failure.
+bool osRtxThreadWaitEnter (uint8_t state, uint32_t timeout) {
+  os_thread_t *thread;
+
+  thread = osRtxThreadGetRunning();
+  if (thread == NULL) {
+    return false;
+  }
+
+  if (osRtxKernelGetState() != osRtxKernelRunning) {
+    osRtxThreadListRemove(thread);
+    return false;
+  }
+
+  if (osRtxInfo.thread.ready.thread_list == NULL) {
+    return false;
+  }
+
+  EvrRtxThreadBlocked(thread, timeout);
+
+  thread->state = state;
+  osRtxThreadDelayInsert(thread, timeout);
+  thread = osRtxThreadListGet(&osRtxInfo.thread.ready);
+  osRtxThreadSwitch(thread);
+
+  return true;
+}
+
+/// Check current running Thread Stack.
+__WEAK void osRtxThreadStackCheck (void) {
+  os_thread_t *thread;
+
+  thread = osRtxThreadGetRunning();
+  if (thread != NULL) {
+    if ((thread->sp <= (uint32_t)thread->stack_mem) ||
+        (*((uint32_t *)thread->stack_mem) != osRtxStackMagicWord)) {
+      osRtxErrorNotify(osRtxErrorStackUnderflow, thread);
+    }
+  }
+}
+
+/// Thread post ISR processing.
+/// \param[in]  thread          thread object.
+void osRtxThreadPostProcess (os_thread_t *thread) {
+  uint32_t thread_flags;
+
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadTerminated)) {
+    return;
+  }
+
+  // Check if Thread is waiting for Thread Flags
+  if (thread->state == osRtxThreadWaitingThreadFlags) {
+    thread_flags = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options);
+    if (thread_flags != 0U) {
+      osRtxThreadWaitExit(thread, thread_flags, false);
+      EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags);
+    }
+  }
+}
+
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_4M(ThreadNew,           osThreadId_t,    osThreadFunc_t, void *, const osThreadAttr_t *, void *)
+SVC0_1 (ThreadGetName,       const char *,    osThreadId_t)
+SVC0_0 (ThreadGetId,         osThreadId_t)
+SVC0_1 (ThreadGetState,      osThreadState_t, osThreadId_t)
+SVC0_1 (ThreadGetStackSize,  uint32_t, osThreadId_t)
+SVC0_1 (ThreadGetStackSpace, uint32_t, osThreadId_t)
+SVC0_2 (ThreadSetPriority,   osStatus_t,      osThreadId_t, osPriority_t)
+SVC0_1 (ThreadGetPriority,   osPriority_t,    osThreadId_t)
+SVC0_0 (ThreadYield,         osStatus_t)
+SVC0_1 (ThreadSuspend,       osStatus_t,      osThreadId_t)
+SVC0_1 (ThreadResume,        osStatus_t,      osThreadId_t)
+SVC0_1 (ThreadDetach,        osStatus_t,      osThreadId_t)
+SVC0_1 (ThreadJoin,          osStatus_t,      osThreadId_t)
+SVC0_0N(ThreadExit,          void)
+SVC0_1 (ThreadTerminate,     osStatus_t,      osThreadId_t)
+SVC0_0 (ThreadGetCount,      uint32_t)
+SVC0_2 (ThreadEnumerate,     uint32_t,        osThreadId_t *, uint32_t)
+SVC0_2 (ThreadFlagsSet,      uint32_t,        osThreadId_t, uint32_t)
+SVC0_1 (ThreadFlagsClear,    uint32_t,        uint32_t)
+SVC0_0 (ThreadFlagsGet,      uint32_t)
+SVC0_3 (ThreadFlagsWait,     uint32_t,        uint32_t, uint32_t, uint32_t)
+
+/// Create a thread and add it to Active Threads.
+/// \note API identical to osThreadContextNew
+osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context) {
+  os_thread_t  *thread;
+  uint32_t      attr_bits;
+  void         *stack_mem;
+  uint32_t      stack_size;
+  osPriority_t  priority;
+  uint8_t       flags;
+  const char   *name;
+  uint32_t     *ptr;
+  uint32_t      n;
+#if (__DOMAIN_NS == 1U)
+  TZ_ModuleId_t tz_module;
+  TZ_MemoryId_t tz_memory;
+#endif
+
+  // Check parameters
+  if (func == NULL) {
+    EvrRtxThreadError(NULL, osErrorParameter);
+    return NULL;
+  }
+
+  // Process attributes
+  if (attr != NULL) {
+    name       = attr->name;
+    attr_bits  = attr->attr_bits;
+    thread     = attr->cb_mem;
+    stack_mem  = attr->stack_mem;
+    stack_size = attr->stack_size;
+    priority   = attr->priority;
+#if (__DOMAIN_NS == 1U)
+    tz_module  = attr->tz_module;
+#endif
+    if (thread != NULL) {
+      if (((uint32_t)thread & 3U) || (attr->cb_size < sizeof(os_thread_t))) {
+        EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    } else {
+      if (attr->cb_size != 0U) {
+        EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    }
+    if (stack_mem != NULL) {
+      if (((uint32_t)stack_mem & 7U) || (stack_size == 0U)) {
+        EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack);
+        return NULL;
+      }
+    }
+    if (priority == osPriorityNone) {
+      priority = osPriorityNormal;
+    } else {
+      if ((priority < osPriorityIdle) || (priority > osPriorityISR)) {
+        EvrRtxThreadError(NULL, osRtxErrorInvalidPriority);
+        return NULL;
+      }
+    }
+  } else {
+    name       = NULL;
+    attr_bits  = 0U;
+    thread     = NULL;
+    stack_mem  = NULL;
+    stack_size = 0U;
+    priority   = osPriorityNormal;
+#if (__DOMAIN_NS == 1U)
+    tz_module  = 0U;
+#endif
+  }
+
+  // Check stack size
+  if ((stack_size != 0U) && ((stack_size & 7U) || (stack_size < (64U + 8U)))) {
+    EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack);
+    return NULL;
+  }
+
+  // Allocate object memory if not provided
+  if (thread == NULL) {
+    if (osRtxInfo.mpi.thread != NULL) {
+      thread = osRtxMemoryPoolAlloc(osRtxInfo.mpi.thread);
+    } else {
+      thread = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_thread_t), 1U);
+    }
+    if (thread == NULL) {
+      EvrRtxThreadError(NULL, osErrorNoMemory);
+      return NULL;
+    }
+    flags = osRtxFlagSystemObject;
+  } else {
+    flags = 0U;
+  }
+
+  // Allocate stack memory if not provided
+  if (stack_mem == NULL) {
+    if (stack_size == 0U) {
+      stack_size = osRtxConfig.thread_stack_size;
+      if (osRtxInfo.mpi.stack != NULL) {
+        stack_mem = osRtxMemoryPoolAlloc(osRtxInfo.mpi.stack);
+        if (stack_mem != NULL) {
+          flags |= osRtxThreadFlagDefStack;
+        }
+      } else {
+        stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U);
+      }
+    } else {
+      stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U);
+    }
+    if (stack_mem == NULL) {
+      EvrRtxThreadError(NULL, osErrorNoMemory);
+      if (flags & osRtxFlagSystemObject) {
+        if (osRtxInfo.mpi.thread != NULL) {
+          osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
+        } else {
+          osRtxMemoryFree(osRtxInfo.mem.common, thread);
+        }
+      }
+      return NULL;
+    }
+    flags |= osRtxFlagSystemMemory;
+  }
+
+#if (__DOMAIN_NS == 1U)
+  // Allocate secure process stack
+  if (tz_module != 0U) {
+    tz_memory = TZ_AllocModuleContext_S(tz_module);
+    if (tz_memory == 0U) {
+      EvrRtxThreadError(NULL, osRtxErrorTZ_AllocContext_S);
+      if (flags & osRtxFlagSystemMemory) {
+        if (flags & osRtxThreadFlagDefStack) {
+          osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem);
+        } else {
+          osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem);
+        }
+      }
+      if (flags & osRtxFlagSystemObject) {
+        if (osRtxInfo.mpi.thread != NULL) {
+          osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
+        } else {
+          osRtxMemoryFree(osRtxInfo.mem.common, thread);
+        }
+      }
+      return NULL;
+    }
+  } else {
+    tz_memory = 0U;
+  }
+#endif
+
+  // Initialize control block
+  thread->id            = osRtxIdThread;
+  thread->state         = osRtxThreadReady;
+  thread->flags         = flags;
+  thread->attr          = (uint8_t)attr_bits;
+  thread->name          = name;
+  thread->thread_next   = NULL;
+  thread->thread_prev   = NULL;
+  thread->delay_next    = NULL;
+  thread->delay_prev    = NULL;
+  thread->thread_join   = NULL;
+  thread->delay         = 0U;
+  thread->priority      = (int8_t)priority;
+  thread->priority_base = (int8_t)priority;
+  thread->stack_frame   = STACK_FRAME_INIT;
+  thread->flags_options = 0U;
+  thread->wait_flags    = 0U;
+  thread->thread_flags  = 0U;
+  thread->mutex_list    = NULL;
+  thread->stack_mem     = stack_mem;
+  thread->stack_size    = stack_size;
+  thread->sp            = (uint32_t)stack_mem + stack_size - 64U;
+  thread->thread_addr   = (uint32_t)func;
+#if (__DOMAIN_NS == 1U)
+  thread->tz_memory     = tz_memory;
+#endif
+
+  // Initialize stack
+   ptr   = (uint32_t *)stack_mem;
+  *ptr++ = osRtxStackMagicWord;
+  if (osRtxConfig.flags & osRtxConfigStackWatermark) {
+    for (n = (stack_size/4U) - (16U + 1U); n; n--) {
+      *ptr++ = osRtxStackFillPattern;
+    }
+  } else {
+    ptr = (uint32_t *)thread->sp;
+  }
+  for (n = 13U; n; n--) {
+    *ptr++ = 0U;                        // R4..R11, R0..R3, R12
+  }
+  *ptr++   = (uint32_t)osThreadExit;    // LR
+  *ptr++   = (uint32_t)func;            // PC
+  *ptr++   = XPSR_INITIAL_VALUE;        // xPSR
+  *(ptr-8) = (uint32_t)argument;        // R0
+
+  // Register post ISR processing function
+  osRtxInfo.post_process.thread = osRtxThreadPostProcess;
+
+  EvrRtxThreadCreated(thread);
+
+  /* Notify the OS event observer of a new thread. */
+  if (osEventObs && osEventObs->thread_create) {
+    thread->context = osEventObs->thread_create((int)thread, context);
+  } else {
+    thread->context = context;
+  }
+
+  osRtxThreadDispatch(thread);
+
+  return thread;
+}
+
+/// Get name of a thread.
+/// \note API identical to osThreadGetName
+const char *svcRtxThreadGetName (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadGetName(thread, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (thread->state == osRtxObjectInactive) {
+    EvrRtxThreadGetName(thread, NULL);
+    return NULL;
+  }
+
+  EvrRtxThreadGetName(thread, thread->name);
+
+  return thread->name;
+}
+
+/// Return the thread ID of the current running thread.
+/// \note API identical to osThreadGetId
+osThreadId_t svcRtxThreadGetId (void) {
+  os_thread_t *thread;
+
+  thread = osRtxThreadGetRunning();
+  EvrRtxThreadGetId(thread);
+  return thread;
+}
+
+/// Get current thread state of a thread.
+/// \note API identical to osThreadGetState
+osThreadState_t svcRtxThreadGetState (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadGetState(thread, osThreadError);
+    return osThreadError;
+  }
+
+  EvrRtxThreadGetState(thread, (osThreadState_t)(thread->state & osRtxThreadStateMask));
+
+  return ((osThreadState_t)(thread->state & osRtxThreadStateMask));
+}
+
+/// Get stack size of a thread.
+/// \note API identical to osThreadGetStackSize
+uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadGetStackSize(thread, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (thread->state == osRtxObjectInactive) {
+    EvrRtxThreadGetStackSize(thread, 0U);
+    return 0U;
+  }
+
+  EvrRtxThreadGetStackSize(thread, thread->stack_size);
+
+  return thread->stack_size;
+}
+
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \note API identical to osThreadGetStackSpace
+uint32_t svcRtxThreadGetStackSpace (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+  uint32_t    *stack;
+  uint32_t     space;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadGetStackSpace(thread, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (thread->state == osRtxObjectInactive) {
+    EvrRtxThreadGetStackSpace(thread, 0U);
+    return 0U;
+  }
+
+  if ((osRtxConfig.flags & osRtxConfigStackWatermark) == 0U) {
+    EvrRtxThreadGetStackSpace(thread, 0U);
+    return 0U;
+  }
+
+  stack = thread->stack_mem;
+  if (*stack++ != osRtxStackMagicWord) {
+    EvrRtxThreadGetStackSpace(thread, 0U);
+    return 0U;
+  }
+  for (space = 4U; space < thread->stack_size; space += 4U) {
+    if (*stack++ != osRtxStackFillPattern) {
+      break;
+    }
+  }
+
+  EvrRtxThreadGetStackSpace(thread, space);
+
+  return space;
+}
+
+/// Change priority of a thread.
+/// \note API identical to osThreadSetPriority
+osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread) ||
+      (priority < osPriorityIdle) || (priority > osPriorityISR)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadTerminated)) {
+    EvrRtxThreadError(thread, osErrorResource);
+    return osErrorResource;
+  }
+
+  if (thread->priority   != (int8_t)priority) {
+    thread->priority      = (int8_t)priority;
+    thread->priority_base = (int8_t)priority;
+    osRtxThreadListSort(thread);
+    osRtxThreadDispatch(NULL);
+  }
+
+  return osOK;
+}
+
+/// Get current priority of a thread.
+/// \note API identical to osThreadGetPriority
+osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadGetPriority(thread, osPriorityError);
+    return osPriorityError;
+  }
+
+  // Check object state
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadTerminated)) {
+    EvrRtxThreadGetPriority(thread, osPriorityError);
+    return osPriorityError;
+  }
+
+  EvrRtxThreadGetPriority(thread, (osPriority_t)thread->priority);
+
+  return ((osPriority_t)thread->priority);
+}
+
+/// Pass control to next thread that is in state READY.
+/// \note API identical to osThreadYield
+osStatus_t svcRtxThreadYield (void) {
+  uint8_t      kernel_state;
+  os_thread_t *thread_running;
+  os_thread_t *thread_ready;
+
+  kernel_state   = osRtxKernelGetState();
+  thread_running = osRtxThreadGetRunning();
+  thread_ready   = osRtxInfo.thread.ready.thread_list;
+  if ((kernel_state == osRtxKernelRunning) &&
+      (thread_ready != NULL) && (thread_running != NULL) &&
+      (thread_ready->priority == thread_running->priority)) {
+    osRtxThreadListRemove(thread_ready);
+    osRtxThreadReadyPut(thread_running);
+    osRtxThreadSwitch(thread_ready);
+  }
+
+  return osOK;
+}
+
+/// Suspend execution of a thread.
+/// \note API identical to osThreadSuspend
+osStatus_t svcRtxThreadSuspend (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  switch (thread->state & osRtxThreadStateMask) {
+    case osRtxThreadRunning:
+      if ((osRtxKernelGetState() != osRtxKernelRunning) ||
+          (osRtxInfo.thread.ready.thread_list == NULL)) {
+        EvrRtxThreadError(thread, osErrorResource);
+        return osErrorResource;
+      }
+      break;
+    case osRtxThreadReady:
+      osRtxThreadListRemove(thread);
+      break;
+    case osRtxThreadBlocked:
+      osRtxThreadListRemove(thread);
+      osRtxThreadDelayRemove(thread);
+      break;
+    case osRtxThreadInactive:
+    case osRtxThreadTerminated:
+    default:
+      EvrRtxThreadError(thread, osErrorResource);
+      return osErrorResource;
+  }
+
+  EvrRtxThreadSuspended(thread);
+
+  if (thread->state == osRtxThreadRunning) {
+    osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
+  }
+
+  // Update Thread State and put it into Delay list
+  thread->state = osRtxThreadBlocked;
+  thread->thread_prev = NULL;
+  thread->thread_next = NULL;
+  osRtxThreadDelayInsert(thread, osWaitForever);
+
+  return osOK;
+}
+
+/// Resume execution of a thread.
+/// \note API identical to osThreadResume
+osStatus_t svcRtxThreadResume (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if ((thread->state & osRtxThreadStateMask) != osRtxThreadBlocked) {
+    EvrRtxThreadError(thread, osErrorResource);
+    return osErrorResource;
+  }
+
+  EvrRtxThreadResumed(thread);
+
+  // Wakeup Thread
+  osRtxThreadListRemove(thread);
+  osRtxThreadDelayRemove(thread);
+  osRtxThreadDispatch(thread);
+
+  return osOK;
+}
+
+/// Free Thread resources.
+/// \param[in]  thread          thread object.
+static void osRtxThreadFree (os_thread_t *thread) {
+
+  // Mark object as inactive
+  thread->state = osRtxThreadInactive;
+
+#if (__DOMAIN_NS == 1U)
+  // Free secure process stack
+  if (thread->tz_memory != 0U) {
+    TZ_FreeModuleContext_S(thread->tz_memory);
+  }
+#endif
+
+  // Free stack memory
+  if (thread->flags & osRtxFlagSystemMemory) {
+    if (thread->flags & osRtxThreadFlagDefStack) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem);
+    }
+  }
+
+  // Free object memory
+  if (thread->flags & osRtxFlagSystemObject) {
+    if (osRtxInfo.mpi.thread != NULL) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.common, thread);
+    }
+  }
+}
+
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \note API identical to osThreadDetach
+osStatus_t svcRtxThreadDetach (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object attributes
+  if ((thread->attr & osThreadJoinable) == 0U) {
+    EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable);
+    return osErrorResource;
+  }
+
+  // Check object state
+  if (thread->state == osRtxThreadInactive) {
+    EvrRtxThreadError(thread, osErrorResource);
+    return osErrorResource;
+  }
+
+  if (thread->state == osRtxThreadTerminated) {
+    osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread);
+    osRtxThreadFree(thread);
+  } else {
+    thread->attr &= ~osThreadJoinable;
+  }
+
+  EvrRtxThreadDetached(thread);
+
+  return osOK;
+}
+
+/// Wait for specified thread to terminate.
+/// \note API identical to osThreadJoin
+osStatus_t svcRtxThreadJoin (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object attributes
+  if ((thread->attr & osThreadJoinable) == 0U) {
+    EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable);
+    return osErrorResource;
+  }
+
+  // Check object state
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadRunning)) {
+    EvrRtxThreadError(thread, osErrorResource);
+    return osErrorResource;
+  }
+
+  if (thread->state == osRtxThreadTerminated) {
+    osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread);
+    osRtxThreadFree(thread);
+  } else {
+    EvrRtxThreadJoinPending(thread);
+    // Suspend current Thread
+    if (osRtxThreadWaitEnter(osRtxThreadWaitingJoin, osWaitForever)) {
+      thread->thread_join = osRtxThreadGetRunning();
+    }
+    return osErrorResource;
+  }
+
+  EvrRtxThreadJoined(thread);
+
+  return osOK;
+}
+
+/// Terminate execution of current running thread.
+/// \note API identical to osThreadExit
+void svcRtxThreadExit (void) {
+  os_thread_t *thread;
+
+  thread = osRtxThreadGetRunning();
+  if (thread == NULL) {
+    return;
+  }
+
+  // Release owned Mutexes
+  osRtxMutexOwnerRelease(thread->mutex_list);
+
+  // Wakeup Thread waiting to Join
+  if (thread->thread_join != NULL) {
+    osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, false);
+    EvrRtxThreadJoined(thread->thread_join);
+  }
+
+  // Switch to next Ready Thread
+  if ((osRtxKernelGetState() != osRtxKernelRunning) ||
+      (osRtxInfo.thread.ready.thread_list == NULL)) {
+    return;
+  }
+  thread->sp = __get_PSP();
+  osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
+  osRtxThreadSetRunning(NULL);
+
+  if (((thread->attr & osThreadJoinable) == 0U) || (thread->thread_join != NULL)) {
+    osRtxThreadFree(thread);
+  } else {
+    // Update Thread State and put it into Terminate Thread list
+    thread->state = osRtxThreadTerminated;
+    thread->thread_prev = NULL;
+    thread->thread_next = osRtxInfo.thread.terminate_list;
+    if (osRtxInfo.thread.terminate_list != NULL) {
+      osRtxInfo.thread.terminate_list->thread_prev = thread;
+    }
+    osRtxInfo.thread.terminate_list = thread;
+  }
+
+  EvrRtxThreadDestroyed(thread);
+}
+
+/// Terminate execution of a thread.
+/// \note API identical to osThreadTerminate
+osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  switch (thread->state & osRtxThreadStateMask) {
+    case osRtxThreadRunning:
+      break;
+    case osRtxThreadReady:
+      osRtxThreadListRemove(thread);
+      break;
+    case osRtxThreadBlocked:
+      osRtxThreadListRemove(thread);
+      osRtxThreadDelayRemove(thread);
+      break;
+    case osRtxThreadInactive:
+    case osRtxThreadTerminated:
+    default:
+      EvrRtxThreadError(thread, osErrorResource);
+      return osErrorResource;
+  }
+
+  if (osEventObs && osEventObs->thread_destroy) {
+    osEventObs->thread_destroy(thread->context);
+  }
+
+  // Release owned Mutexes
+  osRtxMutexOwnerRelease(thread->mutex_list);
+
+  // Wakeup Thread waiting to Join
+  if (thread->thread_join != NULL) {
+    osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, false);
+    EvrRtxThreadJoined(thread->thread_join);
+  }
+
+  // Switch to next Ready Thread when terminating running Thread
+  if (thread->state == osRtxThreadRunning) {
+    if ((osRtxKernelGetState() != osRtxKernelRunning) ||
+        (osRtxInfo.thread.ready.thread_list == NULL)) {
+      EvrRtxThreadError(thread, osErrorResource);
+      return osErrorResource;
+    }
+    thread->sp = __get_PSP();
+    osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
+    osRtxThreadSetRunning(NULL);
+  } else {
+    osRtxThreadDispatch(NULL);
+  }
+
+  if (((thread->attr & osThreadJoinable) == 0U) || (thread->thread_join != NULL)) {
+    osRtxThreadFree(thread);
+  } else {
+    // Update Thread State and put it into Terminate Thread list
+    thread->state = osRtxThreadTerminated;
+    thread->thread_prev = NULL;
+    thread->thread_next = osRtxInfo.thread.terminate_list;
+    if (osRtxInfo.thread.terminate_list != NULL) {
+      osRtxInfo.thread.terminate_list->thread_prev = thread;
+    }
+    osRtxInfo.thread.terminate_list = thread;
+  }
+
+  EvrRtxThreadDestroyed(thread);
+
+  return osOK;
+}
+
+/// Get number of active threads.
+/// \note API identical to osThreadGetCount
+uint32_t svcRtxThreadGetCount (void) {
+  os_thread_t *thread;
+  uint32_t     count;
+
+  // Running Thread
+  count = 1U;
+
+  // Ready List
+  for (thread = osRtxInfo.thread.ready.thread_list;
+       (thread != NULL); thread = thread->thread_next, count++) {};
+
+  // Delay List
+  for (thread = osRtxInfo.thread.delay_list;
+       (thread != NULL); thread = thread->delay_next,  count++) {};
+
+  // Wait List
+  for (thread = osRtxInfo.thread.wait_list;
+       (thread != NULL); thread = thread->delay_next,  count++) {};
+
+  EvrRtxThreadGetCount(count);
+
+  return count;
+}
+
+/// Enumerate active threads.
+/// \note API identical to osThreadEnumerate
+uint32_t svcRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
+  os_thread_t *thread;
+  uint32_t     count;
+
+  // Check parameters
+  if ((thread_array == NULL) || (array_items == 0U)) {
+    EvrRtxThreadEnumerate(thread_array, array_items, 0U);
+    return 0U;
+  }
+
+  // Running Thread
+  *thread_array++ = osRtxThreadGetRunning();
+  count = 1U;
+
+  // Ready List
+  for (thread = osRtxInfo.thread.ready.thread_list;
+       (thread != NULL) && (count < array_items); thread = thread->thread_next, count++) {
+    *thread_array++ = thread;
+  }
+
+  // Delay List
+  for (thread = osRtxInfo.thread.delay_list;
+       (thread != NULL) && (count < array_items); thread = thread->delay_next,  count++) {
+    *thread_array++ = thread;
+  }
+
+  // Wait List
+  for (thread = osRtxInfo.thread.wait_list;
+       (thread != NULL) && (count < array_items); thread = thread->delay_next,  count++) {
+    *thread_array++ = thread;
+  }
+
+  EvrRtxThreadEnumerate(thread_array - count, array_items, count);
+
+  return count;
+}
+
+/// Set the specified Thread Flags of a thread.
+/// \note API identical to osThreadFlagsSet
+uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+  uint32_t     thread_flags;
+  uint32_t     thread_flags0;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread) ||
+      (flags & ~((1U << osRtxThreadFlagsLimit) - 1U))) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadTerminated)) {
+    EvrRtxThreadError(thread, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Set Thread Flags
+  thread_flags = ThreadFlagsSet(thread, flags);
+
+  // Check if Thread is waiting for Thread Flags
+  if (thread->state == osRtxThreadWaitingThreadFlags) {
+    thread_flags0 = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options);
+    if (thread_flags0 != 0U) {
+      if ((thread->flags_options & osFlagsNoClear) == 0U) {
+        thread_flags = thread_flags0 & ~thread->wait_flags;
+      } else {
+        thread_flags = thread_flags0;
+      }
+      osRtxThreadWaitExit(thread, thread_flags0, true);
+      EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags0);
+    }
+  }
+
+  EvrRtxThreadFlagsSetDone(thread, thread_flags);
+
+  return thread_flags;
+}
+
+/// Clear the specified Thread Flags of current running thread.
+/// \note API identical to osThreadFlagsClear
+uint32_t svcRtxThreadFlagsClear (uint32_t flags) {
+  os_thread_t *thread;
+  uint32_t     thread_flags;
+
+  thread = osRtxThreadGetRunning();
+  if (thread == NULL) {
+    EvrRtxThreadError(NULL, osRtxErrorKernelNotRunning);
+    return ((uint32_t)osError);
+  }
+
+  // Check parameters
+  if (flags & ~((1U << osRtxThreadFlagsLimit) - 1U)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadTerminated)) {
+    EvrRtxThreadError(thread, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Clear Thread Flags
+  thread_flags = ThreadFlagsClear(thread, flags);
+
+  EvrRtxThreadFlagsClearDone(thread_flags);
+
+  return thread_flags;
+}
+
+/// Get the current Thread Flags of current running thread.
+/// \note API identical to osThreadFlagsGet
+uint32_t svcRtxThreadFlagsGet (void) {
+  os_thread_t *thread;
+
+  thread = osRtxThreadGetRunning();
+  if (thread == NULL) {
+    EvrRtxThreadFlagsGet(0U);
+    return 0U;
+  }
+
+  // Check object state
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadTerminated)) {
+    EvrRtxThreadFlagsGet(0U);
+    return 0U;
+  }
+
+  EvrRtxThreadFlagsGet(thread->thread_flags);
+
+  return thread->thread_flags;
+}
+
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \note API identical to osThreadFlagsWait
+uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
+  os_thread_t *thread;
+  uint32_t     thread_flags;
+
+  thread = osRtxThreadGetRunning();
+  if (thread == NULL) {
+    EvrRtxThreadError(NULL, osRtxErrorKernelNotRunning);
+    return ((uint32_t)osError);
+  }
+
+  // Check parameters
+  if (flags & ~((1U << osRtxThreadFlagsLimit) - 1U)) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check Thread Flags
+  thread_flags = ThreadFlagsCheck(thread, flags, options);
+  if (thread_flags != 0U) {
+    EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags);
+    return thread_flags;
+  }
+
+  // Check if timeout is specified
+  if (timeout != 0U) {
+    // Store waiting flags and options
+    EvrRtxThreadFlagsWaitPending(flags, options, timeout);
+    thread->wait_flags = flags;
+    thread->flags_options = (uint8_t)options;
+    // Suspend current Thread
+    osRtxThreadWaitEnter(osRtxThreadWaitingThreadFlags, timeout);
+    return ((uint32_t)osErrorTimeout);
+  }
+
+  EvrRtxThreadFlagsWaitNotCompleted(flags, options);
+
+  return ((uint32_t)osErrorResource);
+}
+
+
+//  ==== ISR Calls ====
+
+/// Set the specified Thread Flags of a thread.
+/// \note API identical to osThreadFlagsSet
+__STATIC_INLINE
+uint32_t isrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
+  os_thread_t *thread = (os_thread_t *)thread_id;
+  uint32_t     thread_flags;
+
+  // Check parameters
+  if ((thread == NULL) || (thread->id != osRtxIdThread) ||
+      (flags & ~((1U << osRtxThreadFlagsLimit) - 1U))) {
+    EvrRtxThreadError(thread, osErrorParameter);
+    return ((uint32_t)osErrorParameter);
+  }
+
+  // Check object state
+  if ((thread->state == osRtxThreadInactive) ||
+      (thread->state == osRtxThreadTerminated)) {
+    EvrRtxThreadError(thread, osErrorResource);
+    return ((uint32_t)osErrorResource);
+  }
+
+  // Set Thread Flags
+  thread_flags = ThreadFlagsSet(thread, flags);
+
+  // Register post ISR processing
+  osRtxPostProcess((os_object_t *)thread);
+
+  EvrRtxThreadFlagsSetDone(thread, thread_flags);
+
+  return thread_flags;
+}
+
+
+//  ==== Public API ====
+
+/// Create a thread and add it to Active Threads.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
+  return osThreadContextNew(func, argument, attr, NULL);
+}
+
+osThreadId_t osThreadContextNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context) {
+  EvrRtxThreadNew(func, argument, attr);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(NULL, osErrorISR);
+    return NULL;
+  }
+  return __svcThreadNew(func, argument, attr, context);
+}
+
+/// Get name of a thread.
+const char *osThreadGetName (osThreadId_t thread_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadGetName(thread_id, NULL);
+    return NULL;
+  }
+  return __svcThreadGetName(thread_id);
+}
+
+/// Return the thread ID of the current running thread.
+osThreadId_t osThreadGetId (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadGetId(NULL);
+    return NULL;
+  }
+  return __svcThreadGetId();
+}
+
+/// Get current thread state of a thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadGetState(thread_id, osThreadError);
+    return osThreadError;
+  }
+  return __svcThreadGetState(thread_id);
+}
+
+/// Get stack size of a thread.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadGetStackSize(thread_id, 0U);
+    return 0U;
+  }
+  return __svcThreadGetStackSize(thread_id);
+}
+
+/// Get available stack space of a thread based on stack watermark recording during execution.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadGetStackSpace(thread_id, 0U);
+    return 0U;
+  }
+  return __svcThreadGetStackSpace(thread_id);
+}
+
+/// Change priority of a thread.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
+  EvrRtxThreadSetPriority(thread_id, priority);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(thread_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcThreadSetPriority(thread_id, priority);
+}
+
+/// Get current priority of a thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadGetPriority(thread_id, osPriorityError);
+    return osPriorityError;
+  }
+  return __svcThreadGetPriority(thread_id);
+}
+
+/// Pass control to next thread that is in state READY.
+osStatus_t osThreadYield (void) {
+  EvrRtxThreadYield();
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(NULL, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcThreadYield();
+}
+
+/// Suspend execution of a thread.
+osStatus_t osThreadSuspend (osThreadId_t thread_id) {
+  EvrRtxThreadSuspend(thread_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(thread_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcThreadSuspend(thread_id);
+}
+
+/// Resume execution of a thread.
+osStatus_t osThreadResume (osThreadId_t thread_id) {
+  EvrRtxThreadResume(thread_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(thread_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcThreadResume(thread_id);
+}
+
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+osStatus_t osThreadDetach (osThreadId_t thread_id) {
+  EvrRtxThreadDetach(thread_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(thread_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcThreadDetach(thread_id);
+}
+
+/// Wait for specified thread to terminate.
+osStatus_t osThreadJoin (osThreadId_t thread_id) {
+  EvrRtxThreadJoin(thread_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(thread_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcThreadJoin(thread_id);
+}
+
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void) {
+  EvrRtxThreadExit();
+  __svcThreadExit();
+  EvrRtxThreadError(NULL, osError);
+  for (;;);
+}
+
+/// Terminate execution of a thread.
+osStatus_t osThreadTerminate (osThreadId_t thread_id) {
+  EvrRtxThreadTerminate(thread_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(thread_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcThreadTerminate(thread_id);
+}
+
+/// Get number of active threads.
+uint32_t osThreadGetCount (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadGetCount(0U);
+    return 0U;
+  }
+  return __svcThreadGetCount();
+}
+
+/// Enumerate active threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadEnumerate(thread_array, array_items, 0U);
+    return 0U;
+  }
+  return __svcThreadEnumerate(thread_array, array_items);
+}
+
+/// Set the specified Thread Flags of a thread.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
+  EvrRtxThreadFlagsSet(thread_id, flags);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    return isrRtxThreadFlagsSet(thread_id, flags);
+  } else {
+    return  __svcThreadFlagsSet(thread_id, flags);
+  }
+}
+
+/// Clear the specified Thread Flags of current running thread.
+uint32_t osThreadFlagsClear (uint32_t flags) {
+  EvrRtxThreadFlagsClear(flags);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(NULL, osErrorISR);
+    return ((uint32_t)osErrorISR);
+  }
+  return __svcThreadFlagsClear(flags);
+}
+
+/// Get the current Thread Flags of current running thread.
+uint32_t osThreadFlagsGet (void) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadFlagsGet(0U);
+    return 0U;
+  }
+  return __svcThreadFlagsGet();
+}
+
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
+  EvrRtxThreadFlagsWait(flags, options, timeout);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxThreadError(NULL, osErrorISR);
+    return ((uint32_t)osErrorISR);
+  }
+  return __svcThreadFlagsWait(flags, options, timeout);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.c
new file mode 100755
index 0000000..90bd795
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/TARGET_CORTEX/rtx5/rtx_timer.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       Timer functions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "rtx_lib.h"
+
+
+//  ==== Helper functions ====
+
+/// Insert Timer into the Timer List sorted by Time.
+/// \param[in]  timer           timer object.
+/// \param[in]  tick            timer tick.
+static void TimerInsert (os_timer_t *timer, uint32_t tick) {
+  os_timer_t *prev, *next;
+
+  prev = NULL;
+  next = osRtxInfo.timer.list;
+  while ((next != NULL) && (next->tick <= tick)) {
+    tick -= next->tick;
+    prev  = next;
+    next  = next->next;
+  }
+  timer->tick = tick;
+  timer->prev = prev;
+  timer->next = next;
+  if (next != NULL) {
+    next->tick -= timer->tick;
+    next->prev  = timer;
+  }
+  if (prev != NULL) {
+    prev->next = timer;
+  } else {
+    osRtxInfo.timer.list = timer;
+  }
+}
+
+/// Remove Timer from the Timer List.
+/// \param[in]  timer           timer object.
+static void TimerRemove (os_timer_t *timer) {
+
+  if (timer->next != NULL) {
+    timer->next->tick += timer->tick;
+    timer->next->prev  = timer->prev;
+  }
+  if (timer->prev != NULL) {
+    timer->prev->next  = timer->next;
+  } else {
+    osRtxInfo.timer.list = timer->next;
+  }
+}
+
+/// Unlink Timer from the Timer List Head.
+/// \param[in]  timer           timer object.
+static void TimerUnlink (os_timer_t *timer) {
+
+  if (timer->next != NULL) {
+    timer->next->prev = timer->prev;
+  }
+  osRtxInfo.timer.list = timer->next;
+}
+
+
+//  ==== Library functions ====
+
+/// Timer Tick (called each SysTick).
+void osRtxTimerTick (void) {
+  os_timer_t *timer;
+  osStatus_t  status;
+
+  timer = osRtxInfo.timer.list;
+  if (timer == NULL) {
+    return;
+  }
+
+  timer->tick--;
+  while ((timer != NULL) && (timer->tick == 0U)) {
+    TimerUnlink(timer);
+    status = osMessageQueuePut(osRtxInfo.timer.mq, &timer->finfo, 0U, 0U);
+    if (status != osOK) {
+      osRtxErrorNotify(osRtxErrorTimerQueueOverflow, timer);
+    }
+    if (timer->type == osRtxTimerPeriodic) {
+      TimerInsert(timer, timer->load);
+    } else {
+      timer->state = osRtxTimerStopped;
+    }
+    timer = osRtxInfo.timer.list;
+  }
+}
+
+/// Timer Thread
+__WEAK void osRtxTimerThread (void *argument) {
+  os_timer_finfo_t finfo;
+  osStatus_t       status;
+  (void)           argument;
+
+  osRtxInfo.timer.mq = osMessageQueueNew(osRtxConfig.timer_mq_mcnt, sizeof(os_timer_finfo_t), osRtxConfig.timer_mq_attr);
+  if (osRtxInfo.timer.mq == NULL) {
+    return;
+  }
+  osRtxInfo.timer.tick = osRtxTimerTick;
+  for (;;) {
+    status = osMessageQueueGet(osRtxInfo.timer.mq, &finfo, NULL, osWaitForever);
+    if (status == osOK) {
+      EvrRtxTimerCallback(*(osTimerFunc_t)finfo.fp, finfo.arg);
+      (*(osTimerFunc_t)finfo.fp)(finfo.arg);
+    }
+  }
+}
+
+//  ==== Service Calls ====
+
+//  Service Calls definitions
+SVC0_4M(TimerNew,       osTimerId_t,  osTimerFunc_t, osTimerType_t, void *, const osTimerAttr_t *)
+SVC0_1 (TimerGetName,   const char *, osTimerId_t)
+SVC0_2 (TimerStart,     osStatus_t,   osTimerId_t, uint32_t)
+SVC0_1 (TimerStop,      osStatus_t,   osTimerId_t)
+SVC0_1 (TimerIsRunning, uint32_t,     osTimerId_t)
+SVC0_1 (TimerDelete,    osStatus_t,   osTimerId_t)
+
+/// Create and Initialize a timer.
+/// \note API identical to osTimerNew
+osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
+  os_timer_t *timer;
+  uint8_t     flags;
+  const char *name;
+
+  // Check parameters
+  if ((func == NULL) || ((type != osTimerOnce) && (type != osTimerPeriodic))) {
+    EvrRtxTimerError(NULL, osErrorParameter);
+    return NULL;
+  }
+
+  // Process attributes
+  if (attr != NULL) {
+    name  = attr->name;
+    timer = attr->cb_mem;
+    if (timer != NULL) {
+      if (((uint32_t)timer & 3U) || (attr->cb_size < sizeof(os_timer_t))) {
+        EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    } else {
+      if (attr->cb_size != 0U) {
+        EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock);
+        return NULL;
+      }
+    }
+  } else {
+    name  = NULL;
+    timer = NULL;
+  }
+
+  // Allocate object memory if not provided
+  if (timer == NULL) {
+    if (osRtxInfo.mpi.timer != NULL) {
+      timer = osRtxMemoryPoolAlloc(osRtxInfo.mpi.timer);
+    } else {
+      timer = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_timer_t), 1U);
+    }
+    if (timer == NULL) {
+      EvrRtxTimerError(NULL, osErrorNoMemory);
+      return NULL;
+    }
+    flags = osRtxFlagSystemObject;
+  } else {
+    flags = 0U;
+  }
+
+  // Initialize control block
+  timer->id        = osRtxIdTimer;
+  timer->state     = osRtxTimerStopped;
+  timer->flags     = flags;
+  timer->type      = (uint8_t)type;
+  timer->name      = name;
+  timer->prev      = NULL;
+  timer->next      = NULL;
+  timer->tick      = 0U;
+  timer->load      = 0U;
+  timer->finfo.fp  = (void *)func;
+  timer->finfo.arg = argument;
+
+  EvrRtxTimerCreated(timer);
+
+  return timer;
+}
+
+/// Get name of a timer.
+/// \note API identical to osTimerGetName
+const char *svcRtxTimerGetName (osTimerId_t timer_id) {
+  os_timer_t *timer = (os_timer_t *)timer_id;
+
+  // Check parameters
+  if ((timer == NULL) || (timer->id != osRtxIdTimer)) {
+    EvrRtxTimerGetName(timer, NULL);
+    return NULL;
+  }
+
+  // Check object state
+  if (timer->state == osRtxObjectInactive) {
+    EvrRtxTimerGetName(timer, NULL);
+    return NULL;
+  }
+
+  EvrRtxTimerGetName(timer, timer->name);
+
+  return timer->name;
+}
+
+/// Start or restart a timer.
+/// \note API identical to osTimerStart
+osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) {
+  os_timer_t *timer = (os_timer_t *)timer_id;
+
+  // Check parameters
+  if ((timer == NULL) || (timer->id != osRtxIdTimer) || (ticks == 0U)) {
+    EvrRtxTimerError(timer, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  switch (timer->state) {
+    case osRtxTimerStopped:
+      if (osRtxInfo.timer.tick == NULL) {
+        EvrRtxTimerError(timer, osErrorResource);
+        return osErrorResource;
+      }
+      timer->state = osRtxTimerRunning;
+      timer->load  = ticks;
+      break;
+    case osRtxTimerRunning:
+      TimerRemove(timer);
+      break;
+    case osRtxTimerInactive:
+    default:
+      EvrRtxTimerError(timer, osErrorResource);
+      return osErrorResource;
+  }
+
+  TimerInsert(timer, ticks);
+
+  EvrRtxTimerStarted(timer);
+
+  return osOK;
+}
+
+/// Stop a timer.
+/// \note API identical to osTimerStop
+osStatus_t svcRtxTimerStop (osTimerId_t timer_id) {
+  os_timer_t *timer = (os_timer_t *)timer_id;
+
+  // Check parameters
+  if ((timer == NULL) || (timer->id != osRtxIdTimer)) {
+    EvrRtxTimerError(timer, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  if (timer->state != osRtxTimerRunning) {
+    EvrRtxTimerError(timer, osErrorResource);
+    return osErrorResource;
+  }
+
+  timer->state = osRtxTimerStopped;
+
+  TimerRemove(timer);
+
+  EvrRtxTimerStopped(timer);
+
+  return osOK;
+}
+
+/// Check if a timer is running.
+/// \note API identical to osTimerIsRunning
+uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id) {
+  os_timer_t *timer = (os_timer_t *)timer_id;
+
+  // Check parameters
+  if ((timer == NULL) || (timer->id != osRtxIdTimer)) {
+    EvrRtxTimerIsRunning(timer, 0U);
+    return 0U;
+  }
+
+  // Check object state
+  if (timer->state == osRtxTimerRunning) {
+    EvrRtxTimerIsRunning(timer, 1U);
+    return 1U;
+  }
+
+  EvrRtxTimerIsRunning(timer, 0U);
+  return 0U;
+}
+
+/// Delete a timer.
+/// \note API identical to osTimerDelete
+osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) {
+  os_timer_t *timer = (os_timer_t *)timer_id;
+
+  // Check parameters
+  if ((timer == NULL) || (timer->id != osRtxIdTimer)) {
+    EvrRtxTimerError(timer, osErrorParameter);
+    return osErrorParameter;
+  }
+
+  // Check object state
+  switch (timer->state) {
+    case osRtxTimerStopped:
+      break;
+    case osRtxTimerRunning:
+      TimerRemove(timer);
+      break;
+    case osRtxTimerInactive:
+    default:
+      EvrRtxTimerError(timer, osErrorResource);
+      return osErrorResource;
+  }
+
+  // Mark object as inactive
+  timer->state = osRtxTimerInactive;
+
+  // Free object memory
+  if (timer->flags & osRtxFlagSystemObject) {
+    if (osRtxInfo.mpi.timer != NULL) {
+      osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer);
+    } else {
+      osRtxMemoryFree(osRtxInfo.mem.common, timer);
+    }
+  }
+
+  EvrRtxTimerDestroyed(timer);
+
+  return osOK;
+}
+
+
+//  ==== Public API ====
+
+/// Create and Initialize a timer.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
+  EvrRtxTimerNew(func, type, argument, attr);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxTimerError(NULL, osErrorISR);
+    return NULL;
+  }
+  return __svcTimerNew(func, type, argument, attr);
+}
+
+/// Get name of a timer.
+const char *osTimerGetName (osTimerId_t timer_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxTimerGetName(timer_id, NULL);
+    return NULL;
+  }
+  return __svcTimerGetName(timer_id);
+}
+
+/// Start or restart a timer.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
+  EvrRtxTimerStart(timer_id, ticks);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxTimerError(timer_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcTimerStart(timer_id, ticks);
+}
+
+/// Stop a timer.
+osStatus_t osTimerStop (osTimerId_t timer_id) {
+  EvrRtxTimerStop(timer_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxTimerError(timer_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcTimerStop(timer_id);
+}
+
+/// Check if a timer is running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id) {
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxTimerIsRunning(timer_id, 0U);
+    return 0U;
+  }
+  return __svcTimerIsRunning(timer_id);
+}
+
+/// Delete a timer.
+osStatus_t osTimerDelete (osTimerId_t timer_id) {
+  EvrRtxTimerDelete(timer_id);
+  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+    EvrRtxTimerError(timer_id, osErrorISR);
+    return osErrorISR;
+  }
+  return __svcTimerDelete(timer_id);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Thread.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Thread.cpp
new file mode 100755
index 0000000..f01f1b1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Thread.cpp
@@ -0,0 +1,373 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "rtos/Thread.h"
+
+#include "mbed.h"
+#include "rtos/rtos_idle.h"
+
+static void (*terminate_hook)(osThreadId_t id) = 0;
+extern "C" void thread_terminate_hook(osThreadId_t id)
+{
+    if (terminate_hook != (void (*)(osThreadId_t))NULL) {
+        terminate_hook(id);
+    }
+}
+
+namespace rtos {
+
+void Thread::constructor(osPriority priority,
+        uint32_t stack_size, unsigned char *stack_mem, const char *name) {
+    _tid = 0;
+    _dynamic_stack = (stack_mem == NULL);
+    _finished = false;
+    memset(&_obj_mem, 0, sizeof(_obj_mem));
+    memset(&_attr, 0, sizeof(_attr));
+    _attr.priority = priority;
+    _attr.stack_size = stack_size;
+    _attr.name = name ? name : "application_unnamed_thread";
+    _attr.stack_mem = (uint32_t*)stack_mem;
+}
+
+void Thread::constructor(Callback<void()> task,
+        osPriority priority, uint32_t stack_size, unsigned char *stack_mem, const char *name) {
+    constructor(priority, stack_size, stack_mem, name);
+
+    switch (start(task)) {
+        case osErrorResource:
+            error("OS ran out of threads!\n");
+            break;
+        case osErrorParameter:
+            error("Thread already running!\n");
+            break;
+        case osErrorNoMemory:
+            error("Error allocating the stack memory\n");
+        default:
+            break;
+    }
+}
+
+osStatus Thread::start(Callback<void()> task) {
+    _mutex.lock();
+
+    if ((_tid != 0) || _finished) {
+        _mutex.unlock();
+        return osErrorParameter;
+    }
+
+    if (_attr.stack_mem == NULL) {
+        _attr.stack_mem = new uint32_t[_attr.stack_size/sizeof(uint32_t)];
+        MBED_ASSERT(_attr.stack_mem != NULL);
+    }
+
+    //Fill the stack with a magic word for maximum usage checking
+    for (uint32_t i = 0; i < (_attr.stack_size / sizeof(uint32_t)); i++) {
+        ((uint32_t *)_attr.stack_mem)[i] = 0xE25A2EA5;
+    }
+
+    memset(&_obj_mem, 0, sizeof(_obj_mem));
+    _attr.cb_size = sizeof(_obj_mem);
+    _attr.cb_mem = &_obj_mem;
+    _task = task;
+    _tid = osThreadNew(Thread::_thunk, this, &_attr);
+    if (_tid == NULL) {
+        if (_dynamic_stack) {
+            delete[] (uint32_t *)(_attr.stack_mem);
+            _attr.stack_mem = (uint32_t*)NULL;
+        }
+        _mutex.unlock();
+        _join_sem.release();
+        return osErrorResource;
+    }
+
+    _mutex.unlock();
+    return osOK;
+}
+
+osStatus Thread::terminate() {
+    osStatus_t ret = osOK;
+    _mutex.lock();
+
+    // Set the Thread's tid to NULL and
+    // release the semaphore before terminating
+    // since this thread could be terminating itself
+    osThreadId_t local_id = _tid;
+    _join_sem.release();
+    _tid = (osThreadId_t)NULL;
+    if (!_finished) {
+        _finished = true;
+        ret = osThreadTerminate(local_id);
+    }
+    _mutex.unlock();
+    return ret;
+}
+
+osStatus Thread::join() {
+    int32_t ret = _join_sem.wait();
+    if (ret < 0) {
+        return osError;
+    }
+
+    // The semaphore has been released so this thread is being
+    // terminated or has been terminated. Once the mutex has
+    // been locked it is ensured that the thread is deleted.
+    _mutex.lock();
+    MBED_ASSERT(NULL == _tid);
+    _mutex.unlock();
+
+    // Release sem so any other threads joining this thread wake up
+    _join_sem.release();
+    return osOK;
+}
+
+osStatus Thread::set_priority(osPriority priority) {
+    osStatus_t ret;
+    _mutex.lock();
+
+    ret = osThreadSetPriority(_tid, priority);
+
+    _mutex.unlock();
+    return ret;
+}
+
+osPriority Thread::get_priority() {
+    osPriority_t ret;
+    _mutex.lock();
+
+    ret = osThreadGetPriority(_tid);
+
+    _mutex.unlock();
+    return ret;
+}
+
+int32_t Thread::signal_set(int32_t flags) {
+    return osThreadFlagsSet(_tid, flags);
+}
+
+Thread::State Thread::get_state() {
+    uint8_t state = osThreadTerminated;
+
+    _mutex.lock();
+
+    if (_tid != NULL) {
+#if defined(MBED_OS_BACKEND_RTX5)
+        state = _obj_mem.state;
+#else
+        state = osThreadGetState(_tid);
+#endif
+    }
+
+    _mutex.unlock();
+
+    State user_state;
+
+    switch(state) {
+        case osThreadInactive:
+            user_state = Inactive;
+            break;
+        case osThreadReady:
+            user_state = Ready;
+            break;
+        case osThreadRunning:
+            user_state = Running;
+            break;
+#if defined(MBED_OS_BACKEND_RTX5)
+        case osRtxThreadWaitingDelay:
+            user_state = WaitingDelay;
+            break;
+        case osRtxThreadWaitingJoin:
+            user_state = WaitingJoin;
+            break;
+        case osRtxThreadWaitingThreadFlags:
+            user_state = WaitingThreadFlag;
+            break;
+        case osRtxThreadWaitingEventFlags:
+            user_state = WaitingEventFlag;
+            break;
+        case osRtxThreadWaitingMutex:
+            user_state = WaitingMutex;
+            break;
+        case osRtxThreadWaitingSemaphore:
+            user_state = WaitingSemaphore;
+            break;
+        case osRtxThreadWaitingMemoryPool:
+            user_state = WaitingMemoryPool;
+            break;
+        case osRtxThreadWaitingMessageGet:
+            user_state = WaitingMessageGet;
+            break;
+        case osRtxThreadWaitingMessagePut:
+            user_state = WaitingMessagePut;
+            break;
+#endif
+        case osThreadTerminated:
+        default:
+            user_state = Deleted;
+            break;
+    }
+
+    return user_state;
+}
+
+uint32_t Thread::stack_size() {
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        size = osThreadGetStackSize(_tid);
+    }
+
+    _mutex.unlock();
+    return size;
+}
+
+uint32_t Thread::free_stack() {
+    uint32_t size = 0;
+    _mutex.lock();
+
+#if defined(MBED_OS_BACKEND_RTX5)
+    if (_tid != NULL) {
+        os_thread_t *thread = (os_thread_t *)_tid;
+        size = (uint32_t)thread->sp - (uint32_t)thread->stack_mem;
+    }
+#endif
+
+    _mutex.unlock();
+    return size;
+}
+
+uint32_t Thread::used_stack() {
+    uint32_t size = 0;
+    _mutex.lock();
+
+#if defined(MBED_OS_BACKEND_RTX5)
+    if (_tid != NULL) {
+        os_thread_t *thread = (os_thread_t *)_tid;
+        size = ((uint32_t)thread->stack_mem + thread->stack_size) - thread->sp;
+    }
+#endif
+
+    _mutex.unlock();
+    return size;
+}
+
+uint32_t Thread::max_stack() {
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+#if defined(MBED_OS_BACKEND_RTX5)
+        os_thread_t *thread = (os_thread_t *)_tid;
+        uint32_t high_mark = 0;
+        while (((uint32_t *)(thread->stack_mem))[high_mark] == 0xE25A2EA5)
+            high_mark++;
+        size = thread->stack_size - (high_mark * sizeof(uint32_t));
+#else
+        size = osThreadGetStackSize(_tid) - osThreadGetStackSpace(_tid);
+#endif
+    }
+
+    _mutex.unlock();
+    return size;
+}
+
+const char *Thread::get_name() {
+    return _attr.name;
+}
+
+int32_t Thread::signal_clr(int32_t flags) {
+    return osThreadFlagsClear(flags);
+}
+
+osEvent Thread::signal_wait(int32_t signals, uint32_t millisec) {
+    uint32_t res;
+    osEvent evt;
+    uint32_t options = osFlagsWaitAll;
+    if (signals == 0) {
+        options = osFlagsWaitAny;
+        signals = 0x7FFFFFFF;
+    }
+    res = osThreadFlagsWait(signals, options, millisec);
+    if (res & osFlagsError) {
+        switch (res) {
+            case osFlagsErrorISR:
+                evt.status = osErrorISR;
+                break;
+            case osFlagsErrorResource:
+                evt.status = osOK;
+                break;
+            case osFlagsErrorTimeout:
+                evt.status = (osStatus)osEventTimeout;
+                break;
+            case osFlagsErrorParameter:
+            default:
+                evt.status = (osStatus)osErrorValue;
+                break;
+        }
+    } else {
+        evt.status = (osStatus)osEventSignal;
+        evt.value.signals = res;
+    }
+
+    return evt;
+}
+
+osStatus Thread::wait(uint32_t millisec) {
+    return osDelay(millisec);
+}
+
+osStatus Thread::yield() {
+    return osThreadYield();
+}
+
+osThreadId Thread::gettid() {
+    return osThreadGetId();
+}
+
+void Thread::attach_idle_hook(void (*fptr)(void)) {
+    rtos_attach_idle_hook(fptr);
+}
+
+void Thread::attach_terminate_hook(void (*fptr)(osThreadId_t id)) {
+    terminate_hook = fptr;
+}
+
+Thread::~Thread() {
+    // terminate is thread safe
+    terminate();
+    if (_dynamic_stack) {
+        delete[] (uint32_t*)(_attr.stack_mem);
+        _attr.stack_mem = (uint32_t*)NULL;
+    }
+}
+
+void Thread::_thunk(void * thread_ptr)
+{
+    Thread *t = (Thread*)thread_ptr;
+    t->_task();
+    t->_mutex.lock();
+    t->_tid = (osThreadId)NULL;
+    t->_finished = true;
+    t->_join_sem.release();
+    // rtos will release the mutex automatically
+}
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Thread.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Thread.h
new file mode 100755
index 0000000..cf92877
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/Thread.h
@@ -0,0 +1,377 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef THREAD_H
+#define THREAD_H
+
+#include <stdint.h>
+#include "cmsis_os2.h"
+#include "mbed_rtos1_types.h"
+#include "mbed_rtos_storage.h"
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+#include "rtos/Semaphore.h"
+#include "rtos/Mutex.h"
+
+namespace rtos {
+/** \addtogroup rtos */
+/** @{*/
+
+/** The Thread class allow defining, creating, and controlling thread functions in the system.
+ *
+ *  Example:
+ *  @code
+ *  #include "mbed.h"
+ *  #include "rtos.h"
+ *
+ *  Thread thread;
+ *  DigitalOut led1(LED1);
+ *  volatile bool running = true;
+ *
+ *  // Blink function toggles the led in a long running loop
+ *  void blink(DigitalOut *led) {
+ *      while (running) {
+ *          *led = !*led;
+ *          wait(1);
+ *      }
+ *  }
+ *
+ *  // Spawns a thread to run blink for 5 seconds
+ *  int main() {
+ *      thread.start(callback(blink, &led1));
+ *      wait(5);
+ *      running = false;
+ *      thread.join();
+ *  }
+ *  @endcode
+ *
+ * @note
+ * Memory considerations: The thread control structures will be created on current thread's stack, both for the mbed OS
+ * and underlying RTOS objects (static or dynamic RTOS memory pools are not being used).
+ * Additionally the stack memory for this thread will be allocated on the heap, if it wasn't supplied to the constructor.
+ */
+class Thread : private mbed::NonCopyable<Thread> {
+public:
+    /** Allocate a new thread without starting execution
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size     stack size (in bytes) requirements for the thread function. (default: OS_STACK_SIZE).
+      @param   stack_mem      pointer to the stack area to be used by this thread (default: NULL).
+      @param   name           name to be used for this thread. It has to stay allocated for the lifetime of the thread (default: NULL)
+    */
+    Thread(osPriority priority=osPriorityNormal,
+           uint32_t stack_size=OS_STACK_SIZE,
+           unsigned char *stack_mem=NULL, const char *name=NULL) {
+        constructor(priority, stack_size, stack_mem, name);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+      @param   task           function to be executed by this thread.
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size     stack size (in bytes) requirements for the thread function. (default: OS_STACK_SIZE).
+      @param   stack_mem      pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors. Replaced by thread.start(task).
+
+        @code
+        Thread thread(priority, stack_size, stack_mem);
+
+        osStatus status = thread.start(task);
+        if (status != osOK) {
+            error("oh no!");
+        }
+        @endcode
+    */
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors. "
+        "Replaced by thread.start(task).")
+    Thread(mbed::Callback<void()> task,
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=OS_STACK_SIZE,
+           unsigned char *stack_mem=NULL) {
+        constructor(task, priority, stack_size, stack_mem);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   task           argument to task.
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size     stack size (in bytes) requirements for the thread function. (default: OS_STACK_SIZE).
+      @param   stack_mem      pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors. Replaced by thread.start(callback(task, argument)).
+
+        @code
+        Thread thread(priority, stack_size, stack_mem);
+
+        osStatus status = thread.start(callback(task, argument));
+        if (status != osOK) {
+            error("oh no!");
+        }
+        @endcode
+    */
+    template <typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors. "
+        "Replaced by thread.start(callback(task, argument)).")
+    Thread(T *argument, void (T::*task)(),
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=OS_STACK_SIZE,
+           unsigned char *stack_mem=NULL) {
+        constructor(mbed::callback(task, argument),
+                    priority, stack_size, stack_mem);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   task           argument to task.
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size     stack size (in bytes) requirements for the thread function. (default: OS_STACK_SIZE).
+      @param   stack_mem      pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors. Replaced by thread.start(callback(task, argument)).
+
+        @code
+        Thread thread(priority, stack_size, stack_mem);
+
+        osStatus status = thread.start(callback(task, argument));
+        if (status != osOK) {
+            error("oh no!");
+        }
+        @endcode
+    */
+    template <typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors. "
+        "Replaced by thread.start(callback(task, argument)).")
+    Thread(T *argument, void (*task)(T *),
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=OS_STACK_SIZE,
+           unsigned char *stack_mem=NULL) {
+        constructor(mbed::callback(task, argument),
+                    priority, stack_size, stack_mem);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+        Provided for backwards compatibility
+      @param   task           function to be executed by this thread.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size     stack size (in bytes) requirements for the thread function. (default: OS_STACK_SIZE).
+      @param   stack_mem      pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors. Replaced by thread.start(callback(task, argument)).
+
+        @code
+        Thread thread(priority, stack_size, stack_mem);
+
+        osStatus status = thread.start(callback(task, argument));
+        if (status != osOK) {
+            error("oh no!");
+        }
+        @endcode
+    */
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors. "
+        "Replaced by thread.start(callback(task, argument)).")
+    Thread(void (*task)(void const *argument), void *argument=NULL,
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=OS_STACK_SIZE,
+           unsigned char *stack_mem=NULL) {
+        constructor(mbed::callback((void (*)(void *))task, argument),
+                    priority, stack_size, stack_mem);
+    }
+
+    /** Starts a thread executing the specified function.
+      @param   task           function to be executed by this thread.
+      @return  status code that indicates the execution status of the function.
+      @note a thread can only be started once
+    */
+    osStatus start(mbed::Callback<void()> task);
+
+    /** Starts a thread executing the specified function.
+      @param   obj            argument to task
+      @param   method         function to be executed by this thread.
+      @return  status code that indicates the execution status of the function.
+      @deprecated
+          The start function does not support cv-qualifiers. Replaced by start(callback(obj, method)).
+    */
+    template <typename T, typename M>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "The start function does not support cv-qualifiers. "
+        "Replaced by thread.start(callback(obj, method)).")
+    osStatus start(T *obj, M method) {
+        return start(mbed::callback(obj, method));
+    }
+
+    /** Wait for thread to terminate
+      @return  status code that indicates the execution status of the function.
+      @note not callable from interrupt
+    */
+    osStatus join();
+
+    /** Terminate execution of a thread and remove it from Active Threads
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus terminate();
+
+    /** Set priority of an active thread
+      @param   priority  new priority value for the thread function.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus set_priority(osPriority priority);
+
+    /** Get priority of an active thread
+      @return  current priority value of the thread function.
+    */
+    osPriority get_priority();
+
+    /** Set the specified Thread Flags for the thread.
+      @param   signals  specifies the signal flags of the thread that should be set.
+      @return  signal flags after setting or osFlagsError in case of incorrect parameters.
+    */
+    int32_t signal_set(int32_t signals);
+
+    /** State of the Thread */
+    enum State {
+        Inactive,           /**< NOT USED */
+        Ready,              /**< Ready to run */
+        Running,            /**< Running */
+        WaitingDelay,       /**< Waiting for a delay to occur */
+        WaitingJoin,        /**< Waiting for thread to join. Only happens when using RTX directly. */
+        WaitingThreadFlag,  /**< Waiting for a thread flag to be set */
+        WaitingEventFlag,   /**< Waiting for a event flag to be set */
+        WaitingMutex,       /**< Waiting for a mutex event to occur */
+        WaitingSemaphore,   /**< Waiting for a semaphore event to occur */
+        WaitingMemoryPool,  /**< Waiting for a memory pool */
+        WaitingMessageGet,  /**< Waiting for message to arrive */
+        WaitingMessagePut,  /**< Waiting for message to be send */
+        WaitingInterval,    /**< NOT USED */
+        WaitingOr,          /**< NOT USED */
+        WaitingAnd,         /**< NOT USED */
+        WaitingMailbox,     /**< NOT USED (Mail is implemented as MemoryPool and Queue) */
+
+        /* Not in sync with RTX below here */
+        Deleted,            /**< The task has been deleted or not started */
+    };
+
+    /** State of this Thread
+      @return  the State of this Thread
+    */
+    State get_state();
+    
+    /** Get the total stack memory size for this Thread
+      @return  the total stack memory size in bytes
+    */
+    uint32_t stack_size();
+    
+    /** Get the currently unused stack memory for this Thread
+      @return  the currently unused stack memory in bytes
+    */
+    uint32_t free_stack();
+    
+    /** Get the currently used stack memory for this Thread
+      @return  the currently used stack memory in bytes
+    */
+    uint32_t used_stack();
+    
+    /** Get the maximum stack memory usage to date for this Thread
+      @return  the maximum stack memory usage to date in bytes
+    */
+    uint32_t max_stack();
+
+    /** Get thread name
+      @return  thread name or NULL if the name was not set.
+     */
+    const char *get_name();
+
+    /** Clears the specified Thread Flags of the currently running thread.
+      @param   signals  specifies the signal flags of the thread that should be cleared.
+      @return  signal flags before clearing or osFlagsError in case of incorrect parameters.
+    */
+    static int32_t signal_clr(int32_t signals);
+
+    /** Wait for one or more Thread Flags to become signaled for the current RUNNING thread.
+      @param   signals   wait until all specified signal flags are set or 0 for any single signal flag.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event flag information or error code. @note if @a millisec is set to 0 and flag is no set the event carries osOK value.
+      @note not callable from interrupt
+    */
+    static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever);
+
+    /** Wait for a specified time period in millisec:
+      @param   millisec  time delay value
+      @return  status code that indicates the execution status of the function.
+      @note not callable from interrupt
+    */
+    static osStatus wait(uint32_t millisec);
+
+    /** Pass control to next thread that is in state READY.
+      @return  status code that indicates the execution status of the function.
+      @note not callable from interrupt
+    */
+    static osStatus yield();
+
+    /** Get the thread id of the current running thread.
+      @return  thread ID for reference by other functions or NULL in case of error.
+    */
+    static osThreadId gettid();
+
+    /** Attach a function to be called by the RTOS idle task
+      @param   fptr  pointer to the function to be called
+    */
+    static void attach_idle_hook(void (*fptr)(void));
+
+    /** Attach a function to be called when a task is killed
+      @param   fptr  pointer to the function to be called
+    */
+    static void attach_terminate_hook(void (*fptr)(osThreadId id));
+
+    virtual ~Thread();
+
+private:
+    // Required to share definitions without
+    // delegated constructors
+    void constructor(osPriority priority=osPriorityNormal,
+                     uint32_t stack_size=OS_STACK_SIZE,
+                     unsigned char *stack_mem=NULL,
+                     const char *name=NULL);
+    void constructor(mbed::Callback<void()> task,
+                     osPriority priority=osPriorityNormal,
+                     uint32_t stack_size=OS_STACK_SIZE,
+                     unsigned char *stack_mem=NULL,
+                     const char *name=NULL);
+    static void _thunk(void * thread_ptr);
+
+    mbed::Callback<void()>     _task;
+    osThreadId_t               _tid;
+    osThreadAttr_t             _attr;
+    bool                       _dynamic_stack;
+    Semaphore                  _join_sem;
+    Mutex                      _mutex;
+    mbed_rtos_storage_thread_t _obj_mem;
+    bool                       _finished;
+};
+
+}
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/mbed_lib.json
new file mode 100755
index 0000000..c0d9e20
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/mbed_lib.json
@@ -0,0 +1,6 @@
+{
+    "name": "rtos",
+    "config": {
+        "present": 1
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/rtos.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/rtos.h
new file mode 100755
index 0000000..7a10c8e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/rtos.h
@@ -0,0 +1,47 @@
+
+/** \addtogroup rtos */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_H
+#define RTOS_H
+
+#include "mbed_rtos_storage.h"
+#include "rtos/Thread.h"
+#include "rtos/Mutex.h"
+#include "rtos/RtosTimer.h"
+#include "rtos/Semaphore.h"
+#include "rtos/Mail.h"
+#include "rtos/MemoryPool.h"
+#include "rtos/Queue.h"
+#include "rtos/EventFlags.h"
+
+using namespace rtos;
+
+/* Get mbed lib version number, as RTOS depends on mbed lib features
+   like mbed_error, Callback and others.
+*/
+#include "mbed.h"
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/rtos_idle.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/rtos_idle.h
new file mode 100755
index 0000000..5fa9fb7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/rtos/rtos_idle.h
@@ -0,0 +1,42 @@
+
+/** \addtogroup rtos */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_IDLE_H
+#define RTOS_IDLE_H
+
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtos_attach_idle_hook(void (*fptr)(void));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PeripheralPins.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PeripheralPins.h
new file mode 100755
index 0000000..f96b848
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PeripheralPins.h
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+//*** ADC ***
+#ifdef DEVICE_ANALOGIN
+extern const PinMap PinMap_ADC[];
+extern const PinMap PinMap_ADC_Internal[];
+#endif
+
+//*** DAC ***
+#ifdef DEVICE_ANALOGOUT
+extern const PinMap PinMap_DAC[];
+#endif
+
+//*** I2C ***
+#if DEVICE_I2C
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+#endif
+
+//*** PWM ***
+#if DEVICE_PWMOUT
+extern const PinMap PinMap_PWM[];
+#endif
+
+//*** SERIAL ***
+#ifdef DEVICE_SERIAL
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+#ifdef DEVICE_SERIAL_FC
+extern const PinMap PinMap_UART_RTS[];
+extern const PinMap PinMap_UART_CTS[];
+#endif
+#endif
+
+//*** SPI ***
+#ifdef DEVICE_SPI
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_SSEL[];
+#endif
+
+//*** CAN ***
+#ifdef DEVICE_CAN
+extern const PinMap PinMap_CAN_RD[];
+extern const PinMap PinMap_CAN_TD[];
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PinNamesTypes.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PinNamesTypes.h
new file mode 100755
index 0000000..d51be19
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PinNamesTypes.h
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMESTYPES_H
+#define MBED_PINNAMESTYPES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*  STM PIN data as used in pin_function is coded on 32 bits as below
+ *   [2:0]  Function (like in MODER reg) : Input / Output / Alt / Analog 
+ *     [3]  Output Push-Pull / Open Drain (as in OTYPER reg)
+ *   [5:4]  as in PUPDR reg: No Pull, Pull-up, Pull-Donc
+ *   [7:6]  Reserved for speed config (as in OSPEEDR), but not used yet
+ *  [11:8]  Alternate Num (as in AFRL/AFRG reg)
+ * [16:12]  Channel (Analog/Timer specific)
+ *    [17]  Inverted (Analog/Timer specific)
+ *    [18]  Analog ADC control - Only valid for specific families
+ * [32:19]  Reserved
+ */
+
+#define STM_PIN_FUNCTION_MASK 0x07
+#define STM_PIN_FUNCTION_SHIFT 0
+#define STM_PIN_FUNCTION_BITS (STM_PIN_FUNCTION_MASK << STM_PIN_FUNCTION_SHIFT)
+
+#define STM_PIN_OD_MASK 0x01
+#define STM_PIN_OD_SHIFT 3
+#define STM_PIN_OD_BITS (STM_PIN_OD_MASK << STM_PIN_OD_SHIFT)
+
+#define STM_PIN_PUPD_MASK 0x03
+#define STM_PIN_PUPD_SHIFT 4
+#define STM_PIN_PUPD_BITS (STM_PIN_PUPD_MASK << STM_PIN_PUPD_SHIFT)
+
+#define STM_PIN_SPEED_MASK 0x03
+#define STM_PIN_SPEED_SHIFT 6
+#define STM_PIN_SPEED_BITS (STM_PIN_SPEED_MASK << STM_PIN_SPEED_SHIFT)
+
+#define STM_PIN_AFNUM_MASK 0x0F
+#define STM_PIN_AFNUM_SHIFT 8
+#define STM_PIN_AFNUM_BITS (STM_PIN_AFNUM_MASK << STM_PIN_AFNUM_SHIFT)
+
+#define STM_PIN_CHAN_MASK 0x1F
+#define STM_PIN_CHAN_SHIFT 12
+#define STM_PIN_CHANNEL_BIT (STM_PIN_CHAN_MASK << STM_PIN_CHAN_SHIFT)
+
+#define STM_PIN_INV_MASK 0x01
+#define STM_PIN_INV_SHIFT 17
+#define STM_PIN_INV_BIT (STM_PIN_INV_MASK << STM_PIN_INV_SHIFT)
+
+#define STM_PIN_AN_CTRL_MASK 0x01
+#define STM_PIN_AN_CTRL_SHIFT 18
+#define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT)
+
+#define STM_PIN_FUNCTION(X)         (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK)
+#define STM_PIN_OD(X)               (((X) >> STM_PIN_OD_SHIFT) & STM_PIN_OD_MASK)
+#define STM_PIN_PUPD(X)             (((X) >> STM_PIN_PUPD_SHIFT) & STM_PIN_PUPD_MASK)
+#define STM_PIN_SPEED(X)            (((X) >> STM_PIN_SPEED_SHIFT) & STM_PIN_SPEED_MASK)
+#define STM_PIN_AFNUM(X)            (((X) >> STM_PIN_AFNUM_SHIFT) & STM_PIN_AFNUM_MASK)
+#define STM_PIN_CHANNEL(X)          (((X) >> STM_PIN_CHAN_SHIFT) & STM_PIN_CHAN_MASK)
+#define STM_PIN_INVERTED(X)         (((X) >> STM_PIN_INV_SHIFT) & STM_PIN_INV_MASK)
+#define STM_PIN_ANALOG_CONTROL(X)   (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK)
+
+#define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM)  ((int)(FUNC_OD) |\
+                          ((PUPD  & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
+                          ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT))
+
+#define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \
+                                            ((int)(FUNC_OD) |\
+                       ((PUPD   & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
+                       ((AFNUM  & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
+                       ((CHAN   & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
+                       ((INV    & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
+
+/*
+ * MACROS to support the legacy definition of PIN formats
+ * The STM_MODE_ defines contain the function and the Push-pull/OpenDrain
+ * configuration (legacy inheritance).
+ */
+#define STM_PIN_DATA(FUNC_OD, PUPD, AFNUM) \
+            STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM)
+#define STM_PIN_DATA_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED) \
+            STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED)
+
+typedef enum {
+    STM_PIN_INPUT = 0,
+    STM_PIN_OUTPUT = 1,
+    STM_PIN_ALTERNATE = 2,
+    STM_PIN_ANALOG = 3,
+} StmPinFunction;
+
+#define STM_MODE_INPUT               (STM_PIN_INPUT)
+#define STM_MODE_OUTPUT_PP           (STM_PIN_OUTPUT)
+#define STM_MODE_OUTPUT_OD           (STM_PIN_OUTPUT | STM_PIN_OD_BITS)
+#define STM_MODE_AF_PP               (STM_PIN_ALTERNATE)
+#define STM_MODE_AF_OD               (STM_PIN_ALTERNATE | STM_PIN_OD_BITS)
+#define STM_MODE_ANALOG              (STM_PIN_ANALOG)
+#define STM_MODE_ANALOG_ADC_CONTROL  (STM_PIN_ANALOG | STM_PIN_ANALOG_CONTROL_BIT)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble  = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
+
+/*  Defines to be used by application */
+typedef enum {
+    PIN_INPUT = 0,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PullNone          = 0,
+    PullUp            = 1,
+    PullDown          = 2,
+    OpenDrainPullUp   = 3,
+    OpenDrainNoPull   = 4,
+    OpenDrainPullDown = 5,
+    PushPullNoPull    = PullNone,
+    PushPullPullUp    = PullUp,
+    PushPullPullDown  = PullDown,
+    OpenDrain         = OpenDrainPullUp,
+    PullDefault       = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PortNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PortNames.h
new file mode 100755
index 0000000..6f87eb0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/PortNames.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortE = 4,
+    PortF = 5,
+    PortG = 6,
+    PortH = 7,
+    PortI = 8,
+    PortJ = 9,
+    PortK = 10
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h
new file mode 100755
index 0000000..f5ee2b0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_2
+#define STDIO_UART_RX  PA_15
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c
new file mode 100755
index 0000000..4713a83
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c
@@ -0,0 +1,198 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - Connected to STDIO_UART_TX
+    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+//  {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 - does not support channel >= 16
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC,   NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4,  DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+    {PA_5,  DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_4,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PA_7,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PA_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// TIM2 (PWM_2) cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+//  {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},  // TIM15_CH1N
+//  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},  // TIM15_CH1 - Connected to STDIO_UART_TX
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 - Connected to STDIO_UART_TX
+    {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},  // TIM15_CH2
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+//  {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},  // TIM16_CH1
+    {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+    {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - Connected to LED
+    {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},  // TIM16_CH1N
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_2,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
+    {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
+    {PA_9,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,        NC,       0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_3,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_10,     UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,     UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, // Connected to STDIO_UART_RX
+    {PB_7,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,        NC,       0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_3,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,    NC,    0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_12,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_5_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_11,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_1,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_5,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Connected to LED
+    {PB_3_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Connected to LED
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_0,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,        NC,    0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h
new file mode 100755
index 0000000..f0f0f79
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h
@@ -0,0 +1,142 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+  PA_0  = 0x00,
+  PA_1  = 0x01,
+  PA_2  = 0x02,
+  PA_2_ALT0 = PA_2|ALT0,
+  PA_3  = 0x03,
+  PA_3_ALT0 = PA_3|ALT0,
+  PA_4  = 0x04,
+  PA_4_ALT0 = PA_4|ALT0,
+  PA_5  = 0x05,
+  PA_6  = 0x06,
+  PA_7  = 0x07,
+  PA_8  = 0x08,
+  PA_9  = 0x09,
+  PA_10 = 0x0A,
+  PA_11 = 0x0B,
+  PA_12 = 0x0C,
+  PA_13 = 0x0D,
+  PA_14 = 0x0E,
+  PA_15 = 0x0F,
+
+  PB_0  = 0x10,
+  PB_1  = 0x11,
+  PB_2  = 0x12,
+  PB_3  = 0x13,
+  PB_3_ALT0 = PB_3|ALT0,
+  PB_4  = 0x14,
+  PB_4_ALT0 = PB_4|ALT0,
+  PB_5  = 0x15,
+  PB_5_ALT0 = PB_5|ALT0,
+  PB_6  = 0x16,
+  PB_7  = 0x17,
+
+  PC_14 = 0x2E,
+  PC_15 = 0x2F,
+
+  // ADC internal channels
+  ADC_TEMP = 0xF0,
+  ADC_VREF = 0xF1,
+  ADC_VBAT = 0xF2,
+
+  // Arduino connector namings
+  A0          = PA_0,
+  A1          = PA_1,
+  A2          = PA_3,
+  A3          = PA_4,
+  A4          = PA_5,
+  A5          = PA_6,
+  A6          = PA_7,
+  A7          = PA_2,
+  D0          = PA_10,
+  D1          = PA_9,
+  D2          = PA_12,
+  D3          = PB_0,
+  D4          = PB_7,
+  D5          = PB_6,
+  D6          = PB_1,
+  D7          = PC_14,
+  D8          = PC_15,
+  D9          = PA_8,
+  D10         = PA_11,
+  D11         = PB_5,
+  D12         = PB_4,
+  D13         = PB_3,
+
+  // Generic signals namings
+  LED1        = PB_3,
+  LED2        = PB_3,
+  LED3        = PB_3,
+  LED4        = PB_3,
+  SERIAL_TX   = PA_2,
+  SERIAL_RX   = PA_15,
+  USBTX       = PA_2,
+  USBRX       = PA_15,
+  I2C_SCL     = PB_6,
+  I2C_SDA     = PB_7,
+  SPI_MOSI    = PB_5,
+  SPI_MISO    = PB_4,
+  SPI_SCK     = PB_3,
+  SPI_CS      = PA_11,
+  PWM_OUT     = PB_0,
+
+    //USB pins
+    USB_DM = PA_11,
+    USB_DP = PA_12,
+    USB_NOE = PA_13,
+
+  // Not connected
+  NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c
new file mode 100755
index 0000000..a1ca68c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c
@@ -0,0 +1,374 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.c
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        | or PLL_MSI
+  *                                    | (external 8 MHz xtal)  | (internal 4 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S
new file mode 100755
index 0000000..1b39603
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S
@@ -0,0 +1,366 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l432xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+__initial_sp    EQU     0x20010000 ; Top of RAM
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x0F800 ; 62KB (64KB, -2*1KB for main thread and scheduler)
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     0                                 ; Reserved
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     0                                 ; Reserved
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     USB_IRQHandler                    ; USB FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     0                                 ; Reserved
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     USB_IRQHandler                    [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+USB_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct
new file mode 100755
index 0000000..9da54cc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 256KB FLASH (0x40000) + 64KB SRAM (0x10000)
+LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
+  .ANY (+RW +ZI)
+  }
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S
new file mode 100755
index 0000000..a2f127a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S
@@ -0,0 +1,349 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l432xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+
+__initial_sp    EQU     0x20010000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     0                                 ; Reserved
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     0                                 ; Reserved
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     USB_IRQHandler                    ; USB FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     0                                 ; Reserved
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     USB_IRQHandler                    [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+USB_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct
new file mode 100755
index 0000000..9da54cc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 256KB FLASH (0x40000) + 64KB SRAM (0x10000)
+LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
+  .ANY (+RW +ZI)
+  }
+
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld
new file mode 100755
index 0000000..04dcddc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+  SRAM1 (rwx)  : ORIGIN = 0x20000188, LENGTH = 64k - 0x188
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > SRAM1
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > SRAM1
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > SRAM1
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM1
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S
new file mode 100755
index 0000000..c272e19
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S
@@ -0,0 +1,454 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l432xx.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      29-April-2016
+  * @brief     STM32L432xx devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before
+  // starting main(). software_init_hook() is available and has to be called due
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr
+
+LoopForever:
+    b LoopForever
+
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	TAMP_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_IRQHandler
+	.word	CAN1_TX_IRQHandler
+	.word	CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	0
+	.word	0
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	0
+	.word	0
+	.word	SPI1_IRQHandler
+	.word	0
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	0
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SPI3_IRQHandler
+	.word	0
+	.word	0
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	COMP_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	USB_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	QUADSPI_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	0
+	.word	SWPMI1_IRQHandler
+	.word	TSC_IRQHandler
+	.word	0
+	.word	0
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+	.word	CRS_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_IRQHandler
+	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	USB_IRQHandler
+	.thumb_set USB_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	QUADSPI_IRQHandler
+	.thumb_set QUADSPI_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+
+	.weak	SWPMI1_IRQHandler
+	.thumb_set SWPMI1_IRQHandler,Default_Handler
+
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/startup_stm32l432xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/startup_stm32l432xx.S
new file mode 100755
index 0000000..a3dd09c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/startup_stm32l432xx.S
@@ -0,0 +1,533 @@
+;/********************* COPYRIGHT(c) 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l432xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L432xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler                   ; ADC1
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     0                                 ; Reserved
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     0                                 ; Reserved
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     USB_IRQHandler                    ; USB FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     0                                 ; Reserved
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf
new file mode 100755
index 0000000..9c478c5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf
@@ -0,0 +1,30 @@
+/* [ROM = 256kb = 0x40000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x0803FFFF;
+
+/* [RAM = 48kb + 16kb = 0xC000] */
+/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM1_start__  = 0x20000188;
+define symbol __region_SRAM1_end__    = 0x2000FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+define symbol __size_cstack__ = 0x2000;
+define symbol __size_heap__   = 0x4000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in SRAM1_region   { readwrite, block STACKHEAP };
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h
new file mode 100755
index 0000000..41a1233
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l4xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
new file mode 100755
index 0000000..49f64ad
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
+// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+#define NVIC_NUM_VECTORS        98
+#define NVIC_RAM_VECTOR_ADDRESS SRAM1_BASE    // Vectors positioned at start of SRAM1
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h
new file mode 100755
index 0000000..934e8ed
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST      TIM2
+#define TIM_MST_IRQ  TIM2_IRQn
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
+
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
+
+#define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h
new file mode 100755
index 0000000..984f5ab
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h
@@ -0,0 +1,14870 @@
+/**
+  ******************************************************************************
+  * @file    stm32l432xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L432xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32l432xx
+  * @{
+  */
+
+#ifndef __STM32L432xx_H
+#define __STM32L432xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
+  USB_IRQn                    = 67,     /*!< USB event Interrupt                                               */
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  CRS_IRQn                    = 82      /*!< CRS global interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  uint32_t      RESERVED1;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x300 */
+  uint32_t      RESERVED2;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
+  uint32_t      RESERVED3;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct 
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef  DMA_Request_TypeDef
+
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+  * @brief Firewall
+  */
+
+typedef struct
+{
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+} FLASH_TypeDef;
+
+
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+
+} GPIO_TypeDef;
+
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  uint32_t RESERVED1;  /*!< Reserved,                            Address offset: 0x48 */
+  uint32_t RESERVED2;  /*!< Reserved,                            Address offset: 0x4C */
+  uint32_t RESERVED3;  /*!< Reserved,                            Address offset: 0x50 */
+  uint32_t RESERVED4;  /*!< Reserved,                            Address offset: 0x54 */ 
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
+  uint32_t      RESERVED;    /*!< Reserved,                                                                Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+  __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;    /*!< Reserved  */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
+  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
+} SYSCFG_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[7];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-4C */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/** 
+  * @brief Universal Serial Bus Full Speed Device
+  */
+  
+typedef struct
+{
+  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
+  __IO uint16_t RESERVED0;       /*!< Reserved */     
+  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
+  __IO uint16_t RESERVED1;       /*!< Reserved */       
+  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
+  __IO uint16_t RESERVED2;       /*!< Reserved */       
+  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
+  __IO uint16_t RESERVED3;       /*!< Reserved */       
+  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
+  __IO uint16_t RESERVED4;       /*!< Reserved */       
+  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
+  __IO uint16_t RESERVED5;       /*!< Reserved */       
+  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
+  __IO uint16_t RESERVED6;       /*!< Reserved */       
+  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
+  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
+  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
+  __IO uint16_t RESERVED8;       /*!< Reserved */       
+  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
+  __IO uint16_t RESERVED9;       /*!< Reserved */       
+  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
+  __IO uint16_t RESERVEDA;       /*!< Reserved */       
+  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
+  __IO uint16_t RESERVEDB;       /*!< Reserved */       
+  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
+  __IO uint16_t RESERVEDC;       /*!< Reserved */       
+  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
+  __IO uint16_t RESERVEDD;       /*!< Reserved */       
+  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
+  __IO uint16_t RESERVEDE;       /*!< Reserved */       
+} USB_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
+#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
+
+#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE         ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */
+#define SRAM2_SIZE            ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CRS_BASE              (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define USB_BASE              (APB1PERIPH_BASE + 0x6800U)  /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x6C00U)  /*!< USB_IP Packet Memory Area base address */
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
+
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
+
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC1_COMMON_BASE      (AHB2PERIPH_BASE + 0x08040300U)
+
+
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
+
+
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
+
+
+#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
+#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+//#define CAN                 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP1_COMMON       ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+/* Note: No specific macro feature on this device */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)                                    
+#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)                                    
+#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)                                    
+#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)                                    
+#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)                                    
+#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)                                    
+#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)                                    
+#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)                                    
+#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)                                    
+#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)                                    
+#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)                                   
+#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)                                    
+#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)                                    
+#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)                                    
+#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)                                    
+#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)                                    
+#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)                                    
+#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)                                    
+#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)                                    
+#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)                                    
+#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)                                    
+#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)                                   
+#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)                                    
+#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)                                    
+#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)                                    
+#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)                                    
+#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)                                    
+#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)                                    
+#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)                                   
+#define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos             (29U)                                   
+#define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)                                   
+#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)                                   
+#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)                                    
+#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)                                    
+#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)                                    
+#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos             (5U)                                    
+#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos            (6U)                                    
+#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)                                   
+#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)                                   
+#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)                                   
+#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)                                   
+#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos            (16U)                                   
+#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)                                   
+#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)                                   
+#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos               (21U)                                   
+#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)                                   
+#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)                                   
+#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)                                   
+#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)                                   
+#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)                                   
+#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos             (31U)                                   
+#define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)                                    
+#define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)                                    
+#define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos             (2U)                                    
+#define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)                                    
+#define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)                                    
+#define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)                                   
+#define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)                                    
+#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)                                    
+#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)                                    
+#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)                                    
+#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)                                   
+#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)                                   
+#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)                                   
+#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)                                   
+#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)                                   
+#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)                                   
+#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)                                    
+#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)                                    
+#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)                                    
+#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)                                    
+#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)                                   
+#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)                                   
+#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)                                   
+#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)                                   
+#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)                                   
+#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)                                    
+#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
+#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
+#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
+#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
+#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
+#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
+#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
+#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
+#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
+#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
+#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
+#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos                (16U)                                   
+#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
+#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
+#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
+#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
+#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
+#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
+#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
+#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
+#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
+#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
+#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
+#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)                                    
+#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
+#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
+#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
+#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
+#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
+#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
+#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
+#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos                (16U)                                   
+#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
+#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
+#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
+#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
+#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
+#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
+#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
+#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)                                    
+#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
+#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
+#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
+#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
+#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
+#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
+#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
+#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos                (16U)                                   
+#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
+#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
+#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
+#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
+#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
+#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
+#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
+#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)                                    
+#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)                                    
+#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)                                   
+#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)                                   
+#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)                                   
+#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)                                    
+#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)                                    
+#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)                                   
+#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)                                   
+#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)                                   
+#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)                                    
+#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)                                    
+#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)                                   
+#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)                                   
+#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)                                   
+#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)                                    
+#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)                                    
+#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)                                    
+#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)                                    
+#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)                                    
+#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos            (6U)                                    
+#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos              (8U)                                    
+#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos              (14U)                                   
+#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (20U)                                   
+#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (26U)                                   
+#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)                                    
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)                                   
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)                                   
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)                                    
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)                                   
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)                                   
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)                                    
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)                                   
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)                                   
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)                                    
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)                                   
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)                                   
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)                                    
+#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)                                    
+#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)                                    
+#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)                                    
+#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)                                    
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)                                    
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)                                    
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)                                    
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)                                   
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_CKMODE_Pos             (16U)                                   
+#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos              (18U)                                   
+#define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)                                   
+#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos               (23U)                                   
+#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos             (24U)                                   
+#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)                                          
+#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)                                         
+#define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)                                         
+#define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)                                         
+#define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)                                         
+#define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)                                         
+#define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)                                         
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)                                         
+#define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)                                         
+#define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)                                         
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)                                        
+#define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)                                        
+#define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)                                        
+#define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)                                        
+#define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+  
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)                                         
+#define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)                                         
+#define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)                                         
+#define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)                                         
+#define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)                                         
+#define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)                                         
+#define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)                                        
+#define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)                                        
+#define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)                                        
+#define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)                                         
+#define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)                                         
+#define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)                                         
+#define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)                                         
+#define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)                                      
+#define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)                                      
+#define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)                                      
+#define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)                                      
+#define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)                                      
+#define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)                                      
+#define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)                                       
+#define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)                                      
+#define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)                                       
+#define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)                                      
+#define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)                                       
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)                                       
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)                                       
+#define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)                                      
+#define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)                                       
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)                                      
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos      (0U)                                            
+#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos      (4U)                                            
+#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos      (8U)                                            
+#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos      (12U)                                           
+#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos      (16U)                                           
+#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos      (20U)                                           
+#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos      (24U)                                           
+#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos        (0U)                                          
+#define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos        (1U)                                          
+#define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos        (2U)                                          
+#define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos        (3U)                                          
+#define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos        (4U)                                          
+#define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos        (5U)                                          
+#define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos        (6U)                                          
+#define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos        (7U)                                          
+#define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos        (8U)                                          
+#define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos        (9U)                                          
+#define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos       (10U)                                         
+#define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos       (11U)                                         
+#define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos       (12U)                                         
+#define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos       (13U)                                         
+#define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos       (14U)                                         
+#define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos       (15U)                                         
+#define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos       (16U)                                         
+#define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos       (17U)                                         
+#define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos       (18U)                                         
+#define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos       (19U)                                         
+#define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos       (20U)                                         
+#define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos       (21U)                                         
+#define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos       (22U)                                         
+#define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos       (23U)                                         
+#define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos       (24U)                                         
+#define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos       (25U)                                         
+#define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos       (26U)                                         
+#define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos       (27U)                                         
+#define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos       (28U)                                         
+#define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM31_Pos       (31U)                                         
+#define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos         (0U)                                          
+#define EXTI_IMR1_IM_Msk         (0x9FFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0x9FFFFFFF */
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos        (0U)                                          
+#define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos        (1U)                                          
+#define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos        (2U)                                          
+#define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos        (3U)                                          
+#define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos        (4U)                                          
+#define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos        (5U)                                          
+#define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos        (6U)                                          
+#define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos        (7U)                                          
+#define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos        (8U)                                          
+#define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos        (9U)                                          
+#define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos       (10U)                                         
+#define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos       (11U)                                         
+#define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos       (12U)                                         
+#define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos       (13U)                                         
+#define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos       (14U)                                         
+#define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos       (15U)                                         
+#define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos       (16U)                                         
+#define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos       (17U)                                         
+#define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos       (18U)                                         
+#define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos       (19U)                                         
+#define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos       (20U)                                         
+#define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos       (21U)                                         
+#define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos       (22U)                                         
+#define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos       (23U)                                         
+#define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos       (24U)                                         
+#define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos       (25U)                                         
+#define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos       (26U)                                         
+#define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos       (27U)                                         
+#define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos       (28U)                                         
+#define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM31_Pos       (31U)                                         
+#define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos       (0U)                                          
+#define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos       (1U)                                          
+#define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos       (2U)                                          
+#define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos       (3U)                                          
+#define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos       (4U)                                          
+#define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos       (5U)                                          
+#define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos       (6U)                                          
+#define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos       (7U)                                          
+#define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos       (8U)                                          
+#define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos       (9U)                                          
+#define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos      (10U)                                         
+#define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos      (11U)                                         
+#define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos      (12U)                                         
+#define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos      (13U)                                         
+#define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos      (14U)                                         
+#define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos      (15U)                                         
+#define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos      (16U)                                         
+#define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos      (18U)                                         
+#define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos      (19U)                                         
+#define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos      (20U)                                         
+#define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos      (21U)                                         
+#define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos      (22U)                                         
+#define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos       (0U)                                          
+#define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos       (1U)                                          
+#define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos       (2U)                                          
+#define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos       (3U)                                          
+#define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos       (4U)                                          
+#define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos       (5U)                                          
+#define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos       (6U)                                          
+#define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos       (7U)                                          
+#define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos       (8U)                                          
+#define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos       (9U)                                          
+#define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos      (10U)                                         
+#define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos      (11U)                                         
+#define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos      (12U)                                         
+#define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos      (13U)                                         
+#define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos      (14U)                                         
+#define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos      (15U)                                         
+#define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos      (16U)                                         
+#define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos      (18U)                                         
+#define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos      (19U)                                         
+#define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos      (20U)                                         
+#define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos      (21U)                                         
+#define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos      (22U)                                         
+#define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos     (0U)                                          
+#define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos     (1U)                                          
+#define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos     (2U)                                          
+#define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos     (3U)                                          
+#define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos     (4U)                                          
+#define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos     (5U)                                          
+#define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos     (6U)                                          
+#define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos     (7U)                                          
+#define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos     (8U)                                          
+#define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos     (9U)                                          
+#define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos    (10U)                                         
+#define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos    (11U)                                         
+#define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos    (12U)                                         
+#define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos    (13U)                                         
+#define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos    (14U)                                         
+#define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos    (15U)                                         
+#define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos    (16U)                                         
+#define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos    (18U)                                         
+#define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos    (19U)                                         
+#define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos    (20U)                                         
+#define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos    (21U)                                         
+#define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos    (22U)                                         
+#define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos        (0U)                                          
+#define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos        (1U)                                          
+#define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos        (2U)                                          
+#define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos        (3U)                                          
+#define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos        (4U)                                          
+#define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos        (5U)                                          
+#define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos        (6U)                                          
+#define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos        (7U)                                          
+#define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos        (8U)                                          
+#define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos        (9U)                                          
+#define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos       (10U)                                         
+#define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos       (11U)                                         
+#define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos       (12U)                                         
+#define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos       (13U)                                         
+#define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos       (14U)                                         
+#define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos       (15U)                                         
+#define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos       (16U)                                         
+#define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos       (18U)                                         
+#define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */
+#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos       (19U)                                         
+#define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos       (20U)                                         
+#define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos       (21U)                                         
+#define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos       (22U)                                         
+#define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos       (0U)                                          
+#define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos       (1U)                                          
+#define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos       (2U)                                          
+#define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos       (3U)                                          
+#define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos       (4U)                                          
+#define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos       (5U)                                          
+#define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos       (6U)                                          
+#define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos       (7U)                                          
+#define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM_Pos         (0U)                                          
+#define EXTI_IMR2_IM_Msk         (0xFFU << EXTI_IMR2_IM_Pos)                   /*!< 0x000000FF */
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos       (0U)                                          
+#define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos       (1U)                                          
+#define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos       (2U)                                          
+#define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos       (3U)                                          
+#define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos       (4U)                                          
+#define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos       (5U)                                          
+#define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos       (6U)                                          
+#define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos       (7U)                                          
+#define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT35_Pos      (3U)                                          
+#define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos      (4U)                                          
+#define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos      (5U)                                          
+#define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos      (6U)                                          
+#define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT35_Pos      (3U)                                          
+#define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos      (4U)                                          
+#define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos      (5U)                                          
+#define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos      (6U)                                          
+#define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI35_Pos    (3U)                                          
+#define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos    (4U)                                          
+#define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos    (5U)                                          
+#define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos    (6U)                                          
+#define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF35_Pos       (3U)                                          
+#define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */
+#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos       (4U)                                          
+#define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */
+#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos       (5U)                                          
+#define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */
+#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos       (6U)                                          
+#define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos             (0U)                                 
+#define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                
+#define FLASH_ACR_LATENCY_0WS             (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS             (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS             (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS             (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS             (0x00000004U)
+#define FLASH_ACR_PRFTEN_Pos              (8U)                                 
+#define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk                 
+#define FLASH_ACR_ICEN_Pos                (9U)                                 
+#define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk                   
+#define FLASH_ACR_DCEN_Pos                (10U)                                
+#define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk                   
+#define FLASH_ACR_ICRST_Pos               (11U)                                
+#define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk                  
+#define FLASH_ACR_DCRST_Pos               (12U)                                
+#define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk                  
+#define FLASH_ACR_RUN_PD_Pos              (13U)                                
+#define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)                                
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                  (0U)                                 
+#define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     
+#define FLASH_SR_OPERR_Pos                (1U)                                 
+#define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk                   
+#define FLASH_SR_PROGERR_Pos              (3U)                                 
+#define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk                 
+#define FLASH_SR_WRPERR_Pos               (4U)                                 
+#define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk                  
+#define FLASH_SR_PGAERR_Pos               (5U)                                 
+#define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk                  
+#define FLASH_SR_SIZERR_Pos               (6U)                                 
+#define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk                  
+#define FLASH_SR_PGSERR_Pos               (7U)                                 
+#define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk                  
+#define FLASH_SR_MISERR_Pos               (8U)                                 
+#define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk                  
+#define FLASH_SR_FASTERR_Pos              (9U)                                 
+#define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk                 
+#define FLASH_SR_RDERR_Pos                (14U)                                
+#define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk                   
+#define FLASH_SR_OPTVERR_Pos              (15U)                                
+#define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk                 
+#define FLASH_SR_BSY_Pos                  (16U)                                
+#define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     
+#define FLASH_SR_PEMPTY_Pos               (17U)                                
+#define FLASH_SR_PEMPTY_Msk               (0x1U << FLASH_SR_PEMPTY_Pos)        /*!< 0x00020000 */
+#define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk                  
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                   (0U)                                 
+#define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk                      
+#define FLASH_CR_PER_Pos                  (1U)                                 
+#define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk                     
+#define FLASH_CR_MER1_Pos                 (2U)                                 
+#define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk                    
+#define FLASH_CR_PNB_Pos                  (3U)                                 
+#define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk                     
+#define FLASH_CR_STRT_Pos                 (16U)                                
+#define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    
+#define FLASH_CR_OPTSTRT_Pos              (17U)                                
+#define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk                 
+#define FLASH_CR_FSTPG_Pos                (18U)                                
+#define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk                   
+#define FLASH_CR_EOPIE_Pos                (24U)                                
+#define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   
+#define FLASH_CR_ERRIE_Pos                (25U)                                
+#define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   
+#define FLASH_CR_RDERRIE_Pos              (26U)                                
+#define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk                 
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)                                
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              
+#define FLASH_CR_OPTLOCK_Pos              (30U)                                
+#define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk                 
+#define FLASH_CR_LOCK_Pos                 (31U)                                
+#define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)                                 
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk              
+#define FLASH_ECCR_SYSF_ECC_Pos           (20U)                                
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk              
+#define FLASH_ECCR_ECCIE_Pos              (24U)                                
+#define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk                 
+#define FLASH_ECCR_ECCC_Pos               (30U)                                
+#define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk                  
+#define FLASH_ECCR_ECCD_Pos               (31U)                                
+#define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk                  
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                (0U)                                 
+#define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk                   
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)                                 
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk               
+#define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)                                
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk             
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)                                
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk            
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)                                
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk             
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)                                
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk               
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)                                
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk             
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)                                
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk            
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)                                
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk               
+#define FLASH_OPTR_nBOOT1_Pos             (23U)                                
+#define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk                
+#define FLASH_OPTR_SRAM2_PE_Pos           (24U)                                
+#define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk              
+#define FLASH_OPTR_SRAM2_RST_Pos          (25U)                                
+#define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk             
+#define FLASH_OPTR_nSWBOOT0_Pos           (26U)                                
+#define FLASH_OPTR_nSWBOOT0_Msk           (0x1U << FLASH_OPTR_nSWBOOT0_Pos)    /*!< 0x04000000 */
+#define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk              
+#define FLASH_OPTR_nBOOT0_Pos             (27U)                                
+#define FLASH_OPTR_nBOOT0_Msk             (0x1U << FLASH_OPTR_nBOOT0_Pos)      /*!< 0x08000000 */
+#define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk                
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)                                 
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)                                 
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk        
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)                                
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk         
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)                                 
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk          
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)                                
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk           
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)                                 
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk          
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)                                
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk           
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)                                    
+#define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk                    
+#define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)                                    
+#define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk                    
+#define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)                                    
+#define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk                    
+#define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)                                    
+#define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk                    
+#define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)                                    
+#define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk                    
+#define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)                                   
+#define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk                    
+#define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)                                   
+#define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk                    
+#define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)                                   
+#define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk                    
+#define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)                                   
+#define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk                    
+#define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)                                   
+#define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk                    
+#define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)                                   
+#define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk                   
+#define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)                                   
+#define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk                   
+#define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)                                   
+#define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk                   
+#define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)                                   
+#define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk                   
+#define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)                                   
+#define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk                   
+#define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)                                   
+#define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk                   
+#define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)                                    
+#define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk                     
+#define GPIO_OTYPER_OT1_Pos            (1U)                                    
+#define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk                     
+#define GPIO_OTYPER_OT2_Pos            (2U)                                    
+#define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk                     
+#define GPIO_OTYPER_OT3_Pos            (3U)                                    
+#define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk                     
+#define GPIO_OTYPER_OT4_Pos            (4U)                                    
+#define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk                     
+#define GPIO_OTYPER_OT5_Pos            (5U)                                    
+#define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk                     
+#define GPIO_OTYPER_OT6_Pos            (6U)                                    
+#define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk                     
+#define GPIO_OTYPER_OT7_Pos            (7U)                                    
+#define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk                     
+#define GPIO_OTYPER_OT8_Pos            (8U)                                    
+#define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk                     
+#define GPIO_OTYPER_OT9_Pos            (9U)                                    
+#define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk                     
+#define GPIO_OTYPER_OT10_Pos           (10U)                                   
+#define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk                    
+#define GPIO_OTYPER_OT11_Pos           (11U)                                   
+#define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk                    
+#define GPIO_OTYPER_OT12_Pos           (12U)                                   
+#define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk                    
+#define GPIO_OTYPER_OT13_Pos           (13U)                                   
+#define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk                    
+#define GPIO_OTYPER_OT14_Pos           (14U)                                   
+#define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk                    
+#define GPIO_OTYPER_OT15_Pos           (15U)                                   
+#define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk                    
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)                                    
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk                
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)                                    
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk                
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)                                    
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk                
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)                                    
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk                
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)                                    
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk                
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)                                   
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk                
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)                                   
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk                
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)                                   
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk                
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)                                   
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk                
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)                                   
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk                
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)                                   
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk               
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)                                   
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk               
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)                                   
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk               
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)                                   
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk               
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)                                   
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk               
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)                                   
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk               
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)                                    
+#define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk                    
+#define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)                                    
+#define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk                    
+#define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)                                    
+#define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk                    
+#define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)                                    
+#define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk                    
+#define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)                                    
+#define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk                    
+#define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)                                   
+#define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk                    
+#define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)                                   
+#define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk                    
+#define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)                                   
+#define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk                    
+#define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)                                   
+#define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk                    
+#define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)                                   
+#define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk                    
+#define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)                                   
+#define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk                   
+#define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)                                   
+#define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk                   
+#define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)                                   
+#define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk                   
+#define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)                                   
+#define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk                   
+#define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)                                   
+#define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk                   
+#define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)                                   
+#define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk                   
+#define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)                                    
+#define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk                        
+#define GPIO_IDR_ID1_Pos               (1U)                                    
+#define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk                        
+#define GPIO_IDR_ID2_Pos               (2U)                                    
+#define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk                        
+#define GPIO_IDR_ID3_Pos               (3U)                                    
+#define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk                        
+#define GPIO_IDR_ID4_Pos               (4U)                                    
+#define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk                        
+#define GPIO_IDR_ID5_Pos               (5U)                                    
+#define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk                        
+#define GPIO_IDR_ID6_Pos               (6U)                                    
+#define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk                        
+#define GPIO_IDR_ID7_Pos               (7U)                                    
+#define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk                        
+#define GPIO_IDR_ID8_Pos               (8U)                                    
+#define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk                        
+#define GPIO_IDR_ID9_Pos               (9U)                                    
+#define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk                        
+#define GPIO_IDR_ID10_Pos              (10U)                                   
+#define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk                       
+#define GPIO_IDR_ID11_Pos              (11U)                                   
+#define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk                       
+#define GPIO_IDR_ID12_Pos              (12U)                                   
+#define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk                       
+#define GPIO_IDR_ID13_Pos              (13U)                                   
+#define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk                       
+#define GPIO_IDR_ID14_Pos              (14U)                                   
+#define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk                       
+#define GPIO_IDR_ID15_Pos              (15U)                                   
+#define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk                       
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)                                    
+#define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk                        
+#define GPIO_ODR_OD1_Pos               (1U)                                    
+#define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk                        
+#define GPIO_ODR_OD2_Pos               (2U)                                    
+#define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk                        
+#define GPIO_ODR_OD3_Pos               (3U)                                    
+#define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk                        
+#define GPIO_ODR_OD4_Pos               (4U)                                    
+#define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk                        
+#define GPIO_ODR_OD5_Pos               (5U)                                    
+#define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk                        
+#define GPIO_ODR_OD6_Pos               (6U)                                    
+#define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk                        
+#define GPIO_ODR_OD7_Pos               (7U)                                    
+#define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk                        
+#define GPIO_ODR_OD8_Pos               (8U)                                    
+#define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk                        
+#define GPIO_ODR_OD9_Pos               (9U)                                    
+#define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk                        
+#define GPIO_ODR_OD10_Pos              (10U)                                   
+#define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk                       
+#define GPIO_ODR_OD11_Pos              (11U)                                   
+#define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk                       
+#define GPIO_ODR_OD12_Pos              (12U)                                   
+#define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk                       
+#define GPIO_ODR_OD13_Pos              (13U)                                   
+#define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk                       
+#define GPIO_ODR_OD14_Pos              (14U)                                   
+#define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk                       
+#define GPIO_ODR_OD15_Pos              (15U)                                   
+#define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk                       
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)                                    
+#define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk                       
+#define GPIO_BSRR_BS1_Pos              (1U)                                    
+#define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk                       
+#define GPIO_BSRR_BS2_Pos              (2U)                                    
+#define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk                       
+#define GPIO_BSRR_BS3_Pos              (3U)                                    
+#define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk                       
+#define GPIO_BSRR_BS4_Pos              (4U)                                    
+#define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk                       
+#define GPIO_BSRR_BS5_Pos              (5U)                                    
+#define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk                       
+#define GPIO_BSRR_BS6_Pos              (6U)                                    
+#define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk                       
+#define GPIO_BSRR_BS7_Pos              (7U)                                    
+#define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk                       
+#define GPIO_BSRR_BS8_Pos              (8U)                                    
+#define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk                       
+#define GPIO_BSRR_BS9_Pos              (9U)                                    
+#define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk                       
+#define GPIO_BSRR_BS10_Pos             (10U)                                   
+#define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk                      
+#define GPIO_BSRR_BS11_Pos             (11U)                                   
+#define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk                      
+#define GPIO_BSRR_BS12_Pos             (12U)                                   
+#define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk                      
+#define GPIO_BSRR_BS13_Pos             (13U)                                   
+#define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk                      
+#define GPIO_BSRR_BS14_Pos             (14U)                                   
+#define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk                      
+#define GPIO_BSRR_BS15_Pos             (15U)                                   
+#define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk                      
+#define GPIO_BSRR_BR0_Pos              (16U)                                   
+#define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk                       
+#define GPIO_BSRR_BR1_Pos              (17U)                                   
+#define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk                       
+#define GPIO_BSRR_BR2_Pos              (18U)                                   
+#define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk                       
+#define GPIO_BSRR_BR3_Pos              (19U)                                   
+#define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk                       
+#define GPIO_BSRR_BR4_Pos              (20U)                                   
+#define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk                       
+#define GPIO_BSRR_BR5_Pos              (21U)                                   
+#define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk                       
+#define GPIO_BSRR_BR6_Pos              (22U)                                   
+#define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk                       
+#define GPIO_BSRR_BR7_Pos              (23U)                                   
+#define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk                       
+#define GPIO_BSRR_BR8_Pos              (24U)                                   
+#define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk                       
+#define GPIO_BSRR_BR9_Pos              (25U)                                   
+#define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk                       
+#define GPIO_BSRR_BR10_Pos             (26U)                                   
+#define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk                      
+#define GPIO_BSRR_BR11_Pos             (27U)                                   
+#define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk                      
+#define GPIO_BSRR_BR12_Pos             (28U)                                   
+#define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk                      
+#define GPIO_BSRR_BR13_Pos             (29U)                                   
+#define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk                      
+#define GPIO_BSRR_BR14_Pos             (30U)                                   
+#define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk                      
+#define GPIO_BSRR_BR15_Pos             (31U)                                   
+#define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk                      
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)                                    
+#define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk                      
+#define GPIO_LCKR_LCK1_Pos             (1U)                                    
+#define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk                      
+#define GPIO_LCKR_LCK2_Pos             (2U)                                    
+#define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk                      
+#define GPIO_LCKR_LCK3_Pos             (3U)                                    
+#define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk                      
+#define GPIO_LCKR_LCK4_Pos             (4U)                                    
+#define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk                      
+#define GPIO_LCKR_LCK5_Pos             (5U)                                    
+#define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk                      
+#define GPIO_LCKR_LCK6_Pos             (6U)                                    
+#define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk                      
+#define GPIO_LCKR_LCK7_Pos             (7U)                                    
+#define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk                      
+#define GPIO_LCKR_LCK8_Pos             (8U)                                    
+#define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk                      
+#define GPIO_LCKR_LCK9_Pos             (9U)                                    
+#define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk                      
+#define GPIO_LCKR_LCK10_Pos            (10U)                                   
+#define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk                     
+#define GPIO_LCKR_LCK11_Pos            (11U)                                   
+#define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk                     
+#define GPIO_LCKR_LCK12_Pos            (12U)                                   
+#define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk                     
+#define GPIO_LCKR_LCK13_Pos            (13U)                                   
+#define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk                     
+#define GPIO_LCKR_LCK14_Pos            (14U)                                   
+#define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk                     
+#define GPIO_LCKR_LCK15_Pos            (15U)                                   
+#define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk                     
+#define GPIO_LCKR_LCKK_Pos             (16U)                                   
+#define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk                      
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)                                    
+#define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)                                    
+#define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)                                    
+#define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)                                   
+#define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)                                   
+#define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)                                   
+#define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)                                   
+#define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)                                   
+#define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk                    
+#define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)                                    
+#define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)                                    
+#define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)                                    
+#define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk                   
+#define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)                                   
+#define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk                   
+#define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)                                   
+#define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk                   
+#define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)                                   
+#define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk                   
+#define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)                                   
+#define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk                   
+#define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)                                   
+#define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk                   
+#define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)                                    
+#define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk                        
+#define GPIO_BRR_BR1_Pos               (1U)                                    
+#define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk                        
+#define GPIO_BRR_BR2_Pos               (2U)                                    
+#define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk                        
+#define GPIO_BRR_BR3_Pos               (3U)                                    
+#define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk                        
+#define GPIO_BRR_BR4_Pos               (4U)                                    
+#define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk                        
+#define GPIO_BRR_BR5_Pos               (5U)                                    
+#define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk                        
+#define GPIO_BRR_BR6_Pos               (6U)                                    
+#define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk                        
+#define GPIO_BRR_BR7_Pos               (7U)                                    
+#define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk                        
+#define GPIO_BRR_BR8_Pos               (8U)                                    
+#define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk                        
+#define GPIO_BRR_BR9_Pos               (9U)                                    
+#define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk                        
+#define GPIO_BRR_BR10_Pos              (10U)                                   
+#define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk                       
+#define GPIO_BRR_BR11_Pos              (11U)                                   
+#define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk                       
+#define GPIO_BRR_BR12_Pos              (12U)                                   
+#define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk                       
+#define GPIO_BRR_BR13_Pos              (13U)                                   
+#define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk                       
+#define GPIO_BRR_BR14_Pos              (14U)                                   
+#define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk                       
+#define GPIO_BRR_BR15_Pos              (15U)                                   
+#define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk                       
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos            (13U)                                     
+#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
+#define FW_CSSA_ADD_Pos      (8U)                                              
+#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos      (8U)                                              
+#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
+#define FW_NVDSSA_ADD_Pos    (8U)                                              
+#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos    (8U)                                              
+#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos     (6U)                                              
+#define FW_VDSSA_ADD_Msk     (0x7FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos     (6U)                                              
+#define FW_VDSL_LENG_Msk     (0x7FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos        (0U)                                              
+#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos        (1U)                                              
+#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos        (2U)                                              
+#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos              (14U)                                     
+#define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos              (9U)                                      
+#define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos              (8U)                                      
+#define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos             (0U)                                      
+#define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)                                      
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos       (1U)                                      
+#define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)                                      
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)                                      
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_USV_Pos              (10U)                                     
+#define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */
+#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos             (6U)                                      
+#define PWR_CR2_PVME_Msk             (0x3U << PWR_CR2_PVME_Pos)                /*!< 0x000000C0 */
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos            (7U)                                      
+#define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos            (6U)                                      
+#define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos              (1U)                                      
+#define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos         (3U)                                      
+#define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos             (0U)                                      
+#define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos             (15U)                                     
+#define PWR_CR3_EIWF_Msk             (0x1U << PWR_CR3_EIWF_Pos)                /*!< 0x00008000 */
+#define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos              (10U)                                     
+#define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos              (8U)                                      
+#define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos            (4U)                                      
+#define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos            (3U)                                      
+#define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos            (2U)                                      
+#define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos            (1U)                                      
+#define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos            (0U)                                      
+#define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos             (0U)                                      
+#define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos             (9U)                                      
+#define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos              (8U)                                      
+#define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos              (4U)                                      
+#define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos              (3U)                                      
+#define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos              (2U)                                      
+#define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos              (1U)                                      
+#define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos              (0U)                                      
+#define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos             (15U)                                     
+#define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos              (8U)                                      
+#define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos              (0U)                                      
+#define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos             (4U)                                      
+#define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos             (3U)                                      
+#define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos             (2U)                                      
+#define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos             (1U)                                      
+#define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos             (0U)                                      
+#define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos            (15U)                                     
+#define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos            (14U)                                     
+#define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVDO_Pos             (11U)                                     
+#define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos             (10U)                                     
+#define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos           (9U)                                      
+#define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos           (8U)                                      
+#define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos             (8U)                                      
+#define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos             (0U)                                      
+#define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos            (4U)                                      
+#define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos            (3U)                                      
+#define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos            (2U)                                      
+#define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos            (1U)                                      
+#define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos            (0U)                                      
+#define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos           (15U)                                     
+#define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos           (13U)                                     
+#define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos           (12U)                                     
+#define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos           (11U)                                     
+#define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos           (10U)                                     
+#define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos            (9U)                                      
+#define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos            (8U)                                      
+#define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos            (7U)                                      
+#define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos            (6U)                                      
+#define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos            (5U)                                      
+#define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos            (4U)                                      
+#define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos            (3U)                                      
+#define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos            (2U)                                      
+#define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos            (1U)                                      
+#define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos            (0U)                                      
+#define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos           (14U)                                     
+#define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos           (12U)                                     
+#define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos           (11U)                                     
+#define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos           (10U)                                     
+#define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos            (9U)                                      
+#define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos            (8U)                                      
+#define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos            (7U)                                      
+#define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos            (6U)                                      
+#define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos            (5U)                                      
+#define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos            (4U)                                      
+#define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos            (3U)                                      
+#define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos            (2U)                                      
+#define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos            (1U)                                      
+#define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos            (0U)                                      
+#define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+#define PWR_PUCRB_PB7_Pos            (7U)                                      
+#define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos            (6U)                                      
+#define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos            (5U)                                      
+#define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos            (4U)                                      
+#define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos            (3U)                                      
+#define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos            (1U)                                      
+#define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos            (0U)                                      
+#define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB7_Pos            (7U)                                      
+#define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos            (6U)                                      
+#define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos            (5U)                                      
+#define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos            (3U)                                      
+#define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos            (1U)                                      
+#define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos            (0U)                                      
+#define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos           (15U)                                     
+#define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos           (14U)                                     
+#define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos           (15U)                                     
+#define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos           (14U)                                     
+#define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
+
+
+
+
+/********************  Bit definition for PWR_PUCRH register  ********************/
+#define PWR_PUCRH_PH3_Pos            (3U)                                      
+#define PWR_PUCRH_PH3_Msk            (0x1U << PWR_PUCRH_PH3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRH register  ********************/
+#define PWR_PDCRH_PH3_Pos            (3U)                                      
+#define PWR_PDCRH_PH3_Msk            (0x1U << PWR_PDCRH_PH3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_HSI48_SUPPORT
+#define RCC_PLLP_DIV_2_31_SUPPORT
+#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_MSION_Pos                     (0U)                              
+#define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */
+#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos                    (1U)                              
+#define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos                  (2U)                              
+#define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos                  (3U)                              
+#define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos                  (4U)                              
+#define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos                     (8U)                              
+#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                  (9U)                              
+#define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                    (10U)                             
+#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos                   (11U)                             
+#define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */
+#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos                     (16U)                             
+#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                    (17U)                             
+#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                    (18U)                             
+#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                     (19U)                             
+#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                     (24U)                             
+#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                    (25U)                             
+#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos                 (26U)                             
+#define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos                (27U)                             
+#define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos                 (0U)                              
+#define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos                (8U)                              
+#define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                 (16U)                             
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos                (24U)                             
+#define RCC_ICSCR_HSITRIM_Msk                (0x1FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x1F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)                              
+#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)                              
+#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)                              
+#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)                              
+#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)                             
+#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
+#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
+#define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
+#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
+ 
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+ 
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)                              
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk            
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)                              
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)                              
+#define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk              
+#define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)                              
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk              
+#define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)                             
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk            
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)                             
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk              
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)                             
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk            
+
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)                             
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk              
+#define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)                             
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk            
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)                             
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk              
+#define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */
+
+#define RCC_PLLCFGR_PLLPDIV_Pos              (27U)                             
+#define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk           
+#define RCC_PLLCFGR_PLLPDIV_0                (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLCFGR_PLLPDIV_1                (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLPDIV_2                (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLPDIV_3                (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLCFGR_PLLPDIV_4                (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk      
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos      (27U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk      (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV          RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk   
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0        (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1        (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2        (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3        (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4        (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                (0U)                              
+#define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk             
+#define RCC_CIER_LSERDYIE_Pos                (1U)                              
+#define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk             
+#define RCC_CIER_MSIRDYIE_Pos                (2U)                              
+#define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk             
+#define RCC_CIER_HSIRDYIE_Pos                (3U)                              
+#define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk             
+#define RCC_CIER_HSERDYIE_Pos                (4U)                              
+#define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk             
+#define RCC_CIER_PLLRDYIE_Pos                (5U)                              
+#define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk             
+#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)                              
+#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk         
+#define RCC_CIER_LSECSSIE_Pos                (9U)                              
+#define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk             
+#define RCC_CIER_HSI48RDYIE_Pos              (10U)                             
+#define RCC_CIER_HSI48RDYIE_Msk              (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk           
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)                              
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk              
+#define RCC_CIFR_LSERDYF_Pos                 (1U)                              
+#define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk              
+#define RCC_CIFR_MSIRDYF_Pos                 (2U)                              
+#define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk              
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)                              
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk              
+#define RCC_CIFR_HSERDYF_Pos                 (4U)                              
+#define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk              
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)                              
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk              
+#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)                              
+#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk          
+#define RCC_CIFR_CSSF_Pos                    (8U)                              
+#define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk                 
+#define RCC_CIFR_LSECSSF_Pos                 (9U)                              
+#define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk              
+#define RCC_CIFR_HSI48RDYF_Pos               (10U)                             
+#define RCC_CIFR_HSI48RDYF_Msk               (0x1U << RCC_CIFR_HSI48RDYF_Pos)  /*!< 0x00000400 */
+#define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk            
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                 (0U)                              
+#define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk              
+#define RCC_CICR_LSERDYC_Pos                 (1U)                              
+#define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk              
+#define RCC_CICR_MSIRDYC_Pos                 (2U)                              
+#define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk              
+#define RCC_CICR_HSIRDYC_Pos                 (3U)                              
+#define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk              
+#define RCC_CICR_HSERDYC_Pos                 (4U)                              
+#define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk              
+#define RCC_CICR_PLLRDYC_Pos                 (5U)                              
+#define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk              
+#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)                              
+#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk          
+#define RCC_CICR_CSSC_Pos                    (8U)                              
+#define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk                 
+#define RCC_CICR_LSECSSC_Pos                 (9U)                              
+#define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk              
+#define RCC_CICR_HSI48RDYC_Pos               (10U)                             
+#define RCC_CICR_HSI48RDYC_Msk               (0x1U << RCC_CICR_HSI48RDYC_Pos)  /*!< 0x00000400 */
+#define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk            
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)                              
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk          
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)                              
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk          
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)                              
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk         
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)                             
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk           
+#define RCC_AHB1RSTR_TSCRST_Pos              (16U)                             
+#define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk           
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)                              
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk         
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)                              
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk         
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)                              
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk         
+#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)                              
+#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk         
+#define RCC_AHB2RSTR_ADCRST_Pos              (13U)                             
+#define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk           
+#define RCC_AHB2RSTR_RNGRST_Pos              (18U)                             
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk           
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)                              
+#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk          
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)                              
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk         
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)                              
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk         
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)                              
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk         
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)                             
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk         
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)                             
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk       
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)                             
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk         
+#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)                             
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk         
+#define RCC_APB1RSTR1_CRSRST_Pos             (24U)                             
+#define RCC_APB1RSTR1_CRSRST_Msk             (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk          
+#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)                             
+#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk         
+#define RCC_APB1RSTR1_USBFSRST_Pos           (26U)                             
+#define RCC_APB1RSTR1_USBFSRST_Msk           (0x1U << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR1_USBFSRST               RCC_APB1RSTR1_USBFSRST_Msk        
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)                             
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk          
+#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)                             
+#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk         
+#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)                             
+#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk        
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)                             
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk       
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)                              
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk      
+#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)                              
+#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk       
+#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)                              
+#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk       
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)                              
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk        
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)                             
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk         
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)                             
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk         
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)                             
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk          
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)                              
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk            
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)                              
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk            
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)                              
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk           
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)                             
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk             
+#define RCC_AHB1ENR_TSCEN_Pos                (16U)                             
+#define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk             
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)                              
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk           
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)                              
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk           
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)                              
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk           
+#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)                              
+#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk           
+#define RCC_AHB2ENR_ADCEN_Pos                (13U)                             
+#define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk             
+#define RCC_AHB2ENR_RNGEN_Pos                (18U)                             
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_QSPIEN_Pos               (8U)                              
+#define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk            
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)                              
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk           
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)                              
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk           
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)                              
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk           
+#define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)                             
+#define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk         
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)                             
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk           
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)                             
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk           
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)                             
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk         
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)                             
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk           
+#define RCC_APB1ENR1_I2C3EN_Pos              (23U)                             
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk           
+#define RCC_APB1ENR1_CRSEN_Pos               (24U)                             
+#define RCC_APB1ENR1_CRSEN_Msk               (0x1U << RCC_APB1ENR1_CRSEN_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk            
+#define RCC_APB1ENR1_CAN1EN_Pos              (25U)                             
+#define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk           
+#define RCC_APB1ENR1_USBFSEN_Pos             (26U)                             
+#define RCC_APB1ENR1_USBFSEN_Msk             (0x1U << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR1_USBFSEN                 RCC_APB1ENR1_USBFSEN_Msk          
+#define RCC_APB1ENR1_PWREN_Pos               (28U)                             
+#define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk            
+#define RCC_APB1ENR1_DAC1EN_Pos              (29U)                             
+#define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk           
+#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)                             
+#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk          
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)                             
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk         
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)                              
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk        
+#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)                              
+#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk         
+#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)                              
+#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk         
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)                              
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk          
+#define RCC_APB2ENR_FWEN_Pos                 (7U)                              
+#define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk              
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            
+#define RCC_APB2ENR_USART1EN_Pos             (14U)                             
+#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)                             
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk           
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)                             
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk           
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)                             
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk            
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)                              
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk        
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)                              
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk        
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)                              
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk       
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)                              
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk       
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)                             
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk         
+#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)                             
+#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)                              
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk       
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)                              
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)                              
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)                              
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk       
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)                              
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk       
+#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)                             
+#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk         
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)                             
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)                              
+#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk        
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)                              
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk       
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)                              
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk       
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)                              
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk       
+#define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)                             
+#define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk     
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)                             
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk       
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)                             
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk       
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)                             
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk     
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)                             
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk       
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)                             
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk       
+#define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)                             
+#define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk        
+#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)                             
+#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk       
+#define RCC_APB1SMENR1_USBFSSMEN_Pos         (26U)                             
+#define RCC_APB1SMENR1_USBFSSMEN_Msk         (0x1U << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1SMENR1_USBFSSMEN             RCC_APB1SMENR1_USBFSSMEN_Msk      
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)                             
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk        
+#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)                             
+#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk       
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)                             
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk      
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)                             
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk     
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)                              
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk    
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)                              
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk     
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)                              
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk     
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)                              
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk      
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)                             
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk        
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)                             
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk        
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)                             
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk      
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)                             
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk       
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)                             
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk       
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)                             
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk        
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos              (0U)                              
+#define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk           
+#define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos              (2U)                              
+#define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk           
+#define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)                             
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk          
+#define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)                             
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk             
+#define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)                             
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk             
+#define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)                             
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk           
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)                             
+#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk           
+#define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos                (22U)                             
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk             
+#define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)                             
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk            
+#define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos                 (28U)                             
+#define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk              
+#define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)                             
+#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk           
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                   (0U)                              
+#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                
+#define RCC_BDCR_LSERDY_Pos                  (1U)                              
+#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               
+#define RCC_BDCR_LSEBYP_Pos                  (2U)                              
+#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               
+
+#define RCC_BDCR_LSEDRV_Pos                  (3U)                              
+#define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk               
+#define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                (5U)                              
+#define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk             
+#define RCC_BDCR_LSECSSD_Pos                 (6U)                              
+#define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk              
+
+#define RCC_BDCR_RTCSEL_Pos                  (8U)                              
+#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               
+#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                   (15U)                             
+#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                
+#define RCC_BDCR_BDRST_Pos                   (16U)                             
+#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                
+#define RCC_BDCR_LSCOEN_Pos                  (24U)                             
+#define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk               
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)                             
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk              
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                    (0U)                              
+#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 
+#define RCC_CSR_LSIRDY_Pos                   (1U)                              
+#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                
+
+#define RCC_CSR_MSISRANGE_Pos                (8U)                              
+#define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk             
+#define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos                     (23U)                             
+#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  
+#define RCC_CSR_FWRSTF_Pos                   (24U)                             
+#define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk                
+#define RCC_CSR_OBLRSTF_Pos                  (25U)                             
+#define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk               
+#define RCC_CSR_PINRSTF_Pos                  (26U)                             
+#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               
+#define RCC_CSR_BORRSTF_Pos                  (27U)                             
+#define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk               
+#define RCC_CSR_SFTRSTF_Pos                  (28U)                             
+#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+#define RCC_CRRCR_HSI48ON_Pos                (0U)                              
+#define RCC_CRRCR_HSI48ON_Msk                (0x1U << RCC_CRRCR_HSI48ON_Pos)   /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk             
+#define RCC_CRRCR_HSI48RDY_Pos               (1U)                              
+#define RCC_CRRCR_HSI48RDY_Msk               (0x1U << RCC_CRRCR_HSI48RDY_Pos)  /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk            
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos               (7U)                             
+#define RCC_CRRCR_HSI48CAL_Msk               (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
+#define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_1                 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_2                 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+#define RCC_CRRCR_HSI48CAL_3                 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
+#define RCC_CRRCR_HSI48CAL_4                 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
+#define RCC_CRRCR_HSI48CAL_5                 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
+#define RCC_CRRCR_HSI48CAL_6                 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
+#define RCC_CRRCR_HSI48CAL_7                 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
+#define RCC_CRRCR_HSI48CAL_8                 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)                                   
+#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk                           
+#define RTC_TR_HT_Pos                  (20U)                                   
+#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk                           
+#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)                                   
+#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk                           
+#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)                                   
+#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          
+#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)                                    
+#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          
+#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)                                    
+#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk                           
+#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)                                    
+#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk                           
+#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)                                   
+#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk                           
+#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)                                   
+#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk                           
+#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)                                   
+#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          
+#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)                                   
+#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk                           
+#define RTC_DR_MU_Pos                  (8U)                                    
+#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk                           
+#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)                                    
+#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk                           
+#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)                                    
+#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk                           
+#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)                                   
+#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         
+#define RTC_CR_COE_Pos                 (23U)                                   
+#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk                          
+#define RTC_CR_OSEL_Pos                (21U)                                   
+#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         
+#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)                                   
+#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk                          
+#define RTC_CR_COSEL_Pos               (19U)                                   
+#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos               (17U)                                   
+#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        
+#define RTC_CR_ADD1H_Pos               (16U)                                   
+#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        
+#define RTC_CR_TSIE_Pos                (15U)                                   
+#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         
+#define RTC_CR_WUTIE_Pos               (14U)                                   
+#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        
+#define RTC_CR_ALRBIE_Pos              (13U)                                   
+#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       
+#define RTC_CR_ALRAIE_Pos              (12U)                                   
+#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       
+#define RTC_CR_TSE_Pos                 (11U)                                   
+#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          
+#define RTC_CR_WUTE_Pos                (10U)                                   
+#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         
+#define RTC_CR_ALRBE_Pos               (9U)                                    
+#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        
+#define RTC_CR_ALRAE_Pos               (8U)                                    
+#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        
+#define RTC_CR_FMT_Pos                 (6U)                                    
+#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          
+#define RTC_CR_BYPSHAD_Pos             (5U)                                    
+#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      
+#define RTC_CR_REFCKON_Pos             (4U)                                    
+#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      
+#define RTC_CR_TSEDGE_Pos              (3U)                                    
+#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       
+#define RTC_CR_WUCKSEL_Pos             (0U)                                    
+#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      
+#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)                                   
+#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        
+#define RTC_ISR_RECALPF_Pos            (16U)                                   
+#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     
+#define RTC_ISR_TAMP2F_Pos             (14U)                                   
+#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      
+#define RTC_ISR_TSOVF_Pos              (12U)                                   
+#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       
+#define RTC_ISR_TSF_Pos                (11U)                                   
+#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         
+#define RTC_ISR_WUTF_Pos               (10U)                                   
+#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        
+#define RTC_ISR_ALRBF_Pos              (9U)                                    
+#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       
+#define RTC_ISR_ALRAF_Pos              (8U)                                    
+#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       
+#define RTC_ISR_INIT_Pos               (7U)                                    
+#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        
+#define RTC_ISR_INITF_Pos              (6U)                                    
+#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       
+#define RTC_ISR_RSF_Pos                (5U)                                    
+#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         
+#define RTC_ISR_INITS_Pos              (4U)                                    
+#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       
+#define RTC_ISR_SHPF_Pos               (3U)                                    
+#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        
+#define RTC_ISR_WUTWF_Pos              (2U)                                    
+#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       
+#define RTC_ISR_ALRBWF_Pos             (1U)                                    
+#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      
+#define RTC_ISR_ALRAWF_Pos             (0U)                                    
+#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
+#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   
+#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)                                    
+#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     
+#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    
+#define RTC_ALRMAR_DT_Pos              (28U)                                   
+#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       
+#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)                                   
+#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       
+#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     
+#define RTC_ALRMAR_PM_Pos              (22U)                                   
+#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       
+#define RTC_ALRMAR_HT_Pos              (20U)                                   
+#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       
+#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)                                   
+#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       
+#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     
+#define RTC_ALRMAR_MNT_Pos             (12U)                                   
+#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      
+#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)                                    
+#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      
+#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     
+#define RTC_ALRMAR_ST_Pos              (4U)                                    
+#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       
+#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)                                    
+#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       
+#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     
+#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    
+#define RTC_ALRMBR_DT_Pos              (28U)                                   
+#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       
+#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)                                   
+#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       
+#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     
+#define RTC_ALRMBR_PM_Pos              (22U)                                   
+#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       
+#define RTC_ALRMBR_HT_Pos              (20U)                                   
+#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       
+#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)                                   
+#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       
+#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     
+#define RTC_ALRMBR_MNT_Pos             (12U)                                   
+#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      
+#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)                                    
+#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      
+#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     
+#define RTC_ALRMBR_ST_Pos              (4U)                                    
+#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       
+#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)                                    
+#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       
+#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)                                    
+#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)                                    
+#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    
+#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
+#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)                                   
+#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         
+#define RTC_TSTR_HT_Pos                (20U)                                   
+#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         
+#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)                                   
+#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         
+#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)                                   
+#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        
+#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)                                    
+#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        
+#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)                                    
+#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         
+#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)                                    
+#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         
+#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)                                   
+#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        
+#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)                                   
+#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         
+#define RTC_TSDR_MU_Pos                (8U)                                    
+#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         
+#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)                                    
+#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         
+#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)                                    
+#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         
+#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)                                    
+#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)                                   
+#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       
+#define RTC_CALR_CALW8_Pos             (14U)                                   
+#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      
+#define RTC_CALR_CALW16_Pos            (13U)                                   
+#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     
+#define RTC_CALR_CALM_Pos              (0U)                                    
+#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       
+#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  
+#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
+#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)                                    
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
+#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
+
+/********************  Bits definition for RTC_0R register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)                                    
+#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)                                    
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk                           
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)                                    
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk                           
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)                                    
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk                           
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)                                    
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk                           
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)                                    
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk                           
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)                                    
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk                           
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)                                    
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk                           
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)                                    
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk                           
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)                                    
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk                           
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)                                    
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk                           
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)                                    
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk                          
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)                                    
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk                          
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)                                    
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk                          
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)                                    
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk                          
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)                                    
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk                          
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)                                    
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk                          
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)                                    
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk                          
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)                                    
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk                          
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)                                    
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk                          
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)                                    
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk                          
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)                                    
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk                          
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)                                    
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk                          
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)                                    
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk                          
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)                                    
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk                          
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)                                    
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk                          
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)                                    
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk                          
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)                                    
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk                          
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)                                    
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk                          
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)                                    
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk                          
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)                                    
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk                          
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)                                    
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk                          
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)                                    
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk                          
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       32U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos         (0U)                                          
+#define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */
+#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos         (1U)                                          
+#define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */
+#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos         (2U)                                          
+#define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */
+#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos           (3U)                                          
+#define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */
+#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */
+#define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */
+#define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos          (6U)                                          
+#define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */
+#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos     (7U)                                          
+#define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos          (8U)                                          
+#define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */
+#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos          (9U)                                          
+#define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */
+#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos       (10U)                                         
+#define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */
+#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos         (11U)                                         
+#define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */
+#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos      (12U)                                         
+#define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos        (13U)                                         
+#define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */
+#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos       (14U)                                         
+#define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos     (15U)                                         
+#define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos      (0U)                                          
+#define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos      (1U)                                          
+#define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos         (2U)                                          
+#define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */
+#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos         (3U)                                          
+#define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */
+#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos          (4U)                                          
+#define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */
+#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos        (5U)                                          
+#define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */
+#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos       (6U)                                          
+#define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos        (7U)                                          
+#define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */
+#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos           (8U)                                          
+#define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */
+#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */
+#define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */
+#define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */
+#define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos        (12U)                                         
+#define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */
+#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos       (13U)                                         
+#define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */
+#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos       (14U)                                         
+#define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */
+#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos          (0U)                                          
+#define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */
+#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos           (1U)                                          
+#define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */
+#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos        (2U)                                          
+#define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */
+#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
+#define SPI_SR_UDR_Pos           (3U)                                          
+#define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */
+#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos        (4U)                                          
+#define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */
+#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos          (5U)                                          
+#define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */
+#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
+#define SPI_SR_OVR_Pos           (6U)                                          
+#define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */
+#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
+#define SPI_SR_BSY_Pos           (7U)                                          
+#define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */
+#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
+#define SPI_SR_FRE_Pos           (8U)                                          
+#define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */
+#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos         (9U)                                          
+#define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */
+#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos         (11U)                                         
+#define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */
+#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos            (0U)                                          
+#define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */
+#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos    (0U)                                          
+#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos     (0U)                                          
+#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos     (0U)                                          
+#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos              (0U)                                    
+#define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */
+#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos           (1U)                                    
+#define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos           (2U)                                    
+#define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos            (3U)                                    
+#define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos          (4U)                                    
+#define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
+#define QUADSPI_CR_DFM_Pos             (6U)                                    
+#define QUADSPI_CR_DFM_Msk             (0x1U << QUADSPI_CR_DFM_Pos)            /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
+#define QUADSPI_CR_FSEL_Pos            (7U)                                    
+#define QUADSPI_CR_FSEL_Msk            (0x1U << QUADSPI_CR_FSEL_Pos)           /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
+#define QUADSPI_CR_FTHRES_Pos          (8U)                                    
+#define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos            (16U)                                   
+#define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos            (17U)                                   
+#define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos            (18U)                                   
+#define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos            (19U)                                   
+#define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos            (20U)                                   
+#define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos            (22U)                                   
+#define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos             (23U)                                   
+#define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos       (24U)                                   
+#define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos         (0U)                                    
+#define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos           (8U)                                    
+#define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos          (16U)                                   
+#define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos             (0U)                                    
+#define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos             (1U)                                    
+#define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos             (2U)                                    
+#define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos             (3U)                                    
+#define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos             (4U)                                    
+#define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos            (5U)                                    
+#define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos          (8U)                                    
+#define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos           (0U)                                    
+#define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos           (1U)                                    
+#define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos           (3U)                                    
+#define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos           (4U)                                    
+#define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos             (0U)                                    
+#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)                                    
+#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos          (8U)                                    
+#define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos         (10U)                                   
+#define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos         (12U)                                   
+#define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos         (14U)                                   
+#define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos         (16U)                                   
+#define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos           (18U)                                   
+#define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos          (24U)                                   
+#define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos          (26U)                                   
+#define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos           (28U)                                   
+#define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos           (30U)                                   
+#define QUADSPI_CCR_DHHC_Msk           (0x1U << QUADSPI_CCR_DHHC_Pos)          /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
+#define QUADSPI_CCR_DDRM_Pos           (31U)                                   
+#define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos         (0U)                                    
+#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos      (0U)                                    
+#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos            (0U)                                    
+#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos         (0U)                                    
+#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos        (0U)                                    
+#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos       (0U)                                    
+#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)                                    
+#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */
+
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos          (0U)                                   
+#define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)                                   
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)                                  
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)                                  
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)                                  
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)                                  
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7U << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7U << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7U << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7U << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7U << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7U << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7U << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7U << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7U << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7U << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7U << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7U << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)                                   
+#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)                                   
+#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos            (0U)                                   
+#define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos            (1U)                                   
+#define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)                                   
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)                                   
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos            (8U)                                   
+#define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos           (0U)                                   
+#define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos           (1U)                                   
+#define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos           (2U)                                   
+#define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos           (3U)                                   
+#define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos           (4U)                                   
+#define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos           (5U)                                   
+#define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos           (6U)                                   
+#define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos           (7U)                                   
+#define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos           (8U)                                   
+#define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos           (9U)                                   
+#define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos          (10U)                                  
+#define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos          (11U)                                  
+#define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos          (12U)                                  
+#define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos          (13U)                                  
+#define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos          (14U)                                  
+#define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos          (15U)                                  
+#define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos              (0U)                                   
+#define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)                                        
+#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM1_OR1 register  *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)                                    
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM1_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM1_OR2 register  *******************/
+#define TIM1_OR2_BKINE_Pos             (0U)                                    
+#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKINP_Pos             (9U)                                    
+#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM1_OR3 register  *******************/
+#define TIM1_OR3_BK2INE_Pos            (0U)                                    
+#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2INP_Pos            (9U)                                    
+#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+
+/*******************  Bit definition for TIM2_OR1 register  *******************/
+#define TIM2_OR1_ITR1_RMP_Pos     (0U)                                         
+#define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos     (1U)                                         
+#define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos      (2U)                                         
+#define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM2_OR2 register  *******************/
+#define TIM2_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+
+/*******************  Bit definition for TIM15_OR1 register  ******************/
+#define TIM15_OR1_TI1_RMP_Pos           (0U)                                   
+#define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos      (1U)                                   
+#define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM15_OR2 register  ******************/
+#define TIM15_OR2_BKINE_Pos             (0U)                                   
+#define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */
+#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos           (1U)                                   
+#define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos           (2U)                                   
+#define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKINP_Pos             (9U)                                   
+#define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */
+#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos           (10U)                                  
+#define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos           (11U)                                  
+#define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_OR1 register  ******************/
+#define TIM16_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM16_OR1_TI1_RMP_Msk      (0x7U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000007 */
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+#define TIM16_OR1_TI1_RMP_2        (0x4U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM16_OR2 register  ******************/
+#define TIM16_OR2_BKINE_Pos        (0U)                                        
+#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKINP_Pos        (9U)                                        
+#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)                                       
+#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)                                       
+#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
+#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)                                       
+#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)                                       
+#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)                                       
+#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
+#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
+#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
+#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)                                       
+#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
+#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
+#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
+#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
+#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
+#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)                                       
+#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
+#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
+#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
+#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
+#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
+#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
+#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)                                      
+#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)                                       
+#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
+#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
+#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)                                       
+#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)                                       
+#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)                                       
+#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  ********************/
+#define LPTIM_OR_OR_Pos             (0U)                                       
+#define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */
+#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
+#define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos            (0U)                                        
+#define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos       (2U)                                        
+#define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos        (4U)                                        
+#define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos        (7U)                                        
+#define COMP_CSR_INPSEL_Msk        (0x3U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000180 */
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+#define COMP_CSR_INPSEL_1          (0x2U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000100 */
+
+#define COMP_CSR_WINMODE_Pos       (9U)                                        
+#define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */
+#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_POLARITY_Pos      (15U)                                       
+#define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos          (16U)                                       
+#define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */
+#define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos      (18U)                                       
+#define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos         (22U)                                       
+#define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos        (23U)                                       
+#define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_INMESEL_Pos       (25U)                                       
+#define COMP_CSR_INMESEL_Msk       (0x3U << COMP_CSR_INMESEL_Pos)              /*!< 0x06000000 */
+#define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
+#define COMP_CSR_INMESEL_0         (0x1U << COMP_CSR_INMESEL_Pos)              /*!< 0x02000000 */
+#define COMP_CSR_INMESEL_1         (0x2U << COMP_CSR_INMESEL_Pos)              /*!< 0x04000000 */
+
+#define COMP_CSR_VALUE_Pos         (30U)                                       
+#define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos          (31U)                                       
+#define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)                                  
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos             (1U)                                  
+#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos            (2U)                                  
+#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (4U)                                  
+#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos              (8U)                                  
+#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos              (10U)                                 
+#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos              (12U)                                 
+#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos             (13U)                                 
+#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos           (14U)                                 
+#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos             (15U)                                 
+#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos              (12U)                                
+#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)                                
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)                                  
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)                                  
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+*/
+#define USART_TCBGT_SUPPORT
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TCBGTIE_Pos         (24U)                                    
+#define USART_CR3_TCBGTIE_Msk         (0x1U << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TCBGT_Pos           (25U)                                    
+#define USART_ISR_TCBGT_Msk           (0x1U << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
+#define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos         (7U)                                     
+#define USART_ICR_TCBGTCF_Msk         (0x1U << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)                                          
+#define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)                                          
+#define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)                                          
+#define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)                                          
+#define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)                                          
+#define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)                                          
+#define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)                                         
+#define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)                                          
+#define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)                                          
+#define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)                                          
+#define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)                                          
+#define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)                                          
+#define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)                                          
+#define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)                                          
+#define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)                                          
+#define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)                                          
+#define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)                                          
+#define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)                                          
+#define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)                                         
+#define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)                                          
+#define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)                                          
+#define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)                                          
+#define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)                                          
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)                                          
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)                                          
+#define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)                                          
+#define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_SRIE_Pos       (8U)                                          
+#define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_TCIE_Pos       (7U)                                          
+#define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_TIE_Pos        (6U)                                          
+#define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_RIE_Pos        (5U)                                          
+#define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)                                          
+#define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)                                          
+#define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)                                          
+#define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_TXBEIE_Pos     (1U)                                          
+#define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBFIE_Pos     (0U)                                          
+#define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)                                          
+#define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1_Pos    (0U)                                          
+#define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */
+#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)                                          
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)                                          
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)                                          
+#define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)                                          
+#define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)                            
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk        
+
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)                            
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk        
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)                           
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)                           
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)                           
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)                           
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)                           
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)                            
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)                           
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)                           
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)                           
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device FS Endpoint registers                   */
+/*                                                                            */
+/******************************************************************************/
+#define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
+#define USB_EP1R                             (USB_BASE + 0x0x00000004)   /*!< endpoint 1 register address */
+#define USB_EP2R                             (USB_BASE + 0x0x00000008)   /*!< endpoint 2 register address */
+#define USB_EP3R                             (USB_BASE + 0x0x0000000C)   /*!< endpoint 3 register address */
+#define USB_EP4R                             (USB_BASE + 0x0x00000010)   /*!< endpoint 4 register address */
+#define USB_EP5R                             (USB_BASE + 0x0x00000014)   /*!< endpoint 5 register address */
+#define USB_EP6R                             (USB_BASE + 0x0x00000018)   /*!< endpoint 6 register address */
+#define USB_EP7R                             (USB_BASE + 0x0x0000001C)   /*!< endpoint 7 register address */
+
+/* bit positions */ 
+#define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
+#define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
+#define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
+#define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
+#define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
+#define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+                                                                 
+#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
+                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device FS General registers                    */
+/*                                                                            */
+/******************************************************************************/
+#define USB_CNTR                             (USB_BASE + 0x00000040U)     /*!< Control register */
+#define USB_ISTR                             (USB_BASE + 0x00000044U)     /*!< Interrupt status register */
+#define USB_FNR                              (USB_BASE + 0x00000048U)     /*!< Frame number register */
+#define USB_DADDR                            (USB_BASE + 0x0000004CU)     /*!< Device address register */
+#define USB_BTABLE                           (USB_BASE + 0x00000050U)     /*!< Buffer Table address register */
+#define USB_LPMCSR                           (USB_BASE + 0x00000054U)     /*!< LPM Control and Status register */
+#define USB_BCDR                             (USB_BASE + 0x00000058U)     /*!< Battery Charging detector register*/
+
+/******************  Bits definition for USB_CNTR register  *******************/
+#define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
+#define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
+#define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
+#define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
+#define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
+#define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
+#define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
+#define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
+
+/******************  Bits definition for USB_ISTR register  *******************/
+#define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
+#define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
+#define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
+#define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
+#define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
+#define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
+
+#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
+#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
+#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
+#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
+#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
+#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
+#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
+
+/******************  Bits definition for USB_FNR register  ********************/
+#define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
+#define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
+#define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
+#define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
+#define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
+
+/******************  Bits definition for USB_DADDR register    ****************/
+#define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
+#define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
+#define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
+#define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
+#define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
+#define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
+#define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
+
+#define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/
+#define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
+
+/******************  Bits definition for USB_BCDR register  *******************/
+#define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
+#define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */  
+#define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */ 
+#define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */ 
+#define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */ 
+#define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */  
+#define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */  
+#define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */  
+
+/*******************  Bit definition for LPMCSR register  *********************/
+#define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
+#define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */ 
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)                          
+#define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)                          
+#define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)                          
+#define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)                          
+#define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)                          
+#define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)                          
+#define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)                          
+#define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)                          
+#define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)                          
+#define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)                          
+#define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)                          
+#define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)                          
+#define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)                          
+#define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)                          
+#define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)                          
+#define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)                          
+#define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)                          
+#define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)                          
+#define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)                          
+#define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)                          
+#define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)                          
+#define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)                          
+#define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)                          
+#define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)                          
+#define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)                          
+#define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0                (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1                (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2                (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3                (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4                (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT0_RX_BLSIZE_Msk                 (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)                          
+#define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0                (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1                (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2                (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3                (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4                (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT1_RX_BLSIZE_Msk                 (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)                          
+#define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0                (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1                (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2                (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3                (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4                (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT2_RX_BLSIZE_Msk                 (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)                          
+#define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0                (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1                (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2                (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3                (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4                (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT3_RX_BLSIZE_Msk                 (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)                          
+#define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0                (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1                (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2                (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3                (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4                (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT4_RX_BLSIZE_Msk                 (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)                          
+#define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0                (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1                (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2                (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3                (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4                (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT5_RX_BLSIZE_Msk                 (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)                          
+#define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0                (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1                (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2                (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3                (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4                (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT6_RX_BLSIZE_Msk                 (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)                          
+#define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)                         
+#define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0                (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1                (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2                (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3                (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4                (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos                 (15U)                         
+#define USB_COUNT7_RX_BLSIZE_Msk                 (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                                       ((INSTANCE) == SAI1_Block_B))
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                          ((INSTANCE) == TIM2))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2))
+      
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM15) || \
+                                            ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn                    ADC1_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn        TIM1_TRG_COM_IRQn
+#define HASH_RNG_IRQn                  RNG_IRQn
+#define HASH_CRS_IRQn                  CRS_IRQn
+#define USB_FS_IRQn                    USB_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler              ADC1_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define HASH_RNG_IRQHandler            RNG_IRQHandler
+#define HASH_CRS_IRQHandler            CRS_IRQHandler
+#define USB_FS_IRQHandler              USB_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L432xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h
new file mode 100755
index 0000000..3a13587
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h
@@ -0,0 +1,240 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral�s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+#define STM32L432xx           /*!< STM32L432xx Devices */
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  /* #define STM32L486xx */   /*!< STM32L486xx Devices */
+  /* #define STM32L496xx */   /*!< STM32L496xx Devices */
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.3.1
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h
new file mode 100755
index 0000000..3f229fa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h
@@ -0,0 +1,127 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16];     /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h
new file mode 100755
index 0000000..ece5f16
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h
new file mode 100755
index 0000000..77a1a05
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PB_6
+#define STDIO_UART_RX  PB_7
+#define STDIO_UART     UART_1
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c
new file mode 100755
index 0000000..0241152
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c
@@ -0,0 +1,337 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ARDUINO D1
+    {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ARDUINO D1
+    {PA_1,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ARDUINO D0
+    {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ARDUINO D0
+    {PA_2,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ARDUINO D10
+    {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ARDUINO D10
+    {PA_3,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ARDUINO D4
+    {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ARDUINO D4
+    {PA_4,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ARDUINO D7
+    {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ARDUINO D7
+    {PA_5,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ARDUINO D13 - Connected to LED1
+    {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ARDUINO D13 - Connected to LED1
+    {PA_6,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ARDUINO D12
+    {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ARDUINO D12
+    {PA_7,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ARDUINO D11
+    {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ARDUINO D11
+    {PB_0,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ARDUINO D3
+    {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ARDUINO D3
+    {PB_1,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ARDUINO D6
+    {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ARDUINO D6
+    {PC_0,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ARDUINO A5
+    {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ARDUINO A5
+    {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ARDUINO A5
+    {PC_1,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ARDUINO A4
+    {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ARDUINO A4
+    {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ARDUINO A4
+    {PC_2,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ARDUINO A3
+    {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ARDUINO A3
+    {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ARDUINO A3
+    {PC_3,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ARDUINO A2
+    {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ARDUINO A2
+    {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ARDUINO A2
+    {PC_4,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ARDUINO A1
+    {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ARDUINO A1
+    {PC_5,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ARDUINO A0
+    {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ARDUINO A0
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 18, 0)},
+    {NC,       NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ARDUINO D7
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ARDUINO D13 - Connected to LED1
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+//    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Pin not available on any connector
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Pin not available on any connector
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED2
+    {PC_1,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO A4
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+//    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Pin not available on any connector
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D15
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Pin not available on any connector
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Pin not available on any connector
+    {PC_0,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO A5
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// Warning: Pins using PWM_5 cannot be used as TIMER5 is already used by the us_ticker.
+const PinMap PinMap_PWM[] = {
+    {PA_0,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // ARDUINO D1
+//  {PA_0,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 ARDUINO D1
+    {PA_1,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 ARDUINO D0
+    {PA_1_ALT0,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N ARDUINO D0
+//  {PA_1,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 ARDUINO D0
+    {PA_2,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 ARDUINO D10
+    {PA_2_ALT0,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 ARDUINO D10
+//  {PA_2,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 ARDUINO D10
+    {PA_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 ARDUINO D4
+    {PA_3_ALT0,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 ARDUINO D4
+//  {PA_3,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 ARDUINO D4
+    {PA_5,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 ARDUINO D13 - Connected to LED1
+    {PA_5_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N ARDUINO D13 - Connected to LED1
+    {PA_6,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 ARDUINO D12
+    {PA_6_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 ARDUINO D12
+    {PA_7,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N ARDUINO D11
+    {PA_7_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 ARDUINO D11
+    {PA_7_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N ARDUINO D11
+    {PA_7_ALT2,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 ARDUINO D11
+    {PA_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 Pin not available on any connector
+    {PA_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 Pin not available on any connector
+    {PA_10,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 Pin not available on any connector
+    {PA_11,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 Pin not available on any connector
+    {PA_15,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 ARDUINO D9
+    {PB_0,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 ARDUINO D3
+    {PB_0_ALT0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N ARDUINO D3
+    {PB_0_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N ARDUINO D3
+    {PB_1,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 ARDUINO D6
+    {PB_1_ALT0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N ARDUINO D6
+    {PB_1_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N ARDUINO D6
+    {PB_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 Pin not available on any connector
+    {PB_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 ARDUINO D5
+    {PB_5,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 Pin not available on any connector
+//    {PB_6,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 Pin not available on any connector
+//    {PB_6_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N Pin not available on any connector
+//    {PB_7,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 Pin not available on any connector
+//    {PB_7_ALT0,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N Pin not available on any connector
+    {PB_8,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 ARDUINO D15
+    {PB_8_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 ARDUINO D15
+    {PB_9,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 ARDUINO D14
+    {PB_9_ALT0,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 ARDUINO D14
+    {PB_10,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 Pin not available on any connector
+    {PB_11,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 Pin not available on any connector
+    {PB_13,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N Pin not available on any connector
+    {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N Pin not available on any connector
+    {PB_14,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - Connected to LED2
+    {PB_14_ALT0, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - Connected to LED2
+    {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 - Connected to LED2
+    {PB_15,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N Pin not available on any connector
+    {PB_15_ALT0, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N Pin not available on any connector
+    {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 Pin not available on any connector
+    {PC_6,       PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 Pin not available on any connector
+    {PC_6_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 Pin not available on any connector
+    {PC_7,       PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 Pin not available on any connector
+    {PC_7_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 Pin not available on any connector
+    {PC_8,       PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 Pin not available on any connector
+    {PC_8_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 Pin not available on any connector
+    {PC_9,       PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - Connected to LED3/LED4
+    {PC_9_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - Connected to LED3/LED4
+    {PD_12,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 Pin not available on any connector
+    {PD_13,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 Pin not available on any connector
+    {PD_14,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 ARDUINO D2
+    {PD_15,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 Pin not available on any connector
+    {PE_0,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 Pin not available on any connector
+    {PE_1,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 Pin not available on any connector
+    {PE_3,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 Pin not available on any connector
+    {PE_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 Pin not available on any connector
+    {PE_5,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 Pin not available on any connector
+    {PE_6,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 Pin not available on any connector
+    {PE_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N Pin not available on any connector
+    {PE_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 Pin not available on any connector
+    {PE_10,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N Pin not available on any connector
+    {PE_11,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 Pin not available on any connector
+    {PE_12,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N Pin not available on any connector
+    {PE_13,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 Pin not available on any connector
+    {PE_14,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 Pin not available on any connector
+    {NC,         NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO D1
+    {PA_2,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO D10
+    {PA_9,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector
+    {PB_6,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector - Connected to STDIO_UART_TX
+    {PB_10,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {PB_11,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Pin not available on any connector
+    {PC_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A4
+    {PC_4,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},  // ARDUINO A1
+    {PC_10,      UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Pin not available on any connector
+    {PC_10_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {PC_12,      UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Pin not available on any connector
+    {PD_5,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // PMOD 1
+    {PD_8,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {NC,         NC,       0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO D0
+    {PA_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO D4
+    {PA_10,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector
+    {PB_7,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector - Connected to STDIO_UART_RX
+    {PB_10,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Pin not available on any connector
+    {PB_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {PC_0,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A5
+    {PC_5,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},  // ARDUINO A0
+    {PC_11,      UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Pin not available on any connector
+    {PC_11_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {PD_2,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // PMOD 7
+    {PD_6,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Pin not available on any connector
+    {PD_9,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {NC,         NC,       0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO D0
+    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector
+    {PA_15, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO D9
+    {PB_1,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D6
+    {PB_3,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector
+    {PB_4,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // ARDUINO D5
+    {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Pin not available on any connector
+    {PB_14, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED2
+    {PD_2,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // PMOD 7
+    {PD_4,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // PMOD 2
+    {PD_12, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO D1
+    {PA_6,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D12
+    {PA_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector
+    {PB_4,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO D5
+    {PB_5,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Pin not available on any connector
+//    {PB_7,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Pin not available on any connector
+    {PB_13,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Pin not available on any connector
+    {PB_13_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {PD_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // PMOD 3
+    {PD_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
+    {NC,         NC,       0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+    {PB_5,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Pin not available on any connector
+    {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Pin not available on any connector
+    {PB_15,     SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Pin not available on any connector
+    {PC_3,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A2
+    {PC_12,     SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Pin not available on any connector
+    {PD_4,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // PMOD 2
+    {PE_15,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Pin not available on any connector
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+    {PB_4,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D5
+    {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO D5
+    {PB_14,     SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED2
+    {PC_2,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A3
+    {PC_11,     SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Pin not available on any connector
+    {PD_3,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // PMOD 3
+    {PE_14,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Pin not available on any connector
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13 - Connected to LED1
+    {PB_3,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Pin not available on any connector
+    {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Pin not available on any connector
+    {PB_10,     SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Pin not available on any connector
+    {PB_13,     SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Pin not available on any connector
+    {PC_10,     SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Pin not available on any connector
+    {PD_1,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // PMOD 4
+    {PE_13,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Pin not available on any connector
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D7
+    {PA_4_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO D7
+    {PA_15,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D9
+    {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO D9
+    {PB_9,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO D14
+    {PB_12,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Pin not available on any connector
+    {PD_0,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // PMOD 8
+    {PE_12,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Pin not available on any connector
+    {NC,         NC,    0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Pin not available on any connector
+    {PB_8,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D15
+    {PD_0,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // PMOD 8
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Pin not available on any connector
+    {PB_9,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D14
+    {PD_1,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // PMOD 4
+    {NC,    NC,    0}
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h
new file mode 100755
index 0000000..9c2ea68
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_0_ALT0 = PA_0|ALT0,
+    PA_1  = 0x01,
+    PA_1_ALT0 = PA_1|ALT0,
+    PA_2  = 0x02,
+    PA_2_ALT0 = PA_2|ALT0,
+    PA_3  = 0x03,
+    PA_3_ALT0 = PA_3|ALT0,
+    PA_4  = 0x04,
+    PA_4_ALT0 = PA_4|ALT0,
+    PA_5  = 0x05,
+    PA_5_ALT0 = PA_5|ALT0,
+    PA_6  = 0x06,
+    PA_6_ALT0 = PA_6|ALT0,
+    PA_7  = 0x07,
+    PA_7_ALT0 = PA_7|ALT0,
+    PA_7_ALT1 = PA_7|ALT1,
+    PA_7_ALT2 = PA_7|ALT2,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+    PA_15_ALT0 = PA_15|ALT0,
+
+    PB_0  = 0x10,
+    PB_0_ALT0 = PB_0|ALT0,
+    PB_0_ALT1 = PB_0|ALT1,
+    PB_1  = 0x11,
+    PB_1_ALT0 = PB_1|ALT0,
+    PB_1_ALT1 = PB_1|ALT1,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_3_ALT0 = PB_3|ALT0,
+    PB_4  = 0x14,
+    PB_4_ALT0 = PB_4|ALT0,
+    PB_5  = 0x15,
+    PB_5_ALT0 = PB_5|ALT0,
+    PB_6  = 0x16,
+    PB_6_ALT0 = PB_6|ALT0,
+    PB_7  = 0x17,
+    PB_7_ALT0 = PB_7|ALT0,
+    PB_8  = 0x18,
+    PB_8_ALT0 = PB_8|ALT0,
+    PB_9  = 0x19,
+    PB_9_ALT0 = PB_9|ALT0,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_13_ALT0 = PB_13|ALT0,
+    PB_14 = 0x1E,
+    PB_14_ALT0 = PB_14|ALT0,
+    PB_14_ALT1 = PB_14|ALT1,
+    PB_15 = 0x1F,
+    PB_15_ALT0 = PB_15|ALT0,
+    PB_15_ALT1 = PB_15|ALT1,
+
+    PC_0  = 0x20,
+    PC_0_ALT0 = PC_0|ALT0,
+    PC_0_ALT1 = PC_0|ALT1,
+    PC_1  = 0x21,
+    PC_1_ALT0 = PC_1|ALT0,
+    PC_1_ALT1 = PC_1|ALT1,
+    PC_2  = 0x22,
+    PC_2_ALT0 = PC_2|ALT0,
+    PC_2_ALT1 = PC_2|ALT1,
+    PC_3  = 0x23,
+    PC_3_ALT0 = PC_3|ALT0,
+    PC_3_ALT1 = PC_3|ALT1,
+    PC_4  = 0x24,
+    PC_4_ALT0 = PC_4|ALT0,
+    PC_5  = 0x25,
+    PC_5_ALT0 = PC_5|ALT0,
+    PC_6  = 0x26,
+    PC_6_ALT0 = PC_6|ALT0,
+    PC_7  = 0x27,
+    PC_7_ALT0 = PC_7|ALT0,
+    PC_8  = 0x28,
+    PC_8_ALT0 = PC_8|ALT0,
+    PC_9  = 0x29,
+    PC_9_ALT0 = PC_9|ALT0,
+    PC_10 = 0x2A,
+    PC_10_ALT0 = PC_10|ALT0,
+    PC_11 = 0x2B,
+    PC_11_ALT0 = PC_11|ALT0,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_0  = 0x30,
+    PD_1  = 0x31,
+    PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48,
+    PE_9  = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Arduino connector namings
+    A0          = PC_5,
+    A1          = PC_4,
+    A2          = PC_3,
+    A3          = PC_2,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_1,
+    D1          = PA_0,
+    D2          = PD_14,
+    D3          = PB_0,
+    D4          = PA_3,
+    D5          = PB_4,
+    D6          = PB_1,
+    D7          = PA_4,
+    D8          = PB_2,
+    D9          = PA_15,
+    D10         = PA_2,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = D13, // Green LED (LD1)
+    LED2        = PB_14, // Green LED (LD2)
+    LED3        = PC_9, // Yellow LED (LD3 WIFI) / Blue LED (LD4 BLE)
+    LED4        = LED3,
+    USER_BUTTON = PC_13,
+    BUTTON1     = USER_BUTTON,
+    BUTTON2     = USER_BUTTON,
+    BUTTON3     = USER_BUTTON,
+    BUTTON4     = USER_BUTTON,
+    BUTTON5     = USER_BUTTON,
+    SERIAL_TX   = PB_6,
+    SERIAL_RX   = PB_7,
+    USBTX       = SERIAL_TX,
+    USBRX       = SERIAL_RX,
+    I2C_SCL     = D15,
+    I2C_SDA     = D14,
+    SPI_MOSI    = D11,
+    SPI_MISO    = D12,
+    SPI_SCK     = D13,
+    SPI_CS      = D10,
+    PWM_OUT     = D9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c
new file mode 100755
index 0000000..ee5ac4b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l475xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l475xx.S
new file mode 100755
index 0000000..da45365
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l475xx.S
@@ -0,0 +1,406 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l475xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.2.0
+;* Date               : 28-October-2016
+;* Description        : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+__initial_sp    EQU     0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler)
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved                
+                DCD     0                                 ; Reserved                
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/stm32l475xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/stm32l475xx.sct
new file mode 100755
index 0000000..a657759
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/stm32l475xx.sct
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1 0x20000000 0x00018000  { ; RW data 96k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM2 (0x10000000+0x188) (0x08000-0x188)  {  ; RW data 32k L4-ECC-SRAM2 retained in standby
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S
new file mode 100755
index 0000000..f897a1f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S
@@ -0,0 +1,388 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l475xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.2.0
+;* Date               : 28-October-2016
+;* Description        : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+__initial_sp    EQU     0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved                
+                DCD     0                                 ; Reserved                
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct
new file mode 100755
index 0000000..a657759
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1 0x20000000 0x00018000  { ; RW data 96k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM2 (0x10000000+0x188) (0x08000-0x188)  {  ; RW data 32k L4-ECC-SRAM2 retained in standby
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld
new file mode 100755
index 0000000..ee23416
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld
@@ -0,0 +1,162 @@
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 1024k
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
+  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > SRAM1
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > SRAM1
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > SRAM1
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM1
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S
new file mode 100755
index 0000000..0794ce3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S
@@ -0,0 +1,510 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l475xx.s
+  * @author    MCD Application Team
+  * @version   V1.2.0
+  * @date      28-October-2016
+  * @brief     STM32L475xx devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before 
+  // starting main(). software_init_hook() is available and has to be called due 
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	TAMP_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	CAN1_TX_IRQHandler
+	.word	CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	DFSDM1_FLT3_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC3_IRQHandler
+	.word	FMC_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	DFSDM1_FLT0_IRQHandler
+	.word	DFSDM1_FLT1_IRQHandler
+	.word	DFSDM1_FLT2_IRQHandler
+	.word	COMP_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	OTG_FS_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	QUADSPI_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	SWPMI1_IRQHandler
+	.word	TSC_IRQHandler
+	.word 0
+	.word 0
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_IRQHandler
+	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT3_IRQHandler
+	.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC3_IRQHandler
+	.thumb_set ADC3_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT0_IRQHandler
+	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT1_IRQHandler
+	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT2_IRQHandler
+	.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler	
+	
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+	
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+	
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler	
+	
+	.weak	OTG_FS_IRQHandler
+	.thumb_set OTG_FS_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler	
+	
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler	
+	
+	.weak	QUADSPI_IRQHandler
+	.thumb_set QUADSPI_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler	
+	
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+	
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+	
+	.weak	SWPMI1_IRQHandler
+	.thumb_set SWPMI1_IRQHandler,Default_Handler
+	
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+	
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/startup_stm32l475xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/startup_stm32l475xx.S
new file mode 100755
index 0000000..63361dd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/startup_stm32l475xx.S
@@ -0,0 +1,632 @@
+;/********************* COPYRIGHT(c) 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l475xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.2.0
+;* Date               : 28-October-2016
+;* Description        : STM32L475xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved        
+        DCD     0                                 ; Reserved        
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+        B ADC3_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf
new file mode 100755
index 0000000..15c4254
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf
@@ -0,0 +1,38 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__     = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 96kb + 32kb = 0x20000] */
+/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x10000000;
+define symbol __NVIC_end__            = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM2_start__  = 0x10000188;
+define symbol __region_SRAM2_end__    = 0x10007FFF;
+define symbol __region_SRAM1_start__  = 0x20000000;
+define symbol __region_SRAM1_end__    = 0x20017FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+/* Stack 1/8 and Heap 1/4 of RAM */
+define symbol __size_cstack__ = 0x8000;
+define symbol __size_heap__   = 0xa000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in SRAM1_region   { readwrite, block STACKHEAP };
+place in SRAM2_region { };
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/cmsis.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/cmsis.h
new file mode 100755
index 0000000..3a1c222
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l4xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/cmsis_nvic.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/cmsis_nvic.h
new file mode 100755
index 0000000..e4d724b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/cmsis_nvic.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
+// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+#define NVIC_NUM_VECTORS        98
+#define NVIC_RAM_VECTOR_ADDRESS 0x10000000    // Vectors positioned at start of SRAM2
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h
new file mode 100755
index 0000000..11cd6c1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h
new file mode 100755
index 0000000..834eb2d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h
@@ -0,0 +1,18379 @@
+/**
+  ******************************************************************************
+  * @file    stm32l475xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L475xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32l475xx
+  * @{
+  */
+
+#ifndef __STM32L475xx_H
+#define __STM32L475xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
+  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
+  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
+  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
+  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
+  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
+                                  short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef  DMA_Request_TypeDef
+
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+  * @brief Firewall
+  */
+
+typedef struct
+{
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+       uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
+  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
+  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
+  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
+  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+  __IO uint32_t ASCR;        /*!< GPIO analog switch control register,   Address offset: 0x2C     */
+
+} GPIO_TypeDef;
+
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */
+  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
+  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */
+  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
+  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;    /*!< Reserved  */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
+  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
+} SYSCFG_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/
+  uint32_t Reserved30[2];             /* Reserved                                        030h*/
+  __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/
+  __IO uint32_t CID;                  /* User ID Register                                03Ch*/
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                 040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                 044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                 048h*/
+  __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/
+  uint32_t  Reserved6;                /* Reserved                                        050h*/ 
+  __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/
+  __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/
+  __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/
+   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/
+    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/
+  __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/
+  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/
+  __IO uint32_t DCTL;        /* dev Control Register         804h*/
+  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/
+  uint32_t Reserved0C;       /* Reserved                     80Ch*/
+  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/
+  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/
+  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/
+  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/
+  uint32_t  Reserved20;      /* Reserved                     820h*/
+  uint32_t Reserved9;        /* Reserved                     824h*/
+  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
+  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
+  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
+  __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/
+  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
+  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
+  uint32_t Reserved40;       /* dedicated EP mask           840h*/
+  __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/
+  uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/   
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
+  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;      /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
+#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */
+#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
+
+#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */
+#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE         ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
+#define SRAM2_SIZE            ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+
+#define FMC_BANK1             FMC_BASE
+#define FMC_BANK1_1           FMC_BANK1
+#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)
+#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)
+#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)
+#define FMC_BANK3             (FMC_BASE  + 0x20000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
+
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
+
+#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)
+#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)
+#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)
+
+
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
+
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)
+
+#define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)
+#define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)
+#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)
+#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)
+#define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)
+#define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)
+#define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)
+#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)
+#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)
+#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)
+#define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)
+#define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)
+
+
+#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
+#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+//#define CAN                 ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+/* Aliases to keep compatibility after DFSDM renaming */
+#define DFSDM_Channel0      DFSDM1_Channel0
+#define DFSDM_Channel1      DFSDM1_Channel1
+#define DFSDM_Channel2      DFSDM1_Channel2
+#define DFSDM_Channel3      DFSDM1_Channel3
+#define DFSDM_Channel4      DFSDM1_Channel4
+#define DFSDM_Channel5      DFSDM1_Channel5
+#define DFSDM_Channel6      DFSDM1_Channel6
+#define DFSDM_Channel7      DFSDM1_Channel7
+#define DFSDM_Filter0       DFSDM1_Filter0
+#define DFSDM_Filter1       DFSDM1_Filter1
+#define DFSDM_Filter2       DFSDM1_Filter2
+#define DFSDM_Filter3       DFSDM1_Filter3
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)                                    
+#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)                                    
+#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)                                    
+#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)                                    
+#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)                                    
+#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)                                    
+#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)                                    
+#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)                                    
+#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)                                    
+#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)                                    
+#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)                                   
+#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)                                    
+#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)                                    
+#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)                                    
+#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)                                    
+#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)                                    
+#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)                                    
+#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)                                    
+#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)                                    
+#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)                                    
+#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)                                    
+#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)                                   
+#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)                                    
+#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)                                    
+#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)                                    
+#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)                                    
+#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)                                    
+#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)                                    
+#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)                                   
+#define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos             (29U)                                   
+#define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)                                   
+#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)                                   
+#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)                                    
+#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)                                    
+#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)                                    
+#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos             (5U)                                    
+#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos            (6U)                                    
+#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)                                   
+#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)                                   
+#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)                                   
+#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)                                   
+#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos            (16U)                                   
+#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)                                   
+#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)                                   
+#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos               (21U)                                   
+#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)                                   
+#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)                                   
+#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)                                   
+#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)                                   
+#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)                                   
+#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos             (31U)                                   
+#define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)                                    
+#define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)                                    
+#define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos             (2U)                                    
+#define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)                                    
+#define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)                                    
+#define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)                                   
+#define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)                                    
+#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)                                    
+#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)                                    
+#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)                                    
+#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)                                   
+#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)                                   
+#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)                                   
+#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)                                   
+#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)                                   
+#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)                                   
+#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)                                    
+#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)                                    
+#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)                                    
+#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)                                    
+#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)                                   
+#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)                                   
+#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)                                   
+#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)                                   
+#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)                                   
+#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)                                    
+#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
+#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
+#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
+#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
+#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
+#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
+#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
+#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
+#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
+#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
+#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
+#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos                (16U)                                   
+#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
+#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
+#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
+#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
+#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
+#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
+#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
+#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
+#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
+#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
+#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
+#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)                                    
+#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
+#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
+#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
+#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
+#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
+#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
+#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
+#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos                (16U)                                   
+#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
+#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
+#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
+#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
+#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
+#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
+#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
+#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)                                    
+#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
+#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
+#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
+#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
+#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
+#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
+#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
+#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos                (16U)                                   
+#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
+#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
+#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
+#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
+#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
+#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
+#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
+#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)                                    
+#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)                                    
+#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)                                   
+#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)                                   
+#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)                                   
+#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)                                    
+#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)                                    
+#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)                                   
+#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)                                   
+#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)                                   
+#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)                                    
+#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)                                    
+#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)                                   
+#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)                                   
+#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)                                   
+#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)                                    
+#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)                                    
+#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)                                    
+#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)                                    
+#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)                                    
+#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos            (6U)                                    
+#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos              (8U)                                    
+#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos              (14U)                                   
+#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (20U)                                   
+#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (26U)                                   
+#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)                                    
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)                                   
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)                                   
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)                                    
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)                                   
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)                                   
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)                                    
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)                                   
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)                                   
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)                                    
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)                                   
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)                                   
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)                                    
+#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)                                    
+#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)                                    
+#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)                                    
+#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)                                    
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)                                    
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)                                    
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)                                    
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)                                   
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)                                    
+#define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)                                    
+#define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)                                    
+#define ADC_CSR_EOC_MST_Msk            (0x1U << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)                                    
+#define ADC_CSR_EOS_MST_Msk            (0x1U << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)                                    
+#define ADC_CSR_OVR_MST_Msk            (0x1U << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)                                    
+#define ADC_CSR_JEOC_MST_Msk           (0x1U << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)                                    
+#define ADC_CSR_JEOS_MST_Msk           (0x1U << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)                                    
+#define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)                                    
+#define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)                                    
+#define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos          (10U)                                   
+#define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)                                   
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)                                   
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1U << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)                                   
+#define ADC_CSR_EOC_SLV_Msk            (0x1U << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)                                   
+#define ADC_CSR_EOS_SLV_Msk            (0x1U << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)                                   
+#define ADC_CSR_OVR_SLV_Msk            (0x1U << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)                                   
+#define ADC_CSR_JEOC_SLV_Msk           (0x1U << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)                                   
+#define ADC_CSR_JEOS_SLV_Msk           (0x1U << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)                                   
+#define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)                                   
+#define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)                                   
+#define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos          (26U)                                   
+#define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)                                    
+#define ADC_CCR_DUAL_Msk               (0x1FU << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01U << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02U << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04U << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08U << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10U << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)                                    
+#define ADC_CCR_DELAY_Msk              (0xFU << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1U << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2U << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4U << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8U << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos             (13U)                                   
+#define ADC_CCR_DMACFG_Msk             (0x1U << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
+#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos               (14U)                                   
+#define ADC_CCR_MDMA_Msk               (0x3U << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
+#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0                 (0x1U << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1                 (0x2U << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos             (16U)                                   
+#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos              (18U)                                   
+#define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)                                   
+#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos               (23U)                                   
+#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos             (24U)                                   
+#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)                                    
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+#define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)                                   
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+#define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)                                          
+#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)                                      
+#define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)                                      
+#define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)                                      
+#define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)                                      
+#define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)                                      
+#define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)                                      
+#define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)                                       
+#define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)                                      
+#define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)                                       
+#define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)                                      
+#define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)                                       
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)                                       
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)                                       
+#define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)                                      
+#define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)                                       
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)                                      
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)                                  
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)                                  
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)                                  
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)                                  
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)                                  
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)                                   
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)                                   
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1U << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)                                   
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1U << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)                                   
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1U << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)                                   
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)                                   
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)                                   
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)                                   
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)                                  
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)                                  
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)                                  
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)                                   
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)                                   
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)                                   
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)                                  
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)                                  
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1U << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)                                  
+#define DFSDM_FLTCR1_FAST_Msk           (0x1U << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)                                  
+#define DFSDM_FLTCR1_RCH_Msk            (0x7U << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)                                  
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1U << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)                                  
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1U << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)                                  
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1U << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)                                  
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1U << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)                                  
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)                                   
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)                                   
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1U << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)                                   
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1U << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)                                   
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1U << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)                                   
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1U << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)                                   
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1U << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)                                  
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFU << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)                                   
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFU << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)                                   
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1U << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)                                   
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1U << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)                                   
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1U << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)                                   
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1U << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)                                   
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1U << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)                                   
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1U << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)                                   
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1U << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/*****************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)                                  
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFU << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)                                  
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFU << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)                                  
+#define DFSDM_FLTISR_RCIP_Msk           (0x1U << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)                                  
+#define DFSDM_FLTISR_JCIP_Msk           (0x1U << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)                                   
+#define DFSDM_FLTISR_AWDF_Msk           (0x1U << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)                                   
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1U << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)                                   
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1U << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)                                   
+#define DFSDM_FLTISR_REOCF_Msk          (0x1U << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)                                   
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1U << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/*****************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos       (24U)                                  
+#define DFSDM_FLTICR_CLRSCSDF_Msk       (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF           DFSDM_FLTICR_CLRSCSDF_Msk              /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)                                  
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)                                   
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1U << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)                                   
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)                                   
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/*****************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)                                  
+#define DFSDM_FLTFCR_FORD_Msk           (0x7U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)                                  
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFU << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)                                   
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFU << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)                                   
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)                                   
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)                                   
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)                                   
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1U << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)                                   
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)                                   
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)                                   
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)                                   
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)                                   
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)                                   
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)                                   
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)                                   
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)                                   
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)                                   
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)                                   
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)                                   
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos      (0U)                                            
+#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos      (4U)                                            
+#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos      (8U)                                            
+#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos      (12U)                                           
+#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos      (16U)                                           
+#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos      (20U)                                           
+#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos      (24U)                                           
+#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos        (0U)                                          
+#define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos        (1U)                                          
+#define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos        (2U)                                          
+#define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos        (3U)                                          
+#define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos        (4U)                                          
+#define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos        (5U)                                          
+#define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos        (6U)                                          
+#define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos        (7U)                                          
+#define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos        (8U)                                          
+#define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos        (9U)                                          
+#define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos       (10U)                                         
+#define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos       (11U)                                         
+#define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos       (12U)                                         
+#define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos       (13U)                                         
+#define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos       (14U)                                         
+#define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos       (15U)                                         
+#define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos       (16U)                                         
+#define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos       (17U)                                         
+#define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos       (18U)                                         
+#define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos       (19U)                                         
+#define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos       (20U)                                         
+#define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos       (21U)                                         
+#define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos       (22U)                                         
+#define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos       (23U)                                         
+#define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos       (24U)                                         
+#define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos       (25U)                                         
+#define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos       (26U)                                         
+#define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos       (27U)                                         
+#define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos       (28U)                                         
+#define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos       (29U)                                         
+#define EXTI_IMR1_IM29_Msk       (0x1U << EXTI_IMR1_IM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos       (30U)                                         
+#define EXTI_IMR1_IM30_Msk       (0x1U << EXTI_IMR1_IM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos       (31U)                                         
+#define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos         (0U)                                          
+#define EXTI_IMR1_IM_Msk         (0xFFFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos        (0U)                                          
+#define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos        (1U)                                          
+#define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos        (2U)                                          
+#define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos        (3U)                                          
+#define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos        (4U)                                          
+#define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos        (5U)                                          
+#define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos        (6U)                                          
+#define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos        (7U)                                          
+#define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos        (8U)                                          
+#define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos        (9U)                                          
+#define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos       (10U)                                         
+#define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos       (11U)                                         
+#define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos       (12U)                                         
+#define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos       (13U)                                         
+#define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos       (14U)                                         
+#define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos       (15U)                                         
+#define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos       (16U)                                         
+#define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos       (17U)                                         
+#define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos       (18U)                                         
+#define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos       (19U)                                         
+#define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos       (20U)                                         
+#define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos       (21U)                                         
+#define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos       (22U)                                         
+#define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos       (23U)                                         
+#define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos       (24U)                                         
+#define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos       (25U)                                         
+#define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos       (26U)                                         
+#define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos       (27U)                                         
+#define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos       (28U)                                         
+#define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos       (29U)                                         
+#define EXTI_EMR1_EM29_Msk       (0x1U << EXTI_EMR1_EM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos       (30U)                                         
+#define EXTI_EMR1_EM30_Msk       (0x1U << EXTI_EMR1_EM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos       (31U)                                         
+#define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos       (0U)                                          
+#define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos       (1U)                                          
+#define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos       (2U)                                          
+#define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos       (3U)                                          
+#define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos       (4U)                                          
+#define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos       (5U)                                          
+#define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos       (6U)                                          
+#define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos       (7U)                                          
+#define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos       (8U)                                          
+#define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos       (9U)                                          
+#define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos      (10U)                                         
+#define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos      (11U)                                         
+#define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos      (12U)                                         
+#define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos      (13U)                                         
+#define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos      (14U)                                         
+#define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos      (15U)                                         
+#define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos      (16U)                                         
+#define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos      (18U)                                         
+#define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos      (19U)                                         
+#define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos      (20U)                                         
+#define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos      (21U)                                         
+#define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos      (22U)                                         
+#define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos       (0U)                                          
+#define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos       (1U)                                          
+#define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos       (2U)                                          
+#define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos       (3U)                                          
+#define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos       (4U)                                          
+#define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos       (5U)                                          
+#define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos       (6U)                                          
+#define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos       (7U)                                          
+#define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos       (8U)                                          
+#define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos       (9U)                                          
+#define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos      (10U)                                         
+#define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos      (11U)                                         
+#define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos      (12U)                                         
+#define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos      (13U)                                         
+#define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos      (14U)                                         
+#define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos      (15U)                                         
+#define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos      (16U)                                         
+#define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos      (18U)                                         
+#define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos      (19U)                                         
+#define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos      (20U)                                         
+#define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos      (21U)                                         
+#define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos      (22U)                                         
+#define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos     (0U)                                          
+#define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos     (1U)                                          
+#define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos     (2U)                                          
+#define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos     (3U)                                          
+#define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos     (4U)                                          
+#define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos     (5U)                                          
+#define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos     (6U)                                          
+#define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos     (7U)                                          
+#define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos     (8U)                                          
+#define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos     (9U)                                          
+#define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos    (10U)                                         
+#define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos    (11U)                                         
+#define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos    (12U)                                         
+#define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos    (13U)                                         
+#define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos    (14U)                                         
+#define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos    (15U)                                         
+#define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos    (16U)                                         
+#define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos    (18U)                                         
+#define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos    (19U)                                         
+#define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos    (20U)                                         
+#define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos    (21U)                                         
+#define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos    (22U)                                         
+#define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos        (0U)                                          
+#define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos        (1U)                                          
+#define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos        (2U)                                          
+#define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos        (3U)                                          
+#define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos        (4U)                                          
+#define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos        (5U)                                          
+#define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos        (6U)                                          
+#define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos        (7U)                                          
+#define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos        (8U)                                          
+#define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos        (9U)                                          
+#define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos       (10U)                                         
+#define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos       (11U)                                         
+#define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos       (12U)                                         
+#define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos       (13U)                                         
+#define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos       (14U)                                         
+#define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos       (15U)                                         
+#define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos       (16U)                                         
+#define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos       (18U)                                         
+#define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */
+#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos       (19U)                                         
+#define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos       (20U)                                         
+#define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos       (21U)                                         
+#define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos       (22U)                                         
+#define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos       (0U)                                          
+#define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos       (1U)                                          
+#define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos       (2U)                                          
+#define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos       (3U)                                          
+#define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos       (4U)                                          
+#define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos       (5U)                                          
+#define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos       (6U)                                          
+#define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos       (7U)                                          
+#define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM_Pos         (0U)                                          
+#define EXTI_IMR2_IM_Msk         (0xFFU << EXTI_IMR2_IM_Pos)                   /*!< 0x000000FF */
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos       (0U)                                          
+#define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos       (1U)                                          
+#define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos       (2U)                                          
+#define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos       (3U)                                          
+#define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos       (4U)                                          
+#define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos       (5U)                                          
+#define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos       (6U)                                          
+#define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos       (7U)                                          
+#define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT35_Pos      (3U)                                          
+#define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos      (4U)                                          
+#define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos      (5U)                                          
+#define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos      (6U)                                          
+#define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT35_Pos      (3U)                                          
+#define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos      (4U)                                          
+#define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos      (5U)                                          
+#define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos      (6U)                                          
+#define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI35_Pos    (3U)                                          
+#define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos    (4U)                                          
+#define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos    (5U)                                          
+#define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos    (6U)                                          
+#define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF35_Pos       (3U)                                          
+#define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */
+#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos       (4U)                                          
+#define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */
+#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos       (5U)                                          
+#define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */
+#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos       (6U)                                          
+#define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos             (0U)                                 
+#define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                
+#define FLASH_ACR_LATENCY_0WS             (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS             (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS             (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS             (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS             (0x00000004U)
+#define FLASH_ACR_PRFTEN_Pos              (8U)                                 
+#define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk                 
+#define FLASH_ACR_ICEN_Pos                (9U)                                 
+#define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk                   
+#define FLASH_ACR_DCEN_Pos                (10U)                                
+#define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk                   
+#define FLASH_ACR_ICRST_Pos               (11U)                                
+#define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk                  
+#define FLASH_ACR_DCRST_Pos               (12U)                                
+#define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk                  
+#define FLASH_ACR_RUN_PD_Pos              (13U)                                
+#define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)                                
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                  (0U)                                 
+#define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     
+#define FLASH_SR_OPERR_Pos                (1U)                                 
+#define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk                   
+#define FLASH_SR_PROGERR_Pos              (3U)                                 
+#define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk                 
+#define FLASH_SR_WRPERR_Pos               (4U)                                 
+#define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk                  
+#define FLASH_SR_PGAERR_Pos               (5U)                                 
+#define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk                  
+#define FLASH_SR_SIZERR_Pos               (6U)                                 
+#define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk                  
+#define FLASH_SR_PGSERR_Pos               (7U)                                 
+#define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk                  
+#define FLASH_SR_MISERR_Pos               (8U)                                 
+#define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk                  
+#define FLASH_SR_FASTERR_Pos              (9U)                                 
+#define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk                 
+#define FLASH_SR_RDERR_Pos                (14U)                                
+#define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk                   
+#define FLASH_SR_OPTVERR_Pos              (15U)                                
+#define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk                 
+#define FLASH_SR_BSY_Pos                  (16U)                                
+#define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                   (0U)                                 
+#define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk                      
+#define FLASH_CR_PER_Pos                  (1U)                                 
+#define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk                     
+#define FLASH_CR_MER1_Pos                 (2U)                                 
+#define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk                    
+#define FLASH_CR_PNB_Pos                  (3U)                                 
+#define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk                     
+#define FLASH_CR_BKER_Pos                 (11U)                                
+#define FLASH_CR_BKER_Msk                 (0x1U << FLASH_CR_BKER_Pos)          /*!< 0x00000800 */
+#define FLASH_CR_BKER                     FLASH_CR_BKER_Msk                    
+#define FLASH_CR_MER2_Pos                 (15U)                                
+#define FLASH_CR_MER2_Msk                 (0x1U << FLASH_CR_MER2_Pos)          /*!< 0x00008000 */
+#define FLASH_CR_MER2                     FLASH_CR_MER2_Msk                    
+#define FLASH_CR_STRT_Pos                 (16U)                                
+#define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    
+#define FLASH_CR_OPTSTRT_Pos              (17U)                                
+#define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk                 
+#define FLASH_CR_FSTPG_Pos                (18U)                                
+#define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk                   
+#define FLASH_CR_EOPIE_Pos                (24U)                                
+#define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   
+#define FLASH_CR_ERRIE_Pos                (25U)                                
+#define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   
+#define FLASH_CR_RDERRIE_Pos              (26U)                                
+#define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk                 
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)                                
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              
+#define FLASH_CR_OPTLOCK_Pos              (30U)                                
+#define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk                 
+#define FLASH_CR_LOCK_Pos                 (31U)                                
+#define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)                                 
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk              
+#define FLASH_ECCR_BK_ECC_Pos             (19U)                                
+#define FLASH_ECCR_BK_ECC_Msk             (0x1U << FLASH_ECCR_BK_ECC_Pos)      /*!< 0x00080000 */
+#define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk                
+#define FLASH_ECCR_SYSF_ECC_Pos           (20U)                                
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk              
+#define FLASH_ECCR_ECCIE_Pos              (24U)                                
+#define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk                 
+#define FLASH_ECCR_ECCC_Pos               (30U)                                
+#define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk                  
+#define FLASH_ECCR_ECCD_Pos               (31U)                                
+#define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk                  
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                (0U)                                 
+#define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk                   
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)                                 
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk               
+#define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)                                
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk             
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)                                
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk            
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)                                
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk             
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)                                
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk               
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)                                
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk             
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)                                
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk            
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)                                
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk               
+#define FLASH_OPTR_BFB2_Pos               (20U)                                
+#define FLASH_OPTR_BFB2_Msk               (0x1U << FLASH_OPTR_BFB2_Pos)        /*!< 0x00100000 */
+#define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk                  
+#define FLASH_OPTR_DUALBANK_Pos           (21U)                                
+#define FLASH_OPTR_DUALBANK_Msk           (0x1U << FLASH_OPTR_DUALBANK_Pos)    /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk              
+#define FLASH_OPTR_nBOOT1_Pos             (23U)                                
+#define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk                
+#define FLASH_OPTR_SRAM2_PE_Pos           (24U)                                
+#define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk              
+#define FLASH_OPTR_SRAM2_RST_Pos          (25U)                                
+#define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk             
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)                                 
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)                                 
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk        
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)                                
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk         
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)                                 
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk          
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)                                
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk           
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)                                 
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk          
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)                                
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk           
+
+/******************  Bits definition for FLASH_PCROP2SR register  **********/
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)                                 
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP2ER register  ***********/
+#define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)                                 
+#define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk        
+
+/******************  Bits definition for FLASH_WRP2AR register  ***************/
+#define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)                                 
+#define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk          
+#define FLASH_WRP2AR_WRP2A_END_Pos        (16U)                                
+#define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk           
+
+/******************  Bits definition for FLASH_WRP2BR register  ***************/
+#define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)                                 
+#define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk          
+#define FLASH_WRP2BR_WRP2B_END_Pos        (16U)                                
+#define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk           
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)                                       
+#define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)                                        
+#define FMC_BCRx_MBKEN_Msk         (0x1U << FMC_BCRx_MBKEN_Pos)                /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)                                        
+#define FMC_BCRx_MUXEN_Msk         (0x1U << FMC_BCRx_MUXEN_Pos)                /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)                                        
+#define FMC_BCRx_MTYP_Msk          (0x3U << FMC_BCRx_MTYP_Pos)                 /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)                                        
+#define FMC_BCRx_MWID_Msk          (0x3U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)                                        
+#define FMC_BCRx_FACCEN_Msk        (0x1U << FMC_BCRx_FACCEN_Pos)               /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)                                        
+#define FMC_BCRx_BURSTEN_Msk       (0x1U << FMC_BCRx_BURSTEN_Pos)              /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)                                        
+#define FMC_BCRx_WAITPOL_Msk       (0x1U << FMC_BCRx_WAITPOL_Pos)              /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)                                       
+#define FMC_BCRx_WAITCFG_Msk       (0x1U << FMC_BCRx_WAITCFG_Pos)              /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)                                       
+#define FMC_BCRx_WREN_Msk          (0x1U << FMC_BCRx_WREN_Pos)                 /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)                                       
+#define FMC_BCRx_WAITEN_Msk        (0x1U << FMC_BCRx_WAITEN_Pos)               /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)                                       
+#define FMC_BCRx_EXTMOD_Msk        (0x1U << FMC_BCRx_EXTMOD_Pos)               /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)                                       
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1U << FMC_BCRx_ASYNCWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)                                       
+#define FMC_BCRx_CPSIZE_Msk        (0x7U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */
+#define FMC_BCRx_CPSIZE_0          (0x1U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)                                       
+#define FMC_BCRx_CBURSTRW_Msk      (0x1U << FMC_BCRx_CBURSTRW_Pos)             /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)                                        
+#define FMC_BTRx_ADDSET_Msk        (0xFU << FMC_BTRx_ADDSET_Pos)               /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)                                        
+#define FMC_BTRx_ADDHLD_Msk        (0xFU << FMC_BTRx_ADDHLD_Pos)               /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)                                        
+#define FMC_BTRx_DATAST_Msk        (0xFFU << FMC_BTRx_DATAST_Pos)              /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10U << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20U << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40U << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80U << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)                                       
+#define FMC_BTRx_BUSTURN_Msk       (0xFU << FMC_BTRx_BUSTURN_Pos)              /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)                                       
+#define FMC_BTRx_CLKDIV_Msk        (0xFU << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)                                       
+#define FMC_BTRx_DATLAT_Msk        (0xFU << FMC_BTRx_DATLAT_Pos)               /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1U << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2U << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4U << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8U << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)                                       
+#define FMC_BTRx_ACCMOD_Msk        (0x3U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)                                        
+#define FMC_BWTRx_ADDSET_Msk       (0xFU << FMC_BWTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)                                        
+#define FMC_BWTRx_ADDHLD_Msk       (0xFU << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)                                        
+#define FMC_BWTRx_DATAST_Msk       (0xFFU << FMC_BWTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)                                       
+#define FMC_BWTRx_BUSTURN_Msk      (0xFU << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)                                       
+#define FMC_BWTRx_ACCMOD_Msk       (0x3U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  ********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)                                        
+#define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)                                        
+#define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos           (3U)                                        
+#define FMC_PCR_PTYP_Msk           (0x1U << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */
+#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
+
+#define FMC_PCR_PWID_Pos           (4U)                                        
+#define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)                                        
+#define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)                                        
+#define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)                                       
+#define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)                                       
+#define FMC_PCR_ECCPS_Msk          (0x7U << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  ********************/
+#define FMC_SR_IRS_Pos             (0U)                                        
+#define FMC_SR_IRS_Msk             (0x1U << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)                                        
+#define FMC_SR_ILS_Msk             (0x1U << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)                                        
+#define FMC_SR_IFS_Msk             (0x1U << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)                                        
+#define FMC_SR_IREN_Msk            (0x1U << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)                                        
+#define FMC_SR_ILEN_Msk            (0x1U << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)                                        
+#define FMC_SR_IFEN_Msk            (0x1U << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)                                        
+#define FMC_SR_FEMPT_Msk           (0x1U << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos        (0U)                                        
+#define FMC_PMEM_MEMSET_Msk        (0xFFU << FMC_PMEM_MEMSET_Pos)              /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0          (0x01U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos       (8U)                                        
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFU << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0         (0x01U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos       (16U)                                       
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFU << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0         (0x01U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos        (24U)                                       
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFU << FMC_PMEM_MEMHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0          (0x01U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  *******************/
+#define FMC_PATT_ATTSET_Pos        (0U)                                        
+#define FMC_PATT_ATTSET_Msk        (0xFFU << FMC_PATT_ATTSET_Pos)              /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0          (0x01U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos       (8U)                                        
+#define FMC_PATT_ATTWAIT_Msk       (0xFFU << FMC_PATT_ATTWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0         (0x01U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos       (16U)                                       
+#define FMC_PATT_ATTHOLD_Msk       (0xFFU << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0         (0x01U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos        (24U)                                       
+#define FMC_PATT_ATTHIZ_Msk        (0xFFU << FMC_PATT_ATTHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0          (0x01U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR register  *******************/
+#define FMC_ECCR_ECC_Pos           (0U)                                        
+#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFU << FMC_ECCR_ECC_Pos)           /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)                                    
+#define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk                    
+#define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)                                    
+#define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk                    
+#define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)                                    
+#define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk                    
+#define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)                                    
+#define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk                    
+#define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)                                    
+#define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk                    
+#define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)                                   
+#define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk                    
+#define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)                                   
+#define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk                    
+#define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)                                   
+#define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk                    
+#define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)                                   
+#define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk                    
+#define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)                                   
+#define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk                    
+#define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)                                   
+#define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk                   
+#define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)                                   
+#define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk                   
+#define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)                                   
+#define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk                   
+#define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)                                   
+#define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk                   
+#define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)                                   
+#define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk                   
+#define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)                                   
+#define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk                   
+#define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)                                    
+#define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk                     
+#define GPIO_OTYPER_OT1_Pos            (1U)                                    
+#define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk                     
+#define GPIO_OTYPER_OT2_Pos            (2U)                                    
+#define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk                     
+#define GPIO_OTYPER_OT3_Pos            (3U)                                    
+#define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk                     
+#define GPIO_OTYPER_OT4_Pos            (4U)                                    
+#define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk                     
+#define GPIO_OTYPER_OT5_Pos            (5U)                                    
+#define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk                     
+#define GPIO_OTYPER_OT6_Pos            (6U)                                    
+#define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk                     
+#define GPIO_OTYPER_OT7_Pos            (7U)                                    
+#define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk                     
+#define GPIO_OTYPER_OT8_Pos            (8U)                                    
+#define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk                     
+#define GPIO_OTYPER_OT9_Pos            (9U)                                    
+#define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk                     
+#define GPIO_OTYPER_OT10_Pos           (10U)                                   
+#define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk                    
+#define GPIO_OTYPER_OT11_Pos           (11U)                                   
+#define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk                    
+#define GPIO_OTYPER_OT12_Pos           (12U)                                   
+#define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk                    
+#define GPIO_OTYPER_OT13_Pos           (13U)                                   
+#define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk                    
+#define GPIO_OTYPER_OT14_Pos           (14U)                                   
+#define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk                    
+#define GPIO_OTYPER_OT15_Pos           (15U)                                   
+#define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk                    
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)                                    
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk                
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)                                    
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk                
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)                                    
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk                
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)                                    
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk                
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)                                    
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk                
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)                                   
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk                
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)                                   
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk                
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)                                   
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk                
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)                                   
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk                
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)                                   
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk                
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)                                   
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk               
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)                                   
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk               
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)                                   
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk               
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)                                   
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk               
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)                                   
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk               
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)                                   
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk               
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)                                    
+#define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk                    
+#define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)                                    
+#define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk                    
+#define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)                                    
+#define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk                    
+#define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)                                    
+#define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk                    
+#define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)                                    
+#define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk                    
+#define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)                                   
+#define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk                    
+#define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)                                   
+#define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk                    
+#define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)                                   
+#define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk                    
+#define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)                                   
+#define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk                    
+#define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)                                   
+#define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk                    
+#define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)                                   
+#define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk                   
+#define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)                                   
+#define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk                   
+#define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)                                   
+#define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk                   
+#define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)                                   
+#define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk                   
+#define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)                                   
+#define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk                   
+#define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)                                   
+#define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk                   
+#define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)                                    
+#define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk                        
+#define GPIO_IDR_ID1_Pos               (1U)                                    
+#define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk                        
+#define GPIO_IDR_ID2_Pos               (2U)                                    
+#define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk                        
+#define GPIO_IDR_ID3_Pos               (3U)                                    
+#define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk                        
+#define GPIO_IDR_ID4_Pos               (4U)                                    
+#define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk                        
+#define GPIO_IDR_ID5_Pos               (5U)                                    
+#define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk                        
+#define GPIO_IDR_ID6_Pos               (6U)                                    
+#define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk                        
+#define GPIO_IDR_ID7_Pos               (7U)                                    
+#define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk                        
+#define GPIO_IDR_ID8_Pos               (8U)                                    
+#define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk                        
+#define GPIO_IDR_ID9_Pos               (9U)                                    
+#define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk                        
+#define GPIO_IDR_ID10_Pos              (10U)                                   
+#define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk                       
+#define GPIO_IDR_ID11_Pos              (11U)                                   
+#define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk                       
+#define GPIO_IDR_ID12_Pos              (12U)                                   
+#define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk                       
+#define GPIO_IDR_ID13_Pos              (13U)                                   
+#define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk                       
+#define GPIO_IDR_ID14_Pos              (14U)                                   
+#define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk                       
+#define GPIO_IDR_ID15_Pos              (15U)                                   
+#define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk                       
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)                                    
+#define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk                        
+#define GPIO_ODR_OD1_Pos               (1U)                                    
+#define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk                        
+#define GPIO_ODR_OD2_Pos               (2U)                                    
+#define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk                        
+#define GPIO_ODR_OD3_Pos               (3U)                                    
+#define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk                        
+#define GPIO_ODR_OD4_Pos               (4U)                                    
+#define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk                        
+#define GPIO_ODR_OD5_Pos               (5U)                                    
+#define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk                        
+#define GPIO_ODR_OD6_Pos               (6U)                                    
+#define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk                        
+#define GPIO_ODR_OD7_Pos               (7U)                                    
+#define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk                        
+#define GPIO_ODR_OD8_Pos               (8U)                                    
+#define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk                        
+#define GPIO_ODR_OD9_Pos               (9U)                                    
+#define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk                        
+#define GPIO_ODR_OD10_Pos              (10U)                                   
+#define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk                       
+#define GPIO_ODR_OD11_Pos              (11U)                                   
+#define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk                       
+#define GPIO_ODR_OD12_Pos              (12U)                                   
+#define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk                       
+#define GPIO_ODR_OD13_Pos              (13U)                                   
+#define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk                       
+#define GPIO_ODR_OD14_Pos              (14U)                                   
+#define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk                       
+#define GPIO_ODR_OD15_Pos              (15U)                                   
+#define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk                       
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)                                    
+#define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk                       
+#define GPIO_BSRR_BS1_Pos              (1U)                                    
+#define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk                       
+#define GPIO_BSRR_BS2_Pos              (2U)                                    
+#define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk                       
+#define GPIO_BSRR_BS3_Pos              (3U)                                    
+#define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk                       
+#define GPIO_BSRR_BS4_Pos              (4U)                                    
+#define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk                       
+#define GPIO_BSRR_BS5_Pos              (5U)                                    
+#define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk                       
+#define GPIO_BSRR_BS6_Pos              (6U)                                    
+#define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk                       
+#define GPIO_BSRR_BS7_Pos              (7U)                                    
+#define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk                       
+#define GPIO_BSRR_BS8_Pos              (8U)                                    
+#define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk                       
+#define GPIO_BSRR_BS9_Pos              (9U)                                    
+#define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk                       
+#define GPIO_BSRR_BS10_Pos             (10U)                                   
+#define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk                      
+#define GPIO_BSRR_BS11_Pos             (11U)                                   
+#define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk                      
+#define GPIO_BSRR_BS12_Pos             (12U)                                   
+#define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk                      
+#define GPIO_BSRR_BS13_Pos             (13U)                                   
+#define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk                      
+#define GPIO_BSRR_BS14_Pos             (14U)                                   
+#define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk                      
+#define GPIO_BSRR_BS15_Pos             (15U)                                   
+#define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk                      
+#define GPIO_BSRR_BR0_Pos              (16U)                                   
+#define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk                       
+#define GPIO_BSRR_BR1_Pos              (17U)                                   
+#define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk                       
+#define GPIO_BSRR_BR2_Pos              (18U)                                   
+#define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk                       
+#define GPIO_BSRR_BR3_Pos              (19U)                                   
+#define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk                       
+#define GPIO_BSRR_BR4_Pos              (20U)                                   
+#define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk                       
+#define GPIO_BSRR_BR5_Pos              (21U)                                   
+#define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk                       
+#define GPIO_BSRR_BR6_Pos              (22U)                                   
+#define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk                       
+#define GPIO_BSRR_BR7_Pos              (23U)                                   
+#define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk                       
+#define GPIO_BSRR_BR8_Pos              (24U)                                   
+#define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk                       
+#define GPIO_BSRR_BR9_Pos              (25U)                                   
+#define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk                       
+#define GPIO_BSRR_BR10_Pos             (26U)                                   
+#define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk                      
+#define GPIO_BSRR_BR11_Pos             (27U)                                   
+#define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk                      
+#define GPIO_BSRR_BR12_Pos             (28U)                                   
+#define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk                      
+#define GPIO_BSRR_BR13_Pos             (29U)                                   
+#define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk                      
+#define GPIO_BSRR_BR14_Pos             (30U)                                   
+#define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk                      
+#define GPIO_BSRR_BR15_Pos             (31U)                                   
+#define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk                      
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)                                    
+#define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk                      
+#define GPIO_LCKR_LCK1_Pos             (1U)                                    
+#define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk                      
+#define GPIO_LCKR_LCK2_Pos             (2U)                                    
+#define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk                      
+#define GPIO_LCKR_LCK3_Pos             (3U)                                    
+#define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk                      
+#define GPIO_LCKR_LCK4_Pos             (4U)                                    
+#define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk                      
+#define GPIO_LCKR_LCK5_Pos             (5U)                                    
+#define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk                      
+#define GPIO_LCKR_LCK6_Pos             (6U)                                    
+#define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk                      
+#define GPIO_LCKR_LCK7_Pos             (7U)                                    
+#define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk                      
+#define GPIO_LCKR_LCK8_Pos             (8U)                                    
+#define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk                      
+#define GPIO_LCKR_LCK9_Pos             (9U)                                    
+#define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk                      
+#define GPIO_LCKR_LCK10_Pos            (10U)                                   
+#define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk                     
+#define GPIO_LCKR_LCK11_Pos            (11U)                                   
+#define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk                     
+#define GPIO_LCKR_LCK12_Pos            (12U)                                   
+#define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk                     
+#define GPIO_LCKR_LCK13_Pos            (13U)                                   
+#define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk                     
+#define GPIO_LCKR_LCK14_Pos            (14U)                                   
+#define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk                     
+#define GPIO_LCKR_LCK15_Pos            (15U)                                   
+#define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk                     
+#define GPIO_LCKR_LCKK_Pos             (16U)                                   
+#define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk                      
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)                                    
+#define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)                                    
+#define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)                                    
+#define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)                                   
+#define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)                                   
+#define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)                                   
+#define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)                                   
+#define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)                                   
+#define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk                    
+#define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)                                    
+#define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)                                    
+#define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)                                    
+#define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk                   
+#define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)                                   
+#define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk                   
+#define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)                                   
+#define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk                   
+#define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)                                   
+#define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk                   
+#define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)                                   
+#define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk                   
+#define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)                                   
+#define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk                   
+#define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)                                    
+#define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk                        
+#define GPIO_BRR_BR1_Pos               (1U)                                    
+#define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk                        
+#define GPIO_BRR_BR2_Pos               (2U)                                    
+#define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk                        
+#define GPIO_BRR_BR3_Pos               (3U)                                    
+#define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk                        
+#define GPIO_BRR_BR4_Pos               (4U)                                    
+#define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk                        
+#define GPIO_BRR_BR5_Pos               (5U)                                    
+#define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk                        
+#define GPIO_BRR_BR6_Pos               (6U)                                    
+#define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk                        
+#define GPIO_BRR_BR7_Pos               (7U)                                    
+#define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk                        
+#define GPIO_BRR_BR8_Pos               (8U)                                    
+#define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk                        
+#define GPIO_BRR_BR9_Pos               (9U)                                    
+#define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk                        
+#define GPIO_BRR_BR10_Pos              (10U)                                   
+#define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk                       
+#define GPIO_BRR_BR11_Pos              (11U)                                   
+#define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk                       
+#define GPIO_BRR_BR12_Pos              (12U)                                   
+#define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk                       
+#define GPIO_BRR_BR13_Pos              (13U)                                   
+#define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk                       
+#define GPIO_BRR_BR14_Pos              (14U)                                   
+#define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk                       
+#define GPIO_BRR_BR15_Pos              (15U)                                   
+#define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk                       
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+/******************  Bits definition for GPIO_ASCR register  *******************/
+#define GPIO_ASCR_ASC0_Pos             (0U)                                    
+#define GPIO_ASCR_ASC0_Msk             (0x1U << GPIO_ASCR_ASC0_Pos)            /*!< 0x00000001 */
+#define GPIO_ASCR_ASC0                 GPIO_ASCR_ASC0_Msk                      
+#define GPIO_ASCR_ASC1_Pos             (1U)                                    
+#define GPIO_ASCR_ASC1_Msk             (0x1U << GPIO_ASCR_ASC1_Pos)            /*!< 0x00000002 */
+#define GPIO_ASCR_ASC1                 GPIO_ASCR_ASC1_Msk                      
+#define GPIO_ASCR_ASC2_Pos             (2U)                                    
+#define GPIO_ASCR_ASC2_Msk             (0x1U << GPIO_ASCR_ASC2_Pos)            /*!< 0x00000004 */
+#define GPIO_ASCR_ASC2                 GPIO_ASCR_ASC2_Msk                      
+#define GPIO_ASCR_ASC3_Pos             (3U)                                    
+#define GPIO_ASCR_ASC3_Msk             (0x1U << GPIO_ASCR_ASC3_Pos)            /*!< 0x00000008 */
+#define GPIO_ASCR_ASC3                 GPIO_ASCR_ASC3_Msk                      
+#define GPIO_ASCR_ASC4_Pos             (4U)                                    
+#define GPIO_ASCR_ASC4_Msk             (0x1U << GPIO_ASCR_ASC4_Pos)            /*!< 0x00000010 */
+#define GPIO_ASCR_ASC4                 GPIO_ASCR_ASC4_Msk                      
+#define GPIO_ASCR_ASC5_Pos             (5U)                                    
+#define GPIO_ASCR_ASC5_Msk             (0x1U << GPIO_ASCR_ASC5_Pos)            /*!< 0x00000020 */
+#define GPIO_ASCR_ASC5                 GPIO_ASCR_ASC5_Msk                      
+#define GPIO_ASCR_ASC6_Pos             (6U)                                    
+#define GPIO_ASCR_ASC6_Msk             (0x1U << GPIO_ASCR_ASC6_Pos)            /*!< 0x00000040 */
+#define GPIO_ASCR_ASC6                 GPIO_ASCR_ASC6_Msk                      
+#define GPIO_ASCR_ASC7_Pos             (7U)                                    
+#define GPIO_ASCR_ASC7_Msk             (0x1U << GPIO_ASCR_ASC7_Pos)            /*!< 0x00000080 */
+#define GPIO_ASCR_ASC7                 GPIO_ASCR_ASC7_Msk                      
+#define GPIO_ASCR_ASC8_Pos             (8U)                                    
+#define GPIO_ASCR_ASC8_Msk             (0x1U << GPIO_ASCR_ASC8_Pos)            /*!< 0x00000100 */
+#define GPIO_ASCR_ASC8                 GPIO_ASCR_ASC8_Msk                      
+#define GPIO_ASCR_ASC9_Pos             (9U)                                    
+#define GPIO_ASCR_ASC9_Msk             (0x1U << GPIO_ASCR_ASC9_Pos)            /*!< 0x00000200 */
+#define GPIO_ASCR_ASC9                 GPIO_ASCR_ASC9_Msk                      
+#define GPIO_ASCR_ASC10_Pos            (10U)                                   
+#define GPIO_ASCR_ASC10_Msk            (0x1U << GPIO_ASCR_ASC10_Pos)           /*!< 0x00000400 */
+#define GPIO_ASCR_ASC10                GPIO_ASCR_ASC10_Msk                     
+#define GPIO_ASCR_ASC11_Pos            (11U)                                   
+#define GPIO_ASCR_ASC11_Msk            (0x1U << GPIO_ASCR_ASC11_Pos)           /*!< 0x00000800 */
+#define GPIO_ASCR_ASC11                GPIO_ASCR_ASC11_Msk                     
+#define GPIO_ASCR_ASC12_Pos            (12U)                                   
+#define GPIO_ASCR_ASC12_Msk            (0x1U << GPIO_ASCR_ASC12_Pos)           /*!< 0x00001000 */
+#define GPIO_ASCR_ASC12                GPIO_ASCR_ASC12_Msk                     
+#define GPIO_ASCR_ASC13_Pos            (13U)                                   
+#define GPIO_ASCR_ASC13_Msk            (0x1U << GPIO_ASCR_ASC13_Pos)           /*!< 0x00002000 */
+#define GPIO_ASCR_ASC13                GPIO_ASCR_ASC13_Msk                     
+#define GPIO_ASCR_ASC14_Pos            (14U)                                   
+#define GPIO_ASCR_ASC14_Msk            (0x1U << GPIO_ASCR_ASC14_Pos)           /*!< 0x00004000 */
+#define GPIO_ASCR_ASC14                GPIO_ASCR_ASC14_Msk                     
+#define GPIO_ASCR_ASC15_Pos            (15U)                                   
+#define GPIO_ASCR_ASC15_Msk            (0x1U << GPIO_ASCR_ASC15_Pos)           /*!< 0x00008000 */
+#define GPIO_ASCR_ASC15                GPIO_ASCR_ASC15_Msk                     
+
+/* Legacy defines */
+#define GPIO_ASCR_EN_0                      GPIO_ASCR_ASC0
+#define GPIO_ASCR_EN_1                      GPIO_ASCR_ASC1
+#define GPIO_ASCR_EN_2                      GPIO_ASCR_ASC2
+#define GPIO_ASCR_EN_3                      GPIO_ASCR_ASC3
+#define GPIO_ASCR_EN_4                      GPIO_ASCR_ASC4
+#define GPIO_ASCR_EN_5                      GPIO_ASCR_ASC5
+#define GPIO_ASCR_EN_6                      GPIO_ASCR_ASC6
+#define GPIO_ASCR_EN_7                      GPIO_ASCR_ASC7
+#define GPIO_ASCR_EN_8                      GPIO_ASCR_ASC8
+#define GPIO_ASCR_EN_9                      GPIO_ASCR_ASC9
+#define GPIO_ASCR_EN_10                     GPIO_ASCR_ASC10
+#define GPIO_ASCR_EN_11                     GPIO_ASCR_ASC11
+#define GPIO_ASCR_EN_12                     GPIO_ASCR_ASC12
+#define GPIO_ASCR_EN_13                     GPIO_ASCR_ASC13
+#define GPIO_ASCR_EN_14                     GPIO_ASCR_ASC14
+#define GPIO_ASCR_EN_15                     GPIO_ASCR_ASC15
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos            (13U)                                     
+#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
+#define FW_CSSA_ADD_Pos      (8U)                                              
+#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos      (8U)                                              
+#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
+#define FW_NVDSSA_ADD_Pos    (8U)                                              
+#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos    (8U)                                              
+#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos     (6U)                                              
+#define FW_VDSSA_ADD_Msk     (0x7FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos     (6U)                                              
+#define FW_VDSL_LENG_Msk     (0x7FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos        (0U)                                              
+#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos        (1U)                                              
+#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos        (2U)                                              
+#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos              (14U)                                     
+#define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos              (9U)                                      
+#define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos              (8U)                                      
+#define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos             (0U)                                      
+#define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)                                      
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos       (1U)                                      
+#define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)                                      
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)                                      
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_USV_Pos              (10U)                                     
+#define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */
+#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
+#define PWR_CR2_IOSV_Pos             (9U)                                      
+#define PWR_CR2_IOSV_Msk             (0x1U << PWR_CR2_IOSV_Pos)                /*!< 0x00000200 */
+#define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos             (4U)                                      
+#define PWR_CR2_PVME_Msk             (0xFU << PWR_CR2_PVME_Pos)                /*!< 0x000000F0 */
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos            (7U)                                      
+#define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos            (6U)                                      
+#define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos            (5U)                                      
+#define PWR_CR2_PVME2_Msk            (0x1U << PWR_CR2_PVME2_Pos)               /*!< 0x00000020 */
+#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos            (4U)                                      
+#define PWR_CR2_PVME1_Msk            (0x1U << PWR_CR2_PVME1_Pos)               /*!< 0x00000010 */
+#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos              (1U)                                      
+#define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos         (3U)                                      
+#define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos             (0U)                                      
+#define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos             (15U)                                     
+#define PWR_CR3_EIWF_Msk             (0x1U << PWR_CR3_EIWF_Pos)                /*!< 0x00008000 */
+#define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos              (10U)                                     
+#define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos              (8U)                                      
+#define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos            (4U)                                      
+#define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos            (3U)                                      
+#define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos            (2U)                                      
+#define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos            (1U)                                      
+#define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos            (0U)                                      
+#define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos             (0U)                                      
+#define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos             (9U)                                      
+#define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos              (8U)                                      
+#define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos              (4U)                                      
+#define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos              (3U)                                      
+#define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos              (2U)                                      
+#define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos              (1U)                                      
+#define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos              (0U)                                      
+#define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos             (15U)                                     
+#define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos              (8U)                                      
+#define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos              (0U)                                      
+#define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos             (4U)                                      
+#define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos             (3U)                                      
+#define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos             (2U)                                      
+#define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos             (1U)                                      
+#define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos             (0U)                                      
+#define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos            (15U)                                     
+#define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos            (14U)                                     
+#define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos            (13U)                                     
+#define PWR_SR2_PVMO2_Msk            (0x1U << PWR_SR2_PVMO2_Pos)               /*!< 0x00002000 */
+#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos            (12U)                                     
+#define PWR_SR2_PVMO1_Msk            (0x1U << PWR_SR2_PVMO1_Pos)               /*!< 0x00001000 */
+#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos             (11U)                                     
+#define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos             (10U)                                     
+#define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos           (9U)                                      
+#define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos           (8U)                                      
+#define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos             (8U)                                      
+#define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos             (0U)                                      
+#define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos            (4U)                                      
+#define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos            (3U)                                      
+#define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos            (2U)                                      
+#define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos            (1U)                                      
+#define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos            (0U)                                      
+#define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos           (15U)                                     
+#define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos           (13U)                                     
+#define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos           (12U)                                     
+#define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos           (11U)                                     
+#define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos           (10U)                                     
+#define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos            (9U)                                      
+#define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos            (8U)                                      
+#define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos            (7U)                                      
+#define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos            (6U)                                      
+#define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos            (5U)                                      
+#define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos            (4U)                                      
+#define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos            (3U)                                      
+#define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos            (2U)                                      
+#define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos            (1U)                                      
+#define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos            (0U)                                      
+#define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos           (14U)                                     
+#define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos           (12U)                                     
+#define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos           (11U)                                     
+#define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos           (10U)                                     
+#define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos            (9U)                                      
+#define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos            (8U)                                      
+#define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos            (7U)                                      
+#define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos            (6U)                                      
+#define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos            (5U)                                      
+#define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos            (4U)                                      
+#define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos            (3U)                                      
+#define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos            (2U)                                      
+#define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos            (1U)                                      
+#define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos            (0U)                                      
+#define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+#define PWR_PUCRB_PB15_Pos           (15U)                                     
+#define PWR_PUCRB_PB15_Msk           (0x1U << PWR_PUCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos           (14U)                                     
+#define PWR_PUCRB_PB14_Msk           (0x1U << PWR_PUCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos           (13U)                                     
+#define PWR_PUCRB_PB13_Msk           (0x1U << PWR_PUCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos           (12U)                                     
+#define PWR_PUCRB_PB12_Msk           (0x1U << PWR_PUCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos           (11U)                                     
+#define PWR_PUCRB_PB11_Msk           (0x1U << PWR_PUCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos           (10U)                                     
+#define PWR_PUCRB_PB10_Msk           (0x1U << PWR_PUCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos            (9U)                                      
+#define PWR_PUCRB_PB9_Msk            (0x1U << PWR_PUCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
+#define PWR_PUCRB_PB8_Pos            (8U)                                      
+#define PWR_PUCRB_PB8_Msk            (0x1U << PWR_PUCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
+#define PWR_PUCRB_PB7_Pos            (7U)                                      
+#define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos            (6U)                                      
+#define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos            (5U)                                      
+#define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos            (4U)                                      
+#define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos            (3U)                                      
+#define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB2_Pos            (2U)                                      
+#define PWR_PUCRB_PB2_Msk            (0x1U << PWR_PUCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos            (1U)                                      
+#define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos            (0U)                                      
+#define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB15_Pos           (15U)                                     
+#define PWR_PDCRB_PB15_Msk           (0x1U << PWR_PDCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos           (14U)                                     
+#define PWR_PDCRB_PB14_Msk           (0x1U << PWR_PDCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos           (13U)                                     
+#define PWR_PDCRB_PB13_Msk           (0x1U << PWR_PDCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos           (12U)                                     
+#define PWR_PDCRB_PB12_Msk           (0x1U << PWR_PDCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos           (11U)                                     
+#define PWR_PDCRB_PB11_Msk           (0x1U << PWR_PDCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos           (10U)                                     
+#define PWR_PDCRB_PB10_Msk           (0x1U << PWR_PDCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos            (9U)                                      
+#define PWR_PDCRB_PB9_Msk            (0x1U << PWR_PDCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
+#define PWR_PDCRB_PB8_Pos            (8U)                                      
+#define PWR_PDCRB_PB8_Msk            (0x1U << PWR_PDCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
+#define PWR_PDCRB_PB7_Pos            (7U)                                      
+#define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos            (6U)                                      
+#define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos            (5U)                                      
+#define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos            (3U)                                      
+#define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB2_Pos            (2U)                                      
+#define PWR_PDCRB_PB2_Msk            (0x1U << PWR_PDCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos            (1U)                                      
+#define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos            (0U)                                      
+#define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos           (15U)                                     
+#define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos           (14U)                                     
+#define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos           (13U)                                     
+#define PWR_PUCRC_PC13_Msk           (0x1U << PWR_PUCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos           (12U)                                     
+#define PWR_PUCRC_PC12_Msk           (0x1U << PWR_PUCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos           (11U)                                     
+#define PWR_PUCRC_PC11_Msk           (0x1U << PWR_PUCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos           (10U)                                     
+#define PWR_PUCRC_PC10_Msk           (0x1U << PWR_PUCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos            (9U)                                      
+#define PWR_PUCRC_PC9_Msk            (0x1U << PWR_PUCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
+#define PWR_PUCRC_PC8_Pos            (8U)                                      
+#define PWR_PUCRC_PC8_Msk            (0x1U << PWR_PUCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
+#define PWR_PUCRC_PC7_Pos            (7U)                                      
+#define PWR_PUCRC_PC7_Msk            (0x1U << PWR_PUCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
+#define PWR_PUCRC_PC6_Pos            (6U)                                      
+#define PWR_PUCRC_PC6_Msk            (0x1U << PWR_PUCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
+#define PWR_PUCRC_PC5_Pos            (5U)                                      
+#define PWR_PUCRC_PC5_Msk            (0x1U << PWR_PUCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
+#define PWR_PUCRC_PC4_Pos            (4U)                                      
+#define PWR_PUCRC_PC4_Msk            (0x1U << PWR_PUCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
+#define PWR_PUCRC_PC3_Pos            (3U)                                      
+#define PWR_PUCRC_PC3_Msk            (0x1U << PWR_PUCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
+#define PWR_PUCRC_PC2_Pos            (2U)                                      
+#define PWR_PUCRC_PC2_Msk            (0x1U << PWR_PUCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
+#define PWR_PUCRC_PC1_Pos            (1U)                                      
+#define PWR_PUCRC_PC1_Msk            (0x1U << PWR_PUCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
+#define PWR_PUCRC_PC0_Pos            (0U)                                      
+#define PWR_PUCRC_PC0_Msk            (0x1U << PWR_PUCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos           (15U)                                     
+#define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos           (14U)                                     
+#define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos           (13U)                                     
+#define PWR_PDCRC_PC13_Msk           (0x1U << PWR_PDCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos           (12U)                                     
+#define PWR_PDCRC_PC12_Msk           (0x1U << PWR_PDCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos           (11U)                                     
+#define PWR_PDCRC_PC11_Msk           (0x1U << PWR_PDCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos           (10U)                                     
+#define PWR_PDCRC_PC10_Msk           (0x1U << PWR_PDCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos            (9U)                                      
+#define PWR_PDCRC_PC9_Msk            (0x1U << PWR_PDCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
+#define PWR_PDCRC_PC8_Pos            (8U)                                      
+#define PWR_PDCRC_PC8_Msk            (0x1U << PWR_PDCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
+#define PWR_PDCRC_PC7_Pos            (7U)                                      
+#define PWR_PDCRC_PC7_Msk            (0x1U << PWR_PDCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
+#define PWR_PDCRC_PC6_Pos            (6U)                                      
+#define PWR_PDCRC_PC6_Msk            (0x1U << PWR_PDCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
+#define PWR_PDCRC_PC5_Pos            (5U)                                      
+#define PWR_PDCRC_PC5_Msk            (0x1U << PWR_PDCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
+#define PWR_PDCRC_PC4_Pos            (4U)                                      
+#define PWR_PDCRC_PC4_Msk            (0x1U << PWR_PDCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
+#define PWR_PDCRC_PC3_Pos            (3U)                                      
+#define PWR_PDCRC_PC3_Msk            (0x1U << PWR_PDCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
+#define PWR_PDCRC_PC2_Pos            (2U)                                      
+#define PWR_PDCRC_PC2_Msk            (0x1U << PWR_PDCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
+#define PWR_PDCRC_PC1_Pos            (1U)                                      
+#define PWR_PDCRC_PC1_Msk            (0x1U << PWR_PDCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
+#define PWR_PDCRC_PC0_Pos            (0U)                                      
+#define PWR_PDCRC_PC0_Msk            (0x1U << PWR_PDCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRD register  ********************/
+#define PWR_PUCRD_PD15_Pos           (15U)                                     
+#define PWR_PUCRD_PD15_Msk           (0x1U << PWR_PUCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos           (14U)                                     
+#define PWR_PUCRD_PD14_Msk           (0x1U << PWR_PUCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos           (13U)                                     
+#define PWR_PUCRD_PD13_Msk           (0x1U << PWR_PUCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos           (12U)                                     
+#define PWR_PUCRD_PD12_Msk           (0x1U << PWR_PUCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos           (11U)                                     
+#define PWR_PUCRD_PD11_Msk           (0x1U << PWR_PUCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos           (10U)                                     
+#define PWR_PUCRD_PD10_Msk           (0x1U << PWR_PUCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos            (9U)                                      
+#define PWR_PUCRD_PD9_Msk            (0x1U << PWR_PUCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
+#define PWR_PUCRD_PD8_Pos            (8U)                                      
+#define PWR_PUCRD_PD8_Msk            (0x1U << PWR_PUCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
+#define PWR_PUCRD_PD7_Pos            (7U)                                      
+#define PWR_PUCRD_PD7_Msk            (0x1U << PWR_PUCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
+#define PWR_PUCRD_PD6_Pos            (6U)                                      
+#define PWR_PUCRD_PD6_Msk            (0x1U << PWR_PUCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
+#define PWR_PUCRD_PD5_Pos            (5U)                                      
+#define PWR_PUCRD_PD5_Msk            (0x1U << PWR_PUCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
+#define PWR_PUCRD_PD4_Pos            (4U)                                      
+#define PWR_PUCRD_PD4_Msk            (0x1U << PWR_PUCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
+#define PWR_PUCRD_PD3_Pos            (3U)                                      
+#define PWR_PUCRD_PD3_Msk            (0x1U << PWR_PUCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
+#define PWR_PUCRD_PD2_Pos            (2U)                                      
+#define PWR_PUCRD_PD2_Msk            (0x1U << PWR_PUCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
+#define PWR_PUCRD_PD1_Pos            (1U)                                      
+#define PWR_PUCRD_PD1_Msk            (0x1U << PWR_PUCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
+#define PWR_PUCRD_PD0_Pos            (0U)                                      
+#define PWR_PUCRD_PD0_Msk            (0x1U << PWR_PUCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRD register  ********************/
+#define PWR_PDCRD_PD15_Pos           (15U)                                     
+#define PWR_PDCRD_PD15_Msk           (0x1U << PWR_PDCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos           (14U)                                     
+#define PWR_PDCRD_PD14_Msk           (0x1U << PWR_PDCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos           (13U)                                     
+#define PWR_PDCRD_PD13_Msk           (0x1U << PWR_PDCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos           (12U)                                     
+#define PWR_PDCRD_PD12_Msk           (0x1U << PWR_PDCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos           (11U)                                     
+#define PWR_PDCRD_PD11_Msk           (0x1U << PWR_PDCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos           (10U)                                     
+#define PWR_PDCRD_PD10_Msk           (0x1U << PWR_PDCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos            (9U)                                      
+#define PWR_PDCRD_PD9_Msk            (0x1U << PWR_PDCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
+#define PWR_PDCRD_PD8_Pos            (8U)                                      
+#define PWR_PDCRD_PD8_Msk            (0x1U << PWR_PDCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
+#define PWR_PDCRD_PD7_Pos            (7U)                                      
+#define PWR_PDCRD_PD7_Msk            (0x1U << PWR_PDCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
+#define PWR_PDCRD_PD6_Pos            (6U)                                      
+#define PWR_PDCRD_PD6_Msk            (0x1U << PWR_PDCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
+#define PWR_PDCRD_PD5_Pos            (5U)                                      
+#define PWR_PDCRD_PD5_Msk            (0x1U << PWR_PDCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
+#define PWR_PDCRD_PD4_Pos            (4U)                                      
+#define PWR_PDCRD_PD4_Msk            (0x1U << PWR_PDCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
+#define PWR_PDCRD_PD3_Pos            (3U)                                      
+#define PWR_PDCRD_PD3_Msk            (0x1U << PWR_PDCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
+#define PWR_PDCRD_PD2_Pos            (2U)                                      
+#define PWR_PDCRD_PD2_Msk            (0x1U << PWR_PDCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
+#define PWR_PDCRD_PD1_Pos            (1U)                                      
+#define PWR_PDCRD_PD1_Msk            (0x1U << PWR_PDCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
+#define PWR_PDCRD_PD0_Pos            (0U)                                      
+#define PWR_PDCRD_PD0_Msk            (0x1U << PWR_PDCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRE register  ********************/
+#define PWR_PUCRE_PE15_Pos           (15U)                                     
+#define PWR_PUCRE_PE15_Msk           (0x1U << PWR_PUCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos           (14U)                                     
+#define PWR_PUCRE_PE14_Msk           (0x1U << PWR_PUCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos           (13U)                                     
+#define PWR_PUCRE_PE13_Msk           (0x1U << PWR_PUCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos           (12U)                                     
+#define PWR_PUCRE_PE12_Msk           (0x1U << PWR_PUCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos           (11U)                                     
+#define PWR_PUCRE_PE11_Msk           (0x1U << PWR_PUCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos           (10U)                                     
+#define PWR_PUCRE_PE10_Msk           (0x1U << PWR_PUCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos            (9U)                                      
+#define PWR_PUCRE_PE9_Msk            (0x1U << PWR_PUCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
+#define PWR_PUCRE_PE8_Pos            (8U)                                      
+#define PWR_PUCRE_PE8_Msk            (0x1U << PWR_PUCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
+#define PWR_PUCRE_PE7_Pos            (7U)                                      
+#define PWR_PUCRE_PE7_Msk            (0x1U << PWR_PUCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
+#define PWR_PUCRE_PE6_Pos            (6U)                                      
+#define PWR_PUCRE_PE6_Msk            (0x1U << PWR_PUCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
+#define PWR_PUCRE_PE5_Pos            (5U)                                      
+#define PWR_PUCRE_PE5_Msk            (0x1U << PWR_PUCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
+#define PWR_PUCRE_PE4_Pos            (4U)                                      
+#define PWR_PUCRE_PE4_Msk            (0x1U << PWR_PUCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
+#define PWR_PUCRE_PE3_Pos            (3U)                                      
+#define PWR_PUCRE_PE3_Msk            (0x1U << PWR_PUCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
+#define PWR_PUCRE_PE2_Pos            (2U)                                      
+#define PWR_PUCRE_PE2_Msk            (0x1U << PWR_PUCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
+#define PWR_PUCRE_PE1_Pos            (1U)                                      
+#define PWR_PUCRE_PE1_Msk            (0x1U << PWR_PUCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
+#define PWR_PUCRE_PE0_Pos            (0U)                                      
+#define PWR_PUCRE_PE0_Msk            (0x1U << PWR_PUCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRE register  ********************/
+#define PWR_PDCRE_PE15_Pos           (15U)                                     
+#define PWR_PDCRE_PE15_Msk           (0x1U << PWR_PDCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos           (14U)                                     
+#define PWR_PDCRE_PE14_Msk           (0x1U << PWR_PDCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos           (13U)                                     
+#define PWR_PDCRE_PE13_Msk           (0x1U << PWR_PDCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos           (12U)                                     
+#define PWR_PDCRE_PE12_Msk           (0x1U << PWR_PDCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos           (11U)                                     
+#define PWR_PDCRE_PE11_Msk           (0x1U << PWR_PDCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos           (10U)                                     
+#define PWR_PDCRE_PE10_Msk           (0x1U << PWR_PDCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos            (9U)                                      
+#define PWR_PDCRE_PE9_Msk            (0x1U << PWR_PDCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
+#define PWR_PDCRE_PE8_Pos            (8U)                                      
+#define PWR_PDCRE_PE8_Msk            (0x1U << PWR_PDCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
+#define PWR_PDCRE_PE7_Pos            (7U)                                      
+#define PWR_PDCRE_PE7_Msk            (0x1U << PWR_PDCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
+#define PWR_PDCRE_PE6_Pos            (6U)                                      
+#define PWR_PDCRE_PE6_Msk            (0x1U << PWR_PDCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
+#define PWR_PDCRE_PE5_Pos            (5U)                                      
+#define PWR_PDCRE_PE5_Msk            (0x1U << PWR_PDCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
+#define PWR_PDCRE_PE4_Pos            (4U)                                      
+#define PWR_PDCRE_PE4_Msk            (0x1U << PWR_PDCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
+#define PWR_PDCRE_PE3_Pos            (3U)                                      
+#define PWR_PDCRE_PE3_Msk            (0x1U << PWR_PDCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
+#define PWR_PDCRE_PE2_Pos            (2U)                                      
+#define PWR_PDCRE_PE2_Msk            (0x1U << PWR_PDCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
+#define PWR_PDCRE_PE1_Pos            (1U)                                      
+#define PWR_PDCRE_PE1_Msk            (0x1U << PWR_PDCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
+#define PWR_PDCRE_PE0_Pos            (0U)                                      
+#define PWR_PDCRE_PE0_Msk            (0x1U << PWR_PDCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRF register  ********************/
+#define PWR_PUCRF_PF15_Pos           (15U)                                     
+#define PWR_PUCRF_PF15_Msk           (0x1U << PWR_PUCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos           (14U)                                     
+#define PWR_PUCRF_PF14_Msk           (0x1U << PWR_PUCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos           (13U)                                     
+#define PWR_PUCRF_PF13_Msk           (0x1U << PWR_PUCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos           (12U)                                     
+#define PWR_PUCRF_PF12_Msk           (0x1U << PWR_PUCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos           (11U)                                     
+#define PWR_PUCRF_PF11_Msk           (0x1U << PWR_PUCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos           (10U)                                     
+#define PWR_PUCRF_PF10_Msk           (0x1U << PWR_PUCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos            (9U)                                      
+#define PWR_PUCRF_PF9_Msk            (0x1U << PWR_PUCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
+#define PWR_PUCRF_PF8_Pos            (8U)                                      
+#define PWR_PUCRF_PF8_Msk            (0x1U << PWR_PUCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
+#define PWR_PUCRF_PF7_Pos            (7U)                                      
+#define PWR_PUCRF_PF7_Msk            (0x1U << PWR_PUCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
+#define PWR_PUCRF_PF6_Pos            (6U)                                      
+#define PWR_PUCRF_PF6_Msk            (0x1U << PWR_PUCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
+#define PWR_PUCRF_PF5_Pos            (5U)                                      
+#define PWR_PUCRF_PF5_Msk            (0x1U << PWR_PUCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
+#define PWR_PUCRF_PF4_Pos            (4U)                                      
+#define PWR_PUCRF_PF4_Msk            (0x1U << PWR_PUCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
+#define PWR_PUCRF_PF3_Pos            (3U)                                      
+#define PWR_PUCRF_PF3_Msk            (0x1U << PWR_PUCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
+#define PWR_PUCRF_PF2_Pos            (2U)                                      
+#define PWR_PUCRF_PF2_Msk            (0x1U << PWR_PUCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
+#define PWR_PUCRF_PF1_Pos            (1U)                                      
+#define PWR_PUCRF_PF1_Msk            (0x1U << PWR_PUCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
+#define PWR_PUCRF_PF0_Pos            (0U)                                      
+#define PWR_PUCRF_PF0_Msk            (0x1U << PWR_PUCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRF register  ********************/
+#define PWR_PDCRF_PF15_Pos           (15U)                                     
+#define PWR_PDCRF_PF15_Msk           (0x1U << PWR_PDCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
+#define PWR_PDCRF_PF14_Pos           (14U)                                     
+#define PWR_PDCRF_PF14_Msk           (0x1U << PWR_PDCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
+#define PWR_PDCRF_PF13_Pos           (13U)                                     
+#define PWR_PDCRF_PF13_Msk           (0x1U << PWR_PDCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
+#define PWR_PDCRF_PF12_Pos           (12U)                                     
+#define PWR_PDCRF_PF12_Msk           (0x1U << PWR_PDCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
+#define PWR_PDCRF_PF11_Pos           (11U)                                     
+#define PWR_PDCRF_PF11_Msk           (0x1U << PWR_PDCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
+#define PWR_PDCRF_PF10_Pos           (10U)                                     
+#define PWR_PDCRF_PF10_Msk           (0x1U << PWR_PDCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos            (9U)                                      
+#define PWR_PDCRF_PF9_Msk            (0x1U << PWR_PDCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
+#define PWR_PDCRF_PF8_Pos            (8U)                                      
+#define PWR_PDCRF_PF8_Msk            (0x1U << PWR_PDCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
+#define PWR_PDCRF_PF7_Pos            (7U)                                      
+#define PWR_PDCRF_PF7_Msk            (0x1U << PWR_PDCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
+#define PWR_PDCRF_PF6_Pos            (6U)                                      
+#define PWR_PDCRF_PF6_Msk            (0x1U << PWR_PDCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
+#define PWR_PDCRF_PF5_Pos            (5U)                                      
+#define PWR_PDCRF_PF5_Msk            (0x1U << PWR_PDCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
+#define PWR_PDCRF_PF4_Pos            (4U)                                      
+#define PWR_PDCRF_PF4_Msk            (0x1U << PWR_PDCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
+#define PWR_PDCRF_PF3_Pos            (3U)                                      
+#define PWR_PDCRF_PF3_Msk            (0x1U << PWR_PDCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
+#define PWR_PDCRF_PF2_Pos            (2U)                                      
+#define PWR_PDCRF_PF2_Msk            (0x1U << PWR_PDCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
+#define PWR_PDCRF_PF1_Pos            (1U)                                      
+#define PWR_PDCRF_PF1_Msk            (0x1U << PWR_PDCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
+#define PWR_PDCRF_PF0_Pos            (0U)                                      
+#define PWR_PDCRF_PF0_Msk            (0x1U << PWR_PDCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRG register  ********************/
+#define PWR_PUCRG_PG15_Pos           (15U)                                     
+#define PWR_PUCRG_PG15_Msk           (0x1U << PWR_PUCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
+#define PWR_PUCRG_PG14_Pos           (14U)                                     
+#define PWR_PUCRG_PG14_Msk           (0x1U << PWR_PUCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
+#define PWR_PUCRG_PG13_Pos           (13U)                                     
+#define PWR_PUCRG_PG13_Msk           (0x1U << PWR_PUCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
+#define PWR_PUCRG_PG12_Pos           (12U)                                     
+#define PWR_PUCRG_PG12_Msk           (0x1U << PWR_PUCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
+#define PWR_PUCRG_PG11_Pos           (11U)                                     
+#define PWR_PUCRG_PG11_Msk           (0x1U << PWR_PUCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
+#define PWR_PUCRG_PG10_Pos           (10U)                                     
+#define PWR_PUCRG_PG10_Msk           (0x1U << PWR_PUCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
+#define PWR_PUCRG_PG9_Pos            (9U)                                      
+#define PWR_PUCRG_PG9_Msk            (0x1U << PWR_PUCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
+#define PWR_PUCRG_PG8_Pos            (8U)                                      
+#define PWR_PUCRG_PG8_Msk            (0x1U << PWR_PUCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
+#define PWR_PUCRG_PG7_Pos            (7U)                                      
+#define PWR_PUCRG_PG7_Msk            (0x1U << PWR_PUCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
+#define PWR_PUCRG_PG6_Pos            (6U)                                      
+#define PWR_PUCRG_PG6_Msk            (0x1U << PWR_PUCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
+#define PWR_PUCRG_PG5_Pos            (5U)                                      
+#define PWR_PUCRG_PG5_Msk            (0x1U << PWR_PUCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
+#define PWR_PUCRG_PG4_Pos            (4U)                                      
+#define PWR_PUCRG_PG4_Msk            (0x1U << PWR_PUCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
+#define PWR_PUCRG_PG3_Pos            (3U)                                      
+#define PWR_PUCRG_PG3_Msk            (0x1U << PWR_PUCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
+#define PWR_PUCRG_PG2_Pos            (2U)                                      
+#define PWR_PUCRG_PG2_Msk            (0x1U << PWR_PUCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
+#define PWR_PUCRG_PG1_Pos            (1U)                                      
+#define PWR_PUCRG_PG1_Msk            (0x1U << PWR_PUCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
+#define PWR_PUCRG_PG0_Pos            (0U)                                      
+#define PWR_PUCRG_PG0_Msk            (0x1U << PWR_PUCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRG register  ********************/
+#define PWR_PDCRG_PG15_Pos           (15U)                                     
+#define PWR_PDCRG_PG15_Msk           (0x1U << PWR_PDCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */
+#define PWR_PDCRG_PG14_Pos           (14U)                                     
+#define PWR_PDCRG_PG14_Msk           (0x1U << PWR_PDCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */
+#define PWR_PDCRG_PG13_Pos           (13U)                                     
+#define PWR_PDCRG_PG13_Msk           (0x1U << PWR_PDCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */
+#define PWR_PDCRG_PG12_Pos           (12U)                                     
+#define PWR_PDCRG_PG12_Msk           (0x1U << PWR_PDCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */
+#define PWR_PDCRG_PG11_Pos           (11U)                                     
+#define PWR_PDCRG_PG11_Msk           (0x1U << PWR_PDCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */
+#define PWR_PDCRG_PG10_Pos           (10U)                                     
+#define PWR_PDCRG_PG10_Msk           (0x1U << PWR_PDCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos            (9U)                                      
+#define PWR_PDCRG_PG9_Msk            (0x1U << PWR_PDCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
+#define PWR_PDCRG_PG8_Pos            (8U)                                      
+#define PWR_PDCRG_PG8_Msk            (0x1U << PWR_PDCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
+#define PWR_PDCRG_PG7_Pos            (7U)                                      
+#define PWR_PDCRG_PG7_Msk            (0x1U << PWR_PDCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
+#define PWR_PDCRG_PG6_Pos            (6U)                                      
+#define PWR_PDCRG_PG6_Msk            (0x1U << PWR_PDCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
+#define PWR_PDCRG_PG5_Pos            (5U)                                      
+#define PWR_PDCRG_PG5_Msk            (0x1U << PWR_PDCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
+#define PWR_PDCRG_PG4_Pos            (4U)                                      
+#define PWR_PDCRG_PG4_Msk            (0x1U << PWR_PDCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
+#define PWR_PDCRG_PG3_Pos            (3U)                                      
+#define PWR_PDCRG_PG3_Msk            (0x1U << PWR_PDCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
+#define PWR_PDCRG_PG2_Pos            (2U)                                      
+#define PWR_PDCRG_PG2_Msk            (0x1U << PWR_PDCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
+#define PWR_PDCRG_PG1_Pos            (1U)                                      
+#define PWR_PDCRG_PG1_Msk            (0x1U << PWR_PDCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
+#define PWR_PDCRG_PG0_Pos            (0U)                                      
+#define PWR_PDCRG_PG0_Msk            (0x1U << PWR_PDCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRH register  ********************/
+#define PWR_PUCRH_PH1_Pos            (1U)                                      
+#define PWR_PUCRH_PH1_Msk            (0x1U << PWR_PUCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
+#define PWR_PUCRH_PH0_Pos            (0U)                                      
+#define PWR_PUCRH_PH0_Msk            (0x1U << PWR_PUCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRH register  ********************/
+#define PWR_PDCRH_PH1_Pos            (1U)                                      
+#define PWR_PDCRH_PH1_Msk            (0x1U << PWR_PDCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
+#define PWR_PDCRH_PH0_Pos            (0U)                                      
+#define PWR_PDCRH_PH0_Msk            (0x1U << PWR_PDCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_PLLSAI2_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_MSION_Pos                     (0U)                              
+#define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */
+#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos                    (1U)                              
+#define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos                  (2U)                              
+#define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos                  (3U)                              
+#define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos                  (4U)                              
+#define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos                     (8U)                              
+#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                  (9U)                              
+#define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                    (10U)                             
+#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos                   (11U)                             
+#define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */
+#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos                     (16U)                             
+#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                    (17U)                             
+#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                    (18U)                             
+#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                     (19U)                             
+#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                     (24U)                             
+#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                    (25U)                             
+#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos                 (26U)                             
+#define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos                (27U)                             
+#define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
+#define RCC_CR_PLLSAI2ON_Pos                 (28U)                             
+#define RCC_CR_PLLSAI2ON_Msk                 (0x1U << RCC_CR_PLLSAI2ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */
+#define RCC_CR_PLLSAI2RDY_Pos                (29U)                             
+#define RCC_CR_PLLSAI2RDY_Msk                (0x1U << RCC_CR_PLLSAI2RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos                 (0U)                              
+#define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos                (8U)                              
+#define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                 (16U)                             
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos                (24U)                             
+#define RCC_ICSCR_HSITRIM_Msk                (0x1FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x1F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)                              
+#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)                              
+#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)                              
+#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)                              
+#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)                             
+#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
+#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
+#define RCC_CFGR_MCOSEL_Msk                  (0x7U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [2:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
+#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
+ 
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+ 
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)                              
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk            
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)                              
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)                              
+#define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk              
+#define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)                              
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk              
+#define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)                             
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk            
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)                             
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk              
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)                             
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk            
+
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)                             
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk              
+#define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)                             
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk            
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)                             
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk              
+#define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk      
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk      
+
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                (0U)                              
+#define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk             
+#define RCC_CIER_LSERDYIE_Pos                (1U)                              
+#define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk             
+#define RCC_CIER_MSIRDYIE_Pos                (2U)                              
+#define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk             
+#define RCC_CIER_HSIRDYIE_Pos                (3U)                              
+#define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk             
+#define RCC_CIER_HSERDYIE_Pos                (4U)                              
+#define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk             
+#define RCC_CIER_PLLRDYIE_Pos                (5U)                              
+#define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk             
+#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)                              
+#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk         
+#define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)                              
+#define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk         
+#define RCC_CIER_LSECSSIE_Pos                (9U)                              
+#define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk             
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)                              
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk              
+#define RCC_CIFR_LSERDYF_Pos                 (1U)                              
+#define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk              
+#define RCC_CIFR_MSIRDYF_Pos                 (2U)                              
+#define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk              
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)                              
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk              
+#define RCC_CIFR_HSERDYF_Pos                 (4U)                              
+#define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk              
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)                              
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk              
+#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)                              
+#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk          
+#define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)                              
+#define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk          
+#define RCC_CIFR_CSSF_Pos                    (8U)                              
+#define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk                 
+#define RCC_CIFR_LSECSSF_Pos                 (9U)                              
+#define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk              
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                 (0U)                              
+#define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk              
+#define RCC_CICR_LSERDYC_Pos                 (1U)                              
+#define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk              
+#define RCC_CICR_MSIRDYC_Pos                 (2U)                              
+#define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk              
+#define RCC_CICR_HSIRDYC_Pos                 (3U)                              
+#define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk              
+#define RCC_CICR_HSERDYC_Pos                 (4U)                              
+#define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk              
+#define RCC_CICR_PLLRDYC_Pos                 (5U)                              
+#define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk              
+#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)                              
+#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk          
+#define RCC_CICR_PLLSAI2RDYC_Pos             (7U)                              
+#define RCC_CICR_PLLSAI2RDYC_Msk             (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk          
+#define RCC_CICR_CSSC_Pos                    (8U)                              
+#define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk                 
+#define RCC_CICR_LSECSSC_Pos                 (9U)                              
+#define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk              
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)                              
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk          
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)                              
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk          
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)                              
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk         
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)                             
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk           
+#define RCC_AHB1RSTR_TSCRST_Pos              (16U)                             
+#define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk           
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)                              
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk         
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)                              
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk         
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)                              
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk         
+#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)                              
+#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk         
+#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)                              
+#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk         
+#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)                              
+#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk         
+#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)                              
+#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk         
+#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)                              
+#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk         
+#define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)                             
+#define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk         
+#define RCC_AHB2RSTR_ADCRST_Pos              (13U)                             
+#define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk           
+#define RCC_AHB2RSTR_RNGRST_Pos              (18U)                             
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk           
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FMCRST_Pos              (0U)                              
+#define RCC_AHB3RSTR_FMCRST_Msk              (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk           
+#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)                              
+#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk          
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)                              
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk         
+#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)                              
+#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk         
+#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)                              
+#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk         
+#define RCC_APB1RSTR1_TIM5RST_Pos            (3U)                              
+#define RCC_APB1RSTR1_TIM5RST_Msk            (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk         
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)                              
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk         
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)                              
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk         
+#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)                             
+#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk         
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)                             
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk         
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)                             
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk       
+#define RCC_APB1RSTR1_USART3RST_Pos          (18U)                             
+#define RCC_APB1RSTR1_USART3RST_Msk          (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk       
+#define RCC_APB1RSTR1_UART4RST_Pos           (19U)                             
+#define RCC_APB1RSTR1_UART4RST_Msk           (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk        
+#define RCC_APB1RSTR1_UART5RST_Pos           (20U)                             
+#define RCC_APB1RSTR1_UART5RST_Msk           (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk        
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)                             
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk         
+#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)                             
+#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk         
+#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)                             
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk         
+#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)                             
+#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk         
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)                             
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk          
+#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)                             
+#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk         
+#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)                             
+#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk        
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)                             
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk       
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)                              
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk      
+#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)                              
+#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk       
+#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)                              
+#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk       
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)                              
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk        
+#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)                             
+#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk        
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          
+#define RCC_APB2RSTR_TIM8RST_Pos             (13U)                             
+#define RCC_APB2RSTR_TIM8RST_Msk             (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk          
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)                             
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk         
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)                             
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk         
+#define RCC_APB2RSTR_TIM17RST_Pos            (18U)                             
+#define RCC_APB2RSTR_TIM17RST_Msk            (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk         
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)                             
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk          
+#define RCC_APB2RSTR_SAI2RST_Pos             (22U)                             
+#define RCC_APB2RSTR_SAI2RST_Msk             (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk          
+#define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)                             
+#define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk        
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)                              
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk            
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)                              
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk            
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)                              
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk           
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)                             
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk             
+#define RCC_AHB1ENR_TSCEN_Pos                (16U)                             
+#define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk             
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)                              
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk           
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)                              
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk           
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)                              
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk           
+#define RCC_AHB2ENR_GPIODEN_Pos              (3U)                              
+#define RCC_AHB2ENR_GPIODEN_Msk              (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk           
+#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)                              
+#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk           
+#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)                              
+#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk           
+#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)                              
+#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk           
+#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)                              
+#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk           
+#define RCC_AHB2ENR_OTGFSEN_Pos              (12U)                             
+#define RCC_AHB2ENR_OTGFSEN_Msk              (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk           
+#define RCC_AHB2ENR_ADCEN_Pos                (13U)                             
+#define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk             
+#define RCC_AHB2ENR_RNGEN_Pos                (18U)                             
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_FMCEN_Pos                (0U)                              
+#define RCC_AHB3ENR_FMCEN_Msk                (0x1U << RCC_AHB3ENR_FMCEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk             
+#define RCC_AHB3ENR_QSPIEN_Pos               (8U)                              
+#define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk            
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)                              
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk           
+#define RCC_APB1ENR1_TIM3EN_Pos              (1U)                              
+#define RCC_APB1ENR1_TIM3EN_Msk              (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk           
+#define RCC_APB1ENR1_TIM4EN_Pos              (2U)                              
+#define RCC_APB1ENR1_TIM4EN_Msk              (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk           
+#define RCC_APB1ENR1_TIM5EN_Pos              (3U)                              
+#define RCC_APB1ENR1_TIM5EN_Msk              (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk           
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)                              
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk           
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)                              
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk           
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)                             
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk           
+#define RCC_APB1ENR1_SPI2EN_Pos              (14U)                             
+#define RCC_APB1ENR1_SPI2EN_Msk              (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk           
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)                             
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk           
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)                             
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk         
+#define RCC_APB1ENR1_USART3EN_Pos            (18U)                             
+#define RCC_APB1ENR1_USART3EN_Msk            (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk         
+#define RCC_APB1ENR1_UART4EN_Pos             (19U)                             
+#define RCC_APB1ENR1_UART4EN_Msk             (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk          
+#define RCC_APB1ENR1_UART5EN_Pos             (20U)                             
+#define RCC_APB1ENR1_UART5EN_Msk             (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk          
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)                             
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk           
+#define RCC_APB1ENR1_I2C2EN_Pos              (22U)                             
+#define RCC_APB1ENR1_I2C2EN_Msk              (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk           
+#define RCC_APB1ENR1_I2C3EN_Pos              (23U)                             
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk           
+#define RCC_APB1ENR1_CAN1EN_Pos              (25U)                             
+#define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk           
+#define RCC_APB1ENR1_PWREN_Pos               (28U)                             
+#define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk            
+#define RCC_APB1ENR1_DAC1EN_Pos              (29U)                             
+#define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk           
+#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)                             
+#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk          
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)                             
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk         
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)                              
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk        
+#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)                              
+#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk         
+#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)                              
+#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk         
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)                              
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk          
+#define RCC_APB2ENR_FWEN_Pos                 (7U)                              
+#define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk              
+#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)                             
+#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk          
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            
+#define RCC_APB2ENR_TIM8EN_Pos               (13U)                             
+#define RCC_APB2ENR_TIM8EN_Msk               (0x1U << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk            
+#define RCC_APB2ENR_USART1EN_Pos             (14U)                             
+#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)                             
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk           
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)                             
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk           
+#define RCC_APB2ENR_TIM17EN_Pos              (18U)                             
+#define RCC_APB2ENR_TIM17EN_Msk              (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk           
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)                             
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk            
+#define RCC_APB2ENR_SAI2EN_Pos               (22U)                             
+#define RCC_APB2ENR_SAI2EN_Msk               (0x1U << RCC_APB2ENR_SAI2EN_Pos)  /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk            
+#define RCC_APB2ENR_DFSDM1EN_Pos             (24U)                             
+#define RCC_APB2ENR_DFSDM1EN_Msk             (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk          
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)                              
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk        
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)                              
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk        
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)                              
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk       
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)                              
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk       
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)                             
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk         
+#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)                             
+#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)                              
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk       
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)                              
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)                              
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk       
+#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)                              
+#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)                              
+#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk       
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)                              
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)                              
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)                              
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk       
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)                              
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk       
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)                             
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk       
+#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)                             
+#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk         
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)                             
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+#define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)                              
+#define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk         
+#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)                              
+#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk        
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)                              
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk       
+#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)                              
+#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk       
+#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)                              
+#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk       
+#define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)                              
+#define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk       
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)                              
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk       
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)                              
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk       
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)                             
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk       
+#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)                             
+#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk       
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)                             
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk       
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)                             
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk     
+#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)                             
+#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk     
+#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)                             
+#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk      
+#define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)                             
+#define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk      
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)                             
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk       
+#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)                             
+#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk       
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)                             
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk       
+#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)                             
+#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk       
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)                             
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk        
+#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)                             
+#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk       
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)                             
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk      
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)                             
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk     
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)                              
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk    
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)                              
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk     
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)                              
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk     
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)                              
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk      
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)                             
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk      
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)                             
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk        
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)                             
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk        
+#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)                             
+#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk        
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)                             
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk      
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)                             
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk       
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)                             
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk       
+#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)                             
+#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk       
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)                             
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk        
+#define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)                             
+#define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk        
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)                             
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk      
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos              (0U)                              
+#define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk           
+#define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos              (2U)                              
+#define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk           
+#define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos              (4U)                              
+#define RCC_CCIPR_USART3SEL_Msk              (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk           
+#define RCC_CCIPR_USART3SEL_0                (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1                (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos               (6U)                              
+#define RCC_CCIPR_UART4SEL_Msk               (0x3U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk            
+#define RCC_CCIPR_UART4SEL_0                 (0x1U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1                 (0x2U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000080 */
+
+#define RCC_CCIPR_UART5SEL_Pos               (8U)                              
+#define RCC_CCIPR_UART5SEL_Msk               (0x3U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000300 */
+#define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk            
+#define RCC_CCIPR_UART5SEL_0                 (0x1U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000100 */
+#define RCC_CCIPR_UART5SEL_1                 (0x2U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000200 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)                             
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk          
+#define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)                             
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk             
+#define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos                (14U)                             
+#define RCC_CCIPR_I2C2SEL_Msk                (0x3U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk             
+#define RCC_CCIPR_I2C2SEL_0                  (0x1U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1                  (0x2U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)                             
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk             
+#define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)                             
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk           
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)                             
+#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk           
+#define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos                (22U)                             
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk             
+#define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */
+
+#define RCC_CCIPR_SAI2SEL_Pos                (24U)                             
+#define RCC_CCIPR_SAI2SEL_Msk                (0x3U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x03000000 */
+#define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk             
+#define RCC_CCIPR_SAI2SEL_0                  (0x1U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x01000000 */
+#define RCC_CCIPR_SAI2SEL_1                  (0x2U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x02000000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)                             
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk            
+#define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos                 (28U)                             
+#define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk              
+#define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)                             
+#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk           
+
+#define RCC_CCIPR_DFSDM1SEL_Pos              (31U)                             
+#define RCC_CCIPR_DFSDM1SEL_Msk              (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
+#define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk           
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                   (0U)                              
+#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                
+#define RCC_BDCR_LSERDY_Pos                  (1U)                              
+#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               
+#define RCC_BDCR_LSEBYP_Pos                  (2U)                              
+#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               
+
+#define RCC_BDCR_LSEDRV_Pos                  (3U)                              
+#define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk               
+#define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                (5U)                              
+#define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk             
+#define RCC_BDCR_LSECSSD_Pos                 (6U)                              
+#define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk              
+
+#define RCC_BDCR_RTCSEL_Pos                  (8U)                              
+#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               
+#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                   (15U)                             
+#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                
+#define RCC_BDCR_BDRST_Pos                   (16U)                             
+#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                
+#define RCC_BDCR_LSCOEN_Pos                  (24U)                             
+#define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk               
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)                             
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk              
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                    (0U)                              
+#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 
+#define RCC_CSR_LSIRDY_Pos                   (1U)                              
+#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                
+
+#define RCC_CSR_MSISRANGE_Pos                (8U)                              
+#define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk             
+#define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos                     (23U)                             
+#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  
+#define RCC_CSR_FWRSTF_Pos                   (24U)                             
+#define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk                
+#define RCC_CSR_OBLRSTF_Pos                  (25U)                             
+#define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk               
+#define RCC_CSR_PINRSTF_Pos                  (26U)                             
+#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               
+#define RCC_CSR_BORRSTF_Pos                  (27U)                             
+#define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk               
+#define RCC_CSR_SFTRSTF_Pos                  (28U)                             
+#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)                                   
+#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk                           
+#define RTC_TR_HT_Pos                  (20U)                                   
+#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk                           
+#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)                                   
+#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk                           
+#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)                                   
+#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          
+#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)                                    
+#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          
+#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)                                    
+#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk                           
+#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)                                    
+#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk                           
+#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)                                   
+#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk                           
+#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)                                   
+#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk                           
+#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)                                   
+#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          
+#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)                                   
+#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk                           
+#define RTC_DR_MU_Pos                  (8U)                                    
+#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk                           
+#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)                                    
+#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk                           
+#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)                                    
+#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk                           
+#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)                                   
+#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         
+#define RTC_CR_COE_Pos                 (23U)                                   
+#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk                          
+#define RTC_CR_OSEL_Pos                (21U)                                   
+#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         
+#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)                                   
+#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk                          
+#define RTC_CR_COSEL_Pos               (19U)                                   
+#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos               (17U)                                   
+#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        
+#define RTC_CR_ADD1H_Pos               (16U)                                   
+#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        
+#define RTC_CR_TSIE_Pos                (15U)                                   
+#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         
+#define RTC_CR_WUTIE_Pos               (14U)                                   
+#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        
+#define RTC_CR_ALRBIE_Pos              (13U)                                   
+#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       
+#define RTC_CR_ALRAIE_Pos              (12U)                                   
+#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       
+#define RTC_CR_TSE_Pos                 (11U)                                   
+#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          
+#define RTC_CR_WUTE_Pos                (10U)                                   
+#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         
+#define RTC_CR_ALRBE_Pos               (9U)                                    
+#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        
+#define RTC_CR_ALRAE_Pos               (8U)                                    
+#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        
+#define RTC_CR_FMT_Pos                 (6U)                                    
+#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          
+#define RTC_CR_BYPSHAD_Pos             (5U)                                    
+#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      
+#define RTC_CR_REFCKON_Pos             (4U)                                    
+#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      
+#define RTC_CR_TSEDGE_Pos              (3U)                                    
+#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       
+#define RTC_CR_WUCKSEL_Pos             (0U)                                    
+#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      
+#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)                                   
+#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        
+#define RTC_ISR_RECALPF_Pos            (16U)                                   
+#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     
+#define RTC_ISR_TAMP3F_Pos             (15U)                                   
+#define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      
+#define RTC_ISR_TAMP2F_Pos             (14U)                                   
+#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      
+#define RTC_ISR_TAMP1F_Pos             (13U)                                   
+#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      
+#define RTC_ISR_TSOVF_Pos              (12U)                                   
+#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       
+#define RTC_ISR_TSF_Pos                (11U)                                   
+#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         
+#define RTC_ISR_WUTF_Pos               (10U)                                   
+#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        
+#define RTC_ISR_ALRBF_Pos              (9U)                                    
+#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       
+#define RTC_ISR_ALRAF_Pos              (8U)                                    
+#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       
+#define RTC_ISR_INIT_Pos               (7U)                                    
+#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        
+#define RTC_ISR_INITF_Pos              (6U)                                    
+#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       
+#define RTC_ISR_RSF_Pos                (5U)                                    
+#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         
+#define RTC_ISR_INITS_Pos              (4U)                                    
+#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       
+#define RTC_ISR_SHPF_Pos               (3U)                                    
+#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        
+#define RTC_ISR_WUTWF_Pos              (2U)                                    
+#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       
+#define RTC_ISR_ALRBWF_Pos             (1U)                                    
+#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      
+#define RTC_ISR_ALRAWF_Pos             (0U)                                    
+#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
+#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   
+#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)                                    
+#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     
+#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    
+#define RTC_ALRMAR_DT_Pos              (28U)                                   
+#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       
+#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)                                   
+#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       
+#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     
+#define RTC_ALRMAR_PM_Pos              (22U)                                   
+#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       
+#define RTC_ALRMAR_HT_Pos              (20U)                                   
+#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       
+#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)                                   
+#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       
+#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     
+#define RTC_ALRMAR_MNT_Pos             (12U)                                   
+#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      
+#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)                                    
+#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      
+#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     
+#define RTC_ALRMAR_ST_Pos              (4U)                                    
+#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       
+#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)                                    
+#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       
+#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     
+#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    
+#define RTC_ALRMBR_DT_Pos              (28U)                                   
+#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       
+#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)                                   
+#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       
+#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     
+#define RTC_ALRMBR_PM_Pos              (22U)                                   
+#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       
+#define RTC_ALRMBR_HT_Pos              (20U)                                   
+#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       
+#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)                                   
+#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       
+#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     
+#define RTC_ALRMBR_MNT_Pos             (12U)                                   
+#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      
+#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)                                    
+#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      
+#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     
+#define RTC_ALRMBR_ST_Pos              (4U)                                    
+#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       
+#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)                                    
+#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       
+#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)                                    
+#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)                                    
+#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    
+#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
+#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)                                   
+#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         
+#define RTC_TSTR_HT_Pos                (20U)                                   
+#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         
+#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)                                   
+#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         
+#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)                                   
+#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        
+#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)                                    
+#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        
+#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)                                    
+#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         
+#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)                                    
+#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         
+#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)                                   
+#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        
+#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)                                   
+#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         
+#define RTC_TSDR_MU_Pos                (8U)                                    
+#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         
+#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)                                    
+#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         
+#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)                                    
+#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         
+#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)                                    
+#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)                                   
+#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       
+#define RTC_CALR_CALW8_Pos             (14U)                                   
+#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      
+#define RTC_CALR_CALW16_Pos            (13U)                                   
+#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     
+#define RTC_CALR_CALM_Pos              (0U)                                    
+#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       
+#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)                                   
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)                                   
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)                                   
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  
+#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)                                    
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)                                    
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
+#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)                                    
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
+#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
+
+/********************  Bits definition for RTC_0R register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)                                    
+#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)                                    
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk                           
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)                                    
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk                           
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)                                    
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk                           
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)                                    
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk                           
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)                                    
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk                           
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)                                    
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk                           
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)                                    
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk                           
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)                                    
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk                           
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)                                    
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk                           
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)                                    
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk                           
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)                                    
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk                          
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)                                    
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk                          
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)                                    
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk                          
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)                                    
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk                          
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)                                    
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk                          
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)                                    
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk                          
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)                                    
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk                          
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)                                    
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk                          
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)                                    
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk                          
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)                                    
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk                          
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)                                    
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk                          
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)                                    
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk                          
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)                                    
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk                          
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)                                    
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk                          
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)                                    
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk                          
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)                                    
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk                          
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)                                    
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk                          
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)                                    
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk                          
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)                                    
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk                          
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)                                    
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk                          
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)                                    
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk                          
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)                                    
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk                          
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       32U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos         (0U)                                   
+#define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos          (0U)                                   
+#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */
+#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
+#define SDMMC_CLKCR_CLKEN_Pos           (8U)                                   
+#define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */
+#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
+#define SDMMC_CLKCR_PWRSAV_Pos          (9U)                                   
+#define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */
+#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_BYPASS_Pos          (10U)                                  
+#define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */
+#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos          (11U)                                  
+#define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */
+#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)                                  
+#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */
+#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)                                  
+#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos            (0U)                                   
+#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos          (0U)                                   
+#define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
+
+#define SDMMC_CMD_WAITRESP_Pos          (6U)                                   
+#define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */
+#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000080 */
+
+#define SDMMC_CMD_WAITINT_Pos           (8U)                                   
+#define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */
+#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos          (9U)                                   
+#define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos            (10U)                                  
+#define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */
+#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)                                  
+#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */
+#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)                                   
+#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)                                   
+#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)                                   
+#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)                                   
+#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)                                   
+#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos       (0U)                                   
+#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos       (0U)                                   
+#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos            (0U)                                   
+#define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
+#define SDMMC_DCTRL_DTDIR_Pos           (1U)                                   
+#define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos          (2U)                                   
+#define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
+#define SDMMC_DCTRL_DMAEN_Pos           (3U)                                   
+#define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */
+#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)                                   
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos         (8U)                                   
+#define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
+#define SDMMC_DCTRL_RWSTOP_Pos          (9U)                                   
+#define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
+#define SDMMC_DCTRL_RWMOD_Pos           (10U)                                  
+#define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
+#define SDMMC_DCTRL_SDIOEN_Pos          (11U)                                  
+#define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)                                   
+#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos          (0U)                                   
+#define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos          (1U)                                   
+#define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos          (2U)                                   
+#define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos          (3U)                                   
+#define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos          (4U)                                   
+#define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos           (5U)                                   
+#define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos           (6U)                                   
+#define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos           (7U)                                   
+#define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos           (8U)                                   
+#define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_STBITERR_Pos          (9U)                                   
+#define SDMMC_STA_STBITERR_Msk          (0x1U << SDMMC_STA_STBITERR_Pos)       /*!< 0x00000200 */
+#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDMMC_STA_DBCKEND_Pos           (10U)                                  
+#define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_CMDACT_Pos            (11U)                                  
+#define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
+#define SDMMC_STA_TXACT_Pos             (12U)                                  
+#define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */
+#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
+#define SDMMC_STA_RXACT_Pos             (13U)                                  
+#define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */
+#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
+#define SDMMC_STA_TXFIFOHE_Pos          (14U)                                  
+#define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos          (15U)                                  
+#define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos           (16U)                                  
+#define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos           (17U)                                  
+#define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos           (18U)                                  
+#define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos           (19U)                                  
+#define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
+#define SDMMC_STA_TXDAVL_Pos            (20U)                                  
+#define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
+#define SDMMC_STA_RXDAVL_Pos            (21U)                                  
+#define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */
+#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
+#define SDMMC_STA_SDIOIT_Pos            (22U)                                  
+#define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos         (0U)                                   
+#define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos         (1U)                                   
+#define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)                                   
+#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)                                   
+#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos         (4U)                                   
+#define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos          (5U)                                   
+#define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos          (6U)                                   
+#define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos          (7U)                                   
+#define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos          (8U)                                   
+#define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_STBITERRC_Pos         (9U)                                   
+#define SDMMC_ICR_STBITERRC_Msk         (0x1U << SDMMC_ICR_STBITERRC_Pos)      /*!< 0x00000200 */
+#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos          (10U)                                  
+#define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos           (22U)                                  
+#define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)                                   
+#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)                                   
+#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)                                   
+#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)                                   
+#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)                                   
+#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos        (5U)                                   
+#define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos        (6U)                                   
+#define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos        (7U)                                   
+#define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos        (8U)                                   
+#define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DBCKENDIE_Pos        (10U)                                  
+#define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_CMDACTIE_Pos         (11U)                                  
+#define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
+#define SDMMC_MASK_TXACTIE_Pos          (12U)                                  
+#define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */
+#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
+#define SDMMC_MASK_RXACTIE_Pos          (13U)                                  
+#define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */
+#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
+#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)                                  
+#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)                                  
+#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)                                  
+#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */
+#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)                                  
+#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)                                  
+#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)                                  
+#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */
+#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_TXDAVLIE_Pos         (20U)                                  
+#define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */
+#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
+#define SDMMC_MASK_RXDAVLIE_Pos         (21U)                                  
+#define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */
+#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos         (22U)                                  
+#define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)                                   
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos         (0U)                                   
+#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos         (0U)                                          
+#define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */
+#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos         (1U)                                          
+#define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */
+#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos         (2U)                                          
+#define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */
+#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos           (3U)                                          
+#define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */
+#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */
+#define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */
+#define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos          (6U)                                          
+#define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */
+#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos     (7U)                                          
+#define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos          (8U)                                          
+#define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */
+#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos          (9U)                                          
+#define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */
+#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos       (10U)                                         
+#define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */
+#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos         (11U)                                         
+#define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */
+#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos      (12U)                                         
+#define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos        (13U)                                         
+#define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */
+#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos       (14U)                                         
+#define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos     (15U)                                         
+#define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos      (0U)                                          
+#define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos      (1U)                                          
+#define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos         (2U)                                          
+#define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */
+#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos         (3U)                                          
+#define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */
+#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos          (4U)                                          
+#define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */
+#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos        (5U)                                          
+#define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */
+#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos       (6U)                                          
+#define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos        (7U)                                          
+#define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */
+#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos           (8U)                                          
+#define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */
+#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */
+#define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */
+#define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */
+#define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos        (12U)                                         
+#define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */
+#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos       (13U)                                         
+#define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */
+#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos       (14U)                                         
+#define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */
+#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos          (0U)                                          
+#define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */
+#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos           (1U)                                          
+#define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */
+#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos        (2U)                                          
+#define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */
+#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
+#define SPI_SR_UDR_Pos           (3U)                                          
+#define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */
+#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos        (4U)                                          
+#define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */
+#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos          (5U)                                          
+#define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */
+#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
+#define SPI_SR_OVR_Pos           (6U)                                          
+#define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */
+#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
+#define SPI_SR_BSY_Pos           (7U)                                          
+#define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */
+#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
+#define SPI_SR_FRE_Pos           (8U)                                          
+#define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */
+#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos         (9U)                                          
+#define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */
+#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos         (11U)                                         
+#define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */
+#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos            (0U)                                          
+#define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */
+#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos    (0U)                                          
+#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos     (0U)                                          
+#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos     (0U)                                          
+#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos              (0U)                                    
+#define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */
+#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos           (1U)                                    
+#define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos           (2U)                                    
+#define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos            (3U)                                    
+#define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos          (4U)                                    
+#define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
+#define QUADSPI_CR_FTHRES_Pos          (8U)                                    
+#define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos            (16U)                                   
+#define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos            (17U)                                   
+#define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos            (18U)                                   
+#define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos            (19U)                                   
+#define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos            (20U)                                   
+#define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos            (22U)                                   
+#define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos             (23U)                                   
+#define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos       (24U)                                   
+#define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos         (0U)                                    
+#define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos           (8U)                                    
+#define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos          (16U)                                   
+#define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos             (0U)                                    
+#define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos             (1U)                                    
+#define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos             (2U)                                    
+#define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos             (3U)                                    
+#define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos             (4U)                                    
+#define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos            (5U)                                    
+#define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos          (8U)                                    
+#define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos           (0U)                                    
+#define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos           (1U)                                    
+#define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos           (3U)                                    
+#define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos           (4U)                                    
+#define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos             (0U)                                    
+#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)                                    
+#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos          (8U)                                    
+#define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos         (10U)                                   
+#define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos         (12U)                                   
+#define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos         (14U)                                   
+#define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos         (16U)                                   
+#define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos           (18U)                                   
+#define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos          (24U)                                   
+#define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos          (26U)                                   
+#define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos           (28U)                                   
+#define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DDRM_Pos           (31U)                                   
+#define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos         (0U)                                    
+#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos      (0U)                                    
+#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos            (0U)                                    
+#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos         (0U)                                    
+#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos        (0U)                                    
+#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos       (0U)                                    
+#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)                                    
+#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)                                   
+#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos)    /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */
+
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos          (0U)                                   
+#define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)                                   
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)                                  
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)                                  
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)                                  
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)                                  
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)                                  
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)                                  
+#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos)    /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)                                  
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7U << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7U << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7U << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7U << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7U << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7U << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7U << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7U << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7U << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7U << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7U << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7U << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600U)                      /*!<PG[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000U)                      /*!<PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006U)                      /*!<PG[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060U)                      /*!<PG[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600U)                      /*!<PG[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000U)                      /*!<PG[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)                                   
+#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)                                   
+#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos            (0U)                                   
+#define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos            (1U)                                   
+#define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)                                   
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)                                   
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos            (8U)                                   
+#define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos           (0U)                                   
+#define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos           (1U)                                   
+#define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos           (2U)                                   
+#define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos           (3U)                                   
+#define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos           (4U)                                   
+#define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos           (5U)                                   
+#define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos           (6U)                                   
+#define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos           (7U)                                   
+#define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos           (8U)                                   
+#define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos           (9U)                                   
+#define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos          (10U)                                  
+#define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos          (11U)                                  
+#define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos          (12U)                                  
+#define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos          (13U)                                  
+#define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos          (14U)                                  
+#define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos          (15U)                                  
+#define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
+#define SYSCFG_SWPR_PAGE16_Pos          (16U)                                  
+#define SYSCFG_SWPR_PAGE16_Msk          (0x1U << SYSCFG_SWPR_PAGE16_Pos)       /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/
+#define SYSCFG_SWPR_PAGE17_Pos          (17U)                                  
+#define SYSCFG_SWPR_PAGE17_Msk          (0x1U << SYSCFG_SWPR_PAGE17_Pos)       /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/
+#define SYSCFG_SWPR_PAGE18_Pos          (18U)                                  
+#define SYSCFG_SWPR_PAGE18_Msk          (0x1U << SYSCFG_SWPR_PAGE18_Pos)       /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/
+#define SYSCFG_SWPR_PAGE19_Pos          (19U)                                  
+#define SYSCFG_SWPR_PAGE19_Msk          (0x1U << SYSCFG_SWPR_PAGE19_Pos)       /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/
+#define SYSCFG_SWPR_PAGE20_Pos          (20U)                                  
+#define SYSCFG_SWPR_PAGE20_Msk          (0x1U << SYSCFG_SWPR_PAGE20_Pos)       /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/
+#define SYSCFG_SWPR_PAGE21_Pos          (21U)                                  
+#define SYSCFG_SWPR_PAGE21_Msk          (0x1U << SYSCFG_SWPR_PAGE21_Pos)       /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/
+#define SYSCFG_SWPR_PAGE22_Pos          (22U)                                  
+#define SYSCFG_SWPR_PAGE22_Msk          (0x1U << SYSCFG_SWPR_PAGE22_Pos)       /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/
+#define SYSCFG_SWPR_PAGE23_Pos          (23U)                                  
+#define SYSCFG_SWPR_PAGE23_Msk          (0x1U << SYSCFG_SWPR_PAGE23_Pos)       /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/
+#define SYSCFG_SWPR_PAGE24_Pos          (24U)                                  
+#define SYSCFG_SWPR_PAGE24_Msk          (0x1U << SYSCFG_SWPR_PAGE24_Pos)       /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/
+#define SYSCFG_SWPR_PAGE25_Pos          (25U)                                  
+#define SYSCFG_SWPR_PAGE25_Msk          (0x1U << SYSCFG_SWPR_PAGE25_Pos)       /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/
+#define SYSCFG_SWPR_PAGE26_Pos          (26U)                                  
+#define SYSCFG_SWPR_PAGE26_Msk          (0x1U << SYSCFG_SWPR_PAGE26_Pos)       /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/
+#define SYSCFG_SWPR_PAGE27_Pos          (27U)                                  
+#define SYSCFG_SWPR_PAGE27_Msk          (0x1U << SYSCFG_SWPR_PAGE27_Pos)       /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/
+#define SYSCFG_SWPR_PAGE28_Pos          (28U)                                  
+#define SYSCFG_SWPR_PAGE28_Msk          (0x1U << SYSCFG_SWPR_PAGE28_Pos)       /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/
+#define SYSCFG_SWPR_PAGE29_Pos          (29U)                                  
+#define SYSCFG_SWPR_PAGE29_Msk          (0x1U << SYSCFG_SWPR_PAGE29_Pos)       /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/
+#define SYSCFG_SWPR_PAGE30_Pos          (30U)                                  
+#define SYSCFG_SWPR_PAGE30_Msk          (0x1U << SYSCFG_SWPR_PAGE30_Pos)       /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/
+#define SYSCFG_SWPR_PAGE31_Pos          (31U)                                  
+#define SYSCFG_SWPR_PAGE31_Msk          (0x1U << SYSCFG_SWPR_PAGE31_Pos)       /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos              (0U)                                   
+#define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)                                        
+#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM1_OR1 register  *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)                                    
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
+#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM1_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM1_OR2 register  *******************/
+#define TIM1_OR2_BKINE_Pos             (0U)                                    
+#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKDF1BK0E_Pos         (8U)                                    
+#define TIM1_OR2_BKDF1BK0E_Msk         (0x1U << TIM1_OR2_BKDF1BK0E_Pos)        /*!< 0x00000100 */
+#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM1_OR2_BKINP_Pos             (9U)                                    
+#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM1_OR3 register  *******************/
+#define TIM1_OR3_BK2INE_Pos            (0U)                                    
+#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)                                    
+#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1U << TIM1_OR3_BK2DF1BK1E_Pos)       /*!< 0x00000100 */
+#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */
+#define TIM1_OR3_BK2INP_Pos            (9U)                                    
+#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM8_OR1 register  *******************/
+#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)                                    
+#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000003 */
+#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
+#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000001 */
+#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
+#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM8_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM8_OR1_TI1_RMP_Msk           (0x1U << TIM8_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM8_OR2 register  *******************/
+#define TIM8_OR2_BKINE_Pos             (0U)                                    
+#define TIM8_OR2_BKINE_Msk             (0x1U << TIM8_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM8_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM8_OR2_BKCMP1E_Msk           (0x1U << TIM8_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM8_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM8_OR2_BKCMP2E_Msk           (0x1U << TIM8_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM8_OR2_BKDF1BK2E_Pos         (8U)                                    
+#define TIM8_OR2_BKDF1BK2E_Msk         (0x1U << TIM8_OR2_BKDF1BK2E_Pos)        /*!< 0x00000100 */
+#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM8_OR2_BKINP_Pos             (9U)                                    
+#define TIM8_OR2_BKINP_Msk             (0x1U << TIM8_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM8_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM8_OR2_BKCMP1P_Msk           (0x1U << TIM8_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM8_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM8_OR2_BKCMP2P_Msk           (0x1U << TIM8_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM8_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM8_OR2_ETRSEL_Msk            (0x7U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
+#define TIM8_OR2_ETRSEL_0              (0x1U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM8_OR2_ETRSEL_1              (0x2U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM8_OR2_ETRSEL_2              (0x4U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM8_OR3 register  *******************/
+#define TIM8_OR3_BK2INE_Pos            (0U)                                    
+#define TIM8_OR3_BK2INE_Msk            (0x1U << TIM8_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM8_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM8_OR3_BK2CMP1E_Msk          (0x1U << TIM8_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM8_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM8_OR3_BK2CMP2E_Msk          (0x1U << TIM8_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)                                    
+#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1U << TIM8_OR3_BK2DF1BK3E_Pos)       /*!< 0x00000100 */
+#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */
+#define TIM8_OR3_BK2INP_Pos            (9U)                                    
+#define TIM8_OR3_BK2INP_Msk            (0x1U << TIM8_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM8_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM8_OR3_BK2CMP1P_Msk          (0x1U << TIM8_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM8_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM8_OR3_BK2CMP2P_Msk          (0x1U << TIM8_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_OR1 register  *******************/
+#define TIM2_OR1_ITR1_RMP_Pos     (0U)                                         
+#define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos     (1U)                                         
+#define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos      (2U)                                         
+#define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM2_OR2 register  *******************/
+#define TIM2_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM3_OR1 register  *******************/
+#define TIM3_OR1_TI1_RMP_Pos      (0U)                                         
+#define TIM3_OR1_TI1_RMP_Msk      (0x3U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000003 */
+#define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
+#define TIM3_OR1_TI1_RMP_0        (0x1U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000001 */
+#define TIM3_OR1_TI1_RMP_1        (0x2U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM3_OR2 register  *******************/
+#define TIM3_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM3_OR2_ETRSEL_Msk       (0x7U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
+#define TIM3_OR2_ETRSEL_0         (0x1U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM3_OR2_ETRSEL_1         (0x2U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM3_OR2_ETRSEL_2         (0x4U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM15_OR1 register  ******************/
+#define TIM15_OR1_TI1_RMP_Pos           (0U)                                   
+#define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos      (1U)                                   
+#define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM15_OR2 register  ******************/
+#define TIM15_OR2_BKINE_Pos             (0U)                                   
+#define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */
+#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos           (1U)                                   
+#define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos           (2U)                                   
+#define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKDF1BK0E_Pos         (8U)                                   
+#define TIM15_OR2_BKDF1BK0E_Msk         (0x1U << TIM15_OR2_BKDF1BK0E_Pos)      /*!< 0x00000100 */
+#define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM15_OR2_BKINP_Pos             (9U)                                   
+#define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */
+#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos           (10U)                                  
+#define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos           (11U)                                  
+#define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_OR1 register  ******************/
+#define TIM16_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM16_OR1_TI1_RMP_Msk      (0x3U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM16_OR2 register  ******************/
+#define TIM16_OR2_BKINE_Pos        (0U)                                        
+#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKDF1BK1E_Pos    (8U)                                        
+#define TIM16_OR2_BKDF1BK1E_Msk    (0x1U << TIM16_OR2_BKDF1BK1E_Pos)           /*!< 0x00000100 */
+#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */
+#define TIM16_OR2_BKINP_Pos        (9U)                                        
+#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_OR1 register  ******************/
+#define TIM17_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM17_OR1_TI1_RMP_Msk      (0x3U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
+#define TIM17_OR1_TI1_RMP_0        (0x1U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM17_OR1_TI1_RMP_1        (0x2U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM17_OR2 register  ******************/
+#define TIM17_OR2_BKINE_Pos        (0U)                                        
+#define TIM17_OR2_BKINE_Msk        (0x1U << TIM17_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM17_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM17_OR2_BKCMP1E_Msk      (0x1U << TIM17_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM17_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM17_OR2_BKCMP2E_Msk      (0x1U << TIM17_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM17_OR2_BKDF1BK2E_Pos    (8U)                                        
+#define TIM17_OR2_BKDF1BK2E_Msk    (0x1U << TIM17_OR2_BKDF1BK2E_Pos)           /*!< 0x00000100 */
+#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM17_OR2_BKINP_Pos        (9U)                                        
+#define TIM17_OR2_BKINP_Msk        (0x1U << TIM17_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM17_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM17_OR2_BKCMP1P_Msk      (0x1U << TIM17_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM17_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM17_OR2_BKCMP2P_Msk      (0x1U << TIM17_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)                                       
+#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)                                       
+#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
+#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)                                       
+#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)                                       
+#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)                                       
+#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
+#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
+#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
+#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)                                       
+#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
+#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
+#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
+#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
+#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
+#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)                                       
+#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
+#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
+#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
+#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
+#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
+#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
+#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)                                      
+#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)                                       
+#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
+#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
+#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)                                       
+#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)                                       
+#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)                                       
+#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  ********************/
+#define LPTIM_OR_OR_Pos             (0U)                                       
+#define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */
+#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
+#define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos            (0U)                                        
+#define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos       (2U)                                        
+#define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos        (4U)                                        
+#define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos        (7U)                                        
+#define COMP_CSR_INPSEL_Msk        (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+
+#define COMP_CSR_WINMODE_Pos       (9U)                                        
+#define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */
+#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_POLARITY_Pos      (15U)                                       
+#define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos          (16U)                                       
+#define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */
+#define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos      (18U)                                       
+#define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos         (22U)                                       
+#define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos        (23U)                                       
+#define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_VALUE_Pos         (30U)                                       
+#define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos          (31U)                                       
+#define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)                                  
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos             (1U)                                  
+#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos            (2U)                                  
+#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (4U)                                  
+#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos              (8U)                                  
+#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos              (10U)                                 
+#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos              (12U)                                 
+#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos             (13U)                                 
+#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos           (14U)                                 
+#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos             (15U)                                 
+#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos              (12U)                                
+#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)                                
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP2_CSR_OPALPM_Msk             (0x1U << OPAMP2_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */
+
+#define OPAMP2_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP2_CSR_OPAMODE_Msk            (0x3U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */
+#define OPAMP2_CSR_OPAMODE_0              (0x1U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP2_CSR_OPAMODE_1              (0x2U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP2_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP2_CSR_PGAGAIN_Msk            (0x3U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGAGAIN_0              (0x1U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP2_CSR_PGAGAIN_1              (0x2U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP2_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP2_CSR_VPSEL_Msk              (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_CALON_Pos              (12U)                                
+#define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP2_CSR_CALSEL_Msk             (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)                                  
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)                                  
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_LPOTR register  ****************/
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
+#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
+#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
+#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
+#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos       (7U)                                          
+#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos       (23U)                                         
+#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)                                          
+#define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)                                          
+#define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)                                          
+#define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)                                          
+#define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)                                          
+#define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)                                          
+#define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)                                         
+#define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)                                          
+#define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)                                          
+#define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)                                          
+#define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)                                          
+#define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)                                          
+#define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)                                          
+#define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)                                          
+#define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)                                          
+#define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)                                          
+#define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)                                          
+#define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)                                          
+#define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)                                         
+#define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)                                          
+#define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)                                          
+#define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)                                          
+#define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)                                          
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)                                          
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)                                          
+#define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)                                          
+#define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_SRIE_Pos       (8U)                                          
+#define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_TCIE_Pos       (7U)                                          
+#define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_TIE_Pos        (6U)                                          
+#define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_RIE_Pos        (5U)                                          
+#define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)                                          
+#define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)                                          
+#define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)                                          
+#define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_TXBEIE_Pos     (1U)                                          
+#define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBFIE_Pos     (0U)                                          
+#define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)                                          
+#define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1_Pos    (0U)                                          
+#define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */
+#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)                                          
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)                                          
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)                                          
+#define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)                                          
+#define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)                                           
+#define VREFBUF_CSR_ENVR_Msk    (0x1U << VREFBUF_CSR_ENVR_Pos)                 /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)                                           
+#define VREFBUF_CSR_HIZ_Msk     (0x1U << VREFBUF_CSR_HIZ_Pos)                  /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
+#define VREFBUF_CSR_VRS_Pos     (2U)                                           
+#define VREFBUF_CSR_VRS_Msk     (0x1U << VREFBUF_CSR_VRS_Pos)                  /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRR_Pos     (3U)                                           
+#define VREFBUF_CSR_VRR_Msk     (0x1U << VREFBUF_CSR_VRR_Pos)                  /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos    (0U)                                           
+#define VREFBUF_CCR_TRIM_Msk    (0x3FU << VREFBUF_CCR_TRIM_Pos)                /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)                            
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk        
+
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)                            
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk        
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)                           
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)                           
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)                           
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)                           
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)                           
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)                            
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)                           
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)                           
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)                           
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)                           
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)                           
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)                          
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)                          
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)                          
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)                          
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)                          
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)                          
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)                         
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
+#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)                         
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)                         
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                             
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                         
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)                          
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)                         
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                       (0U)                          
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                        (16U)                         
+#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)                          
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)                          
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)                          
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)                          
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)                         
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)                         
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)                         
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)                         
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)                         
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)                          
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
+#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+
+/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
+#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)                         
+#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
+#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */ 
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)                         
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */ 
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)                         
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ 
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)                         
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */ 
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)                         
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */ 
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)                         
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */ 
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           (16U)                         
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ 
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)                         
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */ 
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)                         
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */ 
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)                         
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */ 
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)                          
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */ 
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)                          
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */ 
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)                          
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)                          
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)                          
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)                          
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */
+
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
+#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
+#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
+#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
+#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+                                                                             
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+                                                                             
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+                                                                              
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+                                                                              
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                                                              
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+                                                                              
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+                                                                               
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+                                                                               
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
+#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
+#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
+#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
+#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
+#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                                ((INSTANCE) == DFSDM1_Filter1) || \
+                                                ((INSTANCE) == DFSDM1_Filter2) || \
+                                                ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* HCD Instances *******************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/******************************* PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                                       ((INSTANCE) == SAI1_Block_B) || \
+                                       ((INSTANCE) == SAI2_Block_A) || \
+                                       ((INSTANCE) == SAI2_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
+                                               ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16)   || \
+                                            ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16)  || \
+                                               ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM3)    || \
+                                                    ((INSTANCE) == TIM4)    || \
+                                                    ((INSTANCE) == TIM5)    || \
+                                                    ((INSTANCE) == TIM8)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16)   || \
+                                                    ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16)  || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2)  || \
+                                                      ((INSTANCE) == TIM3)  || \
+                                                      ((INSTANCE) == TIM4)  || \
+                                                      ((INSTANCE) == TIM5)  || \
+                                                      ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                         ((INSTANCE) == TIM2)   || \
+                                                         ((INSTANCE) == TIM3)   || \
+                                                         ((INSTANCE) == TIM4)   || \
+                                                         ((INSTANCE) == TIM5))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2)  || \
+                                             ((INSTANCE) == TIM3)  || \
+                                             ((INSTANCE) == TIM8))
+      
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4) || \
+                                                       ((INSTANCE) == TIM5) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15) || \
+                                            ((INSTANCE) == TIM16) || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                                  ((INSTANCE) == TIM8))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == UART4)  || \
+                                                 ((INSTANCE) == UART5)  || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3) || \
+                                          ((INSTANCE) == UART4)  || \
+                                          ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn                      ADC1_2_IRQn
+#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn
+#define TIM8_IRQn                      TIM8_UP_IRQn
+#define HASH_RNG_IRQn                  RNG_IRQn
+#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn
+#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn
+#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn
+#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler                ADC1_2_IRQHandler
+#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM8_IRQHandler                TIM8_UP_IRQHandler
+#define HASH_RNG_IRQHandler            RNG_IRQHandler
+#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler
+#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler
+#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler
+#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L475xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l4xx.h
new file mode 100755
index 0000000..1429da9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l4xx.h
@@ -0,0 +1,240 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+#define STM32L475xx           /*!< STM32L475xx Devices */
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  /* #define STM32L486xx */   /*!< STM32L486xx Devices */
+  /* #define STM32L496xx */   /*!< STM32L496xx Devices */
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.3.1
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/system_stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/system_stm32l4xx.h
new file mode 100755
index 0000000..b2b7736
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/system_stm32l4xx.h
@@ -0,0 +1,127 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h
new file mode 100755
index 0000000..e68c4eb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h
new file mode 100755
index 0000000..9f8ff32
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PD_5
+#define STDIO_UART_RX  PD_6
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c
new file mode 100755
index 0000000..fef7dd6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c
@@ -0,0 +1,287 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  5, 0)}, // IN5
+    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  6, 0)}, // IN6
+    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7
+    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8
+    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  9, 0)}, // IN9
+    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
+    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
+    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12
+    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15
+    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16
+    {PC_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  1, 0)}, // IN1
+    {PC_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  2, 0)}, // IN2
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  3, 0)}, // IN3
+    {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
+    {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
+    {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Warning: connected also to GYRO_INT2 pin
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// Warning: TIM5 cannot be used because already used by the us_ticker.
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},  // TIM5_CH1 (used by us_ticker)
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2 (used by us_ticker)
+//  {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+    {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+//  {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3 (used by us_ticker)
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+    {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+//  {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4 (used by us_ticker)
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+//  {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+//  {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+//  {PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+//  {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+//  {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+    {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PB_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N
+    {PB_7,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+//  {PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N
+    {PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3 - Warning: connected also to GYRO_INT2 pin
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4 - Warning: connected also to LCD_COM3 pin
+//  {PB_9,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PB_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+    {PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PB_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+//  {PB_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)},  // TIM8_CH1
+//  {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)},  // TIM8_CH2
+//  {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)},  // TIM8_CH3
+//  {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PC_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)},  // TIM8_CH4
+//  {PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PE_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N - Warning: connected also to LED1
+    {PE_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+    {PE_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PE_12, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+    {PE_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PE_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Warning: UART_2 already used by STDIO
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Warning: Already used by UART_RX
+    {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_4,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_5,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // STDIO_TX
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Warning: UART_2 already used by STDIO
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Warning: Already used by UART_TX
+    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // STDIO_RX
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_1,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_14, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_12, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_4,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_3,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_13, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_11, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PD_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_4,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_5,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PB_7,  UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {NC,    NC,       0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PD_4,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PD_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Warning: does not work on this board due to other components connected on this pin
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PD_1,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // warning: pin used by gyroscope
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // warning: pin used by USB
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PB_9 ,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_12,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h
new file mode 100755
index 0000000..fcb2a41
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h
@@ -0,0 +1,182 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00, // On P1/P2 connectors
+    PA_1  = 0x01, // On P1/P2 connectors
+    PA_2  = 0x02, // On P1/P2 connectors
+    PA_3  = 0x03, // On P1/P2 connectors
+    PA_4  = 0x04,
+    PA_5  = 0x05, // On P1/P2 connectors
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12, // On P1/P2 connectors
+    PB_3  = 0x13, // On P1/P2 connectors
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18, // On P1/P2 connectors
+    PB_9  = 0x19, // On P1/P2 connectors
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E, // On P1/P2 connectors
+    PC_15 = 0x2F, // On P1/P2 connectors
+
+    PD_0  = 0x30, // On P1/P2 connectors
+    PD_1  = 0x31,
+    PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48, // On P1/P2 connectors
+    PE_9  = 0x49,
+    PE_10 = 0x4A, // On P1/P2 connectors
+    PE_11 = 0x4B, // On P1/P2 connectors
+    PE_12 = 0x4C, // On P1/P2 connectors
+    PE_13 = 0x4D, // On P1/P2 connectors
+    PE_14 = 0x4E, // On P1/P2 connectors
+    PE_15 = 0x4F, // On P1/P2 connectors
+
+    PH_0  = 0x70, // On P1/P2 connectors
+    PH_1  = 0x71, // On P1/P2 connectors
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Generic signals namings
+    LED1 = PE_8, // LD5 Green
+    LED2 = PB_2, // LD4 Red
+    LED3 = LED1,
+    LED4 = LED2,
+    JOYSTICK_CENTER = PA_0,
+    JOYSTICK_LEFT = PA_1,
+    JOYSTICK_RIGHT = PA_2,
+    JOYSTICK_UP = PA_3,
+    JOYSTICK_DOWN = PA_5,
+    USER_BUTTON = JOYSTICK_CENTER,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    BUTTON2 = JOYSTICK_LEFT,
+    BUTTON3 = JOYSTICK_RIGHT,
+    BUTTON4 = JOYSTICK_UP, 
+    BUTTON5 = JOYSTICK_DOWN,
+
+    SERIAL_TX = PD_5,
+    SERIAL_RX = PD_6,
+    USBTX = PD_5,
+    USBRX = PD_6,
+
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_9,
+    SPI_MOSI    = PA_7,
+    SPI_MISO    = PA_6,
+    SPI_SCK     = PA_5,
+    SPI_CS      = PA_4,
+    PWM_OUT     = PB_3,
+
+    //USB pins
+    USB_OTG_FS_SOF = PA_8,
+    USB_OTG_FS_VBUS = PA_9,
+    USB_OTG_FS_ID = PA_10,
+    USB_OTG_FS_DM = PA_11,
+    USB_OTG_FS_DP = PA_12,
+    USB_OTG_FS_NOE_ALT = PA_13,
+    USB_OTG_FS_NOE = PC_9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c
new file mode 100755
index 0000000..ee5ac4b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h
new file mode 100755
index 0000000..e89a97b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_2
+#define STDIO_UART_RX  PA_3
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c
new file mode 100755
index 0000000..6431764
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c
@@ -0,0 +1,265 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  5, 0)}, // IN5 - ARDUINO A0
+    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  6, 0)}, // IN6 - ARDUINO A1
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7 // PA_2 is used as SERIAL_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8 // PA_3 is used as SERIAL_RX
+    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  9, 0)}, // IN9 - ARDUINO A2
+    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
+    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
+    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12
+    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3
+    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16
+    {PC_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  1, 0)}, // IN1 - ARDUINO A5
+    {PC_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  2, 0)}, // IN2 - ARDUINO A4
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  3, 0)}, // IN3
+    {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
+    {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
+    {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin)
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// Warning: TIM5 cannot be used because already used by the us_ticker.
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},  // TIM5_CH1 (used by us_ticker)
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2 (used by us_ticker)
+//  {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 // PA_2 is used as SERIAL_TX
+//  {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3 (used by us_ticker)
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4 // PA_3 is used as SERIAL_RX
+//  {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4 (used by us_ticker)
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+//  {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2 - ARDUINO D11
+//  {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+//  {PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+//  {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+//  {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - ARDUINO D3
+    {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1 - ARDUINO D5
+    {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PB_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1 - ARDUINO D10
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N
+    {PB_7,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+//  {PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N
+    {PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+//  {PB_9,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 - ARDUINO D6
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PB_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+    {PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PB_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+//  {PB_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)},  // TIM8_CH1
+//  {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)},  // TIM8_CH2 - ARDUINO D9
+//  {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)},  // TIM8_CH3
+//  {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PC_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)},  // TIM8_CH4
+//  {PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_4,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs
+//  {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+//  {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+ 
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PB_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, 
+//  {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PB_9 ,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_12,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h
new file mode 100755
index 0000000..c78b39c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_2  = 0x32,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Arduino connector namings
+    A0          = PA_0,
+    A1          = PA_1,
+    A2          = PA_4,
+    A3          = PB_0,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_3,
+    D1          = PA_2,
+    D2          = PA_10,
+    D3          = PB_3,
+    D4          = PB_5,
+    D5          = PB_4,
+    D6          = PB_10,
+    D7          = PA_8,
+    D8          = PA_9,
+    D9          = PC_7,
+    D10         = PB_6,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PA_5,
+    LED2        = PA_5,
+    LED3        = PA_5,
+    LED4        = PA_5,
+    USER_BUTTON = PC_13,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PA_2,
+    SERIAL_RX   = PA_3,
+    USBTX       = PA_2,
+    USBRX       = PA_3,
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_9,
+    SPI_MOSI    = PA_7,
+    SPI_MISO    = PA_6,
+    SPI_SCK     = PA_5,
+    SPI_CS      = PB_6,
+    PWM_OUT     = PB_3,
+
+    //USB pins
+    USB_OTG_FS_SOF = PA_8,
+    USB_OTG_FS_VBUS = PA_9,
+    USB_OTG_FS_ID = PA_10,
+    USB_OTG_FS_DM = PA_11,
+    USB_OTG_FS_DP = PA_12,
+    USB_OTG_FS_NOE_ALT = PA_13,
+    USB_OTG_FS_NOE = PC_9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c
new file mode 100755
index 0000000..ee5ac4b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h
new file mode 100755
index 0000000..d260c72
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PC_12
+#define STDIO_UART_RX  PD_2
+#define STDIO_UART     UART_5
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c
new file mode 100755
index 0000000..b2cf6b0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c
@@ -0,0 +1,269 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  5, 0)}, // IN5 - ARDUINO A0
+    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  6, 0)}, // IN6 - ARDUINO A1
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7 // PA_2 is used as SERIAL_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8 // PA_3 is used as SERIAL_RX
+    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  9, 0)}, // IN9 - ARDUINO A2
+    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
+    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
+    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12
+    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3
+    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16
+    {PC_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  1, 0)}, // IN1 - ARDUINO A5
+    {PC_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  2, 0)}, // IN2 - ARDUINO A4
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  3, 0)}, // IN3
+    {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
+    {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
+    {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin)
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// Warning: TIM5 cannot be used because already used by the us_ticker.
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},  // TIM5_CH1 (used by us_ticker)
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2 (used by us_ticker)
+//  {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 // PA_2 is used as SERIAL_TX
+//  {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3 (used by us_ticker)
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4 // PA_3 is used as SERIAL_RX
+//  {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4 (used by us_ticker)
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+//  {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2 - ARDUINO D11
+//  {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+//  {PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+//  {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+//  {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - ARDUINO D3
+    {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1 - ARDUINO D5
+    {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PB_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1 - ARDUINO D10
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N
+    {PB_7,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+//  {PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N
+    {PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+//  {PB_9,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 - ARDUINO D6
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PB_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+    {PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PB_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+//  {PB_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)},  // TIM8_CH1
+//  {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)},  // TIM8_CH2 - ARDUINO D9
+//  {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)},  // TIM8_CH3
+//  {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PC_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)},  // TIM8_CH4
+//  {PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_4,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs
+//  {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+//  {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+ 
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PB_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, 
+//  {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PG_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PG_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PG_9,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PG_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PB_9 ,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_12,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h
new file mode 100755
index 0000000..7a91985
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h
@@ -0,0 +1,168 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_2  = 0x32,
+
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Arduino connector namings
+    A0          = PA_0,
+    A1          = PA_1,
+    A2          = PA_4,
+    A3          = PB_0,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_3,
+    D1          = PA_2,
+    D2          = PA_10,
+    D3          = PB_3,
+    D4          = PB_5,
+    D5          = PB_4,
+    D6          = PB_10,
+    D7          = PA_8,
+    D8          = PA_9,
+    D9          = PC_7,
+    D10         = PB_6,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PG_12,
+    LED2        = PG_12,
+    LED3        = PG_12,
+    LED4        = PG_12,
+    USER_BUTTON = PC_13,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PC_12,
+    SERIAL_RX   = PD_2,
+    USBTX       = PC_12,
+    USBRX       = PD_2,
+    I2C_SCL     = PC_0,
+    I2C_SDA     = PC_1,
+    SPI_MOSI    = PG_11,
+    SPI_MISO    = PG_10,
+    SPI_SCK     = PG_9,
+    SPI_CS      = PG_12,
+    PWM_OUT     = PB_3,
+
+    //USB pins
+    USB_OTG_FS_SOF = PA_8,
+    USB_OTG_FS_VBUS = PA_9,
+    USB_OTG_FS_ID = PA_10,
+    USB_OTG_FS_DM = PA_11,
+    USB_OTG_FS_DP = PA_12,
+    USB_OTG_FS_NOE_ALT = PA_13,
+    USB_OTG_FS_NOE = PC_9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c
new file mode 100755
index 0000000..ee5ac4b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S
new file mode 100755
index 0000000..34373f1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S
@@ -0,0 +1,408 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l476xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+__initial_sp    EQU     0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler)
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     0                                 ; Reserved                
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct
new file mode 100755
index 0000000..a657759
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1 0x20000000 0x00018000  { ; RW data 96k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM2 (0x10000000+0x188) (0x08000-0x188)  {  ; RW data 32k L4-ECC-SRAM2 retained in standby
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S
new file mode 100755
index 0000000..9eba6e1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S
@@ -0,0 +1,390 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l476xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+__initial_sp    EQU     0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     0                                 ; Reserved                
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct
new file mode 100755
index 0000000..a657759
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1 0x20000000 0x00018000  { ; RW data 96k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM2 (0x10000000+0x188) (0x08000-0x188)  {  ; RW data 32k L4-ECC-SRAM2 retained in standby
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld
new file mode 100755
index 0000000..ee23416
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld
@@ -0,0 +1,162 @@
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 1024k
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
+  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > SRAM1
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > SRAM1
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > SRAM1
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM1
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S
new file mode 100755
index 0000000..8e825b1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S
@@ -0,0 +1,513 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l476xx.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      29-April-2016
+  * @brief     STM32L476xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before 
+  // starting main(). software_init_hook() is available and has to be called due 
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	TAMP_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	CAN1_TX_IRQHandler
+	.word	CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	DFSDM1_FLT3_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC3_IRQHandler
+	.word	FMC_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	DFSDM1_FLT0_IRQHandler
+	.word	DFSDM1_FLT1_IRQHandler
+	.word	DFSDM1_FLT2_IRQHandler
+	.word	COMP_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	OTG_FS_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	QUADSPI_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	SWPMI1_IRQHandler
+	.word	TSC_IRQHandler
+	.word	LCD_IRQHandler
+	.word 0
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_IRQHandler
+	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT3_IRQHandler
+	.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC3_IRQHandler
+	.thumb_set ADC3_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT0_IRQHandler
+	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT1_IRQHandler
+	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT2_IRQHandler
+	.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler	
+	
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+	
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+	
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler	
+	
+	.weak	OTG_FS_IRQHandler
+	.thumb_set OTG_FS_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler	
+	
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler	
+	
+	.weak	QUADSPI_IRQHandler
+	.thumb_set QUADSPI_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler	
+	
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+	
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+	
+	.weak	SWPMI1_IRQHandler
+	.thumb_set SWPMI1_IRQHandler,Default_Handler
+	
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+	
+	.weak	LCD_IRQHandler
+	.thumb_set LCD_IRQHandler,Default_Handler
+	
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S
new file mode 100755
index 0000000..8548246
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S
@@ -0,0 +1,637 @@
+;/********************* COPYRIGHT(c) 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l476xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 29-April-2016
+;* Description        : STM32L476xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     LCD_IRQHandler                    ; LCD global interrupt
+        DCD     0                                 ; Reserved        
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+        B ADC3_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+       PUBWEAK LCD_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+LCD_IRQHandler
+       B LCD_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/stm32l476xx.icf b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/stm32l476xx.icf
new file mode 100755
index 0000000..15c4254
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/stm32l476xx.icf
@@ -0,0 +1,38 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__     = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 96kb + 32kb = 0x20000] */
+/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x10000000;
+define symbol __NVIC_end__            = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM2_start__  = 0x10000188;
+define symbol __region_SRAM2_end__    = 0x10007FFF;
+define symbol __region_SRAM1_start__  = 0x20000000;
+define symbol __region_SRAM1_end__    = 0x20017FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+/* Stack 1/8 and Heap 1/4 of RAM */
+define symbol __size_cstack__ = 0x8000;
+define symbol __size_heap__   = 0xa000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in SRAM1_region   { readwrite, block STACKHEAP };
+place in SRAM2_region { };
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/cmsis.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/cmsis.h
new file mode 100755
index 0000000..41a1233
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l4xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/cmsis_nvic.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/cmsis_nvic.h
new file mode 100755
index 0000000..abb7956
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/cmsis_nvic.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
+// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+#define NVIC_NUM_VECTORS        98
+#define NVIC_RAM_VECTOR_ADDRESS 0x10000000    // Vectors positioned at start of SRAM2
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h
new file mode 100755
index 0000000..6c533d1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h
new file mode 100755
index 0000000..6ed0d5b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h
@@ -0,0 +1,18527 @@
+/**
+  ******************************************************************************
+  * @file    stm32l476xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L476xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32l476xx
+  * @{
+  */
+
+#ifndef __STM32L476xx_H
+#define __STM32L476xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
+  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
+  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
+  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
+  LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
+  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
+  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
+                                  short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef  DMA_Request_TypeDef
+
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+  * @brief Firewall
+  */
+
+typedef struct
+{
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+       uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
+  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
+  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
+  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
+  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+  __IO uint32_t ASCR;        /*!< GPIO analog switch control register,   Address offset: 0x2C     */
+
+} GPIO_TypeDef;
+
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LCD
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */
+  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
+  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */
+  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
+  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;    /*!< Reserved  */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
+  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
+} SYSCFG_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/
+  uint32_t Reserved30[2];             /* Reserved                                        030h*/
+  __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/
+  __IO uint32_t CID;                  /* User ID Register                                03Ch*/
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                 040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                 044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                 048h*/
+  __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/
+  uint32_t  Reserved6;                /* Reserved                                        050h*/ 
+  __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/
+  __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/
+  __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/
+   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/
+    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/
+  __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/
+  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/
+  __IO uint32_t DCTL;        /* dev Control Register         804h*/
+  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/
+  uint32_t Reserved0C;       /* Reserved                     80Ch*/
+  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/
+  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/
+  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/
+  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/
+  uint32_t  Reserved20;      /* Reserved                     820h*/
+  uint32_t Reserved9;        /* Reserved                     824h*/
+  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
+  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
+  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
+  __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/
+  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
+  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
+  uint32_t Reserved40;       /* dedicated EP mask           840h*/
+  __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/
+  uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/   
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
+  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;      /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
+#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */
+#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
+
+#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */
+#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE         ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
+#define SRAM2_SIZE            ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+
+#define FMC_BANK1             FMC_BASE
+#define FMC_BANK1_1           FMC_BANK1
+#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)
+#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)
+#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)
+#define FMC_BANK3             (FMC_BASE  + 0x20000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
+
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
+
+#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)
+#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)
+#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)
+
+
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
+
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)
+
+#define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)
+#define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)
+#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)
+#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)
+#define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)
+#define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)
+#define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)
+#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)
+#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)
+#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)
+#define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)
+#define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)
+
+
+#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
+#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+//#define CAN                 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+/* Aliases to keep compatibility after DFSDM renaming */
+#define DFSDM_Channel0      DFSDM1_Channel0
+#define DFSDM_Channel1      DFSDM1_Channel1
+#define DFSDM_Channel2      DFSDM1_Channel2
+#define DFSDM_Channel3      DFSDM1_Channel3
+#define DFSDM_Channel4      DFSDM1_Channel4
+#define DFSDM_Channel5      DFSDM1_Channel5
+#define DFSDM_Channel6      DFSDM1_Channel6
+#define DFSDM_Channel7      DFSDM1_Channel7
+#define DFSDM_Filter0       DFSDM1_Filter0
+#define DFSDM_Filter1       DFSDM1_Filter1
+#define DFSDM_Filter2       DFSDM1_Filter2
+#define DFSDM_Filter3       DFSDM1_Filter3
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)                                    
+#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)                                    
+#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)                                    
+#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)                                    
+#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)                                    
+#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)                                    
+#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)                                    
+#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)                                    
+#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)                                    
+#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)                                    
+#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)                                   
+#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)                                    
+#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)                                    
+#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)                                    
+#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)                                    
+#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)                                    
+#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)                                    
+#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)                                    
+#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)                                    
+#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)                                    
+#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)                                    
+#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)                                   
+#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)                                    
+#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)                                    
+#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)                                    
+#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)                                    
+#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)                                    
+#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)                                    
+#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)                                   
+#define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos             (29U)                                   
+#define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)                                   
+#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)                                   
+#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)                                    
+#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)                                    
+#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)                                    
+#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos             (5U)                                    
+#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos            (6U)                                    
+#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)                                   
+#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)                                   
+#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)                                   
+#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)                                   
+#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos            (16U)                                   
+#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)                                   
+#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)                                   
+#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos               (21U)                                   
+#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)                                   
+#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)                                   
+#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)                                   
+#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)                                   
+#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)                                   
+#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos             (31U)                                   
+#define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)                                    
+#define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)                                    
+#define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos             (2U)                                    
+#define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)                                    
+#define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)                                    
+#define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)                                   
+#define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)                                    
+#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)                                    
+#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)                                    
+#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)                                    
+#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)                                   
+#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)                                   
+#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)                                   
+#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)                                   
+#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)                                   
+#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)                                   
+#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)                                    
+#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)                                    
+#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)                                    
+#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)                                    
+#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)                                   
+#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)                                   
+#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)                                   
+#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)                                   
+#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)                                   
+#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)                                    
+#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
+#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
+#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
+#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
+#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
+#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
+#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
+#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
+#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
+#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
+#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
+#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos                (16U)                                   
+#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
+#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
+#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
+#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
+#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
+#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
+#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
+#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
+#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
+#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
+#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
+#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)                                    
+#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
+#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
+#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
+#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
+#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
+#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
+#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
+#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos                (16U)                                   
+#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
+#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
+#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
+#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
+#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
+#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
+#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
+#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)                                    
+#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
+#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
+#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
+#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
+#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
+#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
+#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
+#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos                (16U)                                   
+#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
+#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
+#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
+#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
+#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
+#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
+#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
+#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)                                    
+#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)                                    
+#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)                                   
+#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)                                   
+#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)                                   
+#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)                                    
+#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)                                    
+#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)                                   
+#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)                                   
+#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)                                   
+#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)                                    
+#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)                                    
+#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)                                   
+#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)                                   
+#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)                                   
+#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)                                    
+#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)                                    
+#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)                                    
+#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)                                    
+#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)                                    
+#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos            (6U)                                    
+#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos              (8U)                                    
+#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos              (14U)                                   
+#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (20U)                                   
+#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (26U)                                   
+#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)                                    
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)                                   
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)                                   
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)                                    
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)                                   
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)                                   
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)                                    
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)                                   
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)                                   
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)                                    
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)                                   
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)                                   
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)                                    
+#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)                                    
+#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)                                    
+#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)                                    
+#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)                                    
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)                                    
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)                                    
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)                                    
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)                                   
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)                                    
+#define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)                                    
+#define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)                                    
+#define ADC_CSR_EOC_MST_Msk            (0x1U << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)                                    
+#define ADC_CSR_EOS_MST_Msk            (0x1U << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)                                    
+#define ADC_CSR_OVR_MST_Msk            (0x1U << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)                                    
+#define ADC_CSR_JEOC_MST_Msk           (0x1U << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)                                    
+#define ADC_CSR_JEOS_MST_Msk           (0x1U << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)                                    
+#define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)                                    
+#define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)                                    
+#define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos          (10U)                                   
+#define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)                                   
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)                                   
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1U << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)                                   
+#define ADC_CSR_EOC_SLV_Msk            (0x1U << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)                                   
+#define ADC_CSR_EOS_SLV_Msk            (0x1U << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)                                   
+#define ADC_CSR_OVR_SLV_Msk            (0x1U << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)                                   
+#define ADC_CSR_JEOC_SLV_Msk           (0x1U << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)                                   
+#define ADC_CSR_JEOS_SLV_Msk           (0x1U << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)                                   
+#define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)                                   
+#define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)                                   
+#define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos          (26U)                                   
+#define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)                                    
+#define ADC_CCR_DUAL_Msk               (0x1FU << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01U << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02U << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04U << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08U << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10U << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)                                    
+#define ADC_CCR_DELAY_Msk              (0xFU << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1U << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2U << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4U << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8U << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos             (13U)                                   
+#define ADC_CCR_DMACFG_Msk             (0x1U << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
+#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos               (14U)                                   
+#define ADC_CCR_MDMA_Msk               (0x3U << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
+#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0                 (0x1U << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1                 (0x2U << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos             (16U)                                   
+#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos              (18U)                                   
+#define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)                                   
+#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos               (23U)                                   
+#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos             (24U)                                   
+#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)                                    
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+#define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)                                   
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+#define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)                                          
+#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)                                      
+#define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)                                      
+#define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)                                      
+#define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)                                      
+#define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)                                      
+#define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)                                      
+#define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)                                       
+#define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)                                      
+#define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)                                       
+#define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)                                      
+#define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)                                       
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)                                       
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)                                       
+#define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)                                      
+#define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)                                       
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)                                      
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)                                  
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)                                  
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)                                  
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)                                  
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)                                  
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)                                   
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)                                   
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1U << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)                                   
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1U << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)                                   
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1U << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)                                   
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)                                   
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)                                   
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)                                   
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)                                  
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)                                  
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)                                  
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)                                   
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)                                   
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)                                   
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)                                  
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)                                  
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1U << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)                                  
+#define DFSDM_FLTCR1_FAST_Msk           (0x1U << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)                                  
+#define DFSDM_FLTCR1_RCH_Msk            (0x7U << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)                                  
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1U << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)                                  
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1U << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)                                  
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1U << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)                                  
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1U << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)                                  
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)                                   
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)                                   
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1U << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)                                   
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1U << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)                                   
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1U << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)                                   
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1U << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)                                   
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1U << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)                                  
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFU << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)                                   
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFU << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)                                   
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1U << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)                                   
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1U << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)                                   
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1U << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)                                   
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1U << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)                                   
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1U << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)                                   
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1U << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)                                   
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1U << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/*****************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)                                  
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFU << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)                                  
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFU << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)                                  
+#define DFSDM_FLTISR_RCIP_Msk           (0x1U << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)                                  
+#define DFSDM_FLTISR_JCIP_Msk           (0x1U << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)                                   
+#define DFSDM_FLTISR_AWDF_Msk           (0x1U << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)                                   
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1U << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)                                   
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1U << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)                                   
+#define DFSDM_FLTISR_REOCF_Msk          (0x1U << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)                                   
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1U << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/*****************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos       (24U)                                  
+#define DFSDM_FLTICR_CLRSCSDF_Msk       (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF           DFSDM_FLTICR_CLRSCSDF_Msk              /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)                                  
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)                                   
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1U << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)                                   
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)                                   
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/*****************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)                                  
+#define DFSDM_FLTFCR_FORD_Msk           (0x7U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)                                  
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFU << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)                                   
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFU << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)                                   
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)                                   
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)                                   
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)                                   
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1U << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)                                   
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)                                   
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)                                   
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)                                   
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)                                   
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)                                   
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)                                   
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)                                   
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)                                   
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)                                   
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)                                   
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)                                   
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos      (0U)                                            
+#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos      (4U)                                            
+#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos      (8U)                                            
+#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos      (12U)                                           
+#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos      (16U)                                           
+#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos      (20U)                                           
+#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos      (24U)                                           
+#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos        (0U)                                          
+#define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos        (1U)                                          
+#define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos        (2U)                                          
+#define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos        (3U)                                          
+#define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos        (4U)                                          
+#define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos        (5U)                                          
+#define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos        (6U)                                          
+#define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos        (7U)                                          
+#define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos        (8U)                                          
+#define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos        (9U)                                          
+#define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos       (10U)                                         
+#define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos       (11U)                                         
+#define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos       (12U)                                         
+#define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos       (13U)                                         
+#define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos       (14U)                                         
+#define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos       (15U)                                         
+#define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos       (16U)                                         
+#define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos       (17U)                                         
+#define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos       (18U)                                         
+#define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos       (19U)                                         
+#define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos       (20U)                                         
+#define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos       (21U)                                         
+#define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos       (22U)                                         
+#define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos       (23U)                                         
+#define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos       (24U)                                         
+#define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos       (25U)                                         
+#define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos       (26U)                                         
+#define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos       (27U)                                         
+#define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos       (28U)                                         
+#define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos       (29U)                                         
+#define EXTI_IMR1_IM29_Msk       (0x1U << EXTI_IMR1_IM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos       (30U)                                         
+#define EXTI_IMR1_IM30_Msk       (0x1U << EXTI_IMR1_IM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos       (31U)                                         
+#define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos         (0U)                                          
+#define EXTI_IMR1_IM_Msk         (0xFFFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos        (0U)                                          
+#define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos        (1U)                                          
+#define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos        (2U)                                          
+#define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos        (3U)                                          
+#define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos        (4U)                                          
+#define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos        (5U)                                          
+#define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos        (6U)                                          
+#define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos        (7U)                                          
+#define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos        (8U)                                          
+#define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos        (9U)                                          
+#define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos       (10U)                                         
+#define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos       (11U)                                         
+#define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos       (12U)                                         
+#define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos       (13U)                                         
+#define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos       (14U)                                         
+#define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos       (15U)                                         
+#define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos       (16U)                                         
+#define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos       (17U)                                         
+#define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos       (18U)                                         
+#define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos       (19U)                                         
+#define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos       (20U)                                         
+#define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos       (21U)                                         
+#define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos       (22U)                                         
+#define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos       (23U)                                         
+#define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos       (24U)                                         
+#define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos       (25U)                                         
+#define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos       (26U)                                         
+#define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos       (27U)                                         
+#define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos       (28U)                                         
+#define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos       (29U)                                         
+#define EXTI_EMR1_EM29_Msk       (0x1U << EXTI_EMR1_EM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos       (30U)                                         
+#define EXTI_EMR1_EM30_Msk       (0x1U << EXTI_EMR1_EM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos       (31U)                                         
+#define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos       (0U)                                          
+#define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos       (1U)                                          
+#define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos       (2U)                                          
+#define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos       (3U)                                          
+#define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos       (4U)                                          
+#define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos       (5U)                                          
+#define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos       (6U)                                          
+#define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos       (7U)                                          
+#define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos       (8U)                                          
+#define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos       (9U)                                          
+#define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos      (10U)                                         
+#define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos      (11U)                                         
+#define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos      (12U)                                         
+#define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos      (13U)                                         
+#define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos      (14U)                                         
+#define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos      (15U)                                         
+#define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos      (16U)                                         
+#define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos      (18U)                                         
+#define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos      (19U)                                         
+#define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos      (20U)                                         
+#define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos      (21U)                                         
+#define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos      (22U)                                         
+#define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos       (0U)                                          
+#define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos       (1U)                                          
+#define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos       (2U)                                          
+#define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos       (3U)                                          
+#define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos       (4U)                                          
+#define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos       (5U)                                          
+#define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos       (6U)                                          
+#define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos       (7U)                                          
+#define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos       (8U)                                          
+#define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos       (9U)                                          
+#define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos      (10U)                                         
+#define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos      (11U)                                         
+#define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos      (12U)                                         
+#define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos      (13U)                                         
+#define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos      (14U)                                         
+#define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos      (15U)                                         
+#define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos      (16U)                                         
+#define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos      (18U)                                         
+#define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos      (19U)                                         
+#define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos      (20U)                                         
+#define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos      (21U)                                         
+#define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos      (22U)                                         
+#define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos     (0U)                                          
+#define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos     (1U)                                          
+#define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos     (2U)                                          
+#define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos     (3U)                                          
+#define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos     (4U)                                          
+#define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos     (5U)                                          
+#define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos     (6U)                                          
+#define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos     (7U)                                          
+#define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos     (8U)                                          
+#define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos     (9U)                                          
+#define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos    (10U)                                         
+#define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos    (11U)                                         
+#define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos    (12U)                                         
+#define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos    (13U)                                         
+#define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos    (14U)                                         
+#define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos    (15U)                                         
+#define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos    (16U)                                         
+#define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos    (18U)                                         
+#define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos    (19U)                                         
+#define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos    (20U)                                         
+#define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos    (21U)                                         
+#define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos    (22U)                                         
+#define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos        (0U)                                          
+#define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos        (1U)                                          
+#define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos        (2U)                                          
+#define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos        (3U)                                          
+#define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos        (4U)                                          
+#define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos        (5U)                                          
+#define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos        (6U)                                          
+#define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos        (7U)                                          
+#define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos        (8U)                                          
+#define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos        (9U)                                          
+#define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos       (10U)                                         
+#define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos       (11U)                                         
+#define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos       (12U)                                         
+#define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos       (13U)                                         
+#define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos       (14U)                                         
+#define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos       (15U)                                         
+#define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos       (16U)                                         
+#define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos       (18U)                                         
+#define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */
+#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos       (19U)                                         
+#define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos       (20U)                                         
+#define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos       (21U)                                         
+#define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos       (22U)                                         
+#define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos       (0U)                                          
+#define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos       (1U)                                          
+#define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos       (2U)                                          
+#define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos       (3U)                                          
+#define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos       (4U)                                          
+#define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos       (5U)                                          
+#define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos       (6U)                                          
+#define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos       (7U)                                          
+#define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM_Pos         (0U)                                          
+#define EXTI_IMR2_IM_Msk         (0xFFU << EXTI_IMR2_IM_Pos)                   /*!< 0x000000FF */
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos       (0U)                                          
+#define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos       (1U)                                          
+#define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos       (2U)                                          
+#define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos       (3U)                                          
+#define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos       (4U)                                          
+#define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos       (5U)                                          
+#define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos       (6U)                                          
+#define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos       (7U)                                          
+#define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT35_Pos      (3U)                                          
+#define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos      (4U)                                          
+#define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos      (5U)                                          
+#define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos      (6U)                                          
+#define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT35_Pos      (3U)                                          
+#define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos      (4U)                                          
+#define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos      (5U)                                          
+#define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos      (6U)                                          
+#define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI35_Pos    (3U)                                          
+#define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos    (4U)                                          
+#define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos    (5U)                                          
+#define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos    (6U)                                          
+#define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF35_Pos       (3U)                                          
+#define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */
+#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos       (4U)                                          
+#define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */
+#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos       (5U)                                          
+#define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */
+#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos       (6U)                                          
+#define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos             (0U)                                 
+#define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                
+#define FLASH_ACR_LATENCY_0WS             (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS             (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS             (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS             (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS             (0x00000004U)
+#define FLASH_ACR_PRFTEN_Pos              (8U)                                 
+#define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk                 
+#define FLASH_ACR_ICEN_Pos                (9U)                                 
+#define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk                   
+#define FLASH_ACR_DCEN_Pos                (10U)                                
+#define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk                   
+#define FLASH_ACR_ICRST_Pos               (11U)                                
+#define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk                  
+#define FLASH_ACR_DCRST_Pos               (12U)                                
+#define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk                  
+#define FLASH_ACR_RUN_PD_Pos              (13U)                                
+#define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)                                
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                  (0U)                                 
+#define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     
+#define FLASH_SR_OPERR_Pos                (1U)                                 
+#define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk                   
+#define FLASH_SR_PROGERR_Pos              (3U)                                 
+#define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk                 
+#define FLASH_SR_WRPERR_Pos               (4U)                                 
+#define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk                  
+#define FLASH_SR_PGAERR_Pos               (5U)                                 
+#define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk                  
+#define FLASH_SR_SIZERR_Pos               (6U)                                 
+#define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk                  
+#define FLASH_SR_PGSERR_Pos               (7U)                                 
+#define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk                  
+#define FLASH_SR_MISERR_Pos               (8U)                                 
+#define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk                  
+#define FLASH_SR_FASTERR_Pos              (9U)                                 
+#define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk                 
+#define FLASH_SR_RDERR_Pos                (14U)                                
+#define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk                   
+#define FLASH_SR_OPTVERR_Pos              (15U)                                
+#define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk                 
+#define FLASH_SR_BSY_Pos                  (16U)                                
+#define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                   (0U)                                 
+#define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk                      
+#define FLASH_CR_PER_Pos                  (1U)                                 
+#define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk                     
+#define FLASH_CR_MER1_Pos                 (2U)                                 
+#define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk                    
+#define FLASH_CR_PNB_Pos                  (3U)                                 
+#define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk                     
+#define FLASH_CR_BKER_Pos                 (11U)                                
+#define FLASH_CR_BKER_Msk                 (0x1U << FLASH_CR_BKER_Pos)          /*!< 0x00000800 */
+#define FLASH_CR_BKER                     FLASH_CR_BKER_Msk                    
+#define FLASH_CR_MER2_Pos                 (15U)                                
+#define FLASH_CR_MER2_Msk                 (0x1U << FLASH_CR_MER2_Pos)          /*!< 0x00008000 */
+#define FLASH_CR_MER2                     FLASH_CR_MER2_Msk                    
+#define FLASH_CR_STRT_Pos                 (16U)                                
+#define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    
+#define FLASH_CR_OPTSTRT_Pos              (17U)                                
+#define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk                 
+#define FLASH_CR_FSTPG_Pos                (18U)                                
+#define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk                   
+#define FLASH_CR_EOPIE_Pos                (24U)                                
+#define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   
+#define FLASH_CR_ERRIE_Pos                (25U)                                
+#define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   
+#define FLASH_CR_RDERRIE_Pos              (26U)                                
+#define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk                 
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)                                
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              
+#define FLASH_CR_OPTLOCK_Pos              (30U)                                
+#define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk                 
+#define FLASH_CR_LOCK_Pos                 (31U)                                
+#define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)                                 
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk              
+#define FLASH_ECCR_BK_ECC_Pos             (19U)                                
+#define FLASH_ECCR_BK_ECC_Msk             (0x1U << FLASH_ECCR_BK_ECC_Pos)      /*!< 0x00080000 */
+#define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk                
+#define FLASH_ECCR_SYSF_ECC_Pos           (20U)                                
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk              
+#define FLASH_ECCR_ECCIE_Pos              (24U)                                
+#define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk                 
+#define FLASH_ECCR_ECCC_Pos               (30U)                                
+#define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk                  
+#define FLASH_ECCR_ECCD_Pos               (31U)                                
+#define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk                  
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                (0U)                                 
+#define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk                   
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)                                 
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk               
+#define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)                                
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk             
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)                                
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk            
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)                                
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk             
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)                                
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk               
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)                                
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk             
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)                                
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk            
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)                                
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk               
+#define FLASH_OPTR_BFB2_Pos               (20U)                                
+#define FLASH_OPTR_BFB2_Msk               (0x1U << FLASH_OPTR_BFB2_Pos)        /*!< 0x00100000 */
+#define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk                  
+#define FLASH_OPTR_DUALBANK_Pos           (21U)                                
+#define FLASH_OPTR_DUALBANK_Msk           (0x1U << FLASH_OPTR_DUALBANK_Pos)    /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk              
+#define FLASH_OPTR_nBOOT1_Pos             (23U)                                
+#define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk                
+#define FLASH_OPTR_SRAM2_PE_Pos           (24U)                                
+#define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk              
+#define FLASH_OPTR_SRAM2_RST_Pos          (25U)                                
+#define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk             
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)                                 
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)                                 
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk        
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)                                
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk         
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)                                 
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk          
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)                                
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk           
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)                                 
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk          
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)                                
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk           
+
+/******************  Bits definition for FLASH_PCROP2SR register  **********/
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)                                 
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP2ER register  ***********/
+#define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)                                 
+#define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk        
+
+/******************  Bits definition for FLASH_WRP2AR register  ***************/
+#define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)                                 
+#define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk          
+#define FLASH_WRP2AR_WRP2A_END_Pos        (16U)                                
+#define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk           
+
+/******************  Bits definition for FLASH_WRP2BR register  ***************/
+#define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)                                 
+#define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk          
+#define FLASH_WRP2BR_WRP2B_END_Pos        (16U)                                
+#define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk           
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)                                       
+#define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)                                        
+#define FMC_BCRx_MBKEN_Msk         (0x1U << FMC_BCRx_MBKEN_Pos)                /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)                                        
+#define FMC_BCRx_MUXEN_Msk         (0x1U << FMC_BCRx_MUXEN_Pos)                /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)                                        
+#define FMC_BCRx_MTYP_Msk          (0x3U << FMC_BCRx_MTYP_Pos)                 /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)                                        
+#define FMC_BCRx_MWID_Msk          (0x3U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)                                        
+#define FMC_BCRx_FACCEN_Msk        (0x1U << FMC_BCRx_FACCEN_Pos)               /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)                                        
+#define FMC_BCRx_BURSTEN_Msk       (0x1U << FMC_BCRx_BURSTEN_Pos)              /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)                                        
+#define FMC_BCRx_WAITPOL_Msk       (0x1U << FMC_BCRx_WAITPOL_Pos)              /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)                                       
+#define FMC_BCRx_WAITCFG_Msk       (0x1U << FMC_BCRx_WAITCFG_Pos)              /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)                                       
+#define FMC_BCRx_WREN_Msk          (0x1U << FMC_BCRx_WREN_Pos)                 /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)                                       
+#define FMC_BCRx_WAITEN_Msk        (0x1U << FMC_BCRx_WAITEN_Pos)               /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)                                       
+#define FMC_BCRx_EXTMOD_Msk        (0x1U << FMC_BCRx_EXTMOD_Pos)               /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)                                       
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1U << FMC_BCRx_ASYNCWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)                                       
+#define FMC_BCRx_CPSIZE_Msk        (0x7U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */
+#define FMC_BCRx_CPSIZE_0          (0x1U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)                                       
+#define FMC_BCRx_CBURSTRW_Msk      (0x1U << FMC_BCRx_CBURSTRW_Pos)             /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)                                        
+#define FMC_BTRx_ADDSET_Msk        (0xFU << FMC_BTRx_ADDSET_Pos)               /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)                                        
+#define FMC_BTRx_ADDHLD_Msk        (0xFU << FMC_BTRx_ADDHLD_Pos)               /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)                                        
+#define FMC_BTRx_DATAST_Msk        (0xFFU << FMC_BTRx_DATAST_Pos)              /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10U << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20U << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40U << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80U << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)                                       
+#define FMC_BTRx_BUSTURN_Msk       (0xFU << FMC_BTRx_BUSTURN_Pos)              /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)                                       
+#define FMC_BTRx_CLKDIV_Msk        (0xFU << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)                                       
+#define FMC_BTRx_DATLAT_Msk        (0xFU << FMC_BTRx_DATLAT_Pos)               /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1U << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2U << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4U << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8U << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)                                       
+#define FMC_BTRx_ACCMOD_Msk        (0x3U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)                                        
+#define FMC_BWTRx_ADDSET_Msk       (0xFU << FMC_BWTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)                                        
+#define FMC_BWTRx_ADDHLD_Msk       (0xFU << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)                                        
+#define FMC_BWTRx_DATAST_Msk       (0xFFU << FMC_BWTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)                                       
+#define FMC_BWTRx_BUSTURN_Msk      (0xFU << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)                                       
+#define FMC_BWTRx_ACCMOD_Msk       (0x3U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  ********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)                                        
+#define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)                                        
+#define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos           (3U)                                        
+#define FMC_PCR_PTYP_Msk           (0x1U << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */
+#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
+
+#define FMC_PCR_PWID_Pos           (4U)                                        
+#define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)                                        
+#define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)                                        
+#define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)                                       
+#define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)                                       
+#define FMC_PCR_ECCPS_Msk          (0x7U << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  ********************/
+#define FMC_SR_IRS_Pos             (0U)                                        
+#define FMC_SR_IRS_Msk             (0x1U << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)                                        
+#define FMC_SR_ILS_Msk             (0x1U << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)                                        
+#define FMC_SR_IFS_Msk             (0x1U << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)                                        
+#define FMC_SR_IREN_Msk            (0x1U << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)                                        
+#define FMC_SR_ILEN_Msk            (0x1U << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)                                        
+#define FMC_SR_IFEN_Msk            (0x1U << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)                                        
+#define FMC_SR_FEMPT_Msk           (0x1U << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos        (0U)                                        
+#define FMC_PMEM_MEMSET_Msk        (0xFFU << FMC_PMEM_MEMSET_Pos)              /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0          (0x01U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos       (8U)                                        
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFU << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0         (0x01U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos       (16U)                                       
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFU << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0         (0x01U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos        (24U)                                       
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFU << FMC_PMEM_MEMHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0          (0x01U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  *******************/
+#define FMC_PATT_ATTSET_Pos        (0U)                                        
+#define FMC_PATT_ATTSET_Msk        (0xFFU << FMC_PATT_ATTSET_Pos)              /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0          (0x01U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos       (8U)                                        
+#define FMC_PATT_ATTWAIT_Msk       (0xFFU << FMC_PATT_ATTWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0         (0x01U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos       (16U)                                       
+#define FMC_PATT_ATTHOLD_Msk       (0xFFU << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0         (0x01U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos        (24U)                                       
+#define FMC_PATT_ATTHIZ_Msk        (0xFFU << FMC_PATT_ATTHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0          (0x01U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR register  *******************/
+#define FMC_ECCR_ECC_Pos           (0U)                                        
+#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFU << FMC_ECCR_ECC_Pos)           /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)                                    
+#define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk                    
+#define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)                                    
+#define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk                    
+#define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)                                    
+#define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk                    
+#define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)                                    
+#define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk                    
+#define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)                                    
+#define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk                    
+#define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)                                   
+#define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk                    
+#define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)                                   
+#define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk                    
+#define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)                                   
+#define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk                    
+#define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)                                   
+#define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk                    
+#define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)                                   
+#define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk                    
+#define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)                                   
+#define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk                   
+#define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)                                   
+#define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk                   
+#define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)                                   
+#define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk                   
+#define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)                                   
+#define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk                   
+#define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)                                   
+#define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk                   
+#define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)                                   
+#define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk                   
+#define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)                                    
+#define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk                     
+#define GPIO_OTYPER_OT1_Pos            (1U)                                    
+#define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk                     
+#define GPIO_OTYPER_OT2_Pos            (2U)                                    
+#define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk                     
+#define GPIO_OTYPER_OT3_Pos            (3U)                                    
+#define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk                     
+#define GPIO_OTYPER_OT4_Pos            (4U)                                    
+#define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk                     
+#define GPIO_OTYPER_OT5_Pos            (5U)                                    
+#define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk                     
+#define GPIO_OTYPER_OT6_Pos            (6U)                                    
+#define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk                     
+#define GPIO_OTYPER_OT7_Pos            (7U)                                    
+#define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk                     
+#define GPIO_OTYPER_OT8_Pos            (8U)                                    
+#define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk                     
+#define GPIO_OTYPER_OT9_Pos            (9U)                                    
+#define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk                     
+#define GPIO_OTYPER_OT10_Pos           (10U)                                   
+#define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk                    
+#define GPIO_OTYPER_OT11_Pos           (11U)                                   
+#define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk                    
+#define GPIO_OTYPER_OT12_Pos           (12U)                                   
+#define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk                    
+#define GPIO_OTYPER_OT13_Pos           (13U)                                   
+#define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk                    
+#define GPIO_OTYPER_OT14_Pos           (14U)                                   
+#define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk                    
+#define GPIO_OTYPER_OT15_Pos           (15U)                                   
+#define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk                    
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)                                    
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk                
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)                                    
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk                
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)                                    
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk                
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)                                    
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk                
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)                                    
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk                
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)                                   
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk                
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)                                   
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk                
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)                                   
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk                
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)                                   
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk                
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)                                   
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk                
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)                                   
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk               
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)                                   
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk               
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)                                   
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk               
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)                                   
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk               
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)                                   
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk               
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)                                   
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk               
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)                                    
+#define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk                    
+#define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)                                    
+#define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk                    
+#define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)                                    
+#define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk                    
+#define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)                                    
+#define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk                    
+#define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)                                    
+#define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk                    
+#define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)                                   
+#define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk                    
+#define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)                                   
+#define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk                    
+#define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)                                   
+#define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk                    
+#define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)                                   
+#define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk                    
+#define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)                                   
+#define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk                    
+#define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)                                   
+#define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk                   
+#define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)                                   
+#define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk                   
+#define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)                                   
+#define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk                   
+#define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)                                   
+#define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk                   
+#define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)                                   
+#define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk                   
+#define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)                                   
+#define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk                   
+#define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)                                    
+#define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk                        
+#define GPIO_IDR_ID1_Pos               (1U)                                    
+#define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk                        
+#define GPIO_IDR_ID2_Pos               (2U)                                    
+#define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk                        
+#define GPIO_IDR_ID3_Pos               (3U)                                    
+#define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk                        
+#define GPIO_IDR_ID4_Pos               (4U)                                    
+#define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk                        
+#define GPIO_IDR_ID5_Pos               (5U)                                    
+#define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk                        
+#define GPIO_IDR_ID6_Pos               (6U)                                    
+#define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk                        
+#define GPIO_IDR_ID7_Pos               (7U)                                    
+#define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk                        
+#define GPIO_IDR_ID8_Pos               (8U)                                    
+#define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk                        
+#define GPIO_IDR_ID9_Pos               (9U)                                    
+#define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk                        
+#define GPIO_IDR_ID10_Pos              (10U)                                   
+#define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk                       
+#define GPIO_IDR_ID11_Pos              (11U)                                   
+#define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk                       
+#define GPIO_IDR_ID12_Pos              (12U)                                   
+#define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk                       
+#define GPIO_IDR_ID13_Pos              (13U)                                   
+#define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk                       
+#define GPIO_IDR_ID14_Pos              (14U)                                   
+#define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk                       
+#define GPIO_IDR_ID15_Pos              (15U)                                   
+#define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk                       
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)                                    
+#define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk                        
+#define GPIO_ODR_OD1_Pos               (1U)                                    
+#define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk                        
+#define GPIO_ODR_OD2_Pos               (2U)                                    
+#define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk                        
+#define GPIO_ODR_OD3_Pos               (3U)                                    
+#define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk                        
+#define GPIO_ODR_OD4_Pos               (4U)                                    
+#define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk                        
+#define GPIO_ODR_OD5_Pos               (5U)                                    
+#define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk                        
+#define GPIO_ODR_OD6_Pos               (6U)                                    
+#define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk                        
+#define GPIO_ODR_OD7_Pos               (7U)                                    
+#define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk                        
+#define GPIO_ODR_OD8_Pos               (8U)                                    
+#define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk                        
+#define GPIO_ODR_OD9_Pos               (9U)                                    
+#define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk                        
+#define GPIO_ODR_OD10_Pos              (10U)                                   
+#define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk                       
+#define GPIO_ODR_OD11_Pos              (11U)                                   
+#define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk                       
+#define GPIO_ODR_OD12_Pos              (12U)                                   
+#define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk                       
+#define GPIO_ODR_OD13_Pos              (13U)                                   
+#define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk                       
+#define GPIO_ODR_OD14_Pos              (14U)                                   
+#define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk                       
+#define GPIO_ODR_OD15_Pos              (15U)                                   
+#define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk                       
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)                                    
+#define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk                       
+#define GPIO_BSRR_BS1_Pos              (1U)                                    
+#define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk                       
+#define GPIO_BSRR_BS2_Pos              (2U)                                    
+#define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk                       
+#define GPIO_BSRR_BS3_Pos              (3U)                                    
+#define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk                       
+#define GPIO_BSRR_BS4_Pos              (4U)                                    
+#define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk                       
+#define GPIO_BSRR_BS5_Pos              (5U)                                    
+#define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk                       
+#define GPIO_BSRR_BS6_Pos              (6U)                                    
+#define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk                       
+#define GPIO_BSRR_BS7_Pos              (7U)                                    
+#define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk                       
+#define GPIO_BSRR_BS8_Pos              (8U)                                    
+#define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk                       
+#define GPIO_BSRR_BS9_Pos              (9U)                                    
+#define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk                       
+#define GPIO_BSRR_BS10_Pos             (10U)                                   
+#define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk                      
+#define GPIO_BSRR_BS11_Pos             (11U)                                   
+#define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk                      
+#define GPIO_BSRR_BS12_Pos             (12U)                                   
+#define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk                      
+#define GPIO_BSRR_BS13_Pos             (13U)                                   
+#define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk                      
+#define GPIO_BSRR_BS14_Pos             (14U)                                   
+#define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk                      
+#define GPIO_BSRR_BS15_Pos             (15U)                                   
+#define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk                      
+#define GPIO_BSRR_BR0_Pos              (16U)                                   
+#define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk                       
+#define GPIO_BSRR_BR1_Pos              (17U)                                   
+#define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk                       
+#define GPIO_BSRR_BR2_Pos              (18U)                                   
+#define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk                       
+#define GPIO_BSRR_BR3_Pos              (19U)                                   
+#define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk                       
+#define GPIO_BSRR_BR4_Pos              (20U)                                   
+#define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk                       
+#define GPIO_BSRR_BR5_Pos              (21U)                                   
+#define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk                       
+#define GPIO_BSRR_BR6_Pos              (22U)                                   
+#define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk                       
+#define GPIO_BSRR_BR7_Pos              (23U)                                   
+#define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk                       
+#define GPIO_BSRR_BR8_Pos              (24U)                                   
+#define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk                       
+#define GPIO_BSRR_BR9_Pos              (25U)                                   
+#define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk                       
+#define GPIO_BSRR_BR10_Pos             (26U)                                   
+#define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk                      
+#define GPIO_BSRR_BR11_Pos             (27U)                                   
+#define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk                      
+#define GPIO_BSRR_BR12_Pos             (28U)                                   
+#define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk                      
+#define GPIO_BSRR_BR13_Pos             (29U)                                   
+#define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk                      
+#define GPIO_BSRR_BR14_Pos             (30U)                                   
+#define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk                      
+#define GPIO_BSRR_BR15_Pos             (31U)                                   
+#define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk                      
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)                                    
+#define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk                      
+#define GPIO_LCKR_LCK1_Pos             (1U)                                    
+#define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk                      
+#define GPIO_LCKR_LCK2_Pos             (2U)                                    
+#define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk                      
+#define GPIO_LCKR_LCK3_Pos             (3U)                                    
+#define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk                      
+#define GPIO_LCKR_LCK4_Pos             (4U)                                    
+#define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk                      
+#define GPIO_LCKR_LCK5_Pos             (5U)                                    
+#define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk                      
+#define GPIO_LCKR_LCK6_Pos             (6U)                                    
+#define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk                      
+#define GPIO_LCKR_LCK7_Pos             (7U)                                    
+#define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk                      
+#define GPIO_LCKR_LCK8_Pos             (8U)                                    
+#define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk                      
+#define GPIO_LCKR_LCK9_Pos             (9U)                                    
+#define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk                      
+#define GPIO_LCKR_LCK10_Pos            (10U)                                   
+#define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk                     
+#define GPIO_LCKR_LCK11_Pos            (11U)                                   
+#define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk                     
+#define GPIO_LCKR_LCK12_Pos            (12U)                                   
+#define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk                     
+#define GPIO_LCKR_LCK13_Pos            (13U)                                   
+#define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk                     
+#define GPIO_LCKR_LCK14_Pos            (14U)                                   
+#define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk                     
+#define GPIO_LCKR_LCK15_Pos            (15U)                                   
+#define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk                     
+#define GPIO_LCKR_LCKK_Pos             (16U)                                   
+#define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk                      
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)                                    
+#define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)                                    
+#define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)                                    
+#define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)                                   
+#define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)                                   
+#define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)                                   
+#define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)                                   
+#define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)                                   
+#define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk                    
+#define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)                                    
+#define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)                                    
+#define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)                                    
+#define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk                   
+#define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)                                   
+#define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk                   
+#define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)                                   
+#define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk                   
+#define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)                                   
+#define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk                   
+#define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)                                   
+#define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk                   
+#define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)                                   
+#define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk                   
+#define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)                                    
+#define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk                        
+#define GPIO_BRR_BR1_Pos               (1U)                                    
+#define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk                        
+#define GPIO_BRR_BR2_Pos               (2U)                                    
+#define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk                        
+#define GPIO_BRR_BR3_Pos               (3U)                                    
+#define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk                        
+#define GPIO_BRR_BR4_Pos               (4U)                                    
+#define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk                        
+#define GPIO_BRR_BR5_Pos               (5U)                                    
+#define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk                        
+#define GPIO_BRR_BR6_Pos               (6U)                                    
+#define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk                        
+#define GPIO_BRR_BR7_Pos               (7U)                                    
+#define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk                        
+#define GPIO_BRR_BR8_Pos               (8U)                                    
+#define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk                        
+#define GPIO_BRR_BR9_Pos               (9U)                                    
+#define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk                        
+#define GPIO_BRR_BR10_Pos              (10U)                                   
+#define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk                       
+#define GPIO_BRR_BR11_Pos              (11U)                                   
+#define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk                       
+#define GPIO_BRR_BR12_Pos              (12U)                                   
+#define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk                       
+#define GPIO_BRR_BR13_Pos              (13U)                                   
+#define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk                       
+#define GPIO_BRR_BR14_Pos              (14U)                                   
+#define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk                       
+#define GPIO_BRR_BR15_Pos              (15U)                                   
+#define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk                       
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+/******************  Bits definition for GPIO_ASCR register  *******************/
+#define GPIO_ASCR_ASC0_Pos             (0U)                                    
+#define GPIO_ASCR_ASC0_Msk             (0x1U << GPIO_ASCR_ASC0_Pos)            /*!< 0x00000001 */
+#define GPIO_ASCR_ASC0                 GPIO_ASCR_ASC0_Msk                      
+#define GPIO_ASCR_ASC1_Pos             (1U)                                    
+#define GPIO_ASCR_ASC1_Msk             (0x1U << GPIO_ASCR_ASC1_Pos)            /*!< 0x00000002 */
+#define GPIO_ASCR_ASC1                 GPIO_ASCR_ASC1_Msk                      
+#define GPIO_ASCR_ASC2_Pos             (2U)                                    
+#define GPIO_ASCR_ASC2_Msk             (0x1U << GPIO_ASCR_ASC2_Pos)            /*!< 0x00000004 */
+#define GPIO_ASCR_ASC2                 GPIO_ASCR_ASC2_Msk                      
+#define GPIO_ASCR_ASC3_Pos             (3U)                                    
+#define GPIO_ASCR_ASC3_Msk             (0x1U << GPIO_ASCR_ASC3_Pos)            /*!< 0x00000008 */
+#define GPIO_ASCR_ASC3                 GPIO_ASCR_ASC3_Msk                      
+#define GPIO_ASCR_ASC4_Pos             (4U)                                    
+#define GPIO_ASCR_ASC4_Msk             (0x1U << GPIO_ASCR_ASC4_Pos)            /*!< 0x00000010 */
+#define GPIO_ASCR_ASC4                 GPIO_ASCR_ASC4_Msk                      
+#define GPIO_ASCR_ASC5_Pos             (5U)                                    
+#define GPIO_ASCR_ASC5_Msk             (0x1U << GPIO_ASCR_ASC5_Pos)            /*!< 0x00000020 */
+#define GPIO_ASCR_ASC5                 GPIO_ASCR_ASC5_Msk                      
+#define GPIO_ASCR_ASC6_Pos             (6U)                                    
+#define GPIO_ASCR_ASC6_Msk             (0x1U << GPIO_ASCR_ASC6_Pos)            /*!< 0x00000040 */
+#define GPIO_ASCR_ASC6                 GPIO_ASCR_ASC6_Msk                      
+#define GPIO_ASCR_ASC7_Pos             (7U)                                    
+#define GPIO_ASCR_ASC7_Msk             (0x1U << GPIO_ASCR_ASC7_Pos)            /*!< 0x00000080 */
+#define GPIO_ASCR_ASC7                 GPIO_ASCR_ASC7_Msk                      
+#define GPIO_ASCR_ASC8_Pos             (8U)                                    
+#define GPIO_ASCR_ASC8_Msk             (0x1U << GPIO_ASCR_ASC8_Pos)            /*!< 0x00000100 */
+#define GPIO_ASCR_ASC8                 GPIO_ASCR_ASC8_Msk                      
+#define GPIO_ASCR_ASC9_Pos             (9U)                                    
+#define GPIO_ASCR_ASC9_Msk             (0x1U << GPIO_ASCR_ASC9_Pos)            /*!< 0x00000200 */
+#define GPIO_ASCR_ASC9                 GPIO_ASCR_ASC9_Msk                      
+#define GPIO_ASCR_ASC10_Pos            (10U)                                   
+#define GPIO_ASCR_ASC10_Msk            (0x1U << GPIO_ASCR_ASC10_Pos)           /*!< 0x00000400 */
+#define GPIO_ASCR_ASC10                GPIO_ASCR_ASC10_Msk                     
+#define GPIO_ASCR_ASC11_Pos            (11U)                                   
+#define GPIO_ASCR_ASC11_Msk            (0x1U << GPIO_ASCR_ASC11_Pos)           /*!< 0x00000800 */
+#define GPIO_ASCR_ASC11                GPIO_ASCR_ASC11_Msk                     
+#define GPIO_ASCR_ASC12_Pos            (12U)                                   
+#define GPIO_ASCR_ASC12_Msk            (0x1U << GPIO_ASCR_ASC12_Pos)           /*!< 0x00001000 */
+#define GPIO_ASCR_ASC12                GPIO_ASCR_ASC12_Msk                     
+#define GPIO_ASCR_ASC13_Pos            (13U)                                   
+#define GPIO_ASCR_ASC13_Msk            (0x1U << GPIO_ASCR_ASC13_Pos)           /*!< 0x00002000 */
+#define GPIO_ASCR_ASC13                GPIO_ASCR_ASC13_Msk                     
+#define GPIO_ASCR_ASC14_Pos            (14U)                                   
+#define GPIO_ASCR_ASC14_Msk            (0x1U << GPIO_ASCR_ASC14_Pos)           /*!< 0x00004000 */
+#define GPIO_ASCR_ASC14                GPIO_ASCR_ASC14_Msk                     
+#define GPIO_ASCR_ASC15_Pos            (15U)                                   
+#define GPIO_ASCR_ASC15_Msk            (0x1U << GPIO_ASCR_ASC15_Pos)           /*!< 0x00008000 */
+#define GPIO_ASCR_ASC15                GPIO_ASCR_ASC15_Msk                     
+
+/* Legacy defines */
+#define GPIO_ASCR_EN_0                      GPIO_ASCR_ASC0
+#define GPIO_ASCR_EN_1                      GPIO_ASCR_ASC1
+#define GPIO_ASCR_EN_2                      GPIO_ASCR_ASC2
+#define GPIO_ASCR_EN_3                      GPIO_ASCR_ASC3
+#define GPIO_ASCR_EN_4                      GPIO_ASCR_ASC4
+#define GPIO_ASCR_EN_5                      GPIO_ASCR_ASC5
+#define GPIO_ASCR_EN_6                      GPIO_ASCR_ASC6
+#define GPIO_ASCR_EN_7                      GPIO_ASCR_ASC7
+#define GPIO_ASCR_EN_8                      GPIO_ASCR_ASC8
+#define GPIO_ASCR_EN_9                      GPIO_ASCR_ASC9
+#define GPIO_ASCR_EN_10                     GPIO_ASCR_ASC10
+#define GPIO_ASCR_EN_11                     GPIO_ASCR_ASC11
+#define GPIO_ASCR_EN_12                     GPIO_ASCR_ASC12
+#define GPIO_ASCR_EN_13                     GPIO_ASCR_ASC13
+#define GPIO_ASCR_EN_14                     GPIO_ASCR_ASC14
+#define GPIO_ASCR_EN_15                     GPIO_ASCR_ASC15
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos            (13U)                                     
+#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
+#define FW_CSSA_ADD_Pos      (8U)                                              
+#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos      (8U)                                              
+#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
+#define FW_NVDSSA_ADD_Pos    (8U)                                              
+#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos    (8U)                                              
+#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos     (6U)                                              
+#define FW_VDSSA_ADD_Msk     (0x7FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos     (6U)                                              
+#define FW_VDSL_LENG_Msk     (0x7FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos        (0U)                                              
+#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos        (1U)                                              
+#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos        (2U)                                              
+#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos              (14U)                                     
+#define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos              (9U)                                      
+#define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos              (8U)                                      
+#define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos             (0U)                                      
+#define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)                                      
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos       (1U)                                      
+#define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)                                      
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)                                      
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_USV_Pos              (10U)                                     
+#define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */
+#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
+#define PWR_CR2_IOSV_Pos             (9U)                                      
+#define PWR_CR2_IOSV_Msk             (0x1U << PWR_CR2_IOSV_Pos)                /*!< 0x00000200 */
+#define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos             (4U)                                      
+#define PWR_CR2_PVME_Msk             (0xFU << PWR_CR2_PVME_Pos)                /*!< 0x000000F0 */
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos            (7U)                                      
+#define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos            (6U)                                      
+#define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos            (5U)                                      
+#define PWR_CR2_PVME2_Msk            (0x1U << PWR_CR2_PVME2_Pos)               /*!< 0x00000020 */
+#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos            (4U)                                      
+#define PWR_CR2_PVME1_Msk            (0x1U << PWR_CR2_PVME1_Pos)               /*!< 0x00000010 */
+#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos              (1U)                                      
+#define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos         (3U)                                      
+#define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos             (0U)                                      
+#define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos             (15U)                                     
+#define PWR_CR3_EIWF_Msk             (0x1U << PWR_CR3_EIWF_Pos)                /*!< 0x00008000 */
+#define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos              (10U)                                     
+#define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos              (8U)                                      
+#define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos            (4U)                                      
+#define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos            (3U)                                      
+#define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos            (2U)                                      
+#define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos            (1U)                                      
+#define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos            (0U)                                      
+#define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos             (0U)                                      
+#define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos             (9U)                                      
+#define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos              (8U)                                      
+#define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos              (4U)                                      
+#define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos              (3U)                                      
+#define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos              (2U)                                      
+#define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos              (1U)                                      
+#define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos              (0U)                                      
+#define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos             (15U)                                     
+#define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos              (8U)                                      
+#define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos              (0U)                                      
+#define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos             (4U)                                      
+#define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos             (3U)                                      
+#define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos             (2U)                                      
+#define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos             (1U)                                      
+#define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos             (0U)                                      
+#define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos            (15U)                                     
+#define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos            (14U)                                     
+#define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos            (13U)                                     
+#define PWR_SR2_PVMO2_Msk            (0x1U << PWR_SR2_PVMO2_Pos)               /*!< 0x00002000 */
+#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos            (12U)                                     
+#define PWR_SR2_PVMO1_Msk            (0x1U << PWR_SR2_PVMO1_Pos)               /*!< 0x00001000 */
+#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos             (11U)                                     
+#define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos             (10U)                                     
+#define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos           (9U)                                      
+#define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos           (8U)                                      
+#define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos             (8U)                                      
+#define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos             (0U)                                      
+#define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos            (4U)                                      
+#define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos            (3U)                                      
+#define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos            (2U)                                      
+#define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos            (1U)                                      
+#define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos            (0U)                                      
+#define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos           (15U)                                     
+#define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos           (13U)                                     
+#define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos           (12U)                                     
+#define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos           (11U)                                     
+#define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos           (10U)                                     
+#define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos            (9U)                                      
+#define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos            (8U)                                      
+#define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos            (7U)                                      
+#define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos            (6U)                                      
+#define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos            (5U)                                      
+#define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos            (4U)                                      
+#define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos            (3U)                                      
+#define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos            (2U)                                      
+#define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos            (1U)                                      
+#define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos            (0U)                                      
+#define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos           (14U)                                     
+#define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos           (12U)                                     
+#define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos           (11U)                                     
+#define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos           (10U)                                     
+#define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos            (9U)                                      
+#define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos            (8U)                                      
+#define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos            (7U)                                      
+#define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos            (6U)                                      
+#define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos            (5U)                                      
+#define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos            (4U)                                      
+#define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos            (3U)                                      
+#define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos            (2U)                                      
+#define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos            (1U)                                      
+#define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos            (0U)                                      
+#define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+#define PWR_PUCRB_PB15_Pos           (15U)                                     
+#define PWR_PUCRB_PB15_Msk           (0x1U << PWR_PUCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos           (14U)                                     
+#define PWR_PUCRB_PB14_Msk           (0x1U << PWR_PUCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos           (13U)                                     
+#define PWR_PUCRB_PB13_Msk           (0x1U << PWR_PUCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos           (12U)                                     
+#define PWR_PUCRB_PB12_Msk           (0x1U << PWR_PUCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos           (11U)                                     
+#define PWR_PUCRB_PB11_Msk           (0x1U << PWR_PUCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos           (10U)                                     
+#define PWR_PUCRB_PB10_Msk           (0x1U << PWR_PUCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos            (9U)                                      
+#define PWR_PUCRB_PB9_Msk            (0x1U << PWR_PUCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
+#define PWR_PUCRB_PB8_Pos            (8U)                                      
+#define PWR_PUCRB_PB8_Msk            (0x1U << PWR_PUCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
+#define PWR_PUCRB_PB7_Pos            (7U)                                      
+#define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos            (6U)                                      
+#define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos            (5U)                                      
+#define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos            (4U)                                      
+#define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos            (3U)                                      
+#define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB2_Pos            (2U)                                      
+#define PWR_PUCRB_PB2_Msk            (0x1U << PWR_PUCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos            (1U)                                      
+#define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos            (0U)                                      
+#define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB15_Pos           (15U)                                     
+#define PWR_PDCRB_PB15_Msk           (0x1U << PWR_PDCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos           (14U)                                     
+#define PWR_PDCRB_PB14_Msk           (0x1U << PWR_PDCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos           (13U)                                     
+#define PWR_PDCRB_PB13_Msk           (0x1U << PWR_PDCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos           (12U)                                     
+#define PWR_PDCRB_PB12_Msk           (0x1U << PWR_PDCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos           (11U)                                     
+#define PWR_PDCRB_PB11_Msk           (0x1U << PWR_PDCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos           (10U)                                     
+#define PWR_PDCRB_PB10_Msk           (0x1U << PWR_PDCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos            (9U)                                      
+#define PWR_PDCRB_PB9_Msk            (0x1U << PWR_PDCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
+#define PWR_PDCRB_PB8_Pos            (8U)                                      
+#define PWR_PDCRB_PB8_Msk            (0x1U << PWR_PDCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
+#define PWR_PDCRB_PB7_Pos            (7U)                                      
+#define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos            (6U)                                      
+#define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos            (5U)                                      
+#define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos            (3U)                                      
+#define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB2_Pos            (2U)                                      
+#define PWR_PDCRB_PB2_Msk            (0x1U << PWR_PDCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos            (1U)                                      
+#define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos            (0U)                                      
+#define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos           (15U)                                     
+#define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos           (14U)                                     
+#define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos           (13U)                                     
+#define PWR_PUCRC_PC13_Msk           (0x1U << PWR_PUCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos           (12U)                                     
+#define PWR_PUCRC_PC12_Msk           (0x1U << PWR_PUCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos           (11U)                                     
+#define PWR_PUCRC_PC11_Msk           (0x1U << PWR_PUCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos           (10U)                                     
+#define PWR_PUCRC_PC10_Msk           (0x1U << PWR_PUCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos            (9U)                                      
+#define PWR_PUCRC_PC9_Msk            (0x1U << PWR_PUCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
+#define PWR_PUCRC_PC8_Pos            (8U)                                      
+#define PWR_PUCRC_PC8_Msk            (0x1U << PWR_PUCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
+#define PWR_PUCRC_PC7_Pos            (7U)                                      
+#define PWR_PUCRC_PC7_Msk            (0x1U << PWR_PUCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
+#define PWR_PUCRC_PC6_Pos            (6U)                                      
+#define PWR_PUCRC_PC6_Msk            (0x1U << PWR_PUCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
+#define PWR_PUCRC_PC5_Pos            (5U)                                      
+#define PWR_PUCRC_PC5_Msk            (0x1U << PWR_PUCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
+#define PWR_PUCRC_PC4_Pos            (4U)                                      
+#define PWR_PUCRC_PC4_Msk            (0x1U << PWR_PUCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
+#define PWR_PUCRC_PC3_Pos            (3U)                                      
+#define PWR_PUCRC_PC3_Msk            (0x1U << PWR_PUCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
+#define PWR_PUCRC_PC2_Pos            (2U)                                      
+#define PWR_PUCRC_PC2_Msk            (0x1U << PWR_PUCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
+#define PWR_PUCRC_PC1_Pos            (1U)                                      
+#define PWR_PUCRC_PC1_Msk            (0x1U << PWR_PUCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
+#define PWR_PUCRC_PC0_Pos            (0U)                                      
+#define PWR_PUCRC_PC0_Msk            (0x1U << PWR_PUCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos           (15U)                                     
+#define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos           (14U)                                     
+#define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos           (13U)                                     
+#define PWR_PDCRC_PC13_Msk           (0x1U << PWR_PDCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos           (12U)                                     
+#define PWR_PDCRC_PC12_Msk           (0x1U << PWR_PDCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos           (11U)                                     
+#define PWR_PDCRC_PC11_Msk           (0x1U << PWR_PDCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos           (10U)                                     
+#define PWR_PDCRC_PC10_Msk           (0x1U << PWR_PDCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos            (9U)                                      
+#define PWR_PDCRC_PC9_Msk            (0x1U << PWR_PDCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
+#define PWR_PDCRC_PC8_Pos            (8U)                                      
+#define PWR_PDCRC_PC8_Msk            (0x1U << PWR_PDCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
+#define PWR_PDCRC_PC7_Pos            (7U)                                      
+#define PWR_PDCRC_PC7_Msk            (0x1U << PWR_PDCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
+#define PWR_PDCRC_PC6_Pos            (6U)                                      
+#define PWR_PDCRC_PC6_Msk            (0x1U << PWR_PDCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
+#define PWR_PDCRC_PC5_Pos            (5U)                                      
+#define PWR_PDCRC_PC5_Msk            (0x1U << PWR_PDCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
+#define PWR_PDCRC_PC4_Pos            (4U)                                      
+#define PWR_PDCRC_PC4_Msk            (0x1U << PWR_PDCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
+#define PWR_PDCRC_PC3_Pos            (3U)                                      
+#define PWR_PDCRC_PC3_Msk            (0x1U << PWR_PDCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
+#define PWR_PDCRC_PC2_Pos            (2U)                                      
+#define PWR_PDCRC_PC2_Msk            (0x1U << PWR_PDCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
+#define PWR_PDCRC_PC1_Pos            (1U)                                      
+#define PWR_PDCRC_PC1_Msk            (0x1U << PWR_PDCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
+#define PWR_PDCRC_PC0_Pos            (0U)                                      
+#define PWR_PDCRC_PC0_Msk            (0x1U << PWR_PDCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRD register  ********************/
+#define PWR_PUCRD_PD15_Pos           (15U)                                     
+#define PWR_PUCRD_PD15_Msk           (0x1U << PWR_PUCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos           (14U)                                     
+#define PWR_PUCRD_PD14_Msk           (0x1U << PWR_PUCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos           (13U)                                     
+#define PWR_PUCRD_PD13_Msk           (0x1U << PWR_PUCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos           (12U)                                     
+#define PWR_PUCRD_PD12_Msk           (0x1U << PWR_PUCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos           (11U)                                     
+#define PWR_PUCRD_PD11_Msk           (0x1U << PWR_PUCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos           (10U)                                     
+#define PWR_PUCRD_PD10_Msk           (0x1U << PWR_PUCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos            (9U)                                      
+#define PWR_PUCRD_PD9_Msk            (0x1U << PWR_PUCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
+#define PWR_PUCRD_PD8_Pos            (8U)                                      
+#define PWR_PUCRD_PD8_Msk            (0x1U << PWR_PUCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
+#define PWR_PUCRD_PD7_Pos            (7U)                                      
+#define PWR_PUCRD_PD7_Msk            (0x1U << PWR_PUCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
+#define PWR_PUCRD_PD6_Pos            (6U)                                      
+#define PWR_PUCRD_PD6_Msk            (0x1U << PWR_PUCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
+#define PWR_PUCRD_PD5_Pos            (5U)                                      
+#define PWR_PUCRD_PD5_Msk            (0x1U << PWR_PUCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
+#define PWR_PUCRD_PD4_Pos            (4U)                                      
+#define PWR_PUCRD_PD4_Msk            (0x1U << PWR_PUCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
+#define PWR_PUCRD_PD3_Pos            (3U)                                      
+#define PWR_PUCRD_PD3_Msk            (0x1U << PWR_PUCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
+#define PWR_PUCRD_PD2_Pos            (2U)                                      
+#define PWR_PUCRD_PD2_Msk            (0x1U << PWR_PUCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
+#define PWR_PUCRD_PD1_Pos            (1U)                                      
+#define PWR_PUCRD_PD1_Msk            (0x1U << PWR_PUCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
+#define PWR_PUCRD_PD0_Pos            (0U)                                      
+#define PWR_PUCRD_PD0_Msk            (0x1U << PWR_PUCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRD register  ********************/
+#define PWR_PDCRD_PD15_Pos           (15U)                                     
+#define PWR_PDCRD_PD15_Msk           (0x1U << PWR_PDCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos           (14U)                                     
+#define PWR_PDCRD_PD14_Msk           (0x1U << PWR_PDCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos           (13U)                                     
+#define PWR_PDCRD_PD13_Msk           (0x1U << PWR_PDCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos           (12U)                                     
+#define PWR_PDCRD_PD12_Msk           (0x1U << PWR_PDCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos           (11U)                                     
+#define PWR_PDCRD_PD11_Msk           (0x1U << PWR_PDCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos           (10U)                                     
+#define PWR_PDCRD_PD10_Msk           (0x1U << PWR_PDCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos            (9U)                                      
+#define PWR_PDCRD_PD9_Msk            (0x1U << PWR_PDCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
+#define PWR_PDCRD_PD8_Pos            (8U)                                      
+#define PWR_PDCRD_PD8_Msk            (0x1U << PWR_PDCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
+#define PWR_PDCRD_PD7_Pos            (7U)                                      
+#define PWR_PDCRD_PD7_Msk            (0x1U << PWR_PDCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
+#define PWR_PDCRD_PD6_Pos            (6U)                                      
+#define PWR_PDCRD_PD6_Msk            (0x1U << PWR_PDCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
+#define PWR_PDCRD_PD5_Pos            (5U)                                      
+#define PWR_PDCRD_PD5_Msk            (0x1U << PWR_PDCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
+#define PWR_PDCRD_PD4_Pos            (4U)                                      
+#define PWR_PDCRD_PD4_Msk            (0x1U << PWR_PDCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
+#define PWR_PDCRD_PD3_Pos            (3U)                                      
+#define PWR_PDCRD_PD3_Msk            (0x1U << PWR_PDCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
+#define PWR_PDCRD_PD2_Pos            (2U)                                      
+#define PWR_PDCRD_PD2_Msk            (0x1U << PWR_PDCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
+#define PWR_PDCRD_PD1_Pos            (1U)                                      
+#define PWR_PDCRD_PD1_Msk            (0x1U << PWR_PDCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
+#define PWR_PDCRD_PD0_Pos            (0U)                                      
+#define PWR_PDCRD_PD0_Msk            (0x1U << PWR_PDCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRE register  ********************/
+#define PWR_PUCRE_PE15_Pos           (15U)                                     
+#define PWR_PUCRE_PE15_Msk           (0x1U << PWR_PUCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos           (14U)                                     
+#define PWR_PUCRE_PE14_Msk           (0x1U << PWR_PUCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos           (13U)                                     
+#define PWR_PUCRE_PE13_Msk           (0x1U << PWR_PUCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos           (12U)                                     
+#define PWR_PUCRE_PE12_Msk           (0x1U << PWR_PUCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos           (11U)                                     
+#define PWR_PUCRE_PE11_Msk           (0x1U << PWR_PUCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos           (10U)                                     
+#define PWR_PUCRE_PE10_Msk           (0x1U << PWR_PUCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos            (9U)                                      
+#define PWR_PUCRE_PE9_Msk            (0x1U << PWR_PUCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
+#define PWR_PUCRE_PE8_Pos            (8U)                                      
+#define PWR_PUCRE_PE8_Msk            (0x1U << PWR_PUCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
+#define PWR_PUCRE_PE7_Pos            (7U)                                      
+#define PWR_PUCRE_PE7_Msk            (0x1U << PWR_PUCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
+#define PWR_PUCRE_PE6_Pos            (6U)                                      
+#define PWR_PUCRE_PE6_Msk            (0x1U << PWR_PUCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
+#define PWR_PUCRE_PE5_Pos            (5U)                                      
+#define PWR_PUCRE_PE5_Msk            (0x1U << PWR_PUCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
+#define PWR_PUCRE_PE4_Pos            (4U)                                      
+#define PWR_PUCRE_PE4_Msk            (0x1U << PWR_PUCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
+#define PWR_PUCRE_PE3_Pos            (3U)                                      
+#define PWR_PUCRE_PE3_Msk            (0x1U << PWR_PUCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
+#define PWR_PUCRE_PE2_Pos            (2U)                                      
+#define PWR_PUCRE_PE2_Msk            (0x1U << PWR_PUCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
+#define PWR_PUCRE_PE1_Pos            (1U)                                      
+#define PWR_PUCRE_PE1_Msk            (0x1U << PWR_PUCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
+#define PWR_PUCRE_PE0_Pos            (0U)                                      
+#define PWR_PUCRE_PE0_Msk            (0x1U << PWR_PUCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRE register  ********************/
+#define PWR_PDCRE_PE15_Pos           (15U)                                     
+#define PWR_PDCRE_PE15_Msk           (0x1U << PWR_PDCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos           (14U)                                     
+#define PWR_PDCRE_PE14_Msk           (0x1U << PWR_PDCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos           (13U)                                     
+#define PWR_PDCRE_PE13_Msk           (0x1U << PWR_PDCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos           (12U)                                     
+#define PWR_PDCRE_PE12_Msk           (0x1U << PWR_PDCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos           (11U)                                     
+#define PWR_PDCRE_PE11_Msk           (0x1U << PWR_PDCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos           (10U)                                     
+#define PWR_PDCRE_PE10_Msk           (0x1U << PWR_PDCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos            (9U)                                      
+#define PWR_PDCRE_PE9_Msk            (0x1U << PWR_PDCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
+#define PWR_PDCRE_PE8_Pos            (8U)                                      
+#define PWR_PDCRE_PE8_Msk            (0x1U << PWR_PDCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
+#define PWR_PDCRE_PE7_Pos            (7U)                                      
+#define PWR_PDCRE_PE7_Msk            (0x1U << PWR_PDCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
+#define PWR_PDCRE_PE6_Pos            (6U)                                      
+#define PWR_PDCRE_PE6_Msk            (0x1U << PWR_PDCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
+#define PWR_PDCRE_PE5_Pos            (5U)                                      
+#define PWR_PDCRE_PE5_Msk            (0x1U << PWR_PDCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
+#define PWR_PDCRE_PE4_Pos            (4U)                                      
+#define PWR_PDCRE_PE4_Msk            (0x1U << PWR_PDCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
+#define PWR_PDCRE_PE3_Pos            (3U)                                      
+#define PWR_PDCRE_PE3_Msk            (0x1U << PWR_PDCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
+#define PWR_PDCRE_PE2_Pos            (2U)                                      
+#define PWR_PDCRE_PE2_Msk            (0x1U << PWR_PDCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
+#define PWR_PDCRE_PE1_Pos            (1U)                                      
+#define PWR_PDCRE_PE1_Msk            (0x1U << PWR_PDCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
+#define PWR_PDCRE_PE0_Pos            (0U)                                      
+#define PWR_PDCRE_PE0_Msk            (0x1U << PWR_PDCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRF register  ********************/
+#define PWR_PUCRF_PF15_Pos           (15U)                                     
+#define PWR_PUCRF_PF15_Msk           (0x1U << PWR_PUCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos           (14U)                                     
+#define PWR_PUCRF_PF14_Msk           (0x1U << PWR_PUCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos           (13U)                                     
+#define PWR_PUCRF_PF13_Msk           (0x1U << PWR_PUCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos           (12U)                                     
+#define PWR_PUCRF_PF12_Msk           (0x1U << PWR_PUCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos           (11U)                                     
+#define PWR_PUCRF_PF11_Msk           (0x1U << PWR_PUCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos           (10U)                                     
+#define PWR_PUCRF_PF10_Msk           (0x1U << PWR_PUCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos            (9U)                                      
+#define PWR_PUCRF_PF9_Msk            (0x1U << PWR_PUCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
+#define PWR_PUCRF_PF8_Pos            (8U)                                      
+#define PWR_PUCRF_PF8_Msk            (0x1U << PWR_PUCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
+#define PWR_PUCRF_PF7_Pos            (7U)                                      
+#define PWR_PUCRF_PF7_Msk            (0x1U << PWR_PUCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
+#define PWR_PUCRF_PF6_Pos            (6U)                                      
+#define PWR_PUCRF_PF6_Msk            (0x1U << PWR_PUCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
+#define PWR_PUCRF_PF5_Pos            (5U)                                      
+#define PWR_PUCRF_PF5_Msk            (0x1U << PWR_PUCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
+#define PWR_PUCRF_PF4_Pos            (4U)                                      
+#define PWR_PUCRF_PF4_Msk            (0x1U << PWR_PUCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
+#define PWR_PUCRF_PF3_Pos            (3U)                                      
+#define PWR_PUCRF_PF3_Msk            (0x1U << PWR_PUCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
+#define PWR_PUCRF_PF2_Pos            (2U)                                      
+#define PWR_PUCRF_PF2_Msk            (0x1U << PWR_PUCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
+#define PWR_PUCRF_PF1_Pos            (1U)                                      
+#define PWR_PUCRF_PF1_Msk            (0x1U << PWR_PUCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
+#define PWR_PUCRF_PF0_Pos            (0U)                                      
+#define PWR_PUCRF_PF0_Msk            (0x1U << PWR_PUCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRF register  ********************/
+#define PWR_PDCRF_PF15_Pos           (15U)                                     
+#define PWR_PDCRF_PF15_Msk           (0x1U << PWR_PDCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
+#define PWR_PDCRF_PF14_Pos           (14U)                                     
+#define PWR_PDCRF_PF14_Msk           (0x1U << PWR_PDCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
+#define PWR_PDCRF_PF13_Pos           (13U)                                     
+#define PWR_PDCRF_PF13_Msk           (0x1U << PWR_PDCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
+#define PWR_PDCRF_PF12_Pos           (12U)                                     
+#define PWR_PDCRF_PF12_Msk           (0x1U << PWR_PDCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
+#define PWR_PDCRF_PF11_Pos           (11U)                                     
+#define PWR_PDCRF_PF11_Msk           (0x1U << PWR_PDCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
+#define PWR_PDCRF_PF10_Pos           (10U)                                     
+#define PWR_PDCRF_PF10_Msk           (0x1U << PWR_PDCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos            (9U)                                      
+#define PWR_PDCRF_PF9_Msk            (0x1U << PWR_PDCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
+#define PWR_PDCRF_PF8_Pos            (8U)                                      
+#define PWR_PDCRF_PF8_Msk            (0x1U << PWR_PDCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
+#define PWR_PDCRF_PF7_Pos            (7U)                                      
+#define PWR_PDCRF_PF7_Msk            (0x1U << PWR_PDCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
+#define PWR_PDCRF_PF6_Pos            (6U)                                      
+#define PWR_PDCRF_PF6_Msk            (0x1U << PWR_PDCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
+#define PWR_PDCRF_PF5_Pos            (5U)                                      
+#define PWR_PDCRF_PF5_Msk            (0x1U << PWR_PDCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
+#define PWR_PDCRF_PF4_Pos            (4U)                                      
+#define PWR_PDCRF_PF4_Msk            (0x1U << PWR_PDCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
+#define PWR_PDCRF_PF3_Pos            (3U)                                      
+#define PWR_PDCRF_PF3_Msk            (0x1U << PWR_PDCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
+#define PWR_PDCRF_PF2_Pos            (2U)                                      
+#define PWR_PDCRF_PF2_Msk            (0x1U << PWR_PDCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
+#define PWR_PDCRF_PF1_Pos            (1U)                                      
+#define PWR_PDCRF_PF1_Msk            (0x1U << PWR_PDCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
+#define PWR_PDCRF_PF0_Pos            (0U)                                      
+#define PWR_PDCRF_PF0_Msk            (0x1U << PWR_PDCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRG register  ********************/
+#define PWR_PUCRG_PG15_Pos           (15U)                                     
+#define PWR_PUCRG_PG15_Msk           (0x1U << PWR_PUCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
+#define PWR_PUCRG_PG14_Pos           (14U)                                     
+#define PWR_PUCRG_PG14_Msk           (0x1U << PWR_PUCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
+#define PWR_PUCRG_PG13_Pos           (13U)                                     
+#define PWR_PUCRG_PG13_Msk           (0x1U << PWR_PUCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
+#define PWR_PUCRG_PG12_Pos           (12U)                                     
+#define PWR_PUCRG_PG12_Msk           (0x1U << PWR_PUCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
+#define PWR_PUCRG_PG11_Pos           (11U)                                     
+#define PWR_PUCRG_PG11_Msk           (0x1U << PWR_PUCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
+#define PWR_PUCRG_PG10_Pos           (10U)                                     
+#define PWR_PUCRG_PG10_Msk           (0x1U << PWR_PUCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
+#define PWR_PUCRG_PG9_Pos            (9U)                                      
+#define PWR_PUCRG_PG9_Msk            (0x1U << PWR_PUCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
+#define PWR_PUCRG_PG8_Pos            (8U)                                      
+#define PWR_PUCRG_PG8_Msk            (0x1U << PWR_PUCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
+#define PWR_PUCRG_PG7_Pos            (7U)                                      
+#define PWR_PUCRG_PG7_Msk            (0x1U << PWR_PUCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
+#define PWR_PUCRG_PG6_Pos            (6U)                                      
+#define PWR_PUCRG_PG6_Msk            (0x1U << PWR_PUCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
+#define PWR_PUCRG_PG5_Pos            (5U)                                      
+#define PWR_PUCRG_PG5_Msk            (0x1U << PWR_PUCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
+#define PWR_PUCRG_PG4_Pos            (4U)                                      
+#define PWR_PUCRG_PG4_Msk            (0x1U << PWR_PUCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
+#define PWR_PUCRG_PG3_Pos            (3U)                                      
+#define PWR_PUCRG_PG3_Msk            (0x1U << PWR_PUCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
+#define PWR_PUCRG_PG2_Pos            (2U)                                      
+#define PWR_PUCRG_PG2_Msk            (0x1U << PWR_PUCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
+#define PWR_PUCRG_PG1_Pos            (1U)                                      
+#define PWR_PUCRG_PG1_Msk            (0x1U << PWR_PUCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
+#define PWR_PUCRG_PG0_Pos            (0U)                                      
+#define PWR_PUCRG_PG0_Msk            (0x1U << PWR_PUCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRG register  ********************/
+#define PWR_PDCRG_PG15_Pos           (15U)                                     
+#define PWR_PDCRG_PG15_Msk           (0x1U << PWR_PDCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */
+#define PWR_PDCRG_PG14_Pos           (14U)                                     
+#define PWR_PDCRG_PG14_Msk           (0x1U << PWR_PDCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */
+#define PWR_PDCRG_PG13_Pos           (13U)                                     
+#define PWR_PDCRG_PG13_Msk           (0x1U << PWR_PDCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */
+#define PWR_PDCRG_PG12_Pos           (12U)                                     
+#define PWR_PDCRG_PG12_Msk           (0x1U << PWR_PDCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */
+#define PWR_PDCRG_PG11_Pos           (11U)                                     
+#define PWR_PDCRG_PG11_Msk           (0x1U << PWR_PDCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */
+#define PWR_PDCRG_PG10_Pos           (10U)                                     
+#define PWR_PDCRG_PG10_Msk           (0x1U << PWR_PDCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos            (9U)                                      
+#define PWR_PDCRG_PG9_Msk            (0x1U << PWR_PDCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
+#define PWR_PDCRG_PG8_Pos            (8U)                                      
+#define PWR_PDCRG_PG8_Msk            (0x1U << PWR_PDCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
+#define PWR_PDCRG_PG7_Pos            (7U)                                      
+#define PWR_PDCRG_PG7_Msk            (0x1U << PWR_PDCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
+#define PWR_PDCRG_PG6_Pos            (6U)                                      
+#define PWR_PDCRG_PG6_Msk            (0x1U << PWR_PDCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
+#define PWR_PDCRG_PG5_Pos            (5U)                                      
+#define PWR_PDCRG_PG5_Msk            (0x1U << PWR_PDCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
+#define PWR_PDCRG_PG4_Pos            (4U)                                      
+#define PWR_PDCRG_PG4_Msk            (0x1U << PWR_PDCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
+#define PWR_PDCRG_PG3_Pos            (3U)                                      
+#define PWR_PDCRG_PG3_Msk            (0x1U << PWR_PDCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
+#define PWR_PDCRG_PG2_Pos            (2U)                                      
+#define PWR_PDCRG_PG2_Msk            (0x1U << PWR_PDCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
+#define PWR_PDCRG_PG1_Pos            (1U)                                      
+#define PWR_PDCRG_PG1_Msk            (0x1U << PWR_PDCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
+#define PWR_PDCRG_PG0_Pos            (0U)                                      
+#define PWR_PDCRG_PG0_Msk            (0x1U << PWR_PDCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRH register  ********************/
+#define PWR_PUCRH_PH1_Pos            (1U)                                      
+#define PWR_PUCRH_PH1_Msk            (0x1U << PWR_PUCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
+#define PWR_PUCRH_PH0_Pos            (0U)                                      
+#define PWR_PUCRH_PH0_Msk            (0x1U << PWR_PUCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRH register  ********************/
+#define PWR_PDCRH_PH1_Pos            (1U)                                      
+#define PWR_PDCRH_PH1_Msk            (0x1U << PWR_PDCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
+#define PWR_PDCRH_PH0_Pos            (0U)                                      
+#define PWR_PDCRH_PH0_Msk            (0x1U << PWR_PDCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_PLLSAI2_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_MSION_Pos                     (0U)                              
+#define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */
+#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos                    (1U)                              
+#define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos                  (2U)                              
+#define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos                  (3U)                              
+#define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos                  (4U)                              
+#define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos                     (8U)                              
+#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                  (9U)                              
+#define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                    (10U)                             
+#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos                   (11U)                             
+#define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */
+#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos                     (16U)                             
+#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                    (17U)                             
+#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                    (18U)                             
+#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                     (19U)                             
+#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                     (24U)                             
+#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                    (25U)                             
+#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos                 (26U)                             
+#define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos                (27U)                             
+#define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
+#define RCC_CR_PLLSAI2ON_Pos                 (28U)                             
+#define RCC_CR_PLLSAI2ON_Msk                 (0x1U << RCC_CR_PLLSAI2ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */
+#define RCC_CR_PLLSAI2RDY_Pos                (29U)                             
+#define RCC_CR_PLLSAI2RDY_Msk                (0x1U << RCC_CR_PLLSAI2RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos                 (0U)                              
+#define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos                (8U)                              
+#define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                 (16U)                             
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos                (24U)                             
+#define RCC_ICSCR_HSITRIM_Msk                (0x1FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x1F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)                              
+#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)                              
+#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)                              
+#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)                              
+#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)                             
+#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
+#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
+#define RCC_CFGR_MCOSEL_Msk                  (0x7U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [2:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
+#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
+ 
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+ 
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)                              
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk            
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)                              
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)                              
+#define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk              
+#define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)                              
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk              
+#define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)                             
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk            
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)                             
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk              
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)                             
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk            
+
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)                             
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk              
+#define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)                             
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk            
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)                             
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk              
+#define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk      
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk      
+
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                (0U)                              
+#define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk             
+#define RCC_CIER_LSERDYIE_Pos                (1U)                              
+#define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk             
+#define RCC_CIER_MSIRDYIE_Pos                (2U)                              
+#define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk             
+#define RCC_CIER_HSIRDYIE_Pos                (3U)                              
+#define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk             
+#define RCC_CIER_HSERDYIE_Pos                (4U)                              
+#define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk             
+#define RCC_CIER_PLLRDYIE_Pos                (5U)                              
+#define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk             
+#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)                              
+#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk         
+#define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)                              
+#define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk         
+#define RCC_CIER_LSECSSIE_Pos                (9U)                              
+#define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk             
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)                              
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk              
+#define RCC_CIFR_LSERDYF_Pos                 (1U)                              
+#define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk              
+#define RCC_CIFR_MSIRDYF_Pos                 (2U)                              
+#define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk              
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)                              
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk              
+#define RCC_CIFR_HSERDYF_Pos                 (4U)                              
+#define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk              
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)                              
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk              
+#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)                              
+#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk          
+#define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)                              
+#define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk          
+#define RCC_CIFR_CSSF_Pos                    (8U)                              
+#define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk                 
+#define RCC_CIFR_LSECSSF_Pos                 (9U)                              
+#define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk              
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                 (0U)                              
+#define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk              
+#define RCC_CICR_LSERDYC_Pos                 (1U)                              
+#define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk              
+#define RCC_CICR_MSIRDYC_Pos                 (2U)                              
+#define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk              
+#define RCC_CICR_HSIRDYC_Pos                 (3U)                              
+#define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk              
+#define RCC_CICR_HSERDYC_Pos                 (4U)                              
+#define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk              
+#define RCC_CICR_PLLRDYC_Pos                 (5U)                              
+#define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk              
+#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)                              
+#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk          
+#define RCC_CICR_PLLSAI2RDYC_Pos             (7U)                              
+#define RCC_CICR_PLLSAI2RDYC_Msk             (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk          
+#define RCC_CICR_CSSC_Pos                    (8U)                              
+#define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk                 
+#define RCC_CICR_LSECSSC_Pos                 (9U)                              
+#define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk              
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)                              
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk          
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)                              
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk          
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)                              
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk         
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)                             
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk           
+#define RCC_AHB1RSTR_TSCRST_Pos              (16U)                             
+#define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk           
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)                              
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk         
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)                              
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk         
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)                              
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk         
+#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)                              
+#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk         
+#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)                              
+#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk         
+#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)                              
+#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk         
+#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)                              
+#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk         
+#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)                              
+#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk         
+#define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)                             
+#define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk         
+#define RCC_AHB2RSTR_ADCRST_Pos              (13U)                             
+#define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk           
+#define RCC_AHB2RSTR_RNGRST_Pos              (18U)                             
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk           
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FMCRST_Pos              (0U)                              
+#define RCC_AHB3RSTR_FMCRST_Msk              (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk           
+#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)                              
+#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk          
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)                              
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk         
+#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)                              
+#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk         
+#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)                              
+#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk         
+#define RCC_APB1RSTR1_TIM5RST_Pos            (3U)                              
+#define RCC_APB1RSTR1_TIM5RST_Msk            (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk         
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)                              
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk         
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)                              
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk         
+#define RCC_APB1RSTR1_LCDRST_Pos             (9U)                              
+#define RCC_APB1RSTR1_LCDRST_Msk             (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR1_LCDRST                 RCC_APB1RSTR1_LCDRST_Msk          
+#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)                             
+#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk         
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)                             
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk         
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)                             
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk       
+#define RCC_APB1RSTR1_USART3RST_Pos          (18U)                             
+#define RCC_APB1RSTR1_USART3RST_Msk          (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk       
+#define RCC_APB1RSTR1_UART4RST_Pos           (19U)                             
+#define RCC_APB1RSTR1_UART4RST_Msk           (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk        
+#define RCC_APB1RSTR1_UART5RST_Pos           (20U)                             
+#define RCC_APB1RSTR1_UART5RST_Msk           (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk        
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)                             
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk         
+#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)                             
+#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk         
+#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)                             
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk         
+#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)                             
+#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk         
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)                             
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk          
+#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)                             
+#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk         
+#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)                             
+#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk        
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)                             
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk       
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)                              
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk      
+#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)                              
+#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk       
+#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)                              
+#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk       
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)                              
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk        
+#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)                             
+#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk        
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          
+#define RCC_APB2RSTR_TIM8RST_Pos             (13U)                             
+#define RCC_APB2RSTR_TIM8RST_Msk             (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk          
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)                             
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk         
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)                             
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk         
+#define RCC_APB2RSTR_TIM17RST_Pos            (18U)                             
+#define RCC_APB2RSTR_TIM17RST_Msk            (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk         
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)                             
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk          
+#define RCC_APB2RSTR_SAI2RST_Pos             (22U)                             
+#define RCC_APB2RSTR_SAI2RST_Msk             (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk          
+#define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)                             
+#define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk        
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)                              
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk            
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)                              
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk            
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)                              
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk           
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)                             
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk             
+#define RCC_AHB1ENR_TSCEN_Pos                (16U)                             
+#define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk             
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)                              
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk           
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)                              
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk           
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)                              
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk           
+#define RCC_AHB2ENR_GPIODEN_Pos              (3U)                              
+#define RCC_AHB2ENR_GPIODEN_Msk              (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk           
+#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)                              
+#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk           
+#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)                              
+#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk           
+#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)                              
+#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk           
+#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)                              
+#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk           
+#define RCC_AHB2ENR_OTGFSEN_Pos              (12U)                             
+#define RCC_AHB2ENR_OTGFSEN_Msk              (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk           
+#define RCC_AHB2ENR_ADCEN_Pos                (13U)                             
+#define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk             
+#define RCC_AHB2ENR_RNGEN_Pos                (18U)                             
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_FMCEN_Pos                (0U)                              
+#define RCC_AHB3ENR_FMCEN_Msk                (0x1U << RCC_AHB3ENR_FMCEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk             
+#define RCC_AHB3ENR_QSPIEN_Pos               (8U)                              
+#define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk            
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)                              
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk           
+#define RCC_APB1ENR1_TIM3EN_Pos              (1U)                              
+#define RCC_APB1ENR1_TIM3EN_Msk              (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk           
+#define RCC_APB1ENR1_TIM4EN_Pos              (2U)                              
+#define RCC_APB1ENR1_TIM4EN_Msk              (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk           
+#define RCC_APB1ENR1_TIM5EN_Pos              (3U)                              
+#define RCC_APB1ENR1_TIM5EN_Msk              (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk           
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)                              
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk           
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)                              
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk           
+#define RCC_APB1ENR1_LCDEN_Pos               (9U)                              
+#define RCC_APB1ENR1_LCDEN_Msk               (0x1U << RCC_APB1ENR1_LCDEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LCDEN                   RCC_APB1ENR1_LCDEN_Msk            
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)                             
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk           
+#define RCC_APB1ENR1_SPI2EN_Pos              (14U)                             
+#define RCC_APB1ENR1_SPI2EN_Msk              (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk           
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)                             
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk           
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)                             
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk         
+#define RCC_APB1ENR1_USART3EN_Pos            (18U)                             
+#define RCC_APB1ENR1_USART3EN_Msk            (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk         
+#define RCC_APB1ENR1_UART4EN_Pos             (19U)                             
+#define RCC_APB1ENR1_UART4EN_Msk             (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk          
+#define RCC_APB1ENR1_UART5EN_Pos             (20U)                             
+#define RCC_APB1ENR1_UART5EN_Msk             (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk          
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)                             
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk           
+#define RCC_APB1ENR1_I2C2EN_Pos              (22U)                             
+#define RCC_APB1ENR1_I2C2EN_Msk              (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk           
+#define RCC_APB1ENR1_I2C3EN_Pos              (23U)                             
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk           
+#define RCC_APB1ENR1_CAN1EN_Pos              (25U)                             
+#define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk           
+#define RCC_APB1ENR1_PWREN_Pos               (28U)                             
+#define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk            
+#define RCC_APB1ENR1_DAC1EN_Pos              (29U)                             
+#define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk           
+#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)                             
+#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk          
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)                             
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk         
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)                              
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk        
+#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)                              
+#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk         
+#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)                              
+#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk         
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)                              
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk          
+#define RCC_APB2ENR_FWEN_Pos                 (7U)                              
+#define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk              
+#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)                             
+#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk          
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            
+#define RCC_APB2ENR_TIM8EN_Pos               (13U)                             
+#define RCC_APB2ENR_TIM8EN_Msk               (0x1U << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk            
+#define RCC_APB2ENR_USART1EN_Pos             (14U)                             
+#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)                             
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk           
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)                             
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk           
+#define RCC_APB2ENR_TIM17EN_Pos              (18U)                             
+#define RCC_APB2ENR_TIM17EN_Msk              (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk           
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)                             
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk            
+#define RCC_APB2ENR_SAI2EN_Pos               (22U)                             
+#define RCC_APB2ENR_SAI2EN_Msk               (0x1U << RCC_APB2ENR_SAI2EN_Pos)  /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk            
+#define RCC_APB2ENR_DFSDM1EN_Pos             (24U)                             
+#define RCC_APB2ENR_DFSDM1EN_Msk             (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk          
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)                              
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk        
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)                              
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk        
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)                              
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk       
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)                              
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk       
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)                             
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk         
+#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)                             
+#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)                              
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk       
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)                              
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)                              
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk       
+#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)                              
+#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)                              
+#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk       
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)                              
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)                              
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)                              
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk       
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)                              
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk       
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)                             
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk       
+#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)                             
+#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk         
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)                             
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+#define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)                              
+#define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk         
+#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)                              
+#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk        
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)                              
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk       
+#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)                              
+#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk       
+#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)                              
+#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk       
+#define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)                              
+#define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk       
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)                              
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk       
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)                              
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk       
+#define RCC_APB1SMENR1_LCDSMEN_Pos           (9U)                              
+#define RCC_APB1SMENR1_LCDSMEN_Msk           (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR1_LCDSMEN               RCC_APB1SMENR1_LCDSMEN_Msk        
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)                             
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk       
+#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)                             
+#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk       
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)                             
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk       
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)                             
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk     
+#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)                             
+#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk     
+#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)                             
+#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk      
+#define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)                             
+#define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk      
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)                             
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk       
+#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)                             
+#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk       
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)                             
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk       
+#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)                             
+#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk       
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)                             
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk        
+#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)                             
+#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk       
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)                             
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk      
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)                             
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk     
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)                              
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk    
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)                              
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk     
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)                              
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk     
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)                              
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk      
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)                             
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk      
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)                             
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk        
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)                             
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk        
+#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)                             
+#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk        
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)                             
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk      
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)                             
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk       
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)                             
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk       
+#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)                             
+#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk       
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)                             
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk        
+#define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)                             
+#define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk        
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)                             
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk      
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos              (0U)                              
+#define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk           
+#define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos              (2U)                              
+#define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk           
+#define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos              (4U)                              
+#define RCC_CCIPR_USART3SEL_Msk              (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk           
+#define RCC_CCIPR_USART3SEL_0                (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1                (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos               (6U)                              
+#define RCC_CCIPR_UART4SEL_Msk               (0x3U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk            
+#define RCC_CCIPR_UART4SEL_0                 (0x1U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1                 (0x2U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000080 */
+
+#define RCC_CCIPR_UART5SEL_Pos               (8U)                              
+#define RCC_CCIPR_UART5SEL_Msk               (0x3U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000300 */
+#define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk            
+#define RCC_CCIPR_UART5SEL_0                 (0x1U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000100 */
+#define RCC_CCIPR_UART5SEL_1                 (0x2U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000200 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)                             
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk          
+#define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)                             
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk             
+#define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos                (14U)                             
+#define RCC_CCIPR_I2C2SEL_Msk                (0x3U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk             
+#define RCC_CCIPR_I2C2SEL_0                  (0x1U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1                  (0x2U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)                             
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk             
+#define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)                             
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk           
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)                             
+#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk           
+#define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos                (22U)                             
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk             
+#define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */
+
+#define RCC_CCIPR_SAI2SEL_Pos                (24U)                             
+#define RCC_CCIPR_SAI2SEL_Msk                (0x3U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x03000000 */
+#define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk             
+#define RCC_CCIPR_SAI2SEL_0                  (0x1U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x01000000 */
+#define RCC_CCIPR_SAI2SEL_1                  (0x2U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x02000000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)                             
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk            
+#define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos                 (28U)                             
+#define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk              
+#define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)                             
+#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk           
+
+#define RCC_CCIPR_DFSDM1SEL_Pos              (31U)                             
+#define RCC_CCIPR_DFSDM1SEL_Msk              (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
+#define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk           
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                   (0U)                              
+#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                
+#define RCC_BDCR_LSERDY_Pos                  (1U)                              
+#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               
+#define RCC_BDCR_LSEBYP_Pos                  (2U)                              
+#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               
+
+#define RCC_BDCR_LSEDRV_Pos                  (3U)                              
+#define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk               
+#define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                (5U)                              
+#define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk             
+#define RCC_BDCR_LSECSSD_Pos                 (6U)                              
+#define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk              
+
+#define RCC_BDCR_RTCSEL_Pos                  (8U)                              
+#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               
+#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                   (15U)                             
+#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                
+#define RCC_BDCR_BDRST_Pos                   (16U)                             
+#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                
+#define RCC_BDCR_LSCOEN_Pos                  (24U)                             
+#define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk               
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)                             
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk              
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                    (0U)                              
+#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 
+#define RCC_CSR_LSIRDY_Pos                   (1U)                              
+#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                
+
+#define RCC_CSR_MSISRANGE_Pos                (8U)                              
+#define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk             
+#define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos                     (23U)                             
+#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  
+#define RCC_CSR_FWRSTF_Pos                   (24U)                             
+#define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk                
+#define RCC_CSR_OBLRSTF_Pos                  (25U)                             
+#define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk               
+#define RCC_CSR_PINRSTF_Pos                  (26U)                             
+#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               
+#define RCC_CSR_BORRSTF_Pos                  (27U)                             
+#define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk               
+#define RCC_CSR_SFTRSTF_Pos                  (28U)                             
+#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)                                   
+#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk                           
+#define RTC_TR_HT_Pos                  (20U)                                   
+#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk                           
+#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)                                   
+#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk                           
+#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)                                   
+#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          
+#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)                                    
+#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          
+#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)                                    
+#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk                           
+#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)                                    
+#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk                           
+#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)                                   
+#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk                           
+#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)                                   
+#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk                           
+#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)                                   
+#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          
+#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)                                   
+#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk                           
+#define RTC_DR_MU_Pos                  (8U)                                    
+#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk                           
+#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)                                    
+#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk                           
+#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)                                    
+#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk                           
+#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)                                   
+#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         
+#define RTC_CR_COE_Pos                 (23U)                                   
+#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk                          
+#define RTC_CR_OSEL_Pos                (21U)                                   
+#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         
+#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)                                   
+#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk                          
+#define RTC_CR_COSEL_Pos               (19U)                                   
+#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos               (17U)                                   
+#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        
+#define RTC_CR_ADD1H_Pos               (16U)                                   
+#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        
+#define RTC_CR_TSIE_Pos                (15U)                                   
+#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         
+#define RTC_CR_WUTIE_Pos               (14U)                                   
+#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        
+#define RTC_CR_ALRBIE_Pos              (13U)                                   
+#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       
+#define RTC_CR_ALRAIE_Pos              (12U)                                   
+#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       
+#define RTC_CR_TSE_Pos                 (11U)                                   
+#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          
+#define RTC_CR_WUTE_Pos                (10U)                                   
+#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         
+#define RTC_CR_ALRBE_Pos               (9U)                                    
+#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        
+#define RTC_CR_ALRAE_Pos               (8U)                                    
+#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        
+#define RTC_CR_FMT_Pos                 (6U)                                    
+#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          
+#define RTC_CR_BYPSHAD_Pos             (5U)                                    
+#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      
+#define RTC_CR_REFCKON_Pos             (4U)                                    
+#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      
+#define RTC_CR_TSEDGE_Pos              (3U)                                    
+#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       
+#define RTC_CR_WUCKSEL_Pos             (0U)                                    
+#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      
+#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)                                   
+#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        
+#define RTC_ISR_RECALPF_Pos            (16U)                                   
+#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     
+#define RTC_ISR_TAMP3F_Pos             (15U)                                   
+#define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      
+#define RTC_ISR_TAMP2F_Pos             (14U)                                   
+#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      
+#define RTC_ISR_TAMP1F_Pos             (13U)                                   
+#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      
+#define RTC_ISR_TSOVF_Pos              (12U)                                   
+#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       
+#define RTC_ISR_TSF_Pos                (11U)                                   
+#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         
+#define RTC_ISR_WUTF_Pos               (10U)                                   
+#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        
+#define RTC_ISR_ALRBF_Pos              (9U)                                    
+#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       
+#define RTC_ISR_ALRAF_Pos              (8U)                                    
+#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       
+#define RTC_ISR_INIT_Pos               (7U)                                    
+#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        
+#define RTC_ISR_INITF_Pos              (6U)                                    
+#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       
+#define RTC_ISR_RSF_Pos                (5U)                                    
+#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         
+#define RTC_ISR_INITS_Pos              (4U)                                    
+#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       
+#define RTC_ISR_SHPF_Pos               (3U)                                    
+#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        
+#define RTC_ISR_WUTWF_Pos              (2U)                                    
+#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       
+#define RTC_ISR_ALRBWF_Pos             (1U)                                    
+#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      
+#define RTC_ISR_ALRAWF_Pos             (0U)                                    
+#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
+#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   
+#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)                                    
+#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     
+#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    
+#define RTC_ALRMAR_DT_Pos              (28U)                                   
+#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       
+#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)                                   
+#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       
+#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     
+#define RTC_ALRMAR_PM_Pos              (22U)                                   
+#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       
+#define RTC_ALRMAR_HT_Pos              (20U)                                   
+#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       
+#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)                                   
+#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       
+#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     
+#define RTC_ALRMAR_MNT_Pos             (12U)                                   
+#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      
+#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)                                    
+#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      
+#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     
+#define RTC_ALRMAR_ST_Pos              (4U)                                    
+#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       
+#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)                                    
+#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       
+#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     
+#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    
+#define RTC_ALRMBR_DT_Pos              (28U)                                   
+#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       
+#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)                                   
+#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       
+#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     
+#define RTC_ALRMBR_PM_Pos              (22U)                                   
+#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       
+#define RTC_ALRMBR_HT_Pos              (20U)                                   
+#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       
+#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)                                   
+#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       
+#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     
+#define RTC_ALRMBR_MNT_Pos             (12U)                                   
+#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      
+#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)                                    
+#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      
+#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     
+#define RTC_ALRMBR_ST_Pos              (4U)                                    
+#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       
+#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)                                    
+#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       
+#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)                                    
+#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)                                    
+#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    
+#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
+#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)                                   
+#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         
+#define RTC_TSTR_HT_Pos                (20U)                                   
+#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         
+#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)                                   
+#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         
+#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)                                   
+#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        
+#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)                                    
+#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        
+#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)                                    
+#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         
+#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)                                    
+#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         
+#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)                                   
+#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        
+#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)                                   
+#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         
+#define RTC_TSDR_MU_Pos                (8U)                                    
+#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         
+#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)                                    
+#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         
+#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)                                    
+#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         
+#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)                                    
+#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)                                   
+#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       
+#define RTC_CALR_CALW8_Pos             (14U)                                   
+#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      
+#define RTC_CALR_CALW16_Pos            (13U)                                   
+#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     
+#define RTC_CALR_CALM_Pos              (0U)                                    
+#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       
+#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)                                   
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)                                   
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)                                   
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  
+#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)                                    
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)                                    
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
+#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)                                    
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
+#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
+
+/********************  Bits definition for RTC_0R register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)                                    
+#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)                                    
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk                           
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)                                    
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk                           
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)                                    
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk                           
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)                                    
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk                           
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)                                    
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk                           
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)                                    
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk                           
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)                                    
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk                           
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)                                    
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk                           
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)                                    
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk                           
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)                                    
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk                           
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)                                    
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk                          
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)                                    
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk                          
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)                                    
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk                          
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)                                    
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk                          
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)                                    
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk                          
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)                                    
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk                          
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)                                    
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk                          
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)                                    
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk                          
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)                                    
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk                          
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)                                    
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk                          
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)                                    
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk                          
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)                                    
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk                          
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)                                    
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk                          
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)                                    
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk                          
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)                                    
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk                          
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)                                    
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk                          
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)                                    
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk                          
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)                                    
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk                          
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)                                    
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk                          
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)                                    
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk                          
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)                                    
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk                          
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)                                    
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk                          
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       32U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN_Pos            (0U)                                       
+#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
+#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos             (1U)                                       
+#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
+#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos             (2U)                                       
+#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
+#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
+#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
+#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos             (5U)                                       
+#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
+#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
+#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos          (7U)                                       
+#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
+#define LCD_CR_BUFEN_Pos            (8U)                                       
+#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
+#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD_Pos              (0U)                                       
+#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
+#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos           (1U)                                       
+#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
+#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos           (3U)                                       
+#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
+#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos             (4U)                                       
+#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
+#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Pulse ON Duration) */
+#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
+#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
+#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos            (7U)                                       
+#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
+#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos              (10U)                                      
+#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
+#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
+#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
+#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos          (13U)                                      
+#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos           (16U)                                      
+#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
+#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos             (18U)                                      
+#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
+#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos              (22U)                                      
+#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
+#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS_Pos              (0U)                                       
+#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
+#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos              (1U)                                       
+#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
+#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos              (2U)                                       
+#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
+#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos              (3U)                                       
+#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
+#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos              (4U)                                       
+#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
+#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos            (5U)                                       
+#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
+#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC_Pos            (1U)                                       
+#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
+#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos            (3U)                                       
+#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
+#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos    (0U)                                       
+#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos         (0U)                                   
+#define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos          (0U)                                   
+#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */
+#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
+#define SDMMC_CLKCR_CLKEN_Pos           (8U)                                   
+#define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */
+#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
+#define SDMMC_CLKCR_PWRSAV_Pos          (9U)                                   
+#define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */
+#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_BYPASS_Pos          (10U)                                  
+#define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */
+#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos          (11U)                                  
+#define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */
+#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)                                  
+#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */
+#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)                                  
+#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos            (0U)                                   
+#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos          (0U)                                   
+#define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
+
+#define SDMMC_CMD_WAITRESP_Pos          (6U)                                   
+#define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */
+#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000080 */
+
+#define SDMMC_CMD_WAITINT_Pos           (8U)                                   
+#define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */
+#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos          (9U)                                   
+#define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos            (10U)                                  
+#define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */
+#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)                                  
+#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */
+#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)                                   
+#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)                                   
+#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)                                   
+#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)                                   
+#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)                                   
+#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos       (0U)                                   
+#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos       (0U)                                   
+#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos            (0U)                                   
+#define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
+#define SDMMC_DCTRL_DTDIR_Pos           (1U)                                   
+#define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos          (2U)                                   
+#define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
+#define SDMMC_DCTRL_DMAEN_Pos           (3U)                                   
+#define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */
+#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)                                   
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos         (8U)                                   
+#define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
+#define SDMMC_DCTRL_RWSTOP_Pos          (9U)                                   
+#define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
+#define SDMMC_DCTRL_RWMOD_Pos           (10U)                                  
+#define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
+#define SDMMC_DCTRL_SDIOEN_Pos          (11U)                                  
+#define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)                                   
+#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos          (0U)                                   
+#define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos          (1U)                                   
+#define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos          (2U)                                   
+#define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos          (3U)                                   
+#define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos          (4U)                                   
+#define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos           (5U)                                   
+#define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos           (6U)                                   
+#define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos           (7U)                                   
+#define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos           (8U)                                   
+#define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_STBITERR_Pos          (9U)                                   
+#define SDMMC_STA_STBITERR_Msk          (0x1U << SDMMC_STA_STBITERR_Pos)       /*!< 0x00000200 */
+#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDMMC_STA_DBCKEND_Pos           (10U)                                  
+#define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_CMDACT_Pos            (11U)                                  
+#define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
+#define SDMMC_STA_TXACT_Pos             (12U)                                  
+#define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */
+#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
+#define SDMMC_STA_RXACT_Pos             (13U)                                  
+#define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */
+#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
+#define SDMMC_STA_TXFIFOHE_Pos          (14U)                                  
+#define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos          (15U)                                  
+#define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos           (16U)                                  
+#define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos           (17U)                                  
+#define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos           (18U)                                  
+#define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos           (19U)                                  
+#define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
+#define SDMMC_STA_TXDAVL_Pos            (20U)                                  
+#define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
+#define SDMMC_STA_RXDAVL_Pos            (21U)                                  
+#define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */
+#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
+#define SDMMC_STA_SDIOIT_Pos            (22U)                                  
+#define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos         (0U)                                   
+#define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos         (1U)                                   
+#define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)                                   
+#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)                                   
+#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos         (4U)                                   
+#define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos          (5U)                                   
+#define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos          (6U)                                   
+#define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos          (7U)                                   
+#define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos          (8U)                                   
+#define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_STBITERRC_Pos         (9U)                                   
+#define SDMMC_ICR_STBITERRC_Msk         (0x1U << SDMMC_ICR_STBITERRC_Pos)      /*!< 0x00000200 */
+#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos          (10U)                                  
+#define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos           (22U)                                  
+#define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)                                   
+#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)                                   
+#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)                                   
+#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)                                   
+#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)                                   
+#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos        (5U)                                   
+#define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos        (6U)                                   
+#define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos        (7U)                                   
+#define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos        (8U)                                   
+#define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DBCKENDIE_Pos        (10U)                                  
+#define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_CMDACTIE_Pos         (11U)                                  
+#define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
+#define SDMMC_MASK_TXACTIE_Pos          (12U)                                  
+#define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */
+#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
+#define SDMMC_MASK_RXACTIE_Pos          (13U)                                  
+#define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */
+#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
+#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)                                  
+#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)                                  
+#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)                                  
+#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */
+#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)                                  
+#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)                                  
+#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)                                  
+#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */
+#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_TXDAVLIE_Pos         (20U)                                  
+#define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */
+#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
+#define SDMMC_MASK_RXDAVLIE_Pos         (21U)                                  
+#define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */
+#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos         (22U)                                  
+#define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)                                   
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos         (0U)                                   
+#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos         (0U)                                          
+#define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */
+#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos         (1U)                                          
+#define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */
+#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos         (2U)                                          
+#define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */
+#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos           (3U)                                          
+#define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */
+#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */
+#define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */
+#define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos          (6U)                                          
+#define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */
+#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos     (7U)                                          
+#define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos          (8U)                                          
+#define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */
+#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos          (9U)                                          
+#define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */
+#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos       (10U)                                         
+#define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */
+#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos         (11U)                                         
+#define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */
+#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos      (12U)                                         
+#define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos        (13U)                                         
+#define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */
+#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos       (14U)                                         
+#define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos     (15U)                                         
+#define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos      (0U)                                          
+#define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos      (1U)                                          
+#define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos         (2U)                                          
+#define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */
+#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos         (3U)                                          
+#define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */
+#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos          (4U)                                          
+#define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */
+#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos        (5U)                                          
+#define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */
+#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos       (6U)                                          
+#define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos        (7U)                                          
+#define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */
+#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos           (8U)                                          
+#define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */
+#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */
+#define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */
+#define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */
+#define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos        (12U)                                         
+#define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */
+#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos       (13U)                                         
+#define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */
+#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos       (14U)                                         
+#define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */
+#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos          (0U)                                          
+#define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */
+#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos           (1U)                                          
+#define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */
+#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos        (2U)                                          
+#define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */
+#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
+#define SPI_SR_UDR_Pos           (3U)                                          
+#define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */
+#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos        (4U)                                          
+#define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */
+#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos          (5U)                                          
+#define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */
+#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
+#define SPI_SR_OVR_Pos           (6U)                                          
+#define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */
+#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
+#define SPI_SR_BSY_Pos           (7U)                                          
+#define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */
+#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
+#define SPI_SR_FRE_Pos           (8U)                                          
+#define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */
+#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos         (9U)                                          
+#define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */
+#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos         (11U)                                         
+#define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */
+#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos            (0U)                                          
+#define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */
+#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos    (0U)                                          
+#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos     (0U)                                          
+#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos     (0U)                                          
+#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos              (0U)                                    
+#define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */
+#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos           (1U)                                    
+#define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos           (2U)                                    
+#define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos            (3U)                                    
+#define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos          (4U)                                    
+#define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
+#define QUADSPI_CR_FTHRES_Pos          (8U)                                    
+#define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos            (16U)                                   
+#define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos            (17U)                                   
+#define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos            (18U)                                   
+#define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos            (19U)                                   
+#define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos            (20U)                                   
+#define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos            (22U)                                   
+#define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos             (23U)                                   
+#define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos       (24U)                                   
+#define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos         (0U)                                    
+#define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos           (8U)                                    
+#define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos          (16U)                                   
+#define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos             (0U)                                    
+#define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos             (1U)                                    
+#define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos             (2U)                                    
+#define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos             (3U)                                    
+#define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos             (4U)                                    
+#define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos            (5U)                                    
+#define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos          (8U)                                    
+#define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos           (0U)                                    
+#define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos           (1U)                                    
+#define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos           (3U)                                    
+#define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos           (4U)                                    
+#define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos             (0U)                                    
+#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)                                    
+#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos          (8U)                                    
+#define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos         (10U)                                   
+#define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos         (12U)                                   
+#define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos         (14U)                                   
+#define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos         (16U)                                   
+#define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos           (18U)                                   
+#define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos          (24U)                                   
+#define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos          (26U)                                   
+#define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos           (28U)                                   
+#define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DDRM_Pos           (31U)                                   
+#define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos         (0U)                                    
+#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos      (0U)                                    
+#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos            (0U)                                    
+#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos         (0U)                                    
+#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos        (0U)                                    
+#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos       (0U)                                    
+#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)                                    
+#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)                                   
+#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos)    /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */
+
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos          (0U)                                   
+#define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)                                   
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)                                  
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)                                  
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)                                  
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)                                  
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)                                  
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)                                  
+#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos)    /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)                                  
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7U << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7U << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7U << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7U << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7U << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7U << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7U << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7U << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7U << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7U << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7U << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7U << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600U)                      /*!<PG[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000U)                      /*!<PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006U)                      /*!<PG[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060U)                      /*!<PG[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600U)                      /*!<PG[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000U)                      /*!<PG[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)                                   
+#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)                                   
+#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos            (0U)                                   
+#define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos            (1U)                                   
+#define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)                                   
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)                                   
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos            (8U)                                   
+#define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos           (0U)                                   
+#define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos           (1U)                                   
+#define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos           (2U)                                   
+#define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos           (3U)                                   
+#define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos           (4U)                                   
+#define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos           (5U)                                   
+#define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos           (6U)                                   
+#define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos           (7U)                                   
+#define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos           (8U)                                   
+#define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos           (9U)                                   
+#define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos          (10U)                                  
+#define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos          (11U)                                  
+#define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos          (12U)                                  
+#define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos          (13U)                                  
+#define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos          (14U)                                  
+#define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos          (15U)                                  
+#define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
+#define SYSCFG_SWPR_PAGE16_Pos          (16U)                                  
+#define SYSCFG_SWPR_PAGE16_Msk          (0x1U << SYSCFG_SWPR_PAGE16_Pos)       /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/
+#define SYSCFG_SWPR_PAGE17_Pos          (17U)                                  
+#define SYSCFG_SWPR_PAGE17_Msk          (0x1U << SYSCFG_SWPR_PAGE17_Pos)       /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/
+#define SYSCFG_SWPR_PAGE18_Pos          (18U)                                  
+#define SYSCFG_SWPR_PAGE18_Msk          (0x1U << SYSCFG_SWPR_PAGE18_Pos)       /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/
+#define SYSCFG_SWPR_PAGE19_Pos          (19U)                                  
+#define SYSCFG_SWPR_PAGE19_Msk          (0x1U << SYSCFG_SWPR_PAGE19_Pos)       /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/
+#define SYSCFG_SWPR_PAGE20_Pos          (20U)                                  
+#define SYSCFG_SWPR_PAGE20_Msk          (0x1U << SYSCFG_SWPR_PAGE20_Pos)       /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/
+#define SYSCFG_SWPR_PAGE21_Pos          (21U)                                  
+#define SYSCFG_SWPR_PAGE21_Msk          (0x1U << SYSCFG_SWPR_PAGE21_Pos)       /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/
+#define SYSCFG_SWPR_PAGE22_Pos          (22U)                                  
+#define SYSCFG_SWPR_PAGE22_Msk          (0x1U << SYSCFG_SWPR_PAGE22_Pos)       /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/
+#define SYSCFG_SWPR_PAGE23_Pos          (23U)                                  
+#define SYSCFG_SWPR_PAGE23_Msk          (0x1U << SYSCFG_SWPR_PAGE23_Pos)       /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/
+#define SYSCFG_SWPR_PAGE24_Pos          (24U)                                  
+#define SYSCFG_SWPR_PAGE24_Msk          (0x1U << SYSCFG_SWPR_PAGE24_Pos)       /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/
+#define SYSCFG_SWPR_PAGE25_Pos          (25U)                                  
+#define SYSCFG_SWPR_PAGE25_Msk          (0x1U << SYSCFG_SWPR_PAGE25_Pos)       /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/
+#define SYSCFG_SWPR_PAGE26_Pos          (26U)                                  
+#define SYSCFG_SWPR_PAGE26_Msk          (0x1U << SYSCFG_SWPR_PAGE26_Pos)       /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/
+#define SYSCFG_SWPR_PAGE27_Pos          (27U)                                  
+#define SYSCFG_SWPR_PAGE27_Msk          (0x1U << SYSCFG_SWPR_PAGE27_Pos)       /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/
+#define SYSCFG_SWPR_PAGE28_Pos          (28U)                                  
+#define SYSCFG_SWPR_PAGE28_Msk          (0x1U << SYSCFG_SWPR_PAGE28_Pos)       /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/
+#define SYSCFG_SWPR_PAGE29_Pos          (29U)                                  
+#define SYSCFG_SWPR_PAGE29_Msk          (0x1U << SYSCFG_SWPR_PAGE29_Pos)       /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/
+#define SYSCFG_SWPR_PAGE30_Pos          (30U)                                  
+#define SYSCFG_SWPR_PAGE30_Msk          (0x1U << SYSCFG_SWPR_PAGE30_Pos)       /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/
+#define SYSCFG_SWPR_PAGE31_Pos          (31U)                                  
+#define SYSCFG_SWPR_PAGE31_Msk          (0x1U << SYSCFG_SWPR_PAGE31_Pos)       /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos              (0U)                                   
+#define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)                                        
+#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM1_OR1 register  *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)                                    
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
+#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM1_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM1_OR2 register  *******************/
+#define TIM1_OR2_BKINE_Pos             (0U)                                    
+#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKDF1BK0E_Pos         (8U)                                    
+#define TIM1_OR2_BKDF1BK0E_Msk         (0x1U << TIM1_OR2_BKDF1BK0E_Pos)        /*!< 0x00000100 */
+#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM1_OR2_BKINP_Pos             (9U)                                    
+#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM1_OR3 register  *******************/
+#define TIM1_OR3_BK2INE_Pos            (0U)                                    
+#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)                                    
+#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1U << TIM1_OR3_BK2DF1BK1E_Pos)       /*!< 0x00000100 */
+#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */
+#define TIM1_OR3_BK2INP_Pos            (9U)                                    
+#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM8_OR1 register  *******************/
+#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)                                    
+#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000003 */
+#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
+#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000001 */
+#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
+#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM8_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM8_OR1_TI1_RMP_Msk           (0x1U << TIM8_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM8_OR2 register  *******************/
+#define TIM8_OR2_BKINE_Pos             (0U)                                    
+#define TIM8_OR2_BKINE_Msk             (0x1U << TIM8_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM8_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM8_OR2_BKCMP1E_Msk           (0x1U << TIM8_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM8_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM8_OR2_BKCMP2E_Msk           (0x1U << TIM8_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM8_OR2_BKDF1BK2E_Pos         (8U)                                    
+#define TIM8_OR2_BKDF1BK2E_Msk         (0x1U << TIM8_OR2_BKDF1BK2E_Pos)        /*!< 0x00000100 */
+#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM8_OR2_BKINP_Pos             (9U)                                    
+#define TIM8_OR2_BKINP_Msk             (0x1U << TIM8_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM8_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM8_OR2_BKCMP1P_Msk           (0x1U << TIM8_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM8_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM8_OR2_BKCMP2P_Msk           (0x1U << TIM8_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM8_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM8_OR2_ETRSEL_Msk            (0x7U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
+#define TIM8_OR2_ETRSEL_0              (0x1U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM8_OR2_ETRSEL_1              (0x2U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM8_OR2_ETRSEL_2              (0x4U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM8_OR3 register  *******************/
+#define TIM8_OR3_BK2INE_Pos            (0U)                                    
+#define TIM8_OR3_BK2INE_Msk            (0x1U << TIM8_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM8_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM8_OR3_BK2CMP1E_Msk          (0x1U << TIM8_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM8_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM8_OR3_BK2CMP2E_Msk          (0x1U << TIM8_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)                                    
+#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1U << TIM8_OR3_BK2DF1BK3E_Pos)       /*!< 0x00000100 */
+#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */
+#define TIM8_OR3_BK2INP_Pos            (9U)                                    
+#define TIM8_OR3_BK2INP_Msk            (0x1U << TIM8_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM8_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM8_OR3_BK2CMP1P_Msk          (0x1U << TIM8_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM8_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM8_OR3_BK2CMP2P_Msk          (0x1U << TIM8_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_OR1 register  *******************/
+#define TIM2_OR1_ITR1_RMP_Pos     (0U)                                         
+#define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos     (1U)                                         
+#define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos      (2U)                                         
+#define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM2_OR2 register  *******************/
+#define TIM2_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM3_OR1 register  *******************/
+#define TIM3_OR1_TI1_RMP_Pos      (0U)                                         
+#define TIM3_OR1_TI1_RMP_Msk      (0x3U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000003 */
+#define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
+#define TIM3_OR1_TI1_RMP_0        (0x1U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000001 */
+#define TIM3_OR1_TI1_RMP_1        (0x2U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM3_OR2 register  *******************/
+#define TIM3_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM3_OR2_ETRSEL_Msk       (0x7U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
+#define TIM3_OR2_ETRSEL_0         (0x1U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM3_OR2_ETRSEL_1         (0x2U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM3_OR2_ETRSEL_2         (0x4U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM15_OR1 register  ******************/
+#define TIM15_OR1_TI1_RMP_Pos           (0U)                                   
+#define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos      (1U)                                   
+#define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM15_OR2 register  ******************/
+#define TIM15_OR2_BKINE_Pos             (0U)                                   
+#define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */
+#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos           (1U)                                   
+#define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos           (2U)                                   
+#define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKDF1BK0E_Pos         (8U)                                   
+#define TIM15_OR2_BKDF1BK0E_Msk         (0x1U << TIM15_OR2_BKDF1BK0E_Pos)      /*!< 0x00000100 */
+#define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM15_OR2_BKINP_Pos             (9U)                                   
+#define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */
+#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos           (10U)                                  
+#define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos           (11U)                                  
+#define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_OR1 register  ******************/
+#define TIM16_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM16_OR1_TI1_RMP_Msk      (0x3U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM16_OR2 register  ******************/
+#define TIM16_OR2_BKINE_Pos        (0U)                                        
+#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKDF1BK1E_Pos    (8U)                                        
+#define TIM16_OR2_BKDF1BK1E_Msk    (0x1U << TIM16_OR2_BKDF1BK1E_Pos)           /*!< 0x00000100 */
+#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */
+#define TIM16_OR2_BKINP_Pos        (9U)                                        
+#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_OR1 register  ******************/
+#define TIM17_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM17_OR1_TI1_RMP_Msk      (0x3U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
+#define TIM17_OR1_TI1_RMP_0        (0x1U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM17_OR1_TI1_RMP_1        (0x2U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM17_OR2 register  ******************/
+#define TIM17_OR2_BKINE_Pos        (0U)                                        
+#define TIM17_OR2_BKINE_Msk        (0x1U << TIM17_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM17_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM17_OR2_BKCMP1E_Msk      (0x1U << TIM17_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM17_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM17_OR2_BKCMP2E_Msk      (0x1U << TIM17_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM17_OR2_BKDF1BK2E_Pos    (8U)                                        
+#define TIM17_OR2_BKDF1BK2E_Msk    (0x1U << TIM17_OR2_BKDF1BK2E_Pos)           /*!< 0x00000100 */
+#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM17_OR2_BKINP_Pos        (9U)                                        
+#define TIM17_OR2_BKINP_Msk        (0x1U << TIM17_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM17_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM17_OR2_BKCMP1P_Msk      (0x1U << TIM17_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM17_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM17_OR2_BKCMP2P_Msk      (0x1U << TIM17_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)                                       
+#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)                                       
+#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
+#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)                                       
+#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)                                       
+#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)                                       
+#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
+#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
+#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
+#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)                                       
+#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
+#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
+#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
+#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
+#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
+#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)                                       
+#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
+#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
+#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
+#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
+#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
+#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
+#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)                                      
+#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)                                       
+#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
+#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
+#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)                                       
+#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)                                       
+#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)                                       
+#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  ********************/
+#define LPTIM_OR_OR_Pos             (0U)                                       
+#define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */
+#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
+#define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos            (0U)                                        
+#define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos       (2U)                                        
+#define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos        (4U)                                        
+#define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos        (7U)                                        
+#define COMP_CSR_INPSEL_Msk        (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+
+#define COMP_CSR_WINMODE_Pos       (9U)                                        
+#define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */
+#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_POLARITY_Pos      (15U)                                       
+#define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos          (16U)                                       
+#define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */
+#define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos      (18U)                                       
+#define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos         (22U)                                       
+#define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos        (23U)                                       
+#define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_VALUE_Pos         (30U)                                       
+#define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos          (31U)                                       
+#define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)                                  
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos             (1U)                                  
+#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos            (2U)                                  
+#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (4U)                                  
+#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos              (8U)                                  
+#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos              (10U)                                 
+#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos              (12U)                                 
+#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos             (13U)                                 
+#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos           (14U)                                 
+#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos             (15U)                                 
+#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos              (12U)                                
+#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)                                
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP2_CSR_OPALPM_Msk             (0x1U << OPAMP2_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */
+
+#define OPAMP2_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP2_CSR_OPAMODE_Msk            (0x3U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */
+#define OPAMP2_CSR_OPAMODE_0              (0x1U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP2_CSR_OPAMODE_1              (0x2U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP2_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP2_CSR_PGAGAIN_Msk            (0x3U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGAGAIN_0              (0x1U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP2_CSR_PGAGAIN_1              (0x2U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP2_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP2_CSR_VPSEL_Msk              (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_CALON_Pos              (12U)                                
+#define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP2_CSR_CALSEL_Msk             (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)                                  
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)                                  
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_LPOTR register  ****************/
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
+#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
+#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
+#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
+#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos       (7U)                                          
+#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos       (23U)                                         
+#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)                                          
+#define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)                                          
+#define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)                                          
+#define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)                                          
+#define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)                                          
+#define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)                                          
+#define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)                                         
+#define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)                                          
+#define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)                                          
+#define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)                                          
+#define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)                                          
+#define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)                                          
+#define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)                                          
+#define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)                                          
+#define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)                                          
+#define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)                                          
+#define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)                                          
+#define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)                                          
+#define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)                                         
+#define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)                                          
+#define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)                                          
+#define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)                                          
+#define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)                                          
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)                                          
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)                                          
+#define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)                                          
+#define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_SRIE_Pos       (8U)                                          
+#define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_TCIE_Pos       (7U)                                          
+#define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_TIE_Pos        (6U)                                          
+#define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_RIE_Pos        (5U)                                          
+#define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)                                          
+#define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)                                          
+#define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)                                          
+#define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_TXBEIE_Pos     (1U)                                          
+#define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBFIE_Pos     (0U)                                          
+#define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)                                          
+#define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1_Pos    (0U)                                          
+#define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */
+#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)                                          
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)                                          
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)                                          
+#define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)                                          
+#define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)                                           
+#define VREFBUF_CSR_ENVR_Msk    (0x1U << VREFBUF_CSR_ENVR_Pos)                 /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)                                           
+#define VREFBUF_CSR_HIZ_Msk     (0x1U << VREFBUF_CSR_HIZ_Pos)                  /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
+#define VREFBUF_CSR_VRS_Pos     (2U)                                           
+#define VREFBUF_CSR_VRS_Msk     (0x1U << VREFBUF_CSR_VRS_Pos)                  /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRR_Pos     (3U)                                           
+#define VREFBUF_CSR_VRR_Msk     (0x1U << VREFBUF_CSR_VRR_Pos)                  /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos    (0U)                                           
+#define VREFBUF_CCR_TRIM_Msk    (0x3FU << VREFBUF_CCR_TRIM_Pos)                /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)                            
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk        
+
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)                            
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk        
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)                           
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)                           
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)                           
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)                           
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)                           
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)                            
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)                           
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)                           
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)                           
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)                           
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)                           
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)                          
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)                          
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)                          
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)                          
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)                          
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)                          
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)                         
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
+#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)                         
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)                         
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                             
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                         
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)                          
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)                         
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                       (0U)                          
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                        (16U)                         
+#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)                          
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)                          
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)                          
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)                          
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)                         
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)                         
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)                         
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)                         
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)                         
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)                          
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
+#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+
+/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
+#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)                         
+#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
+#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */ 
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)                         
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */ 
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)                         
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ 
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)                         
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */ 
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)                         
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */ 
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)                         
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */ 
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           (16U)                         
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ 
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)                         
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */ 
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)                         
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */ 
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)                         
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */ 
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)                          
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */ 
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)                          
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */ 
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)                          
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)                          
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)                          
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)                          
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */
+
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
+#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
+#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
+#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
+#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+                                                                             
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+                                                                             
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+                                                                              
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+                                                                              
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                                                              
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+                                                                              
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+                                                                               
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+                                                                               
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
+#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
+#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
+#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
+#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
+#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                                ((INSTANCE) == DFSDM1_Filter1) || \
+                                                ((INSTANCE) == DFSDM1_Filter2) || \
+                                                ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/******************************* HCD Instances *******************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/******************************* PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                                       ((INSTANCE) == SAI1_Block_B) || \
+                                       ((INSTANCE) == SAI2_Block_A) || \
+                                       ((INSTANCE) == SAI2_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
+                                               ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16)   || \
+                                            ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16)  || \
+                                               ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM3)    || \
+                                                    ((INSTANCE) == TIM4)    || \
+                                                    ((INSTANCE) == TIM5)    || \
+                                                    ((INSTANCE) == TIM8)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16)   || \
+                                                    ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16)  || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2)  || \
+                                                      ((INSTANCE) == TIM3)  || \
+                                                      ((INSTANCE) == TIM4)  || \
+                                                      ((INSTANCE) == TIM5)  || \
+                                                      ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                         ((INSTANCE) == TIM2)   || \
+                                                         ((INSTANCE) == TIM3)   || \
+                                                         ((INSTANCE) == TIM4)   || \
+                                                         ((INSTANCE) == TIM5))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2)  || \
+                                             ((INSTANCE) == TIM3)  || \
+                                             ((INSTANCE) == TIM8))
+      
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4) || \
+                                                       ((INSTANCE) == TIM5) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15) || \
+                                            ((INSTANCE) == TIM16) || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                                  ((INSTANCE) == TIM8))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == UART4)  || \
+                                                 ((INSTANCE) == UART5)  || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3) || \
+                                          ((INSTANCE) == UART4)  || \
+                                          ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn                      ADC1_2_IRQn
+#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn
+#define TIM8_IRQn                      TIM8_UP_IRQn
+#define HASH_RNG_IRQn                  RNG_IRQn
+#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn
+#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn
+#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn
+#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler                ADC1_2_IRQHandler
+#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM8_IRQHandler                TIM8_UP_IRQHandler
+#define HASH_RNG_IRQHandler            RNG_IRQHandler
+#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler
+#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler
+#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler
+#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L476xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h
new file mode 100755
index 0000000..d77dda0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h
@@ -0,0 +1,240 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
+#define STM32L476xx           /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  /* #define STM32L486xx */   /*!< STM32L486xx Devices */
+  /* #define STM32L496xx */   /*!< STM32L496xx Devices */
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.3.1
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/system_stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/system_stm32l4xx.h
new file mode 100755
index 0000000..b2b7736
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/system_stm32l4xx.h
@@ -0,0 +1,127 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h
new file mode 100755
index 0000000..ece5f16
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h
new file mode 100755
index 0000000..e89a97b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_2
+#define STDIO_UART_RX  PA_3
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c
new file mode 100755
index 0000000..6431764
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c
@@ -0,0 +1,265 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  5, 0)}, // IN5 - ARDUINO A0
+    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  6, 0)}, // IN6 - ARDUINO A1
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7 // PA_2 is used as SERIAL_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8 // PA_3 is used as SERIAL_RX
+    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  9, 0)}, // IN9 - ARDUINO A2
+    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
+    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
+    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12
+    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3
+    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16
+    {PC_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  1, 0)}, // IN1 - ARDUINO A5
+    {PC_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  2, 0)}, // IN2 - ARDUINO A4
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  3, 0)}, // IN3
+    {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
+    {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
+    {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin)
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// Warning: TIM5 cannot be used because already used by the us_ticker.
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},  // TIM5_CH1 (used by us_ticker)
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2 (used by us_ticker)
+//  {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 // PA_2 is used as SERIAL_TX
+//  {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3 (used by us_ticker)
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4 // PA_3 is used as SERIAL_RX
+//  {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4 (used by us_ticker)
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+//  {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2 - ARDUINO D11
+//  {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+//  {PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+//  {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+//  {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - ARDUINO D3
+    {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1 - ARDUINO D5
+    {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PB_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1 - ARDUINO D10
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N
+    {PB_7,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+//  {PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N
+    {PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+//  {PB_9,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 - ARDUINO D6
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PB_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+    {PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PB_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+//  {PB_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)},  // TIM8_CH1
+//  {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)},  // TIM8_CH2 - ARDUINO D9
+//  {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)},  // TIM8_CH3
+//  {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PC_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)},  // TIM8_CH4
+//  {PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_4,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs
+//  {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+//  {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+ 
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PB_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, 
+//  {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PB_9 ,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_12,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h
new file mode 100755
index 0000000..c78b39c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_2  = 0x32,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Arduino connector namings
+    A0          = PA_0,
+    A1          = PA_1,
+    A2          = PA_4,
+    A3          = PB_0,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_3,
+    D1          = PA_2,
+    D2          = PA_10,
+    D3          = PB_3,
+    D4          = PB_5,
+    D5          = PB_4,
+    D6          = PB_10,
+    D7          = PA_8,
+    D8          = PA_9,
+    D9          = PC_7,
+    D10         = PB_6,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PA_5,
+    LED2        = PA_5,
+    LED3        = PA_5,
+    LED4        = PA_5,
+    USER_BUTTON = PC_13,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PA_2,
+    SERIAL_RX   = PA_3,
+    USBTX       = PA_2,
+    USBRX       = PA_3,
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_9,
+    SPI_MOSI    = PA_7,
+    SPI_MISO    = PA_6,
+    SPI_SCK     = PA_5,
+    SPI_CS      = PB_6,
+    PWM_OUT     = PB_3,
+
+    //USB pins
+    USB_OTG_FS_SOF = PA_8,
+    USB_OTG_FS_VBUS = PA_9,
+    USB_OTG_FS_ID = PA_10,
+    USB_OTG_FS_DM = PA_11,
+    USB_OTG_FS_DP = PA_12,
+    USB_OTG_FS_NOE_ALT = PA_13,
+    USB_OTG_FS_NOE = PC_9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c
new file mode 100755
index 0000000..6bdfc86
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l486xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l486xx.S
new file mode 100755
index 0000000..fd09220
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l486xx.S
@@ -0,0 +1,410 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l486xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.2
+;* Date               : 12-September-2016
+;* Description        : STM32L486xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+__initial_sp    EQU     0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler)
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     AES_IRQHandler                    ; AES global interrupt
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     AES_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/stm32l486xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/stm32l486xx.sct
new file mode 100755
index 0000000..39fbb38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/stm32l486xx.sct
@@ -0,0 +1,48 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1 0x20000000 0x00018000  { ; RW data 96k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM2 (0x10000000+0x188) (0x08000-0x188)  {  ; RW data 32k L4-ECC-SRAM2 retained in standby
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/startup_stm32l486xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/startup_stm32l486xx.S
new file mode 100755
index 0000000..525d328
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/startup_stm32l486xx.S
@@ -0,0 +1,392 @@
+;********************** COPYRIGHT(c) 2016  STMicroelectronics ******************
+;* File Name          : startup_stm32l486xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.2
+;* Date               : 12-September-2016
+;* Description        : STM32L486xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+__initial_sp    EQU     0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     AES_IRQHandler                    ; AES global interrupt
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     AES_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct
new file mode 100755
index 0000000..39fbb38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct
@@ -0,0 +1,48 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1 0x20000000 0x00018000  { ; RW data 96k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM2 (0x10000000+0x188) (0x08000-0x188)  {  ; RW data 32k L4-ECC-SRAM2 retained in standby
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld
new file mode 100755
index 0000000..d4f7965
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld
@@ -0,0 +1,154 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
+  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > SRAM1
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > SRAM1
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > SRAM1
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM1
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l486xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l486xx.S
new file mode 100755
index 0000000..7cb9d3a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l486xx.S
@@ -0,0 +1,516 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l486xx.s
+  * @author    MCD Application Team
+  * @version   V1.1.2
+  * @date      12-September-2016
+  * @brief     STM32L486xx devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before 
+  // starting main(). software_init_hook() is available and has to be called due 
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	TAMP_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	CAN1_TX_IRQHandler
+	.word	CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	DFSDM1_FLT3_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC3_IRQHandler
+	.word	FMC_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	DFSDM1_FLT0_IRQHandler
+	.word	DFSDM1_FLT1_IRQHandler
+	.word	DFSDM1_FLT2_IRQHandler
+	.word	COMP_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	OTG_FS_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	QUADSPI_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	SWPMI1_IRQHandler
+	.word	TSC_IRQHandler
+	.word	LCD_IRQHandler
+	.word	AES_IRQHandler
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_IRQHandler
+	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT3_IRQHandler
+	.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC3_IRQHandler
+	.thumb_set ADC3_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT0_IRQHandler
+	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT1_IRQHandler
+	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT2_IRQHandler
+	.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler	
+	
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+	
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+	
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler	
+	
+	.weak	OTG_FS_IRQHandler
+	.thumb_set OTG_FS_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler	
+	
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler	
+	
+	.weak	QUADSPI_IRQHandler
+	.thumb_set QUADSPI_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler	
+	
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+	
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+	
+	.weak	SWPMI1_IRQHandler
+	.thumb_set SWPMI1_IRQHandler,Default_Handler
+	
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+	
+	.weak	LCD_IRQHandler
+	.thumb_set LCD_IRQHandler,Default_Handler
+	
+	.weak	AES_IRQHandler
+	.thumb_set AES_IRQHandler,Default_Handler
+	
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/startup_stm32l486xx.S b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/startup_stm32l486xx.S
new file mode 100755
index 0000000..e6a79a8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/startup_stm32l486xx.S
@@ -0,0 +1,642 @@
+;/********************* COPYRIGHT(c) 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l486xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.2
+;* Date               : 12-September-2016
+;* Description        : STM32L486xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     LCD_IRQHandler                    ; LCD global interrupt
+        DCD     AES_IRQHandler                    ; AES global interrupt
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+        B ADC3_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+       PUBWEAK LCD_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+LCD_IRQHandler
+       B LCD_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf
new file mode 100755
index 0000000..8762dac
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf
@@ -0,0 +1,35 @@
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x080FFFFF;
+
+/* [RAM = 96kb + 32kb = 0x20000] */
+/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x10000000;
+define symbol __NVIC_end__            = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM2_start__  = 0x10000188;
+define symbol __region_SRAM2_end__    = 0x10007FFF;
+define symbol __region_SRAM1_start__  = 0x20000000;
+define symbol __region_SRAM1_end__    = 0x20017FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+/* Stack 1/8 and Heap 1/4 of RAM */
+define symbol __size_cstack__ = 0x8000;
+define symbol __size_heap__   = 0xa000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in SRAM1_region   { readwrite, block STACKHEAP };
+place in SRAM2_region { };
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/cmsis.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/cmsis.h
new file mode 100755
index 0000000..41a1233
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l4xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/cmsis_nvic.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/cmsis_nvic.h
new file mode 100755
index 0000000..abb7956
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/cmsis_nvic.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
+// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+#define NVIC_NUM_VECTORS        98
+#define NVIC_RAM_VECTOR_ADDRESS 0x10000000    // Vectors positioned at start of SRAM2
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h
new file mode 100755
index 0000000..6c533d1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h
new file mode 100755
index 0000000..b983061
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h
@@ -0,0 +1,18755 @@
+/**
+  ******************************************************************************
+  * @file    stm32l486xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L486xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32l486xx
+  * @{
+  */
+
+#ifndef __STM32L486xx_H
+#define __STM32L486xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
+  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
+  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
+  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
+  LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */
+  AES_IRQn                    = 79,     /*!< AES global interrupt                                              */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
+  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
+  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
+                                  short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef  DMA_Request_TypeDef
+
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+  * @brief Firewall
+  */
+
+typedef struct
+{
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+       uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
+  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
+  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
+  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
+  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+  __IO uint32_t ASCR;        /*!< GPIO analog switch control register,   Address offset: 0x2C     */
+
+} GPIO_TypeDef;
+
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LCD
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */
+  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
+  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */
+  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
+  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;    /*!< Reserved  */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
+  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
+} SYSCFG_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief AES hardware accelerator
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
+  __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
+  __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
+  __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
+  __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
+  __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
+  __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
+  __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
+  __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
+  __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
+  __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
+  __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
+  __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
+  __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
+  __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
+  __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
+  __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
+  __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
+  __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
+  __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
+  __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
+  __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
+  __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
+  __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
+} AES_TypeDef;
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/
+  uint32_t Reserved30[2];             /* Reserved                                        030h*/
+  __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/
+  __IO uint32_t CID;                  /* User ID Register                                03Ch*/
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                 040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                 044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                 048h*/
+  __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/
+  uint32_t  Reserved6;                /* Reserved                                        050h*/ 
+  __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/
+  __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/
+  __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/
+   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/
+    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/
+  __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/
+  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/
+  __IO uint32_t DCTL;        /* dev Control Register         804h*/
+  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/
+  uint32_t Reserved0C;       /* Reserved                     80Ch*/
+  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/
+  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/
+  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/
+  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/
+  uint32_t  Reserved20;      /* Reserved                     820h*/
+  uint32_t Reserved9;        /* Reserved                     824h*/
+  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
+  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
+  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
+  __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/
+  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
+  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
+  uint32_t Reserved40;       /* dedicated EP mask           840h*/
+  __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/
+  uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/   
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
+  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;      /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
+#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */
+#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
+
+#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */
+#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE         ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
+#define SRAM2_SIZE            ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+
+#define FMC_BANK1             FMC_BASE
+#define FMC_BANK1_1           FMC_BANK1
+#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)
+#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)
+#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)
+#define FMC_BANK3             (FMC_BASE  + 0x20000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
+
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
+
+#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)
+#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)
+#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)
+
+
+#define AES_BASE              (AHB2PERIPH_BASE + 0x08060000U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
+
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)
+
+#define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)
+#define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)
+#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)
+#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)
+#define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)
+#define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)
+#define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)
+#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)
+#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)
+#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)
+#define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)
+#define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)
+
+
+#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
+#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+//#define CAN                 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+/* Aliases to keep compatibility after DFSDM renaming */
+#define DFSDM_Channel0      DFSDM1_Channel0
+#define DFSDM_Channel1      DFSDM1_Channel1
+#define DFSDM_Channel2      DFSDM1_Channel2
+#define DFSDM_Channel3      DFSDM1_Channel3
+#define DFSDM_Channel4      DFSDM1_Channel4
+#define DFSDM_Channel5      DFSDM1_Channel5
+#define DFSDM_Channel6      DFSDM1_Channel6
+#define DFSDM_Channel7      DFSDM1_Channel7
+#define DFSDM_Filter0       DFSDM1_Filter0
+#define DFSDM_Filter1       DFSDM1_Filter1
+#define DFSDM_Filter2       DFSDM1_Filter2
+#define DFSDM_Filter3       DFSDM1_Filter3
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+#define AES                 ((AES_TypeDef *) AES_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)                                    
+#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)                                    
+#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)                                    
+#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)                                    
+#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)                                    
+#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)                                    
+#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)                                    
+#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)                                    
+#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)                                    
+#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)                                    
+#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)                                   
+#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)                                    
+#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)                                    
+#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)                                    
+#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)                                    
+#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)                                    
+#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)                                    
+#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)                                    
+#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)                                    
+#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)                                    
+#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)                                    
+#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)                                   
+#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)                                    
+#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)                                    
+#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)                                    
+#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)                                    
+#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)                                    
+#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)                                    
+#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)                                   
+#define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos             (29U)                                   
+#define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)                                   
+#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)                                   
+#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)                                    
+#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)                                    
+#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)                                    
+#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos             (5U)                                    
+#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos            (6U)                                    
+#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)                                   
+#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)                                   
+#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)                                   
+#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)                                   
+#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos            (16U)                                   
+#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)                                   
+#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)                                   
+#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos               (21U)                                   
+#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)                                   
+#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)                                   
+#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)                                   
+#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)                                   
+#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)                                   
+#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos             (31U)                                   
+#define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)                                    
+#define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)                                    
+#define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos             (2U)                                    
+#define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)                                    
+#define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)                                    
+#define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)                                   
+#define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)                                    
+#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)                                    
+#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)                                    
+#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)                                    
+#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)                                   
+#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)                                   
+#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)                                   
+#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)                                   
+#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)                                   
+#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)                                   
+#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)                                    
+#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)                                    
+#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)                                    
+#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)                                    
+#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)                                   
+#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)                                   
+#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)                                   
+#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)                                   
+#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)                                   
+#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)                                    
+#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
+#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
+#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
+#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
+#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
+#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
+#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
+#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
+#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
+#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
+#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
+#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos                (16U)                                   
+#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
+#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
+#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
+#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
+#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
+#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
+#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
+#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
+#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
+#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
+#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
+#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)                                    
+#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
+#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
+#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
+#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
+#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
+#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
+#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
+#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos                (16U)                                   
+#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
+#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
+#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
+#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
+#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
+#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
+#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
+#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)                                    
+#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
+#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
+#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
+#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
+#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
+#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
+#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
+#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos                (16U)                                   
+#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
+#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
+#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
+#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
+#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
+#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
+#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
+#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)                                    
+#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)                                    
+#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)                                   
+#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)                                   
+#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)                                   
+#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)                                    
+#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)                                    
+#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)                                   
+#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)                                   
+#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)                                   
+#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)                                    
+#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)                                    
+#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)                                   
+#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)                                   
+#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)                                   
+#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)                                    
+#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)                                    
+#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)                                    
+#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)                                    
+#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)                                    
+#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos            (6U)                                    
+#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos              (8U)                                    
+#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos              (14U)                                   
+#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (20U)                                   
+#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (26U)                                   
+#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)                                    
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)                                   
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)                                   
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)                                    
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)                                   
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)                                   
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)                                    
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)                                   
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)                                   
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)                                    
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)                                   
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)                                   
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)                                    
+#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)                                    
+#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)                                    
+#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)                                    
+#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)                                    
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)                                    
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)                                    
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)                                    
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)                                   
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)                                    
+#define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)                                    
+#define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)                                    
+#define ADC_CSR_EOC_MST_Msk            (0x1U << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)                                    
+#define ADC_CSR_EOS_MST_Msk            (0x1U << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)                                    
+#define ADC_CSR_OVR_MST_Msk            (0x1U << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)                                    
+#define ADC_CSR_JEOC_MST_Msk           (0x1U << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)                                    
+#define ADC_CSR_JEOS_MST_Msk           (0x1U << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)                                    
+#define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)                                    
+#define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)                                    
+#define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos          (10U)                                   
+#define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)                                   
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)                                   
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1U << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)                                   
+#define ADC_CSR_EOC_SLV_Msk            (0x1U << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)                                   
+#define ADC_CSR_EOS_SLV_Msk            (0x1U << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)                                   
+#define ADC_CSR_OVR_SLV_Msk            (0x1U << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)                                   
+#define ADC_CSR_JEOC_SLV_Msk           (0x1U << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)                                   
+#define ADC_CSR_JEOS_SLV_Msk           (0x1U << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)                                   
+#define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)                                   
+#define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)                                   
+#define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos          (26U)                                   
+#define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)                                    
+#define ADC_CCR_DUAL_Msk               (0x1FU << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01U << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02U << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04U << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08U << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10U << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)                                    
+#define ADC_CCR_DELAY_Msk              (0xFU << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1U << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2U << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4U << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8U << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos             (13U)                                   
+#define ADC_CCR_DMACFG_Msk             (0x1U << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
+#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos               (14U)                                   
+#define ADC_CCR_MDMA_Msk               (0x3U << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
+#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0                 (0x1U << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1                 (0x2U << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos             (16U)                                   
+#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos              (18U)                                   
+#define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)                                   
+#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos               (23U)                                   
+#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos             (24U)                                   
+#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)                                    
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+#define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)                                   
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+#define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)                                          
+#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Advanced Encryption Standard (AES)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for AES_CR register  *********************/
+#define AES_CR_EN_Pos            (0U)                                          
+#define AES_CR_EN_Msk            (0x1U << AES_CR_EN_Pos)                       /*!< 0x00000001 */
+#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos      (1U)                                          
+#define AES_CR_DATATYPE_Msk      (0x3U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
+#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
+#define AES_CR_DATATYPE_0        (0x1U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1        (0x2U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos          (3U)                                          
+#define AES_CR_MODE_Msk          (0x3U << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
+#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0            (0x1U << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
+#define AES_CR_MODE_1            (0x2U << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos         (5U)                                          
+#define AES_CR_CHMOD_Msk         (0x803U << AES_CR_CHMOD_Pos)                  /*!< 0x00010060 */
+#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0           (0x001U << AES_CR_CHMOD_Pos)                  /*!< 0x00000020 */
+#define AES_CR_CHMOD_1           (0x002U << AES_CR_CHMOD_Pos)                  /*!< 0x00000040 */
+#define AES_CR_CHMOD_2           (0x800U << AES_CR_CHMOD_Pos)                  /*!< 0x00010000 */
+
+#define AES_CR_CCFC_Pos          (7U)                                          
+#define AES_CR_CCFC_Msk          (0x1U << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
+#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos          (8U)                                          
+#define AES_CR_ERRC_Msk          (0x1U << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
+#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
+#define AES_CR_CCFIE_Pos         (9U)                                          
+#define AES_CR_CCFIE_Msk         (0x1U << AES_CR_CCFIE_Pos)                    /*!< 0x00000200 */
+#define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
+#define AES_CR_ERRIE_Pos         (10U)                                         
+#define AES_CR_ERRIE_Msk         (0x1U << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
+#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos       (11U)                                         
+#define AES_CR_DMAINEN_Msk       (0x1U << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
+#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
+#define AES_CR_DMAOUTEN_Pos      (12U)                                         
+#define AES_CR_DMAOUTEN_Msk      (0x1U << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
+
+#define AES_CR_GCMPH_Pos         (13U)                                         
+#define AES_CR_GCMPH_Msk         (0x3U << AES_CR_GCMPH_Pos)                    /*!< 0x00006000 */
+#define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
+#define AES_CR_GCMPH_0           (0x1U << AES_CR_GCMPH_Pos)                    /*!< 0x00002000 */
+#define AES_CR_GCMPH_1           (0x2U << AES_CR_GCMPH_Pos)                    /*!< 0x00004000 */
+
+#define AES_CR_KEYSIZE_Pos       (18U)                                         
+#define AES_CR_KEYSIZE_Msk       (0x1U << AES_CR_KEYSIZE_Pos)                  /*!< 0x00040000 */
+#define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
+
+/*******************  Bit definition for AES_SR register  *********************/
+#define AES_SR_CCF_Pos           (0U)                                          
+#define AES_SR_CCF_Msk           (0x1U << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
+#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos         (1U)                                          
+#define AES_SR_RDERR_Msk         (0x1U << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
+#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos         (2U)                                          
+#define AES_SR_WRERR_Msk         (0x1U << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
+#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
+#define AES_SR_BUSY_Pos          (3U)                                          
+#define AES_SR_BUSY_Msk          (0x1U << AES_SR_BUSY_Pos)                     /*!< 0x00000008 */
+#define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
+
+/*******************  Bit definition for AES_DINR register  *******************/
+#define AES_DINR_Pos             (0U)                                          
+#define AES_DINR_Msk             (0xFFFFFFFFU << AES_DINR_Pos)                 /*!< 0xFFFFFFFF */
+#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
+
+/*******************  Bit definition for AES_DOUTR register  ******************/
+#define AES_DOUTR_Pos            (0U)                                          
+#define AES_DOUTR_Msk            (0xFFFFFFFFU << AES_DOUTR_Pos)                /*!< 0xFFFFFFFF */
+#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
+
+/*******************  Bit definition for AES_KEYR0 register  ******************/
+#define AES_KEYR0_Pos            (0U)                                          
+#define AES_KEYR0_Msk            (0xFFFFFFFFU << AES_KEYR0_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
+
+/*******************  Bit definition for AES_KEYR1 register  ******************/
+#define AES_KEYR1_Pos            (0U)                                          
+#define AES_KEYR1_Msk            (0xFFFFFFFFU << AES_KEYR1_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
+
+/*******************  Bit definition for AES_KEYR2 register  ******************/
+#define AES_KEYR2_Pos            (0U)                                          
+#define AES_KEYR2_Msk            (0xFFFFFFFFU << AES_KEYR2_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
+
+/*******************  Bit definition for AES_KEYR3 register  ******************/
+#define AES_KEYR3_Pos            (0U)                                          
+#define AES_KEYR3_Msk            (0xFFFFFFFFU << AES_KEYR3_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
+
+/*******************  Bit definition for AES_KEYR4 register  ******************/
+#define AES_KEYR4_Pos            (0U)                                          
+#define AES_KEYR4_Msk            (0xFFFFFFFFU << AES_KEYR4_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
+
+/*******************  Bit definition for AES_KEYR5 register  ******************/
+#define AES_KEYR5_Pos            (0U)                                          
+#define AES_KEYR5_Msk            (0xFFFFFFFFU << AES_KEYR5_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
+
+/*******************  Bit definition for AES_KEYR6 register  ******************/
+#define AES_KEYR6_Pos            (0U)                                          
+#define AES_KEYR6_Msk            (0xFFFFFFFFU << AES_KEYR6_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
+
+/*******************  Bit definition for AES_KEYR7 register  ******************/
+#define AES_KEYR7_Pos            (0U)                                          
+#define AES_KEYR7_Msk            (0xFFFFFFFFU << AES_KEYR7_Pos)                /*!< 0xFFFFFFFF */
+#define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
+
+/*******************  Bit definition for AES_IVR0 register   ******************/
+#define AES_IVR0_Pos             (0U)                                          
+#define AES_IVR0_Msk             (0xFFFFFFFFU << AES_IVR0_Pos)                 /*!< 0xFFFFFFFF */
+#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
+
+/*******************  Bit definition for AES_IVR1 register   ******************/
+#define AES_IVR1_Pos             (0U)                                          
+#define AES_IVR1_Msk             (0xFFFFFFFFU << AES_IVR1_Pos)                 /*!< 0xFFFFFFFF */
+#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
+
+/*******************  Bit definition for AES_IVR2 register   ******************/
+#define AES_IVR2_Pos             (0U)                                          
+#define AES_IVR2_Msk             (0xFFFFFFFFU << AES_IVR2_Pos)                 /*!< 0xFFFFFFFF */
+#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
+
+/*******************  Bit definition for AES_IVR3 register   ******************/
+#define AES_IVR3_Pos             (0U)                                          
+#define AES_IVR3_Msk             (0xFFFFFFFFU << AES_IVR3_Pos)                 /*!< 0xFFFFFFFF */
+#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
+
+/*******************  Bit definition for AES_SUSP0R register  ******************/
+#define AES_SUSP0R_Pos           (0U)                                          
+#define AES_SUSP0R_Msk           (0xFFFFFFFFU << AES_SUSP0R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
+
+/*******************  Bit definition for AES_SUSP1R register  ******************/
+#define AES_SUSP1R_Pos           (0U)                                          
+#define AES_SUSP1R_Msk           (0xFFFFFFFFU << AES_SUSP1R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
+
+/*******************  Bit definition for AES_SUSP2R register  ******************/
+#define AES_SUSP2R_Pos           (0U)                                          
+#define AES_SUSP2R_Msk           (0xFFFFFFFFU << AES_SUSP2R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
+
+/*******************  Bit definition for AES_SUSP3R register  ******************/
+#define AES_SUSP3R_Pos           (0U)                                          
+#define AES_SUSP3R_Msk           (0xFFFFFFFFU << AES_SUSP3R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
+
+/*******************  Bit definition for AES_SUSP4R register  ******************/
+#define AES_SUSP4R_Pos           (0U)                                          
+#define AES_SUSP4R_Msk           (0xFFFFFFFFU << AES_SUSP4R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
+
+/*******************  Bit definition for AES_SUSP5R register  ******************/
+#define AES_SUSP5R_Pos           (0U)                                          
+#define AES_SUSP5R_Msk           (0xFFFFFFFFU << AES_SUSP5R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
+
+/*******************  Bit definition for AES_SUSP6R register  ******************/
+#define AES_SUSP6R_Pos           (0U)                                          
+#define AES_SUSP6R_Msk           (0xFFFFFFFFU << AES_SUSP6R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
+
+/*******************  Bit definition for AES_SUSP7R register  ******************/
+#define AES_SUSP7R_Pos           (0U)                                          
+#define AES_SUSP7R_Msk           (0xFFFFFFFFU << AES_SUSP7R_Pos)               /*!< 0xFFFFFFFF */
+#define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)                                      
+#define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)                                      
+#define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)                                      
+#define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)                                      
+#define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)                                      
+#define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)                                      
+#define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)                                       
+#define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)                                      
+#define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)                                       
+#define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)                                      
+#define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)                                       
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)                                       
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)                                       
+#define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)                                      
+#define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)                                       
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)                                      
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)                                  
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)                                  
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)                                  
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)                                  
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)                                  
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)                                   
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)                                   
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1U << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)                                   
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1U << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)                                   
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1U << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)                                   
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)                                   
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)                                   
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)                                   
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)                                  
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)                                  
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)                                  
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)                                   
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)                                   
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)                                   
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)                                  
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)                                  
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1U << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)                                  
+#define DFSDM_FLTCR1_FAST_Msk           (0x1U << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)                                  
+#define DFSDM_FLTCR1_RCH_Msk            (0x7U << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)                                  
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1U << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)                                  
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1U << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)                                  
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1U << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)                                  
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1U << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)                                  
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)                                   
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)                                   
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1U << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)                                   
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1U << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)                                   
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1U << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)                                   
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1U << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)                                   
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1U << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)                                  
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFU << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)                                   
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFU << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)                                   
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1U << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)                                   
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1U << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)                                   
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1U << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)                                   
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1U << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)                                   
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1U << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)                                   
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1U << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)                                   
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1U << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/*****************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)                                  
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFU << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)                                  
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFU << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)                                  
+#define DFSDM_FLTISR_RCIP_Msk           (0x1U << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)                                  
+#define DFSDM_FLTISR_JCIP_Msk           (0x1U << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)                                   
+#define DFSDM_FLTISR_AWDF_Msk           (0x1U << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)                                   
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1U << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)                                   
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1U << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)                                   
+#define DFSDM_FLTISR_REOCF_Msk          (0x1U << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)                                   
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1U << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/*****************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos       (24U)                                  
+#define DFSDM_FLTICR_CLRSCSDF_Msk       (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF           DFSDM_FLTICR_CLRSCSDF_Msk              /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)                                  
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)                                   
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1U << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)                                   
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)                                   
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/*****************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)                                  
+#define DFSDM_FLTFCR_FORD_Msk           (0x7U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)                                  
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFU << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)                                   
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFU << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)                                   
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)                                   
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)                                   
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)                                   
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1U << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)                                   
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)                                   
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)                                   
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)                                   
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)                                   
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)                                   
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)                                   
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)                                   
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)                                   
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)                                   
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)                                   
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)                                   
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos      (0U)                                            
+#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos      (4U)                                            
+#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos      (8U)                                            
+#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos      (12U)                                           
+#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos      (16U)                                           
+#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos      (20U)                                           
+#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos      (24U)                                           
+#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos        (0U)                                          
+#define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos        (1U)                                          
+#define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos        (2U)                                          
+#define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos        (3U)                                          
+#define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos        (4U)                                          
+#define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos        (5U)                                          
+#define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos        (6U)                                          
+#define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos        (7U)                                          
+#define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos        (8U)                                          
+#define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos        (9U)                                          
+#define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos       (10U)                                         
+#define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos       (11U)                                         
+#define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos       (12U)                                         
+#define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos       (13U)                                         
+#define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos       (14U)                                         
+#define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos       (15U)                                         
+#define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos       (16U)                                         
+#define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos       (17U)                                         
+#define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos       (18U)                                         
+#define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos       (19U)                                         
+#define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos       (20U)                                         
+#define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos       (21U)                                         
+#define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos       (22U)                                         
+#define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos       (23U)                                         
+#define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos       (24U)                                         
+#define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos       (25U)                                         
+#define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos       (26U)                                         
+#define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos       (27U)                                         
+#define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos       (28U)                                         
+#define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos       (29U)                                         
+#define EXTI_IMR1_IM29_Msk       (0x1U << EXTI_IMR1_IM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos       (30U)                                         
+#define EXTI_IMR1_IM30_Msk       (0x1U << EXTI_IMR1_IM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos       (31U)                                         
+#define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos         (0U)                                          
+#define EXTI_IMR1_IM_Msk         (0xFFFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos        (0U)                                          
+#define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos        (1U)                                          
+#define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos        (2U)                                          
+#define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos        (3U)                                          
+#define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos        (4U)                                          
+#define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos        (5U)                                          
+#define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos        (6U)                                          
+#define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos        (7U)                                          
+#define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos        (8U)                                          
+#define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos        (9U)                                          
+#define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos       (10U)                                         
+#define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos       (11U)                                         
+#define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos       (12U)                                         
+#define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos       (13U)                                         
+#define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos       (14U)                                         
+#define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos       (15U)                                         
+#define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos       (16U)                                         
+#define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos       (17U)                                         
+#define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos       (18U)                                         
+#define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos       (19U)                                         
+#define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos       (20U)                                         
+#define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos       (21U)                                         
+#define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos       (22U)                                         
+#define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos       (23U)                                         
+#define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos       (24U)                                         
+#define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos       (25U)                                         
+#define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos       (26U)                                         
+#define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos       (27U)                                         
+#define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos       (28U)                                         
+#define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos       (29U)                                         
+#define EXTI_EMR1_EM29_Msk       (0x1U << EXTI_EMR1_EM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos       (30U)                                         
+#define EXTI_EMR1_EM30_Msk       (0x1U << EXTI_EMR1_EM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos       (31U)                                         
+#define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos       (0U)                                          
+#define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos       (1U)                                          
+#define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos       (2U)                                          
+#define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos       (3U)                                          
+#define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos       (4U)                                          
+#define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos       (5U)                                          
+#define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos       (6U)                                          
+#define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos       (7U)                                          
+#define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos       (8U)                                          
+#define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos       (9U)                                          
+#define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos      (10U)                                         
+#define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos      (11U)                                         
+#define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos      (12U)                                         
+#define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos      (13U)                                         
+#define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos      (14U)                                         
+#define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos      (15U)                                         
+#define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos      (16U)                                         
+#define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos      (18U)                                         
+#define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos      (19U)                                         
+#define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos      (20U)                                         
+#define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos      (21U)                                         
+#define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos      (22U)                                         
+#define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos       (0U)                                          
+#define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos       (1U)                                          
+#define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos       (2U)                                          
+#define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos       (3U)                                          
+#define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos       (4U)                                          
+#define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos       (5U)                                          
+#define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos       (6U)                                          
+#define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos       (7U)                                          
+#define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos       (8U)                                          
+#define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos       (9U)                                          
+#define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos      (10U)                                         
+#define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos      (11U)                                         
+#define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos      (12U)                                         
+#define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos      (13U)                                         
+#define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos      (14U)                                         
+#define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos      (15U)                                         
+#define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos      (16U)                                         
+#define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos      (18U)                                         
+#define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos      (19U)                                         
+#define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos      (20U)                                         
+#define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos      (21U)                                         
+#define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos      (22U)                                         
+#define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos     (0U)                                          
+#define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos     (1U)                                          
+#define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos     (2U)                                          
+#define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos     (3U)                                          
+#define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos     (4U)                                          
+#define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos     (5U)                                          
+#define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos     (6U)                                          
+#define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos     (7U)                                          
+#define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos     (8U)                                          
+#define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos     (9U)                                          
+#define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos    (10U)                                         
+#define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos    (11U)                                         
+#define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos    (12U)                                         
+#define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos    (13U)                                         
+#define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos    (14U)                                         
+#define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos    (15U)                                         
+#define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos    (16U)                                         
+#define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos    (18U)                                         
+#define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos    (19U)                                         
+#define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos    (20U)                                         
+#define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos    (21U)                                         
+#define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos    (22U)                                         
+#define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos        (0U)                                          
+#define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos        (1U)                                          
+#define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos        (2U)                                          
+#define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos        (3U)                                          
+#define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos        (4U)                                          
+#define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos        (5U)                                          
+#define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos        (6U)                                          
+#define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos        (7U)                                          
+#define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos        (8U)                                          
+#define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos        (9U)                                          
+#define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos       (10U)                                         
+#define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos       (11U)                                         
+#define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos       (12U)                                         
+#define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos       (13U)                                         
+#define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos       (14U)                                         
+#define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos       (15U)                                         
+#define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos       (16U)                                         
+#define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos       (18U)                                         
+#define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */
+#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos       (19U)                                         
+#define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos       (20U)                                         
+#define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos       (21U)                                         
+#define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos       (22U)                                         
+#define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos       (0U)                                          
+#define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos       (1U)                                          
+#define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos       (2U)                                          
+#define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos       (3U)                                          
+#define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos       (4U)                                          
+#define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos       (5U)                                          
+#define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos       (6U)                                          
+#define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos       (7U)                                          
+#define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM_Pos         (0U)                                          
+#define EXTI_IMR2_IM_Msk         (0xFFU << EXTI_IMR2_IM_Pos)                   /*!< 0x000000FF */
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos       (0U)                                          
+#define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos       (1U)                                          
+#define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos       (2U)                                          
+#define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos       (3U)                                          
+#define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos       (4U)                                          
+#define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos       (5U)                                          
+#define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos       (6U)                                          
+#define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos       (7U)                                          
+#define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT35_Pos      (3U)                                          
+#define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos      (4U)                                          
+#define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos      (5U)                                          
+#define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos      (6U)                                          
+#define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT35_Pos      (3U)                                          
+#define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos      (4U)                                          
+#define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos      (5U)                                          
+#define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos      (6U)                                          
+#define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI35_Pos    (3U)                                          
+#define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos    (4U)                                          
+#define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos    (5U)                                          
+#define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos    (6U)                                          
+#define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF35_Pos       (3U)                                          
+#define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */
+#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos       (4U)                                          
+#define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */
+#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos       (5U)                                          
+#define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */
+#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos       (6U)                                          
+#define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos             (0U)                                 
+#define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                
+#define FLASH_ACR_LATENCY_0WS             (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS             (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS             (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS             (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS             (0x00000004U)
+#define FLASH_ACR_PRFTEN_Pos              (8U)                                 
+#define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk                 
+#define FLASH_ACR_ICEN_Pos                (9U)                                 
+#define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk                   
+#define FLASH_ACR_DCEN_Pos                (10U)                                
+#define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk                   
+#define FLASH_ACR_ICRST_Pos               (11U)                                
+#define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk                  
+#define FLASH_ACR_DCRST_Pos               (12U)                                
+#define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk                  
+#define FLASH_ACR_RUN_PD_Pos              (13U)                                
+#define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)                                
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                  (0U)                                 
+#define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     
+#define FLASH_SR_OPERR_Pos                (1U)                                 
+#define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk                   
+#define FLASH_SR_PROGERR_Pos              (3U)                                 
+#define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk                 
+#define FLASH_SR_WRPERR_Pos               (4U)                                 
+#define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk                  
+#define FLASH_SR_PGAERR_Pos               (5U)                                 
+#define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk                  
+#define FLASH_SR_SIZERR_Pos               (6U)                                 
+#define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk                  
+#define FLASH_SR_PGSERR_Pos               (7U)                                 
+#define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk                  
+#define FLASH_SR_MISERR_Pos               (8U)                                 
+#define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk                  
+#define FLASH_SR_FASTERR_Pos              (9U)                                 
+#define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk                 
+#define FLASH_SR_RDERR_Pos                (14U)                                
+#define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk                   
+#define FLASH_SR_OPTVERR_Pos              (15U)                                
+#define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk                 
+#define FLASH_SR_BSY_Pos                  (16U)                                
+#define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                   (0U)                                 
+#define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk                      
+#define FLASH_CR_PER_Pos                  (1U)                                 
+#define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk                     
+#define FLASH_CR_MER1_Pos                 (2U)                                 
+#define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk                    
+#define FLASH_CR_PNB_Pos                  (3U)                                 
+#define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk                     
+#define FLASH_CR_BKER_Pos                 (11U)                                
+#define FLASH_CR_BKER_Msk                 (0x1U << FLASH_CR_BKER_Pos)          /*!< 0x00000800 */
+#define FLASH_CR_BKER                     FLASH_CR_BKER_Msk                    
+#define FLASH_CR_MER2_Pos                 (15U)                                
+#define FLASH_CR_MER2_Msk                 (0x1U << FLASH_CR_MER2_Pos)          /*!< 0x00008000 */
+#define FLASH_CR_MER2                     FLASH_CR_MER2_Msk                    
+#define FLASH_CR_STRT_Pos                 (16U)                                
+#define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    
+#define FLASH_CR_OPTSTRT_Pos              (17U)                                
+#define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk                 
+#define FLASH_CR_FSTPG_Pos                (18U)                                
+#define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk                   
+#define FLASH_CR_EOPIE_Pos                (24U)                                
+#define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   
+#define FLASH_CR_ERRIE_Pos                (25U)                                
+#define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   
+#define FLASH_CR_RDERRIE_Pos              (26U)                                
+#define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk                 
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)                                
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              
+#define FLASH_CR_OPTLOCK_Pos              (30U)                                
+#define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk                 
+#define FLASH_CR_LOCK_Pos                 (31U)                                
+#define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)                                 
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk              
+#define FLASH_ECCR_BK_ECC_Pos             (19U)                                
+#define FLASH_ECCR_BK_ECC_Msk             (0x1U << FLASH_ECCR_BK_ECC_Pos)      /*!< 0x00080000 */
+#define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk                
+#define FLASH_ECCR_SYSF_ECC_Pos           (20U)                                
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk              
+#define FLASH_ECCR_ECCIE_Pos              (24U)                                
+#define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk                 
+#define FLASH_ECCR_ECCC_Pos               (30U)                                
+#define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk                  
+#define FLASH_ECCR_ECCD_Pos               (31U)                                
+#define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk                  
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                (0U)                                 
+#define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk                   
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)                                 
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk               
+#define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)                                
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk             
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)                                
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk            
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)                                
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk             
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)                                
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk               
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)                                
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk             
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)                                
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk            
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)                                
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk               
+#define FLASH_OPTR_BFB2_Pos               (20U)                                
+#define FLASH_OPTR_BFB2_Msk               (0x1U << FLASH_OPTR_BFB2_Pos)        /*!< 0x00100000 */
+#define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk                  
+#define FLASH_OPTR_DUALBANK_Pos           (21U)                                
+#define FLASH_OPTR_DUALBANK_Msk           (0x1U << FLASH_OPTR_DUALBANK_Pos)    /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk              
+#define FLASH_OPTR_nBOOT1_Pos             (23U)                                
+#define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk                
+#define FLASH_OPTR_SRAM2_PE_Pos           (24U)                                
+#define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk              
+#define FLASH_OPTR_SRAM2_RST_Pos          (25U)                                
+#define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk             
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)                                 
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)                                 
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk        
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)                                
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk         
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)                                 
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk          
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)                                
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk           
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)                                 
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk          
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)                                
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk           
+
+/******************  Bits definition for FLASH_PCROP2SR register  **********/
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)                                 
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP2ER register  ***********/
+#define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)                                 
+#define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk        
+
+/******************  Bits definition for FLASH_WRP2AR register  ***************/
+#define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)                                 
+#define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk          
+#define FLASH_WRP2AR_WRP2A_END_Pos        (16U)                                
+#define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk           
+
+/******************  Bits definition for FLASH_WRP2BR register  ***************/
+#define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)                                 
+#define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk          
+#define FLASH_WRP2BR_WRP2B_END_Pos        (16U)                                
+#define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk           
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)                                       
+#define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)                                        
+#define FMC_BCRx_MBKEN_Msk         (0x1U << FMC_BCRx_MBKEN_Pos)                /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)                                        
+#define FMC_BCRx_MUXEN_Msk         (0x1U << FMC_BCRx_MUXEN_Pos)                /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)                                        
+#define FMC_BCRx_MTYP_Msk          (0x3U << FMC_BCRx_MTYP_Pos)                 /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)                                        
+#define FMC_BCRx_MWID_Msk          (0x3U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)                                        
+#define FMC_BCRx_FACCEN_Msk        (0x1U << FMC_BCRx_FACCEN_Pos)               /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)                                        
+#define FMC_BCRx_BURSTEN_Msk       (0x1U << FMC_BCRx_BURSTEN_Pos)              /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)                                        
+#define FMC_BCRx_WAITPOL_Msk       (0x1U << FMC_BCRx_WAITPOL_Pos)              /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)                                       
+#define FMC_BCRx_WAITCFG_Msk       (0x1U << FMC_BCRx_WAITCFG_Pos)              /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)                                       
+#define FMC_BCRx_WREN_Msk          (0x1U << FMC_BCRx_WREN_Pos)                 /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)                                       
+#define FMC_BCRx_WAITEN_Msk        (0x1U << FMC_BCRx_WAITEN_Pos)               /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)                                       
+#define FMC_BCRx_EXTMOD_Msk        (0x1U << FMC_BCRx_EXTMOD_Pos)               /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)                                       
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1U << FMC_BCRx_ASYNCWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)                                       
+#define FMC_BCRx_CPSIZE_Msk        (0x7U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */
+#define FMC_BCRx_CPSIZE_0          (0x1U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)                                       
+#define FMC_BCRx_CBURSTRW_Msk      (0x1U << FMC_BCRx_CBURSTRW_Pos)             /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)                                        
+#define FMC_BTRx_ADDSET_Msk        (0xFU << FMC_BTRx_ADDSET_Pos)               /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)                                        
+#define FMC_BTRx_ADDHLD_Msk        (0xFU << FMC_BTRx_ADDHLD_Pos)               /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)                                        
+#define FMC_BTRx_DATAST_Msk        (0xFFU << FMC_BTRx_DATAST_Pos)              /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10U << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20U << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40U << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80U << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)                                       
+#define FMC_BTRx_BUSTURN_Msk       (0xFU << FMC_BTRx_BUSTURN_Pos)              /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)                                       
+#define FMC_BTRx_CLKDIV_Msk        (0xFU << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)                                       
+#define FMC_BTRx_DATLAT_Msk        (0xFU << FMC_BTRx_DATLAT_Pos)               /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1U << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2U << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4U << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8U << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)                                       
+#define FMC_BTRx_ACCMOD_Msk        (0x3U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)                                        
+#define FMC_BWTRx_ADDSET_Msk       (0xFU << FMC_BWTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)                                        
+#define FMC_BWTRx_ADDHLD_Msk       (0xFU << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)                                        
+#define FMC_BWTRx_DATAST_Msk       (0xFFU << FMC_BWTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)                                       
+#define FMC_BWTRx_BUSTURN_Msk      (0xFU << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)                                       
+#define FMC_BWTRx_ACCMOD_Msk       (0x3U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  ********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)                                        
+#define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)                                        
+#define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos           (3U)                                        
+#define FMC_PCR_PTYP_Msk           (0x1U << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */
+#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
+
+#define FMC_PCR_PWID_Pos           (4U)                                        
+#define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)                                        
+#define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)                                        
+#define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)                                       
+#define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)                                       
+#define FMC_PCR_ECCPS_Msk          (0x7U << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  ********************/
+#define FMC_SR_IRS_Pos             (0U)                                        
+#define FMC_SR_IRS_Msk             (0x1U << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)                                        
+#define FMC_SR_ILS_Msk             (0x1U << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)                                        
+#define FMC_SR_IFS_Msk             (0x1U << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)                                        
+#define FMC_SR_IREN_Msk            (0x1U << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)                                        
+#define FMC_SR_ILEN_Msk            (0x1U << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)                                        
+#define FMC_SR_IFEN_Msk            (0x1U << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)                                        
+#define FMC_SR_FEMPT_Msk           (0x1U << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos        (0U)                                        
+#define FMC_PMEM_MEMSET_Msk        (0xFFU << FMC_PMEM_MEMSET_Pos)              /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0          (0x01U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos       (8U)                                        
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFU << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0         (0x01U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos       (16U)                                       
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFU << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0         (0x01U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos        (24U)                                       
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFU << FMC_PMEM_MEMHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0          (0x01U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  *******************/
+#define FMC_PATT_ATTSET_Pos        (0U)                                        
+#define FMC_PATT_ATTSET_Msk        (0xFFU << FMC_PATT_ATTSET_Pos)              /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0          (0x01U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos       (8U)                                        
+#define FMC_PATT_ATTWAIT_Msk       (0xFFU << FMC_PATT_ATTWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0         (0x01U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos       (16U)                                       
+#define FMC_PATT_ATTHOLD_Msk       (0xFFU << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0         (0x01U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos        (24U)                                       
+#define FMC_PATT_ATTHIZ_Msk        (0xFFU << FMC_PATT_ATTHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0          (0x01U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR register  *******************/
+#define FMC_ECCR_ECC_Pos           (0U)                                        
+#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFU << FMC_ECCR_ECC_Pos)           /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)                                    
+#define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk                    
+#define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)                                    
+#define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk                    
+#define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)                                    
+#define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk                    
+#define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)                                    
+#define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk                    
+#define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)                                    
+#define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk                    
+#define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)                                   
+#define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk                    
+#define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)                                   
+#define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk                    
+#define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)                                   
+#define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk                    
+#define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)                                   
+#define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk                    
+#define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)                                   
+#define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk                    
+#define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)                                   
+#define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk                   
+#define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)                                   
+#define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk                   
+#define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)                                   
+#define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk                   
+#define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)                                   
+#define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk                   
+#define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)                                   
+#define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk                   
+#define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)                                   
+#define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk                   
+#define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)                                    
+#define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk                     
+#define GPIO_OTYPER_OT1_Pos            (1U)                                    
+#define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk                     
+#define GPIO_OTYPER_OT2_Pos            (2U)                                    
+#define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk                     
+#define GPIO_OTYPER_OT3_Pos            (3U)                                    
+#define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk                     
+#define GPIO_OTYPER_OT4_Pos            (4U)                                    
+#define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk                     
+#define GPIO_OTYPER_OT5_Pos            (5U)                                    
+#define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk                     
+#define GPIO_OTYPER_OT6_Pos            (6U)                                    
+#define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk                     
+#define GPIO_OTYPER_OT7_Pos            (7U)                                    
+#define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk                     
+#define GPIO_OTYPER_OT8_Pos            (8U)                                    
+#define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk                     
+#define GPIO_OTYPER_OT9_Pos            (9U)                                    
+#define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk                     
+#define GPIO_OTYPER_OT10_Pos           (10U)                                   
+#define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk                    
+#define GPIO_OTYPER_OT11_Pos           (11U)                                   
+#define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk                    
+#define GPIO_OTYPER_OT12_Pos           (12U)                                   
+#define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk                    
+#define GPIO_OTYPER_OT13_Pos           (13U)                                   
+#define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk                    
+#define GPIO_OTYPER_OT14_Pos           (14U)                                   
+#define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk                    
+#define GPIO_OTYPER_OT15_Pos           (15U)                                   
+#define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk                    
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)                                    
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk                
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)                                    
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk                
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)                                    
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk                
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)                                    
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk                
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)                                    
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk                
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)                                   
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk                
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)                                   
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk                
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)                                   
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk                
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)                                   
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk                
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)                                   
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk                
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)                                   
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk               
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)                                   
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk               
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)                                   
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk               
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)                                   
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk               
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)                                   
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk               
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)                                   
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk               
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)                                    
+#define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk                    
+#define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)                                    
+#define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk                    
+#define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)                                    
+#define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk                    
+#define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)                                    
+#define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk                    
+#define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)                                    
+#define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk                    
+#define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)                                   
+#define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk                    
+#define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)                                   
+#define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk                    
+#define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)                                   
+#define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk                    
+#define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)                                   
+#define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk                    
+#define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)                                   
+#define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk                    
+#define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)                                   
+#define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk                   
+#define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)                                   
+#define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk                   
+#define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)                                   
+#define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk                   
+#define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)                                   
+#define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk                   
+#define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)                                   
+#define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk                   
+#define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)                                   
+#define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk                   
+#define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)                                    
+#define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk                        
+#define GPIO_IDR_ID1_Pos               (1U)                                    
+#define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk                        
+#define GPIO_IDR_ID2_Pos               (2U)                                    
+#define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk                        
+#define GPIO_IDR_ID3_Pos               (3U)                                    
+#define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk                        
+#define GPIO_IDR_ID4_Pos               (4U)                                    
+#define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk                        
+#define GPIO_IDR_ID5_Pos               (5U)                                    
+#define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk                        
+#define GPIO_IDR_ID6_Pos               (6U)                                    
+#define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk                        
+#define GPIO_IDR_ID7_Pos               (7U)                                    
+#define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk                        
+#define GPIO_IDR_ID8_Pos               (8U)                                    
+#define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk                        
+#define GPIO_IDR_ID9_Pos               (9U)                                    
+#define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk                        
+#define GPIO_IDR_ID10_Pos              (10U)                                   
+#define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk                       
+#define GPIO_IDR_ID11_Pos              (11U)                                   
+#define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk                       
+#define GPIO_IDR_ID12_Pos              (12U)                                   
+#define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk                       
+#define GPIO_IDR_ID13_Pos              (13U)                                   
+#define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk                       
+#define GPIO_IDR_ID14_Pos              (14U)                                   
+#define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk                       
+#define GPIO_IDR_ID15_Pos              (15U)                                   
+#define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk                       
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)                                    
+#define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk                        
+#define GPIO_ODR_OD1_Pos               (1U)                                    
+#define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk                        
+#define GPIO_ODR_OD2_Pos               (2U)                                    
+#define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk                        
+#define GPIO_ODR_OD3_Pos               (3U)                                    
+#define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk                        
+#define GPIO_ODR_OD4_Pos               (4U)                                    
+#define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk                        
+#define GPIO_ODR_OD5_Pos               (5U)                                    
+#define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk                        
+#define GPIO_ODR_OD6_Pos               (6U)                                    
+#define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk                        
+#define GPIO_ODR_OD7_Pos               (7U)                                    
+#define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk                        
+#define GPIO_ODR_OD8_Pos               (8U)                                    
+#define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk                        
+#define GPIO_ODR_OD9_Pos               (9U)                                    
+#define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk                        
+#define GPIO_ODR_OD10_Pos              (10U)                                   
+#define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk                       
+#define GPIO_ODR_OD11_Pos              (11U)                                   
+#define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk                       
+#define GPIO_ODR_OD12_Pos              (12U)                                   
+#define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk                       
+#define GPIO_ODR_OD13_Pos              (13U)                                   
+#define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk                       
+#define GPIO_ODR_OD14_Pos              (14U)                                   
+#define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk                       
+#define GPIO_ODR_OD15_Pos              (15U)                                   
+#define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk                       
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)                                    
+#define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk                       
+#define GPIO_BSRR_BS1_Pos              (1U)                                    
+#define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk                       
+#define GPIO_BSRR_BS2_Pos              (2U)                                    
+#define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk                       
+#define GPIO_BSRR_BS3_Pos              (3U)                                    
+#define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk                       
+#define GPIO_BSRR_BS4_Pos              (4U)                                    
+#define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk                       
+#define GPIO_BSRR_BS5_Pos              (5U)                                    
+#define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk                       
+#define GPIO_BSRR_BS6_Pos              (6U)                                    
+#define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk                       
+#define GPIO_BSRR_BS7_Pos              (7U)                                    
+#define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk                       
+#define GPIO_BSRR_BS8_Pos              (8U)                                    
+#define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk                       
+#define GPIO_BSRR_BS9_Pos              (9U)                                    
+#define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk                       
+#define GPIO_BSRR_BS10_Pos             (10U)                                   
+#define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk                      
+#define GPIO_BSRR_BS11_Pos             (11U)                                   
+#define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk                      
+#define GPIO_BSRR_BS12_Pos             (12U)                                   
+#define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk                      
+#define GPIO_BSRR_BS13_Pos             (13U)                                   
+#define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk                      
+#define GPIO_BSRR_BS14_Pos             (14U)                                   
+#define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk                      
+#define GPIO_BSRR_BS15_Pos             (15U)                                   
+#define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk                      
+#define GPIO_BSRR_BR0_Pos              (16U)                                   
+#define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk                       
+#define GPIO_BSRR_BR1_Pos              (17U)                                   
+#define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk                       
+#define GPIO_BSRR_BR2_Pos              (18U)                                   
+#define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk                       
+#define GPIO_BSRR_BR3_Pos              (19U)                                   
+#define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk                       
+#define GPIO_BSRR_BR4_Pos              (20U)                                   
+#define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk                       
+#define GPIO_BSRR_BR5_Pos              (21U)                                   
+#define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk                       
+#define GPIO_BSRR_BR6_Pos              (22U)                                   
+#define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk                       
+#define GPIO_BSRR_BR7_Pos              (23U)                                   
+#define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk                       
+#define GPIO_BSRR_BR8_Pos              (24U)                                   
+#define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk                       
+#define GPIO_BSRR_BR9_Pos              (25U)                                   
+#define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk                       
+#define GPIO_BSRR_BR10_Pos             (26U)                                   
+#define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk                      
+#define GPIO_BSRR_BR11_Pos             (27U)                                   
+#define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk                      
+#define GPIO_BSRR_BR12_Pos             (28U)                                   
+#define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk                      
+#define GPIO_BSRR_BR13_Pos             (29U)                                   
+#define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk                      
+#define GPIO_BSRR_BR14_Pos             (30U)                                   
+#define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk                      
+#define GPIO_BSRR_BR15_Pos             (31U)                                   
+#define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk                      
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)                                    
+#define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk                      
+#define GPIO_LCKR_LCK1_Pos             (1U)                                    
+#define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk                      
+#define GPIO_LCKR_LCK2_Pos             (2U)                                    
+#define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk                      
+#define GPIO_LCKR_LCK3_Pos             (3U)                                    
+#define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk                      
+#define GPIO_LCKR_LCK4_Pos             (4U)                                    
+#define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk                      
+#define GPIO_LCKR_LCK5_Pos             (5U)                                    
+#define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk                      
+#define GPIO_LCKR_LCK6_Pos             (6U)                                    
+#define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk                      
+#define GPIO_LCKR_LCK7_Pos             (7U)                                    
+#define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk                      
+#define GPIO_LCKR_LCK8_Pos             (8U)                                    
+#define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk                      
+#define GPIO_LCKR_LCK9_Pos             (9U)                                    
+#define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk                      
+#define GPIO_LCKR_LCK10_Pos            (10U)                                   
+#define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk                     
+#define GPIO_LCKR_LCK11_Pos            (11U)                                   
+#define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk                     
+#define GPIO_LCKR_LCK12_Pos            (12U)                                   
+#define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk                     
+#define GPIO_LCKR_LCK13_Pos            (13U)                                   
+#define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk                     
+#define GPIO_LCKR_LCK14_Pos            (14U)                                   
+#define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk                     
+#define GPIO_LCKR_LCK15_Pos            (15U)                                   
+#define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk                     
+#define GPIO_LCKR_LCKK_Pos             (16U)                                   
+#define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk                      
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)                                    
+#define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)                                    
+#define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)                                    
+#define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)                                   
+#define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)                                   
+#define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)                                   
+#define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)                                   
+#define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)                                   
+#define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk                    
+#define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)                                    
+#define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)                                    
+#define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)                                    
+#define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk                   
+#define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)                                   
+#define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk                   
+#define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)                                   
+#define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk                   
+#define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)                                   
+#define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk                   
+#define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)                                   
+#define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk                   
+#define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)                                   
+#define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk                   
+#define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)                                    
+#define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk                        
+#define GPIO_BRR_BR1_Pos               (1U)                                    
+#define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk                        
+#define GPIO_BRR_BR2_Pos               (2U)                                    
+#define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk                        
+#define GPIO_BRR_BR3_Pos               (3U)                                    
+#define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk                        
+#define GPIO_BRR_BR4_Pos               (4U)                                    
+#define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk                        
+#define GPIO_BRR_BR5_Pos               (5U)                                    
+#define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk                        
+#define GPIO_BRR_BR6_Pos               (6U)                                    
+#define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk                        
+#define GPIO_BRR_BR7_Pos               (7U)                                    
+#define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk                        
+#define GPIO_BRR_BR8_Pos               (8U)                                    
+#define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk                        
+#define GPIO_BRR_BR9_Pos               (9U)                                    
+#define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk                        
+#define GPIO_BRR_BR10_Pos              (10U)                                   
+#define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk                       
+#define GPIO_BRR_BR11_Pos              (11U)                                   
+#define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk                       
+#define GPIO_BRR_BR12_Pos              (12U)                                   
+#define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk                       
+#define GPIO_BRR_BR13_Pos              (13U)                                   
+#define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk                       
+#define GPIO_BRR_BR14_Pos              (14U)                                   
+#define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk                       
+#define GPIO_BRR_BR15_Pos              (15U)                                   
+#define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk                       
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+/******************  Bits definition for GPIO_ASCR register  *******************/
+#define GPIO_ASCR_ASC0_Pos             (0U)                                    
+#define GPIO_ASCR_ASC0_Msk             (0x1U << GPIO_ASCR_ASC0_Pos)            /*!< 0x00000001 */
+#define GPIO_ASCR_ASC0                 GPIO_ASCR_ASC0_Msk                      
+#define GPIO_ASCR_ASC1_Pos             (1U)                                    
+#define GPIO_ASCR_ASC1_Msk             (0x1U << GPIO_ASCR_ASC1_Pos)            /*!< 0x00000002 */
+#define GPIO_ASCR_ASC1                 GPIO_ASCR_ASC1_Msk                      
+#define GPIO_ASCR_ASC2_Pos             (2U)                                    
+#define GPIO_ASCR_ASC2_Msk             (0x1U << GPIO_ASCR_ASC2_Pos)            /*!< 0x00000004 */
+#define GPIO_ASCR_ASC2                 GPIO_ASCR_ASC2_Msk                      
+#define GPIO_ASCR_ASC3_Pos             (3U)                                    
+#define GPIO_ASCR_ASC3_Msk             (0x1U << GPIO_ASCR_ASC3_Pos)            /*!< 0x00000008 */
+#define GPIO_ASCR_ASC3                 GPIO_ASCR_ASC3_Msk                      
+#define GPIO_ASCR_ASC4_Pos             (4U)                                    
+#define GPIO_ASCR_ASC4_Msk             (0x1U << GPIO_ASCR_ASC4_Pos)            /*!< 0x00000010 */
+#define GPIO_ASCR_ASC4                 GPIO_ASCR_ASC4_Msk                      
+#define GPIO_ASCR_ASC5_Pos             (5U)                                    
+#define GPIO_ASCR_ASC5_Msk             (0x1U << GPIO_ASCR_ASC5_Pos)            /*!< 0x00000020 */
+#define GPIO_ASCR_ASC5                 GPIO_ASCR_ASC5_Msk                      
+#define GPIO_ASCR_ASC6_Pos             (6U)                                    
+#define GPIO_ASCR_ASC6_Msk             (0x1U << GPIO_ASCR_ASC6_Pos)            /*!< 0x00000040 */
+#define GPIO_ASCR_ASC6                 GPIO_ASCR_ASC6_Msk                      
+#define GPIO_ASCR_ASC7_Pos             (7U)                                    
+#define GPIO_ASCR_ASC7_Msk             (0x1U << GPIO_ASCR_ASC7_Pos)            /*!< 0x00000080 */
+#define GPIO_ASCR_ASC7                 GPIO_ASCR_ASC7_Msk                      
+#define GPIO_ASCR_ASC8_Pos             (8U)                                    
+#define GPIO_ASCR_ASC8_Msk             (0x1U << GPIO_ASCR_ASC8_Pos)            /*!< 0x00000100 */
+#define GPIO_ASCR_ASC8                 GPIO_ASCR_ASC8_Msk                      
+#define GPIO_ASCR_ASC9_Pos             (9U)                                    
+#define GPIO_ASCR_ASC9_Msk             (0x1U << GPIO_ASCR_ASC9_Pos)            /*!< 0x00000200 */
+#define GPIO_ASCR_ASC9                 GPIO_ASCR_ASC9_Msk                      
+#define GPIO_ASCR_ASC10_Pos            (10U)                                   
+#define GPIO_ASCR_ASC10_Msk            (0x1U << GPIO_ASCR_ASC10_Pos)           /*!< 0x00000400 */
+#define GPIO_ASCR_ASC10                GPIO_ASCR_ASC10_Msk                     
+#define GPIO_ASCR_ASC11_Pos            (11U)                                   
+#define GPIO_ASCR_ASC11_Msk            (0x1U << GPIO_ASCR_ASC11_Pos)           /*!< 0x00000800 */
+#define GPIO_ASCR_ASC11                GPIO_ASCR_ASC11_Msk                     
+#define GPIO_ASCR_ASC12_Pos            (12U)                                   
+#define GPIO_ASCR_ASC12_Msk            (0x1U << GPIO_ASCR_ASC12_Pos)           /*!< 0x00001000 */
+#define GPIO_ASCR_ASC12                GPIO_ASCR_ASC12_Msk                     
+#define GPIO_ASCR_ASC13_Pos            (13U)                                   
+#define GPIO_ASCR_ASC13_Msk            (0x1U << GPIO_ASCR_ASC13_Pos)           /*!< 0x00002000 */
+#define GPIO_ASCR_ASC13                GPIO_ASCR_ASC13_Msk                     
+#define GPIO_ASCR_ASC14_Pos            (14U)                                   
+#define GPIO_ASCR_ASC14_Msk            (0x1U << GPIO_ASCR_ASC14_Pos)           /*!< 0x00004000 */
+#define GPIO_ASCR_ASC14                GPIO_ASCR_ASC14_Msk                     
+#define GPIO_ASCR_ASC15_Pos            (15U)                                   
+#define GPIO_ASCR_ASC15_Msk            (0x1U << GPIO_ASCR_ASC15_Pos)           /*!< 0x00008000 */
+#define GPIO_ASCR_ASC15                GPIO_ASCR_ASC15_Msk                     
+
+/* Legacy defines */
+#define GPIO_ASCR_EN_0                      GPIO_ASCR_ASC0
+#define GPIO_ASCR_EN_1                      GPIO_ASCR_ASC1
+#define GPIO_ASCR_EN_2                      GPIO_ASCR_ASC2
+#define GPIO_ASCR_EN_3                      GPIO_ASCR_ASC3
+#define GPIO_ASCR_EN_4                      GPIO_ASCR_ASC4
+#define GPIO_ASCR_EN_5                      GPIO_ASCR_ASC5
+#define GPIO_ASCR_EN_6                      GPIO_ASCR_ASC6
+#define GPIO_ASCR_EN_7                      GPIO_ASCR_ASC7
+#define GPIO_ASCR_EN_8                      GPIO_ASCR_ASC8
+#define GPIO_ASCR_EN_9                      GPIO_ASCR_ASC9
+#define GPIO_ASCR_EN_10                     GPIO_ASCR_ASC10
+#define GPIO_ASCR_EN_11                     GPIO_ASCR_ASC11
+#define GPIO_ASCR_EN_12                     GPIO_ASCR_ASC12
+#define GPIO_ASCR_EN_13                     GPIO_ASCR_ASC13
+#define GPIO_ASCR_EN_14                     GPIO_ASCR_ASC14
+#define GPIO_ASCR_EN_15                     GPIO_ASCR_ASC15
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos            (13U)                                     
+#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
+#define FW_CSSA_ADD_Pos      (8U)                                              
+#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos      (8U)                                              
+#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
+#define FW_NVDSSA_ADD_Pos    (8U)                                              
+#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos    (8U)                                              
+#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos     (6U)                                              
+#define FW_VDSSA_ADD_Msk     (0x7FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos     (6U)                                              
+#define FW_VDSL_LENG_Msk     (0x7FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos        (0U)                                              
+#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos        (1U)                                              
+#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos        (2U)                                              
+#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos              (14U)                                     
+#define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos              (9U)                                      
+#define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos              (8U)                                      
+#define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos             (0U)                                      
+#define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)                                      
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos       (1U)                                      
+#define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)                                      
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)                                      
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_USV_Pos              (10U)                                     
+#define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */
+#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
+#define PWR_CR2_IOSV_Pos             (9U)                                      
+#define PWR_CR2_IOSV_Msk             (0x1U << PWR_CR2_IOSV_Pos)                /*!< 0x00000200 */
+#define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos             (4U)                                      
+#define PWR_CR2_PVME_Msk             (0xFU << PWR_CR2_PVME_Pos)                /*!< 0x000000F0 */
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos            (7U)                                      
+#define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos            (6U)                                      
+#define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos            (5U)                                      
+#define PWR_CR2_PVME2_Msk            (0x1U << PWR_CR2_PVME2_Pos)               /*!< 0x00000020 */
+#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos            (4U)                                      
+#define PWR_CR2_PVME1_Msk            (0x1U << PWR_CR2_PVME1_Pos)               /*!< 0x00000010 */
+#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos              (1U)                                      
+#define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos         (3U)                                      
+#define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos             (0U)                                      
+#define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos             (15U)                                     
+#define PWR_CR3_EIWF_Msk             (0x1U << PWR_CR3_EIWF_Pos)                /*!< 0x00008000 */
+#define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos              (10U)                                     
+#define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos              (8U)                                      
+#define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos            (4U)                                      
+#define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos            (3U)                                      
+#define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos            (2U)                                      
+#define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos            (1U)                                      
+#define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos            (0U)                                      
+#define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos             (0U)                                      
+#define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos             (9U)                                      
+#define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos              (8U)                                      
+#define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos              (4U)                                      
+#define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos              (3U)                                      
+#define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos              (2U)                                      
+#define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos              (1U)                                      
+#define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos              (0U)                                      
+#define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos             (15U)                                     
+#define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos              (8U)                                      
+#define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos              (0U)                                      
+#define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos             (4U)                                      
+#define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos             (3U)                                      
+#define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos             (2U)                                      
+#define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos             (1U)                                      
+#define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos             (0U)                                      
+#define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos            (15U)                                     
+#define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos            (14U)                                     
+#define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos            (13U)                                     
+#define PWR_SR2_PVMO2_Msk            (0x1U << PWR_SR2_PVMO2_Pos)               /*!< 0x00002000 */
+#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos            (12U)                                     
+#define PWR_SR2_PVMO1_Msk            (0x1U << PWR_SR2_PVMO1_Pos)               /*!< 0x00001000 */
+#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos             (11U)                                     
+#define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos             (10U)                                     
+#define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos           (9U)                                      
+#define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos           (8U)                                      
+#define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos             (8U)                                      
+#define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos             (0U)                                      
+#define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos            (4U)                                      
+#define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos            (3U)                                      
+#define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos            (2U)                                      
+#define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos            (1U)                                      
+#define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos            (0U)                                      
+#define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos           (15U)                                     
+#define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos           (13U)                                     
+#define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos           (12U)                                     
+#define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos           (11U)                                     
+#define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos           (10U)                                     
+#define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos            (9U)                                      
+#define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos            (8U)                                      
+#define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos            (7U)                                      
+#define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos            (6U)                                      
+#define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos            (5U)                                      
+#define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos            (4U)                                      
+#define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos            (3U)                                      
+#define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos            (2U)                                      
+#define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos            (1U)                                      
+#define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos            (0U)                                      
+#define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos           (14U)                                     
+#define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos           (12U)                                     
+#define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos           (11U)                                     
+#define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos           (10U)                                     
+#define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos            (9U)                                      
+#define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos            (8U)                                      
+#define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos            (7U)                                      
+#define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos            (6U)                                      
+#define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos            (5U)                                      
+#define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos            (4U)                                      
+#define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos            (3U)                                      
+#define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos            (2U)                                      
+#define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos            (1U)                                      
+#define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos            (0U)                                      
+#define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+#define PWR_PUCRB_PB15_Pos           (15U)                                     
+#define PWR_PUCRB_PB15_Msk           (0x1U << PWR_PUCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos           (14U)                                     
+#define PWR_PUCRB_PB14_Msk           (0x1U << PWR_PUCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos           (13U)                                     
+#define PWR_PUCRB_PB13_Msk           (0x1U << PWR_PUCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos           (12U)                                     
+#define PWR_PUCRB_PB12_Msk           (0x1U << PWR_PUCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos           (11U)                                     
+#define PWR_PUCRB_PB11_Msk           (0x1U << PWR_PUCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos           (10U)                                     
+#define PWR_PUCRB_PB10_Msk           (0x1U << PWR_PUCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos            (9U)                                      
+#define PWR_PUCRB_PB9_Msk            (0x1U << PWR_PUCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
+#define PWR_PUCRB_PB8_Pos            (8U)                                      
+#define PWR_PUCRB_PB8_Msk            (0x1U << PWR_PUCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
+#define PWR_PUCRB_PB7_Pos            (7U)                                      
+#define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos            (6U)                                      
+#define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos            (5U)                                      
+#define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos            (4U)                                      
+#define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos            (3U)                                      
+#define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB2_Pos            (2U)                                      
+#define PWR_PUCRB_PB2_Msk            (0x1U << PWR_PUCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos            (1U)                                      
+#define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos            (0U)                                      
+#define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB15_Pos           (15U)                                     
+#define PWR_PDCRB_PB15_Msk           (0x1U << PWR_PDCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos           (14U)                                     
+#define PWR_PDCRB_PB14_Msk           (0x1U << PWR_PDCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos           (13U)                                     
+#define PWR_PDCRB_PB13_Msk           (0x1U << PWR_PDCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos           (12U)                                     
+#define PWR_PDCRB_PB12_Msk           (0x1U << PWR_PDCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos           (11U)                                     
+#define PWR_PDCRB_PB11_Msk           (0x1U << PWR_PDCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos           (10U)                                     
+#define PWR_PDCRB_PB10_Msk           (0x1U << PWR_PDCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos            (9U)                                      
+#define PWR_PDCRB_PB9_Msk            (0x1U << PWR_PDCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
+#define PWR_PDCRB_PB8_Pos            (8U)                                      
+#define PWR_PDCRB_PB8_Msk            (0x1U << PWR_PDCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
+#define PWR_PDCRB_PB7_Pos            (7U)                                      
+#define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos            (6U)                                      
+#define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos            (5U)                                      
+#define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos            (3U)                                      
+#define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB2_Pos            (2U)                                      
+#define PWR_PDCRB_PB2_Msk            (0x1U << PWR_PDCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos            (1U)                                      
+#define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos            (0U)                                      
+#define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos           (15U)                                     
+#define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos           (14U)                                     
+#define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos           (13U)                                     
+#define PWR_PUCRC_PC13_Msk           (0x1U << PWR_PUCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos           (12U)                                     
+#define PWR_PUCRC_PC12_Msk           (0x1U << PWR_PUCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos           (11U)                                     
+#define PWR_PUCRC_PC11_Msk           (0x1U << PWR_PUCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos           (10U)                                     
+#define PWR_PUCRC_PC10_Msk           (0x1U << PWR_PUCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos            (9U)                                      
+#define PWR_PUCRC_PC9_Msk            (0x1U << PWR_PUCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
+#define PWR_PUCRC_PC8_Pos            (8U)                                      
+#define PWR_PUCRC_PC8_Msk            (0x1U << PWR_PUCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
+#define PWR_PUCRC_PC7_Pos            (7U)                                      
+#define PWR_PUCRC_PC7_Msk            (0x1U << PWR_PUCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
+#define PWR_PUCRC_PC6_Pos            (6U)                                      
+#define PWR_PUCRC_PC6_Msk            (0x1U << PWR_PUCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
+#define PWR_PUCRC_PC5_Pos            (5U)                                      
+#define PWR_PUCRC_PC5_Msk            (0x1U << PWR_PUCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
+#define PWR_PUCRC_PC4_Pos            (4U)                                      
+#define PWR_PUCRC_PC4_Msk            (0x1U << PWR_PUCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
+#define PWR_PUCRC_PC3_Pos            (3U)                                      
+#define PWR_PUCRC_PC3_Msk            (0x1U << PWR_PUCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
+#define PWR_PUCRC_PC2_Pos            (2U)                                      
+#define PWR_PUCRC_PC2_Msk            (0x1U << PWR_PUCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
+#define PWR_PUCRC_PC1_Pos            (1U)                                      
+#define PWR_PUCRC_PC1_Msk            (0x1U << PWR_PUCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
+#define PWR_PUCRC_PC0_Pos            (0U)                                      
+#define PWR_PUCRC_PC0_Msk            (0x1U << PWR_PUCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos           (15U)                                     
+#define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos           (14U)                                     
+#define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos           (13U)                                     
+#define PWR_PDCRC_PC13_Msk           (0x1U << PWR_PDCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos           (12U)                                     
+#define PWR_PDCRC_PC12_Msk           (0x1U << PWR_PDCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos           (11U)                                     
+#define PWR_PDCRC_PC11_Msk           (0x1U << PWR_PDCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos           (10U)                                     
+#define PWR_PDCRC_PC10_Msk           (0x1U << PWR_PDCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos            (9U)                                      
+#define PWR_PDCRC_PC9_Msk            (0x1U << PWR_PDCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
+#define PWR_PDCRC_PC8_Pos            (8U)                                      
+#define PWR_PDCRC_PC8_Msk            (0x1U << PWR_PDCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
+#define PWR_PDCRC_PC7_Pos            (7U)                                      
+#define PWR_PDCRC_PC7_Msk            (0x1U << PWR_PDCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
+#define PWR_PDCRC_PC6_Pos            (6U)                                      
+#define PWR_PDCRC_PC6_Msk            (0x1U << PWR_PDCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
+#define PWR_PDCRC_PC5_Pos            (5U)                                      
+#define PWR_PDCRC_PC5_Msk            (0x1U << PWR_PDCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
+#define PWR_PDCRC_PC4_Pos            (4U)                                      
+#define PWR_PDCRC_PC4_Msk            (0x1U << PWR_PDCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
+#define PWR_PDCRC_PC3_Pos            (3U)                                      
+#define PWR_PDCRC_PC3_Msk            (0x1U << PWR_PDCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
+#define PWR_PDCRC_PC2_Pos            (2U)                                      
+#define PWR_PDCRC_PC2_Msk            (0x1U << PWR_PDCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
+#define PWR_PDCRC_PC1_Pos            (1U)                                      
+#define PWR_PDCRC_PC1_Msk            (0x1U << PWR_PDCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
+#define PWR_PDCRC_PC0_Pos            (0U)                                      
+#define PWR_PDCRC_PC0_Msk            (0x1U << PWR_PDCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRD register  ********************/
+#define PWR_PUCRD_PD15_Pos           (15U)                                     
+#define PWR_PUCRD_PD15_Msk           (0x1U << PWR_PUCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos           (14U)                                     
+#define PWR_PUCRD_PD14_Msk           (0x1U << PWR_PUCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos           (13U)                                     
+#define PWR_PUCRD_PD13_Msk           (0x1U << PWR_PUCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos           (12U)                                     
+#define PWR_PUCRD_PD12_Msk           (0x1U << PWR_PUCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos           (11U)                                     
+#define PWR_PUCRD_PD11_Msk           (0x1U << PWR_PUCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos           (10U)                                     
+#define PWR_PUCRD_PD10_Msk           (0x1U << PWR_PUCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos            (9U)                                      
+#define PWR_PUCRD_PD9_Msk            (0x1U << PWR_PUCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
+#define PWR_PUCRD_PD8_Pos            (8U)                                      
+#define PWR_PUCRD_PD8_Msk            (0x1U << PWR_PUCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
+#define PWR_PUCRD_PD7_Pos            (7U)                                      
+#define PWR_PUCRD_PD7_Msk            (0x1U << PWR_PUCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
+#define PWR_PUCRD_PD6_Pos            (6U)                                      
+#define PWR_PUCRD_PD6_Msk            (0x1U << PWR_PUCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
+#define PWR_PUCRD_PD5_Pos            (5U)                                      
+#define PWR_PUCRD_PD5_Msk            (0x1U << PWR_PUCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
+#define PWR_PUCRD_PD4_Pos            (4U)                                      
+#define PWR_PUCRD_PD4_Msk            (0x1U << PWR_PUCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
+#define PWR_PUCRD_PD3_Pos            (3U)                                      
+#define PWR_PUCRD_PD3_Msk            (0x1U << PWR_PUCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
+#define PWR_PUCRD_PD2_Pos            (2U)                                      
+#define PWR_PUCRD_PD2_Msk            (0x1U << PWR_PUCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
+#define PWR_PUCRD_PD1_Pos            (1U)                                      
+#define PWR_PUCRD_PD1_Msk            (0x1U << PWR_PUCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
+#define PWR_PUCRD_PD0_Pos            (0U)                                      
+#define PWR_PUCRD_PD0_Msk            (0x1U << PWR_PUCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRD register  ********************/
+#define PWR_PDCRD_PD15_Pos           (15U)                                     
+#define PWR_PDCRD_PD15_Msk           (0x1U << PWR_PDCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos           (14U)                                     
+#define PWR_PDCRD_PD14_Msk           (0x1U << PWR_PDCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos           (13U)                                     
+#define PWR_PDCRD_PD13_Msk           (0x1U << PWR_PDCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos           (12U)                                     
+#define PWR_PDCRD_PD12_Msk           (0x1U << PWR_PDCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos           (11U)                                     
+#define PWR_PDCRD_PD11_Msk           (0x1U << PWR_PDCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos           (10U)                                     
+#define PWR_PDCRD_PD10_Msk           (0x1U << PWR_PDCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos            (9U)                                      
+#define PWR_PDCRD_PD9_Msk            (0x1U << PWR_PDCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
+#define PWR_PDCRD_PD8_Pos            (8U)                                      
+#define PWR_PDCRD_PD8_Msk            (0x1U << PWR_PDCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
+#define PWR_PDCRD_PD7_Pos            (7U)                                      
+#define PWR_PDCRD_PD7_Msk            (0x1U << PWR_PDCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
+#define PWR_PDCRD_PD6_Pos            (6U)                                      
+#define PWR_PDCRD_PD6_Msk            (0x1U << PWR_PDCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
+#define PWR_PDCRD_PD5_Pos            (5U)                                      
+#define PWR_PDCRD_PD5_Msk            (0x1U << PWR_PDCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
+#define PWR_PDCRD_PD4_Pos            (4U)                                      
+#define PWR_PDCRD_PD4_Msk            (0x1U << PWR_PDCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
+#define PWR_PDCRD_PD3_Pos            (3U)                                      
+#define PWR_PDCRD_PD3_Msk            (0x1U << PWR_PDCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
+#define PWR_PDCRD_PD2_Pos            (2U)                                      
+#define PWR_PDCRD_PD2_Msk            (0x1U << PWR_PDCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
+#define PWR_PDCRD_PD1_Pos            (1U)                                      
+#define PWR_PDCRD_PD1_Msk            (0x1U << PWR_PDCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
+#define PWR_PDCRD_PD0_Pos            (0U)                                      
+#define PWR_PDCRD_PD0_Msk            (0x1U << PWR_PDCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRE register  ********************/
+#define PWR_PUCRE_PE15_Pos           (15U)                                     
+#define PWR_PUCRE_PE15_Msk           (0x1U << PWR_PUCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos           (14U)                                     
+#define PWR_PUCRE_PE14_Msk           (0x1U << PWR_PUCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos           (13U)                                     
+#define PWR_PUCRE_PE13_Msk           (0x1U << PWR_PUCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos           (12U)                                     
+#define PWR_PUCRE_PE12_Msk           (0x1U << PWR_PUCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos           (11U)                                     
+#define PWR_PUCRE_PE11_Msk           (0x1U << PWR_PUCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos           (10U)                                     
+#define PWR_PUCRE_PE10_Msk           (0x1U << PWR_PUCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos            (9U)                                      
+#define PWR_PUCRE_PE9_Msk            (0x1U << PWR_PUCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
+#define PWR_PUCRE_PE8_Pos            (8U)                                      
+#define PWR_PUCRE_PE8_Msk            (0x1U << PWR_PUCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
+#define PWR_PUCRE_PE7_Pos            (7U)                                      
+#define PWR_PUCRE_PE7_Msk            (0x1U << PWR_PUCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
+#define PWR_PUCRE_PE6_Pos            (6U)                                      
+#define PWR_PUCRE_PE6_Msk            (0x1U << PWR_PUCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
+#define PWR_PUCRE_PE5_Pos            (5U)                                      
+#define PWR_PUCRE_PE5_Msk            (0x1U << PWR_PUCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
+#define PWR_PUCRE_PE4_Pos            (4U)                                      
+#define PWR_PUCRE_PE4_Msk            (0x1U << PWR_PUCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
+#define PWR_PUCRE_PE3_Pos            (3U)                                      
+#define PWR_PUCRE_PE3_Msk            (0x1U << PWR_PUCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
+#define PWR_PUCRE_PE2_Pos            (2U)                                      
+#define PWR_PUCRE_PE2_Msk            (0x1U << PWR_PUCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
+#define PWR_PUCRE_PE1_Pos            (1U)                                      
+#define PWR_PUCRE_PE1_Msk            (0x1U << PWR_PUCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
+#define PWR_PUCRE_PE0_Pos            (0U)                                      
+#define PWR_PUCRE_PE0_Msk            (0x1U << PWR_PUCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRE register  ********************/
+#define PWR_PDCRE_PE15_Pos           (15U)                                     
+#define PWR_PDCRE_PE15_Msk           (0x1U << PWR_PDCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos           (14U)                                     
+#define PWR_PDCRE_PE14_Msk           (0x1U << PWR_PDCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos           (13U)                                     
+#define PWR_PDCRE_PE13_Msk           (0x1U << PWR_PDCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos           (12U)                                     
+#define PWR_PDCRE_PE12_Msk           (0x1U << PWR_PDCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos           (11U)                                     
+#define PWR_PDCRE_PE11_Msk           (0x1U << PWR_PDCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos           (10U)                                     
+#define PWR_PDCRE_PE10_Msk           (0x1U << PWR_PDCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos            (9U)                                      
+#define PWR_PDCRE_PE9_Msk            (0x1U << PWR_PDCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
+#define PWR_PDCRE_PE8_Pos            (8U)                                      
+#define PWR_PDCRE_PE8_Msk            (0x1U << PWR_PDCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
+#define PWR_PDCRE_PE7_Pos            (7U)                                      
+#define PWR_PDCRE_PE7_Msk            (0x1U << PWR_PDCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
+#define PWR_PDCRE_PE6_Pos            (6U)                                      
+#define PWR_PDCRE_PE6_Msk            (0x1U << PWR_PDCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
+#define PWR_PDCRE_PE5_Pos            (5U)                                      
+#define PWR_PDCRE_PE5_Msk            (0x1U << PWR_PDCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
+#define PWR_PDCRE_PE4_Pos            (4U)                                      
+#define PWR_PDCRE_PE4_Msk            (0x1U << PWR_PDCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
+#define PWR_PDCRE_PE3_Pos            (3U)                                      
+#define PWR_PDCRE_PE3_Msk            (0x1U << PWR_PDCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
+#define PWR_PDCRE_PE2_Pos            (2U)                                      
+#define PWR_PDCRE_PE2_Msk            (0x1U << PWR_PDCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
+#define PWR_PDCRE_PE1_Pos            (1U)                                      
+#define PWR_PDCRE_PE1_Msk            (0x1U << PWR_PDCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
+#define PWR_PDCRE_PE0_Pos            (0U)                                      
+#define PWR_PDCRE_PE0_Msk            (0x1U << PWR_PDCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRF register  ********************/
+#define PWR_PUCRF_PF15_Pos           (15U)                                     
+#define PWR_PUCRF_PF15_Msk           (0x1U << PWR_PUCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos           (14U)                                     
+#define PWR_PUCRF_PF14_Msk           (0x1U << PWR_PUCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos           (13U)                                     
+#define PWR_PUCRF_PF13_Msk           (0x1U << PWR_PUCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos           (12U)                                     
+#define PWR_PUCRF_PF12_Msk           (0x1U << PWR_PUCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos           (11U)                                     
+#define PWR_PUCRF_PF11_Msk           (0x1U << PWR_PUCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos           (10U)                                     
+#define PWR_PUCRF_PF10_Msk           (0x1U << PWR_PUCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos            (9U)                                      
+#define PWR_PUCRF_PF9_Msk            (0x1U << PWR_PUCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
+#define PWR_PUCRF_PF8_Pos            (8U)                                      
+#define PWR_PUCRF_PF8_Msk            (0x1U << PWR_PUCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
+#define PWR_PUCRF_PF7_Pos            (7U)                                      
+#define PWR_PUCRF_PF7_Msk            (0x1U << PWR_PUCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
+#define PWR_PUCRF_PF6_Pos            (6U)                                      
+#define PWR_PUCRF_PF6_Msk            (0x1U << PWR_PUCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
+#define PWR_PUCRF_PF5_Pos            (5U)                                      
+#define PWR_PUCRF_PF5_Msk            (0x1U << PWR_PUCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
+#define PWR_PUCRF_PF4_Pos            (4U)                                      
+#define PWR_PUCRF_PF4_Msk            (0x1U << PWR_PUCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
+#define PWR_PUCRF_PF3_Pos            (3U)                                      
+#define PWR_PUCRF_PF3_Msk            (0x1U << PWR_PUCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
+#define PWR_PUCRF_PF2_Pos            (2U)                                      
+#define PWR_PUCRF_PF2_Msk            (0x1U << PWR_PUCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
+#define PWR_PUCRF_PF1_Pos            (1U)                                      
+#define PWR_PUCRF_PF1_Msk            (0x1U << PWR_PUCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
+#define PWR_PUCRF_PF0_Pos            (0U)                                      
+#define PWR_PUCRF_PF0_Msk            (0x1U << PWR_PUCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRF register  ********************/
+#define PWR_PDCRF_PF15_Pos           (15U)                                     
+#define PWR_PDCRF_PF15_Msk           (0x1U << PWR_PDCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
+#define PWR_PDCRF_PF14_Pos           (14U)                                     
+#define PWR_PDCRF_PF14_Msk           (0x1U << PWR_PDCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
+#define PWR_PDCRF_PF13_Pos           (13U)                                     
+#define PWR_PDCRF_PF13_Msk           (0x1U << PWR_PDCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
+#define PWR_PDCRF_PF12_Pos           (12U)                                     
+#define PWR_PDCRF_PF12_Msk           (0x1U << PWR_PDCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
+#define PWR_PDCRF_PF11_Pos           (11U)                                     
+#define PWR_PDCRF_PF11_Msk           (0x1U << PWR_PDCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
+#define PWR_PDCRF_PF10_Pos           (10U)                                     
+#define PWR_PDCRF_PF10_Msk           (0x1U << PWR_PDCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos            (9U)                                      
+#define PWR_PDCRF_PF9_Msk            (0x1U << PWR_PDCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
+#define PWR_PDCRF_PF8_Pos            (8U)                                      
+#define PWR_PDCRF_PF8_Msk            (0x1U << PWR_PDCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
+#define PWR_PDCRF_PF7_Pos            (7U)                                      
+#define PWR_PDCRF_PF7_Msk            (0x1U << PWR_PDCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
+#define PWR_PDCRF_PF6_Pos            (6U)                                      
+#define PWR_PDCRF_PF6_Msk            (0x1U << PWR_PDCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
+#define PWR_PDCRF_PF5_Pos            (5U)                                      
+#define PWR_PDCRF_PF5_Msk            (0x1U << PWR_PDCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
+#define PWR_PDCRF_PF4_Pos            (4U)                                      
+#define PWR_PDCRF_PF4_Msk            (0x1U << PWR_PDCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
+#define PWR_PDCRF_PF3_Pos            (3U)                                      
+#define PWR_PDCRF_PF3_Msk            (0x1U << PWR_PDCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
+#define PWR_PDCRF_PF2_Pos            (2U)                                      
+#define PWR_PDCRF_PF2_Msk            (0x1U << PWR_PDCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
+#define PWR_PDCRF_PF1_Pos            (1U)                                      
+#define PWR_PDCRF_PF1_Msk            (0x1U << PWR_PDCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
+#define PWR_PDCRF_PF0_Pos            (0U)                                      
+#define PWR_PDCRF_PF0_Msk            (0x1U << PWR_PDCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRG register  ********************/
+#define PWR_PUCRG_PG15_Pos           (15U)                                     
+#define PWR_PUCRG_PG15_Msk           (0x1U << PWR_PUCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
+#define PWR_PUCRG_PG14_Pos           (14U)                                     
+#define PWR_PUCRG_PG14_Msk           (0x1U << PWR_PUCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
+#define PWR_PUCRG_PG13_Pos           (13U)                                     
+#define PWR_PUCRG_PG13_Msk           (0x1U << PWR_PUCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
+#define PWR_PUCRG_PG12_Pos           (12U)                                     
+#define PWR_PUCRG_PG12_Msk           (0x1U << PWR_PUCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
+#define PWR_PUCRG_PG11_Pos           (11U)                                     
+#define PWR_PUCRG_PG11_Msk           (0x1U << PWR_PUCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
+#define PWR_PUCRG_PG10_Pos           (10U)                                     
+#define PWR_PUCRG_PG10_Msk           (0x1U << PWR_PUCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
+#define PWR_PUCRG_PG9_Pos            (9U)                                      
+#define PWR_PUCRG_PG9_Msk            (0x1U << PWR_PUCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
+#define PWR_PUCRG_PG8_Pos            (8U)                                      
+#define PWR_PUCRG_PG8_Msk            (0x1U << PWR_PUCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
+#define PWR_PUCRG_PG7_Pos            (7U)                                      
+#define PWR_PUCRG_PG7_Msk            (0x1U << PWR_PUCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
+#define PWR_PUCRG_PG6_Pos            (6U)                                      
+#define PWR_PUCRG_PG6_Msk            (0x1U << PWR_PUCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
+#define PWR_PUCRG_PG5_Pos            (5U)                                      
+#define PWR_PUCRG_PG5_Msk            (0x1U << PWR_PUCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
+#define PWR_PUCRG_PG4_Pos            (4U)                                      
+#define PWR_PUCRG_PG4_Msk            (0x1U << PWR_PUCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
+#define PWR_PUCRG_PG3_Pos            (3U)                                      
+#define PWR_PUCRG_PG3_Msk            (0x1U << PWR_PUCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
+#define PWR_PUCRG_PG2_Pos            (2U)                                      
+#define PWR_PUCRG_PG2_Msk            (0x1U << PWR_PUCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
+#define PWR_PUCRG_PG1_Pos            (1U)                                      
+#define PWR_PUCRG_PG1_Msk            (0x1U << PWR_PUCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
+#define PWR_PUCRG_PG0_Pos            (0U)                                      
+#define PWR_PUCRG_PG0_Msk            (0x1U << PWR_PUCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRG register  ********************/
+#define PWR_PDCRG_PG15_Pos           (15U)                                     
+#define PWR_PDCRG_PG15_Msk           (0x1U << PWR_PDCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */
+#define PWR_PDCRG_PG14_Pos           (14U)                                     
+#define PWR_PDCRG_PG14_Msk           (0x1U << PWR_PDCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */
+#define PWR_PDCRG_PG13_Pos           (13U)                                     
+#define PWR_PDCRG_PG13_Msk           (0x1U << PWR_PDCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */
+#define PWR_PDCRG_PG12_Pos           (12U)                                     
+#define PWR_PDCRG_PG12_Msk           (0x1U << PWR_PDCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */
+#define PWR_PDCRG_PG11_Pos           (11U)                                     
+#define PWR_PDCRG_PG11_Msk           (0x1U << PWR_PDCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */
+#define PWR_PDCRG_PG10_Pos           (10U)                                     
+#define PWR_PDCRG_PG10_Msk           (0x1U << PWR_PDCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos            (9U)                                      
+#define PWR_PDCRG_PG9_Msk            (0x1U << PWR_PDCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
+#define PWR_PDCRG_PG8_Pos            (8U)                                      
+#define PWR_PDCRG_PG8_Msk            (0x1U << PWR_PDCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
+#define PWR_PDCRG_PG7_Pos            (7U)                                      
+#define PWR_PDCRG_PG7_Msk            (0x1U << PWR_PDCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
+#define PWR_PDCRG_PG6_Pos            (6U)                                      
+#define PWR_PDCRG_PG6_Msk            (0x1U << PWR_PDCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
+#define PWR_PDCRG_PG5_Pos            (5U)                                      
+#define PWR_PDCRG_PG5_Msk            (0x1U << PWR_PDCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
+#define PWR_PDCRG_PG4_Pos            (4U)                                      
+#define PWR_PDCRG_PG4_Msk            (0x1U << PWR_PDCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
+#define PWR_PDCRG_PG3_Pos            (3U)                                      
+#define PWR_PDCRG_PG3_Msk            (0x1U << PWR_PDCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
+#define PWR_PDCRG_PG2_Pos            (2U)                                      
+#define PWR_PDCRG_PG2_Msk            (0x1U << PWR_PDCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
+#define PWR_PDCRG_PG1_Pos            (1U)                                      
+#define PWR_PDCRG_PG1_Msk            (0x1U << PWR_PDCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
+#define PWR_PDCRG_PG0_Pos            (0U)                                      
+#define PWR_PDCRG_PG0_Msk            (0x1U << PWR_PDCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRH register  ********************/
+#define PWR_PUCRH_PH1_Pos            (1U)                                      
+#define PWR_PUCRH_PH1_Msk            (0x1U << PWR_PUCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
+#define PWR_PUCRH_PH0_Pos            (0U)                                      
+#define PWR_PUCRH_PH0_Msk            (0x1U << PWR_PUCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRH register  ********************/
+#define PWR_PDCRH_PH1_Pos            (1U)                                      
+#define PWR_PDCRH_PH1_Msk            (0x1U << PWR_PDCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
+#define PWR_PDCRH_PH0_Pos            (0U)                                      
+#define PWR_PDCRH_PH0_Msk            (0x1U << PWR_PDCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_PLLSAI2_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_MSION_Pos                     (0U)                              
+#define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */
+#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos                    (1U)                              
+#define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos                  (2U)                              
+#define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos                  (3U)                              
+#define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos                  (4U)                              
+#define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos                     (8U)                              
+#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                  (9U)                              
+#define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                    (10U)                             
+#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos                   (11U)                             
+#define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */
+#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos                     (16U)                             
+#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                    (17U)                             
+#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                    (18U)                             
+#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                     (19U)                             
+#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                     (24U)                             
+#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                    (25U)                             
+#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos                 (26U)                             
+#define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos                (27U)                             
+#define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
+#define RCC_CR_PLLSAI2ON_Pos                 (28U)                             
+#define RCC_CR_PLLSAI2ON_Msk                 (0x1U << RCC_CR_PLLSAI2ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */
+#define RCC_CR_PLLSAI2RDY_Pos                (29U)                             
+#define RCC_CR_PLLSAI2RDY_Msk                (0x1U << RCC_CR_PLLSAI2RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos                 (0U)                              
+#define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos                (8U)                              
+#define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                 (16U)                             
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos                (24U)                             
+#define RCC_ICSCR_HSITRIM_Msk                (0x1FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x1F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)                              
+#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)                              
+#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)                              
+#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)                              
+#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)                             
+#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
+#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
+#define RCC_CFGR_MCOSEL_Msk                  (0x7U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [2:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
+#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
+ 
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+ 
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)                              
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk            
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)                              
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)                              
+#define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk              
+#define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)                              
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk              
+#define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)                             
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk            
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)                             
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk              
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)                             
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk            
+
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)                             
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk              
+#define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)                             
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk            
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)                             
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk              
+#define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk      
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk      
+
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                (0U)                              
+#define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk             
+#define RCC_CIER_LSERDYIE_Pos                (1U)                              
+#define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk             
+#define RCC_CIER_MSIRDYIE_Pos                (2U)                              
+#define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk             
+#define RCC_CIER_HSIRDYIE_Pos                (3U)                              
+#define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk             
+#define RCC_CIER_HSERDYIE_Pos                (4U)                              
+#define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk             
+#define RCC_CIER_PLLRDYIE_Pos                (5U)                              
+#define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk             
+#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)                              
+#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk         
+#define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)                              
+#define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk         
+#define RCC_CIER_LSECSSIE_Pos                (9U)                              
+#define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk             
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)                              
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk              
+#define RCC_CIFR_LSERDYF_Pos                 (1U)                              
+#define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk              
+#define RCC_CIFR_MSIRDYF_Pos                 (2U)                              
+#define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk              
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)                              
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk              
+#define RCC_CIFR_HSERDYF_Pos                 (4U)                              
+#define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk              
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)                              
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk              
+#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)                              
+#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk          
+#define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)                              
+#define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk          
+#define RCC_CIFR_CSSF_Pos                    (8U)                              
+#define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk                 
+#define RCC_CIFR_LSECSSF_Pos                 (9U)                              
+#define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk              
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                 (0U)                              
+#define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk              
+#define RCC_CICR_LSERDYC_Pos                 (1U)                              
+#define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk              
+#define RCC_CICR_MSIRDYC_Pos                 (2U)                              
+#define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk              
+#define RCC_CICR_HSIRDYC_Pos                 (3U)                              
+#define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk              
+#define RCC_CICR_HSERDYC_Pos                 (4U)                              
+#define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk              
+#define RCC_CICR_PLLRDYC_Pos                 (5U)                              
+#define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk              
+#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)                              
+#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk          
+#define RCC_CICR_PLLSAI2RDYC_Pos             (7U)                              
+#define RCC_CICR_PLLSAI2RDYC_Msk             (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk          
+#define RCC_CICR_CSSC_Pos                    (8U)                              
+#define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk                 
+#define RCC_CICR_LSECSSC_Pos                 (9U)                              
+#define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk              
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)                              
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk          
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)                              
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk          
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)                              
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk         
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)                             
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk           
+#define RCC_AHB1RSTR_TSCRST_Pos              (16U)                             
+#define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk           
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)                              
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk         
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)                              
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk         
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)                              
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk         
+#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)                              
+#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk         
+#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)                              
+#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk         
+#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)                              
+#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk         
+#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)                              
+#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk         
+#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)                              
+#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk         
+#define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)                             
+#define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk         
+#define RCC_AHB2RSTR_ADCRST_Pos              (13U)                             
+#define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk           
+#define RCC_AHB2RSTR_AESRST_Pos              (16U)                             
+#define RCC_AHB2RSTR_AESRST_Msk              (0x1U << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTR_AESRST                  RCC_AHB2RSTR_AESRST_Msk           
+#define RCC_AHB2RSTR_RNGRST_Pos              (18U)                             
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk           
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FMCRST_Pos              (0U)                              
+#define RCC_AHB3RSTR_FMCRST_Msk              (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk           
+#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)                              
+#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk          
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)                              
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk         
+#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)                              
+#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk         
+#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)                              
+#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk         
+#define RCC_APB1RSTR1_TIM5RST_Pos            (3U)                              
+#define RCC_APB1RSTR1_TIM5RST_Msk            (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk         
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)                              
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk         
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)                              
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk         
+#define RCC_APB1RSTR1_LCDRST_Pos             (9U)                              
+#define RCC_APB1RSTR1_LCDRST_Msk             (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR1_LCDRST                 RCC_APB1RSTR1_LCDRST_Msk          
+#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)                             
+#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk         
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)                             
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk         
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)                             
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk       
+#define RCC_APB1RSTR1_USART3RST_Pos          (18U)                             
+#define RCC_APB1RSTR1_USART3RST_Msk          (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk       
+#define RCC_APB1RSTR1_UART4RST_Pos           (19U)                             
+#define RCC_APB1RSTR1_UART4RST_Msk           (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk        
+#define RCC_APB1RSTR1_UART5RST_Pos           (20U)                             
+#define RCC_APB1RSTR1_UART5RST_Msk           (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk        
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)                             
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk         
+#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)                             
+#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk         
+#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)                             
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk         
+#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)                             
+#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk         
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)                             
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk          
+#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)                             
+#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk         
+#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)                             
+#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk        
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)                             
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk       
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)                              
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk      
+#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)                              
+#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk       
+#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)                              
+#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk       
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)                              
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk        
+#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)                             
+#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk        
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          
+#define RCC_APB2RSTR_TIM8RST_Pos             (13U)                             
+#define RCC_APB2RSTR_TIM8RST_Msk             (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk          
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)                             
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk         
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)                             
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk         
+#define RCC_APB2RSTR_TIM17RST_Pos            (18U)                             
+#define RCC_APB2RSTR_TIM17RST_Msk            (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk         
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)                             
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk          
+#define RCC_APB2RSTR_SAI2RST_Pos             (22U)                             
+#define RCC_APB2RSTR_SAI2RST_Msk             (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk          
+#define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)                             
+#define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk        
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)                              
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk            
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)                              
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk            
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)                              
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk           
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)                             
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk             
+#define RCC_AHB1ENR_TSCEN_Pos                (16U)                             
+#define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk             
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)                              
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk           
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)                              
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk           
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)                              
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk           
+#define RCC_AHB2ENR_GPIODEN_Pos              (3U)                              
+#define RCC_AHB2ENR_GPIODEN_Msk              (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk           
+#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)                              
+#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk           
+#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)                              
+#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk           
+#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)                              
+#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk           
+#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)                              
+#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk           
+#define RCC_AHB2ENR_OTGFSEN_Pos              (12U)                             
+#define RCC_AHB2ENR_OTGFSEN_Msk              (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk           
+#define RCC_AHB2ENR_ADCEN_Pos                (13U)                             
+#define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk             
+#define RCC_AHB2ENR_AESEN_Pos                (16U)                             
+#define RCC_AHB2ENR_AESEN_Msk                (0x1U << RCC_AHB2ENR_AESEN_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENR_AESEN                    RCC_AHB2ENR_AESEN_Msk             
+#define RCC_AHB2ENR_RNGEN_Pos                (18U)                             
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_FMCEN_Pos                (0U)                              
+#define RCC_AHB3ENR_FMCEN_Msk                (0x1U << RCC_AHB3ENR_FMCEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk             
+#define RCC_AHB3ENR_QSPIEN_Pos               (8U)                              
+#define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk            
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)                              
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk           
+#define RCC_APB1ENR1_TIM3EN_Pos              (1U)                              
+#define RCC_APB1ENR1_TIM3EN_Msk              (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk           
+#define RCC_APB1ENR1_TIM4EN_Pos              (2U)                              
+#define RCC_APB1ENR1_TIM4EN_Msk              (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk           
+#define RCC_APB1ENR1_TIM5EN_Pos              (3U)                              
+#define RCC_APB1ENR1_TIM5EN_Msk              (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk           
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)                              
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk           
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)                              
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk           
+#define RCC_APB1ENR1_LCDEN_Pos               (9U)                              
+#define RCC_APB1ENR1_LCDEN_Msk               (0x1U << RCC_APB1ENR1_LCDEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LCDEN                   RCC_APB1ENR1_LCDEN_Msk            
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)                             
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk           
+#define RCC_APB1ENR1_SPI2EN_Pos              (14U)                             
+#define RCC_APB1ENR1_SPI2EN_Msk              (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk           
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)                             
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk           
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)                             
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk         
+#define RCC_APB1ENR1_USART3EN_Pos            (18U)                             
+#define RCC_APB1ENR1_USART3EN_Msk            (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk         
+#define RCC_APB1ENR1_UART4EN_Pos             (19U)                             
+#define RCC_APB1ENR1_UART4EN_Msk             (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk          
+#define RCC_APB1ENR1_UART5EN_Pos             (20U)                             
+#define RCC_APB1ENR1_UART5EN_Msk             (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk          
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)                             
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk           
+#define RCC_APB1ENR1_I2C2EN_Pos              (22U)                             
+#define RCC_APB1ENR1_I2C2EN_Msk              (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk           
+#define RCC_APB1ENR1_I2C3EN_Pos              (23U)                             
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk           
+#define RCC_APB1ENR1_CAN1EN_Pos              (25U)                             
+#define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk           
+#define RCC_APB1ENR1_PWREN_Pos               (28U)                             
+#define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk            
+#define RCC_APB1ENR1_DAC1EN_Pos              (29U)                             
+#define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk           
+#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)                             
+#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk          
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)                             
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk         
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)                              
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk        
+#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)                              
+#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk         
+#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)                              
+#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk         
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)                              
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk          
+#define RCC_APB2ENR_FWEN_Pos                 (7U)                              
+#define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk              
+#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)                             
+#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk          
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            
+#define RCC_APB2ENR_TIM8EN_Pos               (13U)                             
+#define RCC_APB2ENR_TIM8EN_Msk               (0x1U << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk            
+#define RCC_APB2ENR_USART1EN_Pos             (14U)                             
+#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)                             
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk           
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)                             
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk           
+#define RCC_APB2ENR_TIM17EN_Pos              (18U)                             
+#define RCC_APB2ENR_TIM17EN_Msk              (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk           
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)                             
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk            
+#define RCC_APB2ENR_SAI2EN_Pos               (22U)                             
+#define RCC_APB2ENR_SAI2EN_Msk               (0x1U << RCC_APB2ENR_SAI2EN_Pos)  /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk            
+#define RCC_APB2ENR_DFSDM1EN_Pos             (24U)                             
+#define RCC_APB2ENR_DFSDM1EN_Msk             (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk          
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)                              
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk        
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)                              
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk        
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)                              
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk       
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)                              
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk       
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)                             
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk         
+#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)                             
+#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)                              
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk       
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)                              
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)                              
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk       
+#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)                              
+#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)                              
+#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk       
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)                              
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)                              
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)                              
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk       
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)                              
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk       
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)                             
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk       
+#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)                             
+#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk         
+#define RCC_AHB2SMENR_AESSMEN_Pos            (16U)                             
+#define RCC_AHB2SMENR_AESSMEN_Msk            (0x1U << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB2SMENR_AESSMEN                RCC_AHB2SMENR_AESSMEN_Msk         
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)                             
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+#define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)                              
+#define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk         
+#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)                              
+#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk        
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)                              
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk       
+#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)                              
+#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk       
+#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)                              
+#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk       
+#define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)                              
+#define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk       
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)                              
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk       
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)                              
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk       
+#define RCC_APB1SMENR1_LCDSMEN_Pos           (9U)                              
+#define RCC_APB1SMENR1_LCDSMEN_Msk           (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR1_LCDSMEN               RCC_APB1SMENR1_LCDSMEN_Msk        
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)                             
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk       
+#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)                             
+#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk       
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)                             
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk       
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)                             
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk     
+#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)                             
+#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk     
+#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)                             
+#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk      
+#define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)                             
+#define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk      
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)                             
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk       
+#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)                             
+#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk       
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)                             
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk       
+#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)                             
+#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk       
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)                             
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk        
+#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)                             
+#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk       
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)                             
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk      
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)                             
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk     
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)                              
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk    
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)                              
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk     
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)                              
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk     
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)                              
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk      
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)                             
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk      
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)                             
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk        
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)                             
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk        
+#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)                             
+#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk        
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)                             
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk      
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)                             
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk       
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)                             
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk       
+#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)                             
+#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk       
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)                             
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk        
+#define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)                             
+#define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk        
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)                             
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk      
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos              (0U)                              
+#define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk           
+#define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos              (2U)                              
+#define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk           
+#define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos              (4U)                              
+#define RCC_CCIPR_USART3SEL_Msk              (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk           
+#define RCC_CCIPR_USART3SEL_0                (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1                (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos               (6U)                              
+#define RCC_CCIPR_UART4SEL_Msk               (0x3U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk            
+#define RCC_CCIPR_UART4SEL_0                 (0x1U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1                 (0x2U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000080 */
+
+#define RCC_CCIPR_UART5SEL_Pos               (8U)                              
+#define RCC_CCIPR_UART5SEL_Msk               (0x3U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000300 */
+#define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk            
+#define RCC_CCIPR_UART5SEL_0                 (0x1U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000100 */
+#define RCC_CCIPR_UART5SEL_1                 (0x2U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000200 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)                             
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk          
+#define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)                             
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk             
+#define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos                (14U)                             
+#define RCC_CCIPR_I2C2SEL_Msk                (0x3U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk             
+#define RCC_CCIPR_I2C2SEL_0                  (0x1U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1                  (0x2U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)                             
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk             
+#define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)                             
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk           
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)                             
+#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk           
+#define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos                (22U)                             
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk             
+#define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */
+
+#define RCC_CCIPR_SAI2SEL_Pos                (24U)                             
+#define RCC_CCIPR_SAI2SEL_Msk                (0x3U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x03000000 */
+#define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk             
+#define RCC_CCIPR_SAI2SEL_0                  (0x1U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x01000000 */
+#define RCC_CCIPR_SAI2SEL_1                  (0x2U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x02000000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)                             
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk            
+#define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos                 (28U)                             
+#define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk              
+#define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)                             
+#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk           
+
+#define RCC_CCIPR_DFSDM1SEL_Pos              (31U)                             
+#define RCC_CCIPR_DFSDM1SEL_Msk              (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
+#define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk           
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                   (0U)                              
+#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                
+#define RCC_BDCR_LSERDY_Pos                  (1U)                              
+#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               
+#define RCC_BDCR_LSEBYP_Pos                  (2U)                              
+#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               
+
+#define RCC_BDCR_LSEDRV_Pos                  (3U)                              
+#define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk               
+#define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                (5U)                              
+#define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk             
+#define RCC_BDCR_LSECSSD_Pos                 (6U)                              
+#define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk              
+
+#define RCC_BDCR_RTCSEL_Pos                  (8U)                              
+#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               
+#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                   (15U)                             
+#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                
+#define RCC_BDCR_BDRST_Pos                   (16U)                             
+#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                
+#define RCC_BDCR_LSCOEN_Pos                  (24U)                             
+#define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk               
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)                             
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk              
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                    (0U)                              
+#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 
+#define RCC_CSR_LSIRDY_Pos                   (1U)                              
+#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                
+
+#define RCC_CSR_MSISRANGE_Pos                (8U)                              
+#define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk             
+#define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos                     (23U)                             
+#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  
+#define RCC_CSR_FWRSTF_Pos                   (24U)                             
+#define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk                
+#define RCC_CSR_OBLRSTF_Pos                  (25U)                             
+#define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk               
+#define RCC_CSR_PINRSTF_Pos                  (26U)                             
+#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               
+#define RCC_CSR_BORRSTF_Pos                  (27U)                             
+#define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk               
+#define RCC_CSR_SFTRSTF_Pos                  (28U)                             
+#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)                                   
+#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk                           
+#define RTC_TR_HT_Pos                  (20U)                                   
+#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk                           
+#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)                                   
+#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk                           
+#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)                                   
+#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          
+#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)                                    
+#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          
+#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)                                    
+#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk                           
+#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)                                    
+#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk                           
+#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)                                   
+#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk                           
+#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)                                   
+#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk                           
+#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)                                   
+#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          
+#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)                                   
+#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk                           
+#define RTC_DR_MU_Pos                  (8U)                                    
+#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk                           
+#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)                                    
+#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk                           
+#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)                                    
+#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk                           
+#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)                                   
+#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         
+#define RTC_CR_COE_Pos                 (23U)                                   
+#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk                          
+#define RTC_CR_OSEL_Pos                (21U)                                   
+#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         
+#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)                                   
+#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk                          
+#define RTC_CR_COSEL_Pos               (19U)                                   
+#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos               (17U)                                   
+#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        
+#define RTC_CR_ADD1H_Pos               (16U)                                   
+#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        
+#define RTC_CR_TSIE_Pos                (15U)                                   
+#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         
+#define RTC_CR_WUTIE_Pos               (14U)                                   
+#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        
+#define RTC_CR_ALRBIE_Pos              (13U)                                   
+#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       
+#define RTC_CR_ALRAIE_Pos              (12U)                                   
+#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       
+#define RTC_CR_TSE_Pos                 (11U)                                   
+#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          
+#define RTC_CR_WUTE_Pos                (10U)                                   
+#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         
+#define RTC_CR_ALRBE_Pos               (9U)                                    
+#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        
+#define RTC_CR_ALRAE_Pos               (8U)                                    
+#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        
+#define RTC_CR_FMT_Pos                 (6U)                                    
+#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          
+#define RTC_CR_BYPSHAD_Pos             (5U)                                    
+#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      
+#define RTC_CR_REFCKON_Pos             (4U)                                    
+#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      
+#define RTC_CR_TSEDGE_Pos              (3U)                                    
+#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       
+#define RTC_CR_WUCKSEL_Pos             (0U)                                    
+#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      
+#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)                                   
+#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        
+#define RTC_ISR_RECALPF_Pos            (16U)                                   
+#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     
+#define RTC_ISR_TAMP3F_Pos             (15U)                                   
+#define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      
+#define RTC_ISR_TAMP2F_Pos             (14U)                                   
+#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      
+#define RTC_ISR_TAMP1F_Pos             (13U)                                   
+#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      
+#define RTC_ISR_TSOVF_Pos              (12U)                                   
+#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       
+#define RTC_ISR_TSF_Pos                (11U)                                   
+#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         
+#define RTC_ISR_WUTF_Pos               (10U)                                   
+#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        
+#define RTC_ISR_ALRBF_Pos              (9U)                                    
+#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       
+#define RTC_ISR_ALRAF_Pos              (8U)                                    
+#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       
+#define RTC_ISR_INIT_Pos               (7U)                                    
+#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        
+#define RTC_ISR_INITF_Pos              (6U)                                    
+#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       
+#define RTC_ISR_RSF_Pos                (5U)                                    
+#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         
+#define RTC_ISR_INITS_Pos              (4U)                                    
+#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       
+#define RTC_ISR_SHPF_Pos               (3U)                                    
+#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        
+#define RTC_ISR_WUTWF_Pos              (2U)                                    
+#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       
+#define RTC_ISR_ALRBWF_Pos             (1U)                                    
+#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      
+#define RTC_ISR_ALRAWF_Pos             (0U)                                    
+#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
+#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   
+#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)                                    
+#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     
+#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    
+#define RTC_ALRMAR_DT_Pos              (28U)                                   
+#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       
+#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)                                   
+#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       
+#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     
+#define RTC_ALRMAR_PM_Pos              (22U)                                   
+#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       
+#define RTC_ALRMAR_HT_Pos              (20U)                                   
+#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       
+#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)                                   
+#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       
+#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     
+#define RTC_ALRMAR_MNT_Pos             (12U)                                   
+#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      
+#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)                                    
+#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      
+#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     
+#define RTC_ALRMAR_ST_Pos              (4U)                                    
+#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       
+#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)                                    
+#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       
+#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     
+#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    
+#define RTC_ALRMBR_DT_Pos              (28U)                                   
+#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       
+#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)                                   
+#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       
+#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     
+#define RTC_ALRMBR_PM_Pos              (22U)                                   
+#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       
+#define RTC_ALRMBR_HT_Pos              (20U)                                   
+#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       
+#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)                                   
+#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       
+#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     
+#define RTC_ALRMBR_MNT_Pos             (12U)                                   
+#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      
+#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)                                    
+#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      
+#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     
+#define RTC_ALRMBR_ST_Pos              (4U)                                    
+#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       
+#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)                                    
+#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       
+#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)                                    
+#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)                                    
+#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    
+#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
+#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)                                   
+#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         
+#define RTC_TSTR_HT_Pos                (20U)                                   
+#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         
+#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)                                   
+#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         
+#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)                                   
+#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        
+#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)                                    
+#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        
+#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)                                    
+#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         
+#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)                                    
+#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         
+#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)                                   
+#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        
+#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)                                   
+#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         
+#define RTC_TSDR_MU_Pos                (8U)                                    
+#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         
+#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)                                    
+#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         
+#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)                                    
+#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         
+#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)                                    
+#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)                                   
+#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       
+#define RTC_CALR_CALW8_Pos             (14U)                                   
+#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      
+#define RTC_CALR_CALW16_Pos            (13U)                                   
+#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     
+#define RTC_CALR_CALM_Pos              (0U)                                    
+#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       
+#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)                                   
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)                                   
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)                                   
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  
+#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)                                    
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)                                    
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
+#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)                                    
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
+#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
+
+/********************  Bits definition for RTC_0R register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)                                    
+#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)                                    
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk                           
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)                                    
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk                           
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)                                    
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk                           
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)                                    
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk                           
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)                                    
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk                           
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)                                    
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk                           
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)                                    
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk                           
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)                                    
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk                           
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)                                    
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk                           
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)                                    
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk                           
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)                                    
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk                          
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)                                    
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk                          
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)                                    
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk                          
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)                                    
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk                          
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)                                    
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk                          
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)                                    
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk                          
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)                                    
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk                          
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)                                    
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk                          
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)                                    
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk                          
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)                                    
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk                          
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)                                    
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk                          
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)                                    
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk                          
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)                                    
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk                          
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)                                    
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk                          
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)                                    
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk                          
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)                                    
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk                          
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)                                    
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk                          
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)                                    
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk                          
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)                                    
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk                          
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)                                    
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk                          
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)                                    
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk                          
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)                                    
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk                          
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       32U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN_Pos            (0U)                                       
+#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
+#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos             (1U)                                       
+#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
+#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos             (2U)                                       
+#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
+#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
+#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
+#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos             (5U)                                       
+#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
+#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
+#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos          (7U)                                       
+#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
+#define LCD_CR_BUFEN_Pos            (8U)                                       
+#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
+#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD_Pos              (0U)                                       
+#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
+#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos           (1U)                                       
+#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
+#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos           (3U)                                       
+#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
+#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos             (4U)                                       
+#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
+#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Pulse ON Duration) */
+#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
+#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
+#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos            (7U)                                       
+#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
+#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos              (10U)                                      
+#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
+#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
+#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
+#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos          (13U)                                      
+#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos           (16U)                                      
+#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
+#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos             (18U)                                      
+#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
+#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos              (22U)                                      
+#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
+#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS_Pos              (0U)                                       
+#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
+#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos              (1U)                                       
+#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
+#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos              (2U)                                       
+#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
+#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos              (3U)                                       
+#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
+#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos              (4U)                                       
+#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
+#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos            (5U)                                       
+#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
+#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC_Pos            (1U)                                       
+#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
+#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos            (3U)                                       
+#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
+#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos    (0U)                                       
+#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos         (0U)                                   
+#define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos          (0U)                                   
+#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */
+#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
+#define SDMMC_CLKCR_CLKEN_Pos           (8U)                                   
+#define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */
+#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
+#define SDMMC_CLKCR_PWRSAV_Pos          (9U)                                   
+#define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */
+#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_BYPASS_Pos          (10U)                                  
+#define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */
+#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos          (11U)                                  
+#define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */
+#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)                                  
+#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */
+#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)                                  
+#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos            (0U)                                   
+#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos          (0U)                                   
+#define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
+
+#define SDMMC_CMD_WAITRESP_Pos          (6U)                                   
+#define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */
+#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000080 */
+
+#define SDMMC_CMD_WAITINT_Pos           (8U)                                   
+#define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */
+#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos          (9U)                                   
+#define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos            (10U)                                  
+#define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */
+#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)                                  
+#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */
+#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)                                   
+#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)                                   
+#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)                                   
+#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)                                   
+#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)                                   
+#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos       (0U)                                   
+#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos       (0U)                                   
+#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos            (0U)                                   
+#define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
+#define SDMMC_DCTRL_DTDIR_Pos           (1U)                                   
+#define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos          (2U)                                   
+#define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
+#define SDMMC_DCTRL_DMAEN_Pos           (3U)                                   
+#define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */
+#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)                                   
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos         (8U)                                   
+#define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
+#define SDMMC_DCTRL_RWSTOP_Pos          (9U)                                   
+#define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
+#define SDMMC_DCTRL_RWMOD_Pos           (10U)                                  
+#define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
+#define SDMMC_DCTRL_SDIOEN_Pos          (11U)                                  
+#define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)                                   
+#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos          (0U)                                   
+#define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos          (1U)                                   
+#define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos          (2U)                                   
+#define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos          (3U)                                   
+#define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos          (4U)                                   
+#define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos           (5U)                                   
+#define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos           (6U)                                   
+#define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos           (7U)                                   
+#define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos           (8U)                                   
+#define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_STBITERR_Pos          (9U)                                   
+#define SDMMC_STA_STBITERR_Msk          (0x1U << SDMMC_STA_STBITERR_Pos)       /*!< 0x00000200 */
+#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDMMC_STA_DBCKEND_Pos           (10U)                                  
+#define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_CMDACT_Pos            (11U)                                  
+#define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
+#define SDMMC_STA_TXACT_Pos             (12U)                                  
+#define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */
+#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
+#define SDMMC_STA_RXACT_Pos             (13U)                                  
+#define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */
+#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
+#define SDMMC_STA_TXFIFOHE_Pos          (14U)                                  
+#define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos          (15U)                                  
+#define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos           (16U)                                  
+#define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos           (17U)                                  
+#define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos           (18U)                                  
+#define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos           (19U)                                  
+#define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
+#define SDMMC_STA_TXDAVL_Pos            (20U)                                  
+#define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
+#define SDMMC_STA_RXDAVL_Pos            (21U)                                  
+#define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */
+#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
+#define SDMMC_STA_SDIOIT_Pos            (22U)                                  
+#define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos         (0U)                                   
+#define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos         (1U)                                   
+#define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)                                   
+#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)                                   
+#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos         (4U)                                   
+#define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos          (5U)                                   
+#define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos          (6U)                                   
+#define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos          (7U)                                   
+#define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos          (8U)                                   
+#define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_STBITERRC_Pos         (9U)                                   
+#define SDMMC_ICR_STBITERRC_Msk         (0x1U << SDMMC_ICR_STBITERRC_Pos)      /*!< 0x00000200 */
+#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos          (10U)                                  
+#define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos           (22U)                                  
+#define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)                                   
+#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)                                   
+#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)                                   
+#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)                                   
+#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)                                   
+#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos        (5U)                                   
+#define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos        (6U)                                   
+#define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos        (7U)                                   
+#define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos        (8U)                                   
+#define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DBCKENDIE_Pos        (10U)                                  
+#define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_CMDACTIE_Pos         (11U)                                  
+#define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
+#define SDMMC_MASK_TXACTIE_Pos          (12U)                                  
+#define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */
+#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
+#define SDMMC_MASK_RXACTIE_Pos          (13U)                                  
+#define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */
+#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
+#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)                                  
+#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)                                  
+#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)                                  
+#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */
+#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)                                  
+#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)                                  
+#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)                                  
+#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */
+#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_TXDAVLIE_Pos         (20U)                                  
+#define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */
+#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
+#define SDMMC_MASK_RXDAVLIE_Pos         (21U)                                  
+#define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */
+#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos         (22U)                                  
+#define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)                                   
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos         (0U)                                   
+#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos         (0U)                                          
+#define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */
+#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos         (1U)                                          
+#define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */
+#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos         (2U)                                          
+#define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */
+#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos           (3U)                                          
+#define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */
+#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */
+#define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */
+#define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos          (6U)                                          
+#define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */
+#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos     (7U)                                          
+#define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos          (8U)                                          
+#define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */
+#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos          (9U)                                          
+#define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */
+#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos       (10U)                                         
+#define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */
+#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos         (11U)                                         
+#define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */
+#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos      (12U)                                         
+#define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos        (13U)                                         
+#define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */
+#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos       (14U)                                         
+#define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos     (15U)                                         
+#define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos      (0U)                                          
+#define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos      (1U)                                          
+#define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos         (2U)                                          
+#define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */
+#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos         (3U)                                          
+#define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */
+#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos          (4U)                                          
+#define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */
+#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos        (5U)                                          
+#define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */
+#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos       (6U)                                          
+#define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos        (7U)                                          
+#define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */
+#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos           (8U)                                          
+#define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */
+#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */
+#define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */
+#define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */
+#define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos        (12U)                                         
+#define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */
+#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos       (13U)                                         
+#define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */
+#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos       (14U)                                         
+#define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */
+#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos          (0U)                                          
+#define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */
+#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos           (1U)                                          
+#define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */
+#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos        (2U)                                          
+#define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */
+#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
+#define SPI_SR_UDR_Pos           (3U)                                          
+#define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */
+#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos        (4U)                                          
+#define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */
+#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos          (5U)                                          
+#define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */
+#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
+#define SPI_SR_OVR_Pos           (6U)                                          
+#define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */
+#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
+#define SPI_SR_BSY_Pos           (7U)                                          
+#define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */
+#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
+#define SPI_SR_FRE_Pos           (8U)                                          
+#define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */
+#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos         (9U)                                          
+#define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */
+#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos         (11U)                                         
+#define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */
+#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos            (0U)                                          
+#define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */
+#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos    (0U)                                          
+#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos     (0U)                                          
+#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos     (0U)                                          
+#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos              (0U)                                    
+#define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */
+#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos           (1U)                                    
+#define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos           (2U)                                    
+#define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos            (3U)                                    
+#define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos          (4U)                                    
+#define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
+#define QUADSPI_CR_FTHRES_Pos          (8U)                                    
+#define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos            (16U)                                   
+#define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos            (17U)                                   
+#define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos            (18U)                                   
+#define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos            (19U)                                   
+#define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos            (20U)                                   
+#define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos            (22U)                                   
+#define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos             (23U)                                   
+#define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos       (24U)                                   
+#define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos         (0U)                                    
+#define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos           (8U)                                    
+#define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos          (16U)                                   
+#define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos             (0U)                                    
+#define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos             (1U)                                    
+#define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos             (2U)                                    
+#define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos             (3U)                                    
+#define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos             (4U)                                    
+#define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos            (5U)                                    
+#define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos          (8U)                                    
+#define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos           (0U)                                    
+#define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos           (1U)                                    
+#define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos           (3U)                                    
+#define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos           (4U)                                    
+#define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos             (0U)                                    
+#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)                                    
+#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos          (8U)                                    
+#define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos         (10U)                                   
+#define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos         (12U)                                   
+#define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos         (14U)                                   
+#define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos         (16U)                                   
+#define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos           (18U)                                   
+#define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos          (24U)                                   
+#define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos          (26U)                                   
+#define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos           (28U)                                   
+#define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DDRM_Pos           (31U)                                   
+#define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos         (0U)                                    
+#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos      (0U)                                    
+#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos            (0U)                                    
+#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos         (0U)                                    
+#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos        (0U)                                    
+#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos       (0U)                                    
+#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)                                    
+#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)                                   
+#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos)    /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */
+
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos          (0U)                                   
+#define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)                                   
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)                                  
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)                                  
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)                                  
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)                                  
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)                                  
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)                                  
+#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos)    /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)                                  
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7U << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7U << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7U << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7U << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7U << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7U << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7U << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000700 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7U << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x00007000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7U << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x00000007 */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7U << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x00000070 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7U << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7U << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600U)                      /*!<PG[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000U)                      /*!<PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006U)                      /*!<PG[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060U)                      /*!<PG[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600U)                      /*!<PG[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000U)                      /*!<PG[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)                                   
+#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)                                   
+#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos            (0U)                                   
+#define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos            (1U)                                   
+#define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)                                   
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)                                   
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos            (8U)                                   
+#define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos           (0U)                                   
+#define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos           (1U)                                   
+#define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos           (2U)                                   
+#define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos           (3U)                                   
+#define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos           (4U)                                   
+#define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos           (5U)                                   
+#define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos           (6U)                                   
+#define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos           (7U)                                   
+#define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos           (8U)                                   
+#define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos           (9U)                                   
+#define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos          (10U)                                  
+#define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos          (11U)                                  
+#define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos          (12U)                                  
+#define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos          (13U)                                  
+#define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos          (14U)                                  
+#define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos          (15U)                                  
+#define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
+#define SYSCFG_SWPR_PAGE16_Pos          (16U)                                  
+#define SYSCFG_SWPR_PAGE16_Msk          (0x1U << SYSCFG_SWPR_PAGE16_Pos)       /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/
+#define SYSCFG_SWPR_PAGE17_Pos          (17U)                                  
+#define SYSCFG_SWPR_PAGE17_Msk          (0x1U << SYSCFG_SWPR_PAGE17_Pos)       /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/
+#define SYSCFG_SWPR_PAGE18_Pos          (18U)                                  
+#define SYSCFG_SWPR_PAGE18_Msk          (0x1U << SYSCFG_SWPR_PAGE18_Pos)       /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/
+#define SYSCFG_SWPR_PAGE19_Pos          (19U)                                  
+#define SYSCFG_SWPR_PAGE19_Msk          (0x1U << SYSCFG_SWPR_PAGE19_Pos)       /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/
+#define SYSCFG_SWPR_PAGE20_Pos          (20U)                                  
+#define SYSCFG_SWPR_PAGE20_Msk          (0x1U << SYSCFG_SWPR_PAGE20_Pos)       /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/
+#define SYSCFG_SWPR_PAGE21_Pos          (21U)                                  
+#define SYSCFG_SWPR_PAGE21_Msk          (0x1U << SYSCFG_SWPR_PAGE21_Pos)       /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/
+#define SYSCFG_SWPR_PAGE22_Pos          (22U)                                  
+#define SYSCFG_SWPR_PAGE22_Msk          (0x1U << SYSCFG_SWPR_PAGE22_Pos)       /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/
+#define SYSCFG_SWPR_PAGE23_Pos          (23U)                                  
+#define SYSCFG_SWPR_PAGE23_Msk          (0x1U << SYSCFG_SWPR_PAGE23_Pos)       /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/
+#define SYSCFG_SWPR_PAGE24_Pos          (24U)                                  
+#define SYSCFG_SWPR_PAGE24_Msk          (0x1U << SYSCFG_SWPR_PAGE24_Pos)       /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/
+#define SYSCFG_SWPR_PAGE25_Pos          (25U)                                  
+#define SYSCFG_SWPR_PAGE25_Msk          (0x1U << SYSCFG_SWPR_PAGE25_Pos)       /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/
+#define SYSCFG_SWPR_PAGE26_Pos          (26U)                                  
+#define SYSCFG_SWPR_PAGE26_Msk          (0x1U << SYSCFG_SWPR_PAGE26_Pos)       /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/
+#define SYSCFG_SWPR_PAGE27_Pos          (27U)                                  
+#define SYSCFG_SWPR_PAGE27_Msk          (0x1U << SYSCFG_SWPR_PAGE27_Pos)       /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/
+#define SYSCFG_SWPR_PAGE28_Pos          (28U)                                  
+#define SYSCFG_SWPR_PAGE28_Msk          (0x1U << SYSCFG_SWPR_PAGE28_Pos)       /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/
+#define SYSCFG_SWPR_PAGE29_Pos          (29U)                                  
+#define SYSCFG_SWPR_PAGE29_Msk          (0x1U << SYSCFG_SWPR_PAGE29_Pos)       /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/
+#define SYSCFG_SWPR_PAGE30_Pos          (30U)                                  
+#define SYSCFG_SWPR_PAGE30_Msk          (0x1U << SYSCFG_SWPR_PAGE30_Pos)       /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/
+#define SYSCFG_SWPR_PAGE31_Pos          (31U)                                  
+#define SYSCFG_SWPR_PAGE31_Msk          (0x1U << SYSCFG_SWPR_PAGE31_Pos)       /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos              (0U)                                   
+#define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)                                        
+#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM1_OR1 register  *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)                                    
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
+#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM1_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM1_OR2 register  *******************/
+#define TIM1_OR2_BKINE_Pos             (0U)                                    
+#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKDF1BK0E_Pos         (8U)                                    
+#define TIM1_OR2_BKDF1BK0E_Msk         (0x1U << TIM1_OR2_BKDF1BK0E_Pos)        /*!< 0x00000100 */
+#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM1_OR2_BKINP_Pos             (9U)                                    
+#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM1_OR3 register  *******************/
+#define TIM1_OR3_BK2INE_Pos            (0U)                                    
+#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)                                    
+#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1U << TIM1_OR3_BK2DF1BK1E_Pos)       /*!< 0x00000100 */
+#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */
+#define TIM1_OR3_BK2INP_Pos            (9U)                                    
+#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM8_OR1 register  *******************/
+#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)                                    
+#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000003 */
+#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
+#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000001 */
+#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
+#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM8_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM8_OR1_TI1_RMP_Msk           (0x1U << TIM8_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM8_OR2 register  *******************/
+#define TIM8_OR2_BKINE_Pos             (0U)                                    
+#define TIM8_OR2_BKINE_Msk             (0x1U << TIM8_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM8_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM8_OR2_BKCMP1E_Msk           (0x1U << TIM8_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM8_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM8_OR2_BKCMP2E_Msk           (0x1U << TIM8_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM8_OR2_BKDF1BK2E_Pos         (8U)                                    
+#define TIM8_OR2_BKDF1BK2E_Msk         (0x1U << TIM8_OR2_BKDF1BK2E_Pos)        /*!< 0x00000100 */
+#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM8_OR2_BKINP_Pos             (9U)                                    
+#define TIM8_OR2_BKINP_Msk             (0x1U << TIM8_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM8_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM8_OR2_BKCMP1P_Msk           (0x1U << TIM8_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM8_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM8_OR2_BKCMP2P_Msk           (0x1U << TIM8_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM8_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM8_OR2_ETRSEL_Msk            (0x7U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
+#define TIM8_OR2_ETRSEL_0              (0x1U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM8_OR2_ETRSEL_1              (0x2U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM8_OR2_ETRSEL_2              (0x4U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM8_OR3 register  *******************/
+#define TIM8_OR3_BK2INE_Pos            (0U)                                    
+#define TIM8_OR3_BK2INE_Msk            (0x1U << TIM8_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM8_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM8_OR3_BK2CMP1E_Msk          (0x1U << TIM8_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM8_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM8_OR3_BK2CMP2E_Msk          (0x1U << TIM8_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)                                    
+#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1U << TIM8_OR3_BK2DF1BK3E_Pos)       /*!< 0x00000100 */
+#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */
+#define TIM8_OR3_BK2INP_Pos            (9U)                                    
+#define TIM8_OR3_BK2INP_Msk            (0x1U << TIM8_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM8_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM8_OR3_BK2CMP1P_Msk          (0x1U << TIM8_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM8_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM8_OR3_BK2CMP2P_Msk          (0x1U << TIM8_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_OR1 register  *******************/
+#define TIM2_OR1_ITR1_RMP_Pos     (0U)                                         
+#define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos     (1U)                                         
+#define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos      (2U)                                         
+#define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM2_OR2 register  *******************/
+#define TIM2_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM3_OR1 register  *******************/
+#define TIM3_OR1_TI1_RMP_Pos      (0U)                                         
+#define TIM3_OR1_TI1_RMP_Msk      (0x3U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000003 */
+#define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
+#define TIM3_OR1_TI1_RMP_0        (0x1U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000001 */
+#define TIM3_OR1_TI1_RMP_1        (0x2U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM3_OR2 register  *******************/
+#define TIM3_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM3_OR2_ETRSEL_Msk       (0x7U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
+#define TIM3_OR2_ETRSEL_0         (0x1U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM3_OR2_ETRSEL_1         (0x2U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM3_OR2_ETRSEL_2         (0x4U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM15_OR1 register  ******************/
+#define TIM15_OR1_TI1_RMP_Pos           (0U)                                   
+#define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos      (1U)                                   
+#define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM15_OR2 register  ******************/
+#define TIM15_OR2_BKINE_Pos             (0U)                                   
+#define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */
+#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos           (1U)                                   
+#define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos           (2U)                                   
+#define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKDF1BK0E_Pos         (8U)                                   
+#define TIM15_OR2_BKDF1BK0E_Msk         (0x1U << TIM15_OR2_BKDF1BK0E_Pos)      /*!< 0x00000100 */
+#define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM15_OR2_BKINP_Pos             (9U)                                   
+#define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */
+#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos           (10U)                                  
+#define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos           (11U)                                  
+#define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_OR1 register  ******************/
+#define TIM16_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM16_OR1_TI1_RMP_Msk      (0x3U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM16_OR2 register  ******************/
+#define TIM16_OR2_BKINE_Pos        (0U)                                        
+#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKDF1BK1E_Pos    (8U)                                        
+#define TIM16_OR2_BKDF1BK1E_Msk    (0x1U << TIM16_OR2_BKDF1BK1E_Pos)           /*!< 0x00000100 */
+#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */
+#define TIM16_OR2_BKINP_Pos        (9U)                                        
+#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_OR1 register  ******************/
+#define TIM17_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM17_OR1_TI1_RMP_Msk      (0x3U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
+#define TIM17_OR1_TI1_RMP_0        (0x1U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM17_OR1_TI1_RMP_1        (0x2U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM17_OR2 register  ******************/
+#define TIM17_OR2_BKINE_Pos        (0U)                                        
+#define TIM17_OR2_BKINE_Msk        (0x1U << TIM17_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM17_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM17_OR2_BKCMP1E_Msk      (0x1U << TIM17_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM17_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM17_OR2_BKCMP2E_Msk      (0x1U << TIM17_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM17_OR2_BKDF1BK2E_Pos    (8U)                                        
+#define TIM17_OR2_BKDF1BK2E_Msk    (0x1U << TIM17_OR2_BKDF1BK2E_Pos)           /*!< 0x00000100 */
+#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM17_OR2_BKINP_Pos        (9U)                                        
+#define TIM17_OR2_BKINP_Msk        (0x1U << TIM17_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM17_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM17_OR2_BKCMP1P_Msk      (0x1U << TIM17_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM17_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM17_OR2_BKCMP2P_Msk      (0x1U << TIM17_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)                                       
+#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)                                       
+#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
+#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)                                       
+#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)                                       
+#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)                                       
+#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
+#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
+#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
+#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)                                       
+#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
+#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
+#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
+#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
+#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
+#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)                                       
+#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
+#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
+#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
+#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
+#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
+#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
+#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)                                      
+#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)                                       
+#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
+#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
+#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)                                       
+#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)                                       
+#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)                                       
+#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  ********************/
+#define LPTIM_OR_OR_Pos             (0U)                                       
+#define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */
+#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
+#define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos            (0U)                                        
+#define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos       (2U)                                        
+#define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos        (4U)                                        
+#define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos        (7U)                                        
+#define COMP_CSR_INPSEL_Msk        (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+
+#define COMP_CSR_WINMODE_Pos       (9U)                                        
+#define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */
+#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_POLARITY_Pos      (15U)                                       
+#define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos          (16U)                                       
+#define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */
+#define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos      (18U)                                       
+#define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos         (22U)                                       
+#define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos        (23U)                                       
+#define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_VALUE_Pos         (30U)                                       
+#define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos          (31U)                                       
+#define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)                                  
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos             (1U)                                  
+#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos            (2U)                                  
+#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (4U)                                  
+#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos              (8U)                                  
+#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos              (10U)                                 
+#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos              (12U)                                 
+#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos             (13U)                                 
+#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos           (14U)                                 
+#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos             (15U)                                 
+#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos              (12U)                                
+#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)                                
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP2_CSR_OPALPM_Msk             (0x1U << OPAMP2_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */
+
+#define OPAMP2_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP2_CSR_OPAMODE_Msk            (0x3U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */
+#define OPAMP2_CSR_OPAMODE_0              (0x1U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP2_CSR_OPAMODE_1              (0x2U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP2_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP2_CSR_PGAGAIN_Msk            (0x3U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGAGAIN_0              (0x1U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP2_CSR_PGAGAIN_1              (0x2U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP2_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP2_CSR_VPSEL_Msk              (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_CALON_Pos              (12U)                                
+#define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP2_CSR_CALSEL_Msk             (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)                                  
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)                                  
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_LPOTR register  ****************/
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
+#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
+#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
+#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
+#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos       (7U)                                          
+#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos       (23U)                                         
+#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)                                          
+#define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)                                          
+#define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)                                          
+#define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)                                          
+#define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)                                          
+#define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)                                          
+#define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)                                         
+#define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)                                          
+#define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)                                          
+#define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)                                          
+#define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)                                          
+#define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)                                          
+#define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)                                          
+#define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)                                          
+#define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)                                          
+#define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)                                          
+#define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)                                          
+#define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)                                          
+#define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)                                         
+#define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)                                          
+#define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)                                          
+#define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)                                          
+#define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)                                          
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)                                          
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)                                          
+#define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)                                          
+#define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_SRIE_Pos       (8U)                                          
+#define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_TCIE_Pos       (7U)                                          
+#define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_TIE_Pos        (6U)                                          
+#define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_RIE_Pos        (5U)                                          
+#define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)                                          
+#define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)                                          
+#define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)                                          
+#define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_TXBEIE_Pos     (1U)                                          
+#define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBFIE_Pos     (0U)                                          
+#define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)                                          
+#define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1_Pos    (0U)                                          
+#define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */
+#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)                                          
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)                                          
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)                                          
+#define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)                                          
+#define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)                                           
+#define VREFBUF_CSR_ENVR_Msk    (0x1U << VREFBUF_CSR_ENVR_Pos)                 /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)                                           
+#define VREFBUF_CSR_HIZ_Msk     (0x1U << VREFBUF_CSR_HIZ_Pos)                  /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
+#define VREFBUF_CSR_VRS_Pos     (2U)                                           
+#define VREFBUF_CSR_VRS_Msk     (0x1U << VREFBUF_CSR_VRS_Pos)                  /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRR_Pos     (3U)                                           
+#define VREFBUF_CSR_VRR_Msk     (0x1U << VREFBUF_CSR_VRR_Pos)                  /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos    (0U)                                           
+#define VREFBUF_CCR_TRIM_Msk    (0x3FU << VREFBUF_CCR_TRIM_Pos)                /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)                            
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk        
+
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)                            
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk        
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)                           
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)                           
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)                           
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)                           
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)                           
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)                            
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)                           
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)                           
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)                           
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)                           
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)                           
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)                          
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)                          
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)                          
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)                          
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)                          
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)                          
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)                         
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
+#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)                         
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)                         
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                             
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                         
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)                          
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)                         
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                       (0U)                          
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                        (16U)                         
+#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)                          
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)                          
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)                          
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)                          
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)                         
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)                         
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)                         
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)                         
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)                         
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)                          
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
+#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+
+/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
+#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)                         
+#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
+#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */ 
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)                         
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */ 
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)                         
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ 
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)                         
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */ 
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)                         
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */ 
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)                         
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */ 
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           (16U)                         
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ 
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)                         
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */ 
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)                         
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */ 
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)                         
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */ 
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)                          
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */ 
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)                          
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */ 
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)                          
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)                          
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)                          
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)                          
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */
+
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
+#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
+#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
+#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
+#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+                                                                             
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+                                                                             
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+                                                                              
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+                                                                              
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                                                              
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+                                                                              
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+                                                                               
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+                                                                               
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
+#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
+#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
+#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
+#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
+#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                                ((INSTANCE) == DFSDM1_Filter1) || \
+                                                ((INSTANCE) == DFSDM1_Filter2) || \
+                                                ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/******************************* HCD Instances *******************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/******************************* PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                                       ((INSTANCE) == SAI1_Block_B) || \
+                                       ((INSTANCE) == SAI2_Block_A) || \
+                                       ((INSTANCE) == SAI2_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
+                                               ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16)   || \
+                                            ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16)  || \
+                                               ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM3)    || \
+                                                    ((INSTANCE) == TIM4)    || \
+                                                    ((INSTANCE) == TIM5)    || \
+                                                    ((INSTANCE) == TIM8)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16)   || \
+                                                    ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16)  || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2)  || \
+                                                      ((INSTANCE) == TIM3)  || \
+                                                      ((INSTANCE) == TIM4)  || \
+                                                      ((INSTANCE) == TIM5)  || \
+                                                      ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                         ((INSTANCE) == TIM2)   || \
+                                                         ((INSTANCE) == TIM3)   || \
+                                                         ((INSTANCE) == TIM4)   || \
+                                                         ((INSTANCE) == TIM5))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2)  || \
+                                             ((INSTANCE) == TIM3)  || \
+                                             ((INSTANCE) == TIM8))
+      
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4) || \
+                                                       ((INSTANCE) == TIM5) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15) || \
+                                            ((INSTANCE) == TIM16) || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                                  ((INSTANCE) == TIM8))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == UART4)  || \
+                                                 ((INSTANCE) == UART5)  || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3) || \
+                                          ((INSTANCE) == UART4)  || \
+                                          ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn                      ADC1_2_IRQn
+#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn
+#define TIM8_IRQn                      TIM8_UP_IRQn
+#define HASH_RNG_IRQn                  RNG_IRQn
+#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn
+#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn
+#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn
+#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler                ADC1_2_IRQHandler
+#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM8_IRQHandler                TIM8_UP_IRQHandler
+#define HASH_RNG_IRQHandler            RNG_IRQHandler
+#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler
+#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler
+#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler
+#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L486xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h
new file mode 100755
index 0000000..4f666df
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h
@@ -0,0 +1,248 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  #define STM32L486xx         /*!< STM32L486xx Devices */
+  /* #define STM32L496xx */   /*!< STM32L496xx Devices */
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.3.1
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
+#elif defined(STM32L4R5xx)
+  #include "stm32l4r5xx.h"
+#elif defined(STM32L4R9xx)
+  #include "stm32l4r9xx.h"
+#elif defined(STM32L4S5xx)
+  #include "stm32l4s5xx.h"
+#elif defined(STM32L4S9xx)
+  #include "stm32l4s9xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/system_stm32l4xx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/system_stm32l4xx.h
new file mode 100755
index 0000000..3f229fa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/system_stm32l4xx.h
@@ -0,0 +1,127 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16];     /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h
new file mode 100755
index 0000000..ece5f16
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c
new file mode 100755
index 0000000..9fc5e1f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c
@@ -0,0 +1,204 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+int adc_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
+    MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // The ADC initialization is done once
+    if (adc_inited == 0) {
+        adc_inited = 1;
+
+        // Enable ADC clock
+        __HAL_RCC_ADC_CLK_ENABLE();
+        __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK);
+
+        obj->handle.State = HAL_ADC_STATE_RESET;
+        // Configure ADC
+        obj->handle.Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV2;          // Asynchronous clock mode, input ADC clock
+        obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
+        obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+        obj->handle.Init.ScanConvMode          = DISABLE;                       // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
+        obj->handle.Init.EOCSelection          = ADC_EOC_SINGLE_CONV;           // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
+        obj->handle.Init.LowPowerAutoWait      = DISABLE;
+        obj->handle.Init.ContinuousConvMode    = DISABLE;                       // Continuous mode disabled to have only 1 conversion at each conversion trig
+        obj->handle.Init.NbrOfConversion       = 1;                             // Parameter discarded because sequencer is disabled
+        obj->handle.Init.DiscontinuousConvMode = DISABLE;                       // Parameter discarded because sequencer is disabled
+        obj->handle.Init.NbrOfDiscConversion   = 1;                             // Parameter discarded because sequencer is disabled
+        obj->handle.Init.ExternalTrigConv      = ADC_SOFTWARE_START;            // Software start to trig the 1st conversion manually, without external event
+        obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+        obj->handle.Init.DMAContinuousRequests = DISABLE;
+        obj->handle.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;      // DR register is overwritten with the last conversion result in case of overrun
+        obj->handle.Init.OversamplingMode      = DISABLE;                       // No oversampling
+
+        if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+            error("Cannot initialize ADC\n");
+        }
+
+        // Calibrate ADC
+        HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
+    }
+}
+
+static inline uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    // Configure ADC channel
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_VREFINT;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        case 16:
+            sConfig.Channel = ADC_CHANNEL_16;
+            break;
+        case 17:
+            sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            break;
+        case 18:
+            sConfig.Channel = ADC_CHANNEL_VBAT;
+            break;
+        default:
+            return 0;
+    }
+
+    sConfig.Rank         = ADC_REGULAR_RANK_1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
+    sConfig.SingleDiff   = ADC_SINGLE_ENDED;
+    sConfig.OffsetNumber = ADC_OFFSET_NONE;
+    sConfig.Offset       = 0;
+
+    HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+    HAL_ADC_Start(&obj->handle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+        return (HAL_ADC_GetValue(&obj->handle));
+    } else {
+        return 0;
+    }
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    uint16_t value = adc_read(obj);
+    // 12-bit to 16-bit conversion
+    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
+    return value;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = adc_read(obj);
+    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c
new file mode 100755
index 0000000..92386ab
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c
@@ -0,0 +1,120 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+// These variables are used for the "free" function
+static int channel1_used = 0;
+static int channel2_used = 0;
+
+void analogout_init(dac_t *obj, PinName pin) {
+    DAC_ChannelConfTypeDef sConfig = {0};
+
+    // Get the peripheral name from the pin and assign it to the object
+    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+    MBED_ASSERT(obj->dac != (DACName)NC);
+
+    // Get the pin function and assign the used channel to the object
+    uint32_t function = pinmap_function(pin, PinMap_DAC);
+    MBED_ASSERT(function != (uint32_t)NC);
+
+    switch (STM_PIN_CHANNEL(function)) {
+        case 1:
+            obj->channel = DAC_CHANNEL_1;
+            break;
+#if defined(DAC_CHANNEL_2)
+        case 2:
+            obj->channel = DAC_CHANNEL_2;
+            break;
+#endif
+        default:
+            error("Unknown DAC channel");
+            break;
+    }
+
+    // Configure GPIO
+    pinmap_pinout(pin, PinMap_DAC);
+
+    // Save the pin for future use
+    obj->pin = pin;
+
+    // Enable DAC clock
+    __HAL_RCC_DAC1_CLK_ENABLE();
+
+    // Configure DAC
+    obj->handle.Instance = DAC;
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
+    if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
+        error("HAL_DAC_Init failed");
+    }
+
+    sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
+    sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
+    sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+    sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE;
+    sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
+
+    if (obj->channel == DAC_CHANNEL_1) {
+        channel1_used = 1;
+    } else { // channel 1 per default
+        channel2_used = 1;
+    }
+
+    if (HAL_DAC_ConfigChannel(&obj->handle, &sConfig, obj->channel) != HAL_OK) {
+        error("Cannot configure DAC channel\n");
+    }
+
+    analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj) {
+    // Reset DAC and disable clock
+    if (obj->channel == DAC_CHANNEL_1) channel1_used = 0;
+#if defined(DAC_CHANNEL_2)
+    if (obj->channel == DAC_CHANNEL_2) channel2_used = 0;
+#endif
+
+    if ((channel1_used == 0) && (channel2_used == 0)) {
+        __HAL_RCC_DAC1_FORCE_RESET();
+        __HAL_RCC_DAC1_RELEASE_RESET();
+        __HAL_RCC_DAC1_CLK_DISABLE();
+    }
+
+    // Configure GPIO
+    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+#endif // DEVICE_ANALOGOUT
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/can_device.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/can_device.h
new file mode 100755
index 0000000..3cb1c1b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/can_device.h
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_DEVICE_H
+#define MBED_CAN_DEVICE_H
+
+#include "cmsis.h"
+#include "stm32l4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_CAN
+
+#define CAN_NUM    1 // Number of CAN peripherals present in the STM32 serie
+
+#define CAN1_IRQ_RX_IRQN        CAN1_RX0_IRQn
+#define CAN1_IRQ_RX_VECT        CAN1_RX0_IRQHandler
+#define CAN1_IRQ_TX_IRQN        CAN1_TX_IRQn
+#define CAN1_IRQ_TX_VECT        CAN1_TX_IRQHandler
+#define CAN1_IRQ_ERROR_IRQN     CAN1_SCE_IRQn
+#define CAN1_IRQ_ERROR_VECT     CAN1_SCE_IRQHandler
+#define CAN1_IRQ_PASSIVE_IRQN   CAN1_SCE_IRQn
+#define CAN1_IRQ_PASSIVE_VECT   CAN1_SCE_IRQHandler
+#define CAN1_IRQ_BUS_IRQN       CAN1_SCE_IRQn
+#define CAN1_IRQ_BUS_VECT       CAN1_SCE_IRQHandler
+
+#endif // DEVICE_CAN
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
new file mode 100755
index 0000000..9ee1672
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
@@ -0,0 +1,150 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_COMMON_OBJECTS_H
+#define MBED_COMMON_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pwmout_s {
+    PWMName pwm;
+    PinName pin;
+    uint32_t prescaler;
+    uint32_t period;
+    uint32_t pulse;
+    uint8_t channel;
+    uint8_t inverted;
+};
+
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t transfer_type;
+#endif
+};
+
+struct serial_s {
+    UARTName uart;
+    int index; // Used by irq
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t stopbits;
+    uint32_t parity;
+    PinName pin_tx;
+    PinName pin_rx;
+#if DEVICE_SERIAL_ASYNCH
+    uint32_t events;
+#endif
+#if DEVICE_SERIAL_FC
+    uint32_t hw_flow_ctl;
+    PinName pin_rts;
+    PinName pin_cts;
+#endif
+};
+
+struct i2c_s {
+    /*  The 1st 2 members I2CName i2c
+     *  and I2C_HandleTypeDef handle should
+     *  be kept as the first members of this struct
+     *  to ensure i2c_get_obj to work as expected
+     */
+    I2CName  i2c;
+    I2C_HandleTypeDef handle;
+    uint8_t index;
+    int hz;
+    PinName sda;
+    PinName scl;
+    IRQn_Type event_i2cIRQ;
+    IRQn_Type error_i2cIRQ;
+    uint32_t XferOperation;
+    volatile uint8_t event;
+    volatile int pending_start;
+#if DEVICE_I2CSLAVE
+    uint8_t slave;
+    volatile uint8_t pending_slave_tx_master_rx;
+    volatile uint8_t pending_slave_rx_maxter_tx;
+#endif
+#if DEVICE_I2C_ASYNCH
+    uint32_t address;
+    uint8_t stop;
+    uint8_t available_events;
+#endif
+};
+
+struct flash_s {
+    /*  nothing to be stored for now */
+    uint32_t dummy;
+};
+
+struct analogin_s {
+    ADC_HandleTypeDef handle;
+    PinName pin;
+    uint8_t channel;
+};
+
+#include "gpio_object.h"
+
+struct dac_s {
+    DACName dac;
+    PinName pin;
+    uint32_t channel;
+    DAC_HandleTypeDef handle;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#if DEVICE_CAN
+struct can_s {
+    CAN_HandleTypeDef CanHandle;
+    int index;
+    int hz;
+};
+#endif
+
+/* STM32L4 HAL doesn't provide this API called in rtc_api.c */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h
new file mode 100755
index 0000000..b613168
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device.h
@@ -0,0 +1,40 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+//=======================================
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html
new file mode 100755
index 0000000..323a733
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html
@@ -0,0 +1,924 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta http-equiv="Content-Type" content="text/html; charset=windows-1252"><link rel="File-List" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/filelist.xml"><link rel="Edit-Time-Data" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/editdata.mso"><title>Release Notes for STM32L4xx HAL Drivers</title><link rel="themeData" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/themedata.thmx"><link rel="colorSchemeMapping" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/colorschememapping.xml"><style>
+<!--
+/* Font Definitions */
+@font-face
+{font-family:"Cambria Math";
+panose-1:2 4 5 3 5 4 6 3 2 4;
+mso-font-charset:1;
+mso-generic-font-family:roman;
+mso-font-format:other;
+mso-font-pitch:variable;
+mso-font-signature:0 0 0 0 0 0;}
+@font-face
+{font-family:Calibri;
+panose-1:2 15 5 2 2 2 4 3 2 4;
+mso-font-charset:0;
+mso-generic-font-family:swiss;
+mso-font-pitch:variable;
+mso-font-signature:-1610611985 1073750139 0 0 159 0;}
+@font-face
+{font-family:Tahoma;
+panose-1:2 11 6 4 3 5 4 4 2 4;
+mso-font-charset:0;
+mso-generic-font-family:swiss;
+mso-font-pitch:variable;
+mso-font-signature:1627400839 -2147483648 8 0 66047 0;}
+@font-face
+{font-family:Verdana;
+panose-1:2 11 6 4 3 5 4 4 2 4;
+mso-font-charset:0;
+mso-generic-font-family:swiss;
+mso-font-pitch:variable;
+mso-font-signature:536871559 0 0 0 415 0;}
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";}
+h1
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 1 Char";
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+mso-outline-level:1;
+font-size:24.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;}
+h2
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 2 Char";
+mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:"Arial","sans-serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;
+font-style:italic;}
+h3
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 3 Char";
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+mso-outline-level:3;
+font-size:13.5pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;}
+a:link, span.MsoHyperlink
+{mso-style-unhide:no;
+color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{mso-style-unhide:no;
+color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-style-unhide:no;
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";}
+p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
+{mso-style-unhide:no;
+mso-style-link:"Balloon Text Char";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:8.0pt;
+font-family:"Tahoma","sans-serif";
+mso-fareast-font-family:"Times New Roman";}
+span.Heading1Char
+{mso-style-name:"Heading 1 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 1";
+mso-ansi-font-size:14.0pt;
+mso-bidi-font-size:14.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#365F91;
+mso-themecolor:accent1;
+mso-themeshade:191;
+font-weight:bold;}
+span.Heading2Char
+{mso-style-name:"Heading 2 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 2";
+mso-ansi-font-size:13.0pt;
+mso-bidi-font-size:13.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#4F81BD;
+mso-themecolor:accent1;
+font-weight:bold;}
+span.Heading3Char
+{mso-style-name:"Heading 3 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 3";
+mso-ansi-font-size:12.0pt;
+mso-bidi-font-size:12.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#4F81BD;
+mso-themecolor:accent1;
+font-weight:bold;}
+span.BalloonTextChar
+{mso-style-name:"Balloon Text Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Balloon Text";
+mso-ansi-font-size:8.0pt;
+mso-bidi-font-size:8.0pt;
+font-family:"Tahoma","sans-serif";
+mso-ascii-font-family:Tahoma;
+mso-hansi-font-family:Tahoma;
+mso-bidi-font-family:Tahoma;}
+.MsoChpDefault
+{mso-style-type:export-only;
+mso-default-props:yes;
+font-size:10.0pt;
+mso-ansi-font-size:10.0pt;
+mso-bidi-font-size:10.0pt;}
+@page WordSection1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.WordSection1
+{page:WordSection1;}
+/* List Definitions */
+@list l0
+{mso-list-id:62067358;
+mso-list-template-ids:-174943062;}
+@list l0:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l0:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1
+{mso-list-id:128015942;
+mso-list-template-ids:-90681214;}
+@list l1:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2
+{mso-list-id:216556000;
+mso-list-template-ids:925924412;}
+@list l2:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l2:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l2:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3
+{mso-list-id:562446694;
+mso-list-template-ids:913898366;}
+@list l3:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l3:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4
+{mso-list-id:797802132;
+mso-list-template-ids:-1971191336;}
+@list l4:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5
+{mso-list-id:907304066;
+mso-list-template-ids:1969781532;}
+@list l5:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6
+{mso-list-id:1050613616;
+mso-list-template-ids:-1009886748;}
+@list l6:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l6:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l6:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7
+{mso-list-id:1234970193;
+mso-list-template-ids:2055904002;}
+@list l7:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l7:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l7:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8
+{mso-list-id:1846092290;
+mso-list-template-ids:-768590846;}
+@list l8:level1
+{mso-level-start-at:2;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9
+{mso-list-id:1894656566;
+mso-list-template-ids:1199983812;}
+@list l9:level1
+{mso-level-start-at:2;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+ol
+{margin-bottom:0in;}
+ul
+{margin-bottom:0in;}
+-->
+</style><meta content="MCD Application Team" name="author"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>Raouf Hosni</o:LastAuthor> <o:Revision>39</o:Revision> <o:TotalTime>137</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2010-10-15T11:07:00Z</o:LastSaved> <o:Pages>3</o:Pages> <o:Words>973</o:Words> <o:Characters>5548</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>46</o:Lines> <o:Paragraphs>13</o:Paragraphs> <o:CharactersWithSpaces>6508</o:CharactersWithSpaces> <o:Version>12.00</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:TrackMoves>false</w:TrackMoves> <w:TrackFormatting/> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:DoNotPromoteQF/> <w:LidThemeOther>EN-US</w:LidThemeOther> <w:LidThemeAsian>X-NONE</w:LidThemeAsian> <w:LidThemeComplexScript>X-NONE</w:LidThemeComplexScript> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> <w:DontGrowAutofit/> <w:SplitPgBreakAndParaMark/> <w:DontVertAlignCellWithSp/> <w:DontBreakConstrainedForcedTables/> <w:DontVertAlignInTxbx/> <w:Word11KerningPairs/> <w:CachedColBalance/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> <m:mathPr> <m:mathFont m:val="Cambria Math"/> <m:brkBin m:val="before"/> <m:brkBinSub m:val="&#45;-"/> <m:smallFrac m:val="off"/> <m:dispDef/> <m:lMargin m:val="0"/> <m:rMargin m:val="0"/> <m:defJc m:val="centerGroup"/> <m:wrapIndent m:val="1440"/> <m:intLim m:val="subSup"/> <m:naryLim m:val="undOvr"/> </m:mathPr></w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" DefUnhideWhenUsed="false" DefSemiHidden="false" DefQFormat="false" LatentStyleCount="267"> <w:LsdException Locked="false" QFormat="true" Name="Normal"/> <w:LsdException Locked="false" QFormat="true" Name="heading 1"/> <w:LsdException Locked="false" QFormat="true" Name="heading 2"/> <w:LsdException Locked="false" QFormat="true" Name="heading 3"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 4"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 5"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 6"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 7"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 8"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 9"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="caption"/> <w:LsdException Locked="false" QFormat="true" Name="Title"/> <w:LsdException Locked="false" Priority="1" Name="Default Paragraph Font"/> <w:LsdException Locked="false" QFormat="true" Name="Subtitle"/> <w:LsdException Locked="false" QFormat="true" Name="Strong"/> <w:LsdException Locked="false" QFormat="true" Name="Emphasis"/> <w:LsdException Locked="false" Priority="99" Name="No List"/> <w:LsdException Locked="false" Priority="99" SemiHidden="true" Name="Placeholder Text"/> <w:LsdException Locked="false" Priority="1" QFormat="true" Name="No Spacing"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading"/> <w:LsdException Locked="false" Priority="61" Name="Light List"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3"/> <w:LsdException Locked="false" Priority="70" Name="Dark List"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 1"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 1"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 1"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 1"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 1"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 1"/> <w:LsdException Locked="false" Priority="99" SemiHidden="true" Name="Revision"/> <w:LsdException Locked="false" Priority="34" QFormat="true" Name="List Paragraph"/> <w:LsdException Locked="false" Priority="29" QFormat="true" Name="Quote"/> <w:LsdException Locked="false" Priority="30" QFormat="true" Name="Intense Quote"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 1"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 1"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 1"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 1"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 1"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 1"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 1"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 1"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 2"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 2"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 2"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 2"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 2"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 2"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 2"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 2"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 2"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 2"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 2"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 2"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 2"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 2"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 3"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 3"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 3"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 3"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 3"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 3"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 3"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 3"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 3"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 3"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 3"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 3"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 3"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 3"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 4"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 4"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 4"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 4"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 4"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 4"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 4"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 4"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 4"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 4"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 4"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 4"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 4"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 4"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 5"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 5"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 5"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 5"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 5"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 5"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 5"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 5"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 5"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 5"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 5"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 5"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 5"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 5"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 6"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 6"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 6"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 6"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 6"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 6"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 6"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 6"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 6"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 6"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 6"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 6"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 6"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 6"/> <w:LsdException Locked="false" Priority="19" QFormat="true" Name="Subtle Emphasis"/> <w:LsdException Locked="false" Priority="21" QFormat="true" Name="Intense Emphasis"/> <w:LsdException Locked="false" Priority="31" QFormat="true" Name="Subtle Reference"/> <w:LsdException Locked="false" Priority="32" QFormat="true" Name="Intense Reference"/> <w:LsdException Locked="false" Priority="33" QFormat="true" Name="Book Title"/> <w:LsdException Locked="false" Priority="37" SemiHidden="true" UnhideWhenUsed="true" Name="Bibliography"/> <w:LsdException Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="TOC Heading"/> </w:LatentStyles> </xml><![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif";} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="7170"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--></head>
+<body link="blue" vlink="blue">
+<div class="WordSection1">
+<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
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+<p class="MsoNormal"><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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+<td style="padding: 1.5pt;">
+<h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release
+Notes for STM32L4xx HAL Drivers</span><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright
+2017 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img style="border: 0px solid ; width: 112px; height: 83px;" alt="" id="_x0000_i1026" src="../../_htmresc/st_logo.png"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;"><o:p>&nbsp;</o:p></span></p>
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0in;" valign="top">
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.1
+/ 21-April-2017</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Maintenance Release of <span style="font-weight: bold;">HAL and Low Layer drivers</span></span></li></ul>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">generic driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add HAL_GetUIDw0(),&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">HAL_GetUIDw1() and&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">HAL_GetUIDw2() APIs</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL DAC </span></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix Sample &amp; Hold configuration in case of multi-channel</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix to ensure proper DMA-based HASH processing suspension/resumption</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix USB PCD lock/unlock and flush TX fifo during device reset</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add wait for synchronization in HAL_RTC_Init() to insure RTC time initialization&nbsp;</span></li></ul></ul><br><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL ADC</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix legacy APIs LL_ADC_REG_SetTrigSource() and&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_INJ_SetTrigSource()</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL DMA&nbsp;</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Write only operation on IFCR register</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.0
+/ 17-February-2017</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Release of <span style="font-weight: bold;">HAL and Low Layer drivers</span> to add support of <span style="font-weight: bold;">STM32L496xx/STM32L4A6xx</span> devices</span></li></ul>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New DCMI, DMA2D, HASH peripherals supported in <span style="font-weight: bold;">new HAL DCMI, HAL &amp; LL DMA2D and HAL HASH</span> drivers</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New CAN2 instance supported in HAL CAN<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm)&nbsp;<br></span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL DCMI </span></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">driver </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">(NEW):&nbsp;</span>stm32l4xx_hal_dcmi.h/.c files</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL DMA2D </span></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">driver </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">(NEW):&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span>stm32l4xx_hal_dma2d.h/.c files</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">driver </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">(NEW):&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_hal_hash.h/.c and extension&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_hal_hash_ex.h/.c files </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL&nbsp;drivers require an update on the application code based on older HAL versions</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL SD</span><span class="Apple-converted-space">&nbsp;</span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall rework of the driver for a more efficient&nbsp;implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Modify initialization API and structures</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Modify Read / Write sequences: separate transfer process and SD Cards state management&nbsp;</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Adding interrupt mode for Read / Write operations</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: &quot;Times New Roman&quot;,serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Refer
+to the following examples in STM32CubeL4 firmware package V1.7.0 to
+identify the changes: BSP example and USB_Device/MSC_Standalone
+application</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span>generic update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_hal_conf_template.h updated for new HAL DCMI, HAL DMA2D and HAL HASH</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">#define HAL_DCMI_MODULE_ENABLED</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">#define HAL_DMA2D_MODULE_ENABLED</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_HASH_MODULE_ENABLED<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_Delay() updated to guarantee minimum delay</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CAN</span> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add support of CAN2 instance</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL GPIO</span> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add support of GPIOI port and STM32L496xx/STM32L4A6xx alternate functions</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL PWR</span> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add support of GPIOI port pull-up/pull-down state in Standby and Shutdown modes</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL QSPI</span> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix QSPI_HandleTypeDef structure to handle data size as uint32_t</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RCC</span> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add new macros for new peripherals clock and reset for CAN2, DCMI, DMA2D, GPIOI and HASH</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix HAL_RCCEx_GetPeriphCLKFreq() to compute peripheral frequencies from MSI frequency</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix HAL_RCCEx_GetPeriphCLKFreq() to compute DFSDM1 frequency from PCLK2 frequency</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Rename some peripheral clock sources to specify the corresponding APB clock:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_DFSDM1CLKSOURCE_PCLK to RCC_DFSDM1CLKSOURCE_PCLK2</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_SWPMI1CLKSOURCE_PCLK to RCC_SWPMI1CLKSOURCE_PCLK1</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_LPTIMxCLKSOURCE_PCLK to RCC_LPTIMxCLKSOURCE_PCLK1</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RTC</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix wrong clear&nbsp;of time and date registers in HAL_RTCEx_TamperTimeStampIRQHandler()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SPI</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add internal timeout to exit HAL_SPI_Abort() and HAL_SPI_Abort_IT()&nbsp;</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix wrong MOE disable conditions with new macro __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SWPMI</span> </span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix peripheral clock management sequence in HAL_SWPMI_Init()</span></li></ul></ul> <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL DMA2D&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;">driver </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"> (NEW)</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL BUS&nbsp;</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add management of new peripherals: CAN2, DCMI, DMA2D, GPIOI and HASH</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL PWR</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">For compatibility purpose accross STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RCC</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix LL_RCC_GetDFSDMClockFreq() to compute frequency from PCLK2 frequency</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SDMMC</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new internal functions after HAL SD rework</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL TIM</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix definition of TIM break input polarity (fix values LL_TIM_BKIN_POLARITY_LOW / LL_TIM_BKIN_POLARITY_HIGH)</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.6.0
+/ 28-October-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Release of <span style="font-weight: bold;">HAL and Low Layer drivers</span> to add support of <span style="font-weight: bold;">STM32L451xx/STM32L452xx/STM32L462xx</span> devices</span></li></ul>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm)&nbsp;<br></span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CRYP</span>&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL CRYP exported macros alignment with other STM32 series to use CRYP handle address as parameter in:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">__HAL_CRYP_ENABLE(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,sans-serif; color: black;">__HAL_CRYP_DISABLE(), __HAL_CRYP_SET_OPERATINGMODE(),
+__HAL_CRYP_SET_CHAININGMODE(), __HAL_CRYP_GET_FLAG(), __HAL_CRYP_CLEAR_FLAG(),
+__HAL_CRYP_GET_IT_SOURCE(), __HAL_CRYP_GET_IT(), __HAL_CRYP_CLEAR_IT(),
+__HAL_CRYP_ENABLE_IT() and __HAL_CRYP_DISABLE_IT()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL FLASH</span>&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Temporary data cache deactivation on&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Flash programming in HAL_FLASH_Program() and HAL_FLASH_Program_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Flash erase in HAL_FLASHEx_Erase() and HAL_FLASHEx_Erase_IT()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">To insure LSB/MSB address order&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">in C compiler&nbsp;assembly output</span><span style="font-size: 10pt; font-family: Verdana;">, split 64-bit programming in 2 double-word write operations</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL I2C</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Fix
+to reset HAL I2C handle LISTEN state option in transfer direction
+change with HAL_I2C_Slave_Sequential_Transmit_IT() and
+HAL_I2C_Slave_Sequential_Receive_IT()&nbsp;</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL SMBUS</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add
+support of Zone read/write feature thanks to new XferOptions parameter
+values SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC,
+SMBUS_OTHER_AND_LAST_FRAME_NO_PEC and
+SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC that may be used in
+HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Master_Receive_IT(),
+HAL_SMBUS_Slave_Transmit_IT() and HAL_SMBUS_Slave_Receive_IT()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL RTC</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Fix
+race conditions on EXTI flags clearing in HAL_RTC_AlarmIRQHandler(),
+HAL_RTCEx_TamperTimeStampIRQHandler() and
+HAL_RTCEx_WakeUpTimerIRQHandler()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Fix CodeSonar&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;">warnings in&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">HAL ADC, HAL CRC, HAL CRYP, HAL I2C, HAL IRDA, HAL SMARTCARD, HAL SMBUS, HAL OPAMP, HAL RTC, HAL UART, HAL USART </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL I2C</span> driver</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add I2C4 management in LL_I2C_DeInit()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SYSTEM</span> driver</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Application
+shall be responsible to write the correct key sequence in SYSCFG_SKR
+register prior to call LL_SYSCFG_EnableSRAM2Erase()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL TIM</span> driver</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs to insure BDTR register initialization in a single write operation&nbsp;</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_BDTR_StructInit()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_BDTR_Init()</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL UTILS</span> driver</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix LL_RCC_PLLSOURCE_HSE in LL_PLL_ConfigSystemClock_HSE() &nbsp;</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.2
+/ 12-September-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL ADC</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">No need to configure number of discontinuous conversions if discontinuous mode is not enabled</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_ADCEx_MultiModeConfigChannel() returns HAL_ERROR if no Slave instance defined<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL DAC</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix calibration with correct handling of DAC_SR_CAL_FLAGx bits in HAL_DACEx_SelfCalibrate()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL FLASH</span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Change in HAL_FLASHEx_OBGetConfig() to not return PCROP and/or WRP data if&nbsp;their respective areas are not defined</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix
+error management in HAL_FLASH_IRQHandler() to simply call
+HAL_FLASH_OperationErrorCallback() instead of calling both
+HAL_FLASH_EndOfOperationCallback() and&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">HAL_FLASH_OperationErrorCallback()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL I2C</span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix wrong state check in HAL_I2C_Master_Sequential_Transmit_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add
+new option I2C_FIRST_AND_NEXT_FRAME to manage a sequencewith start
+condition, address and data to transfer without a final stop condition
+allowing successive calls to HAL_I2C_Master_Sequential_Transmit_IT() </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL IRDA</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add transfer abort functions and associated callbacks in interrupt mode</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA_Abort(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_AbortTransmit(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_AbortReceive()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_Abort_IT(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_AbortTransmit_IT(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_AbortReceive_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_AbortCpltCallback(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_AbortTransmit</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">CpltCallback()</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_IRDA</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">_AbortReceive</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">CpltCallback()</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;"></span><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">IRQ Handler + DMA model optimizations</span></li></ul></ul><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL RTC</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Fix missing wakeup flag clear in HAL_RTCEx_SetWakeUpTimer_IT() &nbsp;</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL SMARTCARD</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add transfer abort functions and associated callbacks in interrupt mode</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortReceive()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_AbortReceive_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortTransmit</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">CpltCallback()</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">, HAL_SMARTCARD_AbortReceive</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">CpltCallback()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">IRQ Handler + DMA model optimizations</span></li></ul></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;">HAL SMBUS</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Fix issue on last data reception in host or device modes</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SPI</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">USE_SPI_CRC</span>
+compilation define added to provide the mean to optimize the HAL SPI
+driver when CRC feature is not used (<span style="font-weight: bold;">when CRC is used, application must be changed to set USE_SPI_CRC in stm32l4xx_hal_conf.h</span> (see Inc\</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_hal_conf_template.h))</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add transfer abort functions and associated callbacks in interrupt mode</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;"></span><span style="font-size: 10pt; font-family: Verdana;">HAL_SPI_Abort()</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_SPI_Abort_IT()</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_SPI_AbortCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SWPMI</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix SWPMI peripheral errors management in DMA (resort to HAL_DMA_Abort_IT() and DMA XferAbortCallback in HAL_SWPMI_IRQHandler())</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL UART</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New APIs to abort&nbsp;UART tranfer with associated callbacks added&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_UART_Abort(),
+HAL_UART_AbortTransmit(), HAL_UART_AbortReceive(), HAL_UART_Abort_IT(),
+HAL_UART_AbortTransmit_IT(), HAL_UART_AbortReceive_IT(),
+HAL_UART_AbortCpltCallback(), HAL_UART_AbortTransmitCpltCallback() and
+HAL_UART_AbortReceiveCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL&nbsp;USART</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New APIs to abort&nbsp;USART tranfer with associated callbacks added</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_USART_Abort(), HAL_USART_Abort_IT() and HAL_USART_AbortCpltCallback()</span></li></ul></ul></ul><p style="margin: 4.5pt 0cm 4.5pt 18pt;" class="MsoNormal"><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;">LL Drivers 
+changes</span></u></b></p><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;"></span></u></b><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;"></span></u></b>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL COMP</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix LL_COMP_INPUT_PLUS_IO3 definition</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.1
+/ 31-May-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL ADC</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Bypass multimode assert_param macro calls depending on configuration</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL CRC</span> driver</span>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">HAL_CRC_DeInit() resets CRC_IDR 
+register to reset value</span></li></ul></ul><p style="margin: 4.5pt 0cm 4.5pt 18pt;" class="MsoNormal"><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;">LL Drivers 
+changes</span></u></b></p><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;"></span></u></b><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;"></span></u></b>
+<ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL BUS</span> driver</span>
+<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">LL_APB1_GRP1_PERIPH_USBFS 
+renamed to LL_APB1_GRP1_PERIPH_USB</span></li></ul>
+</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL SYSTEM</span> driver</span>
+<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Fix typo on 
+LL_DBGMCU_APB1_xxx and </span><span style="font-family: Verdana; font-size: 10pt;">LL_DBGMCU_APB2_xxx</span></li></ul></li></ul>
+<span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0
+/ 29-April-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Maintenance Release of <span style="font-weight: bold;">HAL and Low Layer drivers</span></span></li></ul>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>
+
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Enhance HAL delay and timebase implementation</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Add
+new driver
+stm32l4xx_hal_timebase_tim_template.c which overrides the native HAL
+time base functions (defined as weak) to use the TIM peripheral as time
+base tick source.&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">For more details about the usage of this driver, please refer to
+HAL\HAL_TimeBase example and FreeRTOS-based applications</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0</span></li></ul><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;"></span><ul style="margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RCC</span> driver</span></li></ul><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">To
+use PLLSAI1 and PLLSAI2 indidependently from main system PLL, PLLSAI1
+&amp; PLLSAI2 initialization enriched to add PLL entry clock source and
+divider M</span></li></ul><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_PLLSAI1InitTypeDef includes PLLSAI1Source and </span><span style="font-size: 10pt; font-family: Verdana;">PLLSAI1M new fields </span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_PLLSAI2InitTypeDef includes PLLSAI2Source and </span><span style="font-size: 10pt; font-family: Verdana;">PLLSAI2M new fields</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">DFSDM renaming to DFSDM1&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">All macros __HAL_RCC_DFSDM_xxx() renamed to&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">__HAL_RCC_DFSDM1_xxx()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">DfsdmClockSelection field of RCC_PeriphCLKInitTypeDef renamed to Dfsdm1ClockSelection</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_PERIPHCLK_DFSDM renamed to RCC_PERIPHCLK_DFSDM1</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_DFSDMCLKSOURCE_PCLK renamed to RCC_DFSDM1CLKSOURCE_PCLK</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC_DFSDMCLKSOURCE_SYSCLK renamed to RCC_DFSDM1CLKSOURCE_SYSCLK</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">__HAL_RCC_DFSDM_CONFIG() renamed to __HAL_RCC_DFSDM1_CONFIG()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">__HAL_RCC_GET_DFSDM_SOURCE() renamed to __HAL_RCC_GET_DFSDM1_SOURCE()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Update to avoid waiting on&nbsp;STOPF/BTF/AF flag under DMA ISR by using
+the&nbsp;PPP end of transfer interrupt in the DMA transfer process.&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">This requires the following
+updates on&nbsp;user application:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Configure and enable the I2Cx IRQ in HAL_I2C_MspInit() function</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">In&nbsp;stm32l4xx_it.c file, I2Cx_IRQHandler() function:&nbsp;add a
+call to HAL_I2C_IRQHandler() function</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">UART/USART</span></span><span style="font-size: 10pt; font-family: Verdana;"> drivers</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">IRQ Handler global optimization&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add error management in case of DMA transfer through
+       </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_DMA_Abort_IT() and DMA </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">XferAbortCallback()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">Polling management update:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">The user Timeout value must be estimated for the overall process
+duration</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL IRDA/SMARTCARD</span></span><span style="font-size: 10pt; font-family: Verdana;"> drivers</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">Polling management update:</span></li></ul><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">The user Timeout value must be estimated for the overall process
+duration</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SPI</span> driver</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">Add SPI error management during DMA process: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">this requires the following updates in the user
+       application:</span><span style="font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Configure and enable the SPIx IRQ in
+        HAL_SPI_MspInit() function</span><span style="font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">In stm32l4xx_it.c file, SPIx_IRQHandler()
+        function: add a call to HAL_SPI_IRQHandler() function</span><span style="font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;"><o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Add and customize the
+Error Callback API: HAL_SPI_ErrorCallback()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL QSPI</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Add QSPI error management during DMA process</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;"></span><span style="font-size: 10pt; font-family: Verdana;">Improve </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">the DMA transmit process by&nbsp;using QSPI TC interrupt instead of
+waiting on TC flag under DMA ISR.&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">These two improvements require the following updates on&nbsp;user
+application:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Configure and enable the QSPI&nbsp;IRQ in HAL_QSPI_MspInit() function</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">In&nbsp;stm32l4xx_it.c file,&nbsp;QSPI_IRQHandler() function:&nbsp;add a
+call to HAL_QSPI_IRQHandler() function</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Add the management of non-blocking transfer abort
+service:&nbsp;HAL_QSPI_Abort_IT(). </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">In this case the user must:</span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add new callback HAL_QSPI_AbortCpltCallback()
+       to inform user at the end of abort process</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">A new value of State in
+the HAL_QSPI_StateTypeDef provides the current state during the abort phase</span></li></ul></ul></ul></ul>
+
+<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;"></span><ul style="margin-top: 0cm;" type="square"><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR">Polling management update:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">The user Timeout value must be estimated for the overall process
+duration</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;" lang="FR"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Fix wrong data size management in HAL_QSPI_Receive_DMA()</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;"></span><span style="font-size: 10pt; font-family: Verdana;">New API HAL_QSPI_SetFifoThreshold() and HAL_QSPI_GetFifoThreshold()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL IWDG</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL IWDG driver: r</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">emove&nbsp;HAL_IWDG_Start(),&nbsp;HAL_IWDG_MspInit()
+and&nbsp;HAL_IWDG_GetState()&nbsp;APIs</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API functions are:&nbsp;</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Init():&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">this function insures the configuration and the start of the IWDG
+counter</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Refresh():&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">this function insures the reload of the IWDG counter</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Refer to the following example to identify the changes: IWDG_Example</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL WWDG</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL WWDG driver: remove&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">HAL_WWDG_Start(),&nbsp;HAL_WWDG_Start_IT(),&nbsp;HAL_WWDG_MspDeInit()
+and&nbsp;HAL_WWDG_GetState() APIs</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;"></span><span style="font-size: 11pt; font-family: &quot;Calibri&quot;,sans-serif; color: black;">HAL_WWDG_Refresh</span><span style="font-size: 10pt; font-family: Verdana;">() API to remove counter parameter</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt</span></li></ul><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API
+functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(),
+HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()</span></li></ul></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL DMA</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Global driver code optimization to reduce memory footprint&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">New APIs HAL_DMA_RegisterCallback() and </span><span style="font-size: 10pt; font-family: Verdana;">HAL_DMA_UnRegisterCallback() </span><span style="font-size: 10pt; font-family: Verdana;">to register/unregister the different possible callbacks identified by enum typedef HAL_DMA_CallbackIDTypeDef</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">New API HAL_DMA_Abort_IT() to abort DMA transfer in non-blocking mode for&nbsp;interrupt context</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The new registered Abort callback is called when DMA transfer abortion is completed</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Add new Error Codes: HAL_DMA_ERROR_NO_XFER and
+HAL_DMA_ERROR_NOT_SUPPORTED</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;">Add __HAL_DMA_GET_COUNTER() macro<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL COMP</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">EXTI
+configuration done in HAL_COMP_Init() based on TriggerMode field of
+COMP_InitTypeDef structure; HAL_COMP_Start()/</span><span style="font-size: 10pt; font-family: Verdana;">HAL_COMP_Stop()</span><span style="font-size: 10pt; font-family: Verdana;"> APIs are sufficient to start and stop comparators (HAL_COMP_Start_IT() and HAL_COMP_Stop_IT() are preserved for
+legacy compatibility)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add comparator startup time and scaler bridge&nbsp;stabilization time in HAL_COMP_Init()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix to call HAL_COMP_TriggerCallback() only once when the 2 comparators are configured in window mode</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Inverting &amp; Non-inverting inputs renaming (previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_INVERTING_xxx definitions renamed to COMP_INPUT_MINUS_xxx</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_NONINVERTING_xxx definitions renamed to COMP_INPUT_PLUS_xxx</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Blanking sources renaming to highlight Comparator &amp; Timer instances connections </span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM1OC5 renamed to COMP_BLANKINGSRC_TIM1_OC5_COMP1</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM2OC3 renamed to COMP_BLANKINGSRC_TIM2_OC3_COMP1</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM3OC3 renamed to COMP_BLANKINGSRC_TIM3_OC3_COMP1</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM3OC4 renamed to COMP_BLANKINGSRC_TIM3_OC4_COMP2</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM8OC5 renamed to COMP_BLANKINGSRC_TIM8_OC5_COMP2</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM15OC1 renamed to COMP_BLANKINGSRC_TIM15_OC1_COMP2</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_NONE renamed to </span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRC_NONE</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CRYP</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Software workaround for AES issue on GCM encryption with payload length not a multiple of 128 bits</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add support of payload length not multiple of 32 bits<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL GPIO</span> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add missing GPIO_AF6_COMP1 for STM32L431xx/</span><span style="font-size: 10pt; font-family: Verdana;">STM32L432xx/</span><span style="font-size: 10pt; font-family: Verdana;">STM32L433xx/</span><span style="font-size: 10pt; font-family: Verdana;">STM32L442xx/</span><span style="font-size: 10pt; font-family: Verdana;">STM32L443xx</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">DFSDM renaming to DFSDM1&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">GPIO_AF6_DFSDM renamed to GPIO_AF6_DFSDM1<br></span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL HCD</span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Clear NACK flag before re-enabling the channel for new IN request</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL PCD</span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Host mode</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Use HCLK frequency to set TRDT value</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Device mode</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Force suspend and low-power mode before going to L1 state</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Unmask Start Of Frame interrupt<br></span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">DFSDM renaming to DFSDM1&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">TIM_BREAKINPUTSOURCE_DFSDM&nbsp;renamed to TIM_BREAKINPUTSOURCE_DFSDM1</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SAI</span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;" lang="FR">Update
+      HAL_SAI_IRQHandler:</span><span style="font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;" lang="FR"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="circle"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">Add error management in case of DMA transfer through
+       </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">HAL_DMA_Abort_IT() and DMA </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;">XferAbortCallback()</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;"></span><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SWPMI</span></span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update initialization sequence in&nbsp;voltage class B</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL ADC</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix injected conversion configuration with SW start in LL_ADC_INJ_ConfigQueueContext()</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL BUS</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">DFSDM renaming to DFSDM1&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_APB2_GRP1_PERIPH_DFSDM renamed to LL_APB2_GRP1_PERIPH_DFSDM1</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL COMP</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Window mode renaming to highlight Comparator instances connection&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_COMP_WINDOWMODE_ENABLE renamed to LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Blanking sources renaming to highlight Comparator &amp; Timer instances connections </span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">LL_COMP_BLANKINGSRCE_TIM1OC5 renamed to </span><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRC_TIM1_OC5_COMP1</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM2OC3 renamed to </span><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRC_TIM2_OC3_COMP1</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM3OC3 renamed to </span><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRC_TIM3_OC3_COMP1</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM3OC4 renamed to </span><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRC_TIM3_OC4_COMP2</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM8OC5 renamed to </span><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRC_TIM8_OC5_COMP2</span></li></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRCE_TIM15OC1 renamed to </span><span style="font-size: 10pt; font-family: Verdana;">LL_</span><span style="font-size: 10pt; font-family: Verdana;">COMP_BLANKINGSRC_TIM15_OC1_COMP2</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL I2C</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Add&nbsp;SMBus feature support</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_I2C_InitTypeDef structure enriched with new PeripheralMode field to indicate I2C or SMBus modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New
+APIs LL_I2C_EnableSMBusAlert(), LL_I2C_DisableSMBusAlert(),
+LL_I2C_IsEnabledSMBusAlert(), LL_I2C_EnableSMBusPEC(),
+LL_I2C_DisableSMBusPEC(), LL_I2C_IsEnabledSMBusPEC(),
+LL_I2C_ConfigSMBusTimeout(),&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_I2C_EnableSMBusTimeout(), LL_I2C_DisableSMBusTimeout(), LL_I2C_IsEnabledSMBusTimeout(),</span><span style="font-size: 10pt; font-family: Verdana;"> LL_I2C_SetSMBusTimeoutA(), LL_I2C_GetSMBusTimeoutA(), LL_I2C_SetSMBusTimeoutAMode(), LL_I2C_GetSMBusTimeoutAMode(),&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_I2C_SetSMBusTimeoutB(),
+LL_I2C_GetSMBusTimeoutB(), LL_I2C_SetSMBusTimeoutBMode(),
+LL_I2C_GetSMBusTimeoutBMode(), LL_I2C_IsActiveSMBusFlag_PECERR(), </span><span style="font-size: 10pt; font-family: Verdana;">LL_I2C_IsActiveSMBusFlag_TIMEOUT(),
+LL_I2C_IsActiveSMBusFlag_ALERT(), LL_I2C_ClearSMBusFlag_PECERR(),
+LL_I2C_ClearSMBusFlag_TIMEOUT(), LL_I2C_ClearSMBusFlag_ALERT(),
+LL_I2C_EnableSMBusPECCompare(), LL_I2C_IsEnabledSMBusPECCompare() and
+LL_I2C_GetSMBusPEC()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_SetMode() and LL_I2C_GetMode()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_EnableAutoEndMode(), LL_I2C_DisableAutoEndMode() and LL_I2C_IsEnabledAutoEndMode()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_EnableReloadMode(), LL_I2C_DisableReloadMode() and LL_I2C_IsEnabledReloadMode()<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_EnableSlaveByteControl(), LL_I2C_DisableSlaveByteControl() and </span><span style="font-size: 10pt; font-family: Verdana;">LL_I2C_IsEnabledSlaveByteControl()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_SetTransferRequest(), LL_I2C_GetTransferRequest(), LL_I2C_SetSlaveAddr() and LL_I2C_GetSlaveAdd()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_SetTransferSize() and LL_I2C_GetTransferSize()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_GenerateStopCondition(), LL_I2C_GenerateStartCondition()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_I2C_EnableAuto10BitRead(), LL_I2C_DisableAuto10BitRead() and LL_I2C_IsEnabledAuto10BitRead()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL PWR</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">New APIs LL_PWR_EnterLowPowerRunMode() and LL_PWR_ExitLowPowerRunMode()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RCC</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">DFSDM renaming to DFSDM1&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_RCC_DFSDM_CLKSOURCE renamed to LL_RCC_DFSDM1_CLKSOURCE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_RCC_DFSDM_CLKSOURCE_PCLK&nbsp;renamed to LL_RCC_DFSDM1_CLKSOURCE_PCLK</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_RCC_DFSDM_CLKSOURCE_SYSCLK renamed to LL_RCC_DFSDM1_CLKSOURCE_SYSCLK<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SYSTEM</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">New API LL_FLASH_IsPrefetchEnabled()</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL TIM</span> driver</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">DFSDM renaming to DFSDM1&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">(previous definitions preserved for legacy compatibility)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_BKIN_SOURCE_DFBK renamed to LL_TIM_BKIN_SOURCE_DF1BK</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New OCRef clear input selection definitions LL_TIM_OCREF_CLR_INT_NC and LL_TIM_OCREF_CLR_INT_ETR</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New OCRef clear API&nbsp;LL_TIM_SetOCRefClearInputSource()<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0
+/ 26-February-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Release of <span style="font-weight: bold;">HAL and Low Layer drivers</span> to add support of <span style="font-weight: bold;">STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/ STM32L443xx</span> devices</span></li></ul>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Low Layer driver initialization/de-initialization APIs&nbsp;</span>applicable to all STM32L4xx devices</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">CRS</span> peripheral implemented as an extension of HAL RCC (HAL_RCCEx_CRS_xxxx() APIs)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm)&nbsp; <br></span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span>generic update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add default HSI48_VALUE in stm32l4xx_hal_conf_template</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CRYP</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New error code HAL_CRYP_BUSY_ERROR to reject new request while ongoing processing</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL IRDA</span>/</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">SMARTCARD/UART/USART</span></span><span style="font-size: 10pt; font-family: Verdana;"> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Improvement of baud rate computation at initialization</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b>&nbsp;&nbsp;&nbsp; </p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;">New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_crs.c</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL BUS</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Add read-back register on clock enable functions to&nbsp;take into account any delay on bus</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL ADC</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Trigger sources renaming:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_REG_TRIG_SW_START renamed to LL_ADC_REG_TRIG_SOFTWARE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_REG_TRIG_EXT_TIM<span style="font-style: italic;">x</span>_CC<span style="font-style: italic;">y</span> renamed to LL_ADC_REG_TRIG_EXT_TIM<span style="font-style: italic;">x</span>_CH<span style="font-style: italic;">y</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_INJ_TRIG_SW_START renamed to LL_ADC_INJ_TRIG_SOFTWARE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_INJ_TRIG_EXT_TIM<span style="font-style: italic;">x</span>_CC<span style="font-style: italic;">y</span> renamed to LL_ADC_INJ_TRIG_EXT_TIM<span style="font-style: italic;">x</span>_CH<span style="font-style: italic;">y</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Oversamping data shift renaming:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_OVS_DATA_SHIFT_NONE&nbsp;renamed to LL_ADC_OVS_SHIFT_NONE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_OVS_DATA_SHIFT_<span style="font-style: italic;">xxx</span> renamed to&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_ADC_OVS_SHIFT_<span style="font-style: italic;">xxx</span></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL DAC</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Trigger sources renaming:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_DAC_TRIGGER_SOFTWARE&nbsp;renamed to LL_DAC_TRIG_SOFTWARE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_DAC_TRIGGER_TIM<span style="font-style: italic;">x</span>_TRGO renamed to LL_DAC_TRIG_EXT_TIM<span style="font-style: italic;">x</span>_TRGO</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_DAC_TRIGGER_EXT_IT9 renamed to LL_DAC_TRIG_EXT_EXTI_LINE9</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL LPUART</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Improvement of LPUARTDIV value in baud rate computation in __LL_LPUART_DIV() macro</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL USART</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">Improvement of </span><span style="font-size: 10pt; font-family: Verdana;">USARTDIV value in baud rate computation in __LL_USART_DIV_SAMPLING8() and __LL_USART_DIV_SAMPLING16() macros</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0
+/ 29-January-2016</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">New Low Layer driver initialization/de-initialization APIs</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Naming rule is LL_PPP_Init(), LL_PPP_StructInit(),&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_PPP_DeInit() </span><span style="font-size: 10pt; font-family: Verdana;">
+and more&nbsp;initialization APIs when applicable for peripheral PPP:
+ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR,
+RCC, RNG, RTC, SPI, SWPMI, TIM and USART.&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_adc.c,&nbsp;stm32l4xx_ll_comp.c, stm32l4xx_ll_crc.c, stm32l4xx_ll_dac.c, stm32l4xx_ll_dma.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_exti.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_gpio.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_i2c.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_lptim.c, stm32l4xx_ll_lpuart.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_opamp.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_pwr.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_rcc.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_rng.c,</span><span style="font-size: 10pt; font-family: Verdana;"> stm32l4xx_ll_rtc.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_spi.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_swpmi.c,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_tim.c and </span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_usart.c</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">stm32l4xx_ll_utils.c contains some Low Layer utilities for SysTick, Flash latency and clock configuration.&nbsp;</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix "parameter unused" GCC compilation warnings on __weak functions</span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span>generic update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Declare uwTick as global variable to allow weak HAL_IncTick() API updates in user application&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add new API HAL_SYSCFG_EnableIOAnalogSwitchBooster() and HAL_SYSCFG_DisableIOAnalogSwitchBooster()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL COMP</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Allow comparator lock from the reset state with HAL_COMP_Lock()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CRYP</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix state issue to resume&nbsp;AES calculations</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL DMA</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix state issue after DMA transfer error&nbsp;</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL FLASH</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix __HAL_FLASH_INSTRUCTION_CACHE_RESET() and __HAL_FLASH_DATA_CACHE_RESET() to allow multiple resets </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Add support of repeated start feature with the following new APIs</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Sequential_Receive_IT() and&nbsp; HAL_I2C_Master_Abort_IT(),&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_I2C_Slave_Sequential_Transmit_IT() and HAL_I2C_Slave_Sequential_Receive_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_I2C_EnableListen_IT() and HAL_I2C_DisableListen_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">New user callbacks HAL_I2C_ListenCpltCallback() and HAL_I2C_AddrCallback()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix acknowledge failure error management (STOP being automatically generated)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Review
+state machine and provide new API &nbsp;HAL_I2C_GetMode() to return
+HAL_I2C_MODE_MASTER, HAL_I2C_MODE_SLAVE or HAL_I2C_MODE_NONE<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL IRDA</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Add missing IRDA_CLEAR_IDLEF</span><span style="font-size: 10pt; font-family: Verdana;"> definition for IDLE flag clear with __HAL_IRDA_CLEAR_FLAG()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SD</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">SD card capacity calculation for cards with capacity over 4GB</span><span style="font-size: 10pt; font-family: Verdana;"> in HAL_SD_Get_CardInfo()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SMARTCARD</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Add missing SMARTCARD_STOPBITS_0_5</span><span style="font-size: 10pt; font-family: Verdana;"> definition for frame with 0.5 stop bit</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL SMARTCARD guardtime correction to not expect a minimum&nbsp; of 12 etu<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Add missing UART_STOPBITS_0_5</span><span style="font-size: 10pt; font-family: Verdana;"> definition for frame with 0.5 stop bit</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RX Buffer flush request should not be called at each RXNE processing</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix wrong macro used in assert_param in HAL_LIN_SendBreak()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL USART</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Add missing USART_STOPBITS_0_5</span><span style="font-size: 10pt; font-family: Verdana;"> definition for frame with 0.5 stop bit</span></li></ul></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; height: 20px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p>
+<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL UTILS</span> update (<span style="font-weight: bold;">user code impacted !</span>)</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Move the following functions declaration from stm32l4xx_ll_utils.h to stm32l4xx_ll_utils.c file</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_mDelay(), LL_Init1msTick() and LL_SetSystemCoreClock()</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL ADC</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;FLAG &amp; IT definition name change</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL COMP</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Rename InputInverting and InputNonInverting APIs</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_COMP_Set{/Get}InputNonInverting() renamed to LL_COMP_Set{/Get}InputMinus</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_COMP_Set{/Get}InputInverting() renamed to LL_COMP_Set{/Get}InputPlus</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove LL_COMP_SetWindowMode() and LL_COMP_GetWindowMode()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL DMA</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Add helper macro __LL_DMA_GET_CHANNEL_INSTANCE()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL GPIO</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix definition LL_GPIO_OUTPUT_OPENDRAIN</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
+the explicit possible values in the API description of
+LL_GPIO_GetPinMode(), LL_GPIO_GetPinOutputType(),
+LL_GPIO_GetPinSpeed(), LL_GPIO_GetPinPull(), LL_GPIO_GetAFPin_0_7() and
+LL_GPIO_GetAFPin_8_15()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
+GPIO speed definitions LL_GPIO_SPEED_FREQ_LOW,
+LL_GPIO_SPEED_FREQ_MEDIUM, LL_GPIO_SPEED_FREQ_HIGH and
+LL_GPIO_SPEED_FREQ_VERY_HIGH to align with HAL GPIO <br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL I2C</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Add missing function LL_I2C_ConfigFilters() to configure noise filters<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL LPTIM</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing functions</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_LPTIM_IsEnabled()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_LPTIM_SetWaveform()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_LPTIM_SetPolarity()<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL OPAMP </span>update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename power range APIs</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_OPAMP_Get{/Set}PowerRange() renamed to </span><span style="font-size: 10pt; font-family: Verdana;">LL_OPAMP_Get{/Set}CommonPowerRange()</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SPI</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix LL_SPI_IsEnabled(), LL_SPI_IsEnabledCRC() and LL_SPI_IsEnabledNSSPulse()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove
+LL_SPI_Set{/Get}HalfDuplexDirection() functions: this is managed with
+TransferDirection parameter in LL_SPI_Set{/Get}TransferDirection()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SWPMI</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing function LL_SWPMI_IsActivated()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL&nbsp;TIM</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing functions</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_CC_IsEnabledChannel()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload() and LL_TIM_OC_IsEnabledClear()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_IsEnabledMasterSlaveMode()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_EnableExternalClock(),&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_DisableExternalClock() and&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_IsEnabledExternalClock()</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL USART</span> update</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add LL_USART_STOPBITS_0_5 definition for usage in LL_USART_Set{/Get}StopBitsLength() and LL_USART_ConfigCharacter()</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
+/ 25-November-2015</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span>generic update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Reduce default HSE startup timeout value to 100ms in Inc\stm32l4xx_hal_conf_template.h file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL PWR</span> update (</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">User application code impacted</span></span><span style="font-size: 10pt; font-family: Verdana;">)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Stop 1 with main regulator renamed into Stop 0, to be aligned with latest version of Reference Manual</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry) into </span><span style="font-size: 10pt; font-family: Verdana;">HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Application code using </span><span style="font-size: 10pt; font-family: Verdana;">HAL_PWREx_EnterSTOP1Mode(PWR_LOWPOWERREGULATOR_ON,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STOPEntry</span><span style="font-size: 10pt; font-family: Verdana;">) must be updated to use&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">HAL_PWREx_EnterSTOP1Mode(</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STOPEntry</span><span style="font-size: 10pt; font-family: Verdana;">)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new API HAL_PWREx_EnterSTOP0Mode(</span><span style="font-size: 10pt; font-family: Verdana;">uint8_t STOPEntry</span><span style="font-size: 10pt; font-family: Verdana;">)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Application code using </span><span style="font-size: 10pt; font-family: Verdana;">HAL_PWREx_EnterSTOP1Mode(PWR_MAINREGULATOR_ON,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STOPEntry</span><span style="font-size: 10pt; font-family: Verdana;">) must be updated to use&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">HAL_PWREx_EnterSTOP0Mode(</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STOPEntry</span><span style="font-size: 10pt; font-family: Verdana;">)</span></li></ul></ul><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span>&nbsp;</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL OPAMP</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Provide capability to run calibration despite PGA mode by switching temporary to standalone mode</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SAI</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update SAI block synchronization selection (</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">User application code</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"> impacted</span></span><span style="font-size: 10pt; font-family: Verdana;">)</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Replace uncomplete SAI_SYNCHRONOUS_EXT value for with SAI_SYNCHRONOUS_EXT_SAI1 and SAI_SYNCHRONOUS_EXT_SAI2</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update external synchronization input selection</span><span style="font-size: 10pt; font-family: Verdana;"> (</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">User application code</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"> impacted</span></span><span style="font-size: 10pt; font-family: Verdana;">)</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Remove useless SAI_SYNCEXT_IN_ENABLE value for SynchroExt field in SAI_InitTypeDef structure</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add support of 24bits configuration in PCM protocol</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add codec not ready interrupt management</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix computation of data size, frame length, active frame length, slot size and first bit offset in I2S protocol</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix&nbsp;mute counter setting in HAL_SAI_EnableRxMuteMode()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix
+ambiguous clock strobing values: fix HAL_SAI_Init() to set correct
+CKSTR bits in SAI_xCR1 according to ClockStrobing and AudioMode
+parameters</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fill in the Fifo before enable interrupt in HAL_SAI_Transmit_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix&nbsp;assert on active slot selection in HAL_SAI_Init()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix companding mode management in HAL_SAI_Init()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TSC</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Improve IODefault state management</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL NOR/HAL SRAM/FMC</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">WriteFifo field of FMC_NORSRAM_InitTypeDef structure is not applicable on STM32L47x/STM32L48x devices</span></li></ul></ul><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL PWR</span> update (</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">User </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">application </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">code impacted</span></span><span style="font-size: 10pt; font-family: Verdana;">)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL PWR API change to add new Stop 0 mode and update Stop 1 mode definition</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change LL_PWR_SetPowerMode(uint32_t LowPowerMode) possible <span style="font-style: italic;">LowPowerMode</span> values update&nbsp;</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_MODE_STOP1_LP_REGU renamed into&nbsp;LL_PWR_MODE_STOP1</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Application code using&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_SetPowerMode</span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_MODE_STOP1_LP_REGU</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"></span><span style="font-size: 10pt; font-family: Verdana;">)</span><span style="font-size: 10pt; font-family: Verdana;"> must be updated to use&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_SetPowerMode</span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_MODE_STOP1</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"></span><span style="font-size: 10pt; font-family: Verdana;">)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_MODE_STOP1_MAIN_REGU renamed into LL_PWR_MODE_STOP0</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Application code using&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_SetPowerMode</span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_MODE_STOP1_MAIN_REGU</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"></span><span style="font-size: 10pt; font-family: Verdana;">)</span><span style="font-size: 10pt; font-family: Verdana;"> must be updated to use&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_SetPowerMode</span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">LL_PWR_MODE_STOP0</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"></span><span style="font-size: 10pt; font-family: Verdana;">)</span></li></ul></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1
+/ 16-October-2015</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span>generic update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fine
+tuning of Inc\stm32l4xx_hal_conf_template.h file to keep Flash prefetch
+off as default system configuration (PREFETCH_ENABLE set to 0)<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Removed
+useless assert_param() macro check on input parameters in
+HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel() and
+HAL_TIM_ConfigClockSource(),&nbsp;</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL ADC</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix LL_ADC_GetAnalogWDMonitChannels() for AWD2 and AWD3</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RCC</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add new API LL_RCC_LSE_DisableCSS()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL UTILS</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix LL_GetPackageType()<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
+/ 16-September-2015</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Add Low Layer drivers allowing performance and footprint optimization&nbsp;</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low
+Layer drivers APIs provide register level programming: they require
+deep knowledge of peripherals described in STM32L4x6 Reference Manual</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low
+Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA,
+EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI,
+SWPMI, TIM, USART, WWDG peripherals and additionnal Low Level Bus,
+System and Utilities APIs. <br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low Layer drivers APIs are implemented as static inline function in new <span style="font-style: italic;">Inc/stm32l4xx_ll_ppp.h</span> files for PPP peripherals, there is no configuration file and each </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32l4xx_ll_ppp.h</span> file must be included in user code.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL ADC</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Channel 5 is not usable for ADC3</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CAN</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update HAL_CAN_IRQHandler() to clear&nbsp;ERRI bit prior to call HAL_CAN_ErrorCallback() </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL COMP</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update HAL_COMP_Init() for low power optimization in case of COMP_INVERTINGINPUT_VREFINT </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL CRC</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add new API HAL_CRYPEx_ProcessSuspend()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL DMA</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">HAL_DMA_IRQHandler() to set HAL_DMA_ERROR_TE error bit in handle ErrorCode field</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL FLASH</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add option byte OB_USER_nRST_SHDW to be used with HAL_FLASHEx_OBProgram()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL GPIO</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename
+GPIO speed definitions&nbsp;to GPIO_SPEED_FREQ_LOW,
+GPIO_SPEED_FREQ_MEDIUM, GPIO_SPEED_FREQ_HIGH and
+GPIO_SPEED_FREQ_VERY_HIGH</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix macro __HAL_GPIO_EXTI_GENERATE_SWIT()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL PWR</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix HAL_PWR_DisableWakeUpPin() to clear only appropriate bits in PWR CR3 register</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Combination
+of GPIO pins possible in HAL_PWREx_EnableGPIOPullUp(),
+HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown() and
+HAL_PWREx_DisableGPIOPullDown()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RCC</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add
+LSE Clock Security System (CSS) management with new APIs:
+HAL_RCCEx_EnableLSECSS_IT(), HAL_RCCEx_LSECSS_IRQHandler() and
+HAL_RCCEx_LSECSS_Callback()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add RCC_MCO1SOURCE_NOCLOCK to provide capability to disable MCO output in HAL_RCC_MCOConfig()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update
+HAL_RCC_OscConfig() and HAL_RCCEx_PeriphCLKConfig() to keep backup
+domain enabled when configuring respectively&nbsp;LSE and RTC clock
+source</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update HAL_RCCEx_DisablePLLSAI1() and </span><span style="font-size: 10pt; font-family: Verdana;">HAL_RCCEx_DisablePLLSAI2() </span><span style="font-size: 10pt; font-family: Verdana;">to disable respectively PLLSAI1 and </span><span style="font-size: 10pt; font-family: Verdana;">PLLSAI2 </span><span style="font-size: 10pt; font-family: Verdana;">clock outputs</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update HAL_RCCEx_GetPeriphCLKFreq() to return the frequency in Hz applied to peripherals via HAL_RCCEx_PeriphCLKConfig()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update HAL_RCC_DeInit() to set default MSI range</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Remove old workaround on LSE drive medium configuration values</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SPI</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix issue to receive CRC in RX 2 lines mode 8-bit dataSize and even buffer size.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix macro __HAL_TIM_SET_COMPARE()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Remove enable of&nbsp;Error interrupt in HAL_UART_Transmit_IT()</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
+/ 26-June-2015</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">First official release of <span style="font-weight: bold;">STM32L4xx HAL Drivers</span> for </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"><span style="font-weight: bold;">STM32L471xx/</span><span style="font-weight: bold;"></span><span style="font-weight: bold;">STM32L475xx/ </span><span style="font-weight: bold;">STM32L476xx/ </span><span style="font-weight: bold;"></span><span style="font-weight: bold;">STM32L485xx and </span></span><span style="font-size: 10pt; font-family: Verdana; font-weight: bold; font-style: italic;">STM32L486xx</span><span style="font-size: 10pt; font-family: Verdana;"> devices</span><span style="font-size: 10pt; font-family: Verdana; font-weight: bold;"></span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><b><u><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></u></b>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
+<div style="text-align: justify;">
+<div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistribution
+and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+</font>
+<ol>
+<li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li>
+<li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the
+documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li>
+<li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the
+name of STMicroelectronics nor the names of its contributors may be
+used to endorse or promote products derived </span><br>
+</font> </li>
+</ol>
+<font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
+from this software without specific prior written permission.</span><br>
+<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS
+SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES,
+INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR
+PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+THE POSSIBILITY OF SUCH DAMAGE.</span></font> </div>
+<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></div>
+<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span>
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+<hr align="center" size="2" width="100%"></span></div>
+<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+</body></html>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h
new file mode 100755
index 0000000..901e9a1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h
@@ -0,0 +1,3154 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants 
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO 
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO 
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */ 
+  
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 
+
+/**
+  * @}
+  */   
+   
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#define COMP_LPTIMCONNECTION_ENABLED   COMP_LPTIMCONNECTION_IN1_ENABLED    /*!< COMPX output is connected to LPTIM input 1 */
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+ 
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+  
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    
+  
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP  
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+  
+  
+  
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+  
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+  
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+/**
+  * @}
+  */
+  
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+  
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+
+#if defined(STM32L1) 
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+   
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+   
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+                                              
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+                                                                      
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          
+                                                        
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+#if defined(STM32F7) 
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA                
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       
+#define CF_CARD_HEAD                  ATA_CARD_HEAD           
+#define CF_STATUS_CMD                 ATA_STATUS_CMD          
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+  
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+/**
+  * @}
+  */
+
+  
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+  
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+  
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+  
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+ 
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */  
+  
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888  
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565  
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888  
+#define CM_RGB565               DMA2D_INPUT_RGB565  
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8      
+#define CM_AL44                 DMA2D_INPUT_AL44    
+#define CM_AL88                 DMA2D_INPUT_AL88    
+#define CM_L4                   DMA2D_INPUT_L4      
+#define CM_A8                   DMA2D_INPUT_A8      
+#define CM_A4                   DMA2D_INPUT_A4      
+/**
+  * @}
+  */    
+#endif  /* STM32L4 ||  STM32F7*/
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */  
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */ 
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1 
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH 
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+ 
+ /**
+  * @}
+  */  
+  
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback         
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback   
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */  
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+/**
+  * @}
+  */
+   
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */ 
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */ 
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+/**
+  * @}
+  */  
+   
+  
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */  
+  
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+   
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+   
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+   
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                          ((WAVE) == DAC_WAVE_NOISE)|| \
+                          ((WAVE) == DAC_WAVE_TRIANGLE))
+  
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE                  
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+  
+  
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()   
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG 
+#endif /* STM32F4 */
+/**   
+  * @}
+  */  
+  
+  
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+  
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
+#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE 
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE 
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE  
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE  
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE  
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE  
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE  
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE  
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE  
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE  
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE  
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE  
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE  
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE  
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE  
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE  
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE  
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE  
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE  
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE  
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE  
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE  
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE  
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE  
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE  
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE  
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE  
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
+#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE	
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)                                       
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER 
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS	       
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT	       
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY    
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED  
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS	        SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT	          SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND	      SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE                  
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE                  
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE                  
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE 
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c
new file mode 100755
index 0000000..285da08
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c
@@ -0,0 +1,695 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @brief HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32L4xx HAL Driver version number V1.7.1
+   */
+#define __STM32L4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4xx_HAL_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
+#define __STM32L4xx_HAL_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4xx_HAL_VERSION         ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32L4xx_HAL_VERSION_RC))
+
+#if defined(VREFBUF)
+#define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms (to be confirmed) */
+#endif /* VREFBUF */
+
+/* ------------ SYSCFG registers bit address in the alias region ------------ */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  MEMRMP Register ---*/
+/* Alias word address of FB_MODE bit */
+#define MEMRMP_OFFSET             SYSCFG_OFFSET
+#define FB_MODE_BitNumber         ((uint8_t)0x8)
+#define FB_MODE_BB                (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
+
+/* --- SCSR Register ---*/
+/* Alias word address of SRAM2ER bit */
+#define SCSR_OFFSET              (SYSCFG_OFFSET + 0x18)
+#define BRER_BitNumber           ((uint8_t)0x0)
+#define SCSR_SRAM2ER_BB          (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t uwTick;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the Flash interface the NVIC allocation and initial time base
+          clock configuration.
+      (+) De-initialize common part of the HAL.
+      (+) Configure the time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the Flash prefetch, the Instruction and Data caches,
+  *         the time base source, NVIC and any required global low level hardware 
+  *         by calling the HAL_MspInit() callback function to be optionally defined in user file 
+  *         stm32l4xx_hal_msp.c.
+  *
+  * @note   HAL_Init() function is called at the beginning of program after reset and before 
+  *         the clock configuration.
+  *             
+  * @note   In the default implementation the System Timer (Systick) is used as source of time base.
+  *         The Systick configuration is based on MSI clock, as MSI is the clock
+  *         used after a system Reset and the NVIC configuration is set to Priority group 4.
+  *         Once done, time base tick starts incrementing: the tick variable counter is incremented 
+  *         each 1ms in the SysTick_Handler() interrupt handler.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  /* Configure Flash prefetch, Instruction cache, Data cache */
+  /* Default configuration at reset is:                      */
+  /* - Prefetch disabled                                     */
+  /* - Instruction cache enabled                             */
+  /* - Data cache enabled                                    */
+#if (INSTRUCTION_CACHE_ENABLE == 0)
+   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE == 0)
+   __HAL_FLASH_DATA_CACHE_DISABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
+  HAL_InitTick(TICK_INT_PRIORITY);
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief De-initialize common part of the HAL and stop the source of time base.
+  * @note This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base:
+  *        The time source is configured to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /*Configure the SysTick to have interrupt in 1ms time basis*/
+  HAL_SYSTICK_Config(SystemCoreClock/1000);
+
+  /*Configure the SysTick IRQ priority */
+  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick++;
+}
+
+/**
+  * @brief Provide a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based 
+  *        on variable incremented. 
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a period to guaranty minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait++;
+  } 
+
+  while((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Return the HAL revision.
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32L4xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Return the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
+}
+
+/**
+  * @brief  Return the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+}
+
+/**
+  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+   return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+   return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+   return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+ *  @brief    HAL Debug functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Debug functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+ *  @brief    HAL SYSCFG configuration functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start a hardware SRAM2 erase operation
+      (+) Enable/Disable the Internal FLASH Bank Swapping
+      (+) Configure the Voltage reference buffer
+      (+) Enable/Disable the Voltage reference buffer
+      (+) Enable/Disable the I/O analog switch voltage booster
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start a hardware SRAM2 erase operation.
+  * @note   As long as SRAM2 is not erased the SRAM2ER bit will be set.
+  *         This bit is automatically reset at the end of the SRAM2 erase operation.
+  * @retval None
+  */
+void HAL_SYSCFG_SRAM2Erase(void)
+{
+  /* unlock the write protection of the SRAM2ER bit */
+  SYSCFG->SKR = 0xCA;
+  SYSCFG->SKR = 0x53;
+  /* Starts a hardware SRAM2 erase operation*/
+  *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001;
+}
+
+/**
+  * @brief  Enable the Internal FLASH Bank Swapping.
+  *
+  * @note   This function can be used only for STM32L4xx devices.
+  *
+  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
+  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_EnableMemorySwappingBank(void)
+{
+  *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disable the Internal FLASH Bank Swapping.
+  *
+  * @note   This function can be used only for STM32L4xx devices.
+  *
+  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
+  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableMemorySwappingBank(void)
+{
+
+  *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE;
+}
+
+#if defined(VREFBUF)
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param  VoltageScaling: specifies the output voltage to achieve
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. 
+  *                                                This requires VDDA equal to or higher than 2.4 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V. 
+  *                                                This requires VDDA equal to or higher than 2.8 V.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+  
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param  Mode: specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+  
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+  
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t  tickstart = 0;
+  
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+  
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
+  {
+    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+#endif /* VREFBUF */
+
+/**
+  * @brief  Enable the I/O analog switch voltage booster
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Disable the I/O analog switch voltage booster
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h
new file mode 100755
index 0000000..7e98496
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h
@@ -0,0 +1,651 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_H
+#define __STM32L4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_conf.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+  * @{
+  */
+#define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)
+#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+      
+#define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
+
+#define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+  * @{
+  */
+#define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
+#define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
+  * @{
+  */
+#define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
+#define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
+#define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
+#define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
+#define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
+#define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
+#if defined(SYSCFG_SWPR_PAGE31)
+#define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
+#define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
+#define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
+#define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
+#define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
+#define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
+#define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
+#define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
+#define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
+#define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
+#define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
+#define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
+#define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
+#define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
+#define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
+#define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
+#endif /* SYSCFG_SWPR_PAGE31 */
+
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_SWPR2_PAGE63)
+/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
+  * @{
+  */
+#define SYSCFG_SRAM2WRP_PAGE32         SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
+#define SYSCFG_SRAM2WRP_PAGE33         SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
+#define SYSCFG_SRAM2WRP_PAGE34         SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
+#define SYSCFG_SRAM2WRP_PAGE35         SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
+#define SYSCFG_SRAM2WRP_PAGE36         SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
+#define SYSCFG_SRAM2WRP_PAGE37         SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
+#define SYSCFG_SRAM2WRP_PAGE38         SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
+#define SYSCFG_SRAM2WRP_PAGE39         SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
+#define SYSCFG_SRAM2WRP_PAGE40         SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
+#define SYSCFG_SRAM2WRP_PAGE41         SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
+#define SYSCFG_SRAM2WRP_PAGE42         SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
+#define SYSCFG_SRAM2WRP_PAGE43         SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
+#define SYSCFG_SRAM2WRP_PAGE44         SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
+#define SYSCFG_SRAM2WRP_PAGE45         SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
+#define SYSCFG_SRAM2WRP_PAGE46         SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
+#define SYSCFG_SRAM2WRP_PAGE47         SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
+#define SYSCFG_SRAM2WRP_PAGE48         SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
+#define SYSCFG_SRAM2WRP_PAGE49         SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
+#define SYSCFG_SRAM2WRP_PAGE50         SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
+#define SYSCFG_SRAM2WRP_PAGE51         SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
+#define SYSCFG_SRAM2WRP_PAGE52         SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
+#define SYSCFG_SRAM2WRP_PAGE53         SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
+#define SYSCFG_SRAM2WRP_PAGE54         SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
+#define SYSCFG_SRAM2WRP_PAGE55         SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
+#define SYSCFG_SRAM2WRP_PAGE56         SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
+#define SYSCFG_SRAM2WRP_PAGE57         SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
+#define SYSCFG_SRAM2WRP_PAGE58         SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
+#define SYSCFG_SRAM2WRP_PAGE59         SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
+#define SYSCFG_SRAM2WRP_PAGE60         SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
+#define SYSCFG_SRAM2WRP_PAGE61         SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
+#define SYSCFG_SRAM2WRP_PAGE62         SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
+#define SYSCFG_SRAM2WRP_PAGE63         SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
+
+/**
+  * @}
+  */
+#endif /* SYSCFG_SWPR2_PAGE63 */
+
+#if defined(VREFBUF)
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
+
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSCFG_flags_definition Flags
+  * @{
+  */
+
+#define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */
+#define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */  
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+
+/**
+ * @}
+ */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
+#define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_FREEZE_CAN2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  Main Flash memory mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief  System Flash memory mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
+
+/** @brief  Embedded SRAM mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+
+/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+/** @brief  QUADSPI mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
+
+/**
+  * @brief  Return the boot mode as configured by user.
+  * @retval The boot mode as configured by user. The returned value can be one
+  *         of the following values:
+  *           @arg @ref SYSCFG_BOOT_MAINFLASH
+  *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
+  @if STM32L486xx
+  *           @arg @ref SYSCFG_BOOT_FMC
+  @endif
+  *           @arg @ref SYSCFG_BOOT_SRAM
+  *           @arg @ref SYSCFG_BOOT_QUADSPI
+  */
+#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief  SRAM2 page 0 to 31 write protection enable macro
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
+  * @note   Write protection can only be disabled by a system reset
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
+                                                         SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
+                                                        }while(0)
+
+#if defined(SYSCFG_SWPR2_PAGE63)
+/** @brief  SRAM2 page 32 to 63 write protection enable macro
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
+  * @note   Write protection can only be disabled by a system reset
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
+                                                                SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
+                                                            }while(0)
+#endif /* SYSCFG_SWPR2_PAGE63 */
+
+/** @brief  SRAM2 page write protection unlock prior to erase
+  * @note   Writing a wrong key reactivates the write protection
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\
+                                                 SYSCFG->SKR = 0x53;\
+                                                }while(0)
+
+/** @brief  SRAM2 erase
+  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
+  */
+#define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
+
+/** @brief  Floating Point Unit interrupt enable/disable macros
+  * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
+  */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
+                                                            }while(0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
+                                                            }while(0)
+
+/** @brief  SYSCFG Break ECC lock.
+  *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
+  *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+
+/** @brief  SYSCFG Break SRAM2 parity lock.
+  *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
+
+/** @brief  Check SYSCFG flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag
+  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
+
+/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
+  */
+#define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
+
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__: This parameter can be a value of : 
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+  * @{
+  */
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
+
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+
+#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
+
+#if defined(VREFBUF)
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+#endif /* VREFBUF */
+
+#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#elif defined(SYSCFG_FASTMODEPLUS_PB8)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
+#elif defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#else
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
+#endif
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+  * @{
+  */
+
+/* DBGMCU Peripheral Control functions  *****************************************/
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+  * @{
+  */
+
+/* SYSCFG Control functions  ****************************************************/
+void HAL_SYSCFG_SRAM2Erase(void);
+void HAL_SYSCFG_EnableMemorySwappingBank(void);
+void HAL_SYSCFG_DisableMemorySwappingBank(void);
+
+#if defined(VREFBUF)
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+#endif /* VREFBUF */
+
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c
new file mode 100755
index 0000000..5617796
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c
@@ -0,0 +1,3097 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_adc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          peripheral:
+  *           + Initialization and de-initialization functions
+  *             ++ Initialization and Configuration of ADC
+  *           + Operation functions
+  *             ++ Start, stop, get result of conversions of regular
+  *                group, using 3 possible modes: polling, interruption or DMA.
+  *           + Control functions
+  *             ++ Channels configuration on regular group
+  *             ++ Analog Watchdog configuration
+  *           + State functions
+  *             ++ ADC state machine management
+  *             ++ Interrupts and flags management
+  *          Other functions (extended functions) are available in file 
+  *          "stm32l4xx_hal_adc_ex.c".
+  *
+  @verbatim
+  ==============================================================================
+                     ##### ADC peripheral features #####
+  ==============================================================================
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+  (+) Interrupt generation at the end of regular conversion and in case of 
+      analog watchdog or overrun events.
+  
+  (+) Single and continuous conversion modes.
+  
+  (+) Scan mode for conversion of several channels sequentially.
+  
+  (+) Data alignment with in-built data coherency.
+  
+  (+) Programmable sampling time (channel wise)
+  
+  (+) External trigger (timer or EXTI) with configurable polarity
+  
+  (+) DMA request generation for transfer of conversions data of regular group.
+  
+  (+) Configurable delay between conversions in Dual interleaved mode.
+  
+  (+) ADC channels selectable single/differential input.
+  
+  (+) ADC offset on regular groups.
+
+  (+) ADC calibration
+  
+  (+) ADC conversion of regular group.
+  
+  (+) ADC supply requirements: 1.62 V to 3.6 V.
+  
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to 
+      Vdda or to an external voltage reference).
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Configuration of top level parameters related to ADC ***
+     ============================================================
+     [..]
+
+    (#) Enable the ADC interface
+        (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+        (++) Two clock settings are mandatory: 
+             (+++) ADC clock (core clock, also possibly conversion clock).
+
+             (+++) ADC clock (conversions clock).
+                   Two possible clock sources: synchronous clock derived from APB clock
+                   or asynchronous clock derived from system clock, PLLSAI1 or the PLLSAI2 
+                   running up to 80MHz.
+
+             (+++) Example:
+                   Into HAL_ADC_MspInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
+
+               RCC_ADCCLKSOURCE_PLLSAI2 enable:                   (optional: if asynchronous clock selected)
+               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
+               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLLSAI2;
+               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+        (++) ADC clock source and clock prescaler are configured at ADC level with
+             parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+    (#) ADC pins configuration
+         (++) Enable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+         (++) Configure these ADC pins in analog mode
+              using function HAL_GPIO_Init()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Configure the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
+              into the function of corresponding ADC interruption vector 
+              ADCx_IRQHandler().
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+              using function HAL_DMA_Init().
+         (++) Configure the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
+              into the function of corresponding DMA interruption vector 
+              DMAx_Channelx_IRQHandler().
+  
+     *** Configuration of ADC, group regular, channels parameters ***
+     ================================================================
+     [..]
+
+    (#) Configure the ADC parameters (resolution, data alignment, ...)
+        and regular group parameters (conversion trigger, sequencer, ...)
+        using function HAL_ADC_Init().
+
+    (#) Configure the channels for regular group parameters (channel number, 
+        channel rank into sequencer, ..., into regular group)
+        using function HAL_ADC_ConfigChannel().
+
+    (#) Optionally, configure the analog watchdog parameters (channels
+        monitored, thresholds, ...)
+        using function HAL_ADC_AnalogWDGConfig().
+
+     *** Execution of ADC conversions ***
+     ====================================
+     [..]
+
+    (#) Optionally, perform an automatic ADC calibration to improve the
+        conversion accuracy
+        using function HAL_ADCEx_Calibration_Start().
+
+    (#) ADC driver can be used among three modes: polling, interruption,
+        transfer by DMA.
+
+        (++) ADC conversion by polling:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start()
+          (+++) Wait for ADC conversion completion 
+                using function HAL_ADC_PollForConversion()
+          (+++) Retrieve conversion results 
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop()
+
+        (++) ADC conversion by interruption: 
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_IT()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback()
+                (this function must be implemented in user program)
+          (+++) Retrieve conversion results 
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop_IT()
+
+        (++) ADC conversion with transfer by DMA:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_DMA()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+                (these functions must be implemented in user program)
+          (+++) Conversion results are automatically transferred by DMA into
+                destination variable address.
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop_DMA()
+
+     [..]
+
+    (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+     *** Deinitialization of ADC ***
+     ============================================================
+     [..]
+
+    (#) Disable the ADC interface
+      (++) ADC clock can be hard reset and disabled at RCC top level.
+        (++) Hard reset of ADC peripherals
+             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+        (++) ADC clock disable
+             using the equivalent macro/functions as configuration step.
+             (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+    (#) ADC pins configuration
+         (++) Disable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Disable the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Deinitialize the DMA
+              using function HAL_DMA_Init().
+         (++) Disable the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+    [..]
+  
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+#define ADC_CFGR_FIELDS_1  ((uint32_t)(ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
+                                       ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
+                                       ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
+                                       ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))   /*!< ADC_CFGR fields of parameters that can be updated 
+                                                                                  when no regular conversion is on-going */
+                                      
+#define ADC_CFGR2_FIELDS  ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
+                                       ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
+                                       ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
+                                                                                 (neither regular nor injected) is on-going  */
+
+#define ADC_CFGR_WD_FIELDS  ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
+                                        ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH))  /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
+                                                                                  conversion (neither regular nor injected) is on-going  */
+  
+#define ADC_OFR_FIELDS  ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
+                                                                                                        (neither regular nor injected) is on-going */
+
+
+  
+/* Delay to wait before setting ADEN once ADCAL has been reset
+   must be at least 4 ADC clock cycles.
+   Assuming lowest ADC clock (140 KHz according to DS), this
+   4 ADC clock cycles duration is equal to
+   4 / 140,000 = 0.028 ms.
+   ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
+   the 4 ADC clock cycles have elapsed while waiting for ADRDY
+   to become 1 */        
+  #define ADC_ENABLE_TIMEOUT              ((uint32_t)  2)    /*!< ADC enable time-out value  */
+  #define ADC_DISABLE_TIMEOUT             ((uint32_t)  2)    /*!< ADC disable time-out value */
+   
+    
+                                                                            
+/* Delay for ADC voltage regulator startup time                               */
+/*  Maximum delay is 10 microseconds                                          */
+/* (refer device RM, parameter Tadcvreg_stup).                                */
+#define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */
+  
+  
+/* Timeout to wait for current conversion on going to be completed.           */
+/* Timeout fixed to worst case, for 1 channel.                                */
+/*   - maximum sampling time (640.5 adc_clk)                                  */
+/*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
+/*   - ADC clock with prescaler 256                                           */
+/*     653 * 256 = 167168 clock cycles max                                    */
+/* Unit: cycles of CPU clock.                                                 */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168)  /*!< ADC conversion completion time-out value */
+
+
+
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    ADC Initialization and Configuration functions
+  *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC. 
+      (+) De-initialize the ADC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the ADC peripheral and regular group according to  
+  *         parameters specified in structure "ADC_InitTypeDef".
+  * @note   As prerequisite, ADC clock must be configured at RCC top level
+  *         depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks 
+  *         or AHB clock.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+  *         coming from ADC state reset. Following calls to this function can
+  *         be used to reconfigure some parameters of ADC_InitTypeDef  
+  *         structure on the fly, without modifying MSP configuration. If ADC  
+  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+  *         before HAL_ADC_Init().
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_InitTypeDef".
+  * @note   This function configures the ADC within 2 scopes: scope of entire 
+  *         ADC and scope of regular group. For parameters details, see comments 
+  *         of structure "ADC_InitTypeDef".
+  * @note   Parameters related to common ADC registers (ADC clock mode) are set 
+  *         only if all ADCs are disabled.
+  *         If this is not the case, these common parameters setting are  
+  *         bypassed without error reporting: it can be the intended behaviour in
+  *         case of update of a parameter of ADC_InitTypeDef on the fly,
+  *         without  disabling the other ADCs.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  ADC_Common_TypeDef *tmpADC_Common;
+  uint32_t tmpCFGR = 0;
+  __IO uint32_t wait_loop_index = 0;
+  
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+  
+  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+    
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+    }
+  }
+  
+  
+  /* DISCEN and CONT bits cannot be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+ 
+  
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+    
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Initialize Lock */
+    hadc->Lock = HAL_UNLOCKED;
+  }
+  
+  
+  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
+  /*  Exit deep power down mode if still in that state */
+  if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
+  {
+    /* Exit deep power down mode */ 
+    CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+    
+    /* System was in deep power down mode, calibration must
+     be relaunched or a previously saved calibration factor 
+     re-applied once the ADC voltage regulator is enabled */    
+  }
+  
+  if  (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+  {  
+    /* Enable ADC internal voltage regulator */
+    SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
+    
+    /* Delay for ADC stabilization time */
+    /* Wait loop initialization and execution */
+    /* Note: Variable divided by 2 to compensate partially                    */
+    /*       CPU processing cycles.                                           */
+    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+  }
+  
+  /* Verification that ADC voltage regulator is correctly enabled, whether    */
+  /* or not ADC is coming from state reset (if any potential problem of       */
+  /* clocking, voltage regulator would not be enabled).                       */
+  if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))  
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Set ADC error code to ADC IP internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed and if there is no conversion on going on regular    */
+  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+  /* called to update a parameter on the fly).                                */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+      (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  )
+  {
+    
+    /* Initialize the ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+    
+    /* Configuration of common ADC parameters                                 */
+    
+    /* Pointer to the common control register                                 */
+    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+    
+    
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated only when ADC is disabled:              */
+    /*  - clock configuration                                                 */
+    if ((ADC_IS_ENABLE(hadc) == RESET)   &&
+         (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
+    {
+      /* Reset configuration of ADC common register CCR:                      */
+      /*                                                                      */
+      /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
+      /*     according to adc->Init.ClockPrescaler. It selects the clock      */
+      /*    source and sets the clock division factor.                        */
+      /*                                                                      */
+      /* Some parameters of this register are not reset, since they are set   */
+      /* by other functions and must be kept in case of usage of this         */
+      /* function on the fly (update of a parameter of ADC_InitTypeDef        */
+      /* without needing to reconfigure all other ADC groups/channels         */
+      /* parameters):                                                         */
+      /*   - when multimode feature is available, multimode-related           */
+      /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
+      /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
+      /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+      /*     (set into HAL_ADC_ConfigChannel() or                             */
+      /*     HAL_ADCEx_InjectedConfigChannel() )                              */
+           
+      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
+    }
+    
+    /* Configuration of ADC:                                                  */
+    /*  - resolution                               Init.Resolution            */
+    /*  - data alignment                           Init.DataAlign             */
+    /*  - external trigger to start conversion     Init.ExternalTrigConv      */
+    /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
+    /*  - continuous conversion mode               Init.ContinuousConvMode    */
+    /*  - overrun                                  Init.Overrun               */
+    /*  - discontinuous mode                       Init.DiscontinuousConvMode */
+    /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
+    tmpCFGR  = (ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode)           |
+                hadc->Init.Overrun                                           |
+                hadc->Init.DataAlign                                         |
+                hadc->Init.Resolution                                        |
+                ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode)  );
+    
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+    }
+    
+    /* Enable external trigger if trigger selection is different of software  */
+    /* start.                                                                 */
+    /*  - external trigger to start conversion     Init.ExternalTrigConv      */
+    /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
+    /* Note:  parameter ExternalTrigConvEdge set to "trigger edge none" is    */
+    /*        equivalent to software start.                                   */
+    if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+    &&  (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
+    {
+      tmpCFGR |= ( hadc->Init.ExternalTrigConv |  hadc->Init.ExternalTrigConvEdge);
+    }
+    
+     /* Update Configuration Register CFGR */
+     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated when ADC is disabled or enabled without */
+    /* conversion on going on regular and injected groups:                    */
+    /*  - DMA continuous request          Init.DMAContinuousRequests          */
+    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
+    /*  - Oversampling parameters         Init.Oversampling                   */
+    if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+    {
+      tmpCFGR = ( ADC_CFGR_DFSDM(hadc)                                 |
+                  ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait)       |
+                  ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+               
+      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);                    
+    
+ 
+      if (hadc->Init.OversamplingMode == ENABLE)
+      {
+        assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+        
+        if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
+        ||  (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+        {
+            /* Multi trigger is not applicable to software-triggered conversions */
+            assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
+        }
+    
+    
+       /* Configuration of Oversampler:                                       */
+       /*  - Oversampling Ratio                                               */
+       /*  - Right bit shift                                                  */
+       /*  - Triggered mode                                                   */
+       /*  - Oversampling mode (continued/resumed)                            */
+       MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 
+                               ADC_CFGR2_ROVSE                     | 
+                               hadc->Init.Oversampling.Ratio         |
+                               hadc->Init.Oversampling.RightBitShift |
+                               hadc->Init.Oversampling.TriggeredMode |
+                               hadc->Init.Oversampling.OversamplingStopReset);
+      }
+      else
+      {
+        /* Disable Regular OverSampling */
+        CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+      }
+      
+    }   /*  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
+    
+    
+    
+    /* Configuration of regular group sequencer:                              */
+    /* - if scan mode is disabled, regular channels sequence length is set to */
+    /*   0x00: 1 channel converted (channel on regular rank 1)                */
+    /*   Parameter "NbrOfConversion" is discarded.                            */
+    /*   Note: Scan mode is not present by hardware on this device, but       */
+    /*   emulated by software for alignment over all STM32 devices.           */
+    /* - if scan mode is enabled, regular channels sequence length is set to  */
+    /*   parameter "NbrOfConversion"                                          */
+
+    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+    {
+      /* Set number of ranks in regular group sequencer */     
+      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));  
+    }
+    else
+    {
+      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+    }
+    
+    /* Initialize the ADC state */
+    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    tmp_hal_status = HAL_ERROR;
+  }  /*  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)  && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  ) */
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Deinitialize the ADC peripheral registers to their default reset
+  *         values, with deinitialization of the ADC MSP.           
+  * @note   Keep in mind that all ADCs use the same clock: disabling
+  *         the clock will reset all ADCs.
+  * @note   By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
+  *         reducing the leakage currents and is particularly interesting before
+  *         entering STOP 1 or STOP 2 modes.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Note: No check on ADC_ConversionStop() return status,              */
+  /*       if the conversion stop failed, it is up to                   */
+  /*       HAL_ADC_MspDeInit() to reset the ADC IP.                     */
+  ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped            */
+  /* Flush register JSQR: reset the queue sequencer when injected             */
+  /* queue sequencer is enabled and ADC disabled.                             */
+  /* The software and hardware triggers of the injected sequence are both     */
+  /* internally disabled just after the completion of the last valid          */
+  /* injected sequence.                                                       */
+  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+  
+  /* Disable the ADC peripheral */
+  /* No check on ADC_Disable() return status, if the ADC disabling process
+    failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */  
+  ADC_Disable(hadc);
+  
+  
+  /* ========== Reset ADC registers ========== */
+  /* Reset register IER */
+  __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
+                              ADC_IT_JQOVF | ADC_IT_OVR  |
+                              ADC_IT_JEOS  | ADC_IT_JEOC |
+                              ADC_IT_EOS   | ADC_IT_EOC  |
+                              ADC_IT_EOSMP | ADC_IT_RDY                 ) );
+      
+  /* Reset register ISR */
+  __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+                              ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
+                              ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
+                              ADC_FLAG_EOS   | ADC_FLAG_EOC  |
+                              ADC_FLAG_EOSMP | ADC_FLAG_RDY                   ) );
+  
+  /* Reset register CR */
+ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, 
+    ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": 
+    no direct reset applicable. 
+    Update CR register to reset value where doable by software */
+  CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+  SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);    
+      
+  /* Reset register CFGR */
+  CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
+  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);  
+  
+  /* Reset register CFGR2 */
+  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |   
+                                  ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE    );                                 
+  
+  /* Reset register SMPR1 */
+  CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);                                 
+  
+  /* Reset register SMPR2 */
+  CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | 
+                             ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | 
+                             ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10    );                                 
+  
+  /* Reset register TR1 */
+  CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
+  
+  /* Reset register TR2 */
+  CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);    
+  
+  /* Reset register TR3 */
+  CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);      
+  
+  /* Reset register SQR1 */
+  CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | 
+                            ADC_SQR1_SQ1 | ADC_SQR1_L);                              
+  
+  /* Reset register SQR2 */
+  CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | 
+                            ADC_SQR2_SQ6 | ADC_SQR2_SQ5);                                
+  
+  /* Reset register SQR3 */
+  CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | 
+                            ADC_SQR3_SQ11 | ADC_SQR3_SQ10);                                 
+  
+  /* Reset register SQR4 */
+  CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); 
+  
+  /* Register JSQR was reset when the ADC was disabled */
+  
+  /* Reset register DR */
+  /* bits in access mode read only, no direct reset applicable*/
+    
+  /* Reset register OFR1 */
+  CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); 
+  /* Reset register OFR2 */
+  CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); 
+  /* Reset register OFR3 */
+  CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); 
+  /* Reset register OFR4 */
+  CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+  
+  /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+  /* bits in access mode read only, no direct reset applicable*/
+  
+  /* Reset register AWD2CR */
+  CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+  
+  /* Reset register AWD3CR */
+  CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+  
+  /* Reset register DIFSEL */
+  CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+  
+  /* Reset register CALFACT */
+  CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+  
+  
+  /* ========== Reset common ADC registers ========== */
+        
+  /* Software is allowed to change common parameters only when all the other
+     ADCs are disabled.   */
+  if ((ADC_IS_ENABLE(hadc) == RESET)   &&
+       (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
+  {
+    /* Reset configuration of ADC common register CCR:
+      - clock mode: CKMODE, PRESCEN
+      - multimode related parameters (when this feature is available): MDMA, 
+        DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+      - internal measurement paths: Vbat, temperature sensor, Vref (set into
+        HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+    */
+    ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+  }
+
+  /* DeInit the low level hardware. 
+  
+     For example:
+    __HAL_RCC_ADC_FORCE_RESET();
+    __HAL_RCC_ADC_RELEASE_RESET();
+    __HAL_RCC_ADC_CLK_DISABLE();
+    
+    Keep in mind that all ADCs use the same clock: disabling
+    the clock will reset all ADCs. 
+    
+  */
+  HAL_ADC_MspDeInit(hadc);
+    
+  /* Set ADC error code to none */
+  ADC_CLEAR_ERRORCODE(hadc);
+  
+  /* Reset injected channel configuration parameters */
+  hadc->InjectionConfig.ContextQueue = 0;
+  hadc->InjectionConfig.ChannelCount = 0; 
+    
+  /* Set ADC state */
+  hadc->State = HAL_ADC_STATE_RESET;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the ADC MSP.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspInit must be implemented in the user file.
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the ADC MSP.
+  * @param  hadc: ADC handle
+  * @note   All ADCs use the same clock: disabling the clock will reset all ADCs.
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspDeInit must be implemented in the user file.
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+ *  @brief    ADC IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular group.
+      (+) Stop conversion of regular group.
+      (+) Poll for conversion complete on regular group.
+      (+) Poll for conversion event.
+      (+) Get result of regular channel conversion.
+      (+) Start conversion of regular group and enable interruptions.
+      (+) Stop conversion of regular group and disable interruptions.
+      (+) Handle ADC interrupt request
+      (+) Start conversion of regular group and enable DMA transfer.
+      (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC, start conversion of regular group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled (when multimode feature is available): 
+  *           if ADC is Slave, ADC is enabled but conversion is not started, 
+  *           if ADC is master, ADC is enabled and multimode conversion is started.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_TypeDef       *tmpADC_Master;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+    
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+  
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* State machine update: Check if an injected conversion is ongoing */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));         
+      }
+      else
+      {  
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc); 
+      }
+      /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
+      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
+
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - by default if ADC is Master or Independent or if multimode feature is not available
+        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
+      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+    
+      /* Clear regular group conversion flag and overrun flag                   */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
+      {
+        /* Multimode feature is not available or ADC Instance is Independent or Master, 
+           or is not Slave ADC with dual regular conversions enabled. 
+           Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+        }
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        /* Start ADC */
+        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+      }
+      else
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, update Slave State in setting 
+           HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
+        tmpADC_Master = ADC_MASTER_REGISTER(hadc); 
+        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+           
+        }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);      
+      } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in 
+  *         case of auto_injection mode), disable ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential 
+  *         conversion on injected group. If injected group is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
+      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for regular group conversion to be completed.
+  * @param  hadc: ADC handle
+  * @param  Timeout: Timeout value in millisecond.
+  * @note   Depending on hadc->Init.EOCSelection, EOS or EOC is 
+  *         checked and cleared depending on AUTDLY bit status. 
+  * @note   HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
+  *         DMA-managed conversions configuration: indeed, EOC is immediately 
+  *         reset by the DMA reading the DR register when the converted data is
+  *         available. Therefore, EOC is set for a too short period to be 
+  *         reliably polled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+  uint32_t tmp_Flag_EOC   = 0x00;
+  uint32_t tmp_cfgr       = 0x00;
+  uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set, 
+                                        tmp_eos_raised will be corrected
+                                        accordingly during API execution */
+  ADC_TypeDef *tmpADC_Master;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* If end of conversion selected to end of sequence conversions */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_EOC = ADC_FLAG_EOS;
+  }
+  /* If end of conversion selected to end of unitary conversion */
+  else /* ADC_EOC_SINGLE_CONV */
+  {
+    /* Check that the ADC is not in a DMA-based configuration. Otherwise,
+       returns an error. */
+       
+    /* Check whether dual regular conversions are disabled or unavailable. */
+    if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)  
+    {
+      /* Check DMAEN bit in handle ADC CFGR register */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      } 
+    }
+    else
+    {
+      /* Else need to check Common register CCR MDMA bit field. */
+      if (ADC_MULTIMODE_DMA_ENABLED())
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      }
+    }
+    
+    /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
+    tmp_Flag_EOC = ADC_FLAG_EOC;
+  }
+  
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+  
+  /* Wait until End of unitary conversion or sequence conversions flag is raised */
+  while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+      {
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Next, to clear the polled flag as well as to update the handle State,
+     EOS is checked and the relevant configuration register is retrieved. */
+  /*   1. Check whether or not EOS is set */
+  if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
+  {
+    tmp_eos_raised = 0;
+  }
+  /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
+   regular conversions enabled. */
+   if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) 
+  {
+    /* Retrieve handle ADC CFGR register */
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR);  
+  }
+  else
+  {
+    /* Retrieve Master ADC CFGR register */
+    tmpADC_Master = ADC_MASTER_REGISTER(hadc);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+  }
+
+  /* Clear polled flag */
+  if (tmp_Flag_EOC == ADC_FLAG_EOS)
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);  
+  }
+  else
+  {
+
+    /* Clear end of conversion EOC flag of regular group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
+    /* until data register is read using function HAL_ADC_GetValue().         */
+    /* For regular groups, no new conversion will start before EOC is cleared.*/
+    /* Note that 1. reading DR clears EOC.                                    */ 
+    /*           2. in multimode with dual regular conversions enabled (when  */
+    /*              multimode feature is available), Master AUTDLY bit is     */
+    /*              checked.                                                  */
+    if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    }
+  }
+  
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+  /* If 1. EOS is set
+        2. conversions are software-triggered
+        3. CONT bit is reset (that of handle ADC or Master ADC if applicable)          
+     Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
+        4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
+          can be set */
+  if ((tmp_eos_raised)
+   && (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+   && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
+   {
+     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+     /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
+     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+     { 
+       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+     }
+   }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for ADC event.
+  * @param  hadc: ADC handle
+  * @param  EventType: the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
+  *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+  *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
+  *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+  *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
+  *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
+  * @param  Timeout: Timeout value in millisecond.
+  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set  
+  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten 
+  *         by a new converted data as soon as OVR is cleared.
+  *         To reset OVR flag once the preserved data is retrieved, the user can resort
+  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart = 0; 
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+  
+  /* Get tick count */
+  tickstart = HAL_GetTick();   
+  
+  /* Check selected event flag */
+  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+      {
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  switch(EventType)
+  {
+  /* End Of Sampling event */
+  case ADC_EOSMP_EVENT:
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+     
+    /* Clear the End Of Sampling flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+       
+    break;  
+  
+  /* Analog watchdog (level out of window) event                              */
+  /* Note: In case of several analog watchdog enabled, if needed to know      */
+  /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
+  /* flags HAL_ADC_STATE_AWD/2/3 function.                                    */
+  /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) "        */
+  /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)"        */
+  /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)"        */
+  case ADC_AWD_EVENT:
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+    
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+    
+    break;
+  
+  /* Check analog watchdog 2 flag */
+  case ADC_AWD2_EVENT:
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+      
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+    
+    break;
+  
+  /* Check analog watchdog 3 flag */
+  case ADC_AWD3_EVENT:
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+      
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+    
+    break;
+  
+  /* Injected context queue overflow event */
+  case ADC_JQOVF_EVENT:
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+    
+    /* Set ADC error code to Injected context queue overflow */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+    
+    /* Clear ADC Injected context queue overflow flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+    
+    break;
+    
+  /* Overrun event */
+  default: /* Case ADC_OVR_EVENT */
+    /* If overrun is set to overwrite previous data, overrun event is not     */
+    /* considered as an error.                                                */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+        
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+    }
+    else
+    {
+      /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+         otherwise, data register is potentially overwritten by new converted data as soon
+         as OVR is cleared. */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+    }
+    break;
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : EOC (end of conversion), EOS (end of sequence), 
+  *         OVR overrun.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available): 
+  *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+  *         ADC Master.
+  *         For ADC Slave, ADC is enabled only (conversion is not started).  
+  *         For ADC Master, ADC is enabled and multimode conversion is started.
+  * @note   To guarantee a proper reset of all interruptions once all the needed
+  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure 
+  *         a correct stop of the IT-based conversions.
+  * @note   By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling 
+  *         interruption. If required (e.g. in case of oversampling with trigger
+  *         mode), the user must:
+  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)             
+  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)     
+  *          before calling HAL_ADC_Start_IT().
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_TypeDef       *tmpADC_Master;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+    
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+ 
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* State machine update: Check if an injected conversion is ongoing */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));         
+      }
+      else
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc); 
+      } 
+      /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
+      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
+      
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - by default if ADC is Master or Independent or if multimode feature is not available
+        - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
+      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+   
+      /* By default, disable all interruptions before enabling the desired ones */
+      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+      
+      /* Enable required interruptions */
+      switch(hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV: 
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+         break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+         break;
+      }
+   
+      /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+         ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+         behavior and no CPU time is lost for a non-processed interruption */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);  
+      }   
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion starts at next     */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */ 
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   )
+      {
+        /* Multimode feature is not available or ADC Instance is Independent or Master, 
+           or is not Slave ADC with dual regular conversions enabled.         
+           Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+          
+          /* Enable as well injected interruptions in case 
+           HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+           allows to start regular and injected conversions when JAUTO is
+           set with a single call to HAL_ADC_Start_IT() */
+          switch(hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV: 
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+            break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+            break;
+          }  
+        } /*  if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);           
+        /* Start ADC */     
+        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+      }
+      else
+      {
+        /* hadc is the handle of a Slave ADC with dual regular conversions
+           enabled. Therefore, ADC_CR_ADSTART is NOT set */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, Slave injected interruptions
+           are enabled nevertheless (for same reason as above) */
+        tmpADC_Master = ADC_MASTER_REGISTER(hadc); 
+        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
+        {
+          /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit 
+             and in resetting HAL_ADC_STATE_INJ_EOC bit */
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+          /* Next, set Slave injected interruptions */
+          switch(hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV: 
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+            break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+            break;
+          }         
+        }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);         
+      } /*  if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   ) */     
+    }  /*  if (tmp_hal_status == HAL_OK) */
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+    
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in 
+  *         case of auto_injection mode), disable interrution of 
+  *         end-of-conversion, disable ADC peripheral.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for regular group */
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+    
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY),
+                        HAL_ADC_STATE_READY);
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
+  * @note   Interruptions enabled in this function:
+  *         overrun (if applicable), DMA half transfer, DMA transfer complete. 
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() 
+  *         is designed for single-ADC mode only. For multimode, the dedicated 
+  *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
+  * @param  hadc: ADC handle
+  * @param  pData: Destination Buffer address.
+  * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+    
+    /* Ensure that dual regular conversions are not enabled or unavailable.   */
+    /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
+    if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
+    {
+      /* Enable the ADC peripheral */
+      tmp_hal_status = ADC_Enable(hadc);
+    
+      /* Start conversion if ADC is effectively enabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* State machine update: Check if an injected conversion is ongoing */
+        if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+        {
+          /* Reset ADC error code fields related to regular conversions only */
+          CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));             
+        }
+        else
+        {
+          /* Set ADC error code to none */
+          ADC_CLEAR_ERRORCODE(hadc);
+        }
+        /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
+        ADC_STATE_CLR_SET(hadc->State,
+                          (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
+                          HAL_ADC_STATE_REG_BUSY);
+
+       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - by default if ADC is Master or Independent or if multimode feature is not available
+        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
+        if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+        {
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        }
+      
+        /* Set the DMA transfer complete callback */
+        hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+        
+        /* Set the DMA half transfer complete callback */
+        hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+        
+        /* Set the DMA error callback */
+        hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+        
+        
+        /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
+        /* ADC start (in case of SW start):                                   */
+        
+        /* Clear regular group conversion flag and overrun flag               */
+        /* (To ensure of no unknown state from potential previous ADC         */
+        /* operations)                                                        */
+        __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+        
+        /* With DMA, overrun event is always considered as an error even if 
+           hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,  
+           ADC_IT_OVR is enabled.  */         
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);  
+        
+        
+        /* Enable ADC DMA mode */
+        SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+      
+        /* Start the DMA channel */
+        HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+        
+        /* Enable conversion of regular group.                                  */
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);          
+        /* If software start has been selected, conversion starts immediately.  */
+        /* If external trigger has been selected, conversion will start at next */
+        /* trigger event.                                                       */
+        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+      
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);      
+      }  /* if (tmp_hal_status == HAL_OK) */
+    }
+    else
+    {
+      tmp_hal_status = HAL_ERROR;
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);      
+    } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
+    
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+    
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in 
+  *         case of auto_injection mode), disable ADC DMA transfer, disable 
+  *         ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential 
+  *         conversion on injected group. If injected group is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @note   Case of multimode enabled (when multimode feature is available): 
+  *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. 
+  *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential ADC group regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    }
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep  */
+    /* in memory a potential failing status.                                  */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+    }
+    else
+    {
+      ADC_Disable(hadc);
+    }
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY),
+                        HAL_ADC_STATE_READY);
+    }
+    
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function does not clear ADC flag EOS 
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function: 
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion() 
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param  hadc: ADC handle
+  * @retval ADC group regular conversion data
+  */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+  
+  /* Return ADC converted value */ 
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Handle ADC interrupt request.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+  uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
+  ADC_TypeDef        *tmpADC_Master;  
+  uint32_t tmp_isr      = hadc->Instance->ISR;
+  uint32_t tmp_ier      = hadc->Instance->IER;
+  uint32_t tmp_cfgr     = 0x0;
+  uint32_t tmp_cfgr_jqm = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  
+  /* ====== Check End of Sampling flag for regular group ===== */
+  if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+  {
+    /* Update state machine on end of sampling status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+    }
+        
+    /* End Of Sampling callback */
+      HAL_ADCEx_EndOfSamplingCallback(hadc);
+    
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
+  }  
+  
+  /* ====== Check End of Conversion or Sequence flags for regular group ===== */
+  if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+      (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))  )
+  {
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* Set ADC state */    
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
+    }
+    
+    /* Disable interruption if no further conversion upcoming by regular      */
+    /* external trigger or by continuous mode,                                */
+    /* and if scan sequence if completed.                                     */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
+    {
+      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
+      {
+        /* check CONT bit directly in handle ADC CFGR register */
+        tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
+      }
+      else
+      {
+        /* else need to check Master ADC CONT bit */
+        tmpADC_Master = ADC_MASTER_REGISTER(hadc);
+        tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
+      }
+      
+      /* Carry on if continuous mode is disabled */
+      if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
+      {
+        /* If End of Sequence is reached, disable interrupts */
+        if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+        {
+          /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+          /* ADSTART==0 (no conversion on going)                                */
+          if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+          {
+            /* Disable ADC end of sequence conversion interrupt */
+            /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
+            /* in HAL_Start_IT(), it isn't disabled here because it can be used */
+            /* by overrun IRQ process below.                                    */
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+            /* Clear HAL_ADC_STATE_REG_BUSY bit */
+             CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 
+             /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
+             if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+             { 
+               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+             }           
+          }
+          else
+          {
+            /* Change ADC state to error state */
+            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+            
+            /* Set ADC error code to ADC IP internal error */
+            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+          }
+        }
+      } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
+    }   /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   */
+    
+    /* Conversion complete callback */
+    /* Note:  HAL_ADC_ConvCpltCallback can resort to 
+              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
+              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether 
+              interruption has been triggered by end of conversion or end of 
+              sequence.    */
+      HAL_ADC_ConvCpltCallback(hadc);
+
+    
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
+  }
+  
+  
+  /* ========== Check End of Conversion flag for injected group ========== */
+  if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+      (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))  )      
+  {
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+    }
+    
+
+    /* Check whether interruptions can be disabled only if
+        - injected conversions are software-triggered when injected queue management is disabled
+        OR
+        - auto-injection is enabled, continuous mode is disabled (CONT = 0)
+          and regular conversions are software-triggered */
+          /* If End of Sequence is reached, disable interrupts */
+    if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+    {
+          
+      /* First, retrieve proper registers to check */
+      /* 1a. Are injected conversions that of a dual Slave ? */
+      if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
+      {
+        /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
+           check JQM bit directly in ADC CFGR register */
+        tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); 
+      }
+      else
+      {
+        /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
+           need to check JQM bit of Master ADC CFGR register */
+          tmpADC_Master = ADC_MASTER_REGISTER(hadc);
+          tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR); 
+      }
+      /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */ 
+      if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
+      {
+        /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
+           check JAUTO and CONT bits directly in ADC CFGR register */        
+          tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
+      }
+      else
+      {
+        /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
+           check JAUTO and CONT bits of Master ADC CFGR register */  
+        tmpADC_Master = ADC_MASTER_REGISTER(hadc);
+        tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
+      }
+      
+      /* Secondly, check whether JEOC and JEOS interruptions can be disabled */                                                 
+      if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))  
+         && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&    
+             (ADC_IS_SOFTWARE_START_REGULAR(hadc))))    )
+      {
+        /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit         */
+        /* JADSTART==0 (no conversion on going)                               */
+        if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+        {
+          /* Disable ADC end of sequence conversion interrupt  */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+          /* Clear HAL_ADC_STATE_INJ_BUSY bit */
+           CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
+           /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */                   
+          if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+          { 
+            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+          }           
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+          
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+    } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
+    
+    /* Injected Conversion complete callback */
+    /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to 
+              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+              interruption has been triggered by end of conversion or end of 
+              sequence.    */    
+    HAL_ADCEx_InjectedConvCpltCallback(hadc);
+    
+    /* Clear injected group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+  }
+   
+  /* ========== Check Analog watchdog flags =================================================== */
+  
+  /* ========== Check Analog watchdog 1 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))      
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+    
+    /* Level out of window 1 callback */
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+    /* Clear ADC analog watchdog flag */ 
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+  }
+  
+  /* ========== Check analog watchdog 2 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))      
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+    
+    /* Level out of window 2 callback */
+    HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+    /* Clear ADC analog watchdog flag */ 
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+  } 
+  
+  /* ========== Check analog watchdog 3 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))      
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+    
+    /* Level out of window 3 callback */
+    HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+    /* Clear ADC analog watchdog flag */ 
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+  }
+  
+  /* ========== Check Overrun flag ========== */
+  if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) 
+  {
+    /* If overrun is set to overwrite previous data (default setting),        */
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      overrun_error = 1;
+    }
+    else
+    {
+      /* check DMA configuration, depending on multimode set or not,
+        or whether or not multimode feature is available */
+      if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
+      {
+        /* Multimode not set or feature not available or ADC independent */
+        if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
+        {
+          overrun_error = 1;  
+        }      
+      }
+      else
+      {
+        /* Multimode (when feature is available) is enabled, 
+           Common Control Register MDMA bits must be checked. */
+        if (ADC_MULTIMODE_DMA_ENABLED())
+        {
+          overrun_error = 1;  
+        }
+      }
+    }
+        
+    if (overrun_error == 1)
+    {
+      /* Change ADC state to error state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+      
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+      
+      /* Error callback */ 
+      HAL_ADC_ErrorCallback(hadc);
+    }
+
+    /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
+       old data is preserved until OVR is reset */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);  
+
+  }
+  
+  
+  /* ========== Check Injected context queue overflow flag ========== */
+  if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) 
+  {
+    /* Change ADC state to overrun state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+        
+    /* Set ADC error code to Injected context queue overflow */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+    
+    /* Clear the Injected context queue overflow flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+    
+    /* Error callback */
+    HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+  }
+  
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 1 callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC error callback in non-blocking mode
+  *         (ADC conversion with interruption or transfer by DMA).
+  * @note   In case of error due to overrun when using ADC with DMA transfer 
+  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on regular group
+      (+) Configure the analog watchdog
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group regular.
+  * @note   In case of usage of internal measurement channels:
+  *         Vbat/VrefInt/TempSensor.
+  *         These internal paths can be disabled using function 
+  *         HAL_ADC_DeInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes channel into ADC group regular,
+  *         following calls to this function can be used to reconfigure
+  *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+  *         without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_ChannelConfTypeDef".
+  * @param  hadc: ADC handle
+  * @param  sConfig: Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_Common_TypeDef *tmpADC_Common;
+  uint32_t tmpOffsetShifted;
+  __IO uint32_t wait_loop_index = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
+  assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+  
+  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is  
+     ignored (considered as reset) */
+  assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));  
+  
+  /* Verification of channel number */
+  if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+     assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel rank                                                          */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    
+      /* Regular sequence configuration */
+      /* Clear the old SQx bits then set the new ones for the selected rank */
+      /* For Rank 1 to 4 */
+      if (sConfig->Rank < 5)
+      {      
+        MODIFY_REG(hadc->Instance->SQR1, 
+                  ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank), 
+                  ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
+      }
+      /* For Rank 5 to 9 */
+      else if (sConfig->Rank < 10)
+      {
+        MODIFY_REG(hadc->Instance->SQR2, 
+                  ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank), 
+                  ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
+      }
+      /* For Rank 10 to 14 */
+      else if (sConfig->Rank < 15)
+      {
+        MODIFY_REG(hadc->Instance->SQR3, 
+                  ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank), 
+                  ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
+      }
+      /* For Rank 15 to 16 */
+      else
+      {   
+        MODIFY_REG(hadc->Instance->SQR4, 
+                  ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank), 
+                  ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
+      }
+      
+      
+      /* Parameters update conditioned to ADC state:                              */
+      /* Parameters that can be updated when ADC is disabled or enabled without   */
+      /* conversion on going on regular group:                                    */
+      /*  - Channel sampling time                                                 */
+      /*  - Channel offset                                                        */
+      if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+      {
+       
+        /* Channel sampling time configuration */
+        /* Clear the old sample time then set the new one for the selected channel */
+        /* For channels 10 to 18 */
+        if (sConfig->Channel >= ADC_CHANNEL_10)
+        {
+          ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
+        }
+        else /* For channels 0 to 9 */
+        {
+          ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
+        }
+      
+  
+       /* Configure the offset: offset enable/disable, channel, offset value */
+  
+       /* Shift the offset with respect to the selected ADC resolution. */
+       /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
+      
+       switch (sConfig->OffsetNumber)
+       {
+        /* Configure offset register i when applicable:                         */
+        /* - Enable offset                                                      */
+        /* - Set channel number                                                 */
+        /* - Set offset value                                                   */
+       case ADC_OFFSET_1:
+          MODIFY_REG(hadc->Instance->OFR1,
+                  ADC_OFR_FIELDS,
+                  ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                   
+         break;
+      
+       case ADC_OFFSET_2:
+         MODIFY_REG(hadc->Instance->OFR2,
+                  ADC_OFR_FIELDS, 
+                  ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
+         break;
+          
+       case ADC_OFFSET_3:
+         MODIFY_REG(hadc->Instance->OFR3,
+                  ADC_OFR_FIELDS,
+                  ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
+         break;
+      
+       case ADC_OFFSET_4:
+         MODIFY_REG(hadc->Instance->OFR4,
+                  ADC_OFR_FIELDS,
+                  ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
+         break;
+       
+       /* Case ADC_OFFSET_NONE */
+       default :
+       /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
+          If this is the case, offset OFRx is disabled since
+          sConfig->OffsetNumber = ADC_OFFSET_NONE. */
+         if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+         {
+           CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
+         }
+         if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+         {
+           CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
+         }
+         if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+         {
+           CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
+         }
+         if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+         {
+           CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
+         }
+         break;
+      }  /*  switch (sConfig->OffsetNumber) */
+    
+    }  /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
+    
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated only when ADC is disabled:                */
+    /*  - Single or differential mode                                           */
+    /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
+    if (ADC_IS_ENABLE(hadc) == RESET)
+    {
+      /* Configuration of differential mode */
+      if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+      {
+        /* Disable differential mode (default mode: single-ended) */
+        CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
+      }
+      else
+      {
+        /* Enable differential mode */
+        SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
+        
+        /* Sampling time configuration of channel ADC_IN+1 (negative input)     */
+        /* Clear the old sample time then set the new one for the selected      */
+        /* channel.                                                             */
+        /* Starting from channel 9, SMPR2 register must be configured           */
+        if (sConfig->Channel >= ADC_CHANNEL_9)
+        {
+          ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
+        }
+        else /* For channels 0 to 8, SMPR1 must be configured */
+        {
+          ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
+        }
+      }
+    
+    
+      
+      /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
+      /* If internal channel selected, enable dedicated internal buffers and    */
+      /*  paths.                                                                */
+      /* Note: these internal measurement paths can be disabled using           */
+      /* HAL_ADC_DeInit().                                                      */
+         
+      /* Configuration of common ADC parameters                                 */
+      tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+    
+  
+      /* If the requested internal measurement path has already been enabled,   */
+      /* bypass the configuration processing.                                   */
+      if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+            (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
+          ( (sConfig->Channel == ADC_CHANNEL_VBAT)       &&
+            (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
+          ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
+            (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
+         )
+      {
+        /* Configuration of common ADC parameters (continuation)                */
+  
+        /* Software is allowed to change common parameters only when all ADCs   */
+        /* of the common group are disabled.                                    */
+        if ((ADC_IS_ENABLE(hadc) == RESET)   &&
+           (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
+        {
+          if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+          {
+            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 
+            {
+              SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
+            
+              /* Delay for temperature sensor stabilization time */
+              /* Wait loop initialization and execution */
+              /* Note: Variable divided by 2 to compensate partially          */
+              /*       CPU processing cycles.                                 */
+              wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
+              while(wait_loop_index != 0)
+              {
+                wait_loop_index--;
+              }
+            }
+          }
+          else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+          {
+            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+            {
+              SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
+            }
+          }
+          else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+          { 
+            if (ADC_VREFINT_INSTANCE(hadc))
+            {
+              SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
+            }        
+          }
+        }
+        /* If the requested internal measurement path has already been          */
+        /* enabled and other ADC of the common group are enabled, internal      */
+        /* measurement paths cannot be enabled.                                 */
+        else  
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+          
+          tmp_hal_status = HAL_ERROR;
+        }
+      }
+    
+    } /* if (ADC_IS_ENABLE(hadc) == RESET) */
+    
+  } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
+  
+  /* If a conversion is on going on regular group, no update on regular       */
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Configure the analog watchdog.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the selected analog watchdog, successive  
+  *         calls to this function can be used to reconfigure some parameters 
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting 
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_AnalogWDGConfTypeDef".
+  * @note   Analog watchdog thresholds can be modified while ADC conversion
+  *         is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
+  * @param  hadc: ADC handle
+  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  uint32_t tmpAWDHighThresholdShifted;
+  uint32_t tmpAWDLowThresholdShifted;
+  
+  uint32_t tmpADCFlagAWD2orAWD3;
+  uint32_t tmpADCITAWD2orAWD3;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+  
+  if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
+     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
+     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
+  }
+
+  /* Verify if threshold is within the selected ADC resolution */
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular and injected groups:                      */
+  /*  - Analog watchdog channels                                              */
+  /*  - Analog watchdog thresholds                                            */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+  {
+    
+    /* Analog watchdogs configuration */
+    if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+    {
+      /* Configuration of analog watchdog:                                    */
+      /*  - Set the analog watchdog enable mode: regular and/or injected      */
+      /*    groups, one or overall group of channels.                         */
+      /*  - Set the Analog watchdog channel (is not used if watchdog          */
+      /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                         */
+        MODIFY_REG(hadc->Instance->CFGR,  ADC_CFGR_WD_FIELDS, 
+              AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );                                  
+
+      /* Shift the offset with respect to the selected ADC resolution:         */
+      /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
+      /* are set to 0                                                         */ 
+      tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+      tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+      
+      /* Set the high and low thresholds */
+      MODIFY_REG(hadc->Instance->TR1,
+                 ADC_TR1_HT1 | ADC_TR1_LT1,
+                 ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                  
+      
+      /* Clear the ADC Analog watchdog flag (in case of left enabled by         */
+      /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler()   */
+      /* or HAL_ADC_PollForEvent().                                             */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
+      
+      /* Configure ADC Analog watchdog interrupt */
+      if(AnalogWDGConfig->ITMode == ENABLE)
+      {
+        /* Enable the ADC Analog watchdog interrupt */
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
+      }
+      else
+      {
+        /* Disable the ADC Analog watchdog interrupt */
+        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
+      }
+      
+      /* Update state, clear previous result related to AWD1 */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+    }
+    /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+    else
+    {
+    /* Shift the threshold with respect to the selected ADC resolution         */
+    /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0    */
+      tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+      tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+      if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+      {
+        /* Set the Analog watchdog channel or group of channels. This also    */
+        /* enables the watchdog.                                              */
+        /* Note: Conditional register reset, because several channels can be  */
+        /*       set by successive calls of this function.                    */
+        if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
+        {
+          SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
+        }
+        else
+        {
+          CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+        }
+        
+        /* Set the high and low thresholds */
+        MODIFY_REG(hadc->Instance->TR2,  ADC_TR2_HT2 | ADC_TR2_LT2, 
+                   ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                      
+        
+        /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
+        /* settings.                                                          */
+        tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
+        tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
+        
+        /* Update state, clear previous result related to AWD2 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+      }
+      /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+      else
+      {
+        /* Set the Analog watchdog channel or group of channels. This also    */
+        /* enables the watchdog.                                              */
+        /* Note: Conditional register reset, because several channels can be */
+        /*       set by successive calls of this function.                    */
+        if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) 
+        {
+          SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
+        }
+        else
+        {
+          CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+        }
+        
+        /* Set the high and low thresholds */
+        MODIFY_REG(hadc->Instance->TR3,  ADC_TR3_HT3 | ADC_TR3_LT3, 
+                   ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                    
+        
+        /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
+        /* settings.                                                          */
+        tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
+        tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
+        
+        /* Update state, clear previous result related to AWD3 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+      }
+      
+      /* Clear the ADC Analog watchdog flag (in case left enabled by          */
+      /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
+      /* or HAL_ADC_PollForEvent().                                           */
+      __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
+
+      /* Configure ADC Analog watchdog interrupt */
+      if(AnalogWDGConfig->ITMode == ENABLE)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
+      }
+      else
+      {
+        __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
+      }
+    }
+    
+  }
+  /* If a conversion is on going on regular or injected groups, no update     */
+  /* could be done on neither of the AWD configuration structure parameters.  */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ *  @brief    ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral state and errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions to get in run-time the status of the  
+    peripheral.
+      (+) Check the ADC state
+      (+) Check the ADC error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ADC handle state.
+  * @note   ADC state machine is managed by bitfields, ADC status must be 
+  *         compared with states bits.
+  *         For example:                                                         
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
+  * @param  hadc: ADC handle
+  * @retval ADC handle state (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Return ADC handle state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code.
+  * @param  hadc: ADC handle
+  * @retval ADC error code (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Stop ADC conversion.
+  * @param  hadc: ADC handle
+  * @param  ConversionGroup: ADC group regular and/or injected.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
+  *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
+  *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
+{
+  uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
+  uint32_t tickstart = 0;
+  uint32_t Conversion_Timeout_CPU_cycles = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+    
+  /* Verification if ADC is not already stopped (on regular and injected      */
+  /* groups) to bypass this function if not needed.                           */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
+  {
+    /* Particular case of continuous auto-injection mode combined with        */
+    /* auto-delay mode.                                                       */
+    /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
+    /* injected group stop ADC_CR_JADSTP).                                    */
+    /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
+    /* (see reference manual).                                                */
+    if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) 
+         && (hadc->Init.ContinuousConvMode==ENABLE) 
+         && (hadc->Init.LowPowerAutoWait==ENABLE))
+    {
+      /* Use stop of regular group */
+      ConversionGroup = ADC_REGULAR_GROUP;
+      
+      /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+      while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
+      {
+        if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+          
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+          
+          return HAL_ERROR;
+        }
+        Conversion_Timeout_CPU_cycles ++;
+      }
+      
+      /* Clear JEOS */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+    }
+    
+    /* Stop potential conversion on going on regular group */
+    if (ConversionGroup != ADC_INJECTED_GROUP)
+    {
+      /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+      if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 
+          HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)     )
+      {
+        /* Stop conversions on regular group */
+        SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
+      }
+    }
+    
+    /* Stop potential conversion on going on injected group */
+    if (ConversionGroup != ADC_REGULAR_GROUP)
+    {
+      /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+      if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && 
+          HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)      )
+      {
+        /* Stop conversions on injected group */
+        SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
+      }   
+    }
+    
+    /* Selection of start and stop bits with respect to the regular or injected group */
+    switch(ConversionGroup)
+    {
+    case ADC_REGULAR_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+        break;
+    case ADC_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+        break;
+    /* Case ADC_REGULAR_GROUP only*/
+    default:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+        break;
+    }
+    
+    /* Wait for conversion effectively stopped */
+    
+    
+    tickstart = HAL_GetTick();
+      
+    while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
+    {
+      if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+  } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
+  
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief  Enable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC must be disabled
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0;
+  
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    /* Check if conditions to enable the ADC are fulfilled */
+    if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+      
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+      return HAL_ERROR;
+    }
+    
+    /* Enable the ADC peripheral */
+    ADC_ENABLE(hadc);
+    
+    
+    /* Wait for ADC effectively enabled */
+    tickstart = HAL_GetTick();  
+    
+    while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
+    {
+      /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit 
+          has been cleared (after a calibration), ADEN bit is reset by the 
+          calibration logic.
+			    The workaround is to continue setting ADEN until ADRDY is becomes 1.
+          Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+          4 ADC clock cycle duration */
+      ADC_ENABLE(hadc);
+
+      if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
+      {  
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+        return HAL_ERROR;
+      }
+    }
+  }
+   
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0;
+  
+  /* Verification if ADC is not already disabled:                             */
+  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+  /*       disabled.                                                          */
+  if (ADC_IS_ENABLE(hadc) != RESET)
+  {
+    /* Check if conditions to disable the ADC are fulfilled */
+    if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
+    {
+      /* Disable the ADC peripheral */
+      ADC_DISABLE(hadc);
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+      
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+      return HAL_ERROR;
+    }
+     
+    /* Wait for ADC effectively disabled */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+    
+    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+    {
+      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        
+        return HAL_ERROR;
+      }
+    }
+  }
+  
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA)))
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    /* Is it the end of the regular sequence ? */
+    if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
+    {
+      /* Are conversions software-triggered ? */
+      if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
+      {
+        /* Is CONT bit set ? */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
+        {
+          /* CONT bit is not set, no more conversions expected */
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+          if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+          { 
+            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* DMA End of Transfer interrupt was triggered but conversions sequence
+         is not over. If DMACFG is set to 0, conversions are stopped. */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
+      {
+        /* DMACFG bit is not set, conversions are stopped. */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+        { 
+          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+        }
+      }
+    }
+    
+    /* Conversion complete callback */
+    HAL_ADC_ConvCpltCallback(hadc);
+  }
+  else /* DMA or internal error occurred (or both) */
+  {
+    /* In case of internal error, */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* call Error Callback function */
+      HAL_ADC_ErrorCallback(hadc);
+    }
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Half conversion callback */
+  HAL_ADC_ConvHalfCpltCallback(hadc); 
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+  
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+  
+  /* Error callback */
+  HAL_ADC_ErrorCallback(hadc); 
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h
new file mode 100755
index 0000000..bd11ed3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h
@@ -0,0 +1,1057 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_adc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_ADC_H
+#define __STM32L4xx_HAL_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  ADC group regular oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
+
+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
+                                               This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */
+
+  uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
+                                               The oversampling is either temporary stopped or reset upon an injected
+                                               sequence interruption. 
+                                               If oversampling is enabled on both regular and injected groups, this parameter 
+                                               is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 
+                                               (the oversampling buffer is zeroed during injection sequence).   
+                                               This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */                                               
+}ADC_OversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC instance and ADC group regular.
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+  *            ScanConvMode, EOCSelection, LowPowerAutoWait.
+  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
+  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
+  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
+  *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter 
+  *         (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLLSAI1/PLLSAI2 clocks) and clock prescaler.
+                                       This parameter can be a value of @ref ADC_ClockPrescaler.
+                                       Note: The clock is common for all the ADCs.
+                                       Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 
+                                             AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
+                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
+                                             if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 
+                                             must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
+                                       Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level.
+                                       Note: This parameter can be modified only if all ADCs are disabled. */
+
+  uint32_t Resolution;            /*!< Configure the ADC resolution. 
+                                       This parameter can be a value of @ref ADC_Resolution */
+
+  uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
+                                       Refer to reference manual for alignments formats versus resolutions.
+                                       This parameter can be a value of @ref ADC_Data_align */
+
+  uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
+                                                    Scan direction is upward: from rank 1 to rank 'n'.
+                                       This parameter can be a value of @ref ADC_Scan_mode */
+
+  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
+                                       This parameter can be a value of @ref ADC_EOCSelection. */
+
+  uint32_t LowPowerAutoWait;      /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
+                                       conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
+                                       using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
+                                       This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
+                                       for low frequency applications. 
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
+                                             to free the IRQ vector sequencer.
+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
+                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
+                                             (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+
+  uint32_t ContinuousConvMode;    /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
+                                       after the first ADC conversion start trigger occurred (software start or external trigger).
+                                       This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.
+                                       To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+                                       Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 
+                                       continuous mode or external trigger that could launch a conversion). */
+
+  uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
+                                       (main sequence subdivided in successive parts).
+                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                       This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
+                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+
+  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
+                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
+                                       Caution: external trigger source is common to all ADC instances. */
+                                                                                                        
+  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
+                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+  uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
+                                       or in continuous mode (DMA transfer unlimited, whatever number of conversions).
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
+
+  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+                                       This parameter applies to ADC group regular only.
+                                       This parameter can be a value of @ref ADC_Overrun.
+                                       Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 
+                                       end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 
+                                       HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
+                                       Note: Error reporting with respect to the conversion mode:
+                                             - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 
+                                               overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
+                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+
+  uint32_t OversamplingMode;              /*!< Specify whether the oversampling feature is enabled or disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
+
+  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
+                                               Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+  uint32_t DFSDMConfig;           /*!< Specify whether ADC conversion data is sent directly to DFSDM.
+                                       This parameter can be a value of @ref ADCEx_DFSDM_Mode_Configuration.
+                                       Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */                                               
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */                                                                                          
+}ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of ADC channel for regular group
+  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+  *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
+  *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter 
+  *        (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_channels
+                                        Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+  uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
+                                        This parameter can be a value of @ref ADC_regular_rank
+                                        Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 
+                                        the new channel setting (or parameter number of conversions adjusted) */
+
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time
+                                        (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_sampling_times
+                                        Caution: This parameter applies to a channel that can be used into regular and/or injected group.
+                                                 It overwrites the last setting.
+                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                              Refer to device datasheet for timings values. */
+
+  uint32_t SingleDiff;             /*!< Select single-ended or differential input.
+                                        In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+                                                              Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+                                        This parameter must be a value of @ref ADCEx_SingleDifferential
+                                        Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+                                                 It overwrites the last setting.
+                                        Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
+                                        Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+                                        Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                              If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 
+                                        of another parameter update on the fly) */
+
+  uint32_t OffsetNumber;           /*!< Select the offset number
+                                        This parameter can be a value of @ref ADCEx_OffsetNumber
+                                        Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
+
+  uint32_t Offset;                 /*!< Define the offset to be subtracted from the raw converted data.
+                                        Offset value must be a positive number.
+                                        Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 
+                                        0x3FF, 0xFF or 0x3F respectively.
+                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 
+                                              without continuous mode or external trigger that could launch a conversion). */
+}ADC_ChannelConfTypeDef;
+
+/**
+  * @brief  Structure definition of ADC analog watchdog
+  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+  *         ADC state can be either:
+  *         ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
+  */
+typedef struct
+{
+  uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
+                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+                                   This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
+
+  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected.
+                                   For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset 
+                                   channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
+                                   This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
+
+  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
+                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+                                   This parameter can be a value of @ref ADC_channels. */
+
+  uint32_t ITMode;            /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+                                   between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 
+                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
+
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+                                   between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 
+                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
+}ADC_AnalogWDGConfTypeDef;
+
+/** @defgroup ADC_States ADC States
+  * @{
+  */
+
+/** 
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  * @note   ADC state machine is managed by bitfields, state must be compared
+  *         with bit by bit.
+  *         For example:                                                         
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
+  */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy due to an internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         ((uint32_t)0x00000800)    /*!< Not available on this STM32 serie: End Of Sampling flag raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF         ((uint32_t)0x00004000)    /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */
+#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                    */
+#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error (problem of clocking,
+                                                          enable/disable, erroneous state, ...)       */
+#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                               */
+#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                          */
+#define HAL_ADC_ERROR_JQOVF       ((uint32_t)0x08)   /*!< Injected context queue overflow error       */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler
+  * @{
+  */
+#define ADC_CLOCK_SYNC_PCLK_DIV1      ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided  */
+#define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC_CCR_CKMODE)   /*!< ADC synchronous clock derived from AHB clock divided by 4 */
+
+#define ADC_CLOCKPRESCALER_PCLK_DIV1   ADC_CLOCK_SYNC_PCLK_DIV1    /*!< Obsolete naming, kept for compatibility with some other devices */
+#define ADC_CLOCKPRESCALER_PCLK_DIV2   ADC_CLOCK_SYNC_PCLK_DIV2    /*!< Obsolete naming, kept for compatibility with some other devices */
+#define ADC_CLOCKPRESCALER_PCLK_DIV4   ADC_CLOCK_SYNC_PCLK_DIV4    /*!< Obsolete naming, kept for compatibility with some other devices */
+
+#define ADC_CLOCK_ASYNC_DIV1       ((uint32_t)0x00000000)                                        /*!< ADC asynchronous clock not divided    */
+#define ADC_CLOCK_ASYNC_DIV2       ((uint32_t)ADC_CCR_PRESC_0)                                   /*!< ADC asynchronous clock divided by 2   */
+#define ADC_CLOCK_ASYNC_DIV4       ((uint32_t)ADC_CCR_PRESC_1)                                   /*!< ADC asynchronous clock divided by 4   */
+#define ADC_CLOCK_ASYNC_DIV6       ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 6   */
+#define ADC_CLOCK_ASYNC_DIV8       ((uint32_t)(ADC_CCR_PRESC_2))                                 /*!< ADC asynchronous clock divided by 8   */
+#define ADC_CLOCK_ASYNC_DIV10      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 10  */
+#define ADC_CLOCK_ASYNC_DIV12      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 12  */
+#define ADC_CLOCK_ASYNC_DIV16      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16  */
+#define ADC_CLOCK_ASYNC_DIV32      ((uint32_t)(ADC_CCR_PRESC_3))                                 /*!< ADC asynchronous clock divided by 32  */
+#define ADC_CLOCK_ASYNC_DIV64      ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 64  */
+#define ADC_CLOCK_ASYNC_DIV128     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 128 */
+#define ADC_CLOCK_ASYNC_DIV256     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Resolution ADC Resolution
+  * @{
+  */
+#define ADC_RESOLUTION_12B      ((uint32_t)0x00000000)          /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION_10B      ((uint32_t)ADC_CFGR_RES_0)      /*!< ADC 10-bit resolution */
+#define ADC_RESOLUTION_8B       ((uint32_t)ADC_CFGR_RES_1)      /*!< ADC 8-bit resolution */
+#define ADC_RESOLUTION_6B       ((uint32_t)ADC_CFGR_RES)        /*!< ADC 6-bit resolution */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Data_align ADC conversion data alignment
+  * @{
+  */
+#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)         /*!< Data right alignment */
+#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CFGR_ALIGN)     /*!< Data left alignment  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+  * @{
+  */
+#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_EXTERNALTRIG_T1_CC1           ((uint32_t)0x00000000)                                                  /*!< Event 0 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)                                           /*!< Event 1 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)                                           /*!< Event 2 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))                     /*!< Event 3 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)                                           /*!< Event 4 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))                     /*!< Event 5 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))                     /*!< Event 6 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T8_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 7 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T8_TRGO2         ((uint32_t) ADC_CFGR_EXTSEL_3)                                          /*!< Event 8 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))                     /*!< Event 9 triggers regular group conversion start  */
+#define ADC_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))                     /*!< Event 10 triggers regular group conversion start */
+#define ADC_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 11 triggers regular group conversion start */
+#define ADC_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))                     /*!< Event 12 triggers regular group conversion start */
+#define ADC_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */
+#define ADC_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */
+#define ADC_EXTERNALTRIG_T3_CC4           ((uint32_t)ADC_CFGR_EXTSEL)                                             /*!< Event 15 triggers regular group conversion start */
+#define ADC_SOFTWARE_START                ((uint32_t)0x00000001)                                                  /*!< Software triggers regular group conversion start */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)        /*!< Regular conversions hardware trigger detection disabled */
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR_EXTEN_0)  /*!< Regular conversions hardware trigger detection on the rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR_EXTEN_1)  /*!< Regular conversions hardware trigger detection on the falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR_EXTEN)    /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+  * @{
+  */
+#define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
+#define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
+#define ADC_EOC_SINGLE_SEQ_CONV     ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))  /*!< Reserved for future use */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Overrun ADC overrun
+  * @{
+  */
+#define ADC_OVR_DATA_PRESERVED             ((uint32_t)0x00000000)           /*!< Data preserved in case of overrun   */
+#define ADC_OVR_DATA_OVERWRITTEN           ((uint32_t)ADC_CFGR_OVRMOD)      /*!< Data overwritten in case of overrun */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank ADC group regular sequencer rank
+  * @{
+  */
+#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */
+#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */
+#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */
+#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */
+#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */
+#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */
+#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */
+#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */
+#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */
+#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */
+#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */
+#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */
+#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */
+#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */
+#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */
+#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels ADC channels
+  * @{
+  */
+#define ADC_CHANNEL_0           ((uint32_t)(0x00000000))                                                            /*!< ADC channel 0  */
+#define ADC_CHANNEL_1           ((uint32_t)(ADC_SQR3_SQ10_0))                                                       /*!< ADC channel 1  */
+#define ADC_CHANNEL_2           ((uint32_t)(ADC_SQR3_SQ10_1))                                                       /*!< ADC channel 2  */
+#define ADC_CHANNEL_3           ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 3  */
+#define ADC_CHANNEL_4           ((uint32_t)(ADC_SQR3_SQ10_2))                                                       /*!< ADC channel 4  */
+#define ADC_CHANNEL_5           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 5  */
+#define ADC_CHANNEL_6           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 6  */
+#define ADC_CHANNEL_7           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 7  */
+#define ADC_CHANNEL_8           ((uint32_t)(ADC_SQR3_SQ10_3))                                                       /*!< ADC channel 8  */
+#define ADC_CHANNEL_9           ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 9  */
+#define ADC_CHANNEL_10          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 10 */
+#define ADC_CHANNEL_11          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 11 */
+#define ADC_CHANNEL_12          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))                                     /*!< ADC channel 12 */
+#define ADC_CHANNEL_13          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 13 */
+#define ADC_CHANNEL_14          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))                   /*!< ADC channel 14 */
+#define ADC_CHANNEL_15          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 15 */
+#define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ10_4))                                                       /*!< ADC channel 16 */
+#define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 17 */
+#define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 18 */
+
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on all ADC's
+         (information present in Reference Manual) */ 
+#define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_17                                                                      /*!< ADC temperature sensor channel */
+#define ADC_CHANNEL_VBAT        ADC_CHANNEL_18                                                                      /*!< ADC Vbat channel               */
+#define ADC_CHANNEL_VREFINT     ADC_CHANNEL_0                                                                       /*!< ADC Vrefint channel            */
+
+#if defined(ADC1) && !defined(ADC2)
+#define ADC_CHANNEL_DAC1CH1             (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, they cannot be used both simultenaeously. */
+#define ADC_CHANNEL_DAC1CH2             (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, they cannot be used both simultenaeously. */
+#elif defined(ADC2)
+#define ADC_CHANNEL_DAC1CH1_ADC2        (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
+#define ADC_CHANNEL_DAC1CH2_ADC2        (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
+#if defined(ADC3)
+#define ADC_CHANNEL_DAC1CH1_ADC3        (ADC_CHANNEL_14) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
+#define ADC_CHANNEL_DAC1CH2_ADC3        (ADC_CHANNEL_15) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
+#endif
+#endif
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macro ADC Private Macros
+  * @{
+  */
+
+/**
+  * @brief Test if conversion trigger of regular group is software start
+  *        or external trigger.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                        \
+       (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
+
+/**
+  * @brief Return resolution bits in CFGR register RES[1:0] field.
+  * @param __HANDLE__: ADC handle.
+  * @retval 2-bit field RES of CFGR register.
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
+
+/**
+  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+  * @param __HANDLE__: ADC handle.
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 
+
+/**
+  * @brief Verification of ADC state: enabled or disabled.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (ADC enabled) or RESET (ADC disabled)
+  */
+#define ADC_IS_ENABLE(__HANDLE__)                                                    \
+       (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
+        ) ? SET : RESET)
+
+/**
+  * @brief Check if conversion is on going on regular group.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (conversion is on going) or RESET (no conversion is on going)
+  */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                    \
+       (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET             \
+        ) ? RESET : SET)
+
+/**
+  * @brief Simultaneously clear and set specific bits of the handle State.
+  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.    
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Verify that a given value is aligned with the ADC resolution range.
+  * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
+  * @param __ADC_VALUE__: value checked against the resolution.     
+  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+  */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                         \
+   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))   )
+
+/**
+  * @brief Verify the length of the scheduled regular conversions group.
+  * @param __LENGTH__: number of programmed conversions.   
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
+  */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
+
+
+/**
+  * @brief Verify the number of scheduled regular conversions in discontinuous mode.
+  * @param NUMBER: number of scheduled regular conversions in discontinuous mode.  
+  * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
+  */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+
+
+/**
+  * @brief Verify the ADC clock setting.
+  * @param __ADC_CLOCK__: programmed ADC clock. 
+  * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
+  */
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )  
+	
+
+/**
+  * @brief Verify the ADC resolution setting.
+  * @param __RESOLUTION__: programmed ADC resolution. 
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
+                             
+/**                          
+  * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
+  * @param __RESOLUTION__: programmed ADC resolution when limited to 6 or 8 bits. 
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */ 
+#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
+
+/**
+  * @brief Verify the ADC converted data alignment.
+  * @param __ALIGN__: programmed ADC converted data alignment. 
+  * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
+  */ 		
+#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
+                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )
+	
+
+/**
+  * @brief Verify the ADC scan mode.
+  * @param __SCAN_MODE__: programmed ADC scan mode.
+  * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+  */ 	
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )	
+									 
+/**
+  * @brief Verify the ADC edge trigger setting for regular group.
+  * @param __EDGE__: programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */ 									 
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
+
+/**
+  * @brief Verify the ADC regular conversions external trigger.
+  * @param __REGTRIG__: programmed ADC regular conversions external trigger.
+  * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
+  */ 
+#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)   || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)   || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)   || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)   || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)  || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)   || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)  || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)  || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)  || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)  || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)  || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)   || \
+                                                                                 \
+                                     ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+
+/**
+  * @brief Verify the ADC regular conversions check for converted data availability.
+  * @param __EOC_SELECTION__: converted data availability check.
+  * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
+  */ 								 
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
+                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)       || \
+                                                 ((__EOC_SELECTION__) == ADC_EOC_SINGLE_SEQ_CONV)  )
+	
+/**
+  * @brief Verify the ADC regular conversions overrun handling.
+  * @param __OVR__: ADC regular conversions overrun handling.
+  * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+  */ 		
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
+                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )	                                   
+	
+/**
+  * @brief Verify the ADC conversions sampling time.
+  * @param __TIME__: ADC conversions sampling time.
+  * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
+  */
+#if defined (ADC_SMPR1_SMPPLUS) 
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
+                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
+#else
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
+                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
+#endif
+
+/**
+  * @brief Verify the ADC regular channel setting.
+  * @param __CHANNEL__: programmed ADC regular channel. 
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
+
+/**
+  * @}
+  */
+  
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Fixed timeout values for ADC conversion (including sampling time)        */
+/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111        */
+/* Maximum conversion time is 12.5 + Maximum sampling time                  */
+/*                       or 12.5  + 640.5 = 653 ADC clock cycles            */
+/* Minimum ADC Clock frequency is 0.14 MHz                                  */
+/* Maximum conversion time is                                               */
+/*              653 / 0.14 MHz = 4.66 ms                                    */
+#define ADC_STOP_CONVERSION_TIMEOUT     ((uint32_t) 5)      /*!< ADC stop time-out value */ 
+
+/* Delay for temperature sensor stabilization time.                         */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
+/* Unit: us                                                                 */
+#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 120)
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+         
+/** @defgroup ADC_Exported_Macro ADC Exported Macros
+  * @{
+  */
+
+/** @brief  Reset ADC handle state.
+  * @param  __HANDLE__: ADC handle.
+  * @retval None
+  */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)                                                                        
+         
+         
+/** @brief  Check whether the specified ADC interrupt source is enabled or not.
+  * @param __HANDLE__: ADC handle.
+  * @param __INTERRUPT__: ADC interrupt source to check
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
+  *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3,   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source.  
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+    (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)      \
+     )? SET : RESET                                                            \
+    )
+
+/**
+  * @brief Enable an ADC interrupt.
+  * @param __HANDLE__: ADC handle.
+  * @param __INTERRUPT__: ADC Interrupt to enable
+   *          This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
+  *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3,  ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source. 
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief Disable an ADC interrupt.
+  * @param __HANDLE__: ADC handle.
+  * @param __INTERRUPT__: ADC Interrupt to disable
+  *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
+  *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3,   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source. 
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+  * @brief Check whether the specified ADC flag is set or not.
+  * @param __HANDLE__: ADC handle.
+  * @param __FLAG__: ADC flag to check
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY,     ADC Ready (ADRDY) flag                              
+  *            @arg @ref ADC_FLAG_EOSMP,   ADC End of Sampling flag                            
+  *            @arg @ref ADC_FLAG_EOC,     ADC End of Regular Conversion flag                  
+  *            @arg @ref ADC_FLAG_EOS,     ADC End of Regular sequence of Conversions flag     
+  *            @arg @ref ADC_FLAG_OVR,     ADC overrun flag        
+  *            @arg @ref ADC_FLAG_JEOC,    ADC End of Injected Conversion flag                 
+  *            @arg @ref ADC_FLAG_JEOS,    ADC End of Injected sequence of Conversions flag    
+  *            @arg @ref ADC_FLAG_AWD1,    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2,    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3,    ADC Analog watchdog 3 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_JQOVF,   ADC Injected Context Queue Overflow flag.            
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Clear a specified ADC flag.
+  * @param __HANDLE__: ADC handle.
+  * @param __FLAG__: ADC flag to clear
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY,     ADC Ready (ADRDY) flag                              
+  *            @arg @ref ADC_FLAG_EOSMP,   ADC End of Sampling flag                            
+  *            @arg @ref ADC_FLAG_EOC,     ADC End of Regular Conversion flag                  
+  *            @arg @ref ADC_FLAG_EOS,     ADC End of Regular sequence of Conversions flag     
+  *            @arg @ref ADC_FLAG_OVR,     ADC overrun flag        
+  *            @arg @ref ADC_FLAG_JEOC,    ADC End of Injected Conversion flag                 
+  *            @arg @ref ADC_FLAG_JEOS,    ADC End of Injected sequence of Conversions flag    
+  *            @arg @ref ADC_FLAG_AWD1,    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2,    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3,    ADC Analog watchdog 3 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_JQOVF,   ADC Injected Context Queue Overflow flag.   
+  * @note  Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR).
+  * @retval None
+  */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+       
+
+/**
+  * @}
+  */
+
+/* Include ADC HAL Extended module */
+#include "stm32l4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @brief    IO operation functions 
+  * @{
+  */
+/* IO operation functions  *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+
+/**
+  * @}
+  */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c
new file mode 100755
index 0000000..e43572a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c
@@ -0,0 +1,2315 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          peripheral:
+  *           + Operation functions
+  *             ++ Start, stop, get result of conversions of injected
+  *                group, using 2 possible modes: polling, interruption.
+  *             ++ Calibration
+  *               +++ ADC automatic self-calibration
+  *               +++ Calibration factors get or set
+  *             ++ Multimode feature when available
+  *           + Control functions
+  *             ++ Channels configuration on injected group
+  *           + State functions
+  *             ++ Injected group queues management
+  *          Other functions (generic functions) are available in file 
+  *          "stm32l4xx_hal_adc.c".
+  *
+  @verbatim
+  [..] 
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32l4xx_hal_adc.c".
+  [..]
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  * @{
+  */
+
+#define ADC_JSQR_FIELDS  ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+                                     ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
+                                      ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
+                                                                             once the ADC is enabled */
+                                      
+#define ADC_CFGR2_INJ_FIELDS  ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR  |\
+                                       ADC_CFGR2_OVSS ))     /*!< ADC_CFGR2 injected oversampling parameters that can be updated
+                                                                  when no conversion is on-going (neither regular nor injected) */
+                                       
+/* Fixed timeout value for ADC calibration.                                   */
+/* Values defined to be higher than worst cases: low clock frequency,         */
+/* maximum prescalers.                                                        */
+/* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value             */
+/* according to Data sheet), calibration_time MAX = 112 / f_ADC               */
+/*           112 / 140,000 = 0.8 ms                                           */
+/* At maximum CPU speed (80 MHz), this means                                  */
+/*    0.8 ms * 80 MHz = 64000 CPU cycles                                      */  
+#define ADC_CALIBRATION_TIMEOUT         ((uint32_t) 64000)    /*!< ADC calibration time-out value */ 
+                                    
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @brief    Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      
+      (+) Perform the ADC self-calibration for single or differential ending.
+      (+) Get calibration factors for single or differential ending.
+      (+) Set calibration factors for single or differential ending.
+      
+      (+) Start conversion of injected group.
+      (+) Stop conversion of injected group.
+      (+) Poll for conversion complete on injected group.
+      (+) Get result of injected channel conversion.
+      (+) Start conversion of injected group and enable interruptions.
+      (+) Stop conversion of injected group and disable interruptions.
+      
+      (+) When multimode feature is available, start multimode and enable DMA transfer.
+      (+) Stop multimode and disable ADC DMA transfer.
+      (+) Get result of multimode conversion.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @param  hadc       ADC handle
+  * @param  SingleDiff Selection of single-ended or differential input
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t WaitLoopIndex = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Calibration prerequisite: ADC must be disabled. */
+  
+  /* Disable the ADC (if not already disabled) */
+  tmp_hal_status = ADC_Disable(hadc);
+  
+  /* Check if ADC is effectively disabled */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Change ADC state */
+    /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
+    ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
+    
+    /* Select calibration mode single ended or differential ended */
+    MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
+    
+    /* Start ADC calibration */
+    SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
+    
+    /* Wait for calibration completion */
+    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
+    {
+      WaitLoopIndex++;
+      if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Note: No need to update variable "tmp_hal_status" here: already set    */
+    /*       to state "HAL_ERROR" by function disabling the ADC.              */
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get the calibration factor from automatic conversion result.
+  * @param  hadc: ADC handle.
+  * @param  SingleDiff: Selection of single-ended or differential input
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @retval Converted value
+  */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
+  
+  /* Return the selected ADC calibration value */ 
+  if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+  {
+    return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
+  }
+  else
+  {
+    return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
+  }
+}
+
+/**
+  * @brief  Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
+  * @param  hadc: ADC handle.
+  * @param  SingleDiff: Selection of single-ended or differential input.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @param  CalibrationFactor: Calibration factor (coded on 7 bits maximum)
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
+  assert_param(IS_ADC_CALFACT(CalibrationFactor)); 
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Verification of hardware constraints before modifying the calibration    */
+  /* factors register: ADC must be enabled, no conversion on going.           */
+  if ( (ADC_IS_ENABLE(hadc) != RESET)                            &&
+       (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)  )
+  {
+    /* Set the selected ADC calibration value */
+    if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+    {
+      MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
+    }
+    else
+    {
+      MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
+    }
+  }
+  else
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    /* Update ADC state machine to error */
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of injected group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled when multimode feature is available: 
+  *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first, 
+  *         then for ADC master. 
+  *         For ADC slave, ADC is enabled only (conversion is not started).  
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param  hadc: ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;  
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+  
+    /* In case of software trigger detection enabled, JQDIS must be set 
+      (which can be done only if ADSTART and JADSTART are both cleared).
+       If JQDIS is not set at that point, returns an error
+       - since software trigger detection is disabled. User needs to
+       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.  
+       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 
+         the queue is empty */
+    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)   
+    && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))  
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
+      return HAL_ERROR;
+    }
+
+    
+    /* Process locked */
+    __HAL_LOCK(hadc);
+      
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
+      {
+        /* Reset ADC error code field related to injected conversions only */
+        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);             
+      }
+      else
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+      /* Update ADC state */
+      /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
+      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
+      
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - by default if ADC is Master or Independent or if multimode feature is not available
+        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
+      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+      
+      
+      /* Clear injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+      
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started).                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+      
+      /* Are injected conversions that of a dual Slave ? */
+      if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
+      {
+        /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
+           set ADSTART only if JAUTO is cleared */
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);            
+        if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
+        {
+          SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
+        }
+      }
+      else
+      {
+        /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
+           ADSTART is not set */
+          SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+      }
+    } 
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);    
+    } /* if (tmp_hal_status == HAL_OK) */
+  
+    /* Return function status */
+    return tmp_hal_status;
+  } /*  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
+}
+
+/**
+  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+  *         no regular conversion is on going.
+  * @note   If ADC must be disabled and if conversion is on going on 
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   In case of multimode enabled (when multimode feature is available), 
+  *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled. 
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @param  hadc: ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+  
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on regular group is on-going                       */
+  if (tmp_hal_status == HAL_OK)
+  {
+    if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+      
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Change ADC state */
+      /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
+      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Clear HAL_ADC_STATE_INJ_BUSY bit */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for injected group conversion to be completed.
+  * @param  hadc: ADC handle
+  * @param  Timeout: Timeout value in millisecond.
+  * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+  *         checked and cleared depending on AUTDLY bit status.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t           tickstart;
+  uint32_t           tmp_Flag_End        = 0x00;
+  ADC_TypeDef        *tmpADC_Master;
+  uint32_t           tmp_cfgr            = 0x00;
+  uint32_t           tmp_cfgr_jqm_autdly = 0x00;
+  uint32_t           tmp_jeos_raised     = 0x01; /* by default, assume that JEOS is set, 
+                                                    tmp_jeos_raised will be corrected
+                                                    accordingly during API execution */       
+ 
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of sequence selected */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_End = ADC_FLAG_JEOS;
+  }
+  else /* end of conversion selected */
+  {
+    tmp_Flag_End = ADC_FLAG_JEOC;
+  }
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();  
+     
+   /* Wait until End of Conversion or Sequence flag is raised */
+  while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+      {
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Next, to clear the polled flag as well as to update the handle State,
+     JEOS is checked and the relevant configuration registers are retrieved.
+     JQM, JAUTO and CONT bits will have to be read for the State update,
+     AUTDLY for JEOS clearing. */
+  /*   1. Check whether or not JEOS is set */
+  if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
+  {
+    tmp_jeos_raised = 0;   
+  }
+  /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
+        injected conversions enabled. */
+  if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)
+  {
+    /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
+        check JQM and AUTDLY bits directly in ADC CFGR register */
+    tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);  
+  }
+  else
+  {
+    /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
+        need to check JQM and AUTDLY bits of Master ADC CFGR register */
+    tmpADC_Master = ADC_MASTER_REGISTER(hadc);
+    tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
+  }  
+  /* 3. Check whether or not hadc is the handle of a Slave ADC with dual
+        regular conversions enabled. */ 
+  if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
+  {
+    /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
+       check JAUTO and CONT bits directly in ADC CFGR register */
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
+  }
+  else
+  {
+    /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
+      check JAUTO and CONT bits of Master ADC CFGR register */  
+    tmpADC_Master = ADC_MASTER_REGISTER(hadc);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
+  }
+  
+  
+  
+  /* Clear polled flag */
+  if (tmp_Flag_End == ADC_FLAG_JEOS)
+  {
+    /* Clear end of sequence JEOS flag of injected group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
+    /* For injected groups, no new conversion will start before JEOS is       */
+    /* cleared.                                                               */
+    /* Note that 1. reading ADCx_JDRy clears JEOC.                            */
+    /*           2. in multimode with dual injected conversions enabled (when */
+    /*              multimode feature is available), Master AUTDLY bit is     */
+    /*              checked.                                                  */
+    if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    }
+  }
+  else
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);    
+  }
+  
+  
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+  /* Are injected conversions over ? This is the case if JEOS is set AND
+        - injected conversions are software-triggered when injected queue management is disabled
+        OR
+        - auto-injection is enabled, continuous mode is disabled,
+          and regular conversions are software-triggered */
+  
+  if (tmp_jeos_raised)
+  {
+    if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))  
+       && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&    
+           (ADC_IS_SOFTWARE_START_REGULAR(hadc)))    ))
+    {
+      /* Clear HAL_ADC_STATE_INJ_BUSY bit */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
+      /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+  }
+  
+  
+  /* Return API HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of injected group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : JEOC (end of conversion) or JEOS (end of sequence) 
+  * @note   Case of multimode enabled (when multimode feature is enabled): 
+  *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, 
+  *         then for ADC master. 
+  *         For ADC slave, ADC is enabled only (conversion is not started).  
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param  hadc: ADC handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+
+    /* In case of software trigger detection enabled, JQDIS must be set 
+      (which can be done only if ADSTART and JADSTART are both cleared).
+       If JQDIS is not set at that point, returns an error
+       - since software trigger detection is disabled. User needs to
+       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.  
+       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 
+         the queue is empty */
+    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)   
+    && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))  
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
+      return HAL_ERROR;
+    }
+
+    /* Process locked */
+    __HAL_LOCK(hadc);
+    
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
+      {
+        /* Reset ADC error code field related to injected conversions only */
+        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);            
+      }
+      else
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+      /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
+      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
+      
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - by default if ADC is Master or Independent or if multimode feature is not available
+        - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
+      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+      
+      /* Clear injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+      
+      /* Enable ADC Injected context queue overflow interrupt if this feature   */
+      /* is enabled.                                                            */
+      if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+      }
+      
+      /* Enable ADC end of conversion interrupt */
+      switch(hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV: 
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+          break;
+      }
+      
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started),                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+
+      /* Are injected conversions that of a dual Slave ? */      
+      if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
+      {
+        /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
+           set ADSTART only if JAUTO is cleared */
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);            
+        if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
+        {
+          SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
+        }
+      }
+      else
+      {
+        /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
+           ADSTART is not set */
+          SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);          
+      }
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+    
+    /* Return function status */
+    return tmp_hal_status;
+}
+}
+
+/**
+  * @brief  Stop conversion of injected channels, disable interruption of 
+  *         end-of-conversion. Disable ADC peripheral if no regular conversion
+  *         is on going.
+  * @note   If ADC must be disabled and if conversion is on going on 
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   Case of multimode enabled (when multimode feature is available): 
+  *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, 
+  *         then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled. 
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+  
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on the other group (regular group) is intended to   */
+  /* continue.                                                                */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for injected channels */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+    
+    if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+      
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Change ADC state */
+        /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
+        ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Clear HAL_ADC_STATE_INJ_BUSY bit */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+/**
+  * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+  * @note   Multimode must have been previously configured using 
+  *         HAL_ADCEx_MultiModeConfigChannel() function.
+  *         Interruptions enabled in this function:
+  *          overrun, DMA half transfer, DMA transfer complete. 
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   State field of Slave ADC handle is not updated in this configuration: 
+  *          user should not rely on it for information related to Slave regular 
+  *         conversions.                                                                          
+  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param  pData: Destination Buffer address.
+  * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_HandleTypeDef tmphadcSlave;
+  ADC_Common_TypeDef *tmpADC_Common;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+  
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    
+      return HAL_ERROR;
+    }
+    
+  
+    /* Enable the ADC peripherals: master and slave (in case if not already   */
+    /* enabled previously)                                                    */
+    tmp_hal_status = ADC_Enable(hadc);
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Enable(&tmphadcSlave);
+    }
+  
+    /* Start multimode conversion of ADCs pair */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Update Master State */
+      /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
+      ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
+
+       
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+         
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+      
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+      
+      /* Pointer to the common control register  */
+      tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+      
+      
+      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+      /* start (in case of SW start):                                           */
+  
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable ADC overrun interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+  
+      /* Start the DMA channel */
+      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+          
+      /* Enable conversion of regular group.                                    */
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);      
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+      
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+    
+    /* Return function status */
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+  * @note   Multimode is kept enabled after this function. MultiMode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable 
+  *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.
+  * @note   In case of DMA configured in circular mode, function 
+  *         HAL_ADC_Stop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmphadcSlave;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  
+  /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {                                      
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+    
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+      
+      return HAL_ERROR;
+    }
+    
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+    
+    /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
+    tickstart = HAL_GetTick();  
+    
+    while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          || 
+          ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
+    {
+      if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /*       with HAL_ADC_Stop_DMA() API.                                     */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status == HAL_ERROR)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 
+    }
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* 2. Disable the ADC peripherals: master and slave */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if ADC are effectively disabled */
+      if ((ADC_Disable(hadc) == HAL_OK)         &&
+          (ADC_Disable(&tmphadcSlave) == HAL_OK)   )
+      {
+        tmp_hal_status = HAL_OK;
+      }
+    }
+    else
+    {
+      ADC_Disable(hadc);
+      ADC_Disable(&tmphadcSlave);
+    }
+    /* Change ADC state (ADC master) */
+    /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
+    ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
+    
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
+  * @param  hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
+  * @retval The converted data values.
+  */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+{
+  ADC_Common_TypeDef *tmpADC_Common;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  
+  /* Pointer to the common control register  */
+  tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+  
+  /* Return the multi mode conversion value */
+  return tmpADC_Common->CDR;
+}
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/**
+  * @brief  Get ADC injected group conversion result.
+  * @note   Reading register JDRx automatically clears ADC flag JEOC
+  *         (ADC group injected end of unitary conversion).
+  * @note   This function does not clear ADC flag JEOS 
+  *         (ADC group injected end of sequence conversion)
+  *         Occurrence of flag JEOS rising:
+  *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
+  *            to flag JEOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag JEOC only is raised, at the end of the scan sequence
+  *            both flags JEOC and EOS are raised.
+  *         Flag JEOS must not be cleared by this function because
+  *         it would not be compliant with low power features
+  *         (feature low power auto-wait, not available on all STM32 families).
+  *         To clear this flag, either use function: 
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADCEx_InjectedPollForConversion() 
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+  * @param  hadc: ADC handle
+  * @param  InjectedRank: the converted ADC injected rank.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+  *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+  *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+  *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+  * @retval ADC group injected conversion data
+  */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+  uint32_t tmp_jdr = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+  
+  /* Get ADC converted value */
+  switch(InjectedRank)
+  {  
+    case ADC_INJECTED_RANK_4:
+      tmp_jdr = hadc->Instance->JDR4;
+      break;
+    case ADC_INJECTED_RANK_3: 
+      tmp_jdr = hadc->Instance->JDR3;
+      break;
+    case ADC_INJECTED_RANK_2: 
+      tmp_jdr = hadc->Instance->JDR2;
+      break;
+    case ADC_INJECTED_RANK_1:
+    default:
+      tmp_jdr = hadc->Instance->JDR1;
+      break;
+  }
+  
+  /* Return ADC converted value */ 
+  return tmp_jdr;
+}
+
+/**
+  * @brief  Injected conversion complete callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Injected context queue overflow callback.
+  * @note   This callback is called if injected context queue is enabled
+            (parameter "QueueInjectedContext" in injected channel configuration)
+            and if a new injected context is set when queue is full (maximum 2
+            contexts).
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 2 callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 3 callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+  */
+}
+
+
+/**
+  * @brief  End Of Sampling callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+  */
+}
+
+
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in 
+  *         case of auto_injection mode), disable ADC peripheral if no 
+  *         conversion is on going on injected group.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+  
+  /* Disable ADC peripheral if regular conversions are effectively stopped 
+     and if no injected conversions are on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 
+     
+    if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+      
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Change ADC state */
+        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @brief  Stop ADC conversion of ADC groups regular and injected,
+  *         disable interrution of end-of-conversion,
+  *         disable ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped
+    and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);  
+    
+    /* Disable all regular-related interrupts */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+    
+    /* 2. Disable ADC peripheral if no injected conversions are on-going */
+    if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+    {     
+      tmp_hal_status = ADC_Disable(hadc);
+      /* if no issue reported */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Change ADC state */
+        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in 
+  *         case of auto_injection mode), disable ADC DMA transfer, disable 
+  *         ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. 
+  *         For multimode (when multimode feature is available), 
+  *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped 
+     and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+    
+    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* while DMA transfer is on going)                                        */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);   
+    
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);   
+    }
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+    {    
+      if (tmp_hal_status == HAL_OK)
+      {
+        tmp_hal_status = ADC_Disable(hadc);
+      }
+      else
+      {
+        ADC_Disable(hadc);
+      }
+      
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Change ADC state */
+        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);      
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);  
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+/**
+  * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
+  * @note   Multimode is kept enabled after this function. Multimode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable 
+  *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.  
+  * @note   In case of DMA configured in circular mode, function 
+  *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmphadcSlave;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  
+  /* 1. Stop potential multimode conversion on going, on regular groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+    
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+    
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+      
+      return HAL_ERROR;
+    }
+    
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+    
+    /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
+    tickstart = HAL_GetTick();  
+    
+    while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          || 
+          ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
+    {
+      if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);  
+    }
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* 2. Disable the ADC peripherals: master and slave if no injected        */
+    /*   conversion is on-going.                                              */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+       if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+       {  
+         tmp_hal_status =  ADC_Disable(hadc);
+         if (tmp_hal_status == HAL_OK)
+         {
+           if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
+           {
+             tmp_hal_status =  ADC_Disable(&tmphadcSlave);
+           }
+         }
+       }
+       
+       if (tmp_hal_status == HAL_OK)
+       {
+         /* Both Master and Slave ADC's could be disabled. Update Master State */
+         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+       }
+       else
+       {
+         /* injected (Master or Slave) conversions are still on-going,
+            no Master State change */
+       }
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+  * @brief    ADC Extended Peripheral Control functions
+  *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on injected group
+      (+) Configure multimode when multimode feature is available
+      (+) Enable or Disable Injected Queue
+      (+) Disable ADC voltage regulator
+      (+) Enter ADC deep-power-down mode
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group injected.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes injected group, following calls to this 
+  *         function can be used to reconfigure some parameters of structure
+  *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_InjectionConfTypeDef".
+  * @note   In case of usage of internal measurement channels:
+  *         Vbat/VrefInt/TempSensor.
+  *         These internal paths can be disabled using function 
+  *         HAL_ADC_DeInit().
+  * @note   Caution: For Injected Context Queue use, a context must be fully 
+  *         defined before start of injected conversion. All channels are configured 
+  *         consecutively for the same ADC instance. Therefore, the number of calls to 
+  *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter 
+  *         InjectedNbrOfConversion for each context.
+  *  - Example 1: If 1 context is intended to be used (or if there is no use of the 
+  *    Injected Queue Context feature) and if the context contains 3 injected ranks 
+  *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be  
+  *    called once for each channel (i.e. 3 times) before starting a conversion.   
+  *    This function must not be called to configure a 4th injected channel:   
+  *    it would start a new context into context queue.
+  *  - Example 2: If 2 contexts are intended to be used and each of them contains 
+  *    3 injected ranks (InjectedNbrOfConversion = 3),  
+  *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and  
+  *    for each context (3 channels x 2 contexts = 6 calls). Conversion can  
+  *    start once the 1st context is set, that is after the first three 
+  *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
+  * @param  hadc: ADC handle
+  * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
+  *         injected group.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_Common_TypeDef *tmpADC_Common;
+  uint32_t tmpOffsetShifted;
+  uint32_t wait_loop_index = 0;
+  
+  uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
+  assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+  assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
+  assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
+  
+  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+    assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+  }
+  
+  
+  /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is  
+     ignored (considered as reset) */
+  assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); 
+  
+  /* JDISCEN and JAUTO bits can't be set at the same time  */
+  assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); 
+  
+  /*  DISCEN and JAUTO bits can't be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));  
+  
+  /* Verification of channel number */
+  if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+     assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Configuration of injected group sequencer:                               */
+  /* Hardware constraint: Must fully define injected context register JSQR    */
+  /* before make it entering into injected sequencer queue.                   */
+  /*                                                                          */
+  /* - if scan mode is disabled:                                              */
+  /*    * Injected channels sequence length is set to 0x00: 1 channel         */
+  /*      converted (channel on injected rank 1)                              */
+  /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
+  /*    * Injected context register JSQR setting is simple: register is fully */
+  /*      defined on one call of this function (for injected rank 1) and can  */
+  /*      be entered into queue directly.                                     */
+  /* - if scan mode is enabled:                                               */
+  /*    * Injected channels sequence length is set to parameter               */
+  /*      "InjectedNbrOfConversion".                                          */
+  /*    * Injected context register JSQR setting more complex: register is    */
+  /*      fully defined over successive calls of this function, for each      */
+  /*      injected channel rank. It is entered into queue only when all       */
+  /*      injected ranks have been set.                                       */
+  /*   Note: Scan mode is not present by hardware on this device, but used    */
+  /*   by software for alignment over all STM32 devices.                      */
+
+  if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
+      (sConfigInjected->InjectedNbrOfConversion == 1)  )
+  {
+    /* Configuration of context register JSQR:                                */
+    /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
+    /*    (scan mode disabled, only rank 1 used)                              */
+    /*  - external trigger to start conversion                                */
+    /*  - external trigger polarity                                           */
+    /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+    
+    if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+    {
+      /* Enable external trigger if trigger selection is different of         */
+      /* software start.                                                      */
+      /* Note: This configuration keeps the hardware feature of parameter     */
+      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+      /*       software start.                                                */
+      if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+         && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
+                                             sConfigInjected->ExternalTrigInjecConv     |
+                                             sConfigInjected->ExternalTrigInjecConvEdge                         );
+      }
+      else
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
+      }
+      
+      
+      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); 
+      /* For debug and informative reasons, hadc handle saves JSQR setting */
+      hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
+    
+    }
+  }
+  else
+  {
+    /* Case of scan mode enabled, several channels to set into injected group */
+    /* sequencer.                                                             */
+    /*                                                                        */
+    /* Procedure to define injected context register JSQR over successive     */
+    /* calls of this function, for each injected channel rank:                */
+    /* 1. Start new context and set parameters related to all injected        */
+    /*    channels: injected sequence length and trigger.                     */
+    
+    /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
+    /*   call of the context under setting                                    */
+    if (hadc->InjectionConfig.ChannelCount == 0) 
+    {
+      /* Initialize number of channels that will be configured on the context */
+      /*  being built                                                         */
+      hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
+      /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
+         call, this context will be written in JSQR register at the last call.
+         At this point, the context is merely reset  */
+       hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
+      
+      /* Configuration of context register JSQR:                              */
+      /*  - number of ranks in injected group sequencer                       */
+      /*  - external trigger to start conversion                              */
+      /*  - external trigger polarity                                         */
+      
+      /* Enable external trigger if trigger selection is different of         */
+      /* software start.                                                      */
+      /* Note: This configuration keeps the hardware feature of parameter     */
+      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+      /*       software start.                                                */
+      if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+         && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
+                                             sConfigInjected->ExternalTrigInjecConv |
+                                             sConfigInjected->ExternalTrigInjecConvEdge              );
+      }
+      else
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
+      }
+      
+    } /* if (hadc->InjectionConfig.ChannelCount == 0) */
+    
+
+    /* 2. Continue setting of context under definition with parameter       */
+    /*    related to each channel: channel rank sequence                    */
+    /* Clear the old JSQx bits for the selected rank */
+    tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
+    
+    /* Set the JSQx bits for the selected rank */
+    tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
+
+    /* Decrease channel count  */
+    hadc->InjectionConfig.ChannelCount--;
+    
+    /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
+          call, aggregate the setting to those already built during the previous  
+          HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
+    hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
+    
+    /* 4. End of context setting: if this is the last channel set, then write context
+        into register JSQR and make it enter into queue                   */
+    if (hadc->InjectionConfig.ChannelCount == 0)
+    {
+      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); 
+    }
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on injected group:                                   */
+  /*  - Injected context queue: Queue disable (active context is kept) or     */
+  /*    enable (context decremented, up to 2 contexts queued)                 */
+  /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
+  /*    mode is disabled.                                                     */
+  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+  {
+    /* If auto-injected mode is disabled: no constraint                       */
+    if (sConfigInjected->AutoInjectedConv == DISABLE)
+    {                               
+      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 
+                               ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext)          | 
+                               ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );                          
+    }
+    /* If auto-injected mode is enabled: Injected discontinuous setting is   */
+    /* discarded.                                                             */
+    else
+    {
+            MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 
+                               ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );  
+    }
+
+  }
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular and injected groups:                      */
+  /*  - Automatic injected conversion: can be enabled if injected group       */
+  /*    external triggers are disabled.                                       */
+  /*  - Channel sampling time                                                 */
+  /*  - Channel offset                                                        */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+  {
+    /* If injected group external triggers are disabled (set to injected      */
+    /* software start): no constraint                                         */
+    if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+       || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+    {
+         if (sConfigInjected->AutoInjectedConv == ENABLE)
+         {
+           SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);    
+         }
+         else
+         {
+           CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);    
+         }                                                                                  
+    }
+    /* If Automatic injected conversion was intended to be set and could not  */
+    /* due to injected group external triggers enabled, error is reported.    */
+    else
+    {
+      if (sConfigInjected->AutoInjectedConv == ENABLE)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        
+        tmp_hal_status = HAL_ERROR;
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); 
+      }
+    }
+    
+    if (sConfigInjected->InjecOversamplingMode == ENABLE)
+    {
+      assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+      assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
+      
+      /*  JOVSE must be reset in case of triggered regular mode  */
+      assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS)));
+      
+      /* Configuration of Injected Oversampler:                                 */
+      /*  - Oversampling Ratio                                                  */
+      /*  - Right bit shift                                                     */
+      
+      /* Enable OverSampling mode */
+      
+       MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS, 
+                                 ADC_CFGR2_JOVSE                     | 
+                                 sConfigInjected->InjecOversampling.Ratio         |
+                                 sConfigInjected->InjecOversampling.RightBitShift );
+    }
+    else
+    {
+      /* Disable Regular OverSampling */
+       CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+    }
+    
+    /* Sampling time configuration of the selected channel */
+    /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+    if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
+    {
+      /* Clear the old sample time and set the new one */
+      ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);                
+    }
+    else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
+    {
+     /* Clear the old sample time and set the new one */
+      ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);             
+    }
+    
+    /* Configure the offset: offset enable/disable, channel, offset value */
+    
+    /* Shift the offset with respect to the selected ADC resolution. */
+    /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+    tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+    
+    switch (sConfigInjected->InjectedOffsetNumber)
+    {
+    case ADC_OFFSET_1:
+      /* Configure offset register 1:                                         */
+      /* - Enable offset                                                      */
+      /* - Set channel number                                                 */
+      /* - Set offset value                                                   */
+      MODIFY_REG(hadc->Instance->OFR1, 
+                ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN, 
+                ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                    
+      break;
+    
+    case ADC_OFFSET_2:
+      /* Configure offset register 2:                                         */
+      /* - Enable offset                                                      */
+      /* - Set channel number                                                 */
+      /* - Set offset value                                                   */
+      MODIFY_REG(hadc->Instance->OFR2, 
+                ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2_EN, 
+                ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                     
+      break;
+    
+    case ADC_OFFSET_3:
+      /* Configure offset register 3:                                         */
+      /* - Enable offset                                                      */
+      /* - Set channel number                                                 */
+      /* - Set offset value                                                   */
+      MODIFY_REG(hadc->Instance->OFR3, 
+                ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3_EN, 
+                ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                   
+      break;
+    
+    case ADC_OFFSET_4:
+      /* Configure offset register 1:                                         */
+      /* - Enable offset                                                      */
+      /* - Set channel number                                                 */
+      /* - Set offset value                                                   */
+      MODIFY_REG(hadc->Instance->OFR4, 
+                ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4_EN, 
+                ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                  
+      break;
+    
+    /* Case ADC_OFFSET_NONE */
+    default :
+    /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
+      if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+      {
+        /* Disable offset OFR1*/
+        CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
+      }
+      if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+      {
+        /* Disable offset OFR2*/
+        CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); 
+      }
+      if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+      {
+        /* Disable offset OFR3*/
+        CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); 
+      }
+      if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+      {
+        /* Disable offset OFR4*/
+        CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); 
+      }
+      break;
+    }
+  
+  } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated only when ADC is disabled:                */
+  /*  - Single or differential mode                                           */
+  /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    /* Configuration of differential mode */
+    if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+    {
+      /* Disable differential mode (default mode: single-ended) */
+      CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
+    }
+    else
+    {
+      /* Enable differential mode */
+      SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
+      
+      /* Sampling time configuration of channel ADC_IN+1 (negative input).
+         Starting from channel 9, SMPR2 register must be configured.      */
+      if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
+      {
+        /* Clear the old sample time and set the new one */
+        ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);                     
+      }
+      else /* For channels 0 to 8 */
+      {
+         /* Clear the old sample time and set the new one */
+        ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);                 
+      }
+    }
+    
+
+    /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
+    /* internal measurement paths enable: If internal channel selected,       */
+    /* enable dedicated internal buffers and path.                            */
+    /* Note: these internal measurement paths can be disabled using           */
+    /* HAL_ADC_DeInit().                                                      */
+
+    /* Configuration of common ADC parameters                                 */
+
+    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+  
+    /* If the requested internal measurement path has already been enabled,   */
+    /* bypass the configuration processing.                                   */
+    if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
+          (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
+        ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)       &&
+          (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
+        ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)    &&
+          (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
+       )
+    {
+      /* Configuration of common ADC parameters (continuation)                */
+      /* Software is allowed to change common parameters only when all ADCs   */
+      /* of the common group are disabled.                                    */
+      if ((ADC_IS_ENABLE(hadc) == RESET)   &&
+         (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )              
+      {
+        if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
+        {
+          if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 
+          {
+            SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
+          
+            /* Delay for temperature sensor stabilization time */
+            /* Compute number of CPU cycles to wait for */
+            wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+            while(wait_loop_index != 0)
+            {
+              wait_loop_index--;
+            }
+          }
+        }
+        else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+        { 
+          if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+          {
+            SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
+          }
+        }
+        else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+        { 
+          if (ADC_VREFINT_INSTANCE(hadc))
+          {
+            SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
+          }                       
+        }       
+      }
+      /* If the requested internal measurement path has already been enabled  */
+      /* and other ADC of the common group are enabled, internal              */
+      /* measurement paths cannot be enabled.                                 */
+      else  
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        
+        tmp_hal_status = HAL_ERROR;
+      }
+    }
+    
+  } /* if (ADC_IS_ENABLE(hadc) == RESET) */
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+/**
+  * @brief  Enable ADC multimode and configure multimode parameters
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes multimode parameters, following  
+  *         calls to this function can be used to reconfigure some parameters 
+  *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting 
+  *         the ADCs.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_MultiModeTypeDef".
+  * @note   To move back configuration from multimode to single mode, ADC must
+  *         be reset (using function HAL_ADC_Init() ).
+  * @param  hadc: Master ADC handle
+  * @param  multimode : Structure of ADC multimode configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+{
+  HAL_StatusTypeDef  tmp_hal_status = HAL_OK;
+  ADC_Common_TypeDef *tmpADC_Common;
+  ADC_HandleTypeDef  tmphadcSlave;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_MULTIMODE(multimode->Mode));
+  if(multimode->Mode != ADC_MODE_INDEPENDENT)
+  {
+    assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
+    assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+  
+  if (tmphadcSlave.Instance == NULL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+    
+    return HAL_ERROR;
+  }
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Multimode DMA configuration                                           */
+  /*  - Multimode DMA mode                                                    */
+  if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 
+    && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
+  {
+    /* Pointer to the common control register */
+    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+    
+    /* If multimode is selected, configure all multimode paramaters.          */
+    /* Otherwise, reset multimode parameters (can be used in case of          */
+    /* transition from multimode to independent mode).                        */
+    if(multimode->Mode != ADC_MODE_INDEPENDENT)
+    {
+      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 
+                 multimode->DMAAccessMode |
+                 ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests));
+      
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      /*    Note: Delay range depends on selected resolution:                     */
+      /*      from 1 to 12 clock cycles for 12 bits                               */
+      /*      from 1 to 10 clock cycles for 10 bits,                              */
+      /*      from 1 to 8 clock cycles for 8 bits                                 */
+      /*      from 1 to 6 clock cycles for 6 bits                                 */
+      /*    If a higher delay is selected, it will be clipped to maximum delay    */
+      /*    range                                                                 */
+      if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
+          (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
+      {
+          MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
+                     multimode->Mode | multimode->TwoSamplingDelay    );
+      }
+    }
+    else /* ADC_MODE_INDEPENDENT */
+    {
+      CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
+      
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
+          (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
+      {
+        CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+      }
+    }
+  }
+  /* If one of the ADC sharing the same common group is enabled, no update    */
+  /* could be done on neither of the multimode structure parameters.          */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+} 
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/**
+  * @brief  Enable Injected Queue
+  * @note   This function resets CFGR register JQDIS bit in order to enable the
+  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+  *         are both equal to 0 to ensure that no regular nor injected 
+  *         conversion is ongoing. 
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
+{
+  /* Parameter can be set only if no conversion is on-going                   */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+  {
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+    
+    /* Update state, clear previous result related to injected queue overflow */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable Injected Queue
+  * @note   This function sets CFGR register JQDIS bit in order to disable the
+  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+  *         are both equal to 0 to ensure that no regular nor injected 
+  *         conversion is ongoing. 
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
+{
+  /* Parameter can be set only if no conversion is on-going                   */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+  {
+    SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+    return HAL_OK;    
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable ADC voltage regulator.
+  * @note   Disabling voltage regulator allows to save power. This operation can
+  *         be carried out only when ADC is disabled.
+  * @note   To enable again the voltage regulator, the user is expected to 
+  *         resort to HAL_ADC_Init() API.           
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
+{
+  /* ADVREGEN can be written only when the ADC is disabled  */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
+    return HAL_OK;    
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enter ADC deep-power-down mode
+  * @note   This mode is achieved in setting DEEPPWD bit and allows to save power 
+  *         in reducing leakage currents. It is particularly interesting before 
+  *         entering stop modes.
+  * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+  *         ADC voltage regulator. This means that this API encompasses
+  *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+  *         calibration is lost.    
+  * @note   To exit the ADC deep-power-down mode, the user is expected to 
+  *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
+  *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+  *         saved calibration factor.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
+{
+  /* DEEPPWD can be written only when the ADC is disabled  */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+    return HAL_OK;    
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h
new file mode 100755
index 0000000..7dc27f8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h
@@ -0,0 +1,1744 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_adc_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of ADC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_ADC_EX_H
+#define __STM32L4xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC group injected contexts queue configuration 
+  */
+typedef struct
+{                                                                                                                          
+  uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each 
+                                              HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+                                              JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+  uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
+}ADC_InjectionConfigTypeDef;  
+
+/** 
+  * @brief  ADC handle Structure definition  
+  */ 
+typedef struct
+{
+  ADC_TypeDef                   *Instance;              /*!< Register base address */
+
+  ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
+
+  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
+
+  __IO uint32_t                 State;                  /*!< ADC communication state (bit-map of ADC states) */
+
+  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
+  
+  ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */  
+}ADC_HandleTypeDef;
+
+/** 
+  * @brief  ADC Injected Conversion Oversampling structure definition  
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
+                                               
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
+}ADC_InjOversamplingTypeDef;  
+
+/** 
+  * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
+  *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+  *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
+  * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
+  *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
+  *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
+  *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 
+  *            on ADC groups regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct 
+{
+  uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
+                                               This parameter can be a value of @ref ADC_channels
+                                               Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+  uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
+                                               This parameter must be a value of @ref ADCEx_injected_rank.
+                                               Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 
+                                               the new channel setting (or parameter number of conversions adjusted) */
+
+  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
+                                               Unit: ADC clock cycles.
+                                               Conversion time is the addition of sampling time and processing time
+                                               (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                               This parameter can be a value of @ref ADC_sampling_times.
+                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+                                                        It overwrites the last setting.
+                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                                     Refer to device datasheet for timings values. */
+
+  uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
+                                               In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+                                               This parameter must be a value of @ref ADCEx_SingleDifferential.
+                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+                                                        It overwrites the last setting.
+                                               Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
+                                               Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 
+                                               of another parameter update on the fly) */
+
+  uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
+                                               This parameter can be a value of @ref ADCEx_OffsetNumber.
+                                               Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
+
+  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
+                                               Offset value must be a positive number.
+                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+                                               between Min_Data = 0x000 and Max_Data = 0xFFF,  0x3FF, 0xFF or 0x3F respectively.
+                                               Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 
+                                               without continuous mode or external trigger that could launch a conversion). */
+
+  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
+                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
+                                               (main sequence subdivided in successive parts).
+                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                               Discontinuous mode can be enabled only if continuous mode is disabled. 
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                               Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
+                                               This parameter can be set to ENABLE or DISABLE.      
+                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
+                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  uint32_t QueueInjectedContext;          /*!< Specifies whether the context queue feature is enabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
+                                               new injected context is set when queue is full, error is triggered by interruption and through function 
+                                               'HAL_ADCEx_InjectedQueueOverflowCallback'.
+                                               Caution: This feature request that the sequence is fully configured before injected conversion start.
+                                                        Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
+
+  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
+                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+                                               This parameter can be a value of @ref ADC_injected_external_trigger_source.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
+                                               This parameter can be a value of @ref ADC_injected_external_trigger_edge.
+                                               If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+                                                                                                
+  uint32_t InjecOversamplingMode;             /*!< Specifies whether the oversampling feature is enabled or disabled.
+                                              This parameter can be set to ENABLE or DISABLE.
+                                              Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
+                                              
+  ADC_InjOversamplingTypeDef  InjecOversampling;   /*!< Specifies the Oversampling parameters.
+                                                   Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.    
+                                                   Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */                                                          
+}ADC_InjectionConfTypeDef;
+
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+/** 
+  * @brief  Structure definition of ADC multimode
+  * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
+  *         Both Master and Slave ADCs must be disabled.
+  */
+typedef struct
+{
+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode. 
+                                   This parameter can be a value of @ref ADCEx_Common_mode. */
+
+  uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multimode ADC:
+                                   selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
+                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */
+
+  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
+                                   This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases.
+                                   Delay range depends on selected resolution: 
+                                    from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
+                                    from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.     */
+}ADC_MultiModeTypeDef;
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+  /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO    ((uint32_t)0x00000000)                                                     /*!< Event 0 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)                                             /*!< Event 1 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL_1)                                             /*!< Event 2 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 3 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_2)                                             /*!< Event 4 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 5 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))                      /*!< Event 6 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T8_CC4     ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)                                             /*!< Event 8 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 9 triggers injected group conversion start  */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2   ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))                      /*!< Event 10 triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))                      /*!< Event 12 triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)                                               /*!< Event 15 triggers injected group conversion start */
+#define ADC_INJECTED_SOFTWARE_START      ((uint32_t)0x00000001)                                                     /*!< Software triggers injected group conversion start */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)          /*!< Injected conversions hardware trigger detection disabled                             */ 
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */ 
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */ 
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
+  * @{
+  */
+#define ADC_SINGLE_ENDED                ((uint32_t)0x00000000)       /*!< ADC channel set in single-ended input mode */
+#define ADC_DIFFERENTIAL_ENDED          ((uint32_t)ADC_CR_ADCALDIF)  /*!< ADC channel set in differential mode       */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
+  * @{
+  */
+#define ADC_OFFSET_NONE               ((uint32_t)0x00)     /*!< No offset correction                           */
+#define ADC_OFFSET_1                  ((uint32_t)0x01)     /*!< Offset correction to apply to a first channel  */
+#define ADC_OFFSET_2                  ((uint32_t)0x02)     /*!< Offset correction to apply to a second channel */
+#define ADC_OFFSET_3                  ((uint32_t)0x03)     /*!< Offset correction to apply to a third channel  */
+#define ADC_OFFSET_4                  ((uint32_t)0x04)     /*!< Offset correction to apply to a fourth channel */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
+  * @{
+  */
+#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)      /*!< ADC injected conversion rank 1 */
+#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)      /*!< ADC injected conversion rank 2 */
+#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)      /*!< ADC injected conversion rank 3 */
+#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)      /*!< ADC injected conversion rank 4 */
+/**
+  * @}
+  */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+/** @defgroup ADCEx_Common_mode ADC Extended multimode dual mode
+  * @{
+  */
+#define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000))                                       /*!< Independent ADC conversions mode                           */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_0))                                   /*!< Combined regular simultaneous + injected simultaneous mode */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)(ADC_CCR_DUAL_1))                                   /*!< Combined regular simultaneous + alternate trigger mode     */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))                  /*!< Combined Interleaved mode + injected simultaneous mode     */
+#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))                  /*!< Injected simultaneous mode only                            */
+#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))                  /*!< Regular simultaneous mode only                             */
+#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only                                      */
+#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))                  /*!< Alternate trigger mode only                                */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA mode for multimode
+  * @{
+  */
+#define ADC_DMAACCESSMODE_DISABLED      ((uint32_t)0x00000000)       /*!< DMA multimode disabled: each ADC uses its own DMA channel */
+#define ADC_DMAACCESSMODE_12_10_BITS    ((uint32_t)ADC_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
+#define ADC_DMAACCESSMODE_8_6_BITS      ((uint32_t)ADC_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended delay between 2 sampling phases
+  * @{
+  */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE     ((uint32_t)(0x00000000))                                          /*!< 1 ADC clock cycle delay                                     */ 
+#define ADC_TWOSAMPLINGDELAY_2CYCLES    ((uint32_t)(ADC_CCR_DELAY_0))                                     /*!< 2 ADC clock cycles delay                                    */ 
+#define ADC_TWOSAMPLINGDELAY_3CYCLES    ((uint32_t)(ADC_CCR_DELAY_1))                                     /*!< 3 ADC clock cycles delay                                    */ 
+#define ADC_TWOSAMPLINGDELAY_4CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))                   /*!< 4 ADC clock cycles delay                                    */ 
+#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)(ADC_CCR_DELAY_2))                                     /*!< 5 ADC clock cycles delay                                    */ 
+#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))                   /*!< 6 ADC clock cycles delay                                    */ 
+#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))                   /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution)  */ 
+#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution)  */ 
+#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)(ADC_CCR_DELAY_3))                                     /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution)  */ 
+#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))                   /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */ 
+#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))                   /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */ 
+#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */ 
+/**
+  * @}
+  */
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+/** @defgroup ADCEx_Common_mode ADC Extended Independent ADC Mode
+  * @{
+  */
+#define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000))                                       /*!< Independent ADC conversions mode                           */
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_1                    ((uint32_t)0x00000001)   /*!< Analog watchdog 1 selection */ 
+#define ADC_ANALOGWATCHDOG_2                    ((uint32_t)0x00000002)   /*!< Analog watchdog 2 selection */ 
+#define ADC_ANALOGWATCHDOG_3                    ((uint32_t)0x00000003)   /*!< Analog watchdog 3 selection */ 
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t) 0x00000000)                                             /*!< No analog watchdog selected                                             */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))                    /*!< Analog watchdog applied to a regular group single channel               */
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))                   /*!< Analog watchdog applied to an injected group single channel             */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CFGR_AWD1EN)                                        /*!< Analog watchdog applied to regular group all channels                   */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CFGR_JAWD1EN)                                       /*!< Analog watchdog applied to injected group all channels                  */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))                    /*!< Analog watchdog applied to regular and injected groups all channels     */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
+  * @{
+  */                                                                                                            
+#define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))                                 /*!< ADC regular group selection               */ 
+#define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))                               /*!< ADC injected group selection              */ 
+#define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */ 
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Event_type ADC Extended Event Type
+  * @{
+  */
+#define ADC_EOSMP_EVENT          ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event                                */
+#define ADC_AWD1_EVENT           ((uint32_t)ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
+#define ADC_AWD2_EVENT           ((uint32_t)ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_AWD3_EVENT           ((uint32_t)ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_OVR_EVENT            ((uint32_t)ADC_FLAG_OVR)   /*!< ADC overrun event                                        */
+#define ADC_JQOVF_EVENT          ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event                */
+/**
+  * @}
+  */
+#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
+  * @{
+  */
+#define ADC_IT_RDY           ADC_IER_ADRDY      /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IT_EOSMP         ADC_IER_EOSMP      /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC           ADC_IER_EOC        /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS           ADC_IER_EOS        /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR           ADC_IER_OVR        /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC          ADC_IER_JEOC       /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS          ADC_IER_JEOS       /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_AWD1          ADC_IER_AWD1       /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2          ADC_IER_AWD2       /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
+#define ADC_IT_AWD3          ADC_IER_AWD3       /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
+#define ADC_IT_JQOVF         ADC_IER_JQOVF      /*!< ADC Injected Context Queue Overflow interrupt source */
+
+#define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
+  * @{
+  */
+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready (ADRDY) flag */
+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+#define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
+
+#define ADC_FLAG_AWD           ADC_FLAG_AWD1    /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
+
+#define ADC_FLAG_ALL    (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
+                         ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
+                         ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)   /*!< ADC all flags */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
+                               ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
+                               ADC_FLAG_JQOVF)                             /*!< ADC post-conversion all flags */
+
+/**
+  * @}
+  */
+
+       
+/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
+  * @{
+  */
+#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)   /*!< ADC injected conversion rank 1 */
+#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)   /*!< ADC injected conversion rank 2 */
+#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)   /*!< ADC injected conversion rank 3 */
+#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)   /*!< ADC injected conversion rank 4 */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup ADCEx_Oversampling_Ratio    ADC Extended Oversampling Ratio
+  * @{
+  */
+
+#define ADC_OVERSAMPLING_RATIO_2      ((uint32_t)0x00000000)                            /*!<  ADC Oversampling ratio 2x   */
+#define ADC_OVERSAMPLING_RATIO_4      ((uint32_t)ADC_CFGR2_OVSR_0)                      /*!<  ADC Oversampling ratio 4x   */
+#define ADC_OVERSAMPLING_RATIO_8      ((uint32_t)ADC_CFGR2_OVSR_1)                      /*!<  ADC Oversampling ratio 8x   */
+#define ADC_OVERSAMPLING_RATIO_16     ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!<  ADC Oversampling ratio 16x  */
+#define ADC_OVERSAMPLING_RATIO_32     ((uint32_t)ADC_CFGR2_OVSR_2)                      /*!<  ADC Oversampling ratio 32x  */
+#define ADC_OVERSAMPLING_RATIO_64     ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!<  ADC Oversampling ratio 64x  */
+#define ADC_OVERSAMPLING_RATIO_128    ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!<  ADC Oversampling ratio 128x */
+#define ADC_OVERSAMPLING_RATIO_256    ((uint32_t)(ADC_CFGR2_OVSR))                      /*!<  ADC Oversampling ratio 256x */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Right_Bit_Shift   ADC Extended Oversampling Right Shift
+  * @{
+  */
+#define ADC_RIGHTBITSHIFT_NONE  ((uint32_t)0x00000000)                                               /*!<  ADC No bit shift for oversampling */
+#define ADC_RIGHTBITSHIFT_1     ((uint32_t)ADC_CFGR2_OVSS_0)                                         /*!<  ADC 1 bit shift for oversampling  */
+#define ADC_RIGHTBITSHIFT_2     ((uint32_t)ADC_CFGR2_OVSS_1)                                         /*!<  ADC 2 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_3     ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 3 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_4     ((uint32_t)ADC_CFGR2_OVSS_2)                                         /*!<  ADC 4 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_5     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 5 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_6     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))                    /*!<  ADC 6 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_7     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!<  ADC 7 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_8     ((uint32_t)ADC_CFGR2_OVSS_3)                                         /*!<  ADC 8 bits shift for oversampling */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Triggered_Oversampling_Mode   ADC Extended Triggered Regular Oversampling
+  * @{
+  */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER      ((uint32_t)0x00000000)      /*!<  A single trigger for all channel oversampled conversions */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER       ((uint32_t)ADC_CFGR2_TROVS) /*!<  A trigger for each oversampled conversion                */
+/**
+  * @}
+  */
+  
+/** @defgroup ADCEx_Regular_Oversampling_Mode   ADC Extended Regular Oversampling Continued or Resumed Mode
+  * @{
+  */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE    ((uint32_t)0x00000000)      /*!<  Oversampling buffer maintained during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE      ((uint32_t)ADC_CFGR2_ROVSM) /*!<  Oversampling buffer zeroed during injection sequence     */
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_sampling_times ADC Sampling Times
+  * @{
+  */
+#define ADC_SAMPLETIME_2CYCLES_5       ((uint32_t)0x00000000)                             /*!< Sampling time 2.5 ADC clock cycle    */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_SAMPLETIME_3CYCLES_5      ((uint32_t)ADC_SMPR1_SMPPLUS)                       /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time 
+                                                                                               replaces all sampling time 2.5 ADC clock cycles. These 2 sampling  
+                                                                                               times cannot be used simultaneously. */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+#define ADC_SAMPLETIME_6CYCLES_5      ((uint32_t)ADC_SMPR2_SMP10_0)                       /*!< Sampling time 6.5 ADC clock cycles   */
+#define ADC_SAMPLETIME_12CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_1)                       /*!< Sampling time 12.5 ADC clock cycles  */
+#define ADC_SAMPLETIME_24CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles  */
+#define ADC_SAMPLETIME_47CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_2)                       /*!< Sampling time 47.5 ADC clock cycles  */
+#define ADC_SAMPLETIME_92CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles  */
+#define ADC_SAMPLETIME_247CYCLES_5    ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */
+#define ADC_SAMPLETIME_640CYCLES_5    ((uint32_t)ADC_SMPR2_SMP10)                         /*!< Sampling time 640.5 ADC clock cycles */
+/**
+  * @}
+  */  
+
+/** @defgroup ADC_CFGR_fields ADCx CFGR fields
+  * @{
+  */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO    | ADC_CFGR_JAWD1EN |\
+                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL  | ADC_CFGR_JQM     |\
+                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM  | ADC_CFGR_DISCEN  |\
+                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT     | ADC_CFGR_OVRMOD  |\
+                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL   | ADC_CFGR_ALIGN   |\
+                            ADC_CFGR_RES     | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN)
+#else
+#define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
+                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
+                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
+                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
+                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
+                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+/**
+  * @}
+  */  
+  
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+  * @{
+  */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+                             ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 
+#else
+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+                             ADC_SMPR1_SMP0) 
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+/**
+  * @}
+  */ 
+  
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 
+  * @{
+  */
+/* ADC_CFGR fields of parameters that can be updated when no conversion
+   (neither regular nor injected) is on-going  */  
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_CFGR_FIELDS_2  ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG))
+#else
+#define ADC_CFGR_FIELDS_2  ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+/**
+  * @}
+  */ 
+  
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+/** @defgroup ADCEx_DFSDM_Mode_Configuration   ADC Extended DFSDM mode configuration
+  * @{
+  */
+#define ADC_DFSDM_MODE_DISABLE    ((uint32_t)0x00000000)        /*!< DFSDM mode configuration disabled */
+#define ADC_DFSDM_MODE_ENABLE     ((uint32_t)ADC_CFGR_DFSDMCFG) /*!< DFSDM mode configuration enabled */
+/**
+  * @}
+  */ 
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+  
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+  * @{
+  */
+
+/** @brief  Force ADC instance in multimode mode independant (multimode disable).
+  * @note   This macro must be used only in case of transition from multimode
+  *         to mode independent and in case of unknown previous state,
+  *         to ensure ADC configuration is in mode independent.
+  * @note   Standard way of multimode configuration change is done from
+  *         HAL ADC handle of ADC master using function
+  *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+  *         Usage of this macro is not the Standard way of multimode 
+  *         configuration and can lead to have HAL ADC handles status 
+  *         misaligned. Usage of this macro must be limited to cases 
+  *         mentionned above.
+  * @param  __HANDLE__: ADC handle.
+  * @retval None
+  */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \
+  CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_DUAL)
+
+/**
+  * @}
+  */
+#endif
+
+/* Private macros -----------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+  * @{
+  */
+  
+/**
+  * @brief Test if conversion trigger of injected group is software start
+  *        or external trigger.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (software start) or RESET (external trigger).
+  */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                       \
+       (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
+
+/**
+  * @brief Check if conversion is on going on regular or injected groups.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (conversion is on going) or RESET (no conversion is on going).
+  */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                    \
+       (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET  \
+        ) ? RESET : SET)
+        
+/**
+  * @brief Check if conversion is on going on injected group.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (conversion is on going) or RESET (no conversion is on going).
+  */
+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                   \
+       (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET            \
+        ) ? RESET : SET)  
+                      
+/**
+  * @brief Check whether or not ADC is independent.
+  * @param __HANDLE__: ADC handle.
+  * @note  When multimode feature is not available, the macro always returns SET.   
+  * @retval SET (ADC is independent) or RESET (ADC is not).
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+#define ADC_IS_INDEPENDENT(__HANDLE__)    \
+  ( ( ( ((__HANDLE__)->Instance) == ADC3) \
+    )?                                    \
+     SET                                  \
+     :                                    \
+     RESET                                \
+  ) 
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__)   (SET)
+#endif
+      
+/**
+  * @brief Set the sample time for Channels numbers between 0 and 9.
+  * @param __SAMPLETIME__: Sample time parameter.
+  * @param __CHANNELNB__: Channel number.  
+  * @retval None
+  */
+#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
+    
+/**
+  * @brief Set the sample time for Channels numbers between 10 and 18.
+  * @param __SAMPLETIME__: Sample time parameter.
+  * @param __CHANNELNB__: Channel number.  
+  * @retval None
+  */
+#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
+
+/**
+  * @brief Write SMPR1 register.
+  * @param __HANDLE__    : ADC handle.
+  * @param __SAMPLETIME__: Sample time parameter.
+  * @param __CHANNELNB__ : Channel number.  
+  * @retval None
+  */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
+  do {                                                                         \
+    if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5)                           \
+    {                                                                          \
+       SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS);              \
+    }                                                                          \
+    else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5)                     \
+    {                                                                          \
+       CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS);            \
+    }                                                                          \
+    MODIFY_REG((__HANDLE__)->Instance->SMPR1,                                  \
+               ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)),                     \
+               ADC_SMPR1((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__)));     \
+  } while(0)
+#else
+#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
+                    MODIFY_REG((__HANDLE__)->Instance->SMPR1,                  \
+                               ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)),     \
+                               ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__)))
+#endif
+
+/**
+  * @brief Write SMPR2 register.
+  * @param __HANDLE__    : ADC handle.
+  * @param __SAMPLETIME__: Sample time parameter.
+  * @param __CHANNELNB__ : Channel number.  
+  * @retval None
+  */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
+  do {                                                                         \
+    if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5)                           \
+    {                                                                          \
+       SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS);              \
+    }                                                                          \
+    else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5)                     \
+    {                                                                          \
+      CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS);             \
+    }                                                                          \
+    MODIFY_REG((__HANDLE__)->Instance->SMPR2,                                  \
+               ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)),                    \
+               ADC_SMPR2((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__)));     \
+  } while(0)
+#else
+#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
+                    MODIFY_REG((__HANDLE__)->Instance->SMPR2,                  \
+                               ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)),    \
+                               ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__)))
+#endif
+
+
+/**
+  * @brief Set the selected regular Channel rank for rank between 1 and 4.
+  * @param __CHANNELNB__: Channel number.
+  * @param __RANKNB__: Rank number.    
+  * @retval None
+  */                                                                   
+#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
+
+/**
+  * @brief Set the selected regular Channel rank for rank between 5 and 9.
+  * @param __CHANNELNB__: Channel number.
+  * @param __RANKNB__: Rank number.    
+  * @retval None
+  */
+#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
+
+/**
+  * @brief Set the selected regular Channel rank for rank between 10 and 14.
+  * @param __CHANNELNB__: Channel number.
+  * @param __RANKNB__: Rank number.    
+  * @retval None
+  */
+#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
+
+/**
+  * @brief Set the selected regular Channel rank for rank between 15 and 16.
+  * @param __CHANNELNB__: Channel number.
+  * @param __RANKNB__: Rank number.    
+  * @retval None
+  */
+#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
+
+/**
+  * @brief Set the selected injected Channel rank.
+  * @param __CHANNELNB__: Channel number.
+  * @param __RANKNB__: Rank number.   
+  * @retval None
+  */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
+
+
+/**
+  * @brief Set the Analog Watchdog 1 channel.
+  * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
+  * @retval None
+  */
+#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
+
+/**
+  * @brief Configure the channel number in Analog Watchdog 2 or 3.
+  * @param __CHANNEL__: ADC Channel
+  * @retval None
+  */
+#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__)) 
+
+/**
+  * @brief Configure ADC injected context queue
+  * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
+  * @retval None
+  */                                                                                            
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for injected group
+  * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  POSITION_VAL(ADC_CFGR_JDISCEN))
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for regular group
+  * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
+  * @retval None
+  */                                                                                                  
+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
+/**
+  * @brief Configure the number of discontinuous conversions for regular group.
+  * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
+  * @retval None
+  */
+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
+
+/**
+  * @brief Configure the ADC auto delay mode.
+  * @param __AUTOWAIT__: Auto delay bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
+
+/**
+  * @brief Configure ADC continuous conversion mode.
+  * @param __CONTINUOUS_MODE__: Continuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
+    
+/**
+  * @brief Configure the ADC DMA continuous request.
+  * @param __DMACONTREQ_MODE__: DMA continuous request mode.
+  * @retval None
+  */                                                                              
+#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) <<  POSITION_VAL(ADC_CFGR_DMACFG))
+
+
+/**
+  * @brief Configure the channel number into offset OFRx register.
+  * @param __CHANNEL__: ADC Channel.
+  * @retval None
+  */
+#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
+
+/**
+  * @brief Configure the channel number into differential mode selection register.
+  * @param __CHANNEL__: ADC Channel.
+  * @retval None
+  */
+#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) 
+
+/**
+  * @brief Configure calibration factor in differential mode to be set into calibration register.
+  * @param __CALIBRATION_FACTOR__: Calibration factor value.
+  * @retval None
+  */
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
+/**
+  * @brief Calibration factor in differential mode to be retrieved from calibration register.
+  * @param __CALIBRATION_FACTOR__: Calibration factor value.
+  * @retval None
+  */                                                                                
+#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
+     
+/**
+  * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+  * @param __THRESHOLD__: Threshold value.
+  * @retval None
+  */
+#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+/**
+  * @brief Configure the ADC DMA continuous request for ADC multimode.
+  * @param __DMACONTREQ_MODE__: DMA continuous request mode.
+  * @retval None
+  */                                                                               
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/**
+  * @brief Enable the ADC peripheral.
+  * @param __HANDLE__: ADC handle.
+  * @retval None
+  */
+#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
+
+/**
+  * @brief Verification of hardware constraints before ADC can be enabled.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
+  */
+#define ADC_ENABLING_CONDITIONS(__HANDLE__)                             \
+       (( ( ((__HANDLE__)->Instance->CR) &                                    \
+            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |  \
+             ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN                    ) \
+           ) == RESET                                                         \
+        ) ? SET : RESET)
+         
+/**
+  * @brief Disable the ADC peripheral.
+  * @param __HANDLE__: ADC handle.
+  * @retval None
+  */
+#define ADC_DISABLE(__HANDLE__)                                          \
+  do{                                                                          \
+         (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
+          __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
+  } while(0)
+    
+/**
+  * @brief Verification of hardware constraints before ADC can be disabled.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
+  */
+#define ADC_DISABLING_CONDITIONS(__HANDLE__)                             \
+       (( ( ((__HANDLE__)->Instance->CR) &                                     \
+            (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
+        ) ? SET : RESET)
+         
+/**
+  * @brief Shift the offset with respect to the selected ADC resolution. 
+  * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *         If resolution 12 bits, no shift.
+  *         If resolution 10 bits, shift of 2 ranks on the left.
+  *         If resolution 8 bits, shift of 4 ranks on the left.
+  *         If resolution 6 bits, shift of 6 ranks on the left.
+  *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+  * @param __HANDLE__: ADC handle
+  * @param __OFFSET__: Value to be shifted
+  * @retval None
+  */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+        ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
+
+
+/**
+  * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
+  * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the left.
+  *        If resolution 8 bits, shift of 4 ranks on the left.
+  *        If resolution 6 bits, shift of 6 ranks on the left.
+  *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+  * @param __HANDLE__: ADC handle
+  * @param __THRESHOLD__: Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+        ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
+
+/**
+  * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
+  * @note  Thresholds have to be left-aligned on bit 7.
+  *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
+  *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
+  *        If resolution 8 bits, no shift.
+  *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
+  * @param __HANDLE__: ADC handle
+  * @param __THRESHOLD__: Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+         ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
+            ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
+            (__THRESHOLD__) << 2 )
+
+/**
+  * @brief Report ADC common register.
+  * @param __HANDLE__: ADC handle.
+  * @retval Common control register
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_COMMON_REGISTER(__HANDLE__)   (ADC123_COMMON)       
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_COMMON_REGISTER(__HANDLE__)   (ADC1_COMMON)  
+#endif
+
+/**
+  * @brief Report Master Instance.
+  * @param __HANDLE__: ADC handle.
+  * @note Return same instance if ADC of input handle is independent ADC or if 
+  *       multimode feature is not available.     
+  * @retval Master Instance
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 
+#define ADC_MASTER_REGISTER(__HANDLE__)                                          \
+  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
+    )?                                                                           \
+     ((__HANDLE__)->Instance)                                                    \
+     :                                                                           \
+     (ADC1)                                                                      \
+  )
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_MASTER_REGISTER(__HANDLE__)   ((__HANDLE__)->Instance) 
+#endif
+       
+/**
+  * @brief Clear Common Control Register.
+  * @param __HANDLE__: ADC handle.     
+  * @retval None
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
+                                                                                                      ADC_CCR_PRESC  | \
+                                                                                                      ADC_CCR_VBATEN | \
+                                                                                                      ADC_CCR_TSEN   | \
+                                                                                                      ADC_CCR_VREFEN | \
+                                                                                                      ADC_CCR_MDMA   | \
+                                                                                                      ADC_CCR_DMACFG | \
+                                                                                                      ADC_CCR_DELAY  | \
+                                                                                                      ADC_CCR_DUAL  )
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
+                                                                                                      ADC_CCR_PRESC  | \
+                                                                                                      ADC_CCR_VBATEN | \
+                                                                                                      ADC_CCR_TSEN   | \
+                                                                                                      ADC_CCR_VREFEN )
+#endif                                                
+                                                      
+                                                      
+/**                                                   
+  * @brief Check whether or not dual conversions are enabled.
+  * @param __HANDLE__: ADC handle.
+  * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.   
+  * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__)                                \
+  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+    )?                                                                           \
+     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)  )          \
+     :                                                                           \
+     RESET                                                                       \
+  )
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__)    (RESET) 
+#endif              
+       
+/**
+  * @brief Check whether or not dual regular conversions are enabled.
+  * @param __HANDLE__: ADC handle.
+  * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.   
+  * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)                        \
+  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+    )?                                                                           \
+     ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
+       (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
+       (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
+     :                                                                           \
+     RESET                                                                       \
+  )
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)    (RESET) 
+#endif
+                        
+
+/**
+  * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
+  * @param __HANDLE__: ADC handle.
+  * @note Return SET if multimode feature is not available.     
+  * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)     \
+    )?                                                                         \
+     SET                                                                       \
+     :                                                                         \
+     ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
+  )
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)    (SET) 
+#endif  
+  
+/**
+  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
+  * @param __HANDLE__: ADC handle.
+  * @note Return SET if multimode feature is not available.  
+  * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
+    )?                                                                      \
+     SET                                                                    \
+     :                                                                      \
+     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
+       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
+       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))  
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)    (SET) 
+#endif  
+
+/**
+  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
+  * @param __HANDLE__: ADC handle.
+  * @note Return SET if multimode feature is not available.  
+  * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)          \
+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
+    )?                                                                     \
+     SET                                                                   \
+     :                                                                     \
+     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
+       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
+       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)    (SET) 
+#endif   
+  
+/**
+  * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
+  * @param __INSTANCE__: ADC instance.
+  * @retval SET (ADC enabled) or RESET (ADC disabled)
+  */
+#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__)                                       \
+       (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+          ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
+        ) ? SET : RESET)  
+  
+/**
+  * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
+  */ 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)   
+#define ADC_ANY_OTHER_ENABLED(__HANDLE__)                                   \
+  ( ( ((__HANDLE__)->Instance == ADC1)                                      \
+    )?                                                                      \
+     (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3))     \
+     :                                                                      \
+     ( ( ((__HANDLE__)->Instance == ADC2)                                   \
+       )?                                                                   \
+         (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
+        :                                                                   \
+          ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \
+     )
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_ANY_OTHER_ENABLED(__HANDLE__)    (RESET) 
+#endif  
+
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+/**
+  * @brief Set handle instance of the ADC slave associated to the ADC master.
+  * @param __HANDLE_MASTER__: ADC master handle.
+  * @param __HANDLE_SLAVE__: ADC slave handle.
+  * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL.
+  * @retval None
+  */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
+  ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */  
+ 
+
+/**
+  * @brief Check whether or not multimode is configured in DMA mode.
+  * @note  Return RESET if multimode feature is not available.  
+  * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
+  */ 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)   
+#define ADC_MULTIMODE_DMA_ENABLED()                                     \
+    ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
+  || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))  
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define ADC_MULTIMODE_DMA_ENABLED()    (RESET) 
+#endif  
+ 
+
+/**
+  * @brief Verify the ADC instance connected to the temperature sensor.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */  
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+/*  The temperature sensor measurement path (channel 17) is available on ADC1 */  
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+/*  The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */                        
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
+#endif
+
+/**
+  * @brief Verify the ADC instance connected to the battery voltage VBAT.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */  
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+/*  The battery voltage measurement path (channel 18) is available on ADC1 */  
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+/*  The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */                        
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
+#endif
+
+/**
+  * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
+  * @param __HANDLE__: ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */  
+/*  The internal voltage reference  VREFINT measurement path (channel 0) is available on ADC1 */  
+#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+
+ 
+/**
+  * @brief Verify the length of scheduled injected conversions group.
+  * @param __LENGTH__: number of programmed conversions.   
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
+  */  
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
+  
+  
+/**
+  * @brief Calibration factor size verification (7 bits maximum).
+  * @param __CALIBRATION_FACTOR__: Calibration factor value.
+  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+  */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
+
+ 
+/**
+  * @brief Verify the ADC channel setting.
+  * @param __HANDLE__: ADC handle.
+  * @param __CHANNEL__: programmed ADC channel. 
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_18)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)))
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)))      || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_18)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)   ))) 
+#endif
+ 
+/**
+  * @brief Verify the ADC channel setting in differential mode.
+  * @param __HANDLE__: ADC handle.
+  * @param __CHANNEL__: programmed ADC channel. 
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */  
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_2)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_3)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_4)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_5)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_6)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_7)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_8)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_9)      || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_10)     || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_11)     || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_12)     || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_13)     || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_14)     || \
+                                                      ((__CHANNEL__) == ADC_CHANNEL_15)       )
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)   
+    /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 
+                          channels 0, 16 to 18 can be only used in single-ended mode. 
+       For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
+                 channels 4, 5 and 13 to 18 can only be used in single-ended mode.  */                         
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ((((((__HANDLE__)->Instance) == ADC1)   || \
+                                                         (((__HANDLE__)->Instance) == ADC2))  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_1)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)    || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))) || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_1)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)   || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)   )))
+#endif                     
+                               
+/**                            
+  * @brief Verify the ADC single-ended input or differential mode setting.
+  * @param __SING_DIFF__: programmed channel setting. 
+  * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+  */                           
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
+                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
+                               
+/**
+  * @brief Verify the ADC offset management setting.
+  * @param __OFFSET_NUMBER__: ADC offset management. 
+  * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
+  */ 
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      ) 
+
+/**
+  * @brief Verify the ADC injected channel setting.
+  * @param __CHANNEL__: programmed ADC injected channel. 
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   ) 
+
+/**
+  * @brief Verify the ADC injected conversions external trigger.
+  * @param __INJTRIG__: programmed ADC injected conversions external trigger.
+  * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
+  */ 
+#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
+                                                                                                  \
+                                          ((__INJTRIG__) == ADC_SOFTWARE_START)                   )  
+
+/**
+  * @brief Verify the ADC edge trigger setting for injected group.
+  * @param __EDGE__: programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */ 
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)        || \
+                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
+                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
+                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)   
+/**
+  * @brief Verify the ADC multimode setting.
+  * @param __MODE__: programmed ADC multimode setting.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)          || \
+                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
+                               ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
+                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
+                               ((__MODE__) == ADC_DUALMODE_INTERL)                || \
+                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               ) 
+
+/**
+  * @brief Verify the ADC multimode DMA access setting.
+  * @param __MODE__: programmed ADC multimode DMA access setting.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
+                                               ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
+                                               ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     ) 
+
+/**
+  * @brief Verify the ADC multimode delay setting.
+  * @param __DELAY__: programmed ADC multimode delay setting.
+  * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+  */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   ) 
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/**
+  * @brief Verify the ADC analog watchdog setting.
+  * @param __WATCHDOG__: programmed ADC analog watchdog setting.
+  * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   ) 
+
+/**
+  * @brief Verify the ADC analog watchdog mode setting.
+  * @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting.
+  * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       ) 
+
+/**
+  * @brief Verify the ADC conversion (regular or injected or both).
+  * @param __CONVERSION__: ADC conversion group.
+  * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+  */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)     || \
+                                             ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
+                                             ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
+
+/**
+  * @brief Verify the ADC event type.
+  * @param __EVENT__: ADC event.
+  * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+  */
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
+                                     ((__EVENT__) == ADC_AWD_EVENT)    || \
+                                     ((__EVENT__) == ADC_AWD2_EVENT)   || \
+                                     ((__EVENT__) == ADC_AWD3_EVENT)   || \
+                                     ((__EVENT__) == ADC_OVR_EVENT)    || \
+                                     ((__EVENT__) == ADC_JQOVF_EVENT)  ) 
+
+/**
+  * @brief Verify the ADC oversampling ratio. 
+  * @param __RATIO__: programmed ADC oversampling ratio.
+  * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+  */   
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
+
+/**
+  * @brief Verify the ADC oversampling shift. 
+  * @param __SHIFT__: programmed ADC oversampling shift.
+  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+  */                 
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
+
+/**
+  * @brief Verify the ADC oversampling triggered mode. 
+  * @param __MODE__: programmed ADC oversampling triggered mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 
+
+/**
+  * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 
+  * @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )              
+
+ 
+/**
+  * @brief Verify the DFSDM mode configuration. 
+  * @param __HANDLE__: ADC handle. 
+  * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
+  *      this reason, the input parameter is the ADC handle and not the configuration parameter
+  *      directly.      
+  * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
+  */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \
+                                          ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
+#else                                               
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+
+/**
+  * @brief Return the DFSDM configuration mode. 
+  * @param __HANDLE__: ADC handle. 
+  * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 
+  *       For this reason, the input parameter is the ADC handle and not the configuration parameter
+  *       directly.      
+  * @retval DFSDM configuration mode
+  */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
+#else                                               
+#define ADC_CFGR_DFSDM(__HANDLE__) (0x0)
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+                                                  
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/  
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */ 
+          
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */ 
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
+uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+     
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)   
+/* ADC multimode */
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 
+uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
+
+/* ADC Regular conversions stop */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+
+/**
+  * @}
+  */
+     
+/** @addtogroup ADCEx_Exported_Functions_Group2
+  * @{
+  */ 
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */
+HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c
new file mode 100755
index 0000000..9dfd4d0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c
@@ -0,0 +1,1410 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_can.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   CAN HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Controller Area Network (CAN) peripheral:           
+  *           + Initialization and de-initialization functions 
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================    
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]            
+      (#) Enable the CAN controller interface clock using 
+          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1.
+       
+      (#) CAN pins configuration
+        (++) Enable the clock for the CAN GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();   
+        (++) Connect and configure the involved CAN pins using the 
+              following function HAL_GPIO_Init(); 
+              
+      (#) Initialize and configure the CAN using HAL_CAN_Init() function.   
+                 
+      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or 
+          HAL_CAN_Transmit_IT() function.
+           
+      (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function.
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the CAN peripheral transmission and wait the end of this operation 
+           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+           according to his end application
+       (+) Start the CAN peripheral reception and wait the end of this operation 
+           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+           according to his end application 
+       
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..]    
+       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()         
+       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_CAN_TxCpltCallback 
+       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_CAN_ErrorCallback
+ 
+     *** CAN HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in CAN HAL driver.
+       
+      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+      
+     [..] 
+      (@) You can refer to the CAN HAL driver header file for more useful macros 
+                
+  @endverbatim
+           
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CAN CAN
+  * @brief CAN driver modules
+  * @{
+  */ 
+  
+#ifdef HAL_CAN_MODULE_ENABLED  
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+  * @{
+  */
+#define CAN_TIMEOUT_VALUE  10
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+  * @{
+  */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the CAN. 
+      (+) De-initialize the CAN. 
+         
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initialize the CAN peripheral according to the specified parameters 
+  *         in the CAN_InitStruct structure and initialize the associated handle.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+  uint32_t status = CAN_INITSTATUS_FAILED;  /* Default init status */
+  uint32_t tickstart = 0;
+  
+  /* Check CAN handle */
+  if(hcan == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+  assert_param(IS_CAN_MODE(hcan->Init.Mode));
+  assert_param(IS_CAN_SJW(hcan->Init.SJW));
+  assert_param(IS_CAN_BS1(hcan->Init.BS1));
+  assert_param(IS_CAN_BS2(hcan->Init.BS2));
+  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+  
+  if(hcan->State == HAL_CAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcan->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_CAN_MspInit(hcan);
+  }
+  
+  /* Initialize the CAN state*/
+  hcan->State = HAL_CAN_STATE_BUSY;
+  
+  /* Exit from sleep mode */
+  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+  /* Request initialisation */
+  hcan->Instance->MCR |= CAN_MCR_INRQ ;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait the acknowledge */
+  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  {
+    if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+    {
+      hcan->State= HAL_CAN_STATE_TIMEOUT;
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check acknowledge */
+  if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+  {
+    /* Set the time triggered communication mode */
+    if (hcan->Init.TTCM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_TTCM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+    }
+
+    /* Set the automatic bus-off management */
+    if (hcan->Init.ABOM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_ABOM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (hcan->Init.AWUM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_AWUM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+    }
+
+    /* Set the no automatic retransmission */
+    if (hcan->Init.NART == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_NART;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (hcan->Init.RFLM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_RFLM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (hcan->Init.TXFP == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_TXFP;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+    }
+
+    /* Set the bit timing register */
+    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
+                ((uint32_t)hcan->Init.SJW) | \
+                ((uint32_t)hcan->Init.BS1) | \
+                ((uint32_t)hcan->Init.BS2) | \
+               ((uint32_t)hcan->Init.Prescaler - 1);
+
+    /* Request leave initialisation */
+    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+   
+    /* Wait the acknowledge */
+    while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+    {
+      if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+      {
+         hcan->State= HAL_CAN_STATE_TIMEOUT;
+         /* Process unlocked */
+         __HAL_UNLOCK(hcan);
+         return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check acknowledged */
+    if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+    {
+      status = CAN_INITSTATUS_SUCCESS;
+    }
+  }
+ 
+  if(status == CAN_INITSTATUS_SUCCESS)
+  {
+    /* Set CAN error code to none */
+    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+    
+    /* Initialize the CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+  
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Initialize the CAN state */
+    hcan->State = HAL_CAN_STATE_ERROR;
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the CAN reception filter according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+  *         contains the filter configuration information.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+  uint32_t filternbrbitpos = 0;
+  
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* Check the parameters */
+  assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+  assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+  assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+  assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+  assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+  assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+
+  filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+
+  /* Initialisation mode for the filter */
+  CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
+  
+#if defined(CAN2)
+  /* Select the start slave bank */
+  CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
+  CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
+#endif
+
+  /* Filter Deactivation */
+  CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
+
+  /* Filter Scale */
+  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+  {
+    /* 16-bit scale for the filter */
+    CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+  }
+
+  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+  {
+    /* 32-bit scale for the filter */
+    CAN1->FS1R |= filternbrbitpos;
+    /* 32-bit identifier or First 32-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+    /* 32-bit mask or Second 32-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+  }
+
+  /* Filter Mode */
+  if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+  {
+    /*Id/Mask mode for the filter*/
+    CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CAN1->FM1R |= (uint32_t)filternbrbitpos;
+  }
+
+  /* Filter FIFO assignment */
+  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
+  }
+
+  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CAN1->FFA1R |= (uint32_t)filternbrbitpos;
+  }
+  
+  /* Filter activation */
+  if (sFilterConfig->FilterActivation == ENABLE)
+  {
+    CAN1->FA1R |= filternbrbitpos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the CAN peripheral registers to their default reset values. 
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+  /* Check CAN handle */
+  if(hcan == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_CAN_MspDeInit(hcan);
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcan);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the CAN MSP.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval None
+  */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CAN_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the CAN MSP.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval None
+  */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CAN_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief    I/O operation functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Transmit a CAN frame message.
+      (+) Receive a CAN frame message.
+      (+) Enter CAN peripheral in sleep mode. 
+      (+) Wake up the CAN peripheral from sleep mode.
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initiate and transmit a CAN frame message.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+  uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+  
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX;
+  }
+  
+  /* Select one empty transmit mailbox */
+  if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  {
+    transmitmailbox = 0;
+  }
+  else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+  {
+    transmitmailbox = 1;
+  }
+  else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  {
+    transmitmailbox = 2;
+  }
+
+  if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+  {
+    /* Set up the Id */
+    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+    if (hcan->pTxMsg->IDE == CAN_ID_STD)
+    {
+      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+                                                  hcan->pTxMsg->RTR);
+    }
+    else
+    {
+      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+                                                  hcan->pTxMsg->IDE | \
+                                                  hcan->pTxMsg->RTR);
+    }
+    
+    /* Set up the DLC */
+    hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+    /* Set up the data field */
+    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[0]));
+    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+                                             ((uint32_t)hcan->pTxMsg->Data[4]));
+    /* Request transmission */
+    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+  
+    /* Get tick */
+    tickstart = HAL_GetTick();
+  
+    /* Check End of transmission flag */
+    while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          hcan->State = HAL_CAN_STATE_TIMEOUT;
+          /* Process unlocked */
+          __HAL_UNLOCK(hcan);
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_BUSY_RX;
+    }
+    else
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_READY;
+    }
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_ERROR; 
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initiate and transmit a CAN frame message in Interrupt mode.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+  uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+  
+  if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcan);
+    
+    /* Select one empty transmit mailbox */
+    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+    {
+      transmitmailbox = 0;
+    }
+    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+    {
+      transmitmailbox = 1;
+    }
+    else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+    {
+      transmitmailbox = 2;
+    }
+
+    if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+    {
+      /* Set up the Id */
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+      if(hcan->pTxMsg->IDE == CAN_ID_STD)
+      {
+        assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+                                                  hcan->pTxMsg->RTR);
+      }
+      else
+      {
+        assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+                                                  hcan->pTxMsg->IDE | \
+                                                  hcan->pTxMsg->RTR);
+      }
+    
+      /* Set up the DLC */
+      hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+      hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+      hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+      /* Set up the data field */
+      hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[0]));
+      hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+                                             ((uint32_t)hcan->pTxMsg->Data[4]));
+    
+      if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
+      {
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+      }
+      else
+      {
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_BUSY_TX;
+      }
+      
+      /* Set CAN error code to none */
+      hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcan);
+      
+      /* Enable interrupts: */
+      /*  - Enable Error warning Interrupt */
+      /*  - Enable Error passive Interrupt */
+      /*  - Enable Bus-off Interrupt */
+      /*  - Enable Last error code Interrupt */
+      /*  - Enable Error Interrupt */
+      /*  - Enable Transmit mailbox empty Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+                                CAN_IT_EPV |
+                                CAN_IT_BOF |
+                                CAN_IT_LEC |
+                                CAN_IT_ERR |
+                                CAN_IT_TME  );
+      
+      /* Request transmission */
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive a correct CAN frame.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  FIFONumber:    FIFO number.
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_RX;
+  }
+    
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  /* Check pending message */
+  while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+      {
+        hcan->State = HAL_CAN_STATE_TIMEOUT;
+        /* Process unlocked */
+        __HAL_UNLOCK(hcan);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Get the Id */
+  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  if (hcan->pRxMsg->IDE == CAN_ID_STD)
+  {
+    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  
+  /* Release the FIFO */
+  if(FIFONumber == CAN_FIFO0)
+  {
+    /* Release FIFO0 */
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+  }
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    /* Release FIFO1 */
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcan);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive a correct CAN frame in Interrupt mode.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  FIFONumber:    FIFO number.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  
+  if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
+  {
+    /* Process locked */
+    __HAL_LOCK(hcan);
+  
+    if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_BUSY_RX;
+    }
+    
+    /* Set CAN error code to none */
+    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+    
+    /* Enable interrupts: */
+    /*  - Enable Error warning Interrupt */
+    /*  - Enable Error passive Interrupt */
+    /*  - Enable Bus-off Interrupt */
+    /*  - Enable Last error code Interrupt */
+    /*  - Enable Error Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+                              CAN_IT_EPV |
+                              CAN_IT_BOF |
+                              CAN_IT_LEC |
+                              CAN_IT_ERR );
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    if(FIFONumber == CAN_FIFO0)
+    {
+      /* Enable FIFO 0 message pending Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+    }
+    else
+    {
+      /* Enable FIFO 1 message pending Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+    }
+    
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enter the Sleep (low power) mode.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+  uint32_t tickstart = 0;
+   
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_BUSY; 
+    
+  /* Request Sleep mode */
+   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+   
+  /* Sleep mode status */
+  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  /* Wait the acknowledge */
+  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+  {
+    if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+    {
+      hcan->State = HAL_CAN_STATE_TIMEOUT;
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcan);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wake up the CAN peripheral from sleep mode (after that the CAN peripheral
+  *         is in the normal mode).
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+  uint32_t tickstart = 0;
+    
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_BUSY;  
+ 
+  /* Wake up request */
+  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Sleep mode status */
+  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+  {
+    if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+    {
+      hcan->State= HAL_CAN_STATE_TIMEOUT;
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+      return HAL_TIMEOUT;
+    }
+  }
+  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcan);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle CAN interrupt request.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+  /* Check End of transmission flag */
+  if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+  {
+    if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
+       (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
+       (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
+    {
+      /* Call transmit function */
+      CAN_Transmit_IT(hcan);
+    }
+  }
+  
+  /* Check End of reception flag for FIFO0 */
+  if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
+     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+  {
+    /* Call receive function */
+    CAN_Receive_IT(hcan, CAN_FIFO0);
+  }
+  
+  /* Check End of reception flag for FIFO1 */
+  if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
+     (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+  {
+    /* Call receive function */
+    CAN_Receive_IT(hcan, CAN_FIFO1);
+  }
+  
+  /* Check Error Warning Flag */
+  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG))    &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+  {
+    /* Set CAN error code to EWG error */
+    hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+    /* No need for clear of Error Warning Flag as read-only */
+  }
+  
+  /* Check Error Passive Flag */
+  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV))    &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+  {
+    /* Set CAN error code to EPV error */
+    hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+    /* No need for clear of Error Passive Flag as read-only */ 
+  }
+  
+  /* Check Bus-Off Flag */
+  if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF))    &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+  {
+    /* Set CAN error code to BOF error */
+    hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+    /* No need for clear of Bus-Off Flag as read-only */
+  }
+  
+  /* Check Last error code Flag */
+  if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC))         &&
+     (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+  {
+    switch(hcan->Instance->ESR & CAN_ESR_LEC)
+    {
+      case(CAN_ESR_LEC_0):
+          /* Set CAN error code to STF error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+          break;
+      case(CAN_ESR_LEC_1):
+          /* Set CAN error code to FOR error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+          break;
+      case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+          /* Set CAN error code to ACK error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+          break;
+      case(CAN_ESR_LEC_2):
+          /* Set CAN error code to BR error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+          break;
+      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+          /* Set CAN error code to BD error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+          break;
+      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+          /* Set CAN error code to CRC error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+          break;
+      default:
+          break;
+    }
+
+    /* Clear Last error code Flag */ 
+    hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+  }
+
+  /* Call the Error call Back in case of Errors */
+  if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+  {
+    /* Clear ERRI bit */
+    SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
+    /* Set the CAN state ready to be able to start again the process */
+    hcan->State = HAL_CAN_STATE_READY;
+    /* Call Error callback function */
+    HAL_CAN_ErrorCallback(hcan);
+  }  
+}
+
+/**
+  * @brief  Transmission complete callback in non-blocking mode.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CAN_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Reception complete callback in non-blocking mode.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CAN_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error CAN callback.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Check the CAN state.
+      (+) Check CAN Errors detected during interrupt process.
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CAN handle state.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL state
+  */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+  /* Return CAN handle state */
+  return hcan->State;
+}
+
+/**
+  * @brief  Return the CAN error code.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval CAN Error Code
+  */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+  return hcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+/**
+  * @brief  Initiate and transmit a CAN frame message.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+  /* Disable Transmit mailbox empty Interrupt */
+  __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+  {   
+    /* Disable interrupts: */
+    /*  - Disable Error warning Interrupt */
+    /*  - Disable Error passive Interrupt */
+    /*  - Disable Bus-off Interrupt */
+    /*  - Disable Last error code Interrupt */
+    /*  - Disable Error Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+                               CAN_IT_EPV |
+                               CAN_IT_BOF |
+                               CAN_IT_LEC |
+                               CAN_IT_ERR  );
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_RX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+  }
+  
+  /* Transmission complete callback */ 
+  HAL_CAN_TxCpltCallback(hcan);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive a correct CAN frame.
+  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  FIFONumber: Specify the FIFO number    
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+  /* Get the Id */
+  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  if (hcan->pRxMsg->IDE == CAN_ID_STD)
+  {
+    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  /* Release the FIFO */
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+    
+    /* Disable FIFO 0 message pending Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+    
+    /* Disable FIFO 1 message pending Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+  {
+    /* Disable interrupts: */
+    /*  - Disable Error warning Interrupt */
+    /*  - Disable Error passive Interrupt */
+    /*  - Disable Bus-off Interrupt */
+    /*  - Disable Last error code Interrupt */
+    /*  - Disable Error Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+                               CAN_IT_EPV |
+                               CAN_IT_BOF |
+                               CAN_IT_LEC |
+                               CAN_IT_ERR  );
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+  {
+    /* Disable CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+  }
+
+  /* Receive complete callback */ 
+  HAL_CAN_RxCpltCallback(hcan);
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h
new file mode 100755
index 0000000..f71bf09
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h
@@ -0,0 +1,768 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_can.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_CAN_H
+#define __STM32L4xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
+  HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */
+  HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< Timeout state                       */
+  HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
+  uint32_t Mode;       /*!< Specifies the CAN operating mode.
+                            This parameter can be a value of @ref CAN_operating_mode */
+
+  uint32_t SJW;        /*!< Specifies the maximum number of time quanta
+                            the CAN hardware is allowed to lengthen or
+                            shorten a bit to perform resynchronization.
+                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
+                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
+                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
+                            This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
+                            This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/**
+  * @brief  CAN filter configuration structure definition
+  */
+typedef struct
+{
+  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                       configuration, first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                       configuration, second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (MSBs for a 32-bit configuration,
+                                       first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (LSBs for a 32-bit configuration,
+                                       second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                       This parameter can be a value of @ref CAN_filter_FIFO */
+
+  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                       This parameter can be a value of @ref CAN_filter_mode */
+
+  uint32_t FilterScale;           /*!< Specifies the filter scale.
+                                       This parameter can be a value of @ref CAN_filter_scale */
+
+  uint32_t FilterActivation;      /*!< Enable or disable the filter.
+                                       This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t BankNumber;            /*!< Select the start slave bank filter.
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ 
+
+}CAN_FilterConfTypeDef;
+
+/**
+  * @brief  CAN Tx message structure definition
+  */
+typedef struct
+{
+  uint32_t StdId;    /*!< Specifies the standard identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+  uint32_t ExtId;    /*!< Specifies the extended identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+  uint8_t Data[8];   /*!< Contains the data to be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+}CanTxMsgTypeDef;
+
+/**
+  * @brief  CAN Rx message structure definition
+  */
+typedef struct
+{
+  uint32_t StdId;       /*!< Specifies the standard identifier.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+  uint32_t ExtId;       /*!< Specifies the extended identifier.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
+                             This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
+                             This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+  uint8_t Data[8];      /*!< Contains the data to be received.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
+                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+  * @brief  CAN handle Structure definition
+  */
+typedef struct
+{
+  CAN_TypeDef                 *Instance;  /*!< Register base address          */
+
+  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
+
+  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
+
+  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
+
+  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
+
+  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
+
+  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
+
+}CAN_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+  * @{
+  */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+  * @{
+  */
+#define   HAL_CAN_ERROR_NONE        ((uint32_t)0x00000000)    /*!< No error             */
+#define   HAL_CAN_ERROR_EWG         ((uint32_t)0x00000001)    /*!< EWG error            */
+#define   HAL_CAN_ERROR_EPV         ((uint32_t)0x00000002)    /*!< EPV error            */
+#define   HAL_CAN_ERROR_BOF         ((uint32_t)0x00000004)    /*!< BOF error            */
+#define   HAL_CAN_ERROR_STF         ((uint32_t)0x00000008)    /*!< Stuff error          */
+#define   HAL_CAN_ERROR_FOR         ((uint32_t)0x00000010)    /*!< Form error           */
+#define   HAL_CAN_ERROR_ACK         ((uint32_t)0x00000020)    /*!< Acknowledgment error */
+#define   HAL_CAN_ERROR_BR          ((uint32_t)0x00000040)    /*!< Bit recessive        */
+#define   HAL_CAN_ERROR_BD          ((uint32_t)0x00000080)    /*!< LEC dominant         */
+#define   HAL_CAN_ERROR_CRC         ((uint32_t)0x00000100)   /*!< LEC transfer error   */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_InitStatus CAN initialization Status
+  * @{
+  */
+#define CAN_INITSTATUS_FAILED       ((uint32_t)0x00000000)  /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS      ((uint32_t)0x00000001)  /*!< CAN initialization OK */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+  * @{
+  */
+#define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
+#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
+#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
+#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+  * @{
+  */
+#define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
+#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
+#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
+#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+  * @{
+  */
+#define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
+#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
+#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
+#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
+#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
+#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
+#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
+#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
+#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
+#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
+#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
+#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
+#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
+#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
+#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
+#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+  * @{
+  */
+#define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
+#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
+#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
+#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
+#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
+#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
+#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
+#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+  * @{
+  */
+#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+  * @{
+  */
+#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+  * @{
+  */
+#define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+  * @{
+  */
+#define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+  * @{
+  */
+#define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
+  * @{
+  */
+#define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags CAN Flags
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
+#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
+#define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
+#define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
+#define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_interrupts CAN Interrupts
+  * @{
+  */
+#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
+#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
+#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
+#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
+#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
+#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
+#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
+#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
+
+/**
+  * @}
+  */
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macro CAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset CAN handle state.
+  * @param  __HANDLE__: CAN handle.
+  * @retval None
+  */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+  * @brief  Enable the specified CAN interrupt.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __INTERRUPT__: CAN Interrupt.
+  * @retval None
+  */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CAN interrupt.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __INTERRUPT__: CAN Interrupt.
+  * @retval None
+  */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Return the number of pending received messages.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval The number of pending message.
+  */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief  Check whether the specified CAN flag is set or not.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
+  *            @arg CAN_FLAG_EPV: Error Passive Flag
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief  Clear the specified CAN pending flag.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
+
+
+/** @brief  Check whether the specified CAN interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+  *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
+  *            @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Check the transmission status of a CAN Frame.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @retval The new status of transmission  (TRUE or FALSE).
+  */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+
+
+/**
+  * @brief  Release the specified receive FIFO.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None
+  */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 
+
+/**
+  * @brief  Cancel a transmit request.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @retval None
+  */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+  * @brief  Enable or disable the DBG Freeze for CAN.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __NEWSTATE__: new state of the CAN peripheral. 
+  *         This parameter can be: ENABLE (CAN reception/transmission is frozen
+  *         during debug. Reception FIFO can still be accessed/controlled normally) 
+  *         or DISABLE (CAN is working during debug).
+  * @retval None
+  */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
+
+/**
+ * @}
+ */  
+ 
+/* Exported functions --------------------------------------------------------*/  
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+  * @{
+  */
+  
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ * @{
+ */
+/* addtogroup and de-initialization functions *****************************/ 
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */ 
+ 
+/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief    I/O operation functions 
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */ 
+ 
+/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions 
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */ 
+
+/**
+ * @}
+ */ 
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+  * @{
+  */
+/** @defgroup CAN_transmit_constants CAN Transmit Constants
+  * @{
+  */
+#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+/**
+  * @}
+  */
+#define CAN_FLAG_MASK     ((uint32_t)0x000000FF)
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+  * @{
+  */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+                           ((MODE) == CAN_MODE_LOOPBACK)|| \
+                           ((MODE) == CAN_MODE_SILENT) || \
+                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+                                  ((MODE) == CAN_FILTERMODE_IDLIST))
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+                                  ((FIFO) == CAN_FILTER_FIFO1))
+
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
+                                ((IDTYPE) == CAN_ID_EXT))
+
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c
new file mode 100755
index 0000000..aea1106
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c
@@ -0,0 +1,753 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_comp.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   COMP HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the COMP peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Start/Stop operation functions in polling mode
+  *           + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
+  *           + Peripheral control functions
+  *           + Peripheral state functions
+  *         
+  @verbatim
+================================================================================
+          ##### COMP Peripheral features #####
+================================================================================
+           
+  [..]       
+      The STM32L4xx device family integrates two analog comparators instances
+      COMP1 and COMP2:
+      (#) The COMP input minus (inverting input) and input plus (non inverting input)
+          can be set to internal references or to GPIO pins
+          (refer to GPIO list in reference manual).
+  
+      (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
+          and can be redirected to other peripherals: GPIO pins (in mode
+          alternate functions for comparator), timers.
+          (refer to GPIO list in reference manual).
+  
+      (#) Pairs of comparators instances can be combined in window mode
+          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
+  
+      (#) The comparators have interrupt capability through the EXTI controller
+          with wake-up from sleep and stop modes:
+          (++) COMP1 is internally connected to EXTI Line 21
+          (++) COMP2 is internally connected to EXTI Line 22
+
+          From the corresponding IRQ handler, the right interrupt source can be retrieved
+          using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
+
+            ##### How to use this driver #####
+================================================================================
+  [..]
+      This driver provides functions to configure and program the comparator instances
+      of STM32L4xx devices.
+
+      To use the comparator, perform the following steps:
+      
+      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
+      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
+           using HAL_GPIO_Init().
+      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
+           using HAL_GPIO_Init().
+      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and 
+           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
+           interrupt vector using HAL_NVIC_EnableIRQ() function.
+      
+      (#) Configure the comparator using HAL_COMP_Init() function:
+      (++) Select the input minus (inverting input)
+      (++) Select the input plus (non-inverting input)
+      (++) Select the hysteresis
+      (++) Select the blanking source
+      (++) Select the output polarity  
+      (++) Select the power mode
+      (++) Select the window mode
+      
+      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
+          to enable internal control clock of the comparators.
+          However, this is a legacy strategy. In future STM32 families,
+          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
+          Therefore, for compatibility anticipation, it is recommended to 
+          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
+      
+      (#) Reconfiguration on-the-fly of comparator can be done by calling again
+          function HAL_COMP_Init() with new input structure parameters values.
+      
+      (#) Enable the comparator using HAL_COMP_Start() function.
+      
+      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
+          to manage comparator outputs (events and output level).
+      
+      (#) Disable the comparator using HAL_COMP_Stop() function.
+      
+      (#) De-initialize the comparator using HAL_COMP_DeInit() function.
+      
+      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
+          The only way to unlock the comparator is a device hardware reset.
+  
+  @endverbatim
+  ******************************************************************************
+
+  Table 1. COMP inputs and output for STM32L4xx devices
+  +---------------------------------------------------------+
+  |                |                |   COMP1   |   COMP2   |
+  |----------------|----------------|-----------|-----------|
+  |                | IO1            |    PC5    |    PB4    |
+  | Input plus     | IO2            |    PB2    |    PB6    |
+  |                | IO3 (3)        |    PA1    |    PA3    |
+  |----------------|----------------|-----------------------|
+  |                | 1/4 VrefInt    | Available | Available |
+  |                | 1/2 VrefInt    | Available | Available |
+  |                | 3/4 VrefInt    | Available | Available |
+  | Input minus    | VrefInt        | Available | Available |
+  |                | DAC1 channel 1 | Available | Available |
+  |                | DAC1 channel 2 | Available | Available |
+  |                | IO1            |    PB1    |    PB3    |
+  |                | IO2            |    PC4    |    PB7    |
+  |                | IO3 (3)        |    PA0    |    PA2    |
+  |                | IO4 (3)        |    PA4    |    PA4    |
+  |                | IO5 (3)        |    PA5    |    PA5    |
+  +---------------------------------------------------------+
+  | Output         |                |  PB0  (1) |  PB5  (1) |
+  |                |                |  PB10 (1) |  PB11 (1) |
+  |                |                |  TIM  (2) |  TIM  (2) |
+  +---------------------------------------------------------+
+  (1) GPIO must be set to alternate function for comparator
+  (2) Comparators output to timers is set in timers instances.
+  (3) Only STM32L43x/L44x
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup COMP COMP
+  * @brief COMP HAL module driver
+  * @{
+  */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup COMP_Private_Constants
+  * @{
+  */
+
+/* Delay for COMP startup time.                                               */
+/* Note: Delay required to reach propagation delay specification.             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define COMP_DELAY_STARTUP_US             ((uint32_t) 80U)  /*!< Delay for COMP startup time */
+
+/* Delay for COMP voltage scaler stabilization time.                          */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART_SCALER").                                                */
+/* Unit: us                                                                   */
+#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
+
+#define COMP_OUTPUT_LEVEL_BITOFFSET_POS  ((uint32_t)  30U)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and de-initialization functions. 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions to initialize and de-initialize comparators 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the COMP according to the specified
+  *         parameters in the COMP_InitTypeDef and initialize the associated handle.
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
+{
+  uint32_t tmp_csr = 0;
+  uint32_t exti_line = 0;
+  uint32_t comp_voltage_scaler_not_initialized = 0;
+  __IO uint32_t wait_loop_index = 0;
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
+    assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
+    assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
+    assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
+    assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
+    assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); 
+    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+    assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
+    
+    if(hcomp->State == HAL_COMP_STATE_RESET)
+    {
+      /* Allocate lock resource and initialize it */
+      hcomp->Lock = HAL_UNLOCKED;
+      
+      /* Init SYSCFG and the low level hardware to access comparators */
+      /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE()            */
+      /*       to enable internal control clock of the comparators.           */
+      /*       However, this is a legacy strategy. In future STM32 families,  */
+      /*       COMP clock enable must be implemented by user                  */
+      /*       in "HAL_COMP_MspInit()".                                       */
+      /*       Therefore, for compatibility anticipation, it is recommended   */
+      /*       to implement __HAL_RCC_SYSCFG_CLK_ENABLE()                     */
+      /*       in "HAL_COMP_MspInit()".                                       */
+      __HAL_RCC_SYSCFG_CLK_ENABLE();
+      
+      /* Init the low level hardware */
+      HAL_COMP_MspInit(hcomp);
+    }
+    
+    /* Memorize voltage scaler state before initialization */
+    comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) == 0);
+    
+    /* Set COMP parameters */
+    tmp_csr = (hcomp->Init.InvertingInput    |
+               hcomp->Init.NonInvertingInput |
+               hcomp->Init.BlankingSrce      |
+               hcomp->Init.Hysteresis        |
+               hcomp->Init.OutputPol         |
+               hcomp->Init.Mode               );
+    
+    /* Set parameters in COMP register */
+    /* Note: Update all bits except read-only, lock and enable bits */ 
+#if defined (COMP_CSR_INMESEL)
+    MODIFY_REG(hcomp->Instance->CSR,
+               COMP_CSR_PWRMODE  | COMP_CSR_INMSEL   | COMP_CSR_INPSEL  |
+               COMP_CSR_WINMODE  | COMP_CSR_POLARITY | COMP_CSR_HYST    |
+               COMP_CSR_BLANKING | COMP_CSR_BRGEN    | COMP_CSR_SCALEN  | COMP_CSR_INMESEL,
+               tmp_csr
+              );
+#else
+    MODIFY_REG(hcomp->Instance->CSR,
+               COMP_CSR_PWRMODE  | COMP_CSR_INMSEL   | COMP_CSR_INPSEL  |
+               COMP_CSR_WINMODE  | COMP_CSR_POLARITY | COMP_CSR_HYST    |
+               COMP_CSR_BLANKING | COMP_CSR_BRGEN    | COMP_CSR_SCALEN,
+               tmp_csr
+              );
+#endif
+    
+    /* Set window mode */
+    /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
+    /*       instances. Therefore, this function can update another COMP      */
+    /*       instance that the one currently selected.                        */
+    if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
+    {
+      SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
+    }
+    else
+    {
+      CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
+    }
+    
+    /* Delay for COMP scaler bridge voltage stabilization */
+    /* Apply the delay if voltage scaler bridge is enabled for the first time */
+    if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0) &&
+        (comp_voltage_scaler_not_initialized != 0)               )
+    {
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially                  */
+      /*       CPU processing cycles.                                         */
+      wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2)));
+      while(wait_loop_index != 0)
+      {
+        wait_loop_index--;
+      }
+    }
+    
+    /* Get the EXTI line corresponding to the selected COMP instance */
+    exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+    
+    /* Manage EXTI settings */
+    if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET)
+    {
+      /* Configure EXTI rising edge */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET)
+      {
+        SET_BIT(EXTI->RTSR1, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->RTSR1, exti_line);
+      }
+      
+      /* Configure EXTI falling edge */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET)
+      {
+        SET_BIT(EXTI->FTSR1, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->FTSR1, exti_line);
+      }
+      
+      /* Clear COMP EXTI pending bit (if any) */
+      WRITE_REG(EXTI->PR1, exti_line);
+      
+      /* Configure EXTI event mode */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET)
+      {
+        SET_BIT(EXTI->EMR1, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->EMR1, exti_line);
+      }
+      
+      /* Configure EXTI interrupt mode */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET)
+      {
+        SET_BIT(EXTI->IMR1, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->IMR1, exti_line);
+      }
+    }
+    else
+    {
+      /* Disable EXTI event mode */
+      CLEAR_BIT(EXTI->EMR1, exti_line);
+      
+      /* Disable EXTI interrupt mode */
+      CLEAR_BIT(EXTI->IMR1, exti_line);
+    }
+    
+    /* Set HAL COMP handle state */
+    /* Note: Transition from state reset to state ready,                      */
+    /*       otherwise (coming from state ready or busy) no state update.     */
+    if (hcomp->State == HAL_COMP_STATE_RESET)
+    {
+      hcomp->State = HAL_COMP_STATE_READY;
+    }
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the COMP peripheral.
+  * @note   Deinitialization cannot be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    
+    /* Set COMP_CSR register to reset value */
+    WRITE_REG(hcomp->Instance->CSR, 0x00000000);
+    
+    /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
+    HAL_COMP_MspDeInit(hcomp);
+    
+    /* Set HAL COMP handle state */
+    hcomp->State = HAL_COMP_STATE_RESET;
+    
+    /* Release Lock */
+    __HAL_UNLOCK(hcomp);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Initialize the COMP MSP.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the COMP MSP.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions 
+ *  @brief   Start-Stop operation functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start a comparator instance.
+      (+) Stop a comparator instance.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the comparator.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+  __IO uint32_t wait_loop_index = 0;
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+    if(hcomp->State == HAL_COMP_STATE_READY)
+    {
+      /* Enable the selected comparator */
+      SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
+      
+      /* Set HAL COMP handle state */
+      hcomp->State = HAL_COMP_STATE_BUSY;
+      
+      /* Delay for COMP startup time */
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially                  */
+      /*       CPU processing cycles.                                         */
+      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2)));
+      while(wait_loop_index != 0)
+      {
+        wait_loop_index--;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Stop the comparator.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    
+    if((hcomp->State == HAL_COMP_STATE_BUSY)  ||
+       (hcomp->State == HAL_COMP_STATE_READY)   )
+    {
+      /* Disable the selected comparator */
+      CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
+
+      /* Set HAL COMP handle state */
+      hcomp->State = HAL_COMP_STATE_READY;
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Comparator IRQ handler.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
+{
+  /* Get the EXTI line corresponding to the selected COMP instance */
+  uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+  
+  /* Check COMP EXTI flag */
+  if(READ_BIT(EXTI->PR1, exti_line) != RESET)
+  {
+    /* Check whether comparator is in independent or window mode */
+    if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != RESET)
+    {
+      /* Clear COMP EXTI line pending bit of the pair of comparators          */
+      /* in window mode.                                                      */
+      /* Note: Pair of comparators in window mode can both trig IRQ when      */
+      /*       input voltage is changing from "out of window" area            */
+      /*       (low or high ) to the other "out of window" area (high or low).*/
+      /*       Both flags must be cleared to call comparator trigger          */
+      /*       callback is called once.                                       */
+      WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
+    }
+    else
+    {
+      /* Clear COMP EXTI line pending bit */
+      WRITE_REG(EXTI->PR1, exti_line);
+    }
+    
+    /* COMP trigger user callback */
+    HAL_COMP_TriggerCallback(hcomp);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   Management functions.
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the comparators. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected comparator configuration.
+  * @note   A system reset is required to unlock the comparator configuration.
+  * @note   Locking the comparator from reset state is possible
+  *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    
+    /* Set HAL COMP handle state */
+    hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK));
+  }
+  
+  if(status == HAL_OK)
+  {
+    /* Set the lock bit corresponding to selected comparator */
+    __HAL_COMP_LOCK(hcomp);
+  }
+  
+  return status; 
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  *         The output level depends on the selected polarity.
+  *         If the polarity is not inverted:
+  *           - Comparator output is low when the input plus is at a lower
+  *             voltage than the input minus
+  *           - Comparator output is high when the input plus is at a higher
+  *             voltage than the input minus
+  *         If the polarity is inverted:
+  *           - Comparator output is high when the input plus is at a lower
+  *             voltage than the input minus
+  *           - Comparator output is low when the input plus is at a higher
+  *             voltage than the input minus
+  * @param  hcomp  COMP handle
+  * @retval Returns the selected comparator output level: 
+  *         @arg @ref COMP_OUTPUT_LEVEL_LOW
+  *         @arg @ref COMP_OUTPUT_LEVEL_HIGH
+  *       
+  */
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+  
+  return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
+                    >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+  * @brief  Comparator callback.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_TriggerCallback should be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permit to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the COMP handle state.
+  * @param  hcomp  COMP handle
+  * @retval HAL state
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+{
+  /* Check the COMP handle allocation */
+  if(hcomp == NULL)
+  {
+    return HAL_COMP_STATE_RESET;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+  /* Return HAL COMP handle state */
+  return hcomp->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h
new file mode 100755
index 0000000..2787ba4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h
@@ -0,0 +1,790 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_comp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_COMP_H
+#define __STM32L4xx_HAL_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup COMP_Exported_Types COMP Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+typedef struct
+{
+
+  uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
+                                    (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
+                                    Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
+                                    This parameter can be a value of @ref COMP_WindowMode */
+
+  uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
+                                    Note: For the characteritics of comparator power modes
+                                          (propagation delay and power consumption), refer to device datasheet.
+                                    This parameter can be a value of @ref COMP_PowerMode */
+
+  uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).
+                                    This parameter can be a value of @ref COMP_InputPlus */
+
+  uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).
+                                    This parameter can be a value of @ref COMP_InputMinus */
+
+  uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
+                                    This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t OutputPol;          /*!< Set comparator output polarity.
+                                    This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t BlankingSrce;       /*!< Set comparator blanking source.
+                                    This parameter can be a value of @ref COMP_BlankingSrce */
+
+  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
+                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */
+
+}COMP_InitTypeDef;
+
+/**
+  * @brief  HAL COMP state machine: HAL COMP states definition
+  */
+#define COMP_STATE_BITFIELD_LOCK  ((uint32_t)0x10)
+typedef enum
+{
+  HAL_COMP_STATE_RESET             = 0x00,                                              /*!< COMP not yet initialized                             */
+  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
+  HAL_COMP_STATE_READY             = 0x01,                                              /*!< COMP initialized and ready for use                   */
+  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
+  HAL_COMP_STATE_BUSY              = 0x02,                                              /*!< COMP is running                                      */
+  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
+}HAL_COMP_StateTypeDef;
+
+/** 
+  * @brief  COMP Handle Structure definition
+  */
+typedef struct
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  HAL_LockTypeDef    Lock;            /*!< Locking object           */
+  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
+} COMP_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_WindowMode COMP Window Mode
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
+#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_PowerMode COMP power mode
+  * @{
+  */
+/* Note: For the characteritics of comparator power modes                     */
+/*       (propagation delay and power consumption),                           */
+/*       refer to device datasheet.                                           */
+#define COMP_POWERMODE_HIGHSPEED       ((uint32_t)0x00000000) /*!< High Speed */
+#define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_PWRMODE_0)   /*!< Medium Speed */
+#define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CSR_PWRMODE)     /*!< Ultra-low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
+  * @{
+  */
+#define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
+#define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL_0)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
+#if defined(COMP_CSR_INPSEL_1)
+#define COMP_INPUT_PLUS_IO3            (COMP_CSR_INPSEL_1)    /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputMinus COMP input minus (inverting input)
+  * @{
+  */
+#define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
+#define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
+#define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
+#define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
+#define COMP_INPUT_MINUS_DAC1_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define COMP_INPUT_MINUS_DAC1_CH2      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#endif
+#define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
+#define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
+#if defined(COMP_CSR_INMESEL_1)
+#define COMP_INPUT_MINUS_IO3           (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define COMP_INPUT_MINUS_IO4           (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
+#define COMP_INPUT_MINUS_IO5           (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Hysteresis COMP hysteresis
+  * @{
+  */
+#define COMP_HYSTERESIS_NONE           ((uint32_t)0x00000000) /*!< No hysteresis */
+#define COMP_HYSTERESIS_LOW            (COMP_CSR_HYST_0)      /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM         (COMP_CSR_HYST_1)      /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH           (COMP_CSR_HYST)        /*!< Hysteresis level high */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputPolarity COMP output Polarity
+  * @{
+  */
+#define COMP_OUTPUTPOL_NONINVERTED     ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
+#define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_BlankingSrce  COMP blanking source
+  * @{
+  */
+/* Note: Some blanking sources are not available depending on timer           */
+/*       availability or devices specificities                                */
+/*       (STM32L43xx, STM32L44xx, STM32L45xx, STM32L46xx)                     */
+#define COMP_BLANKINGSRC_NONE                    ((uint32_t)0x00000000) /*!< No blanking source */
+/* Blanking sources for COMP instance: COMP1 */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP1          (COMP_CSR_BLANKING_0)  /*!< Blanking source for COMP1: TIM1 OC5 selected as blanking source for comparator */
+#define COMP_BLANKINGSRC_TIM2_OC3_COMP1          (COMP_CSR_BLANKING_1)  /*!< Blanking source for COMP1: TIM2 OC3 selected as blanking source for comparator */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP1          (COMP_CSR_BLANKING_2)  /*!< Blanking source for COMP1: TIM3 OC3 selected as blanking source for comparator */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+
+/* Blanking sources for COMP instance: COMP2 */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define COMP_BLANKINGSRC_TIM3_OC4_COMP2          (COMP_CSR_BLANKING_0)  /*!< Blanking source for COMP2: TIM3 OC4 selected as blanking source for comparator */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP2          (COMP_CSR_BLANKING_1)  /*!< Blanking source for COMP2: TIM8 OC5 selected as blanking source for comparator */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */       
+#define COMP_BLANKINGSRC_TIM15_OC1_COMP2         (COMP_CSR_BLANKING_2)  /*!< Blanking source for COMP2: TIM15 OC1 selected as blanking source for comparator */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+  * @{
+  */
+/* Note: Comparator output level values are fixed to "0" and "1",             */
+/* corresponding COMP register bit is managed by HAL function to match        */
+/* with these values (independently of bit position in register).             */
+
+/* When output polarity is not inverted, comparator output is low when
+   the input plus is at a lower voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_LOW              ((uint32_t)0x00000000)
+/* When output polarity is not inverted, comparator output is high when
+   the input plus is at a higher voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_HIGH             ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
+  * @{
+  */
+#define COMP_TRIGGERMODE_NONE                 ((uint32_t)0x00000000)                                    /*!< Comparator output triggering no External Interrupt Line */
+#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
+#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
+#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
+#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+  * @{
+  */
+
+/** @defgroup COMP_Handle_Management  COMP Handle Management
+  * @{
+  */
+
+/** @brief  Reset COMP handle state.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+
+/**
+  * @brief  Enable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Disable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Lock the specified comparator configuration.
+  * @note   Using this macro induce HAL COMP handle state machine being no
+  *         more in line with COMP instance state.
+  *         To keep HAL COMP handle state machine updated, it is recommended
+  *         to use function "HAL_COMP_Lock')".
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
+
+/**
+  * @brief  Check whether the specified comparator is locked.
+  * @param  __HANDLE__  COMP handle
+  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
+  */
+#define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exti_Management  COMP external interrupt line management
+  * @{
+  */
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Generate a software interrupt on the COMP1 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Check whether the COMP1 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Clear the COMP1 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Generate a software interrupt on the COMP2 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Check whether the COMP2 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Clear the COMP2 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+  * @{
+  */
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_LINE_COMP1           (EXTI_IMR1_IM21)  /*!< EXTI line 21 connected to COMP1 output */
+#define COMP_EXTI_LINE_COMP2           (EXTI_IMR1_IM22)  /*!< EXTI line 22 connected to COMP2 output */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_IT                        ((uint32_t) 0x01)  /*!< EXTI line event with interruption */
+#define COMP_EXTI_EVENT                     ((uint32_t) 0x02)  /*!< EXTI line event only (without interruption) */
+#define COMP_EXTI_RISING                    ((uint32_t) 0x10)  /*!< EXTI line event on rising edge */
+#define COMP_EXTI_FALLING                   ((uint32_t) 0x20)  /*!< EXTI line event on falling edge */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+  * @{
+  */
+
+/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators 
+  * @{
+  */
+/**
+  * @brief  Get the specified EXTI line for a comparator instance.
+  * @param  __INSTANCE__  specifies the COMP instance.
+  * @retval value of @ref COMP_ExtiLine
+  */
+#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ?                 \
+                                             COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
+  * @{
+  */
+#define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
+                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
+
+#define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
+                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
+                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
+
+#if defined(COMP_CSR_INPSEL_1)
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
+#else
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
+#endif
+
+/* Note: On this STM32 family, comparator input minus parameters are          */
+/*       the same on all COMP instances.                                      */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#if defined(COMP_CSR_INMESEL_1) && defined(DAC_CHANNEL2_SUPPORT)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
+#elif defined(COMP_CSR_INMESEL_1)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
+#elif defined(DAC_CHANNEL2_SUPPORT)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
+#else
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
+#endif
+
+#define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
+                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
+
+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
+
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)  \
+   ((((__INSTANCE__) == COMP1) &&                                     \
+    (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)))        \
+    ||                                                                \
+    (((__INSTANCE__) == COMP2) &&                                     \
+     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+
+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
+
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)  \
+   ((((__INSTANCE__) == COMP1) &&                                     \
+    (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)))        \
+    ||                                                                \
+    (((__INSTANCE__) == COMP2) &&                                     \
+     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
+
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)  \
+   ((((__INSTANCE__) == COMP1) &&                                     \
+    (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)))        \
+    ||                                                                \
+    (((__INSTANCE__) == COMP2) &&                                     \
+     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+
+#define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+
+#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
+                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+/* Callback in interrupt mode */
+void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+  * @{
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h
new file mode 100755
index 0000000..d0a45d7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h
@@ -0,0 +1,397 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CONF_H
+#define __STM32L4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_FIREWALL_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SWPMI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)200U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE) 
+  #define HSI48_VALUE   ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+  #define LSI_VALUE  ((uint32_t)32000U)      /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                       /*!< Value of the Internal Low Speed oscillator in Hz
+                                              The real value may vary depending on the variations
+                                              in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)  /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/**
+  * @brief External clock source for SAI2 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
+  #define EXTERNAL_SAI2_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT               1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32l4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32l4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32l4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32l4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+  #include "stm32l4xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32l4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32l4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32l4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32l4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+  #include "stm32l4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+  #include "stm32l4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+  #include "stm32l4xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32l4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+  #include "stm32l4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+  #include "stm32l4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+  #include "stm32l4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32l4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+  #include "stm32l4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+  #include "stm32l4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+  #include "stm32l4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+  #include "stm32l4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+  #include "stm32l4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+  #include "stm32l4xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+  #include "stm32l4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32l4xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+  #include "stm32l4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+  #include "stm32l4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+  #include "stm32l4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+  #include "stm32l4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+  #include "stm32l4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32l4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+  #include "stm32l4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/* ALL MBED targets use same stm32_assert.h */
+#include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c
new file mode 100755
index 0000000..c39d7c6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c
@@ -0,0 +1,492 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and Configuration functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M4 exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest pre-emption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure SysTick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32l4xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+
+  The table below gives the allowed values of the pre-emption priority and subpriority according
+  to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+  
+    ==========================================================================================================================
+      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+    ==========================================================================================================================
+     NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
+                           |                                   |                             | 4 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------
+     NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
+                           |                                   |                             | 3 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+                           |                                   |                             | 2 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+                           |                                   |                             | 1 bit for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
+                           |                                   |                             | 0 bit for subpriority                       
+    ==========================================================================================================================
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      SysTick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Set the priority grouping field (pre-emption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup: The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+  *                                    1 bit  for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+  *                                    0 bit  for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Set the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority: the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiate a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): 
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Get the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @param   PriorityGroup: the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+  *                                      1 bit for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+  *                                      0 bit for subpriority
+  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Set Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Get Pending Interrupt (read the pending register in the NVIC
+  *         and return the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clear the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Get active interrupt (read the active register in NVIC and return the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configure the SysTick clock source.
+  * @param  CLKSource: specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  Handle SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Initialize and configure the Region and the memory to be protected.
+  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != RESET)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h
new file mode 100755
index 0000000..037c29e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h
@@ -0,0 +1,467 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CORTEX_H
+#define __STM32L4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE           ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE          ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0              ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1              ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2              ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disable the MPU.
+  * @retval None
+  */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Disable the MPU */
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged accessto the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
+  
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 
+  * @brief   Cortex control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/ 
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c
new file mode 100755
index 0000000..5e1d25a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c
@@ -0,0 +1,541 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_crc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   CRC HAL module driver.   
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the CRC peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+         (+) Initialize CRC calculator
+             (++) specify generating polynomial (IP default or non-default one)
+             (++) specify initialization value (IP default or non-default one)
+             (++) specify input data format
+             (++) specify input or output data inversion mode if any
+         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the 
+             input data buffer starting with the previously computed CRC as 
+             initialization value
+         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the 
+             input data buffer starting with the defined initialization value 
+             (default or non-default) to initiate CRC calculation
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRC CRC
+  * @brief CRC HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRC according to the specified parameters 
+          in the CRC_InitTypeDef and create the associated handle
+      (+) DeInitialize the CRC peripheral
+      (+) Initialize the CRC MSP (MCU Specific Package)
+      (+) DeInitialize the CRC MSP
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and create the associated handle.
+  * @param  hcrc: CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if(hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  if(hcrc->State == HAL_CRC_STATE_RESET)
+  {   
+    /* Allocate lock resource and initialize it */
+    hcrc->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_CRC_MspInit(hcrc);
+  }
+  
+  hcrc->State = HAL_CRC_STATE_BUSY; 
+  
+  /* check whether or not non-default generating polynomial has been 
+   * picked up by user */
+  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); 
+  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+  {
+    /* initialize IP with default generating polynomial */
+    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);  
+    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+  }
+  else
+  {
+    /* initialize CRC IP with generating polynomial defined by user */
+    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+  
+  /* check whether or not non-default CRC initial value has been 
+   * picked up by user */
+  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+  {
+    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);  
+  }
+  else
+  {
+    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+  }
+  
+
+  /* set input data inversion mode */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); 
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 
+  
+  /* set output data inversion mode */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); 
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);  
+  
+  /* makes sure the input data format (bytes, halfwords or words stream)
+   * is properly specified by user */
+  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the CRC peripheral. 
+  * @param  hcrc: CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{ 
+  /* Check the CRC handle allocation */
+  if(hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+  
+  /* Check the CRC peripheral state */
+  if(hcrc->State == HAL_CRC_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+  
+  /* Reset CRC calculation unit */
+  __HAL_CRC_DR_RESET(hcrc);
+  
+  /* Reset IDR register content */
+  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
+
+  /* DeInit the low level hardware */
+  HAL_CRC_MspDeInit(hcrc);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRC MSP.
+  * @param  hcrc: CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the CRC MSP.
+  * @param  hcrc: CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief    management functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          using the combination of the previous CRC value and the new one
+          
+       [..]  or
+          
+      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          independently of the previous CRC value.
+
+@endverbatim
+  * @{
+  */
+
+/**                  
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with the previously computed CRC as initialization value.
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.  
+  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the  
+  *        handle field hcrc->InputDataFormat.              
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0; /* CRC input data buffer index */
+  uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
+  
+  /* Process locked */
+  __HAL_LOCK(hcrc); 
+    
+  /* Change CRC peripheral state */  
+  hcrc->State = HAL_CRC_STATE_BUSY;
+  
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:  
+      /* Enter Data to the CRC calculator */
+      for(index = 0; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_BYTES: 
+      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_HALFWORDS: 
+      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+      break;
+      
+    default:
+      break;      
+  }
+  
+  /* Change CRC peripheral state */    
+  hcrc->State = HAL_CRC_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+  
+  /* Return the CRC computed value */ 
+  return temp;
+}
+
+
+/**                  
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with hcrc->Instance->INIT as initialization value.
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.  
+  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the  
+  *        handle field hcrc->InputDataFormat. 
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */  
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0; /* CRC input data buffer index */
+  uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
+    
+  /* Process locked */
+  __HAL_LOCK(hcrc); 
+  
+  /* Change CRC peripheral state */  
+  hcrc->State = HAL_CRC_STATE_BUSY;
+  
+  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is 
+  *  written in hcrc->Instance->DR) */
+  __HAL_CRC_DR_RESET(hcrc);
+  
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:  
+      /* Enter 32-bit input data to the CRC calculator */
+      for(index = 0; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_BYTES: 
+      /* Specific 8-bit input data handling  */
+      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_HALFWORDS: 
+      /* Specific 16-bit input data handling  */
+      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+      break;
+      
+    default:
+      break;    
+  }
+
+  /* Change CRC peripheral state */    
+  hcrc->State = HAL_CRC_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+  
+  /* Return the CRC computed value */ 
+  return temp;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CRC handle state.
+  * @param  hcrc: CRC handle
+  * @retval HAL state
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+  /* Return CRC handle state */
+  return hcrc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+
+/**             
+  * @brief  Enter 8-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.  
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer
+  * @param  BufferLength: input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t i = 0; /* input data buffer index */
+  
+   /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+    * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+    * handling by the IP */
+   for(i = 0; i < (BufferLength/4); i++)
+   {
+      hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3];      
+   }
+   /* last bytes specific handling */
+   if ((BufferLength%4) != 0)
+   {
+     if  (BufferLength%4 == 1)
+     {
+       *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
+     }
+     if  (BufferLength%4 == 2)
+     {
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+     }
+     if  (BufferLength%4 == 3)
+     {
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+       *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];       
+     }
+   }
+  
+  /* Return the CRC computed value */ 
+  return hcrc->Instance->DR;
+}
+
+
+
+/**             
+  * @brief  Enter 16-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.  
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer
+  * @param  BufferLength: input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */  
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t i = 0;  /* input data buffer index */
+  
+  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure 
+   * a correct type handling by the IP */
+  for(i = 0; i < (BufferLength/2); i++)
+  {
+    hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1];     
+  }
+  if ((BufferLength%2) != 0)
+  {
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; 
+  }
+   
+  /* Return the CRC computed value */ 
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h
new file mode 100755
index 0000000..6bbae9f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h
@@ -0,0 +1,368 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_crc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRC_H
+#define __STM32L4xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup CRC_Exported_Types CRC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  CRC HAL State Structure definition  
+  */ 
+typedef enum
+{                                            
+  HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
+}HAL_CRC_StateTypeDef;
+
+
+
+/** 
+  * @brief CRC Init Structure definition  
+  */ 
+typedef struct
+{
+  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.  
+                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default 
+                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. 
+                                            In that case, there is no need to set GeneratingPolynomial field.
+                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+
+  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. 
+                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.   
+                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
+
+  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation, 
+                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */                                                
+
+  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+                                           Value can be either one of
+                                           @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
+                                              
+  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse 
+                                           is set to DEFAULT_INIT_VALUE_ENABLE.   */                                                
+  
+  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. 
+                                           Can be either one of the following values 
+                                           @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
+                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */  
+                                              
+  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+                                            Can be either 
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion, 
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */                                           
+}CRC_InitTypeDef;
+
+
+
+/** 
+  * @brief  CRC Handle Structure definition  
+  */ 
+typedef struct
+{
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */ 
+  
+  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
+  
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+    
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+  
+  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. 
+                                            Can be either 
+                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
+                                                                                                                                    
+                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+                                           must occur if InputBufferFormat is not one of the three values listed above  */ 
+}CRC_HandleTypeDef;
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
+  * @{
+  */
+#define DEFAULT_CRC32_POLY      0x04C11DB7  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define DEFAULT_CRC_INITVALUE   0xFFFFFFFF  /*!< Initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
+  * @{
+  */
+#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00)  /*!< Enable default generating polynomial 0x04C11DB7  */
+#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01)  /*!< Disable default generating polynomial 0x04C11DB7 */
+/**
+  * @}
+  */
+ 
+/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
+  * @{
+  */                                      
+#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00) /*!< Enable initial CRC default value  */
+#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01) /*!< Disable initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
+  * @{
+  */
+#define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000)        /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial  */
+#define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)   /*!< Resort to a 7-bit long generating polynomial  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+  * @{
+  */
+#define HAL_CRC_LENGTH_32B     32          /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B     16          /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B       8          /*!< 8-bit long CRC  */
+#define HAL_CRC_LENGTH_7B       7          /*!< 7-bit long CRC  */
+/**
+  * @}
+  */  
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+  * @{
+  */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set 
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for 
+ * the CRC APIs to provide a correct result */ 
+#define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000)  /*!< Undefined input data format    */
+#define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001)  /*!< Input data in byte format      */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002)  /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003)  /*!< Input data in word format      */                                               
+/**                                               
+  * @}
+  */
+  
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRC handle state.
+  * @param  __HANDLE__: CRC handle.
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+  * @brief  Set CRC INIT non-default value
+  * @param  __HANDLE__: CRC handle
+  * @param  __INIT__: 32-bit initial value  
+  * @retval None
+  */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))    
+
+/**
+  * @brief Store a 8-bit data in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @param __VALUE__: 8-bit value to be stored in the ID register
+  * @retval None
+  */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+  * @brief Return the 8-bit data stored in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @retval 8-bit value of the ID register 
+  */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  CRC_Private_Macros   CRC Private Macros
+  * @{
+  */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+                                        
+
+#define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))   
+                                       
+#define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
+                                       ((LENGTH) == CRC_POLYLENGTH_7B))  
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))                                                     
+
+/**
+  * @}
+  */
+
+/* Include CRC HAL Extended module */
+#include "stm32l4xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */  
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c
new file mode 100755
index 0000000..e1ce5df
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c
@@ -0,0 +1,237 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_crc_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended CRC HAL module driver.
+  *          This file provides firmware functions to manage the extended 
+  *          functionalities of the CRC peripheral.  
+  *         
+  @verbatim
+================================================================================
+            ##### How to use this driver #####
+================================================================================
+    [..]
+         (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+         (+) Configure Input or Output data inversion
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRCEx CRCEx
+  * @brief CRC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+  * @brief    Extended Initialization and Configuration functions.
+  *
+@verbatim    
+ ===============================================================================
+            ##### Extended configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the generating polynomial
+      (+) Configure the input data inversion
+      (+) Configure the output data inversion
+ 
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initialize the CRC polynomial if different from default one.
+  * @param  hcrc: CRC handle
+  * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long).
+  *         This parameter is written in normal representation, e.g.
+  *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 
+  *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021     
+  * @param  PolyLength: CRC polynomial length. 
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
+  *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
+  *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
+  *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)                
+  * @retval HAL status
+  */                                   
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+  uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+  /* Check the parameters */
+  assert_param(IS_CRC_POL_LENGTH(PolyLength));
+  
+  /* check polynomial definition vs polynomial size:
+   * polynomial length must be aligned with polynomial
+   * definition. HAL_ERROR is reported if Pol degree is 
+   * larger than that indicated by PolyLength.
+   * Look for MSB position: msb will contain the degree of
+   *  the second to the largest polynomial member. E.g., for
+   *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+  while (((Pol & (1U << msb)) == 0) && (msb-- > 0)) {}
+
+  switch (PolyLength)
+  {
+    case CRC_POLYLENGTH_7B:
+      if (msb >= HAL_CRC_LENGTH_7B) 
+      {
+        return  HAL_ERROR;
+      }
+      break;
+    case CRC_POLYLENGTH_8B:
+      if (msb >= HAL_CRC_LENGTH_8B)
+      {
+        return  HAL_ERROR;
+      }      
+      break;
+    case CRC_POLYLENGTH_16B:
+      if (msb >= HAL_CRC_LENGTH_16B)
+      {
+        return  HAL_ERROR;
+      }      
+      break;
+    case CRC_POLYLENGTH_32B:
+      /* no polynomial definition vs. polynomial length issue possible */
+      break; 
+    default:
+      break;                        
+  }
+
+  /* set generating polynomial */
+  WRITE_REG(hcrc->Instance->POL, Pol);
+  
+  /* set generating polynomial size */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Reverse Input data mode.
+  * @param  hcrc: CRC handle
+  * @param  InputReverseMode: Input Data inversion mode.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
+  *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
+  *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
+  *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal              
+  * @retval HAL status
+  */                                   
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{  
+  /* Check the parameters */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set input data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);    
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Reverse Output data mode.
+  * @param  hcrc: CRC handle
+  * @param  OutputReverseMode: Output Data inversion mode.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
+  *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)            
+  * @retval HAL status
+  */                                   
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+  /* Check the parameters */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set output data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); 
+      
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h
new file mode 100755
index 0000000..7f6907d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h
@@ -0,0 +1,173 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_crc_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRC_EX_H
+#define __STM32L4xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+  * @{
+  */
+#define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000)      /*!< No input data inversion            */
+#define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion     */
+#define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)   /*!< Word-wise input data inversion     */
+/**
+  * @}
+  */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+  * @{
+  */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000)     /*!< No output data inversion       */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
+/**
+  * @}
+  */
+
+/**                                               
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros
+  * @{
+  */
+    
+/**
+  * @brief  Set CRC output reversal
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)   
+
+/**
+  * @brief  Unset CRC output reversal
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))   
+
+/**
+  * @brief  Set CRC non-default polynomial
+  * @param  __HANDLE__: CRC handle
+  * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial  
+  * @retval None
+  */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  CRCEx_Private_Macros   CRCEx Private Macros
+  * @{
+  */
+  
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+                                                   
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))                                                   
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions 
+  * @{
+  */
+  
+/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+  * @{
+  */
+  
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c
new file mode 100755
index 0000000..833873c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c
@@ -0,0 +1,1457 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cryp.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   CRYP HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Cryptography (CRYP) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Processing functions using polling mode
+  *           + Processing functions using interrupt mode
+  *           + Processing functions using DMA mode
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The CRYP HAL driver can be used as follows:
+    
+      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+         (++) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE()
+         (++) In case of using interrupts (e.g. HAL_CRYP_AES_IT())
+             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+             (+++) Enable the AES IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In AES IRQ handler, call HAL_CRYP_IRQHandler()
+         (++) In case of using DMA to control data transfer (e.g. HAL_CRYPEx_AES_DMA())
+             (+++) Enable the DMA2 interface clock using 
+                 __HAL_RCC_DMA2_CLK_ENABLE()
+             (+++) Configure and enable two DMA channels one for managing data transfer from
+                 memory to peripheral (input channel) and another channel for managing data
+                 transfer from peripheral to memory (output channel)
+             (+++) Associate the initialized DMA handle to the CRYP DMA handle
+                 using __HAL_LINKDMA()
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA channels. The output channel should have higher
+                 priority than the input channel.
+                 Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+                                                       
+      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures:
+         (++) The data type: 1-bit, 8-bit, 16-bit and 32-bit
+         (++) The AES operating mode (encryption, key derivation and/or decryption)
+         (++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC when applicable, CCM when applicable)         
+         (++) The encryption/decryption key if so required
+         (++) The initialization vector or nonce if applicable (not used in ECB mode).
+    
+      (#)Three processing (encryption/decryption) functions are available:
+         (++) Polling mode: encryption and decryption APIs are blocking functions
+              i.e. they process the data and wait till the processing is finished
+         (++) Interrupt mode: encryption and decryption APIs are not blocking functions
+              i.e. they process the data under interrupt
+         (++) DMA mode: encryption and decryption APIs are not blocking functions
+              i.e. the data transfer is ensured by DMA
+         
+       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRYP CRYP
+  * @brief CRYP HAL module driver.
+  * @{
+  */
+
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions --------------------------------------------------------*/
+
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+  * @{
+  */
+
+static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and deinitialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRYP according to the specified parameters 
+          in the CRYP_InitTypeDef and creates the associated handle
+      (+) DeInitialize the CRYP peripheral
+      (+) Initialize the CRYP MSP (MCU Specific Package)
+      (+) De-Initialize the CRYP MSP
+      
+    [..]
+    (@) Specific care must be taken to format the key and the Initialization Vector IV!
+    
+   [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where 
+        b127 is the MSB and b0 the LSB, the key must be stored in MCU memory 
+        (+) as a sequence of words where the MSB word comes first (occupies the
+          lowest memory address) 
+        (+) where each word is byte-swapped:
+         (++)   address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120
+         (++)   address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88
+         (++)   address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56
+         (++)   address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24                 
+    [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
+        The 4 32-bit words that make the key must be stored as follows in MCU memory:  
+         (+)    address n+0 : 0x B12 B13 B14 B15
+         (+)    address n+4 : 0x B8 B9 B10 B11
+         (+)    address n+8 : 0x B4 B5 B6 B7
+         (+)    address n+C : 0x B0 B1 B2 B3  
+    [..]  which leads to the expected setting  
+      (+)       AES_KEYR3 = 0x B15 B14 B13 B12   
+      (+)       AES_KEYR2 = 0x B11 B10 B9 B8      
+      (+)       AES_KEYR1 = 0x B7 B6 B5 B4        
+      (+)       AES_KEYR0 = 0x B3 B2 B1 B0      
+   
+   [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. 
+         The 8 32-bit words that make the key must be stored as follows in MCU memory:
+         (+)    address n+00 : 0x B28 B29 B30 B31
+         (+)    address n+04 : 0x B24 B25 B26 B27
+         (+)    address n+08 : 0x B20 B21 B22 B23
+         (+)    address n+0C : 0x B16 B17 B18 B19            
+         (+)    address n+10 : 0x B12 B13 B14 B15
+         (+)    address n+14 : 0x B8 B9 B10 B11
+         (+)    address n+18 : 0x B4 B5 B6 B7
+         (+)    address n+1C : 0x B0 B1 B2 B3 
+    [..]  which leads to the expected setting 
+      (+)       AES_KEYR7 = 0x B31 B30 B29 B28   
+      (+)       AES_KEYR6 = 0x B27 B26 B25 B24      
+      (+)       AES_KEYR5 = 0x B23 B22 B21 B20        
+      (+)       AES_KEYR4 = 0x B19 B18 B17 B16       
+      (+)       AES_KEYR3 = 0x B15 B14 B13 B12   
+      (+)       AES_KEYR2 = 0x B11 B10 B9 B8      
+      (+)       AES_KEYR1 = 0x B7 B6 B5 B4        
+      (+)       AES_KEYR0 = 0x B3 B2 B1 B0           
+   
+   [..] Initialization Vector IV (4 32-bit words) format must follow the same as 
+        that of a 128-bit long key.   
+  
+  [..]                 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the CRYP according to the specified
+  *         parameters in the CRYP_InitTypeDef and initialize the associated handle.                   
+  * @note Specific care must be taken to format the key and the Initialization Vector IV 
+  *       stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations 
+  *       hereabove.              
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{   
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the instance */
+  assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
+  
+  /* Check the parameters */
+  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+  assert_param(IS_CRYP_ALGOMODE(hcryp->Init.OperatingMode));
+  /* ChainingMode parameter is irrelevant when mode is set to Key derivation */
+  if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+  {
+    assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode));
+  }
+  assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag));
+  
+  /*========================================================*/
+  /* Check the proper operating/chaining modes combinations */
+  /*========================================================*/  
+  /* Check the proper chaining when the operating mode is key derivation and decryption */
+#if defined(AES_CR_NPBLB)
+  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
+         ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR)           \
+       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)      \
+       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)))
+#else  
+  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
+         ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR)           \
+       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)      \
+       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))
+#endif               
+  {
+    return HAL_ERROR;
+  }  
+  /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */  
+#if defined(AES_CR_NPBLB)
+  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) 
+   && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))
+#else  
+  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) 
+   && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
+#endif           
+  {
+    return HAL_ERROR;
+  }
+  
+  
+  /*================*/
+  /* Initialization */
+  /*================*/  
+  /* Initialization start */
+  if(hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcryp->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_CRYP_MspInit(hcryp);
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;  
+  
+  /* Disable the Peripheral */
+  __HAL_CRYP_DISABLE(hcryp);
+  
+  /*=============================================================*/
+  /* AES initialization common to all operating modes            */ 
+  /*=============================================================*/
+  /* Set the Key size selection */
+  MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize);
+  
+  /* Set the default CRYP phase when this parameter is not used.
+     Phase is updated below in case of GCM/GMAC(/CMAC)(/CCM) setting. */
+  hcryp->Phase = HAL_CRYP_PHASE_NOT_USED;
+  
+  
+
+  /*=============================================================*/
+  /* Carry on the initialization based on the AES operating mode */ 
+  /*=============================================================*/
+  /* Key derivation */ 
+  if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+  {
+    MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION);
+    
+    /* Configure the Key registers */
+    if (CRYP_SetKey(hcryp) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  /* Encryption / Decryption (with or without key derivation) / authentication */
+  {  
+#if !defined(AES_CR_NPBLB)    
+    /* Set data type, operating and chaining modes.
+       In case of GCM or GMAC, data type is forced to 0b00 */
+    if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+    {
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);    
+    }
+    else
+#endif    
+    {
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
+    }
+
+    
+   /* Specify the encryption/decryption phase in case of Galois counter mode (GCM), 
+      Galois message authentication code (GMAC), cipher message authentication code (CMAC) when applicable
+      or Counter with Cipher Mode (CCM) when applicable */
+#if defined(AES_CR_NPBLB)      
+   if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+    || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))
+#else
+   if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+    || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
+#endif    
+    {
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase);
+      hcryp->Phase = HAL_CRYP_PHASE_START;
+    }
+
+    
+    /* Configure the Key registers if no need to bypass this step */
+    if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE)
+    {
+      if (CRYP_SetKey(hcryp) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }      
+    }
+    
+    /* If applicable, configure the Initialization Vector */
+    if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB)
+    {
+      if (CRYP_SetInitVector(hcryp) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  
+#if defined(AES_CR_NPBLB)   
+  /* Clear NPBLB field */
+  CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
+#endif  
+
+  /* Reset CrypInCount and CrypOutCount */
+  hcryp->CrypInCount = 0;
+  hcryp->CrypOutCount = 0;
+  
+  /* Reset ErrorCode field */
+  hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+  
+  /* Reset Mode suspension request */
+  hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Enable the Peripheral */
+  __HAL_CRYP_ENABLE(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the CRYP peripheral. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set the default CRYP phase */
+  hcryp->Phase = HAL_CRYP_PHASE_READY;
+  
+  /* Reset CrypInCount and CrypOutCount */
+  hcryp->CrypInCount = 0;
+  hcryp->CrypOutCount = 0;
+  
+  /* Disable the CRYP Peripheral Clock */
+  __HAL_CRYP_DISABLE(hcryp);
+  
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_CRYP_MspDeInit(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_CRYP_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_CRYP_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions 
+ *  @brief   Processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### AES processing functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Encrypt plaintext using AES algorithm in different chaining modes
+      (+) Decrypt cyphertext using AES algorithm in different chaining modes
+    [..]  Three processing functions are available:
+      (+) Polling mode
+      (+) Interrupt mode
+      (+) DMA mode
+
+@endverbatim
+  * @{
+  */
+  
+  
+/**
+  * @brief  Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value 
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).      
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
+}
+ 
+
+/**
+  * @brief  Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{ 
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
+}
+
+
+/**
+  * @brief  Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value 
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES ECB decryption mode with key derivation, 
+  *         the decyphered data are available in pPlainData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Timeout: Specify Timeout value 
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES ECB decryption mode with key derivation, 
+  *         the decyphered data are available in pPlainData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Timeout: Specify Timeout value 
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES CTR decryption mode, 
+  *         the decyphered data are available in pPlainData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Timeout: Specify Timeout value
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
+}
+
+/**
+  * @brief  Encrypt pPlainData in AES ECB encryption mode using Interrupt,
+  *         the cypher data are available in pCypherData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+  * @brief  Encrypt pPlainData in AES CBC encryption mode using Interrupt,
+  *         the cypher data are available in pCypherData.  
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
+}
+  
+
+/**
+  * @brief  Encrypt pPlainData in AES CTR encryption mode using Interrupt,
+  *         the cypher data are available in pCypherData.  
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES ECB decryption mode using Interrupt,
+  *         the decyphered data are available in pPlainData.   
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer.
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).      
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES CBC decryption mode using Interrupt,
+  *         the decyphered data are available in pPlainData.  
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES CTR decryption mode using Interrupt,
+  *         the decyphered data are available in pPlainData. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+  * @brief  Encrypt pPlainData in AES ECB encryption mode using DMA,
+  *         the cypher data are available in pCypherData.   
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+}
+  
+ 
+
+/**
+  * @brief  Encrypt pPlainData in AES CBC encryption mode using DMA,
+  *         the cypher data are available in pCypherData.  
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.       
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+  * @brief  Encrypt pPlainData in AES CTR encryption mode using DMA,
+  *         the cypher data are available in pCypherData. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer.
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.      
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES ECB decryption mode using DMA,
+  *         the decyphered data are available in pPlainData.   
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). 
+  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES CBC decryption mode using DMA,
+  *         the decyphered data are available in pPlainData.  
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.      
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+  * @brief  Decrypt pCypherData in AES CTR decryption mode using DMA,
+  *         the decyphered data are available in pPlainData. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
+  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). 
+  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  /* Re-initialize AES IP with proper parameters */
+  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
+  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+  if (HAL_CRYP_Init(hcryp) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group3 Callback functions 
+ *  @brief   Callback functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Callback functions  #####
+  ==============================================================================  
+    [..]  This section provides Interruption and DMA callback functions:
+      (+) DMA Input data transfer complete
+      (+) DMA Output data transfer complete
+      (+) DMA or Interrupt error
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  CRYP error callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_CRYP_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input DMA transfer complete callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_CRYP_InCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output DMA transfer complete callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_CRYP_OutCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler 
+ *  @brief   AES IRQ handler.
+ *
+@verbatim   
+  ==============================================================================
+                ##### AES IRQ handler management #####
+  ==============================================================================  
+[..]  This section provides AES IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle AES interrupt request.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check if error occurred */
+  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
+  {
+    /* If Write Error occurred */
+    if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
+    {
+      hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR;
+      hcryp->State = HAL_CRYP_STATE_ERROR;
+    }
+    /* If Read Error occurred */
+    if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
+    {
+      hcryp->ErrorCode |= HAL_CRYP_READ_ERROR;
+      hcryp->State = HAL_CRYP_STATE_ERROR;
+    }
+    
+    /* If an error has been reported */
+    if (hcryp->State == HAL_CRYP_STATE_ERROR)
+    {  
+      /* Disable Error and Computation Complete Interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+      /* Clear all Interrupt flags */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);  
+    
+      HAL_CRYP_ErrorCallback(hcryp);
+  
+      return; 
+    }
+
+  }
+  
+  /* Check if computation complete interrupt is enabled 
+     and if the computation complete flag is raised */
+  if((__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET))
+  { 
+#if defined(AES_CR_NPBLB)
+    if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+     || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))
+#else     
+    if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+     || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
+#endif     
+    {
+     /* To ensure proper suspension requests management, CCF flag 
+        is reset in CRYP_AES_Auth_IT() according to the current 
+        phase under handling */
+      CRYP_AES_Auth_IT(hcryp);
+    }
+    else
+    {
+      /* Clear Computation Complete Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      CRYP_AES_IT(hcryp);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions 
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CRYP handle state.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL state
+  */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+  /* Return CRYP handle state */
+  return hcryp->State;
+}
+
+/**
+  * @brief  Return the CRYP peripheral error.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @note   The returned error is a bit-map combination of possible errors          
+  * @retval Error bit-map
+  */
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
+{
+  return hcryp->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Write the Key in KeyRx registers. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+static HAL_StatusTypeDef  CRYP_SetKey(CRYP_HandleTypeDef *hcryp)
+{  
+  uint32_t keyaddr = 0x0;
+  
+  if ((uint32_t)(hcryp->Init.pKey == NULL))
+  {
+    return HAL_ERROR;
+  }
+  
+  
+  keyaddr = (uint32_t)(hcryp->Init.pKey);
+  
+  if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+  {
+    hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;      
+  }  
+  
+  hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write the InitVector/InitCounter in IVRx registers. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t ivaddr = 0x0;
+  
+#if !defined(AES_CR_NPBLB)
+  if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+  {
+    hcryp->Instance->IVR3 = 0;
+    hcryp->Instance->IVR2 = 0;
+    hcryp->Instance->IVR1 = 0;        
+    hcryp->Instance->IVR0 = 0;
+  }
+  else
+#endif
+  {
+    if (hcryp->Init.pInitVect == NULL)
+    {
+      return HAL_ERROR;
+    } 
+  
+    ivaddr = (uint32_t)(hcryp->Init.pInitVect);
+  
+    hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
+  }
+  return HAL_OK;
+}
+
+
+
+/** 
+  * @brief  Handle CRYP block input/output data handling under interruption.
+  * @note   The function is called under interruption only, once
+  *         interruptions have been enabled by HAL_CRYPEx_AES_IT().
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t inputaddr = 0;
+  uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; 
+
+  if(hcryp->State == HAL_CRYP_STATE_BUSY)
+  {
+    if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+    {      
+      /* Read the last available output block from the Data Output Register */
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+      outputaddr+=4;
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+      outputaddr+=4;
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+      outputaddr+=4;
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+      hcryp->pCrypOutBuffPtr += 16;
+      hcryp->CrypOutCount -= 16;
+    
+    }
+    else
+    {
+      /* Read the derived key from the Key registers */
+      if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+      {   
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
+        outputaddr+=4;
+      }
+      
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
+    }
+    
+    /* In case of ciphering or deciphering, check if all output text has been retrieved;
+       In case of key derivation, stop right there */
+    if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION))
+    {
+      /* Disable Computation Complete Flag and Errors Interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      
+     /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      
+      /* Call computation complete callback */
+      HAL_CRYPEx_ComputationCpltCallback(hcryp);
+      
+      return HAL_OK;
+    }
+    /* If suspension flag has been raised, suspend processing */
+    else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+    {
+      /* reset ModeSuspend */
+      hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+      
+      /* Disable Computation Complete Flag and Errors Interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+      
+     /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      
+      return HAL_OK;
+    }
+    else /* Process the rest of input data */
+    {
+      /* Get the Intput data address */
+      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+      
+      /* Increment/decrement instance pointer/counter */
+      hcryp->pCrypInBuffPtr += 16;
+      hcryp->CrypInCount -= 16;
+      
+      /* Write the next input block in the Data Input register */
+      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      inputaddr+=4;
+      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      inputaddr+=4;
+      hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+      inputaddr+=4;
+      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      
+      return HAL_OK;      
+    }
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+        
+
+
+
+/**
+  * @}
+  */
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */  
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h
new file mode 100755
index 0000000..315f76c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h
@@ -0,0 +1,698 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cryp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRYP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRYP_H
+#define __STM32L4xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  CRYP Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t DataType;       /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                             This parameter can be a value of @ref CRYP_Data_Type */
+
+  uint32_t KeySize;        /*!< 128 or 256-bit key length. 
+                             This parameter can be a value of @ref CRYP_Key_Size */
+                             
+  uint32_t OperatingMode;  /*!< AES operating mode. 
+                             This parameter can be a value of @ref CRYP_AES_OperatingMode */
+                             
+  uint32_t ChainingMode;   /*!< AES chaining mode. 
+                             This parameter can be a value of @ref CRYP_AES_ChainingMode */
+                             
+  uint32_t KeyWriteFlag;   /*!< Allows to bypass or not key write-up before decryption. 
+                             This parameter can be a value of @ref CRYP_Key_Write */                             
+                             
+  uint32_t GCMCMACPhase;   /*!< Indicates the processing phase of the Galois Counter Mode (GCM), 
+                             Galois Message Authentication Code (GMAC), Cipher Message 
+                             Authentication Code (CMAC) (when applicable) or Counter with Cipher 
+                             Mode (CCM) (when applicable).
+                             This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */                                                                                          
+
+  uint8_t* pKey;           /*!< Encryption/Decryption Key */
+
+  uint8_t* pInitVect;      /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC (when applicable) 
+                                and CCM (when applicable) modes */
+
+  uint8_t* Header;         /*!< Header used in GCM/GMAC, CMAC (when applicable) and CCM (when applicable) modes */
+
+  uint64_t HeaderSize;     /*!< Header size in bytes */
+                                                     
+}CRYP_InitTypeDef;
+
+/** 
+  * @brief HAL CRYP State structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
+  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
+  HAL_CRYP_STATE_ERROR             = 0x04,  /*!< CRYP error state                      */
+  HAL_CRYP_STATE_SUSPENDED         = 0x05   /*!< CRYP suspended                        */
+}HAL_CRYP_STATETypeDef;
+
+/** 
+  * @brief HAL CRYP phase structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization.             */
+  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase                   */
+  HAL_CRYP_PHASE_START             = 0x03,    /*!< CRYP peripheral has been initialized but 
+                                                 GCM/GMAC(/CMAC)(/CCM) initialization phase has not started */
+  HAL_CRYP_PHASE_INIT_OVER         = 0x04,    /*!< GCM/GMAC(/CMAC)(/CCM) init phase has been carried out    */ 
+  HAL_CRYP_PHASE_HEADER_OVER       = 0x05,    /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been carried out  */ 
+  HAL_CRYP_PHASE_PAYLOAD_OVER      = 0x06,    /*!< GCM(/CCM) payload phase has been carried out             */ 
+  HAL_CRYP_PHASE_FINAL_OVER        = 0x07,    /*!< GCM/GMAC(/CMAC)(/CCM) final phase has been carried out   */
+  HAL_CRYP_PHASE_HEADER_SUSPENDED  = 0x08,    /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been suspended    */
+  HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09,    /*!< GCM(/CCM) payload phase has been suspended               */  
+  HAL_CRYP_PHASE_NOT_USED          = 0x0a     /*!< Phase is irrelevant to the current chaining mode         */                                                                                                                                                                                                                                                                   
+}HAL_PhaseTypeDef;
+
+/** 
+  * @brief HAL CRYP mode suspend definitions
+  */
+typedef enum
+{
+  HAL_CRYP_SUSPEND_NONE            = 0x00,    /*!< CRYP peripheral suspension not requested */
+  HAL_CRYP_SUSPEND                 = 0x01     /*!< CRYP peripheral suspension requested     */                                                                                                                                                                                                                                                                  
+}HAL_SuspendTypeDef;
+
+
+/** 
+  * @brief  HAL CRYP Error Codes definition  
+  */ 
+#define HAL_CRYP_ERROR_NONE      ((uint32_t)0x00000000)  /*!< No error        */
+#define HAL_CRYP_WRITE_ERROR     ((uint32_t)0x00000001)  /*!< Write error     */
+#define HAL_CRYP_READ_ERROR      ((uint32_t)0x00000002)  /*!< Read error      */
+#define HAL_CRYP_DMA_ERROR       ((uint32_t)0x00000004)  /*!< DMA error       */  
+#define HAL_CRYP_BUSY_ERROR      ((uint32_t)0x00000008)  /*!< Busy flag error */  
+
+/** 
+  * @brief  CRYP handle Structure definition
+  */ 
+typedef struct
+{
+      AES_TypeDef              *Instance;        /*!< Register base address        */
+
+      CRYP_InitTypeDef         Init;             /*!< CRYP initialization parameters */
+
+      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
+
+      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
+
+      uint32_t                 CrypInCount;      /*!< Input data size in bytes or, after suspension, the remaining 
+                                                       number of bytes to process */
+
+      uint32_t                 CrypOutCount;     /*!< Output data size in bytes */
+
+      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC (when applicable)
+                                                      or CCM (when applicable) modes.
+                                                      Indicates the last phase carried out to ease
+                                                      phase transitions  */
+
+      DMA_HandleTypeDef        *hdmain;          /*!< CRYP peripheral Input DMA handle parameters */
+
+      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP peripheral Output DMA handle parameters */
+
+      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
+
+   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
+   
+    __IO uint32_t              ErrorCode;        /*!< CRYP peripheral error code */
+     
+     HAL_SuspendTypeDef        SuspendRequest;   /*!< CRYP peripheral suspension request flag */     
+}CRYP_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Key_Size  Key size selection
+  * @{
+  */
+#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)  /*!< 128-bit long key */ 
+#define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE          /*!< 256-bit long key */ 
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Data_Type  AES Data Type selection
+  * @{
+  */
+#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)  /*!< 32-bit data type (no swapping)        */
+#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
+#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
+#define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
+/**
+  * @}
+  */
+  
+ /** @defgroup CRYP_AES_State  AES Enable state
+  * @{
+  */ 
+#define CRYP_AES_DISABLE                 ((uint32_t)0x00000000)   /*!< Disable AES */
+#define CRYP_AES_ENABLE                   AES_CR_EN               /*!< Enable AES  */
+/**
+  * @}
+  */            
+  
+/** @defgroup CRYP_AES_OperatingMode AES operating mode
+  * @{
+  */ 
+#define CRYP_ALGOMODE_ENCRYPT                   ((uint32_t)0x00000000)  /*!< Encryption mode                                              */
+#define CRYP_ALGOMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode                                          */
+#define CRYP_ALGOMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption                                                   */
+#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption                                */
+#define CRYP_ALGOMODE_TAG_GENERATION            ((uint32_t)0x00000000)  /*!< GMAC or CMAC (when applicable) authentication tag generation */
+/**
+  * @}
+  */                   
+
+/** @defgroup CRYP_AES_ChainingMode AES chaining mode
+  * @{
+  */                                                                
+#define CRYP_CHAINMODE_AES_ECB            ((uint32_t)0x00000000)            /*!< Electronic codebook chaining algorithm                   */
+#define CRYP_CHAINMODE_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
+#define CRYP_CHAINMODE_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
+#define CRYP_CHAINMODE_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#if defined(AES_CR_NPBLB)
+#define CRYP_CHAINMODE_AES_CCM            AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode                                 */
+#else
+#define CRYP_CHAINMODE_AES_CMAC           AES_CR_CHMOD_2                    /*!< Cipher message authentication code                       */
+#endif
+/**         
+  * @}
+  */
+  
+/** @defgroup CRYP_Key_Write AES decryption key write-up flag
+  * @{
+  */ 
+#define CRYP_KEY_WRITE_ENABLE            ((uint32_t)0x00000000)  /*!< Enable decryption key writing  */ 
+#define CRYP_KEY_WRITE_DISABLE           ((uint32_t)0x00000001)  /*!< Disable decryption key writing */ 
+/**
+  * @}
+  */  
+  
+/** @defgroup CRYP_DMAIN DMA Input phase management enable state
+  * @{
+  */
+#define CRYP_DMAIN_DISABLE             ((uint32_t)0x00000000)    /*!< Disable DMA Input phase management */
+#define CRYP_DMAIN_ENABLE              AES_CR_DMAINEN            /*!< Enable DMA Input phase management  */
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
+  * @{
+  */
+#define CRYP_DMAOUT_DISABLE             ((uint32_t)0x00000000)   /*!< Disable DMA Output phase management */
+#define CRYP_DMAOUT_ENABLE              AES_CR_DMAOUTEN          /*!< Enable DMA Output phase management  */
+/**
+  * @}
+  */  
+  
+  
+/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CCM/CMAC (when applicable) processing phase selection
+  * @{
+  */
+#define CRYP_GCM_INIT_PHASE             ((uint32_t)0x00000000)  /*!< GCM/GMAC (or CCM) init phase   */ 
+#define CRYP_GCMCMAC_HEADER_PHASE       AES_CR_GCMPH_0          /*!< GCM/GMAC/CCM/CMAC header phase */ 
+#define CRYP_GCM_PAYLOAD_PHASE          AES_CR_GCMPH_1          /*!< GCM/CCM payload phase          */ 
+#define CRYP_GCMCMAC_FINAL_PHASE        AES_CR_GCMPH            /*!< GCM/GMAC/CCM/CMAC final phase  */ 
+/* Definitions duplication for code readibility's sake: 
+   supported or not supported chain modes are not specified for each phase */
+#define CRYP_INIT_PHASE                 ((uint32_t)0x00000000)  /*!< Init phase    */ 
+#define CRYP_HEADER_PHASE               AES_CR_GCMPH_0          /*!< Header phase  */ 
+#define CRYP_PAYLOAD_PHASE              AES_CR_GCMPH_1          /*!< Payload phase */ 
+#define CRYP_FINAL_PHASE                AES_CR_GCMPH            /*!< Final phase   */ 
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Flags   AES status flags
+  * @{
+  */
+
+#define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
+#define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
+#define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
+#define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_Clear_Flags   AES clearing flags
+  * @{
+  */
+
+#define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
+#define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear                */
+/**
+  * @}
+  */
+
+/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
+  * @{
+  */ 
+#define CRYP_IT_CCFIE                         AES_CR_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_ERRIE                         AES_CR_ERRIE /*!< Error interrupt enable                */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Interrupts_Flags   AES Interrupts flags
+  * @{
+  */
+#define CRYP_IT_WRERR   AES_SR_WRERR  /*!< Write Error           */
+#define CRYP_IT_RDERR   AES_SR_RDERR  /*!< Read Error            */
+#define CRYP_IT_CCF     AES_SR_CCF    /*!< Computation completed */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRYP handle state.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+  * @brief  Enable the CRYP AES peripheral.
+  * @param  __HANDLE__: specifies the CRYP handle.  
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  AES_CR_EN)
+
+/**
+  * @brief  Disable the CRYP AES peripheral.
+  * @param  __HANDLE__: specifies the CRYP handle.  
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~AES_CR_EN)
+
+/**
+  * @brief  Set the algorithm operating mode.
+  * @param  __HANDLE__: specifies the CRYP handle.  
+  * @param  __OPERATING_MODE__: specifies the operating mode
+  *          This parameter can be one of the following values:
+  *            @arg @ref CRYP_ALGOMODE_ENCRYPT encryption     
+  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation        
+  *            @arg @ref CRYP_ALGOMODE_DECRYPT decryption 
+  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption  
+  * @retval None
+  */
+#define __HAL_CRYP_SET_OPERATINGMODE(__HANDLE__, __OPERATING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_MODE, (__OPERATING_MODE__))  
+
+
+/**
+  * @brief  Set the algorithm chaining mode.
+  * @param  __HANDLE__: specifies the CRYP handle.  
+  * @param  __CHAINING_MODE__: specifies the chaining mode
+  *          This parameter can be one of the following values:
+  *            @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook     
+  *            @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining        
+  *            @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
+  *            @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code     
+  *            @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
+  * @retval None
+  */
+#define __HAL_CRYP_SET_CHAININGMODE(__HANDLE__, __CHAINING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_CHMOD, (__CHAINING_MODE__))  
+
+
+
+/** @brief  Check whether the specified CRYP status flag is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden  
+  *            @arg @ref CRYP_IT_WRERR Write Error 
+  *            @arg @ref CRYP_IT_RDERR Read Error 
+  *            @arg @ref CRYP_IT_CCF Computation Complete                 
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Clear the CRYP pending status flag.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear  
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
+
+
+
+/** @brief  Check whether the specified CRYP interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param __INTERRUPT__: CRYP interrupt source to check
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt  
+  * @retval State of interruption (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+/** @brief  Check whether the specified CRYP interrupt is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: specifies the interrupt to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_WRERR Write Error 
+  *            @arg @ref CRYP_IT_RDERR Read Error 
+  *            @arg @ref CRYP_IT_CCF  Computation Complete                 
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+
+/** @brief  Clear the CRYP pending interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: specifies the IT to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear    
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/**
+  * @brief  Enable the CRYP interrupt.  
+  * @param  __HANDLE__: specifies the CRYP handle.   
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values:  
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt    
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+
+/**
+  * @brief  Disable the CRYP interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.  
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values:  
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt    
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  CRYP_Private_Macros   CRYP Private Macros
+  * @{
+  */
+
+/**
+  * @brief Verify the key size length.
+  * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. 
+  * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
+  */  
+#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
+                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+/**
+  * @brief Verify the input data type.
+  * @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+  */  
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+/**
+  * @brief Verify the CRYP AES IP running mode.
+  * @param __MODE__: CRYP AES IP running mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */                                     
+#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
+                               ((__MODE__) == CRYP_AES_ENABLE)) 
+
+/**
+  * @brief Verify the selected CRYP algorithm.
+  * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
+  * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
+  */                            
+#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT)        || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION)  || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT)        || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))  
+
+/**
+  * @brief Verify the selected CRYP chaining algorithm.
+  * @param __CHAINMODE__: Selected CRYP chaining algorithm.
+  * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
+  */   
+#if defined(AES_CR_NPBLB)
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM))   
+#else
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))    
+#endif                                
+
+/**
+  * @brief Verify the deciphering key write option.
+  * @param __WRITE__: deciphering key write option.
+  * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
+  */                                   
+#define IS_CRYP_WRITE(__WRITE__)   (((__WRITE__) == CRYP_KEY_WRITE_ENABLE)      || \
+                                    ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
+
+/**
+  * @brief Verify the CRYP input data DMA mode.
+  * @param __MODE__: CRYP input data DMA mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */  
+#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
+                                 ((__MODE__) == CRYP_DMAIN_ENABLE)) 
+
+/**
+  * @brief Verify the CRYP output data DMA mode.
+  * @param __MODE__: CRYP output data DMA mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */                             
+#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
+                                  ((__MODE__) == CRYP_DMAOUT_ENABLE)) 
+
+/**
+  * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
+  * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
+  * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
+  */                               
+#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_INIT_PHASE)    || \
+                                          ((__PHASE__) == CRYP_HEADER_PHASE)  || \
+                                          ((__PHASE__) == CRYP_PAYLOAD_PHASE) || \
+                                          ((__PHASE__) == CRYP_FINAL_PHASE))
+                                      
+/**
+  * @}
+  */
+
+/* Include CRYP HAL Extended module */
+#include "stm32l4xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
+  * @{
+  */
+    
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* MSP initialization/de-initialization functions  ****************************/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions 
+  * @{
+  */  
+
+/* AES encryption/decryption processing functions  ****************************/
+
+/* AES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
+  * @{
+  */ 
+/* CallBack functions  ********************************************************/
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);  
+  
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler 
+  * @{
+  */    
+
+/* AES interrupt handling function  *******************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions 
+  * @{
+  */
+
+/* Peripheral State functions  ************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+uint32_t              HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */  
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c
new file mode 100755
index 0000000..11340c0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c
@@ -0,0 +1,3115 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cryp_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   CRYPEx HAL module driver.
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the Cryptography (CRYP) peripheral.  
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRYPEx CRYPEx
+  * @brief CRYP Extended HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+  * @{
+  */
+#define CRYP_CCF_TIMEOUTVALUE                      22000  /*!< CCF flag raising time-out value */
+#define CRYP_BUSY_TIMEOUTVALUE                     22000  /*!< BUSY flag reset time-out value  */
+
+#define CRYP_POLLING_OFF                             0x0  /*!< No polling when padding */
+#define CRYP_POLLING_ON                              0x1  /*!< Polling when padding    */
+
+#if defined(AES_CR_NPBLB)
+#define AES_POSITION_CR_NPBLB     (uint32_t)POSITION_VAL(AES_CR_NPBLB)    /*!< Required left shift to set background CLUT size */
+#endif
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout);
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function 
+ *  @brief    Extended callback functions. 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Extended callback functions #####
+ =============================================================================== 
+    [..]  This section provides callback function:
+      (+) Computation completed.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Computation completed callbacks.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions 
+ *  @brief   Extended processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### AES extended processing functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes.
+          Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated
+          based on the processing type. Three processing types are available:
+          (++) Polling mode
+          (++) Interrupt mode
+          (++) DMA mode
+      (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES 
+          algorithm in different chaining modes.
+          Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase 
+          so that steps can be skipped if so required. Functions are only differentiated based on the processing type. 
+          Three processing types are available:
+          (++) Polling mode
+          (++) Interrupt mode
+          (++) DMA mode          
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Carry out in polling mode the ciphering or deciphering operation according to
+  *         hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and 
+  *         chaining modes ECB, CBC and CTR are managed by this function in polling mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption
+  *                     or key derivation+decryption.
+  *                     Parameter is meaningless in case of key derivation.      
+  * @param  Size: Length of the input data buffer in bytes, must be a multiple of 16.
+  *               Parameter is meaningless in case of key derivation.  
+  * @param  pOutputData: Pointer to the cipher text in case of encryption or plain text in case of 
+  *                     decryption/key derivation+decryption, or pointer to the derivative keys in
+  *                     case of key derivation only.   
+  * @param  Timeout: Specify Timeout value 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
+{
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Check parameters setting */
+    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+    {
+      if (pOutputData == NULL) 
+      {
+        return  HAL_ERROR;
+      }
+    }
+    else
+    {
+      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
+      {
+        return  HAL_ERROR;
+      }
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+  
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+    /* Call CRYP_ReadKey() API if the operating mode is set to
+       key derivation, CRYP_ProcessData() otherwise  */
+    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+    {
+      if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }    
+    }
+    else
+    {
+      if(CRYP_ProcessData(hcryp, pInputData, Size, pOutputData, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  
+    /* If the state has not been set to SUSPENDED, set it to
+       READY, otherwise keep it as it is */
+    if (hcryp->State != HAL_CRYP_STATE_SUSPENDED)
+    {
+      hcryp->State = HAL_CRYP_STATE_READY;
+    }
+  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+
+/**
+  * @brief  Carry out in interrupt mode the ciphering or deciphering operation according to
+  *         hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and 
+  *         chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption
+  *                     or key derivation+decryption.
+  *                     Parameter is meaningless in case of key derivation.      
+  * @param  Size: Length of the input data buffer in bytes, must be a multiple of 16.
+  *               Parameter is meaningless in case of key derivation.  
+  * @param  pOutputData: Pointer to the cipher text in case of encryption or plain text in case of 
+  *                     decryption/key derivation+decryption, or pointer to the derivative keys in 
+  *                     case of key derivation only.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
+{
+  uint32_t inputaddr = 0;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Check parameters setting */
+    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+    {
+      if (pOutputData == NULL) 
+      {
+        return  HAL_ERROR;
+      }
+    }
+    else
+    {
+      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
+      {
+        return  HAL_ERROR;
+      }
+    }
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* If operating mode is not limited to key derivation only,
+       get the buffers addresses and sizes */
+    if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+    {
+
+      hcryp->CrypInCount = Size;
+      hcryp->pCrypInBuffPtr = pInputData;
+      hcryp->pCrypOutBuffPtr = pOutputData;
+      hcryp->CrypOutCount = Size;
+    }
+    else
+    {
+      /* For key derivation, set output buffer only
+        (will point at derivated key) */
+      hcryp->pCrypOutBuffPtr = pOutputData;
+    }
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+      /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Enable Computation Complete Flag and Error Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+    
+    
+    /* If operating mode is key derivation only, the input data have 
+       already been entered during the initialization process. For
+       the other operating modes, they are fed to the CRYP hardware 
+       block at this point. */
+    if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+    {
+      /* Initiate the processing under interrupt in entering 
+         the first input data */
+      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+      /* Increment/decrement instance pointer/counter */
+      hcryp->pCrypInBuffPtr += 16;
+      hcryp->CrypInCount -= 16;
+      /* Write the first input block in the Data Input register */
+      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      inputaddr+=4;
+      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      inputaddr+=4;
+      hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+      inputaddr+=4;
+      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    }
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+  
+  
+  
+
+
+/**
+  * @brief  Carry out in DMA mode the ciphering or deciphering operation according to
+  *         hcryp->Init structure fields.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption
+  *                     or key derivation+decryption.    
+  * @param  Size: Length of the input data buffer in bytes, must be a multiple of 16.
+  * @param  pOutputData: Pointer to the cipher text in case of encryption or plain text in case of 
+  *                     decryption/key derivation+decryption.
+  * @note   Chaining modes ECB, CBC and CTR are managed by this function in DMA mode.   
+  * @note   Supported operating modes are encryption, decryption and key derivation with decryption. 
+  * @note   No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx 
+  *         registers must be done by software.   
+  * @note   This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx 
+  *         registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
+  * @note   pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
+{
+  uint32_t inputaddr = 0;
+  uint32_t outputaddr = 0;
+  
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Check parameters setting */
+    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+    {
+      /* no DMA channel is provided for key derivation operating mode, 
+         access to AES_KEYRx registers must be done by software */
+      return  HAL_ERROR;
+    }
+    else
+    {
+      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
+      {
+        return  HAL_ERROR;
+      }
+    }
+    
+    
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pInputData;
+    outputaddr = (uint32_t)pOutputData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+  
+
+
+
+
+
+/**
+  * @brief  Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering 
+  *         operation according to hcryp->Init structure fields. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pInputData: 
+  *         - pointer to payload data in GCM or CCM payload phase, 
+  *         - pointer to B0 block in CMAC header phase,
+  *         - pointer to C block in CMAC final phase. 
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases.                                          
+  * @param  Size: 
+  *         - length of the input payload data buffer in bytes in GCM or CCM payload phase,
+  *         - length of B0 block (in bytes) in CMAC header phase,
+  *         - length of C block (in bytes) in CMAC final phase.
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases.   
+  *         - Parameter is meaningless in case of CCM final phase. 
+  *         - Parameter is message length in bytes in case of GCM final phase.  
+  *         - Parameter must be set to zero in case of GMAC final phase.                                      
+  * @param  pOutputData: 
+  *         - pointer to plain or cipher text in GCM/CCM payload phase, 
+  *         - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase.
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases.
+  *         - Parameter is meaningless in case of CMAC header phase.  
+  * @param  Timeout: Specify Timeout value 
+  * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable.
+  * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes 
+  *         can be skipped by the user if so required.          
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
+{
+  uint32_t index          = 0;
+  uint32_t inputaddr      = 0;
+  uint32_t outputaddr     = 0;
+  uint32_t tagaddr        = 0;
+  uint64_t headerlength   = 0; 
+  uint64_t inputlength    = 0;
+  uint64_t payloadlength  = 0; 
+  uint32_t difflength     = 0;
+  uint32_t addhoc_process = 0;  
+  
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* input/output parameters check */
+    if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+    {
+      if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) ||
+          ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0)))
+      {
+        return  HAL_ERROR;
+      }
+#if defined(AES_CR_NPBLB)
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)
+#else      
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif      
+      {
+        /* In case of CMAC or CCM (when applicable) header phase resumption, we can have pInputData = NULL and  Size = 0 */
+        if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))
+        {
+          return  HAL_ERROR;
+        }
+      }
+    }
+    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+    {   
+      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
+      {
+        return  HAL_ERROR;
+      }
+    }
+    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+    {
+      if (pOutputData == NULL)
+      {
+        return  HAL_ERROR;
+      }
+#if !defined(AES_CR_NPBLB)    
+      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
+      {
+        return  HAL_ERROR;
+      }
+#endif        
+    }
+      
+      
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+  
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+    /*==============================================*/
+    /* GCM/GMAC (or CCM when applicable) init phase */
+    /*==============================================*/
+    /* In case of init phase, the input data (Key and Initialization Vector) have 
+       already been entered during the initialization process. Therefore, the
+       API just waits for the CCF flag to be set. */
+    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+    {
+      /* just wait for hash computation */
+      if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  
+      { 
+        hcryp->State = HAL_CRYP_STATE_READY;        
+        __HAL_UNLOCK(hcryp);
+        return HAL_TIMEOUT;
+      }
+      
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      /* Mark that the initialization phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
+    }
+    /*=======================================================*/
+    /* GCM/GMAC or (CCM / CMAC when applicable) header phase */
+    /*=======================================================*/
+    else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+    { 
+#if !defined(AES_CR_NPBLB)          
+      /* Set header phase; for GCM or GMAC, set data-byte at this point */
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+      {
+        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
+      }
+      else
+#endif      
+      {
+        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
+      }
+         
+      /* Enable the Peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+      
+#if !defined(AES_CR_NPBLB)    
+      /* in case of CMAC, enter B0 block in header phase, before the header itself. */
+      /* If Size = 0 (possible case of resumption after CMAC header phase suspension),
+         skip these steps and go directly to header buffer feeding to the HW */
+      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0))
+      {
+        inputaddr = (uint32_t)pInputData; 
+        
+        for( ; (index < Size); index += 16)
+        {
+          /* Write the Input block in the Data Input register */
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          
+          if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  
+          { 
+            hcryp->State = HAL_CRYP_STATE_READY;        
+            __HAL_UNLOCK(hcryp);
+            return HAL_TIMEOUT;
+          }
+          /* Clear CCF Flag */
+          __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);           
+
+          /* If the suspension flag has been raised and if the processing is not about
+           to end, suspend processing */  
+          if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size))        
+          {
+            /* reset SuspendRequest */
+            hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+            /* Change the CRYP state */
+            hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+            /* Mark that the header phase is over */
+            hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+            
+           /* Save current reading and writing locations of Input and Output buffers */
+           hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
+           /* Save the total number of bytes (B blocks + header) that remain to be 
+              processed at this point */
+           hcryp->CrypInCount     =  hcryp->Init.HeaderSize + Size - (index+16);
+        
+           /* Process Unlocked */
+            __HAL_UNLOCK(hcryp);
+        
+            return HAL_OK;
+          } 
+        } /* for(index=0; (index < Size); index += 16) */             
+      }
+#endif /* !defined(AES_CR_NPBLB) */      
+      
+      /* Enter header */  
+      inputaddr = (uint32_t)hcryp->Init.Header; 
+      /* Local variable headerlength is a number of bytes multiple of 128 bits,
+         remaining header data (if any) are handled after this loop */
+      headerlength =  (((hcryp->Init.HeaderSize)/16)*16) ; 
+      if ((hcryp->Init.HeaderSize % 16) != 0)
+      {
+        difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength);   
+      }
+      for(index=0; index < headerlength; index += 16)
+      {
+        /* Write the Input block in the Data Input register */
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        
+        if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  
+        { 
+          hcryp->State = HAL_CRYP_STATE_READY;        
+          __HAL_UNLOCK(hcryp);
+          return HAL_TIMEOUT;
+        }
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); 
+        
+        /* If the suspension flag has been raised and if the processing is not about
+         to end, suspend processing */  
+        if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength))        
+        {
+          /* reset SuspendRequest */
+          hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+          /* Change the CRYP state */
+          hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+          /* Mark that the header phase is over */
+          hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+          
+         /* Save current reading and writing locations of Input and Output buffers */
+         hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
+         /* Save the total number of bytes that remain to be processed at this point */
+          hcryp->CrypInCount =  hcryp->Init.HeaderSize - (index+16);
+      
+         /* Process Unlocked */
+          __HAL_UNLOCK(hcryp);
+      
+          return HAL_OK;
+        }       
+      }
+      
+      /* Case header length is not a multiple of 16 bytes */
+      if (difflength != 0)
+      {
+        hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
+        CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);   
+      }       
+      
+      /* Mark that the header phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+    }
+    /*============================================*/
+    /* GCM (or CCM when applicable) payload phase */
+    /*============================================*/
+    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+    {
+      
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
+      
+      /* if the header phase has been bypassed, AES must be enabled again */
+      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+      {
+        __HAL_CRYP_ENABLE(hcryp);  
+      }
+      
+      inputaddr  = (uint32_t)pInputData;
+      outputaddr = (uint32_t)pOutputData;
+      
+      /* Enter payload */
+      /* Specific handling to manage payload last block size less than 128 bits */
+      if ((Size % 16) != 0)
+      {
+        payloadlength = (Size/16) * 16;
+        difflength = (uint32_t) (Size - payloadlength);
+        addhoc_process = 1;
+      }
+      else
+      {
+        payloadlength = Size;     
+      }
+            
+      /* Feed payload */  
+      for( ; index < payloadlength; index += 16)
+      {
+        /* Write the Input block in the Data Input register */
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        
+        if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  
+        { 
+          hcryp->State = HAL_CRYP_STATE_READY;        
+          __HAL_UNLOCK(hcryp);
+          return HAL_TIMEOUT;
+        }
+          
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+        
+        /* Retrieve output data: read the output block 
+           from the Data Output Register */
+        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+        outputaddr+=4;
+       
+        /* If the suspension flag has been raised and if the processing is not about
+         to end, suspend processing */  
+        if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength))
+        {
+          /* no flag waiting under IRQ handling */
+          if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+          {
+            /* Ensure that Busy flag is reset */
+            if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)  
+            {   
+              hcryp->State = HAL_CRYP_STATE_READY;        
+              __HAL_UNLOCK(hcryp);
+              return HAL_TIMEOUT;
+            }
+          }               
+          /* reset SuspendRequest */
+          hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+          /* Change the CRYP state */
+          hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+          /* Mark that the header phase is over */
+          hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+          
+          /* Save current reading and writing locations of Input and Output buffers */
+          hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;
+          hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
+          /* Save the number of bytes that remain to be processed at this point */
+          hcryp->CrypInCount     =  Size - (index+16);          
+        
+          /* Process Unlocked */
+          __HAL_UNLOCK(hcryp);
+        
+          return HAL_OK;
+        }            
+        
+      }
+      
+      /* Additional processing to manage GCM(/CCM) encryption and decryption cases when 
+         payload last block size less than 128 bits */
+      if (addhoc_process == 1)
+      {
+        
+        hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
+        hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;        
+        CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); 
+       
+      } /* (addhoc_process == 1) */
+         
+      /* Mark that the payload phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;         
+    }
+    /*==================================*/
+    /* GCM/GMAC/CCM or CMAC final phase */
+    /*==================================*/
+    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+    {    
+      tagaddr = (uint32_t)pOutputData;
+      
+#if defined(AES_CR_NPBLB)   
+     /* By default, clear NPBLB field */
+      CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
+#endif        
+      
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
+      
+      /* if the header and payload phases have been bypassed, AES must be enabled again */
+      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+      {
+        __HAL_CRYP_ENABLE(hcryp);  
+      }
+                                                             
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+      {
+        headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
+        inputlength = Size * 8;                    /* input length in bits */ 
+        
+#if !defined(AES_CR_NPBLB)   
+        if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+        {
+          hcryp->Instance->DINR = __RBIT((headerlength)>>32);
+          hcryp->Instance->DINR = __RBIT(headerlength);
+          hcryp->Instance->DINR = __RBIT((inputlength)>>32);
+          hcryp->Instance->DINR = __RBIT(inputlength);
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+        {
+          hcryp->Instance->DINR = __REV((headerlength)>>32);
+          hcryp->Instance->DINR = __REV(headerlength);
+          hcryp->Instance->DINR = __REV((inputlength)>>32);
+          hcryp->Instance->DINR = __REV(inputlength);
+        } 
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+        {
+          hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
+          hcryp->Instance->DINR = __ROR(headerlength, 16);
+          hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
+          hcryp->Instance->DINR = __ROR(inputlength, 16);          
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+        {
+          hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
+          hcryp->Instance->DINR = (uint32_t)(headerlength);
+          hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
+          hcryp->Instance->DINR = (uint32_t)(inputlength);
+        }
+#else        
+        hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
+        hcryp->Instance->DINR = (uint32_t)(headerlength);
+        hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
+        hcryp->Instance->DINR = (uint32_t)(inputlength);
+#endif 
+      }
+#if !defined(AES_CR_NPBLB)             
+      else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)     
+      {
+        inputaddr  = (uint32_t)pInputData;
+        /* Enter the last block made of a 128-bit value formatted
+           from the original B0 packet. */
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      }
+#endif       
+      
+      
+      if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  
+      { 
+          hcryp->State = HAL_CRYP_STATE_READY;        
+          __HAL_UNLOCK(hcryp);
+          return HAL_TIMEOUT;
+      }
+
+      /* Read the Auth TAG in the Data Out register */
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+      tagaddr+=4;
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+      tagaddr+=4;
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+      tagaddr+=4;
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; 
+         
+
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      /* Mark that the final phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+      /* Disable the Peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+    }
+    /*=================================================*/
+    /* case incorrect hcryp->Init.GCMCMACPhase setting */
+    /*=================================================*/
+    else
+    {
+      hcryp->State = HAL_CRYP_STATE_ERROR; 
+      __HAL_UNLOCK(hcryp); 
+      return HAL_ERROR;
+    }
+ 
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+
+
+/**
+  * @brief  Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering 
+  *         operation according to hcryp->Init structure fields. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pInputData: 
+  *         - pointer to payload data in GCM or CCM payload phase, 
+  *         - pointer to B0 block in CMAC header phase,
+  *         - pointer to C block in CMAC final phase. 
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases.                                          
+  * @param  Size: 
+  *         - length of the input payload data buffer in bytes in GCM or CCM payload phase,
+  *         - length of B0 block (in bytes) in CMAC header phase,
+  *         - length of C block (in bytes) in CMAC final phase.
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases.   
+  *         - Parameter is meaningless in case of CCM final phase. 
+  *         - Parameter is message length in bytes in case of GCM final phase.  
+  *         - Parameter must be set to zero in case of GMAC final phase.                                      
+  * @param  pOutputData: 
+  *         - pointer to plain or cipher text in GCM/CCM payload phase, 
+  *         - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase.
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases.
+  *         - Parameter is meaningless in case of CMAC header phase.  
+  * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
+  * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes 
+  *         can be skipped by the user if so required.                                 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
+{
+
+  uint32_t inputaddr      = 0;
+  uint64_t headerlength   = 0;
+  uint64_t inputlength    = 0;
+  uint32_t index          = 0;
+  uint32_t addhoc_process = 0; 
+  uint32_t difflength     = 0;
+  uint32_t difflengthmod4 = 0;
+  uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};     
+ 
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* input/output parameters check */
+    if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+    {
+      if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) ||
+          ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0)))
+      {
+        return  HAL_ERROR;
+      }
+#if defined(AES_CR_NPBLB) 
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)
+#else       
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif         
+      {
+        /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and  Size = 0 */
+        if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))
+        {
+          return  HAL_ERROR;
+        }
+      }      
+    }
+    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+    {   
+      if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL))
+      {
+        return  HAL_ERROR;
+      }
+    }
+    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+    {
+      if (pOutputData == NULL)
+      {
+        return  HAL_ERROR;
+      }
+#if !defined(AES_CR_NPBLB)    
+      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) 
+      {
+        return  HAL_ERROR;
+      }
+#endif
+    }
+    
+    
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+                           
+    /* Enable Computation Complete Flag and Error Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+
+
+
+    /*==============================================*/
+    /* GCM/GMAC (or CCM when applicable) init phase */
+    /*==============================================*/
+    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+    {    
+    /* In case of init phase, the input data (Key and Initialization Vector) have 
+       already been entered during the initialization process. Therefore, the
+       software just waits for the CCF interrupt to be raised and which will
+       be handled by CRYP_AES_Auth_IT() API. */
+    }
+    /*===================================*/
+    /* GCM/GMAC/CCM or CMAC header phase */
+    /*===================================*/   
+    else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+    {
+    
+#if defined(AES_CR_NPBLB)   
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)
+#else    
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif      
+      {
+        /* In case of CMAC, B blocks are first entered, before the header.
+           Therefore, B blocks and the header are entered back-to-back
+           as if it was only one single block. 
+           However, in case of resumption after suspension, if all the
+           B blocks have been entered (in that case, Size = 0), only the
+           remainder of the non-processed header bytes are entered. */
+          if (Size != 0)
+          {
+            hcryp->CrypInCount = Size + hcryp->Init.HeaderSize;
+            hcryp->pCrypInBuffPtr = pInputData;
+          }
+          else
+          {
+            hcryp->CrypInCount = hcryp->Init.HeaderSize;
+            hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+          }
+      }
+      else
+      {
+        /* Get the header addresses and sizes */
+        hcryp->CrypInCount = hcryp->Init.HeaderSize;
+        hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+      }    
+    
+      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+
+#if !defined(AES_CR_NPBLB)       
+      /* Set header phase; for GCM or GMAC, set data-byte at this point */
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+      {
+        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
+      }
+      else
+#endif      
+      {
+        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
+      }
+       
+      /* Enable the Peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+    
+      /* Increment/decrement instance pointer/counter */
+      if (hcryp->CrypInCount == 0)
+      {
+        /* Case of no header */
+        hcryp->State = HAL_CRYP_STATE_READY; 
+        /* Mark that the header phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;         
+        return HAL_OK;        
+      }
+      else if (hcryp->CrypInCount < 16)
+      {
+        hcryp->CrypInCount = 0;
+        addhoc_process = 1;  
+        difflength = (uint32_t) (hcryp->Init.HeaderSize);
+        difflengthmod4 = difflength%4;              
+      }
+      else
+      {
+        hcryp->pCrypInBuffPtr += 16;
+        hcryp->CrypInCount -= 16;
+      }
+      
+      
+#if defined(AES_CR_NPBLB)    
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)
+#else     
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif      
+      { 
+        if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
+        {
+          /* All B blocks will have been entered after the next
+             four DINR writing, so point at header buffer for
+             the next iteration */
+          hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+        }
+      }       
+    
+      /* Enter header first block to initiate the process
+         in the Data Input register */
+      if (addhoc_process == 0)
+      { 
+        /* Header has size equal or larger than 128 bits */        
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      }
+      else
+      {
+        /* Header has size less than 128 bits */ 
+        /* Enter complete words when possible */
+        for( ; index < (difflength/4); index ++)
+        {
+          /* Write the Input block in the Data Input register */
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+        }
+        /* Enter incomplete word padded with zeroes if applicable 
+          (case of header length not a multiple of 32-bits) */
+        if (difflengthmod4 != 0)
+        {         
+          hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+        }         
+        /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
+        for(index=0; index < (4 - ((difflength+3)/4)); index ++)         
+        {
+          hcryp->Instance->DINR = 0;
+        }                 
+      
+      }
+    }
+    /*============================================*/
+    /* GCM (or CCM when applicable) payload phase */
+    /*============================================*/
+    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+    {
+      /* Get the buffer addresses and sizes */
+      hcryp->CrypInCount = Size;
+      hcryp->pCrypInBuffPtr = pInputData;
+      hcryp->pCrypOutBuffPtr = pOutputData;
+      hcryp->CrypOutCount = Size; 
+    
+      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+      
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
+       
+      /* if the header phase has been bypassed, AES must be enabled again */
+      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+      {
+        __HAL_CRYP_ENABLE(hcryp);  
+      }
+      
+      /* No payload case */
+      if (pInputData == NULL)
+      {
+        hcryp->State = HAL_CRYP_STATE_READY;   
+        /* Mark that the header phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; 
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+  
+        return HAL_OK;             
+      }      
+    
+     /* Specific handling to manage payload size less than 128 bits */
+      if (Size < 16)
+      {
+        difflength = (uint32_t) (Size);
+#if defined(AES_CR_NPBLB)  
+        /* In case of GCM encryption or CCM decryption, specify the number of padding
+           bytes in last block of payload */
+        if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
+        {
+          if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
+               &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))   
+           ||  ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM)
+               &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
+          {
+            /* Set NPBLB field in writing the number of padding bytes 
+               for the last block of payload */
+            MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB);
+          }
+        }
+#else
+        /* Software workaround applied to GCM encryption only */ 
+        if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+        {
+          /* Change the mode configured in CHMOD bits of CR register to select CTR mode */   
+          __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR);
+        } 
+#endif        
+
+
+        /* Set hcryp->CrypInCount to 0 (no more data to enter) */ 
+        hcryp->CrypInCount = 0;  
+
+        /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes, 
+            to have a complete block of 128 bits */              
+        difflengthmod4 = difflength%4;                 
+        /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes 
+            to have a complete block of 128 bits */
+        for(index=0; index < (difflength/4); index ++)
+        {
+          /* Write the Input block in the Data Input register */
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+        }
+        /* If required, manage input data size not multiple of 32 bits */
+        if (difflengthmod4 != 0)
+        {         
+          hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+        }         
+        /* Wrap-up in padding with zero-words if applicable */
+        for(index=0; index < (4 - ((difflength+3)/4)); index ++)        
+        {
+          hcryp->Instance->DINR = 0;
+        }               
+      }
+      else
+      {        
+        /* Increment/decrement instance pointer/counter */
+        hcryp->pCrypInBuffPtr += 16;
+        hcryp->CrypInCount -= 16;
+        
+        /* Enter payload first block to initiate the process
+           in the Data Input register */
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      }
+    }
+    /*==================================*/
+    /* GCM/GMAC/CCM or CMAC final phase */
+    /*==================================*/
+    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+    {
+       hcryp->pCrypOutBuffPtr = pOutputData;
+       
+#if defined(AES_CR_NPBLB)   
+     /* By default, clear NPBLB field */
+      CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
+#endif         
+       
+       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
+       
+      /* if the header and payload phases have been bypassed, AES must be enabled again */
+      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+      {
+        __HAL_CRYP_ENABLE(hcryp);  
+      }
+      
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+      {             
+        headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
+        inputlength = Size * 8;                    /* Input length in bits */ 
+        /* Write the number of bits in the header on 64 bits followed by the number
+           of bits in the payload on 64 bits as well */
+        
+#if !defined(AES_CR_NPBLB)           
+        if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+        {
+          hcryp->Instance->DINR = __RBIT((headerlength)>>32);
+          hcryp->Instance->DINR = __RBIT(headerlength);
+          hcryp->Instance->DINR = __RBIT((inputlength)>>32);
+          hcryp->Instance->DINR = __RBIT(inputlength);
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+        {
+          hcryp->Instance->DINR = __REV((headerlength)>>32);
+          hcryp->Instance->DINR = __REV(headerlength);
+          hcryp->Instance->DINR = __REV((inputlength)>>32);
+          hcryp->Instance->DINR = __REV(inputlength);
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+        {
+          hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
+          hcryp->Instance->DINR = __ROR(headerlength, 16);
+          hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
+          hcryp->Instance->DINR = __ROR(inputlength, 16);             
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+        {
+          hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
+          hcryp->Instance->DINR = (uint32_t)(headerlength);
+          hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
+          hcryp->Instance->DINR = (uint32_t)(inputlength);
+        }
+#else
+        hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
+        hcryp->Instance->DINR = (uint32_t)(headerlength);
+        hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
+        hcryp->Instance->DINR = (uint32_t)(inputlength);
+#endif        
+      }
+#if !defined(AES_CR_NPBLB)         
+      else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+      {
+        inputaddr  = (uint32_t)pInputData;
+        /* Enter the last block made of a 128-bit value formatted
+           from the original B0 packet. */
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      }
+#endif      
+    }
+    /*=================================================*/
+    /* case incorrect hcryp->Init.GCMCMACPhase setting */
+    /*=================================================*/
+    else
+    {
+      hcryp->State = HAL_CRYP_STATE_ERROR; 
+      return HAL_ERROR;
+    }
+  
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+
+
+/**
+  * @brief  Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering 
+  *         operation according to hcryp->Init structure fields. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pInputData: 
+  *         - pointer to payload data in GCM or CCM payload phase, 
+  *         - pointer to B0 block in CMAC header phase,
+  *         - pointer to C block in CMAC final phase. 
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases.                                          
+  * @param  Size: 
+  *         - length of the input payload data buffer in bytes in GCM or CCM payload phase,
+  *         - length of B0 block (in bytes) in CMAC header phase,
+  *         - length of C block (in bytes) in CMAC final phase.
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases.   
+  *         - Parameter is meaningless in case of CCM final phase. 
+  *         - Parameter is message length in bytes in case of GCM final phase.  
+  *         - Parameter must be set to zero in case of GMAC final phase.                                      
+  * @param  pOutputData: 
+  *         - pointer to plain or cipher text in GCM/CCM payload phase, 
+  *         - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase.
+  *         - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases.
+  *         - Parameter is meaningless in case of CMAC header phase. 
+  * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
+  * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes 
+  *         can be skipped by the user if so required.
+  * @note   pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.            
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
+{
+  uint32_t inputaddr      = 0;
+  uint32_t outputaddr     = 0;
+  uint32_t tagaddr        = 0;
+  uint64_t headerlength   = 0;
+  uint64_t inputlength    = 0;
+  uint64_t payloadlength  = 0;
+       
+  
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* input/output parameters check */
+    if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+    {
+      if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))
+      {
+        return  HAL_ERROR;
+      }
+#if defined(AES_CR_NPBLB) 
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)
+#else       
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif  
+      {
+        if ((pInputData == NULL) || (Size == 0))
+        {
+          return  HAL_ERROR;
+        }
+      }      
+    }
+    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+    {   
+      if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL))
+      {
+        return  HAL_ERROR;
+      }
+    }
+    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+    {
+      if (pOutputData == NULL)
+      {
+        return  HAL_ERROR;
+      }
+#if !defined(AES_CR_NPBLB)      
+      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
+      {
+        return  HAL_ERROR;
+      }
+#endif
+    }
+    
+    
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+  
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+    /*==============================================*/
+    /* GCM/GMAC (or CCM when applicable) init phase */
+    /*==============================================*/
+    /* In case of init phase, the input data (Key and Initialization Vector) have 
+       already been entered during the initialization process. No DMA transfer is
+       required at that point therefore, the software just waits for the CCF flag 
+       to be raised. */
+    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+    {
+      /* just wait for hash computation */
+      if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  
+      { 
+        hcryp->State = HAL_CRYP_STATE_READY;        
+        __HAL_UNLOCK(hcryp);
+        return HAL_TIMEOUT;
+      }
+      
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      /* Mark that the initialization phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
+      hcryp->State = HAL_CRYP_STATE_READY;
+    }
+    /*====================================*/
+    /* GCM/GMAC/ CCM or CMAC header phase */
+    /*====================================*/     
+    else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+    {     
+#if !defined(AES_CR_NPBLB)     
+      /* Set header phase; for GCM or GMAC, set data-byte at this point */
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+      {
+        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
+      }
+      else
+#endif      
+      {
+        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
+      }
+      
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+      
+#if !defined(AES_CR_NPBLB)         
+      /* enter first B0 block in polling mode (no DMA transfer for B0) */
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+      {
+        inputaddr  = (uint32_t)pInputData;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      
+        if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  
+        { 
+          hcryp->State = HAL_CRYP_STATE_READY;        
+          __HAL_UNLOCK(hcryp);
+          return HAL_TIMEOUT;
+        }
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      }
+#endif      
+      
+      /* No header case */
+      if (hcryp->Init.Header == NULL)
+      {
+        hcryp->State = HAL_CRYP_STATE_READY;   
+        /* Mark that the header phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; 
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+  
+        return HAL_OK;             
+      }
+      
+      inputaddr = (uint32_t)hcryp->Init.Header;
+      if ((hcryp->Init.HeaderSize % 16) != 0)
+      {
+
+        if (hcryp->Init.HeaderSize < 16)        
+        { 
+          hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;                
+          CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF);     
+          
+          hcryp->State = HAL_CRYP_STATE_READY;   
+          /* Mark that the header phase is over */
+          hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;  
+          
+          /* CCF flag indicating header phase AES processing completion 
+             will be checked at the start of the next phase:
+            - payload phase (GCM / CCM when applicable)
+            - final phase (GMAC or CMAC when applicable).  */                     
+        }
+        else
+        {
+          /* Local variable headerlength is a number of bytes multiple of 128 bits,
+            remaining header data (if any) are handled after this loop */
+          headerlength =  (((hcryp->Init.HeaderSize)/16)*16) ;         
+          /* Store the ending transfer point */
+          hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength;
+          hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */
+        
+          /* Set the input and output addresses and start DMA transfer */ 
+          /* (incomplete DMA transfer, will be wrapped up after completion of
+             the first one (initiated here) with data padding */
+          CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, headerlength, 0);
+        }                          
+      }
+      else
+      {
+        hcryp->CrypInCount = 0;
+        /* Set the input address and start DMA transfer */ 
+        CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0);            
+      }
+    }
+    /*============================================*/
+    /* GCM (or CCM when applicable) payload phase */
+    /*============================================*/
+    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+    {
+      /* Coming from header phase, wait for CCF flag to be raised 
+          if header present and fed to the IP in the previous phase */
+      if (hcryp->Init.Header != NULL)
+      {     
+        if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  
+        { 
+          hcryp->State = HAL_CRYP_STATE_READY;        
+          __HAL_UNLOCK(hcryp);
+          return HAL_TIMEOUT;
+        }     
+      }
+      else
+      {
+        /* Enable the Peripheral since wasn't in header phase (no header case) */
+        __HAL_CRYP_ENABLE(hcryp);
+      }
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);     
+    
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
+      
+      /* No payload case */
+      if (pInputData == NULL)
+      {
+        hcryp->State = HAL_CRYP_STATE_READY;   
+        /* Mark that the header phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; 
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+  
+        return HAL_OK;             
+      }
+      
+      
+      /* Specific handling to manage payload size less than 128 bits */ 
+      if ((Size % 16) != 0)
+      {
+        inputaddr  = (uint32_t)pInputData;
+        outputaddr = (uint32_t)pOutputData;      
+        if (Size < 16)
+        {
+          /* Block is now entered in polling mode, no actual gain in resorting to DMA */
+          hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
+          hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;
+            
+          CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON); 
+          
+          /* Change the CRYP state to ready */
+          hcryp->State = HAL_CRYP_STATE_READY;
+          /* Mark that the payload phase is over */
+          hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; 
+  
+          /* Call output data transfer complete callback */
+          HAL_CRYP_OutCpltCallback(hcryp);
+        }
+        else
+        {
+          payloadlength = (Size/16) * 16;          
+          
+          /* Store the ending transfer points */
+          hcryp->pCrypInBuffPtr = pInputData + payloadlength;
+          hcryp->pCrypOutBuffPtr = pOutputData + payloadlength;
+          hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */
+        
+          /* Set the input and output addresses and start DMA transfer */ 
+          /* (incomplete DMA transfer, will be wrapped up with data padding  
+             after completion of the one initiated here) */
+          CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr);                      
+        }
+      }
+      else
+      { 
+        hcryp->CrypInCount = 0;                          
+        inputaddr  = (uint32_t)pInputData;
+        outputaddr = (uint32_t)pOutputData;
+        
+        /* Set the input and output addresses and start DMA transfer */ 
+        CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);         
+      }  
+    }
+    /*==================================*/
+    /* GCM/GMAC/CCM or CMAC final phase */
+    /*==================================*/
+    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+    {
+      /* If coming from header phase (GMAC or CMAC case when applicable), 
+         wait for CCF flag to be raised */
+      if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE)
+      {   
+        if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  
+        { 
+          hcryp->State = HAL_CRYP_STATE_READY;        
+          __HAL_UNLOCK(hcryp);
+          return HAL_TIMEOUT;
+        }
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      }        
+      
+      tagaddr = (uint32_t)pOutputData;
+
+#if defined(AES_CR_NPBLB)   
+     /* By default, clear NPBLB field */
+      CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
+#endif        
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
+      
+      /* if the header and payload phases have been bypassed, AES must be enabled again */
+      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+      {
+        __HAL_CRYP_ENABLE(hcryp);  
+      }
+      
+      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+      {
+        headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
+        inputlength = Size * 8;  /* input length in bits */ 
+        /* Write the number of bits in the header on 64 bits followed by the number
+           of bits in the payload on 64 bits as well */
+#if !defined(AES_CR_NPBLB)          
+        if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+        {
+          hcryp->Instance->DINR = __RBIT((headerlength)>>32);
+          hcryp->Instance->DINR = __RBIT(headerlength);
+          hcryp->Instance->DINR = __RBIT((inputlength)>>32);
+          hcryp->Instance->DINR = __RBIT(inputlength);
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+        {
+          hcryp->Instance->DINR = __REV((headerlength)>>32);
+          hcryp->Instance->DINR = __REV(headerlength);
+          hcryp->Instance->DINR = __REV((inputlength)>>32);
+          hcryp->Instance->DINR = __REV(inputlength);
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+        {
+          hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
+          hcryp->Instance->DINR = __ROR(headerlength, 16);
+          hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
+          hcryp->Instance->DINR = __ROR(inputlength, 16);            
+        }
+        else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+        {
+          hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
+          hcryp->Instance->DINR = (uint32_t)(headerlength);
+          hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
+          hcryp->Instance->DINR = (uint32_t)(inputlength);
+        }
+#else
+        hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
+        hcryp->Instance->DINR = (uint32_t)(headerlength);
+        hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
+        hcryp->Instance->DINR = (uint32_t)(inputlength);
+#endif        
+      }
+#if !defined(AES_CR_NPBLB)           
+      else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+      {
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+        
+        inputaddr  = (uint32_t)pInputData;
+        /* Enter the last block made of a 128-bit value formatted
+           from the original B0 packet. */
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+        inputaddr+=4;
+        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+      }
+#endif      
+      
+      /* No DMA transfer is required at that point therefore, the software 
+         just waits for the CCF flag to be raised. */
+      if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  
+      { 
+          hcryp->State = HAL_CRYP_STATE_READY;        
+          __HAL_UNLOCK(hcryp);
+          return HAL_TIMEOUT;
+      }
+
+      /* Read the Auth TAG in the IN FIFO */
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+      tagaddr+=4;
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+      tagaddr+=4;
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+      tagaddr+=4;
+      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+      
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);            
+  
+      /* Mark that the final phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Disable the Peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+    }
+    /*=================================================*/
+    /* case incorrect hcryp->Init.GCMCMACPhase setting */
+    /*=================================================*/
+    else
+    {
+      hcryp->State = HAL_CRYP_STATE_ERROR;
+      __HAL_UNLOCK(hcryp); 
+      return HAL_ERROR;
+    }    
+  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions 
+ *  @brief   Extended processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+                    ##### AES extended suspension and resumption functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) save in memory the Initialization Vector, the Key registers, the Control register or
+          the Suspend registers when a process is suspended by a higher priority message
+      (+) write back in CRYP hardware block the saved values listed above when the suspended
+          lower priority message processing is resumed.     
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  In case of message processing suspension, read the Initialization Vector. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.    
+  * @param  Output: Pointer to the buffer containing the saved Initialization Vector.
+  * @note   This value has to be stored for reuse by writing the AES_IVRx registers
+  *         as soon as the interrupted processing has to be resumed.
+  *         Applicable to all chaining modes.    
+  * @note   AES must be disabled when reading or resetting the IV values.   
+  * @retval None
+  */
+void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
+{
+  uint32_t outputaddr = (uint32_t)Output;
+    
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0);
+}
+
+/**
+  * @brief  In case of message processing resumption, rewrite the Initialization
+  *         Vector in the AES_IVRx registers.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.      
+  * @param  Input: Pointer to the buffer containing the saved Initialization Vector to
+  *         write back in the CRYP hardware block. 
+  * @note   Applicable to all chaining modes.       
+  * @note   AES must be disabled when reading or resetting the IV values.     
+  * @retval None
+  */
+void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
+{
+  uint32_t ivaddr = (uint32_t)Input;
+  
+  hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
+}
+
+
+/**
+  * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension,  
+  *         read the Suspend Registers.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.  
+  * @param  Output: Pointer to the buffer containing the saved Suspend Registers.
+  * @note   These values have to be stored for reuse by writing back the AES_SUSPxR registers
+  *         as soon as the interrupted processing has to be resumed.       
+  * @retval None
+  */
+void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
+{
+  uint32_t outputaddr = (uint32_t)Output;
+  
+  /* In case of GCM payload phase encryption, check that suspension can be carried out */
+  if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT))
+  {
+    /* Ensure that Busy flag is reset */
+    if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)  
+    { 
+      hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR;
+      hcryp->State = HAL_CRYP_STATE_ERROR;
+              
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);  
+    
+      HAL_CRYP_ErrorCallback(hcryp);
+      return ;
+    }
+  } 
+    
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R);
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); 
+  outputaddr+=4;
+  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R);   
+}
+
+/**
+  * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Suspend
+  *         Registers in the AES_SUSPxR registers.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.    
+  * @param  Input: Pointer to the buffer containing the saved suspend registers to
+  *         write back in the CRYP hardware block. 
+  * @retval None
+  */
+void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
+{
+  uint32_t ivaddr = (uint32_t)Input;
+  
+  hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr));  
+}
+
+
+/**
+  * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, read the Key Registers.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.   
+  * @param  Output: Pointer to the buffer containing the saved Key Registers. 
+  * @param  KeySize: Indicates the key size (128 or 256 bits).
+  * @note   These values have to be stored for reuse by writing back the AES_KEYRx registers
+  *         as soon as the interrupted processing has to be resumed.           
+  * @retval None
+  */
+void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize)
+{
+  uint32_t keyaddr = (uint32_t)Output;
+  
+  if (KeySize == CRYP_KEYSIZE_256B)
+  {
+    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7);
+    keyaddr+=4;
+    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6);
+    keyaddr+=4;
+    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5);
+    keyaddr+=4;
+    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4);
+    keyaddr+=4;                 
+  }  
+  
+  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3);
+  keyaddr+=4;
+  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2);
+  keyaddr+=4;
+  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1);
+  keyaddr+=4;
+  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); 
+}
+
+/**
+  * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key
+  *         Registers in the AES_KEYRx registers.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.   
+  * @param  Input: Pointer to the buffer containing the saved key registers to
+  *         write back in the CRYP hardware block. 
+  * @param  KeySize: Indicates the key size (128 or 256 bits)     
+  * @retval None
+  */
+void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize)
+{  
+  uint32_t keyaddr = (uint32_t)Input;
+  
+  if (KeySize == CRYP_KEYSIZE_256B)
+  {
+    hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;      
+  }  
+  
+    hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));    
+}
+
+
+/**
+  * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, read the Control Register.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.   
+  * @param  Output: Pointer to the buffer containing the saved Control Register.
+  * @note   This values has to be stored for reuse by writing back the AES_CR register
+  *         as soon as the interrupted processing has to be resumed.          
+  * @retval None
+  */
+void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
+{
+  *(uint32_t*)(Output) = hcryp->Instance->CR;    
+}
+
+/**
+  * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Control
+  *         Registers in the AES_CR register.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.   
+  * @param  Input: Pointer to the buffer containing the saved Control Register to
+  *         write back in the CRYP hardware block.   
+  * @retval None
+  */
+void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
+{  
+  hcryp->Instance->CR = *(uint32_t*)(Input);
+  /* At the same time, set handle state back to READY to be able to resume the AES calculations 
+     without the processing APIs returning HAL_BUSY when called. */
+  hcryp->State        = HAL_CRYP_STATE_READY;
+}
+
+/**
+  * @brief  Request CRYP processing suspension when in polling or interruption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module. 
+  * @note   Set the handle field SuspendRequest to the appropriate value so that 
+  *         the on-going CRYP processing is suspended as soon as the required 
+  *         conditions are met.
+  * @note   It is advised not to suspend the CRYP processing when the DMA controller 
+  *         is managing the data transfer     
+  * @retval None
+  */
+void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp)  
+{
+  /* Set Handle Suspend Request field */
+  hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYPEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA CRYP Input Data process complete callback
+  *         for GCM, GMAC, CCM or CMAC chaining modes.
+  * @note   Specific setting of hcryp fields are required only
+  *         in the case of header phase where no output data DMA
+  *         transfer is on-going (only input data transfer is enabled
+  *         in such a case).      
+  * @param  hdma: DMA handle.
+  * @retval None
+  */
+static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma)  
+{
+  uint32_t difflength     = 0;
+  
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for input request  */
+  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+  if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+  { 
+  
+    if (hcryp->CrypInCount != 0)
+    {
+      /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
+      difflength = hcryp->CrypInCount;
+      hcryp->CrypInCount = 0;
+      
+      CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF);      
+    }
+    hcryp->State = HAL_CRYP_STATE_READY;   
+    /* Mark that the header phase is over */
+    hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+  }
+  /* CCF flag indicating header phase AES processing completion 
+     will be checked at the start of the next phase:
+     - payload phase (GCM or CCM when applicable)
+     - final phase (GMAC or CMAC).
+    This allows to avoid the Wait on Flag within the IRQ handling.  */
+  
+  /* Call input data transfer complete callback */
+  HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP Output Data process complete callback
+  *         for GCM, GMAC, CCM or CMAC chaining modes.
+  * @note   This callback is called only in the payload phase.  
+  * @param  hdma: DMA handle.
+  * @retval None
+  */
+static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+  uint32_t difflength     = 0;
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for output request */
+  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+
+  /* Clear CCF Flag */
+  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+  
+  /* Initiate additional transfer to wrap-up data feeding to the IP */
+  if (hcryp->CrypInCount != 0)
+  {
+    /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
+    difflength = hcryp->CrypInCount;
+    hcryp->CrypInCount = 0;
+    
+    CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); 
+  }  
+  
+  /* Change the CRYP state to ready */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  /* Mark that the payload phase is over */
+  hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; 
+  
+  /* Call output data transfer complete callback */
+  HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP communication error callback
+  *         for GCM, GMAC, CCM or CMAC chaining modes.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  hcryp->State= HAL_CRYP_STATE_ERROR;
+  hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
+  HAL_CRYP_ErrorCallback(hcryp);
+  /* Clear Error Flag */
+  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
+}
+
+
+
+/** 
+  * @brief  Handle CRYP block input/output data handling under interruption
+  *         for GCM, GMAC, CCM  or CMAC chaining modes.  
+  * @note   The function is called under interruption only, once
+  *         interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT().  
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t inputaddr   = 0x0;
+  uint32_t outputaddr  = 0x0; 
+  uint32_t index       = 0x0;
+  uint32_t addhoc_process = 0; 
+  uint32_t difflength     = 0;
+  uint32_t difflengthmod4 = 0;
+  uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};
+  uint32_t intermediate_data[4] = {0};        
+  
+  if(hcryp->State == HAL_CRYP_STATE_BUSY)
+  {
+    /*===========================*/
+    /* GCM/GMAC(/CCM) init phase */
+    /*===========================*/  
+    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+    {
+      /* Clear Computation Complete Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      /* Disable Computation Complete Flag and Errors Interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+    
+      /* Mark that the initialization phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
+          
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Call computation complete callback */
+      HAL_CRYPEx_ComputationCpltCallback(hcryp);
+      return HAL_OK;
+    }
+    /*========================================*/
+    /* GCM/GMAC (or CCM or CMAC) header phase */
+    /*========================================*/   
+    else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+    {
+      /* Check if all input header data have been entered */
+      if (hcryp->CrypInCount == 0)
+      {
+        /* Clear Computation Complete Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+        /* Disable Computation Complete Flag and Errors Interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+       /* Mark that the header phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+      
+       /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+      
+        /* Call computation complete callback */
+        HAL_CRYPEx_ComputationCpltCallback(hcryp);
+      
+        return HAL_OK;
+      }
+      /* If suspension flag has been raised, suspend processing */
+      else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+      {
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+       
+        /* reset SuspendRequest */
+        hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+        /* Disable Computation Complete Flag and Errors Interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+        /* Mark that the header phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+      
+       /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+      
+        return HAL_OK;
+      }      
+      else /* Carry on feeding input data to the CRYP hardware block */
+      {
+        /* Clear Computation Complete Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+        /* Get the last Input data address */
+        inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+      
+        /* Increment/decrement instance pointer/counter */
+        if (hcryp->CrypInCount < 16)
+        {
+          difflength = hcryp->CrypInCount;        
+          hcryp->CrypInCount = 0;
+          addhoc_process = 1;  
+          difflengthmod4 = difflength%4;              
+        }
+        else
+        {
+          hcryp->pCrypInBuffPtr += 16;
+          hcryp->CrypInCount -= 16;
+        }        
+        
+#if defined(AES_CR_NPBLB)    
+        if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)
+#else     
+        if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif         
+        { 
+          if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
+          {
+            /* All B blocks will have been entered after the next
+              four DINR writing, so point at header buffer for
+              the next iteration */
+            hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+          }
+        }           
+      
+        /* Write the Input block in the Data Input register */
+        if (addhoc_process == 0)
+        {         
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+        }
+        else
+        {
+          /* Header remainder has size less than 128 bits */ 
+          /* Enter complete words when possible */
+          for( ; index < (difflength/4); index ++)
+          {
+            /* Write the Input block in the Data Input register */
+            hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+            inputaddr+=4;
+          }
+          /* Enter incomplete word padded with zeroes if applicable 
+            (case of header length not a multiple of 32-bits) */
+          if (difflengthmod4 != 0)
+          {         
+            hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+          }         
+          /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
+          for(index=0; index < (4 - ((difflength+3)/4)); index ++)         
+          {
+            hcryp->Instance->DINR = 0;
+          }          
+        }
+      
+        return HAL_OK;      
+      }
+    }
+    /*=======================*/
+    /* GCM/CCM payload phase */
+    /*=======================*/    
+    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+    {
+      /* Get the last output data address */
+      outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+      
+     /* Specific handling to manage payload size less than 128 bits
+        when GCM (or CCM when applicable) encryption or decryption is selected.
+        Check here if the last block output data are read */
+#if defined(AES_CR_NPBLB)  
+      if ((hcryp->CrypOutCount < 16)                                && \
+          (hcryp->CrypOutCount > 0))
+#else    
+      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
+          (hcryp->CrypOutCount < 16)                                && \
+          (hcryp->CrypOutCount > 0))
+#endif          
+      {
+        addhoc_process = 1;
+        difflength = hcryp->CrypOutCount;
+        difflengthmod4 = difflength%4; 
+        hcryp->CrypOutCount = 0;   /* mark that no more output data will be needed */       
+        /* Retrieve intermediate data */
+        for(index=0; index < 4; index ++)
+        {
+          intermediate_data[index] = hcryp->Instance->DOUTR;                 
+        } 
+        /* Retrieve last words of cyphered data */
+        /* First, retrieve complete output words */
+        for(index=0; index < (difflength/4); index ++)
+        {
+          *(uint32_t*)(outputaddr) = intermediate_data[index];
+          outputaddr+=4; 
+        } 
+        /* Next, retrieve partial output word if applicable;
+           at the same time, start masking intermediate data 
+           with a mask of zeros of same size than the padding
+           applied to the last block of payload */ 
+        if (difflengthmod4 != 0)
+        {
+          intermediate_data[difflength/4] &= mask[difflengthmod4-1];
+          *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];            
+        }           
+   
+#if !defined(AES_CR_NPBLB)       
+        if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+        { 
+          /* Change again CHMOD configuration to GCM mode */
+          __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); 
+        
+          /* Select FINAL phase */
+          MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);  
+        
+          /* Before inserting the intermediate data, carry on masking operation
+             with a mask of zeros of same size than the padding applied to the last block of payload */
+          for(index=0; index < (4 - ((difflength+3)/4)); index ++)        
+          {
+            intermediate_data[(difflength+3)/4+index] = 0;
+          }  
+        
+          /* Insert intermediate data to trigger an additional DOUTR reading round */
+          /* Clear Computation Complete Flag before entering new block */
+          __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+          for(index=0; index < 4; index ++)
+          {
+            hcryp->Instance->DINR = intermediate_data[index];          
+          }
+        }
+        else
+#endif        
+        {
+          /* Payload phase is now over */
+          /* Clear Computation Complete Flag */
+          __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);        
+          /* Disable Computation Complete Flag and Errors Interrupts */
+          __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+          /* Change the CRYP state */
+          hcryp->State = HAL_CRYP_STATE_READY;
+          /* Mark that the payload phase is over */
+          hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+      
+          /* Process Unlocked */
+          __HAL_UNLOCK(hcryp);
+      
+          /* Call computation complete callback */
+          HAL_CRYPEx_ComputationCpltCallback(hcryp);
+        }
+        return HAL_OK;
+      }
+      else  
+      { 
+        if (hcryp->CrypOutCount != 0)
+        { 
+          /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ 
+          /* Retrieve the last block available from the CRYP hardware block:
+            read the output block from the Data Output Register */
+          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+          outputaddr+=4;
+          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+          outputaddr+=4;
+          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+          outputaddr+=4;
+          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+          
+          /* Increment/decrement instance pointer/counter */
+          hcryp->pCrypOutBuffPtr += 16;
+          hcryp->CrypOutCount -= 16;                    
+        }
+#if !defined(AES_CR_NPBLB)          
+        else
+        {          
+          /* Software work-around: additional DOUTR reading round to discard the data */
+          for(index=0; index < 4; index ++)
+          {
+            intermediate_data[index] = hcryp->Instance->DOUTR;                 
+          }          
+        }
+#endif         
+      }            
+      
+      /* Check if all output text has been retrieved */
+      if (hcryp->CrypOutCount == 0)
+      {
+        /* Clear Computation Complete Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);        
+        /* Disable Computation Complete Flag and Errors Interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+       /* Mark that the payload phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+      
+       /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+      
+        /* Call computation complete callback */
+        HAL_CRYPEx_ComputationCpltCallback(hcryp);
+      
+        return HAL_OK;
+      }
+      /* If suspension flag has been raised, suspend processing */
+      else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+      {     
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+       
+        /* reset SuspendRequest */
+        hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+        /* Disable Computation Complete Flag and Errors Interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+        /* Mark that the header phase is over */
+        hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+      
+       /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+      
+        return HAL_OK;
+      }            
+      else /* Output data are still expected, carry on feeding the CRYP
+               hardware block with input data */
+      {
+        /* Clear Computation Complete Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);          
+        /* Get the last Input data address */
+        inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+      
+        /* Usual input data feeding case */
+        if (hcryp->CrypInCount < 16)
+        {
+          difflength = (uint32_t) (hcryp->CrypInCount);
+          difflengthmod4 = difflength%4;
+          hcryp->CrypInCount = 0; 
+          
+#if defined(AES_CR_NPBLB)  
+          /* In case of GCM encryption or CCM decryption, specify the number of padding
+             bytes in last block of payload */
+               if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
+                    &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))   
+                ||  ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM)
+                    &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
+               {
+                 /* Set NPBLB field in writing the number of padding bytes 
+                    for the last block of payload */
+                 MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB);
+               }
+#else          
+          /* Software workaround applied to GCM encryption only */ 
+          if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+          {
+            /* Change the mode configured in CHMOD bits of CR register to select CTR mode */   
+            __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR);
+          }   
+#endif                   
+          
+          /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes 
+              to have a complete block of 128 bits */
+          for(index=0; index < (difflength/4); index ++)
+          {
+            /* Write the Input block in the Data Input register */
+            hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+            inputaddr+=4;
+          }
+          /* If required, manage input data size not multiple of 32 bits */
+          if (difflengthmod4 != 0)
+          {         
+            hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+          }         
+          /* Wrap-up in padding with zero-words if applicable */
+          for(index=0; index < (4 - ((difflength+3)/4)); index ++)        
+          {
+            hcryp->Instance->DINR = 0;
+          }                           
+                                    
+        }
+        else
+        {
+          hcryp->pCrypInBuffPtr += 16;
+          hcryp->CrypInCount -= 16;
+          
+          /* Write the Input block in the Data Input register */
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+          inputaddr+=4;
+          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);            
+        }            
+                  
+    
+        return HAL_OK;      
+      }
+    }
+    /*=======================================*/
+    /* GCM/GMAC (or CCM or CMAC) final phase */
+    /*=======================================*/  
+    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+    {
+      /* Clear Computation Complete Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);  
+            
+      /* Get the last output data address */
+      outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+      
+      /* Retrieve the last expected data from the CRYP hardware block:
+         read the output block from the Data Output Register */
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+      outputaddr+=4;
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+      outputaddr+=4;
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+      outputaddr+=4;
+      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+  
+      /* Disable Computation Complete Flag and Errors Interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Mark that the header phase is over */
+      hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+      
+      /* Disable the Peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+      /* Process Unlocked */
+       __HAL_UNLOCK(hcryp);
+      
+      /* Call computation complete callback */
+      HAL_CRYPEx_ComputationCpltCallback(hcryp);
+      
+      return HAL_OK;
+    }
+    else
+    {
+      /* Clear Computation Complete Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);       
+      hcryp->State = HAL_CRYP_STATE_ERROR; 
+      __HAL_UNLOCK(hcryp); 
+      return HAL_ERROR; 
+    }
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }  
+}
+    
+  
+  
+/** 
+  * @brief  Set the DMA configuration and start the DMA transfer
+  *         for GCM, GMAC, CCM  or CMAC chaining modes.   
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  inputaddr: Address of the Input buffer.
+  * @param  Size: Size of the Input buffer un bytes, must be a multiple of 16.
+  * @param  outputaddr: Address of the Output buffer, null pointer when no output DMA stream
+  *         has to be configured.  
+  * @retval None
+  */
+static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+
+  /* Set the input CRYP DMA transfer complete callback */
+  hcryp->hdmain->XferCpltCallback = CRYP_Authentication_DMAInCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmain->XferErrorCallback = CRYP_Authentication_DMAError;
+  
+  if (outputaddr != 0) 
+  { 
+    /* Set the output CRYP DMA transfer complete callback */
+    hcryp->hdmaout->XferCpltCallback = CRYP_Authentication_DMAOutCplt;
+    /* Set the DMA error callback */
+    hcryp->hdmaout->XferErrorCallback = CRYP_Authentication_DMAError;
+  }
+  
+  /* Enable the CRYP peripheral */
+  __HAL_CRYP_ENABLE(hcryp);
+  
+  /* Enable the DMA input stream */
+  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
+  
+  /* Enable the DMA input request */
+  SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+  
+  if (outputaddr != 0) 
+  {   
+    /* Enable the DMA output stream */
+    HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
+  
+    /* Enable the DMA output request */
+    SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+  }
+}  
+
+
+
+/**
+  * @brief  Write/read input/output data in polling mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Input: Pointer to the Input buffer.
+  * @param  Ilength: Length of the Input buffer in bytes, must be a multiple of 16.
+  * @param  Output: Pointer to the returned buffer.
+  * @param  Timeout: Specify Timeout value.  
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+  uint32_t index = 0;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  
+
+  for(index=0; (index < Ilength); index += 16)
+  {
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    
+    /* Wait for CCF flag to be raised */
+    if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  
+    { 
+      hcryp->State = HAL_CRYP_STATE_READY;        
+      __HAL_UNLOCK(hcryp);
+      return HAL_TIMEOUT;
+    }
+      
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+    
+    /* Read the Output block from the Data Output Register */
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4;
+    
+    /* If the suspension flag has been raised and if the processing is not about
+       to end, suspend processing */
+    if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength))
+    {
+      /* Reset SuspendRequest */
+      hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+      
+      /* Save current reading and writing locations of Input and Output buffers */
+      hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;
+      hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
+      /* Save the number of bytes that remain to be processed at this point */
+      hcryp->CrypInCount     =  Ilength - (index+16);
+      
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+      
+      return HAL_OK;
+    }
+    
+    
+  }
+  /* Return function status */
+  return HAL_OK;
+
+}
+
+
+
+
+
+/**
+  * @brief  Read derivative key in polling mode when CRYP hardware block is set
+  *         in key derivation operating mode (mode 2).
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Output: Pointer to the returned buffer.
+  * @param  Timeout: Specify Timeout value.  
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout)
+{
+  uint32_t outputaddr = (uint32_t)Output;
+  
+  /* Wait for CCF flag to be raised */  
+  if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  
+  { 
+    hcryp->State = HAL_CRYP_STATE_READY;        
+    __HAL_UNLOCK(hcryp);
+    return HAL_TIMEOUT;
+  }
+  /* Clear CCF Flag */
+  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+  
+    /* Read the derivative key from the AES_KEYRx registers */
+  if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+  {   
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
+    outputaddr+=4;
+  }
+  
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
+
+    
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the DMA configuration and start the DMA transfer.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  inputaddr: Address of the Input buffer.
+  * @param  Size: Size of the Input buffer in bytes, must be a multiple of 16.
+  * @param  outputaddr: Address of the Output buffer.
+  * @retval None
+  */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+  
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+  /* Enable the DMA input stream */
+  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
+
+  /* Enable the DMA output stream */
+  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
+
+  /* Enable In and Out DMA requests */
+  SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
+  
+  /* Enable the CRYP peripheral */
+  __HAL_CRYP_ENABLE(hcryp);
+}
+
+
+/**
+  * @brief  Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.      
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+  {    
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((HAL_GetTick() - tickstart ) > Timeout)
+      {    
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Wait for Busy Flag to be reset during a GCM payload encryption process suspension. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.         
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY))
+  {    
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((HAL_GetTick() - tickstart ) > Timeout)
+      {    
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK; 
+}
+
+
+/**
+  * @brief  DMA CRYP Input Data process complete callback.
+  * @param  hdma: DMA handle.
+  * @retval None
+  */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for input request  */
+  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+  
+  /* Call input data transfer complete callback */
+  HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP Output Data process complete callback.
+  * @param  hdma: DMA handle.
+  * @retval None
+  */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{  
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for output request */
+  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+
+  /* Clear CCF Flag */
+  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+  
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
+  
+  /* Change the CRYP state to ready */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Call output data transfer complete callback */
+  HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP communication error callback. 
+  * @param  hdma: DMA handle.
+  * @retval None
+  */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  hcryp->State= HAL_CRYP_STATE_ERROR;
+  hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;  
+  HAL_CRYP_ErrorCallback(hcryp);
+  /* Clear Error Flag */
+  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
+}
+
+/**
+  * @brief  Last header or payload block padding when size is not a multiple of 128 bits. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.         
+  * @param  difflength: size remainder after having fed all complete 128-bit blocks.
+  * @param  polling: specifies whether or not polling on CCF must be done after having
+  *                  entered a complete block.     
+  * @retval None
+  */
+static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)
+{
+  uint32_t index          = 0;
+  uint32_t difflengthmod4 = difflength%4;
+  uint32_t inputaddr      = (uint32_t)hcryp->pCrypInBuffPtr; 
+  uint32_t outputaddr     = (uint32_t)hcryp->pCrypOutBuffPtr;   
+  uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};  
+  uint32_t intermediate_data[4] = {0};
+  
+#if defined(AES_CR_NPBLB)  
+  /* In case of GCM encryption or CCM decryption, specify the number of padding
+     bytes in last block of payload */
+     if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
+     {
+       if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
+            &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))   
+        ||  ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM)
+            &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
+       {
+         /* Set NPBLB field in writing the number of padding bytes 
+            for the last block of payload */
+         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB);
+       }
+     }
+#else
+  /* Software workaround applied to GCM encryption only */
+  if ((hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) &&		
+      (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT))
+  {
+    /* Change the mode configured in CHMOD bits of CR register to select CTR mode */   
+    __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR);
+  }  
+#endif  
+  
+  /* Wrap-up entering header or payload data */
+  /* Enter complete words when possible */
+  for(index=0; index < (difflength/4); index ++)
+  {
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+  }
+  /* Enter incomplete word padded with zeroes if applicable 
+    (case of header length not a multiple of 32-bits) */
+  if (difflengthmod4 != 0)
+  {         
+    hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+  }         
+  /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
+  for(index=0; index < (4 - ((difflength+3)/4)); index ++)         
+  {
+    hcryp->Instance->DINR = 0;
+  } 
+
+  if (polling == CRYP_POLLING_ON)
+  {
+    if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  
+    { 
+        hcryp->State = HAL_CRYP_STATE_READY;        
+        __HAL_UNLOCK(hcryp);
+       HAL_CRYP_ErrorCallback(hcryp);
+      } 
+
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+  }
+
+  /* if payload */
+  if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+  {
+       
+    /* Retrieve intermediate data */
+    for(index=0; index < 4; index ++)
+    {
+      intermediate_data[index] = hcryp->Instance->DOUTR;                 
+    }     
+    /* Retrieve last words of cyphered data */
+    /* First, retrieve complete output words */
+    for(index=0; index < (difflength/4); index ++)
+    {
+      *(uint32_t*)(outputaddr) = intermediate_data[index];
+      outputaddr+=4; 
+    } 
+    /* Next, retrieve partial output word if applicable;
+       at the same time, start masking intermediate data 
+       with a mask of zeros of same size than the padding
+       applied to the last block of payload */ 
+    if (difflengthmod4 != 0)
+    {
+      intermediate_data[difflength/4] &= mask[difflengthmod4-1];
+      *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];            
+    }           
+    
+    
+#if !defined(AES_CR_NPBLB)      
+    /* Software workaround applied to GCM encryption only,
+       applicable for AES IP v2 version (where NPBLB is not defined) */           
+    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+    {
+      /* Change again CHMOD configuration to GCM mode */
+      __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC);  
+      
+      /* Select FINAL phase */
+      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
+      
+      /* Before inserting the intermediate data, carry on masking operation
+         with a mask of zeros of same size than the padding applied to the last block of payload */
+      for(index=0; index < (4 - ((difflength+3)/4)); index ++)        
+      {
+        intermediate_data[(difflength+3)/4+index] = 0;
+      }   
+      /* Insert intermediate data */
+      for(index=0; index < 4; index ++)
+      {
+        hcryp->Instance->DINR = intermediate_data[index];          
+      } 
+      
+      /*  Wait for completion, and read data on DOUT. This data is to discard. */ 
+      if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  
+      { 
+        hcryp->State = HAL_CRYP_STATE_READY;        
+        __HAL_UNLOCK(hcryp);
+        HAL_CRYP_ErrorCallback(hcryp);
+      } 
+         
+      /* Read data to discard */ 
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+      for(index=0; index < 4; index ++)
+      {
+        intermediate_data[index] = hcryp->Instance->DOUTR;        
+      }  
+
+    } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */
+#endif  /* !defined(AES_CR_NPBLB) */     
+  }   /* if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) */
+
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */  
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h
new file mode 100755
index 0000000..d82497a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h
@@ -0,0 +1,148 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRYPEx HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRYP_EX_H
+#define __STM32L4xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
+   
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYPEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRYPEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* CallBack functions  ********************************************************/
+void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+  * @{
+  */
+
+/* AES encryption/decryption processing functions  ****************************/
+HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+
+/* AES encryption/decryption/authentication processing functions  *************/
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup CRYPEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* AES suspension/resumption functions  ***************************************/
+void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
+void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
+void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */  
+  
+
+/**
+  * @}
+  */ 
+  
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
+  * @{
+  */
+HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+  
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */     
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c
new file mode 100755
index 0000000..fe5e15f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c
@@ -0,0 +1,1317 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dac.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DAC HAL module driver.
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions      
+  *     
+  *
+  @verbatim      
+  ==============================================================================
+                      ##### DAC Peripheral features #####
+  ==============================================================================
+    [..]        
+      *** DAC Channels ***
+      ====================  
+    [..]  
+    STM32L4 devices integrate one or two 12-bit Digital Analog Converters 
+    (i.e. one or 2 channel(s))
+    1 channel : STM32L451xx STM32L452xx STM32L462xx
+    2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx
+                STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx 
+
+    When 2 channels are available, the 2 converters (i.e. channel1 & channel2)
+    can be used independently or simultaneously (dual mode):
+      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip 
+          peripherals (ex. OPAMPs, comparators).
+      (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output 
+          or connected to on-chip peripherals (ex. OPAMPs, comparators).
+      
+      *** DAC Triggers ***
+      ====================
+    [..]
+    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
+    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. 
+    [..] 
+    Digital to Analog conversion can be triggered by:
+      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+          The used pin (GPIOx_PIN_9) must be configured in input mode.
+  
+      (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 
+          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
+  
+      (#) Software using DAC_TRIGGER_SOFTWARE
+  
+      *** DAC Buffer mode feature ***
+      =============================== 
+      [..] 
+      Each DAC channel integrates an output buffer that can be used to 
+      reduce the output impedance, and to drive external loads directly
+      without having to add an external operational amplifier.
+      To enable, the output buffer use  
+      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+      [..]           
+      (@) Refer to the device datasheet for more details about output 
+          impedance value with and without output buffer.
+
+      *** DAC connect feature ***
+      =============================== 
+      [..] 
+      Each DAC channel can be connected internally. 
+      To connect, use
+      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
+                                               
+      *** GPIO configurations guidelines ***
+      =====================
+      [..] 
+      When a DAC channel is used (ex channel1 on PA4) and the other is not 
+      (ex channel2 on PA5 is configured in Analog and disabled).
+      Channel1 may disturb channel2 as coupling effect.
+      Note that there is no coupling on channel2 as soon as channel2 is turned on.
+      Coupling on adjacent channel could be avoided as follows:
+      when unused PA5 is configured as INPUT PULL-UP or DOWN. 
+      PA5 is configured in ANALOG just before it is turned on.     
+                                               
+      *** DAC Sample and Hold feature ***
+      ========================
+      [..] 
+      For each converter, 2 modes are supported: normal mode and 
+      "sample and hold" mode (i.e. low power mode).
+      In the sample and hold mode, the DAC core converts data, then holds the 
+      converted voltage on a capacitor. When not converting, the DAC cores and 
+      buffer are completely turned  off between samples and the DAC output is 
+      tri-stated, therefore  reducing the overall power consumption. A new 
+      stabilization period is needed before each new conversion.
+
+      The sample and hold allow setting internal or external voltage @
+      low power consumption cost (output value can be at any given rate either 
+      by CPU or DMA).
+
+      The Sample and hold block and registers uses either LSI & run in 
+      several power modes: run mode, sleep mode, low power run, low power sleep 
+      mode & stop1 mode.
+          
+      Low power stop1 mode allows only static conversion.
+          
+      To enable Sample and Hold mode 
+      Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
+      RCC_LSI_ON parameters.
+
+      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
+         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
+           DAC_HoldTime & DAC_RefreshTime;
+    
+
+
+       *** DAC calibration feature ***
+       =================================== 
+      [..] 
+       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.  
+       (++) Calibration aims at correcting some offset of output buffer.
+       (++) The DAC uses either factory calibration settings OR user defined 
+           calibration (trimming) settings (i.e. trimming mode).
+       (++) The user defined settings can be figured out using self calibration 
+           handled by HAL_DACEx_SelfCalibrate.
+       (++) HAL_DACEx_SelfCalibrate:
+       (+++) Runs automatically the calibration.
+       (+++) Enables the user trimming mode
+       (+++) Updates a structure with trimming values with fresh calibration 
+            results. 
+            The user may store the calibration results for larger 
+            (ex monitoring the trimming as a function of temperature 
+            for instance)
+
+       *** DAC wave generation feature ***
+       =================================== 
+       [..]     
+       Both DAC channels can be used to generate
+         (#) Noise wave 
+         (#) Triangle wave
+            
+       *** DAC data format ***
+       =======================
+       [..]   
+       The DAC data format can be:
+         (#) 8-bit right alignment using DAC_ALIGN_8B_R
+         (#) 12-bit left alignment using DAC_ALIGN_12B_L
+         (#) 12-bit right alignment using DAC_ALIGN_12B_R
+  
+       *** DAC data value to voltage correspondence ***  
+       ================================================ 
+       [..] 
+       The analog output voltage on each DAC channel pin is determined
+       by the following equation:
+       [..]
+       DAC_OUTx = VREF+ * DOR / 4095
+       (+) with  DOR is the Data Output Register
+       [..]
+          VEF+ is the input voltage reference (refer to the device datasheet)
+       [..]
+        e.g. To set DAC_OUT1 to 0.7V, use
+       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+  
+       *** DMA requests ***
+       =====================
+       [..]
+       A DMA1 request can be generated when an external trigger (but not a software trigger) 
+       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). 
+       DMA requests are mapped as following:          
+      (#) DAC channel1: mapped either on
+      (++) DMA1 request 6 channel3 
+      (++) or DMA2 request channel4 which must be already configured
+      (#) DAC channel2 (whenever present): mapped either on
+      (++) DMA1 request 5 channel4 
+      (++) or DMA2 request 3 channel5 which must be already configured 
+     [..]
+    (@) For Dual mode and specific signal (Triangle and noise) generation please 
+        refer to Extended Features Driver description        
+      
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]          
+      (+) DAC APB clock must be enabled to get write access to DAC
+          registers using HAL_DAC_Init()
+      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
+
+     *** Calibration mode IO operation ***
+     ======================================
+     [..]    
+       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
+       (+) Run the calibration using HAL_DACEx_SelfCalibrate() 
+       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the DAC peripheral using HAL_DAC_Start() 
+       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
+       (+) Stop the DAC peripheral using HAL_DAC_Stop()
+       
+     *** DMA mode IO operation ***    
+     ==============================
+     [..]    
+       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
+           of data to be transferred at each end of conversion
+       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()  
+           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()  
+           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
+            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()  
+           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
+           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
+       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+                    
+     *** DAC HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DAC HAL driver.
+       
+      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+      
+     [..]
+      (@) You can refer to the DAC HAL driver header file for more useful macros  
+   
+ @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+  /** @defgroup DAC DAC
+  * @brief DAC driver modules  
+  * @{
+  */ 
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DAC_Private_Constants DAC Private Constants
+  * @{
+  */
+#define TIMEOUT_DAC_CALIBCONFIG        ((uint32_t)1)         /* 1   ms        */
+#define HFSEL_ENABLE_THRESHOLD_80MHZ   ((uint32_t)80000000)  /* 80 mHz        */
+/**
+  * @}
+  */ 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DAC_Private_Functions DAC Private Functions
+  * @{
+  */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
+/**
+  * @}
+  */
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DAC. 
+      (+) De-initialize the DAC. 
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct and initialize the associated handle.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{ 
+  /* Check DAC handle */
+  if(hdac == NULL)
+  {
+     return HAL_ERROR;
+  }
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+  
+  if(hdac->State == HAL_DAC_STATE_RESET)
+  {  
+    /* Allocate lock resource and initialize it */
+    hdac->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_DAC_MspInit(hdac);
+  }
+  
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+  
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitialize the DAC peripheral registers to their default reset values.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+  /* Check DAC handle */
+  if(hdac == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_DAC_MspDeInit(hdac);
+
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the DAC MSP.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the DAC MSP.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.  
+  * @retval None
+  */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### IO operation functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+                     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Enable the Peripheral */
+  __HAL_DAC_ENABLE(hdac, Channel);
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+  if(Channel == DAC_CHANNEL_1)
+  {
+    /* Check if software trigger enabled */
+    if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
+    {
+      /* Enable the selected DAC software conversion */
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+    }
+  }
+  else
+  {
+    /* Check if software trigger enabled */
+    if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
+    {
+      /* Enable the selected DAC software conversion*/
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+    }
+  }
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */    
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 
+        
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+  /* Check if software trigger enabled */
+  if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
+  {
+    /* Enable the selected DAC software conversion */
+    SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+  }
+#endif /* STM32L451xx STM32L452xx STM32L462xx */
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+    
+  /* Return function status */
+  return HAL_OK;
+}
+  
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  * @param  pData: The destination peripheral Buffer address.
+  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment: Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Set the DMA transfer complete callback for channel1 */
+  hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+  
+  /* Set the DMA half transfer complete callback for channel1 */
+  hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+     
+  /* Set the DMA error callback for channel1 */
+  hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+  
+  /* Enable the selected DAC channel1 DMA request */
+  SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+  
+  /* Case of use of channel 1 */
+  switch(Alignment)
+  {
+    case DAC_ALIGN_12B_R:
+      /* Get DHR12R1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+      break;
+    case DAC_ALIGN_12B_L:
+      /* Get DHR12L1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+      break;
+    case DAC_ALIGN_8B_R:
+      /* Get DHR8R1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+      break;
+    default:
+      break;
+  }  
+  
+  /* Enable the DMA channel */
+  /* Enable the DAC DMA underrun interrupt */
+  __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+    
+  /* Enable the DMA channel */
+  HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Enable the Peripheral */
+  __HAL_DAC_ENABLE(hdac, Channel);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+#endif /* STM32L451xx STM32L452xx STM32L462xx */   
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+      
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  pData: The destination peripheral Buffer address.
+  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment: Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  if(Channel == DAC_CHANNEL_1)
+  {
+    /* Set the DMA transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+    
+    /* Set the DMA half transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+       
+    /* Set the DMA error callback for channel1 */
+    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+    
+    /* Enable the selected DAC channel1 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+    
+    /* Case of use of channel 1 */
+    switch(Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+        break;
+      case DAC_ALIGN_8B_R:
+        /* Get DHR8R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+        break;
+      default:
+        break;
+    }
+  }
+  else
+  {
+    /* Set the DMA transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+    
+    /* Set the DMA half transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+       
+    /* Set the DMA error callback for channel2 */
+    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+    
+    /* Enable the selected DAC channel2 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+    
+    /* Case of use of channel 2 */
+    switch(Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+        break;
+      case DAC_ALIGN_8B_R:
+        /* Get DHR8R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+        break;
+      default:
+        break;
+    }
+  }
+  
+  /* Enable the DMA channel */
+  if(Channel == DAC_CHANNEL_1)
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+    
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  } 
+  else
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+    
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Enable the Peripheral */
+  __HAL_DAC_ENABLE(hdac, Channel);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+   HAL_StatusTypeDef status = HAL_OK;
+    
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Disable the selected DAC channel DMA request */
+    hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+    
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, Channel);
+  
+  /* Disable the DMA channel */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+  /* Channel1 is used */
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Disable the DMA channel */
+    status = HAL_DMA_Abort(hdac->DMA_Handle1);
+    
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+  }
+  else /* Channel2 is used for */
+  {
+    /* Disable the DMA channel */
+    status = HAL_DMA_Abort(hdac->DMA_Handle2);
+    
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+  }
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#if defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx)
+  /* Disable the DMA channel */
+  status = HAL_DMA_Abort(hdac->DMA_Handle1);
+    
+  /* Disable the DAC DMA underrun interrupt */
+  __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+#endif /* STM32L451xx STM32L452xx STM32L462xx */  
+  
+  /* Check if DMA Channel effectively disabled */
+  if (status != HAL_OK)
+  {
+    /* Update DAC state machine to error */
+    hdac->State = HAL_DAC_STATE_ERROR;
+  }
+  else
+  {
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_READY;
+  }
+  
+  /* Return function status */
+  return status;
+}
+
+/* DAC channel 2 is available on top of DAC channel 1 in */
+/* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+/* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+/**
+  * @brief  Handles DAC interrupt request
+  *         This function uses the interruption of DMA
+  *         underrun.  
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+  if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+  { 
+    /* Check underrun flag of DAC channel 1 */
+    if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+    {
+      /* Change DAC state to error state */
+      hdac->State = HAL_DAC_STATE_ERROR;
+      
+      /* Set DAC error code to chanel1 DMA underrun error */
+      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+      
+      /* Clear the underrun flag */
+      __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+      
+      /* Disable the selected DAC channel1 DMA request */
+      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+      
+      /* Error callback */ 
+      HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+    }
+  }
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+  if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+  {
+    /* Check underrun flag of DAC channel 1 */
+    if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+    {
+      /* Change DAC state to error state */
+      hdac->State = HAL_DAC_STATE_ERROR;
+      
+      /* Set DAC error code to channel2 DMA underrun error */
+      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
+      
+      /* Clear the underrun flag */
+      __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+      
+      /* Disable the selected DAC channel1 DMA request */
+      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+      
+      /* Error callback */ 
+      HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+    }
+  }
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
+  * @param  Alignment: Specifies the data alignment.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)hdac->Instance; 
+  if(Channel == DAC_CHANNEL_1)
+  {
+    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+  }
+  else
+  {
+    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+  }
+
+  /* Set the DAC channel selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode for Channel1 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel1.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for channel1.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels. 
+      (+) Set the specified data holding register value for DAC channel.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Returns the DAC channel data output register value */
+#if defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx)
+  return hdac->Instance->DOR1;
+#endif /* STM32L451xx STM32L452xx STM32L462xx */   
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+  if(Channel == DAC_CHANNEL_1)
+  {
+    return hdac->Instance->DOR1;
+  }
+  else
+  {
+    return hdac->Instance->DOR2;
+  }
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+}
+
+/**
+  * @brief  Configures the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig: DAC configuration structure.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  uint32_t tickstart = 0;
+  
+  /* Check the DAC parameters */
+  
+  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+  assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
+  assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
+  if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
+  {
+    assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));               
+  }
+  assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
+  if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
+  {
+    assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
+    assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
+    assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); 
+  }
+  assert_param(IS_DAC_CHANNEL(Channel));
+ 
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
+  /* Sample on old configuration */ 
+  {
+    /* SampleTime */
+    if (Channel == DAC_CHANNEL_1)
+    {
+      /* Get timeout */
+      tickstart = HAL_GetTick();
+      
+      /* SHSR1 can be written when BWST1  equals RESET */
+      while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
+      {
+        /* Check for the Timeout */
+        if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
+        {
+          /* Update error code */
+          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+
+          /* Change the DMA state */
+          hdac->State = HAL_DAC_STATE_TIMEOUT;
+
+          return HAL_TIMEOUT;
+        }
+      }
+      HAL_Delay(1);
+      hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+    }
+#if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx) 
+    else /* Channel 2 */
+    {
+      /* SHSR2 can be written when BWST2 equals RESET */
+
+      while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
+      {
+        /* Check for the Timeout */
+        if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
+        {
+          /* Update error code */
+          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+
+          /* Change the DMA state */
+          hdac->State = HAL_DAC_STATE_TIMEOUT;
+
+          return HAL_TIMEOUT;
+        }
+      }
+      HAL_Delay(1);
+      hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+    }
+#endif /* STM32L451xx STM32L452xx STM32L462xx */   
+    
+    /* HoldTime */
+    MODIFY_REG (hdac->Instance->SHHR, DAC_SHHR_THOLD1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel);
+    /* RefreshTime */
+    MODIFY_REG (hdac->Instance->SHRR, DAC_SHRR_TREFRESH1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel);
+  }
+    
+  if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
+  /* USER TRIMMING */
+  {
+  /* Get the DAC CCR value */
+  tmpreg1 = hdac->Instance->CCR;
+  /* Clear trimming value */
+  tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
+  /* Configure for the selected trimming offset */
+  tmpreg2 = sConfig->DAC_TrimmingValue;
+  /* Calculate CCR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << Channel;
+  /* Write to DAC CCR */
+  hdac->Instance->CCR = tmpreg1;
+  }
+  /* else factory trimming is used (factory setting are available at reset)*/
+  /* SW Nothing has nothing to do */
+  
+  /* Get the DAC MCR value */
+  tmpreg1 = hdac->Instance->MCR;
+  /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
+  tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); 
+  /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
+  tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
+  /* Calculate MCR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << Channel;
+  /* Write to DAC MCR */
+  hdac->Instance->MCR = tmpreg1;
+  
+  /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
+  CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
+  
+  /* Get the DAC CR value */
+  tmpreg1 = hdac->Instance->CR;
+  /* Clear TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); 
+  /* Configure for the selected DAC channel: trigger */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  tmpreg2 = (sConfig->DAC_Trigger);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << Channel;
+
+  /* Write to DAC CR */
+  hdac->Instance->CR = tmpreg1;
+      
+  /* Disable wave generation */
+  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+ *  @brief   Peripheral State and Errors functions 
+ *
+@verbatim   
+  ==============================================================================
+            ##### Peripheral State and Errors functions #####
+  ==============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DAC state.
+      (+) Check the DAC Errors.
+        
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  return the DAC handle state
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL state
+  */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+  /* Return DAC handle state */
+  return hdac->State;
+}
+
+
+/**
+  * @brief  Return the DAC error code
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval DAC Error Code
+  */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+  return hdac->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DAC_ConvCpltCallbackCh1(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
+{
+    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+    
+  HAL_DAC_ErrorCallbackCh1(hdac); 
+    
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h
new file mode 100755
index 0000000..8ea78f2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h
@@ -0,0 +1,514 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dac.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DAC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DAC_H
+#define __STM32L4xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
+ 
+}HAL_DAC_StateTypeDef;
+ 
+/** 
+  * @brief  DAC handle Structure definition  
+  */ 
+typedef struct
+{
+  DAC_TypeDef                 *Instance;     /*!< Register base address             */
+  
+  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
+
+  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
+  
+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
+  
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
+  
+  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
+  
+}DAC_HandleTypeDef;
+
+/** 
+  * @brief   DAC Configuration sample and hold Channel structure definition  
+  */ 
+typedef struct
+{
+  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */  
+
+  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */    
+  
+  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */  
+}
+DAC_SampleAndHoldConfTypeDef;
+
+/** 
+  * @brief   DAC Configuration regular Channel structure definition  
+  */ 
+typedef struct
+{
+  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
+                                              This parameter can be a value of @ref DAC_SampleAndHold */
+  
+  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
+                                              This parameter can be a value of @ref DAC_trigger_selection */
+  
+  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref DAC_output_buffer */
+
+  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
+  
+  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode 
+                                              This parameter must be a value of @ref DAC_UserTrimming 
+                                              DAC_UserTrimming is either factory or user trimming */
+                                        
+  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value 
+                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */ 
+      
+}DAC_ChannelConfTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+  * @{
+  */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+  * @{
+  */
+#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
+#define  HAL_DAC_ERROR_TIMEOUT           0x08    /*!< Timeout error                     */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+  * @{
+  */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+#endif     /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
+      
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+#endif     /* STM32L451xx STM32L452xx STM32L462xx                         */
+      
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+#endif     /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/
+
+
+
+/**
+  * @}
+  */   
+
+/** @defgroup DAC_output_buffer DAC output buffer
+  * @{
+  */
+#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_MCR_MODE1_1)
+
+/**
+  * @}
+  */
+    
+/** @defgroup DAC_Channel_selection DAC Channel selection
+  * @{
+  */
+#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */    
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment DAC data alignment
+  * @{
+  */
+#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+  * @{
+  */ 
+#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_IT_definition  DAC IT definition
+  * @{
+  */ 
+#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
+  * @{
+  */
+#define DAC_CHIPCONNECT_DISABLE  ((uint32_t)0x00000000)
+#define DAC_CHIPCONNECT_ENABLE     ((uint32_t)DAC_MCR_MODE1_0)
+
+/**
+  * @}
+  */
+
+  /** @defgroup DAC_UserTrimming DAC User Trimming
+  * @{
+  */
+
+#define DAC_TRIMMING_FACTORY        ((uint32_t)0x00000000)           /*!< Factory trimming */
+#define DAC_TRIMMING_USER           ((uint32_t)0x00000001)           /*!< User trimming */
+   
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_SampleAndHold DAC power mode
+  * @{
+  */
+#define DAC_SAMPLEANDHOLD_DISABLE     ((uint32_t)0x00000000)
+#define DAC_SAMPLEANDHOLD_ENABLE      ((uint32_t)DAC_MCR_MODE1_2)
+
+/**
+  * @}
+  */
+      
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @brief Reset DAC handle state.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @retval None
+  */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __DAC_Channel__: specifies the DAC channel
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel.
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __DAC_Channel__: specifies the DAC channel.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
+ 
+/** @brief Set DHR12R1 alignment.
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+/** @brief  Set DHR12R2 alignment.
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+/** @brief  Set DHR12RD alignment.
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt.
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt.
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief  Check whether the specified DAC interrupt source is enabled or not.
+  * @param __HANDLE__: DAC handle
+  * @param __INTERRUPT__: DAC interrupt source to check
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief  Get the selected DAC's flag status.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the DAC flag to get.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @retval None
+  */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the DAC's flag.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the DAC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @retval None
+  */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+  * @}
+  */ 
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+  * @{
+  */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+                                ((CHANNEL) == DAC_CHANNEL_2))
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */    
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#if defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx) 
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+#endif /* STM32L451xx STM32L452xx STM32L462xx */   
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x0000000FF)
+
+/**
+  * @}
+  */
+  
+/* Include DAC HAL Extended module */
+#include "stm32l4xx_hal_dac_ex.h"   
+
+/* Exported functions --------------------------------------------------------*/  
+
+/** @addtogroup DAC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+  * @{
+  */  
+/* Initialization and de-initialization functions *****************************/ 
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */    
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+  * @{
+  */ 
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+  * @{
+  */     
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif 
+  
+
+#endif /*__STM32L4xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c
new file mode 100755
index 0000000..49abcae
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c
@@ -0,0 +1,644 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dac_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DAC HAL module driver.
+  *          This file provides firmware functions to manage the extended 
+  *          functionalities of the DAC peripheral.  
+  *     
+  *
+  @verbatim      
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]          
+      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
+      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
+      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
+      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting 
+          after reset, user setting if HAL_DACEx_SetUserTrimming have been used 
+          at least one time after reset).
+
+ @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DACEx DACEx
+  * @brief DAC Extended HAL module driver
+  * @{
+  */ 
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+  
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+  * @{
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
+ *  @brief    Extended IO operation functions 
+ *
+@verbatim   
+  ==============================================================================
+                 ##### Extended features functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+      (+) Get result of dual mode conversion.
+                     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Select max triangle amplitude. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Enable the triangle wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC. 
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
+  *          This parameter can be one of the following values: 
+  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
+  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{   
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+     
+  /* Enable the noise wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+
+/**
+  * @brief  Set the specified data holding register value for dual DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  Alignment: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{  
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (Alignment == DAC_ALIGN_8B_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)hdac->Instance;
+  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2. 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+   */
+}
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+/**
+  * @brief  Run the self calibration of one DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig: DAC channel configuration structure.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
+  * @retval HAL status
+  * @note   Calibration runs about 7 ms.
+  */
+
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{ 
+  HAL_StatusTypeDef status = HAL_OK;
+   
+  __IO uint32_t tmp = 0;
+  uint32_t trimmingvalue = 0;
+  uint32_t delta;
+  
+  /* store/restore channel configuration structure purpose */
+  uint32_t oldmodeconfiguration = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+    
+ /* Check the DAC handle allocation */
+ /* Check if DAC running */
+  if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdac);
+    
+    /* Store configuration */
+    oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
+    
+    /* Disable the selected DAC channel */
+    CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
+    
+    /* Set mode in MCR  for calibration */
+    MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
+    
+    /* Set DAC Channel1 DHR register to the middle value */
+    tmp = (uint32_t)hdac->Instance; 
+    
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+    if(Channel == DAC_CHANNEL_1)
+    {
+      tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
+    }
+    else
+    {
+      tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
+    }
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 
+    tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
+#endif /* STM32L451xx STM32L452xx STM32L462xx */
+    *(__IO uint32_t *) tmp = 0x0800;
+    
+    /* Enable the selected DAC channel calibration */
+    /* i.e. set DAC_CR_CENx bit */
+    SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
+    
+    /* Init trimming counter */    
+    /* Medium value */
+    trimmingvalue = 16; 
+    delta = 8;
+    while (delta != 0) 
+    {
+      /* Set candidate trimming */
+      MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
+      
+      /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ 
+      /* i.e. minimum time needed between two calibration steps */
+      HAL_Delay(1);
+      
+      if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == (DAC_SR_CAL_FLAG1<<Channel))
+      { 
+        /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
+        trimmingvalue -= delta;
+      }
+      else
+      {
+        /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
+        trimmingvalue += delta;
+      }                   
+      delta >>= 1;
+    }
+    
+    /* Still need to check if right calibration is current value or one step below */
+    /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
+    /* Set candidate trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
+    
+    /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ 
+    /* i.e. minimum time needed between two calibration steps */
+    HAL_Delay(1);
+    
+    if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
+    { 
+      /* OPAMP_CSR_OUTCAL is actually one value more */
+      trimmingvalue++;
+      /* Set right trimming */
+      MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
+    }
+    
+    /* Disable the selected DAC channel calibration */
+    /* i.e. clear DAC_CR_CENx bit */
+    CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
+    
+    sConfig->DAC_TrimmingValue = trimmingvalue;
+    sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+    
+    /* Restore configuration */
+    MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hdac);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set the trimming mode and trimming value (user trimming mode applied).
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig: DAC configuration structure updated with new DAC trimming value.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  NewTrimmingValue: DAC new trimming value
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
+{ 
+  HAL_StatusTypeDef status = HAL_OK;
+     
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
+  
+ /* Check the DAC handle allocation */
+  if(hdac == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdac);
+    
+    /* Set new trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
+    
+    /* Update trimming mode */
+    sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+    sConfig->DAC_TrimmingValue = NewTrimmingValue;
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hdac);
+  }
+  return status;
+}
+
+/**
+  * @brief  Return the DAC trimming value.
+  * @param  hdac : DAC handle
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval Trimming value : range: 0->31
+  *         
+ */
+
+uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  uint32_t trimmingvalue = 0;
+  
+  /* Check the DAC handle allocation */
+  /* And not in Reset state */
+  if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET))
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_DAC_CHANNEL(Channel));
+
+    /* Retrieve trimming  */
+    trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel);
+  }  
+  return trimmingvalue;
+}
+
+/**
+  * @}
+  */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)   
+
+/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Extended Peripheral Control functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels. 
+      (+) Set the specified data holding register value for DAC channel.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+  uint32_t tmp = 0;
+  
+  tmp |= hdac->Instance->DOR1;
+
+  tmp |= hdac->Instance->DOR2 << 16;
+  
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+
+/**
+  * @}
+  */
+
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+/**
+  * @}
+  */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)   
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx private functions
+ *  @brief    Extended private functions
+   * @{
+  */
+
+/**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+    
+  HAL_DACEx_ErrorCallbackCh2(hdac); 
+    
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @}
+  */
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h
new file mode 100755
index 0000000..4b0cbb1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h
@@ -0,0 +1,280 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dac_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DAC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DAC_EX_H
+#define __STM32L4xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+           
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DACEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+   
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+  * @{
+  */ 
+    
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
+  * @{
+  */
+#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+  * @}
+  */       
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+  * @{
+  */   
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif     /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif     /* STM32L451xx STM32L452xx STM32L462xx                         */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))      
+#endif     /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
+
+#define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x0000003FF)
+
+#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
+                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
+
+
+#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+
+#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
+
+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
+                                     ((TRIMMING) == DAC_TRIMMING_USER))
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/  
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+ * @{
+ */    
+/* IO operation functions *****************************************************/
+  
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group3
+  * @{
+  */ 
+/* Peripheral Control functions ***********************************************/
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */    
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
+   
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+
+/** @addtogroup DACEx_Private_Functions
+  * @{
+  */
+
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif   
+
+#endif /*__STM32L4xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c
new file mode 100755
index 0000000..f62ffe4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c
@@ -0,0 +1,1271 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dcmi.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DCMI HAL module driver
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Digital Camera Interface (DCMI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State and Error functions  
+  *           
+  @verbatim      
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The sequence below describes how to use this driver to capture an image
+      from a camera module connected to the DCMI Interface.
+      This sequence does not take into account the configuration of the
+      camera module, which should be made before configuring and enabling
+      the DCMI.
+
+    (#) Program the required configuration through the following parameters:
+        horizontal and vertical polarity, pixel clock polarity, capture rate,
+        synchronization mode, frame delimiter codes, data width, byte and line
+        selection using HAL_DCMI_Init() function.
+        
+    (#) Optionally select JPEG mode; in that case, only the polarity
+        and the capture mode parameters need to be set.        
+        
+    (#) Capture mode can be either snapshot or continuous mode.
+    
+    (#) Configure the DMA_Handle to transfer data from DCMI DR
+        register to the destination memory buffer.
+    
+    -@- In snapshot mode, the interface transfers a single frame through DMA. In
+       continuous mode, the DMA must be set in circular mode to ensure a continuous
+       flow of images data samples.                  
+
+    (#) Program the transfer configuration through the following parameters:
+        DCMI mode, destination memory buffer address and data length then 
+        enable capture using HAL_DCMI_Start_DMA() function.
+        
+    (#) Whether in continuous or snapshot mode, data length parameter must be
+        equal to the frame size.
+        
+    (#) When the frame size is unknown beforehand (e.g. JPEG case), data length must 
+        be large enough to ensure the capture of a frame.  
+        
+    (#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535), 
+        (++) resort to a user-defined work buffer and associate it to the DCMI handle with
+             the function HAL_DCMIEx_WorkBuffer_Associate(), 
+        (++) the DMA must be configured in circular mode, either for snapshot or continuous
+             capture mode, 
+        (++) during capture, the driver copies the image data samples from DCMI DR register
+             to the work buffer,              
+        (++) at each DMA half (respectively complete) transfer interrupt, the first 
+             (resp. second) half of the work buffer is copied to the final destination thru 
+             a second DMA channel.
+        (++) Parameters of this second DMA channel are contained in the memory to memory DMA 
+             handle "DMAM2M_Handle", itself field of the DCMI handle structure. 
+        (++) This memory to memory transfer has length half that of the work buffer and is 
+             carried out in normal mode (not in circular mode).                         
+
+    (#) Optionally, configure and enable the CROP feature to select a 
+        rectangular window from the received image using HAL_DCMI_ConfigCrop() 
+        and HAL_DCMI_EnableCrop() functions. Use HAL_DCMI_DisableCrop() to
+        disable this feature.
+
+    (#) The capture can be stopped with HAL_DCMI_Stop() function.
+
+    (#) To control the DCMI state, use the function HAL_DCMI_GetState().
+    
+    (#) To read the DCMI error code, use the function HAL_DCMI_GetError().  
+    
+    [..]
+    (@) When the frame size is less than the maximum DMA transfer length (i.e. 65535)
+        and when in snapshot mode, user must make sure the FRAME interrupt is disabled.
+        This allows to avoid corner cases where the FRAME interrupt might be triggered
+        before the DMA transfer completion interrupt. In this specific configuration,
+        the driver checks the FRAME capture flag after the DMA transfer end and calls 
+        HAL_DCMI_FrameEventCallback() if the flag is set.           
+
+     *** DCMI HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DCMI HAL driver.
+       
+      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
+      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
+      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
+      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
+      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
+      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
+      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred
+          and that the interruption is enabled at the same time.
+      
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+/** @defgroup DCMI DCMI
+  * @brief DCMI HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Stop_TimeOut DCMI Stop TimeOut
+  * @{
+  */    
+#define DCMI_TIMEOUT_STOP    ((uint32_t)1000)  /*!< 1s  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Shifts DCMI Shifts 
+  * @{
+  */
+#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count       */
+#define DCMI_POSITION_CWSTRT_VST   (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST)   /*!< Required left shift to set crop window vertical start line count */
+
+#define DCMI_POSITION_ESCR_LSC     (uint32_t)POSITION_VAL(DCMI_ESCR_LSC)     /*!< Required left shift to set line start delimiter */
+#define DCMI_POSITION_ESCR_LEC     (uint32_t)POSITION_VAL(DCMI_ESCR_LEC)     /*!< Required left shift to set line end delimiter   */
+#define DCMI_POSITION_ESCR_FEC     (uint32_t)POSITION_VAL(DCMI_ESCR_FEC)     /*!< Required left shift to set frame end delimiter  */
+
+#define DCMI_POSITION_ESUR_LSU     (uint32_t)POSITION_VAL(DCMI_ESUR_LSU)     /*!< Required left shift to set line start delimiter unmask */
+#define DCMI_POSITION_ESUR_LEU     (uint32_t)POSITION_VAL(DCMI_ESUR_LEU)     /*!< Required left shift to set line end delimiter unmask   */
+#define DCMI_POSITION_ESUR_FEU     (uint32_t)POSITION_VAL(DCMI_ESUR_FEU)     /*!< Required left shift to set frame end delimiter unmask  */
+/**
+  * @}
+  */
+  
+#define NPRIME   16  
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint32_t PrimeArray[NPRIME] = { 1,  2,  3,  5, 
+                                7, 11, 13, 17, 
+                               19, 23, 29, 31, 
+                               37, 41, 43, 47};
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+  * @{
+  */
+static void       DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void       DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma);
+static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
+static uint32_t   DCMI_TransferSize(uint32_t InputSize);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
+  * @{
+  */
+
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DCMI
+      (+) De-initialize the DCMI 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initialize the DCMI according to the specified
+  *         parameters in the DCMI_InitTypeDef and create the associated handle.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @note   By default, all interruptions are enabled (line end, frame end, overrun, 
+  *         VSYNC and embedded synchronization error interrupts).                 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{     
+  /* Check the DCMI peripheral state */
+  if(hdcmi == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check function parameters */
+  assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+  assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));  
+  assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+  assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+  assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+  assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+  assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+  assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+
+  assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
+  assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
+  assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
+  assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
+                
+  if(hdcmi->State == HAL_DCMI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hdcmi->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_DCMI_MspInit(hdcmi);
+  } 
+  
+  /* Change the DCMI state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY; 
+  
+  /* Disable DCMI IP before setting the configuration register */
+  __HAL_DCMI_DISABLE(hdcmi); 
+  
+  if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B)
+  {
+    /* Byte select mode must be programmed to the reset value if the extended mode 
+      is not set to 8-bit data capture on every pixel clock */
+    hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL;      
+  }  
+
+  /* Set DCMI parameters */
+  hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |\
+                           DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |\
+                           DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
+                           DCMI_CR_LSM | DCMI_CR_OELS);
+
+  hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
+                                     hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  |\
+                                     hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
+                                     hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
+                                     hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
+                                     hdcmi->Init.LineSelectStart);
+
+  if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+  {
+    hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SynchroCode.FrameStartCode)    |\
+                             ((uint32_t)hdcmi->Init.SynchroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\
+                             ((uint32_t)hdcmi->Init.SynchroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\
+                             ((uint32_t)hdcmi->Init.SynchroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
+  }
+
+  /* By default, enable all interrupts. The user may disable the unwanted ones
+     in resorting to __HAL_DCMI_DISABLE_IT() macro before invoking HAL_DCMI_Start_DMA(). 
+     Enabled interruptions are 
+     - end of line
+     - end of frame
+     - data reception overrun
+     - frame synchronization signal VSYNC
+     - synchronization error */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME|DCMI_IT_OVR|DCMI_IT_ERR|DCMI_IT_VSYNC|DCMI_IT_LINE);
+
+  /* Update error code */
+  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+  
+  /* Initialize the DCMI state*/
+  hdcmi->State  = HAL_DCMI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initialize the DCMI peripheral, reset control registers to 
+  *         their default values.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Before aborting any DCMI transfer, check
+     first whether or not DCMI clock is enabled */
+  if (__HAL_RCC_DCMI_IS_CLK_ENABLED())
+  {
+     if (HAL_DCMI_Stop(hdcmi) != HAL_OK)
+     {
+        /* Issue when stopping DCMI IP */       
+        return HAL_ERROR;
+     }
+  }
+  
+  /* DeInit the DCMI low level hardware */
+  HAL_DCMI_MspDeInit(hdcmi);
+  
+  /* Reset DCMI control register */
+  hdcmi->Instance->CR = 0;    
+
+  /* Update error code */
+  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+  /* Initialize the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the DCMI MSP.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DCMI_MspInit() callback can be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  De-initialize the DCMI MSP.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DCMI_MspDeInit() callback can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions 
+ *  @brief   IO operation functions  
+ *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure destination address and data length, 
+          enable DCMI DMA request and DCMI capture.
+      (+) Stop DCMI capture.
+      (+) Handle DCMI interrupt request.
+      
+    [..]  A set of callbacks is provided:
+        (+) HAL_DCMI_ErrorCallback()
+        (+) HAL_DCMI_LineEventCallback()
+        (+) HAL_DCMI_VsyncEventCallback()
+        (+) HAL_DCMI_FrameEventCallback()
+    
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable DCMI capture in DMA mode. 
+  * @param  hdcmi:     Pointer to a DCMI_HandleTypeDef structure that contains
+  *                    the configuration information for DCMI.
+  * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.
+  * @param  pData:     The destination memory buffer address.
+  * @param  Length:    The length of capture to be transferred (in 32-bit words).
+  * @note  In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length),
+  *        user must beforehand associate a work buffer to the DCMI handle thru the API
+  *        HAL_DCMIEx_WorkBuffer_Associate(). Then, HAL_DCMI_Start_DMA()
+  *        initiates a circular DMA transfer from DCMI DR to the work buffer and each
+  *        half and complete transfer interrupt triggers a copy from the work buffer to
+  *        the final destination pData thru a second DMA channel.     
+  * @note  Following HAL_DCMI_Init() call, all interruptions are enabled (line end, 
+  *        frame end, overrun, VSYNC and embedded synchronization error interrupts).
+  *        User can disable unwanted interrupts thru __HAL_DCMI_DISABLE_IT() macro
+  *        before invoking HAL_DCMI_Start_DMA(). 
+  * @note  For length less than 0xFFFF (DMA maximum transfer length) and in snapshot mode, 
+  *        frame interrupt is disabled before DMA transfer. FRAME capture flag is checked
+  *        in DCMI_DMAXferCplt callback at the end of the DMA transfer. If flag is set,     
+  *        HAL_DCMI_FrameEventCallback() API is called.              
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
+{
+  uint32_t circular_copy_length = 0; 
+    
+  /* Check capture parameter */
+  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+  
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+  
+  /* Configure the DCMI Mode and enable the DCMI IP at the same time */
+  MODIFY_REG(hdcmi->Instance->CR, (DCMI_CR_CM|DCMI_CR_ENABLE), (DCMI_Mode|DCMI_CR_ENABLE));
+
+  /* Set the DMA conversion complete callback */
+  hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
+
+  /* Set the DMA error callback */
+  hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
+
+  if(Length <= 0xFFFF) 
+  {
+    hdcmi->XferCount = 0; /* Mark as direct transfer from DCMI_DR register to final destination buffer */
+
+    /* Enable the DMA channel */
+    if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK)
+    {
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+      
+      /* Set state back to Ready */
+      hdcmi->State = HAL_DCMI_STATE_READY;
+        
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+          
+       return HAL_ERROR;
+    }    
+  }
+  else /* Capture length is longer than DMA maximum transfer size */
+  {  
+     /* Set DMA in circular mode */
+    hdcmi->DMA_Handle->Init.Mode = DMA_CIRCULAR;
+         
+    /* Set the DMA half transfer complete callback */
+    hdcmi->DMA_Handle->XferHalfCpltCallback = DCMI_DMAHalfXferCplt;
+    
+    /* Initialize transfer parameters */
+    hdcmi->XferSize = Length;  /* Store the complete transfer length in DCMI handle */
+    hdcmi->pBuffPtr = pData;   /* Final destination buffer pointer */
+    
+    circular_copy_length = DCMI_TransferSize(Length);
+
+    /* Check if issue in intermediate length computation */
+    if (circular_copy_length == 0) 
+    {
+      /* Set state back to Ready */
+      hdcmi->State = HAL_DCMI_STATE_READY;
+            
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+          
+       return HAL_ERROR;    
+    } 
+    
+    /* Store the number of half - intermediate buffer copies needed */
+    hdcmi->XferCount = 2 * ((Length / circular_copy_length) - 1);  
+    /* Store the half-buffer copy length */
+    hdcmi->HalfCopyLength = circular_copy_length / 2;    
+    
+    /* DCMI DR samples in circular mode will be copied 
+       at the end of the final buffer. 
+       Now compute the circular buffer start address. */
+    /* Start by pointing at the final buffer */ 
+    hdcmi->pCircularBuffer = pData;
+    /* Update pCircularBuffer in "moving" at the end of the final
+       buffer, don't forger to convert in bytes to compute exact address */    
+   hdcmi->pCircularBuffer +=  4 * (((Length / circular_copy_length) - 1) * circular_copy_length); 
+    
+    /* Initiate the circular DMA transfer from DCMI IP to final buffer end */  
+    if ( HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)hdcmi->pCircularBuffer, circular_copy_length) != HAL_OK)
+    {      
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+      
+      /* Set state back to Ready */
+      hdcmi->State = HAL_DCMI_STATE_READY;
+            
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+          
+       return HAL_ERROR;
+    }    
+  }
+
+  /* Enable Capture */
+  SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE);  
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdcmi);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable DCMI capture in DMA mode.  
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI. 
+  * @retval HAL status     
+  */
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
+{
+  uint32_t tickstart = 0;
+
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Disable Capture */
+  CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE);    
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DCMI capture is effectively disabled */
+  while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
+  {
+    if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP)
+    {      
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+      
+      /* Change DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_READY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);      
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Disable the DMA */
+  HAL_DMA_Abort(hdcmi->DMA_Handle);
+  
+  /* Disable DCMI IP */
+  __HAL_DCMI_DISABLE(hdcmi);
+
+  /* Change DCMI state */
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend DCMI capture.  
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI. 
+  * @retval HAL status     
+  */
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
+{
+  uint32_t tickstart = 0;
+
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  if(hdcmi->State == HAL_DCMI_STATE_BUSY)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
+
+    /* Disable Capture */
+    CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE);    
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Check if the DCMI capture is effectively disabled */
+    while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
+    {
+      if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP)
+      {      
+        /* Update error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+        
+        /* Change DCMI state */
+        hdcmi->State = HAL_DCMI_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdcmi);      
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume DCMI capture.  
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI. 
+  * @retval HAL status     
+  */
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+    /* Enable Capture */  
+    SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle DCMI interrupt request.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for the DCMI.
+  * @retval None
+  */
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
+{ 
+  uint32_t misflags = READ_REG(hdcmi->Instance->MISR);
+ 
+  /* Synchronization error interrupt management *******************************/
+  if ((misflags & DCMI_MIS_ERR_MIS) != RESET)  
+  {
+    /* Clear the Synchronization error flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
+
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
+  }
+  
+  /* Overflow interrupt management ********************************************/
+  if ((misflags & DCMI_MIS_OVR_MIS) != RESET)    
+  {
+    /* Clear the Overflow flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
+
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;    
+  }
+  
+  if (hdcmi->ErrorCode != HAL_DCMI_ERROR_NONE)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_READY;    
+
+    /* Set the overflow callback */
+    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
+    
+    /* Abort the DMA Transfer */
+    HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
+
+    /* Error Callback */
+    HAL_DCMI_ErrorCallback(hdcmi);    
+  }
+  
+  /* Line Interrupt management ************************************************/
+  if ((misflags & DCMI_MIS_LINE_MIS) != RESET)  
+  {
+    /* Clear the Line interrupt flag */  
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
+
+    /* Line interrupt Callback */
+    HAL_DCMI_LineEventCallback(hdcmi);
+  }
+  
+  /* VSYNC interrupt management ***********************************************/
+  if ((misflags & DCMI_MIS_VSYNC_MIS) != RESET)    
+  {
+    /* Clear the VSYNC flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
+
+    /* VSYNC Callback */
+    HAL_DCMI_VsyncEventCallback(hdcmi);
+  }
+  
+  /* End of Frame interrupt management ****************************************/
+  if ((misflags & DCMI_MIS_FRAME_MIS) != RESET)      
+  {
+    /* Disable the Line interrupt when using snapshot mode */
+    if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+    {
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE|DCMI_IT_VSYNC|DCMI_IT_ERR|DCMI_IT_OVR);
+      /* Change the DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_READY;       
+    }
+
+    /* Clear the End of Frame flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
+
+    /* End of Frame Callback */
+    HAL_DCMI_FrameEventCallback(hdcmi);
+  }
+}
+
+/**
+  * @brief  Error DCMI callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DCMI_ErrorCallback() callback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Line Event callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+  
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DCMI_LineEventCallback() callback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  VSYNC Event callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DCMI_VsyncEventCallback() callback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Frame Event callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+ 
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DCMI_FrameEventCallback() callback can be implemented in the user file.
+   */
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================  
+[..]  This section provides functions allowing to:
+      (+) Configure the crop feature.
+      (+) Enable/Disable the crop feature.
+			(+) Configure the synchronization delimiters unmasks.
+			(+) Enable/Disable user-specified DCMI interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DCMI crop window coordinates.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @param  X0:    DCMI window crop window X offset (number of pixels clocks to count before the capture). 
+  * @param  Y0:    DCMI window crop window Y offset (image capture starts with this line number, previous
+  *                line data are ignored).
+  * @param  XSize: DCMI crop window horizontal size (in number of pixels per line).  
+  * @param  YSize: DCMI crop window vertical size (in lines count).  
+  * @note For all the parameters, the actual value is the input data + 1 (e.g. YSize = 0x0 means 1 line, 
+  *       YSize = 0x1 means 2 lines, ...)    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
+{
+  /* Check the parameters */
+  assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
+  assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
+  
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Configure CROP */
+  MODIFY_REG(hdcmi->Instance->CWSIZER, (DCMI_CWSIZE_VLINE|DCMI_CWSIZE_CAPCNT), (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE))); 
+  MODIFY_REG(hdcmi->Instance->CWSTRTR, (DCMI_CWSTRT_VST|DCMI_CWSTRT_HOFFCNT), (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST)));   
+
+  /* Initialize the DCMI state*/
+  hdcmi->State  = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the crop feature.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Disable DCMI Crop feature */
+  CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CROP);
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;   
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Enable the crop feature.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Enable DCMI Crop feature */
+  SET_BIT(hdcmi->Instance->CR, DCMI_CR_CROP);  
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Set embedded synchronization delimiters unmasks.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @param  SyncUnmask: pointer to a DCMI_SyncUnmaskTypeDef structure that contains
+  *                the embedded synchronization delimiters unmasks.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Write DCMI embedded synchronization unmask register */
+    hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) |\
+                             ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_POSITION_ESUR_LSU)|\
+                             ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_POSITION_ESUR_LEU)|\
+                             ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_POSITION_ESUR_FEU));
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;  
+}
+
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
+ *  @brief    Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DCMI state.
+      (+) Get the specific DCMI error flag.  
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Return the DCMI state.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL state
+  */
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)  
+{
+  return hdcmi->State;
+}
+
+/**
+* @brief  Return the DCMI error code.
+* @param  hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
+  *               the configuration information for DCMI.
+* @retval DCMI Error Code
+*/
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
+{
+  return hdcmi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+  
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Functions DCMI Private Functions
+  * @{
+  */
+  
+  /**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @note When the size of the frame being captured by the DCMI peripheral is 
+  *       larger than 0xFFFF (DMA maximum transfer length), this API initiates 
+  *       another DMA transfer to copy the second half of the work buffer 
+  *       associated to the DCMI handle to the final destination buffer.                     
+  * @retval None
+  */
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  uint32_t loop_length       = 0;     /* transfer length  */
+  uint32_t * tmpBuffer_Dest  = NULL;
+  uint32_t * tmpBuffer_Orig  = NULL;  
+ 
+  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+
+  if(hdcmi->XferCount != 0)
+  {
+    /* Manage second half buffer copy in case of big transfer */  
+    
+    /* Decrement half-copies counter */
+    hdcmi->XferCount--;       
+    
+    /* Point at DCMI final destination */
+    tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr;  
+    
+    /* Point at DCMI circular buffer mid-location */
+    tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer;           
+    tmpBuffer_Orig +=  hdcmi->HalfCopyLength; 
+    
+    /* copy half the buffer size */
+    loop_length = hdcmi->HalfCopyLength;
+    
+    /* Save next entry to write at next half DMA transfer interruption */
+    hdcmi->pBuffPtr += (uint32_t) loop_length*4;
+    hdcmi->XferSize -= hdcmi->HalfCopyLength;    
+    
+    /* Data copy from work buffer to final destination buffer */
+    /* Enable the DMA Channel */
+    if (HAL_DMA_Start_IT(hdcmi->DMAM2M_Handle, (uint32_t) tmpBuffer_Orig, (uint32_t) tmpBuffer_Dest, loop_length) != HAL_OK)
+    {
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+            
+      /* Change DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_READY;    
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+
+      /* Error Callback */
+      HAL_DCMI_ErrorCallback(hdcmi);    
+    }        
+  }
+  else
+  {
+    /* if End of frame IT is disabled */
+    if((hdcmi->Instance->IER & DCMI_IT_FRAME) == RESET)
+    {
+      /* If End of Frame flag is set */
+      if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
+      {
+        /* Clear the End of Frame flag */
+        __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
+              
+        /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+        if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+        { 
+          /* Disable the Vsync, Error and Overrun interrupts */
+          __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+          
+          hdcmi->State = HAL_DCMI_STATE_READY;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdcmi);          
+        }
+    
+        /* FRAME Callback */
+        HAL_DCMI_FrameEventCallback(hdcmi);
+      }    
+    }
+  }
+}
+
+
+  /**
+  * @brief  DMA Half Transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @note When the size of the frame being captured by the DCMI peripheral is 
+  *       larger than 0xFFFF (DMA maximum transfer length), this API initiates 
+  *       another DMA transfer to copy the first half of the work buffer 
+  *       associated to the DCMI handle to the final destination buffer.   
+  * @retval None
+  */
+static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma)
+{
+  uint32_t loop_length       = 0;     /* transfer length  */
+  uint32_t * tmpBuffer_Dest  = NULL;
+  uint32_t * tmpBuffer_Orig  = NULL;  
+  
+  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  if(hdcmi->XferCount != 0)
+  {
+    /* Manage first half buffer copy in case of big transfer */ 
+    
+    /* Decrement half-copies counter */
+    hdcmi->XferCount--;  
+    
+    /* Point at DCMI final destination */
+    tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr;  
+    
+    /* Point at DCMI circular buffer start */
+    tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer;           
+    
+    /* copy half the buffer size */
+    loop_length = hdcmi->HalfCopyLength;
+    
+    /* Save next entry to write at next DMA transfer interruption */
+    hdcmi->pBuffPtr += (uint32_t) loop_length*4;
+    hdcmi->XferSize -= hdcmi->HalfCopyLength;    
+
+    /* Data copy from work buffer to final destination buffer */
+    /* Enable the DMA Channel */
+    if (HAL_DMA_Start_IT(hdcmi->DMAM2M_Handle, (uint32_t) tmpBuffer_Orig, (uint32_t) tmpBuffer_Dest, loop_length) != HAL_OK)
+    {
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+            
+      /* Change DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_READY;    
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+
+      /* Error Callback */
+      HAL_DCMI_ErrorCallback(hdcmi);    
+    }        
+  }
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
+{
+    DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 
+    
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+    
+    /* Change DCMI state */        
+    hdcmi->State = HAL_DCMI_STATE_READY;
+
+    /* Error Callback */
+    HAL_DCMI_ErrorCallback(hdcmi);
+}
+
+/**
+  * @brief Sub-buffers transfer size computation.
+  * @note In the case of a frame size larger than the maximum DMA transfer length (0xFFFF),
+  *       the tranfer from DCMI DR register to the final output buffer is carried out by a sequence
+  *       of intermediate sub-copies to temporary buffers of size less than 0xFFFF.
+  *       To optimize the number of DMA transfers, the API computes the temporary buffer
+  *       size so that the latter is an even number less than 0xFFFF, that divides the final 
+  *       buffer size and is as high as possible. The API implements a sub-optimum solution for 
+  *       complexity's sake.                 
+  * @note InputSize MUST be even.  
+  * @param  InputSize: full buffer size (in 32-bit words)
+  * @retval Transfer size (in 32-bit words)
+  */
+static uint32_t DCMI_TransferSize(uint32_t InputSize)
+{ 
+  uint32_t j = 1;
+  uint32_t temp = InputSize;
+  uint32_t aPrime[NPRIME] = {0};
+  uint32_t output = 2; /* Want a result which is an even number */
+
+    
+  /* Develop InputSize in product of prime numbers */
+
+  while (j < NPRIME)
+  {
+    if (temp < PrimeArray[j])
+    {
+      break;
+    }
+    while ((temp % PrimeArray[j]) == 0)
+    {
+      aPrime[j]++; 
+      temp /= PrimeArray[j];   
+    }
+    j++;
+  } 
+  
+  /*  Search for the biggest even divisor less or equal to 0xFFFE = 65534 */
+  aPrime[1] -= 1; /* output is initialized to 2, so don't count dividor 2 twice */
+
+   /*  The algorithm below yields a sub-optimal solution
+       but in an acceptable time.  */
+    j =  NPRIME-1;
+  while ((j > 0) &&  (output <= 0xFFFE))
+  { 
+    while (aPrime[j] >0)
+    {
+      if (output * PrimeArray[j] > 0xFFFE)
+      {
+        break;
+      }
+      else
+      {
+        output *= PrimeArray[j]; 
+        aPrime[j]--;
+      }
+    }
+    j--;
+  }
+   
+  
+ 
+  return output;
+}
+
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
+#endif /* HAL_DCMI_MODULE_ENABLED */
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h
new file mode 100755
index 0000000..7243fc8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h
@@ -0,0 +1,656 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dcmi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DCMI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DCMI_H
+#define __STM32L4xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DCMI DCMI
+  * @brief DCMI HAL module driver
+  * @{
+  */  
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Types DCMI Exported Types
+  * @{
+  */
+/** 
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */ 
+typedef struct
+{
+  uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+  uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
+  uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
+  uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
+}DCMI_CodesInitTypeDef;
+
+
+/** 
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */ 
+typedef struct
+{
+  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */
+  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */
+  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */
+}DCMI_SyncUnmaskTypeDef;
+
+
+/** 
+  * @brief   DCMI Init structure definition
+  */  
+typedef struct
+{
+  uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+                                             This parameter can be a value of @ref DCMI_Synchronization_Mode. */
+
+  uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
+                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity.       */
+
+  uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity.       */
+
+  uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity.       */
+
+  uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+                                             This parameter can be a value of @ref DCMI_Capture_Rate.         */
+
+  uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode.   */
+
+  DCMI_CodesInitTypeDef SynchroCode;    /*!< Specifies the frame start delimiter codes.                       */
+
+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.                                
+                                             This parameter can be a value of @ref DCMI_JPEG_Mode.            */    
+
+  uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface. 
+                                            This parameter can be a value of @ref DCMI_Byte_Select_Mode.      */
+                                            
+  uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd.
+                                            This parameter can be a value of @ref DCMI_Byte_Select_Start.     */
+
+  uint32_t LineSelectMode;              /*!< Specifies the data line to be captured by the interface. 
+                                            This parameter can be a value of @ref DCMI_Line_Select_Mode.      */
+                                            
+  uint32_t LineSelectStart;             /*!< Specifies if the data line to be captured by the interface is even or odd.
+                                            This parameter can be a value of @ref DCMI_Line_Select_Start.     */
+                                                                                       
+}DCMI_InitTypeDef;
+
+
+/** 
+  * @brief  HAL DCMI State structures definition
+  */ 
+typedef enum
+{
+  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
+  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
+  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
+  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
+  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
+  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */    
+}HAL_DCMI_StateTypeDef;
+
+
+/** 
+  * @brief  DCMI handle Structure definition
+  */
+typedef struct
+{
+  DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
+
+  DCMI_InitTypeDef              Init;                /*!< DCMI init parameters         */
+
+  HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
+
+  __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
+
+  __IO uint32_t                 XferCount;           /*!< DMA transfers counter        */
+
+  __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
+
+  uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
+
+  DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to DMA handler       */
+
+  DMA_HandleTypeDef             *DMAM2M_Handle;      /*!< Pointer to DMA handler for memory to memory copy
+                                                        (case picture size >  maximum DMA transfer length) */     
+
+  __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
+  
+  uint32_t                      pCircularBuffer;     /*!< Pointer to intermediate copy buffer 
+                                                        (case picture size >  maximum DMA transfer length) */    
+  
+  uint32_t                      HalfCopyLength;      /*!< Intermediate copies length
+                                                        (case picture size >  maximum DMA transfer length) */      
+
+}DCMI_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Error_Code DCMI Error Code
+  * @{
+  */
+#define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
+#define HAL_DCMI_ERROR_OVR       ((uint32_t)0x00000001)    /*!< Overrun error         */
+#define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002)    /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
+#define HAL_DCMI_ERROR_DMA       ((uint32_t)0x00000040)    /*!< DMA error             */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
+  * @{
+  */ 
+#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000)  /*!< The received data are transferred continuously 
+                                                                    into the destination memory through the DMA             */
+#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of 
+                                                                    frame and then transfers a single frame through the DMA */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
+  * @{
+  */ 
+#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000)   /*!< Hardware synchronization data capture (frame/line start/stop)
+                                                                   is synchronized with the HSYNC/VSYNC signals                  */
+#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with 
+                                                                   synchronization codes embedded in the data flow               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_PIXCK_Polarity DCMI Pixel Clock Polarity
+  * @{
+  */
+#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000)      /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
+
+/**
+  * @}
+  */
+ 
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
+  * @{
+  */
+#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Vertical synchronization active Low  */
+#define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
+  * @{
+  */ 
+#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Horizontal synchronization active Low  */
+#define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_JPEG_Mode DCMI JPEG Mode
+  * @{
+  */
+#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000)    /*!< JPEG mode disabled  */
+#define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< JPEG mode enabled   */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
+  * @{
+  */
+#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000)      /*!< All frames are captured        */
+#define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
+  * @{
+  */
+#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000)                       /*!< Interface captures 8-bit data on every pixel clock  */
+#define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
+  * @{
+  */
+#define DCMI_BSM_ALL                 ((uint32_t)0x00000000) /*!< Interface captures all received data */
+#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
+#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
+#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
+  * @{
+  */ 
+#define DCMI_OEBS_ODD               ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */
+#define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
+  * @{
+  */
+#define DCMI_LSM_ALL                 ((uint32_t)0x00000000) /*!< Interface captures all received lines */
+#define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
+  * @{
+  */ 
+#define DCMI_OELS_ODD               ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */
+#define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DCMI_interrupt_sources  DCMI Interrupt Sources
+  * @{
+  */
+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
+#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Flags DCMI Flags
+  * @{
+  */
+
+/** 
+  * @brief   DCMI SR register
+  */ 
+#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */
+#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
+#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */
+/** 
+  * @brief   DCMI RIS register  
+  */ 
+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Capture complete interrupt flag      */ 
+#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag               */ 
+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag */ 
+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                 */ 
+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                  */ 
+/** 
+  * @brief   DCMI MIS register  
+  */ 
+#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Capture complete masked interrupt status      */      
+#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status               */               
+#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status */ 
+#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                 */                 
+#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                  */                  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+ 
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
+  * @{
+  */
+  
+/** @brief Reset DCMI handle state
+  * @param  __HANDLE__: specifies the DCMI handle.
+  * @retval None
+  */
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+
+/**
+  * @brief  Enable the DCMI.
+  * @param  __HANDLE__: DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+  * @brief  Disable the DCMI.
+  * @param  __HANDLE__: DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DCMI pending flag.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: Get the specified flag.
+  *         This parameter can be one of the following values (no combination allowed)
+  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)   
+  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) 
+  *            @arg DCMI_FLAG_FNE: FIFO empty flag                                                  
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag
+  *            @arg DCMI_FLAG_LINERI: Line flag
+  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status      
+  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status               
+  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status 
+  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status                 
+  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status                  
+  * @retval The state of FLAG.
+  */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
+ (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DCMI pending flag.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag
+  *            @arg DCMI_FLAG_LINERI: Line flag
+  * @retval None
+  */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DCMI interrupts.
+  * @param  __HANDLE__:    DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt
+  *            @arg DCMI_IT_OVR: Overrun interrupt
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt
+  *            @arg DCMI_IT_LINE: Line interrupt
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DCMI interrupts.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt
+  *            @arg DCMI_IT_OVR: Overrun interrupt
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt
+  *            @arg DCMI_IT_LINE: Line interrupt
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether or not the specified DCMI interrupt has occurred and that the interruption is enabled at the same time.
+  * @note   A bit in MIS register is set if the corresponding enable bit in 
+  *         DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt flag and source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVR: Overrun interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval The state of INTERRUPT.
+  */
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MIS & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+  
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions 
+ * @{
+ */
+ 
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
+void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+/**
+  * @}
+  */
+  
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions 
+ * @{
+ */
+ 
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
+void              HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+/**
+  * @}
+  */
+  
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions 
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
+/**
+  * @}
+  */
+  
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions 
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
+uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/  
+/** @addtogroup DCMI_Private_Constants DCMI Private Constants
+  * @{
+  */
+  
+/** @defgroup DCMI_Registers_Indices DCMI Registers Indices
+  * @{
+  */  
+#define DCMI_MIS_INDEX        ((uint32_t)0x1000)         /*!< DCMI MIS register index */
+#define DCMI_SR_INDEX         ((uint32_t)0x2000)         /*!< DCMI SR register index */ 
+/**
+  * @}
+  */  
+
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
+  * @{
+  */
+#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFF)  /*!< Window coordinate */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Height DCMI Window Height
+  * @{
+  */ 
+#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFF)  /*!< Window Height */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+   
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Macros DCMI Private Macros
+  * @{
+  */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+                                   ((MODE) == DCMI_MODE_SNAPSHOT))
+                                                                                                
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+                              
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+                                      
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+                                     
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+                                     
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+                                     
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+                                    
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
+                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_14B))
+                                    
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
+                                       ((MODE) == DCMI_BSM_OTHER) || \
+                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \
+                                       ((MODE) == DCMI_BSM_ALTERNATE_2))
+                                                                                                
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
+                                            ((POLARITY) == DCMI_OEBS_EVEN))
+                              
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
+                                       ((MODE) == DCMI_LSM_ALTERNATE_2))
+                                      
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
+                                            ((POLARITY) == DCMI_OELS_EVEN))  
+                                            
+#define IS_DCMI_INTERRUPTS(INTERRUPTS) ((INTERRUPTS) <= DCMI_IER_INT_IE)                                                                                                                                 
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+    
+/**
+  * @}
+  */ 
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h
new file mode 100755
index 0000000..ad596e5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h
@@ -0,0 +1,237 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_def.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DEF
+#define __STM32L4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+#include "stm32_hal_legacy.h"  /* Aliases file for old names compatibility */
+#include <stdio.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \
+                        do{                                                      \
+                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                            (__DMA_HANDLE__).Parent = (__HANDLE__);              \
+                        } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+  /* Reserved for future use */
+  #error " USE_RTOS should be 0 in the current HAL release "
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+#if defined (__CC_ARM)
+#pragma diag_suppress 3731
+#endif
+
+static inline  void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
+{
+	uint32_t newValue;
+	do {
+		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
+
+	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+}
+
+
+static inline  void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
+{
+	uint32_t newValue;
+	do {
+		newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
+
+	} while (__STREXW(newValue,(volatile unsigned long*) ptr));
+}
+
+#if  defined ( __GNUC__ ) && !defined ( __CC_ARM )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC HAL_StatusTypeDef
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
+/* ARM & GNUCompiler
+   ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32L4xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c
new file mode 100755
index 0000000..8cd6cc6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c
@@ -0,0 +1,3029 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dfsdm.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital Filter for Sigma-Delta Modulators
+  *          (DFSDM) peripherals:
+  *           + Initialization and configuration of channels and filters
+  *           + Regular channels configuration
+  *           + Injected channels configuration
+  *           + Regular/Injected Channels DMA Configuration
+  *           + Interrupts and flags management
+  *           + Analog watchdog feature
+  *           + Short-circuit detector feature
+  *           + Extremes detector feature
+  *           + Clock absence detector feature
+  *           + Break generation on analog watchdog or short-circuit event
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    *** Channel initialization ***
+    ==============================
+    [..]
+      (#) User has first to initialize channels (before filters initialization).
+      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
+        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
+        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+      (#) Configure the output clock, input, serial interface, analog watchdog,
+          offset and data right bit shift parameters for this channel using the 
+          HAL_DFSDM_ChannelInit() function.
+
+    *** Channel clock absence detector ***
+    ======================================
+    [..]
+      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
+          HAL_DFSDM_ChannelCkabStart_IT().
+      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
+          absence.
+      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
+          clock absence is detected.
+      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
+          HAL_DFSDM_ChannelCkabStop_IT().
+      (#) Please note that the same mode (polling or interrupt) has to be used 
+          for all channels because the channels are sharing the same interrupt.
+      (#) Please note also that in interrupt mode, if clock absence detector is
+          stopped for one channel, interrupt will be disabled for all channels.
+
+    *** Channel short circuit detector ***
+    ======================================
+    [..]    
+      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
+          or HAL_DFSDM_ChannelScdStart_IT().
+      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
+          circuit.
+      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if 
+          short circuit is detected.
+      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
+          or HAL_DFSDM_ChannelScdStop_IT().
+      (#) Please note that the same mode (polling or interrupt) has to be used 
+          for all channels because the channels are sharing the same interrupt.
+      (#) Please note also that in interrupt mode, if short circuit detector is
+          stopped for one channel, interrupt will be disabled for all channels.
+
+    *** Channel analog watchdog value ***
+    =====================================
+    [..]    
+      (#) Get analog watchdog filter value of a channel using
+          HAL_DFSDM_ChannelGetAwdValue().
+
+    *** Channel offset value ***
+    =====================================
+    [..]    
+      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
+
+    *** Filter initialization ***
+    =============================
+    [..]
+      (#) After channel initialization, user has to init filters.
+      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
+        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+            Please note that DFSDMz_FLT0 global interrupt could be already
+            enabled if interrupt is used for channel.
+        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
+            with DFSDMz filter handle using __HAL_LINKDMA().
+      (#) Configure the regular conversion, injected conversion and filter
+          parameters for this filter using the HAL_DFSDM_FilterInit() function.
+
+    *** Filter regular channel conversion ***
+    =========================================
+    [..]    
+      (#) Select regular channel and enable/disable continuous mode using
+          HAL_DFSDM_FilterConfigRegChannel().
+      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
+          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
+          HAL_DFSDM_FilterRegularMsbStart_DMA().
+      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect 
+          the end of regular conversion.
+      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
+          at the end of regular conversion.
+      (#) Get value of regular conversion and corresponding channel using 
+          HAL_DFSDM_FilterGetRegularValue().
+      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and 
+          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
+          half transfer and at the transfer complete. Please note that 
+          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
+          circular mode.
+      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
+          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
+
+    *** Filter injected channels conversion ***
+    ===========================================
+    [..]
+      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
+      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
+          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
+          HAL_DFSDM_FilterInjectedMsbStart_DMA().
+      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect 
+          the end of injected conversion.
+      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
+          at the end of injected conversion.
+      (#) Get value of injected conversion and corresponding channel using 
+          HAL_DFSDM_FilterGetInjectedValue().
+      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and 
+          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
+          half transfer and at the transfer complete. Please note that 
+          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
+          circular mode.
+      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
+          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
+
+    *** Filter analog watchdog ***
+    ==============================
+    [..]
+      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
+      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
+      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
+
+    *** Filter extreme detector ***
+    ===============================
+    [..]
+      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
+      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
+      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
+      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
+
+    *** Filter conversion time ***
+    ==============================
+    [..]
+      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
+
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_DFSDM_MODULE_ENABLED
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+/** @defgroup DFSDM DFSDM
+  * @brief DFSDM HAL driver module
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Define DFSDM Private Define
+ * @{
+ */
+#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
+#define DFSDM_CHAWSCDR_BKSCD_OFFSET     POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
+#define DFSDM_CHAWSCDR_FOSR_OFFSET      POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
+#define DFSDM_CHCFGR2_OFFSET_OFFSET  POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
+#define DFSDM_CHCFGR2_DTRBS_OFFSET   POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
+#define DFSDM_FLTFCR_FOSR_OFFSET        POSITION_VAL(DFSDM_FLTFCR_FOSR)
+#define DFSDM_FLTCR1_MSB_RCH_OFFSET     8
+#define DFSDM_FLTCR2_EXCH_OFFSET        POSITION_VAL(DFSDM_FLTCR2_EXCH)
+#define DFSDM_FLTCR2_AWDCH_OFFSET       POSITION_VAL(DFSDM_FLTCR2_AWDCH)
+#define DFSDM_FLTISR_CKABF_OFFSET       POSITION_VAL(DFSDM_FLTISR_CKABF)
+#define DFSDM_FLTISR_SCDF_OFFSET        POSITION_VAL(DFSDM_FLTISR_SCDF)
+#define DFSDM_FLTICR_CLRCKABF_OFFSET    POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
+#define DFSDM_FLTICR_CLRSCDF_OFFSET     POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
+#define DFSDM_FLTRDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
+#define DFSDM_FLTJDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
+#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
+#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
+#define DFSDM_FLTEXMAX_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
+#define DFSDM_FLTEXMIN_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
+#define DFSDM_FLTCNVTIMR_DATA_OFFSET    POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
+#define DFSDM_FLTAWSR_HIGH_OFFSET       POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
+#define DFSDM_MSB_MASK               0xFFFF0000U
+#define DFSDM_LSB_MASK               0x0000FFFFU
+#define DFSDM_CKAB_TIMEOUT           5000U
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define DFSDM1_CHANNEL_NUMBER           4U
+#else /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define DFSDM1_CHANNEL_NUMBER           8U
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Variables DFSDM Private Variables
+  * @{
+  */
+__IO uint32_t                v_dfsdm1ChannelCounter = 0;
+DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DFSDM_Private_Functions DFSDM Private Functions
+  * @{
+  */
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
+static void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+static void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
+  * @{
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+ *  @brief    Channel initialization and de-initialization functions 
+ *
+@verbatim
+  ==============================================================================
+        ##### Channel initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the DFSDM channel.
+      (+) De-initialize the DFSDM channel.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DFSDM channel according to the specified parameters
+  *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Check DFSDM Channel handle */
+  if(hdfsdm_channel == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
+  assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
+  assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
+  assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
+  assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
+  assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
+  assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
+  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
+  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
+  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
+  
+  /* Check that channel has not been already initialized */
+  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Call MSP init function */
+  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
+  
+  /* Update the channel counter */
+  v_dfsdm1ChannelCounter++;
+  
+  /* Configure output serial clock and enable global DFSDM interface only for first channel */
+  if(v_dfsdm1ChannelCounter == 1)
+  {
+    assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
+    /* Set the output serial clock source */
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
+    DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
+    
+    /* Reset clock divider */
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
+    if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
+    {
+      assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
+      /* Set the output clock divider */
+      DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << 
+                                             DFSDM_CHCFGR1_CLK_DIV_OFFSET);
+    }
+    
+    /* enable the DFSDM global interface */
+    DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
+  }
+  
+  /* Set channel input parameters */
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | 
+                                         DFSDM_CHCFGR1_CHINSEL);
+  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | 
+                                        hdfsdm_channel->Init.Input.DataPacking | 
+                                        hdfsdm_channel->Init.Input.Pins);
+  
+  /* Set serial interface parameters */
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
+  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | 
+                                        hdfsdm_channel->Init.SerialInterface.SpiClock);
+  
+  /* Set analog watchdog parameters */
+  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
+  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | 
+                                       ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));
+
+  /* Set channel offset and right bit shift */
+  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
+  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | 
+                                        (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
+
+  /* Enable DFSDM channel */
+  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
+  
+  /* Set DFSDM Channel to ready state */
+  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
+
+  /* Store channel handle in DFSDM channel handle table */
+  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initialize the DFSDM channel.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Check DFSDM Channel handle */
+  if(hdfsdm_channel == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check that channel has not been already deinitialized */
+  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the DFSDM channel */
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
+  
+  /* Update the channel counter */
+  v_dfsdm1ChannelCounter--;
+  
+  /* Disable global DFSDM at deinit of last channel */
+  if(v_dfsdm1ChannelCounter == 0)
+  {
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
+  }
+
+  /* Call MSP deinit function */
+  HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
+
+  /* Set DFSDM Channel in reset state */
+  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
+
+  /* Reset channel handle in DFSDM channel handle table */
+  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the DFSDM channel MSP.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  De-initialize the DFSDM channel MSP.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+ *  @brief    Channel operation functions
+ *
+@verbatim
+  ==============================================================================
+                   ##### Channel operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Manage clock absence detector feature.
+      (+) Manage short circuit detector feature.
+      (+) Get analog watchdog value.
+      (+) Modify offset value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to start clock absence detection in polling mode.
+  * @note   Same mode has to be used for all channels.
+  * @note   If clock is not available on this channel during 5 seconds,
+  *         clock absence detection will not be activated and function
+  *         will return HAL_TIMEOUT error.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+  uint32_t tickstart;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Clear clock absence flag */
+    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
+    {
+      DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+      /* Check the Timeout */
+      if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
+      {
+        /* Set timeout status */
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(status == HAL_OK)
+    {
+      /* Start clock absence detection */
+      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the clock absence detection.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 
+                                               uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t channel;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Wait clock absence detection */
+    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Clear clock absence detection flag */
+    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop clock absence detection in polling mode.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop clock absence detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+    
+    /* Clear clock absence flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start clock absence detection in interrupt mode.
+  * @note   Same mode has to be used for all channels.
+  * @note   If clock is not available on this channel during 5 seconds,
+  *         clock absence detection will not be activated and function
+  *         will return HAL_TIMEOUT error.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+  uint32_t tickstart;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Clear clock absence flag */
+    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
+    {
+      DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+      /* Check the Timeout */
+      if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
+      {
+        /* Set timeout status */
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(status == HAL_OK)
+    {
+      /* Activate clock absence detection interrupt */
+      DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
+
+      /* Start clock absence detection */
+      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Clock absence detection callback. 
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function allows to stop clock absence detection in interrupt mode.
+  * @note   Interrupt will be disabled for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop clock absence detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+    
+    /* Clear clock absence flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+    /* Disable clock absence detection interrupt */
+    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start short circuit detection in polling mode.
+  * @note   Same mode has to be used for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Threshold : Short circuit detector threshold.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
+  * @param  BreakSignal : Break signals assigned to short circuit event.
+  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+                                            uint32_t Threshold,
+                                            uint32_t BreakSignal)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Configure threshold and break signals */
+    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
+    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+                                         Threshold);
+    
+    /* Start short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the short circuit detection.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 
+                                              uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t channel;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Wait short circuit detection */
+    while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Clear short circuit detection flag */
+    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop short circuit detection in polling mode.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
+    
+    /* Clear short circuit detection flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start short circuit detection in interrupt mode.
+  * @note   Same mode has to be used for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Threshold : Short circuit detector threshold.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
+  * @param  BreakSignal : Break signals assigned to short circuit event.
+  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+                                               uint32_t Threshold,
+                                               uint32_t BreakSignal)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Activate short circuit detection interrupt */
+    DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
+
+    /* Configure threshold and break signals */
+    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
+    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+                                         Threshold);
+    
+    /* Start short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Short circuit detection callback. 
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function allows to stop short circuit detection in interrupt mode.
+  * @note   Interrupt will be disabled for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
+    
+    /* Clear short circuit detection flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+
+    /* Disable short circuit detection interrupt */
+    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get channel analog watchdog value.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval Channel analog watchdog value.
+  */
+int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
+}
+
+/**
+  * @brief  This function allows to modify channel offset value.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Offset : DFSDM channel offset.
+  *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+                                                int32_t Offset)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Modify channel offset */
+    hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
+    hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+ *  @brief    Channel state function
+ *
+@verbatim
+  ==============================================================================
+                   ##### Channel state function #####
+  ==============================================================================
+    [..]  This section provides function allowing to:
+      (+) Get channel handle state.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to get the current DFSDM channel handle state.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval DFSDM channel state.
+  */
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Return DFSDM channel handle state */
+  return hdfsdm_channel->State;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+ *  @brief    Filter initialization and de-initialization functions 
+ *
+@verbatim
+  ==============================================================================
+        ##### Filter initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the DFSDM filter.
+      (+) De-initialize the DFSDM filter.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DFSDM filter according to the specified parameters
+  *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Check DFSDM Channel handle */
+  if(hdfsdm_filter == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
+  assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
+  assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
+  assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
+  assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
+
+  /* Check parameters compatibility */
+  if((hdfsdm_filter->Instance == DFSDM1_Filter0) && 
+    ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) || 
+     (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Initialize DFSDM filter variables with default values */
+  hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;
+  hdfsdm_filter->InjectedChannelsNbr = 1;
+  hdfsdm_filter->InjConvRemaining    = 1;
+  hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;
+  
+  /* Call MSP init function */
+  HAL_DFSDM_FilterMspInit(hdfsdm_filter);
+
+  /* Set regular parameters */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
+  if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
+  }
+
+  if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
+  }
+
+  /* Set injected parameters */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
+  if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
+  {
+    assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
+    assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
+    hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
+  }
+
+  if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
+  }
+
+  if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
+  }
+  
+  /* Set filter parameters */
+  hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
+  hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
+                                    ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |
+                                  (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));
+
+  /* Store regular and injected triggers and injected scan mode*/
+  hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;
+  hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;
+  hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
+  hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
+  
+  /* Enable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+  /* Set DFSDM filter to ready state */
+  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initializes the DFSDM filter.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Check DFSDM filter handle */
+  if(hdfsdm_filter == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  
+  /* Disable the DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+  
+  /* Call MSP deinit function */
+  HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
+
+  /* Set DFSDM filter in reset state */
+  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DFSDM filter MSP.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_FilterMspInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  De-initializes the DFSDM filter MSP.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+ *  @brief    Filter control functions
+ *
+@verbatim
+  ==============================================================================
+                    ##### Filter control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Select channel and enable/disable continuous mode for regular conversion.
+      (+) Select channels for injected conversion.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to select channel and to enable/disable
+  *         continuous mode for regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Channel for regular conversion.
+  *         This parameter can be a value of @ref DFSDM_Channel_Selection.
+  * @param  ContinuousMode : Enable/disable continuous mode for regular conversion.
+  *         This parameter can be a value of @ref DFSDM_ContinuousMode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel,
+                                                   uint32_t                    ContinuousMode)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
+  assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && 
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Configure channel and continuous mode for regular conversion */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
+    if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
+                                                     DFSDM_FLTCR1_RCONT);
+    }
+    else
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
+    }
+    /* Store continuous mode information */
+    hdfsdm_filter->RegularContMode = ContinuousMode;
+  }  
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to select channels for injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Channels for injected conversion.
+  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && 
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Configure channel for injected conversion */
+    hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
+    /* Store number of injected channels */
+    hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
+    /* Update number of injected channels remaining */
+    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                      hdfsdm_filter->InjectedChannelsNbr : 1;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+ *  @brief    Filter operation functions
+ *
+@verbatim
+  ==============================================================================
+                    ##### Filter operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular/injected channel.
+      (+) Poll for the end of regular/injected conversion.
+      (+) Stop conversion of regular/injected channel.
+      (+) Start conversion of regular/injected channel and enable interrupt.
+      (+) Call the callback functions at the end of regular/injected conversions.
+      (+) Stop conversion of regular/injected channel and disable interrupt.
+      (+) Start conversion of regular/injected channel and enable DMA transfer.
+      (+) Stop conversion of regular/injected channel and disable DMA transfer.
+      (+) Start analog watchdog and enable interrupt.
+      (+) Call the callback function when analog watchdog occurs.
+      (+) Stop analog watchdog and disable interrupt.
+      (+) Start extreme detector.
+      (+) Stop extreme detector.
+      (+) Get result of regular channel conversion.
+      (+) Get result of injected channel conversion.
+      (+) Get extreme detector maximum and minimum values.
+      (+) Get conversion time.
+      (+) Handle DFSDM interrupt request.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to start regular conversion in polling mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Start regular conversion */
+    DFSDM_RegConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the end of regular conversion.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                       uint32_t                    Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get timeout */
+    tickstart = HAL_GetTick();  
+
+    /* Wait end of regular conversion */
+    while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Check if overrun occurs */
+    if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
+    {
+      /* Update error code and call error callback */
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+
+      /* Clear regular overrun flag */
+      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
+    }
+    /* Update DFSDM filter state only if not continuous conversion and SW trigger */
+    if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+    {
+      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+    }
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop regular conversion in polling mode.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop regular conversion */
+    DFSDM_RegConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start regular conversion in interrupt mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Enable interrupts for regular conversions */
+    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
+    
+    /* Start regular conversion */
+    DFSDM_RegConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop regular conversion in interrupt mode.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Disable interrupts for regular conversions */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
+    
+    /* Stop regular conversion */
+    DFSDM_RegConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start regular conversion in DMA mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  *         Please note that data on buffer will contain signed regular conversion
+  *         value on 24 most significant bits and corresponding channel on 3 least
+  *         significant bits.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   int32_t                    *pData,
+                                                   uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for regular conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+          (Length != 1))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
+    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMARegularHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start regular conversion */
+      DFSDM_RegConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start regular conversion in DMA mode and to get
+  *         only the 16 most significant bits of conversion.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  *         Please note that data on buffer will contain signed 16 most significant
+  *         bits of regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                      int16_t                    *pData,
+                                                      uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for regular conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+          (Length != 1))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
+    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMARegularHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start regular conversion */
+      DFSDM_RegConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop regular conversion in DMA mode.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop current DMA transfer */
+    if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Stop regular conversion */
+      DFSDM_RegConvStop(hdfsdm_filter);
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get regular conversion value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel of regular conversion.
+  * @retval Regular conversion value
+  */
+int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                        uint32_t                   *Channel)
+{
+  uint32_t reg = 0;
+  int32_t  value = 0;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of data register for regular channel */
+  reg = hdfsdm_filter->Instance->FLTRDATAR;
+  
+  /* Extract channel and regular conversion value */
+  *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
+  value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
+
+  /* return regular conversion value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in polling mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Start injected conversion */
+    DFSDM_InjConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the end of injected conversion.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                       uint32_t                    Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get timeout */
+    tickstart = HAL_GetTick();  
+
+    /* Wait end of injected conversions */
+    while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Check if overrun occurs */
+    if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
+    {
+      /* Update error code and call error callback */
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+
+      /* Clear injected overrun flag */
+      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
+    }
+
+    /* Update remaining injected conversions */
+    hdfsdm_filter->InjConvRemaining--;
+    if(hdfsdm_filter->InjConvRemaining == 0)
+    {
+      /* Update DFSDM filter state only if trigger is software */
+      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+      {
+        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+      }
+      
+      /* end of injected sequence, reset the value */
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                         hdfsdm_filter->InjectedChannelsNbr : 1;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop injected conversion in polling mode.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop injected conversion */
+    DFSDM_InjConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in interrupt mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Enable interrupts for injected conversions */
+    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
+    
+    /* Start injected conversion */
+    DFSDM_InjConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop injected conversion in interrupt mode.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Disable interrupts for injected conversions */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
+    
+    /* Stop injected conversion */
+    DFSDM_InjConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in DMA mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  *         Please note that data on buffer will contain signed injected conversion
+  *         value on 24 most significant bits and corresponding channel on 3 least
+  *         significant bits.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                    int32_t                    *pData,
+                                                    uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for injected conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+          (Length > hdfsdm_filter->InjConvRemaining))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
+    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start injected conversion */
+      DFSDM_InjConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in DMA mode and to get
+  *         only the 16 most significant bits of conversion.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  *         Please note that data on buffer will contain signed 16 most significant
+  *         bits of injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                       int16_t                    *pData,
+                                                       uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for injected conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+          (Length > hdfsdm_filter->InjConvRemaining))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
+    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start injected conversion */
+      DFSDM_InjConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop injected conversion in DMA mode.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop current DMA transfer */
+    if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Stop regular conversion */
+      DFSDM_InjConvStop(hdfsdm_filter);
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get injected conversion value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel of injected conversion.
+  * @retval Injected conversion value
+  */
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 
+                                         uint32_t                   *Channel)
+{
+  uint32_t reg = 0;
+  int32_t  value = 0;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of data register for injected channel */
+  reg = hdfsdm_filter->Instance->FLTJDATAR;
+  
+  /* Extract channel and injected conversion value */
+  *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
+  value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
+
+  /* return regular conversion value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to start filter analog watchdog in interrupt mode.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  awdParam : DFSDM filter analog watchdog parameters.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,
+                                              DFSDM_Filter_AwdParamTypeDef *awdParam)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
+  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
+  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Set analog watchdog data source */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
+    hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
+
+    /* Set thresholds and break signals */
+    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
+    hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
+                                        awdParam->HighBreakSignal);
+    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
+    hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
+                                        awdParam->LowBreakSignal);
+
+    /* Set channels and interrupt for analog watchdog */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
+    hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
+                                        DFSDM_FLTCR2_AWDIE);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop filter analog watchdog in interrupt mode.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Reset channels for analog watchdog and deactivate interrupt */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
+
+    /* Clear all analog watchdog flags */
+    hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
+    
+    /* Reset thresholds and break signals */
+    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
+    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
+
+    /* Reset analog watchdog data source */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start extreme detector feature.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Channels where extreme detector is enabled.
+  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                           uint32_t                    Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Set channels for extreme detector */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
+    hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);    
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop extreme detector feature.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t     reg1;
+  __IO uint32_t     reg2;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Reset channels for extreme detector */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
+
+    /* Clear extreme detector values */
+    reg1 = hdfsdm_filter->Instance->FLTEXMAX;
+    reg2 = hdfsdm_filter->Instance->FLTEXMIN;    
+    UNUSED(reg1); /* To avoid GCC warning */
+    UNUSED(reg2); /* To avoid GCC warning */
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get extreme detector maximum value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel.
+  * @retval Extreme detector maximum value
+  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
+  */
+int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                       uint32_t                   *Channel)
+{
+  uint32_t reg = 0;
+  int32_t  value = 0;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of extreme detector maximum register */
+  reg = hdfsdm_filter->Instance->FLTEXMAX;
+  
+  /* Extract channel and extreme detector maximum value */
+  *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
+  value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
+
+  /* return extreme detector maximum value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to get extreme detector minimum value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel.
+  * @retval Extreme detector minimum value
+  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
+  */
+int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                       uint32_t                   *Channel)
+{
+  uint32_t reg = 0;
+  int32_t  value = 0;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of extreme detector minimum register */
+  reg = hdfsdm_filter->Instance->FLTEXMIN;
+  
+  /* Extract channel and extreme detector minimum value */
+  *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
+  value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
+
+  /* return extreme detector minimum value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to get conversion time value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval Conversion time value
+  * @note   To get time in second, this value has to be divided by DFSDM clock frequency.
+  */
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  uint32_t reg = 0;
+  uint32_t value = 0;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Get value of conversion timer register */
+  reg = hdfsdm_filter->Instance->FLTCNVTIMR;
+  
+  /* Extract conversion time value */
+  value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
+
+  /* return extreme detector minimum value */
+  return value;
+}
+
+/**
+  * @brief  This function handles the DFSDM interrupts.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Check if overrun occurs during regular conversion */
+  if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \
+     ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))
+  {
+    /* Clear regular overrun flag */
+    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
+
+    /* Update error code */
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+
+    /* Call error callback */
+    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+  }
+  /* Check if overrun occurs during injected conversion */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))
+  {
+    /* Clear injected overrun flag */
+    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
+
+    /* Update error code */
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+
+    /* Call error callback */
+    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+  }
+  /* Check if end of regular conversion */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))
+  {
+    /* Call regular conversion complete callback */
+    HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+
+    /* End of conversion if mode is not continuous and software trigger */
+    if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+    {
+      /* Disable interrupts for regular conversions */
+      hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
+
+      /* Update DFSDM filter state */
+      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+    }
+  }
+  /* Check if end of injected conversion */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))
+  {
+    /* Call injected conversion complete callback */
+    HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+
+    /* Update remaining injected conversions */
+    hdfsdm_filter->InjConvRemaining--;
+    if(hdfsdm_filter->InjConvRemaining == 0)
+    {
+      /* End of conversion if trigger is software */
+      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+      {
+        /* Disable interrupts for injected conversions */
+        hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
+
+        /* Update DFSDM filter state */
+        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+      }
+      /* end of injected sequence, reset the value */
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                         hdfsdm_filter->InjectedChannelsNbr : 1;
+    }
+  }
+  /* Check if analog watchdog occurs */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))
+  {
+    uint32_t reg = 0;
+    uint32_t threshold = 0;
+    uint32_t channel = 0;
+    
+    /* Get channel and threshold */
+    reg = hdfsdm_filter->Instance->FLTAWSR;
+    threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
+    if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
+    {
+      reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
+    }
+    while((reg & 1) == 0)
+    {
+      channel++;
+      reg = reg >> 1;
+    }
+    /* Clear analog watchdog flag */
+    hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
+                                        (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
+                                     (1 << channel);
+
+    /* Call analog watchdog callback */
+    HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
+  }
+  /* Check if clock absence occurs */
+  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
+         ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \
+         ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))
+  {
+    uint32_t reg = 0;
+    uint32_t channel = 0;
+    
+    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
+
+    while(channel < DFSDM1_CHANNEL_NUMBER)
+    {
+      /* Check if flag is set and corresponding channel is enabled */
+      if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))
+      {
+        /* Check clock absence has been enabled for this channel */
+        if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)
+        {
+          /* Clear clock absence flag */
+          hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+          /* Call clock absence callback */
+          HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
+        }
+      }
+      channel++;
+      reg = reg >> 1;
+    }
+  }
+  /* Check if short circuit detection occurs */
+  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
+         ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \
+         ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))
+  {
+    uint32_t reg = 0;
+    uint32_t channel = 0;
+    
+    /* Get channel */
+    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
+    while((reg & 1) == 0)
+    {
+      channel++;
+      reg = reg >> 1;
+    }
+    
+    /* Clear short circuit detection flag */
+    hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+
+    /* Call short circuit detection callback */
+    HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
+  }
+}
+
+/**
+  * @brief  Regular conversion complete callback. 
+  * @note   In interrupt mode, user has to read conversion value in this function
+  *         using HAL_DFSDM_FilterGetRegularValue.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Half regular conversion complete callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Injected conversion complete callback. 
+  * @note   In interrupt mode, user has to read conversion value in this function
+  *         using HAL_DFSDM_FilterGetInjectedValue.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Half injected conversion complete callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Filter analog watchdog callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel.
+  * @param  Threshold : Low or high threshold has been reached.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                        uint32_t Channel, uint32_t Threshold)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  UNUSED(Channel);
+  UNUSED(Threshold);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Error callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+ *  @brief    Filter state functions
+ *
+@verbatim
+  ==============================================================================
+                     ##### Filter state functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Get the DFSDM filter state.
+      (+) Get the DFSDM filter error.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to get the current DFSDM filter handle state.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval DFSDM filter state.
+  */
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Return DFSDM filter handle state */
+  return hdfsdm_filter->State;
+}
+
+/**
+  * @brief  This function allows to get the current DFSDM filter error.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval DFSDM filter error code.
+  */
+uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  return hdfsdm_filter->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA half transfer complete callback for regular conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call regular half conversion complete callback */
+  HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA transfer complete callback for regular conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call regular conversion complete callback */
+  HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA half transfer complete callback for injected conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call injected half conversion complete callback */
+  HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA transfer complete callback for injected conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call injected conversion complete callback */
+  HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA error callback. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Update error code */
+  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
+
+  /* Call error callback */
+  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  This function allows to get the number of injected channels.
+  * @param  Channels : bitfield of injected channels.
+  * @retval Number of injected channels.
+  */
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
+{
+  uint32_t nbChannels = 0;
+  uint32_t tmp;
+  
+  /* Get the number of channels from bitfield */
+  tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
+  while(tmp != 0)
+  {
+    if((tmp & 1) != 0)
+    {
+      nbChannels++;
+    }
+    tmp = (uint32_t) (tmp >> 1);
+  }
+  return nbChannels;
+}
+
+/**
+  * @brief  This function allows to get the channel number from channel instance.
+  * @param  Instance : DFSDM channel instance.
+  * @retval Channel number.
+  */
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
+{
+  uint32_t channel = 0xFF;
+  
+  /* Get channel from instance */
+  if(Instance == DFSDM1_Channel0)
+  {
+    channel = 0;
+  }
+  else if(Instance == DFSDM1_Channel1)
+  {
+    channel = 1;
+  }
+  else if(Instance == DFSDM1_Channel2)
+  {
+    channel = 2;
+  }
+  else if(Instance == DFSDM1_Channel3)
+  {
+    channel = 3;
+  }
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+  else if(Instance == DFSDM1_Channel4)
+  {
+    channel = 4;
+  }
+  else if(Instance == DFSDM1_Channel5)
+  {
+    channel = 5;
+  }
+  else if(Instance == DFSDM1_Channel6)
+  {
+    channel = 6;
+  }
+  else if(Instance == DFSDM1_Channel7)
+  {
+    channel = 7;
+  }
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+
+  return channel;
+}
+
+/**
+  * @brief  This function allows to really start regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Check regular trigger */
+  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
+  {
+    /* Software start of regular conversion */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+  }
+  else /* synchronous trigger */
+  {
+    /* Disable DFSDM filter */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+    
+    /* Set RSYNC bit in DFSDM_FLTCR1 register */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
+
+    /* Enable DFSDM  filter */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+    
+    /* If injected conversion was in progress, restart it */
+    if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
+    {
+      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+      {
+        hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+      }
+      /* Update remaining injected conversions */
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                         hdfsdm_filter->InjectedChannelsNbr : 1;
+    }
+  }
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
+                          HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
+}
+
+/**
+  * @brief  This function allows to really stop regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Disable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+  /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
+  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
+  }
+
+  /* Enable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+  
+  /* If injected conversion was in progress, restart it */
+  if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
+  {
+    if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+    }
+    /* Update remaining injected conversions */
+    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                       hdfsdm_filter->InjectedChannelsNbr : 1;
+  }
+  
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+                          HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+}
+
+/**
+  * @brief  This function allows to really start injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Check injected trigger */
+  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+  {
+    /* Software start of injected conversion */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+  }
+  else /* external or synchronous trigger */
+  {
+    /* Disable DFSDM filter */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+      
+    if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+    {
+      /* Set JSYNC bit in DFSDM_FLTCR1 register */
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
+    }
+    else /* external trigger */
+    {
+      /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
+      hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
+    }
+    
+    /* Enable DFSDM filter */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+    /* If regular conversion was in progress, restart it */
+    if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
+       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+    }
+  }
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
+                         HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
+}
+
+/**
+  * @brief  This function allows to really stop injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Disable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+  /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
+  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
+  }
+  else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
+  {
+    /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
+  }
+
+  /* Enable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+  
+  /* If regular conversion was in progress, restart it */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
+     (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+  }
+
+  /* Update remaining injected conversions */
+  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                     hdfsdm_filter->InjectedChannelsNbr : 1;
+
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+                          HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+}
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h
new file mode 100755
index 0000000..7af5ae4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h
@@ -0,0 +1,755 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dfsdm.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DFSDM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DFSDM_H
+#define __STM32L4xx_HAL_DFSDM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DFSDM
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HAL DFSDM Channel states definition  
+  */ 
+typedef enum
+{
+  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
+  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
+  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
+}HAL_DFSDM_Channel_StateTypeDef;
+
+/** 
+  * @brief  DFSDM channel output clock structure definition  
+  */  
+typedef struct
+{
+  FunctionalState Activation; /*!< Output clock enable/disable */
+  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
+                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */
+  uint32_t        Divider;    /*!< Output clock divider.
+                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
+}DFSDM_Channel_OutputClockTypeDef;
+
+/** 
+  * @brief  DFSDM channel input structure definition  
+  */  
+typedef struct
+{
+  uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
+                             ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,
+                             STM32L496xx, STM32L4A6xx products.
+                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
+  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
+                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */
+  uint32_t Pins;        /*!< Input pins are taken from same or following channel.
+                             This parameter can be a value of @ref DFSDM_Channel_InputPins */
+}DFSDM_Channel_InputTypeDef;
+
+/** 
+  * @brief  DFSDM channel serial interface structure definition  
+  */  
+typedef struct
+{
+  uint32_t Type;     /*!< SPI or Manchester modes.
+                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
+  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
+                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */
+}DFSDM_Channel_SerialInterfaceTypeDef;
+
+/** 
+  * @brief  DFSDM channel analog watchdog structure definition  
+  */  
+typedef struct
+{
+  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
+                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
+  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
+                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+}DFSDM_Channel_AwdTypeDef;
+
+/** 
+  * @brief  DFSDM channel init structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
+  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
+  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
+  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
+  int32_t                              Offset;          /*!< DFSDM channel offset.
+                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
+                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+}DFSDM_Channel_InitTypeDef;
+
+/** 
+  * @brief  DFSDM channel handle structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
+  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
+  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
+}DFSDM_Channel_HandleTypeDef;
+
+/** 
+  * @brief  HAL DFSDM Filter states definition  
+  */ 
+typedef enum
+{
+  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */
+  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */
+  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */
+  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
+  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
+  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
+}HAL_DFSDM_Filter_StateTypeDef;
+
+/** 
+  * @brief  DFSDM filter regular conversion parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
+                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
+  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
+}DFSDM_Filter_RegularParamTypeDef;
+
+/** 
+  * @brief  DFSDM filter injected conversion parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
+                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
+  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
+  uint32_t        ExtTrigger;     /*!< External trigger.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
+  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
+}DFSDM_Filter_InjectedParamTypeDef;
+
+/** 
+  * @brief  DFSDM filter parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t SincOrder;       /*!< Sinc filter order.
+                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
+  uint32_t Oversampling;    /*!< Filter oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+  uint32_t IntOversampling; /*!< Integrator oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
+}DFSDM_Filter_FilterParamTypeDef;
+
+/** 
+  * @brief  DFSDM filter init structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
+  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
+  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
+}DFSDM_Filter_InitTypeDef;
+
+/** 
+  * @brief  DFSDM filter handle structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
+  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
+  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
+  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
+  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
+  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
+  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
+  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
+  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
+  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
+  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
+  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
+  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */  
+}DFSDM_Filter_HandleTypeDef;
+
+/** 
+  * @brief  DFSDM filter analog watchdog parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
+                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
+  uint32_t Channel;         /*!< Analog watchdog channel selection.
+                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
+  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+}DFSDM_Filter_AwdParamTypeDef;
+
+/**
+  * @}
+  */ 
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
+  * @{
+  */
+
+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
+  * @{
+  */
+#define DFSDM_CHANNEL_EXTERNAL_INPUTS    ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+#define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
+  * @{
+  */
+#define DFSDM_CHANNEL_STANDARD_MODE         ((uint32_t)0x00000000U) /*!< Standard data packing mode */
+#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
+#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
+  * @{
+  */
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_RISING         ((uint32_t)0x00000000U) /*!< SPI with rising edge */
+#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */
+#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              ((uint32_t)0x00000000U)  /*!< External SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
+  * @{
+  */
+#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
+#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
+#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
+#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
+  * @{
+  */
+#define DFSDM_FILTER_SW_TRIGGER   ((uint32_t)0x00000000U) /*!< Software trigger */
+#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
+#define DFSDM_FILTER_EXT_TRIGGER  ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
+  * @{
+  */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000U)                           /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */
+#else
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000U)                           /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
+  * @{
+  */
+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
+  * @{
+  */
+#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)               /*!< FastSinc filter type */
+#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
+#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
+#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
+#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
+#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
+  * @{
+  */
+#define DFSDM_FILTER_AWD_FILTER_DATA  ((uint32_t)0x00000000U) /*!< From digital filter */
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
+  * @{
+  */ 
+#define DFSDM_FILTER_ERROR_NONE             ((uint32_t)0x00000000U) /*!< No error */
+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
+#define DFSDM_FILTER_ERROR_DMA              ((uint32_t)0x00000003U) /*!< DMA error occurs */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_BreakSignals DFSDM break signals
+  * @{
+  */
+#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
+#define DFSDM_BREAK_SIGNAL_0  ((uint32_t)0x00000001U) /*!< Break signal 0 */
+#define DFSDM_BREAK_SIGNAL_1  ((uint32_t)0x00000002U) /*!< Break signal 1 */
+#define DFSDM_BREAK_SIGNAL_2  ((uint32_t)0x00000004U) /*!< Break signal 2 */
+#define DFSDM_BREAK_SIGNAL_3  ((uint32_t)0x00000008U) /*!< Break signal 3 */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
+  * @{
+  */
+/* DFSDM Channels ------------------------------------------------------------*/
+/* The DFSDM channels are defined as follows:
+   - in 16-bit LSB the channel mask is set
+   - in 16-bit MSB the channel number is set
+   e.g. for channel 5 definition:
+        - the channel mask is 0x00000020 (bit 5 is set)
+        - the channel number 5 is 0x00050000 
+        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001U)
+#define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002U)
+#define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004U)
+#define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008U)
+#else /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001U)
+#define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002U)
+#define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004U)
+#define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008U)
+#define DFSDM_CHANNEL_4                              ((uint32_t)0x00040010U)
+#define DFSDM_CHANNEL_5                              ((uint32_t)0x00050020U)
+#define DFSDM_CHANNEL_6                              ((uint32_t)0x00060040U)
+#define DFSDM_CHANNEL_7                              ((uint32_t)0x00070080U)
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
+  * @{
+  */
+#define DFSDM_CONTINUOUS_CONV_OFF            ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
+#define DFSDM_CONTINUOUS_CONV_ON             ((uint32_t)0x00000001U) /*!< Conversion are continuous */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
+  * @{
+  */
+#define DFSDM_AWD_HIGH_THRESHOLD            ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
+#define DFSDM_AWD_LOW_THRESHOLD             ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
+ * @{
+ */
+
+/** @brief  Reset DFSDM channel handle state.
+  * @param  __HANDLE__: DFSDM channel handle.
+  * @retval None
+  */
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
+
+/** @brief  Reset DFSDM filter handle state.
+  * @param  __HANDLE__: DFSDM filter handle.
+  * @retval None
+  */
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
+  * @{
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+  * @{
+  */
+/* Channel initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+  * @{
+  */
+/* Channel operation functions ************************************************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+
+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+  * @{
+  */
+/* Channel state function *****************************************************/
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+  * @{
+  */
+/* Filter initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+  * @{
+  */
+/* Filter control functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel,
+                                                   uint32_t                    ContinuousMode);
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+  * @{
+  */
+/* Filter operation functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                              DFSDM_Filter_AwdParamTypeDef* awdParam);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+
+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+  * @{
+  */
+/* Filter state functions *****************************************************/
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
+* @{
+*/
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
+                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
+#else
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
+                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1 <= (RATIO)) && ((RATIO) <= 32))
+#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1F)
+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFF)
+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
+#else
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1 <= (RATIO)) && ((RATIO) <= 1024))
+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1 <= (RATIO)) && ((RATIO) <= 256))
+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
+                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU))
+#else /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_7))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
+                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
+/**
+  * @}
+  */ 
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DFSDM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c
new file mode 100755
index 0000000..78da7a3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c
@@ -0,0 +1,942 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dma.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DMA HAL module driver.
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Channel
+       (except for internal SRAM / FLASH memories: no initialization is 
+       necessary). Please refer to the Reference manual for connection between peripherals
+       and DMA requests.
+
+   (#) For a given Channel, program the required configuration through the following parameters:
+       Channel request, Transfer Direction, Source and Destination data formats,
+       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
+       using HAL_DMA_Init() function.
+
+       Prior to HAL_DMA_Init the CLK shall be enabled for both DMA thanks to: 
+       __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE()
+
+   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
+       detection.
+                    
+   (#) Use HAL_DMA_Abort() function to abort the current transfer
+                   
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred.
+              In this case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e. a member of DMA handle structure).
+
+     *** DMA HAL driver macros list ***
+     ============================================= 
+      [..]
+       Below the list of most used macros in DMA HAL driver.
+
+       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. 
+
+     [..] 
+      (@) You can refer to the DMA HAL driver header file for more useful macros  
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief   Initialization and de-initialization functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Channel source
+    and destination addresses, incrementation and data sizes, transfer direction, 
+    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmp = 0;
+
+  /* Check the DMA handle allocation */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
+  {
+    assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
+  }
+  
+  /* calculation of the channel index */
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+  {
+    /* DMA1 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA1;
+  }
+  else 
+  {
+    /* DMA2 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA2;
+  }
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Get the CR register value */
+  tmp = hdma->Instance->CCR;
+
+  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
+                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
+                      DMA_CCR_DIR));
+
+  /* Prepare the DMA Channel configuration */
+  tmp |=  hdma->Init.Direction        |
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+          hdma->Init.Mode                | hdma->Init.Priority;
+
+  /* Write to DMA Channel CR register */
+  hdma->Instance->CCR = tmp;
+
+  /* Set request selection */
+  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
+  {
+    /* Write to DMA channel selection register */
+    if (DMA1 == hdma->DmaBaseAddress)
+    {
+      /* Reset request selection for DMA1 Channelx */
+      DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
+
+      /* Configure request selection for DMA1 Channelx */
+      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); 
+    }
+    else /* DMA2 */
+    {
+      /* Reset request selection for DMA2 Channelx */
+      DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
+     
+      /* Configure request selection for DMA2 Channelx */
+      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); 
+    }
+  }
+
+  /* Clean callbacks */
+  hdma->XferCpltCallback = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferErrorCallback = NULL;
+  hdma->XferAbortCallback = NULL;
+
+  /* Initialise the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state*/
+  hdma->State  = HAL_DMA_STATE_READY;
+
+  /* Allocate lock resource and initialize it */
+  hdma->Lock = HAL_UNLOCKED;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the DMA peripheral.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  /* Check the DMA handle allocation */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Disable the selected DMA Channelx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Reset DMA Channel control register */
+  hdma->Instance->CCR  = 0;
+
+  /* Calculation of the channel index */
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+  {
+    /* DMA1 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA1;
+  }
+  else 
+  {
+    /* DMA2 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA2;
+  }
+  
+
+  /* Clear all flags */
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+  /* Reset DMA channel selection register */
+  if (DMA1 == hdma->DmaBaseAddress)
+  {
+    /* DMA1 */
+    DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); 
+  }
+  else  
+  {
+    /* DMA2 */
+    DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); 
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA Transfer.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+            
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Configure the source, destination address and the data length & clear flags*/
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+    
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+   /* Process Unlocked */
+   __HAL_UNLOCK(hdma);  
+   status = HAL_BUSY;
+  }  
+  return status;
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Configure the source, destination address and the data length & clear flags*/
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+    
+    /* Enable the transfer complete interrupt */
+    /* Enable the transfer Error interrupt */
+    if(NULL != hdma->XferHalfCpltCallback )
+    {
+      /* Enable the Half transfer complete interrupt as well */
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+    }
+    else
+    {
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+    }
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {      
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma); 
+
+    /* Remain BUSY */
+    status = HAL_BUSY;
+  }    
+  return status;
+}
+
+/**
+  * @brief  Abort the DMA Transfer.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+    * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+        
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+    
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);      
+  }
+  return status; 
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{  
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+        
+    status = HAL_ERROR;
+  }
+  else
+  { 
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+    
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+    
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Call User Abort callback */ 
+    if(hdma->XferAbortCallback != NULL)
+    {
+      hdma->XferAbortCallback(hdma);
+    } 
+  }
+  return status;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
+  *                  the configuration information for the specified DMA Channel.
+  * @param  CompleteLevel: Specifies the DMA level complete.
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+  uint32_t temp;
+  uint32_t tickstart = 0;
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+
+  /* Polling mode not supported in circular mode */
+  if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Get the level transfer complete flag */
+  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
+  {
+    /* Transfer Complete flag */
+    temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
+  }
+  else
+  {
+    /* Half Transfer Complete flag */
+    temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(RESET == (hdma->DmaBaseAddress->ISR & temp))     
+  {
+    if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))    
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Clear all flags */
+      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+    }
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
+  {
+    /* Clear the transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex);
+
+    /* The selected Channelx EN bit is cleared (DMA is disabled and
+    all transfers are complete) */
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+  else
+  {
+    /* Clear the half transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma);  
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle DMA interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+  uint32_t source_it = hdma->Instance->CCR;
+  
+  /* Half Transfer Complete Interrupt management ******************************/
+  if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
+  {
+      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+      {
+        /* Disable the half transfer interrupt */
+        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+      }
+      /* Clear the half transfer complete flag */
+      hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex);
+
+      /* DMA peripheral state is not updated in Half Transfer */
+      /* but in Transfer Complete case */
+
+     if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Half transfer callback */
+        hdma->XferHalfCpltCallback(hdma);
+      }
+  }
+  
+  /* Transfer Complete Interrupt management ***********************************/
+  else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
+  {
+    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+    {
+      /* Disable the transfer complete and error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+    }
+    /* Clear the transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    if(hdma->XferCpltCallback != NULL)
+    {
+      /* Transfer complete callback */
+      hdma->XferCpltCallback(hdma);
+    }
+  }
+
+  /* Transfer Error Interrupt management **************************************/
+  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
+  {
+    /* When a DMA transfer error occurs */
+    /* A hardware clear of its EN bits is performed */
+    /* Disable ALL DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+    /* Update error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    if (hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+  return;
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Channel.
+  * @param  CallbackID:           User Callback identifer
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @param  pCallback:            pointer to private callbacsk function which has pointer to 
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */                          
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+     case  HAL_DMA_XFER_CPLT_CB_ID:
+           hdma->XferCpltCallback = pCallback;
+           break;
+       
+     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+           hdma->XferHalfCpltCallback = pCallback;
+           break;         
+
+     case  HAL_DMA_XFER_ERROR_CB_ID:
+           hdma->XferErrorCallback = pCallback;
+           break;         
+           
+     case  HAL_DMA_XFER_ABORT_CB_ID:
+           hdma->XferAbortCallback = pCallback;
+           break; 
+           
+     default:
+           status = HAL_ERROR;
+           break;                                                            
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  } 
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Channel.
+  * @param  CallbackID:           User Callback identifer
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */              
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+    /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+     case  HAL_DMA_XFER_CPLT_CB_ID:
+           hdma->XferCpltCallback = NULL;
+           break;
+       
+     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+           hdma->XferHalfCpltCallback = NULL;
+           break;         
+
+     case  HAL_DMA_XFER_ERROR_CB_ID:
+           hdma->XferErrorCallback = NULL;
+           break;         
+           
+     case  HAL_DMA_XFER_ABORT_CB_ID:
+           hdma->XferAbortCallback = NULL;
+           break; 
+     
+    case   HAL_DMA_XFER_ALL_CB_ID:
+           hdma->XferCpltCallback = NULL;
+           hdma->XferHalfCpltCallback = NULL;
+           hdma->XferErrorCallback = NULL;
+           hdma->XferAbortCallback = NULL;
+           break; 
+     
+    default:
+           status = HAL_ERROR;
+           break;                                                            
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  } 
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+  
+/**
+  * @}
+  */
+
+
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief    Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the DMA hande state.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  /* Return DMA handle state */
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Channel.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Clear all flags */
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+  
+  /* Configure DMA Channel data length */
+  hdma->Instance->CNDTR = DataLength;
+
+  /* Peripheral to Memory */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CPAR = DstAddress;
+
+    /* Configure DMA Channel source address */
+    hdma->Instance->CMAR = SrcAddress;
+  }
+  /* Memory to Peripheral */
+  else
+  {
+    /* Configure DMA Channel source address */
+    hdma->Instance->CPAR = SrcAddress;
+
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CMAR = DstAddress;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h
new file mode 100755
index 0000000..eedd7f6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h
@@ -0,0 +1,609 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dma.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DMA_H
+#define __STM32L4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
+                                           This parameter can be a value of @ref DMA_request */
+
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
+                                           from memory to memory or from peripheral to memory.
+                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
+                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
+                                           This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_mode
+                                           @note The circular buffer mode cannot be used if the memory-to-memory
+                                                 data transfer is configured on the selected Channel */
+
+  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                     */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+
+/** 
+  * @brief  HAL DMA Callback ID structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01,    /*!< Half transfer     */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02,    /*!< Error             */ 
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03,    /*!< Abort             */ 
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */ 
+    
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
+                                                                                
+  DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
+                                                                                
+  HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
+                                                                                
+  __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
+                                                                                
+  void                  *Parent;                                                     /*!< Parent object state                  */
+
+  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
+
+  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */
+
+  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
+
+  void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer abort callback          */  
+  
+  __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
+
+  DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
+  
+  uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */  
+}DMA_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error                              */
+#define HAL_DMA_ERROR_TE            ((uint32_t)0x00000001)    /*!< Transfer error                        */
+#define HAL_DMA_ERROR_NO_XFER       ((uint32_t)0x00000004)    /*!< no ongoing transfer                   */
+#define HAL_DMA_ERROR_TIMEOUT       ((uint32_t)0x00000020)    /*!< Timeout error                         */
+#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)    /*!< Not supported mode                    */     
+/**
+  * @}
+  */
+
+/** @defgroup DMA_request DMA request
+  * @{
+  */
+#define DMA_REQUEST_0                     ((uint32_t)0x00000000)
+#define DMA_REQUEST_1                     ((uint32_t)0x00000001)
+#define DMA_REQUEST_2                     ((uint32_t)0x00000002)
+#define DMA_REQUEST_3                     ((uint32_t)0x00000003)
+#define DMA_REQUEST_4                     ((uint32_t)0x00000004)
+#define DMA_REQUEST_5                     ((uint32_t)0x00000005)
+#define DMA_REQUEST_6                     ((uint32_t)0x00000006)
+#define DMA_REQUEST_7                     ((uint32_t)0x00000007)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @{
+  */
+#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
+#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @{
+  */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
+
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Channel transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
+   DMA_FLAG_TC7)
+
+/**
+  * @brief  Return the current DMA Channel half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
+   DMA_FLAG_HT7)
+
+/**
+  * @brief  Return the current DMA Channel transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
+   DMA_FLAG_TE7)
+
+/**
+  * @brief  Return the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
+   DMA_ISR_GIF7)
+
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be from 1 to 7 to select the DMA Channel x flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
+ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be from 1 to 7 to select the DMA Channel x flag.
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
+ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
+
+/**
+  * @brief  Enable the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+  * @param  __HANDLE__: DMA handle
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @{
+  */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
+                                     ((REQUEST) == DMA_REQUEST_1) || \
+                                     ((REQUEST) == DMA_REQUEST_2) || \
+                                     ((REQUEST) == DMA_REQUEST_3) || \
+                                     ((REQUEST) == DMA_REQUEST_4) || \
+                                     ((REQUEST) == DMA_REQUEST_5) || \
+                                     ((REQUEST) == DMA_REQUEST_6) || \
+                                     ((REQUEST) == DMA_REQUEST_7))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c
new file mode 100755
index 0000000..78d3776
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c
@@ -0,0 +1,1768 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dma2d.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DMA2D HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the DMA2D peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim 
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Program the required configuration through the following parameters:   
+          the transfer mode, the output color mode and the output offset using 
+          HAL_DMA2D_Init() function.
+
+      (#) Program the required configuration through the following parameters:   
+          the input color mode, the input color, the input alpha value, the alpha mode,
+          the red/blue swap mode, the inverted alpha mode and the input offset using 
+          HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
+          
+     *** Polling mode IO operation ***
+     =================================   
+    [..]        
+       (#) Configure pdata parameter (explained hereafter), destination and data length 
+           and enable the transfer using HAL_DMA2D_Start(). 
+       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
+           user can specify the value of timeout according to his end application.
+               
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..] 
+       (#) Configure pdata parameter, destination and data length and enable 
+           the transfer using HAL_DMA2D_Start_IT(). 
+       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
+       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can 
+           add his own function by customization of function pointer XferCpltCallback (member 
+           of DMA2D handle structure). 
+       (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback 
+           XferErrorCallback.            
+
+         -@-   In Register-to-Memory transfer mode, pdata parameter is the register
+               color, in Memory-to-memory or Memory-to-Memory with pixel format
+               conversion pdata is the source address.
+
+         -@-   Configure the foreground source address, the background source address, 
+               the destination and data length then Enable the transfer using 
+               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
+               in interrupt mode.
+               
+         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
+               are used if the memory to memory with blending transfer mode is selected.
+                   
+      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
+          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
+
+      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
+          
+      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two 
+          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
+          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
+          HAL_DMA2D_DisableDeadTime().          
+   
+      (#) The transfer can be suspended, resumed and aborted using the following
+          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
+          
+      (#) The CLUT loading can be suspended, resumed and aborted using the following
+          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), 
+          HAL_DMA2D_CLUTLoading_Abort().                
+                     
+      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().   
+      
+      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().                         
+
+     *** DMA2D HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DMA2D HAL driver :
+       
+      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
+      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
+      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
+      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.     
+     
+     [..] 
+      (@) You can refer to the DMA2D HAL driver header file for more useful macros
+                                  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA2D  DMA2D
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
+  * @{
+  */
+  
+/** @defgroup DMA2D_TimeOut DMA2D Time Out 
+  * @{
+  */  
+#define DMA2D_TIMEOUT_ABORT           ((uint32_t)1000)  /*!<  1s  */
+#define DMA2D_TIMEOUT_SUSPEND         ((uint32_t)1000)  /*!<  1s  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Shifts DMA2D Shifts 
+  * @{
+  */                                          
+#define DMA2D_POSITION_FGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS)    /*!< Required left shift to set foreground CLUT size */
+#define DMA2D_POSITION_BGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS)    /*!< Required left shift to set background CLUT size */
+                                                                                 
+#define DMA2D_POSITION_FGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM)   /*!< Required left shift to set foreground CLUT color mode */
+#define DMA2D_POSITION_BGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM)   /*!< Required left shift to set background CLUT color mode */
+                                                                                 
+#define DMA2D_POSITION_OPFCCR_AI      (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI)     /*!< Required left shift to set output alpha inversion     */
+#define DMA2D_POSITION_FGPFCCR_AI     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI)    /*!< Required left shift to set foreground alpha inversion */ 
+#define DMA2D_POSITION_BGPFCCR_AI     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI)    /*!< Required left shift to set background alpha inversion */ 
+
+#define DMA2D_POSITION_OPFCCR_RBS     (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS)    /*!< Required left shift to set output Red/Blue swap     */                                                                                 
+#define DMA2D_POSITION_FGPFCCR_RBS    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS)   /*!< Required left shift to set foreground Red/Blue swap */
+#define DMA2D_POSITION_BGPFCCR_RBS    (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS)   /*!< Required left shift to set background Red/Blue swap */
+                                                                                 
+#define DMA2D_POSITION_AMTCR_DT       (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT)      /*!< Required left shift to set deadtime value */
+                                                                                 
+#define DMA2D_POSITION_FGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM)    /*!< Required left shift to set foreground alpha mode */
+#define DMA2D_POSITION_BGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM)    /*!< Required left shift to set background alpha mode */
+
+#define DMA2D_POSITION_FGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
+#define DMA2D_POSITION_BGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
+
+#define DMA2D_POSITION_NLR_PL         (uint32_t)POSITION_VAL(DMA2D_NLR_PL)        /*!< Required left shift to set pixels per lines value */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
+  * @{
+  */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DMA2D
+      (+) De-initialize the DMA2D 
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Initialize the DMA2D according to the specified
+  *         parameters in the DMA2D_InitTypeDef and create the associated handle.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
+{ 
+  /* Check the DMA2D peripheral state */
+  if(hdma2d == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
+  assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
+  assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
+  assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+
+  if(hdma2d->State == HAL_DMA2D_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hdma2d->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_DMA2D_MspInit(hdma2d);
+  }
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;  
+
+  /* DMA2D CR register configuration -------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
+
+  /* DMA2D OPFCCR register configuration ---------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
+
+  /* DMA2D OOR register configuration ------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
+  
+  /* DMA2D OPFCCR RBS and AI fields setting */
+  MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), \
+  ((hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI)|(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS)));
+
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DMA2D peripheral registers to their default reset
+  *         values.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+  
+  /* Check the DMA2D peripheral state */
+  if(hdma2d == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Before aborting any DMA2D transfer or CLUT loading, check
+     first whether or not DMA2D clock is enabled */
+  if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
+  {
+    /* Abort DMA2D transfer if any */
+    if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
+    {
+      if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
+      {
+        /* Issue when aborting DMA2D transfer */       
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Abort background CLUT loading if any */
+      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+      {  
+        if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)        
+        {
+          /* Issue when aborting background CLUT loading */     
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Abort foreground CLUT loading if any */
+        if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+        {
+          if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)  
+          {
+            /* Issue when aborting foreground CLUT loading */     
+            return HAL_ERROR;
+          }        
+        }
+      }
+    }
+  }
+  
+  /* Reset DMA2D control registers*/
+  hdma2d->Instance->CR = 0;
+  hdma2d->Instance->IFCR = 0x3F;
+  hdma2d->Instance->FGOR = 0;
+  hdma2d->Instance->BGOR = 0;
+  hdma2d->Instance->FGPFCCR = 0;
+  hdma2d->Instance->BGPFCCR = 0;
+  hdma2d->Instance->OPFCCR = 0;
+
+  /* Carry on with de-initialization of low level hardware */
+  HAL_DMA2D_MspDeInit(hdma2d);
+  
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+  
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DMA2D MSP.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspInit can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitializes the DMA2D MSP.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspDeInit can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
+ *  @brief   IO operation functions  
+ *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the pdata, destination address and data size then 
+          start the DMA2D transfer.
+      (+) Configure the source for foreground and background, destination address 
+          and data size then start a MultiBuffer DMA2D transfer.
+      (+) Configure the pdata, destination address and data size then 
+          start the DMA2D transfer with interrupt.
+      (+) Configure the source for foreground and background, destination address 
+          and data size then start a MultiBuffer DMA2D transfer with interrupt.
+      (+) Abort DMA2D transfer.
+      (+) Suspend DMA2D transfer.
+      (+) Resume DMA2D transfer. 
+      (+) Enable CLUT transfer.      
+      (+) Configure CLUT loading then start transfer in polling mode.
+      (+) Configure CLUT loading then start transfer in interrupt mode.
+      (+) Abort DMA2D CLUT loading.
+      (+) Suspend DMA2D CLUT loading.
+      (+) Resume DMA2D CLUT loading. 
+      (+) Poll for transfer complete.
+      (+) handle DMA2D interrupt request.
+      (+) Transfer watermark callback.
+      (+) CLUT Transfer Complete callback.
+        
+        
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA2D Transfer.
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.  
+  * @param  pdata:      Configure the source memory Buffer address if 
+  *                     Memory-to-Memory or Memory-to-Memory with pixel format 
+  *                     conversion mode is selected, or configure 
+  *                     the color value if Register-to-Memory mode is selected.
+  * @param  DstAddress: The destination memory Buffer address.
+  * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+  
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.  
+  * @param  pdata:      Configure the source memory Buffer address if 
+  *                     the Memory-to-Memory or Memory-to-Memory with pixel format 
+  *                     conversion mode is selected, or configure 
+  *                     the color value if Register-to-Memory mode is selected.
+  * @param  DstAddress: The destination memory Buffer address.
+  * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer.
+  * @param  hdma2d:      Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                      the configuration information for the DMA2D.  
+  * @param  SrcAddress1: The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2: The source memory Buffer address for the background layer.
+  * @param  DstAddress:  The destination memory Buffer address.
+  * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));  
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY; 
+
+  /* Configure DMA2D Stream source2 address */
+  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.  
+  * @param  SrcAddress1: The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2: The source memory Buffer address for the background layer.
+  * @param  DstAddress:  The destination memory Buffer address.
+  * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).         
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ 
+  /* Configure DMA2D Stream source2 address */
+  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+  
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+  
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D Transfer.
+  * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t tickstart = 0;
+
+  /* Abort the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing ‘0’ has no 
+     effect on START bitvalue). */
+   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DMA2D is effectively disabled */
+  while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+      
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+      
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);  
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);  
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D Transfer.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D. 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t tickstart = 0;
+
+  /* Suspend the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing ‘0’ has no 
+     effect on START bitvalue). */
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DMA2D is effectively suspended */
+  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
+    && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
+  {
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+      
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
+   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+  {    
+    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+  }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless 
+       when no tranfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D Transfer.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Check the SUSP and START bits */
+  if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
+  {
+    /* Ongoing transfer is suspended: change the DMA2D state before resuming */
+    hdma2d->State = HAL_DMA2D_STATE_BUSY;
+  }
+
+  /* Resume the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing ‘0’ has no 
+     effect on START bitvalue). */
+  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));  
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Enable the DMA2D CLUT Transfer.
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{  
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;  
+  
+  if(LayerIdx == 0)
+  {
+    /* Enable the background CLUT loading */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  else
+  {
+    /* Enable the foreground CLUT loading */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);    
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Start DMA2D CLUT Loading.
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().                    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));   
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;   
+    
+  /* Configure the CLUT of the background DMA2D layer */
+  if(LayerIdx == 0)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+    
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), 
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+    
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), 
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));       
+    
+ /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  
+  }
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading with interrupt enabled.
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));   
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;   
+    
+  /* Configure the CLUT of the background DMA2D layer */
+  if(LayerIdx == 0)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+    
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), 
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+            
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);            
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+    
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), 
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+            
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);                   
+    
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  
+  }
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D CLUT loading.
+  * @param  hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart  = 0;
+  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+  uint32_t mask       = DMA2D_BGPFCCR_START;           /* by default, set to background constant   */
+  
+
+  /* Abort the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
+  
+  /* If foreground CLUT loading is considered, update local variables */ 
+  if(LayerIdx == 1)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }
+
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 
+  /* Check if the CLUT loading is aborted */          
+  while((*reg & mask) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+      
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+      
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);      
+   
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+     
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D CLUT loading.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D. 
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart = 0;
+  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+  uint32_t mask       = DMA2D_BGPFCCR_START;           /* by default, set to background constant   */
+  
+
+  /* Suspend the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); 
+  
+  /* If foreground CLUT loading is considered, update local variables */ 
+  if(LayerIdx == 1)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }   
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  /* Check if the CLUT loading is suspended */
+  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
+    && ((*reg & mask) == mask))
+  {
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+      
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
+   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((*reg & mask) != RESET)
+  {    
+    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+  }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless 
+       when no tranfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }  
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D CLUT loading.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D. 
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)      
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the SUSP and START bits for background or foreground CLUT loading */
+  if(LayerIdx == 0)
+  {  
+    /* Background CLUT loading suspension check */
+    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+      && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+    {
+      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+      hdma2d->State = HAL_DMA2D_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* Foreground CLUT loading suspension check */
+    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+      && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
+    {
+      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+      hdma2d->State = HAL_DMA2D_STATE_BUSY;
+    }  
+  }
+
+  /* Resume the CLUT loading */
+  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);  
+
+  return HAL_OK;
+}
+
+
+/**
+
+  * @brief  Polling for transfer complete or CLUT loading.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D. 
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+  __IO uint32_t isrflags = 0x0;  
+
+  /* Polling for DMA2D transfer */
+  if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+  {
+   /* Get tick */
+   tickstart = HAL_GetTick();
+
+    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
+    {
+      isrflags = READ_REG(hdma2d->Instance->ISR); 
+      if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+      {
+        if ((isrflags & DMA2D_FLAG_CE) != RESET)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;        
+        }
+        if ((isrflags & DMA2D_FLAG_TE) != RESET)        
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;        
+        }
+        /* Clear the transfer and configuration error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+        /* Change DMA2D state */
+        hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+        
+        return HAL_ERROR;
+      }
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+        {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+          /* Change the DMA2D state */
+          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+         
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+           
+          return HAL_TIMEOUT;
+        }
+      }        
+    }
+  }
+  /* Polling for CLUT loading (foreground or background) */
+  if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET)  || 
+      ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+   
+    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
+    {
+      isrflags = READ_REG(hdma2d->Instance->ISR);   
+      if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)        
+      {      
+        if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;        
+        }   
+        if ((isrflags & DMA2D_FLAG_CE) != RESET)             
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;        
+        }
+        if ((isrflags & DMA2D_FLAG_TE) != RESET)        
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;        
+        }
+        /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+        
+        /* Change DMA2D state */
+        hdma2d->State= HAL_DMA2D_STATE_ERROR;
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+          
+        return HAL_ERROR;      
+      }      
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+        {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+    
+          /* Change the DMA2D state */
+          hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+        
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+                    
+          return HAL_TIMEOUT;
+        }
+      }      
+    }
+  }
+
+  /* Clear the transfer complete and CLUT loading flags */
+  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
+  
+  /* Change DMA2D state */
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+  
+  return HAL_OK;
+}
+/**
+  * @brief  Handle DMA2D interrupt request.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.  
+  * @retval HAL status
+  */
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
+  uint32_t crflags = READ_REG(hdma2d->Instance->CR);
+        
+  /* Transfer Error Interrupt management ***************************************/
+  if ((isrflags & DMA2D_FLAG_TE) != RESET)
+  {
+    if ((crflags & DMA2D_IT_TE) != RESET)    
+    {
+      /* Disable the transfer Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);  
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+    
+      /* Clear the transfer error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      if(hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* Configuration Error Interrupt management **********************************/
+  if ((isrflags & DMA2D_FLAG_CE) != RESET)
+  {
+    if ((crflags & DMA2D_IT_CE) != RESET)    
+    {  
+      /* Disable the Configuration Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
+  
+      /* Clear the Configuration error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;    
+    
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      if(hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* CLUT access Error Interrupt management ***********************************/
+  if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+  {
+    if ((crflags & DMA2D_IT_CAE) != RESET)    
+    {    
+      /* Disable the CLUT access error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
+  
+      /* Clear the CLUT access error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;    
+    
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      if(hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }  
+  /* Transfer watermark Interrupt management **********************************/
+  if ((isrflags & DMA2D_FLAG_TW) != RESET)
+  {
+    if ((crflags & DMA2D_IT_TW) != RESET)    
+    {    
+      /* Disable the transfer watermark interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
+  
+      /* Clear the transfer watermark flag */  
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
+
+      /* Transfer watermark Callback */
+      HAL_DMA2D_LineEventCallback(hdma2d);
+    }
+  }  
+  /* Transfer Complete Interrupt management ************************************/
+  if ((isrflags & DMA2D_FLAG_TC) != RESET)
+  {
+    if ((crflags & DMA2D_IT_TC) != RESET)    
+    {   
+      /* Disable the transfer complete interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
+  
+      /* Clear the transfer complete flag */  
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    
+    
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_READY;
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      if(hdma2d->XferCpltCallback != NULL)
+      {
+        /* Transfer complete Callback */
+        hdma2d->XferCpltCallback(hdma2d);
+      }         
+    }
+  }
+  /* CLUT Transfer Complete Interrupt management ******************************/
+  if ((isrflags & DMA2D_FLAG_CTC) != RESET)
+  {
+    if ((crflags & DMA2D_IT_CTC) != RESET)    
+    {    
+      /* Disable the CLUT transfer complete interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
+  
+      /* Clear the CLUT transfer complete flag */  
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    
+    
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_READY;
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      /* CLUT Transfer complete Callback */
+      HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);         
+    }
+  }  
+  
+}
+
+/**
+  * @brief  Transfer watermark callback.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+  
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_LineEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  CLUT Transfer Complete callback.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+  
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
+   */
+} 
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the DMA2D foreground or background layer parameters.
+      (+) Configure the DMA2D CLUT transfer.
+      (+) Configure the line watermark
+      (+) Configure the dead time value.
+      (+) Enable or disable the dead time value functionality.      
+          
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DMA2D Layer according to the specified
+  *         parameters in the DMA2D_HandleTypeDef.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{   
+  DMA2D_LayerCfgTypeDef *LayerCfg = &hdma2d->LayerCfg[LayerIdx];
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));  
+  assert_param(IS_DMA2D_OFFSET(LayerCfg->InputOffset));  
+  if(hdma2d->Init.Mode != DMA2D_R2M)
+  {  
+    assert_param(IS_DMA2D_INPUT_COLOR_MODE(LayerCfg->InputColorMode));
+    if(hdma2d->Init.Mode != DMA2D_M2M)
+    {
+      assert_param(IS_DMA2D_ALPHA_MODE(LayerCfg->AlphaMode));
+    }
+  }
+  assert_param(IS_DMA2D_ALPHA_INVERTED(LayerCfg->AlphaInverted)); 
+  assert_param(IS_DMA2D_RB_SWAP(LayerCfg->RedBlueSwap));     
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;   
+  
+  /* Configure the background DMA2D layer */
+  if(LayerIdx == 0)
+  {
+    /* DMA2D BGPFCR register configuration -----------------------------------*/
+    /* Prepare the value to be written to the BGPFCCR register */
+    if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {
+      tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (LayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA));
+    }
+    else
+    {
+      tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (LayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA));
+    }
+    
+    /* Write DMA2D BGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS), \
+              (tmp | (LayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI) |(LayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS)));
+
+              
+    /* DMA2D BGOR register configuration -------------------------------------*/  
+    WRITE_REG(hdma2d->Instance->BGOR, LayerCfg->InputOffset);
+    
+    /* DMA2D BGCOLR register configuration -------------------------------------*/ 
+    if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {    
+      WRITE_REG(hdma2d->Instance->BGCOLR, LayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
+    }    
+  }
+  /* Configure the foreground DMA2D layer */
+  else
+  {
+    /* DMA2D FGPFCR register configuration -----------------------------------*/   
+    /* Prepare the value to be written to the FGPFCCR register */     
+    if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {
+      tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_FGPFCCR_AM) | (LayerCfg->InputAlpha & DMA2D_FGPFCCR_ALPHA));
+    }
+    else
+    {
+      tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_FGPFCCR_AM) | (LayerCfg->InputAlpha << DMA2D_POSITION_FGPFCCR_ALPHA));
+    }
+    
+    /* Write DMA2D FGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_RBS), \
+              (tmp | (LayerCfg->AlphaInverted << DMA2D_POSITION_FGPFCCR_AI) |(LayerCfg->RedBlueSwap << DMA2D_POSITION_FGPFCCR_RBS)));
+
+    
+    /* DMA2D FGOR register configuration -------------------------------------*/
+    WRITE_REG(hdma2d->Instance->FGOR, LayerCfg->InputOffset);      
+   
+    /* DMA2D FGCOLR register configuration -------------------------------------*/   
+    if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {
+      WRITE_REG(hdma2d->Instance->FGCOLR, LayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));      
+    }   
+  }    
+  /* Initialize the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMA2D CLUT Transfer.
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));   
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;     
+  
+  /* Configure the CLUT of the background DMA2D layer */
+  if(LayerIdx == 0)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+     
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), 
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));       
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+   /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+     
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), 
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));       
+  }
+  
+  /* Set the DMA2D state to Ready*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d); 
+    
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Configure the line watermark.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  Line:   Line Watermark configuration (maximum 16-bit long value expected).
+  * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
+  * @note   The transfer watermark interrupt is disabled once it has occurred.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINEWATERMARK(Line));
+  
+  if (Line > DMA2D_LWR_LW)
+  {
+    return HAL_ERROR;  
+  }
+  else
+  {      
+    /* Process locked */
+    __HAL_LOCK(hdma2d);
+    
+    /* Change DMA2D peripheral state */
+    hdma2d->State = HAL_DMA2D_STATE_BUSY;
+  
+    /* Sets the Line watermark configuration */
+    WRITE_REG(hdma2d->Instance->LWR, Line);
+    
+    /* Enable the Line interrupt */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
+        
+    /* Initialize the DMA2D state*/
+    hdma2d->State = HAL_DMA2D_STATE_READY;
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma2d);  
+    
+    return HAL_OK;
+  }  
+}
+
+/**
+  * @brief Enable DMA2D dead time feature.
+  * @param hdma2d: DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Set DMA2D_AMTCR EN bit */
+  SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable DMA2D dead time feature.
+  * @param hdma2d: DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Clear DMA2D_AMTCR EN bit */
+  CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure dead time.
+  * @note The dead time value represents the guaranteed minimum number of cycles between 
+  *       two consecutive transactions on the AHB bus.
+  * @param hdma2d: DMA2D handle.
+  * @param DeadTime: dead time value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);  
+  
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Set DMA2D_AMTCR DT field */
+  MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+
+/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+ *  @brief    Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to :
+      (+) Get the DMA2D state
+      (+) Get the DMA2D error code  
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Return the DMA2D state
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.  
+  * @retval HAL state
+  */
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
+{  
+  return hdma2d->State;
+}
+
+/**
+  * @brief  Return the DMA2D error code
+  * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+  *               the configuration information for DMA2D.
+  * @retval DMA2D Error Code
+  */
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
+{
+  return hdma2d->ErrorCode;
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+
+
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA2D transfer parameters.
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA2D.  
+  * @param  pdata:      The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  Width:      The width of data to be transferred from source to destination.
+  * @param  Height:     The height of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{  
+  uint32_t tmp = 0;
+  uint32_t tmp1 = 0;
+  uint32_t tmp2 = 0;
+  uint32_t tmp3 = 0;
+  uint32_t tmp4 = 0;
+    
+  /* Configure DMA2D data size */
+  MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); 
+  
+  /* Configure DMA2D destination address */
+  WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
+ 
+  /* Register to memory DMA2D mode selected */
+  if (hdma2d->Init.Mode == DMA2D_R2M)
+  {    
+    tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
+    tmp2 = pdata & DMA2D_OCOLR_RED_1;
+    tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
+    tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
+    
+    /* Prepare the value to be written to the OCOLR register according to the color mode */
+    if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
+    {
+      tmp = (tmp3 | tmp2 | tmp1| tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
+    {
+      tmp = (tmp3 | tmp2 | tmp4);  
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
+    {
+      tmp2 = (tmp2 >> 19);
+      tmp3 = (tmp3 >> 10);
+      tmp4 = (tmp4 >> 3 );
+      tmp  = ((tmp3 << 5) | (tmp2 << 11) | tmp4); 
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
+    { 
+      tmp1 = (tmp1 >> 31);
+      tmp2 = (tmp2 >> 19);
+      tmp3 = (tmp3 >> 11);
+      tmp4 = (tmp4 >> 3 );      
+      tmp  = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);    
+    } 
+    else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
+    {
+      tmp1 = (tmp1 >> 28);
+      tmp2 = (tmp2 >> 20);
+      tmp3 = (tmp3 >> 12);
+      tmp4 = (tmp4 >> 4 );
+      tmp  = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
+    }    
+    /* Write to DMA2D OCOLR register */
+    WRITE_REG(hdma2d->Instance->OCOLR, tmp);    
+  } 
+  else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
+  {
+    /* Configure DMA2D source address */
+  WRITE_REG(hdma2d->Instance->FGMAR, pdata);
+  }
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h
new file mode 100755
index 0000000..90f62da
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h
@@ -0,0 +1,619 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dma2d.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DMA2D HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DMA2D_H
+#define __STM32L4xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA2D DMA2D
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
+  * @{
+  */
+#define MAX_DMA2D_LAYER  2U
+
+/** 
+  * @brief DMA2D color Structure definition
+  */
+typedef struct
+{
+  uint32_t Blue;               /*!< Configures the blue value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Green;              /*!< Configures the green value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Red;                /*!< Configures the red value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+} DMA2D_ColorTypeDef;
+
+/** 
+  * @brief DMA2D CLUT Structure definition
+  */
+typedef struct
+{
+  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
+
+  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
+                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */
+
+  uint32_t Size;                    /*!< Configures the DMA2D CLUT size. 
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/** 
+  * @brief DMA2D Init structure definition
+  */
+typedef struct
+{
+  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
+                                                This parameter can be one value of @ref DMA2D_Mode. */
+
+  uint32_t             ColorMode;          /*!< Configures the color format of the output image.
+                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
+
+  uint32_t             OutputOffset;       /*!< Specifies the Offset value. 
+                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+                                                
+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+  
+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
+                                               for the output pixel format converter.
+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */                                                 
+} DMA2D_InitTypeDef;
+
+
+/** 
+  * @brief DMA2D Layer structure definition
+  */
+typedef struct
+{
+  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
+                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode. 
+                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
+
+  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode. 
+                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+
+  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. 
+                                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
+                                               @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between 
+                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 
+                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+                                               - InputAlpha[16:23] is the red value RED[0:7]
+                                               - InputAlpha[8:15] is the green value GREEN[0:7]
+                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */
+
+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+  
+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */
+
+} DMA2D_LayerCfgTypeDef;
+
+/** 
+  * @brief  HAL DMA2D State structures definition
+  */
+typedef enum
+{
+  HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
+  HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
+  HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
+}HAL_DMA2D_StateTypeDef;
+
+/** 
+  * @brief  DMA2D handle Structure definition
+  */
+typedef struct __DMA2D_HandleTypeDef
+{
+  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
+                                                                                                                                          
+  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
+
+  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
+                                                                                                                                           
+  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */                                                                                                                                             
+                                                                                                                                           
+  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters                    */
+
+  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */  
+                                                                                                                                           
+  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
+                                                                                                                                           
+  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */  
+} DMA2D_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Error_Code DMA2D Error Code
+  * @{
+  */
+#define HAL_DMA2D_ERROR_NONE        ((uint32_t)0x00000000U)  /*!< No error             */
+#define HAL_DMA2D_ERROR_TE          ((uint32_t)0x00000001U)  /*!< Transfer error       */
+#define HAL_DMA2D_ERROR_CE          ((uint32_t)0x00000002U)  /*!< Configuration error  */
+#define HAL_DMA2D_ERROR_CAE         ((uint32_t)0x00000004U)  /*!< CLUT access error    */
+#define HAL_DMA2D_ERROR_TIMEOUT     ((uint32_t)0x00000020U)  /*!< Timeout error        */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Mode DMA2D Mode 
+  * @{
+  */
+#define DMA2D_M2M                   ((uint32_t)0x00000000U)  /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 
+  * @{
+  */
+#define DMA2D_OUTPUT_ARGB8888       ((uint32_t)0x00000000U)               /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
+#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
+#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
+  * @{
+  */
+#define DMA2D_INPUT_ARGB8888        ((uint32_t)0x00000000U)  /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888          ((uint32_t)0x00000001U)  /*!< RGB888 color mode   */
+#define DMA2D_INPUT_RGB565          ((uint32_t)0x00000002U)  /*!< RGB565 color mode   */
+#define DMA2D_INPUT_ARGB1555        ((uint32_t)0x00000003U)  /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444        ((uint32_t)0x00000004U)  /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8              ((uint32_t)0x00000005U)  /*!< L8 color mode       */
+#define DMA2D_INPUT_AL44            ((uint32_t)0x00000006U)  /*!< AL44 color mode     */
+#define DMA2D_INPUT_AL88            ((uint32_t)0x00000007U)  /*!< AL88 color mode     */
+#define DMA2D_INPUT_L4              ((uint32_t)0x00000008U)  /*!< L4 color mode       */
+#define DMA2D_INPUT_A8              ((uint32_t)0x00000009U)  /*!< A8 color mode       */
+#define DMA2D_INPUT_A4              ((uint32_t)0x0000000AU)  /*!< A4 color mode       */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
+  * @{
+  */
+#define DMA2D_NO_MODIF_ALPHA        ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA         ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA         ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value
+                                                                with original alpha channel value                              */
+/**
+  * @}
+  */    
+
+/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
+  * @{
+  */
+#define DMA2D_REGULAR_ALPHA         ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
+#define DMA2D_INVERTED_ALPHA        ((uint32_t)0x00000001U)  /*!< Invert the alpha channel value */                                  
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
+  * @{
+  */
+#define DMA2D_RB_REGULAR            ((uint32_t)0x00000000U)  /*!< Select regular mode (RGB or ARGB) */
+#define DMA2D_RB_SWAP               ((uint32_t)0x00000001U)  /*!< Select swap mode (BGR or ABGR) */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
+  * @{
+  */
+#define DMA2D_CCM_ARGB8888          ((uint32_t)0x00000000U)  /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888            ((uint32_t)0x00000001U)  /*!< RGB888 DMA2D CLUT color mode   */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts 
+  * @{
+  */
+#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
+#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
+/**                                                         
+  * @}                                                      
+  */                                                        
+                                                            
+/** @defgroup DMA2D_Flags DMA2D Flags                       
+  * @{                                                      
+  */                                                        
+#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
+/**
+  * @}
+  */
+  
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
+/**
+  * @}
+  */
+  
+  
+/**
+  * @}
+  */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA2D handle state
+  * @param  __HANDLE__: specifies the DMA2D handle.
+  * @retval None
+  */
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+
+/**
+  * @brief  Enable the DMA2D.
+  * @param  __HANDLE__: DMA2D handle
+  * @retval None.
+  */
+#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DMA2D pending flags.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __FLAG__: flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag   
+  * @retval The state of FLAG.
+  */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+  * @brief  Clear the DMA2D pending flags.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag    
+  * @retval None
+  */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DMA2D interrupts.
+  * @param  __HANDLE__: DMA2D handle
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA2D interrupts.
+  * @param  __HANDLE__: DMA2D handle
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval The state of INTERRUPT source.
+  */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+     
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/  
+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */  
+  
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 
+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
+void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+  
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/  
+  
+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
+  * @{
+  */                         
+
+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 
+  * @{
+  */
+#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
+/**
+  * @}
+  */
+  
+/** @defgroup DMA2D_Color_Value DMA2D Color Value
+  * @{
+  */
+#define DMA2D_COLOR_VALUE                 ((uint32_t)0x000000FFU)  /*!< Color value mask */
+/**
+  * @}
+  */      
+
+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
+  * @{
+  */  
+#define DMA2D_MAX_LAYER         2         /*!< DMA2D maximum number of layers */  
+/**
+  * @}
+  */ 
+  
+/** @defgroup DMA2D_Offset DMA2D Offset 
+  * @{
+  */
+#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< Line Offset */
+/**
+  * @}
+  */ 
+  
+/** @defgroup DMA2D_Size DMA2D Size 
+  * @{
+  */
+#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D number of pixels per line */
+#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D number of lines           */
+/**
+  * @}
+  */    
+  
+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
+  * @{
+  */
+#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8)  /*!< DMA2D CLUT size */
+/**
+  * @}
+  */   
+    
+/**
+  * @}
+  */ 
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
+  * @{
+  */
+#define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= DMA2D_MAX_LAYER)
+#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
+                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
+#define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
+#define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
+                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
+                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_A4))
+#define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
+                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
+#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
+                                                 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
+
+#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
+                                   ((RB_Swap) == DMA2D_RB_SWAP))
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
+#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
+                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L496xx || STM32L4A6xx || */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DMA2D_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c
new file mode 100755
index 0000000..7f38588
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c
@@ -0,0 +1,308 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_firewall.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   FIREWALL HAL module driver.
+  *          This file provides firmware functions to manage the Firewall
+  *          Peripheral initialization and enabling.
+  *
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver ##### 
+ ===============================================================================
+  [..]
+    The FIREWALL HAL driver can be used as follows:
+              
+    (#) Declare a FIREWALL_InitTypeDef initialization structure.
+  
+    (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall
+
+    (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API
+    
+    (#) To ensure that any code executed outside the protected segment closes the
+        FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling 
+        __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment
+        or
+        HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment
+        after HAL_FIREWALL_Config() call.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FIREWALL FIREWALL 
+  * @brief HAL FIREWALL module driver
+  * @{
+  */
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup FIREWALL_Exported_Functions FIREWALL Exported Functions
+  * @{
+  */
+
+/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions 
+  * @brief    Initialization and Configuration Functions 
+  *
+@verbatim    
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides the functions allowing to initialize the Firewall.
+    Initialization is done by HAL_FIREWALL_Config(): 
+
+      (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro.
+           
+      (+) Set the protected code segment address start and length.
+          
+      (+) Set the protected non-volatile and/or volatile data segments 
+          address starts and lengths if applicable.          
+          
+      (+) Set the volatile data segment execution and sharing status.
+      
+      (+) Length must be set to 0 for an unprotected segment.      
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
+  * @param fw_init: Firewall initialization structure
+  * @note  The API returns HAL_ERROR if the Firewall is already enabled.     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
+{
+  /* Check the Firewall initialization structure allocation */
+  if(fw_init == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Enable Firewall clock */
+  __HAL_RCC_FIREWALL_CLK_ENABLE();
+
+  /* Make sure that Firewall is not enabled already */
+  if (__HAL_FIREWALL_IS_ENABLED() != RESET)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check Firewall configuration addresses and lengths when segment is protected */
+  /* Code segment */
+  if (fw_init->CodeSegmentLength != 0)
+  {
+    assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress));
+    assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength));  
+  }
+  /* Non volatile data segment */
+  if (fw_init->NonVDataSegmentLength != 0)
+  {
+    assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress));
+    assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength));  
+  }
+  /* Volatile data segment */
+  if (fw_init->VDataSegmentLength != 0)
+  {
+    assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress));
+    assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength));  
+  }
+  
+  /* Check Firewall Configuration Register parameters */
+  assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution));
+  assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared));
+  
+  
+   /* Configuration */
+  
+  /* Protected code segment start address configuration */
+  WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress));
+	/* Protected code segment length configuration */
+  WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength));
+  
+  /* Protected non volatile data segment start address configuration */
+  WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress));
+	/* Protected non volatile data segment length configuration */
+  WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength));
+  
+  /* Protected volatile data segment start address configuration */
+  WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress));
+	/* Protected volatile data segment length configuration */
+  WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));  
+  
+  /* Set Firewall Configuration Register VDE and VDS bits
+     (volatile data execution and shared configuration) */  
+  MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Retrieve the Firewall configuration.
+  * @param fw_config: Firewall configuration, type is same as initialization structure
+  * @note This API can't be executed inside a code area protected by the Firewall
+  *       when the Firewall is enabled
+  * @note If NVDSL register is different from 0, that is, if the non volatile data segment 
+  *       is defined, this API can't be executed when the Firewall is enabled.      
+  * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status            
+  * @retval None
+  */
+void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config)
+{
+
+  /* Enable Firewall clock, in case no Firewall configuration has been carried 
+     out up to this point */
+  __HAL_RCC_FIREWALL_CLK_ENABLE();
+
+  /* Retrieve code segment protection setting */
+  fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD);
+  fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG);
+  
+  /* Retrieve non volatile data segment protection setting */
+  fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD);
+  fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG);
+  
+  /* Retrieve volatile data segment protection setting */
+  fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD);
+  fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG);     
+  
+  /* Retrieve volatile data execution setting */
+  fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE);
+  
+  /* Retrieve volatile data shared setting */
+  fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS);
+  
+  return;
+}
+
+
+
+/**
+  * @brief Enable FIREWALL. 
+  * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register.
+  *       Once enabled, the Firewall cannot be disabled by software. Only a 
+  *       system reset can set again FWDIS bit.           
+  * @retval None
+  */
+void HAL_FIREWALL_EnableFirewall(void)
+{
+  /* Clears FWDIS bit of SYSCFG CFGR1 register */
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
+  
+}
+
+/**
+  * @brief Enable FIREWALL pre arm. 
+  * @note When FPA bit is set, any code executed outside the protected segment 
+  *       will close the Firewall. 
+  * @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro
+  *       but can't be executed inside a code area protected by the Firewall. 
+  * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.   
+  * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, 
+  *       when the non volatile data segment is not defined),
+  *        **  this API can be executed when the Firewall is closed
+  *        **  when the Firewall is opened, user should resort to 
+  *            __HAL_FIREWALL_PREARM_ENABLE() macro instead
+  * @note When the Firewall is enabled and  NVDSL register is different from 0
+  *       (that is, when the non volatile data segment is defined)
+  *       **  FW_CR register can be accessed only when the Firewall is opened: 
+  *           user should resort to  __HAL_FIREWALL_PREARM_ENABLE() macro instead.               
+  * @retval None
+  */
+void HAL_FIREWALL_EnablePreArmFlag(void)
+{
+  /* Set FPA bit */
+  SET_BIT(FIREWALL->CR, FW_CR_FPA);
+}
+
+
+/**
+  * @brief Disable FIREWALL pre arm.
+  * @note When FPA bit is reset, any code executed outside the protected segment 
+  *       when the Firewall is opened will generate a system reset.
+  * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro
+  *       but can't be executed inside a code area protected by the Firewall.
+  * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.   
+  * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, 
+  *       when the non volatile data segment is not defined),
+  *        **  this API can be executed when the Firewall is closed
+  *        **  when the Firewall is opened, user should resort to 
+  *            __HAL_FIREWALL_PREARM_DISABLE() macro instead
+  * @note When the Firewall is enabled and  NVDSL register is different from 0
+  *       (that is, when the non volatile data segment is defined)
+  *       **  FW_CR register can be accessed only when the Firewall is opened: 
+  *           user should resort to  __HAL_FIREWALL_PREARM_DISABLE() macro instead.               
+          
+  * @retval None
+  */
+void HAL_FIREWALL_DisablePreArmFlag(void)
+{
+  /* Clear FPA bit */
+  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h
new file mode 100755
index 0000000..77add8b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h
@@ -0,0 +1,372 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_firewall.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of FIREWALL HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_FIREWALL_H
+#define __STM32L4xx_HAL_FIREWALL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FIREWALL  FIREWALL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup FIREWALL_Exported_Types FIREWALL Exported Types
+  * @{
+  */ 
+
+/** 
+  * @brief FIREWALL Initialization Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CodeSegmentStartAddress;        /*!< Protected code segment start address. This value is 24-bit long, the 8 LSB bits are
+                                                reserved and forced to 0 in order to allow a 256-byte granularity. */
+
+  uint32_t CodeSegmentLength;              /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are 
+                                                reserved and forced to 0 for the length to be a multiple of 256 bytes. */
+
+  uint32_t NonVDataSegmentStartAddress;    /*!< Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB
+                                                bits are reserved and forced to 0 in order to allow a 256-byte granularity. */
+
+  uint32_t NonVDataSegmentLength;          /*!< Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB
+                                                bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */
+ 
+  uint32_t VDataSegmentStartAddress;       /*!< Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits
+                                                are reserved and forced to 0 in order to allow a 64-byte granularity. */
+
+  uint32_t VDataSegmentLength;             /*!< Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB
+                                                bits are reserved and forced to 0 for the length to be a multiple of 64 bytes. */
+  
+  uint32_t VolatileDataExecution;          /*!< Set VDE bit specifying whether or not the volatile data segment can be executed.
+                                                 When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning.
+                                                This parameter can be a value of @ref FIREWALL_VolatileData_Executable */  
+                                           
+  uint32_t VolatileDataShared;             /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a 
+                                                non-protected application code.
+                                                This parameter can be a value of @ref FIREWALL_VolatileData_Shared */  
+                                                                                                                                     
+}FIREWALL_InitTypeDef;
+
+
+/**
+  * @}
+  */
+
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FIREWALL_Exported_Constants FIREWALL Exported Constants
+  * @{
+  */
+
+/** @defgroup FIREWALL_VolatileData_Executable   FIREWALL volatile data segment execution status
+  * @{
+  */
+#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE                 ((uint32_t)0x0000)
+#define FIREWALL_VOLATILEDATA_EXECUTABLE                     ((uint32_t)FW_CR_VDE)
+/**
+  * @}
+  */ 
+
+/** @defgroup FIREWALL_VolatileData_Shared  FIREWALL volatile data segment share status
+  * @{
+  */ 
+#define FIREWALL_VOLATILEDATA_NOT_SHARED                ((uint32_t)0x0000)
+#define FIREWALL_VOLATILEDATA_SHARED                    ((uint32_t)FW_CR_VDS) 
+/**
+  * @}
+  */ 
+
+/** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status
+  * @{
+  */ 
+#define FIREWALL_PRE_ARM_RESET                 ((uint32_t)0x0000)
+#define FIREWALL_PRE_ARM_SET                   ((uint32_t)FW_CR_FPA)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Private macros --------------------------------------------------------*/
+/** @defgroup FIREWALL_Private_Macros   FIREWALL Private Macros
+  * @{
+  */
+#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))                                                   
+#define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
+
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))                                                   
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE)) 
+
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= SRAM1_BASE) && ((ADDRESS) < (SRAM1_BASE + SRAM1_SIZE_MAX)))
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX))                                                        
+    
+  
+#define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \
+                                               ((SHARE) == FIREWALL_VOLATILEDATA_SHARED))
+                                               
+#define IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE) (((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \
+                                                   ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE))                                                                                    
+/**
+  * @}
+  */  
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FIREWALL_Exported_Macros FIREWALL Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether the FIREWALL is enabled or not.
+  * @retval FIREWALL enabling status (TRUE or FALSE).
+  */            
+#define  __HAL_FIREWALL_IS_ENABLED()  HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS)  
+
+
+/** @brief Enable FIREWALL pre arm. 
+  * @note When FPA bit is set, any code executed outside the protected segment 
+  *       closes the Firewall, otherwise it generates a system reset.
+  * @note This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API
+  *       but can be executed inside a code area protected by the Firewall. 
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.    
+  */ 
+#define __HAL_FIREWALL_PREARM_ENABLE()                                         \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_FPA) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+
+                    
+/** @brief Disable FIREWALL pre arm. 
+  * @note When FPA bit is set, any code executed outside the protected segment 
+  *       closes the Firewall, otherwise, it generates a system reset.
+  * @note This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API
+  *       but can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  */ 
+#define __HAL_FIREWALL_PREARM_DISABLE()                                        \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Enable volatile data sharing in setting VDS bit. 
+  * @note When VDS bit is set, the volatile data segment is shared with non-protected
+  *       application code. It can be accessed whatever the Firewall state (opened or closed). 
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  */ 
+#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE()                            \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_VDS) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Disable volatile data sharing in resetting VDS bit. 
+  * @note When VDS bit is reset, the volatile data segment is not shared and cannot be 
+  *       hit by a non protected executable code when the Firewall is closed. If it is 
+  *       accessed in such a condition, a system reset is generated by the Firewall.
+  * @note This macro can be executed inside a code area protected by the Firewall. 
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.     
+  */ 
+#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE()                           \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Enable volatile data execution in setting VDE bit.
+  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be 
+  *       executed whatever the VDE bit value.  
+  * @note When VDE bit is set (with VDS = 0), the volatile data segment is executable. When
+  *       the Firewall call is closed, a "call gate" entry procedure is required to open 
+  *       first the Firewall.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.         
+  */ 
+#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE()                         \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_VDE) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Disable volatile data execution in resetting VDE bit.
+  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be 
+  *       executed whatever the VDE bit value.  
+  * @note When VDE bit is reset (with VDS = 0), the volatile data segment cannot  be executed.
+  * @note This macro can be executed inside a code area protected by the Firewall. 
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.        
+  */
+#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE()                           \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)   
+
+
+/** @brief Check whether or not the volatile data segment is shared.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  * @retval VDS bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
+
+/** @brief Check whether or not the volatile data segment is declared executable.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  * @retval VDE bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
+
+/** @brief Check whether or not the Firewall pre arm bit is set.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  * @retval FPA bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup FIREWALL_Exported_Functions FIREWALL Exported Functions
+  * @{
+  */
+  
+/** @addtogroup FIREWALL_Exported_Functions_Group1 Initialization Functions
+  * @brief    Initialization and Configuration Functions  
+  * @{
+  */  
+  
+/* Initialization functions  ********************************/
+HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init);
+void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config);
+void HAL_FIREWALL_EnableFirewall(void);
+void HAL_FIREWALL_EnablePreArmFlag(void);
+void HAL_FIREWALL_DisablePreArmFlag(void);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */   
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_FIREWALL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c
new file mode 100755
index 0000000..d95af67
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c
@@ -0,0 +1,825 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash.c
+  * @author  MCD Application Team
+  * @version V1.7.1 
+  * @date    21-April-2017
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions 
+  *           + Peripheral Errors functions
+  *  
+ @verbatim    
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+           
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
+       to the Flash memory. It implements the erase and program Flash memory operations 
+       and the read and write protection mechanisms.
+      
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines. 
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Prefetch on I-Code
+      (+) 32 cache lines of 4*64 bits on I-Code
+      (+) 8 cache lines of 4*64 bits on D-Code
+      (+) Error code correction (ECC) : Data in flash are 72-bits word
+          (8 bits added per double word)
+      
+      
+                        ##### How to use this driver #####
+ ==============================================================================
+    [..]                             
+      This driver provides functions and macros to configure and program the FLASH  
+      memory of all STM32L4xx devices. 
+   
+      (#) Flash Memory IO Programming functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Program functions: double word and fast program (full row programming)
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+    
+      (#) Interrupts and flags management functions : 
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_GetError()    
+           
+      (#) Option bytes management functions :
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
+                In this case, a reset is generated
+                         
+    [..] 
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache and the Data cache
+       (+) Reset the Instruction cache and the Data cache
+       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
+       (+) Enable/Disable the Flash interrupts
+       (+) Monitor the Flash flags status
+    
+ @endverbatim                      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define FLASH_NB_DOUBLE_WORDS_IN_ROW  32 
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/**
+  * @brief  Variable used for Program/Erase sectors under interruption 
+  */
+FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+HAL_StatusTypeDef    FLASH_WaitForLastOperation(uint32_t Timeout);
+extern void          FLASH_PageErase(uint32_t Page, uint32_t Banks);
+extern void          FLASH_FlushCaches(void);
+static void          FLASH_SetErrorCode(void);
+static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
+ *  @brief   Programming operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH 
+    program operations.
+ 
+@endverbatim
+  * @{
+  */
+ 
+/**
+  * @brief  Program double word or fast program of a row at a specified address.
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
+  *                This parameter is the data for the double word program and the address where 
+  *                are stored the data for the row fast program
+  * 
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t prog_bit = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+    /* Deactivate the data cache if they are activated to avoid data misbehavior */
+    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+    {
+      /* Disable data cache  */
+      __HAL_FLASH_DATA_CACHE_DISABLE();
+      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+    }
+    else
+    {
+      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+    }
+
+    if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+    {
+      /* Program double-word (64-bit) at a specified address */
+      FLASH_Program_DoubleWord(Address, Data);
+      prog_bit = FLASH_CR_PG;
+    }
+    else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+    {
+      /* Fast program a 32 row double-word (64-bit) at a specified address */
+      FLASH_Program_Fast(Address, (uint32_t)Data);
+      
+      /* If it is the last row, the bit will be cleared at the end of the operation */
+      if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+      {
+        prog_bit = FLASH_CR_FSTPG;
+      }
+    }
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+    
+    /* If the program operation is completed, disable the PG or FSTPG Bit */
+    if (prog_bit != 0)
+    {
+      CLEAR_BIT(FLASH->CR, prog_bit);
+    }
+
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches();
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;  
+}
+
+/**
+  * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
+  *                This parameter is the data for the double word program and the address where 
+  *                are stored the data for the row fast program
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Deactivate the data cache if they are activated to avoid data misbehavior */
+  if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+  {
+    /* Disable data cache  */
+    __HAL_FLASH_DATA_CACHE_DISABLE();
+    pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+  }
+  else
+  {
+    pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+  }
+
+  /* Set internal variables used by the IRQ handler */
+  if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+  {
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
+  }
+  else
+  {
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+  }
+  pFlash.Address = Address;
+    
+  /* Enable End of Operation and Error interrupts */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+  if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+  {
+    /* Program double-word (64-bit) at a specified address */
+    FLASH_Program_DoubleWord(Address, Data);
+  }
+  else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+  {
+    /* Fast program a 32 row double-word (64-bit) at a specified address */
+    FLASH_Program_Fast(Address, (uint32_t)Data);
+  }
+
+  return status;  
+}
+
+/**
+  * @brief Handle FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t tmp_page;
+
+  /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
+  CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
+#endif
+  
+  /* Disable the FSTPG Bit only if it is the last row programmed */
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
+  {
+    CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
+  }
+
+  /* Check FLASH operation error flags */
+  if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))   || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)))
+#else
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
+#endif
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches() ;
+
+    /* FLASH error interrupt user callback */
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
+    {
+       HAL_FLASH_OperationErrorCallback(pFlash.Page);
+    }
+    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
+    {
+        HAL_FLASH_OperationErrorCallback(pFlash.Bank);
+    }
+    else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || 
+            (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
+    {
+       HAL_FLASH_OperationErrorCallback(pFlash.Address);
+    }
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
+    {
+      /* Nb of pages to erased can be decreased */
+      pFlash.NbPagesToErase--;
+
+      /* Check if there are still pages to erase*/
+      if(pFlash.NbPagesToErase != 0)
+      {
+        /* Indicate user which page has been erased*/
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+
+        /* Increment page number */
+        pFlash.Page++;
+        tmp_page = pFlash.Page;
+        FLASH_PageErase(tmp_page, pFlash.Bank);
+      }
+      else
+      {
+        /* No more pages to Erase */
+        /* Reset Address and stop Erase pages procedure */
+        pFlash.Page = 0xFFFFFFFF;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+        
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+      }
+    }
+    else
+    {
+      /* Flush the caches to be sure of the data consistency */
+      FLASH_FlushCaches() ;
+
+      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
+      {
+        /* MassErase ended. Return the selected bank */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+      }
+      else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || 
+              (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+
+      /*Clear the procedure ongoing*/
+      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+    }
+  }
+
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+    /* Disable End of Operation and Error interrupts */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback.
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Page Erase: Page which has been erased 
+  *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback.
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Page Erase: Page number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief   Management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH 
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the FLASH control register access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Unlock the FLASH Option Bytes Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET)
+  {
+    /* Authorizes the Option Byte register programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Lock the FLASH Option Bytes Registers access.
+  * @retval HAL Status 
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the bit to force the option byte reloading */
+  SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); 
+
+  /* Wait for last operation to be completed */
+  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
+ *  @brief   Peripheral Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval FLASH_ErrorCode: The returned value can be:
+  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
+  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag 
+  *            @arg HAL_FLASH_ERROR_NONE: No error set 
+  *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error
+  *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
+  *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
+  *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
+  *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
+  *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
+  *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
+  *            @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
+  *            @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected
+  */
+uint32_t HAL_FLASH_GetError(void)
+{ 
+   return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout: maximum flash operation timeout
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+    
+  uint32_t timeout = HAL_GetTick() + Timeout;
+     
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
+  { 
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }
+    } 
+  }
+  
+  if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))   || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)))
+#else
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
+#endif
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    
+    return HAL_ERROR;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+  
+  /* If there is an error flag set */
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Set the specific FLASH error flag.
+  * @retval None
+  */
+static void FLASH_SetErrorCode(void)
+{  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OP;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD;
+  }
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY;
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PEMPTY);
+  }
+#endif
+  
+  /* Clear error programming flags */
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
+} 
+
+/**
+  * @brief  Program double-word (64-bit) at a specified address.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  /* Set PG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_PG);
+  
+  /* Program the double word */
+  *(__IO uint32_t*)Address = (uint32_t)Data;
+  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+}
+
+/**
+  * @brief  Fast program a row double-word (64-bit) at a specified address.
+  * @param  Address: specifies the address to be programmed.
+  * @param  DataAddress: specifies the address where the data are stored.
+  * @retval None
+  */
+static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
+{
+  uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);
+  __IO uint32_t *dest_addr = (__IO uint32_t*)Address;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
+
+  /* Set FSTPG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
+  
+  /* Disable interrupts to avoid any interruption during the loop */
+  __disable_irq();
+  
+  /* Program the double word of the row */
+  do
+  {
+    *dest_addr++ = *src_addr++;
+  } while (--row_index != 0);
+
+  /* Re-enable the interrupts */
+  __enable_irq();
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h
new file mode 100755
index 0000000..b74c513
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h
@@ -0,0 +1,939 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash.h
+  * @author  MCD Application Team
+  * @version V1.7.1 
+  * @date    21-April-2017
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_FLASH_H
+#define __STM32L4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{ 
+  uint32_t TypeErase;   /*!< Mass erase or page erase.
+                             This parameter can be a value of @ref FLASH_Type_Erase */
+  uint32_t Banks;       /*!< Select bank to erase.
+                             This parameter must be a value of @ref FLASH_Banks 
+                             (FLASH_BANK_BOTH should be used only for mass erase) */        
+  uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled
+                             This parameter must be a value between 0 and (max number of pages in the bank - 1) 
+                             (eg : 255 for 1MB dual bank) */
+  uint32_t NbPages;     /*!< Number of pages to be erased.
+                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/           
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a combination of the values of @ref FLASH_OB_Type */
+  uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
+                                Only one WRP area could be programmed at the same time.
+                                This parameter can be value of @ref FLASH_OB_WRP_Area */
+  uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
+                                This parameter must be a value between 0 and (max number of pages in the bank - 1)
+                                (eg : 25 for 1MB dual bank) */
+  uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).
+                                This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
+  uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
+                                This parameter can be a value of @ref FLASH_OB_Read_Protection */
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASH_OB_USER_Type */
+  uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+                                @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 
+                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 
+                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 
+                                @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 
+                                @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
+  uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
+                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 
+                                and @ref FLASH_OB_PCROP_RDP */
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between begin and end of bank 
+                                => Be careful of the bank swapping for the address */
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between PCROP Start address and end of bank */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum 
+{
+  FLASH_PROC_NONE = 0,
+  FLASH_PROC_PAGE_ERASE,
+  FLASH_PROC_MASS_ERASE,
+  FLASH_PROC_PROGRAM,
+  FLASH_PROC_PROGRAM_LAST
+} FLASH_ProcedureTypeDef;
+
+/**
+  * @brief  FLASH Cache structure definition
+  */
+typedef enum 
+{
+  FLASH_CACHE_DISABLED = 0,
+  FLASH_CACHE_ICACHE_ENABLED,
+  FLASH_CACHE_DCACHE_ENABLED,
+  FLASH_CACHE_ICACHE_DCACHE_ENABLED
+} FLASH_CacheTypeDef;
+
+/** 
+  * @brief  FLASH handle Structure definition  
+  */
+typedef struct
+{
+  HAL_LockTypeDef             Lock;              /* FLASH locking object */
+  __IO uint32_t               ErrorCode;         /* FLASH error code */
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
+  __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */
+  __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */
+  __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */
+  __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
+  __IO FLASH_CacheTypeDef     CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error FLASH Error
+  * @{
+  */ 
+#define HAL_FLASH_ERROR_NONE      ((uint32_t)0x00000000)
+#define HAL_FLASH_ERROR_OP        ((uint32_t)0x00000001)
+#define HAL_FLASH_ERROR_PROG      ((uint32_t)0x00000002)
+#define HAL_FLASH_ERROR_WRP       ((uint32_t)0x00000004)
+#define HAL_FLASH_ERROR_PGA       ((uint32_t)0x00000008)
+#define HAL_FLASH_ERROR_SIZ       ((uint32_t)0x00000010)
+#define HAL_FLASH_ERROR_PGS       ((uint32_t)0x00000020)
+#define HAL_FLASH_ERROR_MIS       ((uint32_t)0x00000040)
+#define HAL_FLASH_ERROR_FAST      ((uint32_t)0x00000080)
+#define HAL_FLASH_ERROR_RD        ((uint32_t)0x00000100)
+#define HAL_FLASH_ERROR_OPTV      ((uint32_t)0x00000200)
+#define HAL_FLASH_ERROR_ECCD      ((uint32_t)0x00000400)
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define HAL_FLASH_ERROR_PEMPTY    ((uint32_t)0x00000800)
+#endif 
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Erase FLASH Erase Type
+  * @{
+  */ 
+#define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)  /*!<Flash mass erase activation*/
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1              ((uint32_t)0x01)                          /*!< Bank 1   */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define FLASH_BANK_2              ((uint32_t)0x02)                          /*!< Bank 2   */
+#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
+#else
+#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1))                /*!< Bank 1   */
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASH_Type_Program FLASH Program Type
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD    ((uint32_t)0x00)  /*!<Program a double-word (64-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_FAST          ((uint32_t)0x01)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
+                                                                 And another 32 row double-word (64-bit) will be programmed */
+#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
+                                                                 And this is the last 32 row double-word (64-bit) programmed */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
+  * @{
+  */
+#define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!< WRP option byte configuration */
+#define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!< RDP option byte configuration */
+#define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP          ((uint32_t)0x08)  /*!< PCROP option byte configuration */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
+  * @{
+  */ 
+#define OB_WRPAREA_BANK1_AREAA    ((uint32_t)0x00)  /*!< Flash Bank 1 Area A */
+#define OB_WRPAREA_BANK1_AREAB    ((uint32_t)0x01)  /*!< Flash Bank 1 Area B */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define OB_WRPAREA_BANK2_AREAA    ((uint32_t)0x02)  /*!< Flash Bank 2 Area A */
+#define OB_WRPAREA_BANK2_AREAB    ((uint32_t)0x04)  /*!< Flash Bank 2 Area B */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0            ((uint32_t)0xAA)
+#define OB_RDP_LEVEL_1            ((uint32_t)0xBB)
+#define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 
+                                                        it's no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
+  * @{
+  */
+#define OB_USER_BOR_LEV           ((uint32_t)0x0001)                   /*!< BOR reset Level */
+#define OB_USER_nRST_STOP         ((uint32_t)0x0002)                   /*!< Reset generated when entering the stop mode */
+#define OB_USER_nRST_STDBY        ((uint32_t)0x0004)                   /*!< Reset generated when entering the standby mode */
+#define OB_USER_IWDG_SW           ((uint32_t)0x0008)                   /*!< Independent watchdog selection */
+#define OB_USER_IWDG_STOP         ((uint32_t)0x0010)                   /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY        ((uint32_t)0x0020)                   /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_WWDG_SW           ((uint32_t)0x0040)                   /*!< Window watchdog selection */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define OB_USER_BFB2              ((uint32_t)0x0080)                   /*!< Dual-bank boot */
+#define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
+#endif
+#define OB_USER_nBOOT1            ((uint32_t)0x0200)                   /*!< Boot configuration */
+#define OB_USER_SRAM2_PE          ((uint32_t)0x0400)                   /*!< SRAM2 parity check enable */
+#define OB_USER_SRAM2_RST         ((uint32_t)0x0800)                   /*!< SRAM2 Erase when system reset */
+#define OB_USER_nRST_SHDW         ((uint32_t)0x1000)                   /*!< Reset generated when entering the shutdown mode */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define OB_USER_nSWBOOT0          ((uint32_t)0x2000)                   /*!< Software BOOT0 */
+#define OB_USER_nBOOT0            ((uint32_t)0x4000)                   /*!< nBOOT0 option bit */
+#endif
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
+  * @{
+  */
+#define OB_BOR_LEVEL_0            ((uint32_t)FLASH_OPTR_BOR_LEV_0)     /*!< Reset level threshold is around 1.7V */
+#define OB_BOR_LEVEL_1            ((uint32_t)FLASH_OPTR_BOR_LEV_1)     /*!< Reset level threshold is around 2.0V */
+#define OB_BOR_LEVEL_2            ((uint32_t)FLASH_OPTR_BOR_LEV_2)     /*!< Reset level threshold is around 2.2V */
+#define OB_BOR_LEVEL_3            ((uint32_t)FLASH_OPTR_BOR_LEV_3)     /*!< Reset level threshold is around 2.5V */
+#define OB_BOR_LEVEL_4            ((uint32_t)FLASH_OPTR_BOR_LEV_4)     /*!< Reset level threshold is around 2.8V */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 
+  * @{
+  */
+#define OB_STOP_RST               ((uint32_t)0x0000)                   /*!< Reset generated when entering the stop mode */
+#define OB_STOP_NORST             ((uint32_t)FLASH_OPTR_nRST_STOP)     /*!< No reset generated when entering the stop mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
+  * @{
+  */
+#define OB_STANDBY_RST            ((uint32_t)0x0000)                   /*!< Reset generated when entering the standby mode */
+#define OB_STANDBY_NORST          ((uint32_t)FLASH_OPTR_nRST_STDBY)    /*!< No reset generated when entering the standby mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
+  * @{
+  */
+#define OB_SHUTDOWN_RST           ((uint32_t)0x0000)                   /*!< Reset generated when entering the shutdown mode */
+#define OB_SHUTDOWN_NORST         ((uint32_t)FLASH_OPTR_nRST_SHDW)     /*!< No reset generated when entering the shutdown mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
+  * @{
+  */
+#define OB_IWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware independent watchdog */
+#define OB_IWDG_SW                ((uint32_t)FLASH_OPTR_IWDG_SW)       /*!< Software independent watchdog */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE       ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Stop mode */
+#define OB_IWDG_STOP_RUN          ((uint32_t)FLASH_OPTR_IWDG_STOP)     /*!< Independent watchdog counter is running in Stop mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Standby mode */
+#define OB_IWDG_STDBY_RUN         ((uint32_t)FLASH_OPTR_IWDG_STDBY)    /*!< Independent watchdog counter is running in Standby mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
+  * @{
+  */
+#define OB_WWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware window watchdog */
+#define OB_WWDG_SW                ((uint32_t)FLASH_OPTR_WWDG_SW)       /*!< Software window watchdog */
+/**
+  * @}
+  */ 
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
+  * @{
+  */
+#define OB_BFB2_DISABLE           ((uint32_t)0x000000)                 /*!< Dual-bank boot disable */
+#define OB_BFB2_ENABLE            ((uint32_t)FLASH_OPTR_BFB2)          /*!< Dual-bank boot enable */
+/**
+  * @}
+  */ 
+/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
+  * @{
+  */
+#define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 256 KB/512 KB Single-bank Flash */
+#define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DUALBANK)      /*!< 256 KB/512 KB Dual-bank Flash */
+/**
+  * @}
+  */ 
+#endif
+
+/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
+  * @{
+  */
+#define OB_BOOT1_SRAM             ((uint32_t)0x000000)                 /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
+#define OB_BOOT1_SYSTEM           ((uint32_t)FLASH_OPTR_nBOOT1)        /*!< System memory is selected as boot space (if BOOT0=1) */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
+  * @{
+  */
+#define OB_SRAM2_PARITY_ENABLE    ((uint32_t)0x0000000)                /*!< SRAM2 parity check enable */
+#define OB_SRAM2_PARITY_DISABLE   ((uint32_t)FLASH_OPTR_SRAM2_PE)      /*!< SRAM2 parity check disable */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
+  * @{
+  */
+#define OB_SRAM2_RST_ERASE        ((uint32_t)0x0000000)                /*!< SRAM2 erased when a system reset occurs */
+#define OB_SRAM2_RST_NOT_ERASE    ((uint32_t)FLASH_OPTR_SRAM2_RST)     /*!< SRAM2 is not erased when a system reset occurs */
+/**
+  * @}
+  */ 
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+/** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
+  * @{
+  */
+#define OB_BOOT0_FROM_OB          ((uint32_t)0x0000000)                /*!< BOOT0 taken from the option bit nBOOT0 */
+#define OB_BOOT0_FROM_PIN         ((uint32_t)FLASH_OPTR_nSWBOOT0)      /*!< BOOT0 taken from PH3/BOOT0 pin */
+/**
+  * @}
+  */ 
+
+/** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
+  * @{
+  */
+#define OB_BOOT0_RESET            ((uint32_t)0x0000000)                /*!< nBOOT0 = 0 */
+#define OB_BOOT0_SET              ((uint32_t)FLASH_OPTR_nBOOT0)        /*!< nBOOT0 = 1 */
+/**
+  * @}
+  */ 
+#endif
+
+/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
+  * @{
+  */
+#define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level 
+                                                                            is decreased from Level 1 to Level 0 */
+#define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 
+                                                                            decreased from Level 1 to Level 0 (full mass erase) */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */ 
+#define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS                /*!< FLASH Zero wait state */
+#define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS                /*!< FLASH One wait state */
+#define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS                /*!< FLASH Two wait states */
+#define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS                /*!< FLASH Three wait states */
+#define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS                /*!< FLASH Four wait states */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */ 
+#define FLASH_KEY1                ((uint32_t)0x45670123U)               /*!< Flash key1 */
+#define FLASH_KEY2                ((uint32_t)0xCDEF89ABU)               /*!< Flash key2: used with FLASH_KEY1 
+                                                                            to unlock the FLASH registers access */
+
+#define FLASH_PDKEY1              ((uint32_t)0x04152637U)               /*!< Flash power down key1 */
+#define FLASH_PDKEY2              ((uint32_t)0xFAFBFCFDU)               /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                                            to unlock the RUN_PD bit in FLASH_ACR */
+
+#define FLASH_OPTKEY1             ((uint32_t)0x08192A3BU)               /*!< Flash option byte key1 */
+#define FLASH_OPTKEY2             ((uint32_t)0x4C5D6E7FU)               /*!< Flash option byte key2: used with FLASH_OPTKEY1 
+                                                                            to allow option bytes operations */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags FLASH Flags Definition
+  * @{
+  */ 
+#define FLASH_FLAG_EOP            FLASH_SR_EOP                         /*!< FLASH End of operation flag */
+#define FLASH_FLAG_OPERR          FLASH_SR_OPERR                       /*!< FLASH Operation error flag */
+#define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR                     /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR                      /*!< FLASH Write protection error flag */
+#define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR                      /*!< FLASH Programming alignment error flag */
+#define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR                      /*!< FLASH Size error flag  */
+#define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR                      /*!< FLASH Programming sequence error flag */
+#define FLASH_FLAG_MISERR         FLASH_SR_MISERR                      /*!< FLASH Fast programming data miss error flag */
+#define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR                     /*!< FLASH Fast programming error flag */
+#define FLASH_FLAG_RDERR          FLASH_SR_RDERR                       /*!< FLASH PCROP read error flag */
+#define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR                     /*!< FLASH Option validity error flag  */
+#define FLASH_FLAG_BSY            FLASH_SR_BSY                         /*!< FLASH Busy flag */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define FLASH_FLAG_PEMPTY         FLASH_SR_PEMPTY                      /*!< FLASH Program empty */
+#endif
+#define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC                      /*!< FLASH ECC correction */
+#define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD                      /*!< FLASH ECC detection */
+
+#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
+                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
+                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
+                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */ 
+#define FLASH_IT_EOP              FLASH_CR_EOPIE                       /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_OPERR            FLASH_CR_ERRIE                       /*!< Error Interrupt source */
+#define FLASH_IT_RDERR            FLASH_CR_RDERRIE                     /*!< PCROP Read Error Interrupt source*/
+#define FLASH_IT_ECCC             (FLASH_ECCR_ECCIE >> 24)             /*!< ECC Correction Interrupt source */
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ *  @brief macros to control FLASH features 
+ *  @{
+ */
+
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__: FLASH Latency                   
+  *         This parameter can be one of the following values :
+  *     @arg FLASH_LATENCY_0: FLASH Zero wait state
+  *     @arg FLASH_LATENCY_1: FLASH One wait state    
+  *     @arg FLASH_LATENCY_2: FLASH Two wait states
+  *     @arg FLASH_LATENCY_3: FLASH Three wait states
+  *     @arg FLASH_LATENCY_4: FLASH Four wait states
+  * @retval None
+  */ 
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency                   
+  *         This parameter can be one of the following values :
+  *     @arg FLASH_LATENCY_0: FLASH Zero wait state
+  *     @arg FLASH_LATENCY_1: FLASH One wait state    
+  *     @arg FLASH_LATENCY_2: FLASH Two wait states
+  *     @arg FLASH_LATENCY_3: FLASH Three wait states
+  *     @arg FLASH_LATENCY_4: FLASH Four wait states
+  */ 
+#define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
+
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval None
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval None
+  */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Enable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+  * @brief  Disable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+  * @brief  Enable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+  * @brief  Disable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+  * @brief  Reset the FLASH instruction Cache.
+  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
+                                                   } while (0)
+
+/**
+  * @brief  Reset the FLASH data Cache.
+  * @note   This function must be used only when the data Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
+                                                   } while (0)
+
+/**
+  * @brief  Enable the FLASH power down during Low-power run mode.
+  * @note   Writing this bit  to 0 this bit, automatically the keys are
+  *         loss and a new unlock sequence is necessary to re-write it to 1.
+  */
+#define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
+                                                   } while (0)
+
+/**
+  * @brief  Disable the FLASH power down during Low-power run mode.
+  * @note   Writing this bit  to 0 this bit, automatically the keys are
+  *         loss and a new unlock sequence is necessary to re-write it to 1.
+  */
+#define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
+                                                   } while (0)
+
+/**
+  * @brief  Enable the FLASH power down during Low-Power sleep mode
+  * @retval none
+  */ 
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+  * @brief  Disable the FLASH power down during Low-Power sleep mode
+  * @retval none
+  */ 
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+  * @}
+  */  
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
+ *  @brief macros to handle FLASH interrupts
+ * @{
+ */ 
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__: FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_OPERR: Error Interrupt    
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
+  * @retval none
+  */  
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+                                                   } while(0)
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__: FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_OPERR: Error Interrupt    
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
+  * @retval none
+  */  
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+                                                   } while(0)
+
+/**
+  * @brief  Check whether the specified FLASH flag is set or not.
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
+  *     @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)          (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
+                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
+                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
+
+/**
+  * @brief  Clear the FLASH's pending flags.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+  *     @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
+  * @retval None
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
+                                                     if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
+                                                   } while(0)
+/**
+  * @}
+  */  
+
+/* Include FLASH HAL Extended module */
+#include "stm32l4xx_hal_flash_ex.h"
+#include "stm32l4xx_hal_flash_ramfunc.h"
+
+/* Exported functions --------------------------------------------------------*/ 
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+
+/* Program operation functions  ***********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void               HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */ 
+void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef  HAL_FLASH_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+uint32_t HAL_FLASH_GetError(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+#define FLASH_SIZE_DATA_REGISTER           ((uint32_t)0x1FFF75E0)
+    
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define FLASH_SIZE                         ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \
+                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
+#else
+#define FLASH_SIZE                         ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
+                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
+#endif
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define FLASH_BANK_SIZE                    (FLASH_SIZE >> 1)
+#else
+#define FLASH_BANK_SIZE                    (FLASH_SIZE)
+#endif
+
+#define FLASH_PAGE_SIZE                    ((uint32_t)0x800)
+
+#define FLASH_TIMEOUT_VALUE                ((uint32_t)50000)/* 50 s */
+/**
+  * @}
+  */
+ 
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ *  @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2)  || \
+                                            ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2))
+#else
+#define IS_FLASH_BANK(BANK)                ((BANK) == FLASH_BANK_1)
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      ((BANK) == FLASH_BANK_1)
+#endif
+
+#define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))  
+
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE)        && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) 
+
+#define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
+                                            ((PAGE) < 256)))))
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
+                                            ((PAGE) < 256))))
+#else
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80)  ? ((PAGE) < 64) : \
+                                            ((PAGE) < 128))))
+#endif
+
+#define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
+                                            ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
+#else
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
+#endif
+
+#define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                            ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
+                                            ((LEVEL) == OB_RDP_LEVEL_2)*/)
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
+#else
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
+#endif
+
+#define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
+                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
+                                            ((LEVEL) == OB_BOR_LEVEL_4))
+
+#define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
+
+#define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
+
+#define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
+
+#define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
+
+#define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
+
+#define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
+
+#define IS_OB_USER_DUALBANK(VALUE)         (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
+#endif
+
+#define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
+
+#define IS_OB_USER_SRAM2_PARITY(VALUE)     (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
+
+#define IS_OB_USER_SRAM2_RST(VALUE)        (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_OB_USER_SWBOOT0(VALUE)          (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
+
+#define IS_OB_USER_BOOT0(VALUE)            (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))
+#endif
+
+#define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
+
+#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || \
+                                            ((LATENCY) == FLASH_LATENCY_1) || \
+                                            ((LATENCY) == FLASH_LATENCY_2) || \
+                                            ((LATENCY) == FLASH_LATENCY_3) || \
+                                            ((LATENCY) == FLASH_LATENCY_4))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c
new file mode 100755
index 0000000..bd6efe7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c
@@ -0,0 +1,1148 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1 
+  * @date    21-April-2017
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH extended peripheral:
+  *           + Extended programming operations functions
+  *  
+ @verbatim    
+ ==============================================================================
+                   ##### Flash Extended features #####
+  ==============================================================================
+           
+  [..] Comparing to other previous devices, the FLASH interface for STM32L4xx 
+       devices contains the following additional features 
+       
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization       
+       (+) PCROP protection for all banks
+   
+                        ##### How to use this driver #####
+ ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory 
+       of all STM32L4xx devices. It includes
+      (#) Flash Memory Erase functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Erase page, erase all sectors
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+                         
+      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
+        (++) Set/Reset the write protection
+        (++) Set the Read protection Level
+        (++) Program the user Option Bytes
+        (++) Configure the PCROP protection
+        
+      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
+        (++) Get the value of a write protection area
+        (++) Know if the read protection is activated
+        (++) Get the value of the user Option Bytes
+        (++) Get the value of a PCROP area
+    
+ @endverbatim                      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx FLASHEx
+  * @brief FALSH Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
+ * @{
+ */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+void                     FLASH_PageErase(uint32_t Page, uint32_t Banks);
+static void              FLASH_MassErase(uint32_t Banks);
+void                     FLASH_FlushCaches(void);
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
+static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
+static uint32_t          FLASH_OB_GetRDP(void);
+static uint32_t          FLASH_OB_GetUser(void);
+static void              FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
+/**
+  * @}
+  */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
+  * @{
+  */ 
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extended FLASH 
+    programming operations Operations.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages.
+  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @param[out]  PageError  : pointer to variable that contains the configuration 
+  *         information on faulty page in case of error (0xFFFFFFFF means that all 
+  *         the pages have been correctly erased)
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t page_index = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+    /* Deactivate the cache if they are activated to avoid data misbehavior */
+    if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
+    {
+      /* Disable instruction cache  */
+      __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+
+      if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+      {
+        /* Disable data cache  */
+        __HAL_FLASH_DATA_CACHE_DISABLE();
+        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+      }
+      else
+      {
+        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+      }
+    }
+    else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+    {
+      /* Disable data cache  */
+      __HAL_FLASH_DATA_CACHE_DISABLE();
+      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+    }
+    else
+    {
+      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+    }
+
+    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /* Mass erase to be done */
+      FLASH_MassErase(pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+      /* If the erase operation is completed, disable the MER1 and MER2 Bits */
+      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+#else
+      /* If the erase operation is completed, disable the MER1 Bit */
+      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
+#endif      
+    }
+    else
+    {
+      /*Initialization of PageError variable*/
+      *PageError = 0xFFFFFFFF;
+      
+      for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
+      {
+        FLASH_PageErase(page_index, pEraseInit->Banks);
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+        /* If the erase operation is completed, disable the PER Bit */
+        CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
+
+        if (status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty address */
+          *PageError = page_index;
+          break;
+        }
+      }
+    }
+    
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches();
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
+  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Deactivate the cache if they are activated to avoid data misbehavior */
+  if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
+  {
+    /* Disable instruction cache  */
+    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+    
+    if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+    {
+      /* Disable data cache  */
+      __HAL_FLASH_DATA_CACHE_DISABLE();
+      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+    }
+    else
+    {
+      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+    }
+  }
+  else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+  {
+    /* Disable data cache  */
+    __HAL_FLASH_DATA_CACHE_DISABLE();
+    pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+  }
+  else
+  {
+    pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+  }
+
+  /* Enable End of Operation and Error interrupts */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+  pFlash.Bank = pEraseInit->Banks;
+
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  {
+    /* Mass erase to be done */
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
+    FLASH_MassErase(pEraseInit->Banks);
+  }
+  else
+  {
+    /* Erase by page to be done */
+    pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
+    pFlash.NbPagesToErase = pEraseInit->NbPages;
+    pFlash.Page = pEraseInit->Page;
+
+    /*Erase 1st page and wait for IT */
+    FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Program Option bytes.
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+  
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Write protection configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
+  {
+    /* Configure of Write protection on the selected area */
+    if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+    
+  }
+  
+  /* Read protection configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
+  {
+    /* Configure the Read protection level */
+    if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+  
+  /* User Configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
+  {
+    /* Configure the user option bytes */
+    if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+  
+  /* PCROP Configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
+  {
+    if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
+    {
+      /* Configure the Proprietary code readout protection */
+      if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Get the Option bytes configuration.
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that contains the 
+  *                  configuration information.
+  * @note   The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate 
+  *         which area is requested for the WRP and PCROP, else no information will be returned
+  * 
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
+     (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
+#else
+  if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
+#endif
+  {
+    pOBInit->OptionType |= OPTIONBYTE_WRP;
+    /* Get write protection on the selected area */
+    FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
+  }
+  
+  /* Get Read protection level */
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+  
+  /* Get the user option bytes */
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+  
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
+#else
+  if(pOBInit->PCROPConfig == FLASH_BANK_1)
+#endif    
+  {
+    pOBInit->OptionType |= OPTIONBYTE_PCROP;
+    /* Get the Proprietary code readout protection */
+    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Mass erase of FLASH memory.
+  * @param  Banks: Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  * @retval None
+  */
+static void FLASH_MassErase(uint32_t Banks)
+{
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_BANK(Banks));
+
+    /* Set the Mass Erase Bit for the bank 1 if requested */
+    if((Banks & FLASH_BANK_1) != RESET)
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_MER1);
+    }
+    
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+    /* Set the Mass Erase Bit for the bank 2 if requested */
+    if((Banks & FLASH_BANK_2) != RESET)
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_MER2);
+    }
+#endif
+  }
+
+  /* Proceed to erase all sectors */
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+  * @brief  Erase the specified FLASH memory page.
+  * @param  Page: FLASH page to erase
+  *         This parameter must be a value between 0 and (max number of pages in the bank - 1)      
+  * @param  Banks: Bank(s) where the page will be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Page in bank 1 to be erased
+  *            @arg FLASH_BANK_2: Page in bank 2 to be erased
+  * @retval None
+  */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PAGE(Page));
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  {
+    assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+
+    if((Banks & FLASH_BANK_1) != RESET)
+    {
+      CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+    }
+    else
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_BKER);
+    }
+  }
+#endif
+
+  /* Proceed to erase the page */
+  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB)));
+  SET_BIT(FLASH->CR, FLASH_CR_PER);
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+  * @brief  Flush the instruction and data caches.
+  * @retval None
+  */
+void FLASH_FlushCaches(void)
+{
+  /* Flush instruction cache  */
+  if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) || 
+     (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+  {
+    /* Reset instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+    /* Enable instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+  }
+  
+  /* Flush data cache */
+  if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) || 
+     (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+  {
+    /* Reset data cache */
+    __HAL_FLASH_DATA_CACHE_RESET();
+    /* Enable data cache */
+    __HAL_FLASH_DATA_CACHE_ENABLE();
+  }
+  
+  /* Reset internal variable */
+  pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+}
+
+/**
+  * @brief  Configure the write protection of the desired pages.
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase Flash memory if the CPU debug 
+  *         features are connected (JTAG or single wire) or boot code is being 
+  *         executed from RAM or System flash, even if WRP is not activated. 
+  * @note   To configure the WRP options, the option lock bit OPTLOCK must be 
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the WRP options, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  WRPArea: specifies the area to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A                      
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B                      
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A  (don't apply for STM32L43x/STM32L44x devices)                    
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B  (don't apply for STM32L43x/STM32L44x devices)                    
+  *
+  * @param  WRPStartOffset: specifies the start page of the write protected area
+  *          This parameter can be page number between 0 and (max number of pages in the bank - 1) 
+  *
+  * @param  WRDPEndOffset: specifies the end page of the write protected area
+  *          This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) 
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRPAREA(WRPArea));
+  assert_param(IS_FLASH_PAGE(WRPStartOffset));
+  assert_param(IS_FLASH_PAGE(WRDPEndOffset));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    /* Configure the write protected area */
+    if(WRPArea == OB_WRPAREA_BANK1_AREAA)
+    {
+      MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+    else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
+    {
+      MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+    else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
+    {
+      MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+    else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
+    {
+      MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+#endif
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set the read protection level.
+  *    
+  * @note   To configure the RDP level, the option lock bit OPTLOCK must be 
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the RDP level, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible 
+  *         to go back to level 1 or 0 !!!
+  *    
+  * @param  RDPLevel: specifies the read protection level.
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *   
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    /* Configure the RDP level in the option bytes register */
+    MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+
+  return status;            
+}
+
+/**
+  * @brief  Program the FLASH User Option Byte.    
+  *   
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the user option bytes, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *   
+  * @param  UserType: The FLASH User Option Bytes to be modified 
+  * @param  UserConfig: The FLASH User Option Bytes values: 
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
+  *         IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), 
+  *         DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 
+  *   
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+  uint32_t optr_reg_val = 0;
+  uint32_t optr_reg_mask = 0;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_USER_TYPE(UserType));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    if((UserType & OB_USER_BOR_LEV) != RESET)
+    {
+      /* BOR level option byte should be modified */
+      assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
+    
+      /* Set value and mask for BOR level option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
+      optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+    }
+
+    if((UserType & OB_USER_nRST_STOP) != RESET)
+    {
+      /* nRST_STOP option byte should be modified */
+      assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
+    
+      /* Set value and mask for nRST_STOP option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
+      optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+    }
+
+    if((UserType & OB_USER_nRST_STDBY) != RESET)
+    {
+      /* nRST_STDBY option byte should be modified */
+      assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
+    
+      /* Set value and mask for nRST_STDBY option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
+      optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+    }
+
+    if((UserType & OB_USER_nRST_SHDW) != RESET)
+    {
+      /* nRST_SHDW option byte should be modified */
+      assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
+    
+      /* Set value and mask for nRST_SHDW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
+      optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+    }
+
+    if((UserType & OB_USER_IWDG_SW) != RESET)
+    {
+      /* IWDG_SW option byte should be modified */
+      assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
+    
+      /* Set value and mask for IWDG_SW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
+      optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+    }
+
+    if((UserType & OB_USER_IWDG_STOP) != RESET)
+    {
+      /* IWDG_STOP option byte should be modified */
+      assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
+    
+      /* Set value and mask for IWDG_STOP option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
+      optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+    }
+
+    if((UserType & OB_USER_IWDG_STDBY) != RESET)
+    {
+      /* IWDG_STDBY option byte should be modified */
+      assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
+    
+      /* Set value and mask for IWDG_STDBY option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
+      optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+    }
+
+    if((UserType & OB_USER_WWDG_SW) != RESET)
+    {
+      /* WWDG_SW option byte should be modified */
+      assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
+    
+      /* Set value and mask for WWDG_SW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
+      optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+    }
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+    if((UserType & OB_USER_BFB2) != RESET)
+    {
+      /* BFB2 option byte should be modified */
+      assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
+    
+      /* Set value and mask for BFB2 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
+      optr_reg_mask |= FLASH_OPTR_BFB2;
+    }
+
+    if((UserType & OB_USER_DUALBANK) != RESET)
+    {
+      /* DUALBANK option byte should be modified */
+      assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
+    
+      /* Set value and mask for DUALBANK option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
+      optr_reg_mask |= FLASH_OPTR_DUALBANK;
+    }
+#endif
+    
+    if((UserType & OB_USER_nBOOT1) != RESET)
+    {
+      /* nBOOT1 option byte should be modified */
+      assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
+    
+      /* Set value and mask for nBOOT1 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
+      optr_reg_mask |= FLASH_OPTR_nBOOT1;
+    }
+
+    if((UserType & OB_USER_SRAM2_PE) != RESET)
+    {
+      /* SRAM2_PE option byte should be modified */
+      assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
+    
+      /* Set value and mask for SRAM2_PE option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
+      optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
+    }
+
+    if((UserType & OB_USER_SRAM2_RST) != RESET)
+    {
+      /* SRAM2_RST option byte should be modified */
+      assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
+    
+      /* Set value and mask for SRAM2_RST option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
+      optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
+    }
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+    if((UserType & OB_USER_nSWBOOT0) != RESET)
+    {
+      /* nSWBOOT0 option byte should be modified */
+      assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
+    
+      /* Set value and mask for nSWBOOT0 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
+      optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+    }
+
+    if((UserType & OB_USER_nBOOT0) != RESET)
+    {
+      /* nBOOT0 option byte should be modified */
+      assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
+    
+      /* Set value and mask for nBOOT0 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
+      optr_reg_mask |= FLASH_OPTR_nBOOT0;
+    }
+#endif
+    
+    /* Configure the option bytes register */
+    MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+
+  return status;            
+}
+
+/**
+  * @brief  Configure the Proprietary code readout protection of the desired addresses.
+  *
+  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be 
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the PCROP options, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
+  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 
+  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
+  *
+  * @param  PCROPStartAddr: specifies the start address of the Proprietary code readout protection
+  *          This parameter can be an address between begin and end of the bank 
+  *
+  * @param  PCROPEndAddr: specifies the end address of the Proprietary code readout protection
+  *          This parameter can be an address between PCROPStartAddr and end of the bank 
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t reg_value = 0;
+  uint32_t bank1_addr;
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  uint32_t bank2_addr;
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+    /* Get the information about the bank swapping */
+    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
+    {
+      bank1_addr = FLASH_BASE;
+      bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+    }
+    else
+    {
+      bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+      bank2_addr = FLASH_BASE;
+    }
+#else
+    bank1_addr = FLASH_BASE;
+#endif
+    
+    {
+      /* Configure the Proprietary code readout protection */
+      if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
+      {
+        reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+        
+        reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+      }
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+      else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
+      {
+        reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+        
+        reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+      }
+#endif
+    }
+    
+    MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  *
+  * @param[in]  WRPArea: specifies the area to be returned.
+  *          This parameter can be one of the following values:
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A                      
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B                      
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)                     
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)                     
+  *
+  * @param[out]  WRPStartOffset: specifies the address where to copied the start page 
+  *                         of the write protected area
+  *
+  * @param[out]  WRDPEndOffset: specifies the address where to copied the end page of 
+  *                        the write protected area
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
+{
+  /* Get the configuration of the write protected area */
+  if(WRPArea == OB_WRPAREA_BANK1_AREAA)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
+  }
+  else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
+  }
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
+  }
+  else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
+  }
+#endif
+}
+
+/**
+  * @brief  Return the FLASH Read Protection level.
+  * @retval FLASH ReadOut Protection Status:
+  *         This return value can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+  if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && 
+      (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2))
+  {
+    return (OB_RDP_LEVEL_1);
+  }
+  else
+  {
+    return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
+  }
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values: 
+  *      For STM32L47x/STM32L48x devices :
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), 
+  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),  
+  *         BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 
+  *      For STM32L43x/STM32L44x devices :
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
+  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),  
+  *         nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27). 
+  */
+static uint32_t FLASH_OB_GetUser(void)
+{
+  uint32_t user_config = READ_REG(FLASH->OPTR);
+  CLEAR_BIT(user_config, FLASH_OPTR_RDP);
+  
+  return user_config;
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  *
+  * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
+  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 
+  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
+  *
+  * @param PCROPStartAddr [out]: specifies the address where to copied the start address 
+  *                         of the Proprietary code readout protection
+  *
+  * @param PCROPEndAddr [out]: specifies the address where to copied the end address of 
+  *                       the Proprietary code readout protection
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
+{
+  uint32_t reg_value = 0;
+  uint32_t bank1_addr;
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  uint32_t bank2_addr;
+#endif
+  
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  /* Get the information about the bank swapping */
+  if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
+  {
+    bank1_addr = FLASH_BASE;
+    bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+  }
+  else
+  {
+    bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+    bank2_addr = FLASH_BASE;
+  }
+#else
+  bank1_addr = FLASH_BASE;
+#endif
+  
+  {
+    if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
+    {
+      reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+      *PCROPStartAddr = (reg_value << 3) + bank1_addr;
+      
+      reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+      *PCROPEndAddr = (reg_value << 3) + bank1_addr;
+    }
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+    else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
+    {
+      reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+      *PCROPStartAddr = (reg_value << 3) + bank2_addr;
+      
+      reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+      *PCROPEndAddr = (reg_value << 3) + bank2_addr;
+    }
+#endif
+  }
+  
+  *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h
new file mode 100755
index 0000000..80e85f1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h
@@ -0,0 +1,98 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1 
+  * @date    21-April-2017
+  * @brief   Header file of FLASH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_FLASH_EX_H
+#define __STM32L4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/ 
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/* Extended Program operation functions  *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c
new file mode 100755
index 0000000..6382464
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c
@@ -0,0 +1,157 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ramfunc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   FLASH RAMFUNC driver.
+  *          This file provides a Flash firmware functions which should be 
+  *          executed from internal SRAM
+  *            + FLASH HalfPage Programming
+  *            + FLASH Power Down in Run mode
+  *
+  *  @verbatim
+  ==============================================================================
+                   ##### Flash RAM functions #####
+  ==============================================================================    
+
+    *** ARM Compiler ***
+    --------------------
+    [..] RAM functions are defined using the toolchain options. 
+         Functions that are executed in RAM should reside in a separate
+         source module. Using the 'Options for File' dialog you can simply change
+         the 'Code / Const' area of a module to a memory space in physical RAM.
+         Available memory areas are declared in the 'Target' tab of the 
+         Options for Target' dialog.
+
+    *** ICCARM Compiler ***
+    -----------------------
+    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+    *** GNU Compiler ***
+    --------------------
+    [..] RAM functions are defined using a specific toolchain attribute
+         "__attribute__((section(".RamFunc")))".
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
+  * @brief FLASH functions executed from RAM
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern FLASH_ProcessTypeDef pFlash;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### ramfunc functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions that should be executed from RAM.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief   Enable the Power down in Run Mode
+  * @note    This function should be called and executed from SRAM memory
+  * @retval None
+  */
+__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
+{
+  /* Enable the Power Down in Run mode*/
+  __HAL_FLASH_POWER_DOWN_ENABLE();
+  
+  return HAL_OK;
+  
+}
+
+/**
+  * @brief   Disable the Power down in Run Mode
+  * @note    This function should be called and executed from SRAM memory
+  * @retval None
+  */
+__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
+{
+  /* Disable the Power Down in Run mode*/
+  __HAL_FLASH_POWER_DOWN_DISABLE();
+
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */   
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+     
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h
new file mode 100755
index 0000000..a09dd20
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h
@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ramfunc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of FLASH RAMFUNC driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_FLASH_RAMFUNC_H
+#define __STM32L4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported macro ------------------------------------------------------------*/
+/** 
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog. 
+*/
+#define __RAM_FUNC HAL_StatusTypeDef 
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
+
+#endif
+                                      
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+__RAM_FUNC  HAL_FLASHEx_EnableRunPowerDown(void);
+__RAM_FUNC  HAL_FLASHEx_DisableRunPowerDown(void);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_FLASH_RAMFUNC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c
new file mode 100755
index 0000000..7b52c96
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c
@@ -0,0 +1,570 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+    (+) The external interrupt/event controller consists of up to 39 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+  
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup GPIO_Private_Defines GPIO Private Defines
+  * @{
+  */
+#define GPIO_MODE             ((uint32_t)0x00000003)
+#define ANALOG_MODE           ((uint32_t)0x00000008)
+#define EXTI_MODE             ((uint32_t)0x10000000)
+#define GPIO_MODE_IT          ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
+#define RISING_EDGE           ((uint32_t)0x00100000)
+#define FALLING_EDGE          ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
+
+#define GPIO_NUMBER           ((uint32_t)16)
+/**
+  * @}
+  */
+  
+/* Private macros ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t temp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != RESET)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1U << position);
+
+    if(iocurrent)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Alternate function mode selection */
+      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+        
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3];
+        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+        GPIOx->AFR[position >> 3] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+      GPIOx->MODER = temp;
+
+      /* In case of Output or Alternate function mode selection */
+      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
+        temp |= (GPIO_Init->Speed << (position * 2));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+      /* In case of Analog mode, check if ADC control mode is selected */
+      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
+      {
+        /* Configure the IO Output Type */
+        temp = GPIOx->ASCR;
+        temp &= ~(GPIO_ASCR_ASC0 << position) ;
+        temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);
+        GPIOx->ASCR = temp;
+      }
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
+      temp |= ((GPIO_Init->Pull) << (position * 2));
+      GPIOx->PUPDR = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2];
+        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
+        SYSCFG->EXTICR[position >> 2] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR1 = temp;
+
+        temp = EXTI->EMR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+    
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != RESET)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1U << position);
+
+    if (iocurrent)
+    {
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+      /* Deactivate the Control bit of Analog mode for the current IO */
+      GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+      
+      tmp = SYSCFG->EXTICR[position >> 2];
+      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+      if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+      {
+        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+        SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+        /* Clear EXTI line configuration */
+        EXTI->IMR1 &= ~((uint32_t)iocurrent);
+        EXTI->EMR1 &= ~((uint32_t)iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~((uint32_t)iocurrent);
+        EXTI->FTSR1 &= ~((uint32_t)iocurrent);
+      }
+    }
+    
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the specified input port pin.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Set or clear the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState: specifies the value to be written to the selected bit.
+  *         This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if(PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Toggle the specified GPIO pin.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the pin to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+* @brief  Lock GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bits to be locked.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+
+  if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h
new file mode 100755
index 0000000..d386421
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_GPIO_H
+#define __STM32L4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins */
+
+  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode */
+
+  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull */
+
+  uint32_t Speed;      /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins 
+                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0,
+  GPIO_PIN_SET
+}GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode GPIO mode
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
+#define  GPIO_MODE_ANALOG_ADC_CONTROL           ((uint32_t)0x0000000B)   /*!< Analog Mode for ADC conversion */
+#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed GPIO speed
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW        ((uint32_t)0x00000000)   /*!< range up to 5 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM     ((uint32_t)0x00000001)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH       ((uint32_t)0x00000002)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_VERY_HIGH  ((uint32_t)0x00000003)   /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */
+/**
+  * @}
+  */
+
+ /** @defgroup GPIO_pull GPIO pull
+   * @brief GPIO Pull-Up or Pull-Down Activation
+   * @{
+   */
+#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+  
+/**
+  * @brief  Check whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__)        ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
+                                     (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
+
+#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                                     ((__MODE__) == GPIO_MODE_ANALOG)             ||\
+                                     ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))
+
+#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
+                                     ((__PULL__) == GPIO_PULLUP)   || \
+                                     ((__PULL__) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extended module */
+#include "stm32l4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/ 
+/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions
+ * @{
+ */
+     
+/* Initialization and de-initialization functions *****************************/
+void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions 
+ * @{
+ */
+   
+/* IO operation functions *****************************************************/
+GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h
new file mode 100755
index 0000000..b58d43c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h
@@ -0,0 +1,668 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of GPIO HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_GPIO_EX_H
+#define __STM32L4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @brief GPIO Extended HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+  * @{
+  */
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
+/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#if defined(STM32L433xx) || defined(STM32L443xx)
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                          */
+#endif /* STM32L433xx || STM32L443xx */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART1 Alternate Function mapping */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
+#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
+
+#if defined(STM32L433xx) || defined(STM32L443xx)
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
+#endif /* STM32L433xx || STM32L443xx */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF3_CAN1          ((uint8_t)0x03)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping  */
+
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#if defined(STM32L452xx) || defined(STM32L462xx)
+#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */
+#endif /* STM32L452xx || STM32L462xx */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_CAN1         ((uint8_t)0x0A)  /* CAN1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 11 selection
+  */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#if defined(STM32L476xx) || defined(STM32L486xx)
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                        */
+#endif /* STM32L476xx || STM32L486xx */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
+
+#if defined(STM32L476xx) || defined(STM32L486xx)
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
+#endif /* STM32L476xx || STM32L486xx */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */
+#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF3_CAN2          ((uint8_t)0x03)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */
+#define GPIO_AF3_QUADSPI       ((uint8_t)0x03)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF3_SPI2          ((uint8_t)0x03)  /* SPI2 Alternate Function mapping */
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF4_DCMI          ((uint8_t)0x04)  /* DCMI Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_DCMI          ((uint8_t)0x05)  /* DCMI Alternate Function mapping   */
+#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping */
+#define GPIO_AF5_QUADSPI       ((uint8_t)0x05)  /* QUADSPI Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /* I2C3 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+#define GPIO_AF8_CAN2          ((uint8_t)0x08)  /* CAN2 Alternate Function mapping    */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_CAN2         ((uint8_t)0x0A)  /* CAN2 Alternate Function mapping */
+#define GPIO_AF10_DCMI         ((uint8_t)0x0A)  /* DCMI Alternate Function mapping */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF12_TIM8_COMP2   ((uint8_t)0x0C)  /* TIM8/COMP2 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */
+#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
+* @{
+  */
+#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U : 7U)
+
+#endif /* STM32L431xx || STM32L433xx || STM32L443xx */
+
+#if defined(STM32L432xx) || defined(STM32L442xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U : 7U)
+
+#endif /* STM32L432xx || STM32L442xx */
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U : 7U)
+
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U :\
+                                      ((__GPIOx__) == (GPIOF))? 5U :\
+                                      ((__GPIOx__) == (GPIOG))? 6U : 7U)
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U :\
+                                      ((__GPIOx__) == (GPIOF))? 5U :\
+                                      ((__GPIOx__) == (GPIOG))? 6U :\
+                                      ((__GPIOx__) == (GPIOH))? 7U : 8U)
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c
new file mode 100755
index 0000000..2b84bd6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c
@@ -0,0 +1,2675 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hash.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   HASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the HASH peripheral:
+  *           + Initialization and de-initialization methods
+  *           + HASH or HMAC processing in polling mode
+  *           + HASH or HMAC processing in interrupt mode
+  *           + HASH or HMAC processing in DMA mode
+  *           + Peripheral State methods
+  *           + HASH or HMAC processing suspension/resumption  
+  *         
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    The HASH HAL driver can be used as follows:
+    
+    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
+        (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+        (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
+            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
+            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
+            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
+        (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_xxx_Start_DMA())
+            (+++) Enable the DMAx interface clock using 
+                   __DMAx_CLK_ENABLE()
+            (+++) Configure and enable one DMA stream to manage data transfer from
+                memory to peripheral (input stream). Managing data transfer from
+                peripheral to memory can be performed only using CPU.
+            (+++) Associate the initialized DMA handle to the HASH DMA handle
+                using  __HAL_LINKDMA()
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                interrupt on the DMA Stream: use
+                 HAL_NVIC_SetPriority() and 
+                 HAL_NVIC_EnableIRQ()
+                
+    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
+        (##) resorts to HAL_HASH_MspInit() for low-level initialization,
+        (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
+        
+    (#)Three processing schemes are available:
+        (##) Polling mode: processing APIs are blocking functions
+             i.e. they process the data and wait till the digest computation is finished,
+             e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
+        (##) Interrupt mode: processing APIs are not blocking functions
+                i.e. they process the data under interrupt,
+                e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
+        (##) DMA mode: processing APIs are not blocking functions and the CPU is
+             not used for data transfer i.e. the data transfer is ensured by DMA,
+                e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA() 
+                for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish() 
+                is then required to retrieve the digest.
+                
+    (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is 
+       initialized and processes the buffer fed in input. When the input data have all been
+       fed to the IP, the digest computation can start.
+       
+    (#)Multi-buffer processing is possible in polling and DMA mode. 
+        (##) In polling mode, only multi-buffer HASH processing is possible. 
+             API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
+             User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as 
+             well the computed digest.
+             
+        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+
+              (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
+             From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
+             Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+             macro then wrap-up the HASH processing in feeding the last input buffer thru the
+             same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to  
+             API HAL_HASH_xxx_Finish().
+             
+             (+++) HMAC processing (requires to resort to extended functions): 
+             after initialization, the key and the first input buffer are entered
+             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+             starts step 2.
+             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
+             point, the HMAC processing is still carrying out step 2.
+             Then, step 2 for the last input buffer and step 3 are carried out by a single call 
+             to HAL_HMACEx_xxx_Step2_3_DMA().
+             
+             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
+              
+             
+    (#)Context swapping. 
+        (##) Two APIs are available to suspend HASH or HMAC processing: 
+             (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
+             (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.    
+                              
+        (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
+            to save in memory the IP context. This context can be restored afterwards
+            to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
+            
+        (##) Once the HASH IP has been restored to the same configuration as that at suspension
+             time, processing can be restarted with the same API call (same API, same handle,
+             same parameters) as done before the suspension. Relevant parameters to restart at 
+             the proper location are internally saved in the HASH handle.   
+                                           
+    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+#if defined (STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HASH  HASH
+  * @brief HASH HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HASH_Private_Constants HASH Private Constants
+  * @{
+  */
+ 
+/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status 
+  * @{
+  */   
+#define HASH_DIGEST_CALCULATION_NOT_STARTED       ((uint32_t)0x00000000) /*!< DCAL not set after input data written in DIN register */ 
+#define HASH_DIGEST_CALCULATION_STARTED           ((uint32_t)0x00000001) /*!< DCAL set after input data written in DIN register     */
+/**
+  * @}
+  */ 
+
+/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers 
+  * @{
+  */ 
+#define HASH_NUMBER_OF_CSR_REGISTERS              54     /*!< Number of Context Swap Registers */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup HASH_TimeOut_Value HASH TimeOut Value 
+  * @{
+  */ 
+#define HASH_TIMEOUTVALUE                         1000   /*!< Time-out value  */
+/**
+  * @}
+  */
+   
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */ 
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
+  * @{
+  */
+
+/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization, configuration and call-back functions. 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the HASH according to the specified parameters 
+          in the HASH_InitTypeDef and create the associated handle
+      (+) DeInitialize the HASH peripheral
+      (+) Initialize the HASH MCU Specific Package (MSP)
+      (+) DeInitialize the HASH MSP
+      
+    [..]  This section provides as well call back functions definitions for user
+          code to manage:
+      (+) Input data transfer to IP completion  
+      (+) Calculated digest retrieval completion
+      (+) Error management                   
+           
+      
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the HASH according to the specified parameters in the
+            HASH_HandleTypeDef and create the associated handle.
+  * @note   Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
+  *         other configuration bits are set by HASH or HMAC processing APIs. 
+  * @note   MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for 
+  *         multi-buffer HASH processing, user needs to resort to 
+  *         __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
+  *         relevant APIs manage themselves the MDMAT bit.   
+  * @param  hhash: HASH handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+  
+  /* Check the hash handle allocation */
+  if(hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  if(hhash->State == HAL_HASH_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhash->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_HASH_MspInit(hhash);
+  }  
+  
+    /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+
+  /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
+  hhash->HashInCount = 0;
+  hhash->HashBuffSize = 0;
+  hhash->HashITCounter = 0;
+  hhash->NbWordsAlreadyPushed = 0;
+  /* Reset digest calculation bridle (MDMAT bit control) */
+  hhash->DigestCalculationDisable = RESET;
+  /* Set phase to READY */
+  hhash->Phase = HAL_HASH_PHASE_READY;   
+  
+  /* Set the data type and reset MDMAT bit */
+  MODIFY_REG(HASH->CR, HASH_CR_DATATYPE|HASH_CR_MDMAT, hhash->Init.DataType);
+  
+  /* Reset HASH handle status */
+  hhash->Status = HAL_OK;
+  
+  /* Set the HASH state to Ready */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the HASH peripheral. 
+  * @param  hhash: HASH handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
+{ 
+  /* Check the HASH handle allocation */
+  if(hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Set the default HASH phase */
+  hhash->Phase = HAL_HASH_PHASE_READY;
+  
+  /* Reset HashInCount, HashITCounter and HashBuffSize */
+  hhash->HashInCount = 0;
+  hhash->HashBuffSize = 0;
+  hhash->HashITCounter = 0;
+  /* Reset digest calculation bridle (MDMAT bit control) */
+  hhash->DigestCalculationDisable = RESET;  
+  
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_HASH_MspDeInit(hhash);
+  
+  /* Reset HASH handle status */
+  hhash->Status = HAL_OK;  
+  
+  /* Set the HASH state to Ready */
+  hhash->State = HAL_HASH_STATE_RESET;
+   
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the HASH MSP.
+  * @param  hhash: HASH handle.
+  * @retval None
+  */
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_MspInit() can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the HASH MSP.
+  * @param  hhash: HASH handle.
+  * @retval None
+  */
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_MspDeInit() can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Input data transfer complete call back.
+  * @note   HAL_HASH_InCpltCallback() is called when the complete input message 
+  *         has been fed to the IP. This API is invoked only when input data are
+  *         entered under interruption or thru DMA. 
+  * @note   In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), 
+  *         HAL_HASH_InCpltCallback() is called at the end of each buffer feeding 
+  *         to the IP.       
+  * @param  hhash: HASH handle.
+  * @retval None
+  */
+__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_InCpltCallback() can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Digest computation complete call back. 
+  * @note   HAL_HASH_DgstCpltCallback() is used under interruption, is not 
+  *         relevant with DMA.
+  * @param  hhash: HASH handle.
+  * @retval None
+  */
+__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_DgstCpltCallback() can be implemented in the user file.
+   */
+}
+                          
+/**
+  * @brief  Error callback.
+  * @note   Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
+  *         to retrieve the error type.
+  * @param  hhash: HASH handle.
+  * @retval None
+  */
+__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_ErrorCallback() can be implemented in the user file.
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode 
+ *  @brief   HASH processing functions using polling mode. 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Polling mode HASH processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+         (++) HAL_HASH_MD5_Start() 
+         (++) HAL_HASH_MD5_Accumulate()                
+      (+) SHA1
+         (++) HAL_HASH_SHA1_Start() 
+         (++) HAL_HASH_SHA1_Accumulate()          
+      
+    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
+          
+    [..]  In case of multi-buffer HASH processing (a single digest is computed while
+          several buffers are fed to the IP), the user can resort to successive calls
+          to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
+          to HAL_HASH_xxx_Start(). 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); 
+}
+
+/**
+  * @brief  If not already done, initialize the HASH peripheral in MD5 mode then 
+  *         processes pInBuffer.
+  * @note   Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed 
+  *         several input buffers back-to-back to the IP that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input 
+  *         buffers feeding and retrieval of digest is done by a call to 
+  *         HAL_HASH_MD5_Start().  
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.   
+  * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
+  *         to read it, feeding at the same time the last input buffer to the IP.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
+  *         to manage the ending buffer with a length in bytes not a multiple of 4.       
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{ 
+  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @param  Timeout: Timeout value    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @brief  If not already done, initialize the HASH peripheral in SHA1 mode then 
+  *         processes pInBuffer.
+  * @note   Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed 
+  *         several input buffers back-to-back to the IP that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input 
+  *         buffers feeding and retrieval of digest is done by a call to 
+  *         HAL_HASH_SHA1_Start().  
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.   
+  * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
+  *         to read it, feeding at the same time the last input buffer to the IP.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
+  *         to manage the ending buffer with a length in bytes not a multiple of 4.       
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+ *  @brief   HASH processing functions using interrupt mode. 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Interruption mode HASH processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in interrupt mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+         (++) HAL_HASH_MD5_Start_IT()           
+      (+) SHA1
+         (++) HAL_HASH_SHA1_Start_IT()
+         
+    [..]  API HAL_HASH_IRQHandler() manages each HASH interruption.
+    
+    [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
+         HMAC processing mode.
+ 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{ 
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @retval HAL status
+  */   
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @brief Handle HASH interrupt request.
+  * @param hhash: HASH handle.
+  * @note  HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.    
+  * @note  In case of error reported during the HASH interruption processing,
+  *        HAL_HASH_ErrorCallback() API is called so that user code can
+  *        manage the error. The error type is available in hhash->Status field.      
+  * @retval None
+  */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+  hhash->Status = HASH_IT(hhash);
+  if (hhash->Status != HAL_OK)
+  {
+    HAL_HASH_ErrorCallback(hhash); 
+    /* After error handling by code user, reset HASH handle HAL status */
+    hhash->Status = HAL_OK;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+ *  @brief   HASH processing functions using DMA mode. 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### DMA mode HASH processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+         (++) HAL_HASH_MD5_Start_DMA() 
+         (++) HAL_HASH_MD5_Finish()            
+      (+) SHA1
+         (++) HAL_HASH_SHA1_Start_DMA()
+         (++) HAL_HASH_SHA1_Finish()
+         
+    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
+          to  HAL_HASH_xxx_Start_DMA() then read the resulting digest with 
+          HAL_HASH_xxx_Finish(). 
+          
+    [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
+          the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be 
+          reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
+          retrieved thanks to HAL_HASH_xxx_Finish().                    
+         
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
+  *         to feed the input buffer to the IP. 
+  * @note   Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
+  *         be called to retrieve the computed digest.   
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{ 
+  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); 
+}
+
+/**
+  * @brief  Return the computed digest in MD5 mode.
+  * @note   The API waits for DCIS to be set then reads the computed digest.
+  * @note   HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
+  *         HMAC MD5 mode.    
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @param  Timeout: Timeout value.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+   return HASH_Finish(hhash, pOutBuffer, Timeout);   
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
+  *         to feed the input buffer to the IP. 
+  * @note   Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
+  *         be called to retrieve the computed digest.   
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); 
+}
+
+
+/**
+  * @brief  Return the computed digest in SHA1 mode.
+  * @note   The API waits for DCIS to be set then reads the computed digest.
+  * @note   HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
+  *         HMAC SHA1 mode.     
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @param  Timeout: Timeout value.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{  
+   return HASH_Finish(hhash, pOutBuffer, Timeout);   
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+ *  @brief   HMAC processing functions using polling mode. 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Polling mode HMAC processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+         (++) HAL_HMAC_MD5_Start()              
+      (+) SHA1
+         (++) HAL_HMAC_SHA1_Start() 
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @param  Timeout: Timeout value.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @param  Timeout: Timeout value.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{ 
+  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @}
+  */
+  
+  
+/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+ *  @brief   HMAC processing functions using interrupt mode. 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Interrupt mode HMAC processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in interrupt mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+         (++) HAL_HMAC_MD5_Start_IT()              
+      (+) SHA1
+         (++) HAL_HMAC_SHA1_Start_IT() 
+
+@endverbatim
+  * @{
+  */  
+  
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+  *         read the computed digest in interrupt mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @retval HAL status
+  */  
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{  
+  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
+}  
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+  *         read the computed digest in interrupt mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{ 
+  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
+}  
+  
+/**
+  * @}
+  */
+    
+  
+
+/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ *  @brief   HMAC processing functions using DMA modes. 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### DMA mode HMAC processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+         (++) HAL_HMAC_MD5_Start_DMA()              
+      (+) SHA1
+         (++) HAL_HMAC_SHA1_Start_DMA() 
+         
+    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing, 
+          user must resort to  HAL_HMAC_xxx_Start_DMA() then read the resulting digest 
+          with HAL_HASH_xxx_Finish().          
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC MD5 mode then initiate the required 
+  *         DMA transfers to feed the key and the input buffer to the IP. 
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve 
+  *         the computed digest.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. 
+  * @note   If MDMAT bit is set before calling this function (multi-buffer
+  *          HASH processing case), the input buffer size (in bytes) must be 
+  *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
+  *          For the processing of the last buffer of the thread, MDMAT bit must
+  *          be reset and the buffer length (in bytes) doesn't have to be a 
+  *          multiple of 4.          
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required 
+  *         DMA transfers to feed the key and the input buffer to the IP. 
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve 
+  *         the computed digest.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   If MDMAT bit is set before calling this function (multi-buffer
+  *          HASH processing case), the input buffer size (in bytes) must be 
+  *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
+  *          For the processing of the last buffer of the thread, MDMAT bit must
+  *          be reset and the buffer length (in bytes) doesn't have to be a 
+  *          multiple of 4.                    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */  
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions  
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State methods #####
+ ===============================================================================  
+    [..]
+    This section permits to get in run-time the state and the peripheral handle 
+    status of the peripheral:
+      (+) HAL_HASH_GetState()            
+      (+) HAL_HASH_GetStatus()
+      
+    [..]
+    Additionally, this subsection provides functions allowing to save and restore
+    the HASH or HMAC processing context in case of calculation suspension: 
+      (+) HAL_HASH_ContextSaving()            
+      (+) HAL_HASH_ContextRestoring()         
+      
+    [..]
+    This subsection provides functions allowing to suspend the HASH processing
+      (+) when input are fed to the IP by software
+          (++) HAL_HASH_SwFeed_ProcessSuspend()          
+      (+) when input are fed to the IP by DMA 
+          (++) HAL_HASH_DMAFeed_ProcessSuspend()               
+    
+ 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the HASH handle state.
+  * @note   The API yields the current state of the handle (BUSY, READY,...). 
+  * @param  hhash: HASH handle.
+  * @retval HAL HASH state
+  */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+  return hhash->State;
+}
+
+
+/**
+  * @brief Return the HASH HAL status.
+  * @note  The API yields the HAL status of the handle: it is the result of the
+  *        latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).   
+  * @param  hhash: HASH handle.
+  * @retval HAL status
+  */                                   
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
+{
+  return hhash->Status;
+}
+
+/**
+  * @brief  Save the HASH context in case of processing suspension.
+  * @param  hhash: HASH handle.  
+  * @param  pMemBuffer: pointer to the memory buffer where the HASH context 
+  *         is saved. 
+  * @note   The IMR, STR, CR then all the CSR registers are saved
+  *         in that order. Only the r/w bits are read to be restored later on.  
+  * @note   By default, all the context swap registers (there are 
+  *         HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. 
+  * @note   pMemBuffer points to a buffer allocated by the user. The buffer size
+  *         must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.    
+  * @retval None
+  */
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+  uint32_t mem_ptr = (uint32_t)pMemBuffer;
+  uint32_t csr_ptr = (uint32_t)HASH->CSR;
+  uint32_t i = 0;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);  
+  
+  /* Save IMR register content */
+  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
+  mem_ptr+=4;   
+  /* Save STR register content */
+  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
+  mem_ptr+=4;
+  /* Save CR register content */ 
+  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
+  mem_ptr+=4;        
+  /* By default, save all CSRs registers */
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--)
+  {
+    *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
+    mem_ptr+=4;
+    csr_ptr+=4;
+  } 
+}
+
+
+/**
+  * @brief  Restore the HASH context in case of processing resumption.
+  * @param  hhash: HASH handle.  
+  * @param  pMemBuffer: pointer to the memory buffer where the HASH context 
+  *         is stored. 
+  * @note   The IMR, STR, CR then all the CSR registers are restored
+  *         in that order. Only the r/w bits are restored.    
+  * @note   By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
+  *         of those) are restored (all of them have been saved by default
+  *         beforehand).    
+  * @retval None
+  */
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+  uint32_t mem_ptr = (uint32_t)pMemBuffer;
+  uint32_t csr_ptr = (uint32_t)HASH->CSR;
+  uint32_t i = 0;
+  
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);    
+
+  /* Restore IMR register content */
+  WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));   
+  mem_ptr+=4;   
+  /* Restore STR register content */
+  WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));     
+  mem_ptr+=4;
+  /* Restore CR register content */ 
+  WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); 
+  mem_ptr+=4;   
+  
+  /* Reset the HASH processor before restoring the Context
+  Swap Registers (CSR) */ 
+  __HAL_HASH_INIT();   
+        
+  /* By default, restore all CSR registers */
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--)
+  {
+    WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));      
+    mem_ptr+=4;
+    csr_ptr+=4;
+  } 
+}
+
+
+/**
+  * @brief  Initiate HASH processing suspension when in polling or interruption mode.
+  * @param  hhash: HASH handle.
+  * @note   Set the handle field SuspendRequest to the appropriate value so that 
+  *         the on-going HASH processing is suspended as soon as the required 
+  *         conditions are met. Note that the actual suspension is carried out
+  *         by the functions HASH_WriteData() in polling mode and HASH_IT() in
+  *         interruption mode.     
+  * @retval None
+  */
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+  /* Set Handle Suspend Request field */
+  hhash->SuspendRequest = HAL_HASH_SUSPEND;
+}
+
+/**
+  * @brief  Suspend the HASH processing when in DMA mode.
+  * @param  hhash: HASH handle.
+  * @note   When suspension attempt occurs at the very end of a DMA transfer and 
+  *         all the data have already been entered in the IP, hhash->State is 
+  *         set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is 
+  *         recommended to wrap-up the processing in reading the digest as usual. 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+  uint32_t tmp_remaining_DMATransferSize_inWords = 0x0;
+  uint32_t tmp_initial_DMATransferSize_inWords = 0x0;
+  uint32_t tmp_words_already_pushed = 0x0;  
+  
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {  
+    /* Set State as suspended (it may be required to update it if suspension failed).
+       The context saving operations must be carried out to be able to resume later on. */   
+    hhash->State = HAL_HASH_STATE_SUSPENDED;
+    
+    /* Disable DMA channel */
+    HAL_DMA_Abort(hhash->hdmain);    
+    
+    /* Clear DMAE bit */
+    CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+    
+    /* At this point, DMA interface is disabled and no transfer is on-going */
+    /* Retrieve from the DMA handle how many words remain to be written */
+    tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR;
+
+    if (tmp_remaining_DMATransferSize_inWords == 0)
+    {
+      /* All the DMA transfer is actually done. Suspension occurred at the very end 
+         of the transfer. Either the digest computation is about to start (HASH case) 
+         or processing is about to move from one step to another (HMAC case).
+         In both cases, the processing can't be suspended at this point. It is
+         safer to
+         - retrieve the low priority block digest before starting the high 
+           priority block processing (HASH case)
+         - re-attempt a new suspension (HMAC case)  
+         */       
+      hhash->State  = HAL_HASH_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+  
+      /* Compute how many words were supposed to be transferred by DMA */
+      tmp_initial_DMATransferSize_inWords = (hhash->HashInCount%4 ?  (hhash->HashInCount+3)/4: hhash->HashInCount/4);
+      
+      /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
+        by HASH IP, correct it */
+      /* tmp_words_already_pushed reflects the number of words that were already pushed before
+         the start of DMA transfer (multi-buffer processing case) */
+      tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
+      if ((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16  != HASH_NBW_PUSHED())
+      {
+        tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ 
+      }
+      /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
+      hhash->pHashInBuffPtr +=  4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
+      
+      /* And store in HashInCount the remaining size to transfer (in bytes) */
+      hhash->HashInCount = 4 * tmp_remaining_DMATransferSize_inWords;      
+  
+    }
+  
+    return HAL_OK;
+  
+  }
+}
+
+
+/**
+  * @}
+  */
+  
+  
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */ 
+
+/**
+  * @brief DMA HASH Input Data transfer completion callback. 
+  * @param hdma: DMA handle.
+  * @note  In case of HMAC processing, HASH_DMAXferCplt() initiates
+  *        the next DMA transfer for the following HMAC step.    
+  * @retval None
+  */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  uint32_t inputaddr = 0x0;
+  uint32_t buffersize = 0x0;
+  
+  if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+  {
+  
+  /* Disable the DMA transfer */
+  CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
+
+  if (READ_BIT(HASH->CR, HASH_CR_MODE) == RESET)
+  {
+    /* If no HMAC processing, input data transfer is now over */
+    
+    /* Change the HASH state to ready */
+    hhash->State = HAL_HASH_STATE_READY;
+    
+    /* Call Input data transfer complete call back */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  else
+  {
+    /* HMAC processing: depending on the current HMAC step and whether or
+      not multi-buffer processing is on-going, the next step is initiated
+      and MDMAT bit is set.  */
+  
+
+    if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+    {
+      /* This is the end of HMAC processing */
+        
+      /* Change the HASH state to ready */
+      hhash->State = HAL_HASH_STATE_READY;
+    
+      /* Call Input data transfer complete call back 
+         (note that the last DMA transfer was that of the key 
+         for the outer HASH operation). */
+      HAL_HASH_InCpltCallback(hhash);        
+    
+      return;
+    }
+    else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+    {
+      inputaddr = (uint32_t)hhash->pHashMsgBuffPtr;     /* DMA transfer start address */
+      buffersize = hhash->HashBuffSize;                 /* DMA transfer size (in bytes) */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
+      
+      /* In case of suspension request, save the new starting parameters */
+      hhash->HashInCount = hhash->HashBuffSize;         /* Initial DMA transfer size (in bytes) */
+      hhash->pHashInBuffPtr  = hhash->pHashMsgBuffPtr ; /* DMA transfer start address           */
+
+      hhash->NbWordsAlreadyPushed = 0;                  /* Reset number of words already pushed */
+            
+      /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ 
+      if (hhash->DigestCalculationDisable != RESET)
+      {
+        /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, 
+           no digest calculation will be triggered at the end of the input buffer feeding to the IP */
+        __HAL_HASH_SET_MDMAT();     
+      }
+    }
+    else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+    {
+      if (hhash->DigestCalculationDisable != RESET)
+      {
+        /* No automatic move to Step 3 as a new message buffer will be fed to the IP
+           (case of multi-buffer HMAC processing):
+           DCAL must not be set.
+           Phase remains in Step 2, MDMAT remains set at this point.
+           Change the HASH state to ready and call Input data transfer complete call back. */
+        hhash->State = HAL_HASH_STATE_READY;
+        HAL_HASH_InCpltCallback(hhash);        
+        return ; 
+      }
+      else
+      {
+        /* Digest calculation is not disabled (case of single buffer input or last buffer
+          of multi-buffer HMAC processing) */
+        inputaddr = (uint32_t)hhash->Init.pKey;       /* DMA transfer start address */  
+        buffersize = hhash->Init.KeySize;             /* DMA transfer size (in bytes) */
+        hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;    /* Move phase from Step 2 to Step 3 */
+        /* In case of suspension request, save the new starting parameters */
+        hhash->HashInCount = hhash->Init.KeySize;     /* Initial size for second DMA transfer (input data) */
+        hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* address passed to DMA, now entering data message */  
+        
+        hhash->NbWordsAlreadyPushed = 0;              /* Reset number of words already pushed */
+      }
+    }
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(buffersize);
+    
+      
+      /* Set the HASH DMA transfert completion call back */
+      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+      
+    /* Enable the DMA In DMA Stream */
+    HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
+    
+    /* Enable DMA requests */
+    SET_BIT(HASH->CR, HASH_CR_DMAE);
+  }
+  }
+
+  return;
+}
+
+/**
+  * @brief DMA HASH communication error callback. 
+  * @param hdma: DMA handle.
+  * @note  HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
+  *        can contain user code to manage the error.    
+  * @retval None
+  */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+    if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+  {
+  /* Set HASH state to ready to prevent any blocking issue in user code 
+     present in HAL_HASH_ErrorCallback() */
+  hhash->State= HAL_HASH_STATE_READY;
+  /* Set HASH handle status to error */
+  hhash->Status = HAL_ERROR;
+  HAL_HASH_ErrorCallback(hhash);
+  /* After error handling by code user, reset HASH handle HAL status */
+  hhash->Status = HAL_OK;
+  
+  }  
+}
+
+/**
+  * @brief  Feed the input buffer to the HASH IP.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to input buffer.
+  * @param  Size: the size of input buffer in bytes.
+  * @note   HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
+  *         or not the HASH processing must be suspended. If this is the case, the
+  *         processing is suspended when possible and the IP feeding point reached at
+  *         suspension time is stored in the handle for resumption later on.  
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t buffercounter;
+  __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+  
+  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
+  {
+    /* Write input data 4 bytes at a time */
+    HASH->DIN = *(uint32_t*)inputaddr;
+    inputaddr+=4;
+    
+    /* If the suspension flag has been raised and if the processing is not about
+       to end, suspend processing */
+    if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size))
+    {
+      /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free 
+         in the input buffer */
+      if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) 
+      {
+        /* Reset SuspendRequest */
+        hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+      
+        /* Depending whether the key or the input data were fed to the IP, the feeding point
+           reached at suspension time is not saved in the same handle fields */ 
+        if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
+        {
+          /* Save current reading and writing locations of Input and Output buffers */
+          hhash->pHashInBuffPtr =  (uint8_t *)inputaddr;
+          /* Save the number of bytes that remain to be processed at this point */
+          hhash->HashInCount    =  Size - (buffercounter + 4);
+        }
+        else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+        {
+          /* Save current reading and writing locations of Input and Output buffers */
+          hhash->pHashKeyBuffPtr  =  (uint8_t *)inputaddr;
+          /* Save the number of bytes that remain to be processed at this point */
+          hhash->HashKeyCount  =  Size - (buffercounter + 4);        
+        }
+        else
+        {
+          /* Unexpected phase: unlock process and report error */
+          hhash->State = HAL_HASH_STATE_READY;
+          __HAL_UNLOCK(hhash);
+          return HAL_ERROR;
+        }
+      
+        /* Set the HASH state to Suspended and exit to stop entering data */
+        hhash->State = HAL_HASH_STATE_SUSPENDED;
+        
+        return HAL_OK;
+      } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))  */
+    } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
+  }   /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4)                 */
+  
+  /* At this point, all the data have been entered to the IP: exit */
+  return  HAL_OK; 
+}
+
+/**
+  * @brief  Retrieve the message digest.
+  * @param  pMsgDigest: pointer to the computed digest.
+  * @param  Size: message digest size in bytes.
+  * @retval None
+  */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+  uint32_t msgdigest = (uint32_t)pMsgDigest;
+  
+  switch(Size)
+  {
+    /* Read the message digest */
+    case 16:  /* MD5 */
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest+=4;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest+=4;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest+=4;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    break;
+    case 20:  /* SHA1 */
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest+=4;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest+=4;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest+=4;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+      msgdigest+=4;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    break;
+  case 28:  /* SHA224 */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+    break;
+  case 32:   /* SHA256 */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+    break;    
+    default:
+    break;
+  }
+}
+
+
+
+/**
+  * @brief  Handle HASH processing Timeout.
+  * @param  hhash: HASH handle.
+  * @param  Flag: specifies the HASH flag to check.
+  * @param  Status: the Flag status (SET or RESET).
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */  
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_HASH_GET_FLAG(Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Set State to Ready to be able to restart later on */
+          hhash->State  = HAL_HASH_STATE_READY;
+          /* Store time out issue in handle status */
+          hhash->Status = HAL_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hhash);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Set State to Ready to be able to restart later on */
+          hhash->State  = HAL_HASH_STATE_READY;
+          /* Store time out issue in handle status */
+          hhash->Status = HAL_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hhash);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  HASH processing in interruption mode.
+  * @param  hhash: HASH handle.
+  * @note   HASH_IT() regularly reads hhash->SuspendRequest to check whether
+  *         or not the HASH processing must be suspended. If this is the case, the
+  *         processing is suspended when possible and the IP feeding point reached at
+  *         suspension time is stored in the handle for resumption later on.  
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
+{
+  if (hhash->State == HAL_HASH_STATE_BUSY)
+  {  
+    /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
+    if(hhash->HashITCounter == 0)
+    {
+      /* Disable Interrupts */
+      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+      /* HASH state set back to Ready to prevent any issue in user code
+         present in HAL_HASH_ErrorCallback() */
+      hhash->State = HAL_HASH_STATE_READY;        
+      return HAL_ERROR;
+    }
+    else if (hhash->HashITCounter == 1)
+    {
+     /* This is the first call to HASH_IT, the first input data are about to be 
+        entered in the IP. A specific processing is carried out at this point to
+        start-up the processing. */ 
+      hhash->HashITCounter = 2;
+    }
+    else
+    {
+      /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
+        the HASH processing or the end of the current step for HMAC processing. */ 
+      hhash->HashITCounter = 3;
+    }
+    
+    /* If digest is ready */
+    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+    {
+      /* Read the digest */
+      HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+      
+      /* Disable Interrupts */
+      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete call back */
+      HAL_HASH_DgstCpltCallback(hhash);
+           
+      return HAL_OK;
+    }       
+
+    /* If IP ready to accept new data */
+    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+    { 
+
+      /* If the suspension flag has been raised and if the processing is not about
+         to end, suspend processing */
+      if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (hhash->HashInCount != 0))
+      {
+        /* Disable Interrupts */
+        __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+    
+        /* Reset SuspendRequest */
+        hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;         
+    
+        /* Change the HASH state */
+        hhash->State = HAL_HASH_STATE_SUSPENDED;
+      
+        return HAL_OK;
+      } 
+      
+      /* Enter input data in the IP thru HASH_Write_Block_Data() call and
+        check whether the digest calculation has been triggered */    
+      if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
+      {
+        /* Call Input data transfer complete call back 
+           (called at the end of each step for HMAC) */
+        HAL_HASH_InCpltCallback(hhash);            
+        
+        if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+        {
+          /* Wait until IP is not busy anymore */
+          if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+          {
+            /* Disable Interrupts */
+            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);       
+            return HAL_TIMEOUT;
+          }            
+          /* Initialization start for HMAC STEP 2 */
+          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
+          __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);  /* Set NBLW for the input message */
+          hhash->HashInCount = hhash->HashBuffSize;         /* Set the input data size (in bytes) */
+          hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr;   /* Set the input data address */
+          hhash->HashITCounter = 1;                         /* Set ITCounter to 1 to indicate the start of a new phase */
+          __HAL_HASH_ENABLE_IT(HASH_IT_DINI);               /* Enable IT (was disabled in HASH_Write_Block_Data) */
+        } 
+        else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+        {
+          /* Wait until IP is not busy anymore */
+          if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+          {
+            /* Disable Interrupts */
+            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);                                 
+            return HAL_TIMEOUT;
+          }             
+          /* Initialization start for HMAC STEP 3 */
+          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;         /* Move phase from Step 2 to Step 3 */                       
+          __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);   /* Set NBLW for the key */                         
+          hhash->HashInCount = hhash->Init.KeySize;          /* Set the key size (in bytes) */                     
+          hhash->pHashInBuffPtr = hhash->Init.pKey;          /* Set the key address */                             
+          hhash->HashITCounter = 1;                          /* Set ITCounter to 1 to indicate the start of a new phase */
+          __HAL_HASH_ENABLE_IT(HASH_IT_DINI);                /* Enable IT (was disabled in HASH_Write_Block_Data) */      
+        }
+      } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
+    }  /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
+
+    /* Return function status */
+    return HAL_OK;  
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Write a block of data in HASH IP in interruption mode.
+  * @param  hhash: HASH handle.
+  * @note   HASH_Write_Block_Data() is called under interruption by HASH_IT().    
+  * @retval HAL status
+  */
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
+{
+  uint32_t inputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;    
+  uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
+  
+  /* If there are more than 64 bytes remaining to be entered */
+  if(hhash->HashInCount > 64)
+  {
+    inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+    /* Write the Input block in the Data IN register
+      (16 32-bit words, or 64 bytes are entered) */
+    for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+    {
+      HASH->DIN = *(uint32_t*)inputaddr;
+      inputaddr+=4;
+    }
+    /* If this is the start of input data entering, an additional word
+      must be entered to start up the HASH processing */
+    if(hhash->HashITCounter == 2)
+    {
+      HASH->DIN = *(uint32_t*)inputaddr;
+      inputaddr+=4;
+      if(hhash->HashInCount >= 68)
+      {
+        /* There are still data waiting to be entered in the IP.
+           Decrement buffer counter and set pointer to the proper
+           memory location for the next data entering round. */
+        hhash->HashInCount -= 68;
+        hhash->pHashInBuffPtr+= 68;
+      }
+      else
+      {
+        /* All the input buffer has been fed to the HW. */
+        hhash->HashInCount = 0;
+      }
+    }
+    else
+    {
+      /* 64 bytes have been entered and there are still some remaining:
+         Decrement buffer counter and set pointer to the proper
+        memory location for the next data entering round.*/
+      hhash->HashInCount -= 64;
+      hhash->pHashInBuffPtr+= 64;
+    }
+  }
+  else
+  {
+    /* 64 or less bytes remain to be entered. This is the last
+      data entering round. */ 
+  
+    /* Get the buffer address */
+    inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+    /* Get the buffer counter */
+    inputcounter = hhash->HashInCount;
+    /* Disable Interrupts */
+    __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
+
+    /* Write the Input block in the Data IN register */
+    for(buffercounter = 0; buffercounter < (inputcounter+3)/4; buffercounter++)
+    {
+      HASH->DIN = *(uint32_t*)inputaddr;
+      inputaddr+=4;
+    }
+    /* Start the Digest calculation */
+    __HAL_HASH_START_DIGEST();
+    /* Return indication that digest calculation has started:
+       this return value triggers the call to Input data transfer 
+       complete call back as well as the proper transition from
+       one step to another in HMAC mode. */          
+    ret = HASH_DIGEST_CALCULATION_STARTED;          
+    /* Reset buffer counter */
+    hhash->HashInCount = 0;
+  }
+  
+  /* Return whether or digest calculation has started */
+  return ret;
+}
+
+/**
+  * @brief  HMAC processing in polling mode.
+  * @param  hhash: HASH handle.
+  * @param  Timeout: Timeout value.  
+  * @retval HAL status
+  */ 
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
+{
+  /* Ensure first that Phase is correct */
+  if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+  
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* HMAC Step 1 processing */
+  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+  {
+    /************************** STEP 1 ******************************************/
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+    
+    /* Write input buffer in Data register */
+    if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK)
+    {
+      return hhash->Status;
+    }
+    
+    /* Check whether or not key entering process has been suspended */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
+    
+      /* Stop right there and return function status */
+      return HAL_OK;
+    }   
+    
+    /* No processing suspension at this point: set DCAL bit. */
+    __HAL_HASH_START_DIGEST();
+    
+    /* Wait for BUSY flag to be cleared */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    
+    /* Move from Step 1 to Step 2 */
+    hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
+     
+  }
+  
+  /* HMAC Step 2 processing.
+     After phase check, HMAC_Processing() may 
+     - directly start up from this point in resumption case
+       if the same Step 2 processing was suspended previously
+    - or fall through from the Step 1 processing carried out hereabove */
+  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+  {
+    /************************** STEP 2 ******************************************/
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
+    
+    /* Write input buffer in Data register */
+    if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount)) != HAL_OK)
+    {
+      return hhash->Status;
+    }       
+    
+    /* Check whether or not data entering process has been suspended */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
+    
+      /* Stop right there and return function status */
+      return HAL_OK;
+    }   
+    
+    /* No processing suspension at this point: set DCAL bit. */
+    __HAL_HASH_START_DIGEST();
+    
+    /* Wait for BUSY flag to be cleared */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    } 
+    
+    /* Move from Step 2 to Step 3 */ 
+    hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; 
+    /* In case Step 1 phase was suspended then resumed,
+       set again Key input buffers and size before moving to
+       next step */
+    hhash->pHashKeyBuffPtr = hhash->Init.pKey;
+    hhash->HashKeyCount    = hhash->Init.KeySize;
+  }
+         
+    
+ /* HMAC Step 3 processing.
+     After phase check, HMAC_Processing() may 
+     - directly start up from this point in resumption case
+       if the same Step 3 processing was suspended previously
+    - or fall through from the Step 2 processing carried out hereabove */
+  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+  { 
+    /************************** STEP 3 ******************************************/
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+    
+    /* Write input buffer in Data register */
+    if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK)
+    {
+      return hhash->Status;
+    }       
+    
+    /* Check whether or not key entering process has been suspended */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
+    
+      /* Stop right there and return function status */
+      return HAL_OK;
+    }   
+    
+    /* No processing suspension at this point: start the Digest calculation. */
+    __HAL_HASH_START_DIGEST();
+    
+    /* Wait for DCIS flag to be set */
+     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }  
+    
+    /* Read the message digest */
+    HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+  }    
+  
+   /* Change the HASH state */
+   hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process Unlock */
+   __HAL_UNLOCK(hhash);
+  
+   /* Return function status */
+   return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Timeout: Timeout value. 
+  * @param  Algorithm: HASH algorithm.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+{
+  uint8_t *pInBuffer_tmp;  /* input data address, input parameter of HASH_WriteData()         */
+  uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */
+
+  /* Initiate HASH processing in case of start or resumption */
+  if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }  
+
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+    
+  /* Check if initialization phase has not been already performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+    MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); 
+    
+    /* Configure the number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(Size);
+    
+    /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as 
+       input parameters of HASH_WriteData() */
+    pInBuffer_tmp = pInBuffer;   /* pInBuffer_tmp is set to the input data address */
+    Size_tmp = Size;             /* Size_tmp contains the input data size in bytes */
+    
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;     
+  }
+  else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) 
+  {
+    /* if the IP has already been initialized, two cases are possible */
+    
+    /* Process resumption time ... */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set 
+        to the API input parameters but to those saved beforehand by HASH_WriteData()
+        when the processing was suspended */
+      pInBuffer_tmp = hhash->pHashInBuffPtr;
+      Size_tmp = hhash->HashInCount;
+    }
+    /* ... or multi-buffer HASH processing end */
+    else   
+    {
+      /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as 
+         input parameters of HASH_WriteData() */    
+      pInBuffer_tmp = pInBuffer;
+      Size_tmp = Size; 
+      /* Configure the number of valid bits in last word of the message */ 
+      __HAL_HASH_SET_NBVALIDBITS(Size);  
+    }
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;     
+  }
+  else
+  {
+    /* Phase error */
+    hhash->State = HAL_HASH_STATE_READY;
+  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+  
+    /* Return function status */
+    return HAL_ERROR;  
+  }
+  
+  
+  /* Write input buffer in Data register */
+  if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK)
+  {
+    return hhash->Status;
+  }    
+  
+  /* If the process has not been suspended, carry on to digest calculation */
+  if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+  {  
+    /* Start the Digest calculation */
+    __HAL_HASH_START_DIGEST();
+    
+    /* Wait for DCIS flag to be set */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+  
+    /* Read the message digest */
+    HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
+    
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+    
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+  
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  If not already done, initialize the HASH peripheral then 
+  *         processes pInBuffer.
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.   
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.       
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
+  * @param  Algorithm: HASH algorithm.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+  uint8_t *pInBuffer_tmp;   /* input data address, input parameter of HASH_WriteData()         */
+  uint32_t Size_tmp = 0x0;  /* input data size (in bytes), input parameter of HASH_WriteData() */
+  
+  /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+   assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
+  
+    
+  /* Initiate HASH processing in case of start or resumption */
+  if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))  
+  {
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }   
+   
+     /* Process Locked */
+    __HAL_LOCK(hhash);
+    
+    /* If resuming the HASH processing */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+    
+      /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set 
+         to the API input parameters but to those saved beforehand by HASH_WriteData()
+         when the processing was suspended */
+      pInBuffer_tmp = hhash->pHashInBuffPtr;  /* pInBuffer_tmp is set to the input data address */
+      Size_tmp = hhash->HashInCount;          /* Size_tmp contains the input data size in bytes */
+      
+    }
+    else  
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY; 
+      
+      /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as 
+         input parameters of HASH_WriteData() */   
+      pInBuffer_tmp = pInBuffer;    /* pInBuffer_tmp is set to the input data address */ 
+      Size_tmp = Size;              /* Size_tmp contains the input data size in bytes */ 
+      
+      /* Check if initialization phase has already be performed */
+      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      {
+        /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); 
+      }
+    
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+      
+    }  
+    
+    /* Write input buffer in Data register */
+    if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK)
+    {
+      return hhash->Status;
+    }    
+    
+    /* If the process has not been suspended, move the state to Ready */
+    if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Return function status */
+    return HAL_OK; 
+    
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+    
+ 
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral, next process pInBuffer then
+  *         read the computed digest in interruption mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Algorithm: HASH algorithm.    
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+{
+    
+  /* If State is ready or suspended, start or resume IT-based HASH processing */
+  if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))  
+  {
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+      
+    /* Process Locked */
+    __HAL_LOCK(hhash);    
+      
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    /* Initialize IT counter */
+    hhash->HashITCounter = 1;
+    
+    /* Check if initialization phase has already be performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+      MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); 
+      
+      /* Configure the number of valid bits in last word of the message */
+     __HAL_HASH_SET_NBVALIDBITS(Size);  
+     
+
+      hhash->HashInCount = Size;               /* Counter used to keep track of number of data
+                                                  to be fed to the IP */ 
+      hhash->pHashInBuffPtr = pInBuffer;       /* Points at data which will be fed to the IP at 
+                                                  the next interruption */
+     /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain 
+        the information describing where the HASH process is stopped. 
+        These variables are used later on to resume the HASH processing at the 
+        correct location. */                                                   
+                           
+      hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */      
+    }
+    
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral then initiate a DMA transfer
+  *         to feed the input buffer to the IP.   
+  * @note   If MDMAT bit is set before calling this function (multi-buffer
+  *          HASH processing case), the input buffer size (in bytes) must be 
+  *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
+  *          For the processing of the last buffer of the thread, MDMAT bit must
+  *          be reset and the buffer length (in bytes) doesn't have to be a 
+  *          multiple of 4.          
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  Algorithm: HASH algorithm.    
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{ 
+  uint32_t inputaddr;
+  uint32_t inputSize = 0x0;
+  
+  /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set 
+     (case of multi-buffer HASH processing) */
+  assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
+  
+  /* If State is ready or suspended, start or resume DMA-based HASH processing */
+  if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Check input parameters */ 
+    if ( (pInBuffer == NULL ) || (Size == 0) ||
+    /* Check phase coherency. Phase must be 
+       either READY (fresh start)
+       or PROCESS (multi-buffer HASH management) */    
+       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+    
+    
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+    
+    /* If not a resumption case */
+    if (hhash->State == HAL_HASH_STATE_READY)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;      
+    
+      /* Check if initialization phase has already been performed. 
+         If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
+         API is processing a new input data message in case of multi-buffer HASH 
+         computation. */
+      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      {
+        /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); 
+      
+        /* Set the phase */
+        hhash->Phase = HAL_HASH_PHASE_PROCESS;      
+      }
+      
+      /* Configure the Number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(Size); 
+    
+      inputaddr = (uint32_t)pInBuffer;     /* DMA transfer start address   */    
+      inputSize = Size;                    /* DMA transfer size (in bytes) */  
+      
+      /* In case of suspension request, save the starting parameters */
+      hhash->pHashInBuffPtr =  pInBuffer;  /* DMA transfer start address   */
+      hhash->HashInCount = Size;           /* DMA transfer size (in bytes) */              
+      
+    }
+    /* If resumption case */
+    else
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY; 
+                
+      /* Resumption case, inputaddr and inputSize are not set to the API input parameters 
+         but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the 
+         processing was suspended */  
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;  /* DMA transfer start address   */  
+      inputSize = hhash->HashInCount;               /* DMA transfer size (in bytes) */
+    }
+      
+    /* Set the HASH DMA transfert complete callback */
+    hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+    /* Set the DMA error callback */
+    hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+    /* Store number of words already pushed to manage proper DMA processing suspension */
+    hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); 
+    
+    /* Enable the DMA In DMA Stream */
+    HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4));
+    
+    /* Enable DMA requests */
+    SET_BIT(HASH->CR, HASH_CR_DMAE);
+    
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}
+
+/**
+  * @brief  Return the computed digest.
+  * @note   The API waits for DCIS to be set then reads the computed digest.  
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Timeout: Timeout value.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{  
+
+  if(hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Check parameter */
+    if (pOutBuffer == NULL)
+    {
+      return  HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+  
+    /* Change the HASH state to busy */
+    hhash->State = HAL_HASH_STATE_BUSY;
+  
+    /* Wait for DCIS flag to be set */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {  
+      return HAL_TIMEOUT;
+    }
+  
+    /* Read the message digest */
+    HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
+  
+    /* Change the HASH state to ready */
+    hhash->State = HAL_HASH_STATE_READY;
+  
+    /* Process UnLock */
+    __HAL_UNLOCK(hhash);
+  
+    /* Return function status */
+    return HAL_OK;
+ 
+  }
+  else
+  {
+    return HAL_BUSY;
+  }    
+ 
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Timeout: Timeout value. 
+  * @param  Algorithm: HASH algorithm.     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+{ 
+
+  /* If State is ready or suspended, start or resume polling-based HASH processing */
+  if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+      
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    /* Check if initialization phase has already be performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+      if(hhash->Init.KeySize > 64)
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);      
+      }
+      else
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);      
+      }
+      /* Set the phase to Step 1 */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+      /* Resort to hhash internal fields to feed the IP.
+         Parameters will be updated in case of suspension to contain the proper
+         information at resumption time. */
+      hhash->pHashOutBuffPtr  = pOutBuffer;            /* Output digest address                                              */
+      hhash->pHashInBuffPtr   = pInBuffer;             /* Input data address, HMAC_Processing input parameter for Step 2     */
+      hhash->HashInCount      = Size;                  /* Input data size, HMAC_Processing input parameter for Step 2        */
+      hhash->HashBuffSize     = Size;                  /* Store the input buffer size for the whole HMAC process             */    
+      hhash->pHashKeyBuffPtr  = hhash->Init.pKey;      /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
+      hhash->HashKeyCount     = hhash->Init.KeySize;   /* Key size, HMAC_Processing input parameter for Step 1 and Step 3    */  
+    }
+    
+    /* Carry out HMAC processing */
+    return HMAC_Processing(hhash, Timeout);
+ 
+  }
+  else
+  {
+    return HAL_BUSY;
+  }  
+}
+
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Algorithm: HASH algorithm.     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+{ 
+  /* If State is ready or suspended, start or resume IT-based HASH processing */
+  if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+      
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+    
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    /* Initialize IT counter */
+    hhash->HashITCounter = 1;
+    
+    /* Check if initialization phase has already be performed */
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+      if(hhash->Init.KeySize > 64)
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);      
+      }
+      else
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);      
+      }
+    
+      /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
+         to feed the IP whatever the HMAC step.
+         Lines below are set to start HMAC Step 1 processing where key is entered first. */
+      hhash->HashInCount     = hhash->Init.KeySize; /* Key size                      */  
+      hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* Key address                   */ 
+      
+      /* Store input and output parameters in handle fields to manage steps transition 
+         or possible HMAC suspension/resumption */
+      hhash->pHashKeyBuffPtr = hhash->Init.pKey;    /* Key address                   */
+      hhash->pHashMsgBuffPtr = pInBuffer;           /* Input message address         */
+      hhash->HashBuffSize    = Size;                /* Input message size (in bytes) */ 
+      hhash->pHashOutBuffPtr = pOutBuffer;          /* Output digest address         */ 
+         
+      /* Configure the number of valid bits in last word of the key */
+      __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+    
+      /* Set the phase to Step 1 */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+    }
+    else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+    {
+      /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
+    
+    }
+    else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+    {
+      /* Restart IT-based HASH processing after Step 2 suspension */    
+    
+    }
+    else
+    {
+      /* Error report as phase incorrect */
+      /* Process Unlock */
+      __HAL_UNLOCK(hhash);
+      hhash->State = HAL_HASH_STATE_READY;
+      return HAL_ERROR;    
+    }
+    
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}  
+
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC mode then initiate the required 
+  *         DMA transfers to feed the key and the input buffer to the IP. 
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   In case of multi-buffer HMAC processing, the input buffer size (in bytes) must 
+  *         be a multiple of 4 otherwise, the HASH digest computation is corrupted.
+  *         Only the length of the last buffer of the thread doesn't have to be a 
+  *         multiple of 4.           
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  Algorithm: HASH algorithm.    
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+  uint32_t inputaddr;
+  uint32_t inputSize = 0x0;
+  
+   /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
+      is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
+   assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
+  
+  /* If State is ready or suspended, start or resume DMA-based HASH processing */  
+  if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Check input parameters */
+    if ((pInBuffer == NULL ) || (Size == 0) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0) ||
+   /* Check phase coherency. Phase must be 
+       either READY (fresh start)
+       or one of HMAC PROCESS steps (multi-buffer HASH management) */    
+       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+  
+  
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+  
+    /* If not a case of resumption after suspension */
+    if (hhash->State == HAL_HASH_STATE_READY)
+    {
+    /* Check whether or not initialization phase has already be performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+  
+      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. 
+         At the same time, ensure MDMAT bit is cleared. */
+      if(hhash->Init.KeySize > 64)
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);      
+      }
+      else
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);      
+      }      
+      
+      /* Store input aparameters in handle fields to manage steps transition 
+         or possible HMAC suspension/resumption */
+      hhash->HashInCount = hhash->Init.KeySize;   /* Initial size for first DMA transfer (key size)      */
+      hhash->pHashKeyBuffPtr = hhash->Init.pKey;  /* Key address                                         */
+      hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+      hhash->pHashMsgBuffPtr = pInBuffer;         /* Input data address                                  */
+      hhash->HashBuffSize = Size;                 /* input data size (in bytes)                          */
+      
+      /* Set DMA input parameters */
+      inputaddr = (uint32_t)(hhash->Init.pKey);   /* Address passed to DMA (start by entering Key message) */
+      inputSize = hhash->Init.KeySize;            /* Size for first DMA transfer (in bytes) */
+ 
+      /* Configure the number of valid bits in last word of the key */
+      __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+    
+      /* Set the phase to Step 1 */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+      
+    }
+      else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+    {
+      /* Process a new input data message in case of multi-buffer HMAC processing 
+        (this is not a resumption case) */
+        
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* Save input parameters to be able to manage possible suspension/resumption */
+        hhash->HashInCount = Size;                /* Input message address       */
+        hhash->pHashInBuffPtr = pInBuffer;        /* Input message size in bytes */
+      
+      /* Set DMA input parameters */
+        inputaddr = (uint32_t)pInBuffer;           /* Input message address       */
+        inputSize = Size;                          /* Input message size in bytes */
+      
+      if (hhash->DigestCalculationDisable == RESET)
+      {
+        /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+        __HAL_HASH_RESET_MDMAT();
+        __HAL_HASH_SET_NBVALIDBITS(inputSize);
+      }    
+    }
+      else
+      {
+        /* Phase not aligned with handle READY state */
+        __HAL_UNLOCK(hhash);
+        /* Return function status */
+        return HAL_ERROR;      
+      }
+    }
+    else
+    {
+       /* Resumption case (phase may be Step 1, 2 or 3) */
+       
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+          
+      /* Set DMA input parameters at resumption location; 
+         inputaddr and inputSize are not set to the API input parameters 
+         but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the 
+         processing was suspended. */       
+      inputaddr = (uint32_t)(hhash->pHashInBuffPtr);  /* Input message address       */
+      inputSize = hhash->HashInCount;                 /* Input message size in bytes */
+    }
+
+  
+    /* Set the HASH DMA transfert complete callback */
+    hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+    /* Set the DMA error callback */
+    hhash->hdmain->XferErrorCallback = HASH_DMAError;
+    
+    /* Store number of words already pushed to manage proper DMA processing suspension */
+    hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); 
+    
+    /* Enable the DMA In DMA Stream */
+    HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4));
+    /* Enable DMA requests */
+    SET_BIT(HASH->CR, HASH_CR_DMAE);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L4A6xx) */
+
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h
new file mode 100755
index 0000000..17682fa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h
@@ -0,0 +1,582 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hash.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of HASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_HASH_H
+#define __STM32L4xx_HAL_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup HASH_Exported_Types HASH Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HASH Configuration Structure definition  
+  */
+typedef struct
+{  
+  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
+                              This parameter can be a value of @ref HASH_Data_Type. */
+  
+  uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */
+  
+  uint8_t* pKey;        /*!< The key is used only in HMAC operation. */
+    
+} HASH_InitTypeDef;
+
+/** 
+  * @brief HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_HASH_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized            */
+  HAL_HASH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_HASH_STATE_BUSY              = 0x02,    /*!< Processing (hashing) is ongoing          */
+  HAL_HASH_STATE_TIMEOUT           = 0x06,    /*!< Timeout state                            */
+  HAL_HASH_STATE_ERROR             = 0x07,    /*!< Error state                              */
+  HAL_HASH_STATE_SUSPENDED         = 0x08     /*!< Suspended state                          */          
+}HAL_HASH_StateTypeDef;
+
+/** 
+  * @brief HAL phase structures definition  
+  */ 
+typedef enum
+{
+  HAL_HASH_PHASE_READY             = 0x01,    /*!< HASH peripheral is ready to start                    */
+  HAL_HASH_PHASE_PROCESS           = 0x02,    /*!< HASH peripheral is in HASH processing phase          */
+  HAL_HASH_PHASE_HMAC_STEP_1       = 0x03,    /*!< HASH peripheral is in HMAC step 1 processing phase
+                                              (step 1 consists in entering the inner hash function key) */
+  HAL_HASH_PHASE_HMAC_STEP_2       = 0x04,    /*!< HASH peripheral is in HMAC step 2 processing phase
+                                              (step 2 consists in entering the message text) */
+  HAL_HASH_PHASE_HMAC_STEP_3       = 0x05     /*!< HASH peripheral is in HMAC step 3 processing phase
+                                              (step 3 consists in entering the outer hash function key) */
+}HAL_HASH_PhaseTypeDef;
+
+/** 
+  * @brief HAL HASH mode suspend definitions
+  */
+typedef enum
+{
+  HAL_HASH_SUSPEND_NONE            = 0x00,    /*!< HASH peripheral suspension not requested */
+  HAL_HASH_SUSPEND                 = 0x01     /*!< HASH peripheral suspension is requested  */                                                                                                                                                                                                                                                                  
+}HAL_HASH_SuspendTypeDef;
+
+
+/** 
+  * @brief  HASH Handle Structure definition  
+  */ 
+typedef struct
+{   
+  HASH_InitTypeDef           Init;             /*!< HASH required parameters */
+  
+  uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */
+
+  uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
+    
+  uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
+
+  uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */             
+
+  uint32_t                   HashBuffSize;     /*!< Size of buffer to be processed */
+
+  __IO uint32_t              HashInCount;      /*!< Counter of inputted data */
+                            
+  __IO uint32_t              HashITCounter;    /*!< Counter of issued interrupts */
+   
+  __IO uint32_t              HashKeyCount;     /*!< Counter for Key inputted data (HMAC only) */
+      
+  HAL_StatusTypeDef          Status;           /*!< HASH peripheral status   */
+
+  HAL_HASH_PhaseTypeDef      Phase;            /*!< HASH peripheral phase   */
+
+  DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters */
+
+  HAL_LockTypeDef            Lock;             /*!< Locking object */
+
+  __IO HAL_HASH_StateTypeDef State;            /*!< HASH peripheral state */
+   
+  HAL_HASH_SuspendTypeDef    SuspendRequest;   /*!< HASH peripheral suspension request flag */        
+   
+  FlagStatus                 DigestCalculationDisable;  /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
+  
+  __IO uint32_t              NbWordsAlreadyPushed;      /*!< Numbers of words already pushed in FIFO before inputting new block */          
+
+} HASH_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants  HASH Exported Constants
+  * @{
+  */
+
+/** @defgroup HASH_Algo_Selection   HASH algorithm selection
+  * @{
+  */ 
+#define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000) /*!< HASH function is SHA1   */
+#define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */
+#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Algorithm_Mode   HASH algorithm mode
+  * @{
+  */ 
+#define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000) /*!< Algorithm is HASH */ 
+#define HASH_ALGOMODE_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Data_Type      HASH input data type
+  * @{
+  */  
+#define HASH_DATATYPE_32B          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
+#define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
+#define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
+#define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode   HMAC key length type
+  * @{
+  */ 
+#define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY           /*!< HMAC Key size is > 64 bytes  */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_flags_definition  HASH flags definitions
+  * @{
+  */  
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                             */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing              */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                       */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data     */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup HASH_interrupts_definition   HASH interrupts definitions
+  * @{
+  */  
+#define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
+
+/**
+  * @}
+  */
+  
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
+/**
+  * @}
+  */  
+  
+  
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HASH_Exported_Macros HASH Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether or not the specified HASH flag is set.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. 
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
+  *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
+  *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.                 
+  *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \
+                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+
+
+/** @brief  Clear the specified HASH flag.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. 
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
+
+
+/** @brief  Enable the specified HASH interrupt.
+  * @param  __INTERRUPT__: specifies the HASH interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief  Disable the specified HASH interrupt.
+  * @param  __INTERRUPT__: specifies the HASH interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Reset HASH handle state.
+  * @param  __HANDLE__: HASH handle.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+
+/** @brief Reset HASH handle status.
+  * @param  __HANDLE__: HASH handle.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
+
+/**
+  * @brief  Enable the multi-buffer DMA transfer mode. 
+  * @note   This bit is set when hashing large files when multiple DMA transfers are needed.  
+  * @retval None
+  */
+#define __HAL_HASH_SET_MDMAT()          SET_BIT(HASH->CR, HASH_CR_MDMAT) 
+
+/**
+  * @brief  Disable the multi-buffer DMA transfer mode.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_MDMAT()        CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
+
+
+
+/**
+  * @brief Start the digest computation.
+  * @retval None
+  */
+#define __HAL_HASH_START_DIGEST()       SET_BIT(HASH->STR, HASH_STR_DCAL)
+
+/**
+  * @brief Set the number of valid bits in the last word written in data register DIN.
+  * @param  __SIZE__: size in bytes of last data written in Data register.
+  * @retval None
+*/
+#define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))                                             
+                                             
+/**
+  * @brief Reset the HASH core.
+  * @retval None
+  */
+#define __HAL_HASH_INIT()       SET_BIT(HASH->CR, HASH_CR_INIT)     
+
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros   HASH Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Return digest length in bytes.
+  * @retval Digest length
+  */
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20 : \
+                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28 : \
+                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32 : 16 ) ) )
+
+/**
+  * @brief  Return number of words already pushed in the FIFO.
+  * @retval Number of words already pushed in the FIFO
+  */
+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)  
+
+/**
+  * @brief Ensure that HASH input data type is valid.
+  * @param __DATATYPE__: HASH input data type. 
+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+  */                                              
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+                                        ((__DATATYPE__) == HASH_DATATYPE_1B))  
+                                    
+                                    
+                                             
+/**
+  * @brief Ensure that input data buffer size is valid for multi-buffer HASH 
+  *        processing in polling mode.
+  * @note  This check is valid only for multi-buffer HASH processing in polling mode.  
+  * @param __SIZE__: input data buffer size. 
+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+  */
+#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__)  (((__SIZE__) % 4) == 0)
+
+/**
+  * @brief Ensure that input data buffer size is valid for multi-buffer HASH 
+  *        processing in DMA mode.
+  * @note  This check is valid only for multi-buffer HASH processing in DMA mode.  
+  * @param __SIZE__: input data buffer size. 
+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+  */  
+#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__)  ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))  
+
+/**
+  * @brief Ensure that input data buffer size is valid for multi-buffer HMAC 
+  *        processing in DMA mode.
+  * @note  This check is valid only for multi-buffer HMAC processing in DMA mode.
+  * @param __HANDLE__: HASH handle.    
+  * @param __SIZE__: input data buffer size. 
+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+  */   
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))                                                                                                                                                      
+
+/**
+  * @brief Ensure that handle phase is set to HASH processing.
+  * @param __HANDLE__: HASH handle.    
+  * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
+  */   
+#define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
+
+/**
+  * @brief Ensure that handle phase is set to HMAC processing.
+  * @param __HANDLE__: HASH handle.    
+  * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
+  */   
+#define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+
+/**
+  * @}
+  */
+
+
+/* Include HASH HAL Extended module */
+#include "stm32l4xx_hal_hash_ex.h"
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions
+  * @{
+  */
+  
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+
+/* Initialization/de-initialization methods  **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode  
+  * @{
+  */
+
+
+/* HASH processing using polling  *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode  
+  * @{
+  */
+
+/* HASH processing using IT  **************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode  
+  * @{
+  */
+
+/* HASH processing using DMA  *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode  
+  * @{
+  */
+
+/* HASH-MAC processing using polling  *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode  
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode  
+  * @{
+  */
+
+/* HASH-HMAC processing using DMA  ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions 
+  * @{
+  */
+
+
+/* Peripheral State methods  **************************************************/
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/  
+
+/** @addtogroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */
+
+/* Private functions */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+  
+#endif /* defined (STM32L4A6xx) */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_HASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c
new file mode 100755
index 0000000..ffa5eec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c
@@ -0,0 +1,934 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hash_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended HASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the HASH peripheral for SHA-224 and SHA-256
+  *          alogrithms:
+  *           + HASH or HMAC processing in polling mode
+  *           + HASH or HMAC processing in interrupt mode
+  *           + HASH or HMAC processing in DMA mode
+  *         Additionally, this file provides functions to manage HMAC
+  *         multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 
+  *         and SHA-256.      
+  *                         
+  *         
+  @verbatim
+ ===============================================================================
+                     ##### HASH peripheral extended features  #####
+ ===============================================================================
+    [..]                                
+    The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
+    the same way as for SHA-1 or MD-5 algorithms.
+    (#) Three modes are available.
+        (##) Polling mode: processing APIs are blocking functions
+             i.e. they process the data and wait till the digest computation is finished,
+             e.g. HAL_HASHEx_xxx_Start()
+        (##) Interrupt mode: processing APIs are not blocking functions
+                i.e. they process the data under interrupt,
+                e.g. HAL_HASHEx_xxx_Start_IT()
+        (##) DMA mode: processing APIs are not blocking functions and the CPU is
+             not used for data transfer i.e. the data transfer is ensured by DMA,
+                e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to 
+                HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
+                
+   (#)Multi-buffer processing is possible in polling and DMA mode. 
+        (##) In polling mode, only multi-buffer HASH processing is possible. 
+             API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
+             User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as 
+             well the computed digest.
+             
+        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+
+              (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
+             From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
+             Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+             macro then wrap-up the HASH processing in feeding the last input buffer thru the
+             same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to  
+             API HAL_HASHEx_xxx_Finish().
+             
+             (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
+             extended functions): after initialization, the key and the first input buffer are entered
+             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+             starts step 2.
+             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
+             point, the HMAC processing is still carrying out step 2.
+             Then, step 2 for the last input buffer and step 3 are carried out by a single call 
+             to HAL_HMACEx_xxx_Step2_3_DMA().
+             
+             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
+             MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.                
+    
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+#if defined (STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HASHEx HASHEx
+  * @brief HASH HAL extended module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
+  * @{
+  */
+
+
+/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode  
+ *  @brief   HASH extended processing functions using polling mode. 
+ *
+@verbatim   
+ ===============================================================================
+               ##### Polling mode HASH extended processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the hash value using one of the following algorithms:
+      (+) SHA224
+         (++) HAL_HASHEx_SHA224_Start() 
+         (++) HAL_HASHEx_SHA224_Accumulate()                
+      (+) SHA256
+         (++) HAL_HASHEx_SHA256_Start() 
+         (++) HAL_HASHEx_SHA256_Accumulate()          
+      
+    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
+          
+    [..]  In case of multi-buffer HASH processing (a single digest is computed while
+          several buffers are fed to the IP), the user can resort to successive calls
+          to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
+          to HAL_HASHEx_xxx_Start(). 
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  If not already done, initialize the HASH peripheral in SHA224 mode then 
+  *         processes pInBuffer.
+  * @note   Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed 
+  *         several input buffers back-to-back to the IP that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input 
+  *         buffers feeding and retrieval of digest is done by a call to 
+  *         HAL_HASHEx_SHA224_Start().  
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.   
+  * @note   Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
+  *         to read it, feeding at the same time the last input buffer to the IP.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
+  *         to manage the ending buffer with a length in bytes not a multiple of 4.       
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+  * @param  Timeout: Timeout value    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+  * @brief  If not already done, initialize the HASH peripheral in SHA256 mode then 
+  *         processes pInBuffer.
+  * @note   Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed 
+  *         several input buffers back-to-back to the IP that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input 
+  *         buffers feeding and retrieval of digest is done by a call to 
+  *         HAL_HASHEx_SHA256_Start().  
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.   
+  * @note   Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
+  *         to read it, feeding at the same time the last input buffer to the IP.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
+  *         to manage the ending buffer with a length in bytes not a multiple of 4.       
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode 
+ *  @brief   HASH extended processing functions using interrupt mode. 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Interruption mode HASH extended processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in interrupt mode
+          the hash value using one of the following algorithms:
+      (+) SHA224
+         (++) HAL_HASHEx_SHA224_Start_IT()           
+      (+) SHA256
+         (++) HAL_HASHEx_SHA256_Start_IT()
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode 
+ *  @brief   HASH extended processing functions using DMA mode. 
+ *
+@verbatim   
+ ===============================================================================
+                ##### DMA mode HASH extended  processing functionss #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the hash value using one of the following algorithms:
+      (+) SHA224
+         (++) HAL_HASHEx_SHA224_Start_DMA() 
+         (++) HAL_HASHEx_SHA224_Finish()            
+      (+) SHA256
+         (++) HAL_HASHEx_SHA256_Start_DMA()
+         (++) HAL_HASHEx_SHA256_Finish()
+         
+    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
+          to  HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with 
+          HAL_HASHEx_xxx_Finish(). 
+          
+    [..]  In case of multi-buffer HASH processing, MDMAT bit must first be set before
+          the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be 
+          reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
+          retrieved thanks to HAL_HASHEx_xxx_Finish(). 
+
+@endverbatim
+  * @{
+  */
+
+
+
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
+  *         to feed the input buffer to the IP. 
+  * @note   Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
+  *         be called to retrieve the computed digest.   
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); 
+}
+
+/**
+  * @brief  Return the computed digest in SHA224 mode.
+  * @note   The API waits for DCIS to be set then reads the computed digest.
+  * @note   HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
+  *         HMAC SHA224 mode.    
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+  * @param  Timeout: Timeout value.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{  
+   return HASH_Finish(hhash, pOutBuffer, Timeout);   
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
+  *         to feed the input buffer to the IP. 
+  * @note   Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
+  *         be called to retrieve the computed digest.   
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); 
+}
+
+/**
+  * @brief  Return the computed digest in SHA256 mode.
+  * @note   The API waits for DCIS to be set then reads the computed digest.
+  * @note   HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
+  *         HMAC SHA256 mode.     
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+  * @param  Timeout: Timeout value.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{  
+   return HASH_Finish(hhash, pOutBuffer, Timeout);   
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode 
+ *  @brief   HMAC extended processing functions using polling mode. 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Polling mode HMAC extended processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the HMAC value using one of the following algorithms:
+      (+) SHA224
+         (++) HAL_HMACEx_SHA224_Start()              
+      (+) SHA256
+         (++) HAL_HMACEx_SHA256_Start() 
+
+@endverbatim
+  * @{
+  */
+
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+  * @param  Timeout: Timeout value.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{ 
+  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+  *         read the computed digest.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+  * @param  Timeout: Timeout value.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{ 
+  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+  * @}
+  */
+  
+  
+/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode 
+ *  @brief   HMAC extended processing functions using interruption mode. 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupt mode HMAC extended processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in interrupt mode
+          the HMAC value using one of the following algorithms:
+      (+) SHA224
+         (++) HAL_HMACEx_SHA224_Start_IT()              
+      (+) SHA256
+         (++) HAL_HMACEx_SHA256_Start_IT() 
+
+@endverbatim
+  * @{
+  */
+  
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+  *         read the computed digest in interrupt mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{ 
+  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
+}  
+  
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+  *         read the computed digest in interrupt mode.  
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.    
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{ 
+  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
+}  
+    
+    
+   
+  
+/**
+  * @}
+  */
+    
+
+/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode 
+ *  @brief   HMAC extended processing functions using DMA mode. 
+ *
+@verbatim   
+ ===============================================================================
+              ##### DMA mode HMAC extended processing functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the HMAC value using one of the following algorithms:
+      (+) SHA224
+         (++) HAL_HMACEx_SHA224_Start_DMA()                        
+      (+) SHA256
+         (++) HAL_HMACEx_SHA256_Start_DMA()
+         
+    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing, 
+          user must resort to  HAL_HMACEx_xxx_Start_DMA() then read the resulting digest 
+          with HAL_HASHEx_xxx_Finish().                              
+
+
+@endverbatim
+  * @{
+  */
+
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required 
+  *         DMA transfers to feed the key and the input buffer to the IP. 
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve 
+  *         the computed digest.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   If MDMAT bit is set before calling this function (multi-buffer
+  *          HASH processing case), the input buffer size (in bytes) must be 
+  *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
+  *          For the processing of the last buffer of the thread, MDMAT bit must
+  *          be reset and the buffer length (in bytes) doesn't have to be a 
+  *          multiple of 4.           
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required 
+  *         DMA transfers to feed the key and the input buffer to the IP. 
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve 
+  *         the computed digest.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. 
+  * @note   If MDMAT bit is set before calling this function (multi-buffer
+  *          HASH processing case), the input buffer size (in bytes) must be 
+  *          a multiple of 4 otherwise, the HASH digest computation is corrupted.
+  *          For the processing of the last buffer of the thread, MDMAT bit must
+  *          be reset and the buffer length (in bytes) doesn't have to be a 
+  *          multiple of 4.          
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode 
+ *  @brief   HMAC extended processing functions in multi-buffer DMA mode. 
+ *
+@verbatim   
+ ===============================================================================
+      ##### Multi-buffer DMA mode HMAC extended processing functions #####
+ ===============================================================================
+    [..]  This section provides functions to manage HMAC multi-buffer 
+          DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
+      (+) MD5
+         (++) HAL_HMACEx_MD5_Step1_2_DMA() 
+         (++) HAL_HMACEx_MD5_Step2_DMA()     
+         (++) HAL_HMACEx_MD5_Step2_3_DMA() 
+      (+) SHA1
+         (++) HAL_HMACEx_SHA1_Step1_2_DMA() 
+         (++) HAL_HMACEx_SHA1_Step2_DMA()     
+         (++) HAL_HMACEx_SHA1_Step2_3_DMA() 
+      (+) SHA256
+         (++) HAL_HMACEx_SHA224_Step1_2_DMA() 
+         (++) HAL_HMACEx_SHA224_Step2_DMA()     
+         (++) HAL_HMACEx_SHA224_Step2_3_DMA()                                         
+      (+) SHA256
+         (++) HAL_HMACEx_SHA256_Step1_2_DMA() 
+         (++) HAL_HMACEx_SHA256_Step2_DMA()     
+         (++) HAL_HMACEx_SHA256_Step2_3_DMA() 
+         
+    [..]  User must first start-up the multi-buffer DMA-based HMAC computation in
+          calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+          intiates step 2 with the first input buffer.
+          
+    [..]  The following buffers are next fed to the IP with a call to the API
+          HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
+          to this API.
+          
+    [..]  Multi-buffer DMA-based HMAC computation is wrapped up by a call to
+          HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input 
+          buffer to the IP then carries out step 3. 
+          
+    [..]  Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
+          SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256. 
+          
+    [..]  If only two buffers need to be consecutively processed, a call to
+          HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
+          is sufficient.                                                                   
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+  * @note   Step 1 consists in writing the inner hash function key in the IP, 
+  *         step 2 consists in writing the message text.       
+  * @note   The API carries out the HMAC step 1 then starts step 2 with
+  *         the first buffer entered to the IP. DCAL bit is not automatically set after
+  *         the message buffer feeding, allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.         
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = SET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+  * @brief  MD5 HMAC step 2 in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP.  
+  * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
+  *         parameter. DCAL bit is not automatically set after the message buffer feeding, 
+  *         allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. 
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.      
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  if (hhash->DigestCalculationDisable != SET)
+  {
+    return HAL_ERROR;  
+  }
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+  * @brief  MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP, 
+  *         step 3 consists in writing the outer hash function key.    
+  * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
+  *         parameter (the input buffer must be the last one of the multi-buffer thread)
+  *         then carries out HMAC step 3. 
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve 
+  *         the computed digest.      
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = RESET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+  * @brief  SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+  * @note   Step 1 consists in writing the inner hash function key in the IP, 
+  *         step 2 consists in writing the message text.   
+  * @note   The API carries out the HMAC step 1 then starts step 2 with
+  *         the first buffer entered to the IP. DCAL bit is not automatically set after
+  *         the message buffer feeding, allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. 
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.        
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = SET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @brief  SHA1 HMAC step 2 in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP.    
+  * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
+  *         parameter. DCAL bit is not automatically set after the message buffer feeding, 
+  *         allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. 
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.      
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  if (hhash->DigestCalculationDisable != SET)
+  {
+    return HAL_ERROR;  
+  }
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @brief  SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP, 
+  *         step 3 consists in writing the outer hash function key.    
+  * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
+  *         parameter (the input buffer must be the last one of the multi-buffer thread)
+  *         then carries out HMAC step 3. 
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve 
+  *         the computed digest.      
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = RESET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @brief  SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+  * @note   Step 1 consists in writing the inner hash function key in the IP, 
+  *         step 2 consists in writing the message text.   
+  * @note   The API carries out the HMAC step 1 then starts step 2 with
+  *         the first buffer entered to the IP. DCAL bit is not automatically set after
+  *         the message buffer feeding, allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. 
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.        
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = SET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  SHA224 HMAC step 2 in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP.    
+  * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
+  *         parameter. DCAL bit is not automatically set after the message buffer feeding, 
+  *         allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.       
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  if (hhash->DigestCalculationDisable != SET)
+  {
+    return HAL_ERROR;  
+  }
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP, 
+  *         step 3 consists in writing the outer hash function key.    
+  * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
+  *         parameter (the input buffer must be the last one of the multi-buffer thread)
+  *         then carries out HMAC step 3. 
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve 
+  *         the computed digest.      
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = RESET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+  * @brief  SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+  * @note   Step 1 consists in writing the inner hash function key in the IP, 
+  *         step 2 consists in writing the message text.   
+  * @note   The API carries out the HMAC step 1 then starts step 2 with
+  *         the first buffer entered to the IP. DCAL bit is not automatically set after
+  *         the message buffer feeding, allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.  
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.       
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = SET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+  * @brief  SHA256 HMAC step 2 in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP.    
+  * @note   The API carries on the HMAC step 2, applied to the buffer entered as input
+  *         parameter. DCAL bit is not automatically set after the message buffer feeding, 
+  *         allowing other messages DMA transfers to occur.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. 
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.      
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  if (hhash->DigestCalculationDisable != SET)
+  {
+    return HAL_ERROR;  
+  }
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+  * @brief  SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+  * @note   Step 2 consists in writing the message text in the IP, 
+  *         step 3 consists in writing the outer hash function key.    
+  * @note   The API wraps up the HMAC step 2 in processing the buffer entered as input
+  *         parameter (the input buffer must be the last one of the multi-buffer thread)
+  *         then carries out HMAC step 3. 
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and 
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back 
+  *         to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve 
+  *         the computed digest.      
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (message buffer).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  hhash->DigestCalculationDisable = RESET;
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L4A6xx) */
+
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h
new file mode 100755
index 0000000..3e930ed
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h
@@ -0,0 +1,182 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hash_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of HASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_HASH_EX_H
+#define __STM32L4xx_HAL_HASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HASHEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+                            
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
+  * @{
+  */
+  
+/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode 
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode  
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode   
+  * @{
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode   
+  * @{
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode  
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode  
+  * @{
+  */
+  
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#endif /* defined (STM32L4A6xx) */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_HASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c
new file mode 100755
index 0000000..e909779
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c
@@ -0,0 +1,1284 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hcd.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   HCD HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#)Declare a HCD_HandleTypeDef handle structure, for example:
+       HCD_HandleTypeDef  hhcd;
+        
+    (#)Fill parameters of Init structure in HCD handle
+  
+    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) 
+
+    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
+        (##) Enable the HCD/USB Low Level interface clock using the following macro
+             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
+           
+        (##) Initialize the related GPIO clocks
+        (##) Configure HCD pin-out
+        (##) Configure HCD NVIC interrupt
+    
+    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
+        (##) hhcd.pData = phost;
+
+    (#)Enable HCD transmission and reception:
+        (##) HAL_HCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HCD HCD 
+  * @brief HCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+  * @{
+  */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); 
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the Host driver.
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
+{ 
+  /* Check the HCD handle allocation */
+  if(hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+
+  if(hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhcd->Lock = HAL_UNLOCKED;
+  
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_HCD_MspInit(hhcd);
+  }
+
+  hhcd->State = HAL_HCD_STATE_BUSY;
+
+  /* Disable the Interrupts */
+ __HAL_HCD_DISABLE(hhcd);
+ 
+ /*Init the Core (common init.) */
+ USB_CoreInit(hhcd->Instance, hhcd->Init);
+ 
+ /* Force Host Mode*/
+ USB_SetCurrentMode(hhcd->Instance , USB_HOST_MODE);
+ 
+ /* Init Host */
+ USB_HostInit(hhcd->Instance, hhcd->Init);
+ 
+ hhcd->State= HAL_HCD_STATE_READY;
+ 
+ return HAL_OK;
+}
+
+/**
+  * @brief  Initialize a Host channel.
+  * @param  hhcd: HCD handle
+  * @param  ch_num: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum: Endpoint number.
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address : Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed: Current device speed.
+  *          This parameter can be one of these values:
+  *            HCD_SPEED_HIGH: High speed mode,
+  *            HCD_SPEED_FULL: Full speed mode,
+  *            HCD_SPEED_LOW: Low speed mode
+  * @param  ep_type: Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type,
+  *            EP_TYPE_ISOC: Isochronous type,
+  *            EP_TYPE_BULK: Bulk type,
+  *            EP_TYPE_INTR: Interrupt type
+  * @param  mps: Max Packet Size.
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  __HAL_LOCK(hhcd); 
+  
+  hhcd->hc[ch_num].dev_addr = dev_address;
+  hhcd->hc[ch_num].max_packet = mps;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].ep_type = ep_type;
+  hhcd->hc[ch_num].ep_num = epnum & 0x7F;
+  hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
+  hhcd->hc[ch_num].speed = speed;
+  /*  reset to 0 */
+  hhcd->hc[ch_num].toggle_out = 0;
+  hhcd->hc[ch_num].toggle_in = 0;
+
+  status =  USB_HC_Init(hhcd->Instance, 
+                        ch_num,
+                        epnum,
+                        dev_address,
+                        speed,
+                        ep_type,
+                        mps);
+  __HAL_UNLOCK(hhcd); 
+  
+  return status;
+}
+
+/**
+  * @brief  Halt a Host channel.
+  * @param  hhcd: HCD handle
+  * @param  ch_num: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  __HAL_LOCK(hhcd);   
+  USB_HC_Halt(hhcd->Instance, ch_num);   
+  __HAL_UNLOCK(hhcd);
+  
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the Host driver.
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Check the HCD handle allocation */
+  if(hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  hhcd->State = HAL_HCD_STATE_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_HCD_MspDeInit(hhcd);
+  
+   __HAL_HCD_DISABLE(hhcd);
+  
+  hhcd->State = HAL_HCD_STATE_RESET; 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the HCD MSP.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the HCD MSP.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions 
+  *  @brief   HCD IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data 
+    Transfer
+       
+@endverbatim
+  * @{
+  */
+  
+/**                                
+  * @brief  Submit a new URB for processing.
+  * @param  hhcd: HCD handle
+  * @param  ch_num: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  direction: Channel number.
+  *          This parameter can be one of these values:
+  *           0 : Output / 1 : Input
+  * @param  ep_type: Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type/
+  *            EP_TYPE_ISOC: Isochronous type/
+  *            EP_TYPE_BULK: Bulk type/
+  *            EP_TYPE_INTR: Interrupt type/
+  * @param  token: Endpoint Type.
+  *          This parameter can be one of these values:
+  *            0: HC_PID_SETUP / 1: HC_PID_DATA1
+  * @param  pbuff: pointer to URB data
+  * @param  length: Length of URB data
+  * @param  do_ping: activate do ping protocol (for high speed only).
+  *          This parameter can be one of these values:
+  *           0 : do ping inactive / 1 : do ping active 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                            uint8_t ch_num, 
+                                            uint8_t direction ,
+                                            uint8_t ep_type,  
+                                            uint8_t token, 
+                                            uint8_t* pbuff, 
+                                            uint16_t length,
+                                            uint8_t do_ping) 
+{
+  if ((hhcd->hc[ch_num].ep_is_in != direction)) {
+    if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){
+      /*  reconfigure the endpoint !!! from tx -> rx, and rx ->tx  */
+      USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+      if (direction)
+      {
+        USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+        USBx_HC(ch_num)->HCCHAR |= 1 << 15;
+      }
+      else
+      {
+        USBx_HC(ch_num)->HCINTMSK &= ~USB_OTG_HCINTMSK_BBERRM;
+        USBx_HC(ch_num)->HCCHAR &= ~(1 << 15);
+      }
+      hhcd->hc[ch_num].ep_is_in = direction;
+      /*  if reception put toggle_in to 1  */
+      if (direction == 1) hhcd->hc[ch_num].toggle_in=1;
+    }
+  }
+  hhcd->hc[ch_num].ep_type  = ep_type;
+  
+  if(token == 0)
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+  }
+  else
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+  }
+  
+  /* Manage Data Toggle */
+  switch(ep_type)
+  {
+  case EP_TYPE_CTRL:
+    if((token == 1) && (direction == 0)) /*send data */
+    {
+      if ( length == 0 )
+      { /* For Status OUT stage, Length==0, Status Out PID = 1 */
+        hhcd->hc[ch_num].toggle_out = 1;
+      }
+      
+      /* Set the Data Toggle bit as per the Flag */
+      if ( hhcd->hc[ch_num].toggle_out == 0)
+      { /* Put the PID 0 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
+      }
+      else
+      { /* Put the PID 1 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+      }
+      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
+      {
+        hhcd->hc[ch_num].do_ping = do_ping;
+      }
+    }
+    else if ((token == 1) && (direction == 1))
+    {
+      if( hhcd->hc[ch_num].toggle_in == 0)
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      }
+      else
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+      }
+    }
+    break;
+  
+  case EP_TYPE_BULK:
+    if(direction == 0)
+    {
+      /* Set the Data Toggle bit as per the Flag */
+      if ( hhcd->hc[ch_num].toggle_out == 0)
+      { /* Put the PID 0 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
+      }
+      else
+      { /* Put the PID 1 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+      }
+      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
+      {
+        hhcd->hc[ch_num].do_ping = do_ping;
+      }
+    }
+    else
+    {
+      if( hhcd->hc[ch_num].toggle_in == 0)
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      }
+      else
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+      }
+    }
+    
+    break;
+  case EP_TYPE_INTR:
+    if(direction == 0)
+    {
+      /* Set the Data Toggle bit as per the Flag */
+      if ( hhcd->hc[ch_num].toggle_out == 0)
+      { /* Put the PID 0 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
+      }
+      else
+      { /* Put the PID 1 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+      }
+    }
+    else
+    {
+      if( hhcd->hc[ch_num].toggle_in == 0)
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      }
+      else
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+      }
+    }
+    break;
+    
+  case EP_TYPE_ISOC: 
+    hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+    break;
+  }
+  
+  hhcd->hc[ch_num].xfer_buff = pbuff;
+  hhcd->hc[ch_num].xfer_len  = length;
+  hhcd->hc[ch_num].urb_state =   URB_IDLE;  
+  hhcd->hc[ch_num].xfer_count = 0 ;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].state = HC_IDLE;
+  
+  return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
+}
+
+/**
+  * @brief  Handle HCD interrupt request.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t i = 0 , interrupt = 0;
+  
+  /* ensure that we are in device mode */
+  if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
+  {
+    /* avoid spurious interrupt */
+    if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) 
+    {
+      return;
+    }
+    
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    }
+    
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
+    }
+
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
+    }   
+    
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
+    }     
+    
+    /* Handle Host Disconnect Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+    {
+      
+      /* Cleanup HPRT */
+      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+       
+      /* Handle Host Port Interrupts */
+      HAL_HCD_Disconnect_Callback(hhcd);
+       USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+    }
+    
+    /* Handle Host Port Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+    {
+      HCD_Port_IRQHandler (hhcd);
+    }
+    
+    /* Handle Host SOF Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+    {
+      HAL_HCD_SOF_Callback(hhcd);
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
+    }
+          
+    /* Handle Host channel Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+    {
+      interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
+      for (i = 0; i < hhcd->Init.Host_channels ; i++)
+      {
+        if (interrupt & (1 << i))
+        {
+          if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
+          {
+            HCD_HC_IN_IRQHandler (hhcd, i);
+          }
+          else
+          {
+            HCD_HC_OUT_IRQHandler (hhcd, i);
+          }
+        }
+      }
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
+    } 
+    
+    /* Handle Rx Queue Level Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
+    {
+      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+      
+      HCD_RXQLVL_IRQHandler (hhcd);
+      
+      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+  }
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_SOF_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Connection Event callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Connect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Disconnection Event callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+} 
+
+/**
+  * @brief  Notify URB state change callback.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  urb_state:
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/ 
+  *            URB_ERROR/  
+  *            URB_STALL/    
+  * @retval None
+  */
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  UNUSED(chnum);
+  UNUSED(urb_state);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   Management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the HCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the Host driver.
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
+{ 
+  __HAL_LOCK(hhcd); 
+  __HAL_HCD_ENABLE(hhcd);
+  USB_DriveVbus(hhcd->Instance, 1);  
+  __HAL_UNLOCK(hhcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Host driver.
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
+{ 
+  __HAL_LOCK(hhcd); 
+  USB_StopHost(hhcd->Instance);
+  __HAL_UNLOCK(hhcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the Host port.
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_ResetPort(hhcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the HCD handle state.
+  * @param  hhcd: HCD handle
+  * @retval HAL state
+  */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+{
+  return hhcd->State;
+}
+
+/**
+  * @brief  Return  URB state for a channel.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval URB state.
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/ 
+  *            URB_ERROR/  
+  *            URB_STALL      
+  */
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].urb_state;
+}
+
+
+/**
+  * @brief  Return the last Host transfer size.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval last transfer size in byte
+  */
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].xfer_count; 
+}
+  
+/**
+  * @brief  Return the Host Channel state.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval Host channel state
+  *          This parameter can be one of these values:
+  *            HC_IDLE/
+  *            HC_XFRC/
+  *            HC_HALTED/
+  *            HC_NYET/ 
+  *            HC_NAK/  
+  *            HC_STALL/ 
+  *            HC_XACTERR/  
+  *            HC_BBLERR/  
+  *            HC_DATATGLERR
+  */
+HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].state;
+}
+
+/**
+  * @brief  Return the current Host frame number.
+  * @param  hhcd: HCD handle
+  * @retval Current Host frame number
+  */
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetCurrentFrame(hhcd->Instance));
+}
+
+/**
+  * @brief  Return the Host enumeration speed.
+  * @param  hhcd: HCD handle
+  * @retval Enumeration speed
+  */
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetHostSpeed(hhcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup HCD_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Handle Host Channel IN interrupt requests.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t tmpreg = 0;
+      
+  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+  }  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    hhcd->hc[chnum].state = HC_STALL;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);    
+    USB_HC_Halt(hhcd->Instance, chnum);    
+  }
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    USB_HC_Halt(hhcd->Instance, chnum);  
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);    
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+  }    
+  
+  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);  
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
+  {
+    
+    if (hhcd->Init.dma_enable)
+    {
+      hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
+                               (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+    }
+    
+    hhcd->hc[chnum].state = HC_XFRC;
+    hhcd->hc[chnum].ErrCnt = 0;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+    
+    
+    if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+        (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    {
+      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+      USB_HC_Halt(hhcd->Instance, chnum); 
+      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+      
+    }
+    else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+    {
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+      hhcd->hc[chnum].urb_state = URB_DONE; 
+      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+    }
+    hhcd->hc[chnum].toggle_in ^= 1;
+    
+  }
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
+  {
+    int reactivate = 0;
+    __HAL_HCD_MASK_HALT_HC_INT(chnum); 
+    
+    if(hhcd->hc[chnum].state == HC_XFRC)
+    {
+      hhcd->hc[chnum].urb_state  = URB_DONE;      
+    }
+    
+    else if (hhcd->hc[chnum].state == HC_STALL) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_STALL;
+    }   
+    
+    else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+            (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      if(hhcd->hc[chnum].ErrCnt++ > 3)
+      {      
+        hhcd->hc[chnum].ErrCnt = 0;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      }
+      
+      /* re-activate the channel  */
+      tmpreg = USBx_HC(chnum)->HCCHAR;
+      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+      if ( hhcd->hc[chnum].urb_state != URB_ERROR) {
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        reactivate = 1;
+      }
+      USBx_HC(chnum)->HCCHAR = tmpreg;
+    }
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+    if (hhcd->hc[chnum].state == 0) reactivate = 1;
+    if (reactivate == 0) HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+  }  
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+     hhcd->hc[chnum].ErrCnt++;
+     hhcd->hc[chnum].state = HC_XACTERR;
+     USB_HC_Halt(hhcd->Instance, chnum);     
+     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+  }
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
+  { 
+    if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+    {
+      __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+      USB_HC_Halt(hhcd->Instance, chnum); 
+    }
+   
+   /* Clear the NAK flag before re-enabling the channel for new IN request */
+    hhcd->hc[chnum].state = HC_NAK;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+   
+    if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+         (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    {
+      /* re-activate the channel  */
+      USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;        
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+     
+    }
+  }
+}
+
+/**
+  * @brief  Handle Host Channel OUT interrupt requests.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t tmpreg = 0;
+  
+  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+  }  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+    
+    if( hhcd->hc[chnum].do_ping == 1)
+    {
+      hhcd->hc[chnum].state = HC_NYET;     
+      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+      USB_HC_Halt(hhcd->Instance, chnum); 
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+    }
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
+  {
+    hhcd->hc[chnum].state = HC_NYET;
+    hhcd->hc[chnum].ErrCnt= 0;    
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);      
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+    
+  }  
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);  
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
+  {
+      hhcd->hc[chnum].ErrCnt = 0;  
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    USB_HC_Halt(hhcd->Instance, chnum);   
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+    hhcd->hc[chnum].state = HC_XFRC;
+
+  }  
+
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);  
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    USB_HC_Halt(hhcd->Instance, chnum);   
+    hhcd->hc[chnum].state = HC_STALL;    
+  }
+
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
+  {  
+    hhcd->hc[chnum].ErrCnt = 0;  
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);   
+    hhcd->hc[chnum].state = HC_NAK;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+  }
+
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);      
+    hhcd->hc[chnum].state = HC_XACTERR;  
+     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);      
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);    
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+  }
+  
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
+  {
+    __HAL_HCD_MASK_HALT_HC_INT(chnum); 
+    
+    if(hhcd->hc[chnum].state == HC_XFRC)
+    {
+      hhcd->hc[chnum].urb_state  = URB_DONE;
+      if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
+      {
+        hhcd->hc[chnum].toggle_out ^= 1; 
+      }      
+    }
+    else if (hhcd->hc[chnum].state == HC_NAK) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+    }  
+    
+    else if (hhcd->hc[chnum].state == HC_NYET) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+      hhcd->hc[chnum].do_ping = 0;
+    }   
+    
+    else if (hhcd->hc[chnum].state == HC_STALL) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_STALL;
+    } 
+    
+    else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+            (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      if(hhcd->hc[chnum].ErrCnt++ > 3)
+      {      
+        hhcd->hc[chnum].ErrCnt = 0;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      }
+      
+      /* re-activate the channel  */
+      tmpreg = USBx_HC(chnum)->HCCHAR;
+      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+      tmpreg |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(chnum)->HCCHAR = tmpreg;     
+    }
+    
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);  
+  }
+} 
+
+/**
+  * @brief  Handle Rx Queue Level interrupt requests.
+  * @param  hhcd: HCD handle
+  * @retval none
+  */
+static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  
+  uint8_t channelnum =0;
+  uint32_t pktsts;
+  uint32_t pktcnt; 
+  uint32_t temp = 0;
+  uint32_t tmpreg = 0;
+  
+  temp = hhcd->Instance->GRXSTSP ;
+  channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;  
+  pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17;
+  pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4;
+    
+  switch (pktsts)
+  {
+  case GRXSTS_PKTSTS_IN:
+    /* Read the data into the Host buffer. */
+    if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void  *)0))
+    {  
+      
+      USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
+     
+      /*manage multiple Xfer */
+      hhcd->hc[channelnum].xfer_buff += pktcnt;           
+      hhcd->hc[channelnum].xfer_count  += pktcnt;
+        
+      if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
+      {
+        /* re-activate the channel when more packets are expected */
+        tmpreg = USBx_HC(channelnum)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(channelnum)->HCCHAR = tmpreg;
+        hhcd->hc[channelnum].toggle_in ^= 1;
+      }
+    }
+    break;
+
+  case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+    break;
+  case GRXSTS_PKTSTS_IN_XFER_COMP:
+  case GRXSTS_PKTSTS_CH_HALTED:
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Handle Host Port interrupt requests.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  
+  __IO uint32_t hprt0, hprt0_dup;
+  
+  /* Handle Host Port Interrupts */
+  hprt0 = USBx_HPRT0;
+  hprt0_dup = USBx_HPRT0;
+  
+  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+  
+  /* Check whether Port Connect Detected */
+  if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+  {  
+    if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+    {
+      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+      HAL_HCD_Connect_Callback(hhcd);
+    }
+    hprt0_dup  |= USB_OTG_HPRT_PCDET;
+    
+  }
+  
+  /* Check whether Port Enable Changed */
+  if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_PENCHNG;
+    
+    if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+    {    
+      if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
+      {
+        if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
+        {
+          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
+        }
+        else
+        {
+          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+        }
+      }
+      else
+      {
+        if(hhcd->Init.speed == HCD_SPEED_FULL)
+        {
+          USBx_HOST->HFIR = (uint32_t)60000;
+        }
+      }
+      HAL_HCD_Connect_Callback(hhcd);
+      
+      if(hhcd->Init.speed == HCD_SPEED_HIGH)
+      {
+        USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); 
+      }
+    }
+    else
+    {
+      /* Cleanup HPRT */
+      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+      
+      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); 
+    }    
+  }
+  
+  /* Check For an overcurrent */
+  if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_POCCHNG;
+  }
+
+  /* Clear Port Interrupts */
+  USBx_HPRT0 = hprt0_dup;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_HCD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
new file mode 100755
index 0000000..2c34736
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h
@@ -0,0 +1,263 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hcd.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of HCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_HCD_H
+#define __STM32L4xx_HAL_HCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_usb.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HCD
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup HCD_Exported_Types HCD Exported Types
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition 
+  * @{
+  */  
+typedef enum 
+{
+  HAL_HCD_STATE_RESET    = 0x00,
+  HAL_HCD_STATE_READY    = 0x01,
+  HAL_HCD_STATE_ERROR    = 0x02,
+  HAL_HCD_STATE_BUSY     = 0x03,
+  HAL_HCD_STATE_TIMEOUT  = 0x04
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;   
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition   
+  * @{
+  */
+typedef struct
+{
+  HCD_TypeDef               *Instance;  /*!< Register base address    */ 
+  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
+  HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
+  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
+  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
+  void                      *pData;     /*!< Pointer Stack Handler    */    
+  
+} HCD_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+  * @{
+  */
+
+/** @defgroup HCD_Speed HCD Speed
+  * @{
+  */
+#define HCD_SPEED_HIGH               0
+#define HCD_SPEED_LOW                2  
+#define HCD_SPEED_FULL               3
+/**
+  * @}
+  */
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
+  * @{
+  */
+#define HCD_PHY_EMBEDDED             1
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)    
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) 
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) 
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) 
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) 
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) 
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps);
+
+HAL_StatusTypeDef       HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,  
+                                  uint8_t ch_num);
+
+void            HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void            HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                                 uint8_t pipe, 
+                                                 uint8_t direction ,
+                                                 uint8_t ep_type,  
+                                                 uint8_t token, 
+                                                 uint8_t* pbuff, 
+                                                 uint16_t length,
+                                                 uint8_t do_ping);
+
+ /* Non-Blocking mode: Interrupt */
+void             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, 
+                                                            uint8_t chnum, 
+                                                            HCD_URBStateTypeDef urb_state);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_HCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c
new file mode 100755
index 0000000..7b6fb65
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c
@@ -0,0 +1,4853 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx channel
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx channel
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode IO sequential operation ***
+    ==============================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+                            several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+
+      (+) Differents sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
+      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
+      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
+      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
+      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SlaveAddr_SHIFT     7U
+#define SlaveAddr_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (0x00000001U)
+#define I2C_XFER_RX_IT          (0x00000002U)
+#define I2C_XFER_LISTEN_IT      (0x00000004U)
+
+#define I2C_XFER_ERROR_IT       (0x00000011U)
+#define I2C_XFER_CPLT_IT        (0x00000012U)
+#define I2C_XFER_RELOAD_IT      (0x00000012U)
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \
+                                            ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
+                                            ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private functions to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private functions to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if(hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if(hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if(hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function 
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+    
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+    }
+
+    while(hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          return HAL_ERROR;
+        }
+        else
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+      {
+        /* Wait until TCR flag is set */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    while(hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          return HAL_ERROR;
+        }
+        else
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Read data from RXDR */
+      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+      {
+        /* Wait until TCR flag is set */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode. 
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_TIMEOUT;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_TIMEOUT;
+    }
+
+    while(hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          return HAL_ERROR;
+        }
+        else
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Normal use case for Transmitter mode */
+        /* A NACK is generated to confirm the end of transfer */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */ 
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_TIMEOUT;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_TIMEOUT;
+    }
+
+    while(hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+          hi2c->XferCount--;
+        }
+
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+        {
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      /* Read data from RXDR */
+      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_TIMEOUT;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+    
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c); 
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+    
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt 
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+    
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if(hi2c->XferSize > 0U)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+      
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+    
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if(hi2c->XferSize > 0U)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+      
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }   
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    /* Set the I2C DMA transfer complete callback */
+    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hi2c->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U)) 
+    {
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    /* Set the I2C DMA transfer complete callback */
+    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmarx->XferHalfCpltCallback = NULL;
+    hi2c->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          return HAL_ERROR;
+        }
+        else
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+      {
+        /* Wait until TCR flag is set */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+
+    }while(hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */ 
+    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Read data from RXDR */
+      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+      {
+        /* Wait until TCR flag is set */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        if(hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }while(hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */ 
+    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart = 0U;
+  uint32_t xfermode = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+    
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+    
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c); 
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process 
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart = 0U;
+  uint32_t xfermode = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+    
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+    
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart = 0U;
+  uint32_t xfermode = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+    
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set the I2C DMA transfer complete callback */
+    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hi2c->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+    /* Update XferCount value */
+    hi2c->XferCount -= hi2c->XferSize;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR and NACK interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart = 0U;
+  uint32_t xfermode = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set the I2C DMA transfer complete callback */
+    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmarx->XferHalfCpltCallback = NULL;
+    hi2c->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Update XferCount value */
+    hi2c->XferCount -= hi2c->XferSize;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR and NACK interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  __IO uint32_t I2C_Trials = 0U;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+      while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+      {
+      	if(Timeout != HAL_MAX_DELAY)
+      	{
+          if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+          {
+            /* Device is ready */
+            hi2c->State = HAL_I2C_STATE_READY;
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+            return HAL_TIMEOUT;
+          }
+        } 
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */ 
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Device is ready */
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (I2C_Trials++ == Trials)
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */ 
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+    }while(I2C_Trials < Trials);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_TIMEOUT;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode = 0U;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If size > MAX_NBYTE_SIZE, use reload mode */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode = 0U;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+    
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+    
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+    
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if(hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process 
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */   
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if(hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Call the Error Callback in case of Error detected */
+  if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode: Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+* @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+{
+  uint16_t devaddress = 0U;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+  {
+    /* Read data from RXDR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR */
+    hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+  {
+    if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+    {
+      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+      
+      if(hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSequentialCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+  {
+    if(hi2c->XferCount == 0U)
+    {
+      if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSequentialCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+
+  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+{
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+  
+  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if(hi2c->XferCount == 0U)
+    {
+      if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
+        (hi2c->State == HAL_I2C_STATE_LISTEN))
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, ITFlags);
+      }
+      else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSequentialCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+  {
+    if(hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if((hi2c->XferCount == 0U) && \
+       (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSequentialCplt(hi2c);
+   }
+  }
+  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Datas have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if(hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSequentialCplt(hi2c);
+      }
+    }
+  }
+
+  /* Check if STOPF is set */
+  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+{
+  uint16_t devaddress = 0U;
+  uint32_t xfermode = 0U;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+    
+    if(hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+      
+      /* Prepare the new XferSize to transfer */
+      if(hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        xfermode = I2C_AUTOEND_MODE;
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
+{
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+  
+  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
+    {
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+  }
+  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* If Memory address size is 8Bit */
+  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* If Memory address size is 8Bit */
+  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection = 0U;
+  uint16_t slaveaddrcode = 0U;
+  uint16_t ownadd1code = 0U;
+  uint16_t ownadd2code = 0U;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if(hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+  }
+
+  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Rx complete callback to inform upper layer of the end of receive process */
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if((ITFlags & I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Disable Interrupts */
+  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      HAL_I2C_MemTxCpltCallback(hi2c);
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MemRxCpltCallback(hi2c);
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+    }
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Clear ADDR flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+  /* Disable all interrupts */
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
+     ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
+  {
+    hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if(hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Store Last receive data if any */
+  if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+
+    if((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if(hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, ITFlags);
+    }
+  }
+  else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    HAL_I2C_ListenCpltCallback(hi2c);
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Slave Rx Complete callback */
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Slave Tx Complete callback */
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+
+    if((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+  HAL_I2C_ListenCpltCallback(hi2c);
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
+     (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+     (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+    
+    /* If state is an abort treatment on goind, don't change state */
+    /* This change will be do later */
+    if(hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+    }
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+  {
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+    hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Abort DMA TX */
+    if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+    {
+      /* Call Directly XferAbortCallback function in case of error */
+      hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+  {
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+    hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Abort DMA RX */
+    if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+    {
+      /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+      hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+    }
+  }
+  else if(hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_AbortCpltCallback(hi2c);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+     hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if(hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+    /* Enable TC interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+  }
+}
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* No specific action, Master fully manage the generation of STOP condition */
+  /* Mean that this generation can arrive at any time, at the end or during DMA process */
+  /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if(hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if(hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+    /* Enable TC interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+  }
+}
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* No specific action, Master fully manage the generation of STOP condition */
+  /* Mean that this generation can arrive at any time, at the end or during DMA process */
+  /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+}
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma: DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Reset AbortCpltCallback */
+  hi2c->hdmatx->XferAbortCallback = NULL;
+  hi2c->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if come from abort from user */
+  if(hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_AbortCpltCallback(hi2c);
+  }
+  else
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+  while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+      {
+        hi2c->State= HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State= HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State= HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    {
+      /* Clear STOP Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+      /* Clear Configuration Register 2 */
+      I2C_RESET_CR2(hi2c);
+
+      hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      hi2c->State= HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State= HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  {
+    /* Wait until STOP Flag is reset */
+    /* AutoEnd should be initiate after AF */
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+        {
+          hi2c->State= HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+    hi2c->State= HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* Get the CR2 register value */
+  tmpreg = hi2c->Instance->CR2;
+
+  /* clear tmpreg specific bits */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+
+  /* update tmpreg */
+  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
+            (uint32_t)Mode | (uint32_t)Request);
+
+  /* update CR2 register */
+  hi2c->Instance->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+     (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  {
+    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+    
+    if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+  else
+  {
+    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+  
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+  
+  if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h
new file mode 100755
index 0000000..93bbd5e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h
@@ -0,0 +1,710 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_I2C_H
+#define __STM32L4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"  
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition  
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                  This parameter calculated by referring to I2C initialization 
+                                         section in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+}I2C_InitTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     IP initilisation status\n
+  *             0  : Reset (IP not initialized)\n
+  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (IP in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (IP busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */ 
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+}HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+}HAL_I2C_ModeTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+}I2C_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+  
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              I2C_CR2_STOP
+#define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       I2C_CR2_START
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+ 
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__: specifies the I2C Handle. 
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32l4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+ /******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+ /******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+ /******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
+#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+/**
+  * @}
+  */ 
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32l4xx_hal_i2c.c file */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c
new file mode 100755
index 0000000..2602734
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c
@@ -0,0 +1,355 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of I2C Extended peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32L4xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop modes
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters 
+      (+) Configure Wake Up Feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable I2C wakeup from stop mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from stop mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c); 
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h
new file mode 100755
index 0000000..e6d115a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_I2C_EX_H
+#define __STM32L4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#else
+#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */
+#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */
+#endif
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(SYSCFG_CFGR1_I2C2_FMP)
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */
+#endif
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(SYSCFG_CFGR1_I2C4_FMP)
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_CFGR1_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
+                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
+/**
+  * @}
+  */ 
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c
new file mode 100755
index 0000000..99d4049
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c
@@ -0,0 +1,2268 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_irda.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   IRDA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the IrDA (Infrared Data Association) Peripheral
+  *          (IRDA)
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The IRDA HAL driver can be used as follows:
+
+    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+        in setting the associated USART or UART in IRDA mode:
+        (++) Enable the USARTx/UARTx interface clock.
+        (++) USARTx/UARTx pins configuration:
+            (+++) Enable the clock for the USARTx/UARTx GPIOs.
+            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+             and HAL_IRDA_Receive_IT() APIs): 
+            (+++) Configure the USARTx/UARTx interrupt priority.
+            (+++) Enable the NVIC USARTx/UARTx IRQ handle.            
+            (+++) The specific IRDA interrupts (Transmission complete interrupt,
+                  RXNE interrupt and Error Interrupts) will be managed using the macros
+                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+                
+        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+             and HAL_IRDA_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+        the normal or low power mode and the clock prescaler in the hirda handle Init structure.
+
+    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_IRDA_MspInit() API.
+        
+         -@@- The specific IRDA interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+     
+    (#) Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+     *** IRDA HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IRDA HAL driver.
+
+       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+     [..]
+       (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IRDA IRDA
+  * @brief HAL IRDA module driver
+  * @{
+  */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+  * @{
+  */
+#define IRDA_TEACK_REACK_TIMEOUT            1000                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
+#define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+  * @{
+  */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+  * @{
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USARTx
+  in asynchronous IRDA mode.
+  (+) For the asynchronous mode only these parameters can be configured:
+      (++) Baud Rate
+      (++) Word Length
+      (++) Parity: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+      (++) Power mode
+      (++) Prescaler setting
+      (++) Receiver/transmitter modes
+
+  [..]
+  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+  (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
+  8-bit or 9-bit), the possible IRDA frame formats are listed in the 
+  following table.
+  
+    Table 1. IRDA frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the IRDA mode according to the specified
+  *         parameters in the IRDA_InitTypeDef and initialize the associated handle.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if(hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the IRDA handle */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+  if(hirda->gState == HAL_IRDA_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hirda->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_IRDA_MspInit(hirda);
+  }
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
+  /* Disable the Peripheral to update the configuration registers */
+  __HAL_IRDA_DISABLE(hirda);
+
+  /* Set the IRDA Communication parameters */
+  if (IRDA_SetConfig(hirda) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
+  /* set the UART/USART in IRDA mode */
+  hirda->Instance->CR3 |= USART_CR3_IREN;
+
+  /* Enable the Peripheral */
+  __HAL_IRDA_ENABLE(hirda);
+
+  /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
+  return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+  * @brief  DeInitialize the IRDA peripheral.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if(hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the IRDA handle */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_IRDA_MspDeInit(hirda);
+  /* Disable the Peripheral */
+  __HAL_IRDA_DISABLE(hirda);
+
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+  hirda->gState    = HAL_IRDA_STATE_RESET;
+  hirda->RxState   = HAL_IRDA_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the IRDA MSP.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the IRDA MSP.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+  *  @brief   IRDA Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+  [..]
+    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+    While receiving data, transmission should be avoided as the data to be transmitted
+    could be corrupted.
+
+    (#) There are two mode of transfer:
+        (++) Blocking mode: the communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) Non-Blocking mode: the communication is performed using Interrupts
+             or DMA, these API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+             will be executed respectively at the end of the Transmit or Receive process
+             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+    (#) Blocking mode APIs are :
+        (++) HAL_IRDA_Transmit()
+        (++) HAL_IRDA_Receive()
+
+    (#) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_IRDA_Transmit_IT()
+        (++) HAL_IRDA_Receive_IT()
+        (++) HAL_IRDA_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (++) HAL_IRDA_Transmit_DMA()
+        (++) HAL_IRDA_Receive_DMA()
+        (++) HAL_IRDA_DMAPause()
+        (++) HAL_IRDA_DMAResume()
+        (++) HAL_IRDA_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+        (++) HAL_IRDA_TxHalfCpltCallback()
+        (++) HAL_IRDA_TxCpltCallback()
+        (++) HAL_IRDA_RxHalfCpltCallback()
+        (++) HAL_IRDA_RxCpltCallback()
+        (++) HAL_IRDA_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_IRDA_Abort()
+        (+) HAL_IRDA_AbortTransmit()
+        (+) HAL_IRDA_AbortReceive()
+        (+) HAL_IRDA_Abort_IT()
+        (+) HAL_IRDA_AbortTransmit_IT()
+        (+) HAL_IRDA_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_IRDA_AbortCpltCallback()
+        (+) HAL_IRDA_AbortTransmitCpltCallback()
+        (+) HAL_IRDA_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send an amount of data in blocking mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be sent.
+  * @param  Timeout Specify timeout value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tickstart = 0;
+
+  /* Check that a Tx process is not already ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+    while(hirda->TxXferCount > 0)
+    {
+      hirda->TxXferCount--;
+
+      if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pData;
+        hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+        pData += 2;
+      }
+      else
+      {
+        hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+      }
+    }
+
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be received.
+  * @param  Timeout Specify timeout value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint16_t uhMask;
+  uint32_t tickstart = 0;
+
+  /* Check that a Rx process is not already ongoing */
+  if(hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+
+    /* Computation of the mask to apply to RDR register
+       of the UART associated to the IRDA */
+    IRDA_MASK_COMPUTATION(hirda);
+    uhMask = hirda->Mask;
+
+    /* Check data remaining to be received */
+    while(hirda->RxXferCount > 0)
+    {
+      hirda->RxXferCount--;
+
+      if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pData ;
+        *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+        pData +=2;
+      }
+      else
+      {
+        *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+      }
+    }
+
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ *                the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the IRDA Transmit Data Register Empty Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+
+    /* Computation of the mask to apply to the RDR register
+       of the UART associated to the IRDA */
+    IRDA_MASK_COMPUTATION(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Set the IRDA DMA transfer complete callback */
+    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+    /* Set the IRDA DMA half transfer complete callback */
+    hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+    /* Set the DMA error callback */
+    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+    /* Set the DMA abort callback */
+    hirda->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the IRDA transmit DMA channel */
+    HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be received.
+  * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
+  *         the parity bit (MSB position).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Set the IRDA DMA transfer complete callback */
+    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+    /* Set the IRDA DMA half transfer complete callback */
+    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+    /* Set the DMA error callback */
+    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+    /* Set the DMA abort callback */
+    hirda->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Pause the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+  /* Process Locked */
+  __HAL_LOCK(hirda);
+
+  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+  {
+    /* Disable the IRDA DMA Tx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the IRDA DMA Rx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+  /* Process Locked */
+  __HAL_LOCK(hirda);
+
+  if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    /* Enable the IRDA DMA Tx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+  }
+  if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the IRDA DMA Rx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+     HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: 
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete  
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of 
+     the stream and the corresponding call back is executed. */
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel */
+    if(hirda->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+
+    IRDA_EndTxTransfer(hirda);
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel */
+    if(hirda->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+
+    IRDA_EndRxTransfer(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+  }
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  hirda->TxXferCount = 0; 
+  hirda->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  hirda->TxXferCount = 0; 
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  hirda->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(hirda->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+    {
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(hirda->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+    {
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the IRDA DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* IRDA Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        hirda->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* IRDA Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        hirda->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hirda->TxXferCount = 0; 
+    hirda->RxXferCount = 0;
+
+    /* Reset errorCode */
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+    /* Restore hirda->gState and hirda->RxState to Ready */
+    hirda->gState  = HAL_IRDA_STATE_READY;
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_IRDA_AbortCpltCallback(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+        hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hirda->TxXferCount = 0; 
+
+      /* Restore hirda->gState to Ready */
+      hirda->gState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_IRDA_AbortTransmitCpltCallback(hirda);
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    hirda->TxXferCount = 0; 
+
+    /* Restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_IRDA_AbortTransmitCpltCallback(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+        hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hirda->RxXferCount = 0; 
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+      /* Restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_IRDA_AbortReceiveCpltCallback(hirda);
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    hirda->RxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+    /* Restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_IRDA_AbortReceiveCpltCallback(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle IRDA interrupt request.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
+  uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+  if (errorflags == RESET)
+  {
+    /* IRDA in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      IRDA_Receive_IT(hirda);
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  cr3its = READ_REG(hirda->Instance->CR3);
+  if(   (errorflags != RESET) 
+     && (    ((cr3its & USART_CR3_EIE) != RESET)
+          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+  {
+    /* IRDA parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+    }
+
+    /* IRDA frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+    }
+
+    /* IRDA noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+    }
+
+    /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+    }
+
+    /* Call IRDA Error Call back function if need be --------------------------*/
+    if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+    {
+      /* IRDA in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        IRDA_Receive_IT(hirda);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
+          (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the IRDA state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        IRDA_EndRxTransfer(hirda);
+
+        /* Disable the IRDA DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the IRDA DMA Rx channel */
+          if(hirda->hdmarx != NULL)
+          {
+            /* Set the IRDA DMA Abort callback : 
+               will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+            hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+            {
+              /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+              hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_IRDA_ErrorCallback(hirda);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_IRDA_ErrorCallback(hirda);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_IRDA_ErrorCallback(hirda);
+        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* IRDA in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    IRDA_Transmit_IT(hirda);
+    return;
+  }
+
+  /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    IRDA_EndTransmit_IT(hirda);
+    return;
+  }
+
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified USART module.
+  * @retval None
+  */
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer complete callback.
+  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA error callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Receive Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   IRDA State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to return the State of IrDA
+    communication process and also return Peripheral Errors occurred during communication process
+     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+         of the IRDA peripheral handle.
+     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+         communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the IRDA handle state.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL state
+  */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+  /* Return IRDA handle state */
+  uint32_t temp1= 0x00, temp2 = 0x00;
+  temp1 = hirda->gState;
+  temp2 = hirda->RxState;
+
+  return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the IRDA handle error code.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval IRDA Error Code
+  */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+  return hirda->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Configure the IRDA peripheral.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t tmpreg                     = 0x00000000;
+  IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
+  HAL_StatusTypeDef ret               = HAL_OK;
+
+  /* Check the communication parameters */
+  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+  assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+  assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+  assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+  assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+  assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Configure the IRDA Word Length, Parity and transfer Mode:
+     Set the M bits according to hirda->Init.WordLength value
+     Set PCE and PS bits according to hirda->Init.Parity value
+     Set TE and RE bits according to hirda->Init.Mode value */
+  tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+  MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+  /*-------------------------- USART GTPR Configuration ----------------------*/
+  MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  IRDA_GETCLOCKSOURCE(hirda, clocksource);
+  switch (clocksource)
+  {
+    case IRDA_CLOCKSOURCE_PCLK1:
+      hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_PCLK2:
+      hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_HSI:
+      hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_SYSCLK:
+      hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_LSE:
+      hirda->Instance->BRR = (uint16_t)((LSE_VALUE  + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_UNDEFINED:
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Check the IRDA Idle State.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the IRDA ErrorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the IRDA state*/
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle IRDA Communication Timeout.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  Flag Specifies the IRDA flag to check.
+  * @param  Status Flag status (SET or RESET)
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+        hirda->gState  = HAL_IRDA_STATE_READY;
+        hirda->RxState = HAL_IRDA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hirda);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+  * @brief  DMA IRDA transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    hirda->TxXferCount = 0;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the IRDA Transmit Complete Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+    HAL_IRDA_TxCpltCallback(hirda);
+  }
+
+}
+
+/**
+  * @brief  DMA IRDA transmit process half complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA receive process complete callback.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    hirda->RxXferCount = 0;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+  }
+
+  HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+  * @brief DMA IRDA receive process half complete callback.
+  * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA communication error callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  if (  (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+      &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
+  {
+    hirda->TxXferCount = 0;
+    IRDA_EndTxTransfer(hirda);
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  if (  (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+      &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
+  {
+    hirda->RxXferCount = 0;
+    IRDA_EndRxTransfer(hirda);
+  }
+
+  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+  HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+  hirda->RxXferCount = 0;
+  hirda->TxXferCount = 0;
+
+  HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+  
+  hirda->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hirda->hdmarx != NULL)
+  {
+    if(hirda->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0;
+  hirda->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+  
+  hirda->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hirda->hdmatx != NULL)
+  {
+    if(hirda->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0;
+  hirda->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  hirda->TxXferCount = 0;
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortTransmitCpltCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hirda->RxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortReceiveCpltCallback(hirda);
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint16_t* tmp;
+
+  /* Check that a Tx process is ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    if(hirda->TxXferCount == 0)
+    {
+      /* Disable the IRDA Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the IRDA Transmit Complete Interrupt */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+      return HAL_OK;
+    }
+    else
+    {
+      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+      {
+        tmp = (uint16_t*) hirda->pTxBuffPtr;
+        hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+        hirda->pTxBuffPtr += 2;
+      }
+      else
+      {
+        hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
+      }
+      hirda->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable the IRDA Transmit Complete Interrupt */
+  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  HAL_IRDA_TxCpltCallback(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_IRDA_Receive_IT()
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint16_t* tmp;
+  uint16_t  uhMask = hirda->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
+    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+    {
+      tmp = (uint16_t*) hirda->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      hirda->pRxBuffPtr +=2;
+    }
+    else
+    {
+      *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+    }
+
+    if(--hirda->RxXferCount == 0)
+    {
+      /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+      HAL_IRDA_RxCpltCallback(hirda);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h
new file mode 100755
index 0000000..4fced53
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h
@@ -0,0 +1,849 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_irda.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IRDA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_IRDA_H
+#define __STM32L4xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+  * @{
+  */
+
+/**
+  * @brief IRDA Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref IRDA_Word_Length */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref IRDA_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+                                           to achieve low-power frequency.
+                                           @note Prescaler value 0 is forbidden */
+
+  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
+                                           This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+  * @brief HAL IRDA State structures definition
+  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains IRDA state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_IRDA_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing 
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_ERROR             = 0xE0U    /*!< Error
+                                                   Value is allowed for gState only */
+}HAL_IRDA_StateTypeDef;
+
+/**
+  * @brief  HAL IRDA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_IRDA_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_IRDA_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_IRDA_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_IRDA_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_IRDA_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_IRDA_ERROR_DMA       = 0x10,     /*!< DMA transfer error  */
+  HAL_IRDA_ERROR_BUSY      = 0x20     /*!< Busy Error          */
+}HAL_IRDA_ErrorTypeDef;
+
+/**
+  * @brief IRDA clock sources definition
+  */
+typedef enum
+{
+  IRDA_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
+  IRDA_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
+  IRDA_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
+  IRDA_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
+  IRDA_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
+  IRDA_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
+}IRDA_ClockSourceTypeDef;
+
+/**
+  * @brief  IRDA handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef            *Instance;        /*!< IRDA registers base address        */
+
+  IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
+
+  uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;      /* !<IRDA Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
+
+  uint16_t                 Mask;             /*!< IRDA RX RDR register mask          */
+
+  DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef          Lock;             /*!< Locking object                     */
+
+  __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management 
+                                                  and also related to Tx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  uint32_t                 ErrorCode;        /*!< IRDA Error code                    */
+
+}IRDA_HandleTypeDef;
+
+/**
+  * @brief  IRDA Configuration enumeration values definition
+  */
+typedef enum
+{
+  IRDA_BAUDRATE        = 0x00,     /*!< IRDA Baud rate          */
+  IRDA_PARITY          = 0x01,     /*!< IRDA frame parity       */
+  IRDA_WORDLENGTH      = 0x02,     /*!< IRDA frame length       */
+  IRDA_MODE            = 0x03,     /*!< IRDA communication mode */
+  IRDA_PRESCALER       = 0x04,     /*!< IRDA prescaling         */
+  IRDA_POWERMODE       = 0x05      /*!< IRDA power mode         */
+}IRDA_ControlTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
+  * @{
+  */
+
+/** @defgroup IRDA_Word_Length IRDA Word Length
+  * @{
+  */
+#define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long frame */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Parity IRDA Parity
+  * @{
+  */
+#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)                      /*!< No parity   */
+#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
+#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+  * @{
+  */
+#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
+#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
+#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+  * @{
+  */
+#define IRDA_POWERMODE_NORMAL               ((uint32_t)0x00000000)       /*!< IRDA normal power mode */ 
+#define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)   /*!< IRDA low power mode    */ 
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_State IRDA State
+  * @{
+  */
+#define IRDA_STATE_DISABLE                  ((uint32_t)0x00000000)     /*!< IRDA disabled  */ 
+#define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)   /*!< IRDA enabled   */ 
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Mode  IRDA Mode
+  * @{
+  */
+#define IRDA_MODE_DISABLE                   ((uint32_t)0x00000000)      /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE                    ((uint32_t)USART_CR3_IREN)  /*!< Associated UART enabled in IRDA mode  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)       /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+  * @{
+  */
+#define IRDA_DMA_TX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA TX disabled */ 
+#define IRDA_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)   /*!< IRDA DMA TX enabled  */ 
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Rx  IRDA DMA Rx
+  * @{
+  */
+#define IRDA_DMA_RX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)   /*!< IRDA DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+  * @{
+  */
+#define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
+#define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
+#define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Flags IRDA Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define IRDA_FLAG_REACK                     ((uint32_t)0x00400000)    /*!< IRDA Receive enable acknowledge flag  */ 
+#define IRDA_FLAG_TEACK                     ((uint32_t)0x00200000)    /*!< IRDA Transmit enable acknowledge flag */ 
+#define IRDA_FLAG_BUSY                      ((uint32_t)0x00010000)    /*!< IRDA Busy flag                        */  
+#define IRDA_FLAG_ABRF                      ((uint32_t)0x00008000)    /*!< IRDA Auto baud rate flag              */
+#define IRDA_FLAG_ABRE                      ((uint32_t)0x00004000)    /*!< IRDA Auto baud rate error             */  
+#define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)    /*!< IRDA Transmit data register empty     */
+#define IRDA_FLAG_TC                        ((uint32_t)0x00000040)    /*!< IRDA Transmission complete            */  
+#define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)    /*!< IRDA Read data register not empty     */
+#define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)    /*!< IRDA Overrun error                    */  
+#define IRDA_FLAG_NE                        ((uint32_t)0x00000004)    /*!< IRDA Noise error                      */
+#define IRDA_FLAG_FE                        ((uint32_t)0x00000002)    /*!< IRDA Framing error                    */
+#define IRDA_FLAG_PE                        ((uint32_t)0x00000001)    /*!< IRDA Parity error                     */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define IRDA_IT_PE                          ((uint16_t)0x0028)     /*!< IRDA Parity error interruption                 */
+#define IRDA_IT_TXE                         ((uint16_t)0x0727)     /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC                          ((uint16_t)0x0626)     /*!< IRDA Transmission complete interruption        */
+#define IRDA_IT_RXNE                        ((uint16_t)0x0525)     /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE                        ((uint16_t)0x0424)     /*!< IRDA Idle interruption                         */
+#define IRDA_IT_ERR                         ((uint16_t)0x0060)       /*!< IRDA Error interruption        */
+#define IRDA_IT_ORE                         ((uint16_t)0x0300)      /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE                          ((uint16_t)0x0200)      /*!< IRDA Noise error interruption   */
+#define IRDA_IT_FE                          ((uint16_t)0x0100)      /*!< IRDA Frame error interruption   */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_IT_CLEAR_Flags   IRDA Interruption Clear Flags
+  * @{
+  */
+#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
+#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
+#define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
+#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
+#define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
+#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interruption_Mask    IRDA interruptions flags mask
+  * @{
+  */
+#define IRDA_IT_MASK  ((uint16_t)0x001F)                             /*!< IRDA Interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+ * @}
+ */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset IRDA handle state.
+  * @param  __HANDLE__: IRDA handle.
+  * @retval None
+  */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
+                                                     } while(0)
+
+/** @brief  Flush the IRDA DR register.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
+    do{                                                                    \
+         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+      } while(0)
+
+/** @brief  Clear the specified IRDA pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF
+  *            @arg @ref IRDA_CLEAR_FEF
+  *            @arg @ref IRDA_CLEAR_NEF
+  *            @arg @ref IRDA_CLEAR_OREF
+  *            @arg @ref IRDA_CLEAR_TCF
+  *            @arg @ref IRDA_CLEAR_IDLEF
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the IRDA PE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief  Clear the IRDA FE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief  Clear the IRDA NE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief  Clear the IRDA ORE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief  Clear the IRDA IDLE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified IRDA flag is set or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_BUSY  Busy flag
+  *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
+  *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
+  *            @arg @ref IRDA_FLAG_NE    Noise Error flag
+  *            @arg @ref IRDA_FLAG_FE    Framing Error flag
+  *            @arg @ref IRDA_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Enable the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief  Disable the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+
+/** @brief  Check whether the specified IRDA interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
+  *            @arg @ref IRDA_IT_NE Noise Error interrupt
+  *            @arg @ref IRDA_IT_FE Framing Error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
+
+/** @brief  Check whether the specified IRDA interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
+                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+
+
+/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief  Set a specific IRDA request flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __REQ__: specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the IRDA one bit sample method.
+  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @retval None
+  */     
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the IRDA one bit sample method.
+  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @retval None
+  */      
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros   IRDA Private Macros
+  * @{
+  */
+
+/** @brief  Compute the mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003F ;                                 \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
+  * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
+
+/** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
+  * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
+
+/**
+  * @brief Ensure that IRDA frame length is valid.
+  * @param __LENGTH__: IRDA frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */ 
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that IRDA frame parity is valid.
+  * @param __PARITY__: IRDA frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
+                                    ((__PARITY__) == IRDA_PARITY_ODD))
+
+/**
+  * @brief Ensure that IRDA communication mode is valid.
+  * @param __MODE__: IRDA communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+  * @brief Ensure that IRDA power mode is valid.
+  * @param __MODE__: IRDA power mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/**
+  * @brief Ensure that IRDA state is valid.
+  * @param __STATE__: IRDA state mode. 
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */ 
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+                                  ((__STATE__) == IRDA_STATE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA associated UART/USART mode is valid.
+  * @param __MODE__: IRDA associated UART/USART mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
+                                 ((__MODE__) == IRDA_MODE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA sampling rate is valid.
+  * @param __ONEBIT__: IRDA sampling rate. 
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */ 
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA DMA TX mode is valid.
+  * @param __DMATX__: IRDA DMA TX mode. 
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */ 
+#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that IRDA DMA RX mode is valid.
+  * @param __DMARX__: IRDA DMA RX mode. 
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */ 
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that IRDA request is valid.
+  * @param __PARAM__: IRDA request. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */ 
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
+#include "stm32l4xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+  * @{
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h
new file mode 100755
index 0000000..5a19356
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h
@@ -0,0 +1,405 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_irda_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IRDA HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_IRDA_EX_H
+#define __STM32L4xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the IRDA clock source.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)  
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART5_SOURCE())                   \
+       {                                                      \
+        case RCC_UART5CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L432xx) || defined (STM32L442xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)  
+#endif
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_IRDA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c
new file mode 100755
index 0000000..9917a4f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c
@@ -0,0 +1,282 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   IWDG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Independent Watchdog (IWDG) peripheral:
+  *           + Initialization and Start functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### IWDG Generic features #####
+  ==============================================================================
+  [..]
+    (+) The IWDG can be started by either software or hardware (configurable
+        through option byte).
+
+    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+        if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both can not be 
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is 
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, 
+        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+        prevented.
+
+    (+) The IWDG is implemented in the VDD voltage domain that is still functional
+        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
+
+    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending 
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+
+    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+         The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
+         devices provide the capability to measure the LSI frequency (LSI clock
+         connected internally to TIM16 CH1 input capture). The measured value
+         can be used to have an IWDG timeout with an acceptable accuracy.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI 
+           clock is forced ON and IWDG counter starts downcounting.
+      (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & 
+           IWDG_WINR.
+      (++) Configure the IWDG prescaler and counter reload value. This reload 
+           value will be loaded in the IWDG counter each time the watchdog is 
+           reloaded, then the IWDG will start counting down from this value.
+      (++) Wait for status flags to be reset
+      (++) Depending on window parameter:
+        (+++) If Window Init parameter is same as Window register value, 
+             nothing more is done but reload counter value in order to exit 
+             function withy exact time base.
+        (+++) Else modify Window register. This will automatically reload
+             watchdog counter.
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
+     *** IWDG HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IWDG HAL driver:
+      (+) __HAL_IWDG_START: Enable the IWDG peripheral
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+  * @brief IWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+  * @{
+  */
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
+   higher prescaler (256), and according to HSI variation, we need to wait at 
+   least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT            48u
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ *  @brief    Initialization and Start functions.
+ *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Start functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the 
+          IWDG_InitTypeDef of associated handle.
+      (+) Manage Window option.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog 
+          is reloaded in order to exit function with correct time base.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the IWDG according to the specified parameters in the 
+  *         IWDG_InitTypeDef and start watchdog. Before exiting function, 
+  *         watchdog is refreshed in order to have correct time base.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+  uint32_t tickstart;
+
+  /* Check the IWDG handle allocation */
+  if(hiwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+  /* Enable IWDG. LSI is turned on automaticaly */
+  __HAL_IWDG_START(hiwdg);
+
+  /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
+  0x5555 in KR */
+  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+  /* Check pending flag, if previous update not done, return timeout */
+  tickstart = HAL_GetTick();
+
+   /* Wait for register to be updated */
+  while(hiwdg->Instance->SR != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* If window parameter is different than current value, modify window 
+  register */
+  if(hiwdg->Instance->WINR != hiwdg->Init.Window)
+  {
+    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+    even if window feature is disabled, Watchdog will be reloaded by writing 
+    windows register */
+    hiwdg->Instance->WINR = hiwdg->Init.Window;
+  }
+  else
+  {
+    /* Reload IWDG counter with value defined in the reload register */
+    __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ *  @brief   IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Refresh the IWDG.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Refresh the IWDG.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h
new file mode 100755
index 0000000..bead6ad
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h
@@ -0,0 +1,257 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_IWDG_H
+#define __STM32L4xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IWDG IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  IWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
+                            This parameter can be a value of @ref IWDG_Prescaler */
+
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/** 
+  * @brief  IWDG Handle Structure definition  
+  */
+typedef struct
+{
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
+
+}IWDG_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+  * @{
+  */
+#define IWDG_PRESCALER_4                0x00000000u                   /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)   /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)   /*!< IWDG prescaler set to 256 */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+  * @{
+  */
+#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the IWDG peripheral.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+  * @brief  Reload IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+  * @{
+  */
+/* Initialization/Start functions  ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+/**
+  * @brief  IWDG Key Register BitMask
+  */
+#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+  * @brief  Check IWDG prescaler value.
+  * @param  __PRESCALER__  IWDG prescaler value
+  * @retval None
+  */
+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+  * @brief  Check IWDG reload value.
+  * @param  __RELOAD__  IWDG reload value
+  * @retval None
+  */
+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+  * @brief  Check IWDG window value.
+  * @param  __WINDOW__  IWDG window value
+  * @retval None
+  */
+#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c
new file mode 100755
index 0000000..0bd57fd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c
@@ -0,0 +1,626 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_lcd.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   LCD Controller HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the LCD Controller (LCD) peripheral:
+  *           + Initialization/de-initialization methods
+  *           + I/O operation methods
+  *           + Peripheral State methods
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+      [..] The LCD HAL driver can be used as follows:
+
+      (#) Declare a LCD_HandleTypeDef handle structure.
+      
+      -@- The frequency generator allows you to achieve various LCD frame rates
+          starting from an LCD input clock frequency (LCDCLK) which can vary
+          from 32 kHz up to 1 MHz.      
+      
+      (#) Initialize the LCD low level resources by implementing the HAL_LCD_MspInit() API:
+                  
+          (++) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
+               (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and
+                  selected clock source (HSE, LSI or LSE)
+
+          (++) LCD pins configuration:
+              (+++) Enable the clock for the LCD GPIOs.
+              (+++) Configure these LCD pins as alternate function no-pull.
+          (++) Enable the LCD interface clock.
+
+      
+      (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
+          Voltage Source, Dead Time, Pulse On Duration, Contrast, High drive and Multiplexer
+          Segment in the Init structure of the LCD handle.
+
+      (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
+
+      -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
+          by calling the customized HAL_LCD_MspInit() API.
+      -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared
+
+      (#) Optionally you can update the LCD configuration using these macros:
+              (++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
+              (++) Voltage output buffer using __HAL_LCD_VOLTAGE_BUFFER_ENABLE() and __HAL_LCD_VOLTAGE_BUFFER_DISABLE() macros
+              (++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
+              (++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
+              (++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
+              (++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro
+
+      (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
+          more time to update the different LCD RAM registers before calling
+          HAL_LCD_UpdateDisplayRequest() API.
+
+      (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
+
+      (#) When LCD RAM memory is updated enable the update display request using
+          the HAL_LCD_UpdateDisplayRequest() API.
+
+      [..] LCD and low power modes:
+           (#) The LCD remain active during Sleep, Low Power run, Low Power Sleep and
+               STOP modes.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+
+/** @defgroup LCD LCD
+  * @brief LCD HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup LCD_Private_Defines LCD Private Defines
+  * @{
+  */
+
+#define LCD_TIMEOUT_VALUE             1000
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LCD_Exported_Functions LCD Exported Functions
+  * @{
+  */
+
+/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the LCD peripheral according to the specified parameters
+  *         in the LCD_InitStruct and initialize the associated handle.
+  * @note   This function can be used only when the LCD is disabled.
+  * @param  hlcd: LCD handle
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00;
+  uint32_t counter = 0;
+
+  /* Check the LCD handle allocation */
+  if(hlcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
+  assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
+  assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
+  assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
+  assert_param(IS_LCD_BIAS(hlcd->Init.Bias));
+  assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
+  assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
+  assert_param(IS_LCD_HIGH_DRIVE(hlcd->Init.HighDrive));
+  assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
+  assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast));
+  assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency));
+  assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode));
+  assert_param(IS_LCD_MUX_SEGMENT(hlcd->Init.MuxSegment));
+
+  if(hlcd->State == HAL_LCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hlcd->Lock = HAL_UNLOCKED;
+
+    /* Initialize the low level hardware (MSP) */
+    HAL_LCD_MspInit(hlcd);
+  }
+
+  hlcd->State = HAL_LCD_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_LCD_DISABLE(hlcd);
+
+  /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
+     in the LCD_SR register */
+  for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
+  {
+    hlcd->Instance->RAM[counter] = 0;
+  }
+  /* Enable the display request */
+  hlcd->Instance->SR |= LCD_SR_UDR;
+
+  /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency:
+     Set PS[3:0] bits according to hlcd->Init.Prescaler value
+     Set DIV[3:0] bits according to hlcd->Init.Divider value
+     Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
+     Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
+     Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
+     Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value
+     Set CC[2:0] bits according to hlcd->Init.Contrast value
+     Set HD bit according to hlcd->Init.HighDrive value */
+   MODIFY_REG(hlcd->Instance->FCR, \
+      (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \
+       LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC | LCD_FCR_HD), \
+      (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
+       hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive));
+
+  /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register
+     This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
+     domain. It is cleared by hardware when writing to the LCD_FCR register.*/
+  LCD_WaitForSynchro(hlcd);
+
+  /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast:
+     Set DUTY[2:0] bits according to hlcd->Init.Duty value
+     Set BIAS[1:0] bits according to hlcd->Init.Bias value
+     Set VSEL bit according to hlcd->Init.VoltageSource value
+     Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
+  MODIFY_REG(hlcd->Instance->CR, \
+    (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
+    (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
+
+  /* Enable the peripheral */
+  __HAL_LCD_ENABLE(hlcd);
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait Until the LCD is enabled */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+    {
+      hlcd->ErrorCode = HAL_LCD_ERROR_ENS;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /*!< Wait Until the LCD Booster is ready */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+    {
+      hlcd->ErrorCode = HAL_LCD_ERROR_RDY;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the LCD state */
+  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
+  hlcd->State= HAL_LCD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the LCD peripheral.
+  * @param  hlcd: LCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
+{
+  /* Check the LCD handle allocation */
+  if(hlcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
+
+  hlcd->State = HAL_LCD_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_LCD_MspDeInit(hlcd);
+
+  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
+  hlcd->State = HAL_LCD_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hlcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the LCD MSP.
+  * @param  hlcd: LCD handle
+  * @retval None
+  */
+__weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlcd);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_LCD_MspDeInit it to be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Initialize the LCD MSP.
+  * @param  hlcd: LCD handle
+  * @retval None
+  */
+__weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlcd);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_LCD_MspInit is to be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Exported_Functions_Group2 IO operation methods
+  *  @brief LCD RAM functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..] Using its double buffer memory the LCD controller ensures the coherency of the
+ displayed information without having to use interrupts to control LCD_RAM
+ modification.
+ The application software can access the first buffer level (LCD_RAM) through
+ the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
+ it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
+ This UDR flag (update display request) requests the updated information to be
+ moved into the second buffer level (LCD_DISPLAY).
+ This operation is done synchronously with the frame (at the beginning of the
+ next frame), until the update is completed, the LCD_RAM is write protected and
+ the UDR flag stays high.
+ Once the update is completed another flag (UDD - Update Display Done) is set and
+ generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
+ The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one
+ even frame.
+ The update will not occur (UDR = 1 and UDD = 0) until the display is
+ enabled (LCDEN = 1).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Write a word in the specific LCD RAM.
+  * @param  hlcd: LCD handle
+  * @param  RAMRegisterIndex: specifies the LCD RAM Register.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_RAM_REGISTER0: LCD RAM Register 0
+  *     @arg LCD_RAM_REGISTER1: LCD RAM Register 1
+  *     @arg LCD_RAM_REGISTER2: LCD RAM Register 2
+  *     @arg LCD_RAM_REGISTER3: LCD RAM Register 3
+  *     @arg LCD_RAM_REGISTER4: LCD RAM Register 4
+  *     @arg LCD_RAM_REGISTER5: LCD RAM Register 5
+  *     @arg LCD_RAM_REGISTER6: LCD RAM Register 6
+  *     @arg LCD_RAM_REGISTER7: LCD RAM Register 7
+  *     @arg LCD_RAM_REGISTER8: LCD RAM Register 8
+  *     @arg LCD_RAM_REGISTER9: LCD RAM Register 9
+  *     @arg LCD_RAM_REGISTER10: LCD RAM Register 10
+  *     @arg LCD_RAM_REGISTER11: LCD RAM Register 11
+  *     @arg LCD_RAM_REGISTER12: LCD RAM Register 12
+  *     @arg LCD_RAM_REGISTER13: LCD RAM Register 13
+  *     @arg LCD_RAM_REGISTER14: LCD RAM Register 14
+  *     @arg LCD_RAM_REGISTER15: LCD RAM Register 15
+  * @param  RAMRegisterMask: specifies the LCD RAM Register Data Mask.
+  * @param  Data: specifies LCD Data Value to be written.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
+{
+  uint32_t tickstart = 0x00;
+
+  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
+  {
+    /* Check the parameters */
+    assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
+
+    if(hlcd->State == HAL_LCD_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(hlcd);
+      hlcd->State = HAL_LCD_STATE_BUSY;
+
+      /* Get timeout */
+      tickstart = HAL_GetTick();
+
+      /*!< Wait Until the LCD is ready */
+      while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+        {
+          hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hlcd);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Copy the new Data bytes to LCD RAM register */
+    MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief Clear the LCD RAM registers.
+  * @param hlcd: LCD handle
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00;
+  uint32_t counter = 0;
+
+  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hlcd);
+
+    hlcd->State = HAL_LCD_STATE_BUSY;
+
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /*!< Wait Until the LCD is ready */
+    while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+      {
+        hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hlcd);
+
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Clear the LCD_RAM registers */
+    for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
+    {
+      hlcd->Instance->RAM[counter] = 0;
+    }
+
+    /* Update the LCD display */
+    HAL_LCD_UpdateDisplayRequest(hlcd);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Update Display Request.
+  * @param  hlcd: LCD handle
+  * @note   Each time software modifies the LCD_RAM it must set the UDR bit to
+  *         transfer the updated data to the second level buffer.
+  *         The UDR bit stays set until the end of the update and during this
+  *         time the LCD_RAM is write protected.
+  * @note   When the display is disabled, the update is performed for all
+  *         LCD_DISPLAY locations.
+  *         When the display is enabled, the update is performed only for locations
+  *         for which commons are active (depending on DUTY). For example if
+  *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00;
+
+  /* Clear the Update Display Done flag before starting the update display request */
+  __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
+
+  /* Enable the display request */
+  hlcd->Instance->SR |= LCD_SR_UDR;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /*!< Wait Until the LCD display is done */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+    {
+      hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hlcd);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  hlcd->State = HAL_LCD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hlcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
+  *  @brief   LCD State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+     This subsection provides a set of functions allowing to control the LCD:
+      (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State.
+      (+) HAL_LCD_GetError() API to return the LCD error code.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the LCD handle state.
+  * @param hlcd: LCD handle
+  * @retval HAL state
+  */
+HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
+{
+  /* Return LCD handle state */
+  return hlcd->State;
+}
+
+/**
+  * @brief Return the LCD error code.
+  * @param hlcd: LCD handle
+  * @retval LCD Error Code
+  */
+uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
+{
+  return hlcd->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Private_Functions LCD Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait until the LCD FCR register is synchronized in the LCDCLK domain.
+  *   This function must be called after any write operation to LCD_FCR register.
+  * @retval None
+  */
+HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /* Loop until FCRSF flag is set */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+    {
+      hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h
new file mode 100755
index 0000000..dc7f4bf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h
@@ -0,0 +1,789 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_lcd.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of LCD Controller HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_LCD_H
+#define __STM32L4xx_HAL_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup LCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LCD_Exported_Types LCD Exported Types
+  * @{
+  */
+
+/**
+  * @brief LCD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t Prescaler;       /*!< Configures the LCD Prescaler.
+                                 This parameter can be one value of @ref LCD_Prescaler */
+  uint32_t Divider;         /*!< Configures the LCD Divider.
+                                 This parameter can be one value of @ref LCD_Divider */
+  uint32_t Duty;            /*!< Configures the LCD Duty.
+                                 This parameter can be one value of @ref LCD_Duty */
+  uint32_t Bias;            /*!< Configures the LCD Bias.
+                                 This parameter can be one value of @ref LCD_Bias */
+  uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
+                                 This parameter can be one value of @ref LCD_Voltage_Source */
+  uint32_t Contrast;        /*!< Configures the LCD Contrast.
+                                 This parameter can be one value of @ref LCD_Contrast */
+  uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
+                                 This parameter can be one value of @ref LCD_DeadTime */
+  uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
+                                 This parameter can be one value of @ref LCD_PulseOnDuration */
+  uint32_t HighDrive;       /*!< Enable or disable the low resistance divider.
+                                 This parameter can be one value of @ref LCD_HighDrive */
+  uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
+                                 This parameter can be one value of @ref LCD_BlinkMode */
+  uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
+                                 This parameter can be one value of @ref LCD_BlinkFrequency */
+  uint32_t MuxSegment;      /*!< Enable or disable mux segment.
+                                 This parameter can be one value of @ref LCD_MuxSegment */
+} LCD_InitTypeDef;
+
+/**
+  * @brief HAL LCD State structures definition
+  */
+typedef enum
+{
+  HAL_LCD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
+  HAL_LCD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_LCD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
+  HAL_LCD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
+  HAL_LCD_STATE_ERROR             = 0x04     /*!< Error */
+} HAL_LCD_StateTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct
+{
+  LCD_TypeDef                   *Instance;  /* LCD registers base address */
+
+  LCD_InitTypeDef               Init;       /* LCD communication parameters */
+
+  HAL_LockTypeDef               Lock;       /* Locking object */
+
+  __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
+
+  __IO uint32_t                 ErrorCode;  /* LCD Error code */
+
+}LCD_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LCD_Exported_Constants LCD Exported Constants
+  * @{
+  */
+
+/** @defgroup  LCD_ErrorCode LCD Error Code
+  * @{
+  */ 
+#define HAL_LCD_ERROR_NONE       ((uint32_t)0x00)    /*!< No error */
+#define HAL_LCD_ERROR_FCRSF      ((uint32_t)0x01)    /*!< Synchro flag timeout error */
+#define HAL_LCD_ERROR_UDR        ((uint32_t)0x02)    /*!< Update display request flag timeout error */
+#define HAL_LCD_ERROR_UDD        ((uint32_t)0x04)    /*!< Update display done flag timeout error */
+#define HAL_LCD_ERROR_ENS        ((uint32_t)0x08)    /*!< LCD enabled status flag timeout error */
+#define HAL_LCD_ERROR_RDY        ((uint32_t)0x10)    /*!< LCD Booster ready timeout error */
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Prescaler LCD Prescaler
+  * @{
+  */
+#define LCD_PRESCALER_1        ((uint32_t)0x00000000)  /*!< CLKPS = LCDCLK        */
+#define LCD_PRESCALER_2        ((uint32_t)0x00400000)  /*!< CLKPS = LCDCLK/2      */
+#define LCD_PRESCALER_4        ((uint32_t)0x00800000)  /*!< CLKPS = LCDCLK/4      */
+#define LCD_PRESCALER_8        ((uint32_t)0x00C00000)  /*!< CLKPS = LCDCLK/8      */
+#define LCD_PRESCALER_16       ((uint32_t)0x01000000)  /*!< CLKPS = LCDCLK/16     */
+#define LCD_PRESCALER_32       ((uint32_t)0x01400000)  /*!< CLKPS = LCDCLK/32     */
+#define LCD_PRESCALER_64       ((uint32_t)0x01800000)  /*!< CLKPS = LCDCLK/64     */
+#define LCD_PRESCALER_128      ((uint32_t)0x01C00000)  /*!< CLKPS = LCDCLK/128    */
+#define LCD_PRESCALER_256      ((uint32_t)0x02000000)  /*!< CLKPS = LCDCLK/256    */
+#define LCD_PRESCALER_512      ((uint32_t)0x02400000)  /*!< CLKPS = LCDCLK/512    */
+#define LCD_PRESCALER_1024     ((uint32_t)0x02800000)  /*!< CLKPS = LCDCLK/1024   */
+#define LCD_PRESCALER_2048     ((uint32_t)0x02C00000)  /*!< CLKPS = LCDCLK/2048   */
+#define LCD_PRESCALER_4096     ((uint32_t)0x03000000)  /*!< CLKPS = LCDCLK/4096   */
+#define LCD_PRESCALER_8192     ((uint32_t)0x03400000)  /*!< CLKPS = LCDCLK/8192   */
+#define LCD_PRESCALER_16384    ((uint32_t)0x03800000)  /*!< CLKPS = LCDCLK/16384  */
+#define LCD_PRESCALER_32768    ((uint32_t)0x03C00000)  /*!< CLKPS = LCDCLK/32768  */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Divider LCD Divider
+  * @{
+  */
+#define LCD_DIVIDER_16    ((uint32_t)0x00000000)  /*!< LCD frequency = CLKPS/16 */
+#define LCD_DIVIDER_17    ((uint32_t)0x00040000)  /*!< LCD frequency = CLKPS/17 */
+#define LCD_DIVIDER_18    ((uint32_t)0x00080000)  /*!< LCD frequency = CLKPS/18 */
+#define LCD_DIVIDER_19    ((uint32_t)0x000C0000)  /*!< LCD frequency = CLKPS/19 */
+#define LCD_DIVIDER_20    ((uint32_t)0x00100000)  /*!< LCD frequency = CLKPS/20 */
+#define LCD_DIVIDER_21    ((uint32_t)0x00140000)  /*!< LCD frequency = CLKPS/21 */
+#define LCD_DIVIDER_22    ((uint32_t)0x00180000)  /*!< LCD frequency = CLKPS/22 */
+#define LCD_DIVIDER_23    ((uint32_t)0x001C0000)  /*!< LCD frequency = CLKPS/23 */
+#define LCD_DIVIDER_24    ((uint32_t)0x00200000)  /*!< LCD frequency = CLKPS/24 */
+#define LCD_DIVIDER_25    ((uint32_t)0x00240000)  /*!< LCD frequency = CLKPS/25 */
+#define LCD_DIVIDER_26    ((uint32_t)0x00280000)  /*!< LCD frequency = CLKPS/26 */
+#define LCD_DIVIDER_27    ((uint32_t)0x002C0000)  /*!< LCD frequency = CLKPS/27 */
+#define LCD_DIVIDER_28    ((uint32_t)0x00300000)  /*!< LCD frequency = CLKPS/28 */
+#define LCD_DIVIDER_29    ((uint32_t)0x00340000)  /*!< LCD frequency = CLKPS/29 */
+#define LCD_DIVIDER_30    ((uint32_t)0x00380000)  /*!< LCD frequency = CLKPS/30 */
+#define LCD_DIVIDER_31    ((uint32_t)0x003C0000)  /*!< LCD frequency = CLKPS/31 */
+/**
+  * @}
+  */
+
+
+/** @defgroup LCD_Duty LCD Duty
+  * @{
+  */
+#define LCD_DUTY_STATIC                 ((uint32_t)0x00000000)            /*!< Static duty */
+#define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
+#define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
+#define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
+#define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
+/**
+  * @}
+  */
+
+
+/** @defgroup LCD_Bias LCD Bias
+  * @{
+  */
+#define LCD_BIAS_1_4                    ((uint32_t)0x00000000)  /*!< 1/4 Bias */
+#define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
+#define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Voltage_Source LCD Voltage Source
+  * @{
+  */
+#define LCD_VOLTAGESOURCE_INTERNAL      ((uint32_t)0x00000000)  /*!< Internal voltage source for the LCD */
+#define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Interrupts LCD Interrupts
+  * @{
+  */
+#define LCD_IT_SOF                      LCD_FCR_SOFIE
+#define LCD_IT_UDD                      LCD_FCR_UDDIE
+/**
+  * @}
+  */
+
+/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
+  * @{
+  */
+#define LCD_PULSEONDURATION_0           ((uint32_t)0x00000000)          /*!< Pulse ON duration = 0 pulse   */
+#define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
+#define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
+#define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
+#define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
+#define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
+#define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
+#define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
+/**
+  * @}
+  */
+
+
+/** @defgroup LCD_DeadTime LCD Dead Time
+  * @{
+  */
+#define LCD_DEADTIME_0                  ((uint32_t)0x00000000)            /*!< No dead Time  */
+#define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
+#define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
+#define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
+#define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
+#define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
+#define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
+#define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_BlinkMode LCD Blink Mode
+  * @{
+  */
+#define LCD_BLINKMODE_OFF               ((uint32_t)0x00000000)  /*!< Blink disabled            */
+#define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
+#define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to
+                                                                    8 pixels according to the programmed duty)  */
+#define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
+  * @{
+  */
+#define LCD_BLINKFREQUENCY_DIV8         ((uint32_t)0x00000000)                /*!< The Blink frequency = fLCD/8    */
+#define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
+#define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
+#define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
+#define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
+#define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
+#define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
+#define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Contrast LCD Contrast
+  * @{
+  */
+#define LCD_CONTRASTLEVEL_0               ((uint32_t)0x00000000)        /*!< Maximum Voltage = 2.60V    */
+#define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
+#define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
+#define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
+#define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
+#define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.26V    */
+#define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.40V    */
+#define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.55V    */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_RAMRegister LCD RAMRegister
+  * @{
+  */
+#define LCD_RAM_REGISTER0               ((uint32_t)0x00000000) /*!< LCD RAM Register 0  */
+#define LCD_RAM_REGISTER1               ((uint32_t)0x00000001) /*!< LCD RAM Register 1  */
+#define LCD_RAM_REGISTER2               ((uint32_t)0x00000002) /*!< LCD RAM Register 2  */
+#define LCD_RAM_REGISTER3               ((uint32_t)0x00000003) /*!< LCD RAM Register 3  */
+#define LCD_RAM_REGISTER4               ((uint32_t)0x00000004) /*!< LCD RAM Register 4  */
+#define LCD_RAM_REGISTER5               ((uint32_t)0x00000005) /*!< LCD RAM Register 5  */
+#define LCD_RAM_REGISTER6               ((uint32_t)0x00000006) /*!< LCD RAM Register 6  */
+#define LCD_RAM_REGISTER7               ((uint32_t)0x00000007) /*!< LCD RAM Register 7  */
+#define LCD_RAM_REGISTER8               ((uint32_t)0x00000008) /*!< LCD RAM Register 8  */
+#define LCD_RAM_REGISTER9               ((uint32_t)0x00000009) /*!< LCD RAM Register 9  */
+#define LCD_RAM_REGISTER10              ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
+#define LCD_RAM_REGISTER11              ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
+#define LCD_RAM_REGISTER12              ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
+#define LCD_RAM_REGISTER13              ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
+#define LCD_RAM_REGISTER14              ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
+#define LCD_RAM_REGISTER15              ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_HighDrive LCD High Drive
+  * @{
+  */
+
+#define LCD_HIGHDRIVE_DISABLE             ((uint32_t)0x00000000)        /*!< High drive disabled */
+#define LCD_HIGHDRIVE_ENABLE              (LCD_FCR_HD)                  /*!< High drive enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_MuxSegment LCD Mux Segment
+  * @{
+  */
+
+#define LCD_MUXSEGMENT_DISABLE            ((uint32_t)0x00000000)        /*!< SEG pin multiplexing disabled */
+#define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Flag_Definition LCD Flags Definition
+  * @{
+  */
+#define LCD_FLAG_ENS                    LCD_SR_ENS   /*!< LCD enabled status */
+#define LCD_FLAG_SOF                    LCD_SR_SOF   /*!< Start of frame flag */
+#define LCD_FLAG_UDR                    LCD_SR_UDR   /*!< Update display request */
+#define LCD_FLAG_UDD                    LCD_SR_UDD   /*!< Update display done */
+#define LCD_FLAG_RDY                    LCD_SR_RDY   /*!< Ready flag */
+#define LCD_FLAG_FCRSF                  LCD_SR_FCRSR /*!< LCD Frame Control Register Synchronization flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup LCD_Exported_Macros LCD Exported Macros
+  * @{
+  */
+
+/** @brief Reset LCD handle state.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
+
+/** @brief  Enable the LCD peripheral.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
+
+/** @brief  Disable the LCD peripheral.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
+
+/** @brief  Enable the low resistance divider.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @note   Displays with high internal resistance may need a longer drive time to
+  *         achieve satisfactory contrast. This function is useful in this case if
+  *         some additional power consumption can be tolerated.
+  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be
+  *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
+  * @retval None
+  */
+#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                       \
+                  do {                                                \
+                    SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
+                    LCD_WaitForSynchro(__HANDLE__);                   \
+                  } while(0)
+
+/** @brief  Disable the low resistance divider.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                        \
+                  do {                                                  \
+                    CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
+                    LCD_WaitForSynchro(__HANDLE__);                     \
+                  } while(0)
+
+/** @brief  Enable the voltage output buffer for higher driving capability.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
+
+/** @brief  Disable the voltage output buffer for higher driving capability.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
+
+/**
+  * @brief  Configure the LCD pulse on duration.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __DURATION__: specifies the LCD pulse on duration in terms of
+  *         CK_PS (prescaled LCD clock period) pulses.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_PULSEONDURATION_0: 0 pulse
+  *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
+  *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
+  *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
+  *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
+  *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
+  *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
+  *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
+  * @retval None
+  */
+#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                        \
+                  do {                                                                    \
+                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
+                    LCD_WaitForSynchro(__HANDLE__);                                       \
+                  } while(0)
+
+/**
+  * @brief  Configure the LCD dead time.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __DEADTIME__: specifies the LCD dead time.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_DEADTIME_0: No dead Time
+  *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
+  * @retval None
+  */
+#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                                \
+                  do {                                                                     \
+                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
+                    LCD_WaitForSynchro(__HANDLE__);                                        \
+                  } while(0)
+
+/**
+  * @brief  Configure the LCD contrast.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __CONTRAST__: specifies the LCD Contrast.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
+  *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
+  *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
+  *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
+  *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
+  *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
+  *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
+  *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
+  * @retval None
+  */
+#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                           \
+              do {                                                                    \
+                MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
+                LCD_WaitForSynchro(__HANDLE__);                                       \
+              } while(0)
+
+/**
+  * @brief  Configure the LCD Blink mode and Blink frequency.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __BLINKMODE__: specifies the LCD blink mode.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_BLINKMODE_OFF:           Blink disabled
+  *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
+  *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8
+  *                                       pixels according to the programmed duty)
+  *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
+  *                                       (all pixels)
+  * @param  __BLINKFREQUENCY__: specifies the LCD blink frequency.
+  *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
+  *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
+  *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
+  *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64
+  *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
+  *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
+  *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
+  *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
+  * @retval None
+  */
+#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)         \
+              do {                                                                    \
+                MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
+                LCD_WaitForSynchro(__HANDLE__);                                       \
+              } while(0)
+
+/** @brief  Enable the specified LCD interrupt.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __INTERRUPT__: specifies the LCD interrupt source to be enabled.
+  *          This parameter can be one of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                      \
+                  do {                                                      \
+                    SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));  \
+                    LCD_WaitForSynchro(__HANDLE__);                         \
+                  } while(0)
+
+/** @brief  Disable the specified LCD interrupt.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __INTERRUPT__: specifies the LCD interrupt source to be disabled.
+  *          This parameter can be one of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                      \
+                  do {                                                       \
+                    CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
+                    LCD_WaitForSynchro(__HANDLE__);                          \
+                  } while(0)
+
+/** @brief  Check whether the specified LCD interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __IT__: specifies the LCD interrupt source to check.
+  *        This parameter can be one of the following values:
+  *        @arg LCD_IT_SOF: Start of Frame Interrupt
+  *        @arg LCD_IT_UDD: Update Display Done Interrupt.
+  * @note If the device is in STOP mode (PCLK not provided) UDD will not
+  *          generate an interrupt even if UDDIE = 1.
+  *          If the display is not enabled the UDD interrupt will never occur.
+  * @retval The state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
+
+/** @brief  Check whether the specified LCD flag is set or not.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
+  * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR
+  *             goes from 0 to 1. On deactivation it reflects the real status of
+  *             LCD so it becomes 0 at the end of the last displayed frame.
+  *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
+  *             the beginning of a new frame, at the same time as the display data is
+  *             updated.
+  *        @arg LCD_FLAG_UDR: Update Display Request flag.
+  *        @arg LCD_FLAG_UDD: Update Display Done flag.
+  *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
+  *             of the step-up converter.
+  *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
+  *             This flag is set by hardware each time the LCD_FCR register is updated
+  *             in the LCDCLK domain.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified LCD pending flag.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be any combination of the following values:
+  *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
+  *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/** @addtogroup LCD_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization methods  **********************************/
+/** @addtogroup LCD_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef    HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
+HAL_StatusTypeDef    HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
+void                 HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
+void                 HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
+/**
+  * @}
+  */
+
+/* IO operation methods *******************************************************/
+/** @addtogroup LCD_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef    HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
+HAL_StatusTypeDef    HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
+HAL_StatusTypeDef    HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
+/**
+  * @}
+  */
+
+/* Peripheral State methods  **************************************************/
+/** @addtogroup LCD_Exported_Functions_Group3
+  * @{
+  */
+HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
+uint32_t             HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LCD_Private_Macros LCD Private Macros
+  * @{
+  */
+
+#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_32768))
+
+#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_31))
+
+#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
+                               ((__DUTY__) == LCD_DUTY_1_2)     || \
+                               ((__DUTY__) == LCD_DUTY_1_3)     || \
+                               ((__DUTY__) == LCD_DUTY_1_4)     || \
+                               ((__DUTY__) == LCD_DUTY_1_8))
+
+#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
+                               ((__BIAS__) == LCD_BIAS_1_2) || \
+                               ((__BIAS__) == LCD_BIAS_1_3))
+
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
+                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
+
+
+#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_7))
+
+#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
+                                    ((__TIME__) == LCD_DEADTIME_1) || \
+                                    ((__TIME__) == LCD_DEADTIME_2) || \
+                                    ((__TIME__) == LCD_DEADTIME_3) || \
+                                    ((__TIME__) == LCD_DEADTIME_4) || \
+                                    ((__TIME__) == LCD_DEADTIME_5) || \
+                                    ((__TIME__) == LCD_DEADTIME_6) || \
+                                    ((__TIME__) == LCD_DEADTIME_7))
+
+#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
+                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
+                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
+                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
+
+#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
+
+#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
+
+#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER15))
+
+#define IS_LCD_HIGH_DRIVE(__VALUE__) (((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
+                                      ((__VALUE__) == LCD_HIGHDRIVE_ENABLE))
+
+#define IS_LCD_MUX_SEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
+                                       ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup LCD_Private_Functions
+  * @{
+  */
+
+HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_LCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c
new file mode 100755
index 0000000..362dfa5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c
@@ -0,0 +1,1672 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_lptim.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   LPTIM HAL module driver. 
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Low Power Timer (LPTIM) peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Start/Stop operation functions in polling mode.
+  *           + Start/Stop operation functions in interrupt mode.
+  *           + Reading operation functions.
+  *           + Peripheral State functions.
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The LPTIM HAL driver can be used as follows:
+
+      (#)Initialize the LPTIM low level resources by implementing the
+        HAL_LPTIM_MspInit():
+         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
+         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
+             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
+             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
+    
+      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
+         configures mainly:
+         (++) The instance: LPTIM1 or LPTIM2.
+         (++) Clock: the counter clock.
+             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
+                              the internal clock; (APB, LSE, LSI or MSI).
+             (+++) Prescaler: select the clock divider.
+         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
+               as counter clock source.
+             (+++) Polarity:   polarity of the active edge for the counter unit
+                               if the ULPTIM input is selected.
+             (+++) SampleTime: clock sampling time to configure the clock glitch
+                               filter.              
+         (++) Trigger: How the counter start.
+             (+++) Source: trigger can be software or one of the hardware triggers.
+             (+++) ActiveEdge : only for hardware trigger.
+             (+++) SampleTime : trigger sampling time to configure the trigger
+                                glitch filter.
+         (++) OutputPolarity : 2 opposite polarities are possible.
+         (++) UpdateMode: specifies whether the update of the autoreload and
+              the compare values is done immediately or after the end of current
+              period.   
+         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
+         (++) Input2Source: Source selected for input2 (GPIO or comparator output). 
+              Input2 is used only for encoder feature so is used only for LPTIM1 instance.
+    
+      (#)Six modes are available:
+      
+         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
+         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
+         mode.
+         
+         (++) One Pulse Mode: To generate pulse with specified width in response
+         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
+         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
+         
+         (++) Set once Mode: In this mode, the output changes the level (from
+         low level to high level if the output polarity is configured high, else
+         the opposite) when a compare match occurs. To start this mode, call 
+         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
+         interruption mode.
+         
+         (++) Encoder Mode: To use the encoder interface call
+         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for 
+         interruption mode. Only available for LPTIM1 instance.
+         
+         (++) Time out Mode: an active edge on one selected trigger input rests
+         the counter. The first trigger event will start the timer, any
+         successive trigger event will reset the counter and the timer will
+         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or 
+         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
+         
+         (++) Counter Mode: counter can be used to count external events on
+         the LPTIM Input1 or it can be used to count internal clock cycles.
+         To start this mode, call HAL_LPTIM_Counter_Start() or 
+         HAL_LPTIM_Counter_Start_IT() for interruption mode.             
+
+    
+      (#) User can stop any process by calling the corresponding API:
+          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
+          already started in interruption mode.
+         
+      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup LPTIM LPTIM
+  * @brief LPTIM HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the LPTIM according to the specified parameters in the
+          LPTIM_InitTypeDef and initialize the associated handle.
+      (+) DeInitialize the LPTIM peripheral.
+      (+) Initialize the LPTIM MSP.
+      (+) DeInitialize the LPTIM MSP. 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the LPTIM according to the specified parameters in the
+  *         LPTIM_InitTypeDef and initialize the associated handle.
+  * @param  hlptim: LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
+{
+  uint32_t tmpcfgr = 0;
+
+  /* Check the LPTIM handle allocation */
+  if(hlptim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));  
+  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
+  {
+    assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+    assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+  }  
+  assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
+    assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+  }  
+  assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));  
+  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
+  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
+  
+  if(hlptim->State == HAL_LPTIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hlptim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_LPTIM_MspInit(hlptim);
+  }
+  
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+  
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+  
+  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
+  {
+    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+  }
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+  }
+    
+  /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+                          LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
+  
+  /* Set initialization parameters */
+  tmpcfgr |= (hlptim->Init.Clock.Source    |
+              hlptim->Init.Clock.Prescaler |
+              hlptim->Init.OutputPolarity  |
+              hlptim->Init.UpdateMode      |
+              hlptim->Init.CounterSource);
+  
+  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
+  {
+    tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |
+                hlptim->Init.UltraLowPowerClock.SampleTime);
+  } 
+  
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable External trigger and set the trigger source */
+    tmpcfgr |= (hlptim->Init.Trigger.Source     |
+                hlptim->Init.Trigger.ActiveEdge |
+                hlptim->Init.Trigger.SampleTime);
+  }
+  
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+
+  /* Configure LPTIM input sources */
+  if(hlptim->Instance == LPTIM1)
+  {
+    /* Check LPTIM1 Input1 and Input2 sources */
+    assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
+    assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance,hlptim->Init.Input2Source));
+    
+    /* Configure LPTIM1 Input1 and Input2 sources */
+    hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
+  }
+  else
+  {
+    /* Check LPTIM2 Input1 source */
+    assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
+    
+    /* Configure LPTIM2 Input1 source */
+    hlptim->Instance->OR = hlptim->Init.Input1Source;
+  }
+  
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the LPTIM peripheral. 
+  * @param  hlptim: LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the LPTIM handle allocation */
+  if(hlptim == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the LPTIM Peripheral Clock */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_LPTIM_MspDeInit(hlptim);
+  
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hlptim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the LPTIM MSP.
+  * @param  hlptim: LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize LPTIM MSP.
+  * @param  hlptim: LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions 
+ *  @brief   Start-Stop operation functions. 
+ *
+@verbatim   
+  ==============================================================================
+                ##### LPTIM Start Stop operation functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start the PWM mode.
+      (+) Stop the PWM mode.
+      (+) Start the One pulse mode.
+      (+) Stop the One pulse mode.
+      (+) Start the Set once mode.
+      (+) Stop the Set once mode.
+      (+) Start the Encoder mode.
+      (+) Stop the Encoder mode.
+      (+) Start the Timeout mode.
+      (+) Stop the Timeout mode.      
+      (+) Start the Counter mode.
+      (+) Stop the Counter mode.
+      
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Start the LPTIM PWM generation.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+ 
+  /* Reset WAVE bit to set PWM mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM PWM generation.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM PWM generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+ 
+  /* Reset WAVE bit to set PWM mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Compare write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }  
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM PWM generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+    /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Compare write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then disable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Disable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }  
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM One pulse generation.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Reset WAVE bit to set one pulse mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM One pulse generation.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM One pulse generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Reset WAVE bit to set one pulse mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Compare write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM One pulse generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Compare write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then disable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Disable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM in Set once mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Set WAVE bit to enable the set once mode */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM Set once mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM Set once mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Set WAVE bit to enable the set once mode */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Compare write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }  
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM Set once mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Compare write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then disable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Disable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  } 
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Encoder interface.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t          tmpcfgr;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+  /* Encoder feature is only available for LPTIM1 instance */
+  if (hlptim->Instance == LPTIM1)
+  {
+    /* Set the LPTIM state */
+    hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+    /* Get the LPTIMx CFGR value */
+    tmpcfgr = hlptim->Instance->CFGR;
+
+    /* Clear CKPOL bits */
+    tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+    /* Set Input polarity */
+    tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
+
+    /* Write to LPTIMx CFGR */
+    hlptim->Instance->CFGR = tmpcfgr;
+
+    /* Set ENC bit to enable the encoder interface */
+    hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+    /* Enable the Peripheral */
+    __HAL_LPTIM_ENABLE(hlptim);
+
+    /* Load the period value in the autoreload register */
+    __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+    /* Start timer in continuous mode */
+    __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+    /* Change the TIM state*/
+    hlptim->State= HAL_LPTIM_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the Encoder interface.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset ENC bit to disable the encoder interface */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Encoder interface in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t          tmpcfgr;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+  /* Encoder feature is only available for LPTIM1 instance */
+  if (hlptim->Instance == LPTIM1)
+  {
+    /* Set the LPTIM state */
+    hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+    /* Configure edge sensitivity for encoder mode */
+    /* Get the LPTIMx CFGR value */
+    tmpcfgr = hlptim->Instance->CFGR;
+
+    /* Clear CKPOL bits */
+    tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+    /* Set Input polarity */
+    tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
+
+    /* Write to LPTIMx CFGR */
+    hlptim->Instance->CFGR = tmpcfgr;
+
+    /* Set ENC bit to enable the encoder interface */
+    hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+    /* Enable "switch to down direction" interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
+
+    /* Enable "switch to up direction" interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);  
+
+    /* Enable the Peripheral */
+    __HAL_LPTIM_ENABLE(hlptim);
+
+    /* Load the period value in the autoreload register */
+    __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+    /* Start timer in continuous mode */
+    __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+    /* Change the TIM state*/
+    hlptim->State= HAL_LPTIM_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the Encoder interface in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset ENC bit to disable the encoder interface */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+  
+  /* Disable "switch to down direction" interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
+  
+  /* Disable "switch to up direction" interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); 
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Timeout function.
+  * @note   The first trigger event will start the timer, any successive
+  *         trigger event will reset the counter and the timer restarts.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Timeout : Specifies the TimeOut value to rest the counter.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Timeout));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+ 
+  /* Set TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the Timeout value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Timeout function.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Timeout function in interrupt mode.
+  * @note   The first trigger event will start the timer, any successive
+  *         trigger event will reset the counter and the timer restarts.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Timeout : Specifies the TimeOut value to rest the counter.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Timeout));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+ 
+  /* Set TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the Timeout value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Timeout function in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Counter mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    /* Check if clock is prescaled */
+    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+    /* Set clock prescaler to 0 */
+    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+  }
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Counter mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Counter mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    /* Check if clock is prescaled */
+    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+    /* Set clock prescaler to 0 */
+    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+  }
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Counter mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions 
+ *  @brief  Read operation functions.
+ *
+@verbatim   
+  ==============================================================================
+                  ##### LPTIM Read operation functions #####
+  ==============================================================================  
+[..]  This section provides LPTIM Reading functions.
+      (+) Read the counter value.
+      (+) Read the period (Auto-reload) value.
+      (+) Read the pulse (Compare)value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the current counter value.
+  * @param  hlptim: LPTIM handle
+  * @retval Counter value.
+  */
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
+{
+    /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  return (hlptim->Instance->CNT);
+}
+
+/**
+  * @brief  Return the current Autoreload (Period) value.
+  * @param  hlptim: LPTIM handle
+  * @retval Autoreload value.
+  */
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
+{
+    /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  return (hlptim->Instance->ARR);
+}
+
+/**
+  * @brief  Return the current Compare (Pulse) value.
+  * @param  hlptim: LPTIM handle
+  * @retval Compare value.
+  */
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
+{
+    /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  return (hlptim->Instance->CMP);
+}
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
+ *  @brief  LPTIM  IRQ handler.
+ *
+@verbatim   
+  ==============================================================================
+                      ##### LPTIM IRQ handler and callbacks  #####
+  ==============================================================================  
+[..]  This section provides LPTIM IRQ handler and callback functions called within 
+      the IRQ handler.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle LPTIM interrupt request.
+  * @param  hlptim: LPTIM handle
+  * @retval None
+  */
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Compare match interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
+    {
+      /* Clear Compare match flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
+      
+      /* Compare match Callback */
+      HAL_LPTIM_CompareMatchCallback(hlptim);      
+    }
+  }
+  
+  /* Autoreload match interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
+    {
+      /* Clear Autoreload match flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+      
+      /* Autoreload match Callback */
+      HAL_LPTIM_AutoReloadMatchCallback(hlptim);      
+    }
+  }
+  
+  /* Trigger detected interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
+    {
+      /* Clear Trigger detected flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+      
+      /* Trigger detected callback */
+      HAL_LPTIM_TriggerCallback(hlptim);      
+    }
+  }
+  
+  /* Compare write interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
+    {
+      /* Clear Compare write flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+      
+      /* Compare write Callback */
+      HAL_LPTIM_CompareWriteCallback(hlptim);      
+    }
+  }
+  
+  /* Autoreload write interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
+    {
+      /* Clear Autoreload write flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+      
+      /* Autoreload write Callback */
+      HAL_LPTIM_AutoReloadWriteCallback(hlptim);      
+    }
+  }
+  
+  /* Direction counter changed from Down to Up interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
+    {
+      /* Clear Direction counter changed from Down to Up flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+      
+      /* Direction counter changed from Down to Up Callback */
+      HAL_LPTIM_DirectionUpCallback(hlptim);      
+    }
+  }
+  
+  /* Direction counter changed from Up to Down interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
+    {
+      /* Clear Direction counter changed from Up to Down flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+      
+      /* Direction counter changed from Up to Down Callback */
+      HAL_LPTIM_DirectionDownCallback(hlptim);      
+    }
+  }
+}
+
+/**
+  * @brief  Compare match callback in non-blocking mode.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Autoreload match callback in non-blocking mode.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Trigger detected callback in non-blocking mode.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_TriggerCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Compare write callback in non-blocking mode.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Autoreload write callback in non-blocking mode. 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions 
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the LPTIM handle state.
+  * @param  hlptim: LPTIM handle
+  * @retval HAL state
+  */
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Return LPTIM handle state */
+  return hlptim->State;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h
new file mode 100755
index 0000000..d5426a7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h
@@ -0,0 +1,704 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_lptim.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of LPTIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_LPTIM_H
+#define __STM32L4xx_HAL_LPTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup LPTIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  LPTIM Clock configuration definition  
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Selects the clock source.
+                           This parameter can be a value of @ref LPTIM_Clock_Source   */
+
+  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
+                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+  
+}LPTIM_ClockConfigTypeDef;
+
+/** 
+  * @brief  LPTIM Clock configuration definition  
+  */
+typedef struct
+{
+  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
+                           if the ULPTIM input is selected.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           Note: If the polarity is configured on 'both edges', an auxiliary clock
+                           (one of the Low power oscillator) must be active.
+                           This parameter can be a value of @ref LPTIM_Clock_Polarity */ 
+  
+  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */  
+  
+}LPTIM_ULPClockConfigTypeDef;
+
+/** 
+  * @brief  LPTIM Trigger configuration definition  
+  */
+typedef struct
+{
+  uint32_t Source;        /*!< Selects the Trigger source.
+                          This parameter can be a value of @ref LPTIM_Trigger_Source */
+  
+  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
+  
+  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */  
+}LPTIM_TriggerConfigTypeDef;
+
+/** 
+  * @brief  LPTIM Initialization Structure definition  
+  */
+typedef struct
+{                                                    
+  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
+                                                    
+  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
+                                                    
+  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
+                                                    
+  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
+                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */
+                                                    
+  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare
+                                                    values is done immediately or after the end of current period.
+                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */
+
+  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
+                                                    or each external event.
+                                                    This parameter can be a value of @ref LPTIM_Counter_Source */  
+
+  uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
+                                                    This parameter can be a value of @ref LPTIM_Input1_Source */  
+
+  uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
+                                                    Note: This parameter is used only for encoder feature so is used only 
+                                                    for LPTIM1 instance.
+                                                    This parameter can be a value of @ref LPTIM_Input2_Source */  
+  
+}LPTIM_InitTypeDef;
+
+/** 
+  * @brief  HAL LPTIM State structure definition  
+  */ 
+typedef enum __HAL_LPTIM_StateTypeDef
+{
+  HAL_LPTIM_STATE_RESET            = 0x00,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_LPTIM_STATE_READY            = 0x01,    /*!< Peripheral Initialized and ready for use    */
+  HAL_LPTIM_STATE_BUSY             = 0x02,    /*!< An internal process is ongoing              */    
+  HAL_LPTIM_STATE_TIMEOUT          = 0x03,    /*!< Timeout state                               */  
+  HAL_LPTIM_STATE_ERROR            = 0x04     /*!< Internal Process is ongoing                */                                                                             
+}HAL_LPTIM_StateTypeDef;
+
+/** 
+  * @brief  LPTIM handle Structure definition  
+  */ 
+typedef struct
+{
+      LPTIM_TypeDef              *Instance;         /*!< Register base address     */
+      
+      LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
+  
+      HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */  
+  
+      HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
+  
+   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
+  
+}LPTIM_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
+  * @{
+  */
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00)
+#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
+/**                                             
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
+  * @{
+  */
+#define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000)
+#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
+#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
+#define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
+#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
+#define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
+/**
+  * @}
+  */ 
+
+/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
+  * @{
+  */
+
+#define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000)
+#define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
+  * @{
+  */
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
+  * @{
+  */
+#define LPTIM_CLOCKPOLARITY_RISING              ((uint32_t)0x00000000)
+#define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
+  * @{
+  */
+#define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFF)
+#define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000)
+#define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
+#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
+#define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
+#define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_6                      ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
+  * @{
+  */
+#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
+#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
+#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
+  * @{
+  */
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
+  * @{
+  */
+
+#define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000)
+#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
+  * @{
+  */
+
+#define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000)
+#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
+/**
+  * @}
+  */
+ 
+/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
+  * @{
+  */
+
+#define LPTIM_INPUT1SOURCE_GPIO         ((uint32_t)0x00000000) /*!< For LPTIM1 and LPTIM2 */
+#define LPTIM_INPUT1SOURCE_COMP1        LPTIM_OR_OR_0          /*!< For LPTIM1 and LPTIM2 */
+#define LPTIM_INPUT1SOURCE_COMP2        LPTIM_OR_OR_1          /*!< For LPTIM2 */
+#define LPTIM_INPUT1SOURCE_COMP1_COMP2  LPTIM_OR_OR            /*!< For LPTIM2 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
+  * @{
+  */
+
+#define LPTIM_INPUT2SOURCE_GPIO         ((uint32_t)0x00000000) /*!< For LPTIM1 */
+#define LPTIM_INPUT2SOURCE_COMP2        LPTIM_OR_OR_1          /*!< For LPTIM1 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
+  * @{
+  */
+
+#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
+#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
+#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
+#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
+  * @{
+  */
+
+#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
+#define LPTIM_IT_UP                              LPTIM_IER_UPIE
+#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
+#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
+#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
+#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
+#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @brief Reset LPTIM handle state.
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
+
+/**
+  * @brief  Enable the LPTIM peripheral.
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
+
+/**
+  * @brief  Disable the LPTIM peripheral.
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))
+
+/**
+  * @brief  Start the LPTIM peripheral in Continuous or in single mode.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
+ 
+    
+/**
+  * @brief  Write the passed parameter in the Autoreload register.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __VALUE__: Autoreload value
+  * @retval None
+  */
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
+
+/**
+  * @brief  Write the passed parameter in the Compare register.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __VALUE__: Compare value
+  * @retval None
+  */
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
+
+/**
+  * @brief  Check whether the specified LPTIM flag is set or not.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __FLAG__: LPTIM flag to check
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
+  * @retval The state of the specified flag (SET or RESET).
+  */
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the specified LPTIM flag.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __FLAG__: LPTIM flag to clear.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
+  * @retval None
+  */
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
+
+/**
+  * @brief  Enable the specified LPTIM interrupt.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __INTERRUPT__: LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval None
+  */
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
+
+ /**
+  * @brief  Disable the specified LPTIM interrupt.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __INTERRUPT__: LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval None
+  */
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
+
+    /**
+  * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __INTERRUPT__: LPTIM interrupt to check.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval Interrupt status.
+  */
+    
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @}
+  */
+   
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* MSP functions  *************************************************************/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* Start/Stop operation functions  *********************************************/
+/* ################################# PWM Mode ################################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# One Pulse Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Set once Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################### Encoder Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# Time out  Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Counter Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* Reading operation functions ************************************************/
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+
+/* LPTIM IRQ functions  *******************************************************/
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
+
+/* CallBack functions  ********************************************************/
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+
+/* Peripheral State functions  ************************************************/
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+
+/**
+  * @}
+  */
+  
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
+  * @{
+  */
+                                                
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+                                                
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
+
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
+                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
+
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))
+
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
+
+#define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFF)
+
+#define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFF)
+
+#define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFF)
+
+#define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFF)
+
+#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
+    ((((__INSTANCE__) == LPTIM1) &&                       \
+     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
+     ||                                                   \
+     (((__INSTANCE__) == LPTIM2) &&                       \
+     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
+
+#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
+     (((__INSTANCE__) == LPTIM1) &&                       \
+     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
+      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
+
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c
new file mode 100755
index 0000000..833c420
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c
@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_msp_template.c
+  * @author  MCD Application Team
+  * @version V1.5.1
+  * @date    31-May-2016
+  * @brief   HAL MSP module.
+  *          This file template is located in the HAL folder and should be copied 
+  *          to the user folder.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL_MSP HAL MSP module driver
+  * @brief HAL MSP module.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the Global MSP.
+  * @param  None
+  * @retval None
+  */
+void HAL_MspInit(void)
+{
+  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
+            modified by the user
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the Global MSP.
+  * @param  None  
+  * @retval None
+  */
+void HAL_MspDeInit(void)
+{
+  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
+            modified by the user
+   */
+}
+
+/**
+  * @brief  Initialize the PPP MSP.
+  * @param  None
+  * @retval None
+  */
+void HAL_PPP_MspInit(void)
+{
+  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
+            modified by the user
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the PPP MSP.
+  * @param  None  
+  * @retval None
+  */
+void HAL_PPP_MspDeInit(void)
+{
+  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
+            modified by the user
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c
new file mode 100755
index 0000000..bce42d5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c
@@ -0,0 +1,1132 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_nand.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   NAND HAL module driver.
+  *          This file provides a generic firmware to drive NAND memories mounted 
+  *          as external device.
+  *         
+  @verbatim
+  ==============================================================================
+                         ##### How to use this driver #####
+  ==============================================================================    
+    [..]
+      This driver is a generic layered driver which contains a set of APIs used to 
+      control NAND flash memories. It uses the FMC layer functions to interface 
+      with NAND devices. This driver is used as follows:
+    
+      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() 
+          with control and timing parameters for both common and attribute spaces.
+            
+      (+) Read NAND flash memory maker and device IDs using the function
+          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef 
+          structure declared by the function caller. 
+        
+      (+) Access NAND flash memory by read/write operations using the functions
+          HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
+          to read/write page(s)/spare area(s). These functions use specific device 
+          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef 
+          structure. The read/write address information is contained by the Nand_Address_Typedef
+          structure passed as parameter.
+        
+      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+        
+      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+          The erase block address information is contained in the Nand_Address_Typedef 
+          structure passed as parameter.
+    
+      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+        
+      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+          feature or the function HAL_NAND_GetECC() to get the ECC correction code. 
+       
+      (+) You can monitor the NAND device HAL state by calling the function
+          HAL_NAND_GetState()  
+
+    [..]
+      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+          If a NAND flash device contains different operations and/or implementations, 
+          it should be implemented separately.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+/** @defgroup NAND NAND
+  * @brief NAND HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/    
+/** @defgroup NAND_Private_Macros NAND Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup NAND_Private_Functions NAND Private Functions
+  * @{
+  */
+static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
+  * @{
+  */
+    
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+            ##### NAND Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize
+    the NAND memory
+  
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Perform NAND memory Initialization sequence.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  ComSpace_Timing: pointer to Common space timing structure
+  * @param  AttSpace_Timing: pointer to Attribute space timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+  /* Check the NAND handle state */
+  if(hnand == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  if(hnand->State == HAL_NAND_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hnand->Lock = HAL_UNLOCKED;
+
+    /* Initialize the low level hardware (MSP) */
+    HAL_NAND_MspInit(hnand);
+  } 
+
+  /* Initialize NAND control Interface */
+  FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+  
+  /* Initialize NAND common space timing Interface */  
+  FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+  
+  /* Initialize NAND attribute space timing Interface */  
+  FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+  
+  /* Enable the NAND device */
+  __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform NAND memory De-Initialization sequence.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)  
+{
+  /* Initialize the low level hardware (MSP) */
+  HAL_NAND_MspDeInit(hnand);
+
+  /* Configure the NAND registers with their reset values */
+  FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+  /* Reset the NAND controller state */
+  hnand->State = HAL_NAND_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnand);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the NAND MSP.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_NAND_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the NAND MSP.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_NAND_MspDeInit could be implemented in the user file
+   */ 
+}
+
+
+/**
+  * @brief  This function handles NAND device interrupt request.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+*/
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+  /* Check NAND interrupt Rising edge flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+  
+    /* Clear NAND interrupt Rising edge pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
+  }
+  
+  /* Check NAND interrupt Level flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+
+    /* Clear NAND interrupt Level pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
+  }
+
+  /* Check NAND interrupt Falling edge flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+  
+    /* Clear NAND interrupt Falling edge pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
+  }
+  
+  /* Check NAND interrupt FIFO empty flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+  
+    /* Clear NAND interrupt FIFO empty pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
+  }  
+}
+
+/**
+  * @brief  NAND interrupt feature callback.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_NAND_ITCallback could be implemented in the user file
+   */
+}
+ 
+/**
+  * @}
+  */
+  
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                    ##### NAND Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the NAND 
+    memory
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the NAND memory electronic signature.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pNAND_ID: NAND ID structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+  __IO uint32_t data = 0;
+  uint32_t deviceaddress = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hnand);  
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  deviceaddress = NAND_DEVICE;
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_BUSY;
+  
+  /* Send Read ID command sequence */ 	
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+
+  /* Read the electronic signature from NAND flash */	
+  data = *(__IO uint32_t *)deviceaddress;
+  
+  /* Return the data read */
+  pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
+  pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
+  pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
+  pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);   
+   
+  return HAL_OK;
+}
+
+/**
+  * @brief  NAND memory reset.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+  uint32_t deviceaddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);
+    
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Identify the device address */  
+  deviceaddress = NAND_DEVICE;
+  
+  /* Update the NAND controller state */   
+  hnand->State = HAL_NAND_STATE_BUSY; 
+  
+  /* Send NAND reset command */  
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+    
+  
+  /* Update the NAND controller state */   
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);    
+  
+  return HAL_OK;
+  
+}
+
+/**
+  * @brief  Read Page(s) from NAND memory block.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress: pointer to NAND address structure
+  * @param  pBuffer: pointer to destination read buffer
+  * @param  NumPageToRead: number of pages to read from block 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+{   
+  __IO uint32_t index  = 0;
+  uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
+  NAND_AddressTypeDef nandaddress;
+  uint32_t addressoffset = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand); 
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  deviceaddress = NAND_DEVICE;
+
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_BUSY;
+  
+  /* Save the content of pAddress as it will be modified */
+  nandaddress.Block     = pAddress->Block;
+  nandaddress.Page      = pAddress->Page;
+  nandaddress.Zone      = pAddress->Zone;
+  
+  /* Page(s) read loop */
+  while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))  
+  {	   
+    /* update the buffer size */
+    size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
+    
+    /* Get the address offset */
+    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+    
+    /* Send read page command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;  
+   
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; 
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); 
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); 
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */    
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+    }
+  
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
+      
+    /* Get Data into Buffer */    
+    for(; index < size; index++)
+    {
+      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+    }
+    
+    /* Increment read pages number */
+    numpagesread++;
+    
+    /* Decrement pages to read */
+    NumPageToRead--;
+    
+    /* Increment the NAND address */
+    addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+  }
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);  
+    
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Write Page(s) to NAND memory block.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress: pointer to NAND address structure
+  * @param  pBuffer: pointer to source buffer to write  
+  * @param  NumPageToWrite: number of pages to write to block 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+{
+  __IO uint32_t index = 0;
+  uint32_t tickstart = 0;
+  uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
+  NAND_AddressTypeDef nandaddress;
+  uint32_t addressoffset = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);  
+
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  deviceaddress = NAND_DEVICE;
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_BUSY;
+  
+  /* Save the content of pAddress as it will be modified */
+  nandaddress.Block     = pAddress->Block;
+  nandaddress.Page      = pAddress->Page;
+  nandaddress.Zone      = pAddress->Zone;
+    
+  /* Page(s) write loop */
+  while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+  {  
+    /* update the buffer size */
+    size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
+    
+    /* Get the address offset */
+    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+ 
+    /* Send write page command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;  
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);  
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);  
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */     
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+    }
+  
+    /* Write data to memory */
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+    }
+   
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+    
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    
+    /* Read status until NAND is ready */
+    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+    {
+      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+      {
+        return HAL_TIMEOUT; 
+      } 
+    }    
+ 
+    /* Increment written pages number */
+    numpageswritten++;
+    
+    /* Decrement pages to write */
+    NumPageToWrite--;
+    
+    /* Increment the NAND address */
+    addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+  }
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);      
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read Spare area(s) from NAND memory. 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress: pointer to NAND address structure
+  * @param  pBuffer: pointer to source buffer to write  
+  * @param  NumSpareAreaToRead: Number of spare area to read  
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+  __IO uint32_t index   = 0; 
+  uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
+  NAND_AddressTypeDef nandaddress;
+  uint32_t addressoffset = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);  
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  deviceaddress = NAND_DEVICE;
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_BUSY;    
+  
+  /* Save the content of pAddress as it will be modified */
+  nandaddress.Block     = pAddress->Block;
+  nandaddress.Page      = pAddress->Page;
+  nandaddress.Zone      = pAddress->Zone;
+  
+  /* Spare area(s) read loop */ 
+  while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+  { 
+    /* update the buffer size */
+    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);   
+
+    /* Get the address offset */
+    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
+    /* Send read spare area command sequence */     
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+    
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; 
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);     
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);     
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */    
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+    } 
+
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;    
+    
+    /* Get Data into Buffer */
+    for ( ;index < size; index++)
+    {
+      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+    }
+    
+    /* Increment read spare areas number */
+    num_spare_area_read++;
+    
+    /* Decrement spare areas to read */
+    NumSpareAreaToRead--;
+    
+    /* Increment the NAND address */
+    addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+  }
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);     
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Write Spare area(s) to NAND memory.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress: pointer to NAND address structure
+  * @param  pBuffer: pointer to source buffer to write  
+  * @param  NumSpareAreaTowrite: number of spare areas to write to block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+  __IO uint32_t index = 0;
+  uint32_t tickstart = 0;
+  uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
+  NAND_AddressTypeDef nandaddress;
+  uint32_t addressoffset = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hnand); 
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  deviceaddress = NAND_DEVICE;
+  
+  /* Update the FMC_NAND controller state */
+  hnand->State = HAL_NAND_STATE_BUSY;  
+  
+  /* Save the content of pAddress as it will be modified */
+  nandaddress.Block     = pAddress->Block;
+  nandaddress.Page      = pAddress->Page;
+  nandaddress.Zone      = pAddress->Zone;
+  
+  /* Spare area(s) write loop */
+  while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+  {  
+    /* update the buffer size */
+    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
+
+    /* Get the address offset */
+    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+    
+    /* Send write Spare area command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;  
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);  
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);  
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); 
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */     
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+    }
+  
+    /* Write data to memory */
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+    }
+   
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+    
+    /* Get tick */
+    tickstart = HAL_GetTick();
+   
+    /* Read status until NAND is ready */
+    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+    {
+      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+      {
+        return HAL_TIMEOUT; 
+      }   
+    }
+
+    /* Increment written spare areas number */
+    num_spare_area_written++;
+    
+    /* Decrement spare areas to write */
+    NumSpareAreaTowrite--;
+    
+    /* Increment the NAND address */
+    addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+  }
+
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  NAND memory Block erase.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress: pointer to NAND address structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+  uint32_t deviceaddress = 0;
+  uint32_t tickstart = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  deviceaddress = NAND_DEVICE;
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_BUSY;  
+  
+  /* Send Erase block command sequence */
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
+
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  
+  /* for 512 and 1 GB devices, 4th cycle is required */     
+  if(hnand->Info.BlockNbr >= 1024)
+  {
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  }  
+		
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; 
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  /* Read status until NAND is ready */
+  while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+  {
+    if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hnand);    
+  
+      return HAL_TIMEOUT; 
+    } 
+  }    
+ 
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);    
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  NAND memory read status. 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval NAND status
+  */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+  uint32_t data = 0;
+  uint32_t deviceaddress = 0;
+  
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
+  /* Identify the device address */
+   deviceaddress = NAND_DEVICE;
+
+  /* Send Read status operation command */
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
+  
+  /* Read status register data */
+  data = *(__IO uint8_t *)deviceaddress;
+
+  /* Return the status */
+  if((data & NAND_ERROR) == NAND_ERROR)
+  {
+    return NAND_ERROR;
+  } 
+  else if((data & NAND_READY) == NAND_READY)
+  {
+    return NAND_READY;
+  }
+
+  return NAND_BUSY; 
+}
+
+/**
+  * @brief  Increment the NAND memory address.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param pAddress: pointer to NAND address structure
+  * @retval The new status of the increment address operation. It can be:
+  *           - NAND_VALID_ADDRESS: When the new address is valid address
+  *           - NAND_INVALID_ADDRESS: When the new address is invalid address
+  */
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+  uint32_t status = NAND_VALID_ADDRESS;
+ 
+  /* Increment page address */
+  pAddress->Page++;
+
+  /* Check NAND address is valid */
+  if(pAddress->Page == hnand->Info.BlockSize)
+  {
+    pAddress->Page = 0;
+    pAddress->Block++;
+    
+    if(pAddress->Block == hnand->Info.ZoneSize)
+    {
+      pAddress->Block = 0;
+      pAddress->Zone++;
+
+      if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
+      {
+        status = NAND_INVALID_ADDRESS;
+      }
+    }
+  } 
+  
+  return (status);
+}
+/**
+  * @}
+  */
+
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                         ##### NAND Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the NAND interface.
+
+@endverbatim
+  * @{
+  */ 
+
+    
+/**
+  * @brief  Enable dynamically NAND ECC feature.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */    
+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_BUSY;
+   
+  /* Enable ECC feature */
+  FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disable dynamically NAND ECC feature.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */  
+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)  
+{
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_BUSY;
+    
+  /* Disable ECC feature */
+  FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disable dynamically NAND ECC feature.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  ECCval: pointer to ECC value 
+  * @param  Timeout: maximum timeout to wait    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_BUSY;  
+   
+  /* Get NAND ECC value */
+  status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_READY;
+
+  return status;  
+}
+                      
+/**
+  * @}
+  */
+  
+    
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                         ##### NAND State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the NAND controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Return the NAND handle state.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL state
+  */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+{
+  /* Return NAND handle state */
+  return hnand->State;
+}
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Increment the NAND memory address. 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  Address: address to be incremented.
+  * @retval The new status of the increment address operation. It can be:
+  *              - NAND_VALID_ADDRESS: When the new address is valid address
+  *              - NAND_INVALID_ADDRESS: When the new address is invalid address   
+  */
+static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
+{
+  uint32_t status = NAND_VALID_ADDRESS;
+ 
+  Address->Page++;
+
+  if(Address->Page == hnand->Info.BlockSize)
+  {
+    Address->Page = 0;
+    Address->Block++;
+    
+    if(Address->Block == hnand->Info.ZoneSize)
+    {
+      Address->Block = 0;
+      Address->Zone++;
+
+      if(Address->Zone == hnand->Info.BlockNbr)
+      {
+        status = NAND_INVALID_ADDRESS;
+      }
+    }
+  } 
+  
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_NAND_MODULE_ENABLED  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h
new file mode 100755
index 0000000..f039545
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h
@@ -0,0 +1,307 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_nand.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of NAND HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_NAND_H
+#define __STM32L4xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_fmc.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NAND
+  * @{
+  */ 
+
+/** @addtogroup NAND_Private_Constants
+  * @{
+  */
+
+#define NAND_DEVICE                FMC_BANK3
+#define NAND_WRITE_TIMEOUT         ((uint32_t)1000)
+
+#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
+#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)  
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)  
+#define NAND_CMD_READID            ((uint8_t)0x90)  
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Private_Macros
+  * @{
+  */
+
+/**
+  * @brief  NAND memory address computation.
+  * @param  __ADDRESS__: NAND memory address.
+  * @param  __HANDLE__: NAND handle.
+  * @retval NAND Raw address value
+  */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
+                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
+
+/**
+  * @brief  NAND memory address cycling.
+  * @param  __ADDRESS__: NAND memory address.
+  * @retval NAND address cycling value.
+  */
+#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HAL NAND State structures definition
+  */
+typedef enum
+{
+  HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
+  HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
+  HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
+  HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
+}HAL_NAND_StateTypeDef;
+   
+/** 
+  * @brief  NAND Memory electronic signature Structure definition
+  */
+typedef struct
+{
+  /*<! NAND memory electronic signature maker and device IDs */
+
+  uint8_t Maker_Id; 
+
+  uint8_t Device_Id;
+
+  uint8_t Third_Id;
+
+  uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/** 
+  * @brief  NAND Memory address Structure definition
+  */
+typedef struct 
+{
+  uint16_t Page;   /*!< NAND memory Page address  */
+
+  uint16_t Zone;   /*!< NAND memory Zone address  */
+
+  uint16_t Block;  /*!< NAND memory Block address */
+
+}NAND_AddressTypeDef;
+
+/** 
+  * @brief  NAND Memory info Structure definition
+  */ 
+typedef struct
+{
+  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
+
+  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
+
+  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
+
+  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
+
+  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
+}NAND_InfoTypeDef;
+
+/** 
+  * @brief  NAND handle Structure definition
+  */   
+typedef struct
+{
+  FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
+  
+  FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
+
+  HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
+
+  __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
+
+  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
+}NAND_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
+ * @{
+ */ 
+
+/** @brief Reset NAND handle state.
+  * @param  __HANDLE__: specifies the NAND handle.
+  * @retval None
+  */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+  * @{
+  */
+    
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 
+  * @{
+  */
+
+/* IO operation functions  ****************************************************/
+HAL_StatusTypeDef   HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef   HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef   HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef   HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef   HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef   HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef   HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t            HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t            HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 
+  * @{
+  */
+
+/* NAND Control functions  ****************************************************/
+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+  * @}
+  */
+    
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 
+  * @{
+  */
+
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c
new file mode 100755
index 0000000..1ab593b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c
@@ -0,0 +1,1067 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_nor.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   NOR HAL module driver.
+  *          This file provides a generic firmware to drive NOR memories mounted 
+  *          as external device.
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================       
+    [..]
+      This driver is a generic layered driver which contains a set of APIs used to 
+      control NOR flash memories. It uses the FMC layer functions to interface 
+      with NOR devices. This driver is used as follows:
+    
+      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() 
+          with control and timing parameters for both normal and extended mode.
+            
+      (+) Read NOR flash memory manufacturer code and device IDs using the function
+          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef 
+          structure declared by the function caller. 
+        
+      (+) Access NOR flash memory by read/write data unit operations using the functions
+          HAL_NOR_Read(), HAL_NOR_Program().
+        
+      (+) Perform NOR flash erase block/chip operations using the functions 
+          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+        
+      (+) Read the NOR flash CFI (common flash interface) IDs using the function
+          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+          structure declared by the function caller.
+        
+      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation  
+       
+      (+) You can monitor the NOR device HAL state by calling the function
+          HAL_NOR_GetState() 
+    [..]
+     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+         If a NOR flash device contains different operations and/or implementations, 
+         it should be implemented separately.
+
+     *** NOR HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in NOR HAL driver.
+       
+      (+) NOR_WRITE : NOR memory write data to specified address
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+
+/** @defgroup NOR NOR
+  * @brief NOR HAL module driver
+  * @{
+  */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+  * @{
+  */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Variables NOR Private Variables
+  * @{
+  */
+
+static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+  * @{
+  */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+           ##### NOR Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize
+    the NOR memory
+  
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Perform the NOR memory Initialization sequence.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Timing: pointer to NOR control timing structure 
+  * @param  ExtTiming: pointer to NOR extended mode timing structure    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+  /* Check the NOR handle parameter */
+  if(hnor == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  if(hnor->State == HAL_NOR_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hnor->Lock = HAL_UNLOCKED;
+
+    /* Initialize the low level hardware (MSP) */
+    HAL_NOR_MspInit(hnor);
+  }
+
+  /* Initialize NOR control Interface */
+  FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+  /* Initialize NOR timing Interface */
+  FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); 
+
+  /* Initialize NOR extended mode timing Interface */
+  FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+  /* Enable the NORSRAM device */
+  __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);  
+
+  /* Initialize NOR Memory Data Width*/
+  if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_8B;
+  }
+  else
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_16B;
+  }
+
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY; 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform NOR memory De-Initialization sequence.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)  
+{
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_NOR_MspDeInit(hnor);
+ 
+  /* Configure the NOR registers with their reset values */
+  FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+  
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnor);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the NOR MSP.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval None
+  */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_NOR_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the NOR MSP.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval None
+  */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_NOR_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  NOR MSP Wait for Ready/Busy signal.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Timeout: Maximum timeout value
+  * @retval None
+  */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+  UNUSED(Timeout);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_NOR_MspWait could be implemented in the user file
+   */ 
+}
+  
+/**
+  * @}
+  */
+
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                ##### NOR Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the NOR memory
+  
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Read NOR flash IDs.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_ID : pointer to NOR ID structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+  uint32_t deviceaddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }  
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read ID command */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+
+  /* Read the NOR IDs */
+  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+  pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+  pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+  pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);   
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return the NOR memory to Read mode.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+  uint32_t deviceaddress = 0;  
+  
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }  
+  
+  NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);   
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read data from NOR memory.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress: pointer to Device address
+  * @param  pData : pointer to read data  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+  uint32_t deviceaddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  } 
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read data command */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
+  NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
+
+  /* Read the data */
+  *pData = *(__IO uint32_t *)(uint32_t)pAddress;
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Program data to NOR memory.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress: Device address
+  * @param  pData : pointer to the data to write   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+  uint32_t deviceaddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  } 
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send program data command */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+
+  /* Write the data */
+  NOR_WRITE(pAddress, *pData);
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Read a block of data from the FMC NOR memory.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  uwAddress: NOR memory internal address to read from.
+  * @param  pData: pointer to the buffer that receives the data read from the 
+  *         NOR memory.
+  * @param  uwBufferSize : number of Half word to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+  uint32_t deviceaddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }  
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read data command */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
+  NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
+  
+  /* Read buffer */
+  while( uwBufferSize > 0) 
+  {
+    *pData++ = *(__IO uint16_t *)uwAddress;
+    uwAddress += 2;
+    uwBufferSize--;
+  } 
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Write a half-word buffer to the FMC NOR memory. This function 
+  *         must be used only with S29GL128P NOR memory. 
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  uwAddress: NOR memory internal address from which the data 
+  * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to 
+  *          64 bytes boundary for example).
+  * @param  pData: pointer to source data buffer. 
+  * @param  uwBufferSize: number of Half words to write. 
+  * @note   The maximum buffer size allowed is NOR memory dependent
+  *         (can be 64 Bytes max for example).
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+  uint16_t * p_currentaddress = (uint16_t *)NULL;
+  uint16_t * p_endaddress = (uint16_t *)NULL;
+  uint32_t lastloadedaddress = 0, deviceaddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }  
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Initialize variables */
+  p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
+  p_endaddress      = p_currentaddress + (uwBufferSize-1);
+  lastloadedaddress = (uint32_t)(uwAddress);
+
+  /* Issue unlock command sequence */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); 
+
+  /* Write Buffer Load Command */
+  NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); 
+  NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); 
+
+  /* Load Data into NOR Buffer */
+  while(p_currentaddress <= p_endaddress)
+  {
+    /* Store last loaded address & data value (for polling) */
+    lastloadedaddress = (uint32_t)p_currentaddress;
+ 
+    NOR_WRITE(p_currentaddress, *pData++);
+    
+    p_currentaddress++;
+  }
+
+  NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); 
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK; 
+  
+}
+
+/**
+  * @brief  Erase the specified block of the NOR memory.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  BlockAddress : Block to erase address 
+  * @param  Address: Device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+  uint32_t deviceaddress = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send block erase command sequence */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+  NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+
+  /* Check the NOR memory status and update the controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+    
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;
+ 
+}
+
+/**
+  * @brief  Erase the entire NOR chip.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Address : Device address  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+  uint32_t deviceaddress = 0;
+  
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Address);
+
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;  
+    
+  /* Send NOR chip erase command sequence */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);  
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+  
+  /* Check the NOR memory status and update the controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+    
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Read NOR flash CFI IDs.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_CFI : pointer to NOR CFI IDs structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+  uint32_t deviceaddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }  
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read CFI query command */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+  /* read the NOR CFI information */
+  pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+  pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+  pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+  pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### NOR Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the NOR interface.
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enable dynamically NOR write operation.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+
+  /* Enable write operation */
+  FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); 
+  
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disable dynamically NOR write operation.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+
+  /* Update the SRAM controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+    
+  /* Disable write operation */
+  FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); 
+  
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_PROTECTED;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */  
+  
+/** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### NOR State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the NOR controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Return the NOR controller handle state.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval NOR controller state
+  */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+{
+  /* Return NOR handle state */
+  return hnor->State;
+}
+
+/**
+  * @brief  Return the NOR operation status.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.   
+  * @param  Address: Device address
+  * @param  Timeout: NOR programming Timeout
+  * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+  *         or HAL_NOR_STATUS_TIMEOUT
+  */
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{ 
+  HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+  uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
+  uint32_t tickstart = 0;
+
+  /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+  HAL_NOR_MspWait(hnor, Timeout);
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        status = HAL_NOR_STATUS_TIMEOUT; 
+      } 
+    } 
+
+    /* Read NOR status register (DQ6 and DQ5) */
+    tmp_sr1 = *(__IO uint16_t *)Address;
+    tmp_sr2 = *(__IO uint16_t *)Address;
+
+    /* If DQ6 did not toggle between the two reads then return NOR_Success */
+    if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) 
+    {
+      return HAL_NOR_STATUS_SUCCESS;
+    }
+    
+    if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
+    {
+      status = HAL_NOR_STATUS_ONGOING;
+    }
+    
+    tmp_sr1 = *(__IO uint16_t *)Address;
+    tmp_sr2 = *(__IO uint16_t *)Address;
+
+    /* If DQ6 did not toggle between the two reads then return NOR_Success */
+    if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) 
+    {
+      return HAL_NOR_STATUS_SUCCESS;
+    }
+    else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+    {
+      return HAL_NOR_STATUS_ERROR;
+    } 
+  }
+
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h
new file mode 100755
index 0000000..9749c3a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h
@@ -0,0 +1,303 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_nor.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of NOR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_NOR_H
+#define __STM32L4xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_fmc.h"
+
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NOR
+  * @{
+  */ 
+
+/** @addtogroup NOR_Private_Constants
+  * @{
+  */
+
+/* NOR device IDs addresses */
+#define MC_ADDRESS               ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS             ((uint16_t)0x10)
+#define CFI2_ADDRESS             ((uint16_t)0x11)
+#define CFI3_ADDRESS             ((uint16_t)0x12)
+#define CFI4_ADDRESS             ((uint16_t)0x13)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B            ((uint8_t)0x0)
+#define NOR_MEMORY_16B           ((uint8_t)0x1)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1       FMC_BANK1_1
+#define NOR_MEMORY_ADRESS2       FMC_BANK1_2
+#define NOR_MEMORY_ADRESS3       FMC_BANK1_3
+#define NOR_MEMORY_ADRESS4       FMC_BANK1_4
+
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Private_Macros
+  * @{
+  */
+
+/**
+  * @brief  NOR memory address shifting.
+  * @param  __NOR_ADDRESS: NOR base address 
+  * @param  __NOR_MEMORY_WIDTH_: NOR memory width
+  * @param  __ADDRESS__: NOR memory address 
+  * @retval NOR shifted address value
+  */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
+            ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
+              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
+              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+  * @brief  NOR memory write data to specified address.
+  * @param  __ADDRESS__: NOR memory address 
+  * @param  __DATA__: Data to write
+  * @retval None
+  */
+#define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HAL SRAM State structures definition  
+  */ 
+typedef enum
+{  
+  HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
+  HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
+  HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
+  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
+  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
+}HAL_NOR_StateTypeDef;
+
+/**
+  * @brief  FMC NOR Status typedef
+  */
+typedef enum
+{
+  HAL_NOR_STATUS_SUCCESS = 0,
+  HAL_NOR_STATUS_ONGOING,
+  HAL_NOR_STATUS_ERROR,
+  HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef; 
+
+/**
+  * @brief  FMC NOR ID typedef
+  */
+typedef struct
+{
+  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
+
+  uint16_t Device_Code1;
+
+  uint16_t Device_Code2;
+
+  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. 
+                                    These codes can be accessed by performing read operations with specific 
+                                    control signals and addresses set.They can also be accessed by issuing 
+                                    an Auto Select command.                                                   */    
+}NOR_IDTypeDef;
+
+/**
+  * @brief  FMC NOR CFI typedef
+  */
+typedef struct
+{
+  uint16_t CFI_1;
+
+  uint16_t CFI_2;
+
+  uint16_t CFI_3;
+
+  uint16_t CFI_4;  /*!< Defines the information stored in the memory's Common flash interface
+                        which contains a description of various electrical and timing parameters, 
+                        density information and functions supported by the memory.                   */
+}NOR_CFITypeDef;
+
+/** 
+  * @brief  NOR handle Structure definition
+  */ 
+typedef struct
+{
+  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
+
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
+
+  FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
+
+  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
+
+  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
+
+}NOR_HandleTypeDef; 
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+  * @{
+  */
+
+/** @brief Reset NOR handle state.
+  * @param  __HANDLE__: NOR handle
+  * @retval None
+  */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+  * @{
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions 
+  * @{
+  */
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions 
+  * @{
+  */
+
+/* NOR Control functions  *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/**
+  * @}
+  */  
+  
+/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions 
+  * @{
+  */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c
new file mode 100755
index 0000000..330f519
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c
@@ -0,0 +1,994 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_opamp.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   OPAMP HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the operational amplifier(s) peripheral: 
+  *           + OPAMP configuration
+  *           + OPAMP calibration
+  *          Thanks to
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *         
+  @verbatim
+================================================================================
+          ##### OPAMP Peripheral Features #####
+================================================================================
+           
+  [..] The device integrates 1 or 2 operational amplifiers OPAMP1 & OPAMP2
+       
+       (#) The OPAMP(s) provide(s) several exclusive running modes.       
+       (++) 1 OPAMP: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx
+       (++) 2 OPAMP: STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx
+
+       (#) The OPAMP(s) provide(s) several exclusive running modes.
+       (++) Standalone mode
+       (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
+       (++) Follower mode
+
+       (#) All OPAMP (same for all OPAMPs) can operate in
+       (++) Either Low range (VDDA < 2.4V) power supply
+       (++) Or High range (VDDA > 2.4V) power supply
+
+       (#) Each OPAMP(s) can be configured in normal and low power mode.
+
+       (#) The OPAMP(s) provide(s) calibration capabilities.  
+       (++) Calibration aims at correcting some offset for running mode.
+       (++) The OPAMP uses either factory calibration settings OR user defined 
+           calibration (trimming) settings (i.e. trimming mode).
+       (++) The user defined settings can be figured out using self calibration 
+           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
+       (++) HAL_OPAMP_SelfCalibrate:
+       (+++) Runs automatically the calibration.
+       (+++) Enables the user trimming mode
+       (+++) Updates the init structure with trimming values with fresh calibration 
+            results. 
+            The user may store the calibration results for larger 
+            (ex monitoring the trimming as a function of temperature 
+            for instance)
+       (+++) HAL_OPAMPEx_SelfCalibrateAll
+            runs calibration of all OPAMPs in parallel to save search time.
+                    
+       (#) Running mode: Standalone mode 
+       (++) Gain is set externally (gain depends on external loads).
+       (++) Follower mode also possible externally by connecting the inverting input to
+           the output.
+       
+       (#) Running mode: Follower mode
+       (++) No Inverting Input is connected.
+       
+       (#) Running mode: Programmable Gain Amplifier (PGA) mode 
+           (Resistor feedback output)
+       (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
+           output.
+       (++) OPAMP gain is either 2, 4, 8 or 16.
+        
+       (#) The OPAMPs inverting input can be selected according to the Reference Manual 
+           "OPAMP function description" chapter.
+       
+       (#) The OPAMPs non inverting input can be selected according to the Reference Manual 
+           "OPAMP function description" chapter.
+       
+      
+            ##### How to use this driver #####
+================================================================================
+  [..] 
+
+    *** Power supply range ***
+    ============================================
+    [..] To run in low power mode:
+
+      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
+      (++) Select OPAMP_POWERSUPPLY_LOW (VDDA lower than 2.4V)
+      (++) Otherwise select OPAMP_POWERSUPPLY_HIGH (VDDA higher than 2.4V)
+
+    *** Low / normal power mode ***
+    ============================================
+    [..] To run in low power mode:
+
+      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
+      (++) Select OPAMP_POWERMODE_LOWPOWER
+      (++) Otherwise select OPAMP_POWERMODE_NORMAL
+
+    *** Calibration ***
+    ============================================
+    [..] To run the OPAMP calibration self calibration:
+
+      (#) Start calibration using HAL_OPAMP_SelfCalibrate. 
+           Store the calibration results.
+
+    *** Running mode ***
+    ============================================
+      
+    [..] To use the OPAMP, perform the following steps:
+            
+      (#) Fill in the HAL_OPAMP_MspInit() to
+      (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
+      (++) Configure the OPAMP input AND output in analog mode using 
+           HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
+  
+      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
+      (++) Select the mode
+      (++) Select the inverting input
+      (++) Select the non-inverting input 
+      (++) If PGA mode is enabled, Select if inverting input is connected.
+      (++) Select either factory or user defined trimming mode.
+      (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
+          (typically values set by HAL_OPAMP_SelfCalibrate function).
+      
+      (#) Enable the OPAMP using HAL_OPAMP_Start() function.
+           
+      (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
+      
+      (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
+          Caution: On STM32L4, HAL OPAMP lock is software lock only (not 
+          hardware lock as on some other STM32 devices)
+
+      (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
+
+    *** Running mode: change of configuration while OPAMP ON  ***
+    ============================================
+    [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
+      (#) If needed, fill in the HAL_OPAMP_MspInit()
+      (++) This is the case for instance if you wish to use new OPAMP I/O
+
+      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
+      (++) As in configure case, select first the parameters you wish to modify.
+      
+      (#) Change from low power mode to normal power mode (& vice versa) requires  
+          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). 
+          In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
+          alone.
+
+  @endverbatim
+  ******************************************************************************
+
+      Table 1.  OPAMPs inverting/non-inverting inputs for the STM32L4 devices:
+      +------------------------------------------------------------------------|     
+      |                 |         | OPAMP1               | OPAMP2              |
+      |-----------------|---------|----------------------|---------------------|
+      | Inverting Input | VM_SEL  |                      |                     |
+      |                 |         |  IO0-> PA1           | IO0-> PA7           |
+      |                 |         |  LOW LEAKAGE IO (2)  | LOW LEAKAGE IO (2)  |
+      |                 |         |  Not connected       | Not connected       |
+      | (1)             |         |    PGA mode only     |   PGA mode only     |
+      |-----------------|---------|----------------------|---------------------|
+      |  Non Inverting  | VP_SEL  |                      |                     |
+      |                 |         |  IO0-> PA0 (GPIO)    | IO0-> PA6  (GPIO)   |
+      |    Input        |         |  DAC1_OUT1 internal  | DAC1_OUT2 internal  |
+      +------------------------------------------------------------------------|
+       (1): NA in follower mode.
+       (2): Available on some package only (ex. BGA132).
+           
+           
+      Table 2.  OPAMPs outputs for the STM32L4 devices:
+
+      +-------------------------------------------------------------------------     
+      |                 |        | OPAMP1                | OPAMP2              |
+      |-----------------|--------|-----------------------|---------------------|
+      | Output          |  VOUT  |  PA3                  |  PB0                |
+      |                 |        |  & (1) ADC12_IN if    | & (1) ADC12_IN if   |
+      |                 |        |  connected internally | connected internally|
+      |-----------------|--------|-----------------------|---------------------|
+       (1): ADC1 or ADC2 shall select IN15.
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+    
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup OPAMP OPAMP
+  * @brief OPAMP module driver
+  * @{
+  */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup OPAMP_Private_Constants
+  * @{
+  */
+
+/* CSR register reset value */ 
+#define OPAMP_CSR_RESET_VALUE             ((uint32_t)0x00000000)
+
+#define OPAMP_CSR_RESET_BITS    (OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE \
+                               | OPAMP_CSR_PGGAIN | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL \
+                               | OPAMP_CSR_CALON | OPAMP_CSR_USERTRIM)
+
+/* CSR Init masks */
+#define OPAMP_CSR_INIT_MASK_PGA (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_PGGAIN \
+                               | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)
+
+#define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VPSEL \
+                                    | OPAMP_CSR_USERTRIM)
+
+#define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VPSEL \
+                                      | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)
+
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+  * @{
+  */
+
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the OPAMP according to the specified
+  *         parameters in the OPAMP_InitTypeDef and initialize the associated handle.
+  * @note   If the selected opamp is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  hopamp: OPAMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
+{ 
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t updateotrlpotr = 0;
+
+  /* Check the OPAMP handle allocation and lock status */
+  /* Init not allowed if calibration is ongoing */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
+                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+       
+    /* Set OPAMP parameters */
+    assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange));
+    assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
+    assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
+    assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
+    
+    if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
+    {
+      assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
+    }
+
+    if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)      
+    {
+      assert_param(IS_OPAMP_INVERTING_INPUT_PGA(hopamp->Init.InvertingInput));
+    }
+    
+    if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
+    {
+      assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
+    }
+    
+    assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); 
+    if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
+    {
+      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+      {
+        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
+        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
+      }
+    else
+      {
+        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower));
+        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower));
+      }
+    }
+     
+    if(hopamp->State == HAL_OPAMP_STATE_RESET)
+    {
+      /* Allocate lock resource and initialize it */
+      hopamp->Lock = HAL_UNLOCKED;
+    }
+
+    /* Call MSP init function */
+    HAL_OPAMP_MspInit(hopamp);
+
+    /* Set operating mode */
+    CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
+                                              
+    if (hopamp->Init.Mode == OPAMP_PGA_MODE)
+    {
+      MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
+                                        hopamp->Init.PowerMode | \
+                                        hopamp->Init.Mode | \
+                                        hopamp->Init.PgaGain | \
+                                        hopamp->Init.InvertingInput    | \
+                                        hopamp->Init.NonInvertingInput | \
+                                        hopamp->Init.UserTrimming);
+    }
+    
+    if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
+    {
+    /* In Follower mode InvertingInput is Not Applicable  */
+    MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \
+                                        hopamp->Init.PowerMode | \
+                                        hopamp->Init.Mode | \
+                                        hopamp->Init.NonInvertingInput | \
+                                        hopamp->Init.UserTrimming);     
+    }     
+    
+    if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
+    {
+      MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
+                                        hopamp->Init.PowerMode | \
+                                        hopamp->Init.Mode | \
+                                        hopamp->Init.InvertingInput    | \
+                                        hopamp->Init.NonInvertingInput | \
+                                        hopamp->Init.UserTrimming);
+    } 
+    
+    if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
+    {
+      /* Set power mode and associated calibration parameters */
+      if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
+      {
+        /* OPAMP_POWERMODE_NORMAL */
+        /* Set calibration mode (factory or user) and values for            */
+        /* transistors differential pair high (PMOS) and low (NMOS) for     */
+        /* normal mode.                                                     */
+        updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
+                         | (hopamp->Init.TrimmingValueN)); 
+        MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
+      }
+      else
+      {
+        /* OPAMP_POWERMODE_LOWPOWER */
+        /* transistors differential pair high (PMOS) and low (NMOS) for     */
+        /* low power mode.                                                     */
+        updateotrlpotr = (((hopamp->Init.TrimmingValuePLowPower) << (OPAMP_INPUT_NONINVERTING)) \
+                         | (hopamp->Init.TrimmingValueNLowPower)); 
+        MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);     
+      }
+    } 
+
+    /* Configure the power supply range */
+    /* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */
+    /* bit OPAMP1_CSR_OPARANGE is used for both OPAMPs */
+    MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, hopamp->Init.PowerSupplyRange);
+    
+    /* Update the OPAMP state*/
+    if (hopamp->State == HAL_OPAMP_STATE_RESET)
+    {
+      /* From RESET state to READY State */
+      hopamp->State = HAL_OPAMP_STATE_READY;
+    }
+    /* else: remain in READY or BUSY state (no update) */
+    return status;
+  }
+}
+
+/**
+  * @brief  DeInitialize the OPAMP peripheral.
+  * @note   Deinitialization can be performed if the OPAMP configuration is locked.
+  *         (the lock is SW in L4)
+  * @param  hopamp: OPAMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the OPAMP handle allocation */
+  /* DeInit not allowed if calibration is ongoing */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+    /* Set OPAMP_CSR register to reset value */
+    /* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */ 
+    /* OPAMP shall be disabled first separately */     
+    CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+    MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE);
+    
+    /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
+    HAL_OPAMP_MspDeInit(hopamp);
+
+    /* Update the OPAMP state*/
+    hopamp->State = HAL_OPAMP_STATE_RESET;   
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hopamp);
+  }
+  
+  return status;
+}
+
+
+/**
+  * @brief  Initialize the OPAMP MSP.
+  * @param  hopamp: OPAMP handle
+  * @retval None
+  */
+__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hopamp);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize OPAMP MSP.
+  * @param  hopamp: OPAMP handle
+  * @retval None
+  */
+__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hopamp);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions 
+ *  @brief   IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                        ##### IO operation functions #####
+ =============================================================================== 
+    [..]
+    This subsection provides a set of functions allowing to manage the OPAMP
+    start, stop and calibration actions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the OPAMP.
+  * @param  hopamp: OPAMP handle
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
+{ 
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the OPAMP handle allocation */
+  /* Check if OPAMP locked */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+    
+    if(hopamp->State == HAL_OPAMP_STATE_READY)
+    {
+      /* Enable the selected opamp */
+      SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+      /* Update the OPAMP state*/     
+      /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
+      hopamp->State = HAL_OPAMP_STATE_BUSY;   
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+    
+   }
+  return status;
+}
+
+/**
+  * @brief  Stop the OPAMP.
+  * @param  hopamp: OPAMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
+{ 
+  HAL_StatusTypeDef status = HAL_OK;
+    
+  /* Check the OPAMP handle allocation */
+  /* Check if OPAMP locked */
+  /* Check if OPAMP calibration ongoing */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
+                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))  
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+    if(hopamp->State == HAL_OPAMP_STATE_BUSY)
+    {
+      /* Disable the selected opamp */
+      CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); 
+    
+      /* Update the OPAMP state*/     
+      /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
+      hopamp->State = HAL_OPAMP_STATE_READY;
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Run the self calibration of one OPAMP.
+  * @note   Calibration is performed in the mode specified in OPAMP init
+  *         structure (mode normal or low-power). To perform calibration for
+  *         both modes, repeat this function twice after OPAMP init structure
+  *         accordingly updated.
+  * @note   Calibration runs about 10 ms.
+  * @param  hopamp handle
+  * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
+  * @retval HAL status
+
+  */
+
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
+{ 
+
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  uint32_t trimmingvaluen = 0;
+  uint32_t trimmingvaluep = 0;
+  uint32_t delta;
+  uint32_t opampmode;
+  
+  __IO uint32_t* tmp_opamp_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */
+    
+  /* Check the OPAMP handle allocation */
+  /* Check if OPAMP locked */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check if OPAMP in calibration mode and calibration not yet enable */
+    if(hopamp->State ==  HAL_OPAMP_STATE_READY)
+    {
+      /* Check the parameter */
+      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+      assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
+
+      /* Save OPAMP mode as in                                       */
+      /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
+      /* the calibration is not working in PGA mode                  */
+      opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_OPAMODE);
+      
+      /* Use of standalone mode */ 
+      MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); 
+
+      /*  user trimming values are used for offset calibration */
+      SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
+      
+      /* Select trimming settings depending on power mode */
+      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+      {
+        tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
+      }
+      else
+      {
+        tmp_opamp_reg_trimming = &hopamp->Instance->LPOTR;
+      }
+      
+      /* Enable calibration */
+      SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
+  
+      /* 1st calibration - N */
+      CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
+      
+      /* Enable the selected opamp */
+      SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+      
+      /* Init trimming counter */    
+      /* Medium value */
+      trimmingvaluen = 16; 
+      delta = 8;
+           
+      while (delta != 0)
+      {
+        /* Set candidate trimming */
+        /* OPAMP_POWERMODE_NORMAL */
+        MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
+        
+        /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+        /* Offset trim time: during calibration, minimum time needed between */
+        /* two steps to have 1 mV accuracy */
+        HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+        if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
+        { 
+          /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+          trimmingvaluen -= delta;
+        }
+        else
+        {
+          /* OPAMP_CSR_CALOUT is LOW try lower trimming */
+          trimmingvaluen += delta;
+        }
+        /* Divide range by 2 to continue dichotomy sweep */       
+        delta >>= 1;
+      }
+
+      /* Still need to check if right calibration is current value or one step below */
+      /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1  */
+      /* Set candidate trimming */
+      MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
+           
+      /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+      /* Offset trim time: during calibration, minimum time needed between */
+      /* two steps to have 1 mV accuracy */
+      HAL_Delay(OPAMP_TRIMMING_DELAY);
+      
+      if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0)
+      { 
+        /* Trimming value is actually one value more */
+        trimmingvaluen++;
+        /* Set right trimming */
+        MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
+      }
+
+      /* 2nd calibration - P */
+      SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
+      
+      /* Init trimming counter */    
+      /* Medium value */
+      trimmingvaluep = 16; 
+      delta = 8;
+      
+      while (delta != 0)
+      {
+        /* Set candidate trimming */
+        /* OPAMP_POWERMODE_NORMAL */
+        MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
+
+        /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+        /* Offset trim time: during calibration, minimum time needed between */
+        /* two steps to have 1 mV accuracy */
+        HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+        if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
+        { 
+          /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+          trimmingvaluep += delta;
+        }
+        else
+        {
+          /* OPAMP_CSR_CALOUT  is LOW try lower trimming */
+          trimmingvaluep -= delta;
+        }
+        
+        /* Divide range by 2 to continue dichotomy sweep */
+        delta >>= 1;
+      }
+      
+      /* Still need to check if right calibration is current value or one step below */
+      /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
+      /* Set candidate trimming */
+      MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
+
+      /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+      /* Offset trim time: during calibration, minimum time needed between */
+      /* two steps to have 1 mV accuracy */
+      HAL_Delay(OPAMP_TRIMMING_DELAY);
+      
+      if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
+      {
+        /* Trimming value is actually one value more */
+        trimmingvaluep++;
+        MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
+      }
+      
+      /* Disable the OPAMP */
+      CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+      
+      /* Disable calibration & set normal mode (operating mode) */
+      CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
+                 
+      /* Self calibration is successful  */
+      /* Store calibration(user trimming) results in init structure. */
+
+      /* Set user trimming mode */  
+      hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+      /* Affect calibration parameters depending on mode normal/low power */
+      if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
+      {
+        /* Write calibration result N */
+        hopamp->Init.TrimmingValueN = trimmingvaluen;
+        /* Write calibration result P */
+        hopamp->Init.TrimmingValueP = trimmingvaluep;
+      }
+      else
+      {
+        /* Write calibration result N */
+        hopamp->Init.TrimmingValueNLowPower = trimmingvaluen;
+        /* Write calibration result P */
+        hopamp->Init.TrimmingValuePLowPower = trimmingvaluep;
+      }
+    
+    /* Restore OPAMP mode after calibration */
+    MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode);
+    }
+    else
+    {
+      /* OPAMP can not be calibrated from this mode */ 
+      status = HAL_ERROR;
+    }   
+  }
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ =============================================================================== 
+    [..]
+    This subsection provides a set of functions allowing to control the OPAMP data 
+    transfers.
+
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected OPAMP configuration.
+  * @note   On STM32L4, HAL OPAMP lock is software lock only (in 
+  *         contrast of hardware lock available on some other STM32 
+  *         devices).
+  * @param  hopamp: OPAMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the OPAMP handle allocation */
+  /* Check if OPAMP locked */
+  /* OPAMP can be locked when enabled and running in normal mode */ 
+  /*   It is meaningless otherwise */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
+                      || (hopamp->State == HAL_OPAMP_STATE_READY) \
+                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
+                      || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+  
+  {
+    status = HAL_ERROR;
+  }
+  
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+    
+   /* OPAMP state changed to locked */
+    hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
+  }
+  return status; 
+}
+
+/**
+  * @brief  Return the OPAMP factory trimming value.
+  * @note            On STM32L4 OPAMP, user can retrieve factory trimming if 
+  *                  OPAMP has never been set to user trimming before.
+  *                  Therefore, this function must be called when OPAMP init  
+  *                  parameter "UserTrimming" is set to trimming factory, 
+  *                  and before OPAMP  calibration (function 
+  *                  "HAL_OPAMP_SelfCalibrate()").
+  *                  Otherwise, factory trimming value cannot be retrieved and 
+  *                  error status is returned.
+  * @param  hopamp : OPAMP handle
+  * @param  trimmingoffset : Trimming offset (P or N)
+  *         This parameter must be a value of @ref OPAMP_FactoryTrimming
+  * @note   Calibration parameter retrieved is corresponding to the mode 
+  *         specified in OPAMP init structure (mode normal or low-power). 
+  *         To retrieve calibration parameters for both modes, repeat this 
+  *         function after OPAMP init structure accordingly updated.
+  * @retval Trimming value (P or N): range: 0->31
+  *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
+  *
+  */
+
+HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
+{
+  HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
+  __IO uint32_t* tmp_opamp_reg_trimming;  /* Selection of register of trimming depending on power mode: OTR or LPOTR */
+  
+  /* Check the OPAMP handle allocation */
+  /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
+                      || (hopamp->State == HAL_OPAMP_STATE_BUSY) \
+                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
+                      || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+  {
+    return OPAMP_FACTORYTRIMMING_DUMMY;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+    assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
+    assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
+    
+    /* Check the trimming mode */
+    if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM) != RESET)
+    {
+      /* This function must called when OPAMP init parameter "UserTrimming"   */
+      /* is set to trimming factory, and before OPAMP calibration (function   */
+      /* "HAL_OPAMP_SelfCalibrate()").                                        */
+      /* Otherwise, factory trimming value cannot be retrieved and error       */
+      /* status is returned.                                                  */
+      trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
+    }
+    else
+    {
+      /* Select trimming settings depending on power mode */
+      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+      {
+        tmp_opamp_reg_trimming = &OPAMP->OTR;
+      }
+      else
+      {
+        tmp_opamp_reg_trimming = &OPAMP->LPOTR;
+      }      
+    
+      /* Get factory trimming  */
+      if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
+      {
+        /* OPAMP_FACTORYTRIMMING_P */
+        trimmingvalue = ((*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
+      }
+      else
+      {
+        /* OPAMP_FACTORYTRIMMING_N */
+        trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN;
+      }
+    }
+  }  
+  return trimmingvalue;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ =============================================================================== 
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the OPAMP handle state.
+  * @param  hopamp : OPAMP handle
+  * @retval HAL state
+  */
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
+{
+  /* Check the OPAMP handle allocation */
+  if(hopamp == NULL)
+  {
+    return HAL_OPAMP_STATE_RESET;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+  /* Return OPAMP handle state */
+  return hopamp->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+  /**
+  * @}
+  */ 
+  
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h
new file mode 100755
index 0000000..0a664cc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h
@@ -0,0 +1,425 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_opamp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of OPAMP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_OPAMP_H
+#define __STM32L4xx_HAL_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+                  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup OPAMP
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  OPAMP Init structure definition  
+  */
+  
+typedef struct
+{
+  uint32_t PowerSupplyRange;            /*!< Specifies the power supply range: above or under 2.4V.
+                                             This parameter must be a value of @ref OPAMP_PowerSupplyRange
+                                             Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */
+
+  uint32_t PowerMode;                   /*!< Specifies the power mode Normal or Low-Power.
+                                             This parameter must be a value of @ref OPAMP_PowerMode */
+  
+  uint32_t Mode;                        /*!< Specifies the OPAMP mode
+                                             This parameter must be a value of @ref OPAMP_Mode 
+                                             mode is either Standalone, - Follower or PGA */
+                                    
+  uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & PGA modes
+                                               - In Standalone mode:   i.e. when mode is OPAMP_STANDALONE_MODE
+                                                 & PGA mode:           i.e. when mode is OPAMP_PGA_MODE
+                                                 This parameter must be a value of @ref OPAMP_InvertingInput 
+                                               - In Follower mode    i.e. when mode is OPAMP_FOLLOWER_MODE
+                                                 This parameter is Not Applicable */ 
+
+  uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp: 
+                                             This parameter must be a value of @ref OPAMP_NonInvertingInput */                                   
+  
+  uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode 
+                                             i.e. when mode is OPAMP_PGA_MODE. 
+                                             This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */
+ 
+  uint32_t UserTrimming;                /*!< Specifies the trimming mode 
+                                             This parameter must be a value of @ref OPAMP_UserTrimming 
+                                             UserTrimming is either factory or user trimming.*/
+                                                                                                                            
+  uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31 
+                                             16 is typical default value */
+                                        
+  uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31 
+                                             16 is typical default value */
+  
+  uint32_t TrimmingValuePLowPower;      /*!< Specifies the offset trimming value (PMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31  
+                                             16 is typical default value */
+
+  uint32_t TrimmingValueNLowPower;      /*!< Specifies the offset trimming value (NMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31  
+                                             16 is typical default value */
+
+}OPAMP_InitTypeDef;
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+
+typedef enum
+{
+  HAL_OPAMP_STATE_RESET               = 0x00000000, /*!< OPAMP is not yet Initialized          */
+  
+  HAL_OPAMP_STATE_READY               = 0x00000001, /*!< OPAMP is initialized and ready for use */
+  HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
+ 
+  HAL_OPAMP_STATE_BUSY                = 0x00000004, /*!< OPAMP is enabled and running in normal mode */                                                                           
+  HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005  /*!< OPAMP is locked
+                                                         only system reset allows reconfiguring the opamp. */
+    
+}HAL_OPAMP_StateTypeDef;
+
+/** 
+  * @brief OPAMP Handle Structure definition
+  */ 
+typedef struct
+{
+  OPAMP_TypeDef       *Instance;                    /*!< OPAMP instance's registers base address   */
+  OPAMP_InitTypeDef   Init;                         /*!< OPAMP required parameters */
+  HAL_StatusTypeDef Status;                         /*!< OPAMP peripheral status   */
+  HAL_LockTypeDef   Lock;                           /*!< Locking object          */
+  __IO HAL_OPAMP_StateTypeDef  State;               /*!< OPAMP communication state */
+  
+} OPAMP_HandleTypeDef;
+
+/** 
+  * @brief HAl_OPAMP_TrimmingValueTypeDef definition 
+  */ 
+
+typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
+  * @{
+  */      
+
+/** @defgroup OPAMP_Mode OPAMP Mode
+  * @{
+  */
+#define OPAMP_STANDALONE_MODE            ((uint32_t)0x00000000) /*!< standalone mode */
+#define OPAMP_PGA_MODE                   OPAMP_CSR_OPAMODE_1    /*!< PGA mode */
+#define OPAMP_FOLLOWER_MODE              OPAMP_CSR_OPAMODE      /*!< follower mode */
+    
+/**
+  * @}
+  */                                        
+                                                                             
+/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_IO0        ((uint32_t)0x00000000)  /*!< OPAMP non-inverting input connected to dedicated IO pin */
+#define OPAMP_NONINVERTINGINPUT_DAC_CH      OPAMP_CSR_VPSEL        /*!< OPAMP non-inverting input connected internally to DAC channel */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
+  * @{
+  */
+
+#define OPAMP_INVERTINGINPUT_IO0              ((uint32_t)0x00000000)  /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */
+#define OPAMP_INVERTINGINPUT_IO1              OPAMP_CSR_VMSEL_0       /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */
+#define OPAMP_INVERTINGINPUT_CONNECT_NO       OPAMP_CSR_VMSEL_1       /*!< OPAMP inverting input not connected externally (PGA mode only) */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
+  * @{
+  */
+
+#define OPAMP_PGA_GAIN_2                ((uint32_t)0x00000000)                        /*!< PGA gain =  2 */
+#define OPAMP_PGA_GAIN_4                OPAMP_CSR_PGGAIN_0                            /*!< PGA gain =  4 */
+#define OPAMP_PGA_GAIN_8                OPAMP_CSR_PGGAIN_1                            /*!< PGA gain =  8 */
+#define OPAMP_PGA_GAIN_16              (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)      /*!< PGA gain = 16 */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_PowerMode OPAMP PowerMode
+  * @{
+  */
+#define OPAMP_POWERMODE_NORMAL        ((uint32_t)0x00000000)
+#define OPAMP_POWERMODE_LOWPOWER      OPAMP_CSR_OPALPM
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
+  * @{
+  */
+#define OPAMP_POWERSUPPLY_LOW          ((uint32_t)0x00000000)  /*!< Power supply range low (VDDA lower than 2.4V) */
+#define OPAMP_POWERSUPPLY_HIGH         OPAMP1_CSR_OPARANGE     /*!< Power supply range high (VDDA higher than 2.4V) */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
+  * @{
+  */
+#define OPAMP_TRIMMING_FACTORY        ((uint32_t)0x00000000)                          /*!< Factory trimming */
+#define OPAMP_TRIMMING_USER           OPAMP_CSR_USERTRIM                              /*!< User trimming */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
+  * @{
+  */
+#define OPAMP_FACTORYTRIMMING_DUMMY    ((uint32_t)0xFFFFFFFF)                           /*!< Dummy value if trimming value could not be retrieved */
+
+#define OPAMP_FACTORYTRIMMING_N        ((uint32_t)0x00000000)                          /*!< Offset trimming N */
+#define OPAMP_FACTORYTRIMMING_P        ((uint32_t)0x00000001)                          /*!< Offset trimming P */
+
+/**
+  * @}
+  */           
+
+ /**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
+  * @brief   OPAMP Private constants and defines
+  * @{
+  */
+
+/* NONINVERTING bit position in OTR & LPOTR */ 
+#define OPAMP_INPUT_NONINVERTING              ((uint32_t) 8) /*!< Non inverting input */  
+
+/* Offset trimming time: during calibration, minimum time needed between two  */
+/* steps to have 1 mV accuracy.                                               */
+/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/
+/* Unit: ms.                                                                  */
+#define OPAMP_TRIMMING_DELAY               ((uint32_t) 1)
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
+  * @{
+  */
+
+/** @brief Reset OPAMP handle state.
+  * @param  __HANDLE__: OPAMP handle.
+  * @retval None
+  */
+#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
+
+/**
+  * @}
+  */ 
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup OPAMP_Private_Macros OPAMP Private Macros
+  * @{
+  */
+
+#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
+                                               ((INPUT) == OPAMP_PGA_MODE) || \
+                                               ((INPUT) == OPAMP_FOLLOWER_MODE))
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+
+#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+                                                    ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
+#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx)  || defined (STM32L442xx)  || defined (STM32L443xx) || defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx) 
+#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0)
+#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */
+
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
+                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+                                             ((INPUT) == OPAMP_INVERTINGINPUT_IO1)|| \
+                                             ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
+#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx)  || defined (STM32L442xx)  || defined (STM32L443xx) || defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx) 
+#define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+                                             ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
+#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */
+
+#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
+                                 ((GAIN) == OPAMP_PGA_GAIN_4) || \
+                                 ((GAIN) == OPAMP_PGA_GAIN_8) || \
+                                 ((GAIN) == OPAMP_PGA_GAIN_16))
+
+#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
+                                      ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) )
+
+#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \
+                                            ((RANGE) == OPAMP_POWERSUPPLY_HIGH)  )
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
+                                     ((TRIMMING) == OPAMP_TRIMMING_USER))
+
+
+#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+
+#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
+                                             ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
+
+/**
+  * @}
+  */ 
+
+/* Include OPAMP HAL Extended module */
+#include "stm32l4xx_hal_opamp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
+/**
+  * @}
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group2
+  * @{
+  */
+
+/* I/O operation functions  *****************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); 
+
+/**
+  * @}
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); 
+HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
+
+/**
+  * @}
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group4
+  * @{
+  */
+
+/* Peripheral State functions  **************************************************/
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_OPAMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c
new file mode 100755
index 0000000..1c5d0bf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c
@@ -0,0 +1,456 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_opamp_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended OPAMP HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
+  *          peripheral:
+  *           + Extended Initialization and de-initialization functions
+  *           + Extended Peripheral Control functions
+  *         
+  @verbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup OPAMPEx OPAMPEx
+  * @brief OPAMP Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+  * @{
+  */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+
+/** @addtogroup OPAMPEx_Exported_Functions_Group1
+  * @brief    Extended operation functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Extended IO operation functions #####
+ ===============================================================================
+  [..]
+      (+) OPAMP Self calibration. 
+
+@endverbatim
+  * @{
+  */
+
+/*  2 OPAMPS available */
+/*  2 OPAMPS can be calibrated in parallel */
+/*  Not available on STM32L43x/STM32L44x where only one OPAMP available */
+
+/**
+  * @brief  Run the self calibration of the 2 OPAMPs in parallel.
+  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is 
+  *         enabled is calibration is successful.
+  * @note   Calibration is performed in the mode specified in OPAMP init
+  *         structure (mode normal or low-power). To perform calibration for
+  *         both modes, repeat this function twice after OPAMP init structure
+  *         accordingly updated.
+  * @note   Calibration runs about 10 ms (5 dichotomy steps, repeated for P  
+  *         and N transistors: 10 steps with 1 ms for each step).
+  * @param  hopamp1 handle
+  * @param  hopamp2 handle
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  uint32_t trimmingvaluen1 = 0;
+  uint32_t trimmingvaluep1 = 0;
+  uint32_t trimmingvaluen2 = 0;
+  uint32_t trimmingvaluep2 = 0;
+
+/* Selection of register of trimming depending on power mode: OTR or LPOTR */
+  __IO uint32_t* tmp_opamp1_reg_trimming;   
+  __IO uint32_t* tmp_opamp2_reg_trimming;
+
+  uint32_t delta;
+  uint32_t opampmode1;
+  uint32_t opampmode2;
+  
+  if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+     (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED)) 
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check if OPAMP in calibration mode and calibration not yet enable */
+    if((hopamp1->State ==  HAL_OPAMP_STATE_READY) && (hopamp2->State ==  HAL_OPAMP_STATE_READY))
+    {
+      /* Check the parameter */
+      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
+      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
+      
+      assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
+      assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
+
+      /* Save OPAMP mode as in                                       */
+      /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
+      /* the calibration is not working in PGA mode                  */
+      opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_OPAMODE);
+      opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_OPAMODE);
+
+      /* Use of standalone mode */ 
+      MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); 
+      MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); 
+      
+      /*  user trimming values are used for offset calibration */
+      SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
+      SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
+      
+      /* Select trimming settings depending on power mode */
+      if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+      {
+        tmp_opamp1_reg_trimming = &OPAMP1->OTR;
+      }
+      else
+      {
+        tmp_opamp1_reg_trimming = &OPAMP1->LPOTR;
+      }
+      
+      if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+      {
+        tmp_opamp2_reg_trimming = &OPAMP2->OTR;
+      }
+      else
+      {
+        tmp_opamp2_reg_trimming = &OPAMP2->LPOTR;
+      }
+      
+      /* Enable calibration */
+      SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+      SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+  
+      /* 1st calibration - N */
+      CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
+      CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
+      
+      /* Enable the selected opamp */
+      SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+      SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+      
+      /* Init trimming counter */    
+      /* Medium value */
+      trimmingvaluen1 = 16; 
+      trimmingvaluen2 = 16; 
+      delta = 8; 
+
+      while (delta != 0)
+      {
+        /* Set candidate trimming */
+        /* OPAMP_POWERMODE_NORMAL */
+        MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
+        MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
+
+        /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+        /* Offset trim time: during calibration, minimum time needed between */
+        /* two steps to have 1 mV accuracy */
+        HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+        if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
+        { 
+          /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
+          trimmingvaluen1 -= delta;
+        }
+        else
+        {
+          /* OPAMP_CSR_CALOUT is LOW try higher trimming */
+          trimmingvaluen1 += delta;
+        }
+
+        if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) 
+        { 
+          /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
+          trimmingvaluen2 -= delta;
+        }
+        else
+        {
+          /* OPAMP_CSR_CALOUT is LOW try higher trimming */
+          trimmingvaluen2 += delta;
+        }
+        /* Divide range by 2 to continue dichotomy sweep */
+        delta >>= 1;
+      }
+
+      /* Still need to check if right calibration is current value or one step below */
+      /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1  */
+      /* Set candidate trimming */
+      MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
+      MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
+      
+      /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+      /* Offset trim time: during calibration, minimum time needed between */
+      /* two steps to have 1 mV accuracy */
+      HAL_Delay(OPAMP_TRIMMING_DELAY);
+      
+      if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0)
+      {
+        /* Trimming value is actually one value more */
+        trimmingvaluen1++;
+        MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
+      }
+       
+      if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0)
+      {
+        /* Trimming value is actually one value more */
+        trimmingvaluen2++;
+        MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
+      }
+      
+      /* 2nd calibration - P */
+      SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
+      SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
+             
+      /* Init trimming counter */    
+      /* Medium value */
+      trimmingvaluep1 = 16; 
+      trimmingvaluep2 = 16; 
+      delta = 8; 
+      
+      while (delta != 0)
+      {
+        /* Set candidate trimming */
+        /* OPAMP_POWERMODE_NORMAL */
+        MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
+        MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
+
+        /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+        /* Offset trim time: during calibration, minimum time needed between */
+        /* two steps to have 1 mV accuracy */
+        HAL_Delay(OPAMP_TRIMMING_DELAY);
+
+        if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) 
+        { 
+          /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+          trimmingvaluep1 += delta;
+        }
+        else
+        {
+          /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
+          trimmingvaluep1 -= delta;
+        }
+
+        if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) 
+        { 
+          /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
+          trimmingvaluep2 += delta;
+        }
+        else
+        {
+          /* OPAMP_CSR_CALOUT is LOW try lower trimming */
+          trimmingvaluep2 -= delta;
+        }
+        /* Divide range by 2 to continue dichotomy sweep */
+        delta >>= 1;
+      }
+      
+      /* Still need to check if right calibration is current value or one step below */
+      /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
+      /* Set candidate trimming */
+      MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
+      MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
+      
+      /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ 
+      /* Offset trim time: during calibration, minimum time needed between */
+      /* two steps to have 1 mV accuracy */
+      HAL_Delay(OPAMP_TRIMMING_DELAY);
+      
+      if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
+      {
+        /* Trimming value is actually one value more */
+        trimmingvaluep1++;
+        MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
+      }
+      
+      if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
+      {
+        /* Trimming value is actually one value more */
+        trimmingvaluep2++;
+        MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
+      }
+      
+      /* Disable the OPAMPs */
+      CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+      CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+            
+      /* Disable calibration & set normal mode (operating mode) */
+      CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+      CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+
+      /* Self calibration is successful */
+      /* Store calibration (user trimming) results in init structure. */
+      
+      /* Set user trimming mode */  
+      hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+      hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+      /* Affect calibration parameters depending on mode normal/low power */
+      if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
+      {
+        /* Write calibration result N */
+        hopamp1->Init.TrimmingValueN = trimmingvaluen1;
+        /* Write calibration result P */
+        hopamp1->Init.TrimmingValueP = trimmingvaluep1;
+      }
+      else
+      {
+        /* Write calibration result N */
+        hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1;
+        /* Write calibration result P */
+        hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1;
+      }
+      
+      if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
+      {
+        /* Write calibration result N */
+        hopamp2->Init.TrimmingValueN = trimmingvaluen2;
+        /* Write calibration result P */
+        hopamp2->Init.TrimmingValueP = trimmingvaluep2;
+      }
+      else
+      {
+        /* Write calibration result N */
+        hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2;
+        /* Write calibration result P */
+        hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2;
+      }
+
+      /* Update OPAMP state */
+      hopamp1->State = HAL_OPAMP_STATE_READY;
+      hopamp2->State = HAL_OPAMP_STATE_READY;
+
+      /* Restore OPAMP mode after calibration */
+      MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1);
+      MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2);
+    }
+    else
+    {
+      /* At least one OPAMP can not be calibrated */ 
+      status = HAL_ERROR;
+    }   
+  }
+  return status;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief   Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+      (+) OPAMP unlock. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the selected OPAMP configuration.
+  * @note   This function must be called only when OPAMP is in state "locked".
+  * @param  hopamp: OPAMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the OPAMP handle allocation */
+  /* Check if OPAMP locked */
+  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET)
+                      || (hopamp->State == HAL_OPAMP_STATE_READY)
+                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
+                      || (hopamp->State == HAL_OPAMP_STATE_BUSY))
+  
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+  
+   /* OPAMP state changed to locked */
+    hopamp->State = HAL_OPAMP_STATE_BUSY;
+  }
+  return status; 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h
new file mode 100755
index 0000000..904fb4f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h
@@ -0,0 +1,107 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_opamp_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of OPAMP HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_OPAMP_EX_H
+#define __STM32L4xx_HAL_OPAMP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup OPAMPEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
+  * @{
+  */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+
+/* I/O operation functions  *****************************************************/
+/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); 
+
+/**
+  * @}
+  */
+#endif
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup OPAMPEx_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_OPAMP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c
new file mode 100755
index 0000000..34cf7ec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c
@@ -0,0 +1,1682 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pcd.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   PCD HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The PCD HAL driver can be used as follows:
+
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:
+         PCD_HandleTypeDef  hpcd;
+        
+     (#) Fill parameters of Init structure in HCD handle
+  
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) 
+
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+         (##) Enable the PCD/USB Low Level interface clock using 
+              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+         (##) Initialize the related GPIO clocks
+         (##) Configure PCD pin-out
+         (##) Configure PCD NVIC interrupt
+    
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:
+         (##) hpcd.pData = pdev;
+
+     (#)Enable PCD transmission and reception:
+         (##) HAL_PCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCD PCD
+  * @brief PCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+    
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/**
+  * USB_OTG_CORE VERSION ID
+  */
+#define USB_OTG_CORE_ID_310A          0x4F54310A
+#define USB_OTG_CORE_ID_320A          0x4F54320A
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+  * @{
+  */
+#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+  * @{
+  */
+#if defined (USB_OTG_FS)
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* USB_OTG_FS */
+#if defined (USB)
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+#endif /* USB */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PCD according to the specified
+  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+  uint32_t index = 0U;
+  
+  /* Check the PCD handle allocation */
+  if(hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+  
+  if(hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpcd->Lock = HAL_UNLOCKED;
+	for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
+	hpcd->EPLock[index].Lock = HAL_UNLOCKED;
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_PCD_MspInit(hpcd);
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Disable the Interrupts */
+  __HAL_PCD_DISABLE(hpcd);
+
+  /*Init the Core (common init.) */
+  USB_CoreInit(hpcd->Instance, hpcd->Init);
+
+  /* Force Device Mode*/
+  USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE);
+
+  /* Init endpoints structures */
+  for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
+  {
+    /* Init ep structure */
+    hpcd->IN_ep[index].is_in = 1;
+    hpcd->IN_ep[index].num = index;
+    hpcd->IN_ep[index].tx_fifo_num = index;
+    /* Control until ep is activated */
+    hpcd->IN_ep[index].type = EP_TYPE_CTRL;
+    hpcd->IN_ep[index].maxpacket =  0;
+    hpcd->IN_ep[index].xfer_buff = 0;
+    hpcd->IN_ep[index].xfer_len = 0;
+  }
+  
+  for (index = 0; index < 15 ; index++)
+  {
+    hpcd->OUT_ep[index].is_in = 0;
+    hpcd->OUT_ep[index].num = index;
+    hpcd->IN_ep[index].tx_fifo_num = index;
+    /* Control until ep is activated */
+    hpcd->OUT_ep[index].type = EP_TYPE_CTRL;
+    hpcd->OUT_ep[index].maxpacket = 0;
+    hpcd->OUT_ep[index].xfer_buff = 0;
+    hpcd->OUT_ep[index].xfer_len = 0;
+  }
+
+  /* Init Device */
+  USB_DevInit(hpcd->Instance, hpcd->Init);
+
+  hpcd->USB_Address = 0;
+  
+  hpcd->State= HAL_PCD_STATE_READY;
+  
+   /* Activate LPM */
+  if (hpcd->Init.lpm_enable ==1)
+  {
+    HAL_PCDEx_ActivateLPM(hpcd);
+  }  
+  /* Activate Battery charging */
+  if (hpcd->Init.battery_charging_enable ==1)
+  {
+    HAL_PCDEx_ActivateBCD(hpcd);
+  }
+  USB_DevDisconnect (hpcd->Instance);  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the PCD peripheral.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Check the PCD handle allocation */
+  if(hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+  
+  /* Stop Device */
+  HAL_PCD_Stop(hpcd);
+    
+  /* DeInit the low level hardware */
+  HAL_PCD_MspDeInit(hpcd);
+  
+  hpcd->State = HAL_PCD_STATE_RESET; 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the PCD MSP.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes PCD MSP.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the PCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Start The USB OTG Device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{ 
+  __HAL_LOCK(hpcd); 
+  USB_DevConnect (hpcd->Instance);
+  __HAL_PCD_ENABLE(hpcd);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop The USB OTG Device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{ 
+  __HAL_LOCK(hpcd); 
+  __HAL_PCD_DISABLE(hpcd);
+  USB_StopDevice(hpcd->Instance);
+  USB_DevDisconnect (hpcd->Instance);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+#if defined (USB_OTG_FS)
+/**
+  * @brief  Handles PCD interrupt request.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
+  uint32_t fifoemptymsk = 0U, temp = 0U;
+  USB_OTG_EPTypeDef *ep = NULL;
+  uint32_t hclk = 80000000;
+  
+  /* ensure that we are in device mode */
+  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+  {
+    /* avoid spurious interrupt */
+    if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 
+    {
+      return;
+    }
+    
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+    {
+      /* incorrect mode, acknowledge the interrupt */
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+    }
+    
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+    {
+      epnum = 0;
+      
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+      
+      while (ep_intr)
+      {
+        if (ep_intr & 0x1)
+        {
+          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
+          
+          if (( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+
+            /* setup/out transaction management for Core ID 310A */
+            if (USBx->GSNPSID == USB_OTG_CORE_ID_310A)
+            {
+              if (!(USBx_OUTEP(0)->DOEPINT & (0x1 << 15)))
+                {
+                  if (hpcd->Init.dma_enable == 1)
+                  {
+                  	hpcd->OUT_ep[epnum].xfer_count =
+                                                 hpcd->OUT_ep[epnum].maxpacket -
+                        (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+                    hpcd->OUT_ep[epnum].xfer_buff +=
+                                                  hpcd->OUT_ep[epnum].maxpacket;
+                  }
+
+                HAL_PCD_DataOutStageCallback(hpcd, epnum);
+
+                if (hpcd->Init.dma_enable == 1)
+                {
+                  if (!epnum && !hpcd->OUT_ep[epnum].xfer_len)
+                  {
+                    /* this is ZLP, so prepare EP0 for next setup */
+                    USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
+                  }
+                }
+              }
+
+              /* Clear the SetPktRcvd flag*/
+              USBx_OUTEP(0)->DOEPINT |= (0x1 << 15) | (0x1 << 5);
+            }
+            else
+            {
+              if (hpcd->Init.dma_enable == 1)
+              {
+                hpcd->OUT_ep[epnum].xfer_count =
+                                               hpcd->OUT_ep[epnum].maxpacket -
+                      (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+                hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+              }
+
+              HAL_PCD_DataOutStageCallback(hpcd, epnum);
+          
+              if (hpcd->Init.dma_enable == 1)
+              {
+                if (!epnum && !hpcd->OUT_ep[epnum].xfer_len)
+                {
+                  /* this is ZLP, so prepare EP0 for next setup */
+                  USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
+                }
+              }
+            }
+          }
+
+          if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+          {
+            /* Inform the upper layer that a setup packet is available */
+            HAL_PCD_SetupStageCallback(hpcd);
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+          }
+          
+          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+          }
+          
+#ifdef USB_OTG_DOEPINT_OTEPSPR 
+          /* Clear Status Phase Received interrupt */
+          if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+          }
+#endif /* USB_OTG_DOEPINT_OTEPSPR */
+        }
+        epnum++;
+        ep_intr >>= 1;
+      }
+    }
+    
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+    {
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+      
+      epnum = 0;
+      
+      while ( ep_intr )
+      {
+        if (ep_intr & 0x1) /* In ITR */
+        {
+          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
+          
+          if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+          {
+            fifoemptymsk = 0x1 << epnum;
+            atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK,  fifoemptymsk);
+            
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+            
+            if (hpcd->Init.dma_enable == 1)
+            {
+              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 
+            }
+            
+            HAL_PCD_DataInStageCallback(hpcd, epnum);
+            
+            if (hpcd->Init.dma_enable == 1)
+            {
+              /* this is ZLP, so prepare EP0 for next setup */
+              if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
+              {
+                /* prepare to rx more setup packets */
+                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
+              }
+            }           
+          }
+          if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+          }
+          if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+          }
+          if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+          }
+          if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+          }       
+          if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+          {
+            PCD_WriteEmptyTxFifo(hpcd , epnum);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1;
+      }
+    }
+    
+    /* Handle Resume Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+    {    
+      /* Clear the Remote Wake-up Signaling */
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+      
+      if(hpcd->LPM_State == LPM_L1)
+      {
+        hpcd->LPM_State = LPM_L0;
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+      }
+      else
+      {
+        HAL_PCD_ResumeCallback(hpcd);
+      }
+      
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+    }
+    
+    /* Handle Suspend Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+    {
+      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+      {
+        
+        HAL_PCD_SuspendCallback(hpcd);
+      }
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+    }
+    
+    /* Handle LPM Interrupt */ 
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+    {
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);      
+      if( hpcd->LPM_State == LPM_L0)
+      {   
+        hpcd->LPM_State = LPM_L1;
+        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;  
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+      }
+      else
+      {
+        HAL_PCD_SuspendCallback(hpcd);
+      }
+    }
+    
+    /* Handle Reset Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+    {
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 
+      USB_FlushTxFifo(hpcd->Instance ,  0x10);
+      
+      for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
+      {
+        USBx_INEP(index)->DIEPINT = 0xFF;
+        USBx_OUTEP(index)->DOEPINT = 0xFF;
+      }
+      USBx_DEVICE->DAINT = 0xFFFFFFFF;
+      USBx_DEVICE->DAINTMSK |= 0x10001;
+      
+      if(hpcd->Init.use_dedicated_ep1)
+      {
+        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); 
+        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);  
+      }
+      else
+      {
+#ifdef USB_OTG_DOEPINT_OTEPSPR
+        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
+#else
+        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+#endif /* USB_OTG_DOEPINT_OTEPSPR */
+        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+      }
+      
+      /* Set Default Address to 0 */
+      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+      
+      /* setup EP0 to receive SETUP packets */
+      USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+      
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+    }
+    
+    /* Handle Enumeration done Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+    {
+      USB_ActivateSetup(hpcd->Instance);
+      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+      
+      hpcd->Init.speed            = USB_OTG_SPEED_FULL;
+      hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ; 
+      
+        /* The USBTRD is configured according to the tables below, depending on AHB frequency 
+        used by application. In the low AHB frequency range it is used to stretch enough the USB response 
+        time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access 
+        latency to the Data FIFO */
+
+      /* Get hclk frequency value */
+      hclk = HAL_RCC_GetHCLKFreq();
+    
+      if((hclk >= 14200000)&&(hclk < 15000000))
+      {
+        /* hclk Clock Range between 14.2-15 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 15000000)&&(hclk < 16000000))
+      {
+        /* hclk Clock Range between 15-16 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 16000000)&&(hclk < 17200000))
+      {
+        /* hclk Clock Range between 16-17.2 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 17200000)&&(hclk < 18500000))
+      {
+        /* hclk Clock Range between 17.2-18.5 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 18500000)&&(hclk < 20000000))
+      {
+        /* hclk Clock Range between 18.5-20 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 20000000)&&(hclk < 21800000))
+      {
+        /* hclk Clock Range between 20-21.8 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 21800000)&&(hclk < 24000000))
+      {
+        /* hclk Clock Range between 21.8-24 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 24000000)&&(hclk < 27700000))
+      {
+        /* hclk Clock Range between 24-27.7 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else if((hclk >= 27700000)&&(hclk < 32000000))
+      {
+        /* hclk Clock Range between 27.7-32 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
+      }
+      
+      else /* if(hclk >= 32000000) */
+      {
+        /* hclk Clock Range between 32-80 MHz */
+        hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
+      }  
+      
+      HAL_PCD_ResetCallback(hpcd);
+      
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+    }
+    
+    /* Handle RxQLevel Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+    {
+      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+      
+      temp = USBx->GRXSTSP;
+      
+      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+      
+      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
+      {
+        if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
+        {
+          USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
+          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+        }
+      }
+      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
+      {
+        USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
+        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+      }
+      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+    
+    /* Handle SOF Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+    {
+      HAL_PCD_SOFCallback(hpcd);
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+    }
+    
+    /* Handle Incomplete ISO IN Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+      HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+    } 
+    
+    /* Handle Incomplete ISO OUT Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+      HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    } 
+    
+    /* Handle Connection event Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+    {
+      HAL_PCD_ConnectCallback(hpcd);
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+    } 
+    
+    /* Handle Disconnection event Interrupt */
+    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+    {
+      temp = hpcd->Instance->GOTGINT;
+      
+      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+      {
+        HAL_PCD_DisconnectCallback(hpcd);
+      }
+      hpcd->Instance->GOTGINT |= temp;
+    }
+  }
+}
+
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+/**
+  * @brief  This function handles PCD interrupt request.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  uint32_t wInterrupt_Mask = 0;
+  
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
+  {
+    /* servicing of the endpoint correct transfer interrupt */
+    /* clear of the CTR flag into the sub */
+    PCD_EP_ISR_Handler(hpcd);
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+    HAL_PCD_ResetCallback(hpcd);
+    HAL_PCD_SetAddress(hpcd, 0);
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);    
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); 
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
+  {
+    
+    hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE);
+
+    /*set wInterrupt_Mask global variable*/
+    wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+      | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+    
+    /*Set interrupt mask*/
+    hpcd->Instance->CNTR = wInterrupt_Mask;
+
+    /* enable L1REQ interrupt */ 
+    if (hpcd->Init.lpm_enable ==1)
+    {
+      wInterrupt_Mask |= USB_CNTR_L1REQM;
+      
+      /* Enable LPM support and enable ACK answer to LPM request*/
+      USB_TypeDef *USBx = hpcd->Instance;
+      hpcd->lpm_active = ENABLE;
+      hpcd->LPM_State = LPM_L0;
+      
+      USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
+      USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
+    } 
+    
+    if(hpcd->LPM_State == LPM_L1)
+    {
+      hpcd->LPM_State = LPM_L0;
+      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+    }
+    
+    HAL_PCD_ResumeCallback(hpcd);
+    
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);     
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
+  {    
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);  
+    
+    /* Force low-power mode in the macrocell */
+    hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+    hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+
+    if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
+    {
+      HAL_PCD_SuspendCallback(hpcd);
+    }
+  }
+
+  /* Handle LPM Interrupt */ 
+  if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);      
+    if( hpcd->LPM_State == LPM_L0)
+    {   
+      /* Force suspend and low-power mode before going to L1 state*/
+      hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+      hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+      
+      hpcd->LPM_State = LPM_L1;
+      hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ;  
+      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+    }
+    else
+    {
+      HAL_PCD_SuspendCallback(hpcd);
+    }
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); 
+    HAL_PCD_SOFCallback(hpcd);
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
+  {
+    /* clear ESOF flag in ISTR */
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); 
+  }
+}
+#endif /* USB */
+
+/**
+  * @brief  Data OUT stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Data IN stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataInStageCallback could be implemented in the user file
+   */ 
+}
+/**
+  * @brief  Setup stage callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SetupStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  USB Start Of Frame callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SOFCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  USB Reset callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResetCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Suspend event callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SuspendCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Resume event callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResumeCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Incomplete ISO OUT callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Incomplete ISO IN callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Connection event callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ConnectCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Disconnection event callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DisconnectCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the PCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Connect the USB device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd); 
+  USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disconnect the USB device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd); 
+  USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the USB Device address.
+  * @param  hpcd: PCD handle
+  * @param  address: new device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+  __HAL_LOCK(hpcd); 
+  hpcd->USB_Address = address;
+  USB_SetDevAddress(hpcd->Instance, address);
+  __HAL_UNLOCK(hpcd);   
+  return HAL_OK;
+}
+/**
+  * @brief  Open and configure an endpoint.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  ep_mps: endpoint max packet size
+  * @param  ep_type: endpoint type   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+  HAL_StatusTypeDef  ret = HAL_OK;
+  PCD_EPTypeDef *ep = NULL;
+  
+  if ((ep_addr & 0x80) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+  }
+  ep->num   = ep_addr & 0x7F;
+  
+  ep->is_in = (0x80 & ep_addr) != 0;
+  ep->maxpacket = ep_mps;
+  ep->type = ep_type;
+    
+  __HAL_LOCK(hpcd);
+  USB_ActivateEndpoint(hpcd->Instance , ep);
+  __HAL_UNLOCK(hpcd);
+  return ret;
+
+}
+
+
+/**
+  * @brief  Deactivate an endpoint.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{  
+  PCD_EPTypeDef *ep = NULL;
+  
+  if ((ep_addr & 0x80) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+  }
+  ep->num   = ep_addr & 0x7F;
+  
+  ep->is_in = (0x80 & ep_addr) != 0;
+  
+  __HAL_LOCK(hpcd); 
+  USB_DeactivateEndpoint(hpcd->Instance , ep);
+  __HAL_UNLOCK(hpcd);   
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Receive an amount of data.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  pBuf: pointer to the reception buffer   
+  * @param  len: amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep = NULL;
+  
+  ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+  
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;  
+  ep->xfer_len = len;
+  ep->xfer_count = 0;
+  ep->is_in = 0;
+  ep->num = ep_addr & 0x7F;
+  
+  __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  
+  if ((ep_addr & 0x7F) == 0 )
+  {
+    USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
+  }
+  else
+  {
+    USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
+  }
+  __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Received Data Size.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval Data Size
+  */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+}
+/**
+  * @brief  Send an amount of data.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  pBuf: pointer to the transmission buffer   
+  * @param  len: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep = NULL;
+  
+  ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;  
+  ep->xfer_len = len;
+  ep->xfer_count = 0;
+  ep->is_in = 1;
+  ep->num = ep_addr & 0x7F;
+  
+  __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  
+  if ((ep_addr & 0x7F) == 0 )
+  {
+    USB_EP0StartXfer(hpcd->Instance,ep,  hpcd->Init.dma_enable);
+  }
+  else
+  {
+    USB_EPStartXfer(hpcd->Instance, ep,  hpcd->Init.dma_enable);
+  }
+  
+  __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set a STALL condition over an endpoint.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep = NULL;
+  
+  if ((0x80 & ep_addr) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  ep->is_stall = 1;
+  ep->num   = ep_addr & 0x7F;
+  ep->is_in = ((ep_addr & 0x80) == 0x80);
+  
+  __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  USB_EPSetStall(hpcd->Instance , ep);
+  if((ep_addr & 0x7F) == 0)
+  {
+    USB_EP0_OutStart(hpcd->Instance,  hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+  }
+  __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear a STALL condition over in an endpoint.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep = NULL;
+  
+  if ((0x80 & ep_addr) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  ep->is_stall = 0;
+  ep->num   = ep_addr & 0x7F;
+  ep->is_in = ((ep_addr & 0x80) == 0x80);
+  
+  __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  USB_EPClearStall(hpcd->Instance , ep);
+  __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Flush an endpoint.
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+  if ((ep_addr & 0x80) == 0x80)
+  {
+    USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
+  }
+  else
+  {
+    USB_FlushRxFifo(hpcd->Instance);
+  }
+  
+  __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate remote wakeup signalling.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return(USB_ActivateRemoteWakeup(hpcd->Instance)); 
+}
+
+/**
+  * @brief  De-activate remote wakeup signalling.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return(USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PCD handle state.
+  * @param  hpcd: PCD handle
+  * @retval HAL state
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+  return hpcd->State;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+  * @{
+  */
+#if defined (USB_OTG_FS)
+/**
+  * @brief  Check FIFO for the next packet to be loaded.
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  USB_OTG_EPTypeDef *ep = NULL;
+  int32_t len = 0U;
+  uint32_t len32b = 0;
+  uint32_t fifoemptymsk = 0;
+
+  ep = &hpcd->IN_ep[epnum];
+  len = ep->xfer_len - ep->xfer_count;
+  
+  if (len > ep->maxpacket)
+  {
+    len = ep->maxpacket;
+  }
+  
+  
+  len32b = (len + 3) / 4;
+ 
+  while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
+          ep->xfer_count < ep->xfer_len &&
+            ep->xfer_len != 0)
+  {
+    /* Write the FIFO */
+    len = ep->xfer_len - ep->xfer_count;
+    
+    if (len > ep->maxpacket)
+    {
+      len = ep->maxpacket;
+    }
+    len32b = (len + 3) / 4;
+    
+    USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); 
+    
+    ep->xfer_buff  += len;
+    ep->xfer_count += len;
+  }
+  
+  if(len <= 0)
+  {
+    fifoemptymsk = 0x1 << epnum;
+    atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
+    
+  }
+  
+  return HAL_OK;  
+}
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+/**
+  * @brief  This function handles PCD Endpoint interrupt request.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+{
+  PCD_EPTypeDef *ep = NULL;
+  uint16_t count = 0;
+  uint8_t epindex = 0;
+  __IO uint16_t wIstr = 0;  
+  __IO uint16_t wEPVal = 0;
+  
+  /* stay in loop while pending interrupts */
+  while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
+  {
+    /* extract highest priority endpoint number */
+    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+    
+    if (epindex == 0)
+    {
+      /* Decode and service control endpoint interrupt */
+      
+      /* DIR bit = origin of the interrupt */   
+      if ((wIstr & USB_ISTR_DIR) == 0)
+      {
+        /* DIR = 0 */
+        
+        /* DIR = 0      => IN  int */
+        /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+        ep = &hpcd->IN_ep[0];
+        
+        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+        ep->xfer_buff += ep->xfer_count;
+ 
+        /* TX COMPLETE */
+        HAL_PCD_DataInStageCallback(hpcd, 0);
+        
+        
+        if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
+        {
+          hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+          hpcd->USB_Address = 0;
+        }
+        
+      }
+      else
+      {
+        /* DIR = 1 */
+        
+        /* DIR = 1 & CTR_RX       => SETUP or OUT int */
+        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+        ep = &hpcd->OUT_ep[0];
+        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+        
+        if ((wEPVal & USB_EP_SETUP) != 0)
+        {
+          /* Get SETUP Packet*/
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+          USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);       
+          /* SETUP bit kept frozen while CTR_RX = 1*/ 
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 
+          
+          /* Process SETUP Packet*/
+          HAL_PCD_SetupStageCallback(hpcd);
+        }
+        
+        else if ((wEPVal & USB_EP_CTR_RX) != 0)
+        {
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+          /* Get Control Data OUT Packet*/
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+          
+          if (ep->xfer_count != 0)
+          {
+            USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+            ep->xfer_buff+=ep->xfer_count;
+          }
+          
+          /* Process Control Data OUT Packet*/
+           HAL_PCD_DataOutStageCallback(hpcd, 0);
+          
+          PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+          PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+        }
+      }
+    }
+    else
+    {
+      /* Decode and service non control endpoints interrupt  */
+	  
+      /* process related endpoint register */
+      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
+      if ((wEPVal & USB_EP_CTR_RX) != 0)
+      {  
+        /* clear int flag */
+        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
+        ep = &hpcd->OUT_ep[epindex];
+        
+        /* OUT double Buffering*/
+        if (ep->doublebuffer == 0)
+        {
+          count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+          if (count != 0)
+          {
+            USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+          }
+        }
+        else
+        {
+          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+          {
+            /*read from endpoint BUF0Addr buffer*/
+            count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+            if (count != 0)
+            {
+              USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+            }
+          }
+          else
+          {
+            /*read from endpoint BUF1Addr buffer*/
+            count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+            if (count != 0)
+            {
+              USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+            }
+          }
+          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);  
+        }
+        /*multi-packet on the NON control OUT endpoint*/
+        ep->xfer_count+=count;
+        ep->xfer_buff+=count;
+       
+        if ((ep->xfer_len == 0) || (count < ep->maxpacket))
+        {
+          /* RX COMPLETE */
+          HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+        }
+        else
+        {
+          HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+        }
+        
+      } /* if((wEPVal & EP_CTR_RX) */
+      
+      if ((wEPVal & USB_EP_CTR_TX) != 0)
+      {
+        ep = &hpcd->IN_ep[epindex];
+        
+        /* clear int flag */
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
+        
+        /* IN double Buffering*/
+        if (ep->doublebuffer == 0)
+        {
+          ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+          if (ep->xfer_count != 0)
+          {
+            USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+          }
+        }
+        else
+        {
+          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+          {
+            /*read from endpoint BUF0Addr buffer*/
+            ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+            if (ep->xfer_count != 0)
+            {
+              USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
+            }
+          }
+          else
+          {
+            /*read from endpoint BUF1Addr buffer*/
+            ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+            if (ep->xfer_count != 0)
+            {
+              USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
+            }
+          }
+          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);  
+        }
+        /*multi-packet on the NON control IN endpoint*/
+        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+        ep->xfer_buff+=ep->xfer_count;
+       
+        /* Zero Length Packet? */
+        if (ep->xfer_len == 0)
+        {
+          /* TX COMPLETE */
+          HAL_PCD_DataInStageCallback(hpcd, ep->num);
+        }
+        else
+        {
+          HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+        }
+      } 
+    }
+  }
+  return HAL_OK;
+}
+#endif /* USB */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h
new file mode 100755
index 0000000..01be38c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h
@@ -0,0 +1,879 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PCD_H
+#define __STM32L4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_usb.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup PCD_Exported_Types PCD Exported Types
+  * @{
+  */
+
+   /** 
+  * @brief  PCD State structure definition  
+  */  
+typedef enum 
+{
+  HAL_PCD_STATE_RESET   = 0x00,
+  HAL_PCD_STATE_READY   = 0x01,
+  HAL_PCD_STATE_ERROR   = 0x02,
+  HAL_PCD_STATE_BUSY    = 0x03,
+  HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum  
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+}PCD_LPM_StateTypeDef;
+
+#if defined (USB)
+/**
+  * @brief  PCD double buffered endpoint direction
+  */
+typedef enum
+{
+  PCD_EP_DBUF_OUT,
+  PCD_EP_DBUF_IN,
+  PCD_EP_DBUF_ERR,
+}PCD_EP_DBUF_DIR;
+
+/**
+  * @brief  PCD endpoint buffer number
+  */
+typedef enum 
+{
+  PCD_EP_NOBUF,
+  PCD_EP_BUF0,
+  PCD_EP_BUF1
+}PCD_EP_BUF_NUM;  
+#endif /* USB */
+
+#if defined (USB_OTG_FS)
+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+typedef USB_TypeDef        PCD_TypeDef;
+typedef USB_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_EPTypeDef      PCD_EPTypeDef;
+#endif /* USB */                         
+typedef struct
+{
+	HAL_LockTypeDef Lock;
+} PCD_EPLockDef;
+
+/** 
+  * @brief  PCD Handle Structure definition  
+  */ 
+typedef struct
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address              */ 
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
+  __IO uint8_t            USB_Address; /*!< USB Address: not used by USB OTG FS */  
+  PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */ 
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
+  PCD_EPLockDef           EPLock[15]; 
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
+  uint32_t                Setup[12];   /*!< Setup packet buffer                */
+  PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
+  uint32_t                BESL;
+  
+  
+  uint32_t lpm_active;                  /*!< Enable or disable the Link Power Management .                                  
+                                        This parameter can be set to ENABLE or DISABLE                      */
+
+  uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.                                  
+                                        This parameter can be set to ENABLE or DISABLE                      */
+  void                    *pData;      /*!< Pointer to upper stack Handler     */    
+  
+} PCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+  
+/* Include PCD HAL Extended module */
+#include "stm32l4xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup PCD_Speed PCD Speed
+  * @{
+  */
+#define PCD_SPEED_FULL               1
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_PHY_Module PCD PHY Module
+  * @{
+  */
+#define PCD_PHY_EMBEDDED             1
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
+  * @{
+  */
+#ifndef USBD_FS_TRDT_VALUE
+ #define USBD_FS_TRDT_VALUE           5
+#endif /* USBD_FS_TRDT_VALUE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#if defined (USB_OTG_FS)
+#define __HAL_PCD_ENABLE(__HANDLE__)                       USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                      USB_DisableGlobalInt ((__HANDLE__)->Instance)
+   
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+                                                          ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+                                                      
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
+                                                                                                             
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()  do {\
+                                                             EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                             EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+                                                           } while(0)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
+                                                             EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                             EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                           } while(0)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
+                                                                   EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                                   EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                                   EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+                                                                   EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+                                                                  } while(0)                                                                   
+                                                         
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)                                                          
+
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+#define __HAL_PCD_ENABLE(__HANDLE__)                                  USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                                 USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_GET_FLAG()                              EXTI->PR1 & (USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG()                            EXTI->PR1 = USB_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()                    do {\
+                                                                        EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\
+                                                                      } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()                   do {\
+                                                                        EXTI->FTSR1 |= (USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                      } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()            do {\
+                                                                        EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\
+                                                                        EXTI->FTSR1 |= USB_WAKEUP_EXTI_LINE;\
+                                                                      } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_WAKEUP_EXTI_LINE)
+
+#endif /* USB */
+                                                                        
+/**
+  * @}
+  */
+
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+  * @{
+  */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+  * @{
+  */
+#if defined (USB_OTG_FS)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            ((uint32_t)0x08)
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           ((uint32_t)0x0C)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    ((uint32_t)0x10)
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the USB EXTI Line */
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+#define  USB_WAKEUP_EXTI_LINE                                         ((uint32_t)0x00020000)  /*!< External interrupt line 17Connected to the USB EXTI Line */
+#endif /* USB */
+
+/**
+  * @}
+  */
+
+#if defined (USB)
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+  * @{
+  */
+#define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64
+#define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32
+#define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16
+#define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8 
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_ENDP PCD ENDP
+  * @{
+  */
+#define PCD_ENDP0                                                     ((uint8_t)0)
+#define PCD_ENDP1                                                     ((uint8_t)1)
+#define PCD_ENDP2                                                     ((uint8_t)2)
+#define PCD_ENDP3                                                     ((uint8_t)3)
+#define PCD_ENDP4                                                     ((uint8_t)4)
+#define PCD_ENDP5                                                     ((uint8_t)5)
+#define PCD_ENDP6                                                     ((uint8_t)6)
+#define PCD_ENDP7                                                     ((uint8_t)7)
+/**
+  * @}
+  */
+
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+  * @{
+  */
+#define PCD_SNG_BUF                                                   0
+#define PCD_DBL_BUF                                                   1
+/**
+  * @}
+  */
+#endif /* USB */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+#if defined (USB)
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(&(USBx)->EP0R + (bEpNum) * 2))
+
+/* ENDPOINT transfer */
+#define USB_EP0StartXfer                          USB_EPStartXfer
+
+/**
+  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wType: Endpoint Type.
+  * @retval None
+  */
+#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+                                  ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+
+/**
+  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval Endpoint Type
+  */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+
+/**
+  * @brief free buffer used from the application realizing it to the line
+          toggles bit SW_BUF in the double buffered endpoint register
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bDir: Direction
+  * @retval None
+  */
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
+{\
+  if ((bDir) == PCD_EP_DBUF_OUT)\
+  { /* OUT double buffered endpoint */\
+    PCD_TX_DTOG((USBx), (bEpNum));\
+  }\
+  else if ((bDir) == PCD_EP_DBUF_IN)\
+  { /* IN double buffered endpoint */\
+    PCD_RX_DTOG((USBx), (bEpNum));\
+  }\
+}
+
+/**
+  * @brief gets direction of the double buffered endpoint
+  * @param   USBx: USB peripheral instance register address.
+  * @param   bEpNum: Endpoint Number.
+  * @retval EP_DBUF_OUT, EP_DBUF_IN,
+  *         EP_DBUF_ERR if the endpoint counter not yet programmed.
+  */
+#define PCD_GET_DB_DIR(USBx, bEpNum)\
+{\
+  if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
+    return(PCD_EP_DBUF_OUT);\
+  else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
+    return(PCD_EP_DBUF_IN);\
+  else\
+    return(PCD_EP_DBUF_ERR);\
+}
+
+/**
+  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wState: new state
+  * @retval None
+  */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
+   \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
+   /* toggle first bit ? */     \
+   if((USB_EPTX_DTOG1 & (wState))!= 0)\
+   {                                                                            \
+     _wRegVal ^= USB_EPTX_DTOG1;        \
+   }                                                                            \
+   /* toggle second bit ?  */         \
+   if((USB_EPTX_DTOG2 & (wState))!= 0)      \
+   {                                                                            \
+     _wRegVal ^= USB_EPTX_DTOG2;        \
+   }                                                                            \
+   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
+  } /* PCD_SET_EP_TX_STATUS */
+
+/**
+  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wState: new state
+  * @retval None
+  */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
+    register uint16_t _wRegVal;   \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
+    /* toggle first bit ? */  \
+    if((USB_EPRX_DTOG1 & (wState))!= 0) \
+    {                                                                             \
+      _wRegVal ^= USB_EPRX_DTOG1;  \
+    }                                                                             \
+    /* toggle second bit ? */  \
+    if((USB_EPRX_DTOG2 & (wState))!= 0) \
+    {                                                                             \
+      _wRegVal ^= USB_EPRX_DTOG2;  \
+    }                                                                             \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+  } /* PCD_SET_EP_RX_STATUS */
+
+/**
+  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wStaterx: new state.
+  * @param  wStatetx: new state.
+  * @retval None
+  */
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
+    register uint32_t _wRegVal;   \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
+    /* toggle first bit ? */  \
+    if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
+    {                                                                                    \
+      _wRegVal ^= USB_EPRX_DTOG1;  \
+    }                                                                                    \
+    /* toggle second bit ? */  \
+    if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
+    {                                                                                    \
+      _wRegVal ^= USB_EPRX_DTOG2;  \
+    }                                                                                    \
+    /* toggle first bit ? */     \
+    if((USB_EPTX_DTOG1 & (wStatetx))!= 0)      \
+    {                                                                                    \
+      _wRegVal ^= USB_EPTX_DTOG1;        \
+    }                                                                                    \
+    /* toggle second bit ?  */         \
+    if((USB_EPTX_DTOG2 & (wStatetx))!= 0)      \
+    {                                                                                    \
+      _wRegVal ^= USB_EPTX_DTOG2;        \
+    }                                                                                    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
+  } /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
+  *         /STAT_RX[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval status
+  */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+
+/**
+  * @brief  sets directly the VALID tx/rx-status into the endpoint register
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+  * @brief  checks stall condition in an endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval TRUE = endpoint in stall condition.
+  */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
+                                   == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
+                                   == USB_EP_RX_STALL)
+
+/**
+  * @brief  set & clear EP_KIND bit.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
+
+/**
+  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+
+/**
+  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+#define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+
+/**
+  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
+                                         {                                                              \
+                                           PCD_RX_DTOG((USBx), (bEpNum));                               \
+                                         }
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
+                                         {                                                              \
+                                            PCD_TX_DTOG((USBx), (bEpNum));                              \
+                                         }
+      
+/**
+  * @brief  Sets address in an endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bAddr: Address.
+  * @retval None
+  */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
+    USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
+
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+     ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+  ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+  ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+  ((uint32_t)(USBx) + 0x400)))
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+    uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+  }
+
+/**
+  * @brief  sets address of the tx/rx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wAddr: address to be set (must be word aligned).
+  * @retval None
+  */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+
+/**
+  * @brief  Gets address of the tx/rx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval address of the buffer.
+  */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+  * @brief  Sets counter of rx buffer with no. of blocks.
+  * @param  dwReg: Register
+  * @param  wCount: Counter.
+  * @param  wNBlocks: no. of Blocks.
+  * @retval None
+  */
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
+    (wNBlocks) = (wCount) >> 5;\
+    if(((wCount) & 0x1f) == 0)\
+    {                                                  \
+      (wNBlocks)--;\
+    }                                                  \
+    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
+  }/* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
+    (wNBlocks) = (wCount) >> 1;\
+    if(((wCount) & 0x1) != 0)\
+    {                                                  \
+      (wNBlocks)++;\
+    }                                                  \
+    *pdwReg = (uint16_t)((wNBlocks) << 10);\
+  }/* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  {\
+    uint16_t wNBlocks;\
+    if((wCount) > 62)                                \
+    {                                                \
+      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
+    }                                                \
+    else                                             \
+    {                                                \
+      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
+    }                                                \
+  }/* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
+    uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+  }
+
+/**
+  * @brief  sets counter for the tx/rx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wCount: Counter value.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
+
+
+/**
+  * @brief  gets counter of the tx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval Counter value
+  */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
+
+/**
+  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wBuf0Addr: buffer 0 address.
+  * @retval Counter value
+  */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
+
+/**
+  * @brief  Sets addresses in a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wBuf0Addr: buffer 0 address.
+  * @param  wBuf1Addr = buffer 1 address.
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
+    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
+    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
+  } /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT 
+  *         EP_DBUF_IN  = IN 
+  * @param  wCount: Counter value 
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
+    if((bDir) == PCD_EP_DBUF_OUT)\
+      /* OUT endpoint */ \
+    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
+    else if((bDir) == PCD_EP_DBUF_IN)\
+      /* IN endpoint */ \
+      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
+  } /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
+    if((bDir) == PCD_EP_DBUF_OUT)\
+    {/* OUT endpoint */                                       \
+      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
+    }                                                         \
+    else if((bDir) == PCD_EP_DBUF_IN)\
+    {/* IN endpoint */                                        \
+      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+    }                                                         \
+  } /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
+    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+  } /* PCD_SET_EP_DBUF_CNT  */
+
+/**
+  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+
+#endif /* USB */
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx)
+
+/** @defgroup PCD_Instance_definition PCD Instance definition
+  * @{
+  */
+#define IS_PCD_ALL_INSTANCE                                        IS_USB_ALL_INSTANCE
+/**
+  * @}
+  */
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c
new file mode 100755
index 0000000..d90cf06
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c
@@ -0,0 +1,521 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   PCD Extended HAL module driver.  
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @defgroup PCDEx PCDEx
+  * @brief PCD Extended HAL module driver
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+  
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    PCDEx control functions 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Update FIFO configuration
+
+@endverbatim
+  * @{
+  */
+#if defined (USB_OTG_FS)
+/**
+  * @brief  Set Tx FIFO
+  * @param  hpcd: PCD handle
+  * @param  fifo: The number of Tx fifo
+  * @param  size: Fifo size
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+  uint8_t index = 0;
+  uint32_t Tx_Offset = 0;
+
+  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
+      When a TxFIFO is not used, the Configuration should be as follows: 
+          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txm can use the space allocated for Txn.
+         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txn should be configured with the minimum space of 16 words
+     The FIFO is used optimally when used TxFIFOs are allocated in the top 
+         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+  
+  Tx_Offset = hpcd->Instance->GRXFSIZ;
+  
+  if(fifo == 0)
+  {
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+  }
+  else
+  {
+    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+    for (index = 0; index < (fifo - 1); index++)
+    {
+      Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16);
+    }
+    
+    /* Multiply Tx_Size by 2 to get higher performance */
+    hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Rx FIFO
+  * @param  hpcd: PCD handle
+  * @param  size: Size of Rx fifo
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+  hpcd->Instance->GRXFSIZ = size;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  
+  hpcd->lpm_active = ENABLE;
+  hpcd->LPM_State = LPM_L0;
+  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  
+  hpcd->lpm_active = DISABLE;
+  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Start BCD When device is connected */
+  if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
+  { 
+    /* Enable DCD : Data Contact Detect */
+    USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+    
+    /* Wait Detect flag or a timeout is happen*/
+    while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > 1000)
+      {
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+        return;
+      }
+    }
+    
+    /* Right response got */
+    HAL_Delay(100); 
+    
+    /* Check Detect flag*/
+    if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
+    {
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+    }
+    
+    /*Primary detection: checks if connected to Standard Downstream Port  
+    (without charging capability) */
+    USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
+    USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
+    HAL_Delay(100); 
+    
+    if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
+    {
+      /* Case of Standard Downstream Port */
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+    }
+    else  
+    {
+      /* start secondary detection to check connection to Charging Downstream 
+      Port or Dedicated Charging Port */
+      USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
+      USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
+      HAL_Delay(100); 
+      
+      if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
+      { 
+        /* case Dedicated Charging Port  */
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+      }
+      else
+      {
+        /* case Charging Downstream Port  */
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+      }
+    }
+    /* Battery Charging capability discovery finished */
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+  }
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+
+  hpcd->battery_charging_active = ENABLE; 
+  USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  hpcd->battery_charging_active = DISABLE; 
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+  return HAL_OK;  
+}
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+/**
+  * @brief  Configure PMA for EP
+  * @param  hpcd : Device instance
+  * @param  ep_addr: endpoint address
+  * @param  ep_kind: endpoint Kind
+  *                  USB_SNG_BUF: Single Buffer used
+  *                  USB_DBL_BUF: Double Buffer used
+  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
+  *                   this parameter is 16-bit value providing the address
+  *                   in PMA allocated to endpoint.
+  *                   In case of double buffer endpoint this parameter
+  *                   is a 32-bit value providing the endpoint buffer 0 address
+  *                   in the LSB part of 32-bit value and endpoint buffer 1 address
+  *                   in the MSB part of 32-bit value.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, 
+                                       uint16_t ep_addr,
+                                       uint16_t ep_kind,
+                                       uint32_t pmaadress)
+
+{
+  PCD_EPTypeDef *ep = NULL;
+  
+  /* initialize ep structure*/
+  if ((0x80 & ep_addr) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  /* Here we check if the endpoint is single or double Buffer*/
+  if (ep_kind == PCD_SNG_BUF)
+  {
+    /*Single Buffer*/
+    ep->doublebuffer = 0;
+    /*Configure te PMA*/
+    ep->pmaadress = (uint16_t)pmaadress;
+  }
+  else /*USB_DBL_BUF*/
+  {
+    /*Double Buffer Endpoint*/
+    ep->doublebuffer = 1;
+    /*Configure the PMA*/
+    ep->pmaaddr0 =  pmaadress & 0xFFFF;
+    ep->pmaaddr1 =  (pmaadress & 0xFFFF0000) >> 16;
+  }
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = ENABLE;
+  
+  USBx->BCDR |= (USB_BCDR_BCDEN);
+  /* Enable DCD : Data Contact Detect */
+  USBx->BCDR |= (USB_BCDR_DCDEN);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = DISABLE;
+  
+  USBx->BCDR &= ~(USB_BCDR_BCDEN);
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  uint32_t tickstart = HAL_GetTick();
+   
+  /* Wait Detect flag or a timeout is happen*/
+  while ((USBx->BCDR & USB_BCDR_DCDET) == 0)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > 1000)
+    {
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+      return;
+    }
+  }
+
+  HAL_Delay(300);
+  
+  /* Data Pin Contact ? Check Detect flag */
+  if (USBx->BCDR & USB_BCDR_DCDET)
+  {
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+  }   
+  /* Primary detection: checks if connected to Standard Downstream Port  
+  (without charging capability) */
+  USBx->BCDR &= ~(USB_BCDR_DCDEN);
+  USBx->BCDR |= (USB_BCDR_PDEN);
+  HAL_Delay(300);
+  
+  /* If Charger detect ? */
+  if (USBx->BCDR & USB_BCDR_PDET)
+  {
+    /* Start secondary detection to check connection to Charging Downstream 
+    Port or Dedicated Charging Port */
+    USBx->BCDR &= ~(USB_BCDR_PDEN);
+    USBx->BCDR |= (USB_BCDR_SDEN);
+    HAL_Delay(300);
+    
+    /* If CDP ? */
+    if (USBx->BCDR & USB_BCDR_SDET)
+    {
+      /* Dedicated Downstream Port DCP */
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+    }
+    else
+    {
+      /* Charging Downstream Port CDP */
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+      
+      /* Battery Charging capability discovery finished 
+      Start Enumeration*/
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+    }
+  }
+  else /* NO */
+  {
+    /* Standard Downstream Port */
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+  }
+}
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->lpm_active = ENABLE;
+  hpcd->LPM_State = LPM_L0;
+  
+  USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
+  USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
+    
+ 
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance; 
+  
+  hpcd->lpm_active = DISABLE;
+  
+  USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN);
+  USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK);
+  
+  return HAL_OK;  
+}
+
+#endif /* USB */
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h
new file mode 100755
index 0000000..45054ab
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h
@@ -0,0 +1,136 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pcd_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PCD_EX_H
+#define __STM32L4xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCDEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+typedef enum  
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+}PCD_LPM_MsgTypeDef;
+
+typedef enum  
+{
+  PCD_BCD_ERROR                     = 0xFF, 
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+  
+}PCD_BCD_MsgTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @{
+  */
+
+#if defined(USB_OTG_FS)
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, 
+                                       uint16_t ep_addr,
+                                       uint16_t ep_kind,
+                                       uint32_t pmaadress);
+#endif /* USB */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c
new file mode 100755
index 0000000..0ba3d39
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c
@@ -0,0 +1,676 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+
+/** @defgroup PWR_Private_Defines PWR Private Defines
+  * @{
+  */
+  
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */ 
+#define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */ 
+#define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */ 
+#define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */ 
+#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+  * @brief Enable access to the backup domain 
+  *        (RTC registers, RTC backup data registers).
+  * @note  After reset, the backup domain is protected against 
+  *        possible unwanted write accesses.
+  * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
+  *        In order to set or modify the RTC clock, the backup domain access must be
+  *        disabled. 
+  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
+  *        back-up domain.                
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);    
+}
+
+/**
+  * @brief Disable access to the backup domain
+  *        (RTC registers, RTC backup data registers).    
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);   
+}
+
+
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief Low Power modes configuration functions
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+ 
+     [..]
+     *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
+
+      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+ 
+    
+    *** WakeUp pin configuration ***
+    ================================
+    [..]
+      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. 
+          The polarity of these pins can be set to configure event detection on high 
+          level (rising edge) or low level (falling edge).
+
+
+   
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+      The devices feature 8 low-power modes:
+      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
+      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
+      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
+      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
+      (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.      
+      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. 
+      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
+      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
+
+
+   *** Low-power run mode ***
+   ==========================
+    [..]
+      (+) Entry: (from main run mode)
+        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. 
+     
+      (+) Exit:
+        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
+             then can the system clock frequency be increased above 2 MHz.
+
+
+   *** Sleep mode / Low-power sleep mode ***
+   =========================================
+    [..]
+      (+) Entry:                                                         
+          The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
+          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. 
+          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).              
+          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
+          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.           
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+     
+      (+) WFI Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+             controller (NVIC) or any wake-up event.
+             
+      (+) WFE Exit:
+        (++) Any wake-up event such as an EXTI line configured in event mode.             
+             
+         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, 
+             the MCU is in Low-power Run mode. 
+
+   *** Stop 0, Stop 1 and Stop 2 modes ***
+   ===============================
+    [..]
+      (+) Entry:                                                 
+          The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
+          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
+          (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.  
+      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
+          (++) PWR_MAINREGULATOR_ON
+          (++) PWR_LOWPOWERREGULATOR_ON
+      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
+          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
+          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
+          
+      (+) WFI Exit:
+          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
+          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts 
+               when programmed in wakeup mode. 
+      (+) WFE Exit:  
+          (++) Any EXTI Line (Internal or External) configured in Event mode.
+       
+       [..]                      
+          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
+          depending on the LPR bit setting. 
+          When exiting Stop 2 mode, the MCU is in Run mode. 
+
+   *** Standby mode ***
+   ====================
+     [..]
+      The Standby mode offers two options: 
+      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
+        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers 
+        and Standby circuitry.      
+      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
+        SRAM and register contents are lost except for the RTC registers, RTC backup registers 
+        and Standby circuitry.
+
+      (++) Entry:                                    
+          (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. 
+                SRAM1 and register contents are lost except for registers in the Backup domain and 
+                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
+                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
+                to set RRS bit.   
+          
+      (++) Exit:
+          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
+                external reset in NRST pin, IWDG reset.
+                
+      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
+          
+
+    *** Shutdown mode ***
+   ======================
+     [..]
+      In Shutdown mode, 
+        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
+        SRAM and registers contents are lost except for backup domain registers.
+
+      (+) Entry:                                    
+          The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
+          
+      (+) Exit:
+          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
+               external reset in NRST pin.
+               
+         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
+
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+      Wakeup event, a tamper event or a time-stamp event, without depending on
+      an external interrupt (Auto-wakeup mode).
+
+      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
+  
+
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+             is necessary to configure the RTC to detect the tamper or time stamp event using the
+             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+
+
+/**
+  * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
+  * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD 
+  *        configuration information.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage thresholds corresponding to each
+  *         detection level.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+  /* Set PLS bits according to PVDLevel value */
+  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
+  
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+
+  /* Configure interrupt mode */
+  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+  
+  /* Configure event mode */
+  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+  
+  /* Configure the edge */
+  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+  
+  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enable the Power Voltage Detector (PVD).
+  * @retval None
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_PVDE);  
+}
+
+/**
+  * @brief Disable the Power Voltage Detector (PVD).
+  * @retval None
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);   
+}
+
+
+
+
+/**
+  * @brief Enable the WakeUp PINx functionality.
+  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
+  *         This parameter can be one of the following legacy values which set the default polarity 
+  *         i.e. detection on high level (rising edge):
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
+  *             
+  *         or one of the following value where the user can explicitly specify the enabled pin and
+  *         the chosen polarity:  
+  *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW 
+  *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW 
+  *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW 
+  *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+  *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW 
+  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); 
+  
+  /* Specifies the Wake-Up pin polarity for the event detection 
+    (rising or falling edge) */
+  MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); 
+    
+  /* Enable wake-up pin */
+  SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
+
+    
+}
+
+/**
+  * @brief Disable the WakeUp PINx functionality.
+  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); 
+}
+
+
+/**
+  * @brief Enter Sleep or Low-power Sleep mode.
+  * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) 
+  * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet 
+  *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set 
+  *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the    
+  *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
+  *        Additionally, the clock frequency must be reduced below 2 MHz.
+  *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must 
+  *        be done before calling HAL_PWR_EnterSLEEPMode() API. 
+  * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in 
+  *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.       
+  * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
+  *           This parameter can be one of the following values:
+  *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
+  *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
+  * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as 
+  *        the interrupt wake up source.   
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Set Regulator parameter */
+  if (Regulator == PWR_MAINREGULATOR_ON)
+  {
+    /* If in low-power run mode at this point, exit it */
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
+    {
+      HAL_PWREx_DisableLowPowerRunMode();  
+    } 
+    /* Regulator now in main mode. */
+  }
+  else
+  {
+    /* If in run mode, first move to low-power run mode.
+       The system clock frequency must be below 2 MHz at this point. */
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
+    {
+      HAL_PWREx_EnableLowPowerRunMode();  
+    } 
+  } 
+    
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+  
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+}
+
+
+/**
+  * @brief Enter Stop mode
+  * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
+  *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
+  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.          
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
+  *        only to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.
+  *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).  
+  * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
+  * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
+  *         startup delay is incurred when waking up.
+  *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
+  *         is higher although the startup time is reduced.
+  * @param Regulator: Specifies the regulator state in Stop mode.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON) 
+  * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  
+  if(Regulator == PWR_LOWPOWERREGULATOR_ON)
+  {
+    HAL_PWREx_EnterSTOP1Mode(STOPEntry);
+  }
+  else
+  {
+    HAL_PWREx_EnterSTOP0Mode(STOPEntry);
+  }
+}
+
+/**
+  * @brief Enter Standby mode.
+  * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched 
+  *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
+  *        in which case the regulator is in low-power mode. 
+  *        SRAM1 and register contents are lost except for registers in the Backup domain and 
+  *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
+  *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
+  *        to set RRS bit.   
+  *        The BOR is available.  
+  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
+  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
+  *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
+  *        same.
+  *        These states are effective in Standby mode only if APC bit is set through
+  *        HAL_PWREx_EnablePullUpPullDownConfig() API.        
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Set Stand-by mode */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+
+/**
+  * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. 
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.
+  *       Setting this bit is useful when the processor is expected to run only on
+  *       interruptions handling.         
+  * @retval None
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+  * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
+  * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.          
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+
+/**
+  * @brief Enable CORTEX M4 SEVONPEND bit. 
+  * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.
+  * @retval None
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+  * @brief Disable CORTEX M4 SEVONPEND bit. 
+  * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.         
+  * @retval None
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+
+
+
+/**
+  * @brief PWR PVD interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVDCallback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_PWR_PVDCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h
new file mode 100755
index 0000000..7a2b6ae
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h
@@ -0,0 +1,429 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PWR_H
+#define __STM32L4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level. */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode. */
+}PWR_PVDTypeDef;
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+
+/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
+  * @{
+  */
+#define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */
+#define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */
+#define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */
+#define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */                               
+/**
+  * @}
+  */
+  
+  
+
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */
+#define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */
+/**
+  * @}
+  */
+  
+
+/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
+  * @{
+  */  
+#define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros  PWR Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether or not a specific PWR flag is set.
+  * @param  __FLAG__: specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3.
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5.          
+  *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
+  *                  entered StandBy mode.
+  *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
+  *                 the internal wakeup line.
+  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the 
+  *                 low-power regulator is ready.
+  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the 
+  *                 regulator is ready in main mode or is in low-power mode. 
+  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready 
+  *                 in the selected voltage range or is still changing to the required voltage level.
+  *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
+  *                  below or above the selected PVD threshold.
+  *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
+  *                  is below or above PVM1 threshold (applicable when USB feature is supported).
+  @if STM32L486xx
+  *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
+  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device). 
+  @endif
+  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
+  *                  is below or above PVM3 threshold. 
+  *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
+  *                  is below or above PVM4 threshold.                           
+  *    
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
+                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
+                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
+
+/** @brief  Clear a specific PWR flag.
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3.
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5.
+  *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
+  *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
+  *                  entered Standby mode.
+  * @retval None   
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
+                                         (PWR->SCR  = (__FLAG__)) :\
+                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
+/**
+  * @brief Enable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                   \
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Check whether or not the PVD EXTI interrupt flag is set.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Clear the PVD EXTI interrupt flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @}
+  */
+  
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  PWR_Private_Macros   PWR Private Macros
+  * @{
+  */
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+                                 
+#define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
+                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
+                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
+                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) 
+                                
+#define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+                                          
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
+                                      
+/**
+  * @}
+  */  
+
+/* Include PWR HAL Extended module */
+#include "stm32l4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+  
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+void HAL_PWR_PVDCallback(void);
+
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c
new file mode 100755
index 0000000..9280365
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c
@@ -0,0 +1,1264 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Extended Initialization and de-initialization functions
+  *           + Extended Peripheral Control functions
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x00000003) /* PH0/PH1 */
+#elif defined (STM32L496xx) || defined (STM32L4A6xx)
+#define PWR_PORTH_AVAILABLE_PINS   ((uint32_t)0x0000FFFF) /* PH0..PH15 */
+#endif
+
+#if defined (STM32L496xx) || defined (STM32L4A6xx)
+#define PWR_PORTI_AVAILABLE_PINS   ((uint32_t)0x00000FFF) /* PI0..PI11 */
+#endif
+
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
+  * @{
+  */
+  
+/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
+  * @{
+  */ 
+#define PVM_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVM threshold crossing */
+#define PVM_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVM threshold crossing        */
+#define PVM_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVM trigger                 */
+#define PVM_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVM trigger                */
+/**
+  * @}
+  */
+  
+/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
+  * @{
+  */ 
+#define PWR_FLAG_SETTING_DELAY_US                      50   /*!< Time out value for REGLPF and VOSF flags setting */
+/**
+  * @}
+  */
+    
+  
+
+/**
+  * @}
+  */
+
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+  
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
+  *  @brief   Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Extended Peripheral Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+
+@endverbatim
+  * @{
+  */
+  
+
+/**
+  * @brief Return Voltage Scaling Range.
+  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
+  */  
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+  return  (PWR->CR1 & PWR_CR1_VOS);
+}
+
+  
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @param  VoltageScaling: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
+  *                                                typical output voltage at 1.2 V,  
+  *                                                system frequency up to 80 MHz.
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
+  *                                                typical output voltage at 1.0 V,                
+  *                                                system frequency up to 26 MHz.
+  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
+  *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
+  *        When moving from Range 2 to Range 1, the system frequency can be increased to
+  *        a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
+  * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
+  *        cleared before returning the status. If the flag is not cleared within
+  *        50 microseconds, HAL_TIMEOUT status is reported.                    
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t wait_loop_index = 0;  
+
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+  
+  /* If Set Range 1 */
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
+  {
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
+    {
+      /* Set Range 1 */
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+      
+      /* Wait until VOSF is cleared */      
+      wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
+      while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
+      {
+        wait_loop_index--;
+      }
+      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else
+  {
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
+    {
+      /* Set Range 2 */
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
+      /* No need to wait for VOSF to be cleared for this transition */
+    }
+  }
+  
+  return HAL_OK;
+}  
+
+
+/**
+  * @brief Enable battery charging.
+  *        When VDD is present, charge the external battery on VBAT thru an internal resistor.  
+  * @param  ResistorSelection: specifies the resistor impedance.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
+  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor 
+  * @retval None
+  */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
+{
+  assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
+  
+  /* Specify resistor selection */
+  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
+  
+  /* Enable battery charging */
+  SET_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+
+/**
+  * @brief Disable battery charging.  
+  * @retval None
+  */
+void HAL_PWREx_DisableBatteryCharging(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 
+}  
+
+
+#if defined(PWR_CR2_USV)
+/**
+  * @brief Enable VDDUSB supply. 
+  * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.  
+  * @retval None
+  */
+void HAL_PWREx_EnableVddUSB(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+
+/**
+  * @brief Disable VDDUSB supply. 
+  * @retval None
+  */
+void HAL_PWREx_DisableVddUSB(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
+}
+#endif /* PWR_CR2_USV */
+
+#if defined(PWR_CR2_IOSV)
+/**
+  * @brief Enable VDDIO2 supply. 
+  * @note  Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. 
+  * @retval None
+  */
+void HAL_PWREx_EnableVddIO2(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+
+/**
+  * @brief Disable VDDIO2 supply. 
+  * @retval None
+  */
+void HAL_PWREx_DisableVddIO2(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+#endif /* PWR_CR2_IOSV */
+
+
+/**
+  * @brief Enable Internal Wake-up Line. 
+  * @retval None
+  */
+void HAL_PWREx_EnableInternalWakeUpLine(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+
+/**
+  * @brief Disable Internal Wake-up Line. 
+  * @retval None
+  */
+void HAL_PWREx_DisableInternalWakeUpLine(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+
+
+/**
+  * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
+  * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in 
+  *        pull-up state in Standby and Shutdown modes. 
+  * @note  This state is effective in Standby and Shutdown modes only if APC bit 
+  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+  * @note  The configuration is lost when exiting the Shutdown mode due to the 
+  *        power-on reset, maintained when exiting the Standby mode. 
+  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+  *        PDy bit of PWR_PDCRx register is cleared unless it is reserved. 
+  * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input 
+  *        parameter at the same time are set.     
+  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less  
+  *         I/O pins are available) or the logical OR of several of them to set 
+  *         several bits for a given port in a single API call.    
+  * @retval HAL Status
+  */   
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{  
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+       break;
+    case PWR_GPIO_B:
+       SET_BIT(PWR->PUCRB, GPIONumber);
+       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+       break;
+    case PWR_GPIO_C:
+       SET_BIT(PWR->PUCRC, GPIONumber);
+       CLEAR_BIT(PWR->PDCRC, GPIONumber);
+       break;
+#if defined(GPIOD)
+    case PWR_GPIO_D:
+       SET_BIT(PWR->PUCRD, GPIONumber);
+       CLEAR_BIT(PWR->PDCRD, GPIONumber);
+       break;
+#endif
+#if defined(GPIOE)
+    case PWR_GPIO_E:
+       SET_BIT(PWR->PUCRE, GPIONumber);
+       CLEAR_BIT(PWR->PDCRE, GPIONumber);
+       break;
+#endif
+#if defined(GPIOF)
+    case PWR_GPIO_F:
+       SET_BIT(PWR->PUCRF, GPIONumber);
+       CLEAR_BIT(PWR->PDCRF, GPIONumber);
+       break;
+#endif
+#if defined(GPIOG)
+    case PWR_GPIO_G:
+       SET_BIT(PWR->PUCRG, GPIONumber);
+       CLEAR_BIT(PWR->PDCRG, GPIONumber);
+       break;
+#endif
+    case PWR_GPIO_H:
+       SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
+#if defined (STM32L496xx) || defined (STM32L4A6xx)
+       CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
+#else       
+       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
+#endif       
+       break;
+#if defined(GPIOI)
+    case PWR_GPIO_I:
+       SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
+       CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
+       break;
+#endif
+    default:
+       return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
+  * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
+  *        in pull-up state in Standby and Shutdown modes.
+  * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input 
+  *        parameter at the same time are reset.      
+  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 
+  *          (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less  
+  *         I/O pins are available) or the logical OR of several of them to reset 
+  *         several bits for a given port in a single API call. 
+  * @retval HAL Status
+  */   
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{  
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+  
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+       break;
+    case PWR_GPIO_B:
+       CLEAR_BIT(PWR->PUCRB, GPIONumber);
+       break;
+    case PWR_GPIO_C:
+       CLEAR_BIT(PWR->PUCRC, GPIONumber);
+       break;
+#if defined(GPIOD)
+    case PWR_GPIO_D:
+       CLEAR_BIT(PWR->PUCRD, GPIONumber);
+       break;
+#endif
+#if defined(GPIOE)
+    case PWR_GPIO_E:
+       CLEAR_BIT(PWR->PUCRE, GPIONumber);
+       break;
+#endif
+#if defined(GPIOF)
+    case PWR_GPIO_F:
+       CLEAR_BIT(PWR->PUCRF, GPIONumber);
+       break;
+#endif
+#if defined(GPIOG)
+    case PWR_GPIO_G:
+       CLEAR_BIT(PWR->PUCRG, GPIONumber);
+       break;
+#endif
+    case PWR_GPIO_H:    
+       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
+       break;
+#if defined(GPIOI)
+    case PWR_GPIO_I:
+       CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
+       break;
+#endif
+    default:
+       return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
+  * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in 
+  *        pull-down state in Standby and Shutdown modes. 
+  * @note  This state is effective in Standby and Shutdown modes only if APC bit
+  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 
+  * @note  The configuration is lost when exiting the Shutdown mode due to the 
+  *        power-on reset, maintained when exiting the Standby mode. 
+  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+  *        PUy bit of PWR_PUCRx register is cleared unless it is reserved. 
+  * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input 
+  *        parameter at the same time are set.         
+  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less  
+  *         I/O pins are available) or the logical OR of several of them to set 
+  *         several bits for a given port in a single API call. 
+  * @retval HAL Status
+  */   
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+  
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+       break;
+    case PWR_GPIO_B:
+       SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+       CLEAR_BIT(PWR->PUCRB, GPIONumber);
+       break;
+    case PWR_GPIO_C:
+       SET_BIT(PWR->PDCRC, GPIONumber);
+       CLEAR_BIT(PWR->PUCRC, GPIONumber);
+       break;
+#if defined(GPIOD)
+    case PWR_GPIO_D:
+       SET_BIT(PWR->PDCRD, GPIONumber);
+       CLEAR_BIT(PWR->PUCRD, GPIONumber);
+       break;
+#endif
+#if defined(GPIOE)
+    case PWR_GPIO_E:
+       SET_BIT(PWR->PDCRE, GPIONumber);
+       CLEAR_BIT(PWR->PUCRE, GPIONumber);
+       break;
+#endif
+#if defined(GPIOF)
+    case PWR_GPIO_F:
+       SET_BIT(PWR->PDCRF, GPIONumber);
+       CLEAR_BIT(PWR->PUCRF, GPIONumber);
+       break;
+#endif
+#if defined(GPIOG)
+    case PWR_GPIO_G:
+       SET_BIT(PWR->PDCRG, GPIONumber);
+       CLEAR_BIT(PWR->PUCRG, GPIONumber);
+       break;
+#endif
+    case PWR_GPIO_H:
+#if defined (STM32L496xx) || defined (STM32L4A6xx)
+       SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
+#else       
+       SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
+#endif  
+       CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
+       break;
+#if defined(GPIOI)
+    case PWR_GPIO_I:
+       SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
+       CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
+       break;
+#endif
+    default:
+       return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
+  * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
+  *        in pull-down state in Standby and Shutdown modes. 
+  * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input 
+  *        parameter at the same time are reset.   
+  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less  
+  *         I/O pins are available) or the logical OR of several of them to reset 
+  *         several bits for a given port in a single API call. 
+  * @retval HAL Status
+  */   
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+   
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+       break;
+    case PWR_GPIO_B:
+       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+       break; 
+    case PWR_GPIO_C:
+       CLEAR_BIT(PWR->PDCRC, GPIONumber);
+       break;
+#if defined(GPIOD)
+    case PWR_GPIO_D:
+       CLEAR_BIT(PWR->PDCRD, GPIONumber);
+       break;
+#endif
+#if defined(GPIOE)
+    case PWR_GPIO_E:
+       CLEAR_BIT(PWR->PDCRE, GPIONumber);
+       break;
+#endif
+#if defined(GPIOF) 
+    case PWR_GPIO_F:
+       CLEAR_BIT(PWR->PDCRF, GPIONumber);
+       break;
+#endif
+#if defined(GPIOG)
+    case PWR_GPIO_G:
+       CLEAR_BIT(PWR->PDCRG, GPIONumber);
+       break;
+#endif
+    case PWR_GPIO_H:
+#if defined (STM32L496xx) || defined (STM32L4A6xx)
+       CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
+#else       
+       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
+#endif     
+       break; 
+#if defined(GPIOI)
+    case PWR_GPIO_I:
+       CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
+       break;
+#endif
+    default:
+       return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief Enable pull-up and pull-down configuration.
+  * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in 
+  *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.    
+  * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
+  *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). 
+  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there 
+  *        is no conflict when setting PUy or PDy bit.         
+  * @retval None
+  */
+void HAL_PWREx_EnablePullUpPullDownConfig(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+
+/**
+  * @brief Disable pull-up and pull-down configuration.
+  * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in 
+  *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.     
+  * @retval None
+  */
+void HAL_PWREx_DisablePullUpPullDownConfig(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+
+
+/**
+  * @brief Enable SRAM2 content retention in Standby mode.
+  * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in 
+  *         Standby mode and its content is kept.    
+  * @retval None
+  */
+void HAL_PWREx_EnableSRAM2ContentRetention(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+
+/**
+  * @brief Disable SRAM2 content retention in Standby mode.
+  * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode 
+  *        and its content is lost.      
+  * @retval None
+  */
+void HAL_PWREx_DisableSRAM2ContentRetention(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+
+
+
+#if defined(PWR_CR2_PVME1)
+/**
+  * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM1(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_1);    
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM1(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_1);    
+}
+#endif /* PWR_CR2_PVME1 */
+
+
+#if defined(PWR_CR2_PVME2)
+/**
+  * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM2(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_2);    
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM2(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_2);    
+}
+#endif /* PWR_CR2_PVME2 */
+
+
+/**
+  * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM3(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_3);    
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM3(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_3);    
+}
+
+
+/**
+  * @brief Enable the Power Voltage Monitoring 4:  VDDA versus 2.2V.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM4(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_4);    
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 4:  VDDA versus 2.2V.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM4(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_4);    
+}
+
+
+
+
+/**
+  * @brief Configure the Peripheral Voltage Monitoring (PVM).
+  * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
+  *        PVM configuration information.
+  * @note The API configures a single PVM according to the information contained 
+  *       in the input structure. To configure several PVMs, the API must be singly 
+  *       called for each PVM used.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage thresholds corresponding to each
+  *         detection level and to each monitored supply.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
+{  
+  /* Check the parameters */
+  assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
+  assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
+
+
+  /* Configure EXTI 35 to 38 interrupts if so required:
+     scan thru PVMType to detect which PVMx is set and
+     configure the corresponding EXTI line accordingly. */
+  switch (sConfigPVM->PVMType)
+  {
+#if defined(PWR_CR2_PVME1)  
+    case PWR_PVM_1:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM1_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); 
+      __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_IT();
+      }
+  
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
+      }
+  
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
+      }
+  
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break; 
+#endif /* PWR_CR2_PVME1 */        
+    
+#if defined(PWR_CR2_PVME2)    
+    case PWR_PVM_2:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM2_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); 
+      __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_IT();
+      }
+  
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
+      }
+  
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
+      }
+  
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+#endif /* PWR_CR2_PVME2 */      
+      
+    case PWR_PVM_3:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM3_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); 
+      __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_IT();
+      }
+  
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
+      }
+  
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
+      }
+  
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+      
+    case PWR_PVM_4:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM4_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); 
+      __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_IT();
+      }
+  
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
+      }
+  
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
+      }
+  
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;  
+      
+    default:
+      return HAL_ERROR;                      
+    
+  }   
+
+  
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief Enter Low-power Run mode
+  * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.  
+  * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the 
+  *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
+  *        Additionally, the clock frequency must be reduced below 2 MHz.
+  *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must 
+  *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.     
+  * @retval None
+  */
+void HAL_PWREx_EnableLowPowerRunMode(void)
+{
+  /* Set Regulator parameter */
+  SET_BIT(PWR->CR1, PWR_CR1_LPR); 
+}
+
+
+/**
+  * @brief Exit Low-power Run mode.
+  * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that 
+  *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode 
+  *        returns HAL_TIMEOUT status). The system clock frequency can then be
+  *        increased above 2 MHz.   
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
+{
+  uint32_t wait_loop_index = 0;
+  
+  /* Clear LPR bit */
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 
+
+  /* Wait until REGLPF is reset */
+  wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
+  while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
+  {
+    wait_loop_index--;
+  }
+  if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enter Stop 0 mode.
+  * @note  In Stop 0 mode, main and low voltage regulators are ON.
+  * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
+  *        only to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.
+  * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
+  * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption
+  *         is higher although the startup time is reduced.
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+    
+  /* Stop 0 mode with Main Regulator */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+
+/**
+  * @brief Enter Stop 1 mode.
+  * @note  In Stop 1 mode, only low power voltage regulator is ON.
+  * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
+  *        only to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.
+  * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
+  * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+    
+  /* Stop 1 mode with Low-Power Regulator */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+
+/**
+  * @brief Enter Stop 2 mode.
+  * @note  In Stop 2 mode, only low power voltage regulator is ON.
+  * @note  In Stop 2 mode, all I/O pins keep the same state as in Run mode.
+  * @note  All clocks in the VCORE domain are stopped, the PLL, the MSI, 
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability 
+  *        (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after 
+  *        receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only 
+  *        to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.   
+  *        The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
+  *        Otherwise, Stop 1 mode is entered.  
+  * @note  When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.     
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+  /* Set Stop mode 2 */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+
+
+
+
+/**
+  * @brief Enter Shutdown mode. 
+  * @note  In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched 
+  *        off. The voltage regulator is disabled and Vcore domain is powered off. 
+  *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
+  *        The BOR is not available.  
+  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.  
+  * @retval None
+  */
+void HAL_PWREx_EnterSHUTDOWNMode(void)
+{
+  
+  /* Set Shutdown mode */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+
+
+/**
+  * @brief This function handles the PWR PVD/PVMx interrupt request.
+  * @note This API should be called under the PVD_PVM_IRQHandler().  
+  * @retval None
+  */
+void HAL_PWREx_PVD_PVM_IRQHandler(void)
+{
+  /* Check PWR exti flag */
+  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+  {
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback();
+
+    /* Clear PVD exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+  }
+  /* Next, successively check PVMx exti flags */
+#if defined(PWR_CR2_PVME1)  
+  if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) 
+  {
+    /* PWR PVM1 interrupt user callback */
+    HAL_PWREx_PVM1Callback();
+   
+    /* Clear PVM1 exti pending bit */
+    __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
+  }
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)  
+  if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) 
+  {
+    /* PWR PVM2 interrupt user callback */
+    HAL_PWREx_PVM2Callback();
+   
+    /* Clear PVM2 exti pending bit */
+    __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
+  }
+#endif /* PWR_CR2_PVME2 */  
+  if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) 
+  {
+    /* PWR PVM3 interrupt user callback */
+    HAL_PWREx_PVM3Callback();
+   
+    /* Clear PVM3 exti pending bit */
+    __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
+  }
+  if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) 
+  {
+    /* PWR PVM4 interrupt user callback */
+    HAL_PWREx_PVM4Callback();
+   
+    /* Clear PVM4 exti pending bit */
+    __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
+  }      
+}
+
+
+#if defined(PWR_CR2_PVME1)
+/**
+  * @brief PWR PVM1 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM1Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM1Callback() API can be implemented in the user file
+   */
+}
+#endif /* PWR_CR2_PVME1 */
+
+#if defined(PWR_CR2_PVME2)
+/**
+  * @brief PWR PVM2 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM2Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM2Callback() API can be implemented in the user file
+   */
+}
+#endif /* PWR_CR2_PVME2 */
+
+/**
+  * @brief PWR PVM3 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM3Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM3Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief PWR PVM4 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM4Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM4Callback() API can be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h
new file mode 100755
index 0000000..8d04403
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h
@@ -0,0 +1,888 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of PWR HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PWR_EX_H
+#define __STM32L4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+  * @{
+  */
+
+
+/**
+  * @brief  PWR PVM configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold. 
+                           This parameter can be a value of @ref PWREx_PVM_Type. 
+                           @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 
+@if STM32L486xx
+                           @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 
+@endif
+                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 
+                           @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWREx_PVM_Mode. */
+}PWR_PVMTypeDef;
+
+/**
+  * @}
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
+  * @{
+  */
+#define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */
+/**
+  * @}
+  */  
+
+
+/** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
+  * @{
+  */                                                      
+#define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
+#define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
+#define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
+#define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
+#define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
+  * @{
+  */
+#if defined(PWR_CR2_PVME1)    
+#define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)  
+#define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
+#define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
+/**
+  * @}
+  */  
+  
+/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
+  * @{
+  */
+#define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
+#define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+  
+  
+
+/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
+  * @{
+  */
+#define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR1_VOS_0     /*!< Voltage scaling range 1 */
+#define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR1_VOS_1     /*!< Voltage scaling range 2 */
+/**
+  * @}
+  */
+
+  
+/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5          ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+  
+/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_DISABLE        ((uint32_t)0x00000000)
+#define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
+  * @{
+  */
+#define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
+#define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
+#define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
+#define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
+#define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
+#define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
+#define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
+#define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
+#define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
+#define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
+#define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
+#define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
+#define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
+#define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */
+#define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */
+#define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_GPIO GPIO port
+  * @{
+  */
+#define PWR_GPIO_A   0x00000000      /*!< GPIO port A */
+#define PWR_GPIO_B   0x00000001      /*!< GPIO port B */
+#define PWR_GPIO_C   0x00000002      /*!< GPIO port C */
+#if defined(GPIOD_BASE)    
+#define PWR_GPIO_D   0x00000003      /*!< GPIO port D */
+#endif
+#if defined(GPIOE_BASE) 
+#define PWR_GPIO_E   0x00000004      /*!< GPIO port E */
+#endif
+#if defined(GPIOF_BASE)   
+#define PWR_GPIO_F   0x00000005      /*!< GPIO port F */
+#endif
+#if defined(GPIOG_BASE)  
+#define PWR_GPIO_G   0x00000006      /*!< GPIO port G */
+#endif
+#define PWR_GPIO_H   0x00000007      /*!< GPIO port H */
+#if defined(GPIOI_BASE) 
+#define PWR_GPIO_I   0x00000008      /*!< GPIO port I */
+#endif
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
+  * @{
+  */    
+#if defined(PWR_CR2_PVME1) 
+#define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
+#define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
+  * @{
+  */    
+#if defined(PWR_CR2_PVME1) 
+#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */
+#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_Flag  PWR Status Flags
+  *        Elements values convention: 0000 0000 0XXY YYYYb
+  *           - Y YYYY  : Flag position in the XX register (5 bits)
+  *           - XX  : Status register (2 bits)
+  *                 - 01: SR1 register
+  *                 - 10: SR2 register
+  *        The only exception is PWR_FLAG_WU, encompassing all
+  *        wake-up flags and set to PWR_SR1_WUF.    
+  * @{   
+  */  
+#define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */
+#define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */
+#define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */
+#define PWR_FLAG_WUF4                       ((uint32_t)0x0023)   /*!< Wakeup event on wakeup pin 4 */
+#define PWR_FLAG_WUF5                       ((uint32_t)0x0024)   /*!< Wakeup event on wakeup pin 5 */
+#define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
+#define PWR_FLAG_SB                         ((uint32_t)0x0028)   /*!< Standby flag */
+#define PWR_FLAG_WUFI                       ((uint32_t)0x002F)   /*!< Wakeup on internal wakeup line */
+
+#define PWR_FLAG_REGLPS                     ((uint32_t)0x0048)   /*!< Low-power regulator start flag */
+#define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */
+#define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */
+#define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */
+#if defined(PWR_CR2_PVME1)
+#define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */
+#define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */
+/**
+  * @}
+  */        
+
+/**
+  * @}
+  */  
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+ * @{
+ */
+
+#if defined(PWR_CR2_PVME1)
+/**
+  * @brief Enable the PVM1 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+
+/**
+  * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM1 Line Status.
+  */
+#define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Clear the PVM1 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
+
+#endif /* PWR_CR2_PVME1 */
+
+
+#if defined(PWR_CR2_PVME2)
+/**
+  * @brief Enable the PVM2 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+
+/**
+  * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+  
+/**
+  * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM2 Line Status.
+  */
+#define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Clear the PVM2 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
+
+#endif /* PWR_CR2_PVME2 */
+
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+
+/**
+  * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+  
+/**
+  * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM3 Line Status.
+  */
+#define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Clear the PVM3 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
+
+
+
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+  
+/**
+  * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
+  * @retval EXTI PVM4 Line Status.
+  */
+#define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Clear the PVM4 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
+  *                                                typical output voltage at 1.2 V,  
+  *                                                system frequency up to 80 MHz.
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
+  *                                                typical output voltage at 1.0 V,                
+  *                                                system frequency up to 26 MHz.  
+  * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
+  *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
+  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.   
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg;                               \
+                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
+                                                            UNUSED(tmpreg);                                     \
+                                                          } while(0)
+
+/**
+  * @}
+  */
+  
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
+  * @{
+  */
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+                                ((PIN) == PWR_WAKEUP_PIN2) || \
+                                ((PIN) == PWR_WAKEUP_PIN3) || \
+                                ((PIN) == PWR_WAKEUP_PIN4) || \
+                                ((PIN) == PWR_WAKEUP_PIN5) || \
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW))
+                                
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
+                               ((TYPE) == PWR_PVM_2) ||\
+                               ((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#elif defined (STM32L471xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
+                               ((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#endif
+
+#if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
+                               ((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#endif                                  
+
+#define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
+                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))  
+                                
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+                                             
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))  
+                                                  
+#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
+                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 
+                                           
+#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
+                                           
+                             
+#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_D) ||\
+                           ((GPIO) == PWR_GPIO_E) ||\
+                           ((GPIO) == PWR_GPIO_H))
+#elif defined (STM32L432xx) || defined (STM32L442xx)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_H))
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_D) ||\
+                           ((GPIO) == PWR_GPIO_E) ||\
+                           ((GPIO) == PWR_GPIO_F) ||\
+                           ((GPIO) == PWR_GPIO_G) ||\
+                           ((GPIO) == PWR_GPIO_H))
+#elif defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_D) ||\
+                           ((GPIO) == PWR_GPIO_E) ||\
+                           ((GPIO) == PWR_GPIO_F) ||\
+                           ((GPIO) == PWR_GPIO_G) ||\
+                           ((GPIO) == PWR_GPIO_H) ||\
+                           ((GPIO) == PWR_GPIO_I))
+#endif
+
+
+/**
+  * @}
+  */  
+  
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 
+  * @{
+  */
+
+
+/* Peripheral Control functions  **********************************************/
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
+void HAL_PWREx_DisableBatteryCharging(void);          
+#if defined(PWR_CR2_USV)
+void HAL_PWREx_EnableVddUSB(void);
+void HAL_PWREx_DisableVddUSB(void);
+#endif /* PWR_CR2_USV */
+#if defined(PWR_CR2_IOSV)
+void HAL_PWREx_EnableVddIO2(void);
+void HAL_PWREx_DisableVddIO2(void);
+#endif /* PWR_CR2_IOSV */
+void HAL_PWREx_EnableInternalWakeUpLine(void);
+void HAL_PWREx_DisableInternalWakeUpLine(void);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+void HAL_PWREx_EnablePullUpPullDownConfig(void);
+void HAL_PWREx_DisablePullUpPullDownConfig(void);
+void HAL_PWREx_EnableSRAM2ContentRetention(void);
+void HAL_PWREx_DisableSRAM2ContentRetention(void);
+#if defined(PWR_CR2_PVME1)
+void HAL_PWREx_EnablePVM1(void);
+void HAL_PWREx_DisablePVM1(void);
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+void HAL_PWREx_EnablePVM2(void);
+void HAL_PWREx_DisablePVM2(void);
+#endif /* PWR_CR2_PVME2 */
+void HAL_PWREx_EnablePVM3(void);
+void HAL_PWREx_DisablePVM3(void);
+void HAL_PWREx_EnablePVM4(void);
+void HAL_PWREx_DisablePVM4(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
+
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWREx_EnableLowPowerRunMode(void);
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSHUTDOWNMode(void);
+
+void HAL_PWREx_PVD_PVM_IRQHandler(void);
+#if defined(PWR_CR2_PVME1) 
+void HAL_PWREx_PVM1Callback(void);
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+void HAL_PWREx_PVM2Callback(void);
+#endif /* PWR_CR2_PVME2 */
+void HAL_PWREx_PVM3Callback(void);
+void HAL_PWREx_PVM4Callback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c
new file mode 100755
index 0000000..1beb35b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c
@@ -0,0 +1,2345 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_qspi.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   QSPI HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the QuadSPI interface (QSPI).
+  *           + Initialization and de-initialization functions
+  *           + Indirect functional mode management
+  *           + Memory-mapped functional mode management
+  *           + Auto-polling functional mode management
+  *           + Interrupts and flags management
+  *           + DMA channel configuration for indirect functional mode
+  *           + Errors management and abort functionality
+  *
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    *** Initialization ***
+    ======================
+    [..]
+      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
+        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure QuadSPI global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel 
+            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), 
+            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure 
+            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
+          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
+
+    *** Indirect functional mode ***
+    ================================
+    [..]
+      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() 
+          functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used and if present the number of bytes.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+      (#) If no data is required for the command, it is sent directly to the memory :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or 
+          HAL_QSPI_Transmit_IT() after the command configuration :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
+             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and 
+             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or 
+          HAL_QSPI_Receive_IT() after the command configuration :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
+             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and 
+             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+
+    *** Auto-polling functional mode ***
+    ====================================
+    [..]
+      (#) Configure the command sequence and the auto-polling functional mode using the 
+          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+             the polling interval and the automatic stop activation.
+      (#) After the configuration :
+         (++) In polling mode, the output of the function is done when the status match is reached. The
+             automatic stop is activated to avoid an infinite loop.
+         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+    *** Memory-mapped functional mode ***
+    =====================================
+    [..]
+      (#) Configure the command sequence and the memory-mapped functional mode using the 
+          HAL_QSPI_MemoryMapped() functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and the size.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The timeout activation and the timeout period.
+      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on 
+          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
+
+    *** Errors management and abort functionality ***
+    =================================================
+    [..]
+      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
+      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and 
+          flushes the fifo :
+         (++) In polling mode, the output of the function is done when the transfer 
+              complete bit is set and the busy bit cleared.
+         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when 
+              the transfer complete bi is set.
+
+    *** Control functions ***
+    =========================
+    [..]
+      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
+      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
+      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
+      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold 
+
+    *** Workarounds linked to Silicon Limitation ***
+    ====================================================
+    [..]
+      (#) Workarounds Implemented inside HAL Driver
+         (++) Extra data written in the FIFO at the end of a read transfer
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup QSPI QSPI
+  * @brief QSPI HAL module driver
+  * @{
+  */
+#ifdef HAL_QSPI_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Constants QSPI Private Constants
+  * @{
+  */
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)          /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+  * @{
+  */
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma); 
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
+  * @{
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions 
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim    
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Initialize the QuadSPI.
+      (+) De-initialize the QuadSPI.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initialize the QSPI mode according to the specified parameters
+  *        in the QSPI_InitTypeDef and initialize the associated handle.
+  * @param hqspi: QSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check the QSPI handle allocation */
+  if(hqspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
+  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
+  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
+  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
+  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
+  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
+  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx) 
+  assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
+
+  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
+  {
+    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
+  }
+#endif
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+  
+  if(hqspi->State == HAL_QSPI_STATE_RESET)
+  {  
+    /* Allocate lock resource and initialize it */
+    hqspi->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_QSPI_MspInit(hqspi);
+    
+    /* Configure the default timeout for the QSPI memory access */
+    HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+  }
+  
+  /* Configure QSPI FIFO Threshold */
+  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, 
+             ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
+
+  /* Wait till BUSY flag reset */
+  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
+  if(status == HAL_OK)
+  {
+    /* Configure QSPI Clock Prescaler and Sample Shift */
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx) 
+    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), 
+               ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) | 
+                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
+#else
+    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), 
+               ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) | 
+                hqspi->Init.SampleShifting));
+#endif
+    
+    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
+    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), 
+               ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) | 
+                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
+    /* Enable the QSPI peripheral */
+    __HAL_QSPI_ENABLE(hqspi);
+  
+    /* Set QSPI error code to none */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;  
+
+    /* Initialize the QSPI state */
+    hqspi->State = HAL_QSPI_STATE_READY;
+  }
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief De-Initialize the QSPI peripheral. 
+  * @param hqspi: QSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Check the QSPI handle allocation */
+  if(hqspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  /* Disable the QSPI Peripheral Clock */
+  __HAL_QSPI_DISABLE(hqspi);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_QSPI_MspDeInit(hqspi);
+
+  /* Set QSPI error code to none */
+  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+  /* Initialize the QSPI state */
+  hqspi->State = HAL_QSPI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the QSPI MSP.
+  * @param hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_MspInit can be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief DeInitialize the QSPI MSP.
+  * @param hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_MspDeInit can be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions 
+  *  @brief QSPI Transmit/Receive functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Handle the interrupts.
+      (+) Handle the command sequence.
+      (+) Transmit data in blocking, interrupt or DMA mode.
+      (+) Receive data in blocking, interrupt or DMA mode.
+      (+) Manage the auto-polling functional mode.
+      (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Handle QSPI interrupt request.
+  * @param hqspi: QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
+{
+  __IO uint32_t *data_reg;
+  uint32_t flag = READ_REG(hqspi->Instance->SR);
+  uint32_t itsource = READ_REG(hqspi->Instance->CR);
+
+  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
+  if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT))
+  {
+    data_reg = &hqspi->Instance->DR;
+
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+    {
+      /* Transmission process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+      {
+        if (hqspi->TxXferCount > 0)
+        {
+          /* Fill the FIFO until the threshold is reached */
+          *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+          hqspi->TxXferCount--;
+        }
+        else
+        {
+          /* No more data available for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+          break;
+        }
+      }
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+    {
+      /* Receiving Process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+      {
+        if (hqspi->RxXferCount > 0)
+        {
+          /* Read the FIFO until the threshold is reached */
+          *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+          hqspi->RxXferCount--;
+        }
+        else
+        {
+          /* All data have been received for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+          break;
+        }
+      }
+    }
+    
+    /* FIFO Threshold callback */
+    HAL_QSPI_FifoThresholdCallback(hqspi);
+  }
+
+  /* QSPI Transfer Complete interrupt occurred -------------------------------*/
+  else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
+
+    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+    
+    /* Transfer complete callback */
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+    {
+      if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
+      {
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+      
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+      /* Clear Busy bit */
+      HAL_QSPI_Abort_IT(hqspi);
+#endif
+      
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* TX Complete callback */
+      HAL_QSPI_TxCpltCallback(hqspi);
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+    {
+      if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
+      {
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+      else
+      {
+        data_reg = &hqspi->Instance->DR;
+        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
+        {
+          if (hqspi->RxXferCount > 0)
+          {
+            /* Read the last data received in the FIFO until it is empty */
+            *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+            hqspi->RxXferCount--;
+          }
+          else
+          {
+            /* All data have been received for the transfer */
+            break;
+          }
+        }
+      }
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+      /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+      HAL_QSPI_Abort_IT(hqspi);
+#endif
+      
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* RX Complete callback */
+      HAL_QSPI_RxCpltCallback(hqspi);
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY)
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* Command Complete callback */
+      HAL_QSPI_CmdCpltCallback(hqspi);
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_ABORT)
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
+      {
+        /* Abort called by the user */
+
+        /* Abort Complete callback */
+        HAL_QSPI_AbortCpltCallback(hqspi);
+      }
+      else 
+      {
+        /* Abort due to an error (eg :  DMA error) */
+
+        /* Error callback */
+        HAL_QSPI_ErrorCallback(hqspi);
+      }
+    }
+  }
+
+  /* QSPI Status Match interrupt occurred ------------------------------------*/
+  else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
+   
+    /* Check if the automatic poll mode stop is activated */
+    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
+    {
+      /* Disable the QSPI Transfer Error and Status Match Interrupts */
+      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+
+    /* Status match callback */
+    HAL_QSPI_StatusMatchCallback(hqspi);
+  }
+
+  /* QSPI Transfer Error interrupt occurred ----------------------------------*/
+  else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
+    
+    /* Disable all the QSPI Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+    /* Set error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
+    
+    if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      
+      /* Disable the DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      HAL_DMA_Abort_IT(hqspi->hdma);
+    }
+    else
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+      
+      /* Error callback */
+      HAL_QSPI_ErrorCallback(hqspi);
+    }
+  }
+
+  /* QSPI Timeout interrupt occurred -----------------------------------------*/
+  else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
+    
+    /* Timeout callback */
+    HAL_QSPI_TimeOutCallback(hqspi);
+  }
+}
+
+/**
+  * @brief Set the command configuration. 
+  * @param hqspi: QSPI handle
+  * @param cmd : structure that contains the command configuration information
+  * @param Timeout : Timeout duration
+  * @note   This function is used only in Indirect Read or Write Modes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_BUSY;   
+    
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+    
+    if (status == HAL_OK)
+    {
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+      
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* When there is no data phase, the transfer start as soon as the configuration is done 
+        so wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+          
+          /* Update QSPI state */
+          hqspi->State = HAL_QSPI_STATE_READY;   
+        }
+      }
+      else
+      {
+        /* Update QSPI state */
+        hqspi->State = HAL_QSPI_STATE_READY;   
+      }
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;   
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief Set the command configuration in interrupt mode. 
+  * @param hqspi: QSPI handle
+  * @param cmd : structure that contains the command configuration information
+  * @note   This function is used only in Indirect Read or Write Modes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_BUSY;   
+    
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+    
+    if (status == HAL_OK)
+    {
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+      }
+      
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+      
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* When there is no data phase, the transfer start as soon as the configuration is done 
+        so activate TC and TE interrupts */
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+
+        /* Enable the QSPI Transfer Error Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+      }
+      else
+      {
+        /* Update QSPI state */
+        hqspi->State = HAL_QSPI_STATE_READY;   
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+      }
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;   
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+  
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief Transmit an amount of data in blocking mode. 
+  * @param hqspi: QSPI handle
+  * @param pData: pointer to data buffer
+  * @param Timeout : Timeout duration
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+      
+      /* Configure counters and size of the handle */
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->pTxBuffPtr = pData;
+    
+      /* Configure QSPI: CCR register with functional as indirect write */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      while(hqspi->TxXferCount > 0)
+      {
+        /* Wait until FT flag is set to send data */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
+
+        if (status != HAL_OK)
+        { 
+          break;
+        }
+
+        *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+        hqspi->TxXferCount--;
+      }
+    
+      if (status == HAL_OK)
+      {
+        /* Wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          /* Clear Transfer Complete bit */
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+          
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+          /* Clear Busy bit */
+          status = HAL_QSPI_Abort(hqspi);
+#endif
+        }
+      }
+    
+      /* Update QSPI state */
+      hqspi->State = HAL_QSPI_STATE_READY;    
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  return status;
+}
+
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @param hqspi: QSPI handle
+  * @param pData: pointer to data buffer
+  * @param Timeout : Timeout duration
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+    
+      /* Configure counters and size of the handle */
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->pRxBuffPtr = pData;
+
+      /* Configure QSPI: CCR register with functional as indirect read */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Start the transfer by re-writing the address in AR register */
+      WRITE_REG(hqspi->Instance->AR, addr_reg);
+      
+      while(hqspi->RxXferCount > 0)
+      {
+        /* Wait until FT or TC flag is set to read received data */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
+
+        if  (status != HAL_OK)
+        { 
+          break;
+        }
+
+        *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+        hqspi->RxXferCount--;
+      }
+    
+      if (status == HAL_OK)
+      {
+        /* Wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if  (status == HAL_OK)
+        { 
+          /* Clear Transfer Complete bit */
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+          /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+          status = HAL_QSPI_Abort(hqspi);
+#endif
+        }
+      }
+
+      /* Update QSPI state */
+      hqspi->State = HAL_QSPI_STATE_READY;    
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with interrupt.
+  * @param  hqspi: QSPI handle
+  * @param  pData: pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{  
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+      /* Configure counters and size of the handle */
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->pTxBuffPtr = pData;
+    
+      /* Configure QSPI: CCR register with functional as indirect write */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+    
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+      
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with interrupt.
+  * @param  hqspi: QSPI handle
+  * @param  pData: pointer to data buffer
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+    
+      /* Configure counters and size of the handle */
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->pRxBuffPtr = pData;
+
+      /* Configure QSPI: CCR register with functional as indirect read */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Start the transfer by re-writing the address in AR register */
+      WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;   
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with DMA. 
+  * @param  hqspi: QSPI handle
+  * @param  pData: pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @note   If DMA peripheral access is configured as halfword, the number 
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number 
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t *tmp;
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Clear the error code */                
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    if(pData != NULL ) 
+    {
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->TxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword 
+          => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 1);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on word 
+          => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 2);
+        }
+      }
+      
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+        
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+        
+        /* Configure size and pointer of the handle */
+        hqspi->TxXferSize = hqspi->TxXferCount;
+        hqspi->pTxBuffPtr = pData;
+        
+        /* Configure QSPI: CCR register with functional mode as indirect write */
+        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+        
+        /* Set the QSPI DMA transfer complete callback */
+        hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
+        
+        /* Set the QSPI DMA Half transfer complete callback */
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
+        
+        /* Set the DMA error callback */
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+        
+        /* Clear the DMA abort callback */      
+        hqspi->hdma->XferAbortCallback = NULL;
+        
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+        MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
+        
+        /* Enable the QSPI transmit DMA Channel */
+        tmp = (uint32_t*)&pData;
+        HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+        
+        /* Enable the QSPI transfer error Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+        
+        /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      }
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;   
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA. 
+  * @param  hqspi: QSPI handle
+  * @param  pData: pointer to data buffer.
+  * @note   This function is used only in Indirect Read Mode
+  * @note   If DMA peripheral access is configured as halfword, the number 
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number 
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t *tmp;
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Clear the error code */                
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    if(pData != NULL) 
+    {
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->RxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword 
+             => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 1);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on word 
+             => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 2);
+        }
+      }
+       
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+        
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+        
+        /* Configure size and pointer of the handle */
+        hqspi->RxXferSize = hqspi->RxXferCount;
+        hqspi->pRxBuffPtr = pData;
+        
+        /* Set the QSPI DMA transfer complete callback */
+        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
+        
+        /* Set the QSPI DMA Half transfer complete callback */
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
+        
+        /* Set the DMA error callback */
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+        
+        /* Clear the DMA abort callback */      
+        hqspi->hdma->XferAbortCallback = NULL;
+        
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+        MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
+        
+        /* Enable the DMA Channel */
+        tmp = (uint32_t*)&pData;
+        HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
+        
+        /* Configure QSPI: CCR register with functional as indirect read */
+        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+        
+        /* Start the transfer by re-writing the address in AR register */
+        WRITE_REG(hqspi->Instance->AR, addr_reg);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+        
+        /* Enable the QSPI transfer error Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+        
+        /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      }
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY; 
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode. 
+  * @param  hqspi: QSPI handle
+  * @param  cmd: structure that contains the command configuration information.
+  * @param  cfg: structure that contains the polling configuration information.
+  * @param  Timeout : Timeout duration
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+  
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+    
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+    
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+      
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+      
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+      
+      /* Configure QSPI: CR register with Match mode and Automatic stop enabled 
+      (otherwise there will be an infinite loop in blocking mode) */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
+               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+      
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+      
+      /* Wait until SM flag is set to go back in idle state */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
+
+      if (status == HAL_OK)
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+        
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;   
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+  
+  /* Return function status */
+  return status;  
+}
+
+/**
+  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode. 
+  * @param  hqspi: QSPI handle
+  * @param  cmd: structure that contains the command configuration information.
+  * @param  cfg: structure that contains the polling configuration information.
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+  
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+    
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+    
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+      
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+      
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+      
+      /* Configure QSPI: CR register with Match mode and Automatic stop mode */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
+               (cfg->MatchMode | cfg->AutomaticStop));
+      
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
+
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+  
+      /* Enable the QSPI Transfer Error and status match Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;   
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+  
+  /* Return function status */
+  return status;  
+}
+
+/**
+  * @brief  Configure the Memory Mapped mode. 
+  * @param  hqspi: QSPI handle
+  * @param  cmd: structure that contains the command configuration information.
+  * @param  cfg: structure that contains the memory mapped configuration information.
+  * @note   This function is used only in Memory mapped Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
+  
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+  
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
+    
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+    
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: CR register with timeout counter enable */
+      MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+      
+      if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+      {
+        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+        
+        /* Configure QSPI: LPTR register with the low-power timeout value */
+        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
+        
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
+
+        /* Enable the QSPI TimeOut Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
+      }
+      
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;   
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+  
+  /* Return function status */
+  return status;  
+}
+
+/**
+  * @brief  Transfer Error callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Abort completed callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Command completed callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_CmdCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_TxCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  FIFO Threshold callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Status Match callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_StatusMatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_TimeOutCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions 
+  *  @brief   QSPI control and State functions 
+  *
+@verbatim   
+ ===============================================================================
+                  ##### Peripheral Control and State functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Check in run-time the state of the driver. 
+      (+) Check the error code set during last operation.
+      (+) Abort any operation.
+
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the QSPI handle state.
+  * @param  hqspi: QSPI handle
+  * @retval HAL state
+  */
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+{
+  /* Return QSPI handle state */
+  return hqspi->State;
+}
+
+/**
+* @brief  Return the QSPI error code.
+* @param  hqspi: QSPI handle
+* @retval QSPI Error Code
+*/
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+{
+  return hqspi->ErrorCode;
+}
+
+/**
+* @brief  Abort the current transmission.
+* @param  hqspi: QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check if the state is in one of the busy states */
+  if ((hqspi->State & 0x2) != 0)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+
+    if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      
+      /* Abort DMA channel */
+      status = HAL_DMA_Abort(hqspi->hdma);
+      if(status != HAL_OK)
+      {
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+      }
+    }  
+    
+    /* Configure QSPI: CR register with Abort request */
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+    
+    /* Wait until TC flag is set to go back in idle state */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
+
+    if(status == HAL_OK)
+    {
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+      
+      /* Wait until BUSY flag is reset */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+    }
+    
+    if (status == HAL_OK)
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+  }
+
+  return status;
+}
+
+/**
+* @brief  Abort the current transmission (non-blocking function)
+* @param  hqspi: QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check if the state is in one of the busy states */
+  if ((hqspi->State & 0x2) != 0)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+    
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_ABORT;   
+    
+    /* Disable all interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
+    
+    if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      
+      /* Abort DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      HAL_DMA_Abort_IT(hqspi->hdma);
+    }  
+    else
+    {
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+      
+      /* Enable the QSPI Transfer Complete Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+      
+      /* Configure QSPI: CR register with Abort request */
+      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+    }
+  }
+  return status;
+}
+
+/** @brief Set QSPI timeout.
+  * @param  hqspi: QSPI handle.
+  * @param  Timeout: Timeout for the QSPI memory access.
+  * @retval None
+  */
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+  hqspi->Timeout = Timeout;
+}
+
+/** @brief Set QSPI Fifo threshold.
+  * @param  hqspi: QSPI handle.
+  * @param  Threshold: Threshold of the Fifo (value between 1 and 16).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Synchronize init structure with new FIFO threshold value */
+    hqspi->Init.FifoThreshold = Threshold;
+    
+    /* Configure QSPI FIFO Threshold */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, 
+               ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
+  }
+  else
+  {
+    status = HAL_BUSY;   
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/** @brief Get QSPI Fifo threshold.
+  * @param  hqspi: QSPI handle.
+  * @retval Fifo threshold (value between 1 and 16)
+  */
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+{
+  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA QSPI receive process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)  
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hqspi->RxXferCount = 0;
+  
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+  * @brief  DMA QSPI transmit process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)     
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hqspi->TxXferCount = 0;
+  
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+  * @brief  DMA QSPI receive process half complete callback. 
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_QSPI_RxHalfCpltCallback(hqspi); 
+}
+
+/**
+  * @brief  DMA QSPI transmit process half complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_QSPI_TxHalfCpltCallback(hqspi);
+}
+
+/**
+  * @brief  DMA QSPI communication error callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hqspi->RxXferCount = 0;
+  hqspi->TxXferCount = 0;
+  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
+  
+  /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+  CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+  /* Abort the QSPI */
+  HAL_QSPI_Abort_IT(hqspi);
+}
+
+/**
+  * @brief  DMA QSPI abort complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)   
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hqspi->RxXferCount = 0;
+  hqspi->TxXferCount = 0;
+
+  if(hqspi->State == HAL_QSPI_STATE_ABORT)
+  {
+    /* DMA Abort called by QSPI abort */
+    /* Clear interrupt */
+    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+    
+    /* Enable the QSPI Transfer Complete Interrupt */
+    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+    
+    /* Configure QSPI: CR register with Abort request */
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+  }
+  else
+  {
+    /* DMA Abort called due to a transfer error interrupt */
+    /* Change state of QSPI */
+    hqspi->State = HAL_QSPI_STATE_READY;
+    
+    /* Error callback */
+    HAL_QSPI_ErrorCallback(hqspi);
+  }
+}
+/**
+  * @brief  Wait for a flag state until timeout.
+  * @param  hqspi: QSPI handle
+  * @param  Flag: Flag checked
+  * @param  State: Value of the flag expected
+  * @param  Timeout: Duration of the timeout
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, 
+                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is in expected state */    
+  while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout))
+      {
+        hqspi->State     = HAL_QSPI_STATE_ERROR;
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+        
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the communication registers.
+  * @param  hqspi: QSPI handle
+  * @param  cmd: structure that contains the command configuration information
+  * @param  FunctionalMode: functional mode to configured
+  *           This parameter can be one of the following values:
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
+  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
+  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
+  * @retval None
+  */
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
+{
+  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
+
+  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+  {
+    /* Configure QSPI: DLR register with the number of data to read or write */
+    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
+  }
+
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+    {
+      /* Configure QSPI: ABR register with alternate bytes value */
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with instruction, address and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
+                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | 
+                                         cmd->Instruction | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with instruction and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
+                                         cmd->AddressMode | cmd->InstructionMode | 
+                                         cmd->Instruction | FunctionalMode));
+      }
+    }
+    else
+    {
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with instruction and address ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | 
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only instruction ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                         cmd->AlternateByteMode | cmd->AddressMode | 
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+      }
+    }
+  }
+  else
+  {
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+    {
+      /* Configure QSPI: ABR register with alternate bytes value */
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with address and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
+                                         cmd->AddressSize | cmd->AddressMode | 
+                                         cmd->InstructionMode | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode | 
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+      }
+    }
+    else
+    {
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with only address ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                         cmd->AlternateByteMode | cmd->AddressSize | 
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only data phase ----*/
+        if (cmd->DataMode != QSPI_DATA_NONE)
+        {
+          /* Configure QSPI: CCR register with all communications parameters */
+          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | 
+                                           cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | 
+                                           cmd->AlternateByteMode | cmd->AddressMode | 
+                                           cmd->InstructionMode | FunctionalMode));
+        }
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_QSPI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h
new file mode 100755
index 0000000..9b2e821
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h
@@ -0,0 +1,706 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_qspi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of QSPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_QSPI_H
+#define __STM32L4xx_HAL_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup QSPI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup QSPI_Exported_Types QSPI Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  QSPI Init structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
+                                  This parameter can be a number between 0 and 255 */ 
+  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
+                                  This parameter can be a value between 1 and 16 */
+  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 
+                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
+                                  This parameter can be a value of @ref QSPI_SampleShifting */
+  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 
+                                  required to address the flash memory. The flash capacity can be up to 4GB 
+                                  (addressed using 32 bits) in indirect mode, but the addressable space in 
+                                  memory-mapped mode is limited to 256MB
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 
+                                  of clock cycles which the chip select must remain high between commands.
+                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */   
+  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
+                                  This parameter can be a value of @ref QSPI_ClockMode */
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx) 
+  uint32_t FlashID;            /* Specifies the Flash which will be used,
+                                  This parameter can be a value of @ref QSPI_Flash_Select */
+  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
+                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */                                               
+#endif
+}QSPI_InitTypeDef;
+
+/** 
+  * @brief HAL QSPI State structures definition  
+  */ 
+typedef enum
+{
+  HAL_QSPI_STATE_RESET             = 0x00,    /*!< Peripheral not initialized                            */
+  HAL_QSPI_STATE_READY             = 0x01,    /*!< Peripheral initialized and ready for use              */
+  HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */ 
+  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */ 
+  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22,    /*!< Peripheral in indirect mode with reception ongoing    */
+  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42,    /*!< Peripheral in auto polling mode ongoing               */
+  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82,    /*!< Peripheral in memory mapped mode ongoing              */
+  HAL_QSPI_STATE_ABORT             = 0x08,    /*!< Peripheral with abort request ongoing                 */
+  HAL_QSPI_STATE_ERROR             = 0x04     /*!< Peripheral in error                                   */
+}HAL_QSPI_StateTypeDef;
+
+/** 
+  * @brief  QSPI Handle Structure definition  
+  */  
+typedef struct
+{
+  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
+  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
+  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
+  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
+  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
+  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
+  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
+  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
+  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
+  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
+  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
+  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
+  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */ 
+}QSPI_HandleTypeDef;
+
+/** 
+  * @brief  QSPI Command structure definition  
+  */
+typedef struct
+{
+  uint32_t Instruction;        /* Specifies the Instruction to be sent
+                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */
+  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AddressSize;        /* Specifies the Address Size
+                                  This parameter can be a value of @ref QSPI_AddressSize */
+  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
+                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */
+  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t InstructionMode;    /* Specifies the Instruction Mode
+                                  This parameter can be a value of @ref QSPI_InstructionMode */
+  uint32_t AddressMode;        /* Specifies the Address Mode
+                                  This parameter can be a value of @ref QSPI_AddressMode */
+  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
+                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */
+  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
+                                  This parameter can be a value of @ref QSPI_DataMode */
+  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
+                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 
+                                  until end of memory)*/
+  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
+                                  This parameter can be a value of @ref QSPI_DdrMode */
+  uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of 
+                                  system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
+                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
+  uint32_t SIOOMode;           /* Specifies the send instruction only once mode
+                                  This parameter can be a value of @ref QSPI_SIOOMode */
+}QSPI_CommandTypeDef;
+
+/** 
+  * @brief  QSPI Auto Polling mode configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received. 
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
+                                  This parameter can be any value between 1 and 4 */
+  uint32_t MatchMode;          /* Specifies the method used for determining a match.
+                                  This parameter can be a value of @ref QSPI_MatchMode */
+  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
+                                  This parameter can be a value of @ref QSPI_AutomaticStop */
+}QSPI_AutoPollingTypeDef;
+                           
+/** 
+  * @brief  QSPI Memory Mapped mode configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select. 
+                                  This parameter can be a value of @ref QSPI_TimeOutActivation */
+}QSPI_MemoryMappedTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
+  * @{
+  */
+
+/** @defgroup QSPI_ErrorCode QSPI Error Code
+  * @{
+  */ 
+#define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error                 */
+#define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error            */
+#define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error           */
+#define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error       */
+#define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008) /*!< Invalid parameters error */
+/**
+  * @}
+  */ 
+
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
+  * @{
+  */
+#define QSPI_SAMPLE_SHIFTING_NONE      ((uint32_t)0x00000000)        /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+/**
+  * @}
+  */ 
+
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
+  * @{
+  */
+#define QSPI_CS_HIGH_TIME_1_CYCLE      ((uint32_t)0x00000000)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ClockMode QSPI Clock Mode
+  * @{
+  */
+#define QSPI_CLOCK_MODE_0              ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+/**
+  * @}
+  */
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx) 
+/** @defgroup QSPI_Flash_Select QSPI Flash Select
+  * @{
+  */
+#define QSPI_FLASH_ID_1                ((uint32_t)0x00000000)      /*!<FLASH 1 selected*/
+#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
+/**
+  * @}
+  */  
+
+  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+  * @{
+  */
+#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
+#define QSPI_DUALFLASH_DISABLE         ((uint32_t)0x00000000)     /*!<Dual-flash mode disabled*/
+/**
+  * @}
+  */ 
+#endif
+
+/** @defgroup QSPI_AddressSize QSPI Address Size
+  * @{
+  */
+#define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
+#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
+#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
+#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
+  * @{
+  */
+#define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
+* @{
+*/
+#define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
+#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
+#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
+#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AddressMode QSPI Address Mode
+* @{
+*/
+#define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
+#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
+#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
+#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
+*/
+#define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
+#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
+#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_DataMode QSPI Data Mode
+  * @{
+  */
+#define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
+#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
+#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
+#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_DdrMode QSPI DDR Mode
+  * @{
+  */
+#define QSPI_DDR_MODE_DISABLE          ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
+  * @{
+  */
+#define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx) 
+#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
+  * @{
+  */
+#define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_MatchMode QSPI Match Mode
+  * @{
+  */
+#define QSPI_MATCH_MODE_AND            ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
+  * @{
+  */
+#define QSPI_AUTOMATIC_STOP_DISABLE    ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
+  * @{
+  */
+#define QSPI_TIMEOUT_COUNTER_DISABLE   ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_Flags QSPI Flags
+  * @{
+  */
+#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+  * @{
+  */  
+#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+  * @brief QSPI Timeout definition
+  * @{
+  */ 
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
+  * @{
+  */
+/** @brief Reset QSPI handle state.
+  * @param  __HANDLE__: QSPI handle.
+  * @retval None
+  */
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+
+/** @brief  Enable the QSPI peripheral.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @retval None
+  */ 
+#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Disable the QSPI peripheral.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Enable the specified QSPI interrupt.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief  Disable the specified QSPI interrupt.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the specified QSPI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 
+
+/**
+  * @brief  Check whether the selected QSPI flag is set or not.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __FLAG__: specifies the QSPI flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
+  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM:   QSPI Status match flag
+  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
+  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
+
+/** @brief  Clears the specified QSPI's flag status.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_TO: QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM: QSPI Status match flag
+  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/  
+/** @addtogroup QSPI_Exported_Functions
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+
+/* IO operation functions *****************************************************/
+/* QSPI IRQ handler method */
+void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+
+/* QSPI status flag polling mode */
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
+
+/* QSPI memory-mapped mode */
+HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
+
+/* Callback functions in non-blocking modes ***********************************/
+void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI status flag polling mode */
+void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI memory-mapped mode */
+void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
+
+/* Peripheral Control and State functions  ************************************/
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
+uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/  
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+* @{
+*/
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
+
+#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0) && ((THR) <= 16))
+
+#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31))
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx) 
+#define IS_QSPI_FLASH_ID(FLASH)            (((FLASH) == QSPI_FLASH_ID_1) || \
+                                            ((FLASH) == QSPI_FLASH_ID_2)) 
+                                  
+#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+                                            ((MODE) == QSPI_DUALFLASH_DISABLE))
+#endif
+
+#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF) 
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31) 
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
+                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
+                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
+                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
+                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
+                                            ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
+                                            ((MODE) == QSPI_DATA_1_LINE)  || \
+                                            ((MODE) == QSPI_DATA_2_LINES) || \
+                                            ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx) 
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+#else
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
+#endif
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 
+
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4)) 
+
+#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
+                                            ((MODE) == QSPI_MATCH_MODE_OR)) 
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 
+
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF) 
+/**
+* @}
+*/ 
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_QSPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c
new file mode 100755
index 0000000..222237d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c
@@ -0,0 +1,1524 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Multiple Speed Internal oscillator
+      (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
+      and I-Cache are disabled, and all peripherals are off except internal
+      SRAM, Flash and JTAG.
+
+      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
+          all peripherals mapped on these busses are running at MSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in analog mode, except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB busses prescalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock source(s) for peripherals which clocks are not
+          derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+#define MSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */  
+#define LSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+#define HSI48_TIMEOUT_VALUE        ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000U) /* 5 s    */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
+            (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_Private_Functions RCC Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal and external oscillators
+      (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+       and APB2).
+
+    [..] Internal/external clock and PLL configuration
+         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+             
+         (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
+             It can be used to generate the clock for the USB OTG FS (48 MHz).
+             The number of flash wait states is automatically adjusted when MSI range is updated with 
+             HAL_RCC_OscConfig() and the MSI is used as System clock source. 
+
+         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also optionally as RTC clock source.
+
+         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
+
+         (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
+           (++) The first output is used to generate the high speed system clock (up to 80MHz).
+           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
+           (++) The third output is used to generate an accurate clock to achieve
+                high-quality audio performance on SAI interface.
+
+         (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
+           (++) The first output is used to generate SAR ADC1 clock.
+           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
+           (++) The Third output is used to generate an accurate clock to achieve
+                high-quality audio performance on SAI interface.
+
+         (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
+           (++) The first output is used to generate SAR ADC2 clock.
+           (++) The second  output is used to generate an accurate clock to achieve
+                high-quality audio performance on SAI interface.
+
+         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
+            (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled.
+             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+             exception vector.
+
+         (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
+             main PLL clock (through a configurable prescaler) on PA8 pin.
+
+    [..] System, AHB and APB busses clocks configuration
+         (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
+             HSE and main PLL.
+             The AHB clock (HCLK) is derived from System clock through configurable
+             prescaler and used to clock the CPU, memory and peripherals mapped
+             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+             from AHB clock through configurable prescalers and used to clock
+             the peripherals mapped on these busses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+
+           (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
+                from an external clock mapped on the SAI_CKIN pin.
+                You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+                divided by 2 to 31.
+                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
+                to configure this clock.
+           (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
+                to work correctly, while the SDMMC1 and RNG peripherals require a frequency 
+                equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
+                through PLLQ divider. You have to enable the peripheral clock and use 
+                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+           (+@) IWDG clock which is always the LSI clock.
+
+
+         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. 
+             The clock source frequency should be adapted depending on the device voltage range
+             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
+
+  @endverbatim
+             
+           Table 1. HCLK clock frequency.             
+           +-------------------------------------------------------+     
+           | Latency         |    HCLK clock frequency (MHz)       |
+           |                 |-------------------------------------|
+           |                 | voltage range 1  | voltage range 2  |
+           |                 |      1.2 V       |     1.0 V        |
+           |-----------------|------------------|------------------|
+           |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |
+           |-----------------|------------------|------------------|
+           |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |
+           |-----------------|------------------|------------------|
+           |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |
+           |-----------------|------------------|------------------|
+           |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |
+           |-----------------|------------------|------------------|
+           |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |
+           +-------------------------------------------------------+
+  * @{
+  */
+
+/**
+  * @brief  Reset the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - MSI ON and used as system clock source
+  *            - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval None
+  */
+void HAL_RCC_DeInit(void)
+{
+  /* Set MSION bit */
+  SET_BIT(RCC->CR, RCC_CR_MSION);
+
+  /* Insure MSIRDY bit is set before writing default MSIRANGE value */
+  while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); }
+  
+  /* Set MSIRANGE default value */
+  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);
+  
+  /* Reset CFGR register (MSI is selected as system clock source) */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */
+#if defined(RCC_PLLSAI2_SUPPORT)
+  
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);
+
+#else
+
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+  
+  /* Reset PLLCFGR register */
+  CLEAR_REG(RCC->PLLCFGR);
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );
+
+  /* Reset PLLSAI1CFGR register */
+  CLEAR_REG(RCC->PLLSAI1CFGR);
+  SET_BIT(RCC->PLLSAI1CFGR,  RCC_PLLSAI1CFGR_PLLSAI1N_4 );
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+  
+  /* Reset PLLSAI2CFGR register */
+  CLEAR_REG(RCC->PLLSAI2CFGR);
+  SET_BIT(RCC->PLLSAI2CFGR,  RCC_PLLSAI2CFGR_PLLSAI2N_4 );
+  
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = MSI_VALUE;
+}
+
+/**
+  * @brief  Initialize the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this macro. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this macro. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(RCC_OscInitStruct != NULL);
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+  /*----------------------------- MSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
+    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
+    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
+
+    /* When the MSI is used as system clock it will not be disabled */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
+    {
+      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
+      {
+        return HAL_ERROR;
+      }
+
+       /* Otherwise, just the calibration and MSI range change are allowed */
+      else
+      {
+        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+           must be correctly programmed according to the frequency of the CPU clock
+           (HCLK) and the supply voltage of the device. */
+        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
+        {
+          /* First increase number of wait states update if necessary */
+          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
+          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
+          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
+          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
+        }
+        else
+        {
+          /* Else, keep current flash latency while decreasing applies */
+          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
+          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
+          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
+          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
+
+          /* Decrease number of wait states update if necessary */
+          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }          
+        }
+
+        /* Update the SystemCoreClock global variable */
+        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+        
+        /* Configure the source of time base considering new system clocks settings*/
+        HAL_InitTick (TICK_INT_PRIORITY);
+      }
+    }
+    else
+    {
+      /* Check the MSI State */
+      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (MSI). */
+        __HAL_RCC_MSI_ENABLE();
+
+        /* Get timeout */
+        tickstart = HAL_GetTick();
+
+        /* Wait till MSI is ready */
+        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
+        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
+         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
+        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
+
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (MSI). */
+        __HAL_RCC_MSI_DISABLE();
+
+        /* Get timeout */
+        tickstart = HAL_GetTick();
+
+        /* Wait till MSI is ready */
+        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || 
+       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+    {
+      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is disabled */
+        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||
+       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is disabled */
+        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is disabled */
+      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+    
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+    
+    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR1, PWR_CR1_DBP);
+      
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+
+    /* Check the LSE State */
+    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is disabled */
+      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+#if defined(RCC_HSI48_SUPPORT)
+  /*------------------------------ HSI48 Configuration -----------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the LSI State */
+    if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is disabled */
+      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* RCC_HSI48_SUPPORT */
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+
+  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    {
+      if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Enable PLL System Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Disable all PLL outputs to save power if no PLLs on */
+        if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
+#if defined(RCC_PLLSAI2_SUPPORT)
+           && 
+           (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
+#endif /* RCC_PLLSAI2_SUPPORT */
+          )
+        {  
+          MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
+        }
+        
+#if defined(RCC_PLLSAI2_SUPPORT)
+        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
+#else
+        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the CPU, AHB and APB busses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency  FLASH Latency
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
+  *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
+  *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycles
+  *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycles
+  *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycles
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+  *
+  * @note   The MSI is used by default as system clock source after
+  *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
+  *         the MSI frequency is set to its default value 4 MHz.
+  *
+  * @note   The HSI can be selected as system clock source after
+  *         from STOP modes or in case of failure of the HSE used directly or indirectly 
+  *         as system clock (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source is ready.
+  *
+  * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  *
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(RCC_ClkInitStruct != NULL);
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+  }
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+    /* HSE is selected as System Clock Source */
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    {
+      /* Check the PLL ready flag */
+      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* MSI is selected as System Clock Source */
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+    {
+      /* Check the MSI ready flag */
+      if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+      {
+        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    {
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+      {
+        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+    {
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
+      {
+        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+      {
+        if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+  
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+  }
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+
+  /* Configure the source of time base considering new system clocks settings*/
+  HAL_InitTick (TICK_INT_PRIORITY);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to:
+    
+    (+) Ouput clock to MCO pin.
+    (+) Retrieve current clock frequencies.
+    (+) Enable the Clock Security System.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Select the clock source to output on MCO pin(PA8).
+  * @note   PA8 should be configured in alternate function mode.
+  * @param  RCC_MCOx  specifies the output direction for the clock source.
+  *          For STM32L4xx family this parameter can have only one value:
+  *            @arg @ref RCC_MCO1  Clock source to output on MCO1 pin(PA8).
+  * @param  RCC_MCOSource  specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
+  @if STM32L443xx
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
+  @endif
+  * @param  RCC_MCODiv  specifies the MCO prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock
+  *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
+  *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
+  *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
+  *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+  /* MCO Clock Enable */
+  __MCO1_CLK_ENABLE();
+
+  /* Configue the MCO1 pin in alternate function mode */
+  GPIO_InitStruct.Pin = MCO1_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+  HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+  /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
+  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv ));
+}
+
+/**
+  * @brief  Return the SYSCLK frequency.
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is MSI, function returns values based on MSI
+  *             Value as defined by the MSI range.
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
+  *           HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
+  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U;
+  uint32_t sysclockfreq = 0U;
+
+  if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ||
+     ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)))
+  {
+    /* MSI or PLL with MSI source used as system clock source */
+
+    /* Get SYSCLK source */
+    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET)
+    { /* MSISRANGE from RCC_CSR applies */
+      msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE);
+    }
+    else
+    { /* MSIRANGE from RCC_CR applies */
+      msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE);
+    }
+    /*MSI frequency range in HZ*/
+    msirange = MSIRangeTable[msirange];
+
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)
+    {
+      /* MSI used as system clock source */
+      sysclockfreq = msirange;
+    }
+  }
+  else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
+  {
+    /* HSI used as system clock source */
+    sysclockfreq = HSI_VALUE;
+  }
+  else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
+  {
+    /* HSE used as system clock source */
+    sysclockfreq = HSE_VALUE;
+  }
+
+  if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
+  {
+    /* PLL used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+    pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ;
+
+    switch (pllsource)
+    {
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+      break;
+
+    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
+    default:
+      pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+      break;
+    }
+    pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U;
+    sysclockfreq = pllvco/pllr;
+  }
+
+  return sysclockfreq;
+}
+
+/**
+  * @brief  Return the HCLK frequency.
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+  * @retval HCLK frequency in Hz
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+  return SystemCoreClock;
+}
+
+/**
+  * @brief  Return the PCLK1 frequency.
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+}
+
+/**
+  * @brief  Return the PCLK2 frequency.
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK2 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+}
+
+/**
+  * @brief  Configure the RCC_OscInitStruct according to the internal
+  *         RCC configuration registers.
+  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Check the parameters */
+  assert_param(RCC_OscInitStruct != NULL);
+
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+#if defined(RCC_HSI48_SUPPORT)
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
+#else
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+#endif /* RCC_HSI48_SUPPORT */
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+   /* Get the MSI configuration -----------------------------------------------*/
+  if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
+  {
+    RCC_OscInitStruct->MSIState = RCC_MSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
+  }
+
+  RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
+  RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) );
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+#if defined(RCC_HSI48_SUPPORT)
+  /* Get the HSI48 configuration ---------------------------------------------*/
+  if((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+  }
+#else
+  RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+#endif /* RCC_HSI48_SUPPORT */
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U) << 1U);
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV));
+#else
+  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET)
+  {
+    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;
+  }
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+}
+
+/**
+  * @brief  Configure the RCC_ClkInitStruct according to the internal
+  *         RCC configuration registers.
+  * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that
+  *         will be configured.
+  * @param  pFLatency  Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Check the parameters */
+  assert_param(RCC_ClkInitStruct != NULL);
+  assert_param(pFLatency != NULL);
+
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+  * @note   The Clock Security System can only be cleared by reset.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON) ;
+}
+
+/**
+  * @brief Handle the RCC Clock Security System interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF interrupt flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CSSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCC_CSSCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RCC_CSSCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup RCC_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Update number of Flash wait states in line with MSI range and current 
+            voltage range.
+  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
+{
+  uint32_t vos = 0;
+  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
+  
+  if(__HAL_RCC_PWR_IS_CLK_ENABLED())
+  {
+    vos = HAL_PWREx_GetVoltageRange();
+  }
+  else
+  {
+    __HAL_RCC_PWR_CLK_ENABLE();
+    vos = HAL_PWREx_GetVoltageRange();
+    __HAL_RCC_PWR_CLK_DISABLE();
+  }
+  
+  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
+  {
+    if(msirange > RCC_MSIRANGE_8)
+    {
+      /* MSI > 16Mhz */
+      if(msirange > RCC_MSIRANGE_10)
+      {
+        /* MSI 48Mhz */
+        latency = FLASH_LATENCY_2; /* 2WS */
+      }
+      else
+      {
+        /* MSI 24Mhz or 32Mhz */
+        latency = FLASH_LATENCY_1; /* 1WS */
+      }
+    }
+    /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */
+  }
+  else
+  {
+    if(msirange > RCC_MSIRANGE_8)
+    {
+      /* MSI > 16Mhz */
+      latency = FLASH_LATENCY_3; /* 3WS */
+    }
+    else
+    {
+      if(msirange == RCC_MSIRANGE_8)
+      {
+        /* MSI 16Mhz */
+        latency = FLASH_LATENCY_2; /* 2WS */
+      }
+      else if(msirange == RCC_MSIRANGE_7) 
+      {
+        /* MSI 8Mhz */
+        latency = FLASH_LATENCY_1; /* 1WS */
+      }
+      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
+    }
+  }
+       
+  __HAL_FLASH_SET_LATENCY(latency);
+  
+  /* Check that the new number of wait states is taken into account to access the Flash
+     memory by reading the FLASH_ACR register */
+  if((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h
new file mode 100755
index 0000000..709970c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h
@@ -0,0 +1,4245 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_RCC_H
+#define __STM32L4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 8     */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 8 and Max_Data = 86    */
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for SAI clock.
+                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
+                            This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */
+
+  uint32_t PLLR;       /*!< PLLR: Division for the main system clock.
+                            User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
+                            This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+  uint32_t MSIState;             /*!< The new state of the MSI.
+                                      This parameter can be a value of @ref RCC_MSI_Config */
+
+  uint32_t MSICalibrationValue;  /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t MSIClockRange;        /*!< The MSI frequency range.
+                                      This parameter can be a value of @ref RCC_MSI_Clock_Range  */
+
+  uint32_t HSI48State;             /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L45x/STM32L46x/STM32L49x/STM32L4Ax devices).
+                                        This parameter can be a value of @ref RCC_HSI48_Config */
+
+  RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
+
+  uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Timeout_Value Timeout Values
+  * @{
+  */
+#define RCC_DBP_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+#define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE        ((uint32_t)0x00000000U)   /*!< Oscillator configuration unchanged */
+#define RCC_OSCILLATORTYPE_HSE         ((uint32_t)0x00000001U)   /*!< HSE to configure */
+#define RCC_OSCILLATORTYPE_HSI         ((uint32_t)0x00000002U)   /*!< HSI to configure */
+#define RCC_OSCILLATORTYPE_LSE         ((uint32_t)0x00000004U)   /*!< LSE to configure */
+#define RCC_OSCILLATORTYPE_LSI         ((uint32_t)0x00000008U)   /*!< LSI to configure */
+#define RCC_OSCILLATORTYPE_MSI         ((uint32_t)0x00000010U)   /*!< MSI to configure */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_OSCILLATORTYPE_HSI48       ((uint32_t)0x00000020U)   /*!< HSI48 to configure */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                    ((uint32_t)0x00000000U)                     /*!< HSE clock deactivation */
+#define RCC_HSE_ON                     RCC_CR_HSEON                               /*!< HSE clock activation */
+#define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    ((uint32_t)0x00000000U)                         /*!< LSE clock deactivation */
+#define RCC_LSE_ON                     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                    ((uint32_t)0x00000000U) /*!< HSI clock deactivation */
+#define RCC_HSI_ON                     RCC_CR_HSION           /*!< HSI clock activation */
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+#define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x10U)      /* Default HSI calibration trimming value */
+#else
+#define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x40U)      /* Default HSI calibration trimming value */
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx    */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    ((uint32_t)0x00000000U) /*!< LSI clock deactivation */
+#define RCC_LSI_ON                     RCC_CSR_LSION          /*!< LSI clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MSI_Config MSI Config
+  * @{
+  */
+#define RCC_MSI_OFF                    ((uint32_t)0x00000000U) /*!< MSI clock deactivation */
+#define RCC_MSI_ON                     RCC_CR_MSION           /*!< MSI clock activation */
+
+#define RCC_MSICALIBRATION_DEFAULT     ((uint32_t)0)   /*!< Default MSI calibration trimming value */
+/**
+  * @}
+  */
+
+#if defined(RCC_HSI48_SUPPORT)
+/** @defgroup RCC_HSI48_Config HSI48 Config
+  * @{
+  */
+#define RCC_HSI48_OFF                  ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
+#define RCC_HSI48_ON                   RCC_CRRCR_HSI48ON      /*!< HSI48 clock activation */
+/**
+  * @}
+  */
+#else
+/** @defgroup RCC_HSI48_Config HSI48 Config
+  * @{
+  */
+#define RCC_HSI48_OFF                  ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
+/**
+  * @}
+  */
+#endif /* RCC_HSI48_SUPPORT */
+
+/** @defgroup RCC_PLL_Config PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */
+#define RCC_PLL_OFF                    ((uint32_t)0x00000001U) /*!< PLL deactivation */
+#define RCC_PLL_ON                     ((uint32_t)0x00000002U) /*!< PLL activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
+  * @{
+  */
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U) /*!< PLLP division factor = 2  */
+#define RCC_PLLP_DIV3                  ((uint32_t)0x00000003U) /*!< PLLP division factor = 3  */
+#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U) /*!< PLLP division factor = 4  */
+#define RCC_PLLP_DIV5                  ((uint32_t)0x00000005U) /*!< PLLP division factor = 5  */
+#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U) /*!< PLLP division factor = 6  */
+#define RCC_PLLP_DIV7                  ((uint32_t)0x00000007U) /*!< PLLP division factor = 7  */
+#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U) /*!< PLLP division factor = 8  */
+#define RCC_PLLP_DIV9                  ((uint32_t)0x00000009U) /*!< PLLP division factor = 9  */
+#define RCC_PLLP_DIV10                 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */
+#define RCC_PLLP_DIV11                 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */
+#define RCC_PLLP_DIV12                 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */
+#define RCC_PLLP_DIV13                 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */
+#define RCC_PLLP_DIV14                 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */
+#define RCC_PLLP_DIV15                 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */
+#define RCC_PLLP_DIV16                 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */
+#define RCC_PLLP_DIV17                 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
+#define RCC_PLLP_DIV18                 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */
+#define RCC_PLLP_DIV19                 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */
+#define RCC_PLLP_DIV20                 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */
+#define RCC_PLLP_DIV21                 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */
+#define RCC_PLLP_DIV22                 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */
+#define RCC_PLLP_DIV23                 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */
+#define RCC_PLLP_DIV24                 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */
+#define RCC_PLLP_DIV25                 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */
+#define RCC_PLLP_DIV26                 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */
+#define RCC_PLLP_DIV27                 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */
+#define RCC_PLLP_DIV28                 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */
+#define RCC_PLLP_DIV29                 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */
+#define RCC_PLLP_DIV30                 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */
+#define RCC_PLLP_DIV31                 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */
+#else
+#define RCC_PLLP_DIV7                  ((uint32_t)0x00000007U) /*!< PLLP division factor = 7  */
+#define RCC_PLLP_DIV17                 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
+  * @{
+  */
+#define RCC_PLLQ_DIV2                  ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */
+#define RCC_PLLQ_DIV4                  ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */
+#define RCC_PLLQ_DIV6                  ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */
+#define RCC_PLLQ_DIV8                  ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
+  * @{
+  */
+#define RCC_PLLR_DIV2                  ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */
+#define RCC_PLLR_DIV4                  ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */
+#define RCC_PLLR_DIV6                  ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */
+#define RCC_PLLR_DIV8                  ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_NONE             ((uint32_t)0x00000000U)  /*!< No clock selected as PLL entry clock source  */
+#define RCC_PLLSOURCE_MSI              RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
+  * @{
+  */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define RCC_PLL_SAI3CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
+#else
+#define RCC_PLL_SAI2CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define RCC_PLL_48M1CLK                RCC_PLLCFGR_PLLQEN      /*!< PLL48M1CLK selection from main PLL */
+#define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
+  * @{
+  */
+#define RCC_PLLSAI1_SAI1CLK            RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
+#define RCC_PLLSAI1_48M2CLK            RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
+#define RCC_PLLSAI1_ADC1CLK            RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
+  * @{
+  */
+#define RCC_PLLSAI2_SAI2CLK            RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
+#define RCC_PLLSAI2_ADC2CLK            RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
+/**
+  * @}
+  */
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
+  * @{
+  */
+#define RCC_MSIRANGE_0                 RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */
+#define RCC_MSIRANGE_1                 RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */
+#define RCC_MSIRANGE_2                 RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */
+#define RCC_MSIRANGE_3                 RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */
+#define RCC_MSIRANGE_4                 RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */
+#define RCC_MSIRANGE_5                 RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */
+#define RCC_MSIRANGE_6                 RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */
+#define RCC_MSIRANGE_7                 RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */
+#define RCC_MSIRANGE_8                 RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */
+#define RCC_MSIRANGE_9                 RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */
+#define RCC_MSIRANGE_10                RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */
+#define RCC_MSIRANGE_11                RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK           ((uint32_t)0x00000001U)  /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK             ((uint32_t)0x00000002U)  /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1            ((uint32_t)0x00000004U)  /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2            ((uint32_t)0x00000008U)  /*!< PCLK2 to configure */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+  * @{
+  */
+#define RCC_SYSCLK_DIV1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
+  * @{
+  */
+#define RCC_HCLK_DIV1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define RCC_HCLK_DIV2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK        ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Index MCO Index
+  * @{
+  */
+#define RCC_MCO1                       ((uint32_t)0x00000000U)
+#define RCC_MCO                        RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_NOCLOCK         ((uint32_t)0x00000000U)                 /*!< MCO1 output disabled, no clock on MCO1 */
+#define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_MSI             RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
+#define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_MCO1SOURCE_HSI48           RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                   RCC_CFGR_MCOPRE_DIV1     /*!< MCO not divided  */      
+#define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_DIV2     /*!< MCO divided by 2 */
+#define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_DIV4     /*!< MCO divided by 4 */
+#define RCC_MCODIV_8                   RCC_CFGR_MCOPRE_DIV8     /*!< MCO divided by 8 */
+#define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_DIV16    /*!< MCO divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt Interrupts
+  * @{
+  */
+#define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */
+#define RCC_IT_MSIRDY                  RCC_CIFR_MSIRDYF      /*!< MSI Ready Interrupt flag */
+#define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF      /*!< HSI16 Ready Interrupt flag */
+#define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */
+#define RCC_IT_PLLSAI1RDY              RCC_CIFR_PLLSAI1RDYF  /*!< PLLSAI1 Ready Interrupt flag */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define RCC_IT_PLLSAI2RDY              RCC_CIFR_PLLSAI2RDYF  /*!< PLLSAI2 Ready Interrupt flag */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define RCC_IT_CSS                     RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
+#define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_IT_HSI48RDY                RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag Flags
+  *        Elements values convention: XXXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - XXX  : Register index
+  *                 - 001: CR register
+  *                 - 010: BDCR register
+  *                 - 011: CSR register
+  *                 - 100: CRRCR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_MSIRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
+#define RCC_FLAG_HSIRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
+#define RCC_FLAG_HSERDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
+#define RCC_FLAG_PLLRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
+#define RCC_FLAG_PLLSAI1RDY            ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define RCC_FLAG_PLLSAI2RDY            ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
+#define RCC_FLAG_LSECSSD               ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< LSI Ready flag */
+#define RCC_FLAG_RMVF                  ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF)))     /*!< Remove reset flag */
+#define RCC_FLAG_FWRST                 ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF)))   /*!< Firewall reset flag */
+#define RCC_FLAG_OBLRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))  /*!< Option Byte Loader reset flag */
+#define RCC_FLAG_PINRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
+#define RCC_FLAG_BORRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF)))  /*!< BOR reset flag */
+#define RCC_FLAG_SFTRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+
+#if defined(RCC_HSI48_SUPPORT)
+/* Flags in the CRRCR register */
+#define RCC_FLAG_HSI48RDY              ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000U) /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */ 
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 
+  * @{
+  */
+#define RCC_STOP_WAKEUPCLOCK_MSI       ((uint32_t)0x00000000U)  /*!< MSI selection after wake-up from STOP */
+#define RCC_STOP_WAKEUPCLOCK_HSI       RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_FLASH_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_CRC_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TSC_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+                                               
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* DMA2D */                                               
+
+
+#define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
+
+#define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
+
+#define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
+
+#define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
+
+#define __HAL_RCC_TSC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
+#endif /* DMA2D */   
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* GPIOI */
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()      do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)    
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0) 
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
+
+#define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
+
+#define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
+#endif /* GPIOI */
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()     CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* LCD */
+
+#if defined(RCC_APB1ENR1_RTCAPBEN)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* RCC_APB1ENR1_RTCAPBEN */
+
+#define __HAL_RCC_WWDG_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+                                               
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_DAC1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_OPAMP_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+
+#define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
+
+#define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
+#endif /* LCD */
+
+#if defined(RCC_APB1ENR1_RTCAPBEN)
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
+#endif /* RCC_APB1ENR1_RTCAPBEN */
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
+
+#define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
+#endif /* USB */
+
+#define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
+
+#define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
+
+#define __HAL_RCC_OPAMP_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
+
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
+
+#define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_FIREWALL_CLK_ENABLE()        do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+
+#define __HAL_RCC_TIM15_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* DFSDM1_Filter0 */
+
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
+
+#define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
+
+#define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
+#endif /* DFSDM1_Filter0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the AHB1 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
+
+#define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
+
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
+
+#define __HAL_RCC_TSC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET)
+#endif /* DMA2D */
+
+
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
+
+#define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
+
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
+
+#define __HAL_RCC_TSC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET)
+#endif /* DMA2D */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the AHB2 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
+
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
+
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET)
+#endif /* GPIOI */
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
+
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
+
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
+
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET)
+#endif /* GPIOI */
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the AHB3 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the APB1 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
+
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
+#endif /* LCD */
+
+#if defined(RCC_APB1ENR1_RTCAPBEN)
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
+#endif /* RCC_APB1ENR1_RTCAPBEN */
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
+
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
+
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
+
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
+
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
+
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
+
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
+#endif /* LCD */
+
+#if defined(RCC_APB1ENR1_RTCAPBEN)
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
+#endif /* RCC_APB1ENR1_RTCAPBEN */
+
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
+
+#define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
+
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
+
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
+
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the APB2 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
+
+#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
+
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
+
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
+#endif /* DFSDM1_Filter0 */
+
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
+
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
+
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
+#endif /* DFSDM1_Filter0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()           WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
+
+#define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
+
+#define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
+
+#define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+#define __HAL_RCC_TSC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
+#endif /* DMA2D */
+
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()         WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
+
+#define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
+
+#define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
+
+#define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
+
+#define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+#define __HAL_RCC_TSC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
+#endif /* DMA2D */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()           WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
+
+#define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
+#endif /* GPIOI */
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()     SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
+
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()         WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
+
+#define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
+
+#define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
+#endif /* GPIOI */
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()   CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB3_FORCE_RESET()           WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_FORCE_RESET()            SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_FORCE_RESET()           SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
+#endif /* QUADSPI */
+
+#define __HAL_RCC_AHB3_RELEASE_RESET()         WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
+
+#define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
+#endif /* LCD */
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
+
+#define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
+
+#define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
+
+#define __HAL_RCC_OPAMP_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
+
+#define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
+
+#define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
+
+
+#define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
+#endif /* LCD */
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
+
+#define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
+
+#define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
+
+#define __HAL_RCC_OPAMP_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
+
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
+
+#define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
+#endif /* DFSDM1_Filter0 */
+
+
+#define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APB2RSTR, 0x00000000U)
+
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
+#endif /* DFSDM1_Filter0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
+
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
+#endif /* DMA2D */
+
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
+
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
+#endif /* DMA2D */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
+#endif /* GPIOI */
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
+
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
+#endif /* GPIOI */
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
+#endif /* FMC_BANK1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
+#endif /* LCD */
+
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
+
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
+
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
+#endif /* LCD */
+
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
+
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
+#endif /* DFSDM1_Filter0 */
+
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
+#endif /* DFSDM1_Filter0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
+
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
+
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
+
+#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET)
+#endif /* DMA2D */
+
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
+
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
+
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
+
+#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
+
+#if defined(DMA2D)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET)
+#endif /* DMA2D */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
+
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
+
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET)
+#endif /* GPIOI */
+
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
+
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
+
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
+
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
+
+#if defined(GPIOD)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
+#endif /* GPIOD */
+
+#if defined(GPIOE)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
+#endif /* GPIOE */
+
+#if defined(GPIOF)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
+#endif /* GPIOF */
+
+#if defined(GPIOG)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
+#endif /* GPIOG */
+
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
+
+#if defined(GPIOI)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET)
+#endif /* GPIOI */
+
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
+
+#if defined(USB_OTG_FS)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
+#endif /* USB_OTG_FS */
+
+#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
+
+#if defined(DCMI)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET)
+#endif /* DCMI */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
+#endif /* AES */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
+#endif /* FMC_BANK1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
+
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
+#endif /* LCD */
+
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
+
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
+
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
+
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
+
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
+
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
+
+#if defined(TIM3)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
+#endif /* TIM3 */
+
+#if defined(TIM4)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
+#endif /* TIM4 */
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
+
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
+
+#if defined(LCD)
+#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
+#endif /* LCD */
+
+#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
+#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
+
+#if defined(SPI2)
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
+#endif /* SPI2 */
+
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
+
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
+
+#if defined(USART3)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
+#endif /* USART3 */
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
+
+#if defined(I2C2)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
+#endif /* I2C2 */
+
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET)
+#endif /* I2C4 */
+
+#if defined(CRS)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
+#endif /* CRS */
+
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
+
+#if defined(CAN2)
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET)
+#endif /* CAN2 */
+
+#if defined(USB)
+#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
+#endif /* USB */
+
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
+
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
+
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
+
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
+
+#if defined(SWPMI1)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
+#endif /* SWPMI1 */
+
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
+
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
+
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
+#endif /* DFSDM1_Filter0 */
+
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
+
+#if defined(SDMMC1)
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
+#endif /* SDMMC1 */
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
+
+#if defined(TIM8)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
+#endif /* TIM8 */
+
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
+
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
+
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
+
+#if defined(TIM17)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
+#endif /* TIM17 */
+
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
+
+#if defined(SAI2)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
+#endif /* SAI2 */
+
+#if defined(DFSDM1_Filter0)
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
+#endif /* DFSDM1_Filter0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
+  * @{   
+  */ 
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_CSR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  * @retval None
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+  * @{   
+  */ 
+
+/** @brief  Macros to enable or disable the RTC clock.
+  * @note   As the RTC is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
+  *         (to be done once after reset).
+  * @note   These macros must be used after the RTC clock source was selected.
+  * @retval None
+  */
+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/**
+  * @}
+  */
+
+/** @brief  Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
+
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+/** @brief  Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICALIBRATIONVALUE__: specifies the calibration trimming value
+  *         (default is RCC_HSICALIBRATION_DEFAULT).
+  *         This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
+  * @retval None
+  */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
+                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
+
+/**
+  * @brief    Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
+  *           in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIASFS)
+
+#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE()  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
+
+/**
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the HSI startup time.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+/**
+  * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).
+  * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.
+  *           It is used (enabled by hardware) as system clock source after
+  *           startup from Reset, wakeup from STOP and STANDBY mode, or in case
+  *           of failure of the HSE used directly or indirectly as system clock
+  *           (if the Clock Security System CSS is enabled).
+  * @note     MSI can not be stopped if it is used as system clock source.
+  *           In this case, you have to select another source of the system
+  *           clock then stop the MSI.
+  * @note     After enabling the MSI, the application software should wait on
+  *           MSIRDY flag to be set indicating that MSI clock is stable and can
+  *           be used as system clock source.
+  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+#define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)
+
+#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
+
+/** @brief  Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal MSI RC.
+  *         Refer to the Application Note AN3300 for more details on how to
+  *         calibrate the MSI.
+  * @param  __MSICALIBRATIONVALUE__: specifies the calibration trimming value
+  *         (default is RCC_MSICALIBRATION_DEFAULT).
+  *         This parameter must be a number between 0 and 255.
+  * @retval None
+  */
+#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
+                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
+
+/**
+  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
+  * @note     After restart from Reset , the MSI clock is around 4 MHz.
+  *           After stop the startup clock can be MSI (at any of its possible
+  *           frequencies, the one that was used before entering stop mode) or HSI.
+  *          After Standby its frequency can be selected between 4 possible values
+  *          (1, 2, 4 or 8 MHz).
+  * @note     MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
+  *          (MSIRDY=1).
+  * @note    The MSI clock range after reset can be modified on the fly.
+  * @param  __MSIRANGEVALUE__: specifies the MSI clock range.
+  *         This parameter must be one of the following values:
+  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
+  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
+  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
+  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
+  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
+  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz
+  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)
+  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz
+  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
+  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
+  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
+  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
+  * @retval None
+  */
+#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
+                  do {                                                         \
+                    SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \
+                    MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
+                  } while(0)
+
+/**
+  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
+  *         After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
+  * @param  __MSIRANGEVALUE__: specifies the MSI clock range.
+  *         This parameter must be one of the following values:
+  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
+  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz
+  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)
+  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz
+  * @retval None
+  */
+#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
+                  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
+
+/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
+  * @retval MSI clock range.
+  *         This parameter must be one of the following values:
+  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
+  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
+  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
+  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
+  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
+  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz
+  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)
+  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz
+  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
+  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
+  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
+  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
+  */
+#define __HAL_RCC_GET_MSI_RANGE()                                              \
+                  ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ?             \
+                   (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) :            \
+                   (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
+
+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (HSE).
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this macro. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__: specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
+  *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.
+  * @retval None
+  */
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                      \
+                    do {                                     \
+                      if((__STATE__) == RCC_HSE_ON)          \
+                      {                                      \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
+                      }                                      \
+                      else if((__STATE__) == RCC_HSE_BYPASS) \
+                      {                                      \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
+                      }                                      \
+                      else                                   \
+                      {                                      \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
+                      }                                      \
+                    } while(0)
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this macro. User should request a transition to LSE Off 
+  *         first and then LSE On or LSE Bypass.  
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  __STATE__: specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
+  *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
+  * @retval None
+  */
+#define __HAL_RCC_LSE_CONFIG(__STATE__)                        \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0)
+
+#if defined(RCC_HSI48_SUPPORT)
+
+/** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   After enabling the HSI48, the application software should wait on HSI48RDY
+  *         flag to be set indicating that HSI48 clock is stable.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSI48_ENABLE()  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
+
+#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
+
+#endif /* RCC_HSI48_SUPPORT */
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it cannot be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
+  *         a Power On Reset (POR).
+  *
+  * @param  __RTC_CLKSOURCE__: specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK  No clock selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
+  *
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  * @retval None
+  */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \
+                  MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+
+/** @brief  Macro to get the RTC clock source.
+  * @retval The returned value can be one of the following:
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK  No clock selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
+  */
+#define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  * @retval None
+  */
+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)
+
+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief  Macro to configure the PLL clock source.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLSOURCE__: specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
+  * @retval None
+  *      
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief  Macro to configure the PLL source division factor M.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 8.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
+  *         of 16 MHz to limit PLL jitter.
+  * @retval None
+  *      
+  */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
+
+/**
+  * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  *
+  * @param  __PLLSOURCE__: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
+  *
+  * @param  __PLLM__: specifies the division factor for PLL VCO input clock.
+  *          This parameter must be a number between 1 and 8.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
+  *         of 16 MHz to limit PLL jitter.
+  *
+  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock.
+  *          This parameter must be a number between 8 and 86.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 64 and 344 MHz.
+  *
+  * @param  __PLLP__: specifies the division factor for SAI clock.
+  *          This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
+  *          else (2 to 31).
+  *
+  * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
+  *          This parameter must be in the range (2, 4, 6 or 8).
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  * @param  __PLLR__: specifies the division factor for the main system clock.
+  * @note   You have to set the PLLR parameter correctly to not exceed 80MHZ.
+  *          This parameter must be in the range (2, 4, 6 or 8).
+  * @retval None
+  */
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+
+#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
+                  (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
+                   (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \
+                   (uint32_t)((__PLLP__) << 27U))
+                    
+#else
+                    
+#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
+                  (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
+                   (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
+
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+
+/**
+  * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
+  * @note   Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 
+  *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot  
+  *         be stopped if used as System Clock.
+  * @param  __PLLCLOCKOUT__: specifies the PLL clock to be output.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve
+  *                                   high-quality audio performance on SAI interface in case.
+  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),
+  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
+  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)
+  * @retval None
+  */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+/**
+  * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
+  * @param  __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve
+  *                                   high-quality audio performance on SAI interface in case.
+  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),
+  *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
+  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)
+  * @retval SET / RESET
+  */
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+/**
+  * @brief  Macro to configure the system clock source.
+  * @param  __SYSCLKSOURCE__: specifies the system clock source.
+  *          This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  * @retval None
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
+  *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
+  * @retval None
+  */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+                  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
+
+/**
+  * @brief  Macro to configure the wake up from stop clock.
+  * @param  __STOPWUCLK__: specifies the clock source used after wake up from stop.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI selected as system clock source
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI selected as system clock source
+  * @retval None
+  */
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
+
+
+/** @brief  Macro to configure the MCO clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
+  @if STM32L443xx
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
+  @endif
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
+  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
+  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
+  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
+  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+
+/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+  *         the selected interrupts).
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  @if STM32L443xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  * @retval None
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+  *        the selected interrupts).
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  @if STM32L443xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  * @retval None
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
+  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  @if STM32L443xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  @endif
+  * @retval None
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
+
+/** @brief  Check whether the RCC interrupt has occurred or not.
+  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
+  *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
+  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  @if STM32L443xx
+  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
+  @endif
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+  *        The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+  * @retval None
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief  Check whether the selected RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_FLAG_MSIRDY  MSI oscillator clock ready
+  *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready
+  *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready
+  *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready
+  *            @arg @ref RCC_FLAG_PLLSAI1RDY  PLLSAI1 clock ready
+  *            @arg @ref RCC_FLAG_PLLSAI2RDY  PLLSAI2 clock ready for devices with PLLSAI2
+  @if STM32L443xx
+  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48
+  @endif
+  *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready
+  *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection
+  *            @arg @ref RCC_FLAG_LSIRDY  LSI oscillator clock ready
+  *            @arg @ref RCC_FLAG_BORRST  BOR reset
+  *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset
+  *            @arg @ref RCC_FLAG_PINRST  Pin reset
+  *            @arg @ref RCC_FLAG_FWRST  FIREWALL reset
+  *            @arg @ref RCC_FLAG_RMVF  Remove reset Flag
+  *            @arg @ref RCC_FLAG_SFTRST  Software reset
+  *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset
+  *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset
+  *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#if defined(RCC_HSI48_SUPPORT)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                     \
+                                        ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR :                  \
+                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                   \
+                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) &    \
+                                          ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
+                                            ? 1U : 0U)
+#else
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \
+                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \
+                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) &    \
+                                          ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
+                                            ? 1U : 0U)
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+/* Defines used for Flags */
+#define CR_REG_INDEX              ((uint32_t)1U)
+#define BDCR_REG_INDEX            ((uint32_t)2U)
+#define CSR_REG_INDEX             ((uint32_t)3U)
+#if defined(RCC_HSI48_SUPPORT)
+#define CRRCR_REG_INDEX           ((uint32_t)4U)
+#endif /* RCC_HSI48_SUPPORT */
+
+#define RCC_FLAG_MASK             ((uint32_t)0x1FU)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros
+  * @{
+  */
+
+#if defined(RCC_HSI48_SUPPORT)
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)   == RCC_OSCILLATORTYPE_MSI)   || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE))
+#else
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+#endif /* RCC_HSI48_SUPPORT */
+
+#define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+                              ((__HSE__) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+                              ((__LSE__) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM  >>  POSITION_VAL(RCC_ICSCR_HSITRIM)))
+
+#define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+
+#define IS_RCC_MSI(__MSI__)  (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
+
+#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
+
+#if defined(RCC_HSI48_SUPPORT)
+#define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
+#endif /* RCC_HSI48_SUPPORT */
+
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
+                             ((__PLL__) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
+
+#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
+#else
+#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
+#endif /*RCC_PLLP_DIV_2_31_SUPPORT */
+
+#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
+                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
+
+#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
+                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
+
+#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \
+                                                  (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK)  || \
+                                                  (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
+                                                 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK)  || \
+                                                  (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
+                                                 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))   
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_1)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_2)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_3)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_4)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_5)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_6)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_7)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_8)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_9)  || \
+                                           ((__RANGE__) == RCC_MSIRANGE_10) || \
+                                           ((__RANGE__) == RCC_MSIRANGE_11))
+
+#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4)  || \
+                                                   ((__RANGE__) == RCC_MSIRANGE_5)  || \
+                                                   ((__RANGE__) == RCC_MSIRANGE_6)  || \
+                                                   ((__RANGE__) == RCC_MSIRANGE_7))
+
+#define IS_RCC_CLOCKTYPE(__CLK__)  ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
+
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+                               ((__PCLK__) == RCC_HCLK_DIV16))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+
+#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
+
+#if defined(RCC_HSI48_SUPPORT)
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
+#else
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
+#endif /* RCC_HSI48_SUPPORT */
+
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
+                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
+                                ((__DIV__) == RCC_MCODIV_16))
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
+                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
+                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
+
+#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
+                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extended module */
+#include "stm32l4xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+void              HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void              HAL_RCC_EnableCSS(void);
+uint32_t          HAL_RCC_GetSysClockFreq(void);
+uint32_t          HAL_RCC_GetHCLKFreq(void);
+uint32_t          HAL_RCC_GetPCLK1Freq(void);
+uint32_t          HAL_RCC_GetPCLK2Freq(void);
+void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+/* CSS NMI IRQ handler */
+void              HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void              HAL_RCC_CSSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c
new file mode 100755
index 0000000..e3f89b1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c
@@ -0,0 +1,2813 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extended peripheral:
+  *           + Extended Peripheral Control functions
+  *           + Extended Clock management functions
+  *           + Extended Clock Recovery System Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx RCCEx
+  * @brief RCC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+#define PLLSAI1_TIMEOUT_VALUE    ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+#define PLLSAI2_TIMEOUT_VALUE    ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE        ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
+
+#define DIVIDER_P_UPDATE          0U
+#define DIVIDER_Q_UPDATE          1U
+#define DIVIDER_R_UPDATE          2U
+
+#define __LSCO_CLK_ENABLE()       __HAL_RCC_GPIOA_CLK_ENABLE()
+#define LSCO_GPIO_PORT            GPIOA
+#define LSCO_PIN                  GPIO_PIN_2
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider);
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider);
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initialize the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains a field PeriphClockSelection which can be a combination of the following values:
+  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
+  @if STM32L462xx
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
+  @if STM32L462xx
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock
+  @if STM32L443xx
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock
+  @if STM32L462xx
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)
+  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)
+  *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source: in this case the access to Backup domain is enabled.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tmpregister = 0;
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*-------------------------- SAI1 clock source configuration ---------------------*/
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
+
+    switch(PeriphClkInit->Sai1ClockSelection)
+    {
+    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+      /* Enable SAI Clock output generated form System PLL . */
+#if defined(RCC_PLLSAI2_SUPPORT)
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
+#else
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
+#endif /* RCC_PLLSAI2_SUPPORT */
+      /* SAI1 clock source config set later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLLSAI1:  /* PLLSAI1 is used as clock source for SAI1*/
+      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
+      /* SAI1 clock source config set later after clock selection check */
+      break;
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+    case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/
+      /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
+      /* SAI1 clock source config set later after clock selection check */
+      break;
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+    case RCC_SAI1CLKSOURCE_PIN:      /* External clock is used as source of SAI1 clock*/
+      /* SAI1 clock source config set later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI1 clock*/
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(SAI2)
+
+  /*-------------------------- SAI2 clock source configuration ---------------------*/
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
+
+    switch(PeriphClkInit->Sai2ClockSelection)
+    {
+    case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
+      /* SAI2 clock source config set later after clock selection check */
+      break;
+
+    case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
+      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
+      /* SAI2 clock source config set later after clock selection check */
+      break;
+
+    case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/
+      /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
+      /* SAI2 clock source config set later after clock selection check */
+      break;
+
+    case RCC_SAI2CLKSOURCE_PIN:      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source config set later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2 clock*/
+      __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /* SAI2 */
+
+  /*-------------------------- RTC clock source configuration ----------------------*/
+  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+    
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+      
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        ret = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(ret == HAL_OK)
+    { 
+      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
+      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
+      
+      if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection))
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpregister;
+      }
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            ret = HAL_TIMEOUT;
+            break;
+          }
+        }
+      }
+      
+      if(ret == HAL_OK)
+      {
+        /* Apply new RTC clock source selection */
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+
+  /*-------------------------- USART1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+    /* Configure the USART1 clock source */
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+  }
+
+  /*-------------------------- USART2 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+    /* Configure the USART2 clock source */
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+  }
+
+#if defined(USART3)
+
+  /*-------------------------- USART3 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+    /* Configure the USART3 clock source */
+    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+  }
+
+#endif /* USART3 */
+
+#if defined(UART4)
+
+  /*-------------------------- UART4 clock source configuration --------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+    /* Configure the UART4 clock source */
+    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+  }
+
+#endif /* UART4 */
+
+#if defined(UART5)
+
+  /*-------------------------- UART5 clock source configuration --------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+    /* Configure the UART5 clock source */
+    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+  }
+
+#endif /* UART5 */
+
+  /*-------------------------- LPUART1 clock source configuration ------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
+
+    /* Configure the LPUAR1 clock source */
+    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+  }
+
+  /*-------------------------- LPTIM1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
+  {
+    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+  }
+
+  /*-------------------------- LPTIM2 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
+  {
+    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
+    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+  }
+
+  /*-------------------------- I2C1 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+    /* Configure the I2C1 clock source */
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+  }
+
+#if defined(I2C2)  
+
+  /*-------------------------- I2C2 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+    /* Configure the I2C2 clock source */
+    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+  }
+
+#endif /* I2C2 */
+
+  /*-------------------------- I2C3 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+    /* Configure the I2C3 clock source */
+    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+  }
+
+#if defined(I2C4)  
+
+  /*-------------------------- I2C4 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    /* Configure the I2C4 clock source */
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+  }
+
+#endif /* I2C4 */
+
+#if defined(USB_OTG_FS) || defined(USB)
+
+  /*-------------------------- USB clock source configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
+  {
+    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
+    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+
+    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+    else
+    {
+      if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
+      {
+        /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
+        ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
+      
+        if(ret != HAL_OK)
+        {
+          /* set overall return value */
+          status = ret;
+        }
+      }
+    }
+  }
+
+#endif /* USB_OTG_FS || USB */
+
+#if defined(SDMMC1)
+
+  /*-------------------------- SDMMC1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
+  {
+    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
+    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
+    
+    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
+    {
+      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
+      
+      if(ret != HAL_OK)
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+  }
+
+#endif /* SDMMC1 */
+
+  /*-------------------------- RNG clock source configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
+  {
+    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
+    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+
+    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
+    {
+      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
+      
+      if(ret != HAL_OK)
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+  }
+
+  /*-------------------------- ADC clock source configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
+
+    /* Configure the ADC interface clock source */
+    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+    
+    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
+    {
+      /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
+      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
+
+      if(ret != HAL_OK)
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+
+    else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
+    {
+      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
+      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
+      
+      if(ret != HAL_OK)
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+
+  }
+
+#if defined(SWPMI1)
+
+  /*-------------------------- SWPMI1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
+
+    /* Configure the SWPMI1 clock source */
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
+  }
+
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Filter0)
+
+  /*-------------------------- DFSDM1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+
+#endif /* DFSDM1_Filter0 */
+
+  return status;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals
+  *         clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART,
+  *         USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  /* Set all possible values for the extended clock type parameter------------*/
+
+#if defined(STM32L431xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                                               \
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \
+                                        RCC_PERIPHCLK_RTC ;
+
+#elif defined(STM32L432xx) || defined(STM32L442xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 |                                                                      \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   |                        RCC_PERIPHCLK_I2C3   |                        \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \
+                                                                RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \
+                                        RCC_PERIPHCLK_RTC ;
+
+#elif defined(STM32L433xx) || defined(STM32L443xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \
+                                        RCC_PERIPHCLK_RTC ;
+
+#elif defined(STM32L451xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  |                        \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                                               \
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    |                        RCC_PERIPHCLK_DFSDM1 | \
+                                        RCC_PERIPHCLK_RTC ;
+
+#elif defined(STM32L452xx) || defined(STM32L462xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  |                        \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    |                        RCC_PERIPHCLK_DFSDM1 | \
+                                        RCC_PERIPHCLK_RTC ;
+
+#elif defined(STM32L471xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3                          | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2                          | \
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
+                                        RCC_PERIPHCLK_RTC ;
+  
+#elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
+                                        RCC_PERIPHCLK_RTC ;
+
+#elif defined(STM32L496xx) || defined(STM32L4A6xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | RCC_PERIPHCLK_I2C4   | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \
+                                        RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
+                                        RCC_PERIPHCLK_RTC ;
+
+#endif /* STM32L431xx */
+
+  /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
+  
+  PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC));
+  PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U;
+  PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N));
+  PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4U) + 7U;
+  PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1U) * 2U;
+  PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1U) * 2U;
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+  /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
+
+  PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;
+  PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;
+  PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N));
+  PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4U) + 7U;
+  PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1U) * 2U;
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+  /* Get the USART1 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
+  /* Get the USART2 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
+
+#if defined(USART3)
+  /* Get the USART3 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
+#endif /* USART3 */
+
+#if defined(UART4)
+  /* Get the UART4 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();
+#endif /* UART4 */
+
+#if defined(UART5)
+  /* Get the UART5 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();
+#endif /* UART5 */
+  
+  /* Get the LPUART1 clock source --------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+
+  /* Get the I2C1 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
+
+#if defined(I2C2)
+   /* Get the I2C2 clock source ----------------------------------------------*/
+  PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
+#endif /* I2C2 */
+
+  /* Get the I2C3 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
+
+#if defined(I2C4)
+  /* Get the I2C4 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c4ClockSelection    = __HAL_RCC_GET_I2C4_SOURCE();
+#endif /* I2C4 */
+
+  /* Get the LPTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+  /* Get the LPTIM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim2ClockSelection  = __HAL_RCC_GET_LPTIM2_SOURCE();
+
+  /* Get the SAI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();
+
+#if defined(SAI2)
+  /* Get the SAI2 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai2ClockSelection    = __HAL_RCC_GET_SAI2_SOURCE();
+#endif /* SAI2 */
+
+  /* Get the RTC clock source ------------------------------------------------*/
+  PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
+
+#if defined(USB_OTG_FS) || defined(USB)
+  /* Get the USB clock source ------------------------------------------------*/
+  PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();
+#endif /* USB_OTG_FS || USB */
+
+#if defined(SDMMC1)
+  /* Get the SDMMC1 clock source ---------------------------------------------*/
+  PeriphClkInit->Sdmmc1ClockSelection   = __HAL_RCC_GET_SDMMC1_SOURCE();
+#endif /* SDMMC1 */
+
+  /* Get the RNG clock source ------------------------------------------------*/
+  PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();
+
+  /* Get the ADC clock source ------------------------------------------------*/
+  PeriphClkInit->AdcClockSelection     = __HAL_RCC_GET_ADC_SOURCE();
+
+#if defined(SWPMI1)
+  /* Get the SWPMI1 clock source ---------------------------------------------*/
+  PeriphClkInit->Swpmi1ClockSelection  = __HAL_RCC_GET_SWPMI1_SOURCE();
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Filter0)
+  /* Get the DFSDM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection  = __HAL_RCC_GET_DFSDM1_SOURCE();
+#endif /* DFSDM1_Filter0 */
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for peripherals with clock source from PLLSAIs 
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk  Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
+  @if STM32L462xx
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
+  @if STM32L462xx
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock
+  @if STM32L443xx
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock
+  @if STM32L462xx
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
+   @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
+  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
+  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
+  @endif
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
+  * @retval Frequency in Hz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  uint32_t frequency = 0U;
+  uint32_t srcclk = 0U;
+  uint32_t pllvco = 0U, plln = 0U, pllp = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+  if(PeriphClk == RCC_PERIPHCLK_RTC)
+  {
+    /* Get the current RTC source */
+    srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+    /* Check if LSE is ready and if RTC clock selection is LSE */
+    if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+    {
+      frequency = LSE_VALUE;
+    }
+    /* Check if LSI is ready and if RTC clock selection is LSI */
+    else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+    {
+      frequency = LSI_VALUE;
+    }
+    /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
+    else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+    {
+      frequency = HSE_VALUE / 32;
+    }
+    /* Clock not enabled for RTC*/
+    else
+    {
+      frequency = 0U;
+    }
+  }
+  else
+  {
+    /* Other external peripheral clock source than RTC */
+    
+    /* Compute PLL clock input */
+    if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)        /* MSI ? */
+    {
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
+      {
+        /*MSI frequency range in HZ*/
+        pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
+      }
+      else
+      {
+        pllvco = 0U;
+      }
+    }
+    else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)   /* HSI ? */
+    {
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+      {
+        pllvco = HSI_VALUE;
+      }
+      else
+      {
+        pllvco = 0U;
+      }
+    }
+    else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)   /* HSE ? */
+    {
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+      {
+        pllvco = HSE_VALUE;
+      }
+      else
+      {
+        pllvco = 0U;
+      }
+    }
+    else /* No source */
+    {
+      pllvco = 0U;
+    }
+
+    /* f(PLL Source) / PLLM */
+    pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U));
+
+    switch(PeriphClk)
+    {
+#if defined(SAI2)
+
+    case RCC_PERIPHCLK_SAI1:
+    case RCC_PERIPHCLK_SAI2:
+
+      if(PeriphClk == RCC_PERIPHCLK_SAI1)
+      {
+        srcclk = __HAL_RCC_GET_SAI1_SOURCE();
+          
+        if(srcclk == RCC_SAI1CLKSOURCE_PIN)
+        {
+          frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+        }
+        /* Else, PLL clock output to check below */
+      }
+      else /* RCC_PERIPHCLK_SAI2 */
+      {
+        srcclk = __HAL_RCC_GET_SAI2_SOURCE();
+          
+        if(srcclk == RCC_SAI2CLKSOURCE_PIN)
+        {
+          frequency = EXTERNAL_SAI2_CLOCK_VALUE;
+        }
+        /* Else, PLL clock output to check below */
+      }
+  
+#else
+
+    case RCC_PERIPHCLK_SAI1:
+
+      if(PeriphClk == RCC_PERIPHCLK_SAI1)
+      {
+        srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL);
+          
+        if(srcclk == RCC_SAI1CLKSOURCE_PIN)
+        {
+          frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+        }
+        /* Else, PLL clock output to check below */
+      }
+      
+#endif /* SAI2 */
+
+      if(frequency == 0U)
+      {
+#if defined(SAI2)
+        if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
+        {
+          if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET)
+          {
+            /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
+            plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+            pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
+#endif             
+            if(pllp == 0U)
+            {
+              if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
+              {
+                pllp = 17U;
+              }
+              else
+              {
+                pllp = 7U;
+              }
+            }
+            frequency = (pllvco * plln) / pllp;
+          }
+        }
+        else if(srcclk == 0U)  /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
+        {
+          if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
+          {
+            /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
+            plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+            pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
+#endif             
+            if(pllp == 0U)
+            {
+              if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
+              {
+                pllp = 17U;
+              }
+              else
+              {
+                pllp = 7U;
+              }
+            }
+            frequency = (pllvco * plln) / pllp;
+          }
+        }
+#else
+        if(srcclk == RCC_SAI1CLKSOURCE_PLL)
+        {
+          if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET)
+          {
+            /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
+            plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+            pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
+#endif             
+            if(pllp == 0U)
+            {
+              if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
+              {
+                pllp = 17U;
+              }
+              else
+              {
+                pllp = 7U;
+              }
+            }
+        
+            frequency = (pllvco * plln) / pllp;
+          }
+          else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+          {
+            /* HSI automatically selected as clock source if PLLs not enabled */
+            frequency = HSI_VALUE;
+          }
+          else
+          {
+            /* No clock source */
+            frequency = 0U;
+          }          
+        }
+        else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)
+        {
+          if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
+          {
+            /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
+            plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+            pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
+#endif             
+            if(pllp == 0U)
+            {
+              if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
+              {
+                pllp = 17U;
+              }
+              else
+              {
+                pllp = 7U;
+              }
+            }
+        
+           frequency = (pllvco * plln) / pllp;
+          }
+          else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+          {
+            /* HSI automatically selected as clock source if PLLs not enabled */
+            frequency = HSI_VALUE;
+          }
+          else
+          {
+            /* No clock source */
+            frequency = 0U;
+          }                     
+        }
+#endif /* SAI2 */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+        else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
+        {
+          if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET)
+          {
+            /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
+            plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
+            if(pllp == 0U)
+            {
+              if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET)
+              {
+                pllp = 17U;
+              }
+              else
+              {
+                pllp = 7U;
+              }
+            }
+            frequency = (pllvco * plln) / pllp;
+          }
+        }
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+        else
+        {
+          /* No clock source */
+          frequency = 0U;
+        }
+      }
+      break;
+    
+#if defined(USB_OTG_FS) || defined(USB)
+    
+    case RCC_PERIPHCLK_USB:
+
+#endif /* USB_OTG_FS || USB */
+
+    case RCC_PERIPHCLK_RNG:
+
+#if defined(SDMMC1)
+
+    case RCC_PERIPHCLK_SDMMC1:
+
+#endif /* SDMMC1 */
+
+      srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
+      
+      if(srcclk == RCC_CCIPR_CLK48SEL)   /* MSI ? */
+      {
+        if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
+        {
+          /*MSI frequency range in HZ*/
+          frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
+        }
+        else
+        {
+          frequency = 0U;
+        }
+      }
+      else if(srcclk == RCC_CCIPR_CLK48SEL_1)  /* PLL ? */
+      {
+        if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
+        {
+          /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */
+          plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
+          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
+        }
+        else
+        {
+          frequency = 0U;
+        }
+      }
+      else if(srcclk == RCC_CCIPR_CLK48SEL_0)  /* PLLSAI1 ? */
+      {
+        if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
+        {
+          /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */
+          plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
+          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U);
+        }
+        else
+        {
+          frequency = 0U;
+        }
+      }
+#if defined(RCC_HSI48_SUPPORT)
+      else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */
+      {
+        frequency = HSI48_VALUE;
+      }
+      else /* No clock source */
+      {
+        frequency = 0U;
+      }
+#else
+      else /* No clock source */
+      {
+        frequency = 0U;
+      }
+#endif /* RCC_HSI48_SUPPORT */
+      break;
+      
+    case RCC_PERIPHCLK_USART1:
+      /* Get the current USART1 source */
+      srcclk = __HAL_RCC_GET_USART1_SOURCE();
+      
+      if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
+      {
+        frequency = HAL_RCC_GetPCLK2Freq();
+      }
+      else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for USART1 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+    case RCC_PERIPHCLK_USART2:
+      /* Get the current USART2 source */
+      srcclk = __HAL_RCC_GET_USART2_SOURCE();
+      
+      if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for USART2 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#if defined(USART3)
+
+    case RCC_PERIPHCLK_USART3:
+      /* Get the current USART3 source */
+      srcclk = __HAL_RCC_GET_USART3_SOURCE();
+      
+      if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for USART3 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#endif /* USART3 */
+
+#if defined(UART4)
+
+    case RCC_PERIPHCLK_UART4:
+      /* Get the current UART4 source */
+      srcclk = __HAL_RCC_GET_UART4_SOURCE();
+      
+      if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for UART4 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#endif /* UART4 */
+
+#if defined(UART5)
+
+    case RCC_PERIPHCLK_UART5:
+      /* Get the current UART5 source */
+      srcclk = __HAL_RCC_GET_UART5_SOURCE();
+      
+      if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for UART5 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#endif /* UART5 */
+      
+    case RCC_PERIPHCLK_LPUART1:
+      /* Get the current LPUART1 source */
+      srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+      
+      if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for LPUART1 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+    case RCC_PERIPHCLK_ADC:
+    
+      srcclk = __HAL_RCC_GET_ADC_SOURCE();
+      
+      if(srcclk == RCC_ADCCLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1)
+      {
+        if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET)
+        {
+          /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */
+          plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
+          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U);
+        }
+      }
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+      else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2)
+      {
+        if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET)
+        {
+          /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */
+          plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
+          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U);
+        }
+      }
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+      /* Clock not enabled for ADC */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#if defined(DFSDM1_Filter0)
+
+    case RCC_PERIPHCLK_DFSDM1:
+      /* Get the current DFSDM1 source */
+      srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();
+      
+      if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2)
+      {
+        frequency = HAL_RCC_GetPCLK2Freq();
+      }
+      else
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      break;
+
+#endif /* DFSDM1_Filter0 */
+
+    case RCC_PERIPHCLK_I2C1:
+      /* Get the current I2C1 source */
+      srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+      
+      if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C1 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#if defined(I2C2)
+
+    case RCC_PERIPHCLK_I2C2:
+      /* Get the current I2C2 source */
+      srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+      
+      if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C2 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#endif /* I2C2 */
+
+    case RCC_PERIPHCLK_I2C3:
+      /* Get the current I2C3 source */
+      srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+      
+      if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C3 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#if defined(I2C4)
+
+    case RCC_PERIPHCLK_I2C4:
+      /* Get the current I2C4 source */
+      srcclk = __HAL_RCC_GET_I2C4_SOURCE();
+      
+      if(srcclk == RCC_I2C4CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((srcclk == RCC_I2C4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C4 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#endif /* I2C4 */
+
+    case RCC_PERIPHCLK_LPTIM1:
+      /* Get the current LPTIM1 source */
+      srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
+      
+      if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+      {
+        frequency = LSI_VALUE;
+      }
+      else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for LPTIM1 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+    case RCC_PERIPHCLK_LPTIM2:
+      /* Get the current LPTIM2 source */
+      srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
+      
+      if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+      {
+        frequency = LSI_VALUE;
+      }
+      else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for LPTIM2 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#if defined(SWPMI1)
+
+    case RCC_PERIPHCLK_SWPMI1:
+      /* Get the current SWPMI1 source */
+      srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
+      
+      if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for SWPMI1 */
+      else
+      {
+        frequency = 0U;
+      }
+      break;
+
+#endif /* SWPMI1 */
+
+    default:
+      break;
+    }
+  }
+
+  return(frequency);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ *  @brief  Extended Clock management functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended clock management functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the 
+    activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,
+    Low speed clock output and clock after wake-up from STOP mode.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLSAI1.
+  * @param  PLLSAI1Init  pointer to an RCC_PLLSAI1InitTypeDef structure that
+  *         contains the configuration information for the PLLSAI1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init)
+{
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
+  assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source));
+  assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M));
+  assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));
+  assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));
+  assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));
+  assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));
+  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
+
+  /* Disable the PLLSAI1 */
+  __HAL_RCC_PLLSAI1_DISABLE();
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait till PLLSAI1 is ready to be updated */
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
+    {
+      status = HAL_TIMEOUT;
+      break;
+    }
+  }
+
+  if(status == HAL_OK)    
+  {
+    /* Configure the PLLSAI1 Multiplication factor N */
+    /* Configure the PLLSAI1 Division factors P, Q and R */
+    __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
+    /* Configure the PLLSAI1 Clock output(s) */    
+    __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
+
+    /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
+    __HAL_RCC_PLLSAI1_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI1 is ready */
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
+      {
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Disable PLLSAI1.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
+{
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Disable the PLLSAI1 */
+  __HAL_RCC_PLLSAI1_DISABLE();
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait till PLLSAI1 is ready */
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
+    {
+      status = HAL_TIMEOUT;
+      break;
+    }
+  }
+  
+  /* Disable the PLLSAI1 Clock outputs */    
+  __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN);
+
+  /* Reset PLL source to save power if no PLLs on */
+  if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
+#if defined(RCC_PLLSAI2_SUPPORT)
+      && 
+     (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
+#endif /* RCC_PLLSAI2_SUPPORT */
+    )
+  {  
+    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
+  }
+  
+  return status;
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+/**
+  * @brief  Enable PLLSAI2.
+  * @param  PLLSAI2Init  pointer to an RCC_PLLSAI2InitTypeDef structure that
+  *         contains the configuration information for the PLLSAI2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init)
+{
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
+  assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source));
+  assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M));
+  assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));
+  assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));
+  assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));
+  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));
+
+  /* Disable the PLLSAI2 */
+  __HAL_RCC_PLLSAI2_DISABLE();
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait till PLLSAI2 is ready to be updated */
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
+    {
+      status = HAL_TIMEOUT;
+      break;
+    }
+  }
+
+  if(status == HAL_OK)    
+  {
+    /* Configure the PLLSAI2 Multiplication factor N */
+    /* Configure the PLLSAI2 Division factors P and R */
+    __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
+    /* Configure the PLLSAI2 Clock output(s) */    
+    __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);
+
+    /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
+    __HAL_RCC_PLLSAI2_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI2 is ready */
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
+      {
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Disable PLLISAI2.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
+{
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Disable the PLLSAI2 */
+  __HAL_RCC_PLLSAI2_DISABLE();
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait till PLLSAI2 is ready */
+  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
+    {
+      status = HAL_TIMEOUT;
+      break;
+    }
+  }
+  
+  /* Disable the PLLSAI2 Clock outputs */    
+  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN);
+
+  /* Reset PLL source to save power if no PLLs on */
+  if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
+      && 
+     (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
+    )
+  {  
+    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
+  }
+  
+  return status;
+}
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
+  * @param  WakeUpClk  Wakeup clock 
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI oscillator selection
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI oscillator selection
+  * @note   This function shall not be called after the Clock Security System on HSE has been
+  *         enabled.
+  * @retval None
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
+  
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+  * @brief  Configure the MSI range after standby mode.
+  * @note   After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
+  * @param  MSIRange  MSI range 
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_MSIRANGE_4  Range 4 around 1 MHz
+  *            @arg @ref RCC_MSIRANGE_5  Range 5 around 2 MHz
+  *            @arg @ref RCC_MSIRANGE_6  Range 6 around 4 MHz (reset value)
+  *            @arg @ref RCC_MSIRANGE_7  Range 7 around 8 MHz
+  * @retval None
+  */
+void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
+{
+  assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
+  
+  __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System.
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+  *         clock with HAL_RCCEx_PeriphCLKConfig().
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disable the LSE Clock Security System.
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+  
+  /* Disable LSE CSS IT if any */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+  * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+  /* Enable LSE CSS */
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+  /* Enable LSE CSS IT */
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+  
+  /* Enable IT on EXTI Line 19 */
+  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
+  * @brief Handle the RCC LSE Clock Security System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+  /* Check RCC LSE CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  {
+    /* RCC LSE Clock Security System interrupt user callback */
+    HAL_RCCEx_LSECSS_Callback();
+
+    /* Clear RCC LSE CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+  }
+}                                                                            
+
+/**
+  * @brief  RCCEx LSE Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
+  * @param  LSCOSource  specifies the Low Speed clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
+  *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  FlagStatus       pwrclkchanged = RESET;
+  FlagStatus       backupchanged = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
+
+  /* LSCO Pin Clock Enable */
+  __LSCO_CLK_ENABLE();
+
+  /* Configue the LSCO pin in analog mode */
+  GPIO_InitStruct.Pin = LSCO_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
+
+  /* Update LSCOSEL clock source in Backup Domain control register */
+  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+  {
+    __HAL_RCC_PWR_CLK_ENABLE();
+    pwrclkchanged = SET;
+  }
+  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+  {
+    HAL_PWR_EnableBkUpAccess();
+    backupchanged = SET;
+  }
+  
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
+  
+  if(backupchanged == SET)
+  {
+    HAL_PWR_DisableBkUpAccess();
+  }
+  if(pwrclkchanged == SET)
+  {
+    __HAL_RCC_PWR_CLK_DISABLE();
+  }
+}
+
+/**
+  * @brief  Disable the Low Speed clock output.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSCO(void)
+{
+  FlagStatus       pwrclkchanged = RESET;
+  FlagStatus       backupchanged = RESET;
+  
+  /* Update LSCOEN bit in Backup Domain control register */
+  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+  {
+    __HAL_RCC_PWR_CLK_ENABLE();
+    pwrclkchanged = SET;
+  }
+  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+  {
+    /* Enable access to the backup domain */
+    HAL_PWR_EnableBkUpAccess();
+    backupchanged = SET;
+  }
+  
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+  
+  /* Restore previous configuration */
+  if(backupchanged == SET)
+  {
+    /* Disable access to the backup domain */
+    HAL_PWR_DisableBkUpAccess();
+  }
+  if(pwrclkchanged == SET)
+  {
+    __HAL_RCC_PWR_CLK_DISABLE();
+  }
+}
+
+/**
+  * @brief  Enable the PLL-mode of the MSI.
+  * @note   Prior to enable the PLL-mode of the MSI for automatic hardware
+  *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
+  * @retval None
+  */
+void HAL_RCCEx_EnableMSIPLLMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
+}
+
+/**
+  * @brief  Disable the PLL-mode of the MSI.
+  * @note   PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
+  * @retval None
+  */
+void HAL_RCCEx_DisableMSIPLLMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
+}
+
+/**
+  * @}
+  */
+
+#if defined(CRS)
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions 
+ *  @brief  Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Clock Recovery System Control functions  #####
+ ===============================================================================
+    [..]
+      For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
+
+      (#) In System clock config, HSI48 needs to be enabled
+
+      (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+      (#) Call CRS functions as follows:
+          (##) Prepare synchronization configuration necessary for HSI48 calibration
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+                        and also HSI48 oscillator smooth trimming.
+              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate 
+                        directly reload value with target and sychronization frequencies values
+          (##) Call function HAL_RCCEx_CRSConfig which
+              (+++) Resets CRS registers to their default values.
+              (+++) Configures CRS registers with synchronization configuration 
+              (+++) Enables automatic calibration and frequency error counter feature
+           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+           should be used as SYNC signal.
+
+          (##) A polling function is provided to wait for complete synchronization
+              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue
+                        application if synchronization is OK
+              
+      (#) User can retrieve information related to synchronization in calling function
+            HAL_RCCEx_CRSGetSynchronizationInfo()
+
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), 
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be 
+           incremented), while when it is detected during the upcounting phase it means that the actual frequency 
+           is higher (and that the TRIM value should be decremented).
+
+      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go 
+          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+              (++) Call function HAL_RCCEx_CRSConfig()
+              (++) Enable CRS_IRQn (thanks to NVIC functions)
+              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+              (++) Implement CRS status management in the following user callbacks called from 
+                   HAL_RCCEx_CRS_IRQHandler():
+                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
+                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+                   (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
+          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+            
+@endverbatim
+ * @{
+ */
+
+/**
+  * @brief  Start automatic synchronization for polling mode
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+  uint32_t value = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+  /* CONFIGURATION */
+
+  /* Before configuration, reset CRS registers to their default values*/
+  __HAL_RCC_CRS_FORCE_RESET();
+  __HAL_RCC_CRS_RELEASE_RESET();
+
+  /* Set the SYNCDIV[2:0] bits according to Prescaler value */
+  /* Set the SYNCSRC[1:0] bits according to Source value */
+  /* Set the SYNCSPOL bit according to Polarity value */
+  value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */
+  value |= pInit->ReloadValue;
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+  value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM));
+  WRITE_REG(CRS->CFGR, value);
+
+  /* Adjust HSI48 oscillator smooth trimming */
+  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM)));
+  
+  /* START AUTOMATIC SYNCHRONIZATION*/
+  
+  /* Enable Automatic trimming & Frequency error counter */
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @retval None
+  */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Return synchronization info 
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+  /* Check the parameter */
+  assert_param(pSynchroInfo != NULL);
+  
+  /* Get the reload value */
+  pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+  
+  /* Get HSI48 oscillator smooth trimming */
+  pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM));
+
+  /* Get Frequency error capture */
+  pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP));
+
+  /* Get Frequency error direction */
+  pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+* @brief Wait for CRS Synchronization status.
+* @param Timeout  Duration of the timeout
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+*        frequency.
+* @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+*          This parameter can be a combination of the following values:
+*            @arg @ref RCC_CRS_TIMEOUT
+*            @arg @ref RCC_CRS_SYNCOK
+*            @arg @ref RCC_CRS_SYNCWARN
+*            @arg @ref RCC_CRS_SYNCERR
+*            @arg @ref RCC_CRS_SYNCMISS
+*            @arg @ref RCC_CRS_TRIMOVF
+*/
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+  uint32_t crsstatus = RCC_CRS_NONE;
+  uint32_t tickstart = 0U;
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+  
+  /* Wait for CRS flag or timeout detection */
+  do
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+      {
+        crsstatus = RCC_CRS_TIMEOUT;
+      }
+    }
+    /* Check CRS SYNCOK flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    {
+      /* CRS SYNC event OK */
+      crsstatus |= RCC_CRS_SYNCOK;
+    
+      /* Clear CRS SYNC event OK bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+    }
+    
+    /* Check CRS SYNCWARN flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    {
+      /* CRS SYNC warning */
+      crsstatus |= RCC_CRS_SYNCWARN;
+    
+      /* Clear CRS SYNCWARN bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+    }
+    
+    /* Check CRS TRIM overflow flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_TRIMOVF;
+    
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+    }
+    
+    /* Check CRS Error flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_SYNCERR;
+    
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+    }
+    
+    /* Check CRS SYNC Missed flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    {
+      /* CRS SYNC Missed */
+      crsstatus |= RCC_CRS_SYNCMISS;
+    
+      /* Clear CRS SYNC Missed bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+    }
+    
+    /* Check CRS Expected SYNC flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    {
+      /* frequency error counter reached a zero value */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+    }
+  } while(RCC_CRS_NONE == crsstatus);
+
+  return crsstatus;
+}
+
+/**
+  * @brief Handle the Clock Recovery System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_CRS_IRQHandler(void)
+{
+  uint32_t crserror = RCC_CRS_NONE;
+  /* Get current IT flags and IT sources values */
+  uint32_t itflags = READ_REG(CRS->ISR);
+  uint32_t itsources = READ_REG(CRS->CR);
+
+  /* Check CRS SYNCOK flag  */
+  if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
+  {
+    /* Clear CRS SYNC event OK flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncOkCallback();
+  }
+  /* Check CRS SYNCWARN flag  */
+  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
+  {
+    /* Clear CRS SYNCWARN flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncWarnCallback();
+  }
+  /* Check CRS Expected SYNC flag  */
+  else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
+  {
+    /* frequency error counter reached a zero value */
+    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_ExpectedSyncCallback();
+  }
+  /* Check CRS Error flags  */
+  else
+  {
+    if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
+    {
+      if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
+      {
+        crserror |= RCC_CRS_SYNCERR;
+      }
+      if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
+      {
+        crserror |= RCC_CRS_SYNCMISS;
+      }
+      if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
+      {
+        crserror |= RCC_CRS_TRIMOVF;
+      }
+
+      /* Clear CRS Error flags */
+      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+    
+      /* user error callback */
+      HAL_RCCEx_CRS_ErrorCallback(crserror);
+    }
+  }
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Error interrupt callback.
+  * @param  Error Combination of Error status. 
+  *         This parameter can be a combination of the following values:
+  *           @arg @ref RCC_CRS_SYNCERR
+  *           @arg @ref RCC_CRS_SYNCMISS
+  *           @arg @ref RCC_CRS_TRIMOVF
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Error);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+  
+#endif /* CRS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Private_Functions
+ * @{
+ */
+
+/**
+  * @brief  Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).
+  * @param  PllSai1  pointer to an RCC_PLLSAI1InitTypeDef structure that
+  *         contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s)
+  * @param  Divider  divider parameter to be updated
+  *
+  * @note   PLLSAI1 is temporary disable to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
+{
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
+  /* P, Q and R dividers are verified in each specific divider case below */
+  assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source));
+  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
+  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
+  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
+  
+  /* Check that PLLSAI1 clock source and divider M can be applied */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
+  {
+    /* PLL clock source and divider M already set, check that no request for change  */ 
+    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
+       || 
+       (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
+       || 
+       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M)
+      )
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Check PLLSAI1 clock source availability */
+    switch(PllSai1->PLLSAI1Source)
+    {
+    case RCC_PLLSOURCE_MSI:
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case RCC_PLLSOURCE_HSI:
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case RCC_PLLSOURCE_HSE:
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+    
+    if(status == HAL_OK)
+    {
+      /* Set PLLSAI1 clock source and divider M */
+      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
+    }
+  }
+  
+  if(status == HAL_OK)
+  {
+    /* Disable the PLLSAI1 */
+    __HAL_RCC_PLLSAI1_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI1 is ready to be updated */
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
+      {
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(status == HAL_OK)    
+    {
+      if(Divider == DIVIDER_P_UPDATE)
+      {
+        assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));
+        /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+        MODIFY_REG(RCC->PLLSAI1CFGR, 
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 
+                   (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | 
+                   (PllSai1->PLLSAI1P << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)));
+#else
+        MODIFY_REG(RCC->PLLSAI1CFGR, 
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, 
+                   (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | 
+                   ((PllSai1->PLLSAI1P >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)));
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+      }
+      else if(Divider == DIVIDER_Q_UPDATE)
+      {
+        assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));
+        /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
+        MODIFY_REG(RCC->PLLSAI1CFGR, 
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, 
+                   (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | 
+                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)));
+      }
+      else
+      {
+        assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));
+        /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
+        MODIFY_REG(RCC->PLLSAI1CFGR, 
+                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, 
+                   (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | 
+                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)));
+      }
+
+      /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
+      __HAL_RCC_PLLSAI1_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till PLLSAI1 is ready */
+      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
+        {
+          status = HAL_TIMEOUT;
+          break;
+        }
+      }
+
+      if(status == HAL_OK)    
+      {
+        /* Configure the PLLSAI1 Clock output(s) */
+        __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
+      }
+    }
+  }
+  
+  return status;
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+/**
+  * @brief  Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).
+  * @param  PllSai2  pointer to an RCC_PLLSAI2InitTypeDef structure that
+  *         contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s)
+  * @param  Divider  divider parameter to be updated
+  *
+  * @note   PLLSAI2 is temporary disable to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
+{
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
+  /* P, Q and R dividers are verified in each specific divider case below */
+  assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source));
+  assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
+  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
+  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
+  
+  /* Check that PLLSAI2 clock source and divider M can be applied */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
+  {
+    /* PLL clock source and divider M already set, check that no request for change  */ 
+    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
+       || 
+       (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
+       || 
+       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai2->PLLSAI2M)
+      )
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Check PLLSAI2 clock source availability */
+    switch(PllSai2->PLLSAI2Source)
+    {
+    case RCC_PLLSOURCE_MSI:
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case RCC_PLLSOURCE_HSI:
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case RCC_PLLSOURCE_HSE:
+      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+    
+    if(status == HAL_OK)
+    {
+      /* Set PLLSAI2 clock source and divider M */
+      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
+    }
+  }
+  
+  if(status == HAL_OK)
+  {
+    /* Disable the PLLSAI2 */
+    __HAL_RCC_PLLSAI2_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI2 is ready to be updated */
+    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
+      {
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(status == HAL_OK)    
+    {
+      if(Divider == DIVIDER_P_UPDATE)
+      {
+        assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));
+        /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/
+        MODIFY_REG(RCC->PLLSAI2CFGR, 
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, 
+                   (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | 
+                   ((PllSai2->PLLSAI2P >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)));
+      }
+      else
+      {
+        assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));
+        /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
+        MODIFY_REG(RCC->PLLSAI2CFGR, 
+                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, 
+                   (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | 
+                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)));
+      }
+
+      /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
+      __HAL_RCC_PLLSAI2_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till PLLSAI2 is ready */
+      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
+        {
+          status = HAL_TIMEOUT;
+          break;
+        }
+      }
+
+      if(status == HAL_OK)    
+      {
+        /* Configure the PLLSAI2 Clock output(s) */
+        __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
+      }
+    }
+  }
+  
+  return status;
+}
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h
new file mode 100755
index 0000000..deb2b1c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h
@@ -0,0 +1,2485 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RCC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_RCC_EX_H
+#define __STM32L4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PLLSAI1 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLLSAI1Source;    /*!< PLLSAI1Source: PLLSAI1 entry clock source.
+                                  This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+  uint32_t PLLSAI1M;         /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
+
+  uint32_t PLLSAI1N;         /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
+                                  This parameter must be a number between 8 and 86 or 127 depending on devices. */
+
+  uint32_t PLLSAI1P;         /*!< PLLSAI1P: specifies the division factor for SAI clock.
+                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
+
+  uint32_t PLLSAI1Q;         /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
+                                  This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
+
+  uint32_t PLLSAI1R;         /*!< PLLSAI1R: specifies the division factor for ADC clock.
+                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
+
+  uint32_t PLLSAI1ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
+                                  This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
+}RCC_PLLSAI1InitTypeDef;
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+/**
+  * @brief  PLLSAI2 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLLSAI2Source;    /*!< PLLSAI2Source: PLLSAI2 entry clock source.
+                                  This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+  uint32_t PLLSAI2M;         /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
+
+  uint32_t PLLSAI2N;         /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
+                                  This parameter must be a number between 8 and 86 or 127 depending on devices. */
+
+  uint32_t PLLSAI2P;         /*!< PLLSAI2P: specifies the division factor for SAI clock.
+                                  This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
+
+  uint32_t PLLSAI2R;         /*!< PLLSAI2R: specifies the division factor for ADC clock.
+                                  This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
+
+  uint32_t PLLSAI2ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
+                                  This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
+}RCC_PLLSAI2InitTypeDef;
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLSAI1InitTypeDef PLLSAI1;  /*!< PLLSAI1 structure parameters.
+                                        This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+  RCC_PLLSAI2InitTypeDef PLLSAI2;  /*!< PLLSAI2 structure parameters.
+                                        This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+  uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+  uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+
+#if defined(USART3)
+
+  uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
+
+#endif /* USART3 */
+
+#if defined(UART4)
+
+  uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+#endif /* UART4 */
+
+#if defined(UART5)
+
+  uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+#endif /* UART5 */
+
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
+
+  uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
+
+#if defined(I2C2)
+
+  uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+#endif /* I2C2 */
+
+  uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+                                        
+#if defined(I2C4)
+
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
+
+#endif /* I2C4 */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+
+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+#if defined(SAI2)
+
+  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source.
+                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+
+#endif /* SAI2 */
+
+#if defined(USB_OTG_FS) || defined(USB)
+
+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+#endif /* USB_OTG_FS || USB */
+
+#if defined(SDMMC1)
+
+  uint32_t Sdmmc1ClockSelection;   /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
+                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
+
+#endif /* SDMMC1 */
+
+  uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
+
+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.
+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
+
+#if defined(SWPMI1)
+
+  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 clock source.
+                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
+
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Filter0)
+
+  uint32_t Dfsdm1ClockSelection;   /*!< Specifies DFSDM1 clock source.
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
+
+#endif /* DFSDM1_Filter0 */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
+}RCC_PeriphCLKInitTypeDef;
+
+#if defined(CRS)
+
+/** 
+  * @brief RCC_CRS Init structure definition  
+  */
+typedef struct
+{
+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
+
+  uint32_t Source;                /*!< Specifies the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
+
+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
+
+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
+                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
+                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
+                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
+                                     This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
+
+}RCC_CRSInitTypeDef;
+
+/** 
+  * @brief RCC_CRS Synchronization structure definition  
+  */
+typedef struct
+{
+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
+                                     This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
+                                     This parameter must be a number between 0 and 0x3F */
+
+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter 
+                                                                    value latched in the time of the last SYNC event.
+                                    This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 
+                                                                    frequency error counter latched in the time of the last SYNC event. 
+                                                                    It shows whether the actual frequency is below or above the target.
+                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
+
+}RCC_CRSSynchroInfoTypeDef;
+
+#endif /* CRS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
+  * @{
+  */
+#define RCC_LSCOSOURCE_LSI             (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
+#define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock output */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
+  * @{
+  */
+#define RCC_PERIPHCLK_USART1           ((uint32_t)0x00000001U)
+#define RCC_PERIPHCLK_USART2           ((uint32_t)0x00000002U)
+#if defined(USART3)
+#define RCC_PERIPHCLK_USART3           ((uint32_t)0x00000004U)
+#endif
+#if defined(UART4)
+#define RCC_PERIPHCLK_UART4            ((uint32_t)0x00000008U)
+#endif
+#if defined(UART5)
+#define RCC_PERIPHCLK_UART5            ((uint32_t)0x00000010U)
+#endif
+#define RCC_PERIPHCLK_LPUART1          ((uint32_t)0x00000020U)
+#define RCC_PERIPHCLK_I2C1             ((uint32_t)0x00000040U)
+#if defined(I2C2)
+#define RCC_PERIPHCLK_I2C2             ((uint32_t)0x00000080U)
+#endif
+#define RCC_PERIPHCLK_I2C3             ((uint32_t)0x00000100U)
+#define RCC_PERIPHCLK_LPTIM1           ((uint32_t)0x00000200U)
+#define RCC_PERIPHCLK_LPTIM2           ((uint32_t)0x00000400U)
+#define RCC_PERIPHCLK_SAI1             ((uint32_t)0x00000800U)
+#if defined(SAI2)
+#define RCC_PERIPHCLK_SAI2             ((uint32_t)0x00001000U)
+#endif
+#if defined(USB_OTG_FS) || defined(USB)
+#define RCC_PERIPHCLK_USB              ((uint32_t)0x00002000U)
+#endif
+#define RCC_PERIPHCLK_ADC              ((uint32_t)0x00004000U)
+#if defined(SWPMI1)
+#define RCC_PERIPHCLK_SWPMI1           ((uint32_t)0x00008000U)
+#endif
+#if defined(DFSDM1_Filter0)
+#define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x00010000U)
+#endif
+#define RCC_PERIPHCLK_RTC              ((uint32_t)0x00020000U)
+#define RCC_PERIPHCLK_RNG              ((uint32_t)0x00040000U)
+#if defined(SDMMC1)
+#define RCC_PERIPHCLK_SDMMC1           ((uint32_t)0x00080000U)
+#endif
+#if defined(I2C4)
+#define RCC_PERIPHCLK_I2C4             ((uint32_t)0x00100000U)
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)
+#define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0
+#define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1
+#define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
+#define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0
+#define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1
+#define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
+/**
+  * @}
+  */
+
+#if defined(USART3)
+/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
+#define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0
+#define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1
+#define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
+/**
+  * @}
+  */
+#endif /* USART3 */
+
+#if defined(UART4)
+/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
+#define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0
+#define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1
+#define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
+/**
+  * @}
+  */
+#endif /* UART4 */
+
+#if defined(UART5)
+/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
+#define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0
+#define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1
+#define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
+/**
+  * @}
+  */
+#endif /* UART5 */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
+  * @{
+  */
+#define RCC_LPUART1CLKSOURCE_PCLK1     ((uint32_t)0x00000000U)
+#define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0
+#define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1
+/**
+  * @}
+  */
+
+#if defined(I2C2)
+/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0
+#define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1
+/**
+  * @}
+  */
+#endif /* I2C2 */
+
+/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0
+#define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1
+/**
+  * @}
+  */
+  
+#if defined(I2C4)
+/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
+  * @{
+  */
+#define RCC_I2C4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_CCIPR2_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_CCIPR2_I2C4SEL_1
+/**
+  * @}
+  */
+#endif /* I2C4 */  
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+  * @{
+  */
+#define RCC_SAI1CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI1SEL_0
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL
+/**
+  * @}
+  */
+
+#if defined(SAI2)
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
+#define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI2SEL_0
+#define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR_SAI2SEL_1
+#define RCC_SAI2CLKSOURCE_PIN          RCC_CCIPR_SAI2SEL
+/**
+  * @}
+  */
+#endif /* SAI2 */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
+#define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
+  * @{
+  */
+#define RCC_LPTIM2CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
+#define RCC_LPTIM2CLKSOURCE_LSI        RCC_CCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_HSI        RCC_CCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE        RCC_CCIPR_LPTIM2SEL
+/**
+  * @}
+  */
+
+#if defined(SDMMC1)
+/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
+  * @{
+  */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_SDMMC1CLKSOURCE_HSI48      ((uint32_t)0x00000000U)
+#else
+#define RCC_SDMMC1CLKSOURCE_NONE       ((uint32_t)0x00000000U)
+#endif /* RCC_HSI48_SUPPORT */
+#define RCC_SDMMC1CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0
+#define RCC_SDMMC1CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1
+#define RCC_SDMMC1CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL
+/**
+  * @}
+  */
+#endif /* SDMMC1 */
+
+/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
+  * @{
+  */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_RNGCLKSOURCE_HSI48         ((uint32_t)0x00000000U)
+#else
+#define RCC_RNGCLKSOURCE_NONE          ((uint32_t)0x00000000U)
+#endif /* RCC_HSI48_SUPPORT */
+#define RCC_RNGCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
+#define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
+#define RCC_RNGCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
+/**
+  * @}
+  */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
+  * @{
+  */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_USBCLKSOURCE_HSI48         ((uint32_t)0x00000000U)
+#else
+#define RCC_USBCLKSOURCE_NONE          ((uint32_t)0x00000000U)
+#endif /* RCC_HSI48_SUPPORT */
+#define RCC_USBCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
+#define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
+#define RCC_USBCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
+  * @{
+  */
+#define RCC_ADCCLKSOURCE_NONE        ((uint32_t)0x00000000U)
+#define RCC_ADCCLKSOURCE_PLLSAI1      RCC_CCIPR_ADCSEL_0
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+#define RCC_ADCCLKSOURCE_PLLSAI2      RCC_CCIPR_ADCSEL_1
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+#define RCC_ADCCLKSOURCE_SYSCLK       RCC_CCIPR_ADCSEL
+/**
+  * @}
+  */
+
+#if defined(SWPMI1)
+/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
+  * @{
+  */
+#define RCC_SWPMI1CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
+#define RCC_SWPMI1CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL
+/**
+  * @}
+  */
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Filter0)
+/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
+  * @{
+  */
+#define RCC_DFSDM1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)
+#define RCC_DFSDM1CLKSOURCE_SYSCLK     RCC_CCIPR_DFSDM1SEL
+/**
+  * @}
+  */
+#endif /* DFSDM1_Filter0 */
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+  * @}
+  */
+
+#if defined(CRS)
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+  * @{
+  */
+#define RCC_CRS_NONE                   ((uint32_t)0x00000000U)
+#define RCC_CRS_TIMEOUT                ((uint32_t)0x00000001U)
+#define RCC_CRS_SYNCOK                 ((uint32_t)0x00000002U)
+#define RCC_CRS_SYNCWARN               ((uint32_t)0x00000004U)
+#define RCC_CRS_SYNCERR                ((uint32_t)0x00000008U)
+#define RCC_CRS_SYNCMISS               ((uint32_t)0x00000010U)
+#define RCC_CRS_TRIMOVF                ((uint32_t)0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+  * @{
+  */
+#define RCC_CRS_SYNC_SOURCE_GPIO       ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+  * @{
+  */
+#define RCC_CRS_SYNC_DIV1        ((uint32_t)0x00000000U)                   /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+  * @{
+  */
+#define RCC_CRS_SYNC_POLARITY_RISING   ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+  * @{
+  */
+#define RCC_CRS_RELOADVALUE_DEFAULT    ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 
+                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+  * @{
+  */
+#define RCC_CRS_ERRORLIMIT_DEFAULT     ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
+  * @{
+  */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 
+                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+                                                                      corresponds to a higher output frequency */  
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+  * @{
+  */
+#define RCC_CRS_FREQERRORDIR_UP        ((uint32_t)0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_DOWN      ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+  * @{
+  */
+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+  * @{
+  */
+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+#endif /* CRS */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+
+
+/**
+  * @brief  Macro to configure the PLLSAI1 clock multiplication and division factors.
+  *
+  * @note   This function must be used only when the PLLSAI1 is disabled.
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
+  *         This parameter must be a number between 8 and 86.
+  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
+  *         output frequency is between 64 and 344 MHz.
+  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
+  *
+  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
+  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
+  *         else (2 to 31).
+  *         SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
+  *
+  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
+  *         This parameter must be in the range (2, 4, 6 or 8).
+  *         USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
+  *
+  * @param  __PLLSAI1R__ specifies the division factor for SAR ADC clock.
+  *         This parameter must be in the range (2, 4, 6 or 8).
+  *         ADC clock frequency = f(PLLSAI1) / PLLSAI1R
+  *
+  * @retval None
+  */
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+
+#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
+                  WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
+                   ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
+                   ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
+                   ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
+
+#else
+
+#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
+                  WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
+                   (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
+                   ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
+                   ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
+                    
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+/**
+  * @brief  Macro to configure the PLLSAI1 clock multiplication factor N.
+  *
+  * @note   This function must be used only when the PLLSAI1 is disabled.
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
+  *          This parameter must be a number between 8 and 86.
+  * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
+  *         output frequency is between 64 and 344 MHz.
+  *         Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
+
+/** @brief  Macro to configure the PLLSAI1 clock division factor P.
+  *
+  * @note   This function must be used only when the PLLSAI1 is disabled.
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
+  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
+  *         else (2 to 31).
+  *         Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
+  *
+  * @retval None
+  */
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+
+#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
+                    
+#else
+
+#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
+
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+/** @brief  Macro to configure the PLLSAI1 clock division factor Q.
+  *
+  * @note   This function must be used only when the PLLSAI1 is disabled.
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
+  *         This parameter must be in the range (2, 4, 6 or 8).
+  *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
+
+/** @brief  Macro to configure the PLLSAI1 clock division factor R.
+  *
+  * @note   This function must be used only when the PLLSAI1 is disabled.
+  * @note   PLLSAI1 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI1R__ specifies the division factor for ADC clock.
+  *         This parameter must be in the range (2, 4, 6 or 8)
+  *         Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
+                  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
+
+/**
+  * @brief  Macros to enable or disable the PLLSAI1.
+  * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
+  * @retval None
+  */
+
+#define __HAL_RCC_PLLSAI1_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
+
+#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
+
+/**
+  * @brief  Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
+  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
+  *         This is mainly used to save Power.
+  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
+  *                                   high-quality audio performance on SAI interface in case.
+  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
+  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
+  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
+  * @retval None
+  */
+
+#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__)   SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
+
+#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__)  CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
+
+/**
+  * @brief  Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
+  * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
+  *                                   high-quality audio performance on SAI interface in case.
+  *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
+  *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
+  *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
+  * @retval SET / RESET
+  */
+#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__)  READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+/**
+  * @brief  Macro to configure the PLLSAI2 clock multiplication and division factors.
+  *
+  * @note   This function must be used only when the PLLSAI2 is disabled.
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
+  *          This parameter must be a number between 8 and 86.
+  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
+  *         output frequency is between 64 and 344 MHz.
+  *
+  * @param  __PLLSAI2P__ specifies the division factor for SAI clock.
+  *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
+  *         else (2 to 31).
+  *         SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
+  *
+  * @param  __PLLSAI2R__ specifies the division factor for SAR ADC clock.
+  *         This parameter must be in the range (2, 4, 6 or 8).
+  *
+  * @retval None
+  */
+
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 
+
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
+                  WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
+                   ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
+                   ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
+
+#else
+
+#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
+                  WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
+                    (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
+                    ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
+                    
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+
+/**
+  * @brief  Macro to configure the PLLSAI2 clock multiplication factor N.
+  *
+  * @note   This function must be used only when the PLLSAI2 is disabled.
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
+  *          This parameter must be a number between 8 and 86.
+  * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
+  *         output frequency is between 64 and 344 MHz.
+  *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
+
+/** @brief  Macro to configure the PLLSAI2 clock division factor P.
+  *
+  * @note   This function must be used only when the PLLSAI2 is disabled.
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI2P__ specifies the division factor.
+  *         This parameter must be a number in the range (7 or 17).
+  *         Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
+
+/** @brief  Macro to configure the PLLSAI2 clock division factor R.
+  *
+  * @note   This function must be used only when the PLLSAI2 is disabled.
+  * @note   PLLSAI2 clock source is common with the main PLL (configured through
+  *         __HAL_RCC_PLL_CONFIG() macro)
+  *
+  * @param  __PLLSAI2R__ specifies the division factor.
+  *         This parameter must be in the range (2, 4, 6 or 8).
+  *         Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
+                  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
+
+/**
+  * @brief  Macros to enable or disable the PLLSAI2.
+  * @note   The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
+  * @retval None
+  */
+
+#define __HAL_RCC_PLLSAI2_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
+
+#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
+
+/**
+  * @brief  Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
+  * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
+  *         This is mainly used to save Power.
+  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
+  *                                   high-quality audio performance on SAI interface in case.
+  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
+  * @retval None
+  */
+
+#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__)  SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
+
+#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
+
+/**
+  * @brief  Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
+  * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
+  *                                   high-quality audio performance on SAI interface in case.
+  *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
+  * @retval SET / RESET
+  */
+#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__)  READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  Macro to configure the SAI1 clock source.
+  * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
+  *         from the PLLSAI1, system PLL or external clock (through a dedicated pin).
+  *          This parameter can be one of the following values:
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
+  @if STM32L486xx
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
+  @endif
+  @if STM32L4A6xx
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
+  @endif
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
+  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
+  *
+  @if STM32L443xx
+  * @note  HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
+  @endif
+  @if STM32L462xx
+  * @note  HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
+  @endif
+  *
+  * @retval None
+  */
+#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
+  @if STM32L486xx
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
+  @endif
+  @if STM32L4A6xx
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
+  @endif
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
+  *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
+  *
+  * @note  Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 
+  *        clock source when PLLs are disabled for devices without PLLSAI2.
+  *
+  */
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
+
+#if defined(SAI2)
+
+/**
+  * @brief  Macro to configure the SAI2 clock source.
+  * @param  __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
+  *         from the PLLSAI2, system PLL or external clock (through a dedicated pin).
+  *          This parameter can be one of the following values:
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
+  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
+  *
+  * @retval None
+  */
+#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
+
+/** @brief  Macro to get the SAI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
+  *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
+  *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
+
+#endif /* SAI2 */
+
+/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
+  *
+  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
+
+#if defined(I2C2)
+
+/** @brief  Macro to configure the I2C2 clock (I2C2CLK).
+  *
+  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
+
+#endif /* I2C2 */
+
+/** @brief  Macro to configure the I2C3 clock (I2C3CLK).
+  *
+  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
+
+#if defined(I2C4)
+
+/** @brief  Macro to configure the I2C4 clock (I2C4CLK).
+  *
+  * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)))
+
+#endif /* I2C4 */
+
+
+/** @brief  Macro to configure the USART1 clock (USART1CLK).
+  *
+  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_LSE  SE selected as USART1 clock
+  * @retval None
+  */
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
+
+/** @brief  Macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
+
+/** @brief  Macro to configure the USART2 clock (USART2CLK).
+  *
+  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
+  * @retval None
+  */
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
+
+/** @brief  Macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
+
+#if defined(USART3)
+
+/** @brief  Macro to configure the USART3 clock (USART3CLK).
+  *
+  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
+  * @retval None
+  */
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
+
+/** @brief  Macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
+
+#endif /* USART3 */
+
+#if defined(UART4)
+
+/** @brief  Macro to configure the UART4 clock (UART4CLK).
+  *
+  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
+  * @retval None
+  */
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
+
+/** @brief  Macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
+
+#endif /* UART4 */
+
+#if defined(UART5)
+
+/** @brief  Macro to configure the UART5 clock (UART5CLK).
+  *
+  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
+  * @retval None
+  */
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
+
+/** @brief  Macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
+
+#endif /* UART5 */
+
+/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
+  *
+  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
+  * @retval None
+  */
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
+
+/** @brief  Macro to get the LPUART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
+  */
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
+
+/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
+  *
+  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock
+  * @retval None
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
+
+/** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).
+  *
+  * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPTIM2 clock
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPTIM2 clock
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  LSI selected as LPTIM2 clock
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPTIM2 clock
+  * @retval None
+  */
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  System Clock selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPUART1 clock
+  */
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
+
+#if defined(SDMMC1)
+
+/** @brief  Macro to configure the SDMMC1 clock.
+  *
+  @if STM32L443xx
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
+  @endif
+  @if STM32L462xx
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
+  @endif
+  @if STM32L486xx
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
+  @endif
+  @if STM32L4A6xx
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
+  @endif
+  *
+  * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
+  *         This parameter can be one of the following values:
+  @if STM32L443xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL Clock selected as SDMMC1 clock
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL Clock selected as SDMMC1 clock
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL Clock selected as SDMMC1 clock
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL Clock selected as SDMMC1 clock
+  @endif
+  * @retval None
+  */
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
+
+/** @brief  Macro to get the SDMMC1 clock.
+  * @retval The clock source can be one of the following values:
+  @if STM32L443xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
+  *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
+  @endif
+  */
+#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
+
+#endif /* SDMMC1 */
+
+/** @brief  Macro to configure the RNG clock.
+  *
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
+  *
+  * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
+  *         This parameter can be one of the following values:
+  @if STM32L443xx
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
+  @endif
+  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
+  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as RNG clock
+  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock
+  * @retval None
+  */
+#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
+
+/** @brief  Macro to get the RNG clock.
+  * @retval The clock source can be one of the following values:
+  @if STM32L443xx
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
+  @endif
+  *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
+  *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
+  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as RNG clock
+  */
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
+
+#if defined(USB_OTG_FS) || defined(USB)
+
+/** @brief  Macro to configure the USB clock (USBCLK).
+  *
+  * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
+  *
+  * @param  __USB_CLKSOURCE__ specifies the USB clock source.
+  *         This parameter can be one of the following values:
+  @if STM32L443xx
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  @endif
+  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
+  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
+  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
+  * @retval None
+  */
+#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
+
+/** @brief  Macro to get the USB clock source.
+  * @retval The clock source can be one of the following values:
+  @if STM32L443xx
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  @endif
+  @if STM32L462xx
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  @endif
+  @if STM32L486xx
+  *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  @endif
+  *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
+  *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
+  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
+  */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
+
+#endif /* USB_OTG_FS || USB */
+
+/** @brief  Macro to configure the ADC interface clock.
+  * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
+  @if STM32L486xx
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
+  @endif
+  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
+  * @retval None
+  */
+#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
+
+/** @brief  Macro to get the ADC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
+  @if STM32L486xx
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
+  @endif
+  @if STM32L4A6xx
+  *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
+  @endif
+  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
+  */
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
+
+#if defined(SWPMI1)
+
+/** @brief  Macro to configure the SWPMI1 clock.
+  * @param  __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1  PCLK1 Clock selected as SWPMI1 clock
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
+  * @retval None
+  */
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
+
+/** @brief  Macro to get the SWPMI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1  PCLK1 Clock selected as SWPMI1 clock
+  *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
+  */
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
+
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Filter0)
+/** @brief  Macro to configure the DFSDM1 clock.
+  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2  PCLK2 Clock selected as DFSDM1 clock
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock
+  * @retval None
+  */
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2  PCLK2 Clock selected as DFSDM1 clock
+  *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock
+  */
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
+
+#endif /* DFSDM1_Filter0 */
+
+/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+
+/** @brief Enable PLLSAI1RDY interrupt.
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI1_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
+
+/** @brief Disable PLLSAI1RDY interrupt.
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
+
+/** @brief Clear the PLLSAI1RDY interrupt pending bit.
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI1_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
+
+/** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
+  * @retval TRUE or FALSE.
+  */
+#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
+
+/** @brief  Check whether the PLLSAI1RDY flag is set or not.
+  * @retval TRUE or FALSE.
+  */
+#define __HAL_RCC_PLLSAI1_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+/** @brief Enable PLLSAI2RDY interrupt.
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI2_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
+
+/** @brief Disable PLLSAI2RDY interrupt.
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
+
+/** @brief Clear the PLLSAI2RDY interrupt pending bit.
+  * @retval None
+  */
+#define __HAL_RCC_PLLSAI2_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
+
+/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
+  * @retval TRUE or FALSE.
+  */
+#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
+
+/** @brief  Check whether the PLLSAI2RDY flag is set or not.
+  * @retval TRUE or FALSE.
+  */
+#define __HAL_RCC_PLLSAI2_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                      \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)  
+  
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                       \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)  
+
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+
+
+#if defined(CRS)
+
+/**
+  * @brief  Enable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the CRS interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
+  *         This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/** @brief  Clear the CRS interrupt pending bits
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
+  */
+/* CRS IT Error Mask */
+#define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+                                                 } \
+                                               } while(0)
+
+/**
+  * @brief  Check whether the specified CRS flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @retval The new state of _FLAG_ (TRUE or FALSE).
+  */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the CRS specified FLAG.
+  * @param __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
+  * @retval None
+  */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
+                                                 } \
+                                               } while(0)
+
+#endif /* CRS */
+
+/**
+  * @}
+  */
+
+#if defined(CRS)
+
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+  * @{
+  */  
+/**
+  * @brief  Enable the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Disable the oscillator clock for frequency error counter.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Enable the automatic hardware adjustement of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Enable or disable the automatic hardware adjustement of TRIM bits.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency 
+  *             of the synchronization source after prescaling. It is then decreased by one in order to 
+  *             reach the expected synchronization on the zero value. The formula is the following:
+  *             RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval None
+  */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+#endif /* CRS */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
+void              HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
+void              HAL_RCCEx_EnableLSECSS(void);
+void              HAL_RCCEx_DisableLSECSS(void);
+void              HAL_RCCEx_EnableLSECSS_IT(void);
+void              HAL_RCCEx_LSECSS_IRQHandler(void);
+void              HAL_RCCEx_LSECSS_Callback(void);
+void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
+void              HAL_RCCEx_DisableLSCO(void);
+void              HAL_RCCEx_EnableMSIPLLMode(void);
+void              HAL_RCCEx_DisableMSIPLLMode(void);
+
+/**
+  * @}
+  */
+
+#if defined(CRS)
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+  * @{
+  */
+
+void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void              HAL_RCCEx_CRS_IRQHandler(void);
+void              HAL_RCCEx_CRS_SyncOkCallback(void);
+void              HAL_RCCEx_CRS_SyncWarnCallback(void);
+void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+
+/**
+  * @}
+  */
+
+#endif /* CRS */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros
+  * @{
+  */
+
+#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
+                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
+
+#if defined(STM32L431xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
+
+#elif defined(STM32L432xx) || defined(STM32L442xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG))
+
+#elif defined(STM32L433xx) || defined(STM32L443xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
+
+#elif defined(STM32L451xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
+
+#elif defined(STM32L452xx) || defined(STM32L462xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
+
+#elif defined(STM32L471xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
+
+#elif defined(STM32L496xx) || defined(STM32L4A6xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)    == RCC_PERIPHCLK_I2C4)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
+
+#else
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
+
+#endif /* STM32L431xx */
+
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+
+#if defined(USART3)
+
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
+
+#endif /* USART3 */
+
+#if defined(UART4)
+
+#define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
+
+#endif /* UART4 */
+
+#if defined(UART5)
+
+#define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
+
+#endif /* UART5 */
+
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+
+#if defined(I2C2)
+
+#define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
+
+#endif /* I2C2 */
+
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+                
+#if defined(I2C4)
+
+#define IS_RCC_I2C4CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
+
+#endif /* I2C4 */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+#define IS_RCC_SAI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
+
+#else
+
+#define IS_RCC_SAI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+#define IS_RCC_SAI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+#define IS_RCC_LPTIM1CLK(__SOURCE__)  \
+               (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_LPTIM2CLK(__SOURCE__)  \
+               (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
+                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
+                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
+
+#if defined(SDMMC1)
+#if defined(RCC_HSI48_SUPPORT)
+
+#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48)   || \
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
+
+#else
+
+#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE)    || \
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
+
+#endif /* RCC_HSI48_SUPPORT */
+#endif /* SDMMC1 */
+
+#if defined(RCC_HSI48_SUPPORT)
+
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
+
+#else
+
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)    || \
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
+
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(USB_OTG_FS) || defined(USB)
+#if defined(RCC_HSI48_SUPPORT)
+
+#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
+
+#else
+
+#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USBCLKSOURCE_NONE)    || \
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
+
+#endif /* RCC_HSI48_SUPPORT */
+#endif /* USB_OTG_FS || USB */
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+
+#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
+
+#else
+
+#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
+                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+
+#if defined(SWPMI1)
+
+#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
+
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Filter0)
+
+#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
+                ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
+
+#endif /* DFSDM1_Filter0 */
+
+#define IS_RCC_PLLSAI1SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)
+
+#define IS_RCC_PLLSAI1M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
+
+#define IS_RCC_PLLSAI1N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+#define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
+#else
+#define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
+                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
+
+#define IS_RCC_PLLSAI1R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
+                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+#define IS_RCC_PLLSAI2SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)
+
+#define IS_RCC_PLLSAI2M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
+
+#define IS_RCC_PLLSAI2N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+#define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
+#else
+#define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+#define IS_RCC_PLLSAI2R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
+                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+#if defined(CRS)
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+                                                
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+
+#endif /* CRS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c
new file mode 100755
index 0000000..9d94bf1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c
@@ -0,0 +1,519 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rng.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   RNG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Random Number Generator (RNG) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The RNG HAL driver can be used as follows:
+
+      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro 
+          in HAL_RNG_MspInit().
+      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+      (#) Wait until the 32-bit Random Number Generator contains a valid 
+          random data using (polling/interrupt) mode.   
+      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RNG RNG
+  * @brief RNG HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG_Private_Constants
+  * @{
+  */
+#define RNG_TIMEOUT_VALUE     2
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group1
+ *  @brief   Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the RNG according to the specified parameters 
+          in the RNG_InitTypeDef and create the associated handle
+      (+) DeInitialize the RNG peripheral
+      (+) Initialize the RNG MSP (MCU Specific Package)
+      (+) DeInitialize the RNG MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the RNG peripheral and initialize the associated handle.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG handle allocation */
+  if(hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); 
+  
+  __HAL_LOCK(hrng);
+  
+  if(hrng->State == HAL_RNG_STATE_RESET)
+  {  
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_RNG_MspInit(hrng);
+  }
+  
+  /* Change RNG peripheral state */
+  hrng->State = HAL_RNG_STATE_BUSY;
+
+  /* Enable the RNG Peripheral */
+  __HAL_RNG_ENABLE(hrng);
+
+  /* Initialize the RNG state */
+  hrng->State = HAL_RNG_STATE_READY;
+  
+  __HAL_UNLOCK(hrng);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the RNG peripheral. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG handle allocation */
+  if(hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Disable the RNG Peripheral */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
+  
+  /* Clear RNG interrupt status flags */
+  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+  
+  /* DeInit the low level hardware */
+  HAL_RNG_MspDeInit(hrng);
+  
+  /* Update the RNG state */
+  hrng->State = HAL_RNG_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  
+  /* Return the function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspDeInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group2
+ *  @brief    Management functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Get the 32 bit Random number
+      (+) Get the 32 bit Random number with interrupt enabled
+      (+) Handle RNG interrupt request 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Generate a 32-bit random number.
+  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag 
+  *         is automatically cleared.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @param  random32bit: pointer to generated random number variable if successful.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
+{
+  uint32_t tickstart = 0;    
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hrng); 
+  
+  /* Check RNS peripheral state */
+  if(hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */  
+    hrng->State = HAL_RNG_STATE_BUSY;  
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+  
+    /* Check if data register contains valid random data */
+    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+      {    
+        hrng->State = HAL_RNG_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrng);
+      
+        return HAL_TIMEOUT;
+      } 
+    }
+  
+    /* Get a 32bit Random number */
+    hrng->RandomNumber = hrng->Instance->DR;
+    *random32bit = hrng->RandomNumber;
+  
+    hrng->State = HAL_RNG_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrng);
+
+  return status;
+}
+
+/**
+  * @brief  Generate a 32-bit random number in interrupt mode.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+  
+  /* Check RNG peripheral state */
+  if(hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */  
+    hrng->State = HAL_RNG_STATE_BUSY;  
+  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+    
+    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+    __HAL_RNG_ENABLE_IT(hrng);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+    
+    status = HAL_ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Handle RNG interrupt request.
+  * @note   In the case of a clock error, the RNG is no more able to generate 
+  *         random numbers because the PLL48CLK clock is not correct. User has 
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). 
+  *         The clock error has no impact on the previously generated 
+  *         random numbers, and the RNG_DR register contents can be used.
+  * @note   In the case of a seed error, the generation of random numbers is 
+  *         interrupted as long as the SECS bit is '1'. If a number is 
+  *         available in the RNG_DR register, it must not be used because it may 
+  *         not have enough entropy. In this case, it is recommended to clear the 
+  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable 
+  *         the RNG peripheral to reinitialize and restart the RNG.
+  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+  *         or CEIS are set.  
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+
+  */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+  /* RNG clock error interrupt occurred */
+  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
+  { 
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+  
+    HAL_RNG_ErrorCallback(hrng);
+    
+    /* Clear the clock error flag */
+    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
+    
+  }
+  
+  /* Check RNG data ready interrupt occurred */    
+  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+  {
+    /* Generate random number once, so disable the IT */
+    __HAL_RNG_DISABLE_IT(hrng);
+    
+    /* Get the 32bit Random number (DRDY flag automatically cleared) */ 
+    hrng->RandomNumber = hrng->Instance->DR;
+    
+    if(hrng->State != HAL_RNG_STATE_ERROR)
+    {
+      /* Change RNG peripheral state */
+      hrng->State = HAL_RNG_STATE_READY; 
+      
+      /* Data Ready callback */ 
+      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+    } 
+  }
+} 
+
+/**
+  * @brief  Return generated random number in polling mode (Obsolete).
+  * @note   Use HAL_RNG_GenerateRandomNumber() API instead.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval random value
+  */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+  {
+    return hrng->RandomNumber; 
+  }
+  else
+  {
+    return 0;
+  }
+}
+
+
+/**
+  * @brief  Return a 32-bit random number with interrupt enabled (Obsolete).
+  * @note   Use HAL_RNG_GenerateRandomNumber_IT() API instead.
+  * @param  hrng: RNG handle
+  * @retval 32-bit random number
+  */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  uint32_t random32bit = 0;
+  
+  /* Process locked */
+  __HAL_LOCK(hrng);
+  
+  /* Change RNG peripheral state */  
+  hrng->State = HAL_RNG_STATE_BUSY;  
+  
+  /* Get a 32bit Random number */ 
+  random32bit = hrng->Instance->DR;
+  
+  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+  __HAL_RNG_ENABLE_IT(hrng); 
+  
+  /* Return the 32 bit random number */   
+  return random32bit;
+}
+
+
+
+/**
+  * @brief  Read latest generated random number. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval random value
+  */
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  return(hrng->RandomNumber);
+}
+
+/**
+  * @brief  Data Ready callback in non-blocking mode. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @param  random32bit: generated random value
+  * @retval None
+  */
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  UNUSED(random32bit);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  RNG error callback.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ErrorCallback must be implemented in the user file.
+   */
+}
+ 
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group3
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the RNG handle state.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL state
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+{
+  /* Return RNG handle state */
+  return hrng->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h
new file mode 100755
index 0000000..53fcd33
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rng.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RNG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_RNG_H
+#define __STM32L4xx_HAL_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RNG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup RNG_Exported_Types RNG Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  RNG HAL State Structure definition  
+  */ 
+typedef enum
+{
+  HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
+  HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
+  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */ 
+  HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
+  HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
+    
+}HAL_RNG_StateTypeDef;
+
+/** 
+  * @brief  RNG Handle Structure definition  
+  */ 
+typedef struct
+{
+  RNG_TypeDef                 *Instance;  /*!< Register base address   */ 
+  
+  HAL_LockTypeDef             Lock;       /*!< RNG locking object      */
+  
+  __IO HAL_RNG_StateTypeDef   State;      /*!< RNG communication state */
+  
+  uint32_t               RandomNumber;    /*!< Last Generated RNG Data */
+  
+}RNG_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
+  * @{
+  */
+
+/** @defgroup RNG_Interrupt_definition  RNG Interrupts Definition
+  * @{
+  */
+#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
+#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
+#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Flag_definition  RNG Flags Definition
+  * @{
+  */ 
+#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
+#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
+#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+  * @{
+  */
+
+/** @brief Reset RNG handle state.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+
+/**
+  * @brief  Enable the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
+
+/**
+  * @brief  Disable the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+  * @brief  Check whether the specified RNG flag is set or not.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __FLAG__: RNG flag
+  *          This parameter can be one of the following values:
+  *            @arg RNG_FLAG_DRDY:  Data ready                
+  *            @arg RNG_FLAG_CECS:  Clock error current status
+  *            @arg RNG_FLAG_SECS:  Seed error current status 
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+
+/**
+  * @brief  Clear the selected RNG flag status.
+  * @param  __HANDLE__: RNG handle
+  * @param  __FLAG__: RNG flag to clear  
+  * @note   WARNING: This is a dummy macro for HAL code alignment,
+  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
+
+
+
+/**
+  * @brief  Enable the RNG interrupt.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
+    
+/**
+  * @brief  Disable the RNG interrupt.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+  * @brief  Check whether the specified RNG interrupt has occurred or not.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RNG_IT_DRDY: Data ready interrupt              
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
+
+/**
+  * @brief  Clear the RNG interrupt status flags.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+  *          This parameter can be one of the following values:            
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
+
+/**
+  * @}
+  */ 
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */  
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+/**
+  * @}
+  */ 
+
+/* Peripheral Control functions  ************************************************/
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
+/**
+  * @}
+  */ 
+
+/* Peripheral State functions  **************************************************/
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c
new file mode 100755
index 0000000..636adf2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c
@@ -0,0 +1,1541 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rtc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   RTC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           + Initialization
+  *           + Calendar (Time and Date) configuration
+  *           + Alarms (Alarm A and Alarm B) configuration
+  *           + WakeUp Timer configuration
+  *           + TimeStamp configuration
+  *           + Tampers configuration
+  *           + Backup Data Registers configuration  
+  *           + RTC Tamper and TimeStamp Pins Selection 
+  *           + Interrupts and flags management
+  *         
+  @verbatim
+ ===============================================================================   
+                          ##### RTC Operating Condition #####
+ ===============================================================================
+  [..] The real-time clock (RTC) and the RTC backup registers can be powered
+       from the VBAT voltage when the main VDD supply is powered off.
+       To retain the content of the RTC backup registers and supply the RTC 
+       when VDD is turned off, VBAT pin can be connected to an optional
+       standby voltage supplied by a battery or by another source.
+
+                   ##### Backup Domain Reset #####
+ ===============================================================================
+  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
+       to their reset values. 
+       A backup domain reset is generated when one of the following events occurs:
+    (#) Software reset, triggered by setting the BDRST bit in the 
+        RCC Backup domain control register (RCC_BDCR).
+    (#) VDD or VBAT power on, if both supplies have previously been powered off.
+    (#) Tamper detection event resets all data backup registers.
+
+                   ##### Backup Domain Access #####
+ ===================================================================
+  [..] After reset, the backup domain (RTC registers, RTC backup data 
+       registers and backup SRAM) is protected against possible unwanted write 
+       accesses.
+
+  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+    (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
+        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
+    (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
+
+                  ##### How to use RTC Driver #####
+ ===================================================================
+  [..]
+    (#) Enable the RTC domain access (see description in the section above).
+    (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+        format using the HAL_RTC_Init() function.
+
+  *** Time and Date configuration ***
+  ===================================
+  [..] 
+    (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+        and HAL_RTC_SetDate() functions.
+    (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+  *** Alarm configuration ***
+  ===========================
+  [..]
+    (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+            You can also configure the RTC Alarm with interrupt mode using the 
+            HAL_RTC_SetAlarm_IT() function.
+    (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+                  ##### RTC and low power modes #####
+ ===================================================================
+  [..] The MCU can be woken up from a low power mode by an RTC alternate
+       function.
+  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+       These RTC alternate functions can wake up the system from the Stop and 
+       Standby low power modes.
+  [..] The system can also wake up from low power modes without depending
+       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+       or the RTC wakeup events.
+  [..] The RTC provides a programmable time base for waking up from the
+       Stop or Standby mode at regular intervals.
+       Wakeup from STOP and Standby modes is possible only when the RTC clock source
+       is LSE or LSI.
+
+   @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RTC RTC
+  * @brief RTC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+  * @{
+  */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+   [..] This section provide functions allowing to initialize and configure the 
+         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable 
+         RTC registers Write protection, enter and exit the RTC initialization mode,
+         RTC registers synchronization check and reference clock detection enable.
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+             It is split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the 
+                 asynchronous prescaler to a high value to minimize power consumption.
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WPR.
+         (#) To configure the RTC Calendar, user application should enter 
+             initialization mode. In this mode, the calendar counter is stopped
+             and its value can be updated. When the initialization sequence is 
+             complete, the calendar restarts counting after 4 RTCCLK cycles.
+         (#) To read the calendar through the shadow registers after Calendar 
+             initialization, calendar update or after wakeup from low power modes
+             the software must first clear the RSF flag. The software must then
+             wait until it is set again before reading the calendar, which means
+             that the calendar registers have been correctly copied into the
+             RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function 
+             implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the RTC according to the specified parameters 
+  *         in the RTC_InitTypeDef structure and initialize the associated handle.
+  * @param  hrtc: RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+  /* Check the RTC peripheral state */
+  if(hrtc == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+  assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+  assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
+  assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+  
+  if(hrtc->State == HAL_RTC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hrtc->Lock = HAL_UNLOCKED;
+
+    /* Initialize RTC MSP */
+    HAL_RTC_MspInit(hrtc);
+  }
+
+  /* Set RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Clear RTC_CR FMT, OSEL and POL Bits */
+    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+    /* Set RTC_CR register */
+    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+    /* Configure the RTC PRER */
+    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
+    hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
+
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_READY;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  DeInitialize the RTC peripheral.
+  * @param  hrtc: RTC handle
+  * @note   This function doesn't reset the RTC Backup Data registers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+
+  /* Set RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    hrtc->Instance->TR = (uint32_t)0x00000000;
+    hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+    /* Reset All CR bits except CR[2:0] */
+    hrtc->Instance->CR &= RTC_CR_WUCKSEL;
+
+    tickstart = HAL_GetTick();
+
+    /* Wait till WUTWF flag is set and if Time out is reached exit */
+    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        /* Set RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Reset all RTC CR register bits */
+    hrtc->Instance->CR &= (uint32_t)0x00000000;
+    hrtc->Instance->WUTR = RTC_WUTR_WUT;
+    hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
+    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
+    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
+    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
+    hrtc->Instance->CALR = (uint32_t)0x00000000;
+    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
+    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
+
+    /* Reset ISR register and exit initialization mode */
+    hrtc->Instance->ISR = (uint32_t)0x00000000;
+
+    /* Reset Tamper configuration register */
+    hrtc->Instance->TAMPCR = 0x00000000;
+
+    /* Reset Option register */
+    hrtc->Instance->OR = 0x00000000;
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+
+        hrtc->State = HAL_RTC_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* De-Initialize RTC MSP */
+  HAL_RTC_MspDeInit(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the RTC MSP.
+  * @param  hrtc: RTC handle  
+  * @retval None
+  */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the RTC MSP.
+  * @param  hrtc: RTC handle 
+  * @retval None
+  */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTC_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ *  @brief   RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+                 ##### RTC Time and Date functions #####
+ ===============================================================================
+ 
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set RTC current time.
+  * @param  hrtc: RTC handle
+  * @param  sTime: Pointer to Time structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FORMAT_BIN: Binary data format 
+  *            @arg RTC_FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+  uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  if(Format == RTC_FORMAT_BIN)
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(sTime->Hours));
+      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+    }
+    else
+    {
+      sTime->TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(sTime->Hours));
+    }
+    assert_param(IS_RTC_MINUTES(sTime->Minutes));
+    assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
+                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
+                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+                        (((uint32_t)sTime->TimeFormat) << 16));
+  }
+  else
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(sTime->Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+    }
+    else
+    {
+      sTime->TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
+              ((uint32_t)(sTime->Minutes) << 8) | \
+              ((uint32_t)sTime->Seconds) | \
+              ((uint32_t)(sTime->TimeFormat) << 16));
+  }
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_ERROR;
+
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set the RTC_TR register */
+    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    /* Clear the bits to be configured */
+    hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
+
+    /* Configure the RTC_CR register */
+    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
+
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_ERROR;
+
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+    
+   hrtc->State = HAL_RTC_STATE_READY;
+
+   __HAL_UNLOCK(hrtc); 
+
+   return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Get RTC current time.
+  * @param  hrtc: RTC handle
+  * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned 
+  *                with input format (BIN or BCD), also SubSeconds field returning the
+  *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
+  *                factor to be used for second fraction ratio computation.
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FORMAT_BIN: Binary data format 
+  *            @arg RTC_FORMAT_BCD: BCD data format
+  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+  *        value in second fraction ratio with time unit following generic formula:
+  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
+  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
+  *        to ensure consistency between the time and date values.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+  /* Get subseconds structure field from the corresponding register*/
+  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+  /* Get SecondFraction structure field from the corresponding register field*/
+  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
+  
+  /* Get the TR register */
+  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
+  /* Fill the structure fields with the read parameters */
+  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
+
+  /* Check the input parameters format */
+  if(Format == RTC_FORMAT_BIN)
+  {
+    /* Convert the time structure parameters to Binary format */
+    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set RTC current date.
+  * @param  hrtc: RTC handle
+  * @param  sDate: Pointer to date structure
+  * @param  Format: specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FORMAT_BIN: Binary data format 
+  *            @arg RTC_FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+  uint32_t datetmpreg = 0;
+
+ /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
+  {
+    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
+  }
+
+  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+  if(Format == RTC_FORMAT_BIN)
+  {
+    assert_param(IS_RTC_YEAR(sDate->Year));
+    assert_param(IS_RTC_MONTH(sDate->Month));
+    assert_param(IS_RTC_DATE(sDate->Date));
+
+   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
+                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
+                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+                 ((uint32_t)sDate->WeekDay << 13));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+    datetmpreg = RTC_Bcd2ToByte(sDate->Month);
+    assert_param(IS_RTC_MONTH(datetmpreg));
+    datetmpreg = RTC_Bcd2ToByte(sDate->Date);
+    assert_param(IS_RTC_DATE(datetmpreg));
+
+    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
+                  (((uint32_t)sDate->Month) << 8) | \
+                  ((uint32_t)sDate->Date) | \
+                  (((uint32_t)sDate->WeekDay) << 13));
+  }
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set the RTC_DR register */
+    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+
+        hrtc->State = HAL_RTC_STATE_ERROR;
+
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    hrtc->State = HAL_RTC_STATE_READY ;
+
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Get RTC current date.
+  * @param  hrtc: RTC handle
+  * @param  sDate: Pointer to Date structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FORMAT_BIN:  Binary data format 
+  *            @arg RTC_FORMAT_BCD:  BCD data format
+  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
+  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+  uint32_t datetmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+  /* Get the DR register */
+  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the structure fields with the read parameters */
+  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); 
+
+  /* Check the input parameters format */
+  if(Format == RTC_FORMAT_BIN)
+  {
+    /* Convert the date structure parameters to Binary format */
+    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ *  @brief   RTC Alarm functions
+ *
+@verbatim   
+ ===============================================================================
+                 ##### RTC Alarm functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @param  hrtc: RTC handle
+  * @param  sAlarm: Pointer to Alarm structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_FORMAT_BIN: Binary data format 
+  *             @arg RTC_FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+  uint32_t tickstart = 0;
+  uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  if(Format == RTC_FORMAT_BIN)
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+    }
+    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+    }
+
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask));
+  }
+  else
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+    }
+
+    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask));   
+  }
+
+  /* Configure the Alarm A or Alarm B Sub Second registers */
+  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the Alarm register */
+  if(sAlarm->Alarm == RTC_ALARM_A)
+  {
+    /* Disable the Alarm A interrupt */
+    __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+    tickstart = HAL_GetTick();
+    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+    /* Configure the Alarm A Sub Second register */
+    hrtc->Instance->ALRMASSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMA_ENABLE(hrtc);
+  }
+  else
+  {
+    /* Disable the Alarm B interrupt */
+    __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
+
+    tickstart = HAL_GetTick();
+    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+    /* Configure the Alarm B Sub Second register */
+    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMB_ENABLE(hrtc);
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the specified RTC Alarm with Interrupt.
+  * @param  hrtc: RTC handle
+  * @param  sAlarm: Pointer to Alarm structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_FORMAT_BIN: Binary data format 
+  *             @arg RTC_FORMAT_BCD: BCD data format
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).   
+  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+  uint32_t tickstart = 0;
+  uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  if(Format == RTC_FORMAT_BIN)
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+    }
+    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+    }
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask));
+  }
+  else
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    } 
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+    
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+    }
+    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask));     
+  }
+  /* Configure the Alarm A or Alarm B Sub Second registers */
+  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the Alarm register */
+  if(sAlarm->Alarm == RTC_ALARM_A)
+  {
+    /* Disable the Alarm A interrupt */
+    __HAL_RTC_ALARMA_DISABLE(hrtc);
+    
+    /* Clear flag alarm A */
+    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+    tickstart = HAL_GetTick();
+    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+    /* Configure the Alarm A Sub Second register */
+    hrtc->Instance->ALRMASSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMA_ENABLE(hrtc);
+    /* Configure the Alarm interrupt */
+    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+  }
+  else
+  {
+    /* Disable the Alarm B interrupt */
+    __HAL_RTC_ALARMB_DISABLE(hrtc);
+    
+    /* Clear flag alarm B */
+    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+    tickstart = HAL_GetTick();
+    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+    /* Configure the Alarm B Sub Second register */
+    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMB_ENABLE(hrtc);
+    /* Configure the Alarm interrupt */
+    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
+  }
+
+  /* RTC Alarm Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+
+  __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY; 
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate the specified RTC Alarm.
+  * @param  hrtc: RTC handle
+  * @param  Alarm: Specifies the Alarm.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_ALARM_A:  AlarmA
+  *            @arg RTC_ALARM_B:  AlarmB
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(Alarm));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  if(Alarm == RTC_ALARM_A)
+  {
+    /* AlarmA */
+    __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+    tickstart = HAL_GetTick();
+
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    {
+      if( (HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else
+  {
+    /* AlarmB */
+    __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
+
+    tickstart = HAL_GetTick();
+
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  hrtc: RTC handle
+  * @param  sAlarm: Pointer to Date structure
+  * @param  Alarm: Specifies the Alarm.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_ALARM_A: AlarmA
+  *             @arg RTC_ALARM_B: AlarmB  
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_FORMAT_BIN: Binary data format 
+  *             @arg RTC_FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+  uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_RTC_ALARM(Alarm));
+
+  if(Alarm == RTC_ALARM_A)
+  {
+    /* AlarmA */
+    sAlarm->Alarm = RTC_ALARM_A;
+
+    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
+  }
+  else
+  {
+    sAlarm->Alarm = RTC_ALARM_B;
+
+    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
+    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
+  }
+
+  /* Fill the structure with the read parameters */
+  /* ALRMAR/ALRMBR registers have same mapping)  */
+  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
+  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
+  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+
+  if(Format == RTC_FORMAT_BIN)
+  {
+    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle Alarm interrupt request.
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
+{
+  /* Clear the EXTI's line Flag for RTC Alarm */
+  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
+
+  /* As alarms are sharing the same EXTI line, exit when no more pending Alarm event */
+  while(((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) ||
+        ((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)))
+  {
+    /* Get the AlarmA interrupt source enable status and pending flag status*/
+    if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET))
+    {
+      /* Clear the AlarmA interrupt pending bit */
+      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+      /* AlarmA callback */
+      HAL_RTC_AlarmAEventCallback(hrtc);
+    }
+
+    /* Get the AlarmB interrupt source enable status and pending flag status*/
+    if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET))
+    {
+      /* Clear the AlarmB interrupt pending bit */
+      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+      /* AlarmB callback */
+      HAL_RTCEx_AlarmBEventCallback(hrtc);
+    }
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+  * @brief  Alarm A callback.
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Handle AlarmA Polling request.
+  * @param  hrtc: RTC handle
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+
+  uint32_t tickstart = HAL_GetTick();   
+  
+  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Clear the Alarm interrupt pending bit */
+  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions 
+ *  @brief   Peripheral Control functions 
+ *
+@verbatim
+ ===============================================================================
+                     ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  hrtc: RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+{
+  uint32_t tickstart = 0;
+
+  /* Clear RSF flag */
+  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
+
+  tickstart = HAL_GetTick();
+
+  /* Wait the registers to be synchronised */
+  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Get RTC state
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the RTC handle state.
+  * @param  hrtc: RTC handle
+  * @retval HAL state
+  */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+{
+  /* Return RTC handle state */
+  return hrtc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Functions RTC Private functions
+  * @{
+  */
+/**
+  * @brief  Enter the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+  * @param  hrtc: RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+{
+  uint32_t tickstart = 0;
+
+  /* Check if the Initialization mode is set */
+  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+
+    tickstart = HAL_GetTick();
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+    {
+      if((HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Convert a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted
+  * @retval Converted byte
+  */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint32_t bcdhigh = 0;
+
+  while(Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted
+  * @retval Converted word
+  */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint32_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h
new file mode 100755
index 0000000..be41b87
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h
@@ -0,0 +1,863 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rtc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RTC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_RTC_H
+#define __STM32L4xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+  * @{
+  */
+/** 
+  * @brief  HAL State structures definition  
+  */
+typedef enum
+{
+  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
+  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
+  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */
+  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */
+  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */
+
+}HAL_RTCStateTypeDef;
+
+/** 
+  * @brief  RTC Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
+                                 This parameter can be a value of @ref RTC_Hour_Formats */
+
+  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+                               
+  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
+                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+
+  uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
+                                 This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
+
+  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
+                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
+                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
+                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
+  
+  uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
+                                 This parameter corresponds to a time unit range between [0-1] Second
+                                 with [1 Sec / SecondFraction +1] granularity */
+ 
+  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
+                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+                                 This parameter corresponds to a time unit range between [0-1] Second
+                                 with [1 Sec / SecondFraction +1] granularity.
+                                 This field will be used only by HAL_RTC_GetTime function */
+  
+  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
+                                 in CR register to store the operation.
+                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/** 
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
+                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t Date;     /*!< Specifies the RTC Date.
+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+  uint8_t Year;     /*!< Specifies the RTC Date Year.
+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition
+  */
+typedef struct
+{
+  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
+
+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+  
+  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
+                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+  uint32_t Alarm;                /*!< Specifies the alarm .
+                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/** 
+  * @brief  Time Handle Structure definition
+  */
+typedef struct
+{
+  RTC_TypeDef               *Instance;  /*!< Register base address    */
+
+  RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
+
+  HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
+
+  __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+  * @{
+  */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+  * @{
+  */
+#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+  * @{
+  */
+#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+  * @{
+  */
+#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMOUTTYPE)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
+  * @{
+  */
+#define RTC_OUTPUT_REMAP_NONE          ((uint32_t)0x00000000)
+#define RTC_OUTPUT_REMAP_POS1          ((uint32_t)RTC_OR_OUT_RMP)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+  * @{
+  */
+#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
+  * @{
+  */
+#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
+  * @{
+  */
+#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
+  * @{
+  */
+#define RTC_FORMAT_BIN                  ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD                  ((uint32_t)0x000000001)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+  * @{
+  */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
+#define RTC_MONTH_MARCH                ((uint8_t)0x03)
+#define RTC_MONTH_APRIL                ((uint8_t)0x04)
+#define RTC_MONTH_MAY                  ((uint8_t)0x05)
+#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
+#define RTC_MONTH_JULY                 ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+  * @{
+  */
+#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
+  * @{
+  */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
+  * @{
+  */
+#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+  * @{
+  */
+#define RTC_ALARM_A                       RTC_CR_ALRAE
+#define RTC_ALARM_B                       RTC_CR_ALRBE
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+  * @{
+  */
+#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked.
+                                                                        There is no comparison on sub seconds
+                                                                        for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm
+                                                                        comparison. Only SS[0] is compared.    */
+#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm
+                                                                        comparison. Only SS[1:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm
+                                                                        comparison. Only SS[2:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm
+                                                                        comparison. Only SS[3:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm
+                                                                        comparison. Only SS[4:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm
+                                                                        comparison. Only SS[5:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm
+                                                                        comparison. Only SS[6:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm
+                                                                        comparison. Only SS[7:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm
+                                                                        comparison. Only SS[8:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm
+                                                                        comparison. Only SS[9:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm
+                                                                        comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm
+                                                                        comparison. Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm
+                                                                        comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm
+                                                                        comparison. Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match
+                                                                        to activate alarm. */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+  * @{
+  */
+#define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)        /*!< Enable Timestamp Interrupt    */
+#define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)       /*!< Enable Wakeup timer Interrupt */
+#define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)      /*!< Enable Alarm A Interrupt      */
+#define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)      /*!< Enable Alarm B Interrupt      */
+#define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE)  /*!< Enable all Tamper Interrupt   */
+#define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt     */
+#define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt     */
+#define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt     */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+  * @{
+  */
+#define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
+#define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
+#define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
+#define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
+#define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
+#define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
+#define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
+#define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
+#define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
+#define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
+#define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
+#define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
+#define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
+#define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
+#define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+  * @{
+  */
+
+/** @brief Reset RTC handle state.
+  * @param  __HANDLE__: RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+  * @brief  Disable the write protection for RTC registers.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
+                        do{                                       \
+                            (__HANDLE__)->Instance->WPR = 0xCA;   \
+                            (__HANDLE__)->Instance->WPR = 0x53;   \
+                          } while(0)
+
+/**
+  * @brief  Enable the write protection for RTC registers.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
+                        do{                                       \
+                            (__HANDLE__)->Instance->WPR = 0xFF;   \
+                          } while(0)
+
+
+/**
+  * @brief  Enable the RTC ALARMA peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+  * @brief  Disable the RTC ALARMA peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+  * @brief  Enable the RTC ALARMB peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+  * @brief  Disable the RTC ALARMB peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+  * @brief  Enable the RTC Alarm interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *             @arg RTC_IT_ALRA: Alarm A interrupt
+  *             @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC Alarm interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC Alarm's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to check.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_ALRAF
+  *            @arg RTC_FLAG_ALRBF
+  *            @arg RTC_FLAG_ALRAWF
+  *            @arg RTC_FLAG_ALRBWF
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Alarm's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_ALRAF
+  *             @arg RTC_FLAG_ALRBF
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt is enabled or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Enable interrupt on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable interrupt on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable event on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable event on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
+                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
+                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
+                                                           } while(0)
+
+/**
+  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
+                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
+                                                           } while(0)
+
+/**
+  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+  * @retval Line Status.
+  */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief Clear the RTC Alarm associated Exti line flag.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @}
+  */
+
+/* Include RTC HAL Extended module */
+#include "stm32l4xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+  * @{
+  */
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+  * @{
+  */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group5
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/ 
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+  * @{
+  */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
+
+#define RTC_TIMEOUT_VALUE  1000
+  
+#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the RTC Alarm event */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+  * @{
+  */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+  * @{
+  */ 
+
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
+                                        ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+#define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
+                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))
+
+#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+                                           ((OPERATION) == RTC_STOREOPERATION_SET))
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
+
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+
+#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
+
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
+
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
+
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
+
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RTC_Private_Functions
+  * @{
+  */
+
+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t            RTC_ByteToBcd2(uint8_t Value);
+uint8_t            RTC_Bcd2ToByte(uint8_t Value);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c
new file mode 100755
index 0000000..0f334cd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c
@@ -0,0 +1,1877 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rtc_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended RTC HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Real Time Clock (RTC) Extended peripheral:
+  *           + RTC Time Stamp functions
+  *           + RTC Tamper functions 
+  *           + RTC Wake-up functions
+  *           + Extended Control functions
+  *           + Extended RTC features functions    
+  *
+  @verbatim
+  ==============================================================================
+                  ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (+) Enable the RTC domain access.
+    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+        format using the HAL_RTC_Init() function.
+
+  *** RTC Wakeup configuration ***
+  ================================
+  [..] 
+    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+        function. You can also configure the RTC Wakeup timer with interrupt mode 
+        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+        function.
+        
+  *** Outputs configuration ***
+  =============================
+  [..]  The RTC has 2 different outputs:
+    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
+        and WaKeUp signals.
+        To output the selected RTC signal, use the HAL_RTC_Init() function.             
+    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
+        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
+    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on 
+        the RTC_OR register.
+    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
+        automatically configured in output alternate function. 
+
+  *** Smooth digital Calibration configuration ***
+  ================================================
+  [..]
+    (+) Configure the RTC Original Digital Calibration Value and the corresponding
+        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() 
+        function.
+
+  *** TimeStamp configuration ***
+  ===============================
+  [..]
+    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
+        You can also configure the RTC TimeStamp with interrupt mode using the
+        HAL_RTCEx_SetTimeStamp_IT() function.
+    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+        function.
+
+  *** Internal TimeStamp configuration ***
+  ===============================
+  [..]
+    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
+        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
+    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+        function.
+
+  *** Tamper configuration ***
+  ============================
+  [..]
+    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge 
+        or Level according to the Tamper filter (if equal to 0 Edge else Level) 
+        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
+        Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
+        with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
+    (+) The default configuration of the Tamper erases the backup registers. To avoid
+        erase, enable the NoErase field on the RTC_TAMPCR register.
+
+  *** Backup Data Registers configuration ***
+  ===========================================
+  [..]
+    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+        function.
+    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+        function.
+
+   @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RTCEx RTCEx
+  * @brief RTC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
+#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
+                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
+                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
+                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
+                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
+                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
+#elif defined(RTC_TAMPER1_SUPPORT)
+#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
+                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
+                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
+                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
+                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
+#elif defined(RTC_TAMPER3_SUPPORT)
+#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
+                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
+                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
+                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
+                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
+#else
+#define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
+                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
+                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
+                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
+#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+  * @{
+  */
+
+
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
+ *  @brief   RTC TimeStamp and Tamper functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+ 
+ [..] This section provide functions allowing to configure TimeStamp feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set TimeStamp.
+  * @note   This API must be called before enabling the TimeStamp feature.
+  * @param  hrtc: RTC handle
+  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+  *         activated.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
+  *                                        rising edge of the related pin.
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
+  *                                         falling edge of the related pin.
+  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+  *               The RTC TimeStamp Pin is per default PC13, but for reasons of
+  *               compatibility, this parameter is required.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  tmpreg|= TimeStampEdge;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  hrtc->Instance->CR = (uint32_t)tmpreg;
+
+  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set TimeStamp with Interrupt.
+  * @param  hrtc: RTC handle
+  * @note   This API must be called before enabling the TimeStamp feature.
+  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+  *         activated.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
+  *                                        rising edge of the related pin.
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
+  *                                         falling edge of the related pin.
+  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+  *               The RTC TimeStamp Pin is per default PC13, but for reasons of
+  *               compatibility, this parameter is required.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  tmpreg |= TimeStampEdge;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  hrtc->Instance->CR = (uint32_t)tmpreg;
+
+  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+  /* Enable IT timestamp */
+  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
+
+  /* RTC timestamp Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate TimeStamp.
+  * @param  hrtc: RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t tmpreg = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* In case of interrupt mode is used, the interrupt source must disabled */
+  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  hrtc->Instance->CR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Internal TimeStamp.
+  * @note   This API must be called before enabling the internal TimeStamp feature.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the internal Time Stamp Enable bits */
+  __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate Internal TimeStamp.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the internal Time Stamp Enable bits */
+  __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RTC TimeStamp value.
+  * @param  hrtc: RTC handle
+  * @param  sTimeStamp: Pointer to Time structure
+  * @param  sTimeStampDate: Pointer to Date structure
+  * @param  Format: specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_FORMAT_BIN: Binary data format 
+  *             @arg RTC_FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
+  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
+
+  /* Fill the Date structure fields with the read parameters */
+  sTimeStampDate->Year = 0;
+  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if(Format == RTC_FORMAT_BIN)
+  {
+    /* Convert the TimeStamp structure parameters to Binary format */
+    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+    /* Convert the DateTimeStamp structure parameters to Binary format */
+    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+  }
+
+  /* Clear the TIMESTAMP Flags */
+  __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
+  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Tamper.
+  * @note   By calling this API we disable the tamper interrupt for all tampers.
+  * @param  hrtc: RTC handle
+  * @param  sTamper: Pointer to Tamper Structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
+  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
+  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Configure the tamper trigger */
+  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+  { 
+    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); 
+  }
+
+  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+  { 
+    sTamper->NoErase = 0;
+#if defined(RTC_TAMPER1_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
+    {
+      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
+    }
+#endif /* RTC_TAMPER1_SUPPORT */
+    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
+    {
+      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
+    }
+#if defined(RTC_TAMPER3_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
+    {
+      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
+    }
+#endif /* RTC_TAMPER3_SUPPORT */
+  }
+
+  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
+  {
+    sTamper->MaskFlag = 0;
+#if defined(RTC_TAMPER1_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
+    {
+      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
+    }
+#endif /* RTC_TAMPER1_SUPPORT */
+    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
+    {
+      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
+    }
+#if defined(RTC_TAMPER3_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
+    {
+      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
+    }
+#endif /* RTC_TAMPER3_SUPPORT */
+  }
+
+  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
+            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
+            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
+
+  hrtc->Instance->TAMPCR |= tmpreg;
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Tamper with interrupt.
+  * @note   By calling this API we force the tamper interrupt for all tampers.
+  * @param  hrtc: RTC handle
+  * @param  sTamper: Pointer to RTC Tamper.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+  assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
+  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
+  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
+  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Configure the tamper trigger */
+  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+  {
+    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
+  }
+
+  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+  { 
+    sTamper->NoErase = 0;
+#if defined(RTC_TAMPER1_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
+    {
+      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
+    }
+#endif /* RTC_TAMPER1_SUPPORT */
+    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
+    {
+      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
+    }
+#if defined(RTC_TAMPER3_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
+    {
+      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
+    }
+#endif /* RTC_TAMPER3_SUPPORT */
+  }
+
+  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
+  {
+    sTamper->MaskFlag = 0;
+#if defined(RTC_TAMPER1_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_1) != 0)
+    {
+      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
+    }
+#endif /* RTC_TAMPER1_SUPPORT */
+    if((sTamper->Tamper & RTC_TAMPER_2) != 0)
+    {
+      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
+    }
+#if defined(RTC_TAMPER3_SUPPORT)
+    if((sTamper->Tamper & RTC_TAMPER_3) != 0)
+    {
+      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
+    }
+#endif /* RTC_TAMPER3_SUPPORT */
+  }
+
+  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
+            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
+            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
+  
+  hrtc->Instance->TAMPCR |= tmpreg;
+
+  /* RTC Tamper Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate Tamper.
+  * @param  hrtc: RTC handle
+  * @param  Tamper: Selected tamper pin.
+  *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+  assert_param(IS_RTC_TAMPER(Tamper));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the selected Tamper pin */
+  hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
+
+#if defined(RTC_TAMPER1_SUPPORT)
+  if ((Tamper & RTC_TAMPER_1) != 0)
+  {
+    /* Disable the Tamper1 interrupt */
+    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
+  }
+#endif /* RTC_TAMPER1_SUPPORT */
+  if ((Tamper & RTC_TAMPER_2) != 0)
+  {
+    /* Disable the Tamper2 interrupt */
+    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
+  }
+#if defined(RTC_TAMPER3_SUPPORT)
+  if ((Tamper & RTC_TAMPER_3) != 0)
+  {
+    /* Disable the Tamper3 interrupt */
+    hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
+  }
+#endif /* RTC_TAMPER3_SUPPORT */
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle TimeStamp interrupt request.
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{ 
+  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
+  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
+
+  /* As Tampers and TimeStamp are sharing the same EXTI line, exit when no more pending event */
+  while(
+        ((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET))
+#if defined(RTC_TAMPER1_SUPPORT)
+        || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET))
+#endif /* RTC_TAMPER1_SUPPORT */
+        || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET))
+#if defined(RTC_TAMPER3_SUPPORT)
+        || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET))
+#endif /* RTC_TAMPER3_SUPPORT */
+       )
+  {
+        
+    /* Get the TimeStamp interrupt source enable status and pending flag status */
+    if((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET))
+    {
+      /* TIMESTAMP callback */ 
+      HAL_RTCEx_TimeStampEventCallback(hrtc);
+      
+      /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */
+      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+    }
+
+#if defined(RTC_TAMPER1_SUPPORT)
+    /* Get the Tamper1 interrupt source enable status and pending flag status */
+    if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET))
+    {
+      /* Clear the Tamper1 interrupt pending bit */
+      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+      
+      /* Tamper1 callback */
+      HAL_RTCEx_Tamper1EventCallback(hrtc);
+    }
+#endif /* RTC_TAMPER1_SUPPORT */
+    
+    /* Get the Tamper2 interrupt source enable status and pending flag status */
+    if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET))
+    {
+      /* Clear the Tamper2 interrupt pending bit */
+      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+      
+      /* Tamper2 callback */
+      HAL_RTCEx_Tamper2EventCallback(hrtc);
+    }
+
+#if defined(RTC_TAMPER3_SUPPORT)
+    /* Get the Tamper3 interrupts source enable status and pending flag status */
+    if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET))
+    {
+      /* Clear the Tamper3 interrupt pending bit */
+      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+      
+      /* Tamper3 callback */
+      HAL_RTCEx_Tamper3EventCallback(hrtc);
+    }
+#endif /* RTC_TAMPER3_SUPPORT */
+  
+  }
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+  * @brief  TimeStamp callback. 
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+  */
+}
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Tamper 1 callback.
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+   */
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Tamper 2 callback. 
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+   */
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Tamper 3 callback. 
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+   */
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+/**
+  * @brief  Handle TimeStamp polling request.
+  * @param  hrtc: RTC handle
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{ 
+  uint32_t tickstart = HAL_GetTick();
+
+  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+  {
+    if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+    {
+      /* Clear the TIMESTAMP OverRun Flag */
+      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+      /* Change TIMESTAMP state */
+      hrtc->State = HAL_RTC_STATE_ERROR; 
+
+      return HAL_ERROR; 
+    }
+
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+  
+  return HAL_OK;
+}
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Handle Tamper 1 Polling.
+  * @param  hrtc: RTC handle
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Get the status of the Interrupt */
+  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Clear the Tamper Flag */
+  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+  
+  return HAL_OK; 
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Handle Tamper 2 Polling.
+  * @param  hrtc: RTC handle
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Get the status of the Interrupt */
+  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Clear the Tamper Flag */
+  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Handle Tamper 3 Polling.
+  * @param  hrtc: RTC handle
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Get the status of the Interrupt */
+  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Clear the Tamper Flag */
+  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
+  * @brief    RTC Wake-up functions
+  *
+@verbatim   
+ ===============================================================================
+                        ##### RTC Wake-up functions #####
+ ===============================================================================  
+
+ [..] This section provide functions allowing to configure Wake-up feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set wake up timer.
+  * @param  hrtc: RTC handle
+  * @param  WakeUpCounter: Wake up counter
+  * @param  WakeUpClock: Wake up clock
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+  {
+    tickstart = HAL_GetTick();
+
+    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+      /* Process Unlocked */ 
+      __HAL_UNLOCK(hrtc);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+  /* Configure the Wakeup Timer counter */
+  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+   /* Enable the Wakeup Timer */
+  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set wake up timer with interrupt.
+  * @param  hrtc: RTC handle
+  * @param  WakeUpCounter: Wake up counter
+  * @param  WakeUpClock: Wake up clock  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+  {
+    tickstart = HAL_GetTick();
+
+    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /* Disable the Wake-Up timer */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+  /* Clear flag Wake-Up */
+  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+
+      /* Process Unlocked */ 
+      __HAL_UNLOCK(hrtc);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the Wakeup Timer counter */
+  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+  /* Configure the Interrupt in the RTC_CR register */
+  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
+  
+  /* Enable the Wakeup Timer */
+  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY; 
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate wake up timer counter.
+  * @param  hrtc: RTC handle 
+  * @retval HAL status
+  */
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t tickstart = 0;
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Disable the Wakeup Timer */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+  /* In case of interrupt mode is used, the interrupt source must disabled */
+  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+
+  tickstart = HAL_GetTick();
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hrtc);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get wake up timer counter.
+  * @param  hrtc: RTC handle 
+  * @retval Counter value
+  */
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+  /* Get the counter value */
+  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+  * @brief  Handle Wake Up Timer interrupt request.
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+  
+  /* Get the pending status of the WAKEUPTIMER Interrupt */
+  if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
+  {   
+    /* Clear the WAKEUPTIMER interrupt pending bit */
+    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+    /* WAKEUPTIMER callback */ 
+    HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+  * @brief  Wake Up Timer callback.
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Handle Wake Up Timer Polling.
+  * @param  hrtc: RTC handle
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+      
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Clear the WAKEUPTIMER Flag */
+  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim   
+ ===============================================================================
+              ##### Extended Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Write a data in a specified RTC Backup data register
+      (+) Read a data in a specified RTC Backup data register
+      (+) Set the Coarse calibration parameters.
+      (+) Deactivate the Coarse calibration parameters
+      (+) Set the Smooth calibration parameters.
+      (+) Configure the Synchronization Shift Control Settings.
+      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+      (+) Enable the RTC reference clock detection.
+      (+) Disable the RTC reference clock detection.
+      (+) Enable the Bypass Shadow feature.
+      (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Write a data in a specified RTC Backup data register.
+  * @param  hrtc: RTC handle 
+  * @param  BackupRegister: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                                 specify the register.
+  * @param  Data: Data to be written in the specified RTC Backup data register.
+  * @retval None
+  */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(BackupRegister));
+
+  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+  tmp += (BackupRegister * 4);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Read data from the specified RTC Backup data Register.
+  * @param  hrtc: RTC handle 
+  * @param  BackupRegister: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                                 specify the register.
+  * @retval Read value
+  */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(BackupRegister));
+
+  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+  tmp += (BackupRegister * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @brief  Set the Smooth calibration parameters.
+  * @param  hrtc: RTC handle  
+  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
+  *          This parameter can be can be one of the following values :
+  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+  * @param  SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *          This parameter can be one any value from 0 to 0x000001FF.
+  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses 
+  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+  *         SmoothCalibMinusPulsesValue must be equal to 0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* check if a calibration is pending*/
+  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    tickstart = HAL_GetTick();
+
+    /* check if a calibration is pending*/
+    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Configure the Smooth calibration settings */
+  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register. 
+  * @param  hrtc: RTC handle    
+  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
+  *          This parameter can be one of the following values :
+  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. 
+  *             @arg RTC_SHIFTADD1S_RESET: No effect.
+  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
+  *          This parameter can be one any value from 0 to 0x7FFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+    tickstart = HAL_GetTick();
+
+    /* Wait until the shift is completed*/
+    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check if the reference clock detection is disabled */
+    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+
+      /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+      if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+      {
+        if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+        {
+          /* Enable the write protection for RTC registers */
+          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+          hrtc->State = HAL_RTC_STATE_ERROR;
+
+          /* Process Unlocked */ 
+          __HAL_UNLOCK(hrtc);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+    else
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+      
+      /* Change RTC state */
+      hrtc->State = HAL_RTC_STATE_ERROR;
+      
+      /* Process Unlocked */ 
+      __HAL_UNLOCK(hrtc);
+
+      return HAL_ERROR;
+    }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  hrtc: RTC handle
+  * @param  CalibOutput : Select the Calibration output Selection .
+  *          This parameter can be one of the following values:
+  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Clear flags before config */
+  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
+
+  /* Configure the RTC_CR register */
+  hrtc->Instance->CR |= (uint32_t)CalibOutput;
+
+  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  hrtc: RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the RTC reference clock detection.
+  * @param  hrtc: RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrtc);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
+
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+   /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the RTC reference clock detection.
+  * @param  hrtc: RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrtc);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
+
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the Bypass Shadow feature.
+  * @param  hrtc: RTC handle
+  * @note   When the Bypass Shadow is enabled the calendar value are taken
+  *         directly from the Calendar counter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set the BYPSHAD bit */
+  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Bypass Shadow feature.
+  * @param  hrtc: RTC handle
+  * @note   When the Bypass Shadow is enabled the calendar value are taken
+  *         directly from the Calendar counter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Reset the BYPSHAD bit */
+  hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+  * @brief    Extended features functions
+  *
+@verbatim   
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) RTC Alarm B callback
+      (+) RTC Poll for Alarm B request
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Alarm B callback.
+  * @param  hrtc: RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Handle Alarm B Polling request.
+  * @param  hrtc: RTC handle
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{ 
+  uint32_t tickstart = HAL_GetTick();
+  
+  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Clear the Alarm Flag */
+  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h
new file mode 100755
index 0000000..df4c98c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h
@@ -0,0 +1,1102 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rtc_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RTC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_RTC_EX_H
+#define __STM32L4xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RTCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+  * @{
+  */
+/**
+  * @brief  RTC Tamper structure definition
+  */
+typedef struct
+{
+  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
+                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
+
+  uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
+                                             This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
+
+  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
+                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
+
+  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
+                                             This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
+
+  uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
+                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
+
+  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+
+  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+
+  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
+                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+
+  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
+                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+
+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
+                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
+}RTC_TamperTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions
+  * @{
+  */
+#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
+  * @{
+  */
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
+#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
+#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
+#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
+#define RTC_BKP_DR20                      ((uint32_t)0x00000014)
+#define RTC_BKP_DR21                      ((uint32_t)0x00000015)
+#define RTC_BKP_DR22                      ((uint32_t)0x00000016)
+#define RTC_BKP_DR23                      ((uint32_t)0x00000017)
+#define RTC_BKP_DR24                      ((uint32_t)0x00000018)
+#define RTC_BKP_DR25                      ((uint32_t)0x00000019)
+#define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
+#define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
+#define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
+#define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
+#define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
+#define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions
+  * @{
+  */ 
+#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
+  * @{
+  */
+#define RTC_TIMESTAMPPIN_DEFAULT          ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E
+#endif /* RTC_TAMPER1_SUPPORT */
+#define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define RTC_TAMPER1_INTERRUPT              RTC_TAMPCR_TAMP1IE
+#endif /* RTC_TAMPER1_SUPPORT */
+#define RTC_TAMPER2_INTERRUPT              RTC_TAMPCR_TAMP2IE
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_TAMPER3_INTERRUPT              RTC_TAMPCR_TAMP3IE
+#endif /* RTC_TAMPER3_SUPPORT */
+#define RTC_ALL_TAMPER_INTERRUPT           RTC_TAMPCR_TAMPIE
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
+  * @{
+  */
+#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
+#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions
+* @{
+*/
+#define RTC_TAMPER_ERASE_BACKUP_ENABLE     ((uint32_t)0x00000000)
+#define RTC_TAMPER_ERASE_BACKUP_DISABLE    ((uint32_t)0x00020000)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions
+* @{
+*/
+#define RTC_TAMPERMASK_FLAG_DISABLE        ((uint32_t)0x00000000)
+#define RTC_TAMPERMASK_FLAG_ENABLE         ((uint32_t)0x00040000)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
+  * @{
+  */
+#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000)  /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800)  /*!< Tamper is activated after 2
+                                                                consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000)  /*!< Tamper is activated after 4
+                                                                consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800)  /*!< Tamper is activated after 8
+                                                                consecutive samples at the active level. */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
+  * @{
+  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 8192  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 4096  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 2048  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 1024  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 512   */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 256   */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
+  * @{
+  */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 1 RTCCLK cycle  */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 8 RTCCLK cycles */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
+  * @{
+  */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)         /*!< TimeStamp on Tamper Detection event is not saved */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
+  * @{
+  */
+#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000)              /*!< TimeStamp on Tamper Detection event saved        */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)    /*!< TimeStamp on Tamper Detection event is not saved */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions
+  * @{
+  */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
+  * @{
+  */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
+                                                                    period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
+                                                                    period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
+                                                                    period is 8s, else 2exp18 RTCCLK seconds */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
+  * @{
+  */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000)  /*!< The number of RTCCLK pulses added
+                                                                       during a X -second window = Y - CALM[8:0]
+                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000)  /*!< The number of RTCCLK pulses subbstited
+                                                                       during a 32-second window = CALM[8:0] */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
+  * @{
+  */
+#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000)
+#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
+  * @{
+  */
+#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the RTC WakeUp Timer peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+
+/**
+  * @brief  Disable the RTC WakeUp Timer peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+  * @brief  Enable the RTC WakeUpTimer interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
+  *         This parameter can be:
+  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC WakeUpTimer interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
+  *         This parameter can be:
+  *            @arg RTC_IT_WUT: WakeUpTimer interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Check whether the specified RTC Wake Up timer interrupt is enabled or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC WakeUpTimer's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_WUTF
+  *             @arg RTC_FLAG_WUTWF
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Wake Up timer's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_WUTF
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Enable the RTC Tamper1 input detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
+
+/**
+  * @brief  Disable the RTC Tamper1 input detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Enable the RTC Tamper2 input detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
+
+/**
+  * @brief  Disable the RTC Tamper2 input detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Enable the RTC Tamper3 input detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
+
+/**
+  * @brief  Disable the RTC Tamper3 input detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
+#endif /* RTC_TAMPER3_SUPPORT */
+
+/**
+  * @brief  Enable the RTC Tamper interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *             @arg  RTC_IT_TAMP: All tampers interrupts
+  *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
+  *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
+  *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
+  * @retval None
+  */   
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC Tamper interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg  RTC_IT_TAMP: All tampers interrupts
+  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
+  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
+  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+  *         This parameter can be:
+  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
+  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
+  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
+  * @retval None
+  */
+#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
+                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
+                                                                      (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
+#else
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET)
+#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
+
+/**
+  * @brief  Check whether the specified RTC Tamper interrupt is enabled or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+  *         This parameter can be:
+  *            @arg  RTC_IT_TAMP: All tampers interrupts
+  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
+  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
+  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC Tamper's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
+  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
+  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Tamper's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag sources to clear.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
+  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
+  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+  * @brief  Enable the RTC TimeStamp peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+  * @brief  Disable the RTC TimeStamp peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+  * @brief  Enable the RTC TimeStamp interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
+  *         This parameter can be:
+  *            @arg RTC_IT_TS: TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC TimeStamp interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. 
+  *         This parameter can be:
+  *            @arg RTC_IT_TS: TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_TS: TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Check whether the specified RTC Time Stamp interrupt is enabled or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_TS: TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC TimeStamp's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_TSF
+  *            @arg RTC_FLAG_TSOVF
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Time Stamp's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TSF
+  *             @arg RTC_FLAG_TSOVF
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+  * @brief  Enable the RTC internal TimeStamp peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
+
+/**
+  * @brief  Disable the RTC internal TimeStamp peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
+
+/**
+  * @brief  Get the selected RTC Internal Time Stamp's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_ITSF
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Internal Time Stamp's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_ITSF
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+  * @brief  Enable the RTC calibration output.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+  * @brief  Disable the calibration output.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+  * @brief  Enable the clock reference detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+  * @brief  Disable the clock reference detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+  * @brief  Get the selected RTC shift operation's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_SHPF
+  * @retval None
+  */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. 
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
+                                                                 } while(0)
+
+/**
+  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+  * This parameter can be:
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
+                                                                  } while(0)
+
+/**
+  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
+  * @retval Line Status.
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief Clear the RTC WakeUp Timer associated Exti line flag.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. 
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
+                                                                      } while(0)
+
+/**
+  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+  * This parameter can be:
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
+                                                                       } while(0)
+
+/**
+  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+  * @retval Line Status.
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTCEx_Exported_Functions
+  * @{
+  */
+
+/* RTC TimeStamp and Tamper functions *****************************************/
+/** @addtogroup RTCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+#if defined(RTC_TAMPER1_SUPPORT)
+void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+#endif /* RTC_TAMPER1_SUPPORT */
+void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+#if defined(RTC_TAMPER3_SUPPORT)
+void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
+#endif /* RTC_TAMPER3_SUPPORT */
+void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#if defined(RTC_TAMPER1_SUPPORT)
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#endif /* RTC_TAMPER1_SUPPORT */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#if defined(RTC_TAMPER3_SUPPORT)
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/* RTC Wake-up functions ******************************************************/
+/** @addtogroup RTCEx_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Extended Control functions ************************************************/
+/** @addtogroup RTCEx_Exported_Functions_Group3
+  * @{
+  */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/* Extended RTC features functions *******************************************/
+/** @addtogroup RTCEx_Exported_Functions_Group4
+  * @{
+  */
+void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/ 
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+  * @{
+  */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+  * @{
+  */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+  * @{
+  */ 
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
+                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+
+#define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))
+
+#define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 
+
+#define IS_RTC_TAMPER_ERASE_MODE(MODE)             (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
+                                                    ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
+
+#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE)        (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
+                                                    ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
+
+#define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
+                                          ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+                                                   ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
+#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+                                 ((SEL) == RTC_SHIFTADD1S_SET))
+
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c
new file mode 100755
index 0000000..160fd53
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c
@@ -0,0 +1,2229 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sai.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SAI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Serial Audio Interface (SAI) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                  ##### How to use this driver #####
+  ==============================================================================
+
+  [..]
+    The SAI HAL driver can be used as follows:
+
+    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
+    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
+        (##) Enable the SAI interface clock.
+        (##) SAI pins configuration:
+            (+++) Enable the clock for the SAI GPIOs.
+            (+++) Configure these SAI pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
+             and HAL_SAI_Receive_IT() APIs):
+            (+++) Configure the SAI interrupt priority.
+            (+++) Enable the NVIC SAI IRQ handle.
+
+        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
+             and HAL_SAI_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+                DMA Tx/Rx Stream.
+
+    (#) The initialization can be done by two ways
+        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
+        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
+
+  [..]
+    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
+        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
+        inside the transmit and receive process.
+  [..]
+    (@) Make sure that either:
+        (+@) PLLSAI1CLK output is configured or
+        (+@) PLLSAI2CLK output is configured or
+        (+@) PLLSAI3CLK output is configured or
+        (+@) External clock source is configured after setting correctly
+             the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE in the stm32l4xx_hal_conf.h file.
+
+  [..]
+    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
+        for the external slaves even if there is no data in the FIFO, However FS signal
+        generation is conditioned by the presence of data in the FIFO.
+
+  [..]
+    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
+        and FS signal for the external slaves.
+
+  [..]
+    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
+        (+@) First bit Offset <= (SLOT size - Data size)
+        (+@) Data size <= SLOT size
+        (+@) Number of SLOT x SLOT size = Frame length
+        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
+
+  [..]
+    Three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
+      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can 
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    =============================
+    [..]
+      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
+      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
+      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
+
+    *** SAI HAL driver additional function list ***
+    ===============================================
+    [..]
+      Below the list the others API available SAI HAL driver :
+
+      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
+      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
+      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
+      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
+      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
+      (+) HAL_SAI_Abort(): Abort the current transfer
+
+    *** SAI HAL driver macros list ***
+    ==================================
+    [..]
+      Below the list of most used macros in SAI HAL driver :
+
+      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
+      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
+      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
+      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
+      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
+          enabled or disabled
+      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SAI SAI
+  * @brief SAI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
+  * @{
+  */
+typedef enum {
+  SAI_MODE_DMA,
+  SAI_MODE_IT
+}SAI_ModeTypedef;
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Constants  SAI Private Constants
+  * @{
+  */
+#define SAI_FIFO_SIZE       8
+#define SAI_DEFAULT_TIMEOUT 4
+#define SAI_LONG_TIMEOUT    1000
+#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions  SAI Private Functions
+  * @{
+  */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
+
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
+  * @{
+  */
+
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]  This subsection provides a set of functions allowing to initialize and
+        de-initialize the SAIx peripheral:
+
+      (+) User must implement HAL_SAI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SAI_Init() to configure the selected device with
+          the selected configuration:
+        (++) Mode (Master/slave TX/RX)
+        (++) Protocol
+        (++) Data Size
+        (++) MCLK Output
+        (++) Audio frequency
+        (++) FIFO Threshold
+        (++) Frame Config
+        (++) Slot Config
+
+      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
+          of the selected SAI peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the structure FrameInit, SlotInit and the low part of
+  *         Init according to the specified parameters and call the function
+  *         HAL_SAI_Init to initialize the SAI block.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  protocol: one of the supported protocol @ref SAI_Protocol
+  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+  *                   the configuration information for SAI module.
+  * @param  nbslot: Number of slot.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+  assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+  
+  switch(protocol)
+  {
+  case SAI_I2S_STANDARD :
+  case SAI_I2S_MSBJUSTIFIED :
+  case SAI_I2S_LSBJUSTIFIED :
+    status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
+    break;
+  case SAI_PCM_LONG :
+  case SAI_PCM_SHORT :
+    status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
+    break;
+  default :
+    status = HAL_ERROR;
+    break;
+  }
+  
+  if(status == HAL_OK)
+  {
+    status = HAL_SAI_Init(hsai);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Initialize the SAI according to the specified parameters.
+  *         in the SAI_InitTypeDef structure and initialize the associated handle.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
+{
+  uint32_t tmpregisterGCR = 0;
+  uint32_t ckstr_bits  = 0;
+  uint32_t syncen_bits = 0;
+  
+  /* Check the SAI handle allocation */
+  if(hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* check the instance */
+  assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
+  
+  /* Check the SAI Block parameters */
+  assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+  assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
+  assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+  assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
+  assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
+  assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
+  assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
+  assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
+  assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
+  assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
+  assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
+  assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
+  assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
+  assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
+  
+  /* Check the SAI Block Frame parameters */
+  assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
+  assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
+  assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
+  assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
+  assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
+  
+  /* Check the SAI Block Slot parameters */
+  assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
+  assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
+  assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
+  assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
+  
+  if(hsai->State == HAL_SAI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsai->Lock = HAL_UNLOCKED;
+    
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_SAI_MspInit(hsai);
+  }
+  
+  hsai->State = HAL_SAI_STATE_BUSY;
+  
+  /* Disable the selected SAI peripheral */
+  SAI_Disable(hsai);
+  
+  /* SAI Block Synchro Configuration -----------------------------------------*/
+  /* This setting must be done with both audio block (A & B) disabled         */
+  switch(hsai->Init.SynchroExt)
+  {
+    case SAI_SYNCEXT_DISABLE :
+      tmpregisterGCR = 0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+      break;
+  }
+  
+  switch(hsai->Init.Synchro)
+  {
+    case SAI_ASYNCHRONOUS :
+      {
+        syncen_bits = 0;
+      }
+      break;
+    case SAI_SYNCHRONOUS :
+      {
+        syncen_bits = SAI_xCR1_SYNCEN_0;
+      }
+      break;
+    case SAI_SYNCHRONOUS_EXT_SAI1 :
+      {
+        syncen_bits = SAI_xCR1_SYNCEN_1;
+      }
+      break;
+    case SAI_SYNCHRONOUS_EXT_SAI2 :
+      {
+        syncen_bits = SAI_xCR1_SYNCEN_1;
+        tmpregisterGCR |= SAI_GCR_SYNCIN_0;
+      }
+      break;
+  }
+  
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+  
+  if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+  {
+    SAI1->GCR = tmpregisterGCR;
+  }
+  else 
+  {
+    SAI2->GCR = tmpregisterGCR;
+  }
+  
+#else
+  
+  SAI1->GCR = tmpregisterGCR;
+  
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+  
+  if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
+  {
+    uint32_t freq = 0;
+    uint32_t tmpval;
+    
+    /* In this case, the MCKDIV value is calculated to get AudioFrequency */
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+    
+    if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B ))
+    {
+      freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+    }
+    if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B ))
+    {
+      freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
+    }
+    
+#else
+    
+    freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+    
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+    
+    /* Configure Master Clock using the following formula :
+       MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
+       FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
+       MCKDIV[3:0] = SAI_CK_x / FS * 512 */
+    /* (freq x 10) to keep Significant digits */
+    tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256);
+    hsai->Init.Mckdiv = tmpval / 10;
+    
+    /* Round result to the nearest integer */
+    if((tmpval % 10) > 8)
+    {
+      hsai->Init.Mckdiv+= 1;
+    }
+  }
+  
+  /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
+  if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  { /* Transmit */
+    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR;
+  }
+  else
+  { /* Receive */
+    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0;
+  }
+  
+  /* SAI Block Configuration -------------------------------------------------*/
+  /* SAI CR1 Configuration */
+  hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
+                         SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
+                         SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
+                         SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
+  
+  hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol |           \
+                        hsai->Init.DataSize | hsai->Init.FirstBit  |           \
+                        ckstr_bits | syncen_bits |                             \
+                        hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
+                        hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20));
+  
+  /* SAI CR2 Configuration */
+  hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
+  hsai->Instance->CR2|=  (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
+  
+  /* SAI Frame Configuration -----------------------------------------*/
+  hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+                           SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
+  hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) |
+                          hsai->FrameInit.FSOffset |
+                          hsai->FrameInit.FSDefinition |
+                          hsai->FrameInit.FSPolarity   |
+                          ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
+  
+  /* SAI Block_x SLOT Configuration ------------------------------------------*/
+  /* This register has no meaning in AC 97 and SPDIF audio protocol */
+  hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |            \
+                             SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
+  
+  hsai->Instance->SLOTR|=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize
+                          | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) <<  8);
+  
+  /* Initialize the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+  
+  /* Initialize the SAI state */
+  hsai->State= HAL_SAI_STATE_READY;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the SAI peripheral.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
+{
+  /* Check the SAI handle allocation */
+  if(hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  hsai->State = HAL_SAI_STATE_BUSY;
+  
+  /* Disabled All interrupt and clear all the flag */
+  hsai->Instance->IMR = 0;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+  
+  /* Disable the SAI */
+  SAI_Disable(hsai);
+  
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+  
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_SAI_MspDeInit(hsai);
+  
+  /* Initialize the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+  
+  /* Initialize the SAI state */
+  hsai->State = HAL_SAI_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the SAI MSP.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the SAI MSP.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
+ *  @brief    Data transfers functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the SAI data
+    transfers.
+
+    (+) There are two modes of transfer:
+      (++) Blocking mode : The communication is performed in the polling mode.
+           The status of all data processing is returned by the same function
+           after finishing transfer.
+      (++) No-Blocking mode : The communication is performed using Interrupts
+           or DMA. These functions return the status of the transfer startup.
+           The end of the data processing will be indicated through the
+           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+
+    (+) Blocking mode functions are :
+      (++) HAL_SAI_Transmit()
+      (++) HAL_SAI_Receive()
+      (++) HAL_SAI_TransmitReceive()
+
+    (+) Non Blocking mode functions with Interrupt are :
+      (++) HAL_SAI_Transmit_IT()
+      (++) HAL_SAI_Receive_IT()
+      (++) HAL_SAI_TransmitReceive_IT()
+
+    (+) Non Blocking mode functions with DMA are :
+      (++) HAL_SAI_Transmit_DMA()
+      (++) HAL_SAI_Receive_DMA()
+      (++) HAL_SAI_TransmitReceive_DMA()
+
+    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+      (++) HAL_SAI_TxCpltCallback()
+      (++) HAL_SAI_RxCpltCallback()
+      (++) HAL_SAI_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+  
+  if((pData == NULL ) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->pBuffPtr = pData;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    
+    /* Check if the SAI is already enabled */
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* fill the fifo with data before to enabled the SAI */
+      SAI_FillFifo(hsai);
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    
+    while(hsai->XferCount > 0)
+    {
+      /* Write data if the FIFO is not full */
+      if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+      {
+        if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+        {
+          hsai->Instance->DR = (*hsai->pBuffPtr++);
+        }
+        else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+        {
+          hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
+          hsai->pBuffPtr+= 2;
+        }
+        else
+        {
+          hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+          hsai->pBuffPtr+= 4;
+        }
+        hsai->XferCount--;
+      }
+      else
+      {
+        /* Check for the Timeout */
+        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
+        {
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+          
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+          
+          /* Disable SAI peripheral */
+          SAI_Disable(hsai);
+          
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+          
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_READY;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+          
+          return HAL_ERROR;
+        }
+      }
+    }
+    
+    hsai->State = HAL_SAI_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+  
+  if((pData == NULL ) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    
+    /* Check if the SAI is already enabled */
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    
+    /* Receive data */
+    while(hsai->XferCount > 0)
+    {
+      if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
+      {
+        if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+        {
+          (*hsai->pBuffPtr++) = hsai->Instance->DR;
+        }
+        else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+        {
+          *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+          hsai->pBuffPtr+= 2;
+        }
+        else
+        {
+          *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+          hsai->pBuffPtr+= 4;
+        }
+        hsai->XferCount--;
+      }
+      else
+      {
+        /* Check for the Timeout */
+        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
+        {
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+          
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+          
+          /* Disable SAI peripheral */
+          SAI_Disable(hsai);
+          
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+          
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_READY;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+          
+          return HAL_ERROR;
+        }
+      }
+    }
+    
+    hsai->State = HAL_SAI_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  if((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+    
+    if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
+    }
+    else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
+    }
+    else
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
+    }
+    
+    /* Fill the fifo before starting the communication */
+    SAI_FillFifo(hsai);
+    
+    /* Enable FRQ and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    
+    /* Check if the SAI is already enabled */
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  if((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+    
+    if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
+    }
+    else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
+    }
+    else
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
+    }
+    
+    /* Enable TXE and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    
+    /* Check if the SAI is already enabled */
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the audio stream playing from the Media.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+  
+  /* Pause the audio file playing by disabling the SAI DMA requests */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the audio stream playing from the Media.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+  
+  /* Enable the SAI DMA requests */
+  hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+  
+  /* If the SAI peripheral is still not enabled, enable it */
+  if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+  {
+    /* Enable SAI peripheral */
+    __HAL_SAI_ENABLE(hsai);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the audio stream playing from the Media.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+  
+  /* Disable the SAI DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+  
+  /* Abort the SAI DMA Streams */
+  if(hsai->hdmatx != NULL)
+  {
+    if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+  
+  if(hsai->hdmarx != NULL)
+  {
+    if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+  
+  /* Disable SAI peripheral */
+  SAI_Disable(hsai);
+  
+  hsai->State = HAL_SAI_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Abort the current transfer and disable the SAI.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+  
+  /* Check SAI DMA is enabled or not */
+  if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+  {
+    /* Disable the SAI DMA request */
+    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+    
+    /* Abort the SAI DMA Streams */
+    if(hsai->hdmatx != NULL)
+    {
+      if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    
+    if(hsai->hdmarx != NULL)
+    {
+      if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  
+  /* Disabled All interrupt and clear all the flag */
+  hsai->Instance->IMR = 0;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+  
+  /* Disable SAI peripheral */
+  SAI_Disable(hsai);
+  
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+  
+  hsai->State = HAL_SAI_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  if((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+    
+    /* Set the SAI Tx DMA Half transfer complete callback */
+    hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
+    
+    /* Set the SAI TxDMA transfer complete callback */
+    hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
+    
+    /* Set the DMA error callback */
+    hsai->hdmatx->XferErrorCallback = SAI_DMAError;
+    
+    /* Set the DMA Tx abort callback */
+    hsai->hdmatx->XferAbortCallback = NULL;
+    
+    /* Enable the Tx DMA Stream */
+    if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
+    
+    /* Enable the interrupts for error handling */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+    
+    /* Enable SAI Tx DMA Request */
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+    
+    /* Wait untill FIFO is not empty */
+    while((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
+      {
+        /* Update error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsai);
+
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Check if the SAI is already enabled */
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+
+  if((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+    
+    /* Set the SAI Rx DMA Half transfer complete callback */
+    hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
+    
+    /* Set the SAI Rx DMA transfer complete callback */
+    hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
+    
+    /* Set the DMA error callback */
+    hsai->hdmarx->XferErrorCallback = SAI_DMAError;
+    
+    /* Set the DMA Rx abort callback */
+    hsai->hdmarx->XferAbortCallback = NULL;
+    
+    /* Enable the Rx DMA Stream */
+    if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
+    
+    /* Check if the SAI is already enabled */
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    
+    /* Enable the interrupts for error handling */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+    
+    /* Enable SAI Rx DMA Request */
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the Tx mute mode.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  val:  value sent during the mute @ref SAI_Block_Mute_Value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
+{
+  assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
+  
+  if(hsai->State != HAL_SAI_STATE_RESET)
+  {
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+    SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable the Tx mute mode.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
+{
+  if(hsai->State != HAL_SAI_STATE_RESET)
+  {
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Enable the Rx mute detection.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  callback: function called when the mute is detected.
+  * @param  counter: number a data before mute detection max 63.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
+{
+  assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
+  
+  if(hsai->State != HAL_SAI_STATE_RESET)
+  {
+    /* set the mute counter */
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
+    SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
+    hsai->mutecallback = callback;
+    /* enable the IT interrupt */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable the Rx mute detection.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
+{
+  if(hsai->State != HAL_SAI_STATE_RESET)
+  {
+    /* set the mutecallback to NULL */
+    hsai->mutecallback = (SAIcallback)NULL;
+    /* enable the IT interrupt */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Handle SAI interrupt request.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+{
+  if(hsai->State != HAL_SAI_STATE_RESET)
+  {
+    uint32_t itflags = hsai->Instance->SR;
+    uint32_t itsources = hsai->Instance->IMR;
+    uint32_t cr1config = hsai->Instance->CR1;
+    uint32_t tmperror;
+    
+    /* SAI Fifo request interrupt occured ------------------------------------*/
+    if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
+    {
+      hsai->InterruptServiceRoutine(hsai);
+    }
+    /* SAI Overrun error interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+    {
+      /* Clear the SAI Overrun flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+      /* Get the SAI error code */
+      tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+      /* Change the SAI error code */
+      hsai->ErrorCode |= tmperror;
+      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+      HAL_SAI_ErrorCallback(hsai);
+    }
+    /* SAI mutedet interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+    {
+      /* Clear the SAI mutedet flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+      /* call the call back function */
+      if(hsai->mutecallback != (SAIcallback)NULL)
+      {
+        /* inform the user that an RX mute event has been detected */
+        hsai->mutecallback();
+      }
+    }
+    /* SAI AFSDET interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
+      
+      /* Check SAI DMA is enabled or not */
+      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if(hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if(hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* Abort SAI */ 
+        HAL_SAI_Abort(hsai);
+        
+        /* Set error callback */
+        HAL_SAI_ErrorCallback(hsai);          
+      }
+    }
+    /* SAI LFSDET interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
+      
+      /* Check SAI DMA is enabled or not */
+      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if(hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+          
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if(hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+          
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* Abort SAI */ 
+        HAL_SAI_Abort(hsai);
+        
+        /* Set error callback */
+        HAL_SAI_ErrorCallback(hsai);
+      }
+    }
+    /* SAI WCKCFG interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
+      
+      /* Check SAI DMA is enabled or not */
+      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if(hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+          
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if(hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+          
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* If WCKCFG occurs, SAI audio block is automatically disabled */
+        /* Disable all interrupts and clear all flags */
+        hsai->Instance->IMR = 0U;
+        hsai->Instance->CLRFR = 0xFFFFFFFFU;
+        /* Set the SAI state to ready to be able to start again the process */
+        hsai->State = HAL_SAI_STATE_READY;
+        
+        /* Initialize XferCount */
+        hsai->XferCount = 0U;
+        
+        /* SAI error Callback */
+        HAL_SAI_ErrorCallback(hsai);        
+      }
+    }
+    /* SAI CNRDY interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+    {
+      /* Clear the SAI CNRDY flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
+      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+      HAL_SAI_ErrorCallback(hsai);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx Transfer Half completed callback.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer half completed callback.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief SAI error callback.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
+ *  @brief    Peripheral State functions
+ *
+@verbatim
+  ===============================================================================
+                ##### Peripheral State and Errors functions #####
+  ===============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SAI handle state.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL state
+  */
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
+{
+  return hsai->State;
+}
+
+/**
+* @brief  Return the SAI error code.
+* @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for the specified SAI Block.
+* @retval SAI Error Code
+*/
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
+{
+  return hsai->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SAI_Private_Functions
+ *  @brief      Private functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SAI I2S protocol according to the specified parameters
+  *         in the SAI_InitTypeDef and create the associated handle.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  protocol: one of the supported protocol.
+  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+  *                the configuration information for SAI module.
+  * @param  nbslot: number of slot minimum value is 2 and max is 16.
+  *                    the value must be a multiple of 2.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
+  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
+  /* Compute ClockStrobing according AudioMode */
+  if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  { /* Transmit */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
+  }
+  else
+  { /* Receive */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
+  }
+  hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
+  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
+  hsai->SlotInit.FirstBitOffset  = 0;
+  hsai->SlotInit.SlotNumber      = nbslot;
+  
+  /* in IS2 the number of slot must be even */
+  if((nbslot & 0x1) != 0 )
+  {
+    return HAL_ERROR;
+  }
+  
+  switch(protocol)
+  {
+  case SAI_I2S_STANDARD :
+    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+    hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
+    break;
+  case SAI_I2S_MSBJUSTIFIED :
+  case SAI_I2S_LSBJUSTIFIED :
+    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+    hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
+    break;
+  default :
+    return HAL_ERROR;
+  }
+  
+  /* Frame definition */
+  switch(datasize)
+  {
+  case SAI_PROTOCOL_DATASIZE_16BIT:
+    hsai->Init.DataSize = SAI_DATASIZE_16;
+    hsai->FrameInit.FrameLength = 32*(nbslot/2);
+    hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+    break;
+  case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+    hsai->Init.DataSize = SAI_DATASIZE_16;
+    hsai->FrameInit.FrameLength = 64*(nbslot/2);
+    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;
+  case SAI_PROTOCOL_DATASIZE_24BIT:
+    hsai->Init.DataSize = SAI_DATASIZE_24;
+    hsai->FrameInit.FrameLength = 64*(nbslot/2);
+    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;
+  case SAI_PROTOCOL_DATASIZE_32BIT:
+    hsai->Init.DataSize = SAI_DATASIZE_32;
+    hsai->FrameInit.FrameLength = 64*(nbslot/2);
+    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;
+  default :
+    return HAL_ERROR;
+  }
+  if(protocol == SAI_I2S_LSBJUSTIFIED)
+  {
+    if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+    {
+      hsai->SlotInit.FirstBitOffset = 16;
+    }
+    if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+    {
+      hsai->SlotInit.FirstBitOffset = 8;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SAI PCM protocol according to the specified parameters
+  *         in the SAI_InitTypeDef and create the associated handle.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  protocol: one of the supported protocol
+  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+  * @param  nbslot: number of slot minimum value is 1 and the max is 16.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
+  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
+  /* Compute ClockStrobing according AudioMode */
+  if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  { /* Transmit */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
+  }
+  else
+  { /* Receive */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
+  }
+  hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
+  hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
+  hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
+  hsai->SlotInit.FirstBitOffset  = 0;
+  hsai->SlotInit.SlotNumber      = nbslot;
+  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
+  
+  switch(protocol)
+  {
+  case SAI_PCM_SHORT :
+    hsai->FrameInit.ActiveFrameLength = 1;
+    break;
+  case SAI_PCM_LONG :
+    hsai->FrameInit.ActiveFrameLength = 13;
+    break;
+  default :
+    return HAL_ERROR;
+  }
+  
+  switch(datasize)
+  {
+  case SAI_PROTOCOL_DATASIZE_16BIT:
+    hsai->Init.DataSize = SAI_DATASIZE_16;
+    hsai->FrameInit.FrameLength = 16 * nbslot;
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+    break;
+  case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+    hsai->Init.DataSize = SAI_DATASIZE_16;
+    hsai->FrameInit.FrameLength = 32 * nbslot;
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;
+  case SAI_PROTOCOL_DATASIZE_24BIT :
+    hsai->Init.DataSize = SAI_DATASIZE_24;
+    hsai->FrameInit.FrameLength = 32 * nbslot;
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;
+  case SAI_PROTOCOL_DATASIZE_32BIT:
+    hsai->Init.DataSize = SAI_DATASIZE_32;
+    hsai->FrameInit.FrameLength = 32 * nbslot;
+    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+    break;
+  default :
+    return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Fill the fifo.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
+{
+  /* fill the fifo with data before to enabled the SAI */
+  while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))
+  {
+    if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->Instance->DR = (*hsai->pBuffPtr++);
+    }
+    else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+      hsai->pBuffPtr+= 2;
+    }
+    else
+    {
+      hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+      hsai->pBuffPtr+= 4;
+    }
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Return the interrupt flag to set according the SAI setup.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  mode: SAI_MODE_DMA or SAI_MODE_IT
+  * @retval the list of the IT flag to enable
+ */
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
+{
+  uint32_t tmpIT = SAI_IT_OVRUDR;
+  
+  if(mode == SAI_MODE_IT)
+  {
+    tmpIT|= SAI_IT_FREQ;
+  }
+  
+  if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
+    ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
+  {
+    tmpIT|= SAI_IT_CNRDY;
+  }
+  
+  if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
+  }
+  else
+  {
+    /* hsai has been configured in master mode */
+    tmpIT|= SAI_IT_WCKCFG;
+  }
+  return tmpIT;
+}
+
+/**
+  * @brief  Disable the SAI and wait for the disabling.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
+{
+  uint32_t tickstart = HAL_GetTick();
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  __HAL_SAI_DISABLE(hsai);
+  while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart) > SAI_DEFAULT_TIMEOUT)
+    {
+      /* Update error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+  if(hsai->XferCount == 0)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+    HAL_SAI_TxCpltCallback(hsai);
+  }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = (*hsai->pBuffPtr++);
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+  if(hsai->XferCount == 0)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+    HAL_SAI_TxCpltCallback(hsai);
+  }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
+    hsai->pBuffPtr+=2;
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+  if(hsai->XferCount == 0)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+    HAL_SAI_TxCpltCallback(hsai);
+  }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
+    hsai->pBuffPtr+=4;
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+  /* Receive data */
+  (*hsai->pBuffPtr++) = hsai->Instance->DR;
+  hsai->XferCount--;
+  
+  /* Check end of the transfer */
+  if(hsai->XferCount == 0)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+    
+    hsai->State = HAL_SAI_STATE_READY;
+    HAL_SAI_RxCpltCallback(hsai);
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+  /* Receive data */
+  *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
+  hsai->pBuffPtr+=2;
+  hsai->XferCount--;
+  
+  /* Check end of the transfer */
+  if(hsai->XferCount == 0)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+    
+    hsai->State = HAL_SAI_STATE_READY;
+    HAL_SAI_RxCpltCallback(hsai);
+  }
+}
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+  /* Receive data */
+  *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
+  hsai->pBuffPtr+=4;
+  hsai->XferCount--;
+  
+  /* Check end of the transfer */
+  if(hsai->XferCount == 0)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+    
+    hsai->State = HAL_SAI_STATE_READY;
+    HAL_SAI_RxCpltCallback(hsai);
+  }
+}
+
+/**
+  * @brief  DMA SAI transmit process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+  {
+    hsai->XferCount = 0;
+    
+    /* Disable SAI Tx DMA Request */
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+    
+    /* Stop the interrupts error handling */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+    
+    hsai->State= HAL_SAI_STATE_READY;
+  }
+  HAL_SAI_TxCpltCallback(hsai);
+}
+
+/**
+  * @brief  DMA SAI transmit process half complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  HAL_SAI_TxHalfCpltCallback(hsai);
+}
+
+/**
+  * @brief  DMA SAI receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+  {
+    /* Disable Rx DMA Request */
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+    hsai->XferCount = 0;
+    
+    /* Stop the interrupts error handling */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+    
+    hsai->State = HAL_SAI_STATE_READY;
+  }
+  HAL_SAI_RxCpltCallback(hsai);
+}
+
+/**
+  * @brief  DMA SAI receive process half complete callback
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  HAL_SAI_RxHalfCpltCallback(hsai);
+}
+/**
+  * @brief  DMA SAI communication error callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Set SAI error code */
+  hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+  
+  /* Disable the SAI DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Disable SAI peripheral */
+  SAI_Disable(hsai);
+    
+  /* Set the SAI state ready to be able to start again the process */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Initialize XferCount */
+  hsai->XferCount = 0U;
+
+  /* SAI error Callback */ 
+  HAL_SAI_ErrorCallback(hsai);
+}
+
+/**
+  * @brief  DMA SAI Abort callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Disable DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Disable all interrupts and clear all flags */
+  hsai->Instance->IMR = 0U;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+  
+  if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
+  {
+    /* Disable SAI peripheral */
+    SAI_Disable(hsai);
+
+    /* Flush the fifo */
+    SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+  }
+  /* Set the SAI state to ready to be able to start again the process */
+  hsai->State = HAL_SAI_STATE_READY;
+  
+  /* Initialize XferCount */
+  hsai->XferCount = 0U;
+
+  /* SAI error Callback */
+  HAL_SAI_ErrorCallback(hsai);
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h
new file mode 100755
index 0000000..383d35f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h
@@ -0,0 +1,849 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sai.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SAI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SAI_H
+#define __STM32L4xx_HAL_SAI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SAI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Types SAI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
+  HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
+  HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
+  HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
+  HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
+}HAL_SAI_StateTypeDef;
+
+/**
+  * @brief  SAI Callback prototype
+  */
+typedef void (*SAIcallback)(void);
+
+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
+  * @brief  SAI Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
+                                     This parameter can be a value of @ref SAI_Block_Mode */
+
+  uint32_t Synchro;             /*!< Specifies SAI Block synchronization
+                                     This parameter can be a value of @ref SAI_Block_Synchronization */
+
+  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
+                                     for BlockA and BlockB
+                                     This parameter can be a value of @ref SAI_Block_SyncExt
+                                     @note: If both audio blocks of same SAI are used, this parameter has
+                                            to be set to the same value for each audio block */
+
+  uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
+                                     This parameter can be a value of @ref SAI_Block_Output_Drive
+                                     @note this value has to be set before enabling the audio block
+                                     but after the audio block configuration. */
+
+  uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
+                                     This parameter can be a value of @ref SAI_Block_NoDivider
+                                     @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+                                              should be aligned to a number equal to a power of 2, from 8 to 256.
+                                              If bit NODIV in the SAI_xCR1 register is set, the frame length can
+                                              take any of the values without constraint since the input clock of
+                                              the audio block should be equal to the bit clock.
+                                              There is no MCLK_x clock which can be output. */
+
+  uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
+                                     This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
+                                     This parameter can be a value of @ref SAI_Audio_Frequency */
+
+  uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
+                                     AudioFrequency the user choice
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+
+  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
+                                     This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
+
+  uint32_t CompandingMode;      /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_Block_Companding_Mode */
+
+  uint32_t TriState;            /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_TRIState_Management */
+
+  /* This part of the structure is automatically filled if your are using the high level initialisation
+     function HAL_SAI_InitProtocol */
+
+  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
+                                 This parameter can be a value of @ref SAI_Block_Protocol */
+
+  uint32_t DataSize;        /*!< Specifies the SAI Block data size.
+                                 This parameter can be a value of @ref SAI_Block_Data_Size */
+
+  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
+                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing */
+}SAI_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
+  * @brief  SAI Frame Init structure definition
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+                                    This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+                                    @note: If master clock MCLK_x pin is declared as an output, the frame length
+                                           should be aligned to a number equal to power of 2 in order to keep
+                                           in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
+                                    This Parameter specifies the length in number of bit clock (SCK + 1)
+                                    of the active level of FS signal in audio frame.
+                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
+                                    This parameter can be a value of @ref SAI_Block_FS_Definition */
+
+  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
+                                    This parameter can be a value of @ref SAI_Block_FS_Polarity */
+
+  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
+                                    This parameter can be a value of @ref SAI_Block_FS_Offset */
+
+}SAI_FrameInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
+  * @brief   SAI Block Slot Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+  uint32_t SlotSize;        /*!< Specifies the Slot Size.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Size */
+
+  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Active */
+}SAI_SlotInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
+  * @brief  SAI handle Structure definition
+  * @{
+  */
+typedef struct __SAI_HandleTypeDef
+{
+  SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
+
+  SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
+
+  SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
+
+  SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
+
+  uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
+
+  uint16_t                  XferSize;     /*!< SAI transfer size */
+
+  uint16_t                  XferCount;    /*!< SAI transfer counter */
+
+  DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
+
+  DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
+
+  SAIcallback               mutecallback; /*!< SAI mute callback */
+
+  void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
+
+  HAL_LockTypeDef           Lock;         /*!< SAI locking object */
+
+  __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
+
+  __IO uint32_t             ErrorCode;    /*!< SAI Error code */
+}SAI_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Constants SAI Exported Constants
+  * @{
+  */
+
+/** @defgroup SAI_Error_Code SAI Error Code
+  * @{
+  */
+#define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error */
+#define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error */
+#define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
+  * @{
+  */
+#define SAI_SYNCEXT_DISABLE          0
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol SAI Supported protocol
+  * @{
+  */
+#define SAI_I2S_STANDARD      0
+#define SAI_I2S_MSBJUSTIFIED  1
+#define SAI_I2S_LSBJUSTIFIED  2
+#define SAI_PCM_LONG          3
+#define SAI_PCM_SHORT         4
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+  * @{
+  */
+#define SAI_PROTOCOL_DATASIZE_16BIT         0
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
+#define SAI_PROTOCOL_DATASIZE_24BIT         2
+#define SAI_PROTOCOL_DATASIZE_32BIT         3
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
+  * @{
+  */
+#define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)
+#define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)
+#define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)
+#define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)
+#define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)
+#define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)
+#define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)
+#define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)
+#define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)
+#define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mode SAI Block Mode
+  * @{
+  */
+#define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)
+#define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
+#define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
+#define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Protocol SAI Block Protocol
+  * @{
+  */
+#define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)
+#define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
+#define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size
+  * @{
+  */
+#define SAI_DATASIZE_8     ((uint32_t)SAI_xCR1_DS_1)
+#define SAI_DATASIZE_10    ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_16    ((uint32_t)SAI_xCR1_DS_2)
+#define SAI_DATASIZE_20    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_24    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
+#define SAI_DATASIZE_32    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
+  * @{
+  */
+#define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)
+#define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
+  * @{
+  */
+#define SAI_CLOCKSTROBING_FALLINGEDGE     0
+#define SAI_CLOCKSTROBING_RISINGEDGE      1
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
+  * @{
+  */
+#define SAI_ASYNCHRONOUS                  0 /*!< Asynchronous */
+#define SAI_SYNCHRONOUS                   1 /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          2 /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2          3 /*!< Synchronous with other SAI, SAI2 */
+/**
+  * @}
+  */ 
+
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)
+#define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
+  * @{
+  */
+#define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)
+#define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)
+/**
+  * @}
+  */
+
+
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
+  * @{
+  */
+#define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)
+#define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
+  * @{
+  */
+#define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)
+#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
+  * @{
+  */
+#define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)
+#define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
+/**
+  * @}
+  */
+
+
+  /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
+  * @{
+  */
+#define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)
+#define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+#define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
+  * @{
+  */
+#define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)
+#define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)
+#define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)
+#define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)
+#define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)
+#define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)
+#define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)
+#define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)
+#define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)
+#define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)
+#define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)
+#define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)
+#define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)
+#define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)
+#define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)
+#define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)
+#define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)
+#define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
+  * @{
+  */
+#define SAI_STEREOMODE               ((uint32_t)0x00000000U)
+#define SAI_MONOMODE                 ((uint32_t)SAI_xCR1_MONO)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_TRIState_Management SAI TRIState Management
+  * @{
+  */
+#define SAI_OUTPUT_NOTRELEASED    ((uint32_t)0x00000000U)
+#define SAI_OUTPUT_RELEASED       ((uint32_t)SAI_xCR2_TRIS)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
+  * @{
+  */
+#define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)
+#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))
+#define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
+  * @{
+  */
+#define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)
+#define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))
+#define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
+#define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
+#define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
+  * @{
+  */
+#define SAI_ZERO_VALUE                     ((uint32_t)0x00000000U)
+#define SAI_LAST_SENT_VALUE                ((uint32_t)SAI_xCR2_MUTEVAL)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
+  * @{
+  */
+#define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
+#define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
+#define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
+#define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
+#define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
+#define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
+#define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
+  * @{
+  */
+#define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
+#define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
+#define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
+#define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
+#define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
+#define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
+#define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
+  * @{
+  */
+#define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)
+#define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)
+#define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)
+#define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)
+#define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Macros SAI Exported Macros
+ *  @brief macros to handle interrupts and specific configurations
+ * @{
+ */
+
+/** @brief Reset SAI handle state.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @retval None
+  */
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+
+/** @brief  Enable or disable the specified SAI interrupts.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval None
+  */
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SAI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SAI flag is set or not.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
+  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+  *            @arg SAI_FLAG_FREQ: FIFO request flag.
+  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
+  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified SAI pending flag.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
+  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+  *            @arg SAI_FLAG_FREQ: Clear FIFO request
+  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
+  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+  *
+  * @retval None
+  */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
+
+ /**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SAI_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+
+/** @addtogroup SAI_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+
+/** @addtogroup SAI_Exported_Functions_Group2
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/** @addtogroup SAI_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SAI_Private_Macros
+  * @{
+  */
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
+                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
+                                               ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
+
+#define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
+                                  ((MODE) == SAI_MODEMASTER_RX) || \
+                                  ((MODE) == SAI_MODESLAVE_TX)  || \
+                                  ((MODE) == SAI_MODESLAVE_RX))
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) 
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
+                                         ((DATASIZE) == SAI_DATASIZE_10) || \
+                                         ((DATASIZE) == SAI_DATASIZE_16) || \
+                                         ((DATASIZE) == SAI_DATASIZE_20) || \
+                                         ((DATASIZE) == SAI_DATASIZE_24) || \
+                                         ((DATASIZE) == SAI_DATASIZE_32))
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+                                     ((BIT) == SAI_FIRSTBIT_LSB))
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
+                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
+                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
+
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
+                                           ((VALUE) == SAI_LAST_SENT_VALUE)) 
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
+                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))  
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+                                                 ((STATE) == SAI_OUTPUT_RELEASED))
+
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+                                       ((MODE) == SAI_STEREOMODE))
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
+
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
+                                      ((SIZE) == SAI_SLOTSIZE_32B))
+
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SAI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c
new file mode 100755
index 0000000..5ea7135
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c
@@ -0,0 +1,2931 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sd.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SD card HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + SD card Control functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to 
+    this memory. The needed STM32 hardware resources (SDMMC1 and GPIO) are performed by 
+    the user in HAL_SD_MspInit() function (MSP layer).                             
+    Basically, the MSP layer configuration should be the same as we provide in the 
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDMMC memories which uses the HAL 
+    SDMMC driver functions to interface with SD and uSD cards devices. 
+    It is used as follows:
+ 
+    (#)Initialize the SDMMC1 low level resources by implementing the HAL_SD_MspInit() API:
+        (##) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_SDMMC1 for
+        PeriphClockSelection and select SDMMC1 clock source (MSI, main PLL or PLLSAI1)
+        (##) Enable the SDMMC1 interface clock using __HAL_RCC_SDMMC1_CLK_ENABLE(); 
+        (##) SDMMC pins configuration for SD card
+            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();   
+            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) Perform DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+             and HAL_SD_WriteBlocks_DMA() APIs).
+            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); 
+            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. 
+        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+            (+++) Configure the SDMMC and DMA interrupt priorities using functions
+                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
+            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() 
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+             and HAL_SD_WriteBlocks_IT() APIs).
+            (+++) Configure the SDMMC interrupt priorities using function
+                  HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() 
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  
+
+         
+  *** SD Card Initialization and configuration ***
+  ================================================    
+  [..]
+    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes 
+    SDMMC IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). 
+    This function provide the following operations:
+  
+    (#) Initialize the SDMMC peripheral interface with defaullt configuration.
+        The initialization process is done at 400KHz. You can change or adapt 
+        this frequency by adjusting the "ClockDiv" field. 
+        The SD Card frequency (SDMMC_CK) is computed as follows:
+
+           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
+
+        In initialization mode and according to the SD Card standard, 
+          make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+  
+        This phase of initialization is done through SDMMC_Init() and 
+        SDMMC_PowerState_ON() SDMMC low level APIs.
+        
+    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+        This phase allows the card initialization and identification 
+        and check the SD Card type (Standard Capacity or High Capacity)
+        The initialization flow is compatible with SD standard.
+
+        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case 
+        of plug-off plug-in.
+  
+    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer 
+        frequency is set to 24MHz. You can change or adapt this frequency by adjusting 
+        the "ClockDiv" field.
+        In transfer mode and according to the SD Card standard, make sure that the 
+        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+        To be able to use a frequency higher than 24MHz, you should use the SDMMC 
+        peripheral in bypass mode. Refer to the corresponding reference manual 
+        for more details.
+  
+    (#) Select the corresponding SD Card according to the address read with the step 2.
+    
+    (#) Configure the SD Card in wide bus mode: 4-bits data.
+  
+  *** SD Card Read operation ***
+  ==============================
+  [..] 
+    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). 
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Rx interrupt event.
+
+    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Rx interrupt event.
+  
+  *** SD Card Write operation ***
+  =============================== 
+  [..] 
+    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). 
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Tx interrupt event.  
+
+    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Tx interrupt event.
+  
+  *** SD card status ***
+  ====================== 
+  [..]
+    (+) The SD Status contains status bits that are related to the SD Memory 
+        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+  *** SD card information ***
+  =========================== 
+  [..]
+    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+        It returns useful information about the SD card such as block size, card type,
+        block number ...
+
+  *** SD card CSD register ***
+  ============================ 
+    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD card CID register ***
+  ============================ 
+    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SD HAL driver.
+       
+    (+) __HAL_SD_ENABLE : Enable the SD device
+    (+) __HAL_SD_DISABLE : Disable the SD device
+    (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer
+    (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer
+    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+      
+    (@) You can refer to the SD HAL driver header file for more useful macros 
+      
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(SDMMC1)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SD 
+  * @{
+  */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SD_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+static uint32_t          SD_InitCard       (SD_HandleTypeDef *hsd);
+static uint32_t          SD_PowerON        (SD_HandleTypeDef *hsd);                      
+static uint32_t          SD_SendSDStatus   (SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t          SD_SendStatus     (SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t          SD_WideBus_Enable (SD_HandleTypeDef *hsd);
+static uint32_t          SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t          SD_FindSCR        (SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static HAL_StatusTypeDef SD_PowerOFF       (SD_HandleTypeDef *hsd);
+static HAL_StatusTypeDef SD_Write_IT       (SD_HandleTypeDef *hsd);
+static HAL_StatusTypeDef SD_Read_IT        (SD_HandleTypeDef *hsd);
+static void              SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void              SD_DMAReceiveCplt (DMA_HandleTypeDef *hdma);
+static void              SD_DMAError       (DMA_HandleTypeDef *hdma);
+static void              SD_DMATxAbort     (DMA_HandleTypeDef *hdma);
+static void              SD_DMARxAbort     (DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SD_Exported_Functions_Group1
+ *  @brief   Initialization and de-initialization functions 
+ *
+@verbatim    
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize the SD
+    card device to be ready for use.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SD according to the specified parameters in the 
+            SD_HandleTypeDef and create the associated handle.
+  * @param  hsd: Pointer to the SD handle  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{ 
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+  assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+
+  if(hsd->State == HAL_SD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsd->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SD_MspInit(hsd);
+  }
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  /* Initialize the Card parameters */
+  if (HAL_SD_InitCard(hsd) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Initialize the error code */
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+  
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+  
+  /* Initialize the SD state */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SD Card.
+  * @param  hsd: Pointer to SD handle
+  * @note   This function initializes the SD card. It could be used when a card 
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  HAL_StatusTypeDef status = HAL_OK;
+  SD_InitTypeDef Init;
+  
+  /* Default SDMMC peripheral configuration for SD card initialization */
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+  Init.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+  Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
+
+  /* Initialize SDMMC peripheral interface with default configuration */
+  status = SDMMC_Init(hsd->Instance, Init);
+  if(status != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable SDMMC Clock */
+  __HAL_SD_DISABLE(hsd); 
+  
+  /* Set Power State to ON */
+  status = SDMMC_PowerState_ON(hsd->Instance);
+  if(status != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Enable SDMMC Clock */
+  __HAL_SD_ENABLE(hsd);
+
+  /* Required power up waiting time before starting the SD initialization sequence */
+  HAL_Delay(2U);
+
+  /* Identify card operating voltage */
+  errorstate = SD_PowerON(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Card initialization */
+  errorstate = SD_InitCard(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the SD card.
+  * @param  hsd: Pointer to SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+
+  hsd->State = HAL_SD_STATE_BUSY;
+  
+  /* Set SD power state to off */ 
+  SD_PowerOFF(hsd);
+  
+  /* De-Initialize the MSP layer */
+  HAL_SD_MspDeInit(hsd);
+  
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+  hsd->State = HAL_SD_STATE_RESET;
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group2
+ *  @brief   Data transfer functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### IO operation functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to manage the data 
+    transfer from/to SD card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
+  *         is managed by polling mode.  
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read 
+  * @param  NumberOfBlocks: Number of SD blocks to read   
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count = 0, *tempbuff = (uint32_t *)pData;
+  
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+ 
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    
+    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_BUSY;
+    
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0;
+    
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      BlockAdd *= 512;
+    }
+      
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    SDMMC_ConfigData(hsd->Instance, &config);
+    
+    /* Read block(s) in polling mode */
+    if(NumberOfBlocks > 1)
+    {
+      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+      
+      /* Read Multi Block command */ 
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+      
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+      
+    /* Poll on SDMMC flags */
+    while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for(count = 0U; count < 8U; count++)
+        {
+          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
+        }
+        tempbuff += 8U;
+      }
+      
+      if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Send stop transmission command in case of multiblock read */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {    
+      if(hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          return HAL_ERROR;
+        }
+      }
+    }
+    
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Empty FIFO if there is still any data */
+    while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
+    {
+      *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
+      tempbuff++;
+      
+      if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);        
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    
+    hsd->State = HAL_SD_STATE_READY;
+    
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in a card. The Data
+  *         transfer is managed by polling mode.  
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written  
+  * @param  NumberOfBlocks: Number of SD blocks to write 
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count = 0;
+  uint32_t *tempbuff = (uint32_t *)pData;
+  
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    
+    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_BUSY;
+    
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0;
+     
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      BlockAdd *= 512;
+    }
+    
+    /* Set Block Size for Card */ 
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+      
+      /* Write Multi Block command */ 
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+      
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Configure the SD DPSM (Data Path State Machine) */ 
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    SDMMC_ConfigData(hsd->Instance, &config);
+    
+    /* Write block(s) in polling mode */
+    while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
+      {
+        /* Write data to SDMMC Tx FIFO */
+        for(count = 0U; count < 8U; count++)
+        {
+          SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
+        }
+        tempbuff += 8U;
+      }
+      
+      if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Send stop transmission command in case of multiblock write */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    { 
+      if(hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          return HAL_ERROR;
+        }
+      }
+    }
+    
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    
+    hsd->State = HAL_SD_STATE_READY;
+    
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
+  *         is managed in interrupt mode. 
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Rx 
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle                 
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read 
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+  
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    
+    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_BUSY;
+    
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+    
+    hsd->pRxBuffPtr = (uint32_t *)pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+    
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
+    
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      BlockAdd *= 512U;
+    }
+    
+    /* Configure the SD DPSM (Data Path State Machine) */ 
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    SDMMC_ConfigData(hsd->Instance, &config);
+    
+    /* Set Block Size for Card */ 
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Read Blocks in IT mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+      
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+      
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer 
+  *         is managed in interrupt mode. 
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Tx 
+  *         interrupt event. 
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written    
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+  
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    
+    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_BUSY;
+    
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+    
+    hsd->pTxBuffPtr = (uint32_t *)pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+    
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); 
+    
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      BlockAdd *= 512U;
+    }
+    
+    /* Set Block Size for Card */ 
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+      
+      /* Write Multi Block command */ 
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+      
+      /* Write Single Block command */ 
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Configure the SD DPSM (Data Path State Machine) */ 
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    SDMMC_ConfigData(hsd->Instance, &config);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
+  *         is managed by DMA mode. 
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Rx 
+  *         interrupt event.
+  * @param  hsd: Pointer SD handle                 
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read  
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+  
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    
+    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_BUSY;
+    
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+    
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+    
+    /* Set the DMA transfer complete callback */
+    hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
+    
+    /* Set the DMA error callback */
+    hsd->hdmarx->XferErrorCallback = SD_DMAError;
+    
+    /* Set the DMA Abort callback */
+    hsd->hdmarx->XferAbortCallback = NULL;
+    
+    /* Enable the DMA Channel */
+    HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+    
+    /* Enable SD DMA transfer */
+    __HAL_SD_DMA_ENABLE(hsd);
+    
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      BlockAdd *= 512U;
+    }
+    
+    /* Configure the SD DPSM (Data Path State Machine) */ 
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    SDMMC_ConfigData(hsd->Instance, &config);
+
+    /* Set Block Size for Card */ 
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Read Blocks in DMA mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+      
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+      
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer 
+  *         is managed by DMA mode. 
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Tx 
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written  
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+  
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    
+    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_BUSY;
+    
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+    
+    /* Enable SD Error interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));    
+    
+    /* Set the DMA transfer complete callback */
+    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
+    
+    /* Set the DMA error callback */
+    hsd->hdmatx->XferErrorCallback = SD_DMAError;
+    
+    /* Set the DMA Abort callback */
+    hsd->hdmatx->XferAbortCallback = NULL;
+    
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      BlockAdd *= 512U;
+    }
+    
+    /* Set Block Size for Card */ 
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+      
+      /* Write Multi Block command */ 
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+      
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Enable SDMMC DMA transfer */
+    __HAL_SD_DMA_ENABLE(hsd);
+    
+    /* Enable the DMA Channel */
+    HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+    
+    /* Configure the SD DPSM (Data Path State Machine) */ 
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    SDMMC_ConfigData(hsd->Instance, &config);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle 
+  * @param  BlockStartAdd: Start Block address
+  * @param  BlockEndAdd: End Block address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    
+    if(BlockEndAdd < BlockStartAdd)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      return HAL_ERROR;
+    }
+    
+    if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_BUSY;
+    
+    /* Check if the card command class supports erase command */
+    if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  
+      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    /* Get start and end block for high capacity cards */
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      BlockStartAdd *= 512U;
+      BlockEndAdd   *= 512U;
+    }
+    
+    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+    if(hsd->SdCard.CardType != CARD_SECURED)
+    {
+      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+      
+      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Send CMD38 ERASE */
+    errorstate = SDMMC_CmdErase(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    
+    hsd->State = HAL_SD_STATE_READY;
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{  
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  /* Check for SDMMC interrupt flags */
+  if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); 
+    
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                             SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+    
+    if((hsd->Context & SD_CONTEXT_IT) != RESET)
+    {
+      if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+          HAL_SD_ErrorCallback(hsd);
+        }
+      }
+      
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      
+      hsd->State = HAL_SD_STATE_READY;
+      if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
+      {
+        HAL_SD_RxCpltCallback(hsd);
+      }
+      else
+      {
+        HAL_SD_TxCpltCallback(hsd);
+      }
+    }
+    else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+    {
+      if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+          HAL_SD_ErrorCallback(hsd);
+        }
+      }
+      if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+      {
+        /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+        in the SD DCTRL register */
+        hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+        
+        hsd->State = HAL_SD_STATE_READY;
+        
+        HAL_SD_TxCpltCallback(hsd);
+      }
+    }
+  }
+  
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE);
+    
+    SD_Write_IT(hsd);
+  }
+  
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF);
+    
+    SD_Read_IT(hsd);
+  }
+  
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
+  {
+    /* Set Error code */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; 
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; 
+    }
+  
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    
+    /* Disable all interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                             SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+    
+    if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+    {
+      /* Abort the SD DMA Streams */
+      if(hsd->hdmatx != NULL)
+      {
+        /* Set the DMA Tx abort callback */
+        hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+        {
+          SD_DMATxAbort(hsd->hdmatx);
+        }
+      }
+      else if(hsd->hdmarx != NULL)
+      {
+        /* Set the DMA Rx abort callback */
+        hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+        {
+          SD_DMARxAbort(hsd->hdmarx);
+        }
+      }
+      else
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_NONE;
+        hsd->State = HAL_SD_STATE_READY;
+        HAL_SD_AbortCallback(hsd);
+      }
+    }
+    else if((hsd->Context & SD_CONTEXT_IT) != RESET)
+    {
+      /* Set the SD state to ready to be able to start again the process */
+      hsd->State = HAL_SD_STATE_READY;
+      HAL_SD_ErrorCallback(hsd);   
+    }
+  }
+}
+
+/**
+  * @brief return the SD state
+  * @param hsd: Pointer to sd handle
+  * @retval HAL state
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+  return hsd->State;
+}
+
+/**
+* @brief  Return the SD error code
+* @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+* @retval SD Error Code
+*/
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+  return hsd->ErrorCode;
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: Pointer to SD handle
+  * @retval None
+  */
+ __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD error callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+ 
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */ 
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group3
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control the SD card 
+    operations and get the related information
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CID register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCID: Pointer to a HAL_SD_CIDTypedef structure that  
+  *         contains all CID register parameters 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
+{
+  uint32_t tmp = 0;
+  
+  /* Byte 0 */
+  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);
+  pCID->ManufacturerID = tmp;
+  
+  /* Byte 1 */
+  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
+  pCID->OEM_AppliID = tmp << 8;
+  
+  /* Byte 2 */
+  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
+  pCID->OEM_AppliID |= tmp;
+  
+  /* Byte 3 */
+  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
+  pCID->ProdName1 = tmp << 24;
+  
+  /* Byte 4 */
+  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);
+  pCID->ProdName1 |= tmp << 16;
+  
+  /* Byte 5 */
+  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
+  pCID->ProdName1 |= tmp << 8;
+  
+  /* Byte 6 */
+  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
+  pCID->ProdName1 |= tmp;
+  
+  /* Byte 7 */
+  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
+  pCID->ProdName2 = tmp;
+  
+  /* Byte 8 */
+  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);
+  pCID->ProdRev = tmp;
+  
+  /* Byte 9 */
+  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
+  pCID->ProdSN = tmp << 24;
+  
+  /* Byte 10 */
+  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
+  pCID->ProdSN |= tmp << 16;
+  
+  /* Byte 11 */
+  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
+  pCID->ProdSN |= tmp << 8;
+  
+  /* Byte 12 */
+  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);
+  pCID->ProdSN |= tmp;
+  
+  /* Byte 13 */
+  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
+  pCID->Reserved1   |= (tmp & 0xF0) >> 4;
+  pCID->ManufactDate = (tmp & 0x0F) << 8;
+  
+  /* Byte 14 */
+  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
+  pCID->ManufactDate |= tmp;
+  
+  /* Byte 15 */
+  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
+  pCID->CID_CRC   = (tmp & 0xFE) >> 1;
+  pCID->Reserved2 = 1;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CSD register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that  
+  *         contains all CSD register parameters  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
+{
+  uint32_t tmp = 0;
+  
+  /* Byte 0 */
+  tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;
+  pCSD->CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
+  pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
+  pCSD->Reserved1      = tmp & 0x03;
+  
+  /* Byte 1 */
+  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
+  pCSD->TAAC = (uint8_t)tmp;
+  
+  /* Byte 2 */
+  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
+  pCSD->NSAC = (uint8_t)tmp;
+  
+  /* Byte 3 */
+  tmp = hsd->CSD[0] & 0x000000FF;
+  pCSD->MaxBusClkFrec = (uint8_t)tmp;
+  
+  /* Byte 4 */
+  tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;
+  pCSD->CardComdClasses = (uint16_t)(tmp << 4);
+  
+  /* Byte 5 */
+  tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;
+  pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
+  pCSD->RdBlockLen       = (uint8_t)(tmp & 0x0F);
+  
+  /* Byte 6 */
+  tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;
+  pCSD->PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
+  pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
+  pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
+  pCSD->DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
+  pCSD->Reserved2       = 0; /*!< Reserved */
+  
+  if(hsd->SdCard.CardType == CARD_SDSC)
+  {
+    pCSD->DeviceSize = (tmp & 0x03) << 10;
+    
+    /* Byte 7 */
+    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
+    pCSD->DeviceSize |= (tmp) << 2;
+    
+    /* Byte 8 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
+    pCSD->DeviceSize |= (tmp & 0xC0) >> 6;
+    
+    pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
+    pCSD->MaxRdCurrentVDDMax = (tmp & 0x07);
+    
+    /* Byte 9 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
+    pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
+    pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
+    pCSD->DeviceSizeMul      = (tmp & 0x03) << 1;
+    /* Byte 10 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
+    pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7;
+    
+    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1) ;
+    hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2));
+    hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen);
+
+    hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512); 
+    hsd->SdCard.LogBlockSize = 512;
+  }
+  else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
+  {
+    /* Byte 7 */
+    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
+    pCSD->DeviceSize = (tmp & 0x3F) << 16;
+    
+    /* Byte 8 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
+    
+    pCSD->DeviceSize |= (tmp << 8);
+    
+    /* Byte 9 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
+    
+    pCSD->DeviceSize |= (tmp);
+    
+    /* Byte 10 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
+    
+    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024);
+    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);   
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+  
+  pCSD->EraseGrSize = (tmp & 0x40) >> 6;
+  pCSD->EraseGrMul  = (tmp & 0x3F) << 1;
+  
+  /* Byte 11 */
+  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
+  pCSD->EraseGrMul     |= (tmp & 0x80) >> 7;
+  pCSD->WrProtectGrSize = (tmp & 0x7F);
+  
+  /* Byte 12 */
+  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);
+  pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7;
+  pCSD->ManDeflECC        = (tmp & 0x60) >> 5;
+  pCSD->WrSpeedFact       = (tmp & 0x1C) >> 2;
+  pCSD->MaxWrBlockLen     = (tmp & 0x03) << 2;
+  
+  /* Byte 13 */
+  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
+  pCSD->MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
+  pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5;
+  pCSD->Reserved3           = 0;
+  pCSD->ContentProtectAppli = (tmp & 0x01);
+  
+  /* Byte 14 */
+  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
+  pCSD->FileFormatGrouop = (tmp & 0x80) >> 7;
+  pCSD->CopyFlag         = (tmp & 0x40) >> 6;
+  pCSD->PermWrProtect    = (tmp & 0x20) >> 5;
+  pCSD->TempWrProtect    = (tmp & 0x10) >> 4;
+  pCSD->FileFormat       = (tmp & 0x0C) >> 2;
+  pCSD->ECC              = (tmp & 0x03);
+  
+  /* Byte 15 */
+  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
+  pCSD->CSD_CRC   = (tmp & 0xFE) >> 1;
+  pCSD->Reserved4 = 1;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the SD status info.
+  * @param  hsd: Pointer to SD handle      
+  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that 
+  *         will contain the SD card status information 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
+{
+  uint32_t tmp = 0;
+  uint32_t sd_status[16];
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  errorstate = SD_SendSDStatus(hsd, sd_status);
+  if(errorstate != HAL_OK)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);   
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Byte 0 */
+    tmp = (sd_status[0] & 0xC0) >> 6;
+    pStatus->DataBusWidth = (uint8_t)tmp;
+    
+    /* Byte 0 */
+    tmp = (sd_status[0] & 0x20) >> 5;
+    pStatus->SecuredMode = (uint8_t)tmp;
+    
+    /* Byte 2 */
+    tmp = (sd_status[0] & 0x00FF0000U) >> 16;
+    pStatus->CardType = (uint16_t)(tmp << 8);
+    
+    /* Byte 3 */
+    tmp = (sd_status[0] & 0xFF000000U) >> 24;
+    pStatus->CardType |= (uint16_t)tmp;
+    
+    /* Byte 4 */
+    tmp = (sd_status[1] & 0xFF);
+    pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24);
+    
+    /* Byte 5 */
+    tmp = (sd_status[1] & 0xFF00) >> 8;
+    pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16);
+    
+    /* Byte 6 */
+    tmp = (sd_status[1] & 0xFF0000) >> 16;
+    pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8);
+    
+    /* Byte 7 */
+    tmp = (sd_status[1] & 0xFF000000U) >> 24;
+    pStatus->ProtectedAreaSize |= (uint32_t)tmp;
+    
+    /* Byte 8 */
+    tmp = (sd_status[2] & 0xFF);
+    pStatus->SpeedClass = (uint8_t)tmp;
+    
+    /* Byte 9 */
+    tmp = (sd_status[2] & 0xFF00) >> 8;
+    pStatus->PerformanceMove = (uint8_t)tmp;
+    
+    /* Byte 10 */
+    tmp = (sd_status[2] & 0xF00000) >> 20;
+    pStatus->AllocationUnitSize = (uint8_t)tmp;
+    
+    /* Byte 11 */
+    tmp = (sd_status[2] & 0xFF000000U) >> 24;
+    pStatus->EraseSize = (uint16_t)(tmp << 8);
+    
+    /* Byte 12 */
+    tmp = (sd_status[3] & 0xFF);
+    pStatus->EraseSize |= (uint16_t)tmp;
+    
+    /* Byte 13 */
+    tmp = (sd_status[3] & 0xFC00) >> 10;
+    pStatus->EraseTimeout = (uint8_t)tmp;
+    
+    /* Byte 13 */
+    tmp = (sd_status[3] & 0x0300) >> 8;
+    pStatus->EraseOffset = (uint8_t)tmp;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the SD card info.
+  * @param  hsd: Pointer to SD handle      
+  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that 
+  *         will contain the SD card status information 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by 
+  *         card.
+  * @param  hsd: Pointer to SD handle       
+  * @param  WideMode: Specifies the SD card wide bus mode 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+  SDMMC_InitTypeDef Init;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  /* Check the parameters */
+  assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+  
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+  
+  if(hsd->SdCard.CardType != CARD_SECURED) 
+  {
+    if(WideMode == SDMMC_BUS_WIDE_8B)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else if(WideMode == SDMMC_BUS_WIDE_4B)
+    {
+      errorstate = SD_WideBus_Enable(hsd);
+      
+      hsd->ErrorCode |= errorstate;
+    }
+    else if(WideMode == SDMMC_BUS_WIDE_1B)
+    {
+      errorstate = SD_WideBus_Disable(hsd);
+      
+      hsd->ErrorCode |= errorstate;
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    }
+  }  
+  else
+  {
+    /* MMC Card does not support this feature */
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+  
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Configure the SDMMC peripheral */
+    Init.ClockEdge           = hsd->Init.ClockEdge;
+    Init.ClockBypass         = hsd->Init.ClockBypass;
+    Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+    Init.BusWide             = WideMode;
+    Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+    Init.ClockDiv            = hsd->Init.ClockDiv;
+
+    SDMMC_Init(hsd->Instance, Init);
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the current sd card data state.
+  * @param  hsd: pointer to SD handle
+  * @retval Card state
+  */
+HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypedef cardstate =  HAL_SD_CARD_TRANSFER;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  uint32_t resp1 = 0;
+  
+  errorstate = SD_SendStatus(hsd, &resp1);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= errorstate;
+  }
+
+  cardstate = (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
+  
+  return cardstate;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypedef CardState;
+  
+  /* DIsable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                           SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+  
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+  
+  if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+  {
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+    
+    /* Abort the SD DMA Tx Stream */
+    if(hsd->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(hsd->hdmatx);
+    }
+    /* Abort the SD DMA Rx Stream */
+    if(hsd->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(hsd->hdmarx);
+    }
+  }
+  
+  hsd->State = HAL_SD_STATE_READY;
+  CardState = HAL_SD_GetCardState(hsd);
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD (IT mode).
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypedef CardState;
+    
+  /* DIsable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                           SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+  
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+  
+  if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+  {
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+    
+    /* Abort the SD DMA Tx Stream */
+    if(hsd->hdmatx != NULL)
+    {
+      hsd->hdmatx->XferAbortCallback =  SD_DMATxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+      {
+        hsd->hdmatx = NULL;
+      }
+    }
+    /* Abort the SD DMA Rx Stream */
+    if(hsd->hdmarx != NULL)
+    {
+      hsd->hdmarx->XferAbortCallback =  SD_DMARxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+      {
+        hsd->hdmarx = NULL;
+      }
+    }
+  }
+  
+  /* No transfer ongoing on both DMA channels*/
+  if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
+  {
+    CardState = HAL_SD_GetCardState(hsd);
+    hsd->State = HAL_SD_STATE_READY;
+    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+    {
+      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+    }
+    if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      HAL_SD_AbortCallback(hsd);
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Private function ----------------------------------------------------------*/  
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+  
+/**
+  * @brief  DMA SD transmit process complete callback 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)     
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  
+  /* Enable DATAEND Interrupt */
+  __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND));
+}
+
+/**
+  * @brief  DMA SD receive process complete callback 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)  
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  /* Send stop command in multiblock write */
+  if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
+  {
+    errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->ErrorCode |= errorstate;
+      HAL_SD_ErrorCallback(hsd);
+    }
+  }
+  
+  /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+  in the SD DCTRL register */
+  hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+  
+  /* Clear all the static flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+  
+  hsd->State = HAL_SD_STATE_READY;
+
+  HAL_SD_RxCpltCallback(hsd);
+}
+
+/**
+  * @brief  DMA SD communication error callback 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypedef CardState;
+  
+  if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+  {
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    
+    /* Disable All interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+      SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+    
+    hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+    CardState = HAL_SD_GetCardState(hsd);
+    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+    {
+      hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+    }
+    
+    hsd->State= HAL_SD_STATE_READY;
+  }
+
+  HAL_SD_ErrorCallback(hsd);
+}
+
+/**
+  * @brief  DMA SD Tx Abort callback 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)   
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypedef CardState;
+  
+  if(hsd->hdmatx != NULL)
+  {
+    hsd->hdmatx = NULL;
+  }
+  
+  /* All DMA channels are aborted */
+  if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
+  {
+    CardState = HAL_SD_GetCardState(hsd);
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    hsd->State = HAL_SD_STATE_READY;
+    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+    {
+      hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+      
+      if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+      {
+        HAL_SD_AbortCallback(hsd);
+      }
+      else
+      {
+        HAL_SD_ErrorCallback(hsd);
+      }
+    }
+  }
+}
+
+/**
+  * @brief  DMA SD Rx Abort callback 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)   
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypedef CardState;
+  
+  if(hsd->hdmarx != NULL)
+  {
+    hsd->hdmarx = NULL;
+  }
+  
+  /* All DMA channels are aborted */
+  if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
+  {
+    CardState = HAL_SD_GetCardState(hsd);
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    hsd->State = HAL_SD_STATE_READY;
+    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+    {
+      hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+      
+      if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+      {
+        HAL_SD_AbortCallback(hsd);
+      }
+      else
+      {
+        HAL_SD_ErrorCallback(hsd);
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the sd card.
+  * @param  hsd: Pointer to SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardCSDTypedef CSD;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  uint16_t sd_rca = 1;
+  
+  /* Check the power State */
+  if(SDMMC_GetPowerState(hsd->Instance) == 0) 
+  {
+    /* Power off */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+  
+  if(hsd->SdCard.CardType != CARD_SECURED) 
+  {
+    /* Send CMD2 ALL_SEND_CID */
+    errorstate = SDMMC_CmdSendCID(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card identification number data */
+      hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+  
+  if(hsd->SdCard.CardType != CARD_SECURED) 
+  {
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+  }
+  if(hsd->SdCard.CardType != CARD_SECURED) 
+  {
+    /* Get the SD card RCA */
+    hsd->SdCard.RelCardAdd = sd_rca;
+    
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card Specific Data */
+      hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+  
+  /* Get the Card Class */
+  hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20);
+  
+  /* Get CSD parameters */
+  HAL_SD_GetCardCSD(hsd, &CSD);
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+  
+  /* Configure SDMMC peripheral interface */
+  SDMMC_Init(hsd->Instance, hsd->Init);
+  
+  /* All cards are initialized */
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores SD information that will be needed in future
+  *         in the SD handle.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+  __IO uint32_t count = 0;
+  uint32_t response = 0, validvoltage = 0;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+  
+  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+  errorstate = SDMMC_CmdOperCond(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->SdCard.CardVersion = CARD_V1_X;
+      
+    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+    while(validvoltage == 0)
+    {
+      if(count++ == SDMMC_MAX_VOLT_TRIAL)
+      {
+        return HAL_SD_ERROR_INVALID_VOLTRANGE;
+      }
+      
+      /* SEND CMD55 APP_CMD with RCA as 0 */
+      errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+      }
+      
+      /* Send CMD41 */
+      errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+      }
+      
+      /* Get command response */
+      response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      
+      /* Get operating voltage*/
+      validvoltage = (((response >> 31) == 1) ? 1 : 0);
+    }
+    /* Card type is SDSC */
+    hsd->SdCard.CardType = CARD_SDSC;
+  }
+  else
+  {
+    hsd->SdCard.CardVersion = CARD_V2_X;
+    
+    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+    while(validvoltage == 0)
+    {
+      if(count++ == SDMMC_MAX_VOLT_TRIAL)
+      {
+        return HAL_SD_ERROR_INVALID_VOLTRANGE;
+      }
+      
+      /* SEND CMD55 APP_CMD with RCA as 0 */
+      errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        return errorstate;
+      }
+      
+      /* Send CMD41 */
+      errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        return errorstate;
+      }
+      
+      /* Get command response */
+      response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      
+      /* Get operating voltage*/
+      validvoltage = (((response >> 31) == 1) ? 1 : 0);
+    }
+    
+    if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+    {
+      hsd->SdCard.CardType = CARD_SDHC_SDXC;
+    }
+    else
+    {
+      hsd->SdCard.CardType = CARD_SDSC;
+    }
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Turns the SDMMC output signals off.
+  * @param  hsd: Pointer to SD handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+  /* Set Power State to OFF */
+  SDMMC_PowerState_OFF(hsd->Instance);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Send Status info command.
+  * @param  hsd: pointer to SD handle
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status 
+  *         SD Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count = 0;
+  
+  /* Check SD response */
+  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  
+  /* Set block size for card if it is not equal to current block size for card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+  
+  /* Send CMD55 */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+  
+  /* Configure the SD DPSM (Data Path State Machine) */ 
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 64;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  SDMMC_ConfigData(hsd->Instance, &config);
+  
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+  
+  /* Get status data */
+  while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
+  {
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+    {
+      for(count = 0; count < 8; count++)
+      {
+        *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);
+      }
+      
+      pSDstatus += 8;
+    }
+    
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+  
+  if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+
+  while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
+  {
+    *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);
+    pSDstatus++;
+    
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+  
+  /* Clear all the static status flags*/
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+  
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card 
+  *         status (Card Status register)  
+  * @retval error state
+  */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if(pCardStatus == NULL)
+  {
+    return HAL_SD_ERROR_PARAM;
+  }
+  
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
+  if(errorstate != HAL_OK)
+  {
+    return errorstate;
+  }
+  
+  /* Get SD card status */
+  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+  
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enables the SDMMC wide bus mode.
+  * @param  hsd: pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2] = {0, 0};
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if(errorstate != HAL_OK)
+  {
+    return errorstate;
+  }
+  
+  /* If requested card supports wide bus operation */
+  if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA.*/
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
+    if(errorstate != HAL_OK)
+    {
+      return errorstate;
+    }
+    
+    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2);
+    if(errorstate != HAL_OK)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}   
+
+/**
+  * @brief  Disables the SDMMC wide bus mode.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2] = {0, 0};
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  
+  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if(errorstate != HAL_OK)
+  {
+    return errorstate;
+  }
+  
+  /* If requested card supports 1 bit mode operation */
+  if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
+    if(errorstate != HAL_OK)
+    {
+      return errorstate;
+    }
+    
+    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0);
+    if(errorstate != HAL_OK)
+    {
+      return errorstate;
+    }
+    
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+  
+  
+/**
+  * @brief  Finds the SD card SCR register value.
+  * @param  hsd: Pointer to SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value  
+  * @retval error state
+  */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t index = 0;
+  uint32_t tempscr[2] = {0, 0};
+  
+  /* Set Block Size To 8 Bytes */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8);
+  if(errorstate != HAL_OK)
+  {
+    return errorstate;
+  }
+
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16));
+  if(errorstate != HAL_OK)
+  {
+    return errorstate;
+  }
+
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 8;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  SDMMC_ConfigData(hsd->Instance, &config);
+  
+  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+  if(errorstate != HAL_OK)
+  {
+    return errorstate;
+  }
+  
+  while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
+  {
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
+    {
+      *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
+      index++;
+    }
+    
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+  
+  if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+    
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+    
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+    
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    
+    *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+      ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24);
+    
+    *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+      ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24);
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Wrap up reading in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count = 0;
+  uint32_t* tmp;
+
+  tmp = (uint32_t*)hsd->pRxBuffPtr;
+  
+  /* Read data from SDMMC Rx FIFO */
+  for(count = 0; count < 8; count++)
+  {
+    *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance);
+  }
+  
+  hsd->pRxBuffPtr += 8;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wrap up writing in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count = 0;
+  uint32_t* tmp;
+  
+  tmp = (uint32_t*)hsd->pTxBuffPtr;
+  
+  /* Write data to SDMMC Tx FIFO */
+  for(count = 0; count < 8; count++)
+  {
+    SDMMC_WriteFIFO(hsd->Instance, (tmp + count));
+  }
+  
+  hsd->pTxBuffPtr += 8;
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h
new file mode 100755
index 0000000..da41cd6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h
@@ -0,0 +1,785 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sd.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SD_H
+#define __STM32L4xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(SDMMC1)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SD SD
+  * @brief SD HAL module driver
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SD_Exported_Types SD Exported Types
+  * @{
+  */
+
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */
+  HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */
+  HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */
+  HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */
+  HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */
+  HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receiving State                  */
+  HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfert State                  */
+  HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */
+}HAL_SD_StateTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  HAL_SD_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */
+  HAL_SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */
+  HAL_SD_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */
+  HAL_SD_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */  
+  HAL_SD_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */
+  HAL_SD_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */
+  HAL_SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */
+  HAL_SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */
+  HAL_SD_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card response Error                     */
+}HAL_SD_CardStateTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition   
+  * @{
+  */
+#define SD_InitTypeDef      SDMMC_InitTypeDef 
+#define SD_TypeDef          SDMMC_TypeDef
+
+/** 
+  * @brief  SD Card Information Structure definition
+  */ 
+typedef struct
+{
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
+  
+  uint32_t CardVersion;                  /*!< Specifies the card version                      */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+  
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+  
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+}HAL_SD_CardInfoTypeDef;
+
+/** 
+  * @brief  SD handle Structure definition
+  */ 
+typedef struct
+{
+  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
+  
+  SD_InitTypeDef               Init;             /*!< SD required parameters              */
+  
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
+  
+  uint32_t                     *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
+  
+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
+  
+  uint32_t                     *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
+  
+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
+  
+  __IO uint32_t                Context;          /*!< SD transfer context                 */
+  
+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
+  
+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */  
+  
+  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */
+  
+  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */
+  
+  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
+  
+  uint32_t                     CSD[4];           /*!< SD card specific data table         */
+  
+  uint32_t                     CID[4];           /*!< SD card identification number table */
+  
+}SD_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register 
+  * @{
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+
+}HAL_SD_CardCSDTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+}HAL_SD_CardCIDTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t CardType;               /*!< Carries information about card type                        */
+  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
+
+}HAL_SD_CardStatusTypedef;
+/** 
+  * @}
+  */
+
+/** 
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants  Exported Constants
+  * @{
+  */
+
+#define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition 
+  * @{
+  */  
+#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
+#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
+#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
+#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
+#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
+#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
+#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the 
+                                                                                       number of transferred bytes does not match the block length   */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock 
+                                                                                       command or if there was an attempt to access a locked card    */
+#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
+#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
+#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
+#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
+#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
+#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out 
+                                                                                       of erase sequence command was received                        */
+#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  
+#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
+#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ 
+#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
+#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
+                                                
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+  * @{
+  */ 
+#define SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
+#define SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
+#define SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
+#define SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */  
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+  * @{
+  */
+#define CARD_SDSC                  ((uint32_t)0x00000000U)
+#define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)
+#define CARD_SECURED               ((uint32_t)0x00000003U)
+    
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+  * @{
+  */
+#define CARD_V1_X                  ((uint32_t)0x00000000U)
+#define CARD_V2_X                  ((uint32_t)0x00000001U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SD device.
+  * @retval None
+  */ 
+#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SD device.
+  * @retval None
+  */
+#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @retval None
+  */ 
+#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @retval None
+  */
+#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
+ 
+/**
+  * @brief  Enable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  * @retval None
+  */
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  * @retval None
+  */
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SD flag is set or not. 
+  * @param  __HANDLE__: SD Handle   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
+  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
+  * @retval The new state of SD FLAG (SET or RESET).
+  */
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SD's pending flags.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SD interrupt has occurred or not.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_DPSMACT:    Data path state machine active interrupt
+  *            @arg SDMMC_IT_CPSMACT:    Command path state machine active interrupt
+  *            @arg SDMMC_IT_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the SD's interrupt pending bits.
+  * @param  __HANDLE__: SD Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @}
+  */
+  
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+  * @{
+  */
+  
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Init     (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit   (SD_HandleTypeDef *hsd);
+void              HAL_SD_MspInit  (SD_HandleTypeDef *hsd);
+void              HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SD_ReadBlocks     (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks    (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase          (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT  (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void              HAL_SD_IRQHandler     (SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void              HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd);
+void              HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd);
+void              HAL_SD_ErrorCallback  (SD_HandleTypeDef *hsd);
+void              HAL_SD_AbortCallback  (SD_HandleTypeDef *hsd);
+
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+  * @{
+  */
+HAL_StatusTypeDef       HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_CardStateTypedef HAL_SD_GetCardState (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_GetCardCID   (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCSD   (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD);
+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo  (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t            HAL_SD_GetError(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Abort   (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+    
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+          
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_SD_H */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c
new file mode 100755
index 0000000..13b4a08
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c
@@ -0,0 +1,2289 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smartcard.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the SMARTCARD peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The SMARTCARD HAL driver can be used as follows:
+
+    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+    (#) Associate a USART to the SMARTCARD handle hsmartcard.
+    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) USART pins configuration:
+            (+++) Enable the clock for the USART GPIOs.
+            (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+             and HAL_SMARTCARD_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+             and HAL_SMARTCARD_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+        error enabling or disabling in the hsmartcard handle Init structure.
+
+    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+        in the hsmartcard handle AdvancedInit structure.
+
+    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_SMARTCARD_MspInit() API.
+        [..]
+        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+    [..]
+    [..] Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** SMARTCARD HAL driver macros list ***
+     ========================================
+     [..]
+       Below the list of most used macros in SMARTCARD HAL driver.
+
+       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+     [..]
+       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARD SMARTCARD
+  * @brief HAL SMARTCARD module driver
+  * @{
+  */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT               1000      /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
+
+#define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))       /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))   /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+  * @{
+  */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USARTx
+  associated to the SmartCard.
+  (+) These parameters can be configured:
+      (++) Baud Rate
+      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+      (++) Receiver/transmitter modes
+      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+      (++) Prescaler value
+      (++) Guard bit time
+      (++) NACK enabling or disabling on transmission error
+
+  (+) The following advanced features can be configured as well:
+      (++) TX and/or RX pin level inversion
+      (++) data logical level inversion
+      (++) RX and TX pins swap
+      (++) RX overrun detection disabling
+      (++) DMA disabling on RX error
+      (++) MSB first on communication line
+      (++) Time out enabling (and if activated, timeout value)
+      (++) Block length
+      (++) Auto-retry counter
+  [..]
+  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+  (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  The USART frame format is given in the following table:
+
+    Table 1. USART frame format.
+    +---------------------------------------------------------------+        
+    | M1M0 bits |  PCE bit  |            USART frame                |        
+    |-----------------------|---------------------------------------|        
+    |     01    |    1      |    | SB | 8 bit data | PB | STB |     |        
+    +---------------------------------------------------------------+        
+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SMARTCARD mode according to the specified
+  *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsmartcard->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_SMARTCARD_MspInit(hsmartcard);
+  }
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral to set smartcard mode */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* In SmartCard mode, the following bits must be kept cleared:
+  - LINEN in the USART_CR2 register,
+  - HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* set the USART in SMARTCARD mode */
+  SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+  /* Set the SMARTCARD Communication parameters */
+  if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Set the SMARTCARD transmission completion indication */  
+  SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
+
+  if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+  {
+    SMARTCARD_AdvFeatureConfig(hsmartcard);
+  }
+
+  /* Enable the Peripheral */
+  SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+  return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD peripheral.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  WRITE_REG(hsmartcard->Instance->CR1, 0x0);
+  WRITE_REG(hsmartcard->Instance->CR2, 0x0);
+  WRITE_REG(hsmartcard->Instance->CR3, 0x0);
+  WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
+  WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
+
+  /* DeInit the low level hardware */
+  HAL_SMARTCARD_MspDeInit(hsmartcard);
+
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+  hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
+  hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+  *  @brief   SMARTCARD Transmit and Receive functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+  [..]
+    Smartcard is a single wire half duplex communication protocol.
+    The Smartcard interface is designed to support asynchronous protocol Smartcards as
+    defined in the ISO 7816-3 standard. The USART should be configured as:
+    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+  [..]
+    (+) There are two modes of transfer:
+        (++) Blocking mode: The communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) Non-Blocking mode: The communication is performed using Interrupts
+             or DMA, the relevant API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+             will be executed respectively at the end of the Transmit or Receive process
+             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+             error is detected.
+
+    (+) Blocking mode APIs are :
+        (++) HAL_SMARTCARD_Transmit()
+        (++) HAL_SMARTCARD_Receive()
+
+    (+) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_SMARTCARD_Transmit_IT()
+        (++) HAL_SMARTCARD_Receive_IT()
+        (++) HAL_SMARTCARD_IRQHandler()
+
+    (+) Non Blocking mode functions with DMA are :
+        (++) HAL_SMARTCARD_Transmit_DMA()
+        (++) HAL_SMARTCARD_Receive_DMA()
+
+    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_SMARTCARD_TxCpltCallback()
+        (++) HAL_SMARTCARD_RxCpltCallback()
+        (++) HAL_SMARTCARD_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_SMARTCARD_Abort()
+        (+) HAL_SMARTCARD_AbortTransmit()
+        (+) HAL_SMARTCARD_AbortReceive()
+        (+) HAL_SMARTCARD_Abort_IT()
+        (+) HAL_SMARTCARD_AbortTransmit_IT()
+        (+) HAL_SMARTCARD_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_SMARTCARD_AbortCpltCallback()
+        (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
+        (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send an amount of data in blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @param  Timeout  Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+    
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    while(hsmartcard->TxXferCount > 0)
+    {
+      hsmartcard->TxXferCount--;
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+    }
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+    if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+    {
+      /* Disable the Peripheral first to update modes */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+      /* Enable the Peripheral */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+    }
+    
+    /* At end of Tx process, restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Check the remain data to be received */
+    while(hsmartcard->RxXferCount > 0)
+    {
+      hsmartcard->RxXferCount--;
+
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+    }
+
+    /* At end of Rx process, restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->pTxBuffPtr = pData;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->pTxBuffPtr = pData;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+    /* Set the SMARTCARD error callback */
+    hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the SMARTCARD transmit DMA channel */
+    HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the UART Error Interrupt: (Frame error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the SMARTCARD associated USART CR3 register */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
+  *         the received data contain the parity bit (MSB position).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+    /* Set the SMARTCARD DMA error callback */
+    hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the SMARTCARD associated USART CR3 register */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmatx);
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  hsmartcard->TxXferCount = 0; 
+  hsmartcard->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmatx);
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  hsmartcard->TxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  hsmartcard->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(hsmartcard->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+    {
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(hsmartcard->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+    {
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* SMARTCARD Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        hsmartcard->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* SMARTCARD Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        hsmartcard->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hsmartcard->TxXferCount = 0; 
+    hsmartcard->RxXferCount = 0;
+
+    /* Reset errorCode */
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+    hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+        hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hsmartcard->TxXferCount = 0; 
+
+      /* Restore hsmartcard->gState to Ready */
+      hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    hsmartcard->TxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+    /* Restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+        hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hsmartcard->RxXferCount = 0; 
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+      /* Restore hsmartcard->RxState to Ready */
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    hsmartcard->RxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle SMARTCARD interrupt requests.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
+  uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == RESET)
+  {
+    /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      SMARTCARD_Receive_IT(hsmartcard);
+      /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  cr3its = READ_REG(hsmartcard->Instance->CR3);
+  if(   (errorflags != RESET) 
+     && (    ((cr3its & USART_CR3_EIE) != RESET)
+          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
+  {
+    /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+    }
+
+    /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+    }
+
+    /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+    }
+
+    /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+    }
+
+    /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+    }
+
+    /* Call SMARTCARD Error Call back function if need be --------------------------*/
+    if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+    {
+      /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        SMARTCARD_Receive_IT(hsmartcard);
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      if (   ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
+          || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        SMARTCARD_EndRxTransfer(hsmartcard);
+
+        /* Disable the SMARTCARD DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the SMARTCARD DMA Rx channel */
+          if(hsmartcard->hdmarx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback : 
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+              hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        }
+      }
+      /* other error type to be considered as blocking :
+          - Frame error in Transmission
+      */
+      else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+      {
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+        SMARTCARD_EndTxTransfer(hsmartcard);
+
+        /* Disable the SMARTCARD DMA Tx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+          /* Abort the SMARTCARD DMA Tx channel */
+          if(hsmartcard->hdmatx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback : 
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA TX */
+            if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+              hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+  if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
+  {
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+    __HAL_UNLOCK(hsmartcard);
+    HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+    /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+     * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+    __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    SMARTCARD_Transmit_IT(hsmartcard);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+  if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET))
+  {
+    SMARTCARD_EndTransmit_IT(hsmartcard);
+    return;
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD error callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Receive Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   SMARTCARD State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### Peripheral State and Errors functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to return the State of SmartCard
+    handle and also return Peripheral Errors occurred during communication process
+     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+         of the SMARTCARD peripheral.
+     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+         communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SMARTCARD handle state.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle state
+  */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Return SMARTCARD handle state */
+  uint32_t temp1= 0x00, temp2 = 0x00;
+  temp1 = hsmartcard->gState;
+  temp2 = hsmartcard->RxState;
+
+  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the SMARTCARD handle error code.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle Error Code
+*/
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  return hsmartcard->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+  * @{
+  */
+
+/**
+  * @brief Configure the SMARTCARD associated USART peripheral.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpreg                          = 0x00000000;
+  SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
+  HAL_StatusTypeDef ret                    = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+  assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+  assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+  assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+  assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+  assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+  assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+  assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+  assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+  assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+  assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+  assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+   * Oversampling is forced to 16 (OVER8 = 0).
+   * Configure the Parity and Mode:
+   *  set PS bit according to hsmartcard->Init.Parity value
+   *  set TE and RE bits according to hsmartcard->Init.Mode value */
+  tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
+  tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = hsmartcard->Init.StopBits;
+  /* Synchronous mode is activated by default */
+  tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+  tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+  tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+  MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+   * - one-bit sampling method versus three samples' majority rule
+   *   according to hsmartcard->Init.OneBitSampling
+   * - NACK transmission in case of parity error according
+   *   to hsmartcard->Init.NACKEnable
+   * - autoretry counter according to hsmartcard->Init.AutoRetryCount     */
+  tmpreg =  (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+  tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
+  MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART GTPR Configuration ----------------------*/
+  tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
+  MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+  /*-------------------------- USART RTOR Configuration ----------------------*/
+  tmpreg =   ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+  if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+  {
+    assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+    tmpreg |=  (uint32_t) hsmartcard->Init.TimeOutValue;
+  }
+  MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+  switch (clocksource)
+  {
+    case SMARTCARD_CLOCKSOURCE_PCLK1:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_PCLK2:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_HSI:
+      hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_SYSCLK:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_LSE:
+      hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+  }
+
+}
+
+/**
+  * @brief Check the SMARTCARD Idle State.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the SMARTCARD ErrorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the SMARTCARD states */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SMARTCARD Communication Timeout.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  Flag Specifies the SMARTCARD flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+        hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+        hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmartcard);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *               the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Tx process, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *               the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+  * @brief  DMA SMARTCARD transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->TxXferCount = 0;
+
+  /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+  in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+  /* Enable the SMARTCARD Transmit Complete Interrupt */
+  __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+}
+
+/**
+  * @brief  DMA SMARTCARD receive process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->RxXferCount = 0;
+
+  /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+     in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD communication error callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+  /* Stop SMARTCARD DMA Tx request if ongoing */
+  if (  (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+      &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+  {
+    hsmartcard->TxXferCount = 0;
+    SMARTCARD_EndTxTransfer(hsmartcard);
+  }
+
+  /* Stop SMARTCARD DMA Rx request if ongoing */
+  if (  (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+      &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+  {
+    hsmartcard->RxXferCount = 0;
+    SMARTCARD_EndRxTransfer(hsmartcard);
+  }
+
+  hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->RxXferCount = 0;
+  hsmartcard->TxXferCount = 0;
+
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+  
+  hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsmartcard->hdmarx != NULL)
+  {
+    if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0;
+  hsmartcard->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+  
+  hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsmartcard->hdmatx != NULL)
+  {
+    if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0;
+  hsmartcard->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+  hsmartcard->TxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+  hsmartcard->RxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief Send an amount of data in non-blocking mode.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMARTCARD module.
+  *         Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Tx process is ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+  {
+    if(hsmartcard->TxXferCount == 0)
+    {
+      /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the SMARTCARD Transmit Complete Interrupt */
+      __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+      return HAL_OK;
+    }
+    else
+    {
+      hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
+      hsmartcard->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable the SMARTCARD Transmit Complete Interrupt */
+  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+  if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+  {
+    /* Disable the Peripheral first to update modes */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+  }
+  
+  /* Tx process is ended, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMARTCARD module.
+  *         Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Rx process is ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+  {
+    *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+    if(--hsmartcard->RxXferCount == 0)
+    {
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
+
+      /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+      if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+      {
+        /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+      }
+
+      /* Disable the SMARTCARD Parity Error Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h
new file mode 100755
index 0000000..ad6d966
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h
@@ -0,0 +1,1017 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smartcard.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SMARTCARD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SMARTCARD_H
+#define __STM32L4xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+  * @{
+  */
+
+/**
+  * @brief SMARTCARD Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits.
+                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
+
+  uint16_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref SMARTCARD_Parity
+                                           @note The parity is enabled by default (PCE is forced to 1).
+                                                 Since the WordLength is forced to 8 bits + parity, M is
+                                                 forced to 1 and the parity bit is the 9th bit. */
+
+  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Mode */
+
+  uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+  uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+  uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+  uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                           Selecting the single sample method increases the receiver tolerance to clock
+                                           deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+
+  uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler. */
+
+  uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
+
+  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
+                                           in case of parity error.
+                                           This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+  uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
+                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+  uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
+                                           it is used to implement the Character Wait Time (CWT) and
+                                           Block Wait Time (BWT). It is coded over 24 bits. */
+
+  uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+                                           This parameter can be any value from 0x0 to 0xFF */
+
+  uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
+                                            receive and transmit mode). When set to 0, retransmission is
+                                            disabled. Otherwise, its maximum value is 7 (before signalling
+                                            an error) */
+
+}SMARTCARD_InitTypeDef;
+
+/**
+  * @brief  SMARTCARD advanced features initalization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
+                                           advanced features may be initialized at the same time. This parameter
+                                           can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
+
+  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
+
+  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
+
+  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
+                                           vs negative/inverted logic).
+                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
+                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
+                                           This parameter can be a value of @ref SMARTCARD_MSB_First */
+                                           
+  uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when 
+                                            relevant flag is available) or once guard time period has elapsed.
+                                           This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */                                            
+}SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL SMARTCARD State structures definition
+  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains SMARTCARD state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_SMARTCARD_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing 
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                        Value is allowed for RxState only */
+  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                        Not to be used for neither gState nor RxState.
+                                                        Value is result of combination (Or) between gState and RxState values */
+  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_ERROR             = 0xE0U    /*!< Error
+                                                        Value is allowed for gState only */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+  * @brief  HAL SMARTCARD Error Code structure definition
+  */
+typedef enum
+{
+  HAL_SMARTCARD_ERROR_NONE      = 0x00,    /*!< No error                */
+  HAL_SMARTCARD_ERROR_PE        = 0x01,    /*!< Parity error            */
+  HAL_SMARTCARD_ERROR_NE        = 0x02,    /*!< Noise error             */
+  HAL_SMARTCARD_ERROR_FE        = 0x04,    /*!< frame error             */
+  HAL_SMARTCARD_ERROR_ORE       = 0x08,    /*!< Overrun error           */
+  HAL_SMARTCARD_ERROR_DMA       = 0x10,    /*!< DMA transfer error      */
+  HAL_SMARTCARD_ERROR_RTO       = 0x20     /*!< Receiver TimeOut error  */
+}HAL_SMARTCARD_ErrorTypeDef;
+
+/**
+  * @brief  SMARTCARD handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef                   *Instance;        /*!< USART registers base address                          */
+
+  SMARTCARD_InitTypeDef           Init;             /*!< SmartCard communication parameters                    */
+
+  SMARTCARD_AdvFeatureInitTypeDef AdvancedInit;     /*!< SmartCard advanced features initialization parameters */
+
+  uint8_t                         *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer               */
+
+  uint16_t                        TxXferSize;       /*!< SmartCard Tx Transfer size                            */
+
+  __IO uint16_t                   TxXferCount;      /*!< SmartCard Tx Transfer Counter                         */
+
+  uint8_t                         *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer               */
+
+  uint16_t                        RxXferSize;       /*!< SmartCard Rx Transfer size                            */
+
+  __IO uint16_t                   RxXferCount;      /*!< SmartCard Rx Transfer Counter                         */
+
+  DMA_HandleTypeDef               *hdmatx;          /*!< SmartCard Tx DMA Handle parameters                    */
+
+  DMA_HandleTypeDef               *hdmarx;          /*!< SmartCard Rx DMA Handle parameters                    */
+
+  HAL_LockTypeDef                 Lock;             /*!< Locking object                                        */
+
+  __IO HAL_SMARTCARD_StateTypeDef    gState;        /*!< SmartCard state information related to global Handle management 
+                                                         and also related to Tx operations.
+                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+  __IO HAL_SMARTCARD_StateTypeDef    RxState;       /*!< SmartCard state information related to Rx operations.
+                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+  uint32_t                        ErrorCode;        /*!< SmartCard Error code                                  */
+
+}SMARTCARD_HandleTypeDef;
+
+/**
+  * @brief  SMARTCARD clock sources
+  */
+typedef enum
+{
+  SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00, /*!< PCLK1 clock source     */
+  SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01, /*!< PCLK2 clock source     */
+  SMARTCARD_CLOCKSOURCE_HSI       = 0x02, /*!< HSI clock source       */
+  SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04, /*!< SYSCLK clock source    */
+  SMARTCARD_CLOCKSOURCE_LSE       = 0x08, /*!< LSE clock source       */
+  SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10  /*!< undefined clock source */
+}SMARTCARD_ClockSourceTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+  * @{
+  */
+#define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M0)              /*!< SMARTCARD frame length */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+  * @{
+  */
+#define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)                      /*!< SMARTCARD frame with 0.5 stop bit  */
+#define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+  * @{
+  */
+#define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)                  /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+  * @{
+  */
+#define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)                  /*!< SMARTCARD RX mode        */
+#define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)                  /*!< SMARTCARD TX mode        */
+#define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))  /*!< SMARTCARD RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+  * @{
+  */
+#define SMARTCARD_POLARITY_LOW              ((uint32_t)0x00000000)                   /*!< SMARTCARD frame low polarity  */
+#define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)               /*!< SMARTCARD frame high polarity */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+  * @{
+  */
+#define SMARTCARD_PHASE_1EDGE               ((uint32_t)0x00000000)                  /*!< SMARTCARD frame phase on first clock transition  */
+#define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)              /*!< SMARTCARD frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+  * @{
+  */
+#define SMARTCARD_LASTBIT_DISABLE           ((uint32_t)0x00000000)                 /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)             /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+  * @{
+  */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    ((uint32_t)0x00000000)                 /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     ((uint32_t)USART_CR3_ONEBIT)           /*!< SMARTCARD frame one-bit sample enabled  */
+/**
+  * @}
+  */
+
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)            /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_DISABLE              ((uint32_t)0x00000000)                /*!< SMARTCARD NACK transmission enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+  * @{
+  */
+#define SMARTCARD_TIMEOUT_DISABLE           ((uint32_t)0x00000000)                /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE            ((uint32_t)USART_CR2_RTOEN)           /*!< SMARTCARD receiver timeout enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE  ((uint32_t)0x00000000)                /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE   ((uint32_t)USART_CR2_TXINV)           /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE  ((uint32_t)0x00000000)                /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE   ((uint32_t)USART_CR2_RXINV)           /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  ((uint32_t)0x00000000)              /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000)                /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)            /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000)              /*!< RX overrun enable  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   ((uint32_t)0x00000000)         /*!< DMA enable on Reception Error  */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  ((uint32_t)USART_CR3_DDRE)     /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000)           /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)   /*!< Most significant bit sent/received first enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+  * @{
+  */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush request */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
+  * @{
+  */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS       ((uint32_t) 17)   /*!< SMARTCARD auto retry counter LSB position in CR3 register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
+  * @{
+  */
+#define SMARTCARD_GTPR_GT_LSB_POS           ((uint32_t) 8)   /*!<  SMARTCARD guard time value LSB position in GTPR register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
+  * @{
+  */
+#define SMARTCARD_RTOR_BLEN_LSB_POS         ((uint32_t) 24)  /*!< SMARTCARD block length LSB position in RTOR register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+  * @{
+  */
+#define SMARTCARD_IT_MASK                   ((uint16_t)0x001F)   /*!< SMARTCARD interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SMARTCARD handle states.
+  * @param  __HANDLE__: SMARTCARD handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
+                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
+                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
+                                                          } while(0)
+
+/** @brief  Flush the Smartcard Data registers.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                                 \
+    do{                                                                              \
+      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+      } while(0)
+
+/** @brief  Clear the specified SMARTCARD pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  @if STM32L443xx
+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)    
+  @endif
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the SMARTCARD PE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+
+/** @brief  Clear the SMARTCARD FE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief  Clear the SMARTCARD NE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief  Clear the SMARTCARD ORE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief  Clear the SMARTCARD IDLE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  @if STM32L443xx
+  *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)  
+  @endif
+  *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
+  *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
+  *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
+  *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
+  *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag  
+  *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
+  *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
+  *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
+  *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Enable the specified SmartCard interrupt.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  @if STM32L443xx
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)             
+  @endif
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief  Disable the specified SmartCard interrupt.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  @if STM32L443xx
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)   
+  @endif
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt   
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+
+/** @brief  Check whether the specified SmartCard interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  @if STM32L443xx
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)    
+  @endif
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_ORE   Overrun error interrupt
+  *            @arg @ref SMARTCARD_IT_NE    Noise error interrupt
+  *            @arg @ref SMARTCARD_IT_FE    Framing error interrupt
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  @if STM32L443xx
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)     
+  @endif
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_ERR   Framing, overrun or noise error interrupt
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
+                                                           (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
+                                                           (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
+
+
+/** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag    
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  @if STM32L443xx
+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)     
+  @endif
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific SMARTCARD request flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __REQ__: specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+  *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @retval None
+  */     
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @retval None
+  */      
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable the USART associated to the SMARTCARD Handle.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable the USART associated to the SMARTCARD Handle
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+  * @{
+  */
+
+/** @brief  Check the Baud rate range. 
+  * @note   The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz)
+  *         divided by the oversampling used on the SMARTCARD (i.e. 16).
+  * @param  __BAUDRATE__: Baud rate set by the configuration function.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001)
+
+/** @brief  Check the block length range.
+  * @note   The maximum SMARTCARD block length is 0xFF.
+  * @param  __LENGTH__: block length.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
+
+/** @brief  Check the receiver timeout value. 
+  * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__: receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFF)
+
+/** @brief  Check the SMARTCARD autoretry counter value. 
+  * @note   The maximum number of retransmissions is 0x7.
+  * @param  __COUNT__: number of retransmissions.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7)
+
+/**
+  * @brief Ensure that SMARTCARD frame length is valid.
+  * @param __LENGTH__: SMARTCARD frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */ 
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/**
+  * @brief Ensure that SMARTCARD frame number of stop bits is valid.
+  * @param __STOPBITS__: SMARTCARD frame number of stop bits. 
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */ 
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/**
+  * @brief Ensure that SMARTCARD frame parity is valid.
+  * @param __PARITY__: SMARTCARD frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/**
+  * @brief Ensure that SMARTCARD communication mode is valid.
+  * @param __MODE__: SMARTCARD communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
+
+/**
+  * @brief Ensure that SMARTCARD frame polarity is valid.
+  * @param __CPOL__: SMARTCARD frame polarity. 
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */ 
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/**
+  * @brief Ensure that SMARTCARD frame phase is valid.
+  * @param __CPHA__: SMARTCARD frame phase. 
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/**
+  * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. 
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame sampling is valid.
+  * @param __ONEBIT__: SMARTCARD frame sampling. 
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD NACK transmission setting is valid.
+  * @param __NACK__: SMARTCARD NACK transmission setting. 
+  * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+  */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/**
+  * @brief Ensure that SMARTCARD receiver timeout setting is valid.
+  * @param __TIMEOUT__: SMARTCARD receiver timeout setting. 
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD advanced features initialization is valid.
+  * @param __INIT__: SMARTCARD advanced features initialization. 
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
+                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
+                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
+                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+  * @param __TXINV__: SMARTCARD frame TX inversion setting. 
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+  * @param __RXINV__: SMARTCARD frame RX inversion setting. 
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame data inversion setting is valid.
+  * @param __DATAINV__: SMARTCARD frame data inversion setting. 
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+  * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. 
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame overrun setting is valid.
+  * @param __OVERRUN__: SMARTCARD frame overrun setting. 
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+  * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. 
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that SMARTCARD frame MSB first setting is valid.
+  * @param __MSBFIRST__: SMARTCARD frame MSB first setting. 
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD request parameter is valid.
+  * @param __PARAM__: SMARTCARD request parameter. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @}
+  */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32l4xx_hal_smartcard_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
+  * @{
+  */
+
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c
new file mode 100755
index 0000000..a73b80e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c
@@ -0,0 +1,208 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smartcard_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides extended firmware functions to manage the following
+  *          functionalities of the SmartCard.
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+  =============================================================================
+               ##### SMARTCARD peripheral extended features  #####
+  =============================================================================
+  [..]
+  The Extended SMARTCARD HAL driver can be used as follows:
+
+    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+  * @brief SMARTCARD Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  * @brief    Extended control functions
+  *
+@verbatim
+  ===============================================================================
+                      ##### Peripheral Control functions #####
+  ===============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the SMARTCARD.
+     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Update on the fly the SMARTCARD block length in RTOR register.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param BlockLength: SMARTCARD block length (8-bit long at most)
+  * @retval None
+  */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+}
+
+/**
+  * @brief Update on the fly the receiver timeout value in RTOR register.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+  assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/**
+  * @brief Enable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Set the USART RTOEN bit */
+    SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Disable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Clear the USART RTOEN bit */
+    CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h
new file mode 100755
index 0000000..e2b7cbe
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h
@@ -0,0 +1,395 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smartcard_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SMARTCARD HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SMARTCARD_EX_H
+#define __STM32L4xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARDEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/  
+/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
+  * @{
+  */
+  
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+  * @{
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#endif /* USART_TCBGT_SUPPORT */  
+#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+  * @}
+  */    
+  
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)    /*!< No advanced feature initialization                  */ 
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)    /*!< TX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)    /*!< RX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)    /*!< Binary data inversion                               */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)    /*!< TX/RX pins swap                                     */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)    /*!< RX overrun disable                                  */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)    /*!< DMA disable on Reception Error                      */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)    /*!< Most significant bit sent/received first            */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION            ((uint32_t)0x00000100)    /*!< TX completion indication before of after guard time */
+#endif /* USART_TCBGT_SUPPORT */   
+/**
+  * @}
+  */
+
+
+  
+  
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT      /*!< SMARTCARD transmission complete before guard time completion */
+#endif /* USART_TCBGT_SUPPORT */ 
+#define SMARTCARD_FLAG_REACK          USART_ISR_REACK      /*!< SMARTCARD receive enable acknowledge flag  */
+#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK      /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY       /*!< SMARTCARD busy flag                        */
+#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF       /*!< SMARTCARD end of block flag                */
+#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF       /*!< SMARTCARD receiver timeout flag            */
+#define SMARTCARD_FLAG_TXE            USART_ISR_TXE        /*!< SMARTCARD transmit data register empty     */
+#define SMARTCARD_FLAG_TC             USART_ISR_TC         /*!< SMARTCARD transmission complete            */
+#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE       /*!< SMARTCARD read data register not empty     */
+#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE       /*!< SMARTCARD idle line detection              */
+#define SMARTCARD_FLAG_ORE            USART_ISR_ORE        /*!< SMARTCARD overrun error                    */
+#define SMARTCARD_FLAG_NE             USART_ISR_NE         /*!< SMARTCARD noise error                      */
+#define SMARTCARD_FLAG_FE             USART_ISR_FE         /*!< SMARTCARD frame error                      */
+#define SMARTCARD_FLAG_PE             USART_ISR_PE         /*!< SMARTCARD parity error                     */
+/**
+  * @}
+  */
+  
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5 bits)
+  *           - XX  : Interrupt source register (2 bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5 bits)
+  * @{
+  */
+#define SMARTCARD_IT_PE                     ((uint16_t)0x0028)        /*!< SMARTCARD parity error interruption                 */
+#define SMARTCARD_IT_TXE                    ((uint16_t)0x0727)        /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC                     ((uint16_t)0x0626)        /*!< SMARTCARD transmission complete interruption        */
+#define SMARTCARD_IT_RXNE                   ((uint16_t)0x0525)        /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE                   ((uint16_t)0x0424)        /*!< SMARTCARD idle line detection interruption          */
+                                                                      
+#define SMARTCARD_IT_ERR                    ((uint16_t)0x0060)        /*!< SMARTCARD error interruption         */
+#define SMARTCARD_IT_ORE                    ((uint16_t)0x0300)        /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE                     ((uint16_t)0x0200)        /*!< SMARTCARD noise error interruption   */
+#define SMARTCARD_IT_FE                     ((uint16_t)0x0100)        /*!< SMARTCARD frame error interruption   */
+
+#define SMARTCARD_IT_EOB                    ((uint16_t)0x0C3B)        /*!< SMARTCARD end of block interruption     */ 
+#define SMARTCARD_IT_RTO                    ((uint16_t)0x0B3A)        /*!< SMARTCARD receiver timeout interruption */
+
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_IT_TCBGT                  ((uint16_t)0x1978)        /*!< SMARTCARD transmission complete before guard time completion interruption */
+#endif /* USART_TCBGT_SUPPORT */ 
+/**
+  * @}
+  */
+  
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+  * @{
+  */
+#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
+#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
+#define SMARTCARD_CLEAR_NEF                 USART_ICR_NCF     /*!< SMARTCARD noise detected clear flag        */
+#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
+#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
+#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#endif /* USART_TCBGT_SUPPORT */ 
+#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
+#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
+/**
+  * @}
+  */  
+    
+/**
+  * @}
+  */ 
+/* Exported macros -----------------------------------------------------------*/  
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+  * @{
+  */
+  
+/** @brief  Report the SMARTCARD clock source.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L432xx) || defined (STM32L442xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#else
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART3)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+       {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#endif /* STM32L432xx || STM32L442xx */
+
+/** @brief  Set the Transmission Completion flag
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if 
+  *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced 
+  *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).     
+  * @retval None
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
+  do {                                                                                                       \
+    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
+    {                                                                                                        \
+     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
+    }                                                                                                        \
+    else                                                                                                     \
+    {                                                                                                        \
+      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+    }                                                                                                        \
+  } while(0)
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)         \
+  do {                                                                \
+    (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+  } while(0)  
+#endif 
+
+/** @brief  Return the transmission completion flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+  *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
+  *        reported.       
+  * @retval Transmission completion flag
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)    (SMARTCARD_FLAG_TC)
+#endif
+  
+/**
+  * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+  * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag. 
+  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+  */ 
+#if defined(USART_TCBGT_SUPPORT)
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
+                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))
+#else
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
+#endif
+
+/**
+  * @}
+  */      
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Peripheral Control functions ***********************************************/
+void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c
new file mode 100755
index 0000000..fdbd042
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c
@@ -0,0 +1,2155 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smbus.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SMBUS HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the System Management Bus (SMBus) peripheral,
+  *          based on I2C principles of operation :
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The SMBUS HAL driver can be used as follows:
+    
+    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+        SMBUS_HandleTypeDef  hsmbus; 
+
+    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+        (##) Enable the SMBUSx interface clock
+        (##) SMBUS pins configuration
+            (+++) Enable the clock for the SMBUS GPIOs
+            (+++) Configure SMBUS pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the SMBUSx interrupt priority 
+            (+++) Enable the NVIC SMBUS IRQ Channel
+
+    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+
+    (#) For SMBUS IO operations, only one mode of operations is available within this driver
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+      (++) The associated previous transfer callback is called at the end of abort process
+      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
+      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+      (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
+      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Alert Error Code using function HAL_SMBUS_GetError()
+      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Error Code using function HAL_SMBUS_GetError()
+
+     *** SMBUS HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in SMBUS HAL driver.
+
+      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
+      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
+      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
+      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
+      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
+      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
+
+     [..]
+       (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+            
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMBUS SMBUS
+  * @brief SMBUS HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)      /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
+#define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
+#define MAX_NBYTE_SIZE      255U
+/**
+  * @}
+  */
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+  * @{
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and 
+          deinitialize the SMBUSx peripheral:
+
+      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures 
+          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+      (+) Call the function HAL_SMBUS_Init() to configure the selected device with 
+          the selected configuration:
+        (++) Clock Timing
+        (++) Bus Timeout
+        (++) Analog Filer mode
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+        (++) Packet Error Check mode
+        (++) Peripheral mode
+
+
+      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration 
+          of the selected SMBUSx peripheral.       
+
+      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+          HAL_SMBUS_ConfigDigitalFilter().  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SMBUS according to the specified parameters 
+  *         in the SMBUS_InitTypeDef and initialize the associated handle.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{ 
+  /* Check the SMBUS handle allocation */
+  if(hsmbus == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+  assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+  assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+  assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+  assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+  assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+  assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+  assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+  assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+  assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+  if(hsmbus->State == HAL_SMBUS_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsmbus->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_SMBUS_MspInit(hsmbus);
+  }
+  
+  hsmbus->State = HAL_SMBUS_STATE_BUSY;
+  
+  /* Disable the selected SMBUS peripheral */
+  __HAL_SMBUS_DISABLE(hsmbus);
+  
+  /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/  
+  /* Configure SMBUSx: Frequency range */
+  hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+  
+  /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/  
+  /* Configure SMBUSx: Bus Timeout  */
+  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+  hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+  /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+  /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+  hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+  
+  if(hsmbus->Init.OwnAddress1 != 0U)
+  {
+    if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+    {
+      hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+    }
+    else /* SMBUS_ADDRESSINGMODE_10BIT */
+    {
+      hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
+    }
+  }
+
+  /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
+  /* Configure SMBUSx: Addressing Master mode */
+  if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+  {
+    hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+  /* AUTOEND and NACK bit will be manage during Transfer process */
+  hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+  
+  /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/  
+  /* Configure SMBUSx: Dual mode and Own Address2 */
+  hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
+
+  /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+  /* Configure SMBUSx: Generalcall and NoStretch mode */
+  hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+  
+  /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
+  if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
+     && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
+  {
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+  }
+
+  /* Enable the selected SMBUS peripheral */
+  __HAL_SMBUS_ENABLE(hsmbus);
+  
+  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+  hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+  hsmbus->State = HAL_SMBUS_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the SMBUS peripheral. 
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the SMBUS handle allocation */
+  if(hsmbus == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  
+  hsmbus->State = HAL_SMBUS_STATE_BUSY;
+  
+  /* Disable the SMBUS Peripheral Clock */
+  __HAL_SMBUS_DISABLE(hsmbus);
+  
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_SMBUS_MspDeInit(hsmbus);
+  
+  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+  hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
+  hsmbus->State = HAL_SMBUS_STATE_RESET;
+  
+   /* Release Lock */
+  __HAL_UNLOCK(hsmbus);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the SMBUS MSP.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief DeInitialize the SMBUS MSP.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Configure Analog noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
+  *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Reset ANOFF bit */
+    hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hsmbus->Instance->CR1 |= AnalogFilter;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure Digital noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Get the old register value */
+    tmpreg = hsmbus->Instance->CR1;
+
+    /* Reset I2C DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+    /* Store the new register value */
+    hsmbus->Instance->CR1 = tmpreg;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the SMBUS data 
+    transfers.
+
+    (#) Blocking mode function to check if device is ready for usage is :
+        (++) HAL_SMBUS_IsDeviceReady()
+
+    (#) There is only one mode of transfer:
+       (++) Non-Blocking mode : The communication is performed using Interrupts.
+            These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the 
+            dedicated SMBUS IRQ when using Interrupt mode.
+
+    (#) Non-Blocking mode functions with Interrupt are :
+        (++) HAL_SMBUS_Master_Transmit_IT()
+        (++) HAL_SMBUS_Master_Receive_IT()
+        (++) HAL_SMBUS_Slave_Transmit_IT()
+        (++) HAL_SMBUS_Slave_Receive_IT()
+        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
+        (++) HAL_SMBUS_DisableListen_IT()
+        (++) HAL_SMBUS_EnableAlert_IT()
+        (++) HAL_SMBUS_DisableAlert_IT()
+
+    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+        (++) HAL_SMBUS_MasterTxCpltCallback()
+        (++) HAL_SMBUS_MasterRxCpltCallback()
+        (++) HAL_SMBUS_SlaveTxCpltCallback()
+        (++) HAL_SMBUS_SlaveRxCpltCallback()
+        (++) HAL_SMBUS_AddrCallback()
+        (++) HAL_SMBUS_ListenCpltCallback()
+        (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{   
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+    
+    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* In case of Quick command, remove autoend mode */
+    /* Manage the stop generation by software */
+    if(hsmbus->pBuffPtr == NULL)
+    {
+      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+    }
+
+    if(Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+    {
+      SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+    }
+    else
+    {
+      /* If transfer direction not change, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+      {
+        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      }
+      /* Else transfer direction change, so generate Restart with new transfer direction */
+      else
+      {
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+      }
+
+      /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+      if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+      {
+        hsmbus->XferSize--;
+        hsmbus->XferCount--;
+      }
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus); 
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  } 
+}
+
+/**
+  * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+    
+    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+    
+    /* In case of Quick command, remove autoend mode */
+    /* Manage the stop generation by software */
+    if(hsmbus->pBuffPtr == NULL)
+    {
+      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+    }
+    
+    if(Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+    
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+    {
+      SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+    }
+    else
+    {
+      /* If transfer direction not change, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+      {
+        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      }
+      /* Else transfer direction change, so generate Restart with new transfer direction */
+      else
+      {
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+      }
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus); 
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  } 
+}
+
+/**
+  * @brief  Abort a master/host SMBUS process communication with Interrupt.
+  * @note   This abort can be called only if state is ready
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+    
+    /* Keep the same state as previous */
+    /* to perform as well the call of the corresponding end of transfer callback */
+    if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+    }
+    else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Wrong usage of abort function */
+      /* This function should be used only in case of abort monitored by master device */
+      return HAL_ERROR;
+    }
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    
+    /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus); 
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+    }
+    else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+    }
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  } 
+}
+
+/**
+  * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  {
+    if((pData == NULL) || (Size == 0U)) 
+    {
+      return  HAL_ERROR;                                    
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+    
+    hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    
+    /* Set SBC bit to manage Acknowledge at each bit */
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+    /* Enable Address Acknowledge */
+    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
+    if(Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+    {
+      SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+    }
+    else
+    {
+      /* Set NBYTE to transmit */
+      SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+
+      /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+      if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+      {
+        hsmbus->XferSize--;
+        hsmbus->XferCount--;
+      }
+    }
+    
+    /* Clear ADDR flag after prepare the transfer parameters */
+    /* This action will generate an acknowledge to the HOST */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus); 
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    /* REnable ADDR interrupt */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR; 
+  } 
+}
+
+/**
+  * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  {
+    if((pData == NULL) || (Size == 0U)) 
+    {
+      return  HAL_ERROR;                                    
+    }
+    
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+    
+    hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    
+    /* Set SBC bit to manage Acknowledge at each bit */
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+    /* Enable Address Acknowledge */
+    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferSize = Size;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
+    /* Set NBYTE to receive */
+    /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+    /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+    /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+    /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+    if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+    {
+      SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+    }
+    else
+    {
+      SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+    }
+
+    /* Clear ADDR flag after prepare the transfer parameters */
+    /* This action will generate an acknowledge to the HOST */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus); 
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process 
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    /* REnable ADDR interrupt */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR; 
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+  
+  /* Enable the Address Match interrupt */
+  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  {
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+  
+    /* Disable the Address Match interrupt */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+  
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the SMBUS alert mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Enable SMBus alert */
+  hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;   
+
+  /* Clear ALERT flag */
+  __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+  /* Enable Alert Interrupt */
+  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+  return HAL_OK; 
+}
+/**
+  * @brief  Disable the SMBUS alert mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Enable SMBus alert */
+  hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;   
+  
+  /* Disable Alert Interrupt */
+  SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Check if target device is ready for communication. 
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{  
+  uint32_t tickstart = 0U;
+  
+  __IO uint32_t SMBUS_Trials = 0U;
+ 
+  if(hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+    
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    
+    do
+    {
+      /* Generate Start */
+      hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
+      
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+      while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+      {
+        if(Timeout != HAL_MAX_DELAY)
+        {    
+          if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+          {
+            /* Device is ready */
+            hsmbus->State = HAL_SMBUS_STATE_READY;
+        
+            /* Process Unlocked */
+            __HAL_UNLOCK(hsmbus);
+            return HAL_TIMEOUT;
+          }
+        } 
+      }
+      
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */ 
+        if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)      
+        {
+          return HAL_TIMEOUT;
+        }
+        
+        /* Clear STOP Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+        /* Device is ready */
+        hsmbus->State = HAL_SMBUS_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmbus);
+        
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */ 
+        if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)      
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      }
+      
+      /* Check if the maximum allowed number of trials has been reached */
+      if (SMBUS_Trials++ == Trials)
+      {
+        /* Generate Stop */
+        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+        
+        /* Wait until STOPF flag is reset */ 
+        if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)      
+        {
+          return HAL_TIMEOUT;
+        }
+        
+        /* Clear STOP Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      }      
+    }while(SMBUS_Trials < Trials);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+        
+    return HAL_TIMEOUT;
+  }      
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  Handle SMBUS event interrupt request.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  uint32_t tmpisrvalue = 0U;
+  
+  /* Use a local variable to store the current ISR flags */
+  /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+  tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
+    
+  /* SMBUS in mode Transmitter ---------------------------------------------------*/
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+  {     
+    /* Slave mode selected */
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+    {
+      SMBUS_Slave_ISR(hsmbus);
+    }
+    /* Master mode selected */
+    else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      SMBUS_Master_ISR(hsmbus);
+    }
+  }
+    
+  /* SMBUS in mode Receiver ----------------------------------------------------*/
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+  {
+    /* Slave mode selected */
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+    {
+      SMBUS_Slave_ISR(hsmbus);
+    }
+    /* Master mode selected */
+    else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      SMBUS_Master_ISR(hsmbus);
+    }
+  } 
+      
+   /* SMBUS in mode Listener Only --------------------------------------------------*/
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
+     && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+  {
+    if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+    {
+      SMBUS_Slave_ISR(hsmbus);
+    }
+  }
+}
+
+/**
+  * @brief  Handle SMBUS error interrupt request.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* SMBUS Bus error interrupt occurred ------------------------------------*/
+  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+  { 
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+   
+    /* Clear BERR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+  }
+  
+  /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+  { 
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+  }
+
+  /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+  { 
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+  }
+
+  /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+  { 
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+    /* Clear TIMEOUT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+  }
+
+  /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+  { 
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+    /* Clear ALERT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+  }
+
+  /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+  if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+  { 
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+    /* Clear PEC error flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+  }
+  
+  /* Call the Error Callback in case of Error detected */
+  if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+  {
+    /* Do not Reset the HAL state in case of ALERT error */
+    if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+    {
+      if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+         || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+      {
+        /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+        /* keep HAL_SMBUS_STATE_LISTEN if set */
+        hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+        hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+      }
+    }
+    
+    /* Call the Error callback to prevent upper layer */
+    HAL_SMBUS_ErrorCallback(hsmbus);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  TransferDirection: Master request Transfer Direction (Write/Read)
+  * @param  AddrMatchCode: Address Match Code
+  * @retval None
+  */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SMBUS error callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_ErrorCallback() could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 
+ *  @brief   Peripheral State and Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SMBUS handle state.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL state
+  */
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Return SMBUS handle state */
+  return hsmbus->State;
+}
+
+/**
+* @brief  Return the SMBUS error code.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *              the configuration information for the specified SMBUS.
+* @retval SMBUS Error Code
+*/
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+  return hsmbus->ErrorCode;
+}
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */  
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ *  @brief   Data transfers Private functions 
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) 
+{
+  uint16_t DevAddress;
+
+  /* Process Locked */
+  __HAL_LOCK(hsmbus);
+  
+  if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+    
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+    
+    /* Call the Error callback to prevent upper layer */
+    HAL_SMBUS_ErrorCallback(hsmbus);
+  }
+  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      /* Disable Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+    
+      /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+      /* Disable the selected SMBUS peripheral */
+      __HAL_SMBUS_DISABLE(hsmbus);
+
+      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+  
+      /* REenable the selected SMBUS peripheral */
+      __HAL_SMBUS_ENABLE(hsmbus);
+
+      HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+    }
+    else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      /* Store Last receive data if any */
+      if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+      {
+        /* Read data from RXDR */
+        (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+        if((hsmbus->XferSize > 0U))
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+
+      /* Disable Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+    
+      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+  
+      HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+    }
+  }
+  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+  {  
+    /* Read data from RXDR */
+    (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+    hsmbus->XferSize--;
+    hsmbus->XferCount--;
+  }
+  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  {
+    /* Write data to TXDR */
+    hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+    hsmbus->XferSize--;
+    hsmbus->XferCount--;	
+  }
+  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+  {
+    if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+    {
+      DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
+      
+      if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+      {    
+        SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+        hsmbus->XferSize = MAX_NBYTE_SIZE;
+      }
+      else
+      {
+        hsmbus->XferSize = hsmbus->XferCount;
+        SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+        /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+        if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+    }
+    else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        {
+          /* Disable Interrupt */
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+      
+          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+        }
+        else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        {
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+      
+          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+        }
+      }
+    }
+  }
+  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+  {
+    if(hsmbus->XferCount == 0U)
+    {
+      /* Specific use case for Quick command */
+      if(hsmbus->pBuffPtr == NULL)
+      {
+        /* Generate a Stop command */
+        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+      }
+      /* Call TxCpltCallback() if no stop mode is set */
+      else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      {
+        /* No Generate Stop, to permit restart mode */
+        /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+        
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        {
+          /* Disable Interrupt */
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+      
+          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+        }
+        else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        {
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+      
+          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+        }
+      }
+    }
+  }
+    
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmbus); 
+  
+  return HAL_OK; 
+}  
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) 
+{
+  uint8_t TransferDirection = 0U;
+  uint16_t SlaveAddrCode = 0U;
+
+  /* Process Locked */
+  __HAL_LOCK(hsmbus);
+  
+  if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+  {
+    /* Check that SMBUS transfer finished */
+    /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if(hsmbus->XferCount == 0U)
+    {
+      /* Clear NACK Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+    }
+    else
+    {
+      /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+      /* Clear NACK Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      /* Set HAL State to "Idle" State, mean to LISTEN state */
+      /* So reset Slave Busy state */
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+      /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+      
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+    
+      /* Call the Error callback to prevent upper layer */
+      HAL_SMBUS_ErrorCallback(hsmbus);
+    }
+  }
+  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+  {
+    TransferDirection = SMBUS_GET_DIR(hsmbus);
+    SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
+      
+    /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+    /* Other ADDRInterrupt will be treat in next Listen usecase */
+    __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Call Slave Addr callback */
+    HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+  }
+  else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+  {
+    if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+    {
+      /* Read data from RXDR */
+      (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+      hsmbus->XferSize--;
+      hsmbus->XferCount--;
+
+      if(hsmbus->XferCount == 1U)
+      {
+        /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+        /* or only the last Byte of Transfer */
+        /* So reset the RELOAD bit mode */
+        hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+        SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      }
+      else if(hsmbus->XferCount == 0U)
+      {
+        /* Last Byte is received, disable Interrupt */
+        SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+        
+        /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+        hsmbus->PreviousState = hsmbus->State;
+        hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmbus);
+
+        /* Call the Rx complete callback to inform upper layer of the end of receive process */
+        HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+      }
+      else
+      {
+        /* Set Reload for next Bytes */
+        SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+
+        /* Ack last Byte Read */
+        hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+      }
+    }    
+    else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+    {
+      if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+      {
+        if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+        {    
+          SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+          hsmbus->XferSize = MAX_NBYTE_SIZE;
+        }
+        else
+        {
+          hsmbus->XferSize = hsmbus->XferCount;
+          SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+          /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+          /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+          if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+          {
+            hsmbus->XferSize--;
+            hsmbus->XferCount--;
+          }
+        }
+      }
+    }
+  }
+  else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Data have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if(hsmbus->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+      hsmbus->XferCount--;
+      hsmbus->XferSize--;
+    }
+    
+    if(hsmbus->XferCount == 0U)
+    {
+      /* Last Byte is Transmitted */
+      /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+      HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+    }
+  }
+
+  /* Check if STOPF is set */
+  if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+  {
+    if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Store Last receive data if any */
+      if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+      {
+        /* Read data from RXDR */
+        (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+        if((hsmbus->XferSize > 0U))
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+
+      /* Disable RX and TX Interrupts */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+      /* Disable ADDR Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+      /* Disable Address Acknowledge */
+      hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+    
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+     /* Clear ADDR flag */
+     __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+      hsmbus->XferOptions = 0U;
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
+      HAL_SMBUS_ListenCpltCallback(hsmbus);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmbus);
+  
+  return HAL_OK;     
+}  
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) 
+{
+  uint32_t tmpisr = 0U;
+
+  if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+  {
+    /* Enable ERR interrupt */
+    tmpisr |= SMBUS_IT_ERRI;
+  }
+  
+  if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+  {
+    /* Enable ADDR, STOP interrupt */
+    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+  }
+  
+  if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+  {
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+  }
+  
+  if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+  {
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+  }
+  
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of SMBUS interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+
+  return HAL_OK;     
+}
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) 
+{
+  uint32_t tmpisr = 0U;
+
+  if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
+  {
+    /* Disable ERR interrupt */
+    tmpisr |= SMBUS_IT_ERRI;
+  }
+  
+  if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+  {
+    /* Disable TC, STOP, NACK, TXI interrupt */
+    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+    
+    if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+       && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+    
+    if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Disable STOPI, NACKI */
+      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+    }
+  }
+  
+  if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+  {
+    /* Disable TC, STOP, NACK, RXI interrupt */
+    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+    
+    if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+       && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+
+    if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Disable STOPI, NACKI */
+      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+    }
+  }
+  
+  if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+  {
+    /* Enable ADDR, STOP interrupt */
+    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+    if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) 
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+  
+  return HAL_OK;
+}
+/**
+  * @brief  Handle SMBUS Communication Timeout.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  Flag Specifies the SMBUS flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
+{  
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {    
+    while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        {
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State= HAL_SMBUS_STATE_READY;
+        
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        {
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State= HAL_SMBUS_STATE_READY;
+        
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;      
+}
+
+/**
+  * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hsmbus SMBUS handle.
+  * @param  DevAddress specifies the slave address to be programmed.
+  * @param  Size specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the SMBUS START condition generation.
+  *   This parameter can be one or a combination  of the following values:
+  *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
+  *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+  *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+  * @param  Request New state of the SMBUS START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+  uint32_t tmpreg = 0U;
+  
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+  assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+    
+  /* Get the CR2 register value */
+  tmpreg = hsmbus->Instance->CR2;
+  
+  /* clear tmpreg specific bits */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
+  
+  /* update tmpreg */
+  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
+              (uint32_t)Mode | (uint32_t)Request);
+    
+  /* update CR2 register */
+  hsmbus->Instance->CR2 = tmpreg;  
+}  
+
+/**
+  * @brief  Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to SMBUS_FIRST_FRAME                  */
+  if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition      */
+  /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
+  else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+  /* it request implicitly to generate a restart condition             */
+  /* then generate a stop condition at the end of transfer             */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
+  else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition               */
+  /* then generate a stop condition at the end of transfer               */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
+  else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h
new file mode 100755
index 0000000..9582dc5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h
@@ -0,0 +1,701 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smbus.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SMBUS HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SMBUS_H
+#define __STM32L4xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"  
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMBUS
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+  * @{
+  */ 
+  
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
+  * @brief  SMBUS Configuration Structure definition  
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
+                                     This parameter calculated by referring to SMBUS initialization 
+                                            section in Reference manual */
+  uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
+                                     This parameter can be a value of @ref SMBUS_Analog_Filter */
+    
+  uint32_t OwnAddress1;            /*!< Specifies the first device own address.
+                                     This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+                                     This parameter can be a value of @ref SMBUS_addressing_mode */
+
+  uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
+                                     This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+  uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
+                                     This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+                                     This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+  uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
+                                     This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+  uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
+                                     This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+  uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
+                                     This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+  uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
+                                     This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+  uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+  																		(Enable bits and different timeout values)
+                                     This parameter calculated by referring to SMBUS initialization 
+                                         section in Reference manual */
+} SMBUS_InitTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup HAL_state_definition HAL state definition
+  * @brief  HAL State definition  
+  * @{
+  */ 
+#define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
+#define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
+#define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */ 
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */ 
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
+#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */  
+#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */      
+#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
+/** 
+  * @}
+  */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+  * @brief  SMBUS Error Code definition  
+  * @{
+  */ 
+#define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
+#define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
+#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */   
+#define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
+#define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
+#define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
+#define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
+#define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
+/** 
+  * @}
+  */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 
+  * @brief  SMBUS handle Structure definition  
+  * @{
+  */
+typedef struct
+{
+  I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
+
+  SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
+
+  uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
+
+  uint16_t                     XferSize;        /*!< SMBUS transfer size                */
+
+  __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
+
+  __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
+
+  __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
+
+  HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
+
+  __IO uint32_t                State;           /*!< SMBUS communication state          */
+
+  __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
+
+}SMBUS_HandleTypeDef;
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+  * @{
+  */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+  * @{
+  */
+#define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
+#define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+  * @{
+  */
+#define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
+#define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+  * @{
+  */
+
+#define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
+#define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
+  * @{
+  */
+
+#define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
+#define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
+#define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
+#define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
+#define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
+#define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
+#define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
+#define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+  * @{
+  */
+#define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
+#define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_nostretch_mode  SMBUS nostretch mode
+  * @{
+  */
+#define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
+#define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+  * @{
+  */
+#define SMBUS_PEC_DISABLE                       (0x00000000U)
+#define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+  * @{
+  */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+  * @{
+  */
+
+#define  SMBUS_SOFTEND_MODE                     (0x00000000U)
+#define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
+#define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
+#define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+  * @{
+  */
+
+#define  SMBUS_NO_STARTSTOP                     (0x00000000U)
+#define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
+#define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+  * @{
+  */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
+#define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE 
+#define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
+#define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
+#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+  * @brief SMBUS Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
+#define SMBUS_IT_TCI                            I2C_CR1_TCIE
+#define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI                            I2C_CR1_RXIE
+#define SMBUS_IT_TXI                            I2C_CR1_TXIE
+#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+  * @brief Flag definition
+  *        Elements values convention: 0xXXXXYYYY
+  *           - XXXXXXXX  : Flag mask
+  * @{
+  */ 
+
+#define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
+#define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
+#define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
+#define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
+#define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
+#define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
+#define  SMBUS_FLAG_TC                          I2C_ISR_TC
+#define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
+#define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
+#define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
+#define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
+#define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
+#define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
+#define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
+#define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
+#define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+  * @{
+  */  
+  
+/** @brief  Reset SMBUS handle state.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+
+/** @brief  Enable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *   
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *   
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+ 
+/** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *   
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SMBUS flag is set or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_FLAG_TXE	    Transmit data register empty
+  *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF 	    NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_TC	    Transfer complete (master mode)
+  *            @arg @ref SMBUS_FLAG_TCR	    Transfer complete reload
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR	    Overrun/Underrun            
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
+  *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
+  *   
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define SMBUS_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+    
+/** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF 	    NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR	    Overrun/Underrun            
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *   
+  * @retval None
+  */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+ 
+/** @brief  Enable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle. 
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Disable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle. 
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the SMBUS Handle. 
+  * @retval None
+  */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+  * @}
+  */ 
+  
+  
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+  * @{
+  */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
+                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK07))  
+
+#define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
+                                                          ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
+                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
+                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
+                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
+                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+                               
+                              
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
+                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
+                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
+                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == SMBUS_FIRST_FRAME)                        || \
+                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
+                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
+                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
+                                                          IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
+                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
+#define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+  * @}
+  */ 
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+  * @{
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+  
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+    
+/* IO operation functions  *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 
+ *  @{
+ */
+
+/* Peripheral State and Errors functions  **************************************************/
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32l4xx_hal_smbus.c file */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_SMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c
new file mode 100755
index 0000000..cf49187
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c
@@ -0,0 +1,2768 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi.c
+  * @author  MCD Application Team
+  * @version V1.5.1
+  * @date    31-May-2016
+  * @brief   SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The SPI HAL driver can be used as follows:
+
+      (#) Declare a SPI_HandleTypeDef handle structure, for example:
+          SPI_HandleTypeDef  hspi;
+
+      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+          (##) Enable the SPIx interface clock
+          (##) SPI pins configuration
+              (+++) Enable the clock for the SPI GPIOs
+              (+++) Configure these SPI pins as alternate function push-pull
+          (##) NVIC configuration if you need to use interrupt process
+              (+++) Configure the SPIx interrupt priority
+              (+++) Enable the NVIC SPI IRQ handle
+          (##) DMA Configuration if you need to use DMA process
+              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+              (+++) Enable the DMAx clock
+              (+++) Configure the DMA handle parameters
+              (+++) Configure the DMA Tx or Rx channel
+              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+
+      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+              by calling the customized HAL_SPI_MspInit() API.
+     [..]
+       Circular mode restriction:
+      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+          (##) Master 2Lines RxOnly
+          (##) Master 1Line Rx
+      (#) The CRC feature is not managed when the DMA circular mode is enabled
+      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPI SPI
+  * @brief SPI HAL module driver
+  * @{
+  */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+  * @{
+  */
+#define SPI_DEFAULT_TIMEOUT 50
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+  * @{
+  */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          de-initialize the SPIx peripheral:
+
+      (+) User must implement HAL_SPI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SPI_Init() to configure the selected device with
+          the selected configuration:
+        (++) Mode
+        (++) Direction
+        (++) Data Size
+        (++) Clock Polarity and Phase
+        (++) NSS Management
+        (++) BaudRate Prescaler
+        (++) FirstBit
+        (++) TIMode
+        (++) CRC Calculation
+        (++) CRC Polynomial if CRC enabled
+        (++) CRC Length, used only with Data8 and Data16
+        (++) FIFO reception threshold
+
+      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+          of the selected SPIx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SPI according to the specified parameters
+  *         in the SPI_InitTypeDef and initialize the associated handle.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+  uint32_t frxth;
+
+  /* Check the SPI handle allocation */
+  if(hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+  assert_param(IS_SPI_MODE(hspi->Init.Mode));
+  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+  assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+  assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+  assert_param(IS_SPI_NSS(hspi->Init.NSS));
+  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+  assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+
+  if(hspi->State == HAL_SPI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hspi->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_SPI_MspInit(hspi);
+  }
+
+  hspi->State = HAL_SPI_STATE_BUSY;
+
+  /* Disable the selected SPI peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* Align by default the rs fifo threshold on the data size */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    frxth = SPI_RXFIFO_THRESHOLD_HF;
+  }
+  else
+  {
+    frxth = SPI_RXFIFO_THRESHOLD_QF;
+  }
+
+  /* CRC calculation is valid only for 16Bit and 8 Bit */
+  if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
+  {
+    /* CRC must be disabled */
+    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  }
+
+  /* Align the CRC Length on the data size */
+  if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+  {
+    /* CRC Length aligned on the data size : value set by default */
+    if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+    {
+      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+    }
+    else
+    {
+      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+    }
+  }
+
+  /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
+  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+  Communication speed, First bit, CRC calculation state, CRC Length */
+  hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
+                         hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+                         hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
+
+  if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+  {
+    hspi->Instance->CR1|= SPI_CR1_CRCL;
+  }
+
+  /* Configure : NSS management */
+  /* Configure : Rx Fifo Threshold */
+  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
+                         hspi->Init.DataSize ) | frxth;
+
+  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Configure : CRC Polynomial */
+  hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State= HAL_SPI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the SPI peripheral.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+  /* Check the SPI handle allocation */
+  if(hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+  hspi->State = HAL_SPI_STATE_BUSY;
+
+  /* Disable the SPI Peripheral Clock */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_SPI_MspDeInit(hspi);
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State = HAL_SPI_STATE_RESET;
+
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the SPI MSP.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspInit should be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the SPI MSP.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspDeInit should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of functions allowing to manage the SPI
+    data transfers.
+
+    [..] The SPI supports master and slave mode :
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode: The communication is performed using Interrupts
+           or DMA, These APIs return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+        exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if(hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->RxXferSize  = 0;
+  hspi->RxXferCount = 0;
+
+  /* Configure communication direction : 1Line */
+  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Transmit data in 16 Bit mode */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* Transmit data in 16 Bit mode */
+    while (hspi->TxXferCount > 0)
+    {
+      /* Wait until TXE flag is set to send data */
+      if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+      {
+          hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+          hspi->pTxBuffPtr += sizeof(uint16_t);
+          hspi->TxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+  /* Transmit data in 8 Bit mode */
+  else
+  {
+    while (hspi->TxXferCount > 0)
+    {
+      /* Wait until TXE flag is set to send data */
+      if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+      {
+        if(hspi->TxXferCount > 1)
+        {
+          /* write on the data register in packing mode */
+          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+          hspi->pTxBuffPtr += sizeof(uint16_t);
+          hspi->TxXferCount -= 2;
+        }
+        else
+        {
+          *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
+          hspi->TxXferCount--;
+        }
+      }
+      else
+      {
+        /* Timeout management */
+        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+
+  /* Enable CRC Transmission */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+     hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+  }
+
+  /* Check the end of the transaction */
+  if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
+  
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    errorcode = HAL_ERROR;
+  }
+
+error:
+  hspi->State = HAL_SPI_STATE_READY;
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  __IO uint16_t tmpreg;
+  uint32_t tickstart = HAL_GetTick();
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+  {
+    /* the receive process is not supported in 2Lines direction master mode */
+    /* in this case we call the TransmitReceive process                     */
+    /* Process Locked */
+    return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if(hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxXferSize  = 0;
+  hspi->TxXferCount = 0;
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+    /* this is done to handle the CRCNEXT before the latest data */
+    hspi->RxXferCount--;
+  }
+
+  /* Set the Rx Fido threshold */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* set fiforxthresold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* set fiforxthresold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+
+  /* Configure communication direction 1Line and enabled SPI if needed */
+  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    /* Transfer loop */
+    while(hspi->RxXferCount > 0)
+    {
+      /* Check the RXNE flag */
+      if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+      {
+        /* read the received data */
+        (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Transfer loop */
+    while(hspi->RxXferCount > 0)
+    {
+      /* Check the RXNE flag */
+      if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+      {
+        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+
+  /* Handle the CRC Transmission */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* freeze the CRC before the latest data */
+    hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+
+    /* Read the latest data */
+    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+    {
+      /* the latest data has not been received */
+      errorcode = HAL_TIMEOUT;
+      goto error;
+    }
+
+    /* Receive last data in 16 Bit mode */
+    if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+    {
+      *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+    }
+    /* Receive last data in 8 Bit mode */
+    else
+    {
+      *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
+    }
+
+    /* Wait until TXE flag */
+    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+    {
+      /* Flag Error*/
+      hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+      errorcode = HAL_TIMEOUT;
+      goto error;
+    }
+
+    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+    {
+      tmpreg = hspi->Instance->DR;
+      UNUSED(tmpreg); /* To avoid GCC warning */
+    }
+    else
+    {
+      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+      UNUSED(tmpreg); /* To avoid GCC warning */
+
+      if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+      {
+        if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        UNUSED(tmpreg); /* To avoid GCC warning */
+      }
+    }
+  }
+  
+  /* Check the end of the transaction */
+  if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
+
+  /* Check if CRC error occurred */
+  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+  }
+
+  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    errorcode = HAL_ERROR;
+  }
+
+error :
+  hspi->State = HAL_SPI_STATE_READY;
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in blocking mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @param  Size: amount of data to be sent and received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+__IO uint16_t tmpreg;
+  uint32_t tickstart = HAL_GetTick();
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if(hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = pRxData;
+  hspi->RxXferCount = Size;
+  hspi->RxXferSize  = Size;
+  hspi->pTxBuffPtr  = pTxData;
+  hspi->TxXferCount = Size;
+  hspi->TxXferSize  = Size;
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* Set the Rx Fido threshold */
+  if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+  {
+    /* set fiforxthreshold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* set fiforxthreshold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Transmit and Receive data in 16 Bit mode */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
+    {
+      /* Check TXE flag */
+      if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+      {
+        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint16_t);
+        hspi->TxXferCount--;
+
+        /* Enable CRC Transmission */
+        if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+        {
+          hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+        }
+      }
+
+      /* Check RXNE flag */
+      if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+      {
+        *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount--;
+      }
+      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
+      {
+        errorcode = HAL_TIMEOUT;
+        goto error;
+      }
+    }
+  }
+  /* Transmit and Receive data in 8 Bit mode */
+  else
+  {
+    while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
+    {
+      /* check TXE flag */
+      if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+      {
+        if(hspi->TxXferCount > 1)
+        {
+          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+          hspi->pTxBuffPtr += sizeof(uint16_t);
+          hspi->TxXferCount -= 2;
+        }
+        else
+        {
+          *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+          hspi->TxXferCount--;
+        }
+
+        /* Enable CRC Transmission */
+        if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+        {
+          hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+        }
+      }
+
+      /* Wait until RXNE flag is reset */
+      if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+      {
+        if(hspi->RxXferCount > 1)
+        {
+          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+          hspi->RxXferCount -= 2;
+          if(hspi->RxXferCount <= 1)
+          {
+            /* set fiforxthresold before to switch on 8 bit data size */
+            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+          }
+        }
+        else
+        {
+          (*hspi->pRxBuffPtr++) =  *(__IO uint8_t *)&hspi->Instance->DR;
+          hspi->RxXferCount--;
+        }
+      }
+      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
+      {
+        errorcode = HAL_TIMEOUT;
+        goto error;
+      }
+    }
+  }
+
+  /* Read CRC from DR to close CRC calculation process */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* Wait until TXE flag */
+    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+    {
+      /* Error on the CRC reception */
+      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+      errorcode = HAL_TIMEOUT;
+      goto error;
+    }
+
+    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+    {
+      tmpreg = hspi->Instance->DR;
+      UNUSED(tmpreg); /* To avoid GCC warning */
+    }
+    else
+    {
+      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+      UNUSED(tmpreg); /* To avoid GCC warning */
+
+      if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+      {
+        if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        UNUSED(tmpreg); /* To avoid GCC warning */
+      }
+    }
+  }
+
+  /* Check if CRC error occurred */
+  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+    /* Clear CRC Flag */
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+
+    errorcode = HAL_ERROR;
+  }
+
+  /* Check the end of the transaction */
+  if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
+
+  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    errorcode = HAL_ERROR;
+  }
+
+error :
+  hspi->State = HAL_SPI_STATE_READY;
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if((pData == NULL) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  if(hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  /* prepare the transfer */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->RxXferSize  = 0;
+  hspi->RxXferCount = 0;
+  hspi->RxISR = NULL;
+
+  /* Set the function for IT treatment */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+  {
+    hspi->TxISR = SPI_TxISR_16BIT;
+  }
+  else
+  {
+    hspi->TxISR = SPI_TxISR_8BIT;
+  }
+
+  /* Configure communication direction : 1Line */
+  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* Enable TXE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
+
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+error :
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if(hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+  if((pData == NULL) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Configure communication */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxXferSize  = 0;
+  hspi->TxXferCount = 0;
+
+  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+    /* the receive process is not supported in 2Lines direction master mode */
+    /* in this we call the TransmitReceive process          */
+    return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
+  }
+
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    hspi->CRCSize = 1;
+    if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+    {
+      hspi->CRCSize = 2;
+    }
+  }
+  else
+  {
+    hspi->CRCSize = 0;
+  }
+
+  hspi->TxISR = NULL;
+  /* check the data size to adapt Rx threshold and the set the function for IT treatment */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+  {
+    /* set fiforxthresold according the reception data length: 16 bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+    hspi->RxISR = SPI_RxISR_16BIT;
+  }
+  else
+  {
+    /* set fiforxthresold according the reception data length: 8 bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+    hspi->RxISR = SPI_RxISR_8BIT;
+  }
+
+  /* Configure communication direction : 1Line */
+  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* Enable TXE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @param  Size: amount of data to be sent and received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
+  if(!((hspi->State == HAL_SPI_STATE_READY) || \
+    ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  hspi->CRCSize = 0;
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    hspi->CRCSize = 1;
+    if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+    {
+      hspi->CRCSize = 2;
+    }
+  }
+
+  if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
+
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Set the function for IT treatment */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+  {
+    hspi->RxISR = SPI_2linesRxISR_16BIT;
+    hspi->TxISR = SPI_2linesTxISR_16BIT;
+  }
+  else
+  {
+    hspi->RxISR = SPI_2linesRxISR_8BIT;
+    hspi->TxISR = SPI_2linesTxISR_8BIT;
+  }
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* check if packing mode is enabled and if there is more than 2 data to receive */
+  if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
+  {
+    /* set fiforxthresold according the reception data length: 16 bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* set fiforxthresold according the reception data length: 8 bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+
+  /* Enable TXE, RXNE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if(hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if((pData == NULL) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->RxXferSize  = 0;
+  hspi->RxXferCount = 0;
+
+  /* Configure communication direction : 1Line */
+  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* Set the SPI TxDMA Half transfer complete callback */
+  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+  /* Set the SPI TxDMA transfer complete callback */
+  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+  /* Set the DMA error callback */
+  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+  /* packing mode is enabled only if the DMA setting is HALWORD */
+  if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+  {
+    /* Check the even/odd of the data size + crc if enabled */
+    if((hspi->TxXferCount & 0x1) == 0)
+    {
+      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+      hspi->TxXferCount = (hspi->TxXferCount >> 1);
+    }
+    else
+    {
+      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+      hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+    }
+  }
+
+  /* Enable the Tx DMA channel */
+  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @note  When the CRC feature is enabled the pData Length must be Size + 1.
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if(hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if((pData == NULL) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxXferSize  = 0;
+  hspi->TxXferCount = 0;
+
+  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+    /* the receive process is not supported in 2Lines direction master mode */
+    /* in this case we call the TransmitReceive process                     */
+    return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
+  }
+
+  /* Configure communication direction : 1Line */
+  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* packing mode management is enabled by the DMA settings */
+  if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+  {
+    /* Restriction the DMA data received is not allowed in this mode */
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+  if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* set fiforxthresold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* set fiforxthresold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+
+  /* Set the SPI RxDMA Half transfer complete callback */
+  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+  /* Set the SPI Rx DMA transfer complete callback */
+  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+  /* Enable the Rx DMA channel */
+  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+error:
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @note  When the CRC feature is enabled the pRxData Length must be Size + 1
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
+  if(!((hspi->State == HAL_SPI_STATE_READY) ||
+      ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* check if the transmit Receive function is not called by a receive master */
+  if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
+
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Reset CRC Calculation + increase the rxsize */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+
+  /* Reset the threshold bit */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+  /* the packing mode management is enabled by the DMA settings according the spi data size */
+  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* set fiforxthreshold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* set fiforxthresold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+    if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+    {
+      if((hspi->TxXferSize & 0x1) == 0x0)
+      {
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+        hspi->TxXferCount = hspi->TxXferCount >> 1;
+      }
+      else
+      {
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+        hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+      }
+    }
+
+    if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+    {
+      /* set fiforxthresold according the reception data length: 16bit */
+      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+      if((hspi->RxXferCount & 0x1) == 0x0 )
+      {
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+        hspi->RxXferCount = hspi->RxXferCount >> 1;
+      }
+      else
+      {
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+        hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
+      }
+    }
+  }
+
+  /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
+     reception request (RXNE) */
+  if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+  {
+    /* Set the SPI Rx DMA Half transfer complete callback */
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+    hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+  }
+  else
+  {
+    /* Set the SPI Rx DMA Half transfer complete callback */
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+    hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+  }
+
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+  /* Enable the Rx DMA channel */
+  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
+
+  /* Set the SPI DMA Tx Abort Complete callback to Null : Tx DMA will be aborted 
+     at end of Rx transfer (when Rx DMA Transfer Complete callback will be executed) */
+  hspi->hdmatx->XferAbortCallback    = NULL;
+  hspi->hdmatx->XferHalfCpltCallback = NULL;
+  hspi->hdmatx->XferCpltCallback     = NULL;
+  hspi->hdmatx->XferErrorCallback    = NULL;
+
+  /* Enable the Tx DMA channel */
+  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+  /* Check if the SPI is already enabled */
+  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Disable the SPI DMA Tx & Rx requests */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Enable the SPI DMA Tx & Rx requests */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+     */
+
+  /* Abort the SPI DMA tx channel */
+  if(hspi->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(hspi->hdmatx);
+  }
+  /* Abort the SPI DMA rx channel */
+  if(hspi->hdmarx != NULL)
+  {
+    HAL_DMA_Abort(hspi->hdmarx);
+  }
+
+  /* Disable the SPI DMA Tx & Rx requests */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+  hspi->State = HAL_SPI_STATE_READY;
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SPI interrupt request.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval None
+  */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+  uint32_t itsource = hspi->Instance->CR2;
+  uint32_t itflag   = hspi->Instance->SR;
+
+  /* SPI in mode Receiver ----------------------------------------------------*/
+  if(((itflag & SPI_FLAG_OVR) == RESET) &&
+     ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+  {
+    hspi->RxISR(hspi);
+    return;
+  }
+
+  /* SPI in mode Transmitter ---------------------------------------------------*/
+  if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+  {
+    hspi->TxISR(hspi);
+    return;
+  }
+
+  /* SPI in Error Treatment ---------------------------------------------------*/
+  if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+  {
+    /* SPI Overrun error interrupt occurred -------------------------------------*/
+    if((itflag & SPI_FLAG_OVR) != RESET)
+    {
+      if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+      {
+        hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);
+      }
+      else
+      {
+        return;
+      }
+    }
+
+    /* SPI Mode Fault error interrupt occurred -------------------------------------*/
+    if((itflag & SPI_FLAG_MODF) != RESET)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+      __HAL_SPI_CLEAR_MODFFLAG(hspi);
+    }
+
+    /* SPI Frame error interrupt occurred ----------------------------------------*/
+    if((itflag & SPI_FLAG_FRE) != RESET)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+      __HAL_SPI_CLEAR_FREFLAG(hspi);
+    }
+
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+    hspi->State = HAL_SPI_STATE_READY;
+    HAL_SPI_ErrorCallback(hspi);
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx Half Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Half Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Half Transfer callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief SPI error callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_ErrorCallback should be implemented in the user file
+   */
+  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+            and user can use HAL_SPI_GetError() API to check the latest error occurred
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   SPI control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SPI.
+     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SPI handle state.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI state
+  */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+  /* Return SPI handle state */
+  return hspi->State;
+}
+
+/**
+  * @brief  Return the SPI error code.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI error code in bitmap format
+  */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+  return hspi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Private_Functions
+ *  @brief   Private functions
+  * @{
+  */
+
+/**
+  * @brief DMA SPI transmit process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+  {
+    /* Disable Tx DMA Request */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+    /* Check the end of the transaction */
+    if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+    {
+      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+    }
+
+    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+    {
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    }
+
+    hspi->TxXferCount = 0;
+    hspi->State = HAL_SPI_STATE_READY;
+
+    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      HAL_SPI_ErrorCallback(hspi);
+      return;
+    }
+  }
+  HAL_SPI_TxCpltCallback(hspi);
+}
+
+/**
+  * @brief DMA SPI receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+  {
+    __IO uint16_t tmpreg;
+
+    /* CRC handling */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Wait until TXE flag */
+      if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+      {
+        /* Error on the CRC reception */
+        hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+      }
+      if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+      {
+        tmpreg = hspi->Instance->DR;
+        UNUSED(tmpreg); /* To avoid GCC warning */
+      }
+      else
+      {
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        UNUSED(tmpreg); /* To avoid GCC warning */
+
+        if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+        {
+          if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+          {
+            /* Error on the CRC reception */
+            hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+          }
+          tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+          UNUSED(tmpreg); /* To avoid GCC warning */
+        }
+      }
+    }
+
+    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+    /* Check the end of the transaction */
+    if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+    {
+      hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+    }
+
+    hspi->RxXferCount = 0;
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Check if CRC error occurred */
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+    {
+      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    }
+
+    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      HAL_SPI_ErrorCallback(hspi);
+      return;
+    }
+  }
+  HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+  * @brief DMA SPI transmit receive process complete callback.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+  {
+    __IO int16_t tmpreg;
+    /* CRC handling */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+      {
+        if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+        }
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        UNUSED(tmpreg); /* To avoid GCC warning */  
+      }
+      else
+      {
+        if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+        }
+        tmpreg = hspi->Instance->DR;
+        UNUSED(tmpreg); /* To avoid GCC warning */  
+      }
+    }
+
+    /* Check the end of the transaction */
+    if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+    {
+      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+    }
+  
+    /* Disable Rx/Tx DMA Request */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+    hspi->TxXferCount = 0;
+    hspi->RxXferCount = 0;
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Check if CRC error occurred */
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+    {
+      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    }
+
+    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      HAL_SPI_ErrorCallback(hspi);
+      return;
+    }
+  }
+  HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+  * @brief DMA SPI half transmit process complete callback.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+  * @brief DMA SPI half receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+  * @brief DMA SPI half transmit receive process complete callback.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+  * @brief DMA SPI communication error callback.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Stop the disable DMA transfer on SPI side */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+  hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
+  hspi->State = HAL_SPI_STATE_READY;
+  HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in packing mode */
+  if(hspi->RxXferCount > 1)
+  {
+    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+    hspi->pRxBuffPtr += sizeof(uint16_t);
+    hspi->RxXferCount -= 2;
+    if(hspi->RxXferCount == 1) 
+    {
+      /* set fiforxthresold according the reception data length: 8bit */
+      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+    }
+  }
+  /* Receive data in 8 Bit mode */
+  else
+  {
+    *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+    hspi->RxXferCount--;
+  }
+
+  /* check end of the reception */
+  if(hspi->RxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
+      return;
+    }
+
+    /* Disable RXNE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+    if(hspi->TxXferCount == 0)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+  UNUSED(tmpreg); /* To avoid GCC warning */
+
+  hspi->CRCSize--;
+
+  /* check end of the reception */
+  if(hspi->CRCSize == 0)
+  {
+    /* Disable RXNE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+    if(hspi->TxXferCount == 0)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in packing Bit mode */
+  if(hspi->TxXferCount >= 2)
+  {
+    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+    hspi->pTxBuffPtr += sizeof(uint16_t);
+    hspi->TxXferCount -= 2;
+  }
+  /* Transmit data in 8 Bit mode */
+  else
+  {
+    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+    hspi->TxXferCount--;
+  }
+
+  /* check the end of the transmission */
+  if(hspi->TxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+    }
+    /* Disable TXE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+    if(hspi->RxXferCount == 0)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 16 Bit mode */
+  *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+  hspi->pRxBuffPtr += sizeof(uint16_t);
+  hspi->RxXferCount--;
+
+  if(hspi->RxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
+      return;
+    }
+
+    /* Disable RXNE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+    if(hspi->TxXferCount == 0)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 16 Bit mode */
+  __IO uint16_t tmpreg = hspi->Instance->DR;
+  UNUSED(tmpreg); /* To avoid GCC warning */
+
+  /* Disable RXNE interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+  SPI_CloseRxTx_ISR(hspi);
+}
+
+/**
+  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 16 Bit mode */
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint16_t);
+  hspi->TxXferCount--;
+
+  /* Enable CRC Transmission */
+  if(hspi->TxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+    }
+    /* Disable TXE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+    if(hspi->RxXferCount == 0)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Manage the CRC 8-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR);
+  UNUSED(tmpreg); /* To avoid GCC warning */
+
+  hspi->CRCSize--;
+
+  if(hspi->CRCSize == 0)
+  {
+    SPI_CloseRx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief  Manage the receive 8-bit in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+  hspi->RxXferCount--;
+
+  /* Enable CRC Transmission */
+  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+  {
+    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+  }
+
+  if(hspi->RxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR =  SPI_RxISR_8BITCRC;
+      return;
+    }
+    SPI_CloseRx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief  Manage the CRC 16-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  __IO uint16_t tmpreg;
+
+  tmpreg = hspi->Instance->DR;
+  UNUSED(tmpreg); /* To avoid GCC warning */
+
+  /* Disable RXNE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+  SPI_CloseRx_ISR(hspi);
+}
+
+/**
+  * @brief  Manage the 16-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+  hspi->pRxBuffPtr += sizeof(uint16_t);
+  hspi->RxXferCount--;
+
+  /* Enable CRC Transmission */
+  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+  {
+    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+  }
+
+  if(hspi->RxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR = SPI_RxISR_16BITCRC;
+      return;
+    }
+    SPI_CloseRx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief  Handle the data 8-bit transmit in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+  hspi->TxXferCount--;
+
+  if(hspi->TxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Enable CRC Transmission */
+      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+    }
+
+    SPI_CloseTx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief  Handle the data 16-bit transmit in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 16 Bit mode */
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint16_t);
+  hspi->TxXferCount--;
+
+  if(hspi->TxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Enable CRC Transmission */
+      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+    }
+    SPI_CloseTx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief Handle SPI Communication Timeout.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param Flag : SPI flag to check
+  * @param State : flag state to check
+  * @param Timeout : Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  while((hspi->Instance->SR & Flag) != State)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+      {
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared
+        on both master and slave sides in order to resynchronize the master
+        and slave for their respective CRC calculation */
+
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+        {
+          /* Disable SPI peripheral */
+          __HAL_SPI_DISABLE(hspi);
+        }
+
+        /* Reset CRC Calculation */
+        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+        {
+          SPI_RESET_CRC(hspi);
+        }
+
+        hspi->State= HAL_SPI_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle SPI FIFO Communication Timeout.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param Fifo : Fifo to check
+  * @param State : Fifo state to check
+  * @param Timeout : Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
+{
+  __IO uint8_t tmpreg;
+  uint32_t tickstart = HAL_GetTick();
+
+  while((hspi->Instance->SR & Fifo) != State)
+  {
+    if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+    {
+      tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+      UNUSED(tmpreg); /* To avoid GCC warning */
+    }
+
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+      {
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared
+                  on both master and slave sides in order to resynchronize the master
+                 and slave for their respective CRC calculation */
+
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+        {
+          /* Disable SPI peripheral */
+          __HAL_SPI_DISABLE(hspi);
+        }
+
+        /* Reset CRC Calculation */
+        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+        {
+          SPI_RESET_CRC(hspi);
+        }
+
+        hspi->State = HAL_SPI_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle the check of the RX transaction complete.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param Timeout : Timeout duration
+  * @retval None
+  */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout)
+{
+  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+  {
+    /* Disable SPI peripheral */
+    __HAL_SPI_DISABLE(hspi);
+  }
+  
+  /* Control the BSY flag */
+  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    return HAL_TIMEOUT;
+  }
+
+  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+  {
+    /* Empty the FRLVL fifo */
+    if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle the check of the RXTX or TX transaction complete.
+  * @param hspi: SPI handle
+  * @param Timeout : Timeout duration
+  */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+{
+  /* Control if the TX fifo is empty */
+  if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    return HAL_TIMEOUT;
+  }
+  /* Control the BSY flag */
+  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    return HAL_TIMEOUT;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle the end of the RXTX transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  /* Disable ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+  /* Check the end of the transaction */
+  if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+  {
+    hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+  }
+
+  /* Check if CRC error occurred */
+  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    hspi->State = HAL_SPI_STATE_READY;
+    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+    if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+    {
+      if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+      {
+      	hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_RxCpltCallback(hspi);
+      }
+      else
+      {
+      	hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_TxRxCpltCallback(hspi);
+      }
+    }
+    else
+    {
+      hspi->State = HAL_SPI_STATE_READY;
+      HAL_SPI_ErrorCallback(hspi);
+    }
+  }
+}
+
+/**
+  * @brief Handle the end of the RX transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+    /* Disable RXNE and ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+    /* Check the end of the transaction */
+    if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+    {
+      hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+    }
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Check if CRC error occurred */
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+    {
+      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+      HAL_SPI_ErrorCallback(hspi);
+    }
+    else
+    {
+      if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+      {
+        HAL_SPI_RxCpltCallback(hspi);
+      }
+      else
+      {
+        HAL_SPI_ErrorCallback(hspi);
+      }
+    }
+}
+
+/**
+  * @brief Handle the end of the TX transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  /* Disable TXE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+  /* Check the end of the transaction */
+  if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+  {
+    hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+  }
+
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+  hspi->State = HAL_SPI_STATE_READY;
+  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+    HAL_SPI_TxCpltCallback(hspi);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c.old b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c.old
new file mode 100755
index 0000000..95068ef
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c.old
@@ -0,0 +1,3850 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The SPI HAL driver can be used as follows:
+
+      (#) Declare a SPI_HandleTypeDef handle structure, for example:
+          SPI_HandleTypeDef  hspi;
+
+      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+          (##) Enable the SPIx interface clock
+          (##) SPI pins configuration
+              (+++) Enable the clock for the SPI GPIOs
+              (+++) Configure these SPI pins as alternate function push-pull
+          (##) NVIC configuration if you need to use interrupt process
+              (+++) Configure the SPIx interrupt priority
+              (+++) Enable the NVIC SPI IRQ handle
+          (##) DMA Configuration if you need to use DMA process
+              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
+              (+++) Enable the DMAx clock
+              (+++) Configure the DMA handle parameters
+              (+++) Configure the DMA Tx or Rx Stream/Channel
+              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+
+      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+              by calling the customized HAL_SPI_MspInit() API.
+     [..]
+       Circular mode restriction:
+      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+          (##) Master 2Lines RxOnly
+          (##) Master 1Line Rx
+      (#) The CRC feature is not managed when the DMA circular mode is enabled
+      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+     [..]
+       Master Receive mode restriction:
+      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+          does not initiate a new transfer the following procedure has to be respected:
+          (##) HAL_SPI_DeInit()
+          (##) HAL_SPI_Init()
+     [..]
+       The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
+       modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
+       maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
+       the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
+     
+
+  @endverbatim
+
+  Additional table :
+
+       DataSize = SPI_DATASIZE_8BIT:
+       +----------------------------------------------------------------------------------------------+
+       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
+       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
+       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
+       |==============================================================================================|
+       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
+       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
+       +----------------------------------------------------------------------------------------------+
+
+       DataSize = SPI_DATASIZE_16BIT:
+       +----------------------------------------------------------------------------------------------+
+       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
+       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
+       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
+       |==============================================================================================|
+       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
+       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
+       +----------------------------------------------------------------------------------------------+
+       @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+       @note
+            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPI SPI
+  * @brief SPI HAL module driver
+  * @{
+  */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+  * @{
+  */
+#define SPI_DEFAULT_TIMEOUT 100U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+  * @{
+  */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+                                                       uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+                                                       uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          de-initialize the SPIx peripheral:
+
+      (+) User must implement HAL_SPI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SPI_Init() to configure the selected device with
+          the selected configuration:
+        (++) Mode
+        (++) Direction
+        (++) Data Size
+        (++) Clock Polarity and Phase
+        (++) NSS Management
+        (++) BaudRate Prescaler
+        (++) FirstBit
+        (++) TIMode
+        (++) CRC Calculation
+        (++) CRC Polynomial if CRC enabled
+        (++) CRC Length, used only with Data8 and Data16
+        (++) FIFO reception threshold
+
+      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+          of the selected SPIx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SPI according to the specified parameters
+  *         in the SPI_InitTypeDef and initialize the associated handle.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+  uint32_t frxth;
+
+  /* Check the SPI handle allocation */
+  if (hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+  assert_param(IS_SPI_MODE(hspi->Init.Mode));
+  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+  assert_param(IS_SPI_NSS(hspi->Init.NSS));
+  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+  {
+    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+  }
+#if (USE_SPI_CRC != 0U)
+  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+  }
+#else
+  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+  if (hspi->State == HAL_SPI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hspi->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_SPI_MspInit(hspi);
+  }
+
+  hspi->State = HAL_SPI_STATE_BUSY;
+
+  /* Disable the selected SPI peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* Align by default the rs fifo threshold on the data size */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    frxth = SPI_RXFIFO_THRESHOLD_HF;
+  }
+  else
+  {
+    frxth = SPI_RXFIFO_THRESHOLD_QF;
+  }
+
+  /* CRC calculation is valid only for 16Bit and 8 Bit */
+  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
+  {
+    /* CRC must be disabled */
+    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  }
+
+  /* Align the CRC Length on the data size */
+  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+  {
+    /* CRC Length aligned on the data size : value set by default */
+    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+    {
+      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+    }
+    else
+    {
+      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+    }
+  }
+
+  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+  Communication speed, First bit and CRC calculation state */
+  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
+                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));
+#if (USE_SPI_CRC != 0U)
+  /* Configure : CRC Length */
+  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+  {
+    hspi->Instance->CR1 |= SPI_CR1_CRCL;
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
+  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
+                                  hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
+
+#if (USE_SPI_CRC != 0U)
+  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+  /* Configure : CRC Polynomial */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+  }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State     = HAL_SPI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initialize the SPI peripheral.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+  /* Check the SPI handle allocation */
+  if (hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check SPI Instance parameter */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+  hspi->State = HAL_SPI_STATE_BUSY;
+
+  /* Disable the SPI Peripheral Clock */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_SPI_MspDeInit(hspi);
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State = HAL_SPI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SPI MSP.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspInit should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize the SPI MSP.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspDeInit should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of functions allowing to manage the SPI
+    data transfers.
+
+    [..] The SPI supports master and slave mode :
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode: The communication is performed using Interrupts
+            or DMA, These APIs return the HAL status.
+            The end of the data processing will be indicated through the
+            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+            will be executed respectively at the end of the transmit or Receive process
+            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+        exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->RxXferSize  = 0U;
+  hspi->RxXferCount = 0U;
+  hspi->TxISR       = NULL;
+  hspi->RxISR       = NULL;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Transmit data in 16 Bit mode */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+    {
+      hspi->Instance->DR = *((uint16_t *)pData);
+      pData += sizeof(uint16_t);
+      hspi->TxXferCount--;
+    }
+    /* Transmit data in 16 Bit mode */
+    while (hspi->TxXferCount > 0U)
+    {
+      /* Wait until TXE flag is set to send data */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+      {
+        hspi->Instance->DR = *((uint16_t *)pData);
+        pData += sizeof(uint16_t);
+        hspi->TxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+  /* Transmit data in 8 Bit mode */
+  else
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+    {
+      if (hspi->TxXferCount > 1U)
+      {
+        /* write on the data register in packing mode */
+        hspi->Instance->DR = *((uint16_t *)pData);
+        pData += sizeof(uint16_t);
+        hspi->TxXferCount -= 2U;
+      }
+      else
+      {
+        *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+        hspi->TxXferCount--;
+      }
+    }
+    while (hspi->TxXferCount > 0U)
+    {
+      /* Wait until TXE flag is set to send data */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+      {
+        if (hspi->TxXferCount > 1U)
+        {
+          /* write on the data register in packing mode */
+          hspi->Instance->DR = *((uint16_t *)pData);
+          pData += sizeof(uint16_t);
+          hspi->TxXferCount -= 2U;
+        }
+        else
+        {
+          *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+          hspi->TxXferCount--;
+        }
+      }
+      else
+      {
+        /* Timeout management */
+        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+#if (USE_SPI_CRC != 0U)
+  /* Enable CRC Transmission */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
+
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+      __HAL_SPI_DISABLE(hspi);
+  }
+
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    errorcode = HAL_ERROR;
+  }
+
+error:
+  hspi->State = HAL_SPI_STATE_READY;
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if (USE_SPI_CRC != 0U)
+  __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+  uint32_t tickstart = 0U;
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_RX;
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxXferSize  = 0U;
+  hspi->TxXferCount = 0U;
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+    /* this is done to handle the CRCNEXT before the latest data */
+    hspi->RxXferCount--;
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Set the Rx Fifo threshold */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* set fiforxthresold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* set fiforxthresold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+
+  /* Configure communication direction: 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Receive data in 8 Bit mode */
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    /* Transfer loop */
+    while (hspi->RxXferCount > 0U)
+    {
+      /* Check the RXNE flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+      {
+        /* read the received data */
+        (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+        pData += sizeof(uint8_t);
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Transfer loop */
+    while (hspi->RxXferCount > 0U)
+    {
+      /* Check the RXNE flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+      {
+        *((uint16_t *)pData) = hspi->Instance->DR;
+        pData += sizeof(uint16_t);
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+      }
+    }
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Handle the CRC Transmission */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* freeze the CRC before the latest data */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+
+    /* Read the latest data */
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* the latest data has not been received */
+      errorcode = HAL_TIMEOUT;
+      goto error;
+    }
+
+    /* Receive last data in 16 Bit mode */
+    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+    {
+      *((uint16_t *)pData) = hspi->Instance->DR;
+    }
+    /* Receive last data in 8 Bit mode */
+    else
+    {
+      (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+    }
+
+    /* Wait the CRC data */
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      errorcode = HAL_TIMEOUT;
+      goto error;
+    }
+
+    /* Read CRC to Flush DR and RXNE flag */
+    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+    {
+      tmpreg = hspi->Instance->DR;
+      /* To avoid GCC warning */
+      UNUSED(tmpreg);
+    }
+    else
+    {
+      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+      /* To avoid GCC warning */
+      UNUSED(tmpreg);
+
+      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+      {
+        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        /* To avoid GCC warning */
+        UNUSED(tmpreg);
+      }
+    }
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    errorcode = HAL_ERROR;
+  }
+
+error :
+  hspi->State = HAL_SPI_STATE_READY;
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in blocking mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @param  Size: amount of data to be sent and received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+                                          uint32_t Timeout)
+{
+  uint32_t tmp = 0U, tmp1 = 0U;
+#if (USE_SPI_CRC != 0U)
+  __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+  uint32_t tickstart = 0U;
+  /* Variable used to alternate Rx and Tx during transfer */
+  uint32_t txallowed = 1U;
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  tmp  = hspi->State;
+  tmp1 = hspi->Init.Mode;
+
+  if (!((tmp == HAL_SPI_STATE_READY) || \
+        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
+
+  /* Set the transaction information */
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferCount = Size;
+  hspi->RxXferSize  = Size;
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->TxXferCount = Size;
+  hspi->TxXferSize  = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Set the Rx Fifo threshold */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
+  {
+    /* set fiforxthreshold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* set fiforxthreshold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Transmit and Receive data in 16 Bit mode */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+    {
+      hspi->Instance->DR = *((uint16_t *)pTxData);
+      pTxData += sizeof(uint16_t);
+      hspi->TxXferCount--;
+    }
+    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+    {
+      /* Check TXE flag */
+      if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+      {
+        hspi->Instance->DR = *((uint16_t *)pTxData);
+        pTxData += sizeof(uint16_t);
+        hspi->TxXferCount--;
+        /* Next Data is a reception (Rx). Tx not allowed */
+        txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+        /* Enable CRC Transmission */
+        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+        {
+          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+          if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+          {
+            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+          }
+          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+        }
+#endif /* USE_SPI_CRC */
+      }
+
+      /* Check RXNE flag */
+      if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+      {
+        *((uint16_t *)pRxData) = hspi->Instance->DR;
+        pRxData += sizeof(uint16_t);
+        hspi->RxXferCount--;
+        /* Next Data is a Transmission (Tx). Tx is allowed */
+        txallowed = 1U;
+      }
+      if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
+      {
+        errorcode = HAL_TIMEOUT;
+        goto error;
+      }
+    }
+  }
+  /* Transmit and Receive data in 8 Bit mode */
+  else
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+    {
+      if (hspi->TxXferCount > 1U)
+      {
+        hspi->Instance->DR = *((uint16_t *)pTxData);
+        pTxData += sizeof(uint16_t);
+        hspi->TxXferCount -= 2U;
+      }
+      else
+      {
+        *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+        hspi->TxXferCount--;
+      }
+    }
+    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+    {
+      /* check TXE flag */
+      if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+      {
+        if (hspi->TxXferCount > 1U)
+        {
+          hspi->Instance->DR = *((uint16_t *)pTxData);
+          pTxData += sizeof(uint16_t);
+          hspi->TxXferCount -= 2U;
+        }
+        else
+        {
+          *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+          hspi->TxXferCount--;
+        }
+        /* Next Data is a reception (Rx). Tx not allowed */
+        txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+        /* Enable CRC Transmission */
+        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+        {
+          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+          if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+          {
+            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+          }
+          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+        }
+#endif /* USE_SPI_CRC */
+      }
+
+      /* Wait until RXNE flag is reset */
+      if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+      {
+        if (hspi->RxXferCount > 1U)
+        {
+          *((uint16_t *)pRxData) = hspi->Instance->DR;
+          pRxData += sizeof(uint16_t);
+          hspi->RxXferCount -= 2U;
+          if (hspi->RxXferCount <= 1U)
+          {
+            /* set fiforxthresold before to switch on 8 bit data size */
+            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+          }
+        }
+        else
+        {
+          (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
+          hspi->RxXferCount--;
+        }
+        /* Next Data is a Transmission (Tx). Tx is allowed */
+        txallowed = 1U;
+      }
+      if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))
+      {
+        errorcode = HAL_TIMEOUT;
+        goto error;
+      }
+    }
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Read CRC from DR to close CRC calculation process */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* Wait until TXE flag */
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Error on the CRC reception */
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      errorcode = HAL_TIMEOUT;
+      goto error;
+    }
+    /* Read CRC */
+    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+    {
+      tmpreg = hspi->Instance->DR;
+      /* To avoid GCC warning */
+      UNUSED(tmpreg);
+    }
+    else
+    {
+      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+      /* To avoid GCC warning */
+      UNUSED(tmpreg);
+
+      if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+      {
+        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        /* To avoid GCC warning */
+        UNUSED(tmpreg);
+      }
+    }
+  }
+
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    /* Clear CRC Flag */
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+
+    errorcode = HAL_ERROR;
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    errorcode = HAL_ERROR;
+  }
+
+error :
+  hspi->State = HAL_SPI_STATE_READY;
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->RxXferSize  = 0U;
+  hspi->RxXferCount = 0U;
+  hspi->RxISR       = NULL;
+
+  /* Set the function for IT treatment */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->TxISR = SPI_TxISR_16BIT;
+  }
+  else
+  {
+    hspi->TxISR = SPI_TxISR_8BIT;
+  }
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Enable TXE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+error :
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+
+  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_RX;
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxXferSize  = 0U;
+  hspi->TxXferCount = 0U;
+  hspi->TxISR       = NULL;
+
+  /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* Set fiforxthresold according the reception data length: 16 bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+    hspi->RxISR = SPI_RxISR_16BIT;
+  }
+  else
+  {
+    /* Set fiforxthresold according the reception data length: 8 bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+    hspi->RxISR = SPI_RxISR_8BIT;
+  }
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    hspi->CRCSize = 1U;
+    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+    {
+      hspi->CRCSize = 2U;
+    }
+    SPI_RESET_CRC(hspi);
+  }
+  else
+  {
+    hspi->CRCSize = 0U;
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Enable TXE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+  /* Note : The SPI must be enabled after unlocking current process
+            to avoid the risk of SPI interrupt handle execution before current
+            process unlock */
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @param  Size: amount of data to be sent and received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t tmp = 0U, tmp1 = 0U;
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
+  tmp  = hspi->State;
+  tmp1 = hspi->Init.Mode;
+
+  if (!((tmp == HAL_SPI_STATE_READY) || \
+        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
+
+  /* Set the transaction information */
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Set the function for IT treatment */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->RxISR     = SPI_2linesRxISR_16BIT;
+    hspi->TxISR     = SPI_2linesTxISR_16BIT;
+  }
+  else
+  {
+    hspi->RxISR     = SPI_2linesRxISR_8BIT;
+    hspi->TxISR     = SPI_2linesTxISR_8BIT;
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    hspi->CRCSize = 1U;
+    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+    {
+      hspi->CRCSize = 2U;
+    }
+    SPI_RESET_CRC(hspi);
+  }
+  else
+  {
+    hspi->CRCSize = 0U;
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Check if packing mode is enabled and if there is more than 2 data to receive */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
+  {
+    /* Set fiforxthresold according the reception data length: 16 bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* Set fiforxthresold according the reception data length: 8 bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+
+  /* Enable TXE, RXNE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+  /* check tx dma handle */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxISR       = NULL;
+  hspi->RxISR       = NULL;
+  hspi->RxXferSize  = 0U;
+  hspi->RxXferCount = 0U;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Set the SPI TxDMA Half transfer complete callback */
+  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+  /* Set the SPI TxDMA transfer complete callback */
+  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+  /* Set the DMA error callback */
+  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmatx->XferAbortCallback = NULL;
+
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+  /* Packing mode is enabled only if the DMA setting is HALWORD */
+  if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+  {
+    /* Check the even/odd of the data size + crc if enabled */
+    if ((hspi->TxXferCount & 0x1U) == 0U)
+    {
+      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+      hspi->TxXferCount = (hspi->TxXferCount >> 1U);
+    }
+    else
+    {
+      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+      hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+    }
+  }
+
+  /* Enable the Tx DMA Stream/Channel */
+  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+  /* check rx dma handle */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
+  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_RX;
+    
+    /* check tx dma handle */
+    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+  hspi->TxXferSize  = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* Set fiforxthresold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* Set fiforxthresold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+    {
+      /* set fiforxthresold according the reception data length: 16bit */
+      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+      if ((hspi->RxXferCount & 0x1U) == 0x0U)
+      {
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+        hspi->RxXferCount = hspi->RxXferCount >> 1U;
+      }
+      else
+      {
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+      }
+    }
+  }
+
+  /* Set the SPI RxDMA Half transfer complete callback */
+  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+  /* Set the SPI Rx DMA transfer complete callback */
+  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  /* Enable the Rx DMA Stream/Channel  */
+  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+error:
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size)
+{
+  uint32_t tmp = 0U, tmp1 = 0U;
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  
+  /* check rx & tx dma handles */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
+  tmp  = hspi->State;
+  tmp1 = hspi->Init.Mode;
+  if (!((tmp == HAL_SPI_STATE_READY) ||
+        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
+
+  /* Set the transaction information */
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+
+
+  /* Reset the threshold bit */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+  /* The packing mode management is enabled by the DMA settings according the spi data size */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* Set fiforxthreshold according the reception data length: 16bit */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+  }
+  else
+  {
+    /* Set fiforxthresold according the reception data length: 8bit */
+    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+    if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+    {
+      if ((hspi->TxXferSize & 0x1U) == 0x0U)
+      {
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+        hspi->TxXferCount = hspi->TxXferCount >> 1U;
+      }
+      else
+      {
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+        hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+      }
+    }
+
+    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+    {
+      /* Set fiforxthresold according the reception data length: 16bit */
+      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+      if ((hspi->RxXferCount & 0x1U) == 0x0U)
+      {
+        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+        hspi->RxXferCount = hspi->RxXferCount >> 1U;
+      }
+      else
+      {
+        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+      }
+    }
+  }
+
+  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+  {
+    /* Set the SPI Rx DMA Half transfer complete callback */
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
+  }
+  else
+  {
+    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
+  }
+
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  /* Enable the Rx DMA Stream/Channel  */
+  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+  is performed in DMA reception complete callback  */
+  hspi->hdmatx->XferHalfCpltCallback = NULL;
+  hspi->hdmatx->XferCpltCallback     = NULL;
+  hspi->hdmatx->XferErrorCallback    = NULL;
+  hspi->hdmatx->XferAbortCallback    = NULL;
+
+  /* Enable the Tx DMA Stream/Channel  */
+  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Abort ongoing transfer (blocking mode).
+  * @param  hspi SPI handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+  *         started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SPI Interrupts (depending of transfer direction)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+  HAL_StatusTypeDef errorcode;
+  __IO uint32_t count, resetcount;
+
+  /* Initialized local variable  */
+  errorcode = HAL_OK;
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+  count = resetcount;
+
+  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+  {
+    hspi->TxISR = SPI_AbortTx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
+    {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
+
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+  {
+    hspi->RxISR = SPI_AbortRx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
+    {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
+
+  /* Clear ERRIE interrupts in case of DMA Mode */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+  /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
+  if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+  {
+    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+    if (hspi->hdmatx != NULL)
+    {
+      /* Set the SPI DMA Abort callback :
+      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+      hspi->hdmatx->XferAbortCallback = NULL;
+
+      /* Abort DMA Tx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+
+      /* Disable Tx DMA Request */
+      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+      if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+
+      /* Disable SPI Peripheral */
+      __HAL_SPI_DISABLE(hspi);
+
+      /* Empty the FRLVL fifo */
+      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+    }
+    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+    if (hspi->hdmarx != NULL)
+    {
+      /* Set the SPI DMA Abort callback :
+      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+      hspi->hdmarx->XferAbortCallback = NULL;
+
+      /* Abort DMA Rx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+
+      /* Disable peripheral */
+      __HAL_SPI_DISABLE(hspi);
+
+      /* Control the BSY flag */
+      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+
+      /* Empty the FRLVL fifo */
+      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+
+      /* Disable Rx DMA Request */
+      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+    }
+  }
+  /* Reset Tx and Rx transfer counters */
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Check error during Abort procedure */
+  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+  {
+    /* return HAL_Error in case of error during Abort procedure */
+    errorcode = HAL_ERROR;
+  }
+  else
+  {
+    /* Reset errorCode */
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  }
+
+  /* Clear the Error flags in the SR register */
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+  /* Restore hspi->state to ready */
+  hspi->State = HAL_SPI_STATE_READY;
+
+  return errorcode;
+}
+
+/**
+  * @brief  Abort ongoing transfer (Interrupt mode).
+  * @param  hspi SPI handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+  *         started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SPI Interrupts (depending of transfer direction)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+  HAL_StatusTypeDef errorcode;
+  uint32_t abortcplt ;
+  __IO uint32_t count, resetcount;
+
+  /* Initialized local variable  */
+  errorcode = HAL_OK;
+  abortcplt = 1U;
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+  count = resetcount;
+
+  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+  {
+    hspi->TxISR = SPI_AbortTx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
+    {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
+
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+  {
+    hspi->RxISR = SPI_AbortRx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
+    {
+      if (count-- == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    }
+    while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
+
+  /* Clear ERRIE interrupts in case of DMA Mode */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (hspi->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+    {
+      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+    }
+    else
+    {
+      hspi->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (hspi->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+    {
+      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+    }
+    else
+    {
+      hspi->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+  if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+  {
+    /* Abort the SPI DMA Tx Stream/Channel */
+    if (hspi->hdmatx != NULL)
+    {
+      /* Abort DMA Tx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+      {
+        hspi->hdmatx->XferAbortCallback = NULL;
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+    /* Abort the SPI DMA Rx Stream/Channel */
+    if (hspi->hdmarx != NULL)
+    {
+      /* Abort DMA Rx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
+      {
+        hspi->hdmarx->XferAbortCallback = NULL;
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+  {
+    /* Abort the SPI DMA Tx Stream/Channel */
+    if (hspi->hdmatx != NULL)
+    {
+      /* Abort DMA Tx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+      {
+        hspi->hdmatx->XferAbortCallback = NULL;
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+  {
+    /* Abort the SPI DMA Rx Stream/Channel */
+    if (hspi->hdmarx != NULL)
+    {
+      /* Abort DMA Rx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
+      {
+        hspi->hdmarx->XferAbortCallback = NULL;
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hspi->RxXferCount = 0U;
+    hspi->TxXferCount = 0U;
+
+    /* Check error during Abort procedure */
+    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+    {
+      /* return HAL_Error in case of error during Abort procedure */
+      errorcode = HAL_ERROR;
+    }
+    else
+    {
+      /* Reset errorCode */
+      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+    }
+
+    /* Clear the Error flags in the SR register */
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+    /* Restore hspi->State to Ready */
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SPI_AbortCpltCallback(hspi);
+  }
+
+  return errorcode;
+}
+
+/**
+  * @brief  Pause the DMA Transfer.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Disable the SPI DMA Tx & Rx requests */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA Transfer.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Enable the SPI DMA Tx & Rx requests */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+     */
+
+  /* Abort the SPI DMA tx Stream/Channel  */
+  if (hspi->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(hspi->hdmatx);
+  }
+  /* Abort the SPI DMA rx Stream/Channel  */
+  if (hspi->hdmarx != NULL)
+  {
+    HAL_DMA_Abort(hspi->hdmarx);
+  }
+
+  /* Disable the SPI DMA Tx & Rx requests */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+  hspi->State = HAL_SPI_STATE_READY;
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SPI interrupt request.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval None
+  */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+  uint32_t itsource = hspi->Instance->CR2;
+  uint32_t itflag   = hspi->Instance->SR;
+
+  /* SPI in mode Receiver ----------------------------------------------------*/
+  if (((itflag & SPI_FLAG_OVR) == RESET) &&
+      ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+  {
+    hspi->RxISR(hspi);
+    return;
+  }
+
+  /* SPI in mode Transmitter -------------------------------------------------*/
+  if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+  {
+    hspi->TxISR(hspi);
+    return;
+  }
+
+  /* SPI in Error Treatment --------------------------------------------------*/
+  if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
+  {
+    /* SPI Overrun error interrupt occurred ----------------------------------*/
+    if ((itflag & SPI_FLAG_OVR) != RESET)
+    {
+      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);
+      }
+      else
+      {
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);
+        return;
+      }
+    }
+
+    /* SPI Mode Fault error interrupt occurred -------------------------------*/
+    if ((itflag & SPI_FLAG_MODF) != RESET)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+      __HAL_SPI_CLEAR_MODFFLAG(hspi);
+    }
+
+    /* SPI Frame error interrupt occurred ------------------------------------*/
+    if ((itflag & SPI_FLAG_FRE) != RESET)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+      __HAL_SPI_CLEAR_FREFLAG(hspi);
+    }
+
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      /* Disable all interrupts */
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+      hspi->State = HAL_SPI_STATE_READY;
+      /* Disable the SPI DMA requests if enabled */
+      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+      {
+        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+        /* Abort the SPI DMA Rx channel */
+        if (hspi->hdmarx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+          HAL_DMA_Abort_IT(hspi->hdmarx);
+        }
+        /* Abort the SPI DMA Tx channel */
+        if (hspi->hdmatx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+          HAL_DMA_Abort_IT(hspi->hdmatx);
+        }
+      }
+      else
+      {
+        /* Call user error callback */
+        HAL_SPI_ErrorCallback(hspi);
+      }
+    }
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx Half Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Half Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Half Transfer callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief SPI error callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_ErrorCallback should be implemented in the user file
+   */
+  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+            and user can use HAL_SPI_GetError() API to check the latest error occurred
+   */
+}
+
+/**
+  * @brief  SPI Abort Complete callback.
+  * @param  hspi SPI handle.
+  * @retval None
+  */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+  * @brief   SPI control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SPI.
+     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SPI handle state.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI state
+  */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+  /* Return SPI handle state */
+  return hspi->State;
+}
+
+/**
+  * @brief  Return the SPI error code.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI error code in bitmap format
+  */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+  /* Return SPI ErrorCode */
+  return hspi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Private_Functions
+  * @brief   Private functions
+  * @{
+  */
+
+/**
+  * @brief DMA SPI transmit process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  uint32_t tickstart = 0U;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* DMA Normal Mode */
+  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+  {
+    /* Disable ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+    /* Disable Tx DMA Request */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+    /* Check the end of the transaction */
+    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    }
+
+    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+    {
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    }
+
+    hspi->TxXferCount = 0U;
+    hspi->State = HAL_SPI_STATE_READY;
+
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      HAL_SPI_ErrorCallback(hspi);
+      return;
+    }
+  }
+  HAL_SPI_TxCpltCallback(hspi);
+}
+
+/**
+  * @brief DMA SPI receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+  __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  /* DMA Normal Mode */
+  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+  {
+    /* Disable ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+    /* CRC handling */
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Wait until RXNE flag */
+      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+      {
+        /* Error on the CRC reception */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      }
+      /* Read CRC */
+      if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+      {
+        tmpreg = hspi->Instance->DR;
+        /* To avoid GCC warning */
+        UNUSED(tmpreg);
+      }
+      else
+      {
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        /* To avoid GCC warning */
+        UNUSED(tmpreg);
+
+        if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+        {
+          if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+          {
+            /* Error on the CRC reception */
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+          }
+          tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+          /* To avoid GCC warning */
+          UNUSED(tmpreg);
+        }
+      }
+    }
+#endif /* USE_SPI_CRC */
+
+    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+    /* Check the end of the transaction */
+    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+    {
+      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+    }
+
+    hspi->RxXferCount = 0U;
+    hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+    /* Check if CRC error occurred */
+    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    }
+#endif /* USE_SPI_CRC */
+
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      HAL_SPI_ErrorCallback(hspi);
+      return;
+    }
+  }
+  HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI transmit receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+  __IO int16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  /* DMA Normal Mode */
+  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+  {
+    /* Disable ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+    /* CRC handling */
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+      {
+        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
+                                          tickstart) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+        }
+        /* Read CRC to Flush DR and RXNE flag */
+        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+        /* To avoid GCC warning */
+        UNUSED(tmpreg);
+      }
+      else
+      {
+        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+        {
+          /* Error on the CRC reception */
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+        }
+        /* Read CRC to Flush DR and RXNE flag */
+        tmpreg = hspi->Instance->DR;
+        /* To avoid GCC warning */
+        UNUSED(tmpreg);
+      }
+    }
+#endif /* USE_SPI_CRC */
+
+    /* Check the end of the transaction */
+    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    }
+
+    /* Disable Rx/Tx DMA Request */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+    hspi->TxXferCount = 0U;
+    hspi->RxXferCount = 0U;
+    hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+    /* Check if CRC error occurred */
+    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    }
+#endif /* USE_SPI_CRC */
+
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      HAL_SPI_ErrorCallback(hspi);
+      return;
+    }
+  }
+  HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI half transmit process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI half receive process complete callback
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI half transmit receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI communication error callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Stop the disable DMA transfer on SPI side */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+  hspi->State = HAL_SPI_STATE_READY;
+  HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hspi->hdmatx->XferAbortCallback = NULL;
+
+  /* Disable Tx DMA Request */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  /* Disable SPI Peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* Empty the FRLVL fifo */
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  /* Check if an Abort process is still ongoing */
+  if (hspi->hdmarx != NULL)
+  {
+    if (hspi->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Check no error during Abort procedure */
+  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+  {
+    /* Reset errorCode */
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  }
+
+  /* Clear the Error flags in the SR register */
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+  /* Restore hspi->State to Ready */
+  hspi->State  = HAL_SPI_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+  * @brief  DMA SPI Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable SPI Peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  /* Disable Rx DMA Request */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+  /* Control the BSY flag */
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  /* Empty the FRLVL fifo */
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  /* Check if an Abort process is still ongoing */
+  if (hspi->hdmatx != NULL)
+  {
+    if (hspi->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Check no error during Abort procedure */
+  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+  {
+    /* Reset errorCode */
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  }
+
+  /* Clear the Error flags in the SR register */
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+  /* Restore hspi->State to Ready */
+  hspi->State  = HAL_SPI_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in packing mode */
+  if (hspi->RxXferCount > 1U)
+  {
+    *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+    hspi->pRxBuffPtr += sizeof(uint16_t);
+    hspi->RxXferCount -= 2U;
+    if (hspi->RxXferCount == 1U)
+    {
+      /* set fiforxthresold according the reception data length: 8bit */
+      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+    }
+  }
+  /* Receive data in 8 Bit mode */
+  else
+  {
+    *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+    hspi->RxXferCount--;
+  }
+
+  /* check end of the reception */
+  if (hspi->RxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
+      return;
+    }
+#endif /* USE_SPI_CRC */
+
+    /* Disable RXNE  and ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+    if (hspi->TxXferCount == 0U)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  __IO uint8_t tmpreg = 0U;
+
+  /* Read data register to flush CRC */
+  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+  /* To avoid GCC warning */
+  UNUSED(tmpreg);
+
+  hspi->CRCSize--;
+
+  /* check end of the reception */
+  if (hspi->CRCSize == 0U)
+  {
+    /* Disable RXNE and ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+    if (hspi->TxXferCount == 0U)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in packing Bit mode */
+  if (hspi->TxXferCount >= 2U)
+  {
+    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+    hspi->pTxBuffPtr += sizeof(uint16_t);
+    hspi->TxXferCount -= 2U;
+  }
+  /* Transmit data in 8 Bit mode */
+  else
+  {
+    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+    hspi->TxXferCount--;
+  }
+
+  /* check the end of the transmission */
+  if (hspi->TxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Set CRC Next Bit to send CRC */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+      /* Disable TXE interrupt */
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+      return;
+    }
+#endif /* USE_SPI_CRC */
+
+    /* Disable TXE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+    if (hspi->RxXferCount == 0U)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 16 Bit mode */
+  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+  hspi->pRxBuffPtr += sizeof(uint16_t);
+  hspi->RxXferCount--;
+
+  if (hspi->RxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
+      return;
+    }
+#endif /* USE_SPI_CRC */
+
+    /* Disable RXNE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+    if (hspi->TxXferCount == 0U)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 16 Bit mode */
+  __IO uint16_t tmpreg = 0U;
+
+  /* Read data register to flush CRC */
+  tmpreg = hspi->Instance->DR;
+
+  /* To avoid GCC warning */
+  UNUSED(tmpreg);
+
+  /* Disable RXNE interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+  SPI_CloseRxTx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 16 Bit mode */
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint16_t);
+  hspi->TxXferCount--;
+
+  /* Enable CRC Transmission */
+  if (hspi->TxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Set CRC Next Bit to send CRC */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+      /* Disable TXE interrupt */
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+      return;
+    }
+#endif /* USE_SPI_CRC */
+
+    /* Disable TXE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+    if (hspi->RxXferCount == 0U)
+    {
+      SPI_CloseRxTx_ISR(hspi);
+    }
+  }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+  * @brief  Manage the CRC 8-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  __IO uint8_t tmpreg = 0U;
+
+  /* Read data register to flush CRC */
+  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+  /* To avoid GCC warning */
+  UNUSED(tmpreg);
+
+  hspi->CRCSize--;
+
+  if (hspi->CRCSize == 0U)
+  {
+    SPI_CloseRx_ISR(hspi);
+  }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+  * @brief  Manage the receive 8-bit in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+  hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+  /* Enable CRC Transmission */
+  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+  }
+#endif /* USE_SPI_CRC */
+
+  if (hspi->RxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR =  SPI_RxISR_8BITCRC;
+      return;
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseRx_ISR(hspi);
+  }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+  * @brief  Manage the CRC 16-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  __IO uint16_t tmpreg = 0U;
+
+  /* Read data register to flush CRC */
+  tmpreg = hspi->Instance->DR;
+
+  /* To avoid GCC warning */
+  UNUSED(tmpreg);
+
+  /* Disable RXNE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+  SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+  * @brief  Manage the 16-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+  hspi->pRxBuffPtr += sizeof(uint16_t);
+  hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+  /* Enable CRC Transmission */
+  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+  }
+#endif /* USE_SPI_CRC */
+
+  if (hspi->RxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR = SPI_RxISR_16BITCRC;
+      return;
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseRx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief  Handle the data 8-bit transmit in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+  hspi->TxXferCount--;
+
+  if (hspi->TxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Enable CRC Transmission */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseTx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief  Handle the data 16-bit transmit in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 16 Bit mode */
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint16_t);
+  hspi->TxXferCount--;
+
+  if (hspi->TxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Enable CRC Transmission */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseTx_ISR(hspi);
+  }
+}
+
+/**
+  * @brief Handle SPI Communication Timeout.
+  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *              the configuration information for SPI module.
+  * @param Flag: SPI flag to check
+  * @param State: flag state to check
+  * @param Timeout: Timeout duration
+  * @param Tickstart: tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+                                                       uint32_t Timeout, uint32_t Tickstart)
+{
+  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
+      {
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared
+        on both master and slave sides in order to resynchronize the master
+        and slave for their respective CRC calculation */
+
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+        {
+          /* Disable SPI peripheral */
+          __HAL_SPI_DISABLE(hspi);
+        }
+
+        /* Reset CRC Calculation */
+        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+        {
+          SPI_RESET_CRC(hspi);
+        }
+
+        hspi->State = HAL_SPI_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle SPI FIFO Communication Timeout.
+  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *              the configuration information for SPI module.
+  * @param Fifo: Fifo to check
+  * @param State: Fifo state to check
+  * @param Timeout: Timeout duration
+  * @param Tickstart: tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+                                                       uint32_t Timeout, uint32_t Tickstart)
+{
+  __IO uint8_t tmpreg;
+
+  while ((hspi->Instance->SR & Fifo) != State)
+  {
+    if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+    {
+      tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+      /* To avoid GCC warning */
+      UNUSED(tmpreg);
+    }
+
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
+      {
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared
+           on both master and slave sides in order to resynchronize the master
+           and slave for their respective CRC calculation */
+
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+        {
+          /* Disable SPI peripheral */
+          __HAL_SPI_DISABLE(hspi);
+        }
+
+        /* Reset CRC Calculation */
+        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+        {
+          SPI_RESET_CRC(hspi);
+        }
+
+        hspi->State = HAL_SPI_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle the check of the RX transaction complete.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  Timeout: Timeout duration
+  * @param  Tickstart: tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
+{
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+  {
+    /* Disable SPI peripheral */
+    __HAL_SPI_DISABLE(hspi);
+  }
+
+  /* Control the BSY flag */
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    return HAL_TIMEOUT;
+  }
+
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+  {
+    /* Empty the FRLVL fifo */
+    if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle the check of the RXTX or TX transaction complete.
+  * @param  hspi: SPI handle
+  * @param  Timeout: Timeout duration
+  * @param  Tickstart: tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Control if the TX fifo is empty */
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    return HAL_TIMEOUT;
+  }
+  /* Control the BSY flag */
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    return HAL_TIMEOUT;
+  }
+
+  /* Control if the RX fifo is empty */
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    return HAL_TIMEOUT;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle the end of the RXTX transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  uint32_t tickstart = 0U;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Disable ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    hspi->State = HAL_SPI_STATE_READY;
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+#endif /* USE_SPI_CRC */
+    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+    {
+      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+      {
+        hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_RxCpltCallback(hspi);
+      }
+      else
+      {
+        hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_TxRxCpltCallback(hspi);
+      }
+    }
+    else
+    {
+      hspi->State = HAL_SPI_STATE_READY;
+      HAL_SPI_ErrorCallback(hspi);
+    }
+#if (USE_SPI_CRC != 0U)
+  }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+  * @brief  Handle the end of the RX transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+  /* Disable RXNE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+  }
+  hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+#endif /* USE_SPI_CRC */
+    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+    {
+      HAL_SPI_RxCpltCallback(hspi);
+    }
+    else
+    {
+      HAL_SPI_ErrorCallback(hspi);
+    }
+#if (USE_SPI_CRC != 0U)
+  }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+  * @brief  Handle the end of the TX transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  uint32_t tickstart = 0U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  /* Disable TXE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+  }
+
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+  hspi->State = HAL_SPI_STATE_READY;
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+    HAL_SPI_TxCpltCallback(hspi);
+  }
+}
+
+/**
+  * @brief  Handle abort a Rx transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+  __IO uint32_t count;
+  
+  /* Disable SPI Peripheral */
+  __HAL_SPI_DISABLE(hspi);
+  
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+  
+  /* Check RXNEIE is disabled */
+  do
+  {
+    if (count-- == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+      break;
+    }
+  }
+  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+  /* Control the BSY flag */
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  /* Empty the FRLVL fifo */
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+  * @brief  Handle abort a Tx or Rx/Tx transaction.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  __IO uint32_t count;
+  
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+  
+  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+  
+  /* Check TXEIE is disabled */
+  do
+  {
+    if (count-- == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+      break;
+    }
+  }
+  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  /* Disable SPI Peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* Empty the FRLVL fifo */
+  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+  }
+
+  hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h
new file mode 100755
index 0000000..bcfdb90
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h
@@ -0,0 +1,696 @@
+ /**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi.h
+  * @author  MCD Application Team
+  * @version V1.5.1
+  * @date    31-May-2016
+  * @brief   Header file of SPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SPI_H
+#define __STM32L4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Mode;                /*!< Specifies the SPI operating mode.
+                                     This parameter can be a value of @ref SPI_Mode */
+
+  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
+                                     This parameter can be a value of @ref SPI_Direction */
+
+  uint32_t DataSize;            /*!< Specifies the SPI data size.
+                                     This parameter can be a value of @ref SPI_Data_Size */
+
+  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
+                                     This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
+                                     This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                     hardware (NSS pin) or by software using the SSI bit.
+                                     This parameter can be a value of @ref SPI_Slave_Select_management */
+
+  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                     used to configure the transmit and receive SCK clock.
+                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                     @note The communication clock is derived from the master
+                                     clock. The slave clock does not need to be set. */
+
+  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not .
+                                     This parameter can be a value of @ref SPI_TI_mode */
+
+  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
+                                     This parameter can be a value of @ref SPI_CRC_Calculation */
+
+  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
+                                     CRC Length is only used with Data8 and Data16, not other data size
+                                     This parameter can be a value of @ref SPI_CRC_length */
+
+  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
+                                     This parameter can be a value of @ref SPI_NSSP_Mode
+                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and
+                                     it takes effect only if the SPI interface is configured as Motorola SPI
+                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
+                                     CPOL setting is ignored).. */
+} SPI_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SPI_STATE_RESET      = 0x00,    /*!< Peripheral not Initialized                         */
+  HAL_SPI_STATE_READY      = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SPI_STATE_BUSY       = 0x02,    /*!< an internal process is ongoing                     */
+  HAL_SPI_STATE_BUSY_TX    = 0x03,    /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x04,    /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x05,    /*!< Data Transmission and Reception process is ongoing*/
+  HAL_SPI_STATE_ERROR      = 0x06     /*!< SPI error state                                   */
+}HAL_SPI_StateTypeDef;
+
+/**
+  * @brief  SPI handle Structure definition
+  */
+typedef struct __SPI_HandleTypeDef
+{
+  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
+
+  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
+
+  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
+
+  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
+
+  uint16_t                   TxXferCount;    /*!< SPI Tx Transfer Counter                  */
+
+  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
+
+  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
+
+  uint16_t                   RxXferCount;    /*!< SPI Rx Transfer Counter                  */
+
+  uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
+
+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
+
+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
+
+  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
+
+  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
+
+  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
+
+}SPI_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_Error_Code SPI Error Code
+  * @{
+  */
+#define HAL_SPI_ERROR_NONE   (uint32_t)0x00000000  /*!< No error                          */
+#define HAL_SPI_ERROR_MODF   (uint32_t)0x00000001  /*!< MODF error                        */
+#define HAL_SPI_ERROR_CRC    (uint32_t)0x00000002  /*!< CRC error                         */
+#define HAL_SPI_ERROR_OVR    (uint32_t)0x00000004  /*!< OVR error                         */
+#define HAL_SPI_ERROR_FRE    (uint32_t)0x00000008  /*!< FRE error                         */
+#define HAL_SPI_ERROR_DMA    (uint32_t)0x00000010  /*!< DMA transfer error                */
+#define HAL_SPI_ERROR_FLAG   (uint32_t)0x00000020  /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040  /*!< Unknown error                     */
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_Mode SPI Mode
+  * @{
+  */
+#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+  * @{
+  */
+#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+  * @{
+  */
+#define SPI_DATASIZE_4BIT               ((uint32_t)0x0300)
+#define SPI_DATASIZE_5BIT               ((uint32_t)0x0400)
+#define SPI_DATASIZE_6BIT               ((uint32_t)0x0500)
+#define SPI_DATASIZE_7BIT               ((uint32_t)0x0600)
+#define SPI_DATASIZE_8BIT               ((uint32_t)0x0700)
+#define SPI_DATASIZE_9BIT               ((uint32_t)0x0800)
+#define SPI_DATASIZE_10BIT              ((uint32_t)0x0900)
+#define SPI_DATASIZE_11BIT              ((uint32_t)0x0A00)
+#define SPI_DATASIZE_12BIT              ((uint32_t)0x0B00)
+#define SPI_DATASIZE_13BIT              ((uint32_t)0x0C00)
+#define SPI_DATASIZE_14BIT              ((uint32_t)0x0D00)
+#define SPI_DATASIZE_15BIT              ((uint32_t)0x0E00)
+#define SPI_DATASIZE_16BIT              ((uint32_t)0x0F00)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+  * @{
+  */
+#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
+#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+  * @{
+  */
+#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
+#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+  * @{
+  */
+#define SPI_NSS_SOFT                    SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+  * @{
+  */
+#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+  * @{
+  */
+#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+  * @{
+  */
+#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
+/**
+  * @}
+  */
+
+/** @defgroup SPI_TI_mode SPI TI mode
+  * @{
+  */
+#define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+  * @{
+  */
+#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+  * @{
+  * This parameter can be one of the following values:
+  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
+  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
+  */
+#define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000)
+#define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001)
+#define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
+  * @{
+  * This parameter can be one of the following values:
+  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+  *          RXNE event is generated if the FIFO
+  *          level is greater or equal to 1/2(16-bits).
+  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+  *          level is greater or equal to 1/4(8 bits). */
+#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
+  * @brief SPI Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define SPI_IT_TXE                      SPI_CR2_TXEIE
+#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
+#define SPI_IT_ERR                      SPI_CR2_ERRIE
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_Flag_definition SPI Flag definition
+  * @brief Flag definition
+  *        Elements values convention: 0xXXXXYYYY
+  *           - XXXX  : Flag register Index
+  *           - YYYY  : Flag mask
+  * @{
+  */
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
+  * @{
+  */
+#define SPI_FTLVL_EMPTY           ((uint32_t)0x0000)
+#define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x0800)
+#define SPI_FTLVL_HALF_FULL       ((uint32_t)0x1000)
+#define SPI_FTLVL_FULL            ((uint32_t)0x1800)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+  * @{
+  */
+#define SPI_FRLVL_EMPTY           ((uint32_t)0x0000)
+#define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x0200)
+#define SPI_FRLVL_HALF_FULL       ((uint32_t)0x0400)
+#define SPI_FRLVL_FULL            ((uint32_t)0x0600)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SPI handle state.
+  * @param  __HANDLE__: SPI handle.
+  * @retval None
+  */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief  Enable or disable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SPI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
+  *            @arg SPI_FLAG_CRCERR: CRC error flag
+  *            @arg SPI_FLAG_MODF: Mode fault flag
+  *            @arg SPI_FLAG_OVR: Overrun flag
+  *            @arg SPI_FLAG_BSY: Busy flag
+  *            @arg SPI_FLAG_FRE: Frame format error flag
+  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the SPI CRCERR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief  Clear the SPI MODF pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  *
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \
+   do{                                              \
+     __IO uint32_t tmpreg;                          \
+     tmpreg = (__HANDLE__)->Instance->SR;           \
+     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+     UNUSED(tmpreg);                                \
+   } while(0)
+
+/** @brief  Clear the SPI OVR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  *
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \
+   do{                                              \
+     __IO uint32_t tmpreg;                          \
+     tmpreg = (__HANDLE__)->Instance->DR;           \
+     tmpreg = (__HANDLE__)->Instance->SR;           \
+     UNUSED(tmpreg);                                \
+   } while(0)
+
+/** @brief  Clear the SPI FRE pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  *
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \
+   do{                                              \
+     __IO uint32_t tmpreg;                          \
+     tmpreg = (__HANDLE__)->Instance->SR;           \
+     UNUSED(tmpreg);                                \
+   } while(0)
+
+/** @brief  Enable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
+
+/** @brief  Disable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros   SPI Private Macros
+  * @{
+  */
+
+/** @brief  Set the SPI transmit-only mode.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+/** @brief  Set the SPI receive-only mode.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+
+/** @brief  Reset the CRC calculation of the SPI.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
+                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+                           ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES) || \
+                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
+                                  ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+                                                 ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+                           ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+                           ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+                         ((NSS) == SPI_NSS_HARD_INPUT) || \
+                         ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+                           ((NSSP) == SPI_NSS_PULSE_DISABLE))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+                               ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+                             ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
+                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
+                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+
+/**
+  * @}
+  */
+
+/* Include SPI HAL Extended module */
+#include "stm32l4xx_hal_spi_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup SPI_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SPI_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SPI_Exported_Functions_Group3
+  * @{
+  */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h.old b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h.old
new file mode 100755
index 0000000..2e51ffb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h.old
@@ -0,0 +1,703 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SPI_H
+#define __STM32L4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Mode;                /*!< Specifies the SPI operating mode.
+                                     This parameter can be a value of @ref SPI_Mode */
+
+  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
+                                     This parameter can be a value of @ref SPI_Direction */
+
+  uint32_t DataSize;            /*!< Specifies the SPI data size.
+                                     This parameter can be a value of @ref SPI_Data_Size */
+
+  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
+                                     This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
+                                     This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                     hardware (NSS pin) or by software using the SSI bit.
+                                     This parameter can be a value of @ref SPI_Slave_Select_management */
+
+  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                     used to configure the transmit and receive SCK clock.
+                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                     @note The communication clock is derived from the master
+                                     clock. The slave clock does not need to be set. */
+
+  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
+                                     This parameter can be a value of @ref SPI_TI_mode */
+
+  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
+                                     This parameter can be a value of @ref SPI_CRC_Calculation */
+
+  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
+                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
+
+  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
+                                     CRC Length is only used with Data8 and Data16, not other data size
+                                     This parameter can be a value of @ref SPI_CRC_length */
+
+  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
+                                     This parameter can be a value of @ref SPI_NSSP_Mode
+                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and
+                                     it takes effect only if the SPI interface is configured as Motorola SPI
+                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
+                                     CPOL setting is ignored).. */
+} SPI_InitTypeDef;
+
+/**
+  * @brief  HAL SPI State structure definition
+  */
+typedef enum
+{
+  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
+  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
+  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
+  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
+} HAL_SPI_StateTypeDef;
+
+/**
+  * @brief  SPI handle Structure definition
+  */
+typedef struct __SPI_HandleTypeDef
+{
+  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
+
+  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
+
+  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
+
+  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
+
+  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
+
+  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
+
+  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
+
+  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
+
+  uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
+
+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
+
+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
+
+  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
+
+  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
+
+  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
+
+} SPI_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_Error_Code SPI Error Code
+  * @{
+  */
+#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
+#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
+#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
+#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
+#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
+#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
+#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Mode SPI Mode
+  * @{
+  */
+#define SPI_MODE_SLAVE                  (0x00000000U)
+#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+  * @{
+  */
+#define SPI_DIRECTION_2LINES            (0x00000000U)
+#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+  * @{
+  */
+#define SPI_DATASIZE_4BIT               (0x00000300U)
+#define SPI_DATASIZE_5BIT               (0x00000400U)
+#define SPI_DATASIZE_6BIT               (0x00000500U)
+#define SPI_DATASIZE_7BIT               (0x00000600U)
+#define SPI_DATASIZE_8BIT               (0x00000700U)
+#define SPI_DATASIZE_9BIT               (0x00000800U)
+#define SPI_DATASIZE_10BIT              (0x00000900U)
+#define SPI_DATASIZE_11BIT              (0x00000A00U)
+#define SPI_DATASIZE_12BIT              (0x00000B00U)
+#define SPI_DATASIZE_13BIT              (0x00000C00U)
+#define SPI_DATASIZE_14BIT              (0x00000D00U)
+#define SPI_DATASIZE_15BIT              (0x00000E00U)
+#define SPI_DATASIZE_16BIT              (0x00000F00U)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+  * @{
+  */
+#define SPI_POLARITY_LOW                (0x00000000U)
+#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+  * @{
+  */
+#define SPI_PHASE_1EDGE                 (0x00000000U)
+#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
+  * @{
+  */
+#define SPI_NSS_SOFT                    SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT              (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+  * @{
+  */
+#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLE           (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+  * @{
+  */
+#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
+  * @{
+  */
+#define SPI_FIRSTBIT_MSB                (0x00000000U)
+#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
+/**
+  * @}
+  */
+
+/** @defgroup SPI_TI_mode SPI TI Mode
+  * @{
+  */
+#define SPI_TIMODE_DISABLE              (0x00000000U)
+#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+  * @{
+  */
+#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
+#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+  * @{
+  * This parameter can be one of the following values:
+  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
+  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
+  */
+#define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
+#define SPI_CRC_LENGTH_8BIT             (0x00000001U)
+#define SPI_CRC_LENGTH_16BIT            (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
+  * @{
+  * This parameter can be one of the following values:
+  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+  *          RXNE event is generated if the FIFO
+  *          level is greater or equal to 1/2(16-bits).
+  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+  *          level is greater or equal to 1/4(8 bits). */
+#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
+  * @{
+  */
+#define SPI_IT_TXE                      SPI_CR2_TXEIE
+#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
+#define SPI_IT_ERR                      SPI_CR2_ERRIE
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Flags_definition SPI Flags Definition
+  * @{
+  */
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
+#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
+#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
+#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
+#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
+#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
+#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
+  * @{
+  */
+#define SPI_FTLVL_EMPTY                 (0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
+#define SPI_FTLVL_HALF_FULL             (0x00001000U)
+#define SPI_FTLVL_FULL                  (0x00001800U)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+  * @{
+  */
+#define SPI_FRLVL_EMPTY                 (0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
+#define SPI_FRLVL_HALF_FULL             (0x00000400U)
+#define SPI_FRLVL_FULL                  (0x00000600U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SPI handle state.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief  Enable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Disable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to disable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Check whether the specified SPI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
+  *            @arg SPI_FLAG_CRCERR: CRC error flag
+  *            @arg SPI_FLAG_MODF: Mode fault flag
+  *            @arg SPI_FLAG_OVR: Overrun flag
+  *            @arg SPI_FLAG_BSY: Busy flag
+  *            @arg SPI_FLAG_FRE: Frame format error flag
+  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the SPI CRCERR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief  Clear the SPI MODF pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
+  do{                                                    \
+    __IO uint32_t tmpreg_modf = 0x00U;                   \
+    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
+    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+    UNUSED(tmpreg_modf);                                 \
+  } while(0U)
+
+/** @brief  Clear the SPI OVR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
+  do{                                              \
+    __IO uint32_t tmpreg_ovr = 0x00U;              \
+    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
+    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
+    UNUSED(tmpreg_ovr);                            \
+  } while(0U)
+
+/** @brief  Clear the SPI FRE pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
+  do{                                              \
+  __IO uint32_t tmpreg_fre = 0x00U;                \
+  tmpreg_fre = (__HANDLE__)->Instance->SR;         \
+  UNUSED(tmpreg_fre);                              \
+  }while(0U)
+
+/** @brief  Enable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/** @brief  Disable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+  * @{
+  */
+
+/** @brief  Set the SPI transmit-only mode.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief  Set the SPI receive-only mode.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief  Reset the CRC calculation of the SPI.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+                           ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
+                                ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+                                ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+                                                ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+                           ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+                           ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
+                         ((NSS) == SPI_NSS_HARD_INPUT) || \
+                         ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+                           ((NSSP) == SPI_NSS_PULSE_DISABLE))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+                               ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+                             ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
+                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
+                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
+
+
+/**
+  * @}
+  */
+
+/* Include SPI HAL Extended module */
+#include "stm32l4xx_hal_spi_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPI_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+                                          uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                             uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c
new file mode 100755
index 0000000..543a289
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c
@@ -0,0 +1,133 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          SPI peripheral extended functionalities :
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPIEx SPIEx
+  * @brief SPI Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+  * @{
+  */
+#define SPI_FIFO_SIZE       4
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+  * @{
+  */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of extended functions to manage the SPI
+    data transfers.
+
+    (#) Rx data flush function:
+        (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Flush the RX fifo.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+  __IO uint32_t tmpreg;
+  uint8_t  count = 0U;
+  while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
+  {
+    count++;
+    tmpreg = hspi->Instance->DR;
+    UNUSED(tmpreg); /* To avoid GCC warning */
+    if (count == SPI_FIFO_SIZE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h
new file mode 100755
index 0000000..1835b59
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h
@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SPI HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SPI_EX_H
+#define __STM32L4xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPIEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SPI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c
new file mode 100755
index 0000000..caec737
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c
@@ -0,0 +1,699 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sram.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SRAM HAL module driver.
+  *          This file provides a generic firmware to drive SRAM memories  
+  *          mounted as external device.
+  *         
+  @verbatim
+  ==============================================================================
+                          ##### How to use this driver #####
+  ==============================================================================  
+  [..]
+    This driver is a generic layered driver which contains a set of APIs used to 
+    control SRAM memories. It uses the FMC layer functions to interface 
+    with SRAM devices.  
+    The following sequence should be followed to configure the FMC to interface
+    with SRAM/PSRAM memories: 
+      
+   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+          SRAM_HandleTypeDef  hsram; and: 
+          
+       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed 
+            values of the structure member.
+            
+       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined 
+            base register instance for NOR or SRAM device 
+                         
+       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+            base register instance for NOR or SRAM extended mode 
+             
+   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended 
+       mode timings; for example:
+          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
+      and fill its fields with the allowed values of the structure member.
+      
+   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+       performs the following sequence:
+          
+       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+       (##) Control register configuration using the FMC NORSRAM interface function 
+            FMC_NORSRAM_Init()
+       (##) Timing register configuration using the FMC NORSRAM interface function 
+            FMC_NORSRAM_Timing_Init()
+       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function 
+            FMC_NORSRAM_Extended_Timing_Init()
+       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()    
+
+   (#) At this stage you can perform read/write accesses from/to the memory connected 
+       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+       following APIs:
+       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+       
+   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation  
+       
+   (#) You can continuously monitor the SRAM device HAL state by calling the function
+       HAL_SRAM_GetState()              
+                             
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+/** @defgroup SRAM SRAM
+  * @brief SRAM HAL module driver.
+  * @{
+  */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/    
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions.
+  *
+  @verbatim    
+  ==============================================================================
+           ##### SRAM Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to initialize/de-initialize
+          the SRAM memory.
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform the SRAM device initialization sequence.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  Timing: Pointer to SRAM control timing structure 
+  * @param  ExtTiming: Pointer to SRAM extended mode timing structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{ 
+  /* Check the SRAM handle parameter */
+  if(hsram == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  if(hsram->State == HAL_SRAM_STATE_RESET)
+  {  
+    /* Allocate lock resource and initialize it */
+    hsram->Lock = HAL_UNLOCKED;
+    
+    /* Initialize the low level hardware (MSP) */
+    HAL_SRAM_MspInit(hsram);
+  }
+  
+  /* Initialize SRAM control Interface */
+  FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+  /* Initialize SRAM timing Interface */
+  FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); 
+
+  /* Initialize SRAM extended mode timing Interface */
+  FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);  
+  
+  /* Enable the NORSRAM device */
+  __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform the SRAM device de-initialization sequence.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{ 
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_SRAM_MspDeInit(hsram);
+   
+  /* Configure the SRAM registers with their reset values */
+  FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+  hsram->State = HAL_SRAM_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SRAM MSP.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SRAM_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the SRAM MSP.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SRAM_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DMA transfer complete error callback.
+  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                  ##### SRAM Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the SRAM memory
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read 8-bit buffer from SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+  __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;  
+  
+  /* Read data from memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint8_t *)psramaddress;
+    pDstBuffer++;
+    psramaddress++;
+  }
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;    
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+    
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Write 8-bit buffer to SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+  __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+  
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint8_t *)psramaddress = *pSrcBuffer; 
+    pSrcBuffer++;
+    psramaddress++;    
+  }    
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);
+    
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Read 16-bit buffer from SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+  __IO uint16_t * psramaddress = (uint16_t *)pAddress;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;  
+  
+  /* Read data from memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint16_t *)psramaddress;
+    pDstBuffer++;
+    psramaddress++;
+  }
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;    
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Write 16-bit buffer to SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+  __IO uint16_t * psramaddress = (uint16_t *)pAddress; 
+  
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint16_t *)psramaddress = *pSrcBuffer; 
+    pSrcBuffer++;
+    psramaddress++;    
+  }    
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Read 32-bit buffer from SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;  
+  
+  /* Read data from memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint32_t *)pAddress;
+    pDstBuffer++;
+    pAddress++;
+  }
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;    
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Write 32-bit buffer to SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint32_t *)pAddress = *pSrcBuffer; 
+    pSrcBuffer++;
+    pAddress++;    
+  }    
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);
+    
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Read a Word data buffer from the SRAM memory using DMA transfer.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);  
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;   
+  
+  /* Configure DMA user callbacks */
+  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
+  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+  /* Enable the DMA Channel */
+  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);  
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Write a Word data buffer to SRAM memory using DMA transfer.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+  
+  /* Configure DMA user callbacks */
+  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
+  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+  /* Enable the DMA Channel */
+  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;  
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);  
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions 
+ *  @brief   Control functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### SRAM Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the SRAM interface.
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enable dynamically SRAM write operation.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+
+  /* Enable write operation */
+  FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); 
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disable dynamically SRAM write operation.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;
+    
+  /* Disable write operation */
+  FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); 
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_PROTECTED;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### SRAM State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the SRAM controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Return the SRAM controller handle state.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL state
+  */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+  /* Return SRAM handle state */
+  return hsram->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h
new file mode 100755
index 0000000..4c3cb94
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h
@@ -0,0 +1,202 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sram.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SRAM_H
+#define __STM32L4xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_fmc.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SRAM
+  * @{
+  */ 
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+  * @{
+  */
+/** 
+  * @brief  HAL SRAM State structures definition  
+  */ 
+typedef enum
+{
+  HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
+  HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
+  HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
+  HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
+  HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
+  
+}HAL_SRAM_StateTypeDef;
+
+/** 
+  * @brief  SRAM handle Structure definition  
+  */ 
+typedef struct
+{
+  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */ 
+  
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
+  
+  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
+
+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ 
+  
+  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
+  
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
+  
+}SRAM_HandleTypeDef; 
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+
+/** @brief Reset SRAM handle state.
+  * @param  __HANDLE__: SRAM handle
+  * @retval None
+  */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @{
+ */
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/**
+  * @}
+  */
+  
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+ * @{
+ */
+
+/* SRAM Control functions  ****************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* SRAM Peripheral State functions ********************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c
new file mode 100755
index 0000000..7ba3f25
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c
@@ -0,0 +1,1550 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_swpmi.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SWPMI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Single Wire Protocol Master Interface (SWPMI).
+  *           + Initialization and Configuration
+  *           + Data transfers functions
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+     The SWPMI HAL driver can be used as follows:
+
+    (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).
+
+    (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
+        (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
+        (##) SWPMI IO configuration:
+            (+++) Enable the clock for the SWPMI GPIO.
+            (+++) Configure these SWPMI pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
+             and HAL_SWPMI_Receive_IT() APIs):
+            (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
+            (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().
+
+        (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
+             and HAL_SWPMI_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channels.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required
+                  Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channels and requests.
+            (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx channels.
+
+    (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.
+
+    (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.
+    
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SWPMI SWPMI
+  * @brief HAL SWPMI module driver
+  * @{
+  */
+#ifdef HAL_SWPMI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup SWPMI_Private_Constants SWPMI Private Constants
+  * @{
+  */
+#define SWPMI_TIMEOUT_VALUE       ((uint32_t) 22000)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SWPMI_DMAError(DMA_HandleTypeDef *hdma);
+static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi);
+static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi);
+static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi);
+static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi);
+static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi);
+static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
+  * @{
+  */
+
+/** @defgroup SWPMI_Exported_Group1 Initialization/de-initialization methods
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the SWPMI peripheral.
+      (+) De-initialize the SWPMI peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
+  * @param hswpmi: SWPMI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t wait_loop_index = 0;
+
+  /* Check the SWPMI handle allocation */
+  if(hswpmi == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_SWPMI_VOLTAGE_CLASS(hswpmi->Init.VoltageClass));
+    assert_param(IS_SWPMI_BITRATE_VALUE(hswpmi->Init.BitRate));
+    assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
+    assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
+
+    if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+    {
+      /* Allocate lock resource and initialize it */
+      hswpmi->Lock = HAL_UNLOCKED;
+    
+      /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+      HAL_SWPMI_MspInit(hswpmi);
+    }
+
+    hswpmi->State = HAL_SWPMI_STATE_BUSY;
+
+    /* Disable SWPMI interface */
+    CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+
+    /* Clear all SWPMI interface flags */
+    WRITE_REG(hswpmi->Instance->ICR, 0x019F);
+
+    /* Apply Voltage class selection */
+    MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
+
+    /* If Voltage class B, apply 300 \B5s delay */
+    if(hswpmi->Init.VoltageClass == SWPMI_VOLTAGE_CLASS_B)
+    {
+      /* Insure 300 \B5s wait to insure SWPMI_IO output not higher than 1.8V */
+      /* Wait loop initialization and execution                            */
+      /* Note: Variable divided by 4 to compensate partially CPU processing cycles. */
+      wait_loop_index = (300 * (SystemCoreClock / (1000000 * 4))) + 150;
+      while(wait_loop_index != 0)
+      {
+        wait_loop_index--;
+      }
+    }
+
+    /* Configure the BRR register (Bitrate) */
+    WRITE_REG(hswpmi->Instance->BRR, hswpmi->Init.BitRate);
+
+    /* Apply SWPMI CR configuration */
+    MODIFY_REG(hswpmi->Instance->CR, \
+               SWPMI_CR_RXDMA | SWPMI_CR_TXDMA  | SWPMI_CR_RXMODE | SWPMI_CR_TXMODE, \
+               hswpmi->Init.TxBufferingMode | hswpmi->Init.RxBufferingMode);
+
+    hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
+    hswpmi->State = HAL_SWPMI_STATE_READY;
+
+    /* Enable SWPMI peripheral if not */
+    SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+  }
+
+  return status;
+}
+
+/**
+  * @brief De-initialize the SWPMI peripheral.
+  * @param hswpmi: SWPMI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the SWPMI handle allocation */
+  if(hswpmi == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_SWPMI_INSTANCE(hswpmi->Instance));
+
+    hswpmi->State = HAL_SWPMI_STATE_BUSY;
+
+    /* Disable SWPMI interface */
+    CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+
+    /* DeInit the low level hardware */
+    HAL_SWPMI_MspDeInit(hswpmi);
+
+    hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
+
+    hswpmi->State = HAL_SWPMI_STATE_RESET;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hswpmi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief Initialize the SWPMI MSP.
+  * @param hswpmi: SWPMI handle
+  * @retval None
+  */
+__weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hswpmi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SWPMI_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the SWPMI MSP.
+  * @param hswpmi: SWPMI handle
+  * @retval None
+  */
+__weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hswpmi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SWPMI_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Exported_Group2 IO operation methods
+  *  @brief SWPMI Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation methods #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of functions allowing to manage the SWPMI
+     data transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA. The end of the data processing will be indicated through the
+           dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
+           the selected DMA channel interrupt handler when using DMA mode.
+           The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or receive process.
+           The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.
+
+    (#) Blocking mode API's are:
+        (++) HAL_SWPMI_Transmit()
+        (++) HAL_SWPMI_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are:
+        (++) HAL_SWPMI_Transmit_IT()
+        (++) HAL_SWPMI_Receive_IT()
+        (++) HAL_SWPMI_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are:
+        (++) HAL_SWPMI_Transmit_DMA()
+        (++) HAL_SWPMI_Receive_DMA()
+        (++) HAL_SWPMI_DMAPause()
+        (++) HAL_SWPMI_DMAResume()
+        (++) HAL_SWPMI_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
+        (++) HAL_SWPMI_TxHalfCpltCallback()
+        (++) HAL_SWPMI_TxCpltCallback()
+        (++) HAL_SWPMI_RxHalfCpltCallback()
+        (++) HAL_SWPMI_RxCpltCallback()
+        (++) HAL_SWPMI_ErrorCallback()
+
+    (#) The capability to launch the above IO operations in loopback mode for 
+        user application verification:    
+        (++) HAL_SWPMI_EnableLoopback()
+        (++) HAL_SWPMI_DisableLoopback()
+        
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
+  *                the configuration information for SWPMI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hswpmi);
+
+    if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
+    {
+      /* Check if a non-blocking receive process is ongoing or not */
+      if(hswpmi->State == HAL_SWPMI_STATE_READY)
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
+
+        /* Disable any transmitter interrupts */
+        __HAL_SWPMI_DISABLE_IT(hswpmi, SWPMI_IT_TCIE | SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
+
+        /* Disable any transmitter flags */
+        __HAL_SWPMI_CLEAR_FLAG(hswpmi, SWPMI_FLAG_TXBEF | SWPMI_FLAG_TXUNRF | SWPMI_FLAG_TCF);
+
+        /* Enable SWPMI peripheral if not */
+        SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+      }
+      else
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
+      }
+
+      do
+      {
+        /* Wait the TXE to write data */
+        if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
+        {
+          hswpmi->Instance->TDR = (*pData++);
+          Size--;
+        }
+        else
+        {
+          /* Check for the Timeout */
+          if(Timeout != HAL_MAX_DELAY)
+          {
+            if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+            {
+              status = HAL_TIMEOUT;
+              break;
+            }
+          }
+        }
+      } while(Size != 0);
+
+      /* Wait on TXBEF flag to be able to start a second transfer */
+      if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
+      {
+        status = HAL_TIMEOUT;
+      }
+
+      if(status == HAL_OK)
+      {
+        /* Check if a non-blocking receive Process is ongoing or not */
+        if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+        {
+          hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
+        }
+        else
+        {
+          hswpmi->State = HAL_SWPMI_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      status = HAL_BUSY;
+    }
+  }
+
+  if((status != HAL_OK) && (status != HAL_BUSY))
+  {
+    hswpmi->State = HAL_SWPMI_STATE_READY;
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hswpmi);
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
+  *                the configuration information for SWPMI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hswpmi);
+
+    if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
+    {
+      /* Check if a non-blocking transmit process is ongoing or not */
+      if(hswpmi->State == HAL_SWPMI_STATE_READY)
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
+
+        /* Disable any receiver interrupts */
+        CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
+
+        /* Enable SWPMI peripheral if not */
+        SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+      }
+      else
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
+      }
+
+      do
+      {
+        /* Wait the RXNE to read data */
+        if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
+        {
+          (*pData++) = hswpmi->Instance->RDR;
+          Size--;
+        }
+        else
+        {
+          /* Check for the Timeout */
+          if(Timeout != HAL_MAX_DELAY)
+          {
+            if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+            {
+              status = HAL_TIMEOUT;
+              break;
+            }
+          }
+        }
+      } while(Size != 0);
+      
+      if(status == HAL_OK)
+      {
+        if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
+        {
+          /* Clear RXBFF at end of reception */
+          WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
+        }
+
+        /* Check if a non-blocking transmit Process is ongoing or not */
+        if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+        {
+          hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
+        }
+        else
+        {
+          hswpmi->State = HAL_SWPMI_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      status = HAL_BUSY;
+    }
+  }
+
+  if((status != HAL_OK) && (status != HAL_BUSY))
+  {
+    hswpmi->State = HAL_SWPMI_STATE_READY;
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hswpmi);
+
+  return status;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with interrupt.
+  * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
+  *                the configuration information for SWPMI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    status =  HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hswpmi);
+
+    if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
+    {
+      /* Update handle */
+      hswpmi->pTxBuffPtr = pData;
+      hswpmi->TxXferSize = Size;
+      hswpmi->TxXferCount = Size;
+      hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
+
+      /* Check if a receive process is ongoing or not */
+      if(hswpmi->State == HAL_SWPMI_STATE_READY)
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
+
+        /* Enable SWPMI peripheral if not */
+        SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+      }
+      else
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
+      }
+
+      /* Enable the SWPMI transmit underrun error */
+      __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+
+      /* Enable the SWPMI interrupts:      */
+      /* - Transmit data register empty    */
+      /* - Transmit buffer empty           */
+      /* - Transmit/Reception completion   */
+      __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TIE | SWPMI_IT_TXBEIE | SWPMI_IT_TCIE);
+    }
+    else
+    {
+      status =  HAL_BUSY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with interrupt.
+  * @param hswpmi: SWPMI handle
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    status =  HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hswpmi);
+
+    if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
+    {
+      /* Update handle */
+      hswpmi->pRxBuffPtr = pData;
+      hswpmi->RxXferSize = Size;
+      hswpmi->RxXferCount = Size;
+      hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
+
+      /* Check if a transmit process is ongoing or not */
+      if(hswpmi->State == HAL_SWPMI_STATE_READY)
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
+
+        /* Enable SWPMI peripheral if not */
+        SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+      }
+      else
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+
+      /* Enable the SWPMI slave resume */
+      /* Enable the SWPMI Data Register not empty Interrupt, receive CRC Error, receive overrun and RxBuf Interrupt */
+      /*  Enable the SWPMI Transmit/Reception completion   */
+      __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
+    }
+    else
+    {
+      status = HAL_BUSY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Transmit an amount of data in non-blocking mode with DMA interrupt.
+  * @param hswpmi: SWPMI handle
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    status =  HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hswpmi);
+
+    if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
+    {
+      /* Update handle */
+      hswpmi->pTxBuffPtr = pData;
+      hswpmi->TxXferSize = Size;
+      hswpmi->TxXferCount = Size;
+      hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
+
+      /* Check if a receive process is ongoing or not */
+      if(hswpmi->State == HAL_SWPMI_STATE_READY)
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
+
+        /* Enable SWPMI peripheral if not */
+        SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+      }
+      else
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
+      }
+
+      /* Set the SWPMI DMA transfer complete callback */
+      hswpmi->hdmatx->XferCpltCallback = SWPMI_DMATransmitCplt;
+
+      /* Set the SWPMI DMA Half transfer complete callback */
+      hswpmi->hdmatx->XferHalfCpltCallback = SWPMI_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
+
+      /* Enable the SWPMI transmit DMA Channel */
+      HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+
+      /* Enable the SWPMI transmit underrun error */
+      __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
+
+      /* Enable the DMA transfer for transmit request by setting the TXDMA bit
+         in the SWPMI CR register */
+      SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
+    }
+    else
+    {
+      status = HAL_BUSY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with DMA interrupt.
+  * @param hswpmi: SWPMI handle
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if((pData == NULL ) || (Size == 0))
+  {
+    status =  HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hswpmi);
+
+    if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
+    {
+      /* Update handle */
+      hswpmi->pRxBuffPtr = pData;
+      hswpmi->RxXferSize = Size;
+      hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
+
+      /* Check if a transmit process is ongoing or not */
+      if(hswpmi->State == HAL_SWPMI_STATE_READY)
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
+
+        /* Enable SWPMI peripheral if not */
+        SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+      }
+      else
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
+      }
+
+      /* Set the SWPMI DMA transfer complete callback */
+      hswpmi->hdmarx->XferCpltCallback = SWPMI_DMAReceiveCplt;
+
+      /* Set the SWPMI DMA Half transfer complete callback */
+      hswpmi->hdmarx->XferHalfCpltCallback = SWPMI_DMARxHalfCplt;
+
+      /* Set the DMA error callback */
+      hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
+
+      /* Enable the DMA request */
+      HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+
+      /* Enable the SWPMI receive CRC Error and receive overrun interrupts */
+      __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE);
+
+      /* Enable the DMA transfer for the receiver request by setting the RXDMA bit
+         in the SWPMI CR register */
+      SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
+    }
+    else
+    {
+      status = HAL_BUSY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hswpmi);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Stop all DMA transfers.
+  * @param hswpmi: SWPMI handle
+  * @retval HAL_OK
+  */
+HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hswpmi);
+
+  /* Disable the SWPMI Tx/Rx DMA requests */
+  CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
+
+  /* Abort the SWPMI DMA tx channel */
+  if(hswpmi->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(hswpmi->hdmatx);
+  }
+  /* Abort the SWPMI DMA rx channel */
+  if(hswpmi->hdmarx != NULL)
+  {
+    HAL_DMA_Abort(hswpmi->hdmarx);
+  }
+
+  /* Disable SWPMI interface */
+  CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
+
+  hswpmi->State = HAL_SWPMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hswpmi);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enable the Loopback mode.
+  * @param hswpmi: SWPMI handle
+  * @note  Loopback mode is to be used only for test purposes
+  * @retval HAL_OK / HAL_BUSY
+  */
+HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hswpmi);
+
+  /* Check SWPMI not enabled */
+  if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
+  {
+    status = HAL_BUSY;
+  }
+  else
+  {
+    /* Set Loopback */
+    SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hswpmi);
+
+  return status;
+}
+
+/**
+  * @brief Disable the Loopback mode.
+  * @param hswpmi: SWPMI handle
+  * @note  Loopback mode is to be used only for test purposes
+  * @retval HAL_OK / HAL_BUSY
+  */
+HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hswpmi);
+
+  /* Check SWPMI not enabled */
+  if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
+  {
+    status = HAL_BUSY;
+  }
+  else
+  {
+    /* Reset Loopback */
+    CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hswpmi);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks
+ *  @brief  SWPMI  IRQ handler.
+ *
+@verbatim   
+  ==============================================================================
+                      ##### SWPMI IRQ handler and callbacks  #####
+  ==============================================================================  
+[..]  This section provides SWPMI IRQ handler and callback functions called within 
+      the IRQ handler.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Handle SWPMI interrupt request.
+  * @param hswpmi: SWPMI handle
+  * @retval None
+  */
+void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
+{
+  uint32_t regisr = READ_REG(hswpmi->Instance->ISR);
+  uint32_t regier = READ_REG(hswpmi->Instance->IER);
+  uint32_t errcode = HAL_SWPMI_ERROR_NONE;
+
+  /* SWPMI CRC error interrupt occurred --------------------------------------*/
+  if(((regisr & SWPMI_FLAG_RXBERF) != RESET) && ((regier & SWPMI_IT_RXBERIE) != RESET))
+  {
+    /* Disable Receive CRC interrupt */
+    CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
+    /* Clear Receive CRC and Receive buffer full flag */
+    WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBERF | SWPMI_FLAG_RXBFF);
+
+    errcode |= HAL_SWPMI_ERROR_CRC;
+  }
+
+  /* SWPMI Over-Run interrupt occurred -----------------------------------------*/
+  if(((regisr & SWPMI_FLAG_RXOVRF) != RESET) && ((regier & SWPMI_IT_RXOVRIE) != RESET))
+  {
+    /* Disable Receive overrun interrupt */
+    CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
+    /* Clear Receive overrun flag */
+    WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXOVRF);
+
+    errcode |= HAL_SWPMI_ERROR_OVR;
+  }
+
+  /* SWPMI Under-Run interrupt occurred -----------------------------------------*/
+  if(((regisr & SWPMI_FLAG_TXUNRF) != RESET) && ((regier & SWPMI_IT_TXUNRIE) != RESET))
+  {
+    /* Disable Transmit under run interrupt */
+    CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
+    /* Clear Transmit under run flag */
+    WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXUNRF);
+
+    errcode |= HAL_SWPMI_ERROR_UDR;
+  }
+
+   /* Call SWPMI Error Call back function if needed --------------------------*/
+  if(errcode != HAL_SWPMI_ERROR_NONE)
+  {
+    hswpmi->ErrorCode |= errcode;
+    
+    if((errcode & HAL_SWPMI_ERROR_UDR) != RESET)
+    {
+      /* Check TXDMA transfer to abort */
+      if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
+      {
+        /* Disable DMA TX at SWPMI level */
+        CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
+        
+        /* Abort the USART DMA Tx channel */
+        if(hswpmi->hdmatx != NULL)
+        {
+          /* Set the SWPMI Tx DMA Abort callback : 
+             will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
+          hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
+          /* Abort DMA TX */
+          if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
+          {
+            /* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */
+            hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
+          }
+        }
+        else
+        {
+          /* Set the SWPMI state ready to be able to start again the process */
+          hswpmi->State = HAL_SWPMI_STATE_READY;
+
+          HAL_SWPMI_ErrorCallback(hswpmi);
+        }
+      }
+      else
+      {
+        /* Set the SWPMI state ready to be able to start again the process */
+        hswpmi->State = HAL_SWPMI_STATE_READY;
+
+        HAL_SWPMI_ErrorCallback(hswpmi);
+      }
+    }
+    else
+    {
+      /* Check RXDMA transfer to abort */
+      if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
+      {
+        /* Disable DMA RX at SWPMI level */
+        CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
+        
+        /* Abort the USART DMA Rx channel */
+        if(hswpmi->hdmarx != NULL)
+        {
+          /* Set the SWPMI Rx DMA Abort callback : 
+             will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
+          hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
+          /* Abort DMA RX */
+          if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
+          {
+            /* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */
+            hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
+          }
+        }
+        else
+        {
+          /* Set the SWPMI state ready to be able to start again the process */
+          hswpmi->State = HAL_SWPMI_STATE_READY;
+
+          HAL_SWPMI_ErrorCallback(hswpmi);
+        }
+      }
+      else
+      {
+        /* Set the SWPMI state ready to be able to start again the process */
+        hswpmi->State = HAL_SWPMI_STATE_READY;
+
+        HAL_SWPMI_ErrorCallback(hswpmi);
+      }
+    }
+  }
+
+  /* SWPMI in mode Receiver ---------------------------------------------------*/
+  if(((regisr & SWPMI_FLAG_RXNE) != RESET) && ((regier & SWPMI_IT_RIE)  != RESET))
+  {
+    SWPMI_Receive_IT(hswpmi);
+  }
+
+  /* SWPMI in mode Transmitter ------------------------------------------------*/
+  if(((regisr & SWPMI_FLAG_TXE) != RESET) && ((regier & SWPMI_IT_TIE) != RESET))
+  {
+    SWPMI_Transmit_IT(hswpmi);
+  }
+
+  /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
+  if(((regisr & SWPMI_FLAG_TXBEF) != RESET) && ((regier & SWPMI_IT_TXBEIE) != RESET))
+  {
+    SWPMI_EndTransmit_IT(hswpmi);
+  }
+
+  /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
+  if(((regisr & SWPMI_FLAG_RXBFF) != RESET) && ((regier & SWPMI_IT_RXBFIE) != RESET))
+  {
+    SWPMI_EndReceive_IT(hswpmi);
+  }
+
+  /* Both Transmission and reception complete ---------------------------------*/
+  if(((regisr & SWPMI_FLAG_TCF) != RESET) && ((regier & SWPMI_IT_TCIE) != RESET))
+  {
+    SWPMI_EndTransmitReceive_IT(hswpmi);
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param hswpmi: SWPMI handle
+  * @retval None
+  */
+__weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hswpmi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SWPMI_TxCpltCallback is to be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hswpmi: SWPMI handle
+  * @retval None
+  */
+__weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hswpmi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_SWPMI_TxHalfCpltCallback is to be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param hswpmi: SWPMI handle
+  * @retval None
+  */
+__weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hswpmi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SWPMI_RxCpltCallback is to be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  hswpmi: SWPMI handle
+  * @retval None
+  */
+__weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hswpmi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_SWPMI_RxHalfCpltCallback is to be implemented in the user file
+   */
+}
+
+/**
+  * @brief SWPMI error callback.
+  * @param hswpmi: SWPMI handle
+  * @retval None
+  */
+__weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hswpmi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SWPMI_ErrorCallback is to be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Exported_Group4 Peripheral Control methods
+  *  @brief   SWPMI control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control methods #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SWPMI.
+     (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
+     (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the SWPMI handle state.
+  * @param hswpmi: SWPMI handle
+  * @retval HAL state
+  */
+HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Return SWPMI handle state */
+  return hswpmi->State;
+}
+
+/**
+* @brief  Return the SWPMI error code.
+* @param  hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains
+  *              the configuration information for the specified SWPMI.
+* @retval SWPMI Error Code
+*/
+uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi)
+{
+  return hswpmi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SWPMI_Private_Functions SWPMI Private Functions
+  * @{
+  */
+
+/**
+  * @brief Transmit an amount of data in interrupt mode.
+  * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
+  * @param  hswpmi: SWPMI handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
+  {
+    if(hswpmi->TxXferCount == 0)
+    {
+      /* Disable the SWPMI TXE and Underrun Interrupts */
+      CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
+    }
+    else
+    {
+      hswpmi->Instance->TDR = (uint32_t)(*hswpmi->pTxBuffPtr++);
+      hswpmi->TxXferCount--;
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Wraps up transmission in non-blocking mode.
+  * @param  hswpmi: SWPMI handle
+  * @retval HAL status
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Clear the SWPMI Transmit buffer empty Flag */
+  WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF);
+  /* Disable the all SWPMI Transmit Interrupts  */
+  CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
+
+  /* Check if a receive Process is ongoing or not */
+  if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+  {
+    hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
+  }
+  else
+  {
+    hswpmi->State = HAL_SWPMI_STATE_READY;
+  }
+  
+  HAL_SWPMI_TxCpltCallback(hswpmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
+  * @param  hswpmi: SWPMI handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if((hswpmi->State == HAL_SWPMI_STATE_BUSY_RX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
+  {
+    *hswpmi->pRxBuffPtr++ = (uint32_t)(hswpmi->Instance->RDR);
+
+    if(--hswpmi->RxXferCount == 0)
+    {
+      /* Wait for RXBFF flag to update state */
+      HAL_SWPMI_RxCpltCallback(hswpmi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Wraps up reception in non-blocking mode.
+  * @param  hswpmi: SWPMI handle
+  * @retval HAL status
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Clear the SWPMI Receive buffer full Flag */
+  WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
+  /* Disable the all SWPMI Receive Interrupts  */
+  CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
+
+  /* Check if a transmit Process is ongoing or not */
+  if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+  {
+    hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
+  }
+  else
+  {
+    hswpmi->State = HAL_SWPMI_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wraps up transmission and reception in non-blocking mode.
+  * @param  hswpmi: SWPMI handle
+  * @retval HAL status
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
+{
+  /* Clear the SWPMI Transmission Complete Flag */
+  WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF);
+  /* Disable the SWPMI Transmission  Complete Interrupt */
+  CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
+
+  /* Check if a receive Process is ongoing or not */
+  if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+  {
+    hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
+  }
+  else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
+  {
+    hswpmi->State = HAL_SWPMI_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief DMA SWPMI transmit process complete callback.
+  * @param hdma: DMA handle
+  * @retval None
+  */
+static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  uint32_t tickstart = 0;
+
+  /* DMA Normal mode*/
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) != SET)
+  {
+    hswpmi->TxXferCount = 0;
+
+    /* Disable the DMA transfer for transmit request by setting the TXDMA bit
+    in the SWPMI CR register */
+    CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    /* Wait the TXBEF */
+    if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      HAL_SWPMI_ErrorCallback(hswpmi);
+    }
+    else
+    {
+      /* No Timeout */
+      /* Check if a receive process is ongoing or not */
+      if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+      {
+        hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
+      }
+      else
+      {
+        hswpmi->State = HAL_SWPMI_STATE_READY;
+      }
+
+      HAL_SWPMI_TxCpltCallback(hswpmi);
+    }
+  }
+  /* DMA Circular mode */
+  else
+  {
+    HAL_SWPMI_TxCpltCallback(hswpmi);
+  }
+}
+
+/**
+  * @brief DMA SWPMI transmit process half complete callback.
+  * @param hdma : DMA handle
+  * @retval None
+  */
+static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_SWPMI_TxHalfCpltCallback(hswpmi);
+}
+
+
+/**
+  * @brief DMA SWPMI receive process complete callback.
+  * @param hdma: DMA handle
+  * @retval None
+  */
+static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* DMA Normal mode*/
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) == RESET)
+  {
+    hswpmi->RxXferCount = 0;
+
+    /* Disable the DMA transfer for the receiver request by setting the RXDMA bit
+    in the SWPMI CR register */
+    CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
+
+    /* Check if a transmit Process is ongoing or not */
+    if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+    {
+      hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
+    }
+    else
+    {
+      hswpmi->State = HAL_SWPMI_STATE_READY;
+    }
+  }
+  HAL_SWPMI_RxCpltCallback(hswpmi);
+}
+
+/**
+  * @brief DMA SWPMI receive process half complete callback.
+  * @param hdma : DMA handle
+  * @retval None
+  */
+static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_SWPMI_RxHalfCpltCallback(hswpmi);
+}
+
+/**
+  * @brief DMA SWPMI communication error callback.
+  * @param hdma: DMA handle
+  * @retval None
+  */
+static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Update handle */
+  hswpmi->RxXferCount = 0;
+  hswpmi->TxXferCount = 0;
+  hswpmi->State= HAL_SWPMI_STATE_READY;
+  hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
+
+  HAL_SWPMI_ErrorCallback(hswpmi);
+}
+
+/**
+  * @brief DMA SWPMI communication abort callback.
+  * @param hdma: DMA handle
+  * @retval None
+  */
+static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Update handle */
+  hswpmi->RxXferCount = 0;
+  hswpmi->TxXferCount = 0;
+  hswpmi->State= HAL_SWPMI_STATE_READY;
+
+  HAL_SWPMI_ErrorCallback(hswpmi);
+}
+
+/**
+  * @brief  Handle SWPMI Communication Timeout.
+  * @param  hswpmi: SWPMI handle
+  * @param  Flag: specifies the SWPMI flag to check.
+  * @param  Tickstart Tick start value
+  * @param  Timeout timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Wait until flag is set */
+  while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        hswpmi->State = HAL_SWPMI_STATE_READY;
+
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h
new file mode 100755
index 0000000..1f78f9d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h
@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_swpmi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SWPMI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SWPMI_H
+#define __STM32L4xx_HAL_SWPMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SWPMI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Types SWPMI Exported Types
+  * @{
+  */
+
+/**
+  * @brief SWPMI Init Structure definition
+  */
+typedef struct
+{
+  uint32_t VoltageClass;             /*!< Specifies the SWP Voltage Class.
+                                          This parameter can be a value of @ref SWPMI_Voltage_Class */
+
+  uint32_t BitRate;                  /*!< Specifies the SWPMI Bitrate.
+                                          This parameter must be a number between 0 and 63.
+                                          The Bitrate is computed using the following formula:
+                                          SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
+                                          */
+
+  uint32_t TxBufferingMode;          /*!< Specifies the transmission buffering mode.
+                                          This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */
+
+  uint32_t RxBufferingMode;          /*!< Specifies the reception buffering mode.
+                                          This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
+
+}SWPMI_InitTypeDef;
+
+
+/**
+  * @brief HAL SWPMI State structures definition
+  */
+typedef enum
+{
+  HAL_SWPMI_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                             */
+  HAL_SWPMI_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SWPMI_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
+  HAL_SWPMI_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
+  HAL_SWPMI_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
+  HAL_SWPMI_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_SWPMI_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
+  HAL_SWPMI_STATE_ERROR             = 0x04     /*!< Error                                              */
+}HAL_SWPMI_StateTypeDef;
+
+/**
+  * @brief  SWPMI handle Structure definition
+  */
+typedef struct
+{
+  SWPMI_TypeDef                  *Instance;     /* SWPMI registers base address         */
+
+  SWPMI_InitTypeDef              Init;          /* SWMPI communication parameters       */
+
+  uint32_t                       *pTxBuffPtr;   /* Pointer to SWPMI Tx transfer Buffer  */
+
+  uint32_t                       TxXferSize;    /* SWPMI Tx Transfer size               */
+
+  uint32_t                       TxXferCount;   /* SWPMI Tx Transfer Counter            */
+
+  uint32_t                       *pRxBuffPtr;   /* Pointer to SWPMI Rx transfer Buffer  */
+
+  uint32_t                       RxXferSize;    /* SWPMI Rx Transfer size               */
+
+  uint32_t                       RxXferCount;   /* SWPMI Rx Transfer Counter            */
+
+  DMA_HandleTypeDef              *hdmatx;       /* SWPMI Tx DMA Handle parameters       */
+
+  DMA_HandleTypeDef              *hdmarx;       /* SWPMI Rx DMA Handle parameters       */
+
+  HAL_LockTypeDef                Lock;          /* SWPMI object                         */
+
+  __IO HAL_SWPMI_StateTypeDef    State;         /* SWPMI communication state            */
+
+  __IO uint32_t                  ErrorCode;     /* SWPMI Error code                     */
+
+}SWPMI_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants
+  * @{
+  */
+
+/**
+  * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap
+  * @{
+  */
+#define HAL_SWPMI_ERROR_NONE                 ((uint32_t)0x00000000) /*!< No error             */
+#define HAL_SWPMI_ERROR_CRC                  ((uint32_t)0x00000004) /*!< frame error          */
+#define HAL_SWPMI_ERROR_OVR                  ((uint32_t)0x00000008) /*!< Overrun error        */
+#define HAL_SWPMI_ERROR_UDR                  ((uint32_t)0x0000000C) /*!< Underrun error       */
+#define HAL_SWPMI_ERROR_DMA                  ((uint32_t)0x00000010) /*!< DMA transfer error   */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class
+  * @{
+  */
+#define SWPMI_VOLTAGE_CLASS_C                ((uint32_t)0x00000000)
+#define SWPMI_VOLTAGE_CLASS_B                SWPMI_OR_CLASS
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode
+  * @{
+  */
+#define SWPMI_TX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
+#define SWPMI_TX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
+#define SWPMI_TX_MULTI_SOFTWAREBUFFER        SWPMI_CR_TXMODE
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode
+  * @{
+  */
+#define SWPMI_RX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
+#define SWPMI_RX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
+#define SWPMI_RX_MULTI_SOFTWAREBUFFER        SWPMI_CR_RXMODE
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Flags SWPMI Status Flags
+  *        Elements values convention: 0xXXXXXXXX
+  *           - 0xXXXXXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define SWPMI_FLAG_RXBFF                 SWPMI_ISR_RXBFF
+#define SWPMI_FLAG_TXBEF                 SWPMI_ISR_TXBEF
+#define SWPMI_FLAG_RXBERF                SWPMI_ISR_RXBERF
+#define SWPMI_FLAG_RXOVRF                SWPMI_ISR_RXOVRF
+#define SWPMI_FLAG_TXUNRF                SWPMI_ISR_TXUNRF
+#define SWPMI_FLAG_RXNE                  SWPMI_ISR_RXNE
+#define SWPMI_FLAG_TXE                   SWPMI_ISR_TXE
+#define SWPMI_FLAG_TCF                   SWPMI_ISR_TCF
+#define SWPMI_FLAG_SRF                   SWPMI_ISR_SRF
+#define SWPMI_FLAG_SUSP                  SWPMI_ISR_SUSP
+#define SWPMI_FLAG_DEACTF                SWPMI_ISR_DEACTF
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the IER register
+  * @{
+  */
+#define SWPMI_IT_SRIE                    SWPMI_IER_SRIE
+#define SWPMI_IT_TCIE                    SWPMI_IER_TCIE
+#define SWPMI_IT_TIE                     SWPMI_IER_TIE
+#define SWPMI_IT_RIE                     SWPMI_IER_RIE
+#define SWPMI_IT_TXUNRIE                 SWPMI_IER_TXUNRIE
+#define SWPMI_IT_RXOVRIE                 SWPMI_IER_RXOVRIE
+#define SWPMI_IT_RXBERIE                 SWPMI_IER_RXBERIE
+#define SWPMI_IT_TXBEIE                  SWPMI_IER_TXBEIE
+#define SWPMI_IT_RXBFIE                  SWPMI_IER_RXBFIE
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros
+  * @{
+  */
+
+/** @brief Reset SWPMI handle state.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @retval None
+  */
+#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
+
+/**
+  * @brief  Enable the SWPMI peripheral.
+  * @param  __HANDLE__: SWPMI handle
+  * @retval None
+  */
+#define __HAL_SWPMI_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
+
+/**
+  * @brief  Disable the SWPMI peripheral.
+  * @param  __HANDLE__: SWPMI handle
+  * @retval None
+  */
+#define __HAL_SWPMI_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
+
+/** @brief  Check whether the specified SWPMI flag is set or not.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
+  *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
+  *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
+  *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
+  *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
+  *            @arg SWPMI_FLAG_RXNE : Receive data register not empty.
+  *            @arg SWPMI_FLAG_TXE : Transmit data register empty.
+  *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
+  *            @arg SWPMI_FLAG_SRF : Slave resume flag.
+  *            @arg SWPMI_FLAG_SUSP : SUSPEND flag.
+  *            @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified SWPMI ISR flag.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
+  *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
+  *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
+  *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
+  *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
+  *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
+  *            @arg SWPMI_FLAG_SRF : Slave resume flag.
+  * @retval None
+  */
+#define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
+
+/** @brief  Enable the specified SWPMI interrupt.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __INTERRUPT__: specifies the SWPMI interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval None
+  */
+#define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief  Disable the specified SWPMI interrupt.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __INTERRUPT__: specifies the SWPMI interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval None
+  */
+#define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief  Check whether the specified SWPMI interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __IT__: specifies the SWPMI interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__)  (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
+
+/** @brief  Check whether the specified SWPMI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __IT__: specifies the SWPMI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);
+HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);
+HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);
+HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);
+
+/* Peripheral Control and State functions  ************************************/
+HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);
+uint32_t               HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Types SWPMI Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Variables SWPMI Private Variables
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Constants SWPMI Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Macros SWPMI Private Macros
+  * @{
+  */
+
+
+#define IS_SWPMI_VOLTAGE_CLASS(__CLASS__)    (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
+                                              ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
+
+#define IS_SWPMI_BITRATE_VALUE(__VALUE__)    (((__VALUE__) <= 63))
+
+
+#define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
+                                              ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
+
+
+#define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
+                                              ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SWPMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c
new file mode 100755
index 0000000..3b2fd25
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c
@@ -0,0 +1,5640 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tim.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + Time Base Initialization
+  *           + Time Base Start
+  *           + Time Base Start Interruption
+  *           + Time Base Start DMA
+  *           + Time Output Compare/PWM Initialization
+  *           + Time Output Compare/PWM Channel Configuration
+  *           + Time Output Compare/PWM  Start
+  *           + Time Output Compare/PWM  Start Interruption
+  *           + Time Output Compare/PWM Start DMA
+  *           + Time Input Capture Initialization
+  *           + Time Input Capture Channel Configuration
+  *           + Time Input Capture Start
+  *           + Time Input Capture Start Interruption
+  *           + Time Input Capture Start DMA
+  *           + Time One Pulse Initialization
+  *           + Time One Pulse Channel Configuration
+  *           + Time One Pulse Start
+  *           + Time Encoder Interface Initialization
+  *           + Time Encoder Interface Start
+  *           + Time Encoder Interface Start Interruption
+  *           + Time Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + Time OCRef clear configuration
+  *           + Time External Clock configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+              in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                     TIM_SlaveConfigTypeDef * sSlaveConfig);
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+ *  @brief    Time Base functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @param  htim: TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the TIM Base peripheral
+  * @param  htim: TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize TIM Base MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim : TIM handle
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Change the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim : TIM handle
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim : TIM handle
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+   /* Enable the TIM Update interrupt */
+   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+   /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim : TIM handle
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim : TIM handle
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((pData == 0 ) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  /* Set the DMA Period elapsed callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel */
+  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim : TIM handle
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ *  @brief    Time Output Compare functions
+ *
+@verbatim
+  ==============================================================================
+                  ##### Time Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the Time Output Compare.
+    (+) Stop the Time Output Compare.
+    (+) Start the Time Output Compare and enable interrupt.
+    (+) Stop the Time Output Compare and disable interrupt.
+    (+) Start the Time Output Compare and enable DMA transfer.
+    (+) Stop the Time Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @param  htim: TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the TIM peripheral
+  * @param  htim: TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+   htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize TIM Output Compare MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim : TIM OC handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+  default:
+    break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
+ *  @brief    Time PWM functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Time PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM OPWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the Time PWM.
+    (+) Stop the Time PWM.
+    (+) Start the Time PWM and enable interrupt.
+    (+) Stop the Time PWM and disable interrupt.
+    (+) Start the Time PWM and enable DMA transfer.
+    (+) Stop the Time PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @param  htim: TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the TIM peripheral
+  * @param  htim: TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize TIM PWM MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ *  @brief    Time Input Capture functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Time Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the Time Input Capture.
+   (+) Stop the Time Input Capture.
+   (+) Start the Time Input Capture and enable interrupt.
+   (+) Stop the Time Input Capture and disable interrupt.
+   (+) Start the Time Input Capture and enable DMA transfer.
+   (+) Stop the Time Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @param  htim: TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the TIM peripheral
+  * @param  htim: TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM INput Capture MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize TIM Input Capture MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim : TIM Input Capture handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim : TIM Input Capture handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement on in DMA mode.
+  * @param  htim : TIM Input Capture handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData: The destination Buffer address.
+  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((pData == 0 ) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement on in DMA mode.
+  * @param  htim : TIM Input Capture handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ *  @brief    Time One Pulse functions
+ *
+@verbatim
+  ==============================================================================
+                        ##### Time One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the Time One Pulse.
+    (+) Stop the Time One Pulse.
+    (+) Start the Time One Pulse and enable interrupt.
+    (+) Stop the Time One Pulse and disable interrupt.
+    (+) Start the Time One Pulse and enable DMA transfer.
+    (+) Stop the Time One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @param  htim: TIM OnePulse handle
+  * @param  OnePulseMode: Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the TIM One Pulse
+  * @param  htim: TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize TIM One Pulse MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channels to be disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+   __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
+ *  @brief    Time Encoder functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Time Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the Time Encoder.
+    (+) Stop the Time Encoder.
+    (+) Start the Time Encoder and enable interrupt.
+    (+) Stop the Time Encoder and disable interrupt.
+    (+) Start the Time Encoder and enable DMA transfer.
+    (+) Stop the Time Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @param  htim: TIM Encoder Interface handle
+  * @param  sConfig: TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
+{
+  uint32_t tmpsmcr = 0;
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS bits */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
+  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitialize the TIM Encoder interface
+  * @param  htim: TIM Encoder handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize TIM Encoder Interface MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim : TIM Encoder Interface handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+    }
+    break;
+    
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+    }
+    break;
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim : TIM Encoder Interface handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+   /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+    }
+    break;
+    
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+    }
+    break;
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim : TIM Encoder Interface handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim : TIM Encoder Interface handle
+  * @param  Channel : TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if(Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if(Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim : TIM Encoder Interface handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1: The destination Buffer address for IC1.
+  * @param  pData2: The destination Buffer address for IC2.
+  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+    }
+    break;
+
+    case TIM_CHANNEL_ALL:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+     /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    default:
+    break;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim : TIM Encoder Interface handle
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if(Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+  }
+  else if(Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ *  @brief    IRQ handler management
+ *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim: TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+        {
+          HAL_TIM_IC_CaptureCallback(htim);
+        }
+        /* Output compare event */
+        else
+        {
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+      {
+        HAL_TIM_IC_CaptureCallback(htim);
+      }
+      /* Output compare event */
+      else
+      {
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+      {
+        HAL_TIM_IC_CaptureCallback(htim);
+      }
+      /* Output compare event */
+      else
+      {
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+      {
+        HAL_TIM_IC_CaptureCallback(htim);
+      }
+      /* Output compare event */
+      else
+      {
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+      HAL_TIM_PeriodElapsedCallback(htim);
+    }
+  }
+  /* TIM Break input event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+      HAL_TIMEx_BreakCallback(htim);
+    }
+  }
+  /* TIM Trigger detection event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+      HAL_TIM_TriggerCallback(htim);
+    }
+  }
+  /* TIM commutation event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+      HAL_TIMEx_CommutationCallback(htim);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ *  @brief   	Peripheral Control functions
+ *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim: TIM Output Compare handle
+  * @param  sConfig: TIM Output Compare configuration structure
+  * @param  Channel : TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef* sConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+     /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+       /* Configure the TIM Channel 4 in Output Compare */
+       TIM_OC4_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+       /* Configure the TIM Channel 5 in Output Compare */
+       TIM_OC5_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+       /* Configure the TIM Channel 6 in Output Compare */
+       TIM_OC6_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim: TIM IC handle
+  * @param  sConfig: TIM Input Capture configuration structure
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+               sConfig->ICPolarity,
+               sConfig->ICSelection,
+               sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+               sConfig->ICPolarity,
+               sConfig->ICSelection,
+               sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+               sConfig->ICPolarity,
+               sConfig->ICSelection,
+               sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim: TIM PWM handle
+  * @param  sConfig: TIM PWM configuration structure
+  * @param  Channel : TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef* sConfig,
+                                            uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+     /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+     /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+    }
+    break;
+
+    case TIM_CHANNEL_5:
+    {
+       /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+     /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+     /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+    }
+    break;
+
+    case TIM_CHANNEL_6:
+    {
+       /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+     /* Configure the Channel 5 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+     /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim: TIM One Pulse handle
+  * @param  sConfig: TIM One Pulse configuration structure
+  * @param  OutputChannel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if(OutputChannel != InputChannel)
+  {
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Extract the Ouput compare configuration from sConfig structure */
+  temp1.OCMode = sConfig->OCMode;
+  temp1.Pulse = sConfig->Pulse;
+  temp1.OCPolarity = sConfig->OCPolarity;
+  temp1.OCNPolarity = sConfig->OCNPolarity;
+  temp1.OCIdleState = sConfig->OCIdleState;
+  temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+  {
+    case TIM_CHANNEL_1:
+    {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      TIM_OC1_SetConfig(htim->Instance, &temp1);
+    }
+    break;
+    case TIM_CHANNEL_2:
+    {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      TIM_OC2_SetConfig(htim->Instance, &temp1);
+    }
+    break;
+    default:
+    break;
+  }
+    switch (InputChannel)
+  {
+    case TIM_CHANNEL_1:
+    {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                        sConfig->ICSelection, sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+    /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+    htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+    }
+    break;
+    case TIM_CHANNEL_2:
+    {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                 sConfig->ICSelection, sConfig->ICFilter);
+
+      /* Reset the IC2PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+      /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+      htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+      /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+      htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim: TIM handle
+  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_DCR
+  * @param  BurstRequestSrc: TIM DMA Request sources
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer: The Buffer address.
+  * @param  BurstLength: DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((BurstBuffer == 0 ) && (BurstLength > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  switch(BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    default:
+    break;
+  }
+   /* configure the DMA Burst Mode */
+   htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+   /* Enable the TIM DMA Request */
+   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+   htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim: TIM handle
+  * @param  BurstRequestSrc: TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch(BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+    }
+    break;
+    case TIM_DMA_CC1:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+    }
+    break;
+    case TIM_DMA_CC2:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+    }
+    break;
+    case TIM_DMA_CC3:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+    }
+    break;
+    case TIM_DMA_CC4:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+    }
+    break;
+    case TIM_DMA_COM:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+    }
+    break;
+    case TIM_DMA_TRIGGER:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+    }
+    break;
+    default:
+    break;
+  }
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim: TIM handle
+  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_DCR
+  * @param  BurstRequestSrc: TIM DMA Request sources
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer: The Buffer address.
+  * @param  BurstLength: DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((BurstBuffer == 0 ) && (BurstLength > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  switch(BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+    }
+    break;
+    default:
+    break;
+  }
+
+  /* configure the DMA Burst Mode */
+  htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim: TIM handle
+  * @param  BurstRequestSrc: TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch(BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+    }
+    break;
+    case TIM_DMA_CC1:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+    }
+    break;
+    case TIM_DMA_CC2:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+    }
+    break;
+    case TIM_DMA_CC3:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+    }
+    break;
+    case TIM_DMA_CC4:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+    }
+    break;
+    case TIM_DMA_COM:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+    }
+    break;
+    case TIM_DMA_TRIGGER:
+    {
+      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+    }
+    break;
+    default:
+    break;
+  }
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim: TIM handle
+  * @param  EventSource: specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim: TIM handle
+  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  *            @arg TIM_Channel_5: TIM Channel 5
+  *            @arg TIM_Channel_6: TIM Channel 6
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  uint32_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Get the TIMx SMCR register value */
+      tmpsmcr = htim->Instance->SMCR;
+      
+      /* Clear the OCREF clear selection bit */
+      tmpsmcr &= ~TIM_SMCR_OCCS;
+
+      /* Clear the ETR Bits */
+      tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+      /* Set TIMx_SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+   }
+    break;
+
+    case TIM_CLEARINPUTSOURCE_OCREFCLR:
+    {
+      /* Clear the OCREF clear selection bit */
+      htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
+    }
+    break;
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+
+      /* Set the OCREF clear selection bit */
+      htim->Instance->SMCR |= TIM_SMCR_OCCS;
+    }
+    break;
+    
+  default:
+    break;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+      {
+        if(sClearInputConfig->ClearInputState != RESET)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+        }
+      }
+      break;
+    case TIM_CHANNEL_2:
+      {
+        if(sClearInputConfig->ClearInputState != RESET)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+        }
+      }
+    break;
+    case TIM_CHANNEL_3:
+      {
+        if(sClearInputConfig->ClearInputState != RESET)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+        }
+      }
+    break;
+    case TIM_CHANNEL_4:
+      {
+        if(sClearInputConfig->ClearInputState != RESET)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+        }
+      }
+    break;
+    case TIM_CHANNEL_5:
+      {
+        if(sClearInputConfig->ClearInputState != RESET)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
+        }
+      }
+    break;
+    case TIM_CHANNEL_6:
+      {
+        if(sClearInputConfig->ClearInputState != RESET)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
+        }
+      }
+    break;
+    default:
+    break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim: TIM handle
+  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+{
+  uint32_t tmpsmcr = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+  case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      /* Disable slave mode to clock the prescaler directly with the internal clock */
+      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+    }
+    break;
+
+  case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+      
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Get the TIMx SMCR register value */
+      tmpsmcr = htim->Instance->SMCR;
+      /* Reset the SMS and TS Bits */
+      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+    }
+    break;
+
+  case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+      
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+    }
+    break;
+
+  case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+      
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+    }
+    break;
+    
+  case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+       /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+    }
+    break;
+
+  case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+    }
+    break;
+    
+  case TIM_CLOCKSOURCE_ITR0:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+    }
+    break;
+    
+  case TIM_CLOCKSOURCE_ITR1:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
+    }
+    break;
+    
+  case TIM_CLOCKSOURCE_ITR2:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
+    }
+    break;
+    
+  case TIM_CLOCKSOURCE_ITR3:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+    }
+    break;
+
+  default:
+    break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim: TIM handle.
+  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim: TIM handle.
+  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the ) and the Slave
+  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+  
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);  
+
+  return HAL_OK;
+    }
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim: TIM handle.
+  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the ) and the Slave 
+  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, 
+                                                        TIM_SlaveConfigTypeDef * sSlaveConfig)
+    {
+      /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+  
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);  
+
+  return HAL_OK;
+    }
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim: TIM handle.
+  * @param  Channel : TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0;
+
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+  case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+  case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+  case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+  case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+  default:
+    break;
+  }
+
+  __HAL_UNLOCK(htim);
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ *  @brief    TIM Callbacks functions
+ *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) Timer Period elapsed callback
+   (+) Timer Output Compare callback
+   (+) Timer Input capture callback
+   (+) Timer Trigger callback
+   (+) Timer Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim : TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+
+}
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim : TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim : TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim : TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim : TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim : TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ *  @brief   Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim: TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim: TIM Ouput Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim: TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim: TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim: TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim: TIM Encoder handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma : pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  htim->State= HAL_TIM_STATE_READY;
+
+  HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma : pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  htim->State= HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma : pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  htim->State= HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+
+  HAL_TIM_IC_CaptureCallback(htim);
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma : pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  htim->State= HAL_TIM_STATE_READY;
+
+  HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma : pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  htim->State= HAL_TIM_STATE_READY;
+
+  HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx: TIM peripheral
+  * @param  Structure: TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1 = 0;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter(only for TIM1 and TIM8) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Time Ouput Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+
+   /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if(IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Time Ouput Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4);
+
+  if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if(IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Time Ouput Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8);
+
+  if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if(IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Time Ouput Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12);
+
+  if(IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+   /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Ouput Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16);
+
+  if(IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Ouput Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20);
+
+  if(IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                     TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+  uint32_t tmpsmcr = 0;
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+ 
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+  case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance, 
+                        sSlaveConfig->TriggerPrescaler, 
+                        sSlaveConfig->TriggerPolarity, 
+                        sSlaveConfig->TriggerFilter);
+    }
+    break;
+    
+  case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+  
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;    
+      
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+      
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;                               
+                               
+    }
+    break;
+    
+  case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+  
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+    }
+    break;
+    
+  case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+  
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                                sSlaveConfig->TriggerPolarity,
+                                sSlaveConfig->TriggerFilter);
+    }
+    break;
+    
+  case TIM_TS_ITR0:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+    
+  case TIM_TS_ITR1:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+    
+  case TIM_TS_ITR2:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+    
+  case TIM_TS_ITR3:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+       
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource: The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
+{
+  uint32_t tmpsmcr = 0;
+
+   /* Get the TIMx SMCR register value */
+   tmpsmcr = TIMx->SMCR;
+   /* Reset the TS Bits */
+   tmpsmcr &= ~TIM_SMCR_TS;
+   /* Set the Input Trigger source and the slave mode*/
+   tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
+   /* Write to TIMx SMCR */
+   TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr = 0;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << Channel;
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h
new file mode 100755
index 0000000..368389f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h
@@ -0,0 +1,1983 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tim.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_TIM_H
+#define __STM32L4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+                                     @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;    /*!< TIM clock filter
+                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct {
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                      This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct {
+  uint32_t  SlaveMode;      /*!< Slave mode selection
+                               This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                  This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;	      /*!< TIM off state in run mode
+                                         This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;	      /*!< TIM off state in IDLE mode
+                                         This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;	 	      /*!< TIM Lock level
+                                         This parameter can be a value of @ref TIM_Lock_level */
+  uint32_t DeadTime;	 	      /*!< TIM dead Time
+                                         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;	 	      /*!< TIM Break State
+                                         This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+  uint32_t BreakPolarity;             /*!< TIM Break input polarity
+                                         This parameter can be a value of @ref TIM_Break_Polarity */
+  uint32_t BreakFilter;               /*!< Specifies the break input filter.
+                                         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t Break2State;	 	      /*!< TIM Break2 State
+                                         This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+  uint32_t Break2Polarity;            /*!< TIM Break2 input polarity
+                                         This parameter can be a value of @ref TIM_Break2_Polarity */
+  uint32_t Break2Filter;              /*!< TIM break2 input filter.
+                                         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t AutomaticOutput;           /*!< TIM Automatic Output Enable state
+                                         This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
+}HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00    /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+typedef struct
+{
+  TIM_TypeDef              *Instance;     /*!< Register base address             */
+  TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
+  HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
+  DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
+                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef          Lock;          /*!< Locking object                    */
+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
+}TIM_HandleTypeDef;
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002)
+#define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    (0x00000000)
+#define TIM_DMABASE_CR2                    (0x00000001)
+#define TIM_DMABASE_SMCR                   (0x00000002)
+#define TIM_DMABASE_DIER                   (0x00000003)
+#define TIM_DMABASE_SR                     (0x00000004)
+#define TIM_DMABASE_EGR                    (0x00000005)
+#define TIM_DMABASE_CCMR1                  (0x00000006)
+#define TIM_DMABASE_CCMR2                  (0x00000007)
+#define TIM_DMABASE_CCER                   (0x00000008)
+#define TIM_DMABASE_CNT                    (0x00000009)
+#define TIM_DMABASE_PSC                    (0x0000000A)
+#define TIM_DMABASE_ARR                    (0x0000000B)
+#define TIM_DMABASE_RCR                    (0x0000000C)
+#define TIM_DMABASE_CCR1                   (0x0000000D)
+#define TIM_DMABASE_CCR2                   (0x0000000E)
+#define TIM_DMABASE_CCR3                   (0x0000000F)
+#define TIM_DMABASE_CCR4                   (0x00000010)
+#define TIM_DMABASE_BDTR                   (0x00000011)
+#define TIM_DMABASE_DCR                    (0x00000012)
+#define TIM_DMABASE_DMAR                   (0x00000013)
+#define TIM_DMABASE_OR1                    (0x00000014)
+#define TIM_DMABASE_CCMR3                  (0x00000015)
+#define TIM_DMABASE_CCR5                   (0x00000016)
+#define TIM_DMABASE_CCR6                   (0x00000017)
+#define TIM_DMABASE_OR2                    (0x00000018)
+#define TIM_DMABASE_OR3                    (0x00000019)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM  Extended Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2             (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4             (TIM_CR1_CKD_1)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE                  (TIM_CCMR1_OC1FE)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE            (TIM_CCER_CC1NE)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                               connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                               connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)                 /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      (TIM_DIER_UIE)
+#define TIM_IT_CC1                         (TIM_DIER_CC1IE)
+#define TIM_IT_CC2                         (TIM_DIER_CC2IE)
+#define TIM_IT_CC3                         (TIM_DIER_CC3IE)
+#define TIM_IT_CC4                         (TIM_DIER_CC4IE)
+#define TIM_IT_COM                         (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER                     (TIM_DIER_TIE)
+#define TIM_IT_BREAK                       (TIM_DIER_BIE)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source 
+  * @{
+  */  
+#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
+#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
+#define TIM_DMA_COM                        (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
+#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
+#define TIM_FLAG_CC5                       (TIM_SR_CC5IF)
+#define TIM_FLAG_CC6                       (TIM_SR_CC6IF)
+#define TIM_FLAG_COM                       (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
+#define TIM_FLAG_BREAK                     (TIM_SR_BIF)
+#define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
+#define TIM_FLAG_SYSTEM_BREAK              (TIM_SR_SBIF)
+#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
+#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
+#define TIM_CHANNEL_3                      ((uint32_t)0x0008)
+#define TIM_CHANNEL_4                      ((uint32_t)0x000C)
+#define TIM_CHANNEL_5                      ((uint32_t)0x0010)
+#define TIM_CHANNEL_6                      ((uint32_t)0x0014)
+#define TIM_CHANNEL_ALL                    ((uint32_t)0x003C)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define	TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
+#define	TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
+#define	TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
+#define	TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
+#define	TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
+#define	TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define	TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
+#define	TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define	TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define	TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                          /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE 	                 (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE                   ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE	 	                 (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE                   ((uint32_t)0x0000)
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF	                 ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1                    (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2                    (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3                    (TIM_BDTR_LOCK)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE                  ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH             (TIM_BDTR_BKP)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 ((uint32_t)0x00000000)
+#define TIM_BREAK2_ENABLE                  ((uint32_t)TIM_BDTR_BK2E)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             ((uint32_t)0x00000000)
+#define TIM_BREAK2POLARITY_HIGH            ((uint32_t)TIM_BDTR_BK2P)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_ENABLE         (TIM_BDTR_AOE)
+#define	TIM_AUTOMATICOUTPUT_DISABLE        ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE       (uint32_t)0x00000000  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)      /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define	TIM_TRGO_RESET            ((uint32_t)0x0000)
+#define	TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
+#define	TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
+#define	TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define	TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
+#define	TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define	TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define	TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define	TIM_TRGO2_RESET                          ((uint32_t)0x00000000)
+#define	TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
+#define	TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
+#define	TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define	TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
+#define	TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
+#define	TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
+#define	TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define	TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
+#define	TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
+#define	TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
+#define	TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define	TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
+#define	TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
+#define	TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
+#define	TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE        ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
+#define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
+#define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
+#define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
+
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0                        ((uint32_t)0x0000)
+#define TIM_TS_ITR1                        ((uint32_t)0x0010)
+#define TIM_TS_ITR2                        ((uint32_t)0x0020)
+#define TIM_TS_ITR3                        ((uint32_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
+#define TIM_TS_ETRF                        ((uint32_t)0x0070)
+#define TIM_TS_NONE                        ((uint32_t)0xFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_XORCOMBINATION    (TIM_CR2_TI1S)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       (0x00000000)
+#define TIM_DMABURSTLENGTH_2TRANSFERS      (0x00000100)
+#define TIM_DMABURSTLENGTH_3TRANSFERS      (0x00000200)
+#define TIM_DMABURSTLENGTH_4TRANSFERS      (0x00000300)
+#define TIM_DMABURSTLENGTH_5TRANSFERS      (0x00000400)
+#define TIM_DMABURSTLENGTH_6TRANSFERS      (0x00000500)
+#define TIM_DMABURSTLENGTH_7TRANSFERS      (0x00000600)
+#define TIM_DMABURSTLENGTH_8TRANSFERS      (0x00000700)
+#define TIM_DMABURSTLENGTH_9TRANSFERS      (0x00000800)
+#define TIM_DMABURSTLENGTH_10TRANSFERS     (0x00000900)
+#define TIM_DMABURSTLENGTH_11TRANSFERS     (0x00000A00)
+#define TIM_DMABURSTLENGTH_12TRANSFERS     (0x00000B00)
+#define TIM_DMABURSTLENGTH_13TRANSFERS     (0x00000C00)
+#define TIM_DMABURSTLENGTH_14TRANSFERS     (0x00000D00)
+#define TIM_DMABURSTLENGTH_15TRANSFERS     (0x00000E00)
+#define TIM_DMABURSTLENGTH_16TRANSFERS     (0x00000F00)
+#define TIM_DMABURSTLENGTH_17TRANSFERS     (0x00001000)
+#define TIM_DMABURSTLENGTH_18TRANSFERS     (0x00001100)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
+#define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
+#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
+#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR  SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__: TIM handle.
+  * @retval None
+  */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+                        do { \
+                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+                            { \
+                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+                            { \
+                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+                            } \
+                          } \
+                        } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+                        do { \
+                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+                          { \
+                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+                            { \
+                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+                            } \
+                            } \
+                        } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__: specifies the TIM Handle.
+  * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__: specifies the TIM Handle.
+  * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__: specifies the TIM Handle.
+  * @param  __DMA__: specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  *            @arg TIM_DMA_BREAK: Break DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__: specifies the TIM Handle.
+  * @param  __DMA__: specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  *            @arg TIM_DMA_BREAK: Break DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__: specifies the TIM Handle.
+  * @param  __FLAG__: specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__: specifies the TIM Handle.
+  * @param  __FLAG__: specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__: TIM handle
+  * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__: TIM handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__: TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __PRESC__: specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __COUNTER__: specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @retval None
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
+   ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __AUTORELOAD__: specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+                        do{                                                    \
+                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+                          } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @retval None
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
+   ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CKD__: specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1
+  *            @arg TIM_CLOCKDIVISION_DIV2
+  *            @arg TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+                        do{                                                    \
+                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
+                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
+                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
+                          } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @retval None
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
+   ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__: TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+                        do{                                                    \
+                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+                          } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__: TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval None
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__: TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__: specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__: TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval None
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+ ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__: TIM handle.
+  * @note  When the USR bit of the TIMx_CR1 register is set, only counter 
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+    ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__: TIM handle.
+  * @note  When the USR bit of the TIMx_CR1 register is reset, any of the 
+  *        following events generate an update interrupt or DMA request (if 
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+      ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+        
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__: TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__: Polarity for TIx source   
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+        do{                                                                     \
+          TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+          TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+        }while(0)
+          
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+  
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
+                                   ((__BASE__) == TIM_DMABASE_OR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_OR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_OR3))
+
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
+
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
+
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+	                                 ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xF)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFF)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                 || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                 || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32l4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
+ *  @brief    Time Base functions
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ *  @brief    Time Output Compare functions
+ * @{
+ */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
+ *  @brief    Time PWM functions
+ * @{
+ */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ *  @brief    Time Input Capture functions
+ * @{
+ */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ *  @brief    Time One Pulse functions
+ * @{
+ */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
+ *  @brief    Time Encoder functions
+ * @{
+ */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ *  @brief    IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ *  @brief   	Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ *  @brief    TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ *  @brief   Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+* @{
+*/
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+* @}
+*/ 
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c
new file mode 100755
index 0000000..39039e4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c
@@ -0,0 +1,2250 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Time OCRef clear configuration
+  *           + Timer remapping capabilities configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
+              Timer Hall Sensor Interface and the commutation event with the corresponding
+              Interrupt and DMA request if needed (Note that One Timer is used to interface
+             with the Hall sensor Interface and another Timer should be used to use
+             the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define BDTR_BKF_SHIFT (16)
+#define BDTR_BK2F_SHIFT (20)
+#define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000) 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Private functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @param  htim: TIM Encoder Interface handle
+  * @param  sConfig: TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the TIM Hall Sensor interface
+  * @param  htim: TIM Hall Sensor handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize TIM Hall Sensor MSP.
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim : TIM Hall Sensor handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+  /* Enable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim : TIM Hall Sensor handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim : TIM Hall Sensor handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim : TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim : TIM Hall Sensor handle
+  * @param  pData: The destination Buffer address.
+  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+   if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  /* Enable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel for Capture 1*/
+  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim : TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim : TIM OC handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+  
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+{
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim : TIM Output Compare handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim : TIM handle
+  * @param  Channel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+
+    default:
+    break;
+  }
+
+  /* Disable the complementary PWM output */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+  {
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim : TIM One Pulse handle
+  * @param  OutputChannel : TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Enable or disable channel grouping
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim: TIM handle
+  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource : the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim: TIM handle
+  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource : the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation Interrupt Request */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim: TIM handle
+  * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource : the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim: TIM handle.
+  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                      TIM_MasterConfigTypeDef * sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+ /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Reset the MSM Bit */
+  tmpsmcr &= ~TIM_SMCR_MSM;
+  /* Set master mode */
+  tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  /* Update TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim: TIM handle
+  * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+{
+  uint32_t tmpbdtr = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+  
+  /* Check input state */
+  __HAL_LOCK(htim);
+  
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+  the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
+  
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+    
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+  }
+  
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+  
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim: TIM handle.
+  * @param  BreakInput: Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig: Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+  uint32_t tmporx = 0;
+  uint32_t bkin_enable_mask = 0;
+  uint32_t bkin_polarity_mask = 0;
+  uint32_t bkin_enable_bitpos = 0;
+  uint32_t bkin_polarity_bitpos = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
+    defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+  {
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+  }
+#else
+   assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+  
+  /* Check input state */
+  __HAL_LOCK(htim);
+  
+  switch(sBreakInputConfig->Source)
+  {
+  case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM1_OR2_BKINE;
+      bkin_enable_bitpos = 0;
+      bkin_polarity_mask = TIM1_OR2_BKINP;
+      bkin_polarity_bitpos = 9;
+    }
+    break;
+  case TIM_BREAKINPUTSOURCE_COMP1:
+    {
+      bkin_enable_mask = TIM1_OR2_BKCMP1E;
+      bkin_enable_bitpos = 1;
+      bkin_polarity_mask = TIM1_OR2_BKCMP1P;
+      bkin_polarity_bitpos = 10;
+    }
+    break;
+  case TIM_BREAKINPUTSOURCE_COMP2:
+    {
+      bkin_enable_mask = TIM1_OR2_BKCMP2E;
+      bkin_enable_bitpos = 2;
+      bkin_polarity_mask = TIM1_OR2_BKCMP2P;
+      bkin_polarity_bitpos = 11;
+    }
+    break;
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
+    defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+  case TIM_BREAKINPUTSOURCE_DFSDM1:
+    {
+      bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
+      bkin_enable_bitpos = 8;
+    }
+    break;    
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+
+  default:
+    break;
+  }
+  
+  switch(BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+      {
+        /* Get the TIMx_OR2 register value */
+        tmporx = htim->Instance->OR2;
+        
+        /* Enable the break input */
+        tmporx &= ~bkin_enable_mask;
+        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+        
+        /* Set the break input polarity */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
+    defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+        if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+        {
+          tmporx &= ~bkin_polarity_mask;
+          tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+        }
+        
+        /* Set TIMx_OR2 */
+        htim->Instance->OR2 = tmporx;        
+      }
+        break;
+    case TIM_BREAKINPUT_BRK2:
+      {
+        /* Get the TIMx_OR3 register value */
+        tmporx = htim->Instance->OR3;
+        
+        /* Enable the break input */
+        tmporx &= ~bkin_enable_mask;
+        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+        
+        /* Set the break input polarity */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
+    defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+        if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+        {
+          tmporx &= ~bkin_polarity_mask;
+          tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+        }
+        
+        /* Set TIMx_OR3 */
+        htim->Instance->OR3 = tmporx;        
+      }
+      break;    
+  default:
+    break;
+  }
+  
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim: TIM handle.
+  * @param  Remap: specifies the TIM remapping source.
+  *
+  @if STM32L486xx
+  *         For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
+  *
+  *                   field1 can have the following values:
+  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM1_ETR_ADC3_NONE:           TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
+  *            @arg TIM_TIM1_ETR_ADC3_AWD1:           TIM1_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM1_ETR_ADC3_AWD2:           TIM1_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM1_ETR_ADC3_AWD3:           TIM1_ETR is connected to ADC3 AWD3
+  *
+  *                   field3 can have the following values:
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *                   field4 can have the following values:
+  *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
+  *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
+  *            @note  When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant 
+  @endif
+  @if STM32L443xx
+  *         For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):
+  *
+  *                   field1 can have the following values:
+  *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *                   field3 can have the following values:
+  *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
+  *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
+  *
+  *            @note  When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant 
+  *
+  @endif
+  @if STM32L486xx
+  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
+  *
+  *                   field1 can have the following values:
+  *            @arg TIM_TIM2_ITR1_TIM8_TRGO:          TIM2_ITR1 is connected to TIM8_TRGO
+  *            @arg TIM_TIM2_ITR1_OTG_FS_SOF:         TIM2_ITR1 is connected to OTG_FS SOF
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
+  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
+  *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
+  *
+  *                   field3 can have the following values:
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  @endif
+  @if STM32L443xx
+  *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
+  *
+  *                   field1 can have the following values:
+  *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1
+  *            @arg TIM_TIM2_ITR1_USB_SOF:            TIM2_ITR1 is connected to USB SOF
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
+  *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
+  *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
+  *
+  *                   field3 can have the following values:
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  *
+  @endif
+  @if STM32L486xx
+  *         For TIM3, the parameter is a combination 2 fields(field1 | field2):
+  *
+  *                   field1 can have the following values:
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM3_ETR_GPIO:                TIM3_ETR is connected to GPIO
+  *            @arg TIM_TIM3_ETR_COMP1:               TIM3_ETR is connected to COMP1 output
+  *
+  @endif
+  @if STM32L486xx
+  *         For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
+  *
+  *                   field1 can have the following values:
+  *            @arg TIM_TIM8_ETR_ADC2_NONE:          TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM8_ETR_ADC3_NONE:          TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
+  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
+  *
+  *                   field3 can have the following values:
+  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
+  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *
+  *                   field4 can have the following values:
+  *            @arg TIM_TIM8_ETR_COMP1:               TIM8_ETR is connected to COMP1 output
+  *            @arg TIM_TIM8_ETR_COMP2:               TIM8_ETR is connected to COMP2 output
+  *            @note  When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant 
+  *
+  @endif
+  *         For TIM15, the parameter is a combination of 3 fields (field1 | field2):
+  *
+  *                   field1 can have the following values:
+  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection 
+  *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
+  *            @arg TIM_TIM15_ENCODERMODE_TIM3:      TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
+  *            @arg TIM_TIM15_ENCODERMODE_TIM4:      TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
+  *
+  @if STM32L486xx
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  @endif
+  @if STM32L443xx
+  *         For TIM16, the parameter can have the following values:
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *            @arg TIM_TIM16_TI1_MSI:               TIM16 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)
+  *            @arg TIM_TIM16_TI1_HSE_32:            TIM16 TI1 is connected to HSE div 32  (note that HSE div 32 must be selected as RTC clock source)
+  *            @arg TIM_TIM16_TI1_MCO:               TIM16 TI1 is connected to MCO
+  *
+  @endif
+  @if STM32L486xx
+  *         For TIM17, the parameter can have the following values:
+  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_MSI:               TIM17 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)
+  *            @arg TIM_TIM17_TI1_HSE_32:            TIM17 TI1 is connected to HSE div 32
+  *            @arg TIM_TIM17_TI1_MCO:               TIM17 TI1 is connected to MCO
+  @endif
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  uint32_t tmpor1 = 0;
+  uint32_t tmpor2 = 0;
+  
+  __HAL_LOCK(htim);
+
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+  
+  /* Set ETR_SEL bit field (if required) */
+  if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
+  {
+    tmpor2 = htim->Instance->OR2;
+    tmpor2 &= ~TIMx_ETRSEL_MASK;
+    tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
+    
+    /* Set TIMx_OR2 */
+    htim->Instance->OR2 = tmpor2;        
+  }
+  
+  /* Set other remapping capabilities */
+  tmpor1 = Remap;
+  tmpor1 &= ~TIMx_ETRSEL_MASK;
+
+  /* Set TIMx_OR1 */
+  htim->Instance->OR1 = Remap;
+  
+  /* Set TIMx_OR1 */
+  htim->Instance->OR1 = tmpor1;        
+  
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim: TIM handle.
+  * @param  Channels: specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim : TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim : TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim: TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma : pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  htim->State= HAL_TIM_STATE_READY;
+
+  HAL_TIMEx_CommutationCallback(htim);
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp = 0;
+
+  tmp = TIM_CCER_CC1NE << Channel;
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |=  (uint32_t)(ChannelNState << Channel);
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h
new file mode 100755
index 0000000..61df2f1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h
@@ -0,0 +1,463 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_TIM_EX_H
+#define __STM32L4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  TIM Hall sensor Configuration Structure definition  
+  */
+
+typedef struct
+{
+                                  
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+                                                                   
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+                                  
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/** 
+  * @brief  TIM Break/Break2 input configuration   
+  */
+typedef struct {
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */
+} TIMEx_BreakInputConfigTypeDef;
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM  Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_ADC1_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ETR_ADC1_AWD1      (TIM1_OR1_ETR_ADC1_RMP_0)                             /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2      (TIM1_OR1_ETR_ADC1_RMP_1)                             /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM1_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ETR_ADC3_AWD1      (TIM1_OR1_ETR_ADC3_RMP_0)                             /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC3_AWD2      (TIM1_OR1_ETR_ADC3_RMP_1)                             /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+#define TIM_TIM1_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM1 TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1          (TIM1_OR1_TI1_RMP)                                    /* !< TIM1 TI1 is connected to COMP1 */
+#define TIM_TIM1_ETR_COMP1          (TIM1_OR2_ETRSEL_0)                                   /* !< TIM1_ETR is connected to COMP1 output */
+#define TIM_TIM1_ETR_COMP2          (TIM1_OR2_ETRSEL_1)                                   /* !< TIM1_ETR is connected to COMP2 output */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM2_ITR1_TIM8_TRGO     ((uint32_t)(0x00000000))                              /* !< TIM2_ITR1 is connected to TIM8_TRGO */
+#define TIM_TIM2_ITR1_OTG_FS_SOF    (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to OTG_FS SOF */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define TIM_TIM2_ITR1_NONE          ((uint32_t)(0x00000000))                              /* !< No internal trigger on TIM2_ITR1 */
+#define TIM_TIM2_ITR1_USB_SOF       (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to USB SOF */
+#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
+       /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define TIM_TIM2_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_LSE            (TIM2_OR1_ETR1_RMP)                                   /* !< TIM2_ETR is connected to LSE */
+#define TIM_TIM2_ETR_COMP1          (TIM2_OR2_ETRSEL_0)                                   /* !< TIM2_ETR is connected to COMP1 output */
+#define TIM_TIM2_ETR_COMP2          (TIM2_OR2_ETRSEL_1)                                   /* !< TIM2_ETR is connected to COMP2 output */
+#define TIM_TIM2_TI4_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2 TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1          (TIM2_OR1_TI4_RMP_0)                                  /* !< TIM2 TI4 is connected to COMP1 output */
+#define TIM_TIM2_TI4_COMP2          (TIM2_OR1_TI4_RMP_1)                                  /* !< TIM2 TI4 is connected to COMP2 output */
+#define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM3_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3 TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1          (TIM3_OR1_TI1_RMP_0)                                  /* !< TIM3 TI1 is connected to COMP1 output */
+#define TIM_TIM3_TI1_COMP2          (TIM3_OR1_TI1_RMP_1)                                  /* !< TIM3 TI1 is connected to COMP2 output */
+#define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
+#define TIM_TIM3_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1          (TIM3_OR2_ETRSEL_0)                                   /* !< TIM3_ETR is connected to COMP1 output */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM8_ETR_ADC2_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM8_ETR_ADC2_AWD1      (TIM8_OR1_ETR_ADC2_RMP_0)                             /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2      (TIM8_OR1_ETR_ADC2_RMP_1)                             /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3      (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0)   /* !< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM8_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM8_ETR_ADC3_AWD1      (TIM8_OR1_ETR_ADC3_RMP_0)                             /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC3_AWD2      (TIM8_OR1_ETR_ADC3_RMP_1)                             /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM8_ETR_COMP1          (TIM8_OR2_ETRSEL_0)                                   /* !< TIM8_ETR is connected to COMP1 output */
+#define TIM_TIM8_ETR_COMP2          (TIM8_OR2_ETRSEL_1)                                   /* !< TIM8_ETR is connected to COMP2 output */
+#define TIM_TIM8_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM8 TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2          (TIM8_OR1_TI1_RMP)                                    /* !< TIM8 TI1 is connected to COMP1 */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#define TIM_TIM15_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM15 TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_LSE           (TIM15_OR1_TI1_RMP)                                   /* !< TIM15 TI1 is connected to LSE */
+#define TIM_TIM15_ENCODERMODE_NONE  ((uint32_t)(0x00000000))                              /* !< No redirection */
+#define TIM_TIM15_ENCODERMODE_TIM2  (TIM15_OR1_ENCODER_MODE_0)                            /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM15_ENCODERMODE_TIM3  (TIM15_OR1_ENCODER_MODE_1)                            /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#define TIM_TIM16_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_LSI           (TIM16_OR1_TI1_RMP_0)                                 /* !< TIM16 TI1 is connected to LSI */
+#define TIM_TIM16_TI1_LSE           (TIM16_OR1_TI1_RMP_1)                                 /* !< TIM16 TI1 is connected to LSE */
+#define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM16_TI1_MSI           (TIM16_OR1_TI1_RMP_2)                                 /* !< TIM16 TI1 is connected to MSI */
+#define TIM_TIM16_TI1_HSE_32        (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to HSE div 32 */
+#define TIM_TIM16_TI1_MCO           (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1)           /* !< TIM16 TI1 is connected to MCO */
+#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
+       /* STM32L451xx || STM32L452xx || STM32L462xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM17_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_MSI           (TIM17_OR1_TI1_RMP_0)                                 /* !< TIM17 TI1 is connected to MSI */
+#define TIM_TIM17_TI1_HSE_32        (TIM17_OR1_TI1_RMP_1)                                 /* !< TIM17 TI1 is connected to HSE div 32 */
+#define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input TIM  Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     ((uint32_t)(0x00000001)) /* !< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    ((uint32_t)(0x00000002)) /* !< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_BREAKINPUTSOURCE_DFSDM1   ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM  Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     ((uint32_t)(0x00000001)) /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
+/**
+  * @}
+  */
+   
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
+#else
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 
+ *  @brief    Timer Hall Sensor functions
+ * @{
+ */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ *  @brief   Timer Complementary Output Compare functions
+ * @{
+ */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ *  @brief    Timer Complementary PWM functions
+ * @{
+ */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ *  @brief    Timer Complementary One Pulse functions
+ * @{
+ */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ *  @brief    Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+* @{
+*/
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+* @}
+*/
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c
new file mode 100755
index 0000000..d0aad5a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c
@@ -0,0 +1,872 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tsc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Touch Sensing Controller (TSC) peripheral:
+  *           + Initialization and De-initialization
+  *           + Channel IOs, Shield IOs and Sampling IOs configuration
+  *           + Start and Stop an acquisition
+  *           + Read acquisition result
+  *           + Interrupts and flags management
+  *         
+  @verbatim
+================================================================================
+                       ##### TSC specific features #####
+================================================================================
+  [..]
+  (#) Proven and robust surface charge transfer acquisition principle
+    
+  (#) Supports up to 3 capacitive sensing channels per group
+    
+  (#) Capacitive sensing channels can be acquired in parallel offering a very good
+      response time
+      
+  (#) Spread spectrum feature to improve system robustness in noisy environments
+   
+  (#) Full hardware management of the charge transfer acquisition sequence
+   
+  (#) Programmable charge transfer frequency
+   
+  (#) Programmable sampling capacitor I/O pin
+   
+  (#) Programmable channel I/O pin
+   
+  (#) Programmable max count value to avoid long acquisition when a channel is faulty
+   
+  (#) Dedicated end of acquisition and max count error flags with interrupt capability
+   
+  (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
+      components
+   
+  (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
+
+   
+                          ##### How to use this driver #####
+================================================================================
+  [..]
+    (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
+
+    (#) GPIO pins configuration
+      (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
+      (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
+           and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
+           using HAL_GPIO_Init() function.
+
+    (#) Interrupts configuration
+      (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority() 
+           and HAL_NVIC_EnableIRQ() and function.
+
+    (#) TSC configuration
+      (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
+
+ [..]   TSC peripheral alternate functions are mapped on AF9.
+ 
+  *** Acquisition sequence ***
+  ===================================
+  [..]
+    (+) Discharge all IOs using HAL_TSC_IODischarge() function.
+    (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
+        of the sampling capacitor and electrodes design.
+    (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
+    (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
+        If the synchronized mode is selected, the acquisition will start as soon as the signal
+        is received on the synchro pin.
+    (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
+        HAL_TSC_GetState() function or using WFI instruction for example.
+    (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
+    (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
+      
+  @endverbatim
+  ******************************************************************************
+
+    Table 1. IOs for the STM32L4xx devices
+    +--------------------------------+     
+    |       IOs    |   TSC functions | 
+    |--------------|-----------------|
+    |   PB12 (AF)  |   TSC_G1_IO1    | 
+    |   PB13 (AF)  |   TSC_G1_IO2    | 
+    |   PB14 (AF)  |   TSC_G1_IO3    | 
+    |   PB15 (AF)  |   TSC_G1_IO4    | 
+    |--------------|-----------------|
+    |   PB4 (AF)   |   TSC_G2_IO1    | 
+    |   PB5 (AF)   |   TSC_G2_IO2    | 
+    |   PB6 (AF)   |   TSC_G2_IO3    | 
+    |   PB7 (AF)   |   TSC_G2_IO4    | 
+    |--------------|-----------------|
+    |   PA15 (AF)  |   TSC_G3_IO1    | 
+    |   PC10 (AF)  |   TSC_G3_IO2    | 
+    |   PC11 (AF)  |   TSC_G3_IO3    | 
+    |   PC12 (AF)  |   TSC_G3_IO4    | 
+    |--------------|-----------------|
+    |   PC6 (AF)   |   TSC_G4_IO1    | 
+    |   PC7 (AF)   |   TSC_G4_IO2    | 
+    |   PC8 (AF)   |   TSC_G4_IO3    | 
+    |   PC9 (AF)   |   TSC_G4_IO4    | 
+    |--------------|-----------------|
+    |   PE10 (AF)  |   TSC_G5_IO1    | 
+    |   PE11 (AF)  |   TSC_G5_IO2    | 
+    |   PE12 (AF)  |   TSC_G5_IO3    | 
+    |   PE13 (AF)  |   TSC_G5_IO4    | 
+    |--------------|-----------------|
+    |   PD10 (AF)  |   TSC_G6_IO1    | 
+    |   PD11 (AF)  |   TSC_G6_IO2    | 
+    |   PD12 (AF)  |   TSC_G6_IO3    | 
+    |   PD13 (AF)  |   TSC_G6_IO4    | 
+    |--------------|-----------------|
+    |   PE2 (AF)   |   TSC_G7_IO1    | 
+    |   PE3 (AF)   |   TSC_G7_IO2    | 
+    |   PE4 (AF)   |   TSC_G7_IO3    | 
+    |   PE5 (AF)   |   TSC_G7_IO4    | 
+    |--------------|-----------------|
+    |   PF14 (AF)  |   TSC_G8_IO1    | 
+    |   PF15 (AF)  |   TSC_G8_IO2    | 
+    |   PG0 (AF)   |   TSC_G8_IO3    | 
+    |   PG1 (AF)   |   TSC_G8_IO4    | 
+    |--------------|-----------------|
+    |   PB10 (AF)  |   TSC_SYNC      | 
+    |   PD2 (AF)   |                 | 
+    +--------------------------------+
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TSC TSC
+  * @brief HAL TSC module driver
+  * @{
+  */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t TSC_extract_groups(uint32_t iomask);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Functions Exported Functions
+  * @{
+  */ 
+
+/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the TSC.
+      (+) De-initialize the TSC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the TSC peripheral according to the specified parameters 
+  *         in the TSC_InitTypeDef structure and initialize the associated handle.
+  * @param  htsc: TSC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
+{
+  /* Check TSC handle allocation */
+  if (htsc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
+  assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
+  assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
+  assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
+  assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
+  assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
+  assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
+  assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
+  assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
+  assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
+  assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+  if(htsc->State == HAL_TSC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htsc->Lock = HAL_UNLOCKED;
+  }
+
+  /* Initialize the TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+
+  /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+  HAL_TSC_MspInit(htsc);
+
+  /*--------------------------------------------------------------------------*/  
+  /* Set TSC parameters */
+
+  /* Enable TSC */
+  htsc->Instance->CR = TSC_CR_TSCE;
+  
+  /* Set all functions */
+  htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
+                         htsc->Init.CTPulseLowLength |
+                         (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) |
+                         htsc->Init.SpreadSpectrumPrescaler |
+                         htsc->Init.PulseGeneratorPrescaler |
+                         htsc->Init.MaxCountValue |
+                         htsc->Init.SynchroPinPolarity |
+                         htsc->Init.AcquisitionMode);
+
+  /* Spread spectrum */
+  if (htsc->Init.SpreadSpectrum == ENABLE)
+  {
+    htsc->Instance->CR |= TSC_CR_SSE;
+  }
+  
+  /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+  htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
+
+  /* Set channel and shield IOs */
+  htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
+  
+  /* Set sampling IOs */
+  htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
+  
+  /* Set the groups to be acquired */
+  htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
+  
+  /* Disable interrupts */
+  htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
+  
+  /* Clear flags */
+  htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
+
+  /*--------------------------------------------------------------------------*/
+  
+  /* Initialize the TSC state */
+  htsc->State = HAL_TSC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitialize the TSC peripheral registers to their default reset values.
+  * @param  htsc: TSC handle  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
+{
+  /* Check TSC handle allocation */
+  if (htsc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+   
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+ 
+  /* DeInit the low level hardware */
+  HAL_TSC_MspDeInit(htsc);
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the TSC MSP.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.  
+  * @retval None
+  */
+__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_MspInit could be implemented in the user file.
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the TSC MSP.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.  
+  * @retval None
+  */
+__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_MspDeInit could be implemented in the user file.
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief    Input and Output operation functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### IO Operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start acquisition in polling mode.
+      (+) Start acquisition in interrupt mode.
+      (+) Stop conversion in polling mode.
+      (+) Stop conversion in interrupt mode.
+      (+) Poll for acquisition completed.
+      (+) Get group acquisition status.
+      (+) Get group acquisition value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the acquisition.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+
+  /* Clear interrupts */
+  __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+  /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+  if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+  {
+    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  }
+  else
+  {
+    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+  }
+  
+  /* Launch the acquisition */
+  __HAL_TSC_START_ACQ(htsc);
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the acquisition in interrupt mode.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+  
+  /* Enable end of acquisition interrupt */
+  __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
+
+  /* Enable max count error interrupt (optional) */
+  if (htsc->Init.MaxCountInterrupt == ENABLE)
+  {
+    __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
+  }
+  else
+  {
+    __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
+  }
+
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+  
+  /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+  if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+  {
+    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  }
+  else
+  {
+    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+  }
+  
+  /* Launch the acquisition */
+  __HAL_TSC_START_ACQ(htsc);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the acquisition previously launched in polling mode.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Stop the acquisition */
+  __HAL_TSC_STOP_ACQ(htsc);
+
+  /* Set touch sensing IOs in low power mode (output push-pull) */
+  __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the acquisition previously launched in interrupt mode.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Stop the acquisition */
+  __HAL_TSC_STOP_ACQ(htsc);
+  
+  /* Set touch sensing IOs in low power mode (output push-pull) */
+  __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  
+  /* Disable interrupts */
+  __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start acquisition and wait until completion.
+  * @note   There is no need of a timeout parameter as the max count error is already
+  *         managed by the TSC peripheral.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Check end of acquisition */
+  while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
+  {
+    /* The timeout (max count error) is managed by the TSC peripheral itself. */
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the acquisition status for a group.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  gx_index: Index of the group
+  * @retval Group status
+  */
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+  /* Return the group status */ 
+  return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
+}
+
+/**
+  * @brief  Get the acquisition measure for a group.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  gx_index: Index of the group
+  * @retval Acquisition measure
+  */
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{       
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+  /* Return the group acquisition counter */ 
+  return htsc->Instance->IOGXCR[gx_index];
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure TSC IOs
+      (+) Discharge TSC IOs
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure TSC IOs.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  config: pointer to the configuration structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ 
+  /* Process locked */
+  __HAL_LOCK(htsc);
+
+  /* Stop acquisition */
+  __HAL_TSC_STOP_ACQ(htsc);
+
+  /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+  htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
+
+  /* Set channel and shield IOs */
+  htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
+  
+  /* Set sampling IOs */
+  htsc->Instance->IOSCR = config->SamplingIOs;
+  
+  /* Set groups to be acquired */
+  htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
+    
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Discharge TSC IOs.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  choice: enable or disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
+{       
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  if (choice == ENABLE)
+  {
+    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  }
+  else
+  {
+    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return the group acquisition counter */ 
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ *  @brief   Peripheral State and Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Get TSC state.
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TSC handle state.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL state
+  */
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  
+  if (htsc->State == HAL_TSC_STATE_BUSY)
+  {
+    /* Check end of acquisition flag */
+    if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+    {
+      /* Check max count error flag */
+      if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+      {
+        /* Change TSC state */
+        htsc->State = HAL_TSC_STATE_ERROR;
+      }
+      else
+      {
+        /* Change TSC state */
+        htsc->State = HAL_TSC_STATE_READY;
+      }
+    }
+  }
+  
+  /* Return TSC state */
+  return htsc->State;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */   
+
+/**
+  * @brief  Handle TSC interrupt request.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval None
+  */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Check if the end of acquisition occurred */
+  if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+  {
+    /* Clear EOA flag */
+    __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
+  }
+  
+  /* Check if max count error occurred */
+  if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+  {
+    /* Clear MCE flag */
+    __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
+    /* Change TSC state */
+    htsc->State = HAL_TSC_STATE_ERROR;
+    /* Conversion completed callback */
+    HAL_TSC_ErrorCallback(htsc);
+  }
+  else
+  {
+    /* Change TSC state */
+    htsc->State = HAL_TSC_STATE_READY;
+    /* Conversion completed callback */
+    HAL_TSC_ConvCpltCallback(htsc);
+  }
+}
+
+/**
+  * @brief  Acquisition completed callback in non-blocking mode.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval None
+  */
+__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_ConvCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Error callback in non-blocking mode.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval None
+  */
+__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_ErrorCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TSC_Private_Functions Private Functions
+  * @{
+  */
+  
+/**
+  * @brief  Utility function used to set the acquired groups mask.
+  * @param  iomask: Channels IOs mask
+  * @retval Acquired groups mask
+  */
+static uint32_t TSC_extract_groups(uint32_t iomask)
+{
+  uint32_t groups = 0;
+  uint32_t idx;
+  
+  for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++)
+  {
+    if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET)
+    {
+      groups |= ((uint32_t)1 << idx);
+    }
+  }
+  
+  return groups;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h
new file mode 100755
index 0000000..f1c3386
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h
@@ -0,0 +1,726 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tsc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of TSC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_TSC_H
+#define __STM32L4xx_HAL_TSC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TSC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TSC_Exported_Types TSC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief TSC state structure definition  
+  */ 
+typedef enum
+{
+  HAL_TSC_STATE_RESET  = 0x00, /*!< TSC registers have their reset value */
+  HAL_TSC_STATE_READY  = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
+  HAL_TSC_STATE_BUSY   = 0x02, /*!< TSC initialization or acquisition is on-going */
+  HAL_TSC_STATE_ERROR  = 0x03  /*!< Acquisition is completed with max count error */
+} HAL_TSC_StateTypeDef;
+
+/** 
+  * @brief TSC group status structure definition  
+  */ 
+typedef enum
+{
+  TSC_GROUP_ONGOING   = 0x00, /*!< Acquisition on group is on-going or not started */
+  TSC_GROUP_COMPLETED = 0x01  /*!< Acquisition on group is completed with success (no max count error) */
+} TSC_GroupStatusTypeDef;
+
+/** 
+  * @brief TSC init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length 
+                                         This parameter can be a value of @ref TSC_CTPulseHL_Config  */
+  uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length
+                                         This parameter can be a value of @ref TSC_CTPulseLL_Config  */
+  uint32_t SpreadSpectrum;          /*!< Spread spectrum activation
+                                         This parameter can be a value of @ref TSC_CTPulseLL_Config  */
+  uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
+                                         This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
+  uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
+                                         This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
+  uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
+                                         This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
+  uint32_t MaxCountValue;           /*!< Max count value
+                                         This parameter can be a value of @ref TSC_MaxCount_Value  */
+  uint32_t IODefaultMode;           /*!< IO default mode
+                                         This parameter can be a value of @ref TSC_IO_Default_Mode  */
+  uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity
+                                         This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
+  uint32_t AcquisitionMode;         /*!< Acquisition mode
+                                         This parameter can be a value of @ref TSC_Acquisition_Mode  */
+  uint32_t MaxCountInterrupt;       /*!< Max count interrupt activation
+                                         This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ChannelIOs;              /*!< Channel IOs mask */
+  uint32_t ShieldIOs;               /*!< Shield IOs mask */
+  uint32_t SamplingIOs;             /*!< Sampling IOs mask */
+} TSC_InitTypeDef;
+
+/** 
+  * @brief TSC IOs configuration structure definition  
+  */ 
+typedef struct
+{
+  uint32_t ChannelIOs;  /*!< Channel IOs mask */
+  uint32_t ShieldIOs;   /*!< Shield IOs mask */
+  uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_IOConfigTypeDef;
+
+/** 
+  * @brief  TSC handle Structure definition  
+  */ 
+typedef struct
+{
+  TSC_TypeDef               *Instance; /*!< Register base address */
+  TSC_InitTypeDef           Init;      /*!< Initialization parameters */
+  __IO HAL_TSC_StateTypeDef State;     /*!< Peripheral state */
+  HAL_LockTypeDef           Lock;      /*!< Lock feature */
+} TSC_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
+  * @{
+  */
+
+/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
+  * @{
+  */
+#define TSC_CTPH_1CYCLE   ((uint32_t)((uint32_t) 0 << 28))
+#define TSC_CTPH_2CYCLES  ((uint32_t)((uint32_t) 1 << 28))
+#define TSC_CTPH_3CYCLES  ((uint32_t)((uint32_t) 2 << 28))
+#define TSC_CTPH_4CYCLES  ((uint32_t)((uint32_t) 3 << 28))
+#define TSC_CTPH_5CYCLES  ((uint32_t)((uint32_t) 4 << 28))
+#define TSC_CTPH_6CYCLES  ((uint32_t)((uint32_t) 5 << 28))
+#define TSC_CTPH_7CYCLES  ((uint32_t)((uint32_t) 6 << 28))
+#define TSC_CTPH_8CYCLES  ((uint32_t)((uint32_t) 7 << 28))
+#define TSC_CTPH_9CYCLES  ((uint32_t)((uint32_t) 8 << 28))
+#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
+#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
+#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
+#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
+#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
+#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
+#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
+  * @{
+  */
+#define TSC_CTPL_1CYCLE   ((uint32_t)((uint32_t) 0 << 24))
+#define TSC_CTPL_2CYCLES  ((uint32_t)((uint32_t) 1 << 24))
+#define TSC_CTPL_3CYCLES  ((uint32_t)((uint32_t) 2 << 24))
+#define TSC_CTPL_4CYCLES  ((uint32_t)((uint32_t) 3 << 24))
+#define TSC_CTPL_5CYCLES  ((uint32_t)((uint32_t) 4 << 24))
+#define TSC_CTPL_6CYCLES  ((uint32_t)((uint32_t) 5 << 24))
+#define TSC_CTPL_7CYCLES  ((uint32_t)((uint32_t) 6 << 24))
+#define TSC_CTPL_8CYCLES  ((uint32_t)((uint32_t) 7 << 24))
+#define TSC_CTPL_9CYCLES  ((uint32_t)((uint32_t) 8 << 24))
+#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
+#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
+#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
+#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
+#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
+#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
+#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
+  * @{
+  */
+#define TSC_SS_PRESC_DIV1 ((uint32_t)0)  
+#define TSC_SS_PRESC_DIV2  (TSC_CR_SSPSC) 
+/**
+  * @}
+  */
+
+/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
+  * @{
+  */
+#define TSC_PG_PRESC_DIV1   ((uint32_t)(0 << 12))
+#define TSC_PG_PRESC_DIV2   ((uint32_t)(1 << 12))
+#define TSC_PG_PRESC_DIV4   ((uint32_t)(2 << 12))
+#define TSC_PG_PRESC_DIV8   ((uint32_t)(3 << 12))
+#define TSC_PG_PRESC_DIV16  ((uint32_t)(4 << 12))
+#define TSC_PG_PRESC_DIV32  ((uint32_t)(5 << 12))
+#define TSC_PG_PRESC_DIV64  ((uint32_t)(6 << 12))
+#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_MaxCount_Value Max Count Value
+  * @{
+  */
+#define TSC_MCV_255   ((uint32_t)(0 << 5))
+#define TSC_MCV_511   ((uint32_t)(1 << 5))
+#define TSC_MCV_1023  ((uint32_t)(2 << 5))
+#define TSC_MCV_2047  ((uint32_t)(3 << 5))
+#define TSC_MCV_4095  ((uint32_t)(4 << 5))
+#define TSC_MCV_8191  ((uint32_t)(5 << 5))
+#define TSC_MCV_16383 ((uint32_t)(6 << 5))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_IO_Default_Mode IO Default Mode
+  * @{
+  */
+#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
+#define TSC_IODEF_IN_FLOAT   (TSC_CR_IODEF)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
+  * @{
+  */
+#define TSC_SYNC_POLARITY_FALLING  ((uint32_t)0)
+#define TSC_SYNC_POLARITY_RISING   (TSC_CR_SYNCPOL)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Acquisition_Mode Acquisition Mode
+  * @{
+  */
+#define TSC_ACQ_MODE_NORMAL  ((uint32_t)0)
+#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_IO_Mode IO Mode
+  * @{
+  */
+#define TSC_IOMODE_UNUSED   ((uint32_t)0)
+#define TSC_IOMODE_CHANNEL  ((uint32_t)1)
+#define TSC_IOMODE_SHIELD   ((uint32_t)2)
+#define TSC_IOMODE_SAMPLING ((uint32_t)3)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_interrupts_definition Interrupts definition
+  * @{
+  */
+#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)  
+#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) 
+/**
+  * @}
+  */
+
+/** @defgroup TSC_flags_definition Flags definition
+  * @{
+  */
+#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
+#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Group_definition Group definition
+  * @{
+  */
+#define TSC_NB_OF_GROUPS (8)
+
+#define TSC_GROUP1 ((uint32_t)0x00000001)
+#define TSC_GROUP2 ((uint32_t)0x00000002)
+#define TSC_GROUP3 ((uint32_t)0x00000004)
+#define TSC_GROUP4 ((uint32_t)0x00000008)
+#define TSC_GROUP5 ((uint32_t)0x00000010)
+#define TSC_GROUP6 ((uint32_t)0x00000020)
+#define TSC_GROUP7 ((uint32_t)0x00000040)
+#define TSC_GROUP8 ((uint32_t)0x00000080)
+#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
+
+#define TSC_GROUP1_IDX ((uint32_t)0)
+#define TSC_GROUP2_IDX ((uint32_t)1)
+#define TSC_GROUP3_IDX ((uint32_t)2)
+#define TSC_GROUP4_IDX ((uint32_t)3)
+#define TSC_GROUP5_IDX ((uint32_t)4)
+#define TSC_GROUP6_IDX ((uint32_t)5)
+#define TSC_GROUP7_IDX ((uint32_t)6)
+#define TSC_GROUP8_IDX ((uint32_t)7)
+
+#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
+#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
+#define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
+#define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
+#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
+
+#define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
+#define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
+#define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
+#define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
+#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
+
+#define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
+#define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
+#define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
+#define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
+#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
+
+#define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
+#define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
+#define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
+#define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
+#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
+
+#define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
+#define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
+#define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
+#define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
+#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
+
+#define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
+#define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
+#define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
+#define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
+#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
+
+#define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
+#define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
+#define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
+#define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
+#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
+
+#define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
+#define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
+#define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
+#define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
+#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
+
+#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+  * @{
+  */
+
+/** @brief Reset TSC handle state.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+
+/**
+  * @brief Enable the TSC peripheral.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+
+/**
+  * @brief Disable the TSC peripheral.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
+
+/**
+  * @brief Start acquisition.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+
+/**
+  * @brief Stop acquisition.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
+
+/**
+  * @brief Set IO default mode to output push-pull low.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
+
+/**
+  * @brief Set IO default mode to input floating.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+
+/**
+  * @brief Set synchronization polarity to falling edge.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
+
+/**
+  * @brief Set synchronization polarity to rising edge and high level.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+
+/**
+  * @brief Enable TSC interrupt.
+  * @param  __HANDLE__: TSC handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief Disable TSC interrupt.
+  * @param  __HANDLE__: TSC handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
+
+/** @brief Check whether the specified TSC interrupt source is enabled or not.
+  * @param  __HANDLE__: TSC Handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief Check whether the specified TSC flag is set or not.
+  * @param  __HANDLE__: TSC handle
+  * @param  __FLAG__: TSC flag
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+  * @brief Clear the TSC's pending flag.
+  * @param  __HANDLE__: TSC handle
+  * @param  __FLAG__: TSC flag
+  * @retval None
+  */
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief Enable schmitt trigger hysteresis on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable schmitt trigger hysteresis on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Open analog switch on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Close analog switch on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Enable a group of IOs in channel mode.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable a group of channel IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Enable a group of IOs in sampling mode.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable a group of sampling IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Enable acquisition groups.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_MASK__: Groups mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
+
+/**
+  * @brief Disable acquisition groups.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_MASK__: Groups mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
+
+/** @brief Gets acquisition group status.
+  * @param  __HANDLE__: TSC Handle
+  * @param  __GX_INDEX__: Group index
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
+  * @{
+  */
+
+#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
+                          ((VAL) == TSC_CTPH_2CYCLES) || \
+                          ((VAL) == TSC_CTPH_3CYCLES) || \
+                          ((VAL) == TSC_CTPH_4CYCLES) || \
+                          ((VAL) == TSC_CTPH_5CYCLES) || \
+                          ((VAL) == TSC_CTPH_6CYCLES) || \
+                          ((VAL) == TSC_CTPH_7CYCLES) || \
+                          ((VAL) == TSC_CTPH_8CYCLES) || \
+                          ((VAL) == TSC_CTPH_9CYCLES) || \
+                          ((VAL) == TSC_CTPH_10CYCLES) || \
+                          ((VAL) == TSC_CTPH_11CYCLES) || \
+                          ((VAL) == TSC_CTPH_12CYCLES) || \
+                          ((VAL) == TSC_CTPH_13CYCLES) || \
+                          ((VAL) == TSC_CTPH_14CYCLES) || \
+                          ((VAL) == TSC_CTPH_15CYCLES) || \
+                          ((VAL) == TSC_CTPH_16CYCLES))
+
+#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
+                          ((VAL) == TSC_CTPL_2CYCLES) || \
+                          ((VAL) == TSC_CTPL_3CYCLES) || \
+                          ((VAL) == TSC_CTPL_4CYCLES) || \
+                          ((VAL) == TSC_CTPL_5CYCLES) || \
+                          ((VAL) == TSC_CTPL_6CYCLES) || \
+                          ((VAL) == TSC_CTPL_7CYCLES) || \
+                          ((VAL) == TSC_CTPL_8CYCLES) || \
+                          ((VAL) == TSC_CTPL_9CYCLES) || \
+                          ((VAL) == TSC_CTPL_10CYCLES) || \
+                          ((VAL) == TSC_CTPL_11CYCLES) || \
+                          ((VAL) == TSC_CTPL_12CYCLES) || \
+                          ((VAL) == TSC_CTPL_13CYCLES) || \
+                          ((VAL) == TSC_CTPL_14CYCLES) || \
+                          ((VAL) == TSC_CTPL_15CYCLES) || \
+                          ((VAL) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
+
+#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
+
+#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
+                              ((VAL) == TSC_PG_PRESC_DIV2) || \
+                              ((VAL) == TSC_PG_PRESC_DIV4) || \
+                              ((VAL) == TSC_PG_PRESC_DIV8) || \
+                              ((VAL) == TSC_PG_PRESC_DIV16) || \
+                              ((VAL) == TSC_PG_PRESC_DIV32) || \
+                              ((VAL) == TSC_PG_PRESC_DIV64) || \
+                              ((VAL) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
+                         ((VAL) == TSC_MCV_511) || \
+                         ((VAL) == TSC_MCV_1023) || \
+                         ((VAL) == TSC_MCV_2047) || \
+                         ((VAL) == TSC_MCV_4095) || \
+                         ((VAL) == TSC_MCV_8191) || \
+                         ((VAL) == TSC_MCV_16383))
+
+#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
+
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
+
+#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
+
+#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
+                            ((VAL) == TSC_IOMODE_CHANNEL) || \
+                            ((VAL) == TSC_IOMODE_SHIELD) || \
+                            ((VAL) == TSC_IOMODE_SAMPLING))
+
+#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/  
+/** @addtogroup TSC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */   
+/******* TSC IRQHandler and Callbacks used in Interrupt mode */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_TSC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c
new file mode 100755
index 0000000..206c426
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c
@@ -0,0 +1,2783 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_uart.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) UART interrupts handling:
+              -@@-  The specific UART interrupts (Transmission complete interrupt,
+                RXNE interrupt and Error Interrupts) are managed using the macros
+                __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+        in the huart handle AdvancedInit structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+        by calling the HAL_LIN_Init() API.
+
+    (#) For the UART Multiprocessor mode, initialize the UART registers
+        by calling the HAL_MultiProcessor_Init() API.
+
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    [..]
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+        calling the customized HAL_UART_MspInit() API.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+#define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define UART_LPUART_BRR_MIN           ((uint32_t)0x00000300)  /* LPUART BRR minimum authorized value */
+#define UART_LPUART_BRR_MAX           ((uint32_t)0x000FFFFF)  /* LPUART BRR maximum authorized value */                                                                      
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+  * @{
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+    and UART multiprocessor mode configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
+  8-bit or 9-bit), the possible UART formats are listed in the 
+  following table.
+  
+  Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if(huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Initialize the half-duplex mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check UART instance */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+  if(huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the LIN mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle .
+  * @param huart: UART handle.
+  * @param BreakDetectLength: specifies the LIN break detection length.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  /* LIN mode limited to 16-bit oversampling only */
+  if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    return HAL_ERROR;
+  }
+  /* LIN mode limited to 8-bit data length */
+  if(huart->Init.WordLength != UART_WORDLENGTH_8B)
+  {
+    return HAL_ERROR;
+  }
+
+  if(huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In LIN mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the multiprocessor mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart: UART handle.
+  * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod: specifies the UART wakeup method.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+  * @note  If the user resorts to idle line detection wake up, the Address parameter
+  *        is useless and ignored by the initialization function.
+  * @note  If the user resorts to address mark wake up, the address length detection
+  *        is configured by default to 4 bits only. For the UART to be able to
+  *        manage 6-, 7- or 8-bit long addresses detection, the API
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+  *        HAL_MultiProcessor_Init().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the wake up method parameter */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+  if(huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In multiprocessor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+  {
+    /* If address mark wake up method is chosen, set the USART address node */
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+  }
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief DeInitialize the UART peripheral.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  huart->Instance->CR1 = 0x0;
+  huart->Instance->CR2 = 0x0;
+  huart->Instance->CR3 = 0x0;
+
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState    = HAL_UART_STATE_RESET;
+  huart->RxState   = HAL_UART_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the UART MSP.
+  * @param huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the UART MSP.
+  * @param huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  * @brief UART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @param huart: UART handle.
+  * @param pData: Pointer to data buffer.
+  * @param Size: Amount of data to be sent.
+  * @param Timeout: Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tickstart = 0;
+
+  /* Check that a Tx process is not already ongoing */
+  if(huart->gState == HAL_UART_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+    while(huart->TxXferCount > 0)
+    {
+      huart->TxXferCount--;
+      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pData;
+        huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+        pData += 2;
+      }
+      else
+      {
+        huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+      }
+    }
+    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @param huart: UART handle.
+  * @param pData: pointer to data buffer.
+  * @param Size: amount of data to be received.
+  * @param Timeout: Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint16_t uhMask;
+  uint32_t tickstart = 0;
+
+  /* Check that a Rx process is not already ongoing */
+  if(huart->RxState == HAL_UART_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* as long as data have to be received */
+    while(huart->RxXferCount > 0)
+    {
+      huart->RxXferCount--;
+      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pData ;
+        *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+        pData +=2;
+      }
+      else
+      {
+        *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+      }
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @param huart: UART handle.
+  * @param pData: pointer to data buffer.
+  * @param Size: amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if(huart->gState == HAL_UART_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Transmit Data Register Empty Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @param huart: UART handle.
+  * @param pData: pointer to data buffer.
+  * @param Size: amount of data to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(huart->RxState == HAL_UART_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pRxBuffPtr = pData;
+    huart->RxXferSize = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART Parity Error and Data Register not empty Interrupts */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @param huart: UART handle.
+  * @param pData: pointer to data buffer.
+  * @param Size: amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if(huart->gState == HAL_UART_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the UART transmit DMA channel */
+    HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @param huart: UART handle.
+  * @param pData: pointer to data buffer.
+  * @param Size: amount of data to be received.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(huart->RxState == HAL_UART_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pRxBuffPtr = pData;
+    huart->RxXferSize = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+  {
+    /* Disable the UART DMA Tx request */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  if(huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: 
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete  
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of 
+     the stream and the corresponding call back is executed. */
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if(huart->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmatx);
+    }
+
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if(huart->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmarx);
+    }
+
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(huart->hdmatx);
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(huart->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0; 
+  huart->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(huart->hdmatx);
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0; 
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(huart->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the UART DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0; 
+    huart->RxXferCount = 0;
+
+    /* Reset errorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback : 
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0; 
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0; 
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback : 
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0; 
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle UART interrupt request.
+  * @param huart: UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+  if (errorflags == RESET)
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      UART_Receive_IT(huart);
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  cr3its = READ_REG(huart->Instance->CR3);
+  if(   (errorflags != RESET)
+     && (   ((cr3its & USART_CR3_EIE) != RESET)
+         || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+    
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* Call UART Error Call back function if need be --------------------------*/
+    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        UART_Receive_IT(huart);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
+          (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Disable the UART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx channel */
+          if(huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback : 
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_UART_ErrorCallback(huart);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_UART_ErrorCallback(huart);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_UART_ErrorCallback(huart);
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  cr3its = READ_REG(huart->Instance->CR3);
+  if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
+  {
+    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
+    /* Set the UART state ready to be able to start again the process */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+    HAL_UARTEx_WakeupCallback(huart);
+    return;
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    UART_Transmit_IT(huart);
+    return;
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief UART error callback.
+  * @param huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the UART.
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+     (+) UART_SetConfig() API configures the UART peripheral
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+     (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+  * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+  *         as it may not have been in mute mode at this very moment).
+  * @param  huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Enter UART mute mode (means UART actually enters mute mode).
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+  * @param huart: UART handle.
+  * @retval None
+  */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+  * @brief  Enable the UART transmitter and disable the UART receiver.
+  * @param  huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the UART receiver and disable the UART transmitter.
+  * @param  huart: UART handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+  huart->gState = HAL_UART_STATE_READY;
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Transmit break characters.
+  * @param  huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ *  @brief   UART Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the UART handle state.
+      (+) Return the UART handle error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the UART handle state.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+  uint32_t temp1= 0x00, temp2 = 0x00;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART handle error code.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+*/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief Configure the UART peripheral.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg                     = 0x00000000;
+  UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
+  uint16_t brrtemp                    = 0x0000;
+  uint16_t usartdiv                   = 0x0000;
+  HAL_StatusTypeDef ret               = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  if(UART_INSTANCE_LOWPOWER(huart))
+  {
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+  }
+  else
+  {
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+  }
+
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+   *  the UART Word Length, Parity, Mode and oversampling:
+   *  set the M bits according to huart->Init.WordLength value
+   *  set PCE and PS bits according to huart->Init.Parity value
+   *  set TE and RE bits according to huart->Init.Mode value
+   *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+  MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+   * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+   * - UART HardWare Flow Control: set CTSE and RTSE bits according
+   *   to huart->Init.HwFlowCtl value
+   * - one-bit sampling method versus three samples' majority rule according
+   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+  }
+  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+
+  /* Check LPUART instance */
+  if(UART_INSTANCE_LOWPOWER(huart))
+  {
+    /* Retrieve frequency clock */
+    tmpreg = 0;
+
+    switch (clocksource)
+    {
+    case UART_CLOCKSOURCE_PCLK1:
+      tmpreg = HAL_RCC_GetPCLK1Freq();
+      break;
+    case UART_CLOCKSOURCE_HSI:
+      tmpreg = (uint32_t) HSI_VALUE;
+      break;
+    case UART_CLOCKSOURCE_SYSCLK:
+      tmpreg = HAL_RCC_GetSysClockFreq();
+      break;
+    case UART_CLOCKSOURCE_LSE:
+      tmpreg = (uint32_t) LSE_VALUE;
+      break;
+    case UART_CLOCKSOURCE_UNDEFINED:
+    default:
+        ret = HAL_ERROR;
+      break;
+    }
+
+    /* if proper clock source reported */
+    if (tmpreg != 0)
+    {
+      /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ( (tmpreg < (3 * huart->Init.BaudRate) ) ||
+           (tmpreg > (4096 * huart->Init.BaudRate) ))
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+        switch (clocksource)
+        {
+        case UART_CLOCKSOURCE_PCLK1:
+          tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+          break;
+        case UART_CLOCKSOURCE_HSI:
+          tmpreg = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate));
+          break;
+        case UART_CLOCKSOURCE_SYSCLK:
+          tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+          break;
+        case UART_CLOCKSOURCE_LSE:
+          tmpreg = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate));
+          break;
+        case UART_CLOCKSOURCE_UNDEFINED:
+        default:
+          ret = HAL_ERROR;
+          break;
+        }
+   
+        if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX))
+        {
+           huart->Instance->BRR = tmpreg;
+        }
+        else
+        {
+          ret = HAL_ERROR;
+        }
+      }  /*   if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */
+    } /* if (tmpreg != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    switch (clocksource)
+    {
+    case UART_CLOCKSOURCE_PCLK1:
+      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_PCLK2:
+      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_HSI:
+      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_SYSCLK:
+      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_LSE:
+      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_UNDEFINED:
+    default:
+        ret = HAL_ERROR;
+      break;
+    }
+
+    brrtemp = usartdiv & 0xFFF0;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+    huart->Instance->BRR = brrtemp;
+  }
+  else
+  {
+    switch (clocksource)
+    {
+    case UART_CLOCKSOURCE_PCLK1:
+      huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_PCLK2:
+      huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_HSI:
+      huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_SYSCLK:
+      huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_LSE:
+      huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+      break;
+    case UART_CLOCKSOURCE_UNDEFINED:
+    default:
+        ret = HAL_ERROR;
+      break;
+    }
+  }
+
+  return ret;
+
+}
+
+/**
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart: UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+  }
+}
+
+/**
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle UART Communication Timeout.
+  * @param  huart UART handle.
+  * @param  Flag Specifies the UART flag to check
+  * @param  Status Flag status (SET or RESET)
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        huart->gState  = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(huart);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+}
+
+
+/**
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+  
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    huart->TxXferCount = 0;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+    HAL_UART_TxCpltCallback(huart);
+  }
+
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+  HAL_UART_TxHalfCpltCallback(huart);
+}
+
+/**
+  * @brief DMA UART receive process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    huart->RxXferCount = 0;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the UART CR3 register */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+  }
+
+  HAL_UART_RxCpltCallback(huart);
+}
+
+/**
+  * @brief DMA UART receive process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+  HAL_UART_RxHalfCpltCallback(huart);
+}
+
+/**
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+  /* Stop UART DMA Tx request if ongoing */
+  if (  (huart->gState == HAL_UART_STATE_BUSY_TX)
+      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
+  {
+    huart->TxXferCount = 0;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if (  (huart->RxState == HAL_UART_STATE_BUSY_RX)
+      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
+  {
+    huart->RxXferCount = 0;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+  HAL_UART_ErrorCallback(huart);
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+  huart->RxXferCount = 0;
+  huart->TxXferCount = 0;
+
+  HAL_UART_ErrorCallback(huart);
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
+  
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(huart->hdmarx != NULL)
+  {
+    if(huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0;
+  huart->RxXferCount = 0;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+}
+
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
+  
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(huart->hdmatx != NULL)
+  {
+    if(huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0;
+  huart->RxXferCount = 0;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+}
+
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+  huart->TxXferCount = 0;
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  huart->RxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+  uint16_t* tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if(huart->TxXferCount == 0)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+      return HAL_OK;
+    }
+    else
+    {
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) huart->pTxBuffPtr;
+        huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+        huart->pTxBuffPtr += 2;
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
+      }
+      huart->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  HAL_UART_TxCpltCallback(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+  uint16_t* tmp;
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      tmp = (uint16_t*) huart->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      huart->pRxBuffPtr +=2;
+    }
+    else
+    {
+      *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+    }
+
+    if(--huart->RxXferCount == 0)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      HAL_UART_RxCpltCallback(huart);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h
new file mode 100755
index 0000000..d4b5cfa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h
@@ -0,0 +1,1435 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_uart.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_UART_H
+#define __STM32L4xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                           - If oversampling is 16 or in LIN mode,
+                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
+                                           - If oversampling is 8,
+                                              Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+                                              Baud Rate Register[3] =  0
+                                              Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref UARTEx_Word_Length. */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref UART_Stop_Bits. */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref UART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Mode. */
+
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
+                                           This parameter can be a value of @ref UART_Over_Sampling. */
+
+  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                           Selecting the single sample method increases the receiver tolerance to clock
+                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+}UART_InitTypeDef;
+
+/**
+  * @brief  UART Advanced Features initalization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
+                                       Advanced Features may be initialized at the same time .
+                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
+
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Tx_Inv.  */
+
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Rx_Inv.  */
+
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
+                                       vs negative/inverted logic).
+                                       This parameter can be a value of @ref UART_Data_Inv. */
+
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */
+
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable */
+
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
+                                       detection is carried out.
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
+                                       This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+
+
+/**
+  * @brief HAL UART State structures definition
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains UART state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing 
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error
+                                                   Value is allowed for gState only */
+}HAL_UART_StateTypeDef;
+
+/**
+  * @brief  HAL UART Error Code structure definition
+  */
+typedef enum
+{
+  HAL_UART_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_UART_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_UART_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_UART_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_UART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_UART_ERROR_DMA       = 0x10,    /*!< DMA transfer error  */
+  HAL_UART_ERROR_BUSY      = 0x20     /*!< Busy Error          */
+}HAL_UART_ErrorTypeDef;
+
+/**
+  * @brief UART clock sources definition
+  */
+typedef enum
+{
+  UART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
+  UART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
+  UART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
+  UART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
+  UART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
+  UART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
+}UART_ClockSourceTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef            *Instance;        /*!< UART registers base address        */
+
+  UART_InitTypeDef         Init;             /*!< UART communication parameters      */
+
+  UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */
+
+  uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;      /*!< UART Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;      /*!< UART Rx Transfer Counter           */
+
+  uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
+
+  DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef           Lock;            /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management 
+                                                  and also related to Tx operations.
+                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.
+                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t             ErrorCode;       /*!< UART Error code                    */
+
+}UART_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
+#define UART_STOPBITS_1                     ((uint32_t)0x00000000)                /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    ((uint32_t)0x00000000)                         /*!< No parity   */
+#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                      /*!< Even parity */
+#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))     /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)                           /*!< No hardware control       */
+#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)                       /*!< Request To Send           */
+#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)                       /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)                    /*!< RX mode        */ 
+#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)                    /*!< TX mode        */ 
+#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))    /*!< RX and TX mode */ 
+/**
+  * @}
+  */
+
+/** @defgroup UART_State  UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)          /*!< UART disabled  */
+#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)        /*!< UART enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                ((uint32_t)0x00000000)          /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+  * @{
+  */
+#define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)          /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)    /*!< One-bit sampling enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x00000000)            /*!< Auto Baud rate detection on start bit            */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)   /*!< Auto Baud rate detection on falling edge         */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)   /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)     /*!< Auto Baud rate detection on 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+  * @{
+  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000)                  /*!< UART receiver timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)             /*!< UART receiver timeout enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN    UART Local Interconnection Network mode
+  * @{
+  */
+#define UART_LIN_DISABLE                    ((uint32_t)0x00000000)                 /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)            /*!< Local Interconnect Network enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000)                /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)            /*!< LIN 11-bit break detection length  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Tx    UART DMA Tx
+  * @{
+  */
+#define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000)                /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)            /*!< UART DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Rx   UART DMA Rx
+  * @{
+  */
+#define UART_DMA_RX_DISABLE                 ((uint32_t)0x00000000)                  /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)              /*!< UART DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
+  * @{
+  */
+#define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x00000000)                  /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)             /*!< UART half-duplex enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000)                  /*!< UART wake-up on idle line    */
+#define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)              /*!< UART wake-up on address mark */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+  * @{
+  */
+#define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
+#define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request          */
+#define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request           */
+#define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
+#define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
+  * @{
+  */
+#define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)          /*!< No advanced feature initialization       */
+#define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)          /*!< TX pin active level inversion            */
+#define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)          /*!< RX pin active level inversion            */
+#define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)          /*!< Binary data inversion                    */
+#define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)          /*!< TX/RX pins swap                          */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)          /*!< RX overrun disable                       */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)          /*!< DMA disable on Reception Error           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040)          /*!< Auto Baud rate detection initialization  */
+#define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)          /*!< Most significant bit sent/received first */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000)              /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)         /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000)              /*!< RX pin active level inversion disable */ 
+#define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)         /*!< RX pin active level inversion enable  */ 
+/**
+  * @}
+  */
+
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000)              /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+  * @{
+  */
+#define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000)              /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)          /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
+  * @{
+  */
+#define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000)              /*!< RX overrun enable  */ 
+#define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */ 
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000)           /*!< RX Auto Baud rate detection enable  */ 
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)      /*!< RX Auto Baud rate detection disable */ 
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
+  * @{
+  */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000)           /*!< DMA enable on Reception Error  */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)       /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
+  * @{
+  */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000)              /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)      /*!< Most significant bit sent/received first enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_STOPMODE_DISABLE    ((uint32_t)0x00000000)              /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE     ((uint32_t)USART_CR1_UESM)          /*!< UART stop mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000)              /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)           /*!< UART mute mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
+  * @{
+  */
+#define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24)                     /*!< UART address-matching LSB position in CR2 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
+  * @{
+  */
+#define UART_WAKEUP_ON_ADDRESS              ((uint32_t)0x00000000)              /*!< UART wake-up on address                         */
+#define UART_WAKEUP_ON_STARTBIT             ((uint32_t)USART_CR3_WUS_1)         /*!< UART wake-up on start bit                       */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    ((uint32_t)USART_CR3_WUS)           /*!< UART wake-up on receive data register not empty */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
+  * @{
+  */
+#define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000)              /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)           /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21)                     /*!< UART Driver Enable assertion time LSB position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16)                     /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
+  * @{
+  */
+#define UART_IT_MASK                        ((uint32_t)0x001F)                  /*!< UART interruptions flags mask */
+/**
+  * @}
+  */
+
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
+  * @{
+  */
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFF                           /*!< UART polling-based communications time-out value */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags     UART Status Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define UART_FLAG_REACK                     ((uint32_t)0x00400000)              /*!< UART receive enable acknowledge flag      */
+#define UART_FLAG_TEACK                     ((uint32_t)0x00200000)              /*!< UART transmit enable acknowledge flag     */
+#define UART_FLAG_WUF                       ((uint32_t)0x00100000)              /*!< UART wake-up from stop mode flag          */
+#define UART_FLAG_RWU                       ((uint32_t)0x00080000)              /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF                      ((uint32_t)0x00040000)              /*!< UART send break flag                      */
+#define UART_FLAG_CMF                       ((uint32_t)0x00020000)              /*!< UART character match flag                 */
+#define UART_FLAG_BUSY                      ((uint32_t)0x00010000)              /*!< UART busy flag                            */
+#define UART_FLAG_ABRF                      ((uint32_t)0x00008000)              /*!< UART auto Baud rate flag                  */
+#define UART_FLAG_ABRE                      ((uint32_t)0x00004000)              /*!< UART auto Baud rate error                 */
+#define UART_FLAG_EOBF                      ((uint32_t)0x00001000)              /*!< UART end of block flag                    */
+#define UART_FLAG_RTOF                      ((uint32_t)0x00000800)              /*!< UART receiver timeout flag                */
+#define UART_FLAG_CTS                       ((uint32_t)0x00000400)              /*!< UART clear to send flag                   */
+#define UART_FLAG_CTSIF                     ((uint32_t)0x00000200)              /*!< UART clear to send interrupt flag         */
+#define UART_FLAG_LBDF                      ((uint32_t)0x00000100)              /*!< UART LIN break detection flag             */
+#define UART_FLAG_TXE                       ((uint32_t)0x00000080)              /*!< UART transmit data register empty         */
+#define UART_FLAG_TC                        ((uint32_t)0x00000040)              /*!< UART transmission complete                */
+#define UART_FLAG_RXNE                      ((uint32_t)0x00000020)              /*!< UART read data register not empty         */
+#define UART_FLAG_IDLE                      ((uint32_t)0x00000010)              /*!< UART idle flag                            */
+#define UART_FLAG_ORE                       ((uint32_t)0x00000008)              /*!< UART overrun error                        */
+#define UART_FLAG_NE                        ((uint32_t)0x00000004)              /*!< UART noise error                          */
+#define UART_FLAG_FE                        ((uint32_t)0x00000002)              /*!< UART frame error                          */
+#define UART_FLAG_PE                        ((uint32_t)0x00000001)              /*!< UART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)
+  * @{
+  */
+#define UART_IT_PE                          ((uint32_t)0x0028)                  /*!< UART parity error interruption                 */    
+#define UART_IT_TXE                         ((uint32_t)0x0727)                  /*!< UART transmit data register empty interruption */    
+#define UART_IT_TC                          ((uint32_t)0x0626)                  /*!< UART transmission complete interruption        */    
+#define UART_IT_RXNE                        ((uint32_t)0x0525)                  /*!< UART read data register not empty interruption */    
+#define UART_IT_IDLE                        ((uint32_t)0x0424)                  /*!< UART idle interruption                         */                                                               
+#define UART_IT_LBD                         ((uint32_t)0x0846)                  /*!< UART LIN break detection interruption          */                
+#define UART_IT_CTS                         ((uint32_t)0x096A)                  /*!< UART CTS interruption                          */                
+#define UART_IT_CM                          ((uint32_t)0x112E)                  /*!< UART character match interruption              */                
+#define UART_IT_WUF                         ((uint32_t)0x1476)                  /*!< UART wake-up from stop mode interruption       */                
+#define UART_IT_ERR                         ((uint32_t)0x0060)                  /*!< UART error interruption         */   
+#define UART_IT_ORE                         ((uint32_t)0x0300)                  /*!< UART overrun error interruption */ 
+#define UART_IT_NE                          ((uint32_t)0x0200)                  /*!< UART noise error interruption   */ 
+#define UART_IT_FE                          ((uint32_t)0x0100)                  /*!< UART frame error interruption   */ 
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
+  * @{
+  */
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
+#define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag         */
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag      */
+#define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag           */
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief  Reset UART handle states.
+  * @param  __HANDLE__: UART handle.
+  * @retval None
+  */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0)
+/** @brief  Flush the UART Data registers.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+    }  while(0)
+
+/** @brief  Clear the specified UART pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag           
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag          
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag         
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag          
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag     
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag  
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag          
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Time Out Clear Flag      
+  *            @arg @ref UART_CLEAR_EOBF     End Of Block Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag        
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag 
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified UART flag is set or not.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag
+  *            @arg @ref UART_FLAG_CMF   Character match flag
+  *            @arg @ref UART_FLAG_BUSY  Busy flag
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref UART_FLAG_EOBF  End of block flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver timeout flag
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
+  *            @arg @ref UART_FLAG_NE    Noise Error flag
+  *            @arg @ref UART_FLAG_FE    Framing Error flag
+  *            @arg @ref UART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM   Character match interrupt
+  *            @arg @ref UART_IT_CTS  CTS change interrupt
+  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TC   Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref UART_IT_PE   Parity Error interrupt
+  *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM   Character match interrupt
+  *            @arg @ref UART_IT_CTS  CTS change interrupt
+  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TC   Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref UART_IT_PE   Parity Error interrupt
+  *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Check whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __IT__: specifies the UART interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM   Character match interrupt
+  *            @arg @ref UART_IT_CTS  CTS change interrupt
+  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TC   Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref UART_IT_ORE  Overrun Error interrupt
+  *            @arg @ref UART_IT_NE   Noise Error interrupt   
+  *            @arg @ref UART_IT_FE   Framing Error interrupt   
+  *            @arg @ref UART_IT_PE   Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief  Check whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __IT__: specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM   Character match interrupt  
+  *            @arg @ref UART_IT_CTS  CTS change interrupt
+  *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TC   Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
+  *            @arg @ref UART_IT_PE   Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
+                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
+
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
+  *            @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
+  *            @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF  Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific UART request flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __REQ__: specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
+
+/** @brief  Enable the UART one bit sample method.
+  * @param  __HANDLE__: specifies the UART Handle.  
+  * @retval None
+  */     
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the UART one bit sample method.
+  * @param  __HANDLE__: specifies the UART Handle.  
+  * @retval None
+  */      
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable UART.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable UART.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/** @brief  Enable CTS flow control.
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance, 
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
+  do{                                                      \
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
+  } while(0)
+
+/** @brief  Disable CTS flow control.
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance, 
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
+  do{                                                       \
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
+  } while(0)
+
+/** @brief  Enable RTS flow control.
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance, 
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
+  do{                                                     \
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
+  } while(0)
+
+/** @brief  Disable RTS flow control.
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance, 
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
+  do{                                                      \
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
+  } while(0)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros   UART Private Macros
+  * @{
+  */
+/** @brief  BRR division operation to set BRR register with LPUART.
+  * @param  __PCLK__: LPUART clock.
+  * @param  __BAUD__: Baud rate set by the user.
+  * @retval Division result
+  */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__)      ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__: UART clock.
+  * @param  __BAUD__: Baud rate set by the user.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__: UART clock.
+  * @param  __BAUD__: Baud rate set by the user.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))
+
+/** @brief  Check whether or not UART instance is Low Power UART.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+  */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
+
+/** @brief  Check UART Baud rate.
+  * @param  __BAUDRATE__: Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+  */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
+
+/** @brief  Check UART assertion time.
+  * @param  __TIME__: 5-bit value assertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1F)
+
+/** @brief  Check UART deassertion time.
+  * @param  __TIME__: 5-bit value deassertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+
+/**
+  * @brief Ensure that UART frame number of stop bits is valid.
+  * @param __STOPBITS__: UART frame number of stop bits. 
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that LPUART frame number of stop bits is valid.
+  * @param __STOPBITS__: LPUART frame number of stop bits. 
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */ 
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                          ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that UART frame parity is valid.
+  * @param __PARITY__: UART frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \
+                                    ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+  * @brief Ensure that UART hardware flow control is valid.
+  * @param __CONTROL__: UART hardware flow control. 
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+  */ 
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+                                   (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+                                    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+                                    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+                                    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+  * @brief Ensure that UART communication mode is valid.
+  * @param __MODE__: UART communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+  * @brief Ensure that UART state is valid.
+  * @param __STATE__: UART state. 
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */ 
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+                                  ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+  * @brief Ensure that UART oversampling is valid.
+  * @param __SAMPLING__: UART oversampling. 
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */ 
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that UART frame sampling is valid.
+  * @param __ONEBIT__: UART frame sampling. 
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate detection mode is valid.
+  * @param __MODE__: UART auto Baud rate detection mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+  * @brief Ensure that UART receiver timeout setting is valid.
+  * @param __TIMEOUT__: UART receiver timeout setting. 
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN state is valid.
+  * @param __LIN__: UART LIN state. 
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+  */
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
+                                     ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN break detection length is valid.
+  * @param __LENGTH__: UART LIN break detection length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+  * @brief Ensure that UART DMA TX state is valid.
+  * @param __DMATX__: UART DMA TX state. 
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA RX state is valid.
+  * @param __DMARX__: UART DMA RX state. 
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that UART half-duplex state is valid.
+  * @param __HDSEL__: UART half-duplex state. 
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+  */
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up method is valid.
+  * @param __WAKEUP__: UART wake-up method . 
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+  */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+  * @brief Ensure that UART request parameter is valid.
+  * @param __PARAM__: UART request parameter. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that UART advanced features initialization is valid.
+  * @param __INIT__: UART advanced features initialization. 
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that UART frame TX inversion setting is valid.
+  * @param __TXINV__: UART frame TX inversion setting. 
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX inversion setting is valid.
+  * @param __RXINV__: UART frame RX inversion setting. 
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame data inversion setting is valid.
+  * @param __DATAINV__: UART frame data inversion setting. 
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+  * @param __SWAP__: UART frame RX/TX pins swap setting. 
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that UART frame overrun setting is valid.
+  * @param __OVERRUN__: UART frame overrun setting. 
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate state is valid.
+  * @param __AUTOBAUDRATE__: UART auto Baud rate state. 
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+  * @param __DMA__: UART DMA enabling or disabling on error setting. 
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that UART frame MSB first setting is valid.
+  * @param __MSBFIRST__: UART frame MSB first setting. 
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that UART stop mode state is valid.
+  * @param __STOPMODE__: UART stop mode state. 
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART mute mode state is valid.
+  * @param __MUTE__: UART mute mode state. 
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+  */
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up selection is valid.
+  * @param __WAKE__: UART wake-up selection. 
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+  */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+  * @brief Ensure that UART driver enable polarity is valid.
+  * @param __POLARITY__: UART driver enable polarity. 
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+  */
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+  * @}
+  */
+
+/* Include UART HAL Extended module */
+#include "stm32l4xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c
new file mode 100755
index 0000000..49a416e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c
@@ -0,0 +1,466 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
+  8-bit or 9-bit), the possible UART formats are listed in the 
+  following table.
+  
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart: UART handle.
+  * @param Polarity: select the driver enable polarity.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime: Driver Enable assertion time:
+  *                         5-bit value defining the time between the activation of the DE (Driver Enable)
+  *                         signal and the beginning of the start bit. It is expressed in sample time
+  *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime: Driver Enable deassertion time:
+  *                         5-bit value defining the time between the end of the last stop bit, in a
+  *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *                         oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+{
+  uint32_t temp = 0x0;
+
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if(huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
+     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt
+
+
+@endverbatim
+  * @{
+  */
+
+
+
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart: UART handle.
+  * @param AddressLength: this parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @param huart: UART handle.
+  * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
+  * This parameter can be one of the following values:
+  *      @arg @ref UART_WAKEUP_ON_ADDRESS
+  *      @arg @ref UART_WAKEUP_ON_STARTBIT
+  *      @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = 0;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Wait until REACK flag is set */
+  if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->gState = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note  The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Set UESM bit */
+  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear UESM bit */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart: UART handle.
+  * @param WakeUpSelection: UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h
new file mode 100755
index 0000000..8977d53
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h
@@ -0,0 +1,638 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_UART_EX_H
+#define __STM32L4xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UART Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+  
+/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B              ((uint32_t)0x00000000)       /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B              ((uint32_t)USART_CR2_ADDM7)  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART5_SOURCE())                   \
+       {                                                      \
+        case RCC_UART5CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L432xx) || defined (STM32L442xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)  
+#endif
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003F ;                                 \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__: UART frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__: UART wake-up address length. 
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c
new file mode 100755
index 0000000..d6502a6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c
@@ -0,0 +1,2282 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_usart.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   USART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
+  *          Peripheral (USART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+    [..]
+      The USART HAL driver can be used as follows:
+
+      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+          (++) Enable the USARTx interface clock.
+          (++) USART pins configuration:
+            (+++) Enable the clock for the USART GPIOs.
+            (+++) Configure these USART pins as alternate function pull-up.
+          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+            (++) USART interrupts handling:
+              -@@-   The specific USART interrupts (Transmission complete interrupt,
+                  RXNE interrupt and Error Interrupts) will be managed using the macros
+                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+          flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
+
+      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+               by calling the customized HAL_USART_MspInit(&husart) API.
+
+    [..]
+     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and                 
+        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.                
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup USART USART
+  * @brief HAL USART Synchronous module driver
+  * @{
+  */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+  * @{
+  */
+#define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
+#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)             /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))    /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+#define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
+                                              USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+  * @{
+  */
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USART
+    in asynchronous and in synchronous modes.
+      (+) For the asynchronous mode only these parameters can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) USART polarity
+        (++) USART phase
+        (++) USART LastBit
+        (++) Receiver/transmitter modes
+
+    [..]
+    The HAL_USART_Init() function follows the USART  synchronous configuration
+    procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
+  8-bit or 9-bit), the possible USART formats are listed in the 
+  following table.
+  
+    Table 1. USART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the USART mode according to the specified
+  *         parameters in the USART_InitTypeDef and initialize the associated handle.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+  /* Check the USART handle allocation */
+  if(husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  if(husart->State == HAL_USART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    husart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_USART_MspInit(husart);
+  }
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_USART_DISABLE(husart);
+
+  /* Set the Usart Communication parameters */
+  if (USART_SetConfig(husart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register
+  - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+  husart->Instance->CR2 &= ~USART_CR2_LINEN;
+  husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+  /* Enable the Peripheral */
+  __HAL_USART_ENABLE(husart);
+
+  /* TEACK and/or REACK to check before moving husart->State to Ready */
+  return (USART_CheckIdleState(husart));
+}
+
+/**
+  * @brief  DeInitialize the USART peripheral.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+  /* Check the USART handle allocation */
+  if(husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  husart->Instance->CR1 = 0x0;
+  husart->Instance->CR2 = 0x0;
+  husart->Instance->CR3 = 0x0;
+
+  /* DeInit the low level hardware */
+  HAL_USART_MspDeInit(husart);
+
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+  husart->State = HAL_USART_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the USART MSP.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the USART MSP.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+  * @brief    USART Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART synchronous
+    data transfers.
+
+    [..] The USART supports master mode only: it cannot receive or send data related to an input
+         clock (SCLK is always an output).
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (++) HAL_USART_Transmit()in simplex mode
+        (++) HAL_USART_Receive() in full duplex receive only
+        (++) HAL_USART_TransmitReceive() in full duplex mode
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (++) HAL_USART_Transmit_IT()in simplex mode
+        (++) HAL_USART_Receive_IT() in full duplex receive only
+        (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+        (++) HAL_USART_IRQHandler()
+
+    (#) No-Blocking mode API's  with DMA are :
+        (++) HAL_USART_Transmit_DMA()in simplex mode
+        (++) HAL_USART_Receive_DMA() in full duplex receive only
+        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+        (++) HAL_USART_DMAPause()
+        (++) HAL_USART_DMAResume()
+        (++) HAL_USART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (++) HAL_USART_TxCpltCallback()
+        (++) HAL_USART_RxCpltCallback()
+        (++) HAL_USART_TxHalfCpltCallback()
+        (++) HAL_USART_RxHalfCpltCallback()
+        (++) HAL_USART_ErrorCallback()
+        (++) HAL_USART_TxRxCpltCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_USART_Abort()
+        (+) HAL_USART_Abort_IT()
+
+    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+        (+) HAL_USART_AbortCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Simplex send an amount of data in blocking mode.
+  * @param  husart USART handle.
+  * @param  pTxData Pointer to data buffer.
+  * @param  Size Amount of data to be sent.
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tickstart = 0;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    /* Check the remaining data to be sent */
+    while(husart->TxXferCount > 0)
+    {
+      husart->TxXferCount--;
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pTxData;
+        husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+        pTxData += 2;
+      }
+      else
+      {
+        husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
+      }
+    }
+
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note  To receive synchronous data, dummy data are simultaneously transmitted.
+  * @param husart USART handle.
+  * @param pRxData Pointer to data buffer.
+  * @param Size Amount of data to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint16_t uhMask;
+  uint32_t tickstart = 0;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+    uhMask = husart->Mask;
+
+    /* as long as data have to be received */
+    while(husart->RxXferCount > 0)
+    {
+      husart->RxXferCount--;
+
+      /* Wait until TC flag is set to send dummy byte in order to generate the
+      * clock for the slave to send data.
+       * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+       * can be written for all the cases. */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
+
+      /* Wait for RXNE Flag */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pRxData ;
+        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+        pRxData +=2;
+      }
+      else
+      {
+        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+      }
+    }
+
+    /* At end of Rx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send and Receive an amount of data in blocking mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer.
+  * @param  pRxData pointer to RX data buffer.
+  * @param  Size amount of data to be sent (same amount to be received).
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint16_t uhMask;
+  uint32_t tickstart = 0;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    husart->RxXferSize = Size;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+    husart->RxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+    uhMask = husart->Mask;
+
+    /* Check the remain data to be sent */
+    while(husart->TxXferCount > 0)
+    {
+      husart->TxXferCount--;
+      husart->RxXferCount--;
+
+      /* Wait until TC flag is set to send data */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pTxData;
+        husart->Instance->TDR = (*tmp & uhMask);
+        pTxData += 2;
+      }
+      else
+      {
+        husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+      }
+
+      /* Wait for RXNE Flag */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pRxData ;
+        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+        pRxData +=2;
+      }
+      else
+      {
+        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+      }
+    }
+
+    /* At end of TxRx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+    are not managed by the USART Transmit Process to avoid the overrun interrupt
+    when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+    to benefit for the frame error and noise interrupts the usart mode should be
+    configured only for transmit "USART_MODE_TX" */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Transmit Data Register Empty Interrupt */
+    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
+  * @param  husart USART handle.
+  * @param  pRxData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+
+    USART_MASK_COMPUTATION(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error and Data Register not empty Interrupts */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Send dummy byte in order to generate the clock for the Slave to send the next data */
+    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+    {
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF);
+    }
+    else
+    {
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send and Receive an amount of data in interrupt mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer.
+  * @param  pRxData pointer to RX data buffer.                         
+  * @param  Size amount of data to be sent (same amount to be received).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
+{
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+    /* Enable the USART Transmit Data Register Empty Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* Set the USART DMA transfer complete callback */
+    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+    /* Set the DMA error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART transmit DMA channel */
+    tmp = (uint32_t*)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  husart USART handle.
+  * @param  pRxData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @note   When the USART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  /* Check that a Rx process is not already ongoing */
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL ) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pRxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Set the USART DMA Rx transfer complete callback */
+    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+    /* Set the USART DMA Rx transfer error callback */
+    husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART receive DMA channel */
+    tmp = (uint32_t*)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+    /* Enable the USART transmit DMA channel: the transmit channel is used in order
+       to generate in the non-blocking mode the clock to the slave device,
+       this mode isn't a simplex receive mode but a full-duplex receive mode */
+    /* Set the USART DMA Tx Complete and Error callback to Null */
+    husart->hdmatx->XferErrorCallback = NULL;
+    husart->hdmatx->XferHalfCpltCallback = NULL;
+    husart->hdmatx->XferCpltCallback = NULL;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer.
+  * @param  pRxData pointer to RX data buffer.
+  * @param  Size amount of data to be received/sent.
+  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    /* Set the USART DMA Rx transfer complete callback */
+    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+    /* Set the USART DMA Tx transfer complete callback */
+    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+    /* Set the USART DMA Tx transfer error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Set the USART DMA Rx transfer error callback */
+    husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART receive DMA channel */
+    tmp = (uint32_t*)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+    /* Enable the USART transmit DMA channel */
+    tmp = (uint32_t*)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Clear the TC flag in the ICR register */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Pause the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
+  {
+    /* Disable the USART DMA Tx request */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  }
+  else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+           (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+  {
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+    {
+      /* Disable the USART DMA Tx request */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+    }
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Disable the USART DMA Rx request */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    /* Enable the USART DMA Tx request */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  }
+  else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+           (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the USART DMA Rx request  before the DMA Tx request */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the USART DMA Tx request */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+     HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: 
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete  
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of 
+     the stream and the corresponding call back is executed. */
+
+  /* Disable the USART Tx/Rx DMA requests */
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+  /* Abort the USART DMA tx channel */
+  if(husart->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(husart->hdmatx);
+  }
+  /* Abort the USART DMA rx channel */
+  if(husart->hdmarx != NULL)
+  {
+    HAL_DMA_Abort(husart->hdmarx);
+  }
+
+  USART_EndTransfer(husart);
+  husart->State = HAL_USART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable USART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the USART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(husart->hdmatx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      husart->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(husart->hdmatx);
+    }
+  }
+
+  /* Disable the USART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(husart->hdmarx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      husart->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(husart->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  husart->TxXferCount = 0; 
+  husart->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable USART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(husart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+    {
+      husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+    }
+    else
+    {
+      husart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(husart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+    {
+      husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+    }
+    else
+    {
+      husart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the USART DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at USART level */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(husart->hdmatx != NULL)
+    {
+      /* USART Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+      {
+        husart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the USART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(husart->hdmarx != NULL)
+    {
+      /* USART Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+      {
+        husart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    husart->TxXferCount = 0; 
+    husart->RxXferCount = 0;
+
+    /* Reset errorCode */
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+    /* Restore husart->State to Ready */
+    husart->State  = HAL_USART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_USART_AbortCpltCallback(husart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle USART interrupt request.
+  * @param  husart USART handle.
+  * @retval None
+  */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+  uint32_t isrflags   = READ_REG(husart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(husart->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+  if (errorflags == RESET)
+  {
+    /* USART in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      if(husart->State == HAL_USART_STATE_BUSY_RX)
+      {
+        USART_Receive_IT(husart);
+      }
+      else
+      {
+        USART_TransmitReceive_IT(husart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  cr3its = READ_REG(husart->Instance->CR3);
+  if(   (errorflags != RESET)
+     && (   ((cr3its & USART_CR3_EIE) != RESET)
+         || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+  {
+    /* USART parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_PE;
+    }
+
+    /* USART frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_FE;
+    }
+
+    /* USART noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_NE;
+    }
+
+    /* USART Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_ORE;
+    }
+
+    /* Call USART Error Call back function if need be --------------------------*/
+    if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+    {
+      /* USART in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        if(husart->State == HAL_USART_STATE_BUSY_RX)
+        {
+          USART_Receive_IT(husart);
+        }
+        else
+        {
+          USART_TransmitReceive_IT(husart);
+        }
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
+          (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the USART state ready to be able to start again the process,
+           Disable Interrupts, and disable DMA requests, if ongoing */
+        USART_EndTransfer(husart);
+
+        /* Disable the USART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+          /* Abort the USART DMA Tx channel */
+          if(husart->hdmatx != NULL)
+          {
+            /* Set the USART Tx DMA Abort callback to NULL : no callback
+               executed at end of DMA abort procedure */
+            husart->hdmatx->XferAbortCallback = NULL;
+            
+            /* Abort DMA TX */
+            HAL_DMA_Abort_IT(husart->hdmatx);
+          }
+
+          /* Abort the USART DMA Rx channel */
+          if(husart->hdmarx != NULL)
+          {
+            /* Set the USART Rx DMA Abort callback : 
+               will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
+              husart->hdmarx->XferAbortCallback(husart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_USART_ErrorCallback(husart);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_USART_ErrorCallback(husart);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_USART_ErrorCallback(husart);
+        husart->ErrorCode = HAL_USART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+
+  /* USART in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+      USART_Transmit_IT(husart);
+    }
+    else
+    {
+      USART_TransmitReceive_IT(husart);
+    }
+    return;
+  }
+
+  /* USART in mode Transmitter (transmission end) -----------------------------*/
+  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    USART_EndTransmit_IT(husart);
+    return;
+  }
+
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief Rx Half Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_TxRxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief USART error callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  USART Abort Complete callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ *  @brief   USART Peripheral State and Error functions
+ *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the USART handle state
+      (+) Return the USART handle error code
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief Return the USART handle state.
+  * @param husart : pointer to a USART_HandleTypeDef structure that contains
+  *              the configuration information for the specified USART.
+  * @retval USART handle state
+  */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+  return husart->State;
+}
+
+/**
+  * @brief Return the USART error code.
+  * @param husart : pointer to a USART_HandleTypeDef structure that contains
+  *              the configuration information for the specified USART.
+  * @retval USART handle Error Code
+  */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+  return husart->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+  * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of process, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+  * @brief  DMA USART transmit process complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    husart->TxXferCount = 0;
+
+    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+      /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+         in the USART CR3 register */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+    }
+  }
+  /* DMA Circular mode */
+  else
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+    HAL_USART_TxCpltCallback(husart);
+   }
+ }
+}
+
+/**
+  * @brief  DMA USART transmit process half complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+  * @brief  DMA USART receive process complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    husart->RxXferCount = 0;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+       in USART CR3 register */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+    /* similarly, disable the DMA TX transfer that was started to provide the
+       clock to the slave device */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+      HAL_USART_RxCpltCallback(husart);
+    }
+    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+    else
+    {
+      HAL_USART_TxRxCpltCallback(husart);
+    }
+    husart->State= HAL_USART_STATE_READY;
+  }
+  /* DMA circular mode */
+  else
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+      HAL_USART_RxCpltCallback(husart);
+    }
+    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+    else
+    {
+      HAL_USART_TxRxCpltCallback(husart);
+    }
+  }    
+
+}
+
+/**
+  * @brief  DMA USART receive process half complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+  * @brief DMA USART communication error callback.
+  * @param  hdma: DMA handle.
+  * @retval None
+  */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  husart->RxXferCount = 0;
+  husart->TxXferCount = 0;
+  USART_EndTransfer(husart);
+
+  husart->ErrorCode |= HAL_USART_ERROR_DMA;
+  husart->State= HAL_USART_STATE_READY;
+
+  HAL_USART_ErrorCallback(husart);
+}
+
+/**
+  * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+  husart->RxXferCount = 0;
+  husart->TxXferCount = 0;
+
+  HAL_USART_ErrorCallback(husart);
+}
+
+/**
+  * @brief  DMA USART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+  
+  husart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(husart->hdmarx != NULL)
+  {
+    if(husart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0;
+  husart->RxXferCount = 0;
+
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+  * @brief  DMA USART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+  
+  husart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(husart->hdmatx != NULL)
+  {
+    if(husart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0;
+  husart->RxXferCount = 0;
+
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+  * @brief  Handle USART Communication Timeout.
+  * @param  husart USART handle.
+  * @param  Flag Specifies the USART flag to check.
+  * @param  Status the Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+        husart->State= HAL_USART_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(husart);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure the USART peripheral.
+  * @param husart: USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpreg                      = 0x0;
+  USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
+  HAL_StatusTypeDef ret                = HAL_OK;
+  uint16_t brrtemp                     = 0x0000;
+  uint16_t usartdiv                    = 0x0000;  
+
+  /* Check the parameters */
+  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+  assert_param(IS_USART_PARITY(husart->Init.Parity));
+  assert_param(IS_USART_MODE(husart->Init.Mode));
+
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+   /* Clear M, PCE, PS, TE and RE bits and configure
+   *  the USART Word Length, Parity and Mode:
+   *  set the M bits according to husart->Init.WordLength value
+   *  set PCE and PS bits according to husart->Init.Parity value
+   *  set TE and RE bits according to husart->Init.Mode value 
+   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8)  */
+  tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+  MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*---------------------------- USART CR2 Configuration ---------------------*/
+  /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
+   * set CPOL bit according to husart->Init.CLKPolarity value
+   * set CPHA bit according to husart->Init.CLKPhase value
+   * set LBCL bit according to husart->Init.CLKLastBit value
+   * set STOP[13:12] bits according to husart->Init.StopBits value */
+  tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+  tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+  tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
+  MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* no CR3 register configuration                                            */
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */ 
+  USART_GETCLOCKSOURCE(husart, clocksource);
+  switch (clocksource)
+  {
+    case USART_CLOCKSOURCE_PCLK1:
+      usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_PCLK2:
+      usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_HSI:
+      usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_SYSCLK:
+      usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_LSE:
+      usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_UNDEFINED:
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+  
+  brrtemp = usartdiv & 0xFFF0;
+  brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+  husart->Instance->BRR = brrtemp;
+
+  return ret;
+}
+
+/**
+  * @brief Check the USART Idle State.
+  * @param husart: USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the USART ErrorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the USART state*/
+  husart->State= HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Simplex send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Transmit_IT().
+  * @note   The USART errors are not managed to avoid the overrun error.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+
+  /* Check that a Tx process is ongoing */
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+
+    if(husart->TxXferCount == 0)
+    {
+      /* Disable the USART Transmit data register empty interrupt */
+      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+      return HAL_OK;
+    }
+    else
+    {
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) husart->pTxBuffPtr;
+        husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+        husart->pTxBuffPtr += 2;
+      }
+      else
+      {
+        husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
+      }
+
+      husart->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Wraps up transmission in non-blocking mode.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+  /* Disable the USART Transmit Complete Interrupt */
+  __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+  __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+  /* Tx process is ended, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+
+  HAL_USART_TxCpltCallback(husart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Simplex receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Receive_IT().
+  * @param  husart USART handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+  uint16_t uhMask = husart->Mask;
+
+  if(husart->State == HAL_USART_STATE_BUSY_RX)
+  {
+
+    if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      tmp = (uint16_t*) husart->pRxBuffPtr;
+      *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+      husart->pRxBuffPtr += 2;
+    }
+    else
+    {
+      *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+    }
+    /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+    husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+
+    if(--husart->RxXferCount == 0)
+    {
+      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore husart->State to Ready */
+      husart->State = HAL_USART_STATE_READY;
+
+      HAL_USART_RxCpltCallback(husart);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_TransmitReceive_IT().
+  * @param husart: USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+  uint16_t uhMask = husart->Mask;
+
+  if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+  {
+
+    if(husart->TxXferCount != 0x00)
+    {
+      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+      {
+        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+        {
+          tmp = (uint16_t*) husart->pTxBuffPtr;
+          husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
+          husart->pTxBuffPtr += 2;
+        }
+        else
+        {
+          husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
+        }
+        husart->TxXferCount--;
+
+        /* Check the latest data transmitted */
+        if(husart->TxXferCount == 0)
+        {
+           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+        }
+      }
+    }
+
+    if(husart->RxXferCount != 0x00)
+    {
+      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+      {
+        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+        {
+          tmp = (uint16_t*) husart->pRxBuffPtr;
+          *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+          husart->pRxBuffPtr += 2;
+        }
+        else
+        {
+          *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+        }
+        husart->RxXferCount--;
+      }
+    }
+
+    /* Check the latest data received */
+    if(husart->RxXferCount == 0)
+    {
+      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore husart->State to Ready */
+      husart->State = HAL_USART_STATE_READY;
+
+      HAL_USART_TxRxCpltCallback(husart);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h
new file mode 100755
index 0000000..a7ed6eb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h
@@ -0,0 +1,718 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_usart.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of USART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_USART_H
+#define __STM32L4xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+  * @{
+  */
+
+/**
+  * @brief USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USARTEx_Word_Length. */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits. */
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode. */
+
+  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_Clock_Polarity. */
+
+  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_Clock_Phase. */
+
+  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_Last_Bit. */
+}USART_InitTypeDef;
+
+/**
+  * @brief HAL USART State structures definition
+  */
+typedef enum
+{
+  HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                  */
+  HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use       */
+  HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                 */
+  HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing           */
+  HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing              */
+  HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
+  HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                  */
+  HAL_USART_STATE_ERROR             = 0x04     /*!< Error                                          */
+}HAL_USART_StateTypeDef;
+
+/**
+  * @brief  HAL USART Error Code structure definition
+  */
+typedef enum
+{
+  HAL_USART_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_USART_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_USART_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_USART_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_USART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_USART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
+}HAL_USART_ErrorTypeDef;
+
+/**
+  * @brief  USART clock sources definitions
+  */
+typedef enum
+{
+  USART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
+  USART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
+  USART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
+  USART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
+  USART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
+  USART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
+}USART_ClockSourceTypeDef;
+
+
+/**
+  * @brief  USART handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef                 *Instance;        /*!< USART registers base address        */
+
+  USART_InitTypeDef             Init;             /*!< USART communication parameters      */
+
+  uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */
+
+  uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */
+
+  __IO uint16_t                 TxXferCount;      /*!< USART Tx Transfer Counter           */
+
+  uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */
+
+  uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */
+
+  __IO uint16_t                 RxXferCount;      /*!< USART Rx Transfer Counter           */
+
+  uint16_t                      Mask;             /*!< USART Rx RDR register mask          */
+
+  DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef               Lock;             /*!< Locking object                      */
+
+  __IO HAL_USART_StateTypeDef   State;            /*!< USART communication state           */
+
+  __IO uint32_t                 ErrorCode;        /*!< USART Error code                    */
+
+}USART_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_Stop_Bits  USART Number of Stop Bits
+  * @{
+  */
+#define USART_STOPBITS_0_5                   USART_CR2_STOP_0                      /*!< USART frame with 0.5 stop bit  */
+#define USART_STOPBITS_1                     ((uint32_t)0x00000000)                /*!< USART frame with 1 stop bit    */   
+#define USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ 
+#define USART_STOPBITS_2                     USART_CR2_STOP_1                      /*!< USART frame with 2 stop bits   */ 
+/**
+  * @}
+  */
+
+/** @defgroup USART_Parity    USART Parity
+  * @{
+  */
+#define USART_PARITY_NONE                   ((uint32_t)0x00000000)                      /*!< No parity   */
+#define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
+#define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Mode   USART Mode
+  * @{
+  */
+#define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
+#define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
+#define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Over_Sampling USART Over Sampling
+  * @{
+  */
+#define USART_OVERSAMPLING_16               ((uint32_t)0x00000000)          /*!< Oversampling by 16 */
+#define USART_OVERSAMPLING_8                ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock  USART Clock
+  * @{
+  */
+#define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000)        /*!< USART clock disable */
+#define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)   /*!< USART clock enable  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Polarity  USART Clock Polarity
+  * @{
+  */
+#define USART_POLARITY_LOW                  ((uint32_t)0x00000000)       /*!< USART Clock signal is steady Low */
+#define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)   /*!< USART Clock signal is steady High  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Phase   USART Clock Phase
+  * @{
+  */
+#define USART_PHASE_1EDGE                   ((uint32_t)0x00000000)       /*!< USART frame phase on first clock transition  */
+#define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)   /*!< USART frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit  USART Last Bit
+  * @{
+  */
+#define USART_LASTBIT_DISABLE               ((uint32_t)0x00000000)       /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)   /*!< USART frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Request_Parameters  USART Request Parameters
+  * @{
+  */
+#define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
+#define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags      USART Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define USART_FLAG_REACK                     ((uint32_t)0x00400000)    /*!< USART receive enable acknowledge flag  */
+#define USART_FLAG_TEACK                     ((uint32_t)0x00200000)    /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY                      ((uint32_t)0x00010000)    /*!< USART busy flag                        */
+#define USART_FLAG_CTS                       ((uint32_t)0x00000400)    /*!< USART clear to send flag               */
+#define USART_FLAG_CTSIF                     ((uint32_t)0x00000200)    /*!< USART clear to send interrupt flag     */
+#define USART_FLAG_LBDF                      ((uint32_t)0x00000100)    /*!< USART LIN break detection flag         */
+#define USART_FLAG_TXE                       ((uint32_t)0x00000080)    /*!< USART transmit data register empty     */
+#define USART_FLAG_TC                        ((uint32_t)0x00000040)    /*!< USART transmission complete            */
+#define USART_FLAG_RXNE                      ((uint32_t)0x00000020)    /*!< USART read data register not empty     */
+#define USART_FLAG_IDLE                      ((uint32_t)0x00000010)    /*!< USART idle flag                        */
+#define USART_FLAG_ORE                       ((uint32_t)0x00000008)    /*!< USART overrun error                    */
+#define USART_FLAG_NE                        ((uint32_t)0x00000004)    /*!< USART noise error                      */
+#define USART_FLAG_FE                        ((uint32_t)0x00000002)    /*!< USART frame error                      */
+#define USART_FLAG_PE                        ((uint32_t)0x00000001)    /*!< USART parity error                     */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+
+#define USART_IT_PE                          ((uint16_t)0x0028)     /*!< USART parity error interruption                 */   
+#define USART_IT_TXE                         ((uint16_t)0x0727)     /*!< USART transmit data register empty interruption */   
+#define USART_IT_TC                          ((uint16_t)0x0626)     /*!< USART transmission complete interruption        */   
+#define USART_IT_RXNE                        ((uint16_t)0x0525)     /*!< USART read data register not empty interruption */   
+#define USART_IT_IDLE                        ((uint16_t)0x0424)     /*!< USART idle interruption                         */   
+#define USART_IT_ERR                         ((uint16_t)0x0060)     /*!< USART error interruption                        */
+#define USART_IT_ORE                         ((uint16_t)0x0300)     /*!< USART overrun error interruption                */ 
+#define USART_IT_NE                          ((uint16_t)0x0200)     /*!< USART noise error interruption                  */ 
+#define USART_IT_FE                          ((uint16_t)0x0100)     /*!< USART frame error interruption                  */ 
+/**
+  * @}
+  */
+
+/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
+  * @{
+  */
+#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
+#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
+#define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
+#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
+#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
+#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
+  * @{
+  */
+#define USART_IT_MASK                             ((uint16_t)0x001F)     /*!< USART interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @brief Reset USART handle state.
+  * @param  __HANDLE__: USART handle.
+  * @retval None
+  */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief  Check whether the specified USART flag is set or not.
+  * @param  __HANDLE__: specifies the USART Handle
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref USART_FLAG_BUSY  Busy flag
+  *            @arg @ref USART_FLAG_CTS   CTS Change flag
+  *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref USART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref USART_FLAG_ORE   OverRun Error flag
+  *            @arg @ref USART_FLAG_NE    Noise Error flag
+  *            @arg @ref USART_FLAG_FE    Framing Error flag
+  *            @arg @ref USART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified USART pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref USART_CLEAR_PEF
+  *            @arg @ref USART_CLEAR_FEF
+  *            @arg @ref USART_CLEAR_NEF
+  *            @arg @ref USART_CLEAR_OREF
+  *            @arg @ref USART_CLEAR_IDLEF
+  *            @arg @ref USART_CLEAR_TCF
+  *            @arg @ref USART_CLEAR_CTSF
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the USART PE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief  Clear the USART FE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief  Clear the USART NE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief  Clear the USART ORE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief  Clear the USART IDLE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief  Enable the specified USART interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC   Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_PE   Parity Error interrupt
+  *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief  Disable the specified USART interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC   Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_PE   Parity Error interrupt
+  *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+
+/** @brief  Check whether the specified USART interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC  Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE OverRun Error interrupt
+  *            @arg @ref USART_IT_NE Noise Error interrupt
+  *            @arg @ref USART_IT_FE Framing Error interrupt
+  *            @arg @ref USART_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief  Check whether the specified USART interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC  Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE OverRun Error interrupt
+  *            @arg @ref USART_IT_NE Noise Error interrupt
+  *            @arg @ref USART_IT_FE Framing Error interrupt
+  *            @arg @ref USART_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
+                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
+                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))
+
+
+/** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
+  *            @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+  *            @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+  *            @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific USART request flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __REQ__: specifies the request flag to set.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (__REQ__))
+
+/** @brief  Enable the USART one bit sample method.
+  * @param  __HANDLE__: specifies the USART Handle.  
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the USART one bit sample method.
+  * @param  __HANDLE__: specifies the USART Handle.  
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable USART.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable USART.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros   USART Private Macros
+  * @{
+  */
+
+/** @brief  Check USART Baud rate.
+  * @param  __BAUDRATE__: Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8).
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
+
+/**
+  * @brief Ensure that USART frame number of stop bits is valid.
+  * @param __STOPBITS__: USART frame number of stop bits. 
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+  * @brief Ensure that USART frame parity is valid.
+  * @param __PARITY__: USART frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+                                     ((__PARITY__) == USART_PARITY_EVEN) || \
+                                     ((__PARITY__) == USART_PARITY_ODD))
+
+/**
+  * @brief Ensure that USART communication mode is valid.
+  * @param __MODE__: USART communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
+
+/**
+  * @brief Ensure that USART oversampling is valid.
+  * @param __SAMPLING__: USART oversampling. 
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */ 
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that USART clock state is valid.
+  * @param __CLOCK__: USART clock state. 
+  * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+  */ 
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+                                   ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+  * @brief Ensure that USART frame polarity is valid.
+  * @param __CPOL__: USART frame polarity. 
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */ 
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+  * @brief Ensure that USART frame phase is valid.
+  * @param __CPHA__: USART frame phase. 
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+  * @brief Ensure that USART frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__: USART frame last bit clock pulse setting. 
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+  * @brief Ensure that USART request parameter is valid.
+  * @param __PARAM__: USART request parameter. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @}
+  */
+
+/* Include USART HAL Extended module */
+#include "stm32l4xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h
new file mode 100755
index 0000000..cf01f07
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h
@@ -0,0 +1,280 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_usart_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of USART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_USART_EX_H
+#define __STM32L4xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+  * @{
+  */
+  
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+  * @{
+  */
+#define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */ 
+#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long USART frame */ 
+#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the USART clock source.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval the USART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L432xx) || defined (STM32L442xx)
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART3)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+       {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#endif /* STM32L432xx || STM32L442xx */
+
+/** @brief  Compute the USART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define USART_MASK_COMPUTATION(__HANDLE__)                            \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003F ;                                 \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+
+/**
+  * @brief Ensure that USART frame length is valid.
+  * @param __LENGTH__: USART frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_9B))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_USART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c
new file mode 100755
index 0000000..5e8ce30
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c
@@ -0,0 +1,322 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   WWDG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Window Watchdog (WWDG) peripheral:
+  *           + Initialization and Configuration function
+  *           + IO operation functions
+  @verbatim
+  ==============================================================================
+                      ##### WWDG specific features #####
+  ==============================================================================
+  [..]
+    Once enabled the WWDG generates a system reset on expiry of a programmed
+    time period, unless the program refreshes the counter (T[6;0] downcounter)
+    before reaching 0x3F value (i.e. a reset is generated when the counter
+    value rolls over from 0x40 to 0x3F).
+
+    (+) An MCU reset is also generated if the counter value is refreshed
+        before the counter has reached the refresh window value. This
+        implies that the counter must be refreshed in a limited window.
+
+    (+) Once enabled the WWDG cannot be disabled except by a system reset.
+
+    (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has 
+        occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
+
+    (+) The WWDG downcounter input clock is derived from the APB clock divided
+        by a programmable prescaler.
+
+    (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
+
+    (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
+        where T[5;0] are the lowest 6 bits of downcounter.
+
+    (+) WWDG Counter refresh is allowed between the following limits :
+        (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
+        (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
+
+    (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms
+
+    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety 
+        operations or data logging must be performed before the actual reset is
+        generated. When the downcounter reaches the value 0x40, an EWI interrupt
+        is generated and the corresponding interrupt service routine (ISR) can 
+        be used to trigger specific actions (such as communications or data 
+        logging), before resetting the device.
+        In some applications, the EWI interrupt can be used to manage a software
+        system check and/or system recovery/graceful degradation, without 
+        generating a WWDG reset. In this case, the corresponding interrupt 
+        service routine (ISR) should reload the WWDG counter to avoid the WWDG 
+        reset, then trigger the required actions.
+        Note:When the EWI interrupt cannot be served, e.g. due to a system lock 
+        in a higher priority task, the WWDG reset will eventually be generated.
+
+    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+        the WWDG counter either continues to work normally or stops, depending 
+        on DBG_WWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+
+    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup 
+        Interrupt mode using using HAL_WWDG_Init() function.
+        This enables WWDG peripheral and the downcounter starts downcounting 
+        from given counter value.
+        Init function can be called again to modify all watchdog parameters, 
+        however if EWI mode has been set once, it can't be clear until next 
+        reset.
+
+    (+) The application program must refresh the WWDG counter at regular
+        intervals during normal operation to prevent an MCU reset using
+        HAL_WWDG_Refresh() function. This operation must occur only when
+        the counter is lower than the window value already programmed.
+
+    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when 
+        the counter reaches 0x40. User can add his own code in weak function 
+        HAL_WWDG_EarlyWakeupCallback().
+
+     *** WWDG HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in WWDG HAL driver.
+
+      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
+      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
+      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+  * @brief WWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+          ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+      (+) Initialize and start the WWDG according to the specified parameters
+          in the WWDG_InitTypeDef of associated handle.
+      (+) Initialize the WWDG MSP.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the WWDG according to the specified.
+  *         parameters in the WWDG_InitTypeDef of  associated handle.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check the WWDG handle allocation */
+  if(hwwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+  /* Init the low level hardware */
+  HAL_WWDG_MspInit(hwwdg);
+
+  /* Set WWDG Counter */
+  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+  /* Set WWDG Prescaler and Window */
+  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the WWDG MSP.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @note   When rewriting this function in user file, mechanism may be added
+  *         to avoid multiple initialize when HAL_WWDG_Init function is called
+  *         again to change parameters.
+  * @retval None
+  */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================  
+  [..]
+    This section provides functions allowing to:
+    (+) Refresh the WWDG.
+    (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Refresh the WWDG.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Write to WWDG CR the WWDG Counter value to refresh with */
+  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle WWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+  *         or data logging must be performed before the actual reset is generated.
+  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with 
+  *         EWIMode set to WWDG_EWI_ENABLE.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is
+  *         generated and the corresponding Interrupt Service Routine (ISR) can
+  *         be used to trigger specific actions (such as communications or data
+  *         logging), before resetting the device.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check if Early Wakeup Interrupt is enable */
+  if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+  {
+    /* Check if WWDG Early Wakeup Interrupt occurred */
+    if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+    {
+      /* Clear the WWDG Early Wakeup flag */
+      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+      /* Early Wakeup callback */ 
+      HAL_WWDG_EarlyWakeupCallback(hwwdg);
+    }
+  }
+}
+
+
+/**
+  * @brief  WWDG Early Wakeup callback.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h
new file mode 100755
index 0000000..7039355
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of WWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_WWDG_H
+#define __STM32L4xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  WWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
+                               This parameter can be a value of @ref WWDG_Prescaler */
+
+  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
+                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
+                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+                               This parameter can be a value of @ref WWDG_EWI_Mode */
+
+}WWDG_InitTypeDef;
+
+/**
+  * @brief  WWDG handle Structure definition
+  */
+typedef struct
+{
+  WWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
+
+}WWDG_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+  * @{
+  */
+#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+  * @brief WWDG Flag definition
+  * @{
+  */
+#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+  * @{
+  */
+#define WWDG_PRESCALER_1                    0x00000000u       /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8                    WWDG_CFR_WDGTB    /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+  * @{
+  */
+#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
+#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+  * @{
+  */
+#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
+
+#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
+                                             ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+  * @}
+  */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the WWDG peripheral.
+  * @param  __HANDLE__  WWDG handle
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+  * @brief  Enable the WWDG early wakeup interrupt.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt to enable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the selected WWDG interrupt has occurred or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the it to check.
+  *        This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief  Clear the WWDG interrupt pending bits.
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified WWDG flag is set or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the WWDG's pending flags.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval None
+  */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
+  * @param  __HANDLE__  WWDG Handle.
+  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
+  * @retval state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/**
+  * @}
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c
new file mode 100755
index 0000000..1a309d0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c
@@ -0,0 +1,1062 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_adc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   ADC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_adc.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)
+
+/** @addtogroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+  * @{
+  */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent  */
+/*       of device clock setting.                                             */
+/*       In user application, ADC timeout values should be defined with       */
+/*       temporal values, in function of device clock settings.               */
+/*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          APB prescaler 16, ADC prescaler 4.                                */
+/*        - ADC clock from asynchronous clock (PLLSAI) with prescaler 1,      */
+/*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
+/*          CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4.    */
+/* Unit: CPU cycles.                                                          */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          ((uint32_t) 512U * 16U * 4U)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* common to several ADC instances.                                           */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
+  (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC instance.                                                              */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
+  (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
+  )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
+  (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
+   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
+  )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
+  (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group regular                                                          */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
+  (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
+  (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
+   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
+  )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
+  (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
+  )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
+  (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
+   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
+  (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
+  (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group injected                                                         */
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
+  (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
+  )
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
+  (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
+  )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
+  (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
+   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
+  (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
+  (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
+   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
+  )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* multimode.                                                                 */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
+  (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
+  )
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
+  (   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
+  )
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \
+  (   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)           \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
+  )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
+  (   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
+  )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of all ADC instances belonging to
+  *         the same ADC common instance to their default reset values.
+  * @note   This function is performing a hard reset, using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 serie, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         To de-initialize only 1 ADC instance, use
+  *         function @ref LL_ADC_DeInit().
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+  
+  /* Force reset of ADC clock (core clock) */
+  LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
+  
+  /* Release reset of ADC clock (core clock) */
+  LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
+  
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of ADC common parameters
+  *         (all ADC instances belonging to the same ADC common instance)
+  *         and multimode (for devices with several ADC instances available).
+  * @note   The setting of ADC common parameters is conditioned to
+  *         ADC instances state:
+  *         All ADC instances belonging to the same ADC common instance
+  *         must be disabled.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are initialized
+  *          - ERROR: ADC common registers are not initialized
+  */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+  assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+  
+#if defined(ADC_MULTIMODE_SUPPORT)
+  assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
+  if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+  {
+    assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
+    assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
+  }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Note: Hardware constraint (refer to description of functions             */
+  /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
+  /*       On this STM32 serie, setting of these features is conditioned to   */
+  /*       ADC state:                                                         */
+  /*       All ADC instances of the ADC common group must be disabled.        */
+  if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - common to several ADC                                               */
+    /*    (all ADC instances belonging to the same ADC common instance)       */
+    /*    - Set ADC clock (conversion clock)                                  */
+    /*  - multimode (if several ADC instances available on the                */
+    /*    selected device)                                                    */
+    /*    - Set ADC multimode configuration                                   */
+    /*    - Set ADC multimode DMA transfer                                    */
+    /*    - Set ADC multimode: delay between 2 sampling phases                */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                   ADC_CCR_CKMODE
+                 | ADC_CCR_PRESC
+                 | ADC_CCR_DUAL
+                 | ADC_CCR_MDMA
+                 | ADC_CCR_DELAY
+                ,
+                   ADC_CommonInitStruct->CommonClock
+                 | ADC_CommonInitStruct->Multimode
+                 | ADC_CommonInitStruct->MultiDMATransfer
+                 | ADC_CommonInitStruct->MultiTwoSamplingDelay
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                   ADC_CCR_CKMODE
+                 | ADC_CCR_PRESC
+                 | ADC_CCR_DUAL
+                 | ADC_CCR_MDMA
+                 | ADC_CCR_DELAY
+                ,
+                   ADC_CommonInitStruct->CommonClock
+                 | LL_ADC_MULTI_INDEPENDENT
+                );
+    }
+#else
+    LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+#endif
+  }
+  else
+  {
+    /* Initialization error: One or several ADC instances belonging to        */
+    /* the same ADC common instance are not disabled.                         */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+  /* Set ADC_CommonInitStruct fields to default values */
+  /* Set fields of ADC common */
+  /* (all ADC instances belonging to the same ADC common instance) */
+  ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+  
+#if defined(ADC_MULTIMODE_SUPPORT)
+  /* Set fields of ADC multimode */
+  ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
+  ADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+  ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+  * @brief  De-initialize registers of the selected ADC instance
+  *         to their default reset values.
+  * @note   To reset all ADC instances quickly (perform a hard reset),
+  *         use function @ref LL_ADC_CommonDeInit().
+  * @note   If this functions returns error status, it means that ADC instance
+  *         is in an unknown state.
+  *         In this case, perform a hard reset using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 serie, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         Refer to function @ref LL_ADC_CommonDeInit().
+  * @param  ADCx ADC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are de-initialized
+  *          - ERROR: ADC registers are not de-initialized
+  */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+  ErrorStatus status = SUCCESS;
+  
+  __IO uint32_t timeout_cpu_cycles = 0U;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  
+  /* Disable ADC instance if not already disabled.                            */
+  if(LL_ADC_IsEnabled(ADCx) == 1U)
+  {
+    /* Set ADC group regular trigger source to SW start to ensure to not      */
+    /* have an external trigger event occurring during the conversion stop    */
+    /* ADC disable process.                                                   */
+    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+    
+    /* Stop potential ADC conversion on going on ADC group regular.           */
+    if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
+    {
+      if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
+      {
+        LL_ADC_REG_StopConversion(ADCx);
+      }
+    }
+    
+    /* Set ADC group injected trigger source to SW start to ensure to not     */
+    /* have an external trigger event occurring during the conversion stop    */
+    /* ADC disable process.                                                   */
+    LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+    
+    /* Stop potential ADC conversion on going on ADC group injected.          */
+    if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
+    {
+      if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
+      {
+        LL_ADC_INJ_StopConversion(ADCx);
+      }
+    }
+    
+    /* Wait for ADC conversions are effectively stopped                       */
+    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+    while ((  LL_ADC_REG_IsStopConversionOngoing(ADCx) 
+            | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
+    {
+      if(timeout_cpu_cycles-- == 0U)
+      {
+        /* Time-out error */
+        status = ERROR;
+      }
+    }
+    
+    /* Flush group injected contexts queue (register JSQR):                   */
+    /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
+    /*       contexts queue is maintained with the last active context).      */
+    LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+    
+    /* Disable the ADC instance */
+    LL_ADC_Disable(ADCx);
+    
+    /* Wait for ADC instance is effectively disabled */
+    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+    while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
+    {
+      if(timeout_cpu_cycles-- == 0U)
+      {
+        /* Time-out error */
+        status = ERROR;
+      }
+    }
+  }
+  
+  /* Check whether ADC state is compliant with expected state */
+  if(READ_BIT(ADCx->CR,
+              (  ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+               | ADC_CR_ADDIS | ADC_CR_ADEN                                     )
+             )
+     == 0U)
+  {
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    CLEAR_BIT(ADCx->IER,
+              (  LL_ADC_IT_ADRDY
+               | LL_ADC_IT_EOC
+               | LL_ADC_IT_EOS
+               | LL_ADC_IT_OVR
+               | LL_ADC_IT_EOSMP
+               | LL_ADC_IT_JEOC
+               | LL_ADC_IT_JEOS
+               | LL_ADC_IT_JQOVF
+               | LL_ADC_IT_AWD1
+               | LL_ADC_IT_AWD2
+               | LL_ADC_IT_AWD3 )
+             );
+    
+    /* Reset register ISR */
+    SET_BIT(ADCx->ISR,
+            (  LL_ADC_FLAG_ADRDY
+             | LL_ADC_FLAG_EOC
+             | LL_ADC_FLAG_EOS
+             | LL_ADC_FLAG_OVR
+             | LL_ADC_FLAG_EOSMP
+             | LL_ADC_FLAG_JEOC
+             | LL_ADC_FLAG_JEOS
+             | LL_ADC_FLAG_JQOVF
+             | LL_ADC_FLAG_AWD1
+             | LL_ADC_FLAG_AWD2
+             | LL_ADC_FLAG_AWD3 )
+           );
+    
+    /* Reset register CR */
+    /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
+    /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
+    /*    access mode "read-set": no direct reset applicable.                 */
+    /*  - Reset Calibration mode to default setting (single ended).           */
+    /*  - Disable ADC internal voltage regulator.                             */
+    /*  - Enable ADC deep power down.                                         */
+    /*    Note: ADC internal voltage regulator disable and ADC deep power     */
+    /*          down enable are conditioned to ADC state disabled:            */
+    /*          already done above.                                           */
+    CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+    SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+    
+    /* Reset register CFGR */
+    MODIFY_REG(ADCx->CFGR,
+               (  ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
+                | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
+                | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
+                | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
+                | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
+                | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN  ),
+                ADC_CFGR_JQDIS
+              );
+    
+    /* Reset register CFGR2 */
+    CLEAR_BIT(ADCx->CFGR2,
+              (  ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
+               | ADC_CFGR2_OVSR   | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
+             );
+    
+    /* Reset register SMPR1 */
+    CLEAR_BIT(ADCx->SMPR1,
+              (  ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+               | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+               | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+             );
+    
+    /* Reset register SMPR2 */
+    CLEAR_BIT(ADCx->SMPR2,
+              (  ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
+               | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
+               | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
+             );
+    
+    /* Reset register TR1 */
+    MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+    
+    /* Reset register TR2 */
+    MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+    
+    /* Reset register TR3 */
+    MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+    
+    /* Reset register SQR1 */
+    CLEAR_BIT(ADCx->SQR1,
+              (  ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
+               | ADC_SQR1_SQ1 | ADC_SQR1_L)
+             );
+    
+    /* Reset register SQR2 */
+    CLEAR_BIT(ADCx->SQR2,
+              (  ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
+               | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
+             );
+    
+    /* Reset register SQR3 */
+    CLEAR_BIT(ADCx->SQR3,
+              (  ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
+               | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
+             );
+    
+    /* Reset register SQR4 */
+    CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+    
+    /* Reset register JSQR */
+    CLEAR_BIT(ADCx->JSQR,
+              (  ADC_JSQR_JL
+               | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
+               | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1  )
+             );
+    
+    /* Reset register DR */
+    /* Note: bits in access mode read only, no direct reset applicable */
+    
+    /* Reset register OFR1 */
+    CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+    /* Reset register OFR2 */
+    CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+    /* Reset register OFR3 */
+    CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+    /* Reset register OFR4 */
+    CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+    
+    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+    /* Note: bits in access mode read only, no direct reset applicable */
+    
+    /* Reset register AWD2CR */
+    CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+    
+    /* Reset register AWD3CR */
+    CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+    
+    /* Reset register DIFSEL */
+    CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+    
+    /* Reset register CALFACT */
+    CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+  }
+  else
+  {
+    /* ADC instance is in an unknown state */
+    /* Need to performing a hard reset of ADC instance, using high level      */
+    /* clock source RCC ADC reset.                                            */
+    /* Caution: On this STM32 serie, if several ADC instances are available   */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    /* Caution: On this STM32 serie, if several ADC instances are available   */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 families).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, some other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  
+  assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+  assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+  assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
+  
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if(LL_ADC_IsEnabled(ADCx) == 0U)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC instance                                                        */
+    /*    - Set ADC data resolution                                           */
+    /*    - Set ADC conversion data alignment                                 */
+    /*    - Set ADC low power mode                                            */
+    MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_RES
+               | ADC_CFGR_ALIGN
+               | ADC_CFGR_AUTDLY
+              ,
+                 ADC_InitStruct->Resolution
+               | ADC_InitStruct->DataAlignment
+               | ADC_InitStruct->LowPowerMode
+              );
+    
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
+  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+  /* Set ADC_InitStruct fields to default values */
+  /* Set fields of ADC instance */
+  ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
+  ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
+  
+}
+
+/**
+  * @brief  Initialize some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+  if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+  }
+  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+  assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
+  
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if(LL_ADC_IsEnabled(ADCx) == 0U)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group regular                                                   */
+    /*    - Set ADC group regular trigger source                              */
+    /*    - Set ADC group regular sequencer length                            */
+    /*    - Set ADC group regular sequencer discontinuous mode                */
+    /*    - Set ADC group regular continuous mode                             */
+    /*    - Set ADC group regular conversion data transfer: no transfer or    */
+    /*      transfer by DMA, and DMA requests mode                            */
+    /*    - Set ADC group regular overrun behavior                            */
+    /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
+    /*       setting of trigger source to SW start.                           */
+    if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR,
+                   ADC_CFGR_EXTSEL
+                 | ADC_CFGR_EXTEN
+                 | ADC_CFGR_DISCEN
+                 | ADC_CFGR_DISCNUM
+                 | ADC_CFGR_CONT
+                 | ADC_CFGR_DMAEN
+                 | ADC_CFGR_DMACFG
+                 | ADC_CFGR_OVRMOD
+                ,
+                   ADC_REG_InitStruct->TriggerSource
+                 | ADC_REG_InitStruct->SequencerDiscont
+                 | ADC_REG_InitStruct->ContinuousMode
+                 | ADC_REG_InitStruct->DMATransfer
+                 | ADC_REG_InitStruct->Overrun
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR,
+                   ADC_CFGR_EXTSEL
+                 | ADC_CFGR_EXTEN
+                 | ADC_CFGR_DISCEN
+                 | ADC_CFGR_DISCNUM
+                 | ADC_CFGR_CONT
+                 | ADC_CFGR_DMAEN
+                 | ADC_CFGR_DMACFG
+                 | ADC_CFGR_OVRMOD
+                ,
+                   ADC_REG_InitStruct->TriggerSource
+                 | LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | ADC_REG_InitStruct->ContinuousMode
+                 | ADC_REG_InitStruct->DMATransfer
+                 | ADC_REG_InitStruct->Overrun
+                );
+    }
+    
+    /* Set ADC group regular sequencer length and scan direction */
+    LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+  /* Set ADC_REG_InitStruct fields to default values */
+  /* Set fields of ADC group regular */
+  /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
+  /*       setting of trigger source to SW start.                             */
+  ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
+  ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
+  ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
+  ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+  * @brief  Initialize some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+  if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+  }
+  assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+  
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if(LL_ADC_IsEnabled(ADCx) == 0U)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group injected                                                  */
+    /*    - Set ADC group injected trigger source                             */
+    /*    - Set ADC group injected sequencer length                           */
+    /*    - Set ADC group injected sequencer discontinuous mode               */
+    /*    - Set ADC group injected conversion trigger: independent or         */
+    /*      from ADC group regular                                            */
+    /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
+    /*       setting of trigger source to SW start.                           */
+    if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR,
+                   ADC_CFGR_JDISCEN
+                 | ADC_CFGR_JAUTO
+                ,
+                   ADC_INJ_InitStruct->SequencerDiscont
+                 | ADC_INJ_InitStruct->TrigAuto
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR,
+                   ADC_CFGR_JDISCEN
+                 | ADC_CFGR_JAUTO
+                ,
+                   LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | ADC_INJ_InitStruct->TrigAuto
+                );
+    }
+    
+    MODIFY_REG(ADCx->JSQR,
+                 ADC_JSQR_JEXTSEL
+               | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JL
+              ,
+                 ADC_INJ_InitStruct->TriggerSource
+               | ADC_INJ_InitStruct->SequencerLength
+              );
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+  /* Set ADC_INJ_InitStruct fields to default values */
+  /* Set fields of ADC group injected */
+  ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
+  ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+  ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+  ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h
new file mode 100755
index 0000000..52c31cb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h
@@ -0,0 +1,7361 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_adc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of ADC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_ADC_H
+#define __STM32L4xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)
+
+/** @defgroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Internal mask for ADC group regular sequencer:                             */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+/* - sequencer register offset                                                */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET                 (0x00000000U)
+#define ADC_SQR2_REGOFFSET                 (0x00000100U)
+#define ADC_SQR3_REGOFFSET                 (0x00000200U)
+#define ADC_SQR4_REGOFFSET                 (0x00000300U)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted  */
+/* into ADC group regular sequencer ranks literals definition.                */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
+
+
+
+/* Internal mask for ADC group injected sequencer:                            */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
+/* - data register offset                                                     */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET                 (0x00000000U)
+#define ADC_JDR2_REGOFFSET                 (0x00000100U)
+#define ADC_JDR3_REGOFFSET                 (0x00000200U)
+#define ADC_JDR4_REGOFFSET                 (0x00000300U)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition.               */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
+
+
+
+/* Internal mask for ADC group regular trigger:                               */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+/* - regular trigger source                                                   */
+/* - regular trigger edge                                                     */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1U)) | \
+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2U)) | \
+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3U))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3U))  )
+
+/* Definition of ADC group regular trigger bits information.                  */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
+
+
+
+/* Internal mask for ADC group injected trigger:                              */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
+/* - injected trigger source                                                  */
+/* - injected trigger edge                                                    */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
+                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 1U)) | \
+                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 2U)) | \
+                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 3U))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )
+
+/* Definition of ADC group injected trigger bits information.                 */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
+
+
+
+
+
+
+/* Internal mask for ADC channel:                                             */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+/* - channel identifier defined by number                                     */
+/* - channel identifier defined by bitfield                                   */
+/* - channel differentiation between external channels (connected to          */
+/*   GPIO pins) and internal channels (connected to internal paths)           */
+/* - channel sampling time defined by SMPRx register offset                   */
+/*   and SMPx bits positions into SMPRx register                              */
+#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET                (0x00000000U)
+#define ADC_SMPR2_REGOFFSET                (0x02000000U)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000U)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into           */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_NUMBER               (0x00000000U)
+#define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )
+#define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )
+#define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
+#define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )
+#define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )
+#define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )
+#define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
+#define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )
+#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )
+
+/* Definition of channels ID bitfield information to be inserted into         */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
+
+/* Definition of channels sampling time information to be inserted into       */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
+#define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
+#define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
+#define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
+#define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
+#define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
+#define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
+#define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
+#define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
+#define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
+#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
+#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
+#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
+#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
+#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
+#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
+#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
+#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
+#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
+
+
+/* Internal mask for ADC mode single or differential ended:                   */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
+/* the relevant bits for:                                                     */
+/* (concatenation of multiple bits used in different registers)               */
+/* - ADC calibration: calibration start, calibration factor get or set        */
+/* - ADC channels: set each ADC channel ending mode                           */
+#define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
+
+
+/* Internal mask for ADC analog watchdog:                                     */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+/* (concatenation of multiple bits used in different analog watchdogs,        */
+/* (feature of several watchdogs not available on all STM32 families)).       */
+/* - analog watchdog 1: monitored channel defined by number,                  */
+/*   selection of ADC group (ADC groups regular and-or injected).             */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
+/*   selection on groups.                                                     */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET              (0x00000000U)
+#define ADC_AWD_CR2_REGOFFSET              (0x00100000U)
+#define ADC_AWD_CR3_REGOFFSET              (0x00200000U)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024U)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+
+
+/* Internal mask for ADC offset:                                              */
+/* Internal register offset for ADC offset number configuration */
+#define ADC_OFR1_REGOFFSET                 (0x00000000U)
+#define ADC_OFR2_REGOFFSET                 (0x00000001U)
+#define ADC_OFR3_REGOFFSET                 (0x00000002U)
+#define ADC_OFR4_REGOFFSET                 (0x00000003U)
+#define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS         ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS      (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
+#define ADC_TR1_HT1_BITOFFSET_POS          (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   ( 3000U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          ( 3000U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: isolate bits with the
+  *         selected mask and shift them to the register LSB
+  *         (shift mask on register position bit 0).
+  * @param  __BITS__ Bits in register 32 bits
+  * @param  __MASK__ Mask in register 32 bits
+  * @retval Bits in register 32 bits
+  */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
+  (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+  */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of ADC common parameters
+  *         and multimode
+  *         (all ADC instances belonging to the same ADC common instance).
+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+  *         is conditioned to ADC instances state (all ADC instances
+  *         sharing the same ADC common instance):
+  *         All ADC instances sharing the same ADC common instance must be
+  *         disabled.
+  */
+typedef struct
+{
+  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+                                             @note On this STM32 serie, if ADC group injected is used, some
+                                                   clock ratio constraints between ADC clock and AHB clock
+                                                   must be respected. Refer to reference manual.
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+
+  uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
+
+  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 families).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t Resolution;                  /*!< Set ADC resolution.
+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+                                                   In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group regular sequencer is enabled
+                                                   (scan length of 2 ranks or more).
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+                                             data preserved or overwritten.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+                                                   In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group injected sequencer is enabled
+                                                   (scan length of 2 ranks or more).
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+                                             Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+  * @{
+  */
+#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */
+#define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+  * @{
+  */
+#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
+#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
+#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
+#define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */
+#define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */
+#define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */
+#define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+  * @{
+  */
+/* List of ADC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+#define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000U)                               /*!< ADC asynchronous clock without prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */
+#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */
+#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */
+#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */
+#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */
+#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */
+#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */
+#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */
+#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */
+#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */
+#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define LL_ADC_RESOLUTION_12B              (0x00000000U)             /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
+#define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+  * @{
+  */
+#define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+  * @{
+  */
+#define LL_ADC_LP_MODE_NONE                (0x00000000U)             /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
+  * @{
+  */
+#define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+  * @{
+  */
+#define LL_ADC_OFFSET_DISABLE              (0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define LL_ADC_GROUP_REGULAR               (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED              (0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003U) /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
+#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
+#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
+#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
+#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
+#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
+#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
+#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
+#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
+#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
+#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_0  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
+#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
+#if defined(ADC1) && !defined(ADC2)
+#define LL_ADC_CHANNEL_DAC1CH1             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
+#define LL_ADC_CHANNEL_DAC1CH2             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
+#elif defined(ADC2)
+#define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
+#define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
+#if defined(ADC3)
+#define LL_ADC_CHANNEL_DAC1CH1_ADC3        (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
+#define LL_ADC_CHANNEL_DAC1CH2_ADC3        (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
+#endif
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000U)                                                                                                   /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+  * @{
+  */
+#define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE             (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000U)              /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+  * @}
+  */
+
+#if defined(ADC_CFGR_DFSDMCFG)
+/** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DFSDM_TRANSFER_NONE     (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */
+#define LL_ADC_REG_DFSDM_TRANSFER_ENABLE   (ADC_CFGR_DFSDMCFG)     /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
+/**
+  * @}
+  */
+#endif /* ADC_CFGR_DFSDMCFG */
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT      (0x00000000U)       /*!< ADC sampling time let to default settings. */
+#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
+/**
+  * @}
+  */
+#endif /* ADC_SMPR1_SMPPLUS */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+* @{
+*/
+#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000U)                                     /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000U)                                                                                                       /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                     /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
+  * @{
+  */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
+#define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000U)         /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000U)                                               /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+  * @{
+  */
+#define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+  * @{
+  */
+#define LL_ADC_AWD_DISABLE                 (0x00000000U)                                                                             /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
+#if defined(ADC1) && !defined(ADC2)
+#define LL_ADC_AWD_CH_DAC1CH1_REG          ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH1_INJ          ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH1_REG_INJ      ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_DAC1CH2_REG          ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH2_INJ          ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH2_REG_INJ      ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
+#elif defined(ADC2)
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+#if defined(ADC3)
+#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
+#endif
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+  * @{
+  */
+#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+  * @{
+  */
+#define LL_ADC_OVS_DISABLE                 (0x00000000U)                               /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+#define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define LL_ADC_OVS_REG_CONT                (0x00000000U)/*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+#define LL_ADC_OVS_RATIO_2                 (0x00000000U)                                  /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
+  * @{
+  */
+#define LL_ADC_OVS_SHIFT_NONE              (0x00000000U)                                                     /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+/**
+  * @}
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define LL_ADC_MULTI_INDEPENDENT           (0x00000000U)                                             /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
+  * @{
+  */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000U)                            /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000U)                                                 /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
+  * @{
+  */
+#define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+  * @}
+  */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SW_START           (LL_ADC_REG_TRIG_SOFTWARE)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
+#define LL_ADC_REG_TRIG_EXT_TIM2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
+#define LL_ADC_REG_TRIG_EXT_TIM3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
+#define LL_ADC_REG_TRIG_EXT_TIM4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
+
+#define LL_ADC_INJ_TRIG_SW_START           (LL_ADC_INJ_TRIG_SOFTWARE)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
+
+#define LL_ADC_OVS_DATA_SHIFT_NONE        (LL_ADC_OVS_SHIFT_NONE)
+#define LL_ADC_OVS_DATA_SHIFT_1           (LL_ADC_OVS_SHIFT_RIGHT_1)
+#define LL_ADC_OVS_DATA_SHIFT_2           (LL_ADC_OVS_SHIFT_RIGHT_2)
+#define LL_ADC_OVS_DATA_SHIFT_3           (LL_ADC_OVS_SHIFT_RIGHT_3)
+#define LL_ADC_OVS_DATA_SHIFT_4           (LL_ADC_OVS_SHIFT_RIGHT_4)
+#define LL_ADC_OVS_DATA_SHIFT_5           (LL_ADC_OVS_SHIFT_RIGHT_5)
+#define LL_ADC_OVS_DATA_SHIFT_6           (LL_ADC_OVS_SHIFT_RIGHT_6)
+#define LL_ADC_OVS_DATA_SHIFT_7           (LL_ADC_OVS_SHIFT_RIGHT_7)
+#define LL_ADC_OVS_DATA_SHIFT_8           (LL_ADC_OVS_SHIFT_RIGHT_8)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+  * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+  
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values.                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Indications for estimation of ADC timeout delays, for this           */
+/*       STM32 serie:                                                         */
+/*       - ADC calibration time: maximum delay is 112/fADC.                   */
+/*         (refer to device datasheet, parameter "tCAL")                      */
+/*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+/*         (refer to device datasheet, parameter "tSTAB")                     */
+/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+/*         cycles                                                             */
+/*       - ADC conversion time: duration depending on ADC clock and ADC       */
+/*         configuration.                                                     */
+/*         (refer to device reference manual, section "Timing")               */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tADCVREG_STUP").                                                */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US (  10U)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time.                   */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tstart_vrefint").                                               */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_VREFINT_STAB_US       (  12U)  /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time.                           */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ( 120U)  /*!< Delay for temperature sensor stabilization time */
+
+/* Delay required between ADC end of calibration and ADC enable.              */
+/* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
+/*       are required between ADC end of calibration and ADC enable.          */
+/*       Wait time can be computed in user application by waiting for the     */
+/*       equivalent number of CPU cycles, by taking into account              */
+/*       ratio of CPU clock versus ADC clock prescalers.                      */
+/* Unit: ADC clock cycles.                                                    */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U)  /*!< Delay required between ADC end of calibration and ADC enable */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals LL_ADC_CHANNEL_x.
+  * @note   Example:
+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
+  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                  \
+    ? (                                                                                    \
+       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+      )                                                                                    \
+      :                                                                                    \
+      (                                                                                    \
+       POSITION_VAL((__CHANNEL__))                                                         \
+      )                                                                                    \
+  )
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
+  *         (1, 2, 3, 4) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \
+  (((__DECIMAL_NB__) <= 9U)                                                                                     \
+    ? (                                                                                                         \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       |        \
+       (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
+      )                                                                                                         \
+      :                                                                                                         \
+      (                                                                                                         \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                              | \
+       (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+      )                                                                                                         \
+  )
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#if defined (ADC1) && defined (ADC2) && defined (ADC3)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  (((__ADC_INSTANCE__) == ADC1)                                                \
+    ? (                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
+      )                                                                        \
+      :                                                                        \
+      ((__ADC_INSTANCE__) == ADC2)                                             \
+      ? (                                                                      \
+         ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \
+         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \
+         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \
+        )                                                                      \
+        :                                                                      \
+        ((__ADC_INSTANCE__) == ADC3)                                           \
+        ? (                                                                    \
+           ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                   \
+           ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                   \
+           ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                   \
+           ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) ||                   \
+           ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3)                      \
+          )                                                                    \
+          :                                                                    \
+          (0U)                                                                 \
+  )
+#elif defined (ADC1) && defined (ADC2)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  (((__ADC_INSTANCE__) == ADC1)                                                \
+    ? (                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
+      )                                                                        \
+      :                                                                        \
+      ((__ADC_INSTANCE__) == ADC2)                                             \
+      ? (                                                                      \
+         ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \
+         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \
+         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \
+        )                                                                      \
+        :                                                                      \
+        (0U)                                                                   \
+  )
+#elif defined (ADC1)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  (                                                                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)       ||                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1)    ||                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2)                                  \
+  )
+#endif
+
+/**
+  * @brief  Helper macro to define ADC analog watchdog parameter:
+  *         define a single channel to monitor with analog watchdog
+  *         from sequencer channel and groups definition.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+  *         Example:
+  *           LL_ADC_SetAnalogWDMonitChannels(
+  *             ADC1, LL_ADC_AWD1,
+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
+  *         (1, 2, 3, 4) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  * @param  __GROUP__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_GROUP_REGULAR
+  *         @arg @ref LL_ADC_GROUP_INJECTED
+  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ         (2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ         (2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)(6)
+  *         
+  *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.
+  */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
+  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
+    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                        \
+      :                                                                                                   \
+      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
+       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    \
+         :                                                                                                \
+         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  \
+  )
+
+/**
+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+  *         or @ref LL_ADC_SetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to set the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           LL_ADC_SetAnalogWDThresholds
+  *            (< ADCx param >,
+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is 
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to get the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+  *            (LL_ADC_RESOLUTION_8B,
+  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the ADC analog watchdog threshold high
+  *         or low from raw value containing both thresholds concatenated.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, to get analog watchdog threshold high from the register raw value:
+  *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
+  * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
+  (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
+
+/**
+  * @brief  Helper macro to set the ADC calibration value with both single ended
+  *         and differential modes calibration factors concatenated.
+  * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
+  *         Example, to set calibration factors single ended to 0x55
+  *         and differential ended to 0x2A:
+  *           LL_ADC_SetCalibrationFactor(
+  *             ADC1,
+  *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+  * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+  * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
+  (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
+  (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC123_COMMON)
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC12_COMMON)
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC1_COMMON)
+#endif
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1) |                                                    \
+   LL_ADC_IsEnabled(ADC2) |                                                    \
+   LL_ADC_IsEnabled(ADC3)  )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1) |                                                    \
+   LL_ADC_IsEnabled(ADC2)  )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1))
+#endif
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted 
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                         __ADC_RESOLUTION_CURRENT__,\
+                                         __ADC_RESOLUTION_TARGET__)            \
+  (((__DATA__)                                                                 \
+    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))    \
+   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))       \
+  )
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                      __ADC_DATA__,\
+                                      __ADC_RESOLUTION__)                      \
+  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+  )
+
+/* Legacy define */
+#define __LL_ADC_CALC_DATA_VOLTAGE()  __LL_ADC_CALC_DATA_TO_VOLTAGE()
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 serie, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                         __ADC_RESOLUTION__)                   \
+  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
+                                       (__ADC_RESOLUTION__),                   \
+                                       LL_ADC_RESOLUTION_12B)                  \
+  )
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor calibration values
+  *         stored in system memory for each device during production.
+  * @note   Calculation formula:
+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL1 (calibrated in factory)
+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL2 (calibrated in factory)
+  *         Caution: Calculation relevancy under reserve that calibration
+  *                  parameters are correct (address and data).
+  *                  To calculate temperature using temperature sensor
+  *                  datasheet typical values (generic values less, therefore
+  *                  less accurate than calibrated values),
+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   On this STM32 serie, calibration data of temperature sensor
+  *         corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         temperature sensor.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+  *                                 temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+  *                                 sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+                                  __TEMPSENSOR_ADC_DATA__,\
+                                  __ADC_RESOLUTION__)                              \
+  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
+                                                    (__ADC_RESOLUTION__),          \
+                                                    LL_ADC_RESOLUTION_12B)         \
+                   * (__VREFANALOG_VOLTAGE__))                                     \
+                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
+        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
+     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
+    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+   ) + TEMPSENSOR_CAL1_TEMP                                                        \
+  )
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  *                  If temperature sensor calibration values are available on
+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+  *                  temperature calculation will be more accurate using
+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+  *                                       On STM32L4, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                       On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                             __TEMPSENSOR_TYP_CALX_V__,\
+                                             __TEMPSENSOR_CALX_TEMP__,\
+                                             __VREFANALOG_VOLTAGE__,\
+                                             __TEMPSENSOR_ADC_DATA__,\
+                                             __ADC_RESOLUTION__)               \
+  ((( (                                                                        \
+       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+                 * 1000)                                                       \
+       -                                                                       \
+       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+                 * 1000)                                                       \
+      )                                                                        \
+    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
+   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
+  )
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+  * @{
+  */
+/* Note: LL ADC functions to set DMA transfer are located into sections of    */
+/*       configuration of ADC instance, groups and multimode (if available):  */
+/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+
+/**
+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+  *         ADC register address from ADC instance and a list of ADC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These ADC registers are data registers:
+  *         when ADC conversion data is available in ADC data registers,
+  *         ADC generates a DMA transfer request.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+  * @note   For devices with several ADC: in multimode, some devices
+  *         use a different data register outside of ADC instance scope
+  *         (common data register). This macro manages this register difference,
+  *         only ADC instance has to be set as parameter.
+  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
+  * @param  ADCx ADC instance
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+  *         
+  *         (1) Available on devices with several ADC instances.
+  * @retval ADC register address
+  */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+  register uint32_t data_reg_addr = 0U;
+  
+  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+  {
+    /* Retrieve address of register DR */
+    data_reg_addr = (uint32_t)&(ADCx->DR);
+  }
+  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+  {
+    /* Retrieve address of register CDR */
+    data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+  }
+  
+  return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+  /* Retrieve address of register DR */
+  return (uint32_t)&(ADCx->DR);
+}
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+  * @{
+  */
+
+/**
+  * @brief  Set parameter common to several ADC: Clock source and prescaler.
+  * @note   On this STM32 serie, if ADC group injected is used, some
+  *         clock ratio constraints between ADC clock and AHB clock
+  *         must be respected.
+  *         Refer to reference manual.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
+  *         CCR      PRESC          LL_ADC_SetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  CommonClock This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: Clock source and prescaler.
+  * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
+  *         CCR      PRESC          LL_ADC_GetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Set ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   This function is intended to set calibration parameters
+  *         without having to perform a new calibration using
+  *         @ref LL_ADC_StartCalibration().
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  *         (calibration factor must be specified for each of these
+  *         differential modes, if used afterwards and if the application
+  *         requires their calibration).
+  * @note   In case of setting calibration factors of both modes single ended
+  *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+  *         both calibration factors must be concatenated.
+  *         To perform this processing, use helper macro
+  *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled, without calibration on going, without conversion
+  *         on going on group regular.
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+  MODIFY_REG(ADCx->CALFACT,
+             SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+             CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
+}
+
+/**
+  * @brief  Get ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   Calibration factors are set by hardware after performing
+  *         a calibration run using function @ref LL_ADC_StartCalibration().
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Retrieve bits with position in register depending on parameter           */
+  /* "SingleDiff".                                                            */
+  /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
+  /* containing other bits reserved for other purpose.                        */
+  return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
+}
+
+/**
+  * @brief  Set ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     RES            LL_ADC_SetResolution
+  * @param  ADCx ADC instance
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+}
+
+/**
+  * @brief  Get ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR     RES            LL_ADC_GetResolution
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+}
+
+/**
+  * @brief  Set ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
+  * @param  ADCx ADC instance
+  * @param  DataAlignment This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+}
+
+/**
+  * @brief  Get ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+}
+
+/**
+  * @brief  Set ADC low power mode.
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - Do not use with interruption or DMA since these modes
+  *             have to clear immediately the EOC flag to free the
+  *             IRQ vector sequencer.
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
+  * @param  ADCx ADC instance
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+}
+
+/**
+  * @brief  Get ADC low power mode:
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - Do not use with interruption or DMA since these modes
+  *             have to clear immediately the EOC flag to free the
+  *             IRQ vector sequencer.
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+}
+
+/**
+  * @brief  Set ADC selected offset number 1, 2, 3 or 4.
+  * @note   This function set the 2 items of offset configuration:
+  *         - ADC channel to which the offset programmed will be applied
+  *           (independently of channel mapped on ADC group regular
+  *           or group injected)
+  *         - Offset level (offset to be subtracted from the raw
+  *           converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @note   This function enables the offset, by default. It can be forced
+  *         to disable state using function LL_ADC_SetOffsetState().
+  * @note   If a channel is mapped on several offsets numbers, only the offset
+  *         with the lowest value is considered for the subtraction.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @note   On STM32L4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
+  *         OFR1     OFFSET1        LL_ADC_SetOffset\n
+  *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2        LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3        LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4        LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+  
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+             ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         Channel to which the offset programmed will be applied
+  *         (independently of channel mapped on ADC group regular
+  *         or group injected)
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @note   On STM32L4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
+  *         (1, 2, 3, 4) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+  
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         Offset level (offset to be subtracted from the raw
+  *         converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
+  *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
+  *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
+  *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+  
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+/**
+  * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+  *         force offset state disable or enable
+  *         without modifying offset channel or offset value.
+  * @note   This function should be needed only in case of offset to be
+  *         enabled-disabled dynamically, and should not be needed in other cases:
+  *         function LL_ADC_SetOffset() automatically enables the offset.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
+  *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
+  *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
+  *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetState This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_DISABLE
+  *         @arg @ref LL_ADC_OFFSET_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
+{
+  register uint32_t *preg = (uint32_t *)((uint32_t)
+                            ((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
+  
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSET1_EN,
+             OffsetState);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         offset state disabled or enabled.
+  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
+  *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
+  *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
+  *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_DISABLE
+  *         @arg @ref LL_ADC_OFFSET_ENABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+  
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+}
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/**
+  * @brief  Set ADC sampling time common configuration impacting
+  *         settings of sampling time channel wise.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll SMPR1    SMPPLUS        LL_ADC_SetSamplingTimeCommonConfig
+  * @param  ADCx ADC instance
+  * @param  SamplingTimeCommonConfig This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
+{
+  MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
+}
+
+/**
+  * @brief  Get ADC sampling time common configuration impacting
+  *         settings of sampling time channel wise.
+  * @rmtoll SMPR1    SMPPLUS        LL_ADC_GetSamplingTimeCommonConfig
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
+}
+#endif /* ADC_SMPR1_SMPPLUS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group regular conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 serie, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge 
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 families having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_REG_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
+  *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group regular trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to 
+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
+  *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+  register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+  
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
+  register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
+  
+  /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
+          | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source internal (SW start)
+            or external.
+  * @note   In case of group regular trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_REG_GetTriggerSource().
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
+}
+
+/**
+  * @brief  Set ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+}
+
+
+/**
+  * @brief  Set ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group regular 
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   It is not possible to enable both ADC auto-injected mode
+  *         and ADC group regular sequencer discontinuous mode.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+  *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+  *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   This function performs configuration of:
+  *         - Channels ordering into each rank of scan sequence:
+  *           whatever channel can be placed into whatever rank.
+  * @note   On this STM32 serie, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 serie, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register and register position depending on parameter "Rank".         */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   On this STM32 serie, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
+  *         (1, 2, 3, 4) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+  
+  return (uint32_t) (READ_BIT(*preg,
+                              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                     << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                    );
+}
+
+/**
+  * @brief  Set ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @note   It is not possible to enable both ADC group regular 
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
+  * @param  ADCx ADC instance
+  * @param  Continuous This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+}
+
+/**
+  * @brief  Get ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+}
+
+/**
+  * @brief  Set ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *        (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
+  *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
+  * @param  ADCx ADC instance
+  * @param  DMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
+  *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+}
+
+#if defined(ADC_CFGR_DFSDMCFG)
+/**
+  * @brief  Set ADC group regular conversion data transfer to DFSDM.
+  * @note   DFSDM transfer cannot be used if DMA transfer is enabled.
+  * @note   To configure DFSDM source address (peripheral address),
+  *         use the same function as for DMA transfer:
+  *         function @ref LL_ADC_DMA_GetRegAddr().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     DFSDMCFG       LL_ADC_REG_GetDFSDMTransfer
+  * @param  ADCx ADC instance
+  * @param  DFSDMTransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data transfer to DFSDM.
+  * @rmtoll CFGR     DFSDMCFG       LL_ADC_REG_GetDFSDMTransfer
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
+}
+#endif /* ADC_CFGR_DFSDMCFG */
+
+/**
+  * @brief  Set ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @note   Compatibility with devices without feature overrun:
+  *         other devices without this feature have a behavior
+  *         equivalent to data overwritten.
+  *         The default setting of overrun is data preserved.
+  *         Therefore, for compatibility with all devices, parameter
+  *         overrun should be set to data overwritten.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
+  * @param  ADCx ADC instance
+  * @param  Overrun This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+}
+
+/**
+  * @brief  Get ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group injected conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 serie, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge 
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 families having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_INJ_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group injected trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to 
+  *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+  register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+  
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
+  register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
+  
+  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
+          | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source internal (SW start)
+            or external
+  * @note   In case of group injected trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_INJ_GetTriggerSource.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer length and scan direction.
+  * @note   This function performs configuration of:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer length and scan direction.
+  * @note   This function retrieves:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 serie, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 serie, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register depending on parameter "Rank".                               */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  MODIFY_REG(ADCx->JSQR,
+             ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
+             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
+}
+
+/**
+  * @brief  Get ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
+  *         (1, 2, 3, 4) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR,
+                             ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
+                    << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+                   );
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @note   This mode can be used to extend number of data registers
+  *         updated after one ADC conversion trigger and with data 
+  *         permanently kept (not erased by successive conversions of scan of
+  *         ADC sequencer ranks), up to 5 data registers:
+  *         1 data register on ADC group regular, 4 data registers
+  *         on ADC group injected.            
+  * @note   If ADC group injected injected trigger source is set to an
+  *         external trigger, this feature must be must be set to
+  *         independent trigger.
+  *         ADC group injected automatic trigger is compliant only with 
+  *         group injected trigger source set to SW start, without any 
+  *         further action on  ADC group injected conversion start or stop: 
+  *         in this case, ADC group injected is controlled only 
+  *         from ADC group regular.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
+  * @param  ADCx ADC instance
+  * @param  TrigAuto This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+}
+
+/**
+  * @brief  Set ADC group injected contexts queue mode.
+  * @note   A context is a setting of group injected sequencer:
+  *         - group injected trigger
+  *         - sequencer length
+  *         - sequencer ranks
+  *         If contexts queue is disabled:
+  *         - only 1 sequence can be configured
+  *           and is active perpetually.
+  *         If contexts queue is enabled:
+  *         - up to 2 contexts can be queued
+  *           and are checked in and out as a FIFO stack (first-in, first-out).
+  *         - If a new context is set when queues is full, error is triggered
+  *           by interruption "Injected Queue Overflow".
+  *         - Two behaviors are possible when all contexts have been processed:
+  *           the contexts queue can maintain the last context active perpetually
+  *           or can be empty and injected group triggers are disabled.
+  *         - Triggers can be only external (not internal SW start)
+  *         - Caution: The sequence must be fully configured in one time
+  *           (one write of register JSQR makes a check-in of a new context
+  *           into the queue).
+  *           Therefore functions to set separately injected trigger and
+  *           sequencer channels cannot be used, register JSQR must be set
+  *           using function @ref LL_ADC_INJ_ConfigQueueContext().
+  * @note   This parameter can be modified only when no conversion is on going
+  *         on either groups regular or injected.
+  * @note   A modification of the context mode (bit JQDIS) causes the contexts
+  *         queue to be flushed and the register JSQR is cleared.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
+  *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
+  * @param  ADCx ADC instance
+  * @param  QueueMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
+}
+
+/**
+  * @brief  Get ADC group injected context queue mode.
+  * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
+  *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
+}
+
+/**
+  * @brief  Set one context on ADC group injected that will be checked in
+  *         contexts queue.
+  * @note   A context is a setting of group injected sequencer:
+  *         - group injected trigger
+  *         - sequencer length
+  *         - sequencer ranks
+  *         This function is intended to be used when contexts queue is enabled,
+  *         because the sequence must be fully configured in one time
+  *         (functions to set separately injected trigger and sequencer channels
+  *         cannot be used):
+  *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
+  * @note   In the contexts queue, only the active context can be read.
+  *         The parameters of this function can be read using functions:
+  *         @arg @ref LL_ADC_INJ_GetTriggerSource()
+  *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
+  *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
+  * @note   On this STM32 serie, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 serie, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  *
+  *         Note: This parameter is discarded in case of SW start:
+  *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @param  Rank1_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @param  Rank2_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @param  Rank3_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @param  Rank4_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+                                                   uint32_t TriggerSource,
+                                                   uint32_t ExternalTriggerEdge,
+                                                   uint32_t SequencerNbRanks,
+                                                   uint32_t Rank1_Channel,
+                                                   uint32_t Rank2_Channel,
+                                                   uint32_t Rank3_Channel,
+                                                   uint32_t Rank4_Channel)
+{
+  /* Set bits with content of parameter "Rankx_Channel" with bits position    */
+  /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
+  /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
+  /* because containing other bits reserved for other purpose.                */
+  /* If parameter "TriggerSource" is set to SW start, then parameter          */
+  /* "ExternalTriggerEdge" is discarded.                                      */
+  MODIFY_REG(ADCx->JSQR           ,
+             ADC_JSQR_JEXTSEL |
+             ADC_JSQR_JEXTEN  |
+             ADC_JSQR_JSQ4    |
+             ADC_JSQR_JSQ3    |
+             ADC_JSQR_JSQ2    |
+             ADC_JSQR_JSQ1    |
+             ADC_JSQR_JL          ,
+             TriggerSource       |
+             (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) |
+             ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+             ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+             ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+             ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+             SequencerNbRanks
+            );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+  * @{
+  */
+
+/**
+  * @brief  Set sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 serie, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @param  SamplingTime This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+  *
+  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+  *             can be replaced by 3.5 ADC clock cycles.
+  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+  /* Set bits with content of parameter "SamplingTime" with bits position     */
+  /* in register and register position depending on parameter "Channel".      */
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+             SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 serie, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1            (7)
+  *         @arg @ref LL_ADC_CHANNEL_2            (7)
+  *         @arg @ref LL_ADC_CHANNEL_3            (7)
+  *         @arg @ref LL_ADC_CHANNEL_4            (7)
+  *         @arg @ref LL_ADC_CHANNEL_5            (7)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
+  *         
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
+  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+  *
+  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+  *             can be replaced by 3.5 ADC clock cycles.
+  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+  
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+                    >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   Channel ending is on channel scope: independently of channel mapped
+  *         on ADC group regular or injected.
+  *         In differential mode: Differential measurement is carried out
+  *         between the selected channel 'i' (positive input) and
+  *         channel 'i+1' (negative input). Only channel 'i' has to be
+  *         configured, channel 'i+1' is configured automatically.
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
+  *         are internally fixed to single-ended inputs configuration.
+  * @note   For ADC channels configured in differential mode, both inputs
+  *         should be biased at (Vref+)/2 +/-200mV.
+  *         (Vref+ is the analog voltage reference)
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  * @param  SingleDiff This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+  /* Bits of channels in single or differential mode are set only for         */
+  /* differential mode (for single mode, mask of bits allowed to be set is    */
+  /* shifted out of range of bits of channels in single or differential mode. */
+  MODIFY_REG(ADCx->DIFSEL,
+             Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+             (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Get mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  *         Therefore, to ensure a channel is configured in single-ended mode,
+  *         the configuration of channel itself and the channel 'i-1' must be
+  *         read back (to ensure that the selected channel channel has not been
+  *         configured in differential mode by the previous channel).
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
+  *         are internally fixed to single-ended inputs configuration.
+  * @note   One or several values can be selected. In this case, the value
+  *         returned is null if all channels are in single ended-mode.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  * @retval 0: channel in single-ended mode, else: channel in differential mode
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+  * @{
+  */
+
+/**
+  * @brief  Set ADC analog watchdog monitored channels:
+  *         a single channel, multiple channels or all channels,
+  *         on ADC groups regular and-or injected.
+  * @note   Once monitored channels are selected, analog watchdog
+  *         is enabled.
+  * @note   In case of need to define a single channel to monitor
+  *         with analog watchdog from sequencer channel definition,
+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+  * @note   On this STM32 serie, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDChannelGroup This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ         (2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ          (0)(2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ         (2)(5)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)(6)
+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)(6)
+  *         
+  *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
+  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
+  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
+  *         (6) On STM32L4, parameter available on devices with several ADC instances.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
+  /* in register and register position depending on parameter "AWDy".         */
+  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
+  /* containing other bits reserved for other purpose.                        */
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+  
+  MODIFY_REG(*preg,
+             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+             AWDChannelGroup & AWDy);
+}
+
+/**
+  * @brief  Get ADC analog watchdog monitored channel.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Applicable only when the analog watchdog is set to monitor
+  *           one channel.
+  * @note   On this STM32 serie, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2 (1)
+  *         @arg @ref LL_ADC_AWD3 (1)
+  *         
+  *         (1) On this AWD number, monitored channel can be retrieved
+  *             if only 1 channel is programmed (or none or all channels).
+  *             This function cannot retrieve monitored channel if
+  *             multiple channels are programmed simultaneously
+  *             by bitfield.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         
+  *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+  
+  /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to   */
+  /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK.                   */
+  register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
+  
+  /* Set variable of AWD1 monitored channel according to AWD1 features        */
+  /* and ADC channel definition:                                              */
+  /* - channel ID with number                                                 */
+  /* - channel ID with bitfield                                               */
+  /* - AWD1 single or all channels                                            */
+  /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of  */
+  /*   AWD2 or AWD3 selected).                                                */
+  register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
+  
+  register uint32_t AWD1ChannelGroup = ( (  AWD123ChannelGroup
+                                          | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
+                                          | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & 0x00000001U))
+                                         )
+                                        * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
+                                       );
+  
+  /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3      */
+  /* features and ADC channel definition:                                     */
+  /* - channel ID with number                                                 */
+  /* - channel ID with bitfield                                               */
+  /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to    */
+  /*   shift AWD1 equivalent single-all channels out of register)             */
+  /* - AWD2-3 enable or disable                                               */
+  /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3,    */
+  /*       channel can be read back if only 1 channel monitoring              */
+  /*       is activated, therefore the channel monitoring value channel "3"   */
+  /*       is not not supported by this function, there is no risk of         */
+  /*       conflict.                                                          */
+  register uint32_t AWD23Enabled = ((0x00000001U >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
+  
+  register uint32_t AWD23ChannelGroup = (((  AWD123ChannelGroup
+                                           | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+                                           | ((ADC_CFGR_AWD1SGL) >> ((0x00000001U >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
+                                           | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)
+                                          ) >> AWD23Enabled
+                                         ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U));
+  
+  return (AWD1ChannelGroup | AWD23ChannelGroup);
+}
+
+/**
+  * @brief  Set ADC analog watchdog thresholds value of both thresholds
+  *         high and low.
+  * @note   If value of only one threshold high or low must be set,
+  *         use function @ref LL_ADC_SetAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 serie, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
+{
+  /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
+  /* position in register and register position depending on parameter        */
+  /* "AWDy".                                                                  */
+  /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+  /* containing other bits reserved for other purpose.                        */
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             ADC_TR1_HT1 | ADC_TR1_LT1,
+             (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+}
+
+/**
+  * @brief  Set ADC analog watchdog threshold value of threshold
+  *         high or low.
+  * @note   If values of both thresholds high or low must be set,
+  *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 serie, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+  /* position in register and register position depending on parameters       */
+  /* "AWDThresholdsHighLow" and "AWDy".                                       */
+  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+  /* containing other bits reserved for other purpose.                        */
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             AWDThresholdsHighLow,
+             AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
+}
+
+/**
+  * @brief  Get ADC analog watchdog threshold value of threshold high,
+  *         threshold low or raw data with ADC thresholds high and low
+  *         concatenated.
+  * @note   If raw data with ADC thresholds high and low is retrieved,
+  *         the data of each threshold high or low can be isolated
+  *         using helper macro:
+  *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+  * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+  
+  return (uint32_t)(READ_BIT(*preg,
+                             (AWDThresholdsHighLow | ADC_TR1_LT1))
+                    >> POSITION_VAL(AWDThresholdsHighLow)
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+  * @{
+  */
+
+/**
+  * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 families).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @param  OvsScope This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+}
+
+/**
+  * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 families).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+}
+
+/**
+  * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   On this STM32 serie, oversampling discontinuous mode 
+  *         (triggered mode) can be used only when oversampling is 
+  *         set on group regular only and in resumed mode.
+  * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @param  OverSamplingDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+}
+
+/**
+  * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+}
+
+/**
+  * @brief  Set ADC oversampling
+  *         (impacting both ADC groups regular and injected)
+  * @note   This function set the 2 items of oversampling configuration:
+  *         - ratio
+  *         - shift
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+  * @param  ADCx ADC instance
+  * @param  Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  * @param  Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+}
+
+/**
+  * @brief  Get ADC oversampling ratio
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+  * @param  ADCx ADC instance
+  * @retval Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+}
+
+/**
+  * @brief  Get ADC oversampling shift
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+  * @param  ADCx ADC instance
+  * @retval Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+  * @{
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Set ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  Multimode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+  * @brief  Get ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+  * @brief  Set ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled
+  *         or enabled without conversion on going on group regular.
+  * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
+  *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiDMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
+}
+
+/**
+  * @brief  Get ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
+  *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+}
+
+/**
+  * @brief  Set ADC multimode delay between 2 sampling phases.
+  * @note   The sampling delay range depends on ADC resolution:
+  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
+  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
+  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
+  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+  *         
+  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+  *         (3) Parameter available only if ADC resolution is 12 bits.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+  * @brief  Get ADC multimode delay between 2 sampling phases.
+  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+  *         
+  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+  *         (3) Parameter available only if ADC resolution is 12 bits.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+/** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name
+  * @{
+  */
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+__STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource);
+}
+__STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Put ADC instance in deep power down state.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_DEEPPWD);
+}
+
+/**
+  * @brief  Disable ADC deep power down mode.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance deep power down state.
+  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD));
+}
+
+/**
+  * @brief  Enable ADC instance internal voltage regulator.
+  * @note   On this STM32 serie, after ADC internal voltage regulator enable,
+  *         a delay for ADC internal voltage regulator stabilization
+  *         is required before performing a ADC calibration or ADC enable.
+  *         Refer to device datasheet, parameter tADCVREG_STUP.
+  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADVREGEN);
+}
+
+/**
+  * @brief  Disable ADC internal voltage regulator.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance internal voltage regulator state.
+  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
+}
+
+/**
+  * @brief  Enable the selected ADC instance.
+  * @note   On this STM32 serie, after ADC enable, a delay for 
+  *         ADC internal analog stabilization is required before performing a
+  *         ADC conversion start.
+  *         Refer to device datasheet, parameter tSTAB.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+  * @rmtoll CR       ADEN           LL_ADC_Enable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADEN);
+}
+
+/**
+  * @brief  Disable the selected ADC instance.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be not disabled. Must be enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CR       ADDIS          LL_ADC_Disable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADDIS);
+}
+
+/**
+  * @brief  Get the selected ADC instance enable state.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
+}
+
+/**
+  * @brief  Get the selected ADC instance disable state.
+  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no ADC disable command on going.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
+}
+
+/**
+  * @brief  Start ADC calibration in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   On this STM32 serie, a minimum number of ADC clock cycles
+  *         are required between ADC end of calibration and ADC enable.
+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  *         (calibration run must be performed for each of these
+  *         differential modes, if used afterwards and if the application
+  *         requires their calibration).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
+  *         CR       ADCALDIF       LL_ADC_StartCalibration
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+  * @brief  Get ADC calibration state.
+  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+  * @param  ADCx ADC instance
+  * @retval 0: calibration complete, 1: calibration in progress.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group regular conversion.
+  * @note   On this STM32 serie, this function is relevant for both 
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTART);
+}
+
+/**
+  * @brief  Stop ADC group regular conversion.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTP);
+}
+
+/**
+  * @brief  Get ADC group regular conversion state.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
+}
+
+/**
+  * @brief  Get ADC group regular command of conversion stop state
+  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get ADC multimode conversion data of ADC master, ADC slave
+  *         or raw data with ADC master and slave concatenated.
+  * @note   If raw data with ADC master and slave concatenated is retrieved,
+  *         a macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  *         (however this macro is mainly intended for multimode
+  *         transfer by DMA, because this function can do the same
+  *         by getting multimode conversion data of ADC master or ADC slave
+  *         separately).
+  * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
+  *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  ConversionData This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+                             ConversionData)
+                    >> POSITION_VAL(ConversionData)
+                   );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group injected conversion.
+  * @note   On this STM32 serie, this function is relevant for both 
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group injected,
+  *         without conversion stop command on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTART);
+}
+
+/**
+  * @brief  Stop ADC group injected conversion.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTP);
+}
+
+/**
+  * @brief  Get ADC group injected conversion state.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
+}
+
+/**
+  * @brief  Get ADC group injected command of conversion stop state
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+  * @{
+  */
+
+/**
+  * @brief  Get flag ADC ready.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
+}
+
+/**
+  * @brief  Get flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
+}
+
+/**
+  * @brief  Get flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
+}
+
+/**
+  * @brief  Get flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
+}
+
+/**
+  * @brief  Get flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+  * @brief  Get flag ADC group injected contexts queue overflow.
+  * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 1 flag
+  * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
+}
+
+/**
+  * @brief  Clear flag ADC ready.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+  * @brief  Clear flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+  * @brief  Clear flag ADC group injected contexts queue overflow.
+  * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 1.
+  * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get flag multimode ADC ready of the ADC master.
+  * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC ready of the ADC slave.
+  * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+  * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+  * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC master.
+  * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
+  * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
+  * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
+  * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+  * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+  * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
+  * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
+  * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
+  * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
+}
+
+/**
+  * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
+  * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
+  * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
+  * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
+  * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
+  * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Enable ADC group regular interruption overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected context queue overflow.
+  * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Disable interruption ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group injected context queue overflow.
+  * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Get state of interruption ADC ready
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular overrun
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sampling
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
+}
+
+/**
+  * @brief  Get state of interruption ADC analog watchdog 1
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 2
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 3
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h
new file mode 100755
index 0000000..c4ffe5a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h
@@ -0,0 +1,1827 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_bus.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of BUS LL module.
+
+  @verbatim                
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]  
+      A delay between an RCC peripheral clock enable and the effective peripheral 
+      enabling should be taken into account in order to manage the peripheral read/write 
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]  
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_BUS_H
+#define __STM32L4xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
+#define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHB1ENR_FLASHEN
+#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
+#define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHB1ENR_TSCEN
+#if defined(DMA2D)
+#define LL_AHB1_GRP1_PERIPH_DMA2D          RCC_AHB1ENR_DMA2DEN
+#endif /* DMA2D */
+#define LL_AHB1_GRP1_PERIPH_SRAM1          RCC_AHB1SMENR_SRAM1SMEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_AHB2_GRP1_PERIPH_GPIOA          RCC_AHB2ENR_GPIOAEN
+#define LL_AHB2_GRP1_PERIPH_GPIOB          RCC_AHB2ENR_GPIOBEN
+#define LL_AHB2_GRP1_PERIPH_GPIOC          RCC_AHB2ENR_GPIOCEN
+#if defined(GPIOD)
+#define LL_AHB2_GRP1_PERIPH_GPIOD          RCC_AHB2ENR_GPIODEN
+#endif /*GPIOD*/
+#if defined(GPIOE)
+#define LL_AHB2_GRP1_PERIPH_GPIOE          RCC_AHB2ENR_GPIOEEN
+#endif /*GPIOE*/
+#if defined(GPIOF)
+#define LL_AHB2_GRP1_PERIPH_GPIOF          RCC_AHB2ENR_GPIOFEN
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_AHB2_GRP1_PERIPH_GPIOG          RCC_AHB2ENR_GPIOGEN
+#endif /* GPIOG */
+#define LL_AHB2_GRP1_PERIPH_GPIOH          RCC_AHB2ENR_GPIOHEN
+#if defined(GPIOI)
+#define LL_AHB2_GRP1_PERIPH_GPIOI          RCC_AHB2ENR_GPIOIEN
+#endif /* GPIOI */
+#if defined(USB_OTG_FS)
+#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+#endif /* USB_OTG_FS */
+#define LL_AHB2_GRP1_PERIPH_ADC            RCC_AHB2ENR_ADCEN
+#if defined(DCMI)
+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+#endif /* DCMI */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+#endif /* AES */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+#define LL_AHB2_GRP1_PERIPH_SRAM2          RCC_AHB2SMENR_SRAM2SMEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(FMC_Bank1_R)
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#endif /* FMC_Bank1_R */
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR1_TIM3EN
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR1_TIM4EN
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR1_TIM5EN
+#endif /* TIM5 */
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR1_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR1_TIM7EN
+#if defined(LCD)
+#define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR1_LCDEN
+#endif /* LCD */
+#if defined(RCC_APB1ENR1_RTCAPBEN)
+#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR1_RTCAPBEN
+#endif /* RCC_APB1ENR1_RTCAPBEN */
+#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN
+#endif /* SPI2 */
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR1_SPI3EN
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR1_USART2EN
+#if defined(USART3)
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR1_USART3EN
+#endif /* USART3 */
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR1_UART4EN
+#endif /* UART4 */
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR1_UART5EN
+#endif /* UART5 */
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN
+#if defined(I2C2)
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR1_I2C2EN
+#endif /* I2C2 */
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN
+#if defined(CRS)
+#define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR1_CRSEN
+#endif /* CRS */
+#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR1_CAN1EN
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR1_CAN2EN
+#endif /* CAN2 */
+#if defined(USB)
+#define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR1_USBFSEN
+#endif /* USB */
+#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR1_PWREN
+#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR1_DAC1EN
+#define LL_APB1_GRP1_PERIPH_OPAMP          RCC_APB1ENR1_OPAMPEN
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP2_PERIPH_ALL            0xFFFFFFFFU
+#define LL_APB1_GRP2_PERIPH_LPUART1        RCC_APB1ENR2_LPUART1EN
+#if defined(I2C4)
+#define LL_APB1_GRP2_PERIPH_I2C4           RCC_APB1ENR2_I2C4EN
+#endif /* I2C4 */
+#if defined(SWPMI1)
+#define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1ENR2_SWPMI1EN
+#endif /* SWPMI1 */
+#define LL_APB1_GRP2_PERIPH_LPTIM2         RCC_APB1ENR2_LPTIM2EN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN
+#define LL_APB2_GRP1_PERIPH_FW             RCC_APB2ENR_FWEN
+#if defined(SDMMC1)
+#define LL_APB2_GRP1_PERIPH_SDMMC1         RCC_APB2ENR_SDMMC1EN
+#endif /* SDMMC1 */
+#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
+#endif /* TIM8 */
+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
+#if defined(TIM17)
+#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
+#endif /* TIM17 */
+#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
+#if defined(SAI2)
+#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
+#endif /* SAI2 */
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN
+#endif /* DFSDM1_Channel0 */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+*/
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM          LL_APB2_GRP1_PERIPH_DFSDM1
+#endif /* DFSDM1_Channel0 */
+/**
+@endcond
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      TSCEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2DEN       LL_AHB1_GRP1_EnableClock  
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      TSCEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2DEN       LL_AHB1_GRP1_IsEnabledClock  
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      TSCEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2DEN       LL_AHB1_GRP1_DisableClock  
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1ENR      DMA2DRST      LL_AHB1_GRP1_ReleaseReset 
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    DMA2DSMEN     LL_AHB1_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    DMA2DSMEN     LL_AHB1_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOIEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      ADCEN         LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      AESEN         LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOIEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      ADCEN         LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      AESEN         LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOIEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      ADCEN         LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      AESEN         LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIOFRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIOGRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     GPIOIRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     OTGFSRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     AESRST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIOFRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIOGRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     GPIOIRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     OTGFSRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     AESRST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOISMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    OTGFSSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    DCMISMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    HASHSMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOISMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    OTGFSSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    DCMISMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    HASHSMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_EnableClockStopSleep\n
+  *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_DisableClockStopSleep\n
+  *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     LCDEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     CRSEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     CAN1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     USBFSEN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     CAN2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     PWREN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     DAC1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_EnableClock\n
+  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_EnableClock\n
+  *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_EnableClock\n
+  *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     LCDEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     CRSEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USBFSEN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     DAC1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     LCDEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     CRSEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     CAN1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     USBFSEN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     CAN2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     PWREN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     DAC1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR1, Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_DisableClock\n
+  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_DisableClock\n
+  *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_DisableClock\n
+  *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR2, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    TIM3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    TIM4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    TIM5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    TIM6RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    TIM7RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    SPI3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    USART2RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    USART3RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    UART4RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    UART5RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    I2C2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    CAN1RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    USBFSRST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    CAN2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    PWRRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    DAC1RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    OPAMPRST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ForceReset\n
+  *         APB1RSTR2    I2C4RST       LL_APB1_GRP2_ForceReset\n
+  *         APB1RSTR2    SWPMI1RST     LL_APB1_GRP2_ForceReset\n
+  *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_ALL
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    TIM3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    TIM4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    TIM5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    TIM6RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    TIM7RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    SPI3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    USART2RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    USART3RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    UART4RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    UART5RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    I2C2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    CAN1RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    USBFSRST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    CAN2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    PWRRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    DAC1RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    OPAMPRST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ReleaseReset\n
+  *         APB1RSTR2    I2C4RST       LL_APB1_GRP2_ReleaseReset\n
+  *         APB1RSTR2    SWPMI1RST     LL_APB1_GRP2_ReleaseReset\n
+  *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_ALL
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   TIM3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   TIM4SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   TIM5SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   TIM6SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   TIM7SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   SPI3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   USART2SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   USART3SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   UART4SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   UART5SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   I2C2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   CAN1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   USBFSSMEN     LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   CAN2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   PWRSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   DAC1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   OPAMPSMEN     LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1SMENR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_EnableClockStopSleep\n
+  *         APB1SMENR2   I2C4SMEN      LL_APB1_GRP2_EnableClockStopSleep\n
+  *         APB1SMENR2   SWPMI1SMEN    LL_APB1_GRP2_EnableClockStopSleep\n
+  *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1SMENR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   TIM3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   TIM4SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   TIM5SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   TIM6SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   TIM7SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   SPI3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   USART2SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   USART3SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   UART4SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   UART5SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   I2C2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   CAN1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   USBFSSMEN     LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   CAN2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   PWRSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   DAC1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   OPAMPSMEN     LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1SMENR1, Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_DisableClockStopSleep\n
+  *         APB1SMENR2   I2C4SMEN      LL_APB1_GRP2_DisableClockStopSleep\n
+  *         APB1SMENR2   SWPMI1SMEN    LL_APB1_GRP2_DisableClockStopSleep\n
+  *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1SMENR2, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      FWEN          LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      FWEN          LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SDMMC1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SDMMC1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    SDMMC1SMEN    LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    TIM8SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    TIM15SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    SAI2SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR    DFSDM1SMEN    LL_APB2_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    SDMMC1SMEN    LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    TIM8SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    TIM15SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    SAI2SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR    DFSDM1SMEN    LL_APB2_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c
new file mode 100755
index 0000000..27b494c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c
@@ -0,0 +1,343 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_comp.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   COMP LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_comp.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP_LL COMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of COMP hierarchical scope:          */
+/* COMP instance.                                                             */
+
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
+  (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
+   || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
+   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
+  )
+
+/* Note: On this STM32 serie, comparator input plus parameters are            */
+/*       the same on all COMP instances.                                      */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#if defined(COMP_CSR_INPSEL_1)
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
+  (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
+   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
+   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                             \
+  )
+#else
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
+  (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
+   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
+  )
+#endif
+
+/* Note: On this STM32 serie, comparator input minus parameters are           */
+/*       the same on all COMP instances.                                      */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#if defined(COMP_CSR_INMESEL_1) && defined(DAC_CHANNEL2_SUPPORT)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
+  (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5)                           \
+  )
+#elif defined(COMP_CSR_INMESEL_1)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
+  (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5)                           \
+  )
+#elif defined(DAC_CHANNEL2_SUPPORT)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
+  (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
+  )
+#else
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
+  (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
+  )
+#endif
+
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
+  (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
+   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
+   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
+   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
+  )
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
+  (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
+   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
+  )
+
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)          \
+  (   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)    \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of the selected COMP instance
+  *         to their default reset values.
+  * @note   If comparator is locked, de-initialization by software is
+  *         not possible.
+  *         The only way to unlock the comparator is a device hardware reset.
+  * @param  COMPx COMP instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: COMP registers are de-initialized
+  *          - ERROR: COMP registers are not de-initialized
+  */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+  
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       COMP instance must not be locked.                                  */
+  if(LL_COMP_IsLocked(COMPx) == 0U)
+  {
+    LL_COMP_WriteReg(COMPx, CSR, 0x00000000U);
+
+  }
+  else
+  {
+    /* Comparator instance is locked: de-initialization by software is         */
+    /* not possible.                                                           */
+    /* The only way to unlock the comparator is a device hardware reset.       */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of COMP instance.
+  * @note   This function configures features of the selected COMP instance.
+  *         Some features are also available at scope COMP common instance
+  *         (common to several COMP instances).
+  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
+  * @param  COMPx COMP instance
+  * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: COMP registers are initialized
+  *          - ERROR: COMP registers are not initialized
+  */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+  assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+  assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+  assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+  assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
+  assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+  assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
+  
+  /* Note: Hardware constraint (refer to description of this function)        */
+  /*       COMP instance must not be locked.                                  */
+  if(LL_COMP_IsLocked(COMPx) == 0U)
+  {
+    /* Configuration of comparator instance :                                 */
+    /*  - PowerMode                                                           */
+    /*  - InputPlus                                                           */
+    /*  - InputMinus                                                          */
+    /*  - InputHysteresis                                                     */
+    /*  - OutputPolarity                                                      */
+    /*  - OutputBlankingSource                                                */
+#if defined(COMP_CSR_INMESEL_1)
+    MODIFY_REG(COMPx->CSR,
+                 COMP_CSR_PWRMODE
+               | COMP_CSR_INPSEL
+               | COMP_CSR_SCALEN
+               | COMP_CSR_BRGEN
+               | COMP_CSR_INMESEL
+               | COMP_CSR_INMSEL
+               | COMP_CSR_HYST
+               | COMP_CSR_POLARITY
+               | COMP_CSR_BLANKING
+              ,
+                 COMP_InitStruct->PowerMode
+               | COMP_InitStruct->InputPlus
+               | COMP_InitStruct->InputMinus
+               | COMP_InitStruct->InputHysteresis
+               | COMP_InitStruct->OutputPolarity
+               | COMP_InitStruct->OutputBlankingSource
+              );
+#else
+    MODIFY_REG(COMPx->CSR,
+                 COMP_CSR_PWRMODE
+               | COMP_CSR_INPSEL
+               | COMP_CSR_SCALEN
+               | COMP_CSR_BRGEN
+               | COMP_CSR_INMSEL
+               | COMP_CSR_HYST
+               | COMP_CSR_POLARITY
+               | COMP_CSR_BLANKING
+              ,
+                 COMP_InitStruct->PowerMode
+               | COMP_InitStruct->InputPlus
+               | COMP_InitStruct->InputMinus
+               | COMP_InitStruct->InputHysteresis
+               | COMP_InitStruct->OutputPolarity
+               | COMP_InitStruct->OutputBlankingSource
+              );
+#endif
+
+  }
+  else
+  {
+    /* Initialization error: COMP instance is locked.                         */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+  * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+  /* Set COMP_InitStruct fields to default values */
+  COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_ULTRALOWPOWER;
+  COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
+  COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
+  COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
+  COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
+  COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h
new file mode 100755
index 0000000..8d5d8f6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h
@@ -0,0 +1,896 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_comp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of COMP LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_COMP_H
+#define __STM32L4xx_LL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @defgroup COMP_LL COMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+  * @{
+  */
+
+/* COMP registers bits positions */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of COMP instance.
+  */
+typedef struct
+{
+  uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
+                                             This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+
+  uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+
+  uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+
+  uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
+
+  uint32_t OutputPolarity;              /*!< Set comparator output polarity.
+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+  uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+  * @{
+  */
+#define LL_COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)      /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+  * @{
+  */
+#define LL_COMP_POWERMODE_HIGHSPEED     ((uint32_t)0x00000000U)                   /*!< COMP power mode to high speed */
+#define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CSR_PWRMODE_0)                      /*!< COMP power mode to medium speed */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_PLUS_IO1          ((uint32_t)0x00000000U)                 /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
+#define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_INPSEL_0)                     /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
+#if defined(COMP_CSR_INPSEL_1)
+#define LL_COMP_INPUT_PLUS_IO3          (COMP_CSR_INPSEL_1)                     /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT  (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt  */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt  */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT  (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt  */
+#define LL_COMP_INPUT_MINUS_VREFINT     (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
+#endif
+#define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
+#if defined(COMP_CSR_INMESEL_1)
+#define LL_COMP_INPUT_MINUS_IO3         (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO4         (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO5         (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_LEGACY Comparator inputs legacy literals name
+  * @{
+  */
+#define LL_COMP_WINDOWMODE_ENABLE         LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define LL_COMP_INVERTINGINPUT_1_4VREFINT LL_COMP_INPUT_MINUS_1_4VREFINT
+#define LL_COMP_INVERTINGINPUT_1_2VREFINT LL_COMP_INPUT_MINUS_1_2VREFINT
+#define LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT
+#define LL_COMP_INVERTINGINPUT_VREFINT    LL_COMP_INPUT_MINUS_VREFINT
+#define LL_COMP_INVERTINGINPUT_DAC1       LL_COMP_INPUT_MINUS_DAC1_CH1
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_COMP_INVERTINGINPUT_DAC2       LL_COMP_INPUT_MINUS_DAC1_CH2
+#endif
+#define LL_COMP_INVERTINGINPUT_IO1        LL_COMP_INPUT_MINUS_IO1
+#define LL_COMP_INVERTINGINPUT_IO2        LL_COMP_INPUT_MINUS_IO2
+#if defined(COMP_CSR_INMESEL_1)
+#define LL_COMP_INVERTINGINPUT_IO3        LL_COMP_INPUT_MINUS_IO3
+#define LL_COMP_INVERTINGINPUT_IO4        LL_COMP_INPUT_MINUS_IO4
+#define LL_COMP_INVERTINGINPUT_IO5        LL_COMP_INPUT_MINUS_IO5
+#endif
+
+#define LL_COMP_NONINVERTINGINPUT_IO1     LL_COMP_INPUT_PLUS_IO1
+#define LL_COMP_NONINVERTINGINPUT_IO2     LL_COMP_INPUT_PLUS_IO2
+#if defined(COMP_CSR_INPSEL_1)
+#define LL_COMP_NONINVERTINGINPUT_IO3     LL_COMP_INPUT_PLUS_IO3
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+  * @{
+  */
+#define LL_COMP_HYSTERESIS_NONE         ((uint32_t)0x00000000U)             /*!< No hysteresis */
+#define LL_COMP_HYSTERESIS_LOW          (                  COMP_CSR_HYST_0) /*!< Hysteresis level low */
+#define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CSR_HYST_1                  ) /*!< Hysteresis level medium */
+#define LL_COMP_HYSTERESIS_HIGH         (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+  * @{
+  */
+#define LL_COMP_OUTPUTPOL_NONINVERTED   ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_POLARITY)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
+  * @{
+  */
+#define LL_COMP_BLANKINGSRC_NONE            ((uint32_t)0x00000000U) /*!<Comparator output without blanking */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1) */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE_LEGACY Comparator output blanking source legacy literals name
+  * @{
+  */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5    (LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)
+#define LL_COMP_BLANKINGSRC_TIM2_OC3    (LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)
+#define LL_COMP_BLANKINGSRC_TIM3_OC3    (LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)
+
+#define LL_COMP_BLANKINGSRC_TIM3_OC4    (LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)
+#define LL_COMP_BLANKINGSRC_TIM8_OC5    (LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)
+#define LL_COMP_BLANKINGSRC_TIM15_OC1   (LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+  * @{
+  */
+#define LL_COMP_OUTPUT_LEVEL_LOW        ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH       ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
+  * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for comparator startup time.                                         */
+/* Note: Delay required to reach propagation delay specification.             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 80U)  /*!< Delay for COMP startup time */
+
+/* Delay for comparator voltage scaler stabilization time.                    */
+/* Note: Voltage scaler is used when selecting comparator input               */
+/*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART_SCALER").                                                */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+  * @{
+  */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+  * @{
+  */
+
+/**
+  * @brief  Write a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to select the COMP common instance
+  *         to which is belonging the selected COMP instance.
+  * @note   COMP common register instance can be used to
+  *         set parameters common to several COMP instances.
+  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
+  * @param  __COMPx__ COMP instance
+  * @retval COMP common instance or value "0" if there is no COMP common instance.
+  */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
+  (COMP12_COMMON)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+  * @{
+  */
+
+/**
+  * @brief  Set window mode of a pair of comparators instances
+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+  * @rmtoll CSR      WINMODE        LL_COMP_SetCommonWindowMode
+  * @param  COMPxy_COMMON Comparator common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+  * @param  WindowMode This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+  /* Note: On this STM32 serie, window mode can be set only                   */
+  /*       from COMP instance: COMP2.                                         */
+  MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode);
+}
+
+/**
+  * @brief  Get window mode of a pair of comparators instances
+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+  * @rmtoll CSR      WINMODE        LL_COMP_GetCommonWindowMode
+  * @param  COMPxy_COMMON Comparator common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+  * @{
+  */
+
+/**
+  * @brief  Set comparator instance operating mode to adjust power and speed.
+  * @rmtoll CSR      PWRMODE        LL_COMP_SetPowerMode
+  * @param  COMPx Comparator instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode);
+}
+
+/**
+  * @brief  Get comparator instance operating mode to adjust power and speed.
+  * @rmtoll CSR      PWRMODE        LL_COMP_GetPowerMode
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+  * @{
+  */
+
+/**
+  * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   On this STM32 serie, scaler bridge is configurable:
+  *         to optimize power consumption, this function enables the
+  *         voltage scaler bridge only when required
+  *         (when selecting comparator input based on VrefInt: VrefInt or
+  *         subdivision of VrefInt).
+  *         - For scaler bridge power consumption values, 
+  *           refer to device datasheet, parameter "IDDA(SCALER)".
+  *         - Voltage scaler requires a delay for voltage stabilization.
+  *           Refer to device datasheet, parameter "tSTART_SCALER".
+  *         - Scaler bridge is common for all comparator instances,
+  *           therefore if at least one of the comparator instance
+  *           is requiring the scaler bridge, it remains enabled.
+  * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
+  *         CSR      INPSEL         LL_COMP_ConfigInputs\n
+  *         CSR      BRGEN          LL_COMP_ConfigInputs\n
+  *         CSR      SCALEN         LL_COMP_ConfigInputs
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
+  *         
+  *         (*) Parameter not available on all devices.
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
+  *         
+  *         (*) Parameter not available on all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+#if defined(COMP_CSR_INMESEL_1)
+  MODIFY_REG(COMPx->CSR,
+             COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
+             InputMinus | InputPlus);
+#else
+  MODIFY_REG(COMPx->CSR,
+             COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
+             InputMinus | InputPlus);
+#endif
+}
+
+/**
+  * @brief  Set comparator input plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INPSEL         LL_COMP_SetInputPlus
+  * @param  COMPx Comparator instance
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
+  *         
+  *         (*) Parameter not available on all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
+}
+
+/**
+  * @brief  Get comparator input plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INPSEL         LL_COMP_GetInputPlus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
+  *         
+  *         (*) Parameter not available on all devices.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
+}
+
+/**
+  * @brief  Set comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   On this STM32 serie, scaler bridge is configurable:
+  *         to optimize power consumption, this function enables the
+  *         voltage scaler bridge only when required
+  *         (when selecting comparator input based on VrefInt: VrefInt or
+  *         subdivision of VrefInt).
+  *         - For scaler bridge power consumption values, 
+  *           refer to device datasheet, parameter "IDDA(SCALER)".
+  *         - Voltage scaler requires a delay for voltage stabilization.
+  *           Refer to device datasheet, parameter "tSTART_SCALER".
+  *         - Scaler bridge is common for all comparator instances,
+  *           therefore if at least one of the comparator instance
+  *           is requiring the scaler bridge, it remains enabled.
+  * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus\n
+  *         CSR      BRGEN          LL_COMP_SetInputMinus\n
+  *         CSR      SCALEN         LL_COMP_SetInputMinus
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
+  *         
+  *         (*) Parameter not available on all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+#if defined(COMP_CSR_INMESEL_1)
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
+#else
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
+#endif
+}
+
+/**
+  * @brief  Get comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus\n
+  *         CSR      BRGEN          LL_COMP_GetInputMinus\n
+  *         CSR      SCALEN         LL_COMP_GetInputMinus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
+  *         
+  *         (*) Parameter not available on all devices.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_INMESEL_1)
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
+#else
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
+#endif
+}
+
+/**
+  * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
+  * @rmtoll CSR      HYST           LL_COMP_SetInputHysteresis
+  * @param  COMPx Comparator instance
+  * @param  InputHysteresis This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_HYSTERESIS_NONE
+  *         @arg @ref LL_COMP_HYSTERESIS_LOW
+  *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+  *         @arg @ref LL_COMP_HYSTERESIS_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
+}
+
+/**
+  * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
+  * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_HYSTERESIS_NONE
+  *         @arg @ref LL_COMP_HYSTERESIS_LOW
+  *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+  *         @arg @ref LL_COMP_HYSTERESIS_HIGH
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+  * @{
+  */
+
+/**
+  * @brief  Set comparator instance output polarity.
+  * @rmtoll CSR      POLARITY       LL_COMP_SetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @param  OutputPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
+}
+
+/**
+  * @brief  Get comparator instance output polarity.
+  * @rmtoll CSR      POLARITY       LL_COMP_GetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
+}
+
+/**
+  * @brief  Set comparator instance blanking source.
+  * @note   Blanking source may be specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   Availability of parameters of blanking source from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CSR      BLANKING       LL_COMP_SetOutputBlankingSource
+  * @param  COMPx Comparator instance
+  * @param  BlankingSource This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
+  *         
+  *         (1) Parameter availability depending on timer availability
+  *             on the selected device.
+  *         (2) On STM32L4, parameter available only on comparator instance: COMP1.
+  *         (3) On STM32L4, parameter available only on comparator instance: COMP2.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
+}
+
+/**
+  * @brief  Get comparator instance blanking source.
+  * @note   Availability of parameters of blanking source from timer
+  *         depends on timers availability on the selected device.
+  * @note   Blanking source may be specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      BLANKING       LL_COMP_GetOutputBlankingSource
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
+  *         
+  *         (1) Parameter availability depending on timer availability
+  *             on the selected device.
+  *         (2) On STM32L4, parameter available only on comparator instance: COMP1.
+  *         (3) On STM32L4, parameter available only on comparator instance: COMP2.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_Legacy_Functions Configuration of COMP, legacy functions name
+  * @{
+  */
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+__STATIC_INLINE void LL_COMP_SetInputNonInverting(COMP_TypeDef *COMPx, uint32_t InputNonInverting)
+{
+  LL_COMP_SetInputPlus(COMPx, InputNonInverting);
+}
+__STATIC_INLINE uint32_t LL_COMP_GetInputNonInverting(COMP_TypeDef *COMPx)
+{
+  return LL_COMP_GetInputPlus(COMPx);
+}
+
+__STATIC_INLINE void LL_COMP_SetInputInverting(COMP_TypeDef *COMPx, uint32_t InputInverting)
+{
+  LL_COMP_SetInputMinus(COMPx, InputInverting);
+}
+__STATIC_INLINE uint32_t LL_COMP_GetInputInverting(COMP_TypeDef *COMPx)
+{
+  return LL_COMP_GetInputMinus(COMPx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+  * @{
+  */
+
+/**
+  * @brief  Enable comparator instance.
+  * @note   After enable from off state, comparator requires a delay
+  *         to reach reach propagation delay specification.
+  *         Refer to device datasheet, parameter "tSTART".
+  * @rmtoll CSR      EN             LL_COMP_Enable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+  * @brief  Disable comparator instance.
+  * @rmtoll CSR      EN             LL_COMP_Disable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+  CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+  * @brief  Get comparator enable state
+  *         (0: COMP is disabled, 1: COMP is enabled)
+  * @rmtoll CSR      EN             LL_COMP_IsEnabled
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+  return (READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN));
+}
+
+/**
+  * @brief  Lock comparator instance.
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll CSR      LOCK           LL_COMP_Lock
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
+}
+
+/**
+  * @brief  Get comparator lock state
+  *         (0: COMP is unlocked, 1: COMP is locked).
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll CSR      LOCK           LL_COMP_IsLocked
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+  return (READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK));
+}
+
+/**
+  * @brief  Read comparator instance output level.
+  * @note   The comparator output level depends on the selected polarity
+  *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
+  *         If the comparator polarity is not inverted:
+  *          - Comparator output is low when the input plus
+  *            is at a lower voltage than the input minus
+  *          - Comparator output is high when the input plus
+  *            is at a higher voltage than the input minus
+  *         If the comparator polarity is inverted:
+  *          - Comparator output is high when the input plus
+  *            is at a lower voltage than the input minus
+  *          - Comparator output is low when the input plus
+  *            is at a higher voltage than the input minus
+  * @rmtoll CSR      VALUE          LL_COMP_ReadOutputLevel
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
+                    >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h
new file mode 100755
index 0000000..37c75bf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h
@@ -0,0 +1,657 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_CORTEX_H
+#define __STM32L4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+  {
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+  else
+  {
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c
new file mode 100755
index 0000000..2409b57
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c
@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_crc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   CRC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_crc.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize CRC registers (Registers restored to their default values).
+  * @param  CRCx CRC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: CRC registers are de-initialized
+  *          - ERROR: CRC registers are not de-initialized
+  */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+  if (CRCx == CRC)
+  {
+    /* Force CRC reset */
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
+
+    /* Release CRC reset */
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (CRC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.h
new file mode 100755
index 0000000..381e453
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.h
@@ -0,0 +1,479 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_crc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_CRC_H
+#define __STM32L4xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
+  * @{
+  */
+#define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
+  * @{
+  */
+#define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
+#define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
+#define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
+  * @{
+  */
+#define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
+  * @brief    Normal representation of this polynomial value is
+  *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Reset the CRC calculation unit.
+  * @note   If Programmable Initial CRC value feature
+  *         is available, also set the Data Register to the value stored in the
+  *         CRC_INIT register, otherwise, reset Data Register to its default value.
+  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
+  * @param  CRCx CRC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+  SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+  * @brief  Configure size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @param  PolySize This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
+}
+
+/**
+  * @brief  Return size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the input data
+  * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
+}
+
+/**
+  * @brief  Return type of reversal for input data bit order
+  * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
+}
+
+/**
+  * @brief  Initialize the Programmable initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to write the correct value
+  * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
+  * @rmtoll INIT         INIT          LL_CRC_SetInitialData
+  * @param  CRCx CRC Instance
+  * @param  InitCrc Value to be programmed in Programmable initial CRC value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
+{
+  WRITE_REG(CRCx->INIT, InitCrc);
+}
+
+/**
+  * @brief  Return current Initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to read the correct value
+  * @rmtoll INIT         INIT          LL_CRC_GetInitialData
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable initial CRC value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->INIT));
+}
+
+/**
+  * @brief  Initialize the Programmable polynomial value
+  *         (coefficients of the polynomial to be used for CRC calculation).
+  * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
+{
+  WRITE_REG(CRCx->POL, PolynomCoef);
+}
+
+/**
+  * @brief  Return current Programmable polynomial value
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable Polynomial value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->POL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Write given 32-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData32
+  * @param  CRCx CRC Instance
+  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+  * @brief  Write given 16-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData16
+  * @param  CRCx CRC Instance
+  * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
+{
+  *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
+}
+
+/**
+  * @brief  Write given 8-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData8
+  * @param  CRCx CRC Instance
+  * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
+{
+  *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
+}
+
+/**
+  * @brief  Return current CRC calculation result. 32 bits value is returned.
+  * @rmtoll DR           DR            LL_CRC_ReadData32
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+  */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+  * @brief  Return current CRC calculation result. 16 bits value is returned.
+  * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData16
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
+  */
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+{
+  return (uint16_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 8 bits value is returned.
+  * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData8
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+{
+  return (uint8_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 7 bits value is returned.
+  * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData7
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+{
+  return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
+}
+
+/**
+  * @brief  Return data stored in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
+  * @param  CRCx CRC Instance
+  * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+  */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+  * @brief  Store data in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
+  * @param  CRCx CRC Instance
+  * @param  InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c
new file mode 100755
index 0000000..a0a8108
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_crs.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   CRS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_crs.h"
+#include "stm32l4xx_ll_bus.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRS_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-Initializes CRS peripheral registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: CRS registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_CRS_DeInit(void)
+{
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
+
+  return  SUCCESS;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+  
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h
new file mode 100755
index 0000000..40267e6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h
@@ -0,0 +1,801 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_crs.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_CRS_H
+#define __STM32L4xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+  * @{
+  */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
+  * @{
+  */
+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
+  * @{
+  */
+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+  * @{
+  */
+#define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+  * @{
+  */
+#define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+  * @{
+  */
+#define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+  * @{
+  */
+#define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+  * @{
+  */
+/**
+  * @brief Reset value of the RELOAD field
+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+  */
+#define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)      
+
+/**
+  * @brief Reset value of Frequency error limit.
+  */
+#define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)      
+
+/**
+  * @brief Reset value of the HSI48 Calibration field
+  * @note The default value is 32, which corresponds to the middle of the trimming interval. 
+  *       The trimming step is around 67 kHz between two consecutive TRIM steps. 
+  *       A higher TRIM value corresponds to a higher output frequency
+  */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x20U)      
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+  * @{
+  */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+  * @{
+  */
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between 
+  *         the target frequency and the frequency of the synchronization source after
+  *         prescaling. It is then decreased by one in order to reach the expected
+  *         synchronization on the zero value. The formula is the following:
+  *              RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval Reload value (in Hz)
+  */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+  * @{
+  */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Frequency error counter
+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Disable Frequency error counter
+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Check if Frequency error counter is enabled or not
+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
+}
+
+/**
+  * @brief  Enable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Disable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Check if Automatic trimming is enabled or not
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
+}
+
+/**
+  * @brief  Set HSI48 oscillator smooth trimming
+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
+  * @param  Value a number between Min_Data = 0 and Max_Data = 63
+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT 
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI48 oscillator smooth trimming
+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
+  * @retval a number between Min_Data = 0 and Max_Data = 63
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Set counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT 
+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+  * @brief  Get counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Set frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
+  * @param  Value a number between Min_Data = 0 and Max_Data = 255
+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT 
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Get frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
+  * @retval A number between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Set division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+  * @brief  Get division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+  * @brief  Set SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+  * @brief  Get SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+  * @brief  Set input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+  * @brief  Get input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+  * @brief  Configure CRS for the synchronization
+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
+  * @param  Settings This parameter can be a combination of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CFGR, 
+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, 
+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate software SYNC event
+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Get the frequency error direction latched in the time of the last 
+  * SYNC event
+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if SYNC event OK signal occurred or not
+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
+}
+
+/**
+  * @brief  Check if SYNC warning signal occurred or not
+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error signal occurred or not
+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
+}
+
+/**
+  * @brief  Check if Expected SYNC signal occurred or not
+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
+}
+
+/**
+  * @brief  Check if SYNC error signal occurred or not
+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
+}
+
+/**
+  * @brief  Check if SYNC missed error signal occurred or not
+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
+}
+
+/**
+  * @brief  Check if Trimming overflow or underflow occurred or not
+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
+}
+
+/**
+  * @brief  Clear the SYNC event OK flag
+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+  * @brief  Clear the  SYNC warning flag
+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also 
+  * the ERR flag
+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+  * @brief  Clear Expected SYNC flag
+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Disable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Check if SYNC event OK interrupt is enabled or not
+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
+}
+
+/**
+  * @brief  Enable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Disable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Check if SYNC warning interrupt is enabled or not
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
+}
+
+/**
+  * @brief  Enable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Disable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
+}
+
+/**
+  * @brief  Enable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Disable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Check if Expected SYNC interrupt is enabled or not
+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+  
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_CRS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c
new file mode 100755
index 0000000..79f8ba4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c
@@ -0,0 +1,308 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_dac.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DAC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_dac.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DAC1)
+
+/** @addtogroup DAC_LL DAC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+  * @{
+  */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
+  (                                                                            \
+      ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
+   || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
+  )
+#else
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
+  (                                                                            \
+   ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                     \
+  )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
+  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
+  )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
+  (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
+   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
+   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+  )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)      \
+  (   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
+  )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
+  (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
+   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
+  )
+
+#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)                     \
+  (   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
+   || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
+  )
+
+#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)                                 \
+  (   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
+   || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of the selected DAC instance
+  *         to their default reset values.
+  * @param  DACx DAC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DAC registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(DACx));
+  
+  /* Force reset of DAC clock */
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
+  
+  /* Release reset of DAC clock */
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
+  
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of DAC instance.
+  * @note   The setting of these parameters by function @ref LL_DAC_Init()
+  *         is conditioned to DAC state:
+  *         DAC instance must be disabled.
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DAC registers are initialized
+  *          - ERROR: DAC registers are not initialized
+  */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(DACx));
+  assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
+  assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+  assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+  assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
+  assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
+  assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+  if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+  {
+    assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
+  }
+  
+  /* Note: Hardware constraint (refer to description of this function)        */
+  /*       DAC instance must be disabled.                                     */
+  if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
+  {
+    /* Configuration of DAC channel:                                          */
+    /*  - TriggerSource                                                       */
+    /*  - WaveAutoGeneration                                                  */
+    /*  - OutputBuffer                                                        */
+    /*  - OutputConnection                                                    */
+    /*  - OutputMode                                                          */
+    if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+    {
+      MODIFY_REG(DACx->CR,
+                 (  DAC_CR_TSEL1
+                  | DAC_CR_WAVE1
+                  | DAC_CR_MAMP1
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                ,
+                 (  DAC_InitStruct->TriggerSource
+                  | DAC_InitStruct->WaveAutoGeneration
+                  | DAC_InitStruct->WaveAutoGenerationConfig
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                );
+    }
+    else
+    {
+      MODIFY_REG(DACx->CR,
+                 (  DAC_CR_TSEL1
+                  | DAC_CR_WAVE1
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                ,
+                 (  DAC_InitStruct->TriggerSource
+                  | LL_DAC_WAVE_AUTO_GENERATION_NONE
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                );
+    }
+    
+    MODIFY_REG(DACx->MCR,
+               (  DAC_MCR_MODE1_1
+                | DAC_MCR_MODE1_0
+                | DAC_MCR_MODE1_2
+               ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+              ,
+               (  DAC_InitStruct->OutputBuffer
+                | DAC_InitStruct->OutputConnection
+                | DAC_InitStruct->OutputMode
+               ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+              );
+  }
+  else
+  {
+    /* Initialization error: DAC instance is not disabled.                    */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+  * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+  *                       whose fields will be set to default values.
+  * @retval None
+  */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+  /* Set DAC_InitStruct fields to default values */
+  DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
+  DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+  /* Note: Parameter discarded if wave auto generation is disabled,           */
+  /*       set anyway to its default value.                                   */
+  DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+  DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
+  DAC_InitStruct->OutputConnection         = LL_DAC_OUTPUT_CONNECT_GPIO;
+  DAC_InitStruct->OutputMode               = LL_DAC_OUTPUT_MODE_NORMAL;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h
new file mode 100755
index 0000000..74c4160
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h
@@ -0,0 +1,1983 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_dac.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DAC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_DAC_H
+#define __STM32L4xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DAC1)
+
+/** @defgroup DAC_LL DAC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+  * @{
+  */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
+/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */
+/* - channel bits position into register SWTRIG                               */
+/* - channel register offset of data holding register DHRx                    */
+/* - channel register offset of data output register DORx                     */
+/* - channel register offset of sample-and-hold sample time register SHSRx    */
+
+#define DAC_CR_CH1_BITOFFSET           0U    /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET           16U   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+#else
+#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_DHR12R1_REGOFFSET      0x00000000U             /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET      0x00100000U             /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET       0x02000000U             /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DHR12R2_REGOFFSET      0x00030000U             /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET      0x00400000U             /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET       0x05000000U             /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000U
+#define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET         0x00000000U             /* Register DORx channel 1 taken as reference */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DOR2_REGOFFSET         0x10000000U             /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+#else
+#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_SHSR1_REGOFFSET        0x00000000U             /* Register SHSRx channel 1 taken as reference */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_SHSR2_REGOFFSET        0x00001000U             /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */
+#define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
+#else
+#define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* DAC registers bits positions */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                16U  /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                20U  /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                  8U  /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS                        4095U  /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: isolate bits with the
+  *         selected mask and shift them to the register LSB
+  *         (shift mask on register position bit 0).
+  * @param  __BITS__ Bits in register 32 bits
+  * @param  __MASK__ Mask in register 32 bits
+  * @retval Bits in register 32 bits
+*/
+#define __DAC_MASK_SHIFT(__BITS__, __MASK__)                                   \
+  (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+*/
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of DAC instance.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+                                             This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+  uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+  uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
+                                             If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+                                             If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+                                             @note If waveform automatic generation mode is disabled, this parameter is discarded.
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+
+  uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+
+  uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
+
+  uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
+
+} LL_DAC_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+  * @{
+  */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+  * @brief    Flags defines which can be used with LL_DAC_ReadReg function
+  * @{
+  */
+/* DAC channel 1 flags */
+#define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
+#define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
+#define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/* DAC channel 2 flags */
+#define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
+#define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
+#define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+  * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
+  * @{
+  */
+#define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+  * @{
+  */
+#define LL_DAC_CHANNEL_1                   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_CHANNEL_2                   (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
+  * @{
+  */
+#define LL_DAC_MODE_NORMAL_OPERATION       0x00000000U             /*!< DAC channel in mode normal operation */
+#define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+  * @{
+  */
+#define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+  * @{
+  */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000U             /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+  * @{
+  */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000U                                                         /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+  * @{
+  */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000U                                                         /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
+  * @{
+  */
+#define LL_DAC_OUTPUT_MODE_NORMAL          0x00000000U             /*!< The selected DAC channel output is on mode normal. */
+#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+  * @{
+  */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000U             /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
+  * @{
+  */
+#define LL_DAC_OUTPUT_CONNECT_GPIO         0x00000000U             /*!< The selected DAC channel output is connected to external pin */
+#define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
+  * @{
+  */
+#define LL_DAC_TRIGGER_SOFTWARE            (LL_DAC_TRIG_SOFTWARE)
+#define LL_DAC_TRIGGER_TIM2_TRGO           (LL_DAC_TRIG_EXT_TIM2_TRGO)
+#define LL_DAC_TRIGGER_TIM4_TRGO           (LL_DAC_TRIG_EXT_TIM4_TRGO)
+#define LL_DAC_TRIGGER_TIM5_TRGO           (LL_DAC_TRIG_EXT_TIM5_TRGO)
+#define LL_DAC_TRIGGER_TIM6_TRGO           (LL_DAC_TRIG_EXT_TIM6_TRGO)
+#define LL_DAC_TRIGGER_TIM7_TRGO           (LL_DAC_TRIG_EXT_TIM7_TRGO)
+#define LL_DAC_TRIGGER_TIM8_TRGO           (LL_DAC_TRIG_EXT_TIM8_TRGO)
+#define LL_DAC_TRIGGER_EXT_IT9             (LL_DAC_TRIG_EXT_EXTI_LINE9)
+
+#define LL_DAC_WAVEGENERATION_NONE         (LL_DAC_WAVE_AUTO_GENERATION_NONE)
+#define LL_DAC_WAVEGENERATION_NOISE        (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
+#define LL_DAC_WAVEGENERATION_TRIANGLE     (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
+
+#define LL_DAC_CONNECT_GPIO                (LL_DAC_OUTPUT_CONNECT_GPIO)
+#define LL_DAC_CONNECT_INTERNAL            (LL_DAC_OUTPUT_CONNECT_INTERNAL)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
+  * @{
+  */
+#define LL_DAC_RESOLUTION_12B              0x00000000U             /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B               0x00000002U             /*!< DAC channel resolution 8 bits */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
+  * @{
+  */
+/* List of DAC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_MASK  /*!< DAC channel data holding register 8 bits right aligned */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
+  * @note   Only DAC IP HW delays are defined in DAC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup       */
+/* (transition from disable to enable).                                       */
+/* Note: DAC channel startup time depends on board application environment:   */
+/*       impedance connected to DAC channel output.                           */
+/*       The delay below is specified under conditions:                       */
+/*        - voltage maximum transition (lowest to highest value)              */
+/*        - until voltage reaches final value +-1LSB                          */
+/*        - DAC channel output buffer enabled                                 */
+/*        - load impedance of 5kOhm (min), 50pF (max)                         */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tWAKEUP").                                                      */
+/* Unit: us                                                                   */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             8U  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+
+/* Delay for DAC channel voltage settling time.                               */
+/* Note: DAC channel startup time depends on board application environment:   */
+/*       impedance connected to DAC channel output.                           */
+/*       The delay below is specified under conditions:                       */
+/*        - voltage maximum transition (lowest to highest value)              */
+/*        - until voltage reaches final value +-1LSB                          */
+/*        - DAC channel output buffer enabled                                 */
+/*        - load impedance of 5kOhm min, 50pF max                             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSETTLING").                                                    */
+/* Unit: us                                                                   */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                     2U  /*!< Delay for DAC channel voltage settling time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in DAC register
+  * @param  __INSTANCE__ DAC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DAC register
+  * @param  __INSTANCE__ DAC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get DAC channel number in decimal format
+  *         from literals LL_DAC_CHANNEL_x.
+  *         Example:
+  *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+  *            will return decimal number "1".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval 1...2 (value "2" depending on DAC channel 2 availability)
+  */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
+  ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+  * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+  *         from number in decimal format.
+  *         Example:
+  *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+  *           will return a data equivalent to "LL_DAC_CHANNEL_1".
+  * @note  If the input parameter does not correspond to a DAC channel,
+  *        this macro returns value '0'.
+  * @param  __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
+  (((__DECIMAL_NB__) == 1U)                                                     \
+    ? (                                                                        \
+       LL_DAC_CHANNEL_1                                                        \
+      )                                                                        \
+      :                                                                        \
+      (((__DECIMAL_NB__) == 2U)                                                 \
+        ? (                                                                    \
+           LL_DAC_CHANNEL_2                                                    \
+          )                                                                    \
+          :                                                                    \
+          (                                                                    \
+           0                                                                   \
+          )                                                                    \
+      )                                                                        \
+  )
+#else
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
+  (((__DECIMAL_NB__) == 1U)                                                     \
+    ? (                                                                        \
+       LL_DAC_CHANNEL_1                                                        \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+       0                                                                       \
+      )                                                                        \
+  )
+#endif  /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Helper macro to define the DAC conversion data full-scale digital
+  *         value corresponding to the selected DAC resolution.
+  * @note   DAC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_RESOLUTION_12B
+  *         @arg @ref LL_DAC_RESOLUTION_8B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
+  ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+
+/**
+  * @brief  Helper macro to calculate the DAC conversion data (unit: digital
+  *         value) corresponding to a voltage (unit: mVolt).
+  * @note   This helper macro is intended to provide input data in voltage
+  *         rather than digital value,
+  *         to be used with LL DAC functions such as
+  *         @ref LL_DAC_ConvertData12RightAligned().
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+  *                         (unit: mVolt).
+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_RESOLUTION_12B
+  *         @arg @ref LL_DAC_RESOLUTION_8B
+  * @retval DAC conversion data (unit: digital value)
+  */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
+                                      __DAC_VOLTAGE__,\
+                                      __DAC_RESOLUTION__)                      \
+  ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
+   / (__VREFANALOG_VOLTAGE__)                                                  \
+  )
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+  * @{
+  */
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+  * @{
+  */
+
+/**
+  * @brief  Set the operating mode for the selected DAC channel:
+  *         calibration or normal operating mode.
+  * @rmtoll CR       CEN1           LL_DAC_SetMode\n
+  *         CR       CEN2           LL_DAC_SetMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  ChannelMode This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
+  *         @arg @ref LL_DAC_MODE_CALIBRATION
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the operating mode for the selected DAC channel:
+  *         calibration or normal operating mode.
+  * @rmtoll CR       CEN1           LL_DAC_GetMode\n
+  *         CR       CEN2           LL_DAC_GetMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
+  *         @arg @ref LL_DAC_MODE_CALIBRATION
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the offset trimming value for the selected DAC channel.
+  *         Trimming has an impact when output buffer is enabled
+  *         and is intended to replace factory calibration default values.
+  * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
+  *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
+{
+  MODIFY_REG(DACx->CCR,
+             DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the offset trimming value for the selected DAC channel.
+  *         Trimming has an impact when output buffer is enabled
+  *         and is intended to replace factory calibration default values.
+  * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
+  *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the conversion trigger source for the selected DAC channel.
+  * @note   For conversion trigger source to be effective, DAC trigger
+  *         must be enabled using function @ref LL_DAC_EnableTrigger().
+  * @note   To set conversion trigger source, DAC channel must be disabled.
+  *         Otherwise, the setting is discarded.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
+  *         CR       TSEL2          LL_DAC_SetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the conversion trigger source for the selected DAC channel.
+  * @note   For conversion trigger source to be effective, DAC trigger
+  *         must be enabled using function @ref LL_DAC_EnableTrigger().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
+  *         CR       TSEL2          LL_DAC_GetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_DAC_TRIGGER_EXT_IT9
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the waveform automatic generation mode
+  *         for the selected DAC channel.
+  * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
+  *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  WaveAutoGeneration This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the waveform automatic generation mode
+  *         for the selected DAC channel.
+  * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
+  *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the noise waveform generation for the selected DAC channel:
+  *         Noise mode and parameters LFSR (linear feedback shift register).
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
+  *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  NoiseLFSRMask This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Set the noise waveform generation for the selected DAC channel:
+  *         Noise mode and parameters LFSR (linear feedback shift register).
+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
+  *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the triangle waveform generation for the selected DAC channel:
+  *         triangle mode and amplitude.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
+  *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriangleAmplitude This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Set the triangle waveform generation for the selected DAC channel:
+  *         triangle mode and amplitude.
+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
+  *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the output for the selected DAC channel.
+  * @note   This function set several features:
+  *         - mode normal or sample-and-hold
+  *         - buffer
+  *         - connection to GPIO or internal path.
+  *         These features can also be set individually using
+  *         dedicated functions:
+  *         - @ref LL_DAC_SetOutputBuffer()
+  *         - @ref LL_DAC_SetOutputMode()
+  *         - @ref LL_DAC_SetOutputConnection()
+  * @note   On this STM32 serie, output connection depends on output mode
+  *         (normal or sample and hold) and output buffer state.
+  *         - if output connection is set to internal path and output buffer
+  *           is enabled (whatever output mode):
+  *           output connection is also connected to GPIO pin
+  *           (both connections to GPIO pin and internal path).
+  *         - if output connection is set to GPIO pin, output buffer
+  *           is disabled, output mode set to sample and hold:
+  *           output connection is also connected to internal path
+  *           (both connections to GPIO pin and internal path).
+  * @note   Mode sample-and-hold requires an external capacitor
+  *         to be connected between DAC channel output and ground.
+  *         Capacitor value depends on load on DAC channel output and 
+  *         sample-and-hold timings configured.
+  *         As indication, capacitor typical value is 100nF
+  *         (refer to device datasheet, parameter "CSH").
+  * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
+  *         CR       MODE2          LL_DAC_ConfigOutput
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputMode This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+  * @param  OutputBuffer This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  * @param  OutputConnection This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
+{
+  MODIFY_REG(DACx->MCR,
+             (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Set the output mode normal or sample-and-hold
+  *         for the selected DAC channel.
+  * @note   Mode sample-and-hold requires an external capacitor
+  *         to be connected between DAC channel output and ground.
+  *         Capacitor value depends on load on DAC channel output and 
+  *         sample-and-hold timings configured.
+  *         As indication, capacitor typical value is 100nF
+  *         (refer to device datasheet, parameter "CSH").
+  * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
+  *         CR       MODE2          LL_DAC_SetOutputMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputMode This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
+{
+  MODIFY_REG(DACx->MCR,
+             DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
+  * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
+  *         CR       MODE2          LL_DAC_GetOutputMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the output buffer for the selected DAC channel.
+  * @note   On this STM32 serie, when buffer is enabled, its offset can be
+  *         trimmed: factory calibration default values can be
+  *         replaced by user trimming values, using function
+  *         @ref LL_DAC_SetTrimmingValue().
+  * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
+  *         CR       MODE2          LL_DAC_SetOutputBuffer
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputBuffer This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+  MODIFY_REG(DACx->MCR,
+             DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the output buffer state for the selected DAC channel.
+  * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
+  *         CR       MODE2          LL_DAC_GetOutputBuffer
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the output connection for the selected DAC channel.
+  * @note   On this STM32 serie, output connection depends on output mode (normal or
+  *         sample and hold) and output buffer state.
+  *         - if output connection is set to internal path and output buffer
+  *           is enabled (whatever output mode):
+  *           output connection is also connected to GPIO pin
+  *           (both connections to GPIO pin and internal path).
+  *         - if output connection is set to GPIO pin, output buffer
+  *           is disabled, output mode set to sample and hold:
+  *           output connection is also connected to internal path
+  *           (both connections to GPIO pin and internal path).
+  * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
+  *         CR       MODE2          LL_DAC_SetOutputConnection
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputConnection This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
+{
+  MODIFY_REG(DACx->MCR,
+             DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the output connection for the selected DAC channel.
+  * @note   On this STM32 serie, output connection depends on output mode (normal or
+  *         sample and hold) and output buffer state.
+  *         - if output connection is set to internal path and output buffer
+  *           is enabled (whatever output mode):
+  *           output connection is also connected to GPIO pin
+  *           (both connections to GPIO pin and internal path).
+  *         - if output connection is set to GPIO pin, output buffer
+  *           is disabled, output mode set to sample and hold:
+  *           output connection is also connected to internal path
+  *           (both connections to GPIO pin and internal path).
+  * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
+  *         CR       MODE2          LL_DAC_GetOutputConnection
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the sample-and-hold timing for the selected DAC channel:
+  *         sample time
+  * @note   Sample time must be set when DAC channel is disabled
+  *         or during DAC operation when DAC channel flag BWSTx is reset,
+  *         otherwise the setting is ignored.
+  *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
+  * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
+  *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             DAC_SHSR1_TSAMPLE1,
+             SampleTime);
+}
+
+/**
+  * @brief  Get the sample-and-hold timing for the selected DAC channel:
+  *         sample time
+  * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
+  *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
+  
+  return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
+}
+
+/**
+  * @brief  Set the sample-and-hold timing for the selected DAC channel:
+  *         hold time
+  * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
+  *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
+{
+  MODIFY_REG(DACx->SHHR,
+             DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the sample-and-hold timing for the selected DAC channel:
+  *         hold time
+  * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
+  *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the sample-and-hold timing for the selected DAC channel:
+  *         refresh time
+  * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
+  *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
+{
+  MODIFY_REG(DACx->SHRR,
+             DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the sample-and-hold timing for the selected DAC channel:
+  *         refresh time
+  * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
+  *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name
+  * @{
+  */
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+__STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode)
+{
+  LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode);
+}
+__STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DAC DMA transfer request of the selected channel.
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_DAC_DMA_GetRegAddr().
+  * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
+  *         CR       DMAEN2         LL_DAC_EnableDMAReq
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC DMA transfer request of the selected channel.
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_DAC_DMA_GetRegAddr().
+  * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
+  *         CR       DMAEN2         LL_DAC_DisableDMAReq
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC DMA transfer request state of the selected channel.
+  *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+  * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
+  *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (READ_BIT(DACx->CR,
+                   DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+          == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+  * @brief  Function to help to configure DMA transfer to DAC: retrieve the
+  *         DAC register address from DAC instance and a list of DAC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These DAC registers are data holding registers:
+  *         when DAC conversion is requested, DAC generates a DMA transfer
+  *         request to have data available in DAC data holding registers.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+  *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+  *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+  * @retval DAC register address
+  */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+  /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
+  /* DAC channel selected.                                                    */
+  return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+  * @{
+  */
+
+/**
+  * @brief  Enable DAC selected channel.
+  * @rmtoll CR       EN1            LL_DAC_Enable\n
+  *         CR       EN2            LL_DAC_Enable
+  * @note   After enable from off state, DAC channel requires a delay
+  *         for output voltage to reach accuracy +/- 1 LSB.
+  *         Refer to device datasheet, parameter "tWAKEUP".
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC selected channel.
+  * @rmtoll CR       EN1            LL_DAC_Disable\n
+  *         CR       EN2            LL_DAC_Disable
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC enable state of the selected channel.
+  *         (0: DAC channel is disabled, 1: DAC channel is enabled)
+  * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
+  *         CR       EN2            LL_DAC_IsEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (READ_BIT(DACx->CR,
+                   DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+          == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+  * @brief  Enable DAC trigger of the selected channel.
+  * @note   - If DAC trigger is disabled, DAC conversion is performed
+  *           automatically once the data holding register is updated,
+  *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+  *           @ref LL_DAC_ConvertData12RightAligned(), ...
+  *         - If DAC trigger is enabled, DAC conversion is performed
+  *           only when a hardware of software trigger event is occurring.
+  *           Select trigger source using
+  *           function @ref LL_DAC_SetTriggerSource().
+  * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
+  *         CR       TEN2           LL_DAC_EnableTrigger
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC trigger of the selected channel.
+  * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
+  *         CR       TEN2           LL_DAC_DisableTrigger
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC trigger state of the selected channel.
+  *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+  * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
+  *         CR       TEN2           LL_DAC_IsTriggerEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (READ_BIT(DACx->CR,
+                   DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+          == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+  * @brief  Trig DAC conversion by software for the selected DAC channel.
+  * @note   Preliminarily, DAC trigger must be set to software trigger
+  *         using function @ref LL_DAC_SetTriggerSource()
+  *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
+  *         and DAC trigger must be enabled using
+  *         function @ref LL_DAC_EnableTrigger().
+  * @note   For devices featuring DAC with 2 channels: this function
+  *         can perform a SW start of both DAC channels simultaneously.
+  *         Two channels can be selected as parameter.
+  *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+  * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
+  *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
+  * @param  DACx DAC instance
+  * @param  DAC_Channel  This parameter can a combination of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->SWTRIGR,
+          (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (LSB aligned on bit 0),
+  *         for the selected DAC channel.
+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
+  *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             DAC_DHR12R1_DACC1DHR,
+             Data);
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (MSB aligned on bit 15),
+  *         for the selected DAC channel.
+  * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
+  *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             DAC_DHR12L1_DACC1DHR,
+             Data);
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 8 bits left alignment (LSB aligned on bit 0),
+  *         for the selected DAC channel.
+  * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
+  *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             DAC_DHR8R1_DACC1DHR,
+             Data);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (LSB aligned on bit 0),
+  *         for both DAC channels.
+  * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
+  *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+  MODIFY_REG(DACx->DHR12RD,
+             (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+             ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (MSB aligned on bit 15),
+  *         for both DAC channels.
+  * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
+  *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+  /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
+  /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
+  /*       the 4 LSB must be taken into account for the shift value.          */
+  MODIFY_REG(DACx->DHR12LD,
+             (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+             ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 8 bits left alignment (LSB aligned on bit 0),
+  *         for both DAC channels.
+  * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
+  *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+  * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+  MODIFY_REG(DACx->DHR8RD,
+             (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+             ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @brief  Retrieve output data currently generated for the selected DAC channel.
+  * @note   Whatever alignment and resolution settings
+  *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+  *         @ref LL_DAC_ConvertData12RightAligned(), ...),
+  *         output data format is 12 bits right aligned (LSB aligned on bit 0).
+  * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
+  *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
+  
+  return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+/**
+  * @brief  Get DAC calibration offset flag for DAC channel 1
+  * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Get DAC calibration offset flag for DAC channel 2
+  * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2));
+}
+
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @brief  Get DAC busy writing sample time flag for DAC channel 1
+  * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Get DAC busy writing sample time flag for DAC channel 2
+  * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2));
+}
+
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @brief  Get DAC underrun flag for DAC channel 1
+  * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Get DAC underrun flag for DAC channel 2
+  * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Clear DAC underrun flag for DAC channel 1
+  * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Clear DAC underrun flag for DAC channel 2
+  * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_IT_Management IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Enable DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Disable DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Disable DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Get DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Get DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
+void        LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c
new file mode 100755
index 0000000..88ab69f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c
@@ -0,0 +1,400 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_dma.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DMA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_dma.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= (uint32_t)0x0000FFFFU)
+
+#define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      (((__VALUE__) == LL_DMA_REQUEST_0)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_1)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_2)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_3)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_4)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_5)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_6)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_7))
+
+#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+                                                         (((INSTANCE) == DMA2) && \
+                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+                                                         (((INSTANCE) == DMA2) && \
+                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                          ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#endif
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#endif
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the DMA registers to their default reset values.
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_ALL
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are de-initialized
+  *          - ERROR: DMA registers are not de-initialized
+  */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
+  ErrorStatus status = SUCCESS;
+
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
+
+  if (Channel == LL_DMA_CHANNEL_ALL)
+  {
+    if (DMAx == DMA1)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+    }
+#if defined(DMA2)
+    else if (DMAx == DMA2)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+    }
+#endif
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+    /* Disable the selected DMAx_Channely */
+    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+    /* Reset DMAx_Channely control register */
+    LL_DMA_WriteReg(tmp, CCR, 0U);
+
+    /* Reset DMAx_Channely remaining bytes register */
+    LL_DMA_WriteReg(tmp, CNDTR, 0U);
+
+    /* Reset DMAx_Channely peripheral address register */
+    LL_DMA_WriteReg(tmp, CPAR, 0U);
+
+    /* Reset DMAx_Channely memory address register */
+    LL_DMA_WriteReg(tmp, CMAR, 0U);
+
+    /* Reset Request register field for DMAx Channel */
+    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
+
+    if (Channel == LL_DMA_CHANNEL_1)
+    {
+      /* Reset interrupt pending bits for DMAx Channel1 */
+      LL_DMA_ClearFlag_GI1(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_2)
+    {
+      /* Reset interrupt pending bits for DMAx Channel2 */
+      LL_DMA_ClearFlag_GI2(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_3)
+    {
+      /* Reset interrupt pending bits for DMAx Channel3 */
+      LL_DMA_ClearFlag_GI3(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_4)
+    {
+      /* Reset interrupt pending bits for DMAx Channel4 */
+      LL_DMA_ClearFlag_GI4(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_5)
+    {
+      /* Reset interrupt pending bits for DMAx Channel5 */
+      LL_DMA_ClearFlag_GI5(DMAx);
+    }
+
+    else if (Channel == LL_DMA_CHANNEL_6)
+    {
+      /* Reset interrupt pending bits for DMAx Channel6 */
+      LL_DMA_ClearFlag_GI6(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_7)
+    {
+      /* Reset interrupt pending bits for DMAx Channel7 */
+      LL_DMA_ClearFlag_GI7(DMAx);
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+  * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+  *         @arg @ref __LL_DMA_GET_INSTANCE
+  *         @arg @ref __LL_DMA_GET_CHANNEL
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are initialized
+  *          - ERROR: Not applicable
+  */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+  /* Check the DMA parameters from DMA_InitStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+  assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+  /*---------------------------- DMAx CCR Configuration ------------------------
+   * Configure DMAx_Channely: data transfer direction, data transfer mode,
+   *                          peripheral and memory increment mode,
+   *                          data size alignment and  priority level with parameters :
+   * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+   * - Mode:           DMA_CCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
+   * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
+   * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+   * - Priority:               DMA_CCR_PL[1:0] bits
+   */
+  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
+                        DMA_InitStruct->Mode                   | \
+                        DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
+                        DMA_InitStruct->MemoryOrM2MDstIncMode  | \
+                        DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+                        DMA_InitStruct->MemoryOrM2MDstDataSize | \
+                        DMA_InitStruct->Priority);
+
+  /*-------------------------- DMAx CMAR Configuration -------------------------
+   * Configure the memory or destination base address with parameter :
+   * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+   */
+  LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+  /*-------------------------- DMAx CPAR Configuration -------------------------
+   * Configure the peripheral or source base address with parameter :
+   * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+   */
+  LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+  /*--------------------------- DMAx CNDTR Configuration -----------------------
+   * Configure the peripheral base address with parameter :
+   * - NbData: DMA_CNDTR_NDT[15:0] bits
+   */
+  LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+  /*--------------------------- DMAx CSELR Configuration -----------------------
+   * Configure the peripheral base address with parameter :
+   * - PeriphRequest: DMA_CSELR[31:0] bits
+   */
+  LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval None
+  */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Set DMA_InitStruct fields to default values */
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = (uint32_t)0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = (uint32_t)0x00000000U;
+  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
+  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
+  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
+  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+  DMA_InitStruct->NbData                 = (uint32_t)0x00000000U;
+  DMA_InitStruct->PeriphRequest          = LL_DMA_REQUEST_0;
+  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h
new file mode 100755
index 0000000..65ac16c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h
@@ -0,0 +1,2114 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_dma.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_DMA_H
+#define __STM32L4xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  * @{
+  */
+/* Define used to get CSELR register offset */
+#define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define DMA_POSITION_CSELR_CXS            POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note: The circular buffer mode cannot be used if the memory to memory
+                                               data transfer direction is configured on the selected Channel
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
+                                        This parameter can be a value of @ref DMA_LL_EC_REQUEST
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA_WriteReg function
+  * @{
+  */
+#define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
+#define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
+#define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
+#define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
+#define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
+#define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
+#define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
+#define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
+#define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
+#define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
+#define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
+#define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
+#define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
+#define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA_ReadReg function
+  * @{
+  */
+#define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
+#define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
+#define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
+#define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
+#define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
+#define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
+#define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
+#define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
+#define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
+#define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
+#define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
+#define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
+#define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
+#define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
+#define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
+#define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
+#define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
+#define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
+#define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
+#define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
+#define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
+  * @{
+  */
+#define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
+#define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+  * @{
+  */
+#define LL_DMA_CHANNEL_1                  ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2                  ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3                  ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4                  ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5                  ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6                  ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_7                  ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL                ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                ((uint32_t)0x00000000U) /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+  * @{
+  */
+#define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+  * @{
+  */
+#define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
+#define LL_DMA_MEMORY_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               ((uint32_t)0x00000000U) /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
+  * @{
+  */
+#define LL_DMA_REQUEST_0                  ((uint32_t)0x00000000U) /*!< DMA peripheral request 0  */
+#define LL_DMA_REQUEST_1                  ((uint32_t)0x00000001U) /*!< DMA peripheral request 1  */
+#define LL_DMA_REQUEST_2                  ((uint32_t)0x00000002U) /*!< DMA peripheral request 2  */
+#define LL_DMA_REQUEST_3                  ((uint32_t)0x00000003U) /*!< DMA peripheral request 3  */
+#define LL_DMA_REQUEST_4                  ((uint32_t)0x00000004U) /*!< DMA peripheral request 4  */
+#define LL_DMA_REQUEST_5                  ((uint32_t)0x00000005U) /*!< DMA peripheral request 5  */
+#define LL_DMA_REQUEST_6                  ((uint32_t)0x00000006U) /*!< DMA peripheral request 6  */
+#define LL_DMA_REQUEST_7                  ((uint32_t)0x00000007U) /*!< DMA peripheral request 7  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Channely into DMAx
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
+  * @retval DMAx
+  */
+#if defined(DMA2)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
+(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
+#endif
+
+/**
+  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
+  * @retval LL_DMA_CHANNEL_y
+  */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __CHANNEL__ LL_DMA_CHANNEL_y
+  * @retval DMAx_Channely
+  */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
+ DMA2_Channel7)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Enable DMA channel.
+  * @rmtoll CCR          EN            LL_DMA_EnableChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+  * @brief  Disable DMA channel.
+  * @rmtoll CCR          EN            LL_DMA_DisableChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+  * @brief  Check if DMA channel is enabled or disabled.
+  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_EN) == (DMA_CCR_EN));
+}
+
+/**
+  * @brief  Configure all parameters link to DMA transfer.
+  * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
+  *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
+  *         CCR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CCR          PINC          LL_DMA_ConfigTransfer\n
+  *         CCR          MINC          LL_DMA_ConfigTransfer\n
+  *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CCR          PL            LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+             DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+             Configuration);
+}
+
+/**
+  * @brief  Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
+  *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+             DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+  * @brief  Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
+  *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+  * @brief  Set DMA mode circular or normal.
+  * @note The circular buffer mode cannot be used if the memory-to-memory
+  * data transfer is configured on the selected Channel.
+  * @rmtoll CCR          CIRC          LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+             Mode);
+}
+
+/**
+  * @brief  Get DMA mode circular or normal.
+  * @rmtoll CCR          CIRC          LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_CIRC));
+}
+
+/**
+  * @brief  Set Peripheral increment mode.
+  * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+             PeriphOrM2MSrcIncMode);
+}
+
+/**
+  * @brief  Get Peripheral increment mode.
+  * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_PINC));
+}
+
+/**
+  * @brief  Set Memory increment mode.
+  * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+             MemoryOrM2MDstIncMode);
+}
+
+/**
+  * @brief  Get Memory increment mode.
+  * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_MINC));
+}
+
+/**
+  * @brief  Set Peripheral size.
+  * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+             PeriphOrM2MSrcDataSize);
+}
+
+/**
+  * @brief  Get Peripheral size.
+  * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_PSIZE));
+}
+
+/**
+  * @brief  Set Memory size.
+  * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+             MemoryOrM2MDstDataSize);
+}
+
+/**
+  * @brief  Get Memory size.
+  * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_MSIZE));
+}
+
+/**
+  * @brief  Set Channel priority level.
+  * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+             Priority);
+}
+
+/**
+  * @brief  Get Channel priority level.
+  * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_PL));
+}
+
+/**
+  * @brief  Set Number of data to transfer.
+  * @note   This action has no effect if
+  *         channel is enabled.
+  * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+             DMA_CNDTR_NDT, NbData);
+}
+
+/**
+  * @brief  Get Number of data to transfer.
+  * @note   Once the channel is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+                   DMA_CNDTR_NDT));
+}
+
+/**
+  * @brief  Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
+  * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
+  *         CMAR         MA            LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+                                            uint32_t DstAddress, uint32_t Direction)
+{
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get Memory address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+/**
+  * @brief  Get Peripheral address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+/**
+  * @brief  Set DMA request for DMA instance on Channel x.
+  * @note   Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
+  * @rmtoll CSELR        C1S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C2S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C3S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C4S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C5S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C6S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C7S           LL_DMA_SetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphRequest This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_REQUEST_0
+  *         @arg @ref LL_DMA_REQUEST_1
+  *         @arg @ref LL_DMA_REQUEST_2
+  *         @arg @ref LL_DMA_REQUEST_3
+  *         @arg @ref LL_DMA_REQUEST_4
+  *         @arg @ref LL_DMA_REQUEST_5
+  *         @arg @ref LL_DMA_REQUEST_6
+  *         @arg @ref LL_DMA_REQUEST_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
+{
+  MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+             DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
+}
+
+/**
+  * @brief  Get DMA request for DMA instance on Channel x.
+  * @rmtoll CSELR        C1S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C2S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C3S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C4S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C5S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C6S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C7S           LL_DMA_GetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_REQUEST_0
+  *         @arg @ref LL_DMA_REQUEST_1
+  *         @arg @ref LL_DMA_REQUEST_2
+  *         @arg @ref LL_DMA_REQUEST_3
+  *         @arg @ref LL_DMA_REQUEST_4
+  *         @arg @ref LL_DMA_REQUEST_5
+  *         @arg @ref LL_DMA_REQUEST_6
+  *         @arg @ref LL_DMA_REQUEST_7
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+                   DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Channel 1 global interrupt flag.
+  * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
+}
+
+/**
+  * @brief  Get Channel 2 global interrupt flag.
+  * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
+}
+
+/**
+  * @brief  Get Channel 3 global interrupt flag.
+  * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
+}
+
+/**
+  * @brief  Get Channel 4 global interrupt flag.
+  * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
+}
+
+/**
+  * @brief  Get Channel 5 global interrupt flag.
+  * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
+}
+
+/**
+  * @brief  Get Channel 6 global interrupt flag.
+  * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
+}
+
+/**
+  * @brief  Get Channel 7 global interrupt flag.
+  * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
+}
+
+/**
+  * @brief  Get Channel 1 transfer complete flag.
+  * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
+}
+
+/**
+  * @brief  Get Channel 2 transfer complete flag.
+  * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
+}
+
+/**
+  * @brief  Get Channel 3 transfer complete flag.
+  * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
+}
+
+/**
+  * @brief  Get Channel 4 transfer complete flag.
+  * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
+}
+
+/**
+  * @brief  Get Channel 5 transfer complete flag.
+  * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
+}
+
+/**
+  * @brief  Get Channel 6 transfer complete flag.
+  * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
+}
+
+/**
+  * @brief  Get Channel 7 transfer complete flag.
+  * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
+}
+
+/**
+  * @brief  Get Channel 1 half transfer flag.
+  * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
+}
+
+/**
+  * @brief  Get Channel 2 half transfer flag.
+  * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
+}
+
+/**
+  * @brief  Get Channel 3 half transfer flag.
+  * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
+}
+
+/**
+  * @brief  Get Channel 4 half transfer flag.
+  * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
+}
+
+/**
+  * @brief  Get Channel 5 half transfer flag.
+  * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
+}
+
+/**
+  * @brief  Get Channel 6 half transfer flag.
+  * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
+}
+
+/**
+  * @brief  Get Channel 7 half transfer flag.
+  * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
+}
+
+/**
+  * @brief  Get Channel 1 transfer error flag.
+  * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
+}
+
+/**
+  * @brief  Get Channel 2 transfer error flag.
+  * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
+}
+
+/**
+  * @brief  Get Channel 3 transfer error flag.
+  * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
+}
+
+/**
+  * @brief  Get Channel 4 transfer error flag.
+  * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
+}
+
+/**
+  * @brief  Get Channel 5 transfer error flag.
+  * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
+}
+
+/**
+  * @brief  Get Channel 6 transfer error flag.
+  * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
+}
+
+/**
+  * @brief  Get Channel 7 transfer error flag.
+  * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
+}
+
+/**
+  * @brief  Clear Channel 1 global interrupt flag.
+  * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+  * @brief  Clear Channel 2 global interrupt flag.
+  * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+  * @brief  Clear Channel 3 global interrupt flag.
+  * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+  * @brief  Clear Channel 4 global interrupt flag.
+  * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+  * @brief  Clear Channel 5 global interrupt flag.
+  * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+  * @brief  Clear Channel 6 global interrupt flag.
+  * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+/**
+  * @brief  Clear Channel 7 global interrupt flag.
+  * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+
+/**
+  * @brief  Clear Channel 1  transfer complete flag.
+  * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+  * @brief  Clear Channel 2  transfer complete flag.
+  * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+  * @brief  Clear Channel 3  transfer complete flag.
+  * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+  * @brief  Clear Channel 4  transfer complete flag.
+  * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+  * @brief  Clear Channel 5  transfer complete flag.
+  * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+  * @brief  Clear Channel 6  transfer complete flag.
+  * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+/**
+  * @brief  Clear Channel 7  transfer complete flag.
+  * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+
+/**
+  * @brief  Clear Channel 1  half transfer flag.
+  * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+  * @brief  Clear Channel 2  half transfer flag.
+  * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+  * @brief  Clear Channel 3  half transfer flag.
+  * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+  * @brief  Clear Channel 4  half transfer flag.
+  * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+  * @brief  Clear Channel 5  half transfer flag.
+  * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+  * @brief  Clear Channel 6  half transfer flag.
+  * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+/**
+  * @brief  Clear Channel 7  half transfer flag.
+  * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+
+/**
+  * @brief  Clear Channel 1 transfer error flag.
+  * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+  * @brief  Clear Channel 2 transfer error flag.
+  * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+  * @brief  Clear Channel 3 transfer error flag.
+  * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+  * @brief  Clear Channel 4 transfer error flag.
+  * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+  * @brief  Clear Channel 5 transfer error flag.
+  * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+  * @brief  Clear Channel 6 transfer error flag.
+  * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+/**
+  * @brief  Clear Channel 7 transfer error flag.
+  * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+/**
+  * @brief  Enable Transfer complete interrupt.
+  * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief  Enable Half transfer interrupt.
+  * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief  Enable Transfer error interrupt.
+  * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+  * @brief  Disable Transfer complete interrupt.
+  * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief  Disable Half transfer interrupt.
+  * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief  Disable Transfer error interrupt.
+  * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+  * @brief  Check if Transfer complete Interrupt is enabled.
+  * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_TCIE) == (DMA_CCR_TCIE));
+}
+
+/**
+  * @brief  Check if Half transfer Interrupt is enabled.
+  * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_HTIE) == (DMA_CCR_HTIE));
+}
+
+/**
+  * @brief  Check if Transfer error Interrupt is enabled.
+  * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_TEIE) == (DMA_CCR_TEIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c
new file mode 100755
index 0000000..2bdd4e5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c
@@ -0,0 +1,630 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_dma2d.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   DMA2D LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_dma2d.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA2D)
+
+/** @addtogroup DMA2D_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants
+  * @{
+  */
+#define LL_DMA2D_COLOR            0xFFU                                      /*!< Maximum output color setting                   */
+#define LL_DMA2D_NUMBEROFLINES    DMA2D_NLR_NL                               /*!< Maximum number of lines                        */
+#define LL_DMA2D_NUMBEROFPIXELS   (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos)         /*!< Maximum number of pixels per lines             */
+#define LL_DMA2D_OFFSET_MAX       0x3FFFU                                    /*!< Maximum output line offset expressed in pixels */
+#define LL_DMA2D_CLUTSIZE_MAX     0xFFU                                      /*!< Maximum CLUT size                              */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA2D_MODE(MODE)          (((MODE) == LL_DMA2D_MODE_M2M)       || \
+                                         ((MODE) == LL_DMA2D_MODE_M2M_PFC)   || \
+                                         ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \
+                                         ((MODE) == LL_DMA2D_MODE_R2M))
+
+#define IS_LL_DMA2D_OCMODE(MODE_ARGB)   (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444))
+
+#define IS_LL_DMA2D_GREEN(GREEN)        ((GREEN) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_RED(RED)            ((RED)   <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_BLUE(BLUE)          ((BLUE)  <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_ALPHA(ALPHA)        ((ALPHA) <= LL_DMA2D_COLOR)
+
+#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
+#define IS_LL_DMA2D_OFFSET_MODE(MODE)   (((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \
+                                         ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES))
+
+#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
+#define IS_LL_DMA2D_OFFSET(OFFSET)      ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
+
+#define IS_LL_DMA2D_LINE(LINES)         ((LINES)  <= LL_DMA2D_NUMBEROFLINES)
+#define IS_LL_DMA2D_PIXEL(PIXELS)       ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
+
+#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
+#define IS_LL_DMA2D_SWAP_MODE(MODE)     (((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \
+                                         ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO))
+
+#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
+#define IS_LL_DMA2D_ALPHAINV(ALPHA)     (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \
+                                         ((ALPHA) == LL_DMA2D_ALPHA_INVERTED))
+
+#define IS_LL_DMA2D_RBSWAP(RBSWAP)      (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \
+                                         ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP))
+
+#define IS_LL_DMA2D_LCMODE(MODE_ARGB)   (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8)       || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44)     || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88)     || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4)       || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8)       || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4))
+
+#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \
+                                          ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888))
+
+#define IS_LL_DMA2D_CLUTSIZE(SIZE)      ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
+
+#define IS_LL_DMA2D_ALPHAMODE(MODE)     (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
+                                         ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE)  || \
+                                         ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+  * @{
+  */
+
+/**
+  * @brief  De-initialize DMA2D registers (registers restored to their default values).
+  * @param  DMA2Dx DMA2D Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA2D registers are de-initialized
+  *          - ERROR: DMA2D registers are not de-initialized
+  */
+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+
+  if (DMA2Dx == DMA2D)
+  {
+    /* Force reset of DMA2D clock */
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2D);
+
+    /* Release reset of DMA2D clock */
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2D);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
+  * @note   DMA2D transfers must be disabled to set initialization bits in configuration registers,
+  *         otherwise ERROR result is returned.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure
+  *         that contains the configuration information for the specified DMA2D peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
+  *          - ERROR: Issue occurred during DMA2D registers initialization
+  */
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
+  uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode));
+  assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode));
+  assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
+  assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
+  assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen));
+  assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed));
+  assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue));
+  assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha));
+  assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset));
+  assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode));
+  assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode));
+
+  /* DMA2D transfers must be disabled to configure bits in initialization registers */
+  tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx);
+  tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx);
+  tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx);
+  if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U))
+  {
+    /* DMA2D CR register configuration -------------------------------------------*/
+    LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode);
+
+    /* DMA2D OPFCCR register configuration ---------------------------------------*/
+    MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \
+               (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode));
+
+    /* DMA2D OOR register configuration ------------------------------------------*/
+    LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
+
+    /* DMA2D NLR register configuration ------------------------------------------*/
+    LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines);
+
+    /* DMA2D OMAR register configuration ------------------------------------------*/
+    LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
+
+    /* DMA2D OCOLR register configuration ------------------------------------------*/
+    DMA2D_ColorStruct.ColorMode   = DMA2D_InitStruct->ColorMode;
+    DMA2D_ColorStruct.OutputBlue  = DMA2D_InitStruct->OutputBlue;
+    DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
+    DMA2D_ColorStruct.OutputRed   = DMA2D_InitStruct->OutputRed;
+    DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
+    LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct);
+
+    status = SUCCESS;
+  }
+  /* If DMA2D transfers are not disabled, return ERROR */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
+  * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+  /* Set DMA2D_InitStruct fields to default values */
+  DMA2D_InitStruct->Mode                = LL_DMA2D_MODE_M2M;
+  DMA2D_InitStruct->ColorMode           = LL_DMA2D_OUTPUT_MODE_ARGB8888;
+  DMA2D_InitStruct->NbrOfLines          = 0x0U;
+  DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
+  DMA2D_InitStruct->LineOffset          = 0x0U;
+  DMA2D_InitStruct->OutputBlue          = 0x0U;
+  DMA2D_InitStruct->OutputGreen         = 0x0U;
+  DMA2D_InitStruct->OutputRed           = 0x0U;
+  DMA2D_InitStruct->OutputAlpha         = 0x0U;
+  DMA2D_InitStruct->OutputMemoryAddress = 0x0U;
+  DMA2D_InitStruct->AlphaInversionMode  = LL_DMA2D_ALPHA_REGULAR;
+  DMA2D_InitStruct->RBSwapMode          = LL_DMA2D_RB_MODE_REGULAR;
+}
+
+/**
+  * @brief  Configure the foreground or background according to the specified parameters
+  *         in the LL_DMA2D_LayerCfgTypeDef structure.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
+  *         the configuration information for the specified layer.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval None
+  */
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset));
+  assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode));
+  assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode));
+  assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize));
+  assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode));
+  assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green));
+  assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red));
+  assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue));
+  assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha));
+  assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode));
+  assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode));
+
+  if (LayerIdx == 0U)
+  {
+    /* Configure the background memory address */
+    LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+    /* Configure the background line offset */
+    LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+    /* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion
+       CLUT size, CLUT Color mode and Color mode */
+    MODIFY_REG(DMA2Dx->BGPFCCR, \
+               (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \
+                DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \
+               ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
+                DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
+                (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
+                DMA2D_LayerCfg->ColorMode));
+
+    /* Configure the background color */
+    LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+    /* Configure the background CLUT memory address */
+    LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+  }
+  else
+  {
+    /* Configure the foreground memory address */
+    LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+    /* Configure the foreground line offset */
+    LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+    /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion
+       CLUT size, CLUT Color mode and Color mode */
+    MODIFY_REG(DMA2Dx->FGPFCCR, \
+               (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_AM | \
+                DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
+               ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
+                DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
+                (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
+                DMA2D_LayerCfg->ColorMode));
+
+    /* Configure the foreground color */
+    LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+    /* Configure the foreground CLUT memory address */
+    LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+  }
+}
+
+/**
+  * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
+  * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
+{
+  /* Set DMA2D_LayerCfg fields to default values */
+  DMA2D_LayerCfg->MemoryAddress      = 0x0U;
+  DMA2D_LayerCfg->ColorMode          = LL_DMA2D_INPUT_MODE_ARGB8888;
+  DMA2D_LayerCfg->LineOffset         = 0x0U;
+  DMA2D_LayerCfg->CLUTColorMode      = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888;
+  DMA2D_LayerCfg->CLUTSize           = 0x0U;
+  DMA2D_LayerCfg->AlphaMode          = LL_DMA2D_ALPHA_MODE_NO_MODIF;
+  DMA2D_LayerCfg->Alpha              = 0x0U;
+  DMA2D_LayerCfg->Blue               = 0x0U;
+  DMA2D_LayerCfg->Green              = 0x0U;
+  DMA2D_LayerCfg->Red                = 0x0U;
+  DMA2D_LayerCfg->CLUTMemoryAddress  = 0x0U;
+  DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
+  DMA2D_LayerCfg->RBSwapMode         = LL_DMA2D_RB_MODE_REGULAR;
+}
+
+/**
+  * @brief  Initialize DMA2D output color register according to the specified parameters
+  *         in DMA2D_ColorStruct.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains
+  *         the color configuration information for the specified DMA2D peripheral.
+  * @retval None
+  */
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
+{
+  uint32_t outgreen = 0U;
+  uint32_t outred   = 0U;
+  uint32_t outalpha = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode));
+  assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen));
+  assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed));
+  assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue));
+  assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha));
+
+  /* DMA2D OCOLR register configuration ------------------------------------------*/
+  if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+    outred = DMA2D_ColorStruct->OutputRed << 16U;
+    outalpha = DMA2D_ColorStruct->OutputAlpha << 24U;
+  }
+  else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+    outred = DMA2D_ColorStruct->OutputRed << 16U;
+    outalpha = 0x00000000U;
+  }
+  else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+    outred = DMA2D_ColorStruct->OutputRed << 11U;
+    outalpha = 0x00000000U;
+  }
+  else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+    outred = DMA2D_ColorStruct->OutputRed << 10U;
+    outalpha = DMA2D_ColorStruct->OutputAlpha << 15U;
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 4U;
+    outred = DMA2D_ColorStruct->OutputRed << 8U;
+    outalpha = DMA2D_ColorStruct->OutputAlpha << 12U;
+  }
+  LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha));
+}
+
+/**
+  * @brief  Return DMA2D output Blue color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU));
+  }
+  
+  return color;
+}
+
+/**
+  * @brief  Return DMA2D output Green color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U);
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U);
+  }
+  
+  return color;
+}
+
+/**
+  * @brief  Return DMA2D output Red color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U);
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U);
+  }
+  
+  return color;
+}
+
+/**
+  * @brief  Return DMA2D output Alpha color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U);
+  }
+  else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565))
+  {
+    color = 0x0U;
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U);
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U);
+  }
+  
+  return color;
+}
+
+/**
+  * @brief  Configure DMA2D transfer size.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+  * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+  * @retval None
+  */
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \
+             ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (DMA2D) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h
new file mode 100755
index 0000000..d0069d0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h
@@ -0,0 +1,2055 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_dma2d.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DMA2D LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_DMA2D_H
+#define __STM32L4xx_LL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA2D)
+
+/** @defgroup DMA2D_LL DMA2D
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL DMA2D Init Structure Definition
+  */
+typedef struct
+{
+  uint32_t Mode;                 /*!< Specifies the DMA2D transfer mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
+
+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputMemoryAddress;  /*!< Specifies the memory address.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+
+  uint32_t LineOffset;           /*!< Specifies the output line offset value.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
+
+  uint32_t NbrOfLines;           /*!< Specifies the number of lines of the area to be transferred.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+
+  uint32_t NbrOfPixelsPerLines;  /*!< Specifies the number of pixels per lines of the area to be transfered.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+
+  uint32_t AlphaInversionMode;   /*!< Specifies the output alpha inversion mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
+
+  uint32_t RBSwapMode;           /*!< Specifies the output Red Blue swap mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
+
+} LL_DMA2D_InitTypeDef;
+
+/**
+  * @brief LL DMA2D Layer Configuration Structure Definition
+  */
+typedef struct
+{
+  uint32_t MemoryAddress;        /*!< Specifies the foreground or background memory address.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
+
+  uint32_t LineOffset;           /*!< Specifies the foreground or background line offset value.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
+
+  uint32_t ColorMode;            /*!< Specifies the foreground or background color mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
+
+  uint32_t CLUTColorMode;        /*!< Specifies the foreground or background CLUT color mode.
+                                       - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
+
+  uint32_t CLUTSize;             /*!< Specifies the foreground or background CLUT size.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
+
+  uint32_t AlphaMode;            /*!< Specifies the foreground or background alpha mode.
+                                       - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
+
+  uint32_t Alpha;                /*!< Specifies the foreground or background Alpha value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
+
+  uint32_t Blue;                 /*!< Specifies the foreground or background Blue color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
+
+  uint32_t Green;                /*!< Specifies the foreground or background Green color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
+
+  uint32_t Red;                  /*!< Specifies the foreground or background Red color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
+
+  uint32_t CLUTMemoryAddress;    /*!< Specifies the foreground or background CLUT memory address.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
+
+  uint32_t AlphaInversionMode;   /*!< Specifies the foreground or background alpha inversion mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
+
+  uint32_t RBSwapMode;           /*!< Specifies the foreground or background Red Blue swap mode.
+                                      This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
+
+} LL_DMA2D_LayerCfgTypeDef;
+
+/**
+  * @brief LL DMA2D Output Color Structure Definition
+  */
+typedef struct
+{
+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+} LL_DMA2D_ColorTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA2D_ReadReg function
+  * @{
+  */
+#define LL_DMA2D_FLAG_CEIF          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
+#define LL_DMA2D_FLAG_CTCIF         DMA2D_ISR_CTCIF    /*!< CLUT Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_CAEIF         DMA2D_ISR_CAEIF    /*!< CLUT Access Error Interrupt Flag */
+#define LL_DMA2D_FLAG_TWIF          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
+#define LL_DMA2D_FLAG_TCIF          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_TEIF          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA2D_ReadReg and  LL_DMA2D_WriteReg functions
+  * @{
+  */
+#define LL_DMA2D_IT_CEIE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
+#define LL_DMA2D_IT_CTCIE            DMA2D_CR_CTCIE   /*!< CLUT Transfer Complete Interrupt */
+#define LL_DMA2D_IT_CAEIE            DMA2D_CR_CAEIE   /*!< CLUT Access Error Interrupt */
+#define LL_DMA2D_IT_TWIE             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
+#define LL_DMA2D_IT_TCIE             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
+#define LL_DMA2D_IT_TEIE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_DMA2D_MODE_M2M                       0x00000000U                       /*!< DMA2D memory to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_PFC                   DMA2D_CR_MODE_0                   /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND                 DMA2D_CR_MODE_1                   /*!< DMA2D memory to memory with blending transfer mode */
+#define LL_DMA2D_MODE_R2M                       DMA2D_CR_MODE                     /*!< DMA2D register to memory transfer mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
+  * @{
+  */
+#define LL_DMA2D_OUTPUT_MODE_ARGB8888     0x00000000U                           /*!< ARGB8888 */
+#define LL_DMA2D_OUTPUT_MODE_RGB888       DMA2D_OPFCCR_CM_0                     /*!< RGB888   */
+#define LL_DMA2D_OUTPUT_MODE_RGB565       DMA2D_OPFCCR_CM_1                     /*!< RGB565   */
+#define LL_DMA2D_OUTPUT_MODE_ARGB1555     (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
+#define LL_DMA2D_OUTPUT_MODE_ARGB4444     DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
+  * @{
+  */
+#define LL_DMA2D_INPUT_MODE_ARGB8888      0x00000000U                                                /*!< ARGB8888 */
+#define LL_DMA2D_INPUT_MODE_RGB888        DMA2D_FGPFCCR_CM_0                                         /*!< RGB888   */
+#define LL_DMA2D_INPUT_MODE_RGB565        DMA2D_FGPFCCR_CM_1                                         /*!< RGB565   */
+#define LL_DMA2D_INPUT_MODE_ARGB1555      (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)                    /*!< ARGB1555 */
+#define LL_DMA2D_INPUT_MODE_ARGB4444      DMA2D_FGPFCCR_CM_2                                         /*!< ARGB4444 */
+#define LL_DMA2D_INPUT_MODE_L8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)                    /*!< L8       */
+#define LL_DMA2D_INPUT_MODE_AL44          (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)                    /*!< AL44     */
+#define LL_DMA2D_INPUT_MODE_AL88          (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88     */
+#define LL_DMA2D_INPUT_MODE_L4            DMA2D_FGPFCCR_CM_3                                         /*!< L4       */
+#define LL_DMA2D_INPUT_MODE_A8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)                    /*!< A8       */
+#define LL_DMA2D_INPUT_MODE_A4            (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)                    /*!< A4       */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
+  * @{
+  */
+#define LL_DMA2D_ALPHA_MODE_NO_MODIF       0x00000000U             /*!< No modification of the alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE        DMA2D_FGPFCCR_AM_0      /*!< Replace original alpha channel value by programmed alpha value */
+#define LL_DMA2D_ALPHA_MODE_COMBINE        DMA2D_FGPFCCR_AM_1      /*!< Replace original alpha channel value by programmed alpha value
+                                                                   with original alpha channel value                              */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
+  * @{
+  */
+#define LL_DMA2D_RB_MODE_REGULAR          0x00000000U                      /*!< RGB or ARGB */
+#define LL_DMA2D_RB_MODE_SWAP             DMA2D_FGPFCCR_RBS                /*!< BGR or ABGR */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
+  * @{
+  */
+#define LL_DMA2D_ALPHA_REGULAR          0x00000000U                     /*!< Regular alpha  */
+#define LL_DMA2D_ALPHA_INVERTED         DMA2D_FGPFCCR_AI                /*!< Inverted alpha */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
+  * @{
+  */
+#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888          0x00000000U                     /*!< ARGB8888 */
+#define LL_DMA2D_CLUT_COLOR_MODE_RGB888            DMA2D_FGPFCCR_CCM               /*!< RGB888   */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in DMA2D register.
+  * @param  __INSTANCE__ DMA2D Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA2D register.
+  * @param  __INSTANCE__ DMA2D Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Start a DMA2D transfer.
+  * @rmtoll CR          START            LL_DMA2D_Start
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
+}
+
+/**
+  * @brief  Indicate if a DMA2D transfer is ongoing.
+  * @rmtoll CR          START            LL_DMA2D_IsTransferOngoing
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START));
+}
+
+/**
+  * @brief  Suspend DMA2D transfer.
+  * @note   This API can be used to suspend automatic foreground or background CLUT loading.
+  * @rmtoll CR          SUSP            LL_DMA2D_Suspend
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+}
+
+/**
+  * @brief  Resume DMA2D transfer.
+  * @note   This API can be used to resume automatic foreground or background CLUT loading.
+  * @rmtoll CR          SUSP            LL_DMA2D_Resume
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D transfer is suspended.
+  * @note   This API can be used to indicate whether or not automatic foreground or
+  *         background CLUT loading is suspended.
+  * @rmtoll CR          SUSP            LL_DMA2D_IsSuspended
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP));
+}
+
+/**
+  * @brief  Abort DMA2D transfer.
+  * @note   This API can be used to abort automatic foreground or background CLUT loading.
+  * @rmtoll CR          ABORT            LL_DMA2D_Abort
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+}
+
+/**
+  * @brief  Indicate if DMA2D transfer is aborted.
+  * @note   This API can be used to indicate whether or not automatic foreground or
+  *         background CLUT loading is aborted.
+  * @rmtoll CR          ABORT            LL_DMA2D_IsAborted
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT));
+}
+
+/**
+  * @brief  Set DMA2D mode.
+  * @rmtoll CR          MODE          LL_DMA2D_SetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_MODE_M2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
+  *         @arg @ref LL_DMA2D_MODE_R2M
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
+}
+
+/**
+  * @brief  Return DMA2D mode
+  * @rmtoll CR          MODE         LL_DMA2D_GetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_MODE_M2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
+  *         @arg @ref LL_DMA2D_MODE_R2M
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
+}
+
+/**
+  * @brief  Set DMA2D output color mode.
+  * @rmtoll OPFCCR          CM          LL_DMA2D_SetOutputColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D output color mode.
+  * @rmtoll OPFCCR          CM         LL_DMA2D_GetOutputColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D output Red Blue swap mode.
+  * @rmtoll OPFCCR          RBS          LL_DMA2D_SetOutputRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  RBSwapMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
+}
+
+/**
+  * @brief  Return DMA2D output Red Blue swap mode.
+  * @rmtoll OPFCCR          RBS         LL_DMA2D_GetOutputRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
+}
+
+/**
+  * @brief  Set DMA2D output alpha inversion mode.
+  * @rmtoll OPFCCR          AI          LL_DMA2D_SetOutputAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AlphaInversionMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+  * @brief  Return DMA2D output alpha inversion mode.
+  * @rmtoll OPFCCR          AI         LL_DMA2D_GetOutputAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
+}
+
+/**
+  * @brief  Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll OOR          LO          LL_DMA2D_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll OOR          LO         LL_DMA2D_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
+  * @rmtoll NLR          PL          LL_DMA2D_SetNbrOfPixelsPerLines
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
+}
+
+/**
+  * @brief  Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
+  * @rmtoll NLR          PL          LL_DMA2D_GetNbrOfPixelsPerLines
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
+}
+
+/**
+  * @brief  Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+  * @rmtoll NLR          NL          LL_DMA2D_SetNbrOfLines
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
+}
+
+/**
+  * @brief  Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+  * @rmtoll NLR          NL          LL_DMA2D_GetNbrOfLines
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
+}
+
+/**
+  * @brief  Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll OMAR          MA          LL_DMA2D_SetOutputMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll OMAR          MA          LL_DMA2D_GetOutputMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
+}
+
+/**
+  * @brief  Set DMA2D output color, expressed on 32 bits ([31:0] bits).
+  * @note   Output color format depends on output color mode, ARGB8888, RGB888,
+  *         RGB565, ARGB1555 or ARGB4444.
+  * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
+  *       with respect to color mode is not done by the user code.
+  * @rmtoll OCOLR        BLUE        LL_DMA2D_SetOutputColor\n
+  *         OCOLR        GREEN       LL_DMA2D_SetOutputColor\n
+  *         OCOLR        RED         LL_DMA2D_SetOutputColor\n
+  *         OCOLR        ALPHA       LL_DMA2D_SetOutputColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
+{
+  MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
+             OutputColor);
+}
+
+/**
+  * @brief  Get DMA2D output color, expressed on 32 bits ([31:0] bits).
+  * @note   Alpha channel and red, green, blue color values must be retrieved from the returned
+  *         value based on the output color mode (ARGB8888, RGB888,  RGB565, ARGB1555 or ARGB4444)
+  *         as set by @ref LL_DMA2D_SetOutputColorMode.
+  * @rmtoll OCOLR        BLUE        LL_DMA2D_GetOutputColor\n
+  *         OCOLR        GREEN       LL_DMA2D_GetOutputColor\n
+  *         OCOLR        RED         LL_DMA2D_GetOutputColor\n
+  *         OCOLR        ALPHA       LL_DMA2D_GetOutputColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
+                             (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
+}
+
+/**
+  * @brief  Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+  * @rmtoll LWR          LW          LL_DMA2D_SetLineWatermark
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
+{
+  MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
+}
+
+/**
+  * @brief  Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+  * @rmtoll LWR          LW          LL_DMA2D_GetLineWatermark
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
+}
+
+/**
+  * @brief  Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
+  * @rmtoll AMTCR          DT          LL_DMA2D_SetDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DeadTime Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
+{
+  MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
+}
+
+/**
+  * @brief  Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
+  * @rmtoll AMTCR          DT          LL_DMA2D_GetDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
+}
+
+/**
+  * @brief  Enable DMA2D dead time functionality.
+  * @rmtoll AMTCR          EN            LL_DMA2D_EnableDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+  * @brief  Disable DMA2D dead time functionality.
+  * @rmtoll AMTCR          EN            LL_DMA2D_DisableDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+  * @brief  Indicate if DMA2D dead time functionality is enabled.
+  * @rmtoll AMTCR          EN            LL_DMA2D_IsEnabledDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN));
+}
+
+/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_SetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_GetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
+}
+
+/**
+  * @brief  Enable DMA2D foreground CLUT loading.
+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_EnableCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D foreground CLUT loading is enabled.
+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_IsEnabledCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START));
+}
+
+/**
+  * @brief  Set DMA2D foreground color mode.
+  * @rmtoll FGPFCCR          CM          LL_DMA2D_FGND_SetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground color mode.
+  * @rmtoll FGPFCCR          CM         LL_DMA2D_FGND_GetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha mode.
+  * @rmtoll FGPFCCR          AM          LL_DMA2D_FGND_SetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AphaMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha mode.
+  * @rmtoll FGPFCCR          AM         LL_DMA2D_FGND_GetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          ALPHA          LL_DMA2D_FGND_SetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          ALPHA         LL_DMA2D_FGND_GetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground Red Blue swap mode.
+  * @rmtoll FGPFCCR          RBS          LL_DMA2D_FGND_SetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  RBSwapMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground Red Blue swap mode.
+  * @rmtoll FGPFCCR          RBS         LL_DMA2D_FGND_GetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha inversion mode.
+  * @rmtoll FGPFCCR          AI          LL_DMA2D_FGND_SetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AlphaInversionMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha inversion mode.
+  * @rmtoll FGPFCCR          AI         LL_DMA2D_FGND_GetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
+}
+
+/**
+  * @brief  Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll FGOR          LO          LL_DMA2D_FGND_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll FGOR          LO         LL_DMA2D_FGND_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetColor
+  * @rmtoll FGCOLR          GREEN        LL_DMA2D_FGND_SetColor
+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_SetColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
+             ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+  * @brief  Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          RED         LL_DMA2D_FGND_GetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          GREEN          LL_DMA2D_FGND_SetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          GREEN         LL_DMA2D_FGND_GetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          BLUE          LL_DMA2D_FGND_SetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
+}
+
+/**
+  * @brief  Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_GetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_SetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_GetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_SetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
+}
+
+/**
+  * @brief  Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_GetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT color mode.
+  * @rmtoll FGPFCCR          CCM          LL_DMA2D_FGND_SetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground CLUT color mode.
+  * @rmtoll FGPFCCR          CCM         LL_DMA2D_FGND_GetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_SetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_GetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
+}
+
+/**
+  * @brief  Enable DMA2D background CLUT loading.
+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_EnableCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D background CLUT loading is enabled.
+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_IsEnabledCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START));
+}
+
+/**
+  * @brief  Set DMA2D background color mode.
+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_SetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D background color mode.
+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_GetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D background alpha mode.
+  * @rmtoll BGPFCCR          AM         LL_DMA2D_BGND_SetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AphaMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
+}
+
+/**
+  * @brief  Return DMA2D background alpha mode.
+  * @rmtoll BGPFCCR          AM          LL_DMA2D_BGND_GetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
+}
+
+/**
+  * @brief  Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          ALPHA         LL_DMA2D_BGND_SetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          ALPHA          LL_DMA2D_BGND_GetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background Red Blue swap mode.
+  * @rmtoll BGPFCCR          RBS         LL_DMA2D_BGND_SetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  RBSwapMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
+}
+
+/**
+  * @brief  Return DMA2D background Red Blue swap mode.
+  * @rmtoll BGPFCCR          RBS          LL_DMA2D_BGND_GetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
+}
+
+/**
+  * @brief  Set DMA2D background alpha inversion mode.
+  * @rmtoll BGPFCCR          AI         LL_DMA2D_BGND_SetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AlphaInversionMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+  * @brief  Return DMA2D background alpha inversion mode.
+  * @rmtoll BGPFCCR          AI          LL_DMA2D_BGND_GetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
+}
+
+/**
+  * @brief  Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll BGOR          LO         LL_DMA2D_BGND_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll BGOR          LO          LL_DMA2D_BGND_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_SetColor
+  * @rmtoll BGCOLR          GREEN        LL_DMA2D_BGND_SetColor
+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
+             ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+  * @brief  Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          RED         LL_DMA2D_BGND_SetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_GetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          GREEN         LL_DMA2D_BGND_SetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          GREEN          LL_DMA2D_BGND_GetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
+}
+
+/**
+  * @brief  Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          BLUE          LL_DMA2D_BGND_GetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
+}
+
+/**
+  * @brief  Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGCMAR          MA         LL_DMA2D_BGND_SetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGCMAR          MA           LL_DMA2D_BGND_GetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
+}
+
+/**
+  * @brief  Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          CS         LL_DMA2D_BGND_SetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
+}
+
+/**
+  * @brief  Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          CS           LL_DMA2D_BGND_GetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background CLUT color mode.
+  * @rmtoll BGPFCCR          CCM         LL_DMA2D_BGND_SetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+  * @brief  Return DMA2D background CLUT color mode.
+  * @rmtoll BGPFCCR          CCM          LL_DMA2D_BGND_GetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the DMA2D Configuration Error Interrupt Flag is set or not
+  * @rmtoll ISR          CEIF            LL_DMA2D_IsActiveFlag_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF));
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
+  * @rmtoll ISR          CTCIF            LL_DMA2D_IsActiveFlag_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF));
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
+  * @rmtoll ISR          CAEIF            LL_DMA2D_IsActiveFlag_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF));
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
+  * @rmtoll ISR          TWIF            LL_DMA2D_IsActiveFlag_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF));
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Complete Interrupt Flag is set or not
+  * @rmtoll ISR          TCIF            LL_DMA2D_IsActiveFlag_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF));
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Error Interrupt Flag is set or not
+  * @rmtoll ISR          TEIF            LL_DMA2D_IsActiveFlag_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF));
+}
+
+/**
+  * @brief  Clear DMA2D Configuration Error Interrupt Flag
+  * @rmtoll IFCR          CCEIF          LL_DMA2D_ClearFlag_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
+}
+
+/**
+  * @brief  Clear DMA2D CLUT Transfer Complete Interrupt Flag
+  * @rmtoll IFCR          CCTCIF          LL_DMA2D_ClearFlag_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
+}
+
+/**
+  * @brief  Clear DMA2D CLUT Access Error Interrupt Flag
+  * @rmtoll IFCR          CAECIF          LL_DMA2D_ClearFlag_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Watermark Interrupt Flag
+  * @rmtoll IFCR          CTWIF          LL_DMA2D_ClearFlag_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Complete Interrupt Flag
+  * @rmtoll IFCR          CTCIF          LL_DMA2D_ClearFlag_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Error Interrupt Flag
+  * @rmtoll IFCR          CTEIF          LL_DMA2D_ClearFlag_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Configuration Error Interrupt
+  * @rmtoll CR          CEIE        LL_DMA2D_EnableIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+  * @brief  Enable CLUT Transfer Complete Interrupt
+  * @rmtoll CR          CTCIE        LL_DMA2D_EnableIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+  * @brief  Enable CLUT Access Error Interrupt
+  * @rmtoll CR          CAEIE        LL_DMA2D_EnableIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+  * @brief  Enable Transfer Watermark Interrupt
+  * @rmtoll CR          TWIE        LL_DMA2D_EnableIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+  * @brief  Enable Transfer Complete Interrupt
+  * @rmtoll CR          TCIE        LL_DMA2D_EnableIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+  * @brief  Enable Transfer Error Interrupt
+  * @rmtoll CR          TEIE        LL_DMA2D_EnableIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+  * @brief  Disable Configuration Error Interrupt
+  * @rmtoll CR          CEIE        LL_DMA2D_DisableIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+  * @brief  Disable CLUT Transfer Complete Interrupt
+  * @rmtoll CR          CTCIE        LL_DMA2D_DisableIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+  * @brief  Disable CLUT Access Error Interrupt
+  * @rmtoll CR          CAEIE        LL_DMA2D_DisableIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+  * @brief  Disable Transfer Watermark Interrupt
+  * @rmtoll CR          TWIE        LL_DMA2D_DisableIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete Interrupt
+  * @rmtoll CR          TCIE        LL_DMA2D_DisableIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Error Interrupt
+  * @rmtoll CR          TEIE        LL_DMA2D_DisableIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+  * @brief  Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
+  * @rmtoll CR          CEIE        LL_DMA2D_IsEnabledIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE));
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
+  * @rmtoll CR          CTCIE        LL_DMA2D_IsEnabledIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE));
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
+  * @rmtoll CR          CAEIE        LL_DMA2D_IsEnabledIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE));
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
+  * @rmtoll CR          TWIE        LL_DMA2D_IsEnabledIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE));
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
+  * @rmtoll CR          TCIE        LL_DMA2D_IsEnabledIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE));
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
+  * @rmtoll CR          TEIE        LL_DMA2D_IsEnabledIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE));
+}
+
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+  * @{
+  */
+
+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (DMA2D) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_DMA2D_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c
new file mode 100755
index 0000000..e94a119
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c
@@ -0,0 +1,303 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_exti.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   EXTI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_exti.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the EXTI registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are de-initialized
+  *          - ERROR: not applicable
+  */
+uint32_t LL_EXTI_DeInit(void)
+{
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR1,   0xFF820000U);
+  /* Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR1,   0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR1,  0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR1,  0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+  /* Pending register set to default reset values */
+  LL_EXTI_WriteReg(PR1,    0x007DFFFFU);
+
+  /* Interrupt mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(IMR2,        0x00000087U);
+  /* Event mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(EMR2,        0x00000000U);
+  /* Rising Trigger selection register 2 set to default reset values */
+  LL_EXTI_WriteReg(RTSR2,       0x00000000U);
+  /* Falling Trigger selection register 2 set to default reset values */
+  LL_EXTI_WriteReg(FTSR2,       0x00000000U);
+  /* Software interrupt event register 2 set to default reset values */
+  LL_EXTI_WriteReg(SWIER2,      0x00000000U);
+  /* Pending register 2 set to default reset values */
+  LL_EXTI_WriteReg(PR2,         0x00000078U);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are initialized
+  *          - ERROR: not applicable
+  */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+  assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+  /* ENABLE LineCommand */
+  if (EXTI_InitStruct->LineCommand != DISABLE)
+  {
+    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+    /* Configure EXTI Lines in range from 0 to 31 */
+    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        default:
+          status = ERROR;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Rising Trigger on provided Lines */
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+    /* Configure EXTI Lines in range from 32 to 63 */
+    if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        default:
+          status = ERROR;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable IT on provided Lines */
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+  }
+  /* DISABLE LineCommand */
+  else
+  {
+    /* De-configure EXTI Lines in range from 0 to 31 */
+    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+    /* De-configure EXTI Lines in range from 32 to 63 */
+    LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+    LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval None
+  */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->LineCommand    = DISABLE;
+  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (EXTI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h
new file mode 100755
index 0000000..8e31cc7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h
@@ -0,0 +1,1362 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_exti.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_EXTI_H
+#define __STM32L4xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
+#if defined(EXTI_IMR1_IM16)
+#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR1_IM18)
+#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
+#if defined(EXTI_IMR1_IM20)
+#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR1_IM21)
+#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR1_IM22)
+#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
+#endif
+#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
+#if defined(EXTI_IMR1_IM24)
+#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR1_IM25)
+#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR1_IM26)
+#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR1_IM27)
+#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR1_IM28)
+#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR1_IM29)
+#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR1_IM30)
+#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR1_IM31)
+#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
+#if defined(EXTI_IMR2_IM33)
+#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
+#endif
+#if defined(EXTI_IMR2_IM34)
+#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
+#endif
+#if defined(EXTI_IMR2_IM35)
+#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
+#endif
+#if defined(EXTI_IMR2_IM36)
+#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
+#endif
+#if defined(EXTI_IMR2_IM37)
+#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
+#endif
+#if defined(EXTI_IMR2_IM38)
+#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
+#endif
+#if defined(EXTI_IMR2_IM39)
+#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
+#endif
+#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR1, ExtiLine);
+}
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @note The reset value for the direct lines (lines from 32 to 34, line
+  *       39) is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @note The reset value for the direct lines (lines from 32 to 34, line
+  *       39) is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+  * @note The reset value for the direct lines (lines from 32 to 34, line
+  *       39) is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine));
+
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
+  * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+
+/**
+  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR2, ExtiLine);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c
new file mode 100755
index 0000000..509f8b2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c
@@ -0,0 +1,771 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_fmc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   FMC Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  =============================================================================
+                        ##### FMC peripheral features #####
+  =============================================================================
+    [..] The Flexible memory controller (FMC) includes following memory controllers:
+         (+) The NOR/PSRAM memory controller
+         (+) The NAND memory controller
+
+    [..] The FMC functional block makes the interface with synchronous and asynchronous static
+         memories. Its main purposes are:
+         (+) to translate AHB transactions into the appropriate external device protocol.
+         (+) to meet the access time requirements of the external memory devices.
+
+    [..] All external memories share the addresses, data and control signals with the controller.
+         Each external device is accessed by means of a unique Chip Select. The FMC performs
+         only one access at a time to an external device.
+         The main features of the FMC controller are the following:
+          (+) Interface with static-memory mapped devices including:
+             (++) Static random access memory (SRAM).
+             (++) NOR Flash memory.
+             (++) PSRAM (4 memory banks).
+             (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+                data
+          (+) Independent Chip Select control for each memory bank
+          (+) Independent configuration for each memory bank
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+
+#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
+
+/** @defgroup FMC_LL FMC Low Layer
+  * @brief FMC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
+  * @{
+  */
+
+/* ----------------------- FMC registers bit mask --------------------------- */
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN  | \
+                                      FMC_PCR_PTYP    | FMC_PCR_PWID   | \
+                                      FMC_PCR_ECCEN   | FMC_PCR_TCLR   | \
+                                      FMC_PCR_TAR     | FMC_PCR_ECCPS))
+
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEM_MEMSET  | FMC_PMEM_MEMWAIT |\
+                                      FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATT_ATTSET  | FMC_PATT_ATTWAIT |\
+                                      FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
+
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+#if defined(FMC_BCR1_WFDIS)
+#define BCR_CLEAR_MASK                  ((uint32_t)(FMC_BCRx_MBKEN   | FMC_BCRx_MUXEN     |\
+                                                    FMC_BCRx_MTYP    | FMC_BCRx_MWID      |\
+                                                    FMC_BCRx_FACCEN  | FMC_BCRx_BURSTEN   |\
+                                                    FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG   |\
+                                                    FMC_BCRx_WREN    | FMC_BCRx_WAITEN    |\
+                                                    FMC_BCRx_EXTMOD  | FMC_BCRx_ASYNCWAIT |\
+                                                    FMC_BCRx_CPSIZE  | FMC_BCRx_CBURSTRW  |\
+                                                    FMC_BCR1_CCLKEN  | FMC_BCR1_WFDIS))
+#else
+#define BCR_CLEAR_MASK                  ((uint32_t)(FMC_BCRx_MBKEN   | FMC_BCRx_MUXEN     |\
+                                                    FMC_BCRx_MTYP    | FMC_BCRx_MWID      |\
+                                                    FMC_BCRx_FACCEN  | FMC_BCRx_BURSTEN   |\
+                                                    FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG   |\
+                                                    FMC_BCRx_WREN    | FMC_BCRx_WAITEN    |\
+                                                    FMC_BCRx_EXTMOD  | FMC_BCRx_ASYNCWAIT |\
+                                                    FMC_BCRx_CPSIZE  | FMC_BCRx_CBURSTRW  |\
+                                                    FMC_BCR1_CCLKEN))
+#endif /* FMC_BCR1_WFDIS */
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK                 ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD  |\
+                                                   FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
+                                                   FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT  |\
+                                                   FMC_BTRx_ACCMOD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#define BWTR_CLEAR_MASK                ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD | \
+                                                   FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD | \
+                                                   FMC_BWTRx_BUSTURN))
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions
+  * @brief    NORSRAM Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                   ##### How to use NORSRAM device driver #####
+  ==============================================================================
+
+  [..]
+    This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+    to run the NORSRAM external devices.
+
+    (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+    (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+    (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+    (+) FMC NORSRAM bank extended timing configuration using the function
+        FMC_NORSRAM_Extended_Timing_Init()
+    (+) FMC NORSRAM bank enable/disable write operation using the functions
+        FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NORSRAM interface
+    (+) De-initialize the FMC NORSRAM interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the FMC_NORSRAM device according to the specified
+  *         control parameters in the FMC_NORSRAM_InitTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Init Pointer to NORSRAM Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+  assert_param(IS_FMC_MUX(Init->DataAddressMux));
+  assert_param(IS_FMC_MEMORY(Init->MemoryType));
+  assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+  assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+  assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+  assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+  assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+  assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+  assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+  assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+  assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+#if defined(FMC_BCR1_WFDIS)
+  assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
+#endif /* FMC_BCR1_WFDIS */
+  assert_param(IS_FMC_PAGESIZE(Init->PageSize));
+
+  /* Disable NORSRAM Device */
+  __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
+  /* Set NORSRAM device control parameters */
+  if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+  {
+    MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE
+               | Init->DataAddressMux
+               | Init->MemoryType
+               | Init->MemoryDataWidth
+               | Init->BurstAccessMode
+               | Init->WaitSignalPolarity
+               | Init->WaitSignalActive
+               | Init->WriteOperation
+               | Init->WaitSignal
+               | Init->ExtendedMode
+               | Init->AsynchronousWait
+               | Init->WriteBurst
+               | Init->ContinuousClock
+#if defined(FMC_BCR1_WFDIS)
+               | Init->WriteFifo
+#endif /* FMC_BCR1_WFDIS */
+               | Init->PageSize
+                                                                     )
+              );
+  }
+  else
+  {
+    MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE
+               | Init->DataAddressMux
+               | Init->MemoryType
+               | Init->MemoryDataWidth
+               | Init->BurstAccessMode
+               | Init->WaitSignalPolarity
+               | Init->WaitSignalActive
+               | Init->WriteOperation
+               | Init->WaitSignal
+               | Init->ExtendedMode
+               | Init->AsynchronousWait
+               | Init->WriteBurst
+               | Init->ContinuousClock
+#if defined(FMC_BCR1_WFDIS)
+               | Init->WriteFifo
+#endif /* FMC_BCR1_WFDIS */
+               | Init->PageSize
+                                                                     )
+              );
+  }
+
+  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+  if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+  {
+    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
+  }
+
+#if defined(FMC_BCR1_WFDIS)
+  if (Init->NSBank != FMC_NORSRAM_BANK1)
+  {
+    /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
+    SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
+  }
+
+#endif /* FMC_BCR1_WFDIS */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitialize the FMC_NORSRAM peripheral
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  ExDevice Pointer to NORSRAM extended mode device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Disable the FMC_NORSRAM device */
+  __FMC_NORSRAM_DISABLE(Device, Bank);
+
+  /* De-initialize the FMC_NORSRAM device */
+  /* FMC_NORSRAM_BANK1 */
+  if (Bank == FMC_NORSRAM_BANK1)
+  {
+    Device->BTCR[Bank] = 0x000030DB;
+  }
+  /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+  else
+  {
+    Device->BTCR[Bank] = 0x000030D2;
+  }
+
+  Device->BTCR[Bank + 1] = 0x0FFFFFFF;
+  ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmpr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+  assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+  assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+  assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+  assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+  assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+  assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Set FMC_NORSRAM device timing parameters */
+  MODIFY_REG(Device->BTCR[Bank + 1],                                                    \
+             BTR_CLEAR_MASK,                                                                     \
+             (uint32_t)(Timing->AddressSetupTime                                               | \
+                        ((Timing->AddressHoldTime)        << POSITION_VAL(FMC_BTRx_ADDHLD))        | \
+                        ((Timing->DataSetupTime)          << POSITION_VAL(FMC_BTRx_DATAST))        | \
+                        ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FMC_BTRx_BUSTURN))       | \
+                        (((Timing->CLKDivision) - 1)        << POSITION_VAL(FMC_BTRx_CLKDIV))        | \
+                        (((Timing->DataLatency) - 2)        << POSITION_VAL(FMC_BTRx_DATLAT))        | \
+                        (Timing->AccessMode)));
+
+  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+  if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+  {
+    tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
+    tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV));
+    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @param  ExtendedMode FMC Extended Mode
+  *          This parameter can be one of the following values:
+  *            @arg FMC_EXTENDED_MODE_DISABLE
+  *            @arg FMC_EXTENDED_MODE_ENABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+
+  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+  if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+  {
+    /* Check the parameters */
+    assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+    assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+    assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+    assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+    assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+    assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+    assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+    MODIFY_REG(Device->BWTR[Bank],                                                  \
+               BWTR_CLEAR_MASK,                                                              \
+               (uint32_t)(Timing->AddressSetupTime                                         | \
+                          ((Timing->AddressHoldTime)        << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \
+                          ((Timing->DataSetupTime)          << POSITION_VAL(FMC_BWTRx_DATAST)) | \
+                          Timing->AccessMode                                                          | \
+                          ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FMC_BWTRx_BUSTURN))));
+  }
+  else
+  {
+    Device->BWTR[Bank] = 0x0FFFFFFF;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_NORSRAM_Group2 Control functions
+ *  @brief   management functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### FMC_NORSRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NORSRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically FMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Enable write operation */
+  SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Disable write operation */
+  CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/** @defgroup FMC_NAND FMC NAND Controller functions
+  * @brief    NAND Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use NAND device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC NAND banks in order
+    to run the NAND external devices.
+
+    (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+    (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+    (+) FMC NAND bank common space timing configuration using the function
+        FMC_NAND_CommonSpace_Timing_Init()
+    (+) FMC NAND bank attribute space timing configuration using the function
+        FMC_NAND_AttributeSpace_Timing_Init()
+    (+) FMC NAND bank enable/disable ECC correction feature using the functions
+        FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+    (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NAND interface
+    (+) De-initialize the FMC NAND interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FMC_NAND device according to the specified
+  *         control parameters in the FMC_NAND_HandleTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Init Pointer to NAND Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+  assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
+                                              FMC_PCR_MEMORY_TYPE_NAND                              |
+                                              Init->MemoryDataWidth                                 |
+                                              Init->EccComputation                                  |
+                                              Init->ECCPageSize                                     |
+                                              ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCR_TCLR)) |
+                                              ((Init->TARSetupTime) << POSITION_VAL(FMC_PCR_TAR))));
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Common space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime                                           |
+                                               ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |
+                                               ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |
+                                               ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ))));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime                                           |
+                                               ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATT_ATTWAIT)) |
+                                               ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATT_ATTHOLD)) |
+                                               ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATT_ATTHIZ))));
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitialize the FMC_NAND device
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Disable the NAND Bank */
+  __FMC_NAND_DISABLE(Device, Bank);
+
+  /* De-initialize the NAND Bank */
+    /* Set the FMC_NAND_BANK3 registers to their reset values */
+    WRITE_REG(Device->PCR,  0x00000018);
+    WRITE_REG(Device->SR,   0x00000040);
+    WRITE_REG(Device->PMEM, 0xFCFCFCFC);
+    WRITE_REG(Device->PATT, 0xFCFCFCFC);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   management functions
+ *
+@verbatim
+  ==============================================================================
+                       ##### FMC_NAND Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NAND interface.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Enable ECC feature */
+    SET_BIT(Device->PCR, FMC_PCR_ECCEN);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Disable ECC feature */
+    CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  ECCval Pointer to ECC value
+  * @param  Bank NAND bank number
+  * @param  Timeout Timeout wait value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FIFO is empty */
+  while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+    /* Get the ECCR register value */
+    *ECCval = (uint32_t)Device->ECCR;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
+
+#endif /* FMC_BANK1 */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h
new file mode 100755
index 0000000..c6e66f0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h
@@ -0,0 +1,979 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_fmc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of FMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_FMC_H
+#define __STM32L4xx_LL_FMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+
+/** @addtogroup FMC_LL
+  * @{
+  */
+
+/** @addtogroup FMC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+                                        ((__BANK__) == FMC_NORSRAM_BANK2) || \
+                                        ((__BANK__) == FMC_NORSRAM_BANK3) || \
+                                        ((__BANK__) == FMC_NORSRAM_BANK4))
+
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+                              ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+                                    ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+                                    ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_WRITE_BURST(__BURST__)          (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+                                                ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+
+#define IS_FMC_PAGESIZE(__SIZE__)              (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_512) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_1024))
+
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__)     (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                                ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#if defined(FMC_BCR1_WFDIS)
+#define IS_FMC_WRITE_FIFO(__FIFO__)            (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
+                                                ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
+
+#endif /* FMC_BCR1_WFDIS */
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+                                       ((__MODE__) == FMC_ACCESS_MODE_B) || \
+                                       ((__MODE__) == FMC_ACCESS_MODE_C) || \
+                                       ((__MODE__) == FMC_ACCESS_MODE_D))
+
+#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
+
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
+                                      ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
+
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
+                                         ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
+
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+                                 ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
+  * @{
+  */
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
+  * @{
+  */
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Setup_Time FMC_Setup_Time
+  * @{
+  */
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
+  * @{
+  */
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
+  * @{
+  */
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
+  * @{
+  */
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
+  * @{
+  */
+
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
+  * @{
+  */
+
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
+  * @{
+  */
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+/**
+  * @}
+  */
+
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+                                      ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                             ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+                                                ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+                                                ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+                                          ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+                                         ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                     ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
+
+/** @defgroup FMC_Data_Latency FMC Data Latency
+  * @{
+  */
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
+  * @{
+  */
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
+  * @{
+  */
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
+  * @{
+  */
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
+  * @{
+  */
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types
+  * @{
+  */
+
+#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef
+
+#define FMC_NORSRAM_DEVICE                    FMC_Bank1_R
+#define FMC_NORSRAM_EXTENDED_DEVICE           FMC_Bank1E_R
+#define FMC_NAND_DEVICE                       FMC_Bank3_R
+
+/**
+  * @brief  FMC_NORSRAM Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                     */
+
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
+                                              multiplexed on the data bus or not.
+                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */
+
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
+                                              the corresponding memory device.
+                                              This parameter can be a value of @ref FMC_Memory_Type                      */
+
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */
+
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
+                                              valid only with synchronous burst Flash memories.
+                                              This parameter can be a value of @ref FMC_Burst_Access_Mode                */
+
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
+                                              the Flash memory in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */
+
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
+                                              clock cycle before the wait state or during the wait state,
+                                              valid only when accessing memories in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Timing                      */
+
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC.
+                                              This parameter can be a value of @ref FMC_Write_Operation                  */
+
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
+                                              signal, valid for Flash memory access in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal                      */
+
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
+                                              This parameter can be a value of @ref FMC_Extended_Mode                    */
+
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
+                                              valid only with asynchronous Flash memories.
+                                              This parameter can be a value of @ref FMC_AsynchronousWait                 */
+
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
+                                              This parameter can be a value of @ref FMC_Write_Burst                      */
+
+  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care
+                                              through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Continous_Clock                  */
+
+  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.
+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care
+                                              through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Write_FIFO.
+                                              @note This Parameter is not available for STM32L47x/L48x devices.         */
+
+  uint32_t PageSize;                     /*!< Specifies the memory page size.
+                                              This parameter can be a value of @ref FMC_Page_Size                        */
+}FMC_NORSRAM_InitTypeDef;
+
+/**
+  * @brief  FMC_NORSRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address setup time.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address hold time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data setup time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+                                              NOR Flash memories.                                                        */
+
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the bus turnaround.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
+
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+                                              accesses.                                                                  */
+
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
+                                              to the memory before getting the first data.
+                                              The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+                                                with synchronous burst mode enable                                       */
+
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
+                                              This parameter can be a value of @ref FMC_Access_Mode                      */
+
+}FMC_NORSRAM_TimingTypeDef;
+
+/**
+  * @brief  FMC_NAND Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
+                                        This parameter can be a value of @ref FMC_NAND_Bank                    */
+
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
+                                        This parameter can be any value of @ref FMC_Wait_feature               */
+
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
+                                        This parameter can be any value of @ref FMC_NAND_Data_Width            */
+
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
+                                        This parameter can be any value of @ref FMC_ECC                        */
+
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
+                                        This parameter can be any value of @ref FMC_ECC_Page_Size              */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_NAND_InitTypeDef;
+
+/**
+  * @brief  FMC_NAND Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
+                                      the command assertion for NAND-Flash read or write access
+                                      to common/Attribute or I/O memory space (depending on
+                                      the memory space timing to be configured).
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
+
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
+                                      command for NAND-Flash read or write access to
+                                      common/Attribute or I/O memory space (depending on the
+                                      memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
+                                      (and data for write access) after the command de-assertion
+                                      for NAND-Flash read or write access to common/Attribute
+                                      or I/O memory space (depending on the memory space timing
+                                      to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
+                                      data bus is kept in HiZ after the start of a NAND-Flash
+                                      write access to common/Attribute or I/O memory space (depending
+                                      on the memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+}FMC_NAND_PCC_TimingTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+  * @{
+  */
+#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+  * @{
+  */
+
+#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FMC_BCRx_MUXEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+  * @{
+  */
+
+#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FMC_BCRx_MTYP_0)
+#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)FMC_BCRx_MTYP_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
+  * @{
+  */
+
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FMC_BCRx_MWID_0)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FMC_BCRx_MWID_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
+  * @{
+  */
+
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FMC_BCRx_FACCEN)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+  * @{
+  */
+
+#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FMC_BCRx_BURSTEN)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+  * @{
+  */
+
+#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FMC_BCRx_WAITPOL)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+  * @{
+  */
+
+#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)FMC_BCRx_WAITCFG)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+  * @{
+  */
+
+#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)FMC_BCRx_WREN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+  * @{
+  */
+
+#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FMC_BCRx_WAITEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+  * @{
+  */
+
+#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)FMC_BCRx_EXTMOD)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+  * @{
+  */
+
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FMC_BCRx_ASYNCWAIT)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Page_Size FMC Page Size
+  * @{
+  */
+#define FMC_PAGE_SIZE_NONE                      ((uint32_t)0x00000000)
+#define FMC_PAGE_SIZE_128                       ((uint32_t)FMC_BCRx_CPSIZE_0)
+#define FMC_PAGE_SIZE_256                       ((uint32_t)FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_512                       ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
+#define FMC_PAGE_SIZE_1024                      ((uint32_t)FMC_BCRx_CPSIZE_2)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+  * @{
+  */
+
+#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)FMC_BCRx_CBURSTRW)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Continous_Clock FMC Continous Clock
+  * @{
+  */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)FMC_BCR1_CCLKEN)
+/**
+  * @}
+  */
+
+#if defined(FMC_BCR1_WFDIS)
+/** @defgroup FMC_Write_FIFO FMC Write FIFO
+  * @{
+  */
+#define FMC_WRITE_FIFO_DISABLE                  ((uint32_t)FMC_BCR1_WFDIS)
+#define FMC_WRITE_FIFO_ENABLE                   ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+#endif /* FMC_BCR1_WFDIS */
+/** @defgroup FMC_Access_Mode FMC Access Mode
+  * @{
+  */
+
+#define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B                        ((uint32_t)FMC_BTRx_ACCMOD_0)
+#define FMC_ACCESS_MODE_C                        ((uint32_t)FMC_BTRx_ACCMOD_1)
+#define FMC_ACCESS_MODE_D                        ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller
+  * @{
+  */
+
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+  * @{
+  */
+#define FMC_NAND_BANK3                          ((uint32_t)0x00000100)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+  * @{
+  */
+#define FMC_NAND_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
+#define FMC_NAND_WAIT_FEATURE_ENABLE            ((uint32_t)FMC_PCR_PWAITEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+  * @{
+  */
+#define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)FMC_PCR_PTYP)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+  * @{
+  */
+#define FMC_NAND_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
+#define FMC_NAND_MEM_BUS_WIDTH_16               ((uint32_t)FMC_PCR_PWID_0)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC FMC NAND ECC
+  * @{
+  */
+#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE                     ((uint32_t)FMC_PCR_ECCEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
+  * @{
+  */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FMC_PCR_ECCPS_0)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FMC_PCR_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FMC_PCR_ECCPS_2)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Interrupt_definition FMC Interrupt definition
+  * @brief FMC Interrupt definition
+  * @{
+  */
+#define FMC_IT_RISING_EDGE                ((uint32_t)FMC_SR_IREN)
+#define FMC_IT_LEVEL                      ((uint32_t)FMC_SR_ILEN)
+#define FMC_IT_FALLING_EDGE               ((uint32_t)FMC_SR_IFEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Flag_definition FMC Flag definition
+  * @brief FMC Flag definition
+  * @{
+  */
+#define FMC_FLAG_RISING_EDGE                    ((uint32_t)FMC_SR_IRS)
+#define FMC_FLAG_LEVEL                          ((uint32_t)FMC_SR_ILS)
+#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)FMC_SR_IFS)
+#define FMC_FLAG_FEMPT                          ((uint32_t)FMC_SR_FEMPT)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
+  * @{
+  */
+
+/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
+ *  @brief macros to handle NOR device enable/disable and read/write operations
+ *  @{
+ */
+
+/**
+  * @brief  Enable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval none
+  */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval none
+  */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Macros FMC NAND Macros
+ *  @brief macros to handle NAND device enable/disable
+ *  @{
+ */
+
+/**
+  * @brief  Enable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__ FMC_NAND Bank
+  * @retval None
+  */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__ FMC_NAND Bank
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Interrupt FMC Interrupt
+ *  @brief macros to handle FMC interrupts
+ * @{
+ */
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND Instance
+  * @param  __BANK__      FMC_NAND Bank
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND Instance
+  * @param  __BANK__      FMC_NAND Bank
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __FLAG__ FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT FIFO empty flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __FLAG__ FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT FIFO empty flag.
+  * @retval None
+  */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup FMC_LL_Exported_Functions
+ *  @{
+ */
+
+/** @addtogroup FMC_NORSRAM
+ *  @{
+ */
+
+/** @addtogroup FMC_NORSRAM_Group1
+ *  @{
+ */
+
+/* FMC_NORSRAM Controller functions ******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_NORSRAM_Group2
+ *  @{
+ */
+
+/* FMC_NORSRAM Control functions */
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_NAND
+ *  @{
+ */
+
+/* FMC_NAND Controller functions **********************************************/
+/* Initialization/de-initialization functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group1
+ *  @{
+ */
+
+HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/**
+  * @}
+  */
+
+/* FMC_NAND Control functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group2
+ *  @{
+ */
+
+HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_BANK1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c
new file mode 100755
index 0000000..ea68657
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c
@@ -0,0 +1,311 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_gpio.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   GPIO LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_gpio.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
+
+/** @addtogroup GPIO_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  * @param  GPIOx GPIO Port
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are de-initialized
+  *          - ERROR:   Wrong GPIO Port
+  */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Force and Release reset on clock of GPIOx Port */
+  if (GPIOx == GPIOA)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC);
+  }
+#if defined(GPIOD)
+  else if (GPIOx == GPIOD)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD);
+  }
+#endif /* GPIOD */
+#if defined(GPIOE)
+  else if (GPIOx == GPIOE)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE);
+  }
+#endif /* GPIOE */
+#if defined(GPIOF)
+  else if (GPIOx == GPIOF)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF);
+  }
+#endif /* GPIOF */
+#if defined(GPIOG)
+  else if (GPIOx == GPIOG)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG);
+  }
+#endif /* GPIOG */
+#if defined(GPIOH)
+  else if (GPIOx == GPIOH)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH);
+  }
+#endif /* GPIOH */
+#if defined(GPIOI)
+  else if (GPIOx == GPIOI)
+  {
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOI);
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI);
+  }
+#endif /* GPIOI */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+  * @param  GPIOx GPIO Port
+  * @param  GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+  *         that contains the configuration information for the specified GPIO peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  uint32_t pinpos     = 0x00000000U;
+  uint32_t currentpin = 0x00000000U;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /* Initialize  pinpos on first pin set */
+  pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+  /* Configure the port pins */
+  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+  {
+    /* Get current io position */
+    currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+
+    if (currentpin)
+    {
+      /* Pin Mode configuration */
+      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+        /* Speed mode configuration */
+        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+      {
+        /* Check Alternate parameter */
+        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+        /* Speed mode configuration */
+        if (POSITION_VAL(currentpin) < 0x00000008U)
+        {
+          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+        else
+        {
+          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+      }
+    }
+    pinpos++;
+  }
+
+  if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+  {
+    /* Check Output mode parameters */
+    assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+    /* Output mode configuration*/
+    LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+  }
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+  * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h
new file mode 100755
index 0000000..0b0a307
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h
@@ -0,0 +1,1066 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_GPIO_H
+#define __STM32L4xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
+                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
+                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
+                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+                                           GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER,
+                             (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
+             (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+                             (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+                             (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+             (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+#if defined(GPIO_ASCR_ASC0)
+/**
+  * @brief  Connect analog switch to ADC input of several pins for a dedicated port.
+  * @note   This bit must be set prior to the ADC conversion.
+  *         Only the IO which connected to the ADC input are effective.
+  *         Other IO must be kept reset value
+  * @rmtoll ASCR         ASCy          LL_GPIO_EnablePinAnalogControl
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_EnablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  SET_BIT(GPIOx->ASCR, PinMask);
+}
+
+/**
+  * @brief  Disconnect analog switch to ADC input of several pins for a dedicated port.
+  * @rmtoll ASCR         ASCy          LL_GPIO_DisablePinAnalogControl
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_DisablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  CLEAR_BIT(GPIOx->ASCR, PinMask);
+}
+#endif /* GPIO_ASCR_ASC0 */
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c
new file mode 100755
index 0000000..123155a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c
@@ -0,0 +1,265 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_i2c.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   I2C LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_i2c.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
+                                                 ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the I2C registers to their default reset values.
+  * @param  I2Cx I2C Instance.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are de-initialized
+  *          - ERROR: I2C registers are not de-initialized
+  */
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+  }
+#if defined(I2C2)
+  else if (I2Cx == I2C2)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+  }
+#endif
+  else if (I2Cx == I2C3)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
+  }
+#if defined(I2C4)
+  else if (I2Cx == I2C4)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_I2C4);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C4);
+  }
+#endif
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+  * @param  I2Cx I2C Instance.
+  * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are initialized
+  *          - ERROR: Not applicable
+  */
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  /* Check the I2C parameters from I2C_InitStruct */
+  assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+  assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+  assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+  assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+  assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+  assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+  /* Disable the selected I2Cx Peripheral */
+  LL_I2C_Disable(I2Cx);
+
+  /*---------------------------- I2Cx CR1 Configuration ------------------------
+   * Configure the analog and digital noise filters with parameters :
+   * - AnalogFilter: I2C_CR1_ANFOFF bit
+   * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+   */
+  LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+  /*---------------------------- I2Cx TIMINGR Configuration --------------------
+   * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+   * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+   *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+   */
+  LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+  /* Enable the selected I2Cx Peripheral */
+  LL_I2C_Enable(I2Cx);
+
+  /*---------------------------- I2Cx OAR1 Configuration -----------------------
+   * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+   * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
+   * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
+   */
+  LL_I2C_DisableOwnAddress1(I2Cx);
+  LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+  /* OwnAdress1 == 0 is reserved for General Call address */
+  if (I2C_InitStruct->OwnAddress1 != 0U)
+  {
+    LL_I2C_EnableOwnAddress1(I2Cx);
+  }
+
+  /*---------------------------- I2Cx MODE Configuration -----------------------
+  * Configure I2Cx peripheral mode with parameter :
+   * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+   */
+  LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+  /*---------------------------- I2Cx CR2 Configuration ------------------------
+   * Configure the ACKnowledge or Non ACKnowledge condition
+   * after the address receive match code or next received byte with parameter :
+   * - TypeAcknowledge: I2C_CR2_NACK bit
+   */
+  LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
+  * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval None
+  */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Set I2C_InitStruct fields to default values */
+  I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
+  I2C_InitStruct->Timing          = 0U;
+  I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
+  I2C_InitStruct->DigitalFilter   = 0U;
+  I2C_InitStruct->OwnAddress1     = 0U;
+  I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+  I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h
new file mode 100755
index 0000000..bcb7418
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h
@@ -0,0 +1,2246 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_i2c.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of I2C LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_I2C_H
+#define __STM32L4xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
+                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+
+  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+                                     This parameter must be set by referring to the STM32CubeMX Tool and
+                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
+
+  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+
+                                     This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
+                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+
+  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
+                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+
+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+
+  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
+  * @{
+  */
+#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
+#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
+#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
+#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
+#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
+#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
+#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
+#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
+  * @{
+  */
+#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
+#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
+#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
+#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
+#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
+#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
+#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
+#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
+#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
+#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
+#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
+#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
+#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
+  * @{
+  */
+#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
+#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
+#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
+#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
+#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
+#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+  * @{
+  */
+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */
+#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+  * @{
+  */
+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
+#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+  * @{
+  */
+#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+  * @{
+  */
+#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+  * @{
+  */
+#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
+#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
+#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+  * @{
+  */
+#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+  * @{
+  */
+#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+  * @{
+  */
+#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+  * @{
+  */
+#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
+#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
+#define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+  * @{
+  */
+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                  /*!< Don't Generate Stop and Start condition.                */
+#define LL_I2C_GENERATE_STOP                I2C_CR2_STOP                                                 /*!< Generate Stop condition (Size should be set to 0).      */
+#define LL_I2C_GENERATE_START_READ          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
+#define LL_I2C_GENERATE_START_WRITE         I2C_CR2_START                                                /*!< Generate Start for write request.                       */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  I2C_CR2_START                                                /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START                                                /*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+  * @{
+  */
+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */
+#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
+#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
+#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+  * @{
+  */
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
+  * @param  __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+  * @param  __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+  * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+  * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
+        ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
+         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
+         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
+         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
+         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C peripheral (PE = 1).
+  * @rmtoll CR1          PE            LL_I2C_Enable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Disable I2C peripheral (PE = 0).
+  * @note   When PE = 0, the I2C SCL and SDA lines are released.
+  *         Internal state machines and status bits are put back to their reset value.
+  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
+  * @rmtoll CR1          PE            LL_I2C_Disable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Check if the I2C peripheral is enabled or disabled.
+  * @rmtoll CR1          PE            LL_I2C_IsEnabled
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+}
+
+/**
+  * @brief  Configure Noise Filters (Analog and Digital).
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         The filters can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
+  *         CR1          DNF           LL_I2C_ConfigFilters
+  * @param  I2Cx I2C Instance.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+  * @brief  Configure Digital Noise Filter.
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Get the current Digital Noise Filter configuration.
+  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Enable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Disable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Check if Analog Noise Filter is enabled or disabled.
+  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
+}
+
+/**
+  * @brief  Enable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA transmission requests are enabled or disabled.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
+}
+
+/**
+  * @brief  Enable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA reception requests are enabled or disabled.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
+  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
+  * @param  I2Cx I2C Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr = 0U;
+
+  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TXDR register */
+    data_reg_addr = (uint32_t) & (I2Cx->TXDR);
+  }
+  else
+  {
+    /* return address of RXDR register */
+    data_reg_addr = (uint32_t) & (I2Cx->RXDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @brief  Enable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Disable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Check if Clock stretching is enabled or disabled.
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+}
+
+/**
+  * @brief  Enable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Disable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
+  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
+}
+
+/**
+  * @brief  Enable Wakeup from STOP.
+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when Digital Filter is disabled.
+  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Disable Wakeup from STOP.
+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Check if Wakeup from STOP is enabled or disabled.
+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
+}
+
+/**
+  * @brief  Enable General Call.
+  * @note   When enabled the Address 0x00 is ACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Disable General Call.
+  * @note   When disabled the Address 0x00 is NACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Check if General Call is enabled or disabled.
+  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
+}
+
+/**
+  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
+  * @note   Changing this bit is not allowed, when the START bit is set.
+  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @param  AddressingMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+  * @brief  Get the Master addressing mode.
+  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+  * @brief  Set the Own Address1.
+  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
+  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+  * @param  OwnAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
+  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Disable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
+}
+
+/**
+  * @brief  Set the 7bits Own Address2.
+  * @note   This action has no effect if own address2 is enabled.
+  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
+  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+  * @param  OwnAddrMask This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Disable  acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
+}
+
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
+  * @param  I2Cx I2C Instance.
+  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+  WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+  * @brief  Get the Timing Prescaler setting.
+  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+  * @brief  Get the SCL low period setting.
+  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+  * @brief  Get the SCL high period setting.
+  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+  * @brief  Get the SDA hold time.
+  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+  * @brief  Get the SDA setup time.
+  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+  * @brief  Configure peripheral mode.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
+  *         CR1          SMBDEN        LL_I2C_SetMode
+  * @param  I2Cx I2C Instance.
+  * @param  PeripheralMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+  * @brief  Get peripheral mode.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
+  *         CR1          SMBDEN        LL_I2C_GetMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+  * @brief  Enable SMBus alert (Host or Device mode)
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is drived low and
+  *           Alert Response Address Header acknowledge is enabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Disable SMBus alert (Host or Device mode)
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+  *           Alert Response Address Header acknowledge is disabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is not supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
+}
+
+/**
+  * @brief  Enable SMBus Packet Error Calculation (PEC).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Disable SMBus Packet Error Calculation (PEC).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
+}
+
+/**
+  * @brief  Configure the SMBus Clock Timeout.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @param  TimeoutB
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+                                               uint32_t TimeoutB)
+{
+  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA setting.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+  * @brief  Set the SMBus Clock TimeoutA mode.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA mode.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutB is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Enable the SMBus Clock Timeout.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Disable the SMBus Clock Timeout.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Disable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Check if the TXIS Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
+}
+
+/**
+  * @brief  Enable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Disable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Check if the RXNE Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
+}
+
+/**
+  * @brief  Enable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Disable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Check if Address match interrupt is enabled or disabled.
+  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
+}
+
+/**
+  * @brief  Enable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Disable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
+  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
+}
+
+/**
+  * @brief  Enable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Disable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Check if STOP detection interrupt is enabled or disabled.
+  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
+}
+
+/**
+  * @brief  Enable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
+}
+
+/**
+  * @brief  Enable Error interrupts.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Disable Error interrupts.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Check if Error interrupts are enabled or disabled.
+  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Indicate the status of Transmit data register empty flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
+}
+
+/**
+  * @brief  Indicate the status of Transmit interrupt flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
+}
+
+/**
+  * @brief  Indicate the status of Receive data register not empty flag.
+  * @note   RESET: When Receive data register is read.
+  *         SET: When the received data is copied in Receive data register.
+  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
+}
+
+/**
+  * @brief  Indicate the status of Address matched flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When the received slave address matched with one of the enabled slave address.
+  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
+}
+
+/**
+  * @brief  Indicate the status of Not Acknowledge received flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a NACK is received after a byte transmission.
+  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
+}
+
+/**
+  * @brief  Indicate the status of Stop detection flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Stop condition is detected.
+  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=1 and NBYTES date have been transferred.
+  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
+}
+
+/**
+  * @brief  Indicate the status of Bus error flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a misplaced Start or Stop condition is detected.
+  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
+}
+
+/**
+  * @brief  Indicate the status of Arbitration lost flag.
+  * @note   RESET: Clear default value.
+  *         SET: When arbitration lost.
+  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
+}
+
+/**
+  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
+}
+
+/**
+  * @brief  Indicate the status of SMBus PEC error flag in reception.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When the received PEC does not match with the PEC register content.
+  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
+}
+
+/**
+  * @brief  Indicate the status of SMBus Timeout detection flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When a timeout or extended clock timeout occurs.
+  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
+}
+
+/**
+  * @brief  Indicate the status of SMBus alert flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When SMBus host configuration, SMBus alert enabled and
+  *              a falling edge event occurs on SMBA pin.
+  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
+}
+
+/**
+  * @brief  Indicate the status of Bus Busy flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Start condition is detected.
+  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
+}
+
+/**
+  * @brief  Clear Address Matched flag.
+  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+  * @brief  Clear Not Acknowledge flag.
+  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+  * @brief  Clear Stop detection flag.
+  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+  * @brief  Clear Transmit data register empty flag (TXE).
+  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
+  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+  * @brief  Clear Bus error flag.
+  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+  * @brief  Clear Arbitration lost flag.
+  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+  * @brief  Clear Overrun/Underrun flag.
+  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+  * @brief  Clear SMBus PEC error flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+  * @brief  Clear SMBus Timeout detection flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+  * @brief  Clear SMBus Alert flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable automatic STOP condition generation (master mode).
+  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+  *         This bit has no effect in slave mode or when RELOAD bit is set.
+  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Disable automatic STOP condition generation (master mode).
+  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Check if automatic STOP condition is enabled or disabled.
+  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
+}
+
+/**
+  * @brief  Enable reload mode (master mode).
+  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Disable reload mode (master mode).
+  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Check if reload mode is enabled or disabled.
+  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
+}
+
+/**
+  * @brief  Configure the number of bytes for transfer.
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Get the number of bytes configured for transfer.
+  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+  * @note   Usage in Slave mode only.
+  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
+  * @param  I2Cx I2C Instance.
+  * @param  TypeAcknowledge This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ACK
+  *         @arg @ref LL_I2C_NACK
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+  * @brief  Generate a START or RESTART condition
+  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
+  *         This action has no effect when RELOAD is set.
+  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+  * @brief  Generate a STOP condition after the current byte transfer (master mode).
+  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master sends the complete 10bit slave address read sequence :
+  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
+}
+
+/**
+  * @brief  Configure the transfer direction (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @param  TransferRequest This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+  * @brief  Get the transfer direction requested (master mode).
+  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+  * @brief  Configure the slave address for transfer (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+  * @brief  Get the slave address programmed for transfer.
+  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
+  *         CR2          ADD10         LL_I2C_HandleTransfer\n
+  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
+  *         CR2          START         LL_I2C_HandleTransfer\n
+  *         CR2          STOP          LL_I2C_HandleTransfer\n
+  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
+  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
+  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
+  *         CR2          HEAD10R       LL_I2C_HandleTransfer
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr Specifies the slave address to be programmed.
+  * @param  SlaveAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
+  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
+  * @param  TransferSize Specifies the number of bytes to be programmed.
+  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
+  * @param  EndMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_RELOAD
+  *         @arg @ref LL_I2C_MODE_AUTOEND
+  *         @arg @ref LL_I2C_MODE_SOFTEND
+  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+  *         @arg @ref LL_I2C_GENERATE_STOP
+  *         @arg @ref LL_I2C_GENERATE_START_READ
+  *         @arg @ref LL_I2C_GENERATE_START_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+             SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
+}
+
+/**
+  * @brief  Indicate the value of transfer direction (slave mode).
+  * @note   RESET: Write transfer, Slave enters in receiver mode.
+  *         SET: Read transfer, Slave enters in transmitter mode.
+  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_DIRECTION_WRITE
+  *         @arg @ref LL_I2C_DIRECTION_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+  * @brief  Return the slave matched address.
+  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+  *         This bit has no effect when RELOAD bit is set.
+  *         This bit has no effect in device mode when SBC bit is not set.
+  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
+}
+
+/**
+  * @brief  Get the SMBus Packet Error byte calculated.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+*/
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+  * @brief  Read Receive Data register.
+  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+  * @brief  Write in Transmit Data Register .
+  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
+  * @param  I2Cx I2C Instance.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+  WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h
new file mode 100755
index 0000000..d691da4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h
@@ -0,0 +1,363 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IWDG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_IWDG_H
+#define __STM32L4xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
+#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
+  * @{
+  */
+#define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
+#define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
+  * @{
+  */
+#define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
+#define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
+#define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
+#define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
+#define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
+#define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+  * @{
+  */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Start the Independent Watchdog
+  * @note   Except if the hardware watchdog option is selected
+  * @rmtoll KR           KEY           LL_IWDG_Enable
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+  * @brief  Select the prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_SetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+  WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+  * @brief  Get the selected prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_GetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->PR));
+}
+
+/**
+  * @brief  Specify the IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+  WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+  * @brief  Get the specified IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->RLR));
+}
+
+/**
+  * @brief  Specify high limit of the window value to be compared to the down-counter.
+  * @rmtoll WINR         WIN           LL_IWDG_SetWindow
+  * @param  IWDGx IWDG Instance
+  * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
+{
+  WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+  * @brief  Get the high limit of the window value specified.
+  * @rmtoll WINR         WIN           LL_IWDG_GetWindow
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->WINR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if flag Prescaler Value Update is set or not
+  * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+}
+
+/**
+  * @brief  Check if flag Reload Value Update is set or not
+  * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+}
+
+/**
+  * @brief  Check if flag Window Value Update is set or not
+  * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
+}
+
+/**
+  * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
+  * @rmtoll SR           PVU           LL_IWDG_IsReady\n
+  *         SR           WVU           LL_IWDG_IsReady\n
+  *         SR           RVU           LL_IWDG_IsReady
+  * @param  IWDGx IWDG Instance
+  * @retval State of bits (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* IWDG) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c
new file mode 100755
index 0000000..5eef8c6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c
@@ -0,0 +1,212 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_lptim.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   LPTIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_lptim.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPTIM1) || defined (LPTIM2)
+
+/** @addtogroup LPTIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+                                       || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+                                   || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
+                                          || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPTIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set LPTIMx registers to their reset values.
+  * @param  LPTIMx LP Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx registers are de-initialized
+  *          - ERROR: invalid LPTIMx instance
+  */
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx)); 
+ 
+  if (LPTIMx == LPTIM1)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);  
+  } 
+#if defined(LPTIM2)
+  else if (LPTIMx == LPTIM2)
+  { 
+    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+  }
+#endif
+  else
+  {
+    result = ERROR;
+  }
+  
+  return result;
+}
+
+/**
+  * @brief  Set each fields of the LPTIM_InitStruct structure to its default
+  *         value.
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval None
+  */
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+  /* Set the default configuration */
+  LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
+  LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
+  LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
+  LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+  * @brief  Configure the LPTIMx peripheral according to the specified parameters.
+  * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
+  * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
+  * @param  LPTIMx LP Timer Instance
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx instance has been initialized
+  *          - ERROR: LPTIMx instance hasn't been initialized
+  */
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+  ErrorStatus result = SUCCESS;
+  
+  /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled 
+     (ENABLE bit is reset to 0).
+  */
+  if (LL_LPTIM_IsEnabled(LPTIMx))
+  {
+    result = ERROR;
+  }
+  else
+  {
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx)); 
+  assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+  assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+  assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+  
+  /* Set CKSEL bitfield according to ClockSource value */
+  /* Set PRESC bitfield according to Prescaler value */
+  /* Set WAVE bitfield according to Waveform value */
+  /* Set WAVEPOL bitfield according to Polarity value */
+  MODIFY_REG(LPTIMx->CFGR, 
+             (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), 
+             LPTIM_InitStruct->ClockSource | \
+             LPTIM_InitStruct->Prescaler | \
+             LPTIM_InitStruct->Waveform | \
+             LPTIM_InitStruct->Polarity);
+  }
+
+  return result;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (LPTIM1) || defined (LPTIM2) */
+
+/**
+  * @}
+  */
+  
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h
new file mode 100755
index 0000000..3edb395
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h
@@ -0,0 +1,1431 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_lptim.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of LPTIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_LPTIM_H
+#define __STM32L4xx_LL_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+#if defined (LPTIM1) || defined (LPTIM2)
+	
+/** @defgroup LPTIM_LL LPTIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  LPTIM Init structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
+                                This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
+
+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
+
+  uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
+                                This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
+
+                                This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
+
+  uint32_t Waveform;       /*!< Specifies the waveform shape.
+                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
+
+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+
+  uint32_t Polarity;       /*!< Specifies waveform polarity.
+                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
+
+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+} LL_LPTIM_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
+  * @{
+  */
+#define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
+#define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
+#define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
+#define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
+#define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
+#define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
+#define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
+  * @{
+  */
+#define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE       /*!< Compare match Interrupt Enable */
+#define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE       /*!< Autoreload match Interrupt Enable */
+#define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE    /*!< External trigger valid edge Interrupt Enable */
+#define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE      /*!< Compare register update OK Interrupt Enable */
+#define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE      /*!< Autoreload register update OK Interrupt Enable */
+#define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE         /*!< Direction change to UP Interrupt Enable */
+#define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE       /*!< Direction change to down Interrupt Enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
+  * @{
+  */
+#define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT       /*!<LP Timer starts in continuous mode*/
+#define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT       /*!<LP Tilmer starts in single mode*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
+  * @{
+  */
+#define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U             /*!<Preload is disabled: registers are updated after each APB bus write access*/
+#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD      /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
+  * @{
+  */
+#define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U             /*!<The counter is incremented following each internal clock pulse*/
+#define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE    /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
+  * @{
+  */
+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U             /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE         /*!<LPTIM  generates a Set Once waveform*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
+  * @{
+  */
+#define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U              /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+#define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL        /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
+  * @{
+  */
+#define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
+#define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
+#define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
+#define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
+#define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
+#define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
+#define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
+#define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
+  * @{
+  */
+#define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                   /*!<External input trigger is connected to TIMx_ETR input*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                          /*!<External input trigger is connected to RTC Alarm A*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                          /*!<External input trigger is connected to RTC Alarm B*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                          /*!<External input trigger is connected to RTC Tamper 2*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
+#define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
+#define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                            /*!<External input trigger is connected to COMP2 output*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
+  * @{
+  */
+#define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U             /*!<Any trigger active level change is considered as a valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0     /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1     /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT       /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
+  * @{
+  */
+#define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0    /*!<LPTIM counter starts when a rising edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1    /*!<LPTIM counter starts when a falling edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN      /*!<LPTIM counter starts when a rising or a falling edge is detected*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
+  * @{
+  */
+#define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U             /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
+#define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL        /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
+  * @{
+  */
+#define LL_LPTIM_CLK_FILTER_NONE              0x00000000U             /*!<Any external clock signal level change is considered as a valid transition*/
+#define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0      /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1      /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT        /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U             /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0      /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1      /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
+  * @{
+  */
+#define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U             /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0      /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1      /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
+  * @{
+  */
+#define LL_LPTIM_INPUT1_SRC_GPIO         0x00000000U             /*!< For LPTIM1 and LPTIM2 */
+#define LL_LPTIM_INPUT1_SRC_COMP1        LPTIM_OR_OR_0           /*!< For LPTIM1 and LPTIM2 */
+#define LL_LPTIM_INPUT1_SRC_COMP2        LPTIM_OR_OR_1           /*!< For LPTIM2 */
+#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2  LPTIM_OR_OR             /*!< For LPTIM2 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
+  * @{
+  */
+#define LL_LPTIM_INPUT2_SRC_GPIO         0x00000000U             /*!< For LPTIM1 */
+#define LL_LPTIM_INPUT2_SRC_COMP2        LPTIM_OR_OR_1           /*!< For LPTIM1 */
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the LPTIM instance
+  * @note After setting the ENABLE bit, a delay of two counter clock is needed
+  *       before the LPTIM instance is actually enabled.
+  * @rmtoll CR           ENABLE        LL_LPTIM_Enable
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+  * @brief  Disable the LPTIM instance
+  * @rmtoll CR           ENABLE        LL_LPTIM_Disable
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM instance is enabled.
+  * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
+}
+
+/**
+  * @brief  Starts the LPTIM counter in the desired mode.
+  * @note LPTIM instance must be enabled before starting the counter.
+  * @note It is possible to change on the fly from One Shot mode to
+  *       Continuous mode.
+  * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
+  *         CR           SNGSTRT       LL_LPTIM_StartCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  OperatingMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
+  *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
+{
+  MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
+}
+
+
+/**
+  * @brief  Set the LPTIM registers update mode (enable/disable register preload)
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  UpdateMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
+}
+
+/**
+  * @brief  Get the LPTIM registers update mode
+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
+}
+
+/**
+  * @brief  Set the auto reload value
+  * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+  * @note After a write to the LPTIMx_ARR register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before  the ARROK flag be set, will
+  *       lead to unpredictable results.
+  * @note autoreload value be strictly greater than the compare value.
+  * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
+{
+  MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
+}
+
+/**
+  * @brief  Get actual auto reload value
+  * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
+}
+
+/**
+  * @brief  Set the compare value
+  * @note After a write to the LPTIMx_CMP register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before the CMPOK flag be set, will
+  *       lead to unpredictable results.
+  * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value
+  * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
+}
+
+/**
+  * @brief  Get actual counter value
+  * @note When the LPTIM instance is running with an asynchronous clock, reading
+  *       the LPTIMx_CNT register may return unreliable values. So in this case
+  *       it is necessary to perform two consecutive read accesses and verify
+  *       that the two returned values are identical.
+  * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Counter value
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
+}
+
+/**
+  * @brief  Set the counter mode (selection of the LPTIM counter clock source).
+  * @note The counter mode can be set only when the LPTIM instance is disabled.
+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
+}
+
+/**
+  * @brief  Get the counter mode
+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
+}
+
+/**
+  * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note Regarding the LPTIM output polarity the change takes effect
+  *       immediately, so the output default value will change immediately after
+  *       the polarity is re-configured, even before the timer is enabled.
+  * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
+  *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Waveform This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
+}
+
+/**
+  * @brief  Set  waveform shape
+  * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Waveform This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
+}
+
+/**
+  * @brief  Get actual waveform shape
+  * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
+}
+
+/**
+  * @brief  Set  output polarity
+  * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
+}
+
+/**
+  * @brief  Get actual output polarity
+  * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
+}
+
+/**
+  * @brief  Set actual prescaler division ratio.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When the LPTIM is configured to be clocked by an internal clock source
+  *       and the LPTIM counter is configured to be updated by active edges
+  *       detected on the LPTIM external Input1, the internal clock provided to
+  *       the LPTIM must be not be prescaled.
+  * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
+}
+
+/**
+  * @brief  Get actual prescaler division ratio.
+  * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
+}
+
+/**
+  * @brief  Set LPTIM input 1 source (default GPIO).
+  * @rmtoll OR         OR_0         LL_LPTIM_SetInput1Src
+  * @rmtoll OR         OR_1         LL_LPTIM_SetInput1Src
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Src This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
+  *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
+  *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
+  *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+  WRITE_REG(LPTIMx->OR, Src);
+}
+
+/**
+  * @brief  Set LPTIM input 2 source (default GPIO).
+  * @rmtoll OR         OR_0         LL_LPTIM_SetInput2Src
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Src This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
+  *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+  WRITE_REG(LPTIMx->OR, Src);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note The first trigger event will start the timer, any successive trigger
+  *       event will reset the counter and the timer will restart.
+  * @note The timeout value corresponds to the compare value; if no trigger
+  *       occurs within the expected time frame, the MCU is waked-up by the
+  *       compare match event.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+  * @brief  Disable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note A trigger event arriving when the timer is already started will be
+  *       ignored.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+  * @brief  Indicate whether the timeout function is enabled.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
+}
+
+/**
+  * @brief  Start the LPTIM counter
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
+}
+
+/**
+  * @brief  Configure the external trigger used as a trigger event for the LPTIM.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for the trigger.
+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
+  *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
+  *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
+}
+
+/**
+  * @brief  Get actual external trigger source.
+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
+}
+
+/**
+  * @brief  Get actual external trigger filter.
+  * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
+}
+
+/**
+  * @brief  Get actual external trigger polarity.
+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set the source of the clock used by the LPTIM instance.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
+}
+
+/**
+  * @brief  Get actual LPTIM instance clock source.
+  * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
+}
+
+/**
+  * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When both external clock signal edges are considered active ones,
+  *       the LPTIM must also be clocked by an internal clock source with a
+  *       frequency equal to at least four times the external clock frequency.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for external clock.
+  * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
+  *         CFGR         CKPOL         LL_LPTIM_ConfigClock
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockFilter This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LL_LPTIM_CLK_FILTER_2
+  *         @arg @ref LL_LPTIM_CLK_FILTER_4
+  *         @arg @ref LL_LPTIM_CLK_FILTER_8
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+  * @brief  Get actual clock polarity
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+  * @brief  Get actual clock digital filter
+  * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LL_LPTIM_CLK_FILTER_2
+  *         @arg @ref LL_LPTIM_CLK_FILTER_4
+  *         @arg @ref LL_LPTIM_CLK_FILTER_8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
+  * @{
+  */
+
+/**
+  * @brief  Configure the encoder mode.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
+}
+
+/**
+  * @brief  Get actual encoder mode.
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+  * @brief  Enable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note In this mode the LPTIM instance must be clocked by an internal clock
+  *       source. Also, the prescaler division ratio must be equal to 1.
+  * @note LPTIM instance must be configured in continuous mode prior enabling
+  *       the encoder mode.
+  * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+  * @brief  Disable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM operates in encoder mode.
+  * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear the compare match flag (CMPMCF)
+  * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
+}
+
+/**
+  * @brief  Inform application whether a compare match interrupt has occurred.
+  * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
+}
+
+/**
+  * @brief  Clear the autoreload match flag (ARRMCF)
+  * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
+}
+
+/**
+  * @brief  Inform application whether a autoreload match interrupt has occured.
+  * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
+}
+
+/**
+  * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
+  * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
+}
+
+/**
+  * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
+  * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
+}
+
+/**
+  * @brief  Clear the compare register update interrupt flag (CMPOKCF).
+  * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
+  * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
+}
+
+/**
+  * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
+  * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
+  * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
+}
+
+/**
+  * @brief  Clear the counter direction change to up interrupt flag (UPCF).
+  * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+  * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
+}
+
+/**
+  * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
+  * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+  * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable compare match interrupt (CMPMIE).
+  * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
+}
+
+/**
+  * @brief  Disable compare match interrupt (CMPMIE).
+  * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
+}
+
+/**
+  * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
+  * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
+}
+
+/**
+  * @brief  Enable autoreload match interrupt (ARRMIE).
+  * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
+}
+
+/**
+  * @brief  Disable autoreload match interrupt (ARRMIE).
+  * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+  * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
+}
+
+/**
+  * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
+}
+
+/**
+  * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
+}
+
+/**
+  * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
+}
+
+/**
+  * @brief  Enable compare register write completed interrupt (CMPOKIE).
+  * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
+}
+
+/**
+  * @brief  Disable compare register write completed interrupt (CMPOKIE).
+  * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
+}
+
+/**
+  * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
+  * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
+}
+
+/**
+  * @brief  Enable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll IER          ARROKIE       LL_LPTIM_EnableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
+}
+
+/**
+  * @brief  Disable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll IER          ARROKIE       LL_LPTIM_DisableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+  * @rmtoll IER          ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
+}
+
+/**
+  * @brief  Enable direction change to up interrupt (UPIE).
+  * @rmtoll IER          UPIE          LL_LPTIM_EnableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
+}
+
+/**
+  * @brief  Disable direction change to up interrupt (UPIE).
+  * @rmtoll IER          UPIE          LL_LPTIM_DisableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
+  * @rmtoll IER          UPIE          LL_LPTIM_IsEnabledIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
+}
+
+/**
+  * @brief  Enable direction change to down interrupt (DOWNIE).
+  * @rmtoll IER          DOWNIE        LL_LPTIM_EnableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
+}
+
+/**
+  * @brief  Disable direction change to down interrupt (DOWNIE).
+  * @rmtoll IER          DOWNIE        LL_LPTIM_DisableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+  * @rmtoll IER          DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPTIM1 || LPTIM2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c
new file mode 100755
index 0000000..7b1459a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c
@@ -0,0 +1,272 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_lpuart.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   LPUART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_lpuart.h"
+#include "stm32l4xx_ll_rcc.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @addtogroup LPUART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of LPUART registers                  */
+
+/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
+/*              value :                                                       */
+/*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
+/*                - LPUART_BRR register value should be >= 0x300              */
+/*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
+/*              Baudrate specified by the user should belong to [8, 26000000].*/
+#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U))
+
+/* __VALUE__ BRR content must be greater than or equal to 0x300. */
+#define IS_LL_LPUART_BRR(__VALUE__) ((__VALUE__) >= 0x300U)
+
+#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
+                                        || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
+                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
+                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
+
+#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
+                                     || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
+                                     || ((__VALUE__) == LL_LPUART_PARITY_ODD))
+
+#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
+                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
+                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
+
+#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
+                                       || ((__VALUE__) == LL_LPUART_STOPBITS_2))
+
+#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
+                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
+                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
+                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPUART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize LPUART registers (Registers restored to their default values).
+  * @param  LPUARTx LPUART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+
+  if (LPUARTx == LPUART1)
+  {
+    /* Force reset of LPUART peripheral */
+    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1);
+
+    /* Release reset of LPUART peripheral */
+    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize LPUART registers according to the specified
+  *         parameters in LPUART_InitStruct.
+  * @note   As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),
+  *         LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  LPUARTx LPUART Instance
+  * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *         that contains the configuration information for the specified LPUART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
+  *          - ERROR: Problem occurred during LPUART Registers initialization
+  */
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+  assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+  assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
+  assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
+  assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
+  assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
+  assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+  /* LPUART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
+  if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
+  {
+    /*---------------------------- LPUART CR1 Configuration -----------------------
+     * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
+     */
+    MODIFY_REG(LPUARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
+               (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
+
+    /*---------------------------- LPUART CR2 Configuration -----------------------
+     * Configure LPUARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
+     */
+    LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
+
+    /*---------------------------- LPUART CR3 Configuration -----------------------
+     * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.
+     */
+    LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- LPUART BRR Configuration -----------------------
+     * Retrieve Clock frequency used for LPUART Peripheral
+     */
+    periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+
+    /* Configure the LPUART Baud Rate :
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (LPUART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_LPUART_SetBaudRate(LPUARTx,
+                            periphclk,
+                            LPUART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 0x300 */
+      assert_param(IS_LL_LPUART_BRR(LPUARTx->BRR));
+    }
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
+  * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  /* Set LPUART_InitStruct fields to default values */
+  LPUART_InitStruct->BaudRate            = 9600U;
+  LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
+  LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
+  LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
+  LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
+  LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (LPUART1) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h
new file mode 100755
index 0000000..076c3bd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h
@@ -0,0 +1,2149 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_lpuart.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of LPUART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_LPUART_H
+#define __STM32L4xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+  * @{
+  */
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL     256U
+#define LPUART_BRR_MASK               0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE          0x00000300U
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL LPUART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
+  * @{
+  */
+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */
+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */
+#define LL_LPUART_ICR_NCF                  USART_ICR_NCF                 /*!< Noise detected flag */
+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */
+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */
+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */
+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */
+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */
+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
+  * @{
+  */
+#define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */
+#define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */
+#define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE                 USART_ISR_RXNE                /*!< Read data register not empty flag */
+#define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE                  USART_ISR_TXE                 /*!< Transmit data register empty flag */
+#define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */
+#define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */
+#define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
+  * @{
+  */
+#define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE               USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
+#define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE                USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
+#define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */
+#define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+  * @{
+  */
+#define LL_LPUART_DIRECTION_NONE           0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_LPUART_PARITY_NONE              0x00000000U                        /*!< Parity control disabled */
+#define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_LPUART_WAKEUP_IDLELINE          0x00000000U                        /*!<  LPUART wake up from Mute mode on Idle Line */
+#define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B             0x00000000U                        /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_LPUART_STOPBITS_1               0x00000000U                        /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_LPUART_TXRX_STANDARD            0x00000000U                        /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD     0x00000000U                        /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD     0x00000000U                        /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE    0x00000000U                        /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_LPUART_BITORDER_LSBFIRST        0x00000000U                        /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_LPUART_ADDRESS_DETECT_4B        0x00000000U                        /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_LPUART_HWCONTROL_NONE           0x00000000U                        /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_LPUART_WAKEUP_ON_ADDRESS        0x00000000U                             /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U                        /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U                       /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U                       /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+  * @param  __BAUDRATE__ Baud Rate value to achieve
+  * @retval LPUARTDIV value to be used for BRR register filling
+  */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  LPUART Enable
+  * @rmtoll CR1          UE            LL_LPUART_Enable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  LPUART Disable
+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
+  *         flags, in the LPUARTx_ISR are set to their default values.
+  * @note   In order to go into low-power mode without generating errors on the line,
+  *         the TE bit must be reset before and the software must wait
+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+  *         The DMA requests are also reset when UE = 0 so the DMA channel must
+  *         be disabled before resetting the UE bit.
+  * @rmtoll CR1          UE            LL_LPUART_Disable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled
+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+  * @brief  LPUART enabled in STOP Mode
+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+  *         LPUART clock selection is HSI or LSE in RCC.
+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  LPUART disabled in STOP Mode
+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled in STOP Mode
+  *         (able to wake up MCU from Stop mode or not)
+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
+  *         CR1          TE            LL_LPUART_SetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
+  *         CR1          TE            LL_LPUART_GetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
+  *         CR1          PCE           LL_LPUART_SetParity
+  * @param  LPUARTx LPUART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
+  *         CR1          PCE           LL_LPUART_GetParity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
+  *         CR1          M             LL_LPUART_ConfigCharacter\n
+  *         CR2          STOP          LL_LPUART_ConfigCharacter
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+                                               uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  *
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Set Address of the LPUART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
+  *
+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock and expected Baud Rate values
+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
+  *         (Baud rate value != 0).
+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+  *         a care should be taken when generating high baud rates using high PeriphClk
+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
+{
+  LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
+{
+  register uint32_t lpuartdiv = 0x0U;
+  register uint32_t brrresult = 0x0U;
+
+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+  {
+    brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+  }
+
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : c
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the LPUART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+}
+
+/**
+  * @brief  Check if the LPUART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+}
+
+/**
+  * @brief  Check if the LPUART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+}
+
+/**
+  * @brief  Check if the LPUART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+}
+
+/**
+  * @brief  Check if the LPUART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+}
+
+/**
+  * @brief  Check if the LPUART Read Data Register Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE          LL_LPUART_IsActiveFlag_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Data Register Empty Flag is set or not
+  * @rmtoll ISR          TXE           LL_LPUART_IsActiveFlag_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+}
+
+/**
+  * @brief  Check if the LPUART CTS interrupt Flag is set or not
+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+}
+
+/**
+  * @brief  Check if the LPUART CTS Flag is set or not
+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+}
+
+/**
+  * @brief  Check if the LPUART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+}
+
+/**
+  * @brief  Check if the LPUART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+}
+
+/**
+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+}
+
+/**
+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NCF           LL_LPUART_ClearFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Enable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_LPUART_EnableIT_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Enable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_LPUART_EnableIT_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Disable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_LPUART_DisableIT_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_LPUART_DisableIT_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+  * @brief  Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXNEIE        LL_LPUART_IsEnabledIT_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+  * @brief  Check if the LPUART TX Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXEIE         LL_LPUART_IsEnabledIT_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+}
+
+/**
+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+}
+
+/**
+  * @brief  Get the LPUART data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
+  * @param  LPUARTx LPUART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr = 0U;
+
+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
+{
+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
+{
+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+  LPUARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+  LPUARTx->TDR = Value & 0x1FFU;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put LPUART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data flush
+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_LPUART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c
new file mode 100755
index 0000000..49be22d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c
@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_opamp.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   OPAMP LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_opamp.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (OPAMP1) || defined (OPAMP2)
+
+/** @addtogroup OPAMP_LL OPAMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup OPAMP_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of OPAMP hierarchical scope:         */
+/* OPAMP instance.                                                            */
+
+#define IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)                                 \
+  (   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMAL)                          \
+   || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER))
+
+#define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)                       \
+  (   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
+   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
+   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
+  )
+
+/* Note: Comparator non-inverting inputs parameters are the same on all       */
+/*       OPAMP instances.                                                     */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__)     \
+  (   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
+   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1)             \
+  )
+
+/* Note: Comparator non-inverting inputs parameters are the same on all       */
+/*       OPAMP instances.                                                     */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__)           \
+  (   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
+   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
+   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMP_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup OPAMP_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of the selected OPAMP instance
+  *         to their default reset values.
+  * @param  OPAMPx OPAMP instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: OPAMP registers are de-initialized
+  *          - ERROR: OPAMP registers are not de-initialized
+  */
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+  
+  LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
+
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of OPAMP instance.
+  * @note   This function reset bit of calibration mode to ensure
+  *         to be in functional mode, in order to have OPAMP parameters
+  *         (inputs selection, ...) set with the corresponding OPAMP mode
+  *         to be effective.
+  * @note   This function configures features of the selected OPAMP instance.
+  *         Some features are also available at scope OPAMP common instance
+  *         (common to several OPAMP instances).
+  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
+  * @param  OPAMPx OPAMP instance
+  * @param  OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: OPAMP registers are initialized
+  *          - ERROR: OPAMP registers are not initialized
+  */
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+  assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode));
+  assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
+  assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
+  
+  /* Note: OPAMP inverting input can be used with OPAMP in mode standalone    */
+  /*       or PGA with external capacitors for filtering circuit.             */
+  /*       Otherwise (OPAMP in mode follower), OPAMP inverting input is       */
+  /*       not used (not connected to GPIO pin).                              */
+  if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+  {
+    assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
+  }
+  
+  /* Configuration of OPAMP instance :                                        */
+  /*  - PowerMode                                                             */
+  /*  - Functional mode                                                       */
+  /*  - Input non-inverting                                                   */
+  /*  - Input inverting                                                       */
+  /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode.      */
+  if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+  {
+    MODIFY_REG(OPAMPx->CSR,
+                 OPAMP_CSR_OPALPM
+               | OPAMP_CSR_OPAMODE
+               | OPAMP_CSR_CALON
+               | OPAMP_CSR_VMSEL
+               | OPAMP_CSR_VPSEL
+              ,
+                 (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
+               | OPAMP_InitStruct->FunctionalMode
+               | OPAMP_InitStruct->InputNonInverting
+               | OPAMP_InitStruct->InputInverting
+              );
+  }
+  else
+  {
+    MODIFY_REG(OPAMPx->CSR,
+                 OPAMP_CSR_OPALPM
+               | OPAMP_CSR_OPAMODE
+               | OPAMP_CSR_CALON
+               | OPAMP_CSR_VMSEL
+               | OPAMP_CSR_VPSEL
+              ,
+                 (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
+               | LL_OPAMP_MODE_FOLLOWER
+               | OPAMP_InitStruct->InputNonInverting
+               | LL_OPAMP_INPUT_INVERT_CONNECT_NO
+              );
+  }
+  
+  return SUCCESS;
+}
+
+/**
+  * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
+  * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+  /* Set OPAMP_InitStruct fields to default values */
+  OPAMP_InitStruct->PowerMode         = LL_OPAMP_POWERMODE_NORMAL;
+  OPAMP_InitStruct->FunctionalMode    = LL_OPAMP_MODE_FOLLOWER;
+  OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
+  /* Note: Parameter discarded if OPAMP in functional mode follower,          */
+  /*       set anyway to its default value.                                   */
+  OPAMP_InitStruct->InputInverting    = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* OPAMP1 || OPAMP2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h
new file mode 100755
index 0000000..22ee05d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h
@@ -0,0 +1,885 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_opamp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of OPAMP LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_OPAMP_H
+#define __STM32L4xx_LL_OPAMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (OPAMP1) || defined (OPAMP2)
+
+/** @defgroup OPAMP_LL OPAMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
+  * @{
+  */
+
+/* Internal mask for OPAMP power mode:                                        */
+/* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for:         */
+/* - OPAMP power mode into control register                                   */
+/* - OPAMP trimming register offset                                           */
+
+/* Internal register offset for OPAMP trimming configuration */
+#define OPAMP_POWERMODE_OTR_REGOFFSET       ((uint32_t)0x00000000U)
+#define OPAMP_POWERMODE_LPOTR_REGOFFSET     ((uint32_t)0x00000001U)
+#define OPAMP_POWERMODE_OTR_REGOFFSET_MASK  (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
+
+/* Mask for OPAMP power mode into control register */
+#define OPAMP_POWERMODE_CSR_BIT_MASK        (OPAMP_CSR_OPALPM)
+
+/* Internal mask for OPAMP trimming of transistors differential pair NMOS     */
+/* or PMOS.                                                                   */
+/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */
+/* - OPAMP trimming selection of transistors differential pair                */
+/* - OPAMP trimming values of transistors differential pair                   */
+#define OPAMP_TRIMMING_SELECT_MASK          (OPAMP1_CSR_CALSEL)
+#define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Register address
+*/
+#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__)                        \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
+
+
+
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of OPAMP instance.
+  */
+typedef struct
+{
+  uint32_t PowerMode;                   /*!< Set OPAMP power mode.
+                                             This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */
+
+  uint32_t FunctionalMode;              /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
+                                             This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
+                                             @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
+
+  uint32_t InputNonInverting;           /*!< Set OPAMP input non-inverting connection.
+                                             This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
+
+  uint32_t InputInverting;              /*!< Set OPAMP inverting input connection.
+                                             This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
+                                             @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
+
+} LL_OPAMP_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
+  * @{
+  */
+
+/** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range
+  * @{
+  */
+#define LL_OPAMP_POWERSUPPLY_RANGE_LOW  ((uint32_t)0x00000000U) /*!< Power supply range low. On STM32L4 serie: Vdda lower than 2.4V. */
+#define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE)   /*!< Power supply range high. On STM32L4 serie: Vdda higher than 2.4V. */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode
+  * @{
+  */
+#define LL_OPAMP_POWERMODE_NORMAL       (OPAMP_POWERMODE_OTR_REGOFFSET)                      /*!< OPAMP power mode normal */
+#define LL_OPAMP_POWERMODE_LOWPOWER     (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPALPM) /*!< OPAMP power mode low-power */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
+  * @{
+  */
+#define LL_OPAMP_MODE_FUNCTIONAL        ((uint32_t)0x00000000U)                     /*!< OPAMP functional mode */
+#define LL_OPAMP_MODE_CALIBRATION       (OPAMP_CSR_CALON)                           /*!< OPAMP calibration mode */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
+  * @{
+  */
+#define LL_OPAMP_MODE_STANDALONE        ((uint32_t)0x00000000U)                     /*!< OPAMP functional mode, OPAMP operation in standalone */
+#define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0) /*!< OPAMP functional mode, OPAMP operation in follower */
+#define LL_OPAMP_MODE_PGA               (OPAMP_CSR_OPAMODE_1)                       /*!< OPAMP functional mode, OPAMP operation in PGA */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
+  * @{
+  */
+#define LL_OPAMP_PGA_GAIN_2             ((uint32_t)0x00000000U)                    /*!< OPAMP PGA gain 2 */
+#define LL_OPAMP_PGA_GAIN_4             (OPAMP_CSR_PGGAIN_0)                       /*!< OPAMP PGA gain 4 */
+#define LL_OPAMP_PGA_GAIN_8             (OPAMP_CSR_PGGAIN_1)                       /*!< OPAMP PGA gain 8 */
+#define LL_OPAMP_PGA_GAIN_16            (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
+  * @{
+  */
+#define LL_OPAMP_INPUT_NONINVERT_IO0      ((uint32_t)0x00000000U) /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH1    (OPAMP1_CSR_VPSEL)      /*!< OPAMP non inverting input connected to DAC1 channel1 output */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
+  * @{
+  */
+#define LL_OPAMP_INPUT_INVERT_IO0        ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_IO1        (OPAMP_CSR_VMSEL_0)     /*!< OPAMP inverting input (low leakage input) connected to GPIO pin (available only on package BGA132). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1)     /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering) */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_INPUT_LEGACY OPAMP inputs legacy literals name
+  * @{
+  */
+#define LL_OPAMP_NONINVERTINGINPUT_IO0      LL_OPAMP_INPUT_NONINVERT_IO0
+#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH   LL_OPAMP_INPUT_NONINV_DAC1_CH1
+
+#define LL_OPAMP_INVERTINGINPUT_IO0         LL_OPAMP_INPUT_INVERT_IO0
+#define LL_OPAMP_INVERTINGINPUT_IO1         LL_OPAMP_INPUT_INVERT_IO1
+#define LL_OPAMP_INVERTINGINPUT_CONNECT_NO  LL_OPAMP_INPUT_INVERT_CONNECT_NO
+
+#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1   LL_OPAMP_INPUT_NONINV_DAC1_CH1
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
+  * @{
+  */
+#define LL_OPAMP_TRIMMING_FACTORY       ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */
+#define LL_OPAMP_TRIMMING_USER          (OPAMP_CSR_USERTRIM)    /*!< OPAMP trimming factors set to user values */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
+  * @{
+  */
+#define LL_OPAMP_TRIMMING_NMOS          (OPAMP_OTR_TRIMOFFSETN)                     /*!< OPAMP trimming of transistors differential pair NMOS */
+#define LL_OPAMP_TRIMMING_PMOS          (OPAMP_OTR_TRIMOFFSETP | OPAMP1_CSR_CALSEL) /*!< OPAMP trimming of transistors differential pair PMOS */
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EC_HW_DELAYS  Definitions of OPAMP hardware constraints delays
+  * @note   Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for OPAMP startup time (transition from state disable to enable).    */
+/* Note: OPAMP startup time depends on board application environment:         */
+/*       impedance connected to OPAMP output.                                 */
+/*       The delay below is specified under conditions:                       */
+/*        - OPAMP in mode low power                                           */
+/*        - OPAMP in functional mode follower                                 */
+/*        - load impedance of 4kOhm (min), 50pF (max)                         */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tWAKEUP").                                                      */
+/* Unit: us                                                                   */
+#define LL_OPAMP_DELAY_STARTUP_US         ((uint32_t) 30U)  /*!< Delay for OPAMP startup time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
+  * @{
+  */
+/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
+  * @{
+  */
+/**
+  * @brief  Write a value in OPAMP register
+  * @param  __INSTANCE__ OPAMP Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in OPAMP register
+  * @param  __INSTANCE__ OPAMP Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EM_HELPER_MACRO OPAMP helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to select the OPAMP common instance
+  *         to which is belonging the selected OPAMP instance.
+  * @note   OPAMP common register instance can be used to
+  *         set parameters common to several OPAMP instances.
+  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
+  * @param  __OPAMPx__ OPAMP instance
+  * @retval OPAMP common instance
+  */
+#if defined(OPAMP1) && defined(OPAMP2)
+#define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \
+  (OPAMP12_COMMON)
+#else
+#define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \
+  (OPAMP1_COMMON)
+#endif
+
+/**
+  * @brief  Helper macro to check if all OPAMP instances sharing the same
+  *         OPAMP common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         OPAMP state:
+  *         All OPAMP instances of the OPAMP common group must be disabled.
+  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
+  * @retval 0: All OPAMP instances sharing the same OPAMP common instance
+  *            are disabled.
+  *         1: At least one OPAMP instance sharing the same OPAMP common instance
+  *            is enabled
+  */
+#if defined(OPAMP1) && defined(OPAMP2)
+#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \
+  (LL_OPAMP_IsEnabled(OPAMP1) |                                                \
+   LL_OPAMP_IsEnabled(OPAMP2)  )
+#else
+#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \
+  (LL_OPAMP_IsEnabled(OPAMP1))
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
+  * @{
+  */
+
+/** @defgroup OPAMP_LL_EF_Configuration_opamp_common Configuration of OPAMP hierarchical scope: common to several OPAMP instances
+  * @{
+  */
+
+/**
+  * @brief  Set OPAMP power range.
+  * @note   The OPAMP power range applies to several OPAMP instances
+  *         (if several OPAMP instances available on the selected device).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         OPAMP state:
+  *         All OPAMP instances of the OPAMP common group must be disabled.
+  *         This check can be done with function @ref LL_OPAMP_IsEnabled() for each
+  *         OPAMP instance or by using helper macro
+  *         @ref __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CSR      OPARANGE       LL_OPAMP_SetCommonPowerRange
+  * @param  OPAMPxy_COMMON OPAMP common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
+  * @param  PowerRange This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
+  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange)
+{
+  MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, PowerRange);
+}
+
+/**
+  * @brief  Get OPAMP power range.
+  * @note   The OPAMP power range applies to several OPAMP instances
+  *         (if several OPAMP instances available on the selected device).
+  * @rmtoll CSR      OPARANGE       LL_OPAMP_GetCommonPowerRange
+  * @param  OPAMPxy_COMMON OPAMP common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
+  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(OPAMP1->CSR, OPAMP1_CSR_OPARANGE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
+  * @{
+  */
+
+/**
+  * @brief  Set OPAMP power mode.
+  * @note   The OPAMP must be disabled to change this configuration.
+  * @rmtoll CSR      OPALPM         LL_OPAMP_SetPowerMode
+  * @param  OPAMPx OPAMP instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
+  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
+{
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPALPM, (PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK));
+}
+
+/**
+  * @brief  Get OPAMP power mode.
+  * @rmtoll CSR      OPALPM         LL_OPAMP_GetPowerMode
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
+  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
+{
+  register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPALPM));
+  
+  return (uint32_t)(power_mode | (power_mode >> (POSITION_VAL(OPAMP_CSR_OPALPM))));
+}
+
+/**
+  * @brief  Set OPAMP mode calibration or functional.
+  * @note   OPAMP mode corresponds to functional or calibration mode:
+  *          - functional mode: OPAMP operation in standalone, follower, ...
+  *            Set functional mode using function
+  *            @ref LL_OPAMP_SetFunctionalMode().
+  *          - calibration mode: offset calibration of the selected
+  *            transistors differential pair NMOS or PMOS.
+  * @note   On this STM32 serie, during calibration, OPAMP functional
+  *         mode must be set to standalone or follower mode
+  *         (in order to open internal connections to resistors
+  *         of PGA mode).
+  *         Refer to function @ref LL_OPAMP_SetFunctionalMode().
+  * @rmtoll CSR      CALON          LL_OPAMP_SetMode
+  * @param  OPAMPx OPAMP instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+  *         @arg @ref LL_OPAMP_MODE_CALIBRATION
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
+{
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
+}
+
+/**
+  * @brief  Get OPAMP mode calibration or functional.
+  * @note   OPAMP mode corresponds to functional or calibration mode:
+  *          - functional mode: OPAMP operation in standalone, follower, ...
+  *            Set functional mode using function
+  *            @ref LL_OPAMP_SetFunctionalMode().
+  *          - calibration mode: offset calibration of the selected
+  *            transistors differential pair NMOS or PMOS.
+  * @rmtoll CSR      CALON          LL_OPAMP_GetMode
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+  *         @arg @ref LL_OPAMP_MODE_CALIBRATION
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
+{
+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
+}
+
+/**
+  * @brief  Set OPAMP functional mode by setting internal connections.
+  *         OPAMP operation in standalone, follower, ...
+  * @note   This function reset bit of calibration mode to ensure
+  *         to be in functional mode, in order to have OPAMP parameters
+  *         (inputs selection, ...) set with the corresponding OPAMP mode
+  *         to be effective.
+  * @rmtoll CSR      OPAMODE        LL_OPAMP_SetFunctionalMode
+  * @param  OPAMPx OPAMP instance
+  * @param  FunctionalMode This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_MODE_STANDALONE
+  *         @arg @ref LL_OPAMP_MODE_FOLLOWER
+  *         @arg @ref LL_OPAMP_MODE_PGA
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
+{
+  /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAMODE | OPAMP_CSR_CALON, FunctionalMode);
+}
+
+/**
+  * @brief  Get OPAMP functional mode from setting of internal connections.
+  *         OPAMP operation in standalone, follower, ...
+  * @rmtoll CSR      OPAMODE        LL_OPAMP_GetFunctionalMode
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_MODE_STANDALONE
+  *         @arg @ref LL_OPAMP_MODE_FOLLOWER
+  *         @arg @ref LL_OPAMP_MODE_PGA
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
+{
+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMODE));
+}
+
+/**
+  * @brief  Set OPAMP PGA gain.
+  * @note   Preliminarily, OPAMP must be set in mode PGA
+  *         using function @ref LL_OPAMP_SetFunctionalMode().
+  * @rmtoll CSR      PGGAIN         LL_OPAMP_SetPGAGain
+  * @param  OPAMPx OPAMP instance
+  * @param  PGAGain This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_PGA_GAIN_2
+  *         @arg @ref LL_OPAMP_PGA_GAIN_4
+  *         @arg @ref LL_OPAMP_PGA_GAIN_8
+  *         @arg @ref LL_OPAMP_PGA_GAIN_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
+{
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN, PGAGain);
+}
+
+/**
+  * @brief  Get OPAMP PGA gain.
+  * @note   Preliminarily, OPAMP must be set in mode PGA
+  *         using function @ref LL_OPAMP_SetFunctionalMode().
+  * @rmtoll CSR      PGGAIN         LL_OPAMP_GetPGAGain
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_PGA_GAIN_2
+  *         @arg @ref LL_OPAMP_PGA_GAIN_4
+  *         @arg @ref LL_OPAMP_PGA_GAIN_8
+  *         @arg @ref LL_OPAMP_PGA_GAIN_16
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
+{
+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
+  * @{
+  */
+
+/**
+  * @brief  Set OPAMP non-inverting input connection.
+  * @rmtoll CSR      VPSEL          LL_OPAMP_SetInputNonInverting
+  * @param  OPAMPx OPAMP instance
+  * @param  InputNonInverting This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+  *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
+{
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
+}
+
+/**
+  * @brief  Get OPAMP non-inverting input connection.
+  * @rmtoll CSR      VPSEL          LL_OPAMP_GetInputNonInverting
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+  *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
+{
+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
+}
+
+/**
+  * @brief  Set OPAMP inverting input connection.
+  * @note   OPAMP inverting input is used with OPAMP in mode standalone
+  *         or PGA with external capacitors for filtering circuit.
+  *         Otherwise (OPAMP in mode follower), OPAMP inverting input
+  *         is not used (not connected to GPIO pin).
+  * @rmtoll CSR      VMSEL          LL_OPAMP_SetInputInverting
+  * @param  OPAMPx OPAMP instance
+  * @param  InputInverting This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+  *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
+{
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSEL, InputInverting);
+}
+
+/**
+  * @brief  Get OPAMP inverting input connection.
+  * @rmtoll CSR      VMSEL          LL_OPAMP_GetInputInverting
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+  *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
+{
+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EF_Configuration_Legacy_Functions Configuration of OPAMP, legacy functions name
+  * @{
+  */
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+__STATIC_INLINE void LL_OPAMP_SetNonInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t NonInvertingInput)
+{
+  LL_OPAMP_SetInputNonInverting(OPAMPx, NonInvertingInput);
+}
+
+__STATIC_INLINE void LL_OPAMP_SetInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t InvertingInput)
+{
+  LL_OPAMP_SetInputInverting(OPAMPx, InvertingInput);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
+  * @{
+  */
+
+/**
+  * @brief  Set OPAMP trimming mode.
+  * @rmtoll CSR      USERTRIM       LL_OPAMP_SetTrimmingMode
+  * @param  OPAMPx OPAMP instance
+  * @param  TrimmingMode This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
+  *         @arg @ref LL_OPAMP_TRIMMING_USER
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
+{
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
+}
+
+/**
+  * @brief  Get OPAMP trimming mode.
+  * @rmtoll CSR      USERTRIM       LL_OPAMP_GetTrimmingMode
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
+  *         @arg @ref LL_OPAMP_TRIMMING_USER
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
+{
+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
+}
+
+/**
+  * @brief  Set OPAMP offset to calibrate the selected transistors
+  *         differential pair NMOS or PMOS.
+  * @note   Preliminarily, OPAMP must be set in mode calibration
+  *         using function @ref LL_OPAMP_SetMode().
+  * @rmtoll CSR      CALSEL         LL_OPAMP_SetCalibrationSelection
+  * @param  OPAMPx OPAMP instance
+  * @param  TransistorsDiffPair This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
+{
+  /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because            */
+  /* containing other bits reserved for other purpose.                        */
+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
+}
+
+/**
+  * @brief  Get OPAMP offset to calibrate the selected transistors
+  *         differential pair NMOS or PMOS.
+  * @note   Preliminarily, OPAMP must be set in mode calibration
+  *         using function @ref LL_OPAMP_SetMode().
+  * @rmtoll CSR      CALSEL         LL_OPAMP_GetCalibrationSelection
+  * @param  OPAMPx OPAMP instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
+{
+  register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
+  
+  return (CalibrationSelection |
+          ((OPAMP_OTR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_OTR_TRIMOFFSETP) * (CalibrationSelection && OPAMP_CSR_CALSEL))));
+}
+
+/**
+  * @brief  Get OPAMP calibration result of toggling output.
+  * @note   This functions returns:
+  *         0 if OPAMP calibration output is reset
+  *         1 if OPAMP calibration output is set
+  * @rmtoll CSR      CALOUT         LL_OPAMP_IsCalibrationOutputSet
+  * @param  OPAMPx OPAMP instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
+{
+  return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT);
+}
+
+/**
+  * @brief  Set OPAMP trimming factor for the selected transistors
+  *         differential pair NMOS or PMOS, corresponding to the selected
+  *         power mode.
+  * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_SetTrimmingValue\n
+  *         OTR      TRIMOFFSETP    LL_OPAMP_SetTrimmingValue\n
+  *         LPOTR    TRIMLPOFFSETN  LL_OPAMP_SetTrimmingValue\n
+  *         LPOTR    TRIMLPOFFSETP  LL_OPAMP_SetTrimmingValue
+  * @param  OPAMPx OPAMP instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
+  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
+  * @param  TransistorsDiffPair This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
+  * @param  TrimmingValue 0x00...0x1F
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
+{
+  register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+  
+  /* Set bits with position in register depending on parameter                */
+  /* "TransistorsDiffPair".                                                   */
+  /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
+  /* containing other bits reserved for other purpose.                        */
+  MODIFY_REG(*preg,
+             (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
+             TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)));
+}
+
+/**
+  * @brief  Get OPAMP trimming factor for the selected transistors
+  *         differential pair NMOS or PMOS, corresponding to the selected
+  *         power mode.
+  * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_GetTrimmingValue\n
+  *         OTR      TRIMOFFSETP    LL_OPAMP_GetTrimmingValue\n
+  *         LPOTR    TRIMLPOFFSETN  LL_OPAMP_GetTrimmingValue\n
+  *         LPOTR    TRIMLPOFFSETP  LL_OPAMP_GetTrimmingValue
+  * @param  OPAMPx OPAMP instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
+  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
+  * @param  TransistorsDiffPair This parameter can be one of the following values:
+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
+  * @retval 0x0...0x1F
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
+{
+  register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+  
+  /* Retrieve bits with position in register depending on parameter           */
+  /* "TransistorsDiffPair".                                                   */
+  /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
+  /* containing other bits reserved for other purpose.                        */
+  return (uint32_t)(READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
+                    >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
+  * @{
+  */
+/**
+  * @brief  Enable OPAMP instance.
+  * @note   After enable from off state, OPAMP requires a delay
+  *         to fullfill wake up time specification.
+  *         Refer to device datasheet, parameter "tWAKEUP".
+  * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Enable
+  * @param  OPAMPx OPAMP instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
+{
+  SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
+}
+
+/**
+  * @brief  Disable OPAMP instance.
+  * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Disable
+  * @param  OPAMPx OPAMP instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
+{
+  CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
+}
+
+/**
+  * @brief  Get OPAMP instance enable state
+  *         (0: OPAMP is disabled, 1: OPAMP is enabled)
+  * @rmtoll CSR      OPAMPXEN       LL_OPAMP_IsEnabled
+  * @param  OPAMPx OPAMP instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
+{
+  return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* OPAMP1 || OPAMP2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_OPAMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c
new file mode 100755
index 0000000..7c6d7b1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_pwr.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   PWR LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_pwr.h"
+#include "stm32l4xx_ll_bus.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PWR_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the PWR registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: PWR registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_PWR_DeInit(void)
+{
+  /* Force reset of PWR clock */
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+  /* Release reset of PWR clock */
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+  return SUCCESS;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined(PWR) */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h
new file mode 100755
index 0000000..d870a84
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h
@@ -0,0 +1,1440 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_PWR_H
+#define __STM32L4xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF
+#define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
+#define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
+#define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
+#define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
+#define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
+#define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
+#define LL_PWR_SR1_SBF                     PWR_SR1_SBF
+#define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
+#define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
+#define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
+#define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
+#define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
+#if defined(PWR_SR2_PVMO4)
+#define LL_PWR_SR2_PVMO4                   PWR_SR2_PVMO4
+#endif /* PWR_SR2_PVMO4 */
+#if defined(PWR_SR2_PVMO3)
+#define LL_PWR_SR2_PVMO3                   PWR_SR2_PVMO3
+#endif /* PWR_SR2_PVMO3 */
+#if defined(PWR_SR2_PVMO2)
+#define LL_PWR_SR2_PVMO2                   PWR_SR2_PVMO2
+#endif /* PWR_SR2_PVMO2 */
+#if defined(PWR_SR2_PVMO1)
+#define LL_PWR_SR2_PVMO1                   PWR_SR2_PVMO1
+#endif /* PWR_SR2_PVMO1 */
+#define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
+#define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
+#define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
+#define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR1_VOS_1)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
+  * @{
+  */
+#define LL_PWR_MODE_STOP0                  (PWR_CR1_LPMS_STOP0)
+#define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_STOP1)
+#define LL_PWR_MODE_STOP2                  (PWR_CR1_LPMS_STOP2)
+#define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_STANDBY)
+#define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_SHUTDOWN)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
+  * @{
+  */
+#if defined(PWR_CR2_PVME1)
+#define LL_PWR_PVM_VDDUSB_1_2V             (PWR_CR2_PVME1)     /* Monitoring VDDUSB vs. 1.2V */
+#endif
+#if defined(PWR_CR2_PVME2)
+#define LL_PWR_PVM_VDDIO2_0_9V             (PWR_CR2_PVME2)     /* Monitoring VDDIO2 vs. 0.9V */
+#endif
+#if defined(PWR_CR2_PVME3)
+#define LL_PWR_PVM_VDDA_1_62V              (PWR_CR2_PVME3)     /* Monitoring VDDA vs. 1.62V  */
+#endif
+#if defined(PWR_CR2_PVME4)
+#define LL_PWR_PVM_VDDA_2_2V               (PWR_CR2_PVME4)     /* Monitoring VDDA vs. 2.2V   */
+#endif
+/**
+  * @}
+  */
+  
+/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0                  (PWR_CR2_PLS_LEV0)  /* VPVD0 around 2.0 V */
+#define LL_PWR_PVDLEVEL_1                  (PWR_CR2_PLS_LEV1)  /* VPVD1 around 2.2 V */
+#define LL_PWR_PVDLEVEL_2                  (PWR_CR2_PLS_LEV2)  /* VPVD2 around 2.4 V */
+#define LL_PWR_PVDLEVEL_3                  (PWR_CR2_PLS_LEV3)  /* VPVD3 around 2.5 V */
+#define LL_PWR_PVDLEVEL_4                  (PWR_CR2_PLS_LEV4)  /* VPVD4 around 2.6 V */
+#define LL_PWR_PVDLEVEL_5                  (PWR_CR2_PLS_LEV5)  /* VPVD5 around 2.8 V */
+#define LL_PWR_PVDLEVEL_6                  (PWR_CR2_PLS_LEV6)  /* VPVD6 around 2.9 V */
+#define LL_PWR_PVDLEVEL_7                  (PWR_CR2_PLS_LEV7)  /* External input analog voltage   (Compare internally to VREFINT) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
+#define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
+#define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
+#define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
+#define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
+  * @{
+  */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K      ((uint32_t)0x00000000)
+#define LL_PWR_BATT_CHARGRESISTOR_1_5K     (PWR_CR4_VBRS)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GPIO GPIO
+  * @{
+  */
+#define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
+#define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
+#define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
+#define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
+#define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
+#if defined(GPIOF)
+#define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))
+#endif
+#if defined(GPIOG)
+#define LL_PWR_GPIO_G                      ((uint32_t)(&(PWR->PUCRG)))
+#endif
+#if defined(GPIOH)
+#define LL_PWR_GPIO_H                      ((uint32_t)(&(PWR->PUCRH)))
+#endif
+#if defined(GPIOI)
+#define LL_PWR_GPIO_I                      ((uint32_t)(&(PWR->PUCRI)))
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
+  * @{
+  */
+#define LL_PWR_GPIO_BIT_0                  ((uint32_t)0x00000001)
+#define LL_PWR_GPIO_BIT_1                  ((uint32_t)0x00000002)
+#define LL_PWR_GPIO_BIT_2                  ((uint32_t)0x00000004)
+#define LL_PWR_GPIO_BIT_3                  ((uint32_t)0x00000008)
+#define LL_PWR_GPIO_BIT_4                  ((uint32_t)0x00000010)
+#define LL_PWR_GPIO_BIT_5                  ((uint32_t)0x00000020)
+#define LL_PWR_GPIO_BIT_6                  ((uint32_t)0x00000040)
+#define LL_PWR_GPIO_BIT_7                  ((uint32_t)0x00000080)
+#define LL_PWR_GPIO_BIT_8                  ((uint32_t)0x00000100)
+#define LL_PWR_GPIO_BIT_9                  ((uint32_t)0x00000200)
+#define LL_PWR_GPIO_BIT_10                 ((uint32_t)0x00000400)
+#define LL_PWR_GPIO_BIT_11                 ((uint32_t)0x00000800)
+#define LL_PWR_GPIO_BIT_12                 ((uint32_t)0x00001000)
+#define LL_PWR_GPIO_BIT_13                 ((uint32_t)0x00002000)
+#define LL_PWR_GPIO_BIT_14                 ((uint32_t)0x00004000)
+#define LL_PWR_GPIO_BIT_15                 ((uint32_t)0x00008000)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Switch the regulator from main mode to low-power mode
+  * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+  * @brief  Switch the regulator from low-power mode to main mode
+  * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+  * @brief  Check if the regulator is in low-power mode
+  * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR));
+}
+
+/**
+  * @brief  Switch from run main mode to run low-power mode.
+  * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
+{
+  LL_PWR_EnableLowPowerRunMode();
+}
+
+/**
+  * @brief  Switch from run main mode to low-power mode.
+  * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
+{
+  LL_PWR_DisableLowPowerRunMode();
+}
+
+/**
+  * @brief  Set the main internal regulator output voltage
+  * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the main internal regulator output voltage
+  * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));
+}
+
+/**
+  * @brief  Set Low-Power mode
+  * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP0
+  *         @arg @ref LL_PWR_MODE_STOP1
+  *         @arg @ref LL_PWR_MODE_STOP2
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  *         @arg @ref LL_PWR_MODE_SHUTDOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
+}
+
+/**
+  * @brief  Get Low-Power mode
+  * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP0
+  *         @arg @ref LL_PWR_MODE_STOP1
+  *         @arg @ref LL_PWR_MODE_STOP2
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  *         @arg @ref LL_PWR_MODE_SHUTDOWN
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
+}
+
+#if defined(PWR_CR2_PVME1)
+/**
+  * @brief  Enable VDDUSB supply
+  * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+  * @brief  Disable VDDUSB supply
+  * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+  * @brief  Check if VDDUSB supply is enabled
+  * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
+{
+  return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV));
+}
+#endif
+
+#if defined(PWR_CR2_IOSV)
+/**
+  * @brief  Enable VDDIO2 supply
+  * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+  * @brief  Disable VDDIO2 supply
+  * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+  * @brief  Check if VDDIO2 supply is enabled
+  * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
+{
+  return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV));
+}
+#endif
+
+/**
+  * @brief  Enable the Power Voltage Monitoring on a peripheral
+  * @rmtoll CR2          PVME1         LL_PWR_EnablePVM\n
+  *         CR2          PVME2         LL_PWR_EnablePVM\n
+  *         CR2          PVME3         LL_PWR_EnablePVM\n
+  *         CR2          PVME4         LL_PWR_EnablePVM
+  * @param  PeriphVoltage This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
+  *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_1_62V
+  *         @arg @ref LL_PWR_PVM_VDDA_2_2V
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
+{
+  SET_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+  * @brief  Disable the Power Voltage Monitoring on a peripheral
+  * @rmtoll CR2          PVME1         LL_PWR_DisablePVM\n
+  *         CR2          PVME2         LL_PWR_DisablePVM\n
+  *         CR2          PVME3         LL_PWR_DisablePVM\n
+  *         CR2          PVME4         LL_PWR_DisablePVM
+  * @param  PeriphVoltage This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
+  *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_1_62V
+  *         @arg @ref LL_PWR_PVM_VDDA_2_2V
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
+{
+  CLEAR_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+  * @brief  Check if Power Voltage Monitoring is enabled on a peripheral
+  * @rmtoll CR2          PVME1         LL_PWR_IsEnabledPVM\n
+  *         CR2          PVME2         LL_PWR_IsEnabledPVM\n
+  *         CR2          PVME3         LL_PWR_IsEnabledPVM\n
+  *         CR2          PVME4         LL_PWR_IsEnabledPVM
+  * @param  PeriphVoltage This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
+  *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_1_62V
+  *         @arg @ref LL_PWR_PVM_VDDA_2_2V
+  *
+  *         (*) value not defined in all devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
+{
+  return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage));
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR2          PLS           LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR2          PLS           LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE));
+}
+
+/**
+  * @brief  Enable Internal Wake-up line
+  * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableInternWU(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+  * @brief  Disable Internal Wake-up line
+  * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableInternWU(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+  * @brief  Check if Internal Wake-up line is enabled
+  * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
+{
+  return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF));
+}
+
+/**
+  * @brief  Enable pull-up and pull-down configuration
+  * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+  * @brief  Disable pull-up and pull-down configuration
+  * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+  * @brief  Check if pull-up and pull-down configuration  is enabled
+  * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
+{
+  return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC));
+}
+
+/**
+  * @brief  Enable SRAM2 content retention in Standby mode
+  * @rmtoll CR3          RRS           LL_PWR_EnableSRAM2Retention
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+  * @brief  Disable SRAM2 content retention in Standby mode
+  * @rmtoll CR3          RRS           LL_PWR_DisableSRAM2Retention
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+  * @brief  Check if SRAM2 content retention in Standby mode  is enabled
+  * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAM2Retention
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
+{
+  return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS));
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\n
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\n
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\n
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin));
+}
+
+/**
+  * @brief  Set the resistor impedance
+  * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
+  * @param  Resistor This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
+{
+  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
+}
+
+/**
+  * @brief  Get the resistor impedance
+  * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
+}
+
+/**
+  * @brief  Enable battery charging
+  * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
+{
+  SET_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+  * @brief  Disable battery charging
+  * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+  * @brief  Check if battery charging is enabled
+  * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
+{
+  return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE));
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity low for the event detection
+  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity high for the event detection
+  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+  * @brief  Get the Wake-Up pin polarity for the event detection
+  * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin));
+}
+
+/**
+  * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
+  * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRF        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRG        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRH        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRI        PU0-11        LL_PWR_EnableGPIOPullUp
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F (*)
+  *         @arg @ref LL_PWR_GPIO_G (*)
+  *         @arg @ref LL_PWR_GPIO_H
+  *         @arg @ref LL_PWR_GPIO_I (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  SET_BIT(*((uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+  * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
+  * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRF        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRG        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRH        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRI        PU0-11        LL_PWR_DisableGPIOPullUp
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F (*)
+  *         @arg @ref LL_PWR_GPIO_G (*)
+  *         @arg @ref LL_PWR_GPIO_H
+  *         @arg @ref LL_PWR_GPIO_I (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+  * @brief  Check if GPIO pull-up state is enabled
+  * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRF        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRG        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRH        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRI        PU0-11        LL_PWR_IsEnabledGPIOPullUp
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F (*)
+  *         @arg @ref LL_PWR_GPIO_G (*)
+  *         @arg @ref LL_PWR_GPIO_H
+  *         @arg @ref LL_PWR_GPIO_I (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber));
+}
+
+/**
+  * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
+  * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRF        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRG        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRH        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRI        PD0-11        LL_PWR_EnableGPIOPullDown
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F (*)
+  *         @arg @ref LL_PWR_GPIO_G (*)
+  *         @arg @ref LL_PWR_GPIO_H
+  *         @arg @ref LL_PWR_GPIO_I (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  register uint32_t temp = (uint32_t)(GPIO) + 4;
+  SET_BIT(*((uint32_t *)(temp)), GPIONumber);
+}
+
+/**
+  * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
+  * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRF        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRG        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRH        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRI        PD0-11        LL_PWR_DisableGPIOPullDown
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F (*)
+  *         @arg @ref LL_PWR_GPIO_G (*)
+  *         @arg @ref LL_PWR_GPIO_H
+  *         @arg @ref LL_PWR_GPIO_I (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  register uint32_t temp = (uint32_t)(GPIO) + 4;
+  CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber);
+}
+
+/**
+  * @brief  Check if GPIO pull-down state is enabled
+  * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRF        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRG        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRH        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRI        PD0-11        LL_PWR_IsEnabledGPIOPullDown
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F (*)
+  *         @arg @ref LL_PWR_GPIO_G (*)
+  *         @arg @ref LL_PWR_GPIO_H
+  *         @arg @ref LL_PWR_GPIO_I (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  register uint32_t temp = (uint32_t)(GPIO) + 4;
+  return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Internal Wake-up line Flag
+  * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
+{
+  return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI));
+}
+
+/**
+  * @brief  Get Stand-By Flag
+  * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+  return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF));
+}
+
+/**
+  * @brief  Get Wake-up Flag 5
+  * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+  return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5));
+}
+
+/**
+  * @brief  Get Wake-up Flag 4
+  * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+  return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4));
+}
+
+/**
+  * @brief  Get Wake-up Flag 3
+  * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+  return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3));
+}
+
+/**
+  * @brief  Get Wake-up Flag 2
+  * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+  return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2));
+}
+
+/**
+  * @brief  Get Wake-up Flag 1
+  * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+  return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1));
+}
+
+/**
+  * @brief  Clear Stand-By Flag
+  * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
+}
+
+/**
+  * @brief  Clear Wake-up Flags
+  * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 5
+  * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 4
+  * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 3
+  * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 2
+  * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 1
+  * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
+}
+
+/**
+  * @brief  Indicate whether VDDA voltage is below or above PVM4 threshold
+  * @rmtoll SR2          PVMO4         LL_PWR_IsActiveFlag_PVMO4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4));
+}
+
+/**
+  * @brief  Indicate whether VDDA voltage is below or above PVM3 threshold
+  * @rmtoll SR2          PVMO3         LL_PWR_IsActiveFlag_PVMO3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3));
+}
+
+#if defined(PWR_SR2_PVMO2)
+/**
+  * @brief  Indicate whether VDDIO2 voltage is below or above PVM2 threshold
+  * @rmtoll SR2          PVMO2         LL_PWR_IsActiveFlag_PVMO2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2));
+}
+#endif /* PWR_SR2_PVMO2 */
+
+#if defined(PWR_SR2_PVMO1)
+/**
+  * @brief  Indicate whether VDDUSB voltage is below or above PVM1 threshold
+  * @rmtoll SR2          PVMO1         LL_PWR_IsActiveFlag_PVMO1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1));
+}
+#endif /* PWR_SR2_PVMO1 */
+
+/**
+  * @brief  Indicate whether VDD voltage is below or above the selected PVD threshold
+  * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO));
+}
+
+/**
+  * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+  * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF));
+}
+
+/**
+  * @brief  Indicate whether the regulator is ready in main mode or is in low-power mode
+  * @note: Take care, return value "0" means the regulator is ready.  Return value "1" means the output voltage range is still changing.
+  * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF));
+}
+
+/**
+  * @brief  Indicate whether or not the low-power regulator is ready
+  * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
+{
+  return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+*/
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+#define LL_PWR_IsActiveFlag_VOSF  LL_PWR_IsActiveFlag_VOS
+/**
+@endcond
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c
new file mode 100755
index 0000000..5d750e9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c
@@ -0,0 +1,1556 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_rcc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   RCC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_rcc.h"
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+  * @{
+  */
+#if defined(RCC_CCIPR_USART3SEL)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+#else
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
+
+#endif /* RCC_CCIPR_USART3SEL */
+#if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+                                             || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
+#elif defined(RCC_CCIPR_UART4SEL)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
+#elif defined(RCC_CCIPR_UART5SEL)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
+#endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/
+
+#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
+
+#if defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#elif !defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#else
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
+
+#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL */
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
+
+#if defined(RCC_CCIPR_SAI2SEL)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+#else
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
+#endif /* RCC_CCIPR_SAI2SEL */
+
+#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
+
+#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
+
+#if defined(USB_OTG_FS) || defined(USB)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB_OTG_FS || USB */
+
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+
+#if defined(SWPMI1)
+#define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
+#endif /* DFSDM1_Channel0 */
+
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+  * @{
+  */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+uint32_t RCC_PLL_GetFreqDomain_SAI(void);
+uint32_t RCC_PLL_GetFreqDomain_48M(void);
+uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
+uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
+uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
+#if defined(RCC_PLLSAI2_SUPPORT)
+uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
+uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);
+#endif /*RCC_PLLSAI2_SUPPORT*/
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Reset the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *         - MSI  ON and used as system clock source
+  *         - HSE, HSI, PLL and PLLSAIxSource OFF
+  *         - AHB, APB1 and APB2 prescaler set to 1.
+  *         - CSS, MCO OFF
+  *         - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *         - Peripheral clocks
+  *         - LSI, LSE and RTC clocks
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RCC registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RCC_DeInit(void)
+{
+  uint32_t vl_mask = 0U;
+
+  /* Set MSION bit */
+  LL_RCC_MSI_Enable();
+
+  /* Insure MSIRDY bit is set before writing default MSIRANGE value */
+  while (LL_RCC_MSI_IsReady() == 0U)
+  {
+    __NOP();
+  }
+
+  /* Set MSIRANGE default value */
+  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
+  /* Set MSITRIM bits to the reset value*/
+  LL_RCC_MSI_SetCalibTrimming(0);
+
+  /* Set HSITRIM bits to the reset value*/
+  LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+  /* Reset CFGR register */
+  LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+  vl_mask = 0xFFFFFFFFU;
+
+  /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */
+  CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON  | RCC_CR_HSEON |
+  RCC_CR_PLLON));
+
+  /* Reset PLLSAI1ON bit */
+  CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+  /* Reset PLLSAI2ON bit */
+  CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+  /* Write new mask in CR register */
+  LL_RCC_WriteReg(CR, vl_mask);
+
+  /* Reset PLLCFGR register */
+  LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
+
+  /* Reset PLLSAI1CFGR register */
+  LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+  /* Reset PLLSAI2CFGR register */
+  LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+  /* Reset HSEBYP bit */
+  LL_RCC_HSE_DisableBypass();
+
+  /* Disable all interrupts */
+  LL_RCC_WriteReg(CIER, 0x00000000U);
+
+  return SUCCESS;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
+  *         and different peripheral clocks available on the device.
+  * @note   If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
+  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
+  *         or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note   (*) MSI_VALUE is a constant defined in this file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  * @note   (**) HSI_VALUE is a constant defined in this file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  * @note   (***) HSE_VALUE is a constant defined in this file (default value
+  *               8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *               frequency of the crystal used. Otherwise, this function may
+  *               have wrong result.
+  * @note   The result of this function could be incorrect when using fractional
+  *         value for HSE crystal.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  * @{
+  */
+
+/**
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
+  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+  *         must be called to update structure fields. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+  * @retval None
+  */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+  /* Get SYSCLK frequency */
+  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+  * @brief  Return USARTx clock frequency
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+  if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+  {
+    /* USART1CLK clock frequency */
+    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+    {
+      case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+        usart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          usart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          usart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
+      default:
+        usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+  {
+    /* USART2CLK clock frequency */
+    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+    {
+      case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+        usart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          usart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          usart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
+      default:
+        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else
+  {
+#if defined(RCC_CCIPR_USART3SEL)
+    if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
+    {
+      /* USART3CLK clock frequency */
+      switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+      {
+        case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
+          usart_frequency = RCC_GetSystemClockFreq();
+          break;
+
+        case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
+          if (LL_RCC_HSI_IsReady())
+          {
+            usart_frequency = HSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
+          if (LL_RCC_LSE_IsReady())
+          {
+            usart_frequency = LSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
+        default:
+          usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+          break;
+      }
+    }
+#endif /* RCC_CCIPR_USART3SEL */
+  }
+  return usart_frequency;
+}
+
+#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
+/**
+  * @brief  Return UARTx clock frequency
+  * @param  UARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE
+  * @retval UART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+{
+  uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+
+#if defined(RCC_CCIPR_UART4SEL)
+  if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
+  {
+    /* UART4CLK clock frequency */
+    switch (LL_RCC_GetUARTClockSource(UARTxSource))
+    {
+      case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
+        uart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          uart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          uart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */
+      default:
+        uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#endif /* RCC_CCIPR_UART4SEL */
+
+#if defined(RCC_CCIPR_UART5SEL)
+  if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
+  {
+    /* UART5CLK clock frequency */
+    switch (LL_RCC_GetUARTClockSource(UARTxSource))
+    {
+      case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
+        uart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          uart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          uart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */
+      default:
+        uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#endif /* RCC_CCIPR_UART5SEL */
+
+  return uart_frequency;
+}
+#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
+
+/**
+  * @brief  Return I2Cx clock frequency
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval I2C clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+  */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+  if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+  {
+    /* I2C1 CLK clock frequency */
+    switch (LL_RCC_GetI2CClockSource(I2CxSource))
+    {
+      case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+        i2c_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          i2c_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
+      default:
+        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#if defined(RCC_CCIPR_I2C2SEL)
+  else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
+  {
+    /* I2C2 CLK clock frequency */
+    switch (LL_RCC_GetI2CClockSource(I2CxSource))
+    {
+      case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+        i2c_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          i2c_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
+      default:
+        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#endif /*RCC_CCIPR_I2C2SEL*/
+  else
+  {
+    if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+    {
+      /* I2C3 CLK clock frequency */
+      switch (LL_RCC_GetI2CClockSource(I2CxSource))
+      {
+        case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+          i2c_frequency = RCC_GetSystemClockFreq();
+          break;
+
+        case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
+          if (LL_RCC_HSI_IsReady())
+          {
+            i2c_frequency = HSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
+        default:
+          i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+          break;
+      }
+    }
+#if defined(RCC_CCIPR2_I2C4SEL)
+    else
+    {
+      if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
+      {
+        /* I2C4 CLK clock frequency */
+        switch (LL_RCC_GetI2CClockSource(I2CxSource))
+        {
+          case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
+            i2c_frequency = RCC_GetSystemClockFreq();
+            break;
+
+          case LL_RCC_I2C4_CLKSOURCE_HSI:    /* I2C4 Clock is HSI Osc. */
+            if (LL_RCC_HSI_IsReady())
+            {
+              i2c_frequency = HSI_VALUE;
+            }
+            break;
+
+          case LL_RCC_I2C4_CLKSOURCE_PCLK1:  /* I2C4 Clock is PCLK1 */
+          default:
+            i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+            break;
+        }
+      }
+    }
+#endif /*RCC_CCIPR2_I2C4SEL*/
+  }
+
+  return i2c_frequency;
+}
+
+/**
+  * @brief  Return LPUARTx clock frequency
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval LPUART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
+{
+  uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
+
+  /* LPUART1CLK clock frequency */
+  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+  {
+    case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
+      lpuart_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
+      if (LL_RCC_HSI_IsReady())
+      {
+        lpuart_frequency = HSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
+      if (LL_RCC_LSE_IsReady())
+      {
+        lpuart_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
+    default:
+      lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+      break;
+  }
+
+  return lpuart_frequency;
+}
+
+/**
+  * @brief  Return LPTIMx clock frequency
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  * @retval LPTIM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
+  {
+    /* LPTIM1CLK clock frequency */
+    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+    {
+      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
+        if (LL_RCC_LSI_IsReady())
+        {
+          lptim_frequency = LSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          lptim_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          lptim_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
+      default:
+        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else
+  {
+    if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
+    {
+      /* LPTIM2CLK clock frequency */
+      switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+      {
+        case LL_RCC_LPTIM2_CLKSOURCE_LSI:    /* LPTIM2 Clock is LSI Osc. */
+          if (LL_RCC_LSI_IsReady())
+          {
+            lptim_frequency = LSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_LPTIM2_CLKSOURCE_HSI:    /* LPTIM2 Clock is HSI Osc. */
+          if (LL_RCC_HSI_IsReady())
+          {
+            lptim_frequency = HSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_LPTIM2_CLKSOURCE_LSE:    /* LPTIM2 Clock is LSE Osc. */
+          if (LL_RCC_LSE_IsReady())
+          {
+            lptim_frequency = LSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_LPTIM2_CLKSOURCE_PCLK1:  /* LPTIM2 Clock is PCLK1 */
+        default:
+          lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+          break;
+      }
+    }
+  }
+
+  return lptim_frequency;
+}
+
+/**
+  * @brief  Return SAIx clock frequency
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval SAI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
+  */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+  uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+  if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
+  {
+    /* SAI1CLK clock frequency */
+    switch (LL_RCC_GetSAIClockSource(SAIxSource))
+    {
+      case LL_RCC_SAI1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SAI1 clock source */
+        if (LL_RCC_PLLSAI1_IsReady())
+        {
+          sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+        }
+        break;
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+      case LL_RCC_SAI1_CLKSOURCE_PLLSAI2:    /* PLLSAI2 clock used as SAI1 clock source */
+        if (LL_RCC_PLLSAI2_IsReady())
+        {
+          sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+        }
+        break;
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+      case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */
+        if (LL_RCC_PLL_IsReady())
+        {
+          sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+        }
+        break;
+
+      case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */
+      default:
+        sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+        break;
+    }
+  }
+  else
+  {
+#if defined(RCC_CCIPR_SAI2SEL)
+    if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
+    {
+      /* SAI2CLK clock frequency */
+      switch (LL_RCC_GetSAIClockSource(SAIxSource))
+      {
+        case LL_RCC_SAI2_CLKSOURCE_PLLSAI1:  /* PLLSAI1 clock used as SAI2 clock source */
+          if (LL_RCC_PLLSAI1_IsReady())
+          {
+            sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+          }
+          break;
+
+  #if defined(RCC_PLLSAI2_SUPPORT)
+        case LL_RCC_SAI2_CLKSOURCE_PLLSAI2:  /* PLLSAI2 clock used as SAI2 clock source */
+          if (LL_RCC_PLLSAI2_IsReady())
+          {
+            sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+          }
+          break;
+
+  #endif /* RCC_PLLSAI2_SUPPORT */
+        case LL_RCC_SAI2_CLKSOURCE_PLL:      /* PLL clock used as SAI2 clock source */
+          if (LL_RCC_PLL_IsReady())
+          {
+            sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+          }
+          break;
+
+        case LL_RCC_SAI2_CLKSOURCE_PIN:      /* External input clock used as SAI2 clock source */
+        default:
+          sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+          break;
+      }
+    }
+#endif /* RCC_CCIPR_SAI2SEL */
+  }
+
+  return sai_frequency;
+}
+
+/**
+  * @brief  Return SDMMCx clock frequency
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+  * @retval SDMMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+  */
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+{
+  uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
+
+  /* SDMMC1CLK clock frequency */
+  switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+  {
+    case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SDMMC1 clock source */
+      if (LL_RCC_PLLSAI1_IsReady())
+      {
+        sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_PLL:        /* PLL clock used as SDMMC1 clock source */
+      if (LL_RCC_PLL_IsReady())
+      {
+        sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_MSI:        /* MSI clock used as SDMMC1 clock source */
+      if (LL_RCC_MSI_IsReady())
+      {
+        sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      }
+      break;
+
+#if defined(RCC_HSI48_SUPPORT)
+    case LL_RCC_SDMMC1_CLKSOURCE_HSI48:      /* HSI48 used as SDMMC1 clock source */
+      if (LL_RCC_HSI48_IsReady())
+      {
+        sdmmc_frequency = HSI48_VALUE;
+      }
+      break;
+#else
+    case LL_RCC_SDMMC1_CLKSOURCE_NONE:       /* No clock used as SDMMC1 clock source */
+#endif
+    default:
+      sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+      break;
+  }
+
+  return sdmmc_frequency;
+}
+
+/**
+  * @brief  Return RNGx clock frequency
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval RNG clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+  */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+{
+  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
+
+  /* RNGCLK clock frequency */
+  switch (LL_RCC_GetRNGClockSource(RNGxSource))
+  {
+    case LL_RCC_RNG_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as RNG clock source */
+      if (LL_RCC_PLLSAI1_IsReady())
+      {
+        rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
+      if (LL_RCC_PLL_IsReady())
+      {
+        rng_frequency = RCC_PLL_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_MSI:           /* MSI clock used as RNG clock source */
+      if (LL_RCC_MSI_IsReady())
+      {
+        rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      }
+      break;
+
+
+#if defined(RCC_HSI48_SUPPORT)
+    case LL_RCC_RNG_CLKSOURCE_HSI48:      /* HSI48 used as SDMMC1 clock source */
+      if (LL_RCC_HSI48_IsReady())
+      {
+        rng_frequency = HSI48_VALUE;
+      }
+      break;
+#else
+    case LL_RCC_RNG_CLKSOURCE_NONE:       /* No clock used as SDMMC1 clock source */
+#endif
+    default:
+      rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+      break;
+
+  }
+
+  return rng_frequency;
+}
+
+
+#if   defined(USB_OTG_FS)||defined(USB)
+/**
+  * @brief  Return USBx clock frequency
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval USB clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+  */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+  /* USBCLK clock frequency */
+  switch (LL_RCC_GetUSBClockSource(USBxSource))
+  {
+    case LL_RCC_USB_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as USB clock source */
+      if (LL_RCC_PLLSAI1_IsReady())
+      {
+        usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
+      if (LL_RCC_PLL_IsReady())
+      {
+        usb_frequency = RCC_PLL_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_MSI:           /* MSI clock used as USB clock source */
+      if (LL_RCC_MSI_IsReady())
+      {
+        usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      }
+      break;
+
+#if defined(RCC_HSI48_SUPPORT)
+    case LL_RCC_USB_CLKSOURCE_HSI48:      /* HSI48 used as USB clock source */
+      if (LL_RCC_HSI48_IsReady())
+      {
+        usb_frequency = HSI48_VALUE;
+      }
+      break;
+#else
+    case LL_RCC_USB_CLKSOURCE_NONE:       /* No clock used as USB clock source */
+#endif
+    default:
+      usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+      break;
+  }
+
+  return usb_frequency;
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+  * @brief  Return ADCx clock frequency
+  * @param  ADCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval ADC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+  */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+  uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+  /* ADCCLK clock frequency */
+  switch (LL_RCC_GetADCClockSource(ADCxSource))
+  {
+    case LL_RCC_ADC_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as ADC clock source */
+      if (LL_RCC_PLLSAI1_IsReady())
+      {
+        adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
+      }
+      break;
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+    case LL_RCC_ADC_CLKSOURCE_PLLSAI2:       /* PLLSAI2 clock used as ADC clock source */
+      if (LL_RCC_PLLSAI2_IsReady())
+      {
+         adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
+      }
+      break;
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+    case LL_RCC_ADC_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as ADC clock source */
+      adc_frequency = RCC_GetSystemClockFreq();
+      break;
+    case LL_RCC_ADC_CLKSOURCE_NONE:          /* No clock used as ADC clock source */
+    default:
+      adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+      break;
+  }
+
+  return adc_frequency;
+}
+
+#if defined(SWPMI1)
+/**
+  * @brief  Return SWPMIx clock frequency
+  * @param  SWPMIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE
+  * @retval SWPMI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
+  */
+uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
+{
+  uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));
+
+  /* SWPMI1CLK clock frequency */
+  switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
+  {
+    case LL_RCC_SWPMI1_CLKSOURCE_HSI:        /* SWPMI1 Clock is HSI Osc. */
+      if (LL_RCC_HSI_IsReady())
+      {
+        swpmi_frequency = HSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SWPMI1_CLKSOURCE_PCLK1:      /* SWPMI1 Clock is PCLK1 */
+    default:
+      swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+      break;
+  }
+
+  return swpmi_frequency;
+}
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Return DFSDMx clock frequency
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval DFSDM clock frequency (in Hz)
+  */
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
+{
+  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
+
+  /* DFSDM1CLK clock frequency */
+  switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+  {
+    case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:     /* DFSDM1 Clock is SYSCLK */
+      dfsdm_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:      /* DFSDM1 Clock is PCLK2 */
+    default:
+      dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+      break;
+  }
+
+  return dfsdm_frequency;
+}
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Return SYSTEM clock frequency
+  * @retval SYSTEM clock frequency (in Hz)
+  */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+  uint32_t frequency = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetSysClkSource())
+  {
+    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
+      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
+      frequency = HSI_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
+      frequency = RCC_PLL_GetFreqDomain_SYS();
+      break;
+
+    default:
+      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return HCLK clock frequency
+  * @param  SYSCLK_Frequency SYSCLK clock frequency
+  * @retval HCLK clock frequency (in Hz)
+  */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+  /* HCLK clock frequency */
+  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return PCLK1 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK1 clock frequency */
+  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return PCLK2 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK2 clock frequency */
+  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return PLL clock frequency used for system domain
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+     SYSCLK = PLL_VCO / PLLR
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+}
+/**
+  * @brief  Return PLL clock frequency used for SAI domain
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t RCC_PLL_GetFreqDomain_SAI(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
+     SAI Domain clock = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
+}
+
+/**
+  * @brief  Return PLL clock frequency used for 48 MHz domain
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t RCC_PLL_GetFreqDomain_48M(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+     48M Domain clock = PLL_VCO / PLLQ
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
+}
+
+/**
+  * @brief  Return PLLSAI1 clock frequency used for SAI domain
+  * @retval PLLSAI1 clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
+  /* SAI Domain clock  = PLLSAI1_VCO / PLLSAI1P */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
+}
+
+/**
+  * @brief  Return PLLSAI1 clock frequency used for 48Mhz domain
+  * @retval PLLSAI1 clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
+  /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1Q */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
+}
+
+/**
+  * @brief  Return PLLSAI1 clock frequency used for ADC domain
+  * @retval PLLSAI1 clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
+  /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1R */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+  * @brief  Return PLLSAI2 clock frequency used for SAI domain
+  * @retval PLLSAI2 clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
+  /* SAI Domain clock  = PLLSAI2_VCO / PLLSAI2P */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
+}
+
+  /**
+  * @brief  Return PLLSAI2 clock frequency used for ADC domain
+  * @retval PLLSAI2 clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
+  /* 48M Domain clock  = PLLSAI2_VCO / PLLSAI2R */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?
+                                     LL_RCC_MSI_GetRange() :
+                                     LL_RCC_MSI_GetRangeAfterStandby()));
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
+}
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h
new file mode 100755
index 0000000..e0d119a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h
@@ -0,0 +1,4479 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_RCC_H
+#define __STM32L4xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+
+static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+  * @{
+  */
+/* Defines used to perform offsets*/
+/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
+#define RCC_OFFSET_CCIPR        0U
+#define RCC_OFFSET_CCIPR2       0x14U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to 
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    8000000U   /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if defined(RCC_HSI48_SUPPORT)
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+  * @{
+  */
+#define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CICR_MSIRDYC                RCC_CICR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */
+#endif /* RCC_HSI48_SUPPORT */
+#define LL_RCC_CICR_PLLSAI1RDYC            RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_CICR_PLLSAI2RDYC            RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
+#define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+  * @{
+  */
+#define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIFR_MSIRDYF                RCC_CIFR_MSIRDYF     /*!< MSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
+#endif /* RCC_HSI48_SUPPORT */
+#define LL_RCC_CIFR_PLLSAI1RDYF            RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_CIFR_PLLSAI2RDYF            RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
+#define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_FWRSTF                  RCC_CSR_FWRSTF     /*!< Firewall reset flag */
+#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
+#define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF    /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
+#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+  * @{
+  */
+#define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIER_MSIRDYIE               RCC_CIER_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */
+#endif /* RCC_HSI48_SUPPORT */
+#define LL_RCC_CIER_PLLSAI1RDYIE           RCC_CIER_PLLSAI1RDYIE  /*!< PLLSAI1 Ready Interrupt Enable */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_CIER_PLLSAI2RDYIE           RCC_CIER_PLLSAI2RDYIE  /*!< PLLSAI2 Ready Interrupt Enable */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
+  * @{
+  */
+#define LL_RCC_MSIRANGE_0                  RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */
+#define LL_RCC_MSIRANGE_1                  RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */
+#define LL_RCC_MSIRANGE_2                  RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */
+#define LL_RCC_MSIRANGE_3                  RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */
+#define LL_RCC_MSIRANGE_4                  RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */
+#define LL_RCC_MSIRANGE_5                  RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */
+#define LL_RCC_MSIRANGE_6                  RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */
+#define LL_RCC_MSIRANGE_7                  RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */
+#define LL_RCC_MSIRANGE_8                  RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */
+#define LL_RCC_MSIRANGE_9                  RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */
+#define LL_RCC_MSIRANGE_10                 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */
+#define LL_RCC_MSIRANGE_11                 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MSISRANGE  MSI range after Standby mode
+  * @{
+  */
+#define LL_RCC_MSISRANGE_4                 RCC_CSR_MSISRANGE_1  /*!< MSI = 1 MHz    */
+#define LL_RCC_MSISRANGE_5                 RCC_CSR_MSISRANGE_2  /*!< MSI = 2 MHz    */
+#define LL_RCC_MSISRANGE_6                 RCC_CSR_MSISRANGE_4  /*!< MSI = 4 MHz    */
+#define LL_RCC_MSISRANGE_7                 RCC_CSR_MSISRANGE_8  /*!< MSI = 8 MHz    */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
+  * @{
+  */
+#define LL_RCC_LSCO_CLKSOURCE_LSI          0x00000000U                 /*!< LSI selection for low speed clock  */
+#define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock  */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+  * @{
+  */
+#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+  * @{
+  */
+#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK  Wakeup from Stop and CSS backup clock selection
+  * @{
+  */
+#define LL_RCC_STOP_WAKEUPCLOCK_MSI        0x00000000U             /*!< MSI selection after wake-up from STOP */
+#define LL_RCC_STOP_WAKEUPCLOCK_HSI        RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_NOCLOCK          0x00000000U                            /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< Main PLL selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE              (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1       /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2       /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4       /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8       /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16      /*!< MCO divided by 16 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USART1_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2      (RCC_CCIPR_USART1SEL << 16U)                           /*!< PCLK2 clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)   /*!< LSE clock used as USART1 clock source */
+#define LL_RCC_USART2_CLKSOURCE_PCLK1      (RCC_CCIPR_USART2SEL << 16U)                           /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)   /*!< LSE clock used as USART2 clock source */
+#if defined(RCC_CCIPR_USART3SEL)
+#define LL_RCC_USART3_CLKSOURCE_PCLK1      (RCC_CCIPR_USART3SEL << 16U)                           /*!< PCLK1 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)   /*!< LSE clock used as USART3 clock source */
+#endif /* RCC_CCIPR_USART3SEL */
+/**
+  * @}
+  */
+
+#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
+/** @defgroup RCC_LL_EC_UART4_CLKSOURCE  Peripheral UART clock source selection
+  * @{
+  */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE_PCLK1       (RCC_CCIPR_UART4SEL << 16U)                           /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)  /*!< SYSCLK clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)  /*!< HSI clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)    /*!< LSE clock used as UART4 clock source */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE_PCLK1       (RCC_CCIPR_UART5SEL << 16U)                           /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0)  /*!< SYSCLK clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1)  /*!< HSI clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL)    /*!< LSE clock used as UART5 clock source */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+  * @}
+  */
+#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
+
+/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK1     0x00000000U                     /*!< PCLK1 clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0          /*!< SYSCLK clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1          /*!< HSI clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL            /*!< LSE clock used as LPUART1 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U))                                                  /*!< PCLK1 clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
+#if defined(RCC_CCIPR_I2C2SEL)
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U))                                                  /*!< PCLK1 clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
+#endif /* RCC_CCIPR_I2C2SEL */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U))                                                  /*!< PCLK1 clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U))                                                    /*!< PCLK1 clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      RCC_CCIPR_LPTIM1SEL                                    /*!< PCLK1 clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))   /*!< LSE clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1      RCC_CCIPR_LPTIM2SEL                                    /*!< PCLK1 clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))   /*!< LSE clock used as LPTIM2 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1      RCC_CCIPR_SAI1SEL                                    /*!< PLLSAI1 clock used as SAI1 clock source */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2      (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U))   /*!< PLLSAI2 clock used as SAI1 clock source */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_SAI1_CLKSOURCE_PLL          (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U))   /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN          (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U))     /*!< External input clock used as SAI1 clock source */
+
+#if defined(RCC_CCIPR_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1      RCC_CCIPR_SAI2SEL                                    /*!< PLLSAI1 clock used as SAI2 clock source */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2      (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U))   /*!< PLLSAI2 clock used as SAI2 clock source */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_SAI2_CLKSOURCE_PLL          (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U))   /*!< PLL clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PIN          (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U))     /*!< External input clock used as SAI2 clock source */
+#endif /* RCC_CCIPR_SAI2SEL *//**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE  Peripheral SDMMC clock source selection
+  * @{
+  */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_SDMMC1_CLKSOURCE_HSI48      0x00000000U          /*!< HSI48 clock used as SDMMC1 clock source */
+#else
+#define LL_RCC_SDMMC1_CLKSOURCE_NONE       0x00000000U          /*!< No clock used as SDMMC1 clock source */
+#endif
+#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */
+#define LL_RCC_SDMMC1_CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */
+#define LL_RCC_SDMMC1_CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL   /*!< MSI clock used as SDMMC1 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_RNG_CLKSOURCE_HSI48         0x00000000U          /*!< HSI48 clock used as RNG clock source */
+#else
+#define LL_RCC_RNG_CLKSOURCE_NONE          0x00000000U          /*!< No clock used as RNG clock source */
+#endif
+#define LL_RCC_RNG_CLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_MSI           RCC_CCIPR_CLK48SEL   /*!< MSI clock used as RNG clock source */
+/**
+  * @}
+  */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_USB_CLKSOURCE_HSI48         0x00000000U          /*!< HSI48 clock used as USB clock source */
+#else
+#define LL_RCC_USB_CLKSOURCE_NONE          0x00000000U          /*!< No clock used as USB clock source */
+#endif
+#define LL_RCC_USB_CLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_MSI           RCC_CCIPR_CLK48SEL   /*!< MSI clock used as USB clock source */
+/**
+  * @}
+  */
+
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
+  * @{
+  */
+#define LL_RCC_ADC_CLKSOURCE_NONE          0x00000000U          /*!< No clock used as ADC clock source */
+#define LL_RCC_ADC_CLKSOURCE_PLLSAI1       RCC_CCIPR_ADCSEL_0   /*!< PLLSAI1 clock used as ADC clock source */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_ADC_CLKSOURCE_PLLSAI2       RCC_CCIPR_ADCSEL_1   /*!< PLLSAI2 clock used as ADC clock source */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_ADC_CLKSOURCE_SYSCLK        RCC_CCIPR_ADCSEL     /*!< SYSCLK clock used as ADC clock source */
+/**
+  * @}
+  */
+
+#if defined(SWPMI1)
+/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE  Peripheral SWPMI1 clock source selection
+  * @{
+  */
+#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1      0x00000000U          /*!< PCLK1 used as SWPMI1 clock source */
+#define LL_RCC_SWPMI1_CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL  /*!< HSI used as SWPMI1 clock source */
+/**
+  * @}
+  */
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM1 clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2      0x00000000U          /*!< PCLK2 used as DFSDM1 clock source */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK     RCC_CCIPR_DFSDM1SEL  /*!< SYSCLK used as DFSDM1 clock source */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 */
+
+/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
+#define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
+#if defined(RCC_CCIPR_USART3SEL)
+#define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
+#endif /* RCC_CCIPR_USART3SEL */
+/**
+  * @}
+  */
+
+#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
+/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
+  * @{
+  */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE             RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE             RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+  * @}
+  */
+#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
+
+/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
+#if defined(RCC_CCIPR_I2C2SEL)
+#define LL_RCC_I2C2_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
+#endif /* RCC_CCIPR_I2C2SEL */
+#define LL_RCC_I2C3_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE              ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+#define LL_RCC_LPTIM2_CLKSOURCE            RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAI1  Peripheral SAI get clock source
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
+#if defined(RCC_CCIPR_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE              RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */
+#endif /* RCC_CCIPR_SAI2SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC1  Peripheral SDMMC get clock source
+  * @{
+  */
+#define LL_RCC_SDMMC1_CLKSOURCE            RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
+/**
+  * @}
+  */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
+  * @{
+  */
+#define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
+/**
+  * @}
+  */
+
+#if defined(SWPMI1)
+/** @defgroup RCC_LL_EC_SWPMI1  Peripheral SWPMI1 get clock source
+  * @{
+  */
+#define LL_RCC_SWPMI1_CLKSOURCE            RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */
+/**
+  * @}
+  */
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM1  Peripheral DFSDM1 get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE            RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLSAI1 and PLLSAI2 entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_NONE              0x00000000U             /*!< No clock */
+#define LL_RCC_PLLSOURCE_MSI               RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLSAI1 and PLLSAI2 division factor
+  * @{
+  */
+#define LL_RCC_PLLM_DIV_1                  0x00000000U                                 /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 */
+#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_0)                        /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 */
+#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1)                        /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 */
+#define LL_RCC_PLLM_DIV_4                  ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 */
+#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2)                        /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 */
+#define LL_RCC_PLLM_DIV_6                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 */
+#define LL_RCC_PLLM_DIV_7                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 */
+#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM)                          /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
+  * @{
+  */
+#define LL_RCC_PLLR_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_0)   /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
+#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_1)   /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
+#define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)     /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
+  * @{
+  */
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+#define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLPDIV_1)                                              /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 3 */
+#define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLPDIV_2)                                              /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 5 */
+#define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2)  /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLPDIV_3)                                              /*!< Main PLL division factor for PLLP output by 8 */
+#define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 9 */
+#define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 10 */
+#define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)) /*!< Main PLL division factor for PLLP output by 11 */
+#define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 12 */
+#define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3)  /*!< Main PLL division factor for PLLP output by 13 */
+#define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3)  /*!< Main PLL division factor for PLLP output by 14 */
+#define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 15 */
+#define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLPDIV_4)                                              /*!< Main PLL division factor for PLLP output by 16 */
+#define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 17 */
+#define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 18 */
+#define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)) /*!< Main PLL division factor for PLLP output by 19 */
+#define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 20 */
+#define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 21 */
+#define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 22 */
+#define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 23 */
+#define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 24 */
+#define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 25 */
+#define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 26 */
+#define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 27 */
+#define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 28 */
+#define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 29 */
+#define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 30 */
+#define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 31 */
+#else
+#define LL_RCC_PLLP_DIV_7                  0x00000000U            /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLP)     /*!< Main PLL division factor for PLLP output by 17 */
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
+  * @{
+  */
+#define LL_RCC_PLLQ_DIV_2                  0x00000000U             /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_0)    /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_1)    /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)      /*!< Main PLL division factor for PLLQ output by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSAI1Q  PLLSAI1 division factor (PLLSAI1Q)
+  * @{
+  */
+#define LL_RCC_PLLSAI1Q_DIV_2              0x00000000U                  /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
+#define LL_RCC_PLLSAI1Q_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
+#define LL_RCC_PLLSAI1Q_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
+#define LL_RCC_PLLSAI1Q_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1Q)   /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSAI1P  PLLSAI1 division factor (PLLSAI1P)
+  * @{
+  */
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+#define LL_RCC_PLLSAI1P_DIV_2              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
+#define LL_RCC_PLLSAI1P_DIV_3              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
+#define LL_RCC_PLLSAI1P_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
+#define LL_RCC_PLLSAI1P_DIV_5              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
+#define LL_RCC_PLLSAI1P_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
+#define LL_RCC_PLLSAI1P_DIV_7              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
+#define LL_RCC_PLLSAI1P_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
+#define LL_RCC_PLLSAI1P_DIV_9              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
+#define LL_RCC_PLLSAI1P_DIV_10             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
+#define LL_RCC_PLLSAI1P_DIV_11             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
+#define LL_RCC_PLLSAI1P_DIV_12             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
+#define LL_RCC_PLLSAI1P_DIV_13             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
+#define LL_RCC_PLLSAI1P_DIV_14             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
+#define LL_RCC_PLLSAI1P_DIV_15             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
+#define LL_RCC_PLLSAI1P_DIV_16             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
+#define LL_RCC_PLLSAI1P_DIV_17             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
+#define LL_RCC_PLLSAI1P_DIV_18             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
+#define LL_RCC_PLLSAI1P_DIV_19             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
+#define LL_RCC_PLLSAI1P_DIV_20             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
+#define LL_RCC_PLLSAI1P_DIV_21             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
+#define LL_RCC_PLLSAI1P_DIV_22             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
+#define LL_RCC_PLLSAI1P_DIV_23             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
+#define LL_RCC_PLLSAI1P_DIV_24             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
+#define LL_RCC_PLLSAI1P_DIV_25             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
+#define LL_RCC_PLLSAI1P_DIV_26             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
+#define LL_RCC_PLLSAI1P_DIV_27             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
+#define LL_RCC_PLLSAI1P_DIV_28             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
+#define LL_RCC_PLLSAI1P_DIV_29             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
+#define LL_RCC_PLLSAI1P_DIV_30             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
+#define LL_RCC_PLLSAI1P_DIV_31             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
+#else
+#define LL_RCC_PLLSAI1P_DIV_7              0x00000000U                /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
+#define LL_RCC_PLLSAI1P_DIV_17             (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSAI1R  PLLSAI1 division factor (PLLSAI1R)
+  * @{
+  */
+#define LL_RCC_PLLSAI1R_DIV_2              0x00000000U                  /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
+#define LL_RCC_PLLSAI1R_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
+#define LL_RCC_PLLSAI1R_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
+#define LL_RCC_PLLSAI1R_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1R)   /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI2P  PLLSAI2 division factor (PLLSAI2P)
+  * @{
+  */
+#define LL_RCC_PLLSAI2P_DIV_7              0x00000000U                /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
+#define LL_RCC_PLLSAI2P_DIV_17             (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSAI2R  PLLSAI2 division factor (PLLSAI2R)
+  * @{
+  */
+#define LL_RCC_PLLSAI2R_DIV_2              0x00000000U                  /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */
+#define LL_RCC_PLLSAI2R_DIV_4              (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */
+#define LL_RCC_PLLSAI2R_DIV_6              (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */
+#define LL_RCC_PLLSAI2R_DIV_8              (RCC_PLLSAI2CFGR_PLLSAI2R)   /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/** @defgroup RCC_LL_EC_MSIRANGESEL  MSI clock range selection
+  * @{
+  */
+#define LL_RCC_MSIRANGESEL_STANDBY         0U                  /*!< MSI Range is provided by MSISRANGE */
+#define LL_RCC_MSIRANGESEL_RUN             1U                  /*!< MSI Range is provided by MSIRANGE */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+*/
+#if defined(DFSDM1_Channel0)
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK       LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+#define LL_RCC_DFSDM_CLKSOURCE_PCLK        LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK      LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+#define LL_RCC_DFSDM_CLKSOURCE             LL_RCC_DFSDM1_CLKSOURCE
+#endif /* DFSDM1_Channel0 */
+#if defined(SWPMI1)
+#define LL_RCC_SWPMI1_CLKSOURCE_PCLK       LL_RCC_SWPMI1_CLKSOURCE_PCLK1
+#endif /* SWPMI1 */
+/**
+@endcond
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency on system domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLN__ Between 8 and 86
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_8
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+                   ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
+
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLN__ Between 8 and 86
+  * @param  __PLLP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_3
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_5
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLP_DIV_9
+  *         @arg @ref LL_RCC_PLLP_DIV_10
+  *         @arg @ref LL_RCC_PLLP_DIV_11
+  *         @arg @ref LL_RCC_PLLP_DIV_12
+  *         @arg @ref LL_RCC_PLLP_DIV_13
+  *         @arg @ref LL_RCC_PLLP_DIV_14
+  *         @arg @ref LL_RCC_PLLP_DIV_15
+  *         @arg @ref LL_RCC_PLLP_DIV_16
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  *         @arg @ref LL_RCC_PLLP_DIV_18
+  *         @arg @ref LL_RCC_PLLP_DIV_19
+  *         @arg @ref LL_RCC_PLLP_DIV_20
+  *         @arg @ref LL_RCC_PLLP_DIV_21
+  *         @arg @ref LL_RCC_PLLP_DIV_22
+  *         @arg @ref LL_RCC_PLLP_DIV_23
+  *         @arg @ref LL_RCC_PLLP_DIV_24
+  *         @arg @ref LL_RCC_PLLP_DIV_25
+  *         @arg @ref LL_RCC_PLLP_DIV_26
+  *         @arg @ref LL_RCC_PLLP_DIV_27
+  *         @arg @ref LL_RCC_PLLP_DIV_28
+  *         @arg @ref LL_RCC_PLLP_DIV_29
+  *         @arg @ref LL_RCC_PLLP_DIV_30
+  *         @arg @ref LL_RCC_PLLP_DIV_31
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+                   ((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos))
+
+#else
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLN__ Between 8 and 86
+  * @param  __PLLP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+                   (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
+
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLN__ Between 8 and 86
+  * @param  __PLLQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+                   ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
+
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLSAI1 frequency used for SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLSAI1N__ Between 8 and 86
+  * @param  __PLLSAI1P__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
+  * @retval PLLSAI1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
+                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+                    ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos))
+#else
+/**
+  * @brief  Helper macro to calculate the PLLSAI1 frequency used for SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLSAI1N__ Between 8 and 86
+  * @param  __PLLSAI1P__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
+  * @retval PLLSAI1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
+                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+                    (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+/**
+  * @brief  Helper macro to calculate the PLLSAI1 frequency used on 48M domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLSAI1N__ Between 8 and 86
+  * @param  __PLLSAI1Q__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+  * @retval PLLSAI1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
+                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+                    ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
+
+/**
+  * @brief  Helper macro to calculate the PLLSAI1 frequency used on ADC domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLSAI1N__ Between 8 and 86
+  * @param  __PLLSAI1R__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
+  * @retval PLLSAI1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
+                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+                    ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
+
+/**
+  * @brief  Helper macro to calculate the PLLSAI2 frequency used for SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLSAI2N__ Between 8 and 86
+  * @param  __PLLSAI2P__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17
+  * @retval PLLSAI2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
+                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
+                    (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
+/**
+  * @brief  Helper macro to calculate the PLLSAI2 frequency used on ADC domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  __PLLSAI2N__ Between 8 and 86
+  * @param  __PLLSAI2R__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8
+  * @retval PLLSAI2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
+                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
+                    ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
+
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
+  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
+
+/**
+  * @brief  Helper macro to calculate the MSI frequency (in Hz)
+  * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
+  * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
+  *        __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
+  *        else by LL_RCC_MSI_GetRange()
+  *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+  *              (LL_RCC_MSI_IsEnabledRangeSelect()?
+  *               LL_RCC_MSI_GetRange():
+  *               LL_RCC_MSI_GetRangeAfterStandby()))
+  * @param  __MSISEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MSIRANGESEL_STANDBY
+  *         @arg @ref LL_RCC_MSIRANGESEL_RUN
+  * @param  __MSIRANGE__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MSIRANGE_0
+  *         @arg @ref LL_RCC_MSIRANGE_1
+  *         @arg @ref LL_RCC_MSIRANGE_2
+  *         @arg @ref LL_RCC_MSIRANGE_3
+  *         @arg @ref LL_RCC_MSIRANGE_4
+  *         @arg @ref LL_RCC_MSIRANGE_5
+  *         @arg @ref LL_RCC_MSIRANGE_6
+  *         @arg @ref LL_RCC_MSIRANGE_7
+  *         @arg @ref LL_RCC_MSIRANGE_8
+  *         @arg @ref LL_RCC_MSIRANGE_9
+  *         @arg @ref LL_RCC_MSIRANGE_10
+  *         @arg @ref LL_RCC_MSIRANGE_11
+  *         @arg @ref LL_RCC_MSISRANGE_4
+  *         @arg @ref LL_RCC_MSISRANGE_5
+  *         @arg @ref LL_RCC_MSISRANGE_6
+  *         @arg @ref LL_RCC_MSISRANGE_7
+  * @retval MSI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)   (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
+                           (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
+                           (MSIRangeTable[(__MSIRANGE__) >> 4U]))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI even in stop mode
+  * @note HSI oscillator is forced ON even in Stop mode
+  * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Disable HSI in stop mode
+  * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+  * @brief  Enable HSI Automatic from stop mode
+  * @rmtoll CR           HSIASFS       LL_RCC_HSI_EnableAutoFromStop
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIASFS);
+}
+
+/**
+  * @brief  Disable HSI Automatic from stop mode
+  * @rmtoll CR           HSIASFS       LL_RCC_HSI_DisableAutoFromStop
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
+}
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 16, which, when added to the HSICAL value,
+  *       should trim the HSI to 16 MHz +/- 1 %
+  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value Between Min_Data = 0 and Max_Data = 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval Between Min_Data = 0 and Max_Data = 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_HSI48_SUPPORT)
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI48
+  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+  * @brief  Disable HSI48
+  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+  * @brief  Check if HSI48 oscillator Ready
+  * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+  return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
+}
+
+/**
+  * @brief  Get HSI48 Calibration value
+  * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_HSI48_SUPPORT */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+  * @brief  Enable Clock security system on LSE.
+  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+  * @brief  Disable Clock security system on LSE.
+  * @note Clock security system can be disabled only after a LSE
+  *       failure detection. In that case it MUST be disabled by software.
+  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+/**
+  * @brief  Check if CSS on LSE failure Detection
+  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MSI MSI
+  * @{
+  */
+
+/**
+  * @brief  Enable MSI oscillator
+  * @rmtoll CR           MSION         LL_RCC_MSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_MSION);
+}
+
+/**
+  * @brief  Disable MSI oscillator
+  * @rmtoll CR           MSION         LL_RCC_MSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_MSION);
+}
+
+/**
+  * @brief  Check if MSI oscillator Ready
+  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
+}
+
+/**
+  * @brief  Enable MSI PLL-mode (Hardware auto calibration with LSE)
+  * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
+  *       and ready (LSERDY set by hardware)
+  * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
+  *       ready
+  * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_EnablePLLMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+  * @brief  Disable MSI-PLL mode
+  * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
+  *       the Clock Security System on LSE detects a LSE failure
+  * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_DisablePLLMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+  * @brief  Enable MSI clock range selection with MSIRANGE register
+  * @note Write 0 has no effect. After a standby or a reset
+  *       MSIRGSEL is at 0 and the MSI range value is provided by
+  *       MSISRANGE
+  * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_EnableRangeSelection
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
+}
+
+/**
+  * @brief  Check if MSI clock range is selected with MSIRANGE register
+  * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_IsEnabledRangeSelect
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
+}
+
+/**
+  * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
+  * @rmtoll CR           MSIRANGE      LL_RCC_MSI_SetRange
+  * @param  Range This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MSIRANGE_0
+  *         @arg @ref LL_RCC_MSIRANGE_1
+  *         @arg @ref LL_RCC_MSIRANGE_2
+  *         @arg @ref LL_RCC_MSIRANGE_3
+  *         @arg @ref LL_RCC_MSIRANGE_4
+  *         @arg @ref LL_RCC_MSIRANGE_5
+  *         @arg @ref LL_RCC_MSIRANGE_6
+  *         @arg @ref LL_RCC_MSIRANGE_7
+  *         @arg @ref LL_RCC_MSIRANGE_8
+  *         @arg @ref LL_RCC_MSIRANGE_9
+  *         @arg @ref LL_RCC_MSIRANGE_10
+  *         @arg @ref LL_RCC_MSIRANGE_11
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
+}
+
+/**
+  * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
+  * @rmtoll CR           MSIRANGE      LL_RCC_MSI_GetRange
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_MSIRANGE_0
+  *         @arg @ref LL_RCC_MSIRANGE_1
+  *         @arg @ref LL_RCC_MSIRANGE_2
+  *         @arg @ref LL_RCC_MSIRANGE_3
+  *         @arg @ref LL_RCC_MSIRANGE_4
+  *         @arg @ref LL_RCC_MSIRANGE_5
+  *         @arg @ref LL_RCC_MSIRANGE_6
+  *         @arg @ref LL_RCC_MSIRANGE_7
+  *         @arg @ref LL_RCC_MSIRANGE_8
+  *         @arg @ref LL_RCC_MSIRANGE_9
+  *         @arg @ref LL_RCC_MSIRANGE_10
+  *         @arg @ref LL_RCC_MSIRANGE_11
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
+}
+
+/**
+  * @brief  Configure MSI range used after standby
+  * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_SetRangeAfterStandby
+  * @param  Range This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MSISRANGE_4
+  *         @arg @ref LL_RCC_MSISRANGE_5
+  *         @arg @ref LL_RCC_MSISRANGE_6
+  *         @arg @ref LL_RCC_MSISRANGE_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
+{
+  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
+}
+
+/**
+  * @brief  Get MSI range used after standby
+  * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_GetRangeAfterStandby
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_MSISRANGE_4
+  *         @arg @ref LL_RCC_MSISRANGE_5
+  *         @arg @ref LL_RCC_MSISRANGE_6
+  *         @arg @ref LL_RCC_MSISRANGE_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
+}
+
+/**
+  * @brief  Get MSI Calibration value
+  * @note When MSITRIM is written, MSICAL is updated with the sum of
+  *       MSITRIM and the factory trim value
+  * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
+  * @retval Between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
+}
+
+/**
+  * @brief  Set MSI Calibration trimming
+  * @note user-programmable trimming value that is added to the MSICAL
+  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
+  * @param  Value Between Min_Data = 0 and Max_Data = 255
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
+}
+
+/**
+  * @brief  Get MSI Calibration trimming
+  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
+  * @retval Between 0 and 255
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSCO LSCO
+  * @{
+  */
+
+/**
+  * @brief  Enable Low speed clock
+  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+  * @brief  Disable Low speed clock
+  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+  * @brief  Configure Low speed clock selection
+  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
+}
+
+/**
+  * @brief  Get Low speed clock selection
+  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+  * @brief  Set Clock After Wake-Up From Stop mode
+  * @rmtoll CFGR         STOPWUCK      LL_RCC_SetClkAfterWakeFromStop
+  * @param  Clock This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
+}
+
+/**
+  * @brief  Get Clock After Wake-Up From Stop mode
+  * @rmtoll CFGR         STOPWUCK      LL_RCC_GetClkAfterWakeFromStop
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
+  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_MSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *
+  *         (*) value not defined in all devices.
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_8
+  *         @arg @ref LL_RCC_MCO1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
+}
+
+#if defined(UART4) || defined(UART5)
+/**
+  * @brief  Configure UARTx clock source
+  * @rmtoll CCIPR        UARTxSEL      LL_RCC_SetUARTClockSource
+  * @param  UARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
+}
+#endif /* UART4 || UART5 */
+
+/**
+  * @brief  Configure LPUART1x clock source
+  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); 
+  MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+  MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
+}
+
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll CCIPR        SAIxSEL       LL_RCC_SetSAIClockSource
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+  MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+}
+
+/**
+  * @brief  Configure SDMMC1 clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetSDMMCClockSource
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
+}
+
+/**
+  * @brief  Configure RNG clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetRNGClockSource
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
+}
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+  * @brief  Configure USB clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetUSBClockSource
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+  * @brief  Configure ADC clock source
+  * @rmtoll CCIPR        ADCSEL        LL_RCC_SetADCClockSource
+  * @param  ADCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
+}
+
+#if defined(SWPMI1)
+/**
+  * @brief  Configure SWPMI clock source
+  * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_SetSWPMIClockSource
+  * @param  SWPMIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
+}
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Configure DFSDM Kernel clock source
+  * @rmtoll CCIPR        DFSDM1SEL     LL_RCC_SetDFSDMClockSource
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
+}
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
+  * @param  USARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
+}
+
+#if defined(UART4) || defined(UART5)
+/**
+  * @brief  Get UARTx clock source
+  * @rmtoll CCIPR        UARTxSEL      LL_RCC_GetUARTClockSource
+  * @param  UARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
+}
+#endif /* UART4 || UART5 */
+
+/**
+  * @brief  Get LPUARTx clock source
+  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
+  * @param  LPUARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
+  * @param  I2Cx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+  *
+  *         (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); 
+  return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x0000FF0000U) >> 16U)) >> ((I2Cx & 0x0000FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
+}
+
+/**
+  * @brief  Get LPTIMx clock source
+  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
+  * @param  LPTIMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U | LPTIMx);
+}
+
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll CCIPR        SAIxSEL       LL_RCC_GetSAIClockSource
+  * @param  SAIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx);
+}
+
+/**
+  * @brief  Get SDMMCx clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetSDMMCClockSource
+  * @param  SDMMCx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
+}
+
+/**
+  * @brief  Get RNGx clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource
+  * @param  RNGx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
+}
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+  * @brief  Get USBx clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
+  * @param  USBx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+  * @brief  Get ADCx clock source
+  * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
+  * @param  ADCx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
+}
+
+#if defined(SWPMI1)
+/**
+  * @brief  Get SWPMIx clock source
+  * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_GetSWPMIClockSource
+  * @param  SPWMIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
+}
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Get DFSDMx Kernel clock source
+  * @rmtoll CCIPR        DFSDM1SEL     LL_RCC_GetDFSDMClockSource
+  * @param  DFSDMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
+}
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *       set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Enable PLL
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Disable PLL
+  * @note Cannot be disabled if the PLL clock is used as the system clock
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Check if PLL Ready
+  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+  * @brief  Configure PLL used for SYSCLK Domain
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+/**
+  * @brief  Configure PLL used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note PLLN/PLLP can be written only when PLL is disabled
+  * @note This  can be selected for SAI1 or SAI2 (*)
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLPDIV       LL_RCC_PLL_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_3
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_5
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLP_DIV_9
+  *         @arg @ref LL_RCC_PLLP_DIV_10
+  *         @arg @ref LL_RCC_PLLP_DIV_11
+  *         @arg @ref LL_RCC_PLLP_DIV_12
+  *         @arg @ref LL_RCC_PLLP_DIV_13
+  *         @arg @ref LL_RCC_PLLP_DIV_14
+  *         @arg @ref LL_RCC_PLLP_DIV_15
+  *         @arg @ref LL_RCC_PLLP_DIV_16
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  *         @arg @ref LL_RCC_PLLP_DIV_18
+  *         @arg @ref LL_RCC_PLLP_DIV_19
+  *         @arg @ref LL_RCC_PLLP_DIV_20
+  *         @arg @ref LL_RCC_PLLP_DIV_21
+  *         @arg @ref LL_RCC_PLLP_DIV_22
+  *         @arg @ref LL_RCC_PLLP_DIV_23
+  *         @arg @ref LL_RCC_PLLP_DIV_24
+  *         @arg @ref LL_RCC_PLLP_DIV_25
+  *         @arg @ref LL_RCC_PLLP_DIV_26
+  *         @arg @ref LL_RCC_PLLP_DIV_27
+  *         @arg @ref LL_RCC_PLLP_DIV_28
+  *         @arg @ref LL_RCC_PLLP_DIV_29
+  *         @arg @ref LL_RCC_PLLP_DIV_30
+  *         @arg @ref LL_RCC_PLLP_DIV_31
+  * @retval None
+  */
+#else
+/**
+  * @brief  Configure PLL used for SAI domain clock
+  * @note   PLL Source and PLLM Divider can be written only when PLL,
+  *         PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note   PLLN/PLLP can be written only when PLL is disabled
+  * @note   This  can be selected for SAI1 or SAI2 (*)
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  * @retval None
+  */
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+}
+
+/**
+  * @brief  Configure PLL used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note PLLN/PLLQ can be written only when PLL is disabled
+  * @note This  can be selected for USB, RNG, SDMMC
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
+}
+
+/**
+  * @brief  Get Main PLL multiplication factor for VCO
+  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
+  * @retval Between 8 and 86
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
+}
+
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+/**
+  * @brief  Get Main PLL division factor for PLLP
+  * @note   used for PLLSAI3CLK (SAI1 and SAI2 clock)
+  * @rmtoll PLLCFGR      PLLPDIV       LL_RCC_PLL_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_3
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_5
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLP_DIV_9
+  *         @arg @ref LL_RCC_PLLP_DIV_10
+  *         @arg @ref LL_RCC_PLLP_DIV_11
+  *         @arg @ref LL_RCC_PLLP_DIV_12
+  *         @arg @ref LL_RCC_PLLP_DIV_13
+  *         @arg @ref LL_RCC_PLLP_DIV_14
+  *         @arg @ref LL_RCC_PLLP_DIV_15
+  *         @arg @ref LL_RCC_PLLP_DIV_16
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  *         @arg @ref LL_RCC_PLLP_DIV_18
+  *         @arg @ref LL_RCC_PLLP_DIV_19
+  *         @arg @ref LL_RCC_PLLP_DIV_20
+  *         @arg @ref LL_RCC_PLLP_DIV_21
+  *         @arg @ref LL_RCC_PLLP_DIV_22
+  *         @arg @ref LL_RCC_PLLP_DIV_23
+  *         @arg @ref LL_RCC_PLLP_DIV_24
+  *         @arg @ref LL_RCC_PLLP_DIV_25
+  *         @arg @ref LL_RCC_PLLP_DIV_26
+  *         @arg @ref LL_RCC_PLLP_DIV_27
+  *         @arg @ref LL_RCC_PLLP_DIV_28
+  *         @arg @ref LL_RCC_PLLP_DIV_29
+  *         @arg @ref LL_RCC_PLLP_DIV_30
+  *         @arg @ref LL_RCC_PLLP_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
+}
+#else
+/**
+  * @brief  Get Main PLL division factor for PLLP
+  * @note   used for PLLSAI3CLK (SAI1 and SAI2 clock)
+  * @rmtoll PLLCFGR      PLLP          LL_RCC_PLL_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+}
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+
+/**
+  * @brief  Get Main PLL division factor for PLLQ
+  * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
+  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLR
+  * @note used for PLLCLK (system clock)
+  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+  * @brief  Get Division factor for the main PLL and other PLL
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+/**
+  * @brief  Enable PLL output mapped on SAI domain clock
+  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_SAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+  * @brief  Disable PLL output mapped on SAI domain clock
+  * @note Cannot be disabled if the PLL clock is used as the system
+  *       clock
+  * @note In order to save power, when the PLLCLK  of the PLL is
+  *       not used,  should be 0
+  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_SAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+  * @brief  Enable PLL output mapped on 48MHz domain clock
+  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_48M
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+  * @brief  Disable PLL output mapped on 48MHz domain clock
+  * @note Cannot be disabled if the PLL clock is used as the system
+  *       clock
+  * @note In order to save power, when the PLLCLK  of the PLL is
+  *       not used,  should be 0
+  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_48M
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+  * @brief  Enable PLL output mapped on SYSCLK domain
+  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+  * @brief  Disable PLL output mapped on SYSCLK domain
+  * @note Cannot be disabled if the PLL clock is used as the system
+  *       clock
+  * @note In order to save power, when the PLLCLK  of the PLL is
+  *       not used, Main PLL  should be 0
+  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLSAI1
+  * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
+}
+
+/**
+  * @brief  Disable PLLSAI1
+  * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
+}
+
+/**
+  * @brief  Check if PLLSAI1 Ready
+  * @rmtoll CR           PLLSAI1RDY    LL_RCC_PLLSAI1_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
+}
+
+/**
+  * @brief  Configure PLLSAI1 used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
+  * @note This  can be selected for USB, RNG, SDMMC
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_48M\n
+  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_48M\n
+  *         PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
+}
+
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+  * @brief  Configure PLLSAI1 used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
+  * @note This  can be selected for SAI1 or SAI2 (*)
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+  *         PLLSAI1CFGR  PLLSAI1PDIV   LL_RCC_PLLSAI1_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
+  * @retval None
+  */
+#else
+/**
+  * @brief  Configure PLLSAI1 used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
+  * @note This  can be selected for SAI1 or SAI2 (*)
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+  *         PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
+  * @retval None
+  */
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
+             PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+#else
+  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+}
+
+/**
+  * @brief  Configure PLLSAI1 used for ADC domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI1 and PLLSAI2 (*) are disabled
+  * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
+  * @note This  can be selected for ADC
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+  *         PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_ConfigDomain_ADC
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
+}
+
+/**
+  * @brief  Get SAI1PLL multiplication factor for VCO
+  * @rmtoll PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_GetN
+  * @retval Between 8 and 86
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
+}
+
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+  * @brief  Get SAI1PLL division factor for PLLSAI1P
+  * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
+  * @rmtoll PLLSAI1CFGR  PLLSAI1PDIV      LL_RCC_PLLSAI1_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
+  */
+#else
+/**
+  * @brief  Get SAI1PLL division factor for PLLSAI1P
+  * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
+  * @rmtoll PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
+  */
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
+{
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
+#else
+  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+}
+
+/**
+  * @brief  Get SAI1PLL division factor for PLLSAI1Q
+  * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
+  * @rmtoll PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
+}
+
+/**
+  * @brief  Get PLLSAI1 division factor for PLLSAIR
+  * @note used for PLLADC1CLK (ADC clock)
+  * @rmtoll PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
+}
+
+/**
+  * @brief  Enable PLLSAI1 output mapped on SAI domain clock
+  * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_EnableDomain_SAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
+{
+  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
+}
+
+/**
+  * @brief  Disable PLLSAI1 output mapped on SAI domain clock
+  * @note In order to save power, when  of the PLLSAI1 is
+  *       not used,  should be 0
+  * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_DisableDomain_SAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
+{
+  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
+}
+
+/**
+  * @brief  Enable PLLSAI1 output mapped on 48MHz domain clock
+  * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_EnableDomain_48M
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
+{
+  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
+}
+
+/**
+  * @brief  Disable PLLSAI1 output mapped on 48MHz domain clock
+  * @note In order to save power, when  of the PLLSAI1 is
+  *       not used,  should be 0
+  * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_DisableDomain_48M
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
+{
+  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
+}
+
+/**
+  * @brief  Enable PLLSAI1 output mapped on ADC domain clock
+  * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_EnableDomain_ADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
+{
+  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
+}
+
+/**
+  * @brief  Disable PLLSAI1 output mapped on ADC domain clock
+  * @note In order to save power, when  of the PLLSAI1 is
+  *       not used, Main PLLSAI1  should be 0
+  * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_DisableDomain_ADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
+{
+  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLSAI2
+  * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
+}
+
+/**
+  * @brief  Disable PLLSAI2
+  * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
+}
+
+/**
+  * @brief  Check if PLLSAI2 Ready
+  * @rmtoll CR           PLLSAI2RDY    LL_RCC_PLLSAI2_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
+}
+
+/**
+  * @brief  Configure PLLSAI2 used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI2 and PLLSAI2 are disabled
+  * @note PLLN/PLLP can be written only when PLLSAI2 is disabled
+  * @note This  can be selected for SAI1 or SAI2
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+  *         PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
+}
+
+/**
+  * @brief  Configure PLLSAI2 used for ADC domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLSAI2 and PLLSAI2 are disabled
+  * @note PLLN/PLLR can be written only when PLLSAI2 is disabled
+  * @note This  can be selected for ADC
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_ADC\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_ADC\n
+  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_ADC\n
+  *         PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_ConfigDomain_ADC
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  * @param  PLLN Between 8 and 86
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);
+}
+
+/**
+  * @brief  Get SAI2PLL multiplication factor for VCO
+  * @rmtoll PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_GetN
+  * @retval Between 8 and 86
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
+}
+
+/**
+  * @brief  Get SAI2PLL division factor for PLLSAI2P
+  * @note   used for PLLSAI2CLK (SAI1 or SAI2 clock).
+  * @rmtoll PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7
+  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
+}
+
+/**
+  * @brief  Get SAI2PLL division factor for PLLSAI2R
+  * @note used for PLLADC2CLK (ADC clock)
+  * @rmtoll PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6
+  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
+}
+
+/**
+  * @brief  Enable PLLSAI2 output mapped on SAI domain clock
+  * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_EnableDomain_SAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
+{
+  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
+}
+
+/**
+  * @brief  Disable PLLSAI2 output mapped on SAI domain clock
+  * @note In order to save power, when  of the PLLSAI2 is
+  *       not used,  should be 0
+  * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_DisableDomain_SAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
+{
+  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
+}
+
+/**
+  * @brief  Enable PLLSAI2 output mapped on ADC domain clock
+  * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_EnableDomain_ADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
+{
+  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+
+/**
+  * @brief  Disable PLLSAI2 output mapped on ADC domain clock
+  * @note In order to save power, when  of the PLLSAI2 is
+  *       not used, Main PLLSAI2  should be 0
+  * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_DisableDomain_ADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
+{
+  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+  * @brief  Clear MSI ready interrupt flag
+  * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+  * @brief  Clear PLL ready interrupt flag
+  * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Clear HSI48 ready interrupt flag
+  * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Clear PLLSAI1 ready interrupt flag
+  * @rmtoll CICR         PLLSAI1RDYC   LL_RCC_ClearFlag_PLLSAI1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+  * @brief  Clear PLLSAI1 ready interrupt flag
+  * @rmtoll CICR         PLLSAI2RDYC   LL_RCC_ClearFlag_PLLSAI2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  Clear Clock security system interrupt flag
+  * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_CSSC);
+}
+
+/**
+  * @brief  Clear LSE Clock security system interrupt flag
+  * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
+}
+
+/**
+  * @brief  Check if MSI ready interrupt occurred or not
+  * @rmtoll CIFR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
+}
+
+/**
+  * @brief  Check if PLL ready interrupt occurred or not
+  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Check if HSI48 ready interrupt occurred or not
+  * @rmtoll CIR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Check if PLLSAI1 ready interrupt occurred or not
+  * @rmtoll CIFR         PLLSAI1RDYF   LL_RCC_IsActiveFlag_PLLSAI1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+  * @brief  Check if PLLSAI1 ready interrupt occurred or not
+  * @rmtoll CIFR         PLLSAI2RDYF   LL_RCC_IsActiveFlag_PLLSAI2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  Check if Clock security system interrupt occurred or not
+  * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
+}
+
+/**
+  * @brief  Check if LSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
+}
+
+/**
+  * @brief  Check if RCC flag FW reset is set or not.
+  * @rmtoll CSR          FWRSTF        LL_RCC_IsActiveFlag_FWRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
+  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Low Power reset is set or not.
+  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag is set or not.
+  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Window Watchdog reset is set or not.
+  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Enable MSI ready interrupt
+  * @rmtoll CIER         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Enable PLL ready interrupt
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Enable HSI48 ready interrupt
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Enable PLLSAI1 ready interrupt
+  * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_EnableIT_PLLSAI1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+  * @brief  Enable PLLSAI2 ready interrupt
+  * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_EnableIT_PLLSAI2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  Enable LSE clock security system interrupt
+  * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Disable MSI ready interrupt
+  * @rmtoll CIER         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Disable PLL ready interrupt
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Disable HSI48 ready interrupt
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Disable PLLSAI1 ready interrupt
+  * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_DisableIT_PLLSAI1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+  * @brief  Disable PLLSAI2 ready interrupt
+  * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_DisableIT_PLLSAI2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  Disable LSE clock security system interrupt
+  * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
+}
+
+/**
+  * @brief  Checks if MSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
+}
+
+/**
+  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Checks if PLLSAI1 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_IsEnabledIT_PLLSAI1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
+}
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+  * @brief  Checks if PLLSAI2 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_IsEnabledIT_PLLSAI2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+#if defined(UART4) || defined(UART5)
+uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+#endif /* UART4 || UART5 */
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+#if defined(USB_OTG_FS) || defined(USB)
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB */
+uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+#if defined(SWPMI1)
+uint32_t    LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
+#endif /* SWPMI1 */
+#if defined(DFSDM1_Channel0)
+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM1_Channel0 */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c
new file mode 100755
index 0000000..e1c3b4a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c
@@ -0,0 +1,116 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_rng.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   RNG LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_rng.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @addtogroup RNG_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RNG_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize RNG registers (Registers restored to their default values).
+  * @param  RNGx RNG Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RNG registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+
+  /* Enable RNG reset state */
+  LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
+
+  /* Release RNG from reset state */
+  LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
+
+  return (SUCCESS);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (RNG) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h
new file mode 100755
index 0000000..94325a4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h
@@ -0,0 +1,355 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_rng.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RNG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_RNG_H
+#define __STM32L4xx_LL_RNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RNG)
+
+/** @defgroup RNG_LL RNG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
+  * @{
+  */
+
+/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RNG_ReadReg function
+  * @{
+  */
+#define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
+#define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
+#define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
+#define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
+#define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
+  * @{
+  */
+#define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
+  * @{
+  */
+
+/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RNG register
+  * @param  __INSTANCE__ RNG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RNG register
+  * @param  __INSTANCE__ RNG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
+  * @{
+  */
+/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Enable Random Number Generation
+  * @rmtoll CR           RNGEN         LL_RNG_Enable
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+  * @brief  Disable Random Number Generation
+  * @rmtoll CR           RNGEN         LL_RNG_Disable
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
+{
+  CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+  * @brief  Check if Random Number Generator is enabled
+  * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate if the RNG Data ready Flag is set or not
+  * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
+}
+
+/**
+  * @brief  Indicate if the Clock Error Current Status Flag is set or not
+  * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
+}
+
+/**
+  * @brief  Indicate if the Seed Error Current Status Flag is set or not
+  * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
+}
+
+/**
+  * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
+  * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
+}
+
+/**
+  * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
+  * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
+}
+
+/**
+  * @brief  Clear Clock Error interrupt Status (CEIS) Flag
+  * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
+{
+  WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
+}
+
+/**
+  * @brief  Clear Seed Error interrupt Status (SEIS) Flag
+  * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
+{
+  WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Random Number Generator Interrupt
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_EnableIT
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+  * @brief  Disable Random Number Generator Interrupt
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_DisableIT
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
+{
+  CLEAR_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+  * @brief  Check if Random Number Generator Interrupt is enabled
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_IsEnabledIT
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_Data_Management Data Management
+  * @{
+  */
+
+/**
+  * @brief  Return32-bit Random Number value
+  * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
+  * @param  RNGx RNG Instance
+  * @retval Generated 32-bit random value
+  */
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
+{
+  return (uint32_t)(READ_REG(RNGx->DR));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RNG) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c
new file mode 100755
index 0000000..6c359de
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c
@@ -0,0 +1,897 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_rtc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   RTC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_rtc.h"
+#include "stm32l4xx_ll_cortex.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+  * @{
+  */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
+
+#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_MAY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_JULY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RTC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-Initializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are de-initialized
+  *          - ERROR: RTC registers are not de-initialized
+  */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Reset TR, DR and CR registers */
+    LL_RTC_WriteReg(RTCx, TR,       0x00000000U);
+#if defined(RTC_WAKEUP_SUPPORT)
+    LL_RTC_WriteReg(RTCx, WUTR,     RTC_WUTR_WUT);
+#endif /* RTC_WAKEUP_SUPPORT */
+    LL_RTC_WriteReg(RTCx, DR  ,     (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+    /* Reset All CR bits except CR[2:0] */
+#if defined(RTC_WAKEUP_SUPPORT)
+    LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
+#else
+    LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
+#endif /* RTC_WAKEUP_SUPPORT */
+    LL_RTC_WriteReg(RTCx, PRER,     (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+    LL_RTC_WriteReg(RTCx, ALRMAR,   0x00000000U);
+    LL_RTC_WriteReg(RTCx, ALRMBR,   0x00000000U);
+    LL_RTC_WriteReg(RTCx, SHIFTR,   0x00000000U);
+    LL_RTC_WriteReg(RTCx, CALR,     0x00000000U);
+    LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
+    LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
+
+    /* Reset ISR register and exit initialization mode */
+    LL_RTC_WriteReg(RTCx, ISR,      0x00000000U);
+
+    /* Reset Tamper and alternate functions configuration register */
+    LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U);
+
+    /* Reset Option register */
+    LL_RTC_WriteReg(RTCx, OR, 0x00000000U);
+
+    /* Wait till the RTC RSF flag is set */
+    status = LL_RTC_WaitForSynchro(RTCx);
+  }
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters
+  *         in RTC_InitStruct.
+  * @param  RTCx RTC Instance
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in
+  *         initialization mode only.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized
+  */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+  assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+  assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Set Hour Format */
+    LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+    /* Configure Synchronous and Asynchronous prescaler factor */
+    LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+    LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    status = SUCCESS;
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  /* Set RTC_InitStruct fields to default values */
+  RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
+  RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+  RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+    }
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+                         RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+    }
+    else
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTC);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+  RTC_TimeStruct->Hours      = 0U;
+  RTC_TimeStruct->Minutes    = 0U;
+  RTC_TimeStruct->Seconds    = 0U;
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Day register is configured
+  *          - ERROR: RTC Day register is not configured
+  */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+  {
+    RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+  }
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+    assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+    assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+  }
+  else
+  {
+    assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+    assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+    assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+  }
+  assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+    }
+    else
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTC);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+  * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+  RTC_DateStruct->Day     = 1U;
+  RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
+  RTC_DateStruct->Year    = 0U;
+}
+
+/**
+  * @brief  Set the RTC Alarm A.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMA registers are configured
+  *          - ERROR: ALARMA registers are not configured
+  */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMA_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMA_EnableWeekday(RTCx);
+    LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the RTC Alarm B.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (@ref LL_RTC_ALMB_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMB registers are configured
+  *          - ERROR: ALARMB registers are not configured
+  */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMB_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMB_EnableWeekday(RTCx);
+    LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode
+  */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+  ErrorStatus status = SUCCESS;
+  uint32_t tmp = 0U;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Check if the Initialization mode is set */
+  if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+  {
+    /* Set the Initialization mode */
+    LL_RTC_EnableInitMode(RTCx);
+
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+    while ((timeout != 0U) && (tmp != 1U))
+    {
+      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+      {
+        timeout --;
+      }
+      tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+      if (timeout == 0U)
+      {
+        status = ERROR;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Exit the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts
+  *         counting after 4 RTCCLK cycles.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC exited from in Init mode
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable initialization mode */
+  LL_RTC_DisableInitMode(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar
+  *         initialization, calendar update or after wakeup from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+  ErrorStatus status = SUCCESS;
+  uint32_t tmp = 0U;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Clear RSF flag */
+  LL_RTC_ClearFlag_RS(RTCx);
+
+  /* Wait the registers to be synchronised */
+  tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+  while ((timeout != 0U) && (tmp != 0U))
+  {
+    if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+    {
+      timeout--;
+    }
+    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+    if (timeout == 0U)
+    {
+      status = ERROR;
+    }
+  }
+
+  if (status != ERROR)
+  {
+    timeout = RTC_SYNCHRO_TIMEOUT;
+    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+    while ((timeout != 0U) && (tmp != 1U))
+    {
+      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+      {
+        timeout--;
+      }
+      tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+      if (timeout == 0U)
+      {
+        status = ERROR;
+      }
+    }
+  }
+
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RTC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h
new file mode 100755
index 0000000..a935f5a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h
@@ -0,0 +1,3953 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_rtc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of RTC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_RTC_H
+#define __STM32L4xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_LL_Private_Constants RTC Private Constants
+  * @{
+  */
+/* Masks Definition */
+#define RTC_INIT_MASK                 ((uint32_t)0xFFFFFFFFU)
+#define RTC_RSF_MASK                  ((uint32_t)0xFFFFFF5FU)
+
+/* Write protection defines */
+#define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
+#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
+#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
+
+/* Defines used to combine date & time */
+#define RTC_OFFSET_WEEKDAY            24U
+#define RTC_OFFSET_DAY                16U
+#define RTC_OFFSET_MONTH              8U
+#define RTC_OFFSET_HOUR               16U
+#define RTC_OFFSET_MINUTE             8U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  RTC Init structures definition
+  */
+typedef struct
+{
+  uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
+                              This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
+                              
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetHourFormat(). */
+
+  uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+                              
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetAsynchPrescaler(). */
+
+  uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
+                              
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetSynchPrescaler(). */
+} LL_RTC_InitTypeDef;
+
+/**
+  * @brief  RTC Time structure definition
+  */
+typedef struct
+{
+  uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+                            This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
+
+  uint8_t Hours;       /*!< Specifies the RTC Time Hours.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
+
+  uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
+
+  uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
+} LL_RTC_TimeTypeDef;
+
+/**
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                         This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
+
+  uint8_t Month;    /*!< Specifies the RTC Date Month.
+                         This parameter can be a value of @ref RTC_LL_EC_MONTH
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
+
+  uint8_t Day;      /*!< Specifies the RTC Date Day.
+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
+
+  uint8_t Year;     /*!< Specifies the RTC Date Year.
+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
+} LL_RTC_DateTypeDef;
+
+/**
+  * @brief  RTC Alarm structure definition
+  */
+typedef struct
+{
+  LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A 
+                                      or @ref LL_RTC_ALMB_SetMask() for ALARM B
+                                 */
+
+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
+                                      for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
+                                 */
+
+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
+                                      If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
+                                      for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
+
+                                      If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
+                                      for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
+                                 */
+} LL_RTC_AlarmTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+  * @{
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+  * @{
+  */
+#define LL_RTC_FORMAT_BIN                  0x000000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD                  0x000000001U /*!< BCD data format */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
+  * @{
+  */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
+  * @{
+  */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RTC_ReadReg function
+  * @{
+  */
+#define LL_RTC_ISR_ITSF                    RTC_ISR_ITSF
+#define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
+#define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
+#define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
+#define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
+#define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
+#define LL_RTC_ISR_TSF                     RTC_ISR_TSF
+#define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
+#define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
+#define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
+#define LL_RTC_ISR_INITF                   RTC_ISR_INITF
+#define LL_RTC_ISR_RSF                     RTC_ISR_RSF
+#define LL_RTC_ISR_INITS                   RTC_ISR_INITS
+#define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
+#define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
+#define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
+#define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
+  * @{
+  */
+#define LL_RTC_CR_TSIE                     RTC_CR_TSIE
+#define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
+#define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
+#define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
+#define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE
+#define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE
+#define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE
+#define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
+  * @{
+  */
+#define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
+#define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
+#define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
+#define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thrusday  */
+#define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
+#define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
+#define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_MONTH  MONTH
+  * @{
+  */
+#define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
+#define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
+#define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
+#define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
+#define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
+#define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
+#define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
+#define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
+#define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
+#define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
+#define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
+#define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
+  * @{
+  */
+#define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
+  * @{
+  */
+#define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
+#define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
+#define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
+#define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
+  * @{
+  */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U                          /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
+  * @{
+  */
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
+  * @{
+  */
+#define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
+  * @{
+  */
+#define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
+  * @{
+  */
+#define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
+  * @{
+  */
+#define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
+  * @{
+  */
+#define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
+  * @{
+  */
+#define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
+  * @{
+  */
+#define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
+  * @{
+  */
+#define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER  TAMPER
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+#if defined(RTC_TAMPCR_TAMPPRCH)
+/** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
+  * @{
+  */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
+#define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+  * @}
+  */
+#endif /* RTC_TAMPCR_TAMPPRCH */
+
+#if defined(RTC_TAMPCR_TAMPFLT)
+/** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
+  * @{
+  */
+#define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
+/**
+  * @}
+  */
+#endif /* RTC_TAMPCR_TAMPFLT */
+
+#if defined(RTC_TAMPCR_TAMPFREQ)
+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
+  * @{
+  */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAMPCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
+/**
+  * @}
+  */
+#endif /* RTC_TAMPCR_TAMPFREQ */
+
+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
+  * @{
+  */
+#define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE          (RTC_CR_WUCKSEL_2)                    /*!< ck_spre (usually 1 Hz) clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
+/**
+  * @}
+  */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EC_BKP  BACKUP
+  * @{
+  */
+#define LL_RTC_BKP_DR0                     0x00000000U
+#define LL_RTC_BKP_DR1                     0x00000001U
+#define LL_RTC_BKP_DR2                     0x00000002U
+#define LL_RTC_BKP_DR3                     0x00000003U
+#define LL_RTC_BKP_DR4                     0x00000004U
+#if RTC_BKP_NUMBER > 5
+#define LL_RTC_BKP_DR5                     0x00000005U
+#define LL_RTC_BKP_DR6                     0x00000006U
+#define LL_RTC_BKP_DR7                     0x00000007U
+#define LL_RTC_BKP_DR8                     0x00000008U
+#define LL_RTC_BKP_DR9                     0x00000009U
+#define LL_RTC_BKP_DR10                    0x0000000AU
+#define LL_RTC_BKP_DR11                    0x0000000BU
+#define LL_RTC_BKP_DR12                    0x0000000CU
+#define LL_RTC_BKP_DR13                    0x0000000DU
+#define LL_RTC_BKP_DR14                    0x0000000EU
+#define LL_RTC_BKP_DR15                    0x0000000FU
+#endif /* RTC_BKP_NUMBER > 5 */
+
+#if RTC_BKP_NUMBER > 16
+#define LL_RTC_BKP_DR16                    0x00000010U
+#define LL_RTC_BKP_DR17                    0x00000011U
+#define LL_RTC_BKP_DR18                    0x00000012U
+#define LL_RTC_BKP_DR19                    0x00000013U
+#endif /* RTC_BKP_NUMBER > 16 */
+
+#if RTC_BKP_NUMBER > 20
+#define LL_RTC_BKP_DR20                    0x00000014U
+#define LL_RTC_BKP_DR21                    0x00000015U
+#define LL_RTC_BKP_DR22                    0x00000016U
+#define LL_RTC_BKP_DR23                    0x00000017U
+#define LL_RTC_BKP_DR24                    0x00000018U
+#define LL_RTC_BKP_DR25                    0x00000019U
+#define LL_RTC_BKP_DR26                    0x0000001AU
+#define LL_RTC_BKP_DR27                    0x0000001BU
+#define LL_RTC_BKP_DR28                    0x0000001CU
+#define LL_RTC_BKP_DR29                    0x0000001DU
+#define LL_RTC_BKP_DR30                    0x0000001EU
+#define LL_RTC_BKP_DR31                    0x0000001FU
+#endif /* RTC_BKP_NUMBER > 20 */
+/**
+  * @}
+  */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
+  * @{
+  */
+#define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 1 Hz */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion 
+  * @{
+  */
+#define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
+  * @{
+  */
+#define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+  * @{
+  */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RTC register
+  * @param  __INSTANCE__ RTC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RTC register
+  * @param  __INSTANCE__ RTC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
+  * @param  __VALUE__ Byte to be converted
+  * @retval Converted byte
+  */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
+
+/**
+  * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
+  * @param  __VALUE__ BCD value to be converted
+  * @retval Converted byte
+  */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Date Date helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to retrieve weekday.
+  * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Year in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Year in BCD format (0x00 . . . 0x99)
+  */
+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Month in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Day in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Day in BCD format (0x01 . . . 0x31)
+  */
+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Time Time helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to retrieve hour in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
+  */
+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve minute in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Minutes in BCD format (0x00. . .0x59)
+  */
+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve second in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Seconds in  format (0x00. . .0x59)
+  */
+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+  * @{
+  */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set Hours format (24 hour/day or AM/PM hour format)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll CR           FMT           LL_RTC_SetHourFormat
+  * @param  RTCx RTC Instance
+  * @param  HourFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
+}
+
+/**
+  * @brief  Get Hours format (24 hour/day or AM/PM hour format)
+  * @rmtoll CR           FMT           LL_RTC_GetHourFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
+}
+
+/**
+  * @brief  Select the flag to be routed to RTC_ALARM output
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           OSEL          LL_RTC_SetAlarmOutEvent
+  * @param  RTCx RTC Instance
+  * @param  AlarmOutput This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
+  *         @arg @ref LL_RTC_ALARMOUT_ALMA
+  *         @arg @ref LL_RTC_ALARMOUT_ALMB
+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
+}
+
+/**
+  * @brief  Get the flag to be routed to RTC_ALARM output
+  * @rmtoll CR           OSEL          LL_RTC_GetAlarmOutEvent
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
+  *         @arg @ref LL_RTC_ALARMOUT_ALMA
+  *         @arg @ref LL_RTC_ALARMOUT_ALMB
+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
+}
+
+/**
+  * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
+  * @note   Used only when RTC_ALARM is mapped on PC13
+  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
+  * @param  RTCx RTC Instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
+{
+  MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);
+}
+
+/**
+  * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
+  * @note   used only when RTC_ALARM is mapped on PC13
+  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
+}
+
+/**
+  * @brief  Enable initialization mode
+  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+  *         and prescaler register (RTC_PRER).
+  *         Counters are stopped and start counting from the new value when INIT is reset.
+  * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Set the Initialization mode */
+  WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
+}
+
+/**
+  * @brief  Disable initialization mode (Free running mode)
+  * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Exit Initialization mode */
+  WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
+}
+
+/**
+  * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           POL           LL_RTC_SetOutputPolarity
+  * @param  RTCx RTC Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
+}
+
+/**
+  * @brief  Get Output polarity
+  * @rmtoll CR           POL           LL_RTC_GetOutputPolarity
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
+}
+
+/**
+  * @brief  Enable Bypass the shadow registers
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+  * @brief  Disable Bypass the shadow registers
+  * @rmtoll CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+  * @brief  Check if Shadow registers bypass is enabled or not.
+  * @rmtoll CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
+}
+
+/**
+  * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll CR           REFCKON       LL_RTC_EnableRefClock
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+  * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll CR           REFCKON       LL_RTC_DisableRefClock
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+  * @brief  Set Asynchronous prescaler factor
+  * @rmtoll PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
+  * @param  RTCx RTC Instance
+  * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+  * @brief  Set Synchronous prescaler factor
+  * @rmtoll PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
+  * @param  RTCx RTC Instance
+  * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
+{
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
+}
+
+/**
+  * @brief  Get Asynchronous prescaler factor
+  * @rmtoll PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data = 0 and Max_Data = 0x7F
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+  * @brief  Get Synchronous prescaler factor
+  * @rmtoll PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
+}
+
+/**
+  * @brief  Enable the write protection for RTC registers.
+  * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
+}
+
+/**
+  * @brief  Disable the write protection for RTC registers.
+  * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
+}
+
+/**
+  * @brief  Enable RTC_OUT remap
+  * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);
+}
+
+/**
+  * @brief  Disable RTC_OUT remap
+  * @rmtoll OR           OUT_RMP       LL_RTC_DisableOutRemap
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Time Time
+  * @{
+  */
+
+/**
+  * @brief  Set time format (AM/24-hour or PM notation)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll TR           PM            LL_RTC_TIME_SetFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get time format (AM or PM notation)
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @rmtoll TR           PM            LL_RTC_TIME_GetFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
+}
+
+/**
+  * @brief  Set Hours in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
+  * @rmtoll TR           HT            LL_RTC_TIME_SetHour\n
+  *         TR           HU            LL_RTC_TIME_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
+             (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
+}
+
+/**
+  * @brief  Get Hours in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
+  *       Binary format
+  * @rmtoll TR           HT            LL_RTC_TIME_GetHour\n
+  *         TR           HU            LL_RTC_TIME_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
+  return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
+}
+
+/**
+  * @brief  Set Minutes in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll TR           MNT           LL_RTC_TIME_SetMinute\n
+  *         TR           MNU           LL_RTC_TIME_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
+             (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
+}
+
+/**
+  * @brief  Get Minutes in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
+  *       to Binary format
+  * @rmtoll TR           MNT           LL_RTC_TIME_GetMinute\n
+  *         TR           MNU           LL_RTC_TIME_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
+  return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
+}
+
+/**
+  * @brief  Set Seconds in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll TR           ST            LL_RTC_TIME_SetSecond\n
+  *         TR           SU            LL_RTC_TIME_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
+             (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
+}
+
+/**
+  * @brief  Get Seconds in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
+  *       to Binary format
+  * @rmtoll TR           ST            LL_RTC_TIME_GetSecond\n
+  *         TR           SU            LL_RTC_TIME_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
+  return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
+}
+
+/**
+  * @brief  Set time (hour, minute and second) in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note TimeFormat and Hours should follow the same format
+  * @rmtoll TR           PM            LL_RTC_TIME_Config\n
+  *         TR           HT            LL_RTC_TIME_Config\n
+  *         TR           HU            LL_RTC_TIME_Config\n
+  *         TR           MNT           LL_RTC_TIME_Config\n
+  *         TR           MNU           LL_RTC_TIME_Config\n
+  *         TR           ST            LL_RTC_TIME_Config\n
+  *         TR           SU            LL_RTC_TIME_Config
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+  register uint32_t temp = 0U;
+
+  temp = Format12_24                                                                                    | \
+         (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
+         (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
+  MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
+}
+
+/**
+  * @brief  Get time (hour, minute and second) in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  *       are available to get independently each parameter.
+  * @rmtoll TR           HT            LL_RTC_TIME_Get\n
+  *         TR           HU            LL_RTC_TIME_Get\n
+  *         TR           MNT           LL_RTC_TIME_Get\n
+  *         TR           MNU           LL_RTC_TIME_Get\n
+  *         TR           ST            LL_RTC_TIME_Get\n
+  *         TR           SU            LL_RTC_TIME_Get
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Memorize whether the daylight saving time change has been performed
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           BKP           LL_RTC_TIME_EnableDayLightStore
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+  * @brief  Disable memorization whether the daylight saving time change has been performed.
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           BKP           LL_RTC_TIME_DisableDayLightStore
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+  * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
+  * @rmtoll CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
+}
+
+/**
+  * @brief  Subtract 1 hour (winter time change)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           SUB1H         LL_RTC_TIME_DecHour
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_SUB1H);
+}
+
+/**
+  * @brief  Add 1 hour (summer time change)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ADD1H         LL_RTC_TIME_IncHour
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ADD1H);
+}
+
+/**
+  * @brief  Get Sub second value in the synchronous prescaler counter.
+  * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
+  *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
+  *        SubSeconds value in second fraction ratio with time unit following
+  *        generic formula:
+  *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+  *        This conversion can be performed only if no shift operation is pending
+  *        (ie. SHFP=0) when PREDIV_S >= SS.
+  * @rmtoll SSR          SS            LL_RTC_TIME_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Sub second value (number between 0 and 65535)
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
+}
+
+/**
+  * @brief  Synchronize to a remote clock with a high degree of precision.
+  * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   When REFCKON is set, firmware must not write to Shift control register.
+  * @rmtoll SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
+  *         SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
+  * @param  RTCx RTC Instance
+  * @param  ShiftSecond This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
+  *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
+  * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
+{
+  WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Date Date
+  * @{
+  */
+
+/**
+  * @brief  Set Year in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
+  * @rmtoll DR           YT            LL_RTC_DATE_SetYear\n
+  *         DR           YU            LL_RTC_DATE_SetYear
+  * @param  RTCx RTC Instance
+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
+             (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
+}
+
+/**
+  * @brief  Get Year in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
+  * @rmtoll DR           YT            LL_RTC_DATE_GetYear\n
+  *         DR           YU            LL_RTC_DATE_GetYear
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x99
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
+  return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
+}
+
+/**
+  * @brief  Set Week day
+  * @rmtoll DR           WDU           LL_RTC_DATE_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
+}
+
+/**
+  * @brief  Get Week day
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @rmtoll DR           WDU           LL_RTC_DATE_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
+}
+
+/**
+  * @brief  Set Month in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
+  * @rmtoll DR           MT            LL_RTC_DATE_SetMonth\n
+  *         DR           MU            LL_RTC_DATE_SetMonth
+  * @param  RTCx RTC Instance
+  * @param  Month This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
+             (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
+}
+
+/**
+  * @brief  Get Month in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+  * @rmtoll DR           MT            LL_RTC_DATE_GetMonth\n
+  *         DR           MU            LL_RTC_DATE_GetMonth
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
+  return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
+}
+
+/**
+  * @brief  Set Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll DR           DT            LL_RTC_DATE_SetDay\n
+  *         DR           DU            LL_RTC_DATE_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
+             (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
+}
+
+/**
+  * @brief  Get Day in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll DR           DT            LL_RTC_DATE_GetDay\n
+  *         DR           DU            LL_RTC_DATE_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
+  return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
+}
+
+/**
+  * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
+  * @rmtoll DR           WDU           LL_RTC_DATE_Config\n
+  *         DR           MT            LL_RTC_DATE_Config\n
+  *         DR           MU            LL_RTC_DATE_Config\n
+  *         DR           DT            LL_RTC_DATE_Config\n
+  *         DR           DU            LL_RTC_DATE_Config\n
+  *         DR           YT            LL_RTC_DATE_Config\n
+  *         DR           YU            LL_RTC_DATE_Config
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @param  Month This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
+{
+  register uint32_t temp = 0U;
+
+  temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
+         (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
+         (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
+         (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
+
+  MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
+}
+
+/**
+  * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
+  * and __LL_RTC_GET_DAY are available to get independently each parameter.
+  * @rmtoll DR           WDU           LL_RTC_DATE_Get\n
+  *         DR           MT            LL_RTC_DATE_Get\n
+  *         DR           MU            LL_RTC_DATE_Get\n
+  *         DR           DT            LL_RTC_DATE_Get\n
+  *         DR           DU            LL_RTC_DATE_Get\n
+  *         DR           YT            LL_RTC_DATE_Get\n
+  *         DR           YU            LL_RTC_DATE_Get
+  * @param  RTCx RTC Instance
+  * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_ALARMA ALARMA
+  * @{
+  */
+
+/**
+  * @brief  Enable Alarm A
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+  * @brief  Disable Alarm A
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+  * @brief  Specify the Alarm A masks.
+  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
+  *         ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
+  *         ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
+  *         ALRMAR       MSK1          LL_RTC_ALMA_SetMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMA_MASK_NONE
+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMA_MASK_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
+}
+
+/**
+  * @brief  Get the Alarm A masks.
+  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
+  *         ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
+  *         ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
+  *         ALRMAR       MSK1          LL_RTC_ALMA_GetMask
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMA_MASK_NONE
+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMA_MASK_ALL
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
+}
+
+/**
+  * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+  * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
+  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+  * @brief  Set ALARM A Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_SetDay\n
+  *         ALRMAR       DU            LL_RTC_ALMA_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
+             (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_GetDay\n
+  *         ALRMAR       DU            LL_RTC_ALMA_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
+  return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
+}
+
+/**
+  * @brief  Set ALARM A Weekday
+  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
+}
+
+/**
+  * @brief  Get ALARM A Weekday
+  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+  * @brief  Set Alarm A time format (AM/24-hour or PM notation)
+  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get Alarm A time format (AM or PM notation)
+  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
+}
+
+/**
+  * @brief  Set ALARM A Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_SetHour\n
+  *         ALRMAR       HU            LL_RTC_ALMA_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
+             (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetHour\n
+  *         ALRMAR       HU            LL_RTC_ALMA_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
+  return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
+}
+
+/**
+  * @brief  Set ALARM A Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
+             (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
+  return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
+}
+
+/**
+  * @brief  Set ALARM A Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
+  *         ALRMAR       SU            LL_RTC_ALMA_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
+             (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
+  *         ALRMAR       SU            LL_RTC_ALMA_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+  return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
+}
+
+/**
+  * @brief  Set Alarm A Time (hour, minute and second) in BCD format
+  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       SU            LL_RTC_ALMA_ConfigTime
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+  register uint32_t temp = 0U;
+
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
+         (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
+
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
+}
+
+/**
+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       HU            LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       ST            LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       SU            LL_RTC_ALMA_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Set Alarm A Mask the most-significant bits starting at this bit
+  * @note This register can be written only when ALRAE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Get Alarm A Mask the most-significant bits starting at this bit
+  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Set Alarm A Sub seconds value
+  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
+  * @param  RTCx RTC Instance
+  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
+}
+
+/**
+  * @brief  Get Alarm A Sub seconds value
+  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_ALARMB ALARMB
+  * @{
+  */
+
+/**
+  * @brief  Enable Alarm B
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+  * @brief  Disable Alarm B
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+  * @brief  Specify the Alarm B masks.
+  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
+  *         ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
+  *         ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
+  *         ALRMBR       MSK1          LL_RTC_ALMB_SetMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMB_MASK_NONE
+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMB_MASK_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
+}
+
+/**
+  * @brief  Get the Alarm B masks.
+  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
+  *         ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
+  *         ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
+  *         ALRMBR       MSK1          LL_RTC_ALMB_GetMask
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMB_MASK_NONE
+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMB_MASK_ALL
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
+}
+
+/**
+  * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+  * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
+  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+  * @brief  Set ALARM B Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_SetDay\n
+  *         ALRMBR       DU            LL_RTC_ALMB_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
+             (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_GetDay\n
+  *         ALRMBR       DU            LL_RTC_ALMB_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
+  return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
+}
+
+/**
+  * @brief  Set ALARM B Weekday
+  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
+}
+
+/**
+  * @brief  Get ALARM B Weekday
+  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+  * @brief  Set ALARM B time format (AM/24-hour or PM notation)
+  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get ALARM B time format (AM or PM notation)
+  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
+}
+
+/**
+  * @brief  Set ALARM B Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_SetHour\n
+  *         ALRMBR       HU            LL_RTC_ALMB_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
+             (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetHour\n
+  *         ALRMBR       HU            LL_RTC_ALMB_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
+  return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
+}
+
+/**
+  * @brief  Set ALARM B Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
+             (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
+  return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
+}
+
+/**
+  * @brief  Set ALARM B Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
+  *         ALRMBR       SU            LL_RTC_ALMB_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
+             (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
+  *         ALRMBR       SU            LL_RTC_ALMB_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
+  return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
+}
+
+/**
+  * @brief  Set Alarm B Time (hour, minute and second) in BCD format
+  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       SU            LL_RTC_ALMB_ConfigTime
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+  register uint32_t temp = 0U;
+
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
+         (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
+
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
+}
+
+/**
+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       HU            LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       ST            LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       SU            LL_RTC_ALMB_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Set Alarm B Mask the most-significant bits starting at this bit
+  * @note This register can be written only when ALRBE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Get Alarm B Mask the most-significant bits starting at this bit
+  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Set Alarm B Sub seconds value
+  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
+  * @param  RTCx RTC Instance
+  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
+}
+
+/**
+  * @brief  Get Alarm B Sub seconds value
+  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Timestamp Timestamp
+  * @{
+  */
+
+/**
+  * @brief  Enable internal event timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ITSE          LL_RTC_TS_EnableInternalEvent
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ITSE);
+}
+
+/**
+  * @brief  Disable internal event timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ITSE          LL_RTC_TS_DisableInternalEvent
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
+}
+
+/**
+  * @brief  Enable Timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSE           LL_RTC_TS_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+  * @brief  Disable Timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSE           LL_RTC_TS_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+  * @brief  Set Time-stamp event active edge
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
+  * @rmtoll CR           TSEDGE        LL_RTC_TS_SetActiveEdge
+  * @param  RTCx RTC Instance
+  * @param  Edge This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
+}
+
+/**
+  * @brief  Get Time-stamp event active edge
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSEDGE        LL_RTC_TS_GetActiveEdge
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
+}
+
+/**
+  * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
+  * @rmtoll TSTR         PM            LL_RTC_TS_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
+}
+
+/**
+  * @brief  Get Timestamp Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll TSTR         HT            LL_RTC_TS_GetHour\n
+  *         TSTR         HU            LL_RTC_TS_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll TSTR         MNT           LL_RTC_TS_GetMinute\n
+  *         TSTR         MNU           LL_RTC_TS_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll TSTR         ST            LL_RTC_TS_GetSecond\n
+  *         TSTR         SU            LL_RTC_TS_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+  * @brief  Get Timestamp time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll TSTR         HT            LL_RTC_TS_GetTime\n
+  *         TSTR         HU            LL_RTC_TS_GetTime\n
+  *         TSTR         MNT           LL_RTC_TS_GetTime\n
+  *         TSTR         MNU           LL_RTC_TS_GetTime\n
+  *         TSTR         ST            LL_RTC_TS_GetTime\n
+  *         TSTR         SU            LL_RTC_TS_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR,
+                             RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+  * @brief  Get Timestamp Week day
+  * @rmtoll TSDR         WDU           LL_RTC_TS_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Month in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+  * @rmtoll TSDR         MT            LL_RTC_TS_GetMonth\n
+  *         TSDR         MU            LL_RTC_TS_GetMonth
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll TSDR         DT            LL_RTC_TS_GetDay\n
+  *         TSDR         DU            LL_RTC_TS_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+  * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
+  * and __LL_RTC_GET_DAY are available to get independently each parameter.
+  * @rmtoll TSDR         WDU           LL_RTC_TS_GetDate\n
+  *         TSDR         MT            LL_RTC_TS_GetDate\n
+  *         TSDR         MU            LL_RTC_TS_GetDate\n
+  *         TSDR         DT            LL_RTC_TS_GetDate\n
+  *         TSDR         DU            LL_RTC_TS_GetDate
+  * @param  RTCx RTC Instance
+  * @retval Combination of Weekday, Day and Month
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+  * @brief  Get time-stamp sub second value
+  * @rmtoll TSSSR        SS            LL_RTC_TS_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
+}
+
+#if defined(RTC_TAMPCR_TAMPTS)
+/**
+  * @brief  Activate timestamp on tamper detection event
+  * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_EnableOnTamper
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
+}
+
+/**
+  * @brief  Disable timestamp on tamper detection event
+  * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_DisableOnTamper
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
+}
+#endif /* RTC_TAMPCR_TAMPTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+  * @{
+  */
+
+/**
+  * @brief  Enable RTC_TAMPx input detection
+  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable\n
+  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Enable\n
+  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Enable
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_1 
+  *         @arg @ref LL_RTC_TAMPER_2 
+  *         @arg @ref LL_RTC_TAMPER_3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  SET_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Clear RTC_TAMPx input detection
+  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Disable\n
+  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Disable\n
+  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Disable
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_1 
+  *         @arg @ref LL_RTC_TAMPER_2 
+  *         @arg @ref LL_RTC_TAMPER_3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Enable Tamper mask flag
+  * @note Associated Tamper IT must not enabled when tamper mask is set.
+  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
+  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_EnableMask\n
+  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_EnableMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  SET_BIT(RTCx->TAMPCR, Mask);
+}
+
+/**
+  * @brief  Disable Tamper mask flag
+  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
+  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_DisableMask\n
+  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_DisableMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Mask);
+}
+
+/**
+  * @brief  Enable backup register erase after Tamper event detection
+  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
+  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
+  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Disable backup register erase after Tamper event detection
+  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
+  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
+  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  SET_BIT(RTCx->TAMPCR, Tamper);
+}
+
+#if defined(RTC_TAMPCR_TAMPPUDIS)
+/**
+  * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
+  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
+}
+
+/**
+  * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
+  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
+}
+#endif /* RTC_TAMPCR_TAMPPUDIS */
+
+#if defined(RTC_TAMPCR_TAMPPRCH)
+/**
+  * @brief  Set RTC_TAMPx precharge duration
+  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
+  * @param  RTCx RTC Instance
+  * @param  Duration This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
+{
+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
+}
+
+/**
+  * @brief  Get RTC_TAMPx precharge duration
+  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
+}
+#endif /* RTC_TAMPCR_TAMPPRCH */
+
+#if defined(RTC_TAMPCR_TAMPFLT)
+/**
+  * @brief  Set RTC_TAMPx filter count
+  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
+  * @param  RTCx RTC Instance
+  * @param  FilterCount This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
+{
+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
+}
+
+/**
+  * @brief  Get RTC_TAMPx filter count
+  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
+}
+#endif /* RTC_TAMPCR_TAMPFLT */
+
+#if defined(RTC_TAMPCR_TAMPFREQ)
+/**
+  * @brief  Set Tamper sampling frequency
+  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
+  * @param  RTCx RTC Instance
+  * @param  SamplingFreq This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
+{
+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
+}
+
+/**
+  * @brief  Get Tamper sampling frequency
+  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
+}
+#endif /* RTC_TAMPCR_TAMPFREQ */
+
+/**
+  * @brief  Enable Active level for Tamper input
+  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
+  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
+  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  SET_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Disable Active level for Tamper input
+  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
+  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
+  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 
+  *         
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Wakeup Wakeup
+  * @{
+  */
+
+/**
+  * @brief  Enable Wakeup timer
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+  * @brief  Disable Wakeup timer
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+  * @brief  Check if Wakeup timer is enabled or not
+  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_IsEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
+}
+
+/**
+  * @brief  Select Wakeup clock
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
+  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
+  * @param  RTCx RTC Instance
+  * @param  WakeupClock This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
+}
+
+/**
+  * @brief  Get Wakeup clock
+  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
+}
+
+/**
+  * @brief  Set Wakeup auto-reload value
+  * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
+  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
+  * @param  RTCx RTC Instance
+  * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
+{
+  MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
+}
+
+/**
+  * @brief  Get Wakeup auto-reload value
+  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+  * @}
+  */
+#endif /* RTC_WAKEUP_SUPPORT */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
+  * @param  RTCx RTC Instance
+  * @param  BackupRegister This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  *         @arg @ref LL_RTC_BKP_DR5
+  *         @arg @ref LL_RTC_BKP_DR6
+  *         @arg @ref LL_RTC_BKP_DR7
+  *         @arg @ref LL_RTC_BKP_DR8
+  *         @arg @ref LL_RTC_BKP_DR9
+  *         @arg @ref LL_RTC_BKP_DR10
+  *         @arg @ref LL_RTC_BKP_DR11
+  *         @arg @ref LL_RTC_BKP_DR12
+  *         @arg @ref LL_RTC_BKP_DR13
+  *         @arg @ref LL_RTC_BKP_DR14
+  *         @arg @ref LL_RTC_BKP_DR15
+  *         @arg @ref LL_RTC_BKP_DR16
+  *         @arg @ref LL_RTC_BKP_DR17
+  *         @arg @ref LL_RTC_BKP_DR18
+  *         @arg @ref LL_RTC_BKP_DR19
+  *         @arg @ref LL_RTC_BKP_DR20
+  *         @arg @ref LL_RTC_BKP_DR21
+  *         @arg @ref LL_RTC_BKP_DR22
+  *         @arg @ref LL_RTC_BKP_DR23
+  *         @arg @ref LL_RTC_BKP_DR24
+  *         @arg @ref LL_RTC_BKP_DR25
+  *         @arg @ref LL_RTC_BKP_DR26
+  *         @arg @ref LL_RTC_BKP_DR27
+  *         @arg @ref LL_RTC_BKP_DR28
+  *         @arg @ref LL_RTC_BKP_DR29
+  *         @arg @ref LL_RTC_BKP_DR30
+  *         @arg @ref LL_RTC_BKP_DR31
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
+{
+  register uint32_t tmp = 0U;
+
+  tmp = (uint32_t)(&(RTCx->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
+  * @param  RTCx RTC Instance
+  * @param  BackupRegister This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  *         @arg @ref LL_RTC_BKP_DR5
+  *         @arg @ref LL_RTC_BKP_DR6
+  *         @arg @ref LL_RTC_BKP_DR7
+  *         @arg @ref LL_RTC_BKP_DR8
+  *         @arg @ref LL_RTC_BKP_DR9
+  *         @arg @ref LL_RTC_BKP_DR10
+  *         @arg @ref LL_RTC_BKP_DR11
+  *         @arg @ref LL_RTC_BKP_DR12
+  *         @arg @ref LL_RTC_BKP_DR13
+  *         @arg @ref LL_RTC_BKP_DR14
+  *         @arg @ref LL_RTC_BKP_DR15
+  *         @arg @ref LL_RTC_BKP_DR16
+  *         @arg @ref LL_RTC_BKP_DR17
+  *         @arg @ref LL_RTC_BKP_DR18
+  *         @arg @ref LL_RTC_BKP_DR19
+  *         @arg @ref LL_RTC_BKP_DR20
+  *         @arg @ref LL_RTC_BKP_DR21
+  *         @arg @ref LL_RTC_BKP_DR22
+  *         @arg @ref LL_RTC_BKP_DR23
+  *         @arg @ref LL_RTC_BKP_DR24
+  *         @arg @ref LL_RTC_BKP_DR25
+  *         @arg @ref LL_RTC_BKP_DR26
+  *         @arg @ref LL_RTC_BKP_DR27
+  *         @arg @ref LL_RTC_BKP_DR28
+  *         @arg @ref LL_RTC_BKP_DR29
+  *         @arg @ref LL_RTC_BKP_DR30
+  *         @arg @ref LL_RTC_BKP_DR31
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
+{
+  register uint32_t tmp = 0U;
+
+  tmp = (uint32_t)(&(RTCx->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+  * @{
+  */
+
+/**
+  * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
+  * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           COE           LL_RTC_CAL_SetOutputFreq\n
+  *         CR           COSEL         LL_RTC_CAL_SetOutputFreq
+  * @param  RTCx RTC Instance
+  * @param  Frequency This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
+}
+
+/**
+  * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
+  * @rmtoll CR           COE           LL_RTC_CAL_GetOutputFreq\n
+  *         CR           COSEL         LL_RTC_CAL_GetOutputFreq
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
+}
+
+/**
+  * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+  * @rmtoll CALR         CALP          LL_RTC_CAL_SetPulse
+  * @param  RTCx RTC Instance
+  * @param  Pulse This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
+}
+
+/**
+  * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
+  * @rmtoll CALR         CALP          LL_RTC_CAL_IsPulseInserted
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
+}
+
+/**
+  * @brief  Set the calibration cycle period
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
+  * @rmtoll CALR         CALW8         LL_RTC_CAL_SetPeriod\n
+  *         CALR         CALW16        LL_RTC_CAL_SetPeriod
+  * @param  RTCx RTC Instance
+  * @param  Period This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
+}
+
+/**
+  * @brief  Get the calibration cycle period
+  * @rmtoll CALR         CALW8         LL_RTC_CAL_GetPeriod\n
+  *         CALR         CALW16        LL_RTC_CAL_GetPeriod
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
+}
+
+/**
+  * @brief  Set Calibration minus
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
+  * @rmtoll CALR         CALM          LL_RTC_CAL_SetMinus
+  * @param  RTCx RTC Instance
+  * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
+}
+
+/**
+  * @brief  Get Calibration minus
+  * @rmtoll CALR         CALM          LL_RTC_CAL_GetMinus
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Internal Time-stamp flag
+  * @rmtoll ISR          ITSF          LL_RTC_IsActiveFlag_ITS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF));
+}
+
+/**
+  * @brief  Get Recalibration pending Flag
+  * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Get RTC_TAMP3 detection flag
+  * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Get RTC_TAMP2 detection flag
+  * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Get RTC_TAMP1 detection flag
+  * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Get Time-stamp overflow flag
+  * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
+}
+
+/**
+  * @brief  Get Time-stamp flag
+  * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Get Wakeup timer flag
+  * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Get Alarm B flag
+  * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
+}
+
+/**
+  * @brief  Get Alarm A flag
+  * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
+}
+
+/**
+  * @brief  Clear Internal Time-stamp flag
+  * @rmtoll ISR          ITSF          LL_RTC_ClearFlag_ITS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Clear RTC_TAMP3 detection flag
+  * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Clear RTC_TAMP2 detection flag
+  * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Clear RTC_TAMP1 detection flag
+  * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Clear Time-stamp overflow flag
+  * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Clear Time-stamp flag
+  * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Clear Wakeup timer flag
+  * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Clear Alarm B flag
+  * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Clear Alarm A flag
+  * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Get Initialization flag
+  * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
+}
+
+/**
+  * @brief  Get Registers synchronization flag
+  * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
+}
+
+/**
+  * @brief  Clear Registers synchronization flag
+  * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Get Initialization status flag
+  * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
+}
+
+/**
+  * @brief  Get Shift operation pending flag
+  * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Get Wakeup timer write flag
+  * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Get Alarm B write flag
+  * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
+}
+
+/**
+  * @brief  Get Alarm A write flag
+  * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Time-stamp interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSIE          LL_RTC_EnableIT_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+  * @brief  Disable Time-stamp interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSIE          LL_RTC_DisableIT_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Enable Wakeup timer interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+  * @brief  Disable Wakeup timer interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTIE         LL_RTC_DisableIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Enable Alarm B interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBIE        LL_RTC_EnableIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+  * @brief  Disable Alarm B interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBIE        LL_RTC_DisableIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+  * @brief  Enable Alarm A interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAIE        LL_RTC_EnableIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+  * @brief  Disable Alarm A interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAIE        LL_RTC_DisableIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Enable Tamper 3 interrupt
+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
+}
+
+/**
+  * @brief  Disable Tamper 3 interrupt
+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_DisableIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Enable Tamper 2 interrupt
+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
+}
+
+/**
+  * @brief  Disable Tamper 2 interrupt
+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_DisableIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Enable Tamper 1 interrupt
+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
+}
+
+/**
+  * @brief  Disable Tamper 1 interrupt
+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_DisableIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Enable all Tamper Interrupt
+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
+}
+
+/**
+  * @brief  Disable all Tamper Interrupt
+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_DisableIT_TAMP
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
+}
+
+/**
+  * @brief  Check if  Time-stamp interrupt is enabled or not
+  * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Check if  Wakeup timer interrupt is enabled or not
+  * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Check if  Alarm B interrupt is enabled or not
+  * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
+}
+
+/**
+  * @brief  Check if  Alarm A interrupt is enabled or not
+  * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Check if  Tamper 3 interrupt is enabled or not
+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Check if  Tamper 2 interrupt is enabled or not
+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE));
+
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Check if  Tamper 1 interrupt is enabled or not
+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Check if all the TAMPER interrupts are enabled or not
+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
+void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RTC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c
new file mode 100755
index 0000000..d0434cd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c
@@ -0,0 +1,1502 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_sdmmc.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SDMMC Low Layer HAL module driver.  
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the SDMMC peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                       ##### SDMMC peripheral features #####
+  ==============================================================================        
+    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+         devices.
+    
+    [..] The SDMMC features include the following:
+         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
+             for three different data bus modes: 1-bit (default), 4-bit and 8-bit
+         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
+         (+) Full compliance with SD Memory Card Specifications Version 2.0
+         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
+             different data bus modes: 1-bit (default) and 4-bit
+         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
+             Rev1.1)
+         (+) Data transfer up to 48 MHz for the 8 bit mode
+         (+) Data and command output enable signals to control external bidirectional drivers.
+                 
+   
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers 
+      that interfaces with the SDMMC peripheral.
+      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
+      is used in the device's driver to perform SDMMC operations and functionalities.
+   
+      This driver is almost transparent for the final user, it is only used to implement other
+      functionalities of the external device.
+   
+    [..]
+      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
+          PLL is well configured.
+          The SDMMC peripheral uses two clock signals:
+          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
+          (++) APB2 bus clock (PCLK2)
+       
+          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) for STM32L496xG and STM32L4A6xG
+               Frequency(PCLK2) >= (3 / 4 x Frequency(SDMMC_CK)) otherwise
+  
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+          peripheral.
+
+      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) 
+          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
+                
+      (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
+  
+      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) 
+          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. 
+  
+      (+) When using the DMA mode 
+          (++) Configure the DMA in the MSP layer of the external device
+          (++) Active the needed channel Request 
+          (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
+               __SDMMC_DMA_DISABLE().
+  
+      (+) To control the CPSM (Command Path State Machine) and send 
+          commands to the card use the SDMMC_SendCommand(SDMMCx), 
+          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
+          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according 
+          to the selected command to be sent.
+          The parameters that should be filled are:
+           (++) Command Argument
+           (++) Command Index
+           (++) Command Response type
+           (++) Command Wait
+           (++) CPSM Status (Enable or Disable).
+  
+          -@@- To check if the command is well received, read the SDMMC_CMDRESP
+              register using the SDMMC_GetCommandResponse().
+              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
+              SDMMC_GetResponse() function.
+  
+      (+) To control the DPSM (Data Path State Machine) and send/receive 
+           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), 
+          SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
+  
+    *** Read Operations ***
+    =======================
+    [..]
+      (#) First, user has to fill the data structure (pointer to
+          SDMMC_DataInitTypeDef) according to the selected data type to be received.
+          The parameters that should be filled are:
+           (++) Data TimeOut
+           (++) Data Length
+           (++) Data Block size
+           (++) Data Transfer direction: should be from card (To SDMMC)
+           (++) Data Transfer mode
+           (++) DPSM Status (Enable or Disable)
+                                     
+      (#) Configure the SDMMC resources to receive the data from the card
+          according to selected transfer mode (Refer to Step 8, 9 and 10).
+  
+      (#) Send the selected Read command (refer to step 11).
+                    
+      (#) Use the SDMMC flags/interrupts to check the transfer status.
+  
+    *** Write Operations ***
+    ========================
+    [..]
+     (#) First, user has to fill the data structure (pointer to
+         SDMMC_DataInitTypeDef) according to the selected data type to be received.
+         The parameters that should be filled are:
+          (++) Data TimeOut
+          (++) Data Length
+          (++) Data Block size
+          (++) Data Transfer direction:  should be to card (To CARD)
+          (++) Data Transfer mode
+          (++) DPSM Status (Enable or Disable)
+  
+     (#) Configure the SDMMC resources to send the data to the card according to 
+         selected transfer mode.
+                     
+     (#) Send the selected Write command.
+                    
+     (#) Use the SDMMC flags/interrupts to check the transfer status.
+  
+    *** Command management operations ***
+    =====================================
+    [..]
+     (#) The commands used for Read/Write/Erase operations are managed in 
+         separate functions. 
+         Each function allows to send the needed command with the related argument,
+         then check the response.
+         By the same approach, you could implement a command and check the response.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(SDMMC1)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+  * @brief Low layer module for SD
+  * @{
+  */
+
+#if defined (HAL_SD_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
+static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
+static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
+static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
+static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDMMC according to the specified
+  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
+  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); 
+  assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+  
+  /* Set SDMMC configuration parameters */
+  /* Write to SDMMC CLKCR */
+  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge           |\
+                                              Init.ClockBypass         |\
+                                              Init.ClockPowerSave      |\
+                                              Init.BusWide             |\
+                                              Init.HardwareFlowControl |\
+                                              Init.ClockDiv);  
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### I/O operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+{
+  /* Read data from Rx FIFO */ 
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+{ 
+  /* Write data to FIFO */ 
+  SDMMCx->FIFO = *pWriteData;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set SDMMC Power state to ON. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+{  
+  /* Set power state to ON */ 
+  SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Set SDMMC Power state to OFF. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to OFF */
+  SDMMCx->POWER = (uint32_t)0x00000000;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get SDMMC Power state. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Power status of the controller. The returned value can be one of the 
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON 
+  */
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+}
+
+/**
+  * @brief  Configure the SDMMC command path according to the specified parameters in
+  *         SDMMC_CmdInitTypeDef structure and send the command 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains 
+  *         the configuration information for the SDMMC command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
+  assert_param(IS_SDMMC_RESPONSE(Command->Response));
+  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDMMC_CPSM(Command->CPSM));
+
+  /* Set the SDMMC Argument value */
+  SDMMCx->ARG = Command->Argument;
+
+  /* Set SDMMC command parameters */
+  /* Write to SDMMC CMD register */
+  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, Command->CmdIndex         |\
+                                          Command->Response         |\
+                                          Command->WaitForInterrupt |\
+                                          Command->CPSM); 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return the command index of last command for which response received
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+{
+  return (uint8_t)(SDMMCx->RESPCMD);
+}
+
+
+/**
+  * @brief  Return the response received from the card for the last command
+  * @param  SDMMCx: Pointer to SDMMC register base    
+  * @param  Response: Specifies the SDMMC response register. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_RESP1: Response Register 1
+  *            @arg SDMMC_RESP2: Response Register 2
+  *            @arg SDMMC_RESP3: Response Register 3
+  *            @arg SDMMC_RESP4: Response Register 4  
+  * @retval The Corresponding response register value
+  */
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_RESP(Response));
+  
+  /* Get the response */
+  tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
+  
+  return (*(__IO uint32_t *) tmp);
+}  
+
+/**
+  * @brief  Configure the SDMMC data path according to the specified 
+  *         parameters in the SDMMC_DataInitTypeDef.
+  * @param  SDMMCx: Pointer to SDMMC register base  
+  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDMMC data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
+  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDMMC_DPSM(Data->DPSM));
+
+  /* Set the SDMMC Data TimeOut value */
+  SDMMCx->DTIMER = Data->DataTimeOut;
+
+  /* Set the SDMMC DataLength value */
+  SDMMCx->DLEN = Data->DataLength;
+
+  /* Set the SDMMC data configuration parameters */
+  /* Write to SDMMC DCTRL */
+  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\
+                                              Data->TransferDir   |\
+                                              Data->TransferMode  |\
+                                              Data->DPSM);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->DCOUNT);
+}
+
+/**
+  * @brief  Get the FIFO data
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval Data received
+  */
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDMMCx: Pointer to SDMMC register base   
+  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+  * @retval None
+  */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
+
+  /* Set SDMMC read wait mode */
+  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Commands management functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send the Data Block Lenght command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = 0;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Stop Transfer command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Send CMD12 STOP_TRANSMISSION  */
+  sdmmc_cmdinit.Argument         = 0;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Select Deselect command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  addr: Address of the card to be selected  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Go Idle State command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = 0;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdError(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Operating Condition command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp7(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Application command to verify that that the next command 
+  *         is an application specific com-mand rather than a standard command
+  *         and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  Argument: Command Argument 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  /* If there is a HAL_ERROR, it is a MMC card, else
+  it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating 
+  *         condition register (OCR)
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Bus Width command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  BusWidth: BusWidth
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send SCR command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Send CMD51 SD_APP_SEND_SCR */
+  sdmmc_cmdinit.Argument         = 0;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CID command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Send CMD2 ALL_SEND_CID */
+  sdmmc_cmdinit.Argument         = 0;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  pRCA: Card RCA  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = 0;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status register command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = 0;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Sends host capacity support information and activates the card's 
+  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate = SDMMC_ERROR_NONE;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/  
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+    
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+  
+  do
+  {
+    if (count-- == 0)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+  
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+  
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index  
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+{
+  uint32_t response_r1;
+  uint32_t flags;
+
+  flags = SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The Timeout is expressed in ms */
+  register uint32_t count = Timeout * (SystemCoreClock / 8 /1000);
+  
+  do
+  {
+    if (count-- == 0)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDMMC_GET_FLAG(SDMMCx, flags));
+  
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* Check response received is of desired command */
+  if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+  
+  /* We have received response, retrieve it for analysis  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+  
+  if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+  {
+    return SDMMC_ERROR_ADDR_MISALIGNED;
+  }
+  else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+  {
+    return SDMMC_ERROR_BLOCK_LEN_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+  {
+    return SDMMC_ERROR_ERASE_SEQ_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+  {
+    return SDMMC_ERROR_BAD_ERASE_PARAM;
+  }
+  else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+  {
+    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+  }
+  else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+  {
+    return SDMMC_ERROR_CARD_ECC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+  {
+    return SDMMC_ERROR_CC_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+  {
+    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+  {
+    return SDMMC_ERROR_CID_CSD_OVERWRITE;
+  }
+  else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+  {
+    return SDMMC_ERROR_WP_ERASE_SKIP;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+  {
+    return SDMMC_ERROR_CARD_ECC_DISABLED;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+  {
+    return SDMMC_ERROR_ERASE_RESET;
+  }
+  else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+  {
+    return SDMMC_ERROR_AKE_SEQ_ERR;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+  
+  do
+  {
+    if (count-- == 0)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
+    
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+  
+  do
+  {
+    if (count-- == 0)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
+  
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+ 
+  {  
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+  }
+  
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
+  *         address RCA   
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+  uint32_t response_r1;
+  
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+  
+  do
+  {
+    if (count-- == 0)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
+  
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* Check response received is of desired command */
+  if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+  
+  /* We have received response, retrieve it.  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+  
+  if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+  {
+    *pRCA = (uint16_t) (response_r1 >> 16);
+    
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+  
+  do
+  {
+    if (count-- == 0)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
+
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+  }
+  
+  return SDMMC_ERROR_NONE;
+  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* (HAL_SD_MODULE_ENABLED) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h
new file mode 100755
index 0000000..8b1b018
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h
@@ -0,0 +1,1095 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_sdmmc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of low layer SDMMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_SDMMC_H
+#define __STM32L4xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(SDMMC1)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_Driver
+  * @{
+  */
+
+/** @addtogroup SDMMC_LL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+  * @{
+  */
+  
+/** 
+  * @brief  SDMMC Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
+
+  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
+                                      enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
+
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
+                                      disabled when the bus is idle.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
+
+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
+
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
+
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
+
+}SDMMC_InitTypeDef;
+  
+
+/** 
+  * @brief  SDMMC Command Control structure 
+  */
+typedef struct                                                                                            
+{
+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
+                                     to a card as part of a command message. If a command
+                                     contains an argument, it must be loaded into this register
+                                     before writing the command to the command register.              */
+
+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
+                                     Max_Data = 64                                                    */
+
+  uint32_t Response;            /*!< Specifies the SDMMC response type.
+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
+
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
+                                     enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
+
+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
+}SDMMC_CmdInitTypeDef;
+
+
+/** 
+  * @brief  SDMMC Data Control structure 
+  */
+typedef struct
+{
+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
+
+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
+ 
+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
+ 
+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+ 
+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
+ 
+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
+}SDMMC_DataInitTypeDef;
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+  * @{
+  */
+#define SDMMC_ERROR_NONE                     ((uint32_t)0x00000000U)   /*!< No error                                                      */
+#define SDMMC_ERROR_CMD_CRC_FAIL             ((uint32_t)0x00000001U)   /*!< Command response received (but CRC check failed)              */
+#define SDMMC_ERROR_DATA_CRC_FAIL            ((uint32_t)0x00000002U)   /*!< Data block sent/received (CRC check failed)                   */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT          ((uint32_t)0x00000004U)   /*!< Command response timeout                                      */
+#define SDMMC_ERROR_DATA_TIMEOUT             ((uint32_t)0x00000008U)   /*!< Data timeout                                                  */
+#define SDMMC_ERROR_TX_UNDERRUN              ((uint32_t)0x00000010U)   /*!< Transmit FIFO underrun                                        */
+#define SDMMC_ERROR_RX_OVERRUN               ((uint32_t)0x00000020U)   /*!< Receive FIFO overrun                                          */
+#define SDMMC_ERROR_ADDR_MISALIGNED          ((uint32_t)0x00000040U)   /*!< Misaligned address                                            */
+#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the 
+                                                                            number of transferred bytes does not match the block length   */
+#define SDMMC_ERROR_ERASE_SEQ_ERR            ((uint32_t)0x00000100U)   /*!< An error in the sequence of erase command occurs              */
+#define SDMMC_ERROR_BAD_ERASE_PARAM          ((uint32_t)0x00000200U)   /*!< An invalid selection for erase groups                         */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION     ((uint32_t)0x00000400U)   /*!< Attempt to program a write protect block                      */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock 
+                                                                            command or if there was an attempt to access a locked card    */
+#define SDMMC_ERROR_COM_CRC_FAILED           ((uint32_t)0x00001000U)   /*!< CRC check of the previous command failed                      */
+#define SDMMC_ERROR_ILLEGAL_CMD              ((uint32_t)0x00002000U)   /*!< Command is not legal for the card state                       */
+#define SDMMC_ERROR_CARD_ECC_FAILED          ((uint32_t)0x00004000U)   /*!< Card internal ECC was applied but failed to correct the data  */
+#define SDMMC_ERROR_CC_ERR                   ((uint32_t)0x00008000U)   /*!< Internal card controller error                                */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR      ((uint32_t)0x00010000U)   /*!< General or unknown error                                      */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN     ((uint32_t)0x00020000U)   /*!< The card could not sustain data reading in stream rmode       */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00040000U)   /*!< The card could not sustain data programming in stream mode    */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE        ((uint32_t)0x00080000U)   /*!< CID/CSD overwrite error                                       */
+#define SDMMC_ERROR_WP_ERASE_SKIP            ((uint32_t)0x00100000U)   /*!< Only partial address space was erased                         */
+#define SDMMC_ERROR_CARD_ECC_DISABLED        ((uint32_t)0x00200000U)   /*!< Command has been executed without using internal ECC          */
+#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out 
+                                                                            of erase sequence command was received                        */
+#define SDMMC_ERROR_AKE_SEQ_ERR              ((uint32_t)0x00800000U)   /*!< Error in sequence of authentication                           */
+#define SDMMC_ERROR_INVALID_VOLTRANGE        ((uint32_t)0x01000000U)   /*!< Error in case of invalid voltage range                        */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE        ((uint32_t)0x02000000U)   /*!< Error when addressed block is out of range                    */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE   ((uint32_t)0x04000000U)   /*!< Error when command request is not applicable                  */
+#define SDMMC_ERROR_INVALID_PARAMETER        ((uint32_t)0x08000000U)   /*!< the used parameter is not valid                               */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE      ((uint32_t)0x10000000U)   /*!< Error when feature is not insupported                         */
+#define SDMMC_ERROR_BUSY                     ((uint32_t)0x20000000U)   /*!< Error when transfer process is busy                           */
+#define SDMMC_ERROR_DMA                      ((uint32_t)0x40000000U)   /*!< Error while DMA transfer                                      */
+#define SDMMC_ERROR_TIMEOUT                  ((uint32_t)0x80000000U)   /*!< Timeout error                                                 */
+
+/** 
+  * @brief SDMMC Commands Index 
+  */
+#define SDMMC_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */
+#define SDMMC_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SDMMC_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SDMMC_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
+                                                                       operating condition register (OCR) content in the response on the CMD line.                  */
+#define SDMMC_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SDMMC_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
+                                                                       and asks the card whether card supports voltage.                                             */
+#define SDMMC_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SDMMC_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11U)  /*!< SD card doesn't support it.                                                              */
+#define SDMMC_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */
+#define SDMMC_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
+#define SDMMC_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)  /*!< Reserved                                                                                 */
+#define SDMMC_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
+#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
+                                                                           (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
+                                                                           for SDHS and SDXC.                                                                       */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by 
+                                                                           STOP_TRANSMISSION command.                                                               */
+#define SDMMC_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
+#define SDMMC_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SDMMC_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
+#define SDMMC_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SDMMC_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SDMMC_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SDMMC_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SDMMC_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SDMMC_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
+                                                                           system set by switch function command (CMD6).                                            */
+#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased. 
+                                                                           Reserved for each command system set by switch function command (CMD6).                  */
+#define SDMMC_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
+#define SDMMC_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
+                                                                           the SET_BLOCK_LEN command.                                                               */
+#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather 
+                                                                           than a standard command.                                                                 */
+#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
+                                                                           for general purpose/application specific commands.                                       */
+#define SDMMC_CMD_NO_CMD                              ((uint8_t)64U)  /*!< No command                                                                               */ 
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDMMC_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
+                                                                            widths are given in SCR register.                                                       */
+#define SDMMC_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                            */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
+                                                                           32bit+CRC data block.                                                                    */
+#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
+                                                                           send its operating condition register (OCR) content in the response on the CMD line.     */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
+#define SDMMC_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                               */
+#define SDMMC_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                               */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDMMC_CMD_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)
+#define SDMMC_CMD_SD_APP_GET_MID                      ((uint8_t)44U)
+#define SDMMC_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)
+#define SDMMC_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)
+#define SDMMC_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)
+#define SDMMC_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)
+#define SDMMC_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)
+
+/** 
+  * @brief  Masks for errors Card Status R1 (OCR Register) 
+  */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)
+#define SDMMC_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)
+#define SDMMC_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)
+#define SDMMC_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)
+#define SDMMC_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)
+#define SDMMC_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)
+#define SDMMC_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)
+#define SDMMC_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)
+#define SDMMC_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)
+#define SDMMC_OCR_CC_ERROR                 ((uint32_t)0x00100000U)
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)
+#define SDMMC_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)
+#define SDMMC_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)
+#define SDMMC_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)
+#define SDMMC_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)
+#define SDMMC_OCR_ERASE_RESET              ((uint32_t)0x00002000U)
+#define SDMMC_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)
+#define SDMMC_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)
+
+/** 
+  * @brief  Masks for R6 Response 
+  */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)
+#define SDMMC_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)
+#define SDMMC_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)
+
+#define SDMMC_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)
+#define SDMMC_HIGH_CAPACITY                ((uint32_t)0x40000000U)
+#define SDMMC_STD_CAPACITY                 ((uint32_t)0x00000000U)
+#define SDMMC_CHECK_PATTERN                ((uint32_t)0x000001AAU)
+
+#define SDMMC_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_MAX_TRIAL                    ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_ALLZERO                      ((uint32_t)0x00000000U)
+
+#define SDMMC_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)
+#define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
+#define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)
+
+#define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
+
+#define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)
+#define SDMMC_8TO15BITS                    ((uint32_t)0x0000FF00U)
+#define SDMMC_16TO23BITS                   ((uint32_t)0x00FF0000U)
+#define SDMMC_24TO31BITS                   ((uint32_t)0xFF000000U)
+#define SDMMC_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)
+
+#define SDMMC_HALFFIFO                     ((uint32_t)0x00000008U)
+#define SDMMC_HALFFIFOBYTES                ((uint32_t)0x00000020U)
+
+/** 
+  * @brief  Command Class supported
+  */
+#define SDMMC_CCCC_ERASE                   ((uint32_t)0x00000020U)
+
+#define SDMMC_CMDTIMEOUT                   ((uint32_t)5000U)        /* Command send and response timeout */
+#define SDMMC_MAXERASETIMEOUT              ((uint32_t)63000U)       /* Max erase Timeout 63 s            */
+#define SDMMC_STOPTRANSFERTIMEOUT          ((uint32_t)100000000U)   /* Timeout for STOP TRANSMISSION command */
+
+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
+  * @{
+  */
+#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
+
+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
+                                  ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
+  * @{
+  */
+#define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   
+
+#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
+                                      ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
+  * @{
+  */
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
+
+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
+                                        ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Bus_Wide Bus Width
+  * @{
+  */
+#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000U)
+#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
+#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
+
+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
+                                ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+                                ((WIDE) == SDMMC_BUS_WIDE_8B))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
+  * @{
+  */
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)
+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
+
+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
+                                                ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDMMC_LL_Clock_Division Clock Division
+  * @{
+  */
+#define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)
+/**
+  * @}
+  */  
+    
+
+/** @defgroup SDMMC_LL_Command_Index Command Index
+  * @{
+  */
+#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Response_Type Response Type
+  * @{
+  */
+#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000U)
+#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
+#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
+
+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
+                                    ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+                                    ((RESPONSE) == SDMMC_RESPONSE_LONG))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
+  * @{
+  */
+#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000U)
+#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT 
+#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
+
+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
+                            ((WAIT) == SDMMC_WAIT_IT) || \
+                            ((WAIT) == SDMMC_WAIT_PEND))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_CPSM_State CPSM State
+  * @{
+  */
+#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000U)
+#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
+
+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
+                            ((CPSM) == SDMMC_CPSM_ENABLE))
+/**
+  * @}
+  */  
+
+/** @defgroup SDMMC_LL_Response_Registers Response Register
+  * @{
+  */
+#define SDMMC_RESP1                          ((uint32_t)0x00000000U)
+#define SDMMC_RESP2                          ((uint32_t)0x00000004U)
+#define SDMMC_RESP3                          ((uint32_t)0x00000008U)
+#define SDMMC_RESP4                          ((uint32_t)0x0000000CU)
+
+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
+                            ((RESP) == SDMMC_RESP2) || \
+                            ((RESP) == SDMMC_RESP3) || \
+                            ((RESP) == SDMMC_RESP4))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Length Data Lenght
+  * @{
+  */
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
+  * @{
+  */
+#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)
+#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
+#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
+#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
+#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
+#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
+#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 
+#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
+  * @{
+  */
+#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR
+
+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
+                                   ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
+  * @{
+  */
+#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE
+
+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
+                                     ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_DPSM_State DPSM State
+  * @{
+  */
+#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000U)
+#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
+
+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
+                            ((DPSM) == SDMMC_DPSM_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
+  * @{
+  */
+#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)
+#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
+
+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
+                                      ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+/**
+  * @}
+  */  
+
+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
+  * @{
+  */
+#define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL
+#define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL
+#define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT
+#define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT
+#define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR
+#define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR
+#define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND
+#define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT
+#define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND
+#define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND
+#define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE
+#define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF
+#define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF
+#define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF
+#define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE
+#define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE
+#define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT
+#define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT
+#define SDMMC_IT_TXACT                       SDMMC_STA_TXACT
+#define SDMMC_IT_RXACT                       SDMMC_STA_RXACT
+#define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL
+#define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL
+/**
+  * @}
+  */ 
+
+/** @defgroup SDMMC_LL_Flags Flags
+  * @{
+  */
+#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
+#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
+#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
+#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
+#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
+#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
+#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
+#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
+#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
+#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
+#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
+#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
+#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
+#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
+#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
+#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
+#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
+#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT
+#define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT
+#define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT
+#define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL
+#define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL
+
+#define SDMMC_STATIC_FLAGS                   ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+                                                         SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
+                                                         SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
+                                                         SDMMC_FLAG_DBCKEND))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+  * @{
+  */
+  
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+  * @brief SDMMC_LL registers bit address in the alias region
+  * @{
+  */
+/* ---------------------- SDMMC registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
+                                             SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\
+                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
+
+/* --- DCTRL Register ---*/
+/* SDMMC DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
+                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
+                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
+                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))
+
+/* SDMMC Initialization Frequency (400KHz max) */
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
+
+/* SDMMC Data Transfer Frequency (25MHz max) */
+#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SDMMC device.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */ 
+#define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
+
+/**
+  * @brief  Disable the SDMMC device.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */
+#define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */ 
+#define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @param  __INSTANCE__: SDMMC Instance   
+  * @retval None
+  */
+#define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
+ 
+/**
+  * @brief  Enable the SDMMC device interrupt.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  *            @arg SDMMC_IT_TXACT:      Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:      Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXDAVL:     Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:     Data available in receive FIFO interrupt
+  * @retval None
+  */
+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDMMC device interrupt.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  *            @arg SDMMC_IT_TXACT:      Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:      Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXDAVL:     Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:     Data available in receive FIFO interrupt
+  * @retval None
+  */
+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDMMC flag is set or not. 
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  *            @arg SDMMC_FLAG_TXACT:      Data transmit in progress
+  *            @arg SDMMC_FLAG_RXACT:      Data receive in progress
+  *            @arg SDMMC_FLAG_TXDAVL:     Data available in transmit FIFO
+  *            @arg SDMMC_FLAG_RXDAVL:     Data available in receive FIFO
+  * @retval The new state of SDMMC_FLAG (SET or RESET).
+  */
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+
+
+/**
+  * @brief  Clears the SDMMC pending flags.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval None
+  */
+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  *            @arg SDMMC_IT_TXACT:      Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:      Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXDAVL:     Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:     Data available in receive FIFO interrupt
+  * @retval The new state of SDMMC_IT (SET or RESET).
+  */
+#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the SDMMC's interrupt pending bits.
+  * @param  __INSTANCE__: Pointer to SDMMC register base 
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @retval None
+  */  
+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @retval None
+  */  
+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Enable the SD I/O Mode Operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @retval None
+  */  
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 
+
+/**
+  * @brief  Disable the SD I/O Mode Operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base 
+  * @retval None
+  */  
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 
+
+/**
+  * @brief  Enable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 
+
+/**
+  * @brief  Disable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 
+      
+/**
+  * @brief  Enable the CMDTRANS mode.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 
+
+/**
+  * @brief  Disable the CMDTRANS mode.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+  * @{
+  */
+  
+/* Initialization/de-initialization functions  **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
+/**
+  * @}
+  */
+  
+/* I/O operation functions  *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+  * @{
+  */
+uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
+/**
+  * @}
+  */
+  
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
+uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
+uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+
+/* SDMMC Commands management functions */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_SDMMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c
new file mode 100755
index 0000000..4d3e260
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c
@@ -0,0 +1,309 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_spi.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SPI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_spi.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @addtogroup SPI_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+  * @{
+  */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
+                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
+                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
+                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
+                                            SPI_CR1_BIDIMODE)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+  * @{
+  */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
+                                              || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
+                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+                                || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)  \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+                                    || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+                                 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+                               || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+                               || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+                                    || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+                                          || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+  if (SPIx == SPI1)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    status = SUCCESS;
+  }
+#endif /* SPI1 */
+#if defined(SPI2)
+  if (SPIx == SPI2)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    status = SUCCESS;
+  }
+#endif /* SPI2 */
+#if defined(SPI3)
+  if (SPIx == SPI3)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    status = SUCCESS;
+  }
+#endif /* SPI3 */
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+  *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+  */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the SPI Instance SPIx*/
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+  /* Check the SPI parameters from SPI_InitStruct*/
+  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+  assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+  if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+  {
+    /*---------------------------- SPIx CR1 Configuration ------------------------
+     * Configure SPIx CR1 with parameters:
+     * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+     * - Master/Slave Mode:  SPI_CR1_MSTR bit
+     * - ClockPolarity:      SPI_CR1_CPOL bit
+     * - ClockPhase:         SPI_CR1_CPHA bit
+     * - NSS management:     SPI_CR1_SSM bit
+     * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+     * - BitOrder:           SPI_CR1_LSBFIRST bit
+     * - CRCCalculation:     SPI_CR1_CRCEN bit
+     */
+    MODIFY_REG(SPIx->CR1,
+               SPI_CR1_CLEAR_MASK,
+               SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+               SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+               SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+               SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+    /*---------------------------- SPIx CR2 Configuration ------------------------
+     * Configure SPIx CR2 with parameters:
+     * - DataWidth:          DS[3:0] bits
+     * - NSS management:     SSOE bit
+     */
+    MODIFY_REG(SPIx->CR2,
+               SPI_CR2_DS | SPI_CR2_SSOE,
+               SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+
+    /*---------------------------- SPIx CRCPR Configuration ----------------------
+     * Configure SPIx CRCPR with parameters:
+     * - CRCPoly:            CRCPOLY[15:0] bits
+     */
+    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+    {
+      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+    }
+    status = SUCCESS;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * whose fields will be set to default values.
+  * @retval None
+  */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  /* Set SPI_InitStruct fields to default values */
+  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
+  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
+  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
+  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
+  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
+  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
+  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
+  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct->CRCPoly           = 7U;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h
new file mode 100755
index 0000000..16fc9cd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h
@@ -0,0 +1,1429 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_spi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SPI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_SPI_H
+#define __STM32L4xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @defgroup SPI_LL SPI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structures definition
+  */
+typedef struct
+{
+  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+  uint32_t DataWidth;               /*!< Specifies the SPI data width.
+                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
+                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
+  * @{
+  */
+#define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
+#define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
+#define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
+#define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
+#define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
+#define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
+#define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+  * @{
+  */
+#define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
+#define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+  * @{
+  */
+#define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
+#define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+  * @{
+  */
+#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
+#define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+  * @{
+  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+  * @{
+  */
+#define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+  * @{
+  */
+#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
+#define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
+#define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+  * @{
+  */
+#define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
+#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
+#define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
+#define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
+#define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
+#define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
+#define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
+#define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
+#define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
+#define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
+#define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
+#define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
+#define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
+#define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
+#define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+  * @{
+  */
+#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+  * @{
+  */
+#define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
+#define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+  * @{
+  */
+#define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+  * @{
+  */
+#define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
+#define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
+#define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+  * @{
+  */
+#define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
+#define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
+#define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+  * @{
+  */
+#define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable SPI peripheral
+  * @rmtoll CR1          SPE           LL_SPI_Enable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Disable SPI peripheral
+  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
+  * @rmtoll CR1          SPE           LL_SPI_Disable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Check if SPI peripheral is enabled
+  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+}
+
+/**
+  * @brief  Set SPI operation mode to Master or Slave
+  * @note   This bit should not be changed when communication is ongoing.
+  * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
+  *         CR1          SSI           LL_SPI_SetMode
+  * @param  SPIx SPI Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+  * @brief  Get SPI operation mode (Master or Slave)
+  * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
+  *         CR1          SSI           LL_SPI_GetMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+  * @brief  Set serial protocol used
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR2          FRF           LL_SPI_SetStandard
+  * @param  SPIx SPI Instance
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+  * @brief  Get serial protocol used
+  * @rmtoll CR2          FRF           LL_SPI_GetStandard
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+  * @brief  Set clock phase
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
+  * @param  SPIx SPI Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Get clock phase
+  * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+  * @brief  Set clock polarity
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
+  * @param  SPIx SPI Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Get clock polarity
+  * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+  * @brief  Set baud rate prescaler
+  * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+  * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @param  BaudRate This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+  * @brief  Get baud rate prescaler
+  * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+  * @brief  Set transfer bit order
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Get transfer bit order
+  * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+  * @brief  Set transfer direction mode
+  * @note   For Half-Duplex mode, Rx Direction is set by default.
+  *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+  * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_SetTransferDirection
+  * @param  SPIx SPI Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+  * @brief  Get transfer direction mode
+  * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_GetTransferDirection
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+  * @brief  Set frame data width
+  * @rmtoll CR2          DS            LL_SPI_SetDataWidth
+  * @param  SPIx SPI Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+}
+
+/**
+  * @brief  Get frame data width
+  * @rmtoll CR2          DS            LL_SPI_GetDataWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+}
+
+/**
+  * @brief  Set threshold of RXFIFO that triggers an RXNE event
+  * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+}
+
+/**
+  * @brief  Get threshold of RXFIFO that triggers an RXNE event
+  * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+  * @{
+  */
+
+/**
+  * @brief  Enable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Disable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Check if CRC is enabled
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+}
+
+/**
+  * @brief  Set CRC Length
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
+  * @param  SPIx SPI Instance
+  * @param  CRCLength This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+}
+
+/**
+  * @brief  Get CRC Length
+  * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+}
+
+/**
+  * @brief  Set CRCNext to transfer CRC on the line
+  * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
+  * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+  * @brief  Set polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+  WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+  * @brief  Get polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+  * @brief  Get Rx CRC
+  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+  * @brief  Get Tx CRC
+  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+  * @{
+  */
+
+/**
+  * @brief  Set NSS mode
+  * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+  * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
+  * @param  SPIx SPI Instance
+  * @param  NSS This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
+  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+  * @brief  Get NSS mode
+  * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+  register uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+  register uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
+  return (Ssm | Ssoe);
+}
+
+/**
+  * @brief  Enable NSS pulse management
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+  * @brief  Disable NSS pulse management
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+  * @brief  Check if NSS pulse is enabled
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Check if Rx buffer is not empty
+  * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+}
+
+/**
+  * @brief  Check if Tx buffer is empty
+  * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+}
+
+/**
+  * @brief  Get CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+}
+
+/**
+  * @brief  Get mode fault error flag
+  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+}
+
+/**
+  * @brief  Get overrun error flag
+  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+}
+
+/**
+  * @brief  Get busy flag
+  * @note   The BSY flag is cleared under any one of the following conditions:
+  * -When the SPI is correctly disabled
+  * -When a fault is detected in Master mode (MODF bit set to 1)
+  * -In Master mode, when it finishes a data transmission and no new data is ready to be
+  * sent
+  * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+  * each data transfer.
+  * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+}
+
+/**
+  * @brief  Get frame format error flag
+  * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+}
+
+/**
+  * @brief  Get FIFO reception Level
+  * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_EMPTY
+  *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+  *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+  *         @arg @ref LL_SPI_RX_FIFO_FULL
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+}
+
+/**
+  * @brief  Get FIFO Transmission Level
+  * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_TX_FIFO_EMPTY
+  *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+  *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+  *         @arg @ref LL_SPI_TX_FIFO_FULL
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+}
+
+/**
+  * @brief  Clear CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+  * @brief  Clear mode fault error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_SR
+  *         register followed by a write access to the SPIx_CR1 register
+  * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+  tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear overrun error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_DR
+  *         register followed by a read access to the SPIx_SR register
+  * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->DR;
+  (void) tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear frame format error flag
+  * @note   Clearing this flag is done by reading SPIx_SR register
+  * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Enable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Enable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Disable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Disable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Disable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Check if error interrupt is enabled
+  * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+}
+
+/**
+  * @brief  Check if Rx buffer not empty interrupt is enabled
+  * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+}
+
+/**
+  * @brief  Check if Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+}
+
+/**
+  * @brief  Set parity of  Last DMA reception
+  * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
+  * @param  SPIx SPI Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+}
+
+/**
+  * @brief  Get parity configuration for  Last DMA reception
+  * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+}
+
+/**
+  * @brief  Set parity of  Last DMA transmission
+  * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
+  * @param  SPIx SPI Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+}
+
+/**
+  * @brief  Get parity configuration for Last DMA transmission
+  * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+  return (uint32_t) & (SPIx->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+  * @{
+  */
+
+/**
+  * @brief  Read 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData8
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+  return (uint8_t)(READ_REG(SPIx->DR));
+}
+
+/**
+  * @brief  Read 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+  return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+  * @brief  Write 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData8
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+  *((__IO uint8_t *)&SPIx->DR) = TxData;
+}
+
+/**
+  * @brief  Write 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+  *((__IO uint16_t *)&SPIx->DR) = TxData;
+}
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c
new file mode 100755
index 0000000..949bc6d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c
@@ -0,0 +1,190 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_swpmi.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   SWPMI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_swpmi.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (SWPMI1)
+
+/** @addtogroup SWPMI_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SWPMI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
+
+#define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \
+                                          || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI))
+
+#define IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \
+                                          || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI))
+
+#define IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__) (((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \
+                                           || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SWPMI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SWPMI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SWPMI peripheral registers to their default reset values.
+  * @param  SWPMIx SWPMI Instance
+  * @retval An ErrorStatus enumeration value
+  *          - SUCCESS: SWPMI registers are de-initialized
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx)
+{
+  /* Check the parameter */
+  assert_param(IS_SWPMI_INSTANCE(SWPMIx));
+
+  LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1);
+  LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
+  * @note   As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0),
+  *         SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SWPMIx           SWPMI Instance
+  * @param  SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
+  *                          the configuration information for the SWPMI peripheral.
+  * @retval An ErrorStatus enumeration value
+  *          - SUCCESS: SWPMI registers are initialized
+  *          - ERROR: SWPMI registers are not initialized
+  */
+ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_SWPMI_INSTANCE(SWPMIx));
+  assert_param(IS_LL_SWPMI_BITRATE_VALUE(SWPMI_InitStruct->BitRatePrescaler));
+  assert_param(IS_LL_SWPMI_SW_BUFFER_TX(SWPMI_InitStruct->TxBufferingMode));
+  assert_param(IS_LL_SWPMI_SW_BUFFER_RX(SWPMI_InitStruct->RxBufferingMode));
+  assert_param(IS_LL_SWPMI_VOLTAGE_CLASS(SWPMI_InitStruct->VoltageClass));
+
+  /* SWPMI needs to be in deactivated state, in order to be able to configure some bits */
+  if (LL_SWPMI_IsActivated(SWPMIx) == 0)
+  {
+    /* Configure the BRR register (Bitrate) */
+    LL_SWPMI_SetBitRatePrescaler(SWPMIx, SWPMI_InitStruct->BitRatePrescaler);
+
+    /* Configure the voltage class */
+    LL_SWPMI_SetVoltageClass(SWPMIx, SWPMI_InitStruct->VoltageClass);
+
+    /* Set the new configuration of the SWPMI peripheral */
+    MODIFY_REG(SWPMIx->CR,
+              (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
+              (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
+  }
+  /* Else (SWPMI not in deactivated state => return ERROR) */
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_SWPMI_InitTypeDef field to default value.
+  * @param  SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
+  *                          the configuration information for the SWPMI peripheral.
+  * @retval None
+  */
+void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
+{
+  /* Set SWPMI_InitStruct fields to default values */
+  SWPMI_InitStruct->VoltageClass     = LL_SWPMI_VOLTAGE_CLASS_C;
+  SWPMI_InitStruct->BitRatePrescaler = (uint32_t)0x00000001;
+  SWPMI_InitStruct->TxBufferingMode  = LL_SWPMI_SW_BUFFER_TX_SINGLE;
+  SWPMI_InitStruct->RxBufferingMode  = LL_SWPMI_SW_BUFFER_RX_SINGLE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (SWPMI1) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h
new file mode 100755
index 0000000..a2452f4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h
@@ -0,0 +1,1171 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_swpmi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SWPMI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_SWPMI_H
+#define __STM32L4xx_LL_SWPMI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (SWPMI1)
+
+/** @defgroup SWPMI_LL SWPMI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  SWPMI Init structures definition
+  */
+typedef struct
+{
+  uint32_t VoltageClass;           /*!< Specifies the SWP Voltage Class.
+                                        This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
+
+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
+
+  uint32_t BitRatePrescaler;       /*!< Specifies the SWPMI bitrate prescaler.
+                                        This parameter must be a number between Min_Data=0 and Max_Data=63.
+
+                                        The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
+
+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
+
+  uint32_t TxBufferingMode;        /*!< Specifies the transmission buffering mode.
+                                        This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
+
+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
+
+  uint32_t RxBufferingMode;        /*!< Specifies the reception buffering mode.
+                                        This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
+
+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
+} LL_SWPMI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
+  * @{
+  */
+
+/** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_SWPMI_WriteReg function
+  * @{
+  */
+#define LL_SWPMI_ICR_CRXBFF                SWPMI_ICR_CRXBFF  /*!< Clear receive buffer full flag     */
+#define LL_SWPMI_ICR_CTXBEF                SWPMI_ICR_CTXBEF  /*!< Clear transmit buffer empty flag   */
+#define LL_SWPMI_ICR_CRXBERF               SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag       */
+#define LL_SWPMI_ICR_CRXOVRF               SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag   */
+#define LL_SWPMI_ICR_CTXUNRF               SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
+#define LL_SWPMI_ICR_CTCF                  SWPMI_ICR_CTCF    /*!< Clear transfer complete flag       */
+#define LL_SWPMI_ICR_CSRF                  SWPMI_ICR_CSRF    /*!< Clear slave resume flag            */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_SWPMI_ReadReg function
+  * @{
+  */
+#define LL_SWPMI_ISR_RXBFF                 SWPMI_ISR_RXBFF   /*!< Receive buffer full flag           */
+#define LL_SWPMI_ISR_TXBEF                 SWPMI_ISR_TXBEF   /*!< Transmit buffer empty flag         */
+#define LL_SWPMI_ISR_RXBERF                SWPMI_ISR_RXBERF  /*!< Receive CRC error flag             */
+#define LL_SWPMI_ISR_RXOVRF                SWPMI_ISR_RXOVRF  /*!< Receive overrun error flag         */
+#define LL_SWPMI_ISR_TXUNRF                SWPMI_ISR_TXUNRF  /*!< Transmit underrun error flag       */
+#define LL_SWPMI_ISR_RXNE                  SWPMI_ISR_RXNE    /*!< Receive data register not empty    */
+#define LL_SWPMI_ISR_TXE                   SWPMI_ISR_TXE     /*!< Transmit data register empty       */
+#define LL_SWPMI_ISR_TCF                   SWPMI_ISR_TCF     /*!< Transfer complete flag             */
+#define LL_SWPMI_ISR_SRF                   SWPMI_ISR_SRF     /*!< Slave resume flag                  */
+#define LL_SWPMI_ISR_SUSP                  SWPMI_ISR_SUSP    /*!< SUSPEND flag                       */
+#define LL_SWPMI_ISR_DEACTF                SWPMI_ISR_DEACTF  /*!< DEACTIVATED flag                   */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SWPMI_ReadReg and  LL_SWPMI_WriteReg functions
+  * @{
+  */
+#define LL_SWPMI_IER_SRIE                  SWPMI_IER_SRIE    /*!< Slave resume interrupt enable            */
+#define LL_SWPMI_IER_TCIE                  SWPMI_IER_TCIE    /*!< Transmit complete interrupt enable       */
+#define LL_SWPMI_IER_TIE                   SWPMI_IER_TIE     /*!< Transmit interrupt enable                */
+#define LL_SWPMI_IER_RIE                   SWPMI_IER_RIE     /*!< Receive interrupt enable                 */
+#define LL_SWPMI_IER_TXUNRIE               SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
+#define LL_SWPMI_IER_RXOVRIE               SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable   */
+#define LL_SWPMI_IER_RXBERIE               SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable       */
+#define LL_SWPMI_IER_TXBEIE                SWPMI_IER_TXBEIE  /*!< Transmit buffer empty interrupt enable   */
+#define LL_SWPMI_IER_RXBFIE                SWPMI_IER_RXBFIE  /*!< Receive buffer full interrupt enable     */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
+  * @{
+  */
+#define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for reception */
+#define LL_SWPMI_SW_BUFFER_RX_MULTI  SWPMI_CR_RXMODE         /*!< Multi software buffermode for reception   */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
+  * @{
+  */
+#define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for transmission */
+#define LL_SWPMI_SW_BUFFER_TX_MULTI  SWPMI_CR_TXMODE         /*!< Multi software buffermode for transmission   */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
+  * @{
+  */
+#define LL_SWPMI_VOLTAGE_CLASS_C     ((uint32_t)0x00000000)  /*!< SWPMI_IO uses directly VDD voltage to operate in class C          */
+#define LL_SWPMI_VOLTAGE_CLASS_B     SWPMI_OR_CLASS          /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
+  * @{
+  */
+#define LL_SWPMI_DMA_REG_DATA_TRANSMIT     (uint32_t)0       /*!< Get address of data register used for transmission */
+#define LL_SWPMI_DMA_REG_DATA_RECEIVE      (uint32_t)1       /*!< Get address of data register used for reception    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
+  * @{
+  */
+
+/** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in SWPMI register
+  * @param  __INSTANCE__ SWPMI Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in SWPMI register
+  * @param  __INSTANCE__ SWPMI Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
+  * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
+  * @param  __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
+  * @param  __FSWPCLK__ PCLK or HSI frequency (in Hz)
+  * @retval Bitrate prescaler (BRR register)
+  */
+#define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__)   ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
+  * @{
+  */
+
+/** @defgroup SWPMI_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set Reception buffering mode
+  * @note   If Multi software buffer mode is chosen, RXDMA bits must also be set.
+  * @rmtoll CR           RXMODE        LL_SWPMI_SetReceptionMode
+  * @param  SWPMIx SWPMI Instance
+  * @param  RxBufferingMode This parameter can be one of the following values:
+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
+{
+  MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
+}
+
+/**
+  * @brief  Get Reception buffering mode
+  * @rmtoll CR           RXMODE        LL_SWPMI_GetReceptionMode
+  * @param  SWPMIx SWPMI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
+{
+  return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
+}
+
+/**
+  * @brief  Set Transmission buffering mode
+  * @note   If Multi software buffer mode is chosen, TXDMA bits must also be set.
+  * @rmtoll CR           TXMODE        LL_SWPMI_SetTransmissionMode
+  * @param  SWPMIx SWPMI Instance
+  * @param  TxBufferingMode This parameter can be one of the following values:
+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
+{
+  MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
+}
+
+/**
+  * @brief  Get Transmission buffering mode
+  * @rmtoll CR           TXMODE        LL_SWPMI_GetTransmissionMode
+  * @param  SWPMIx SWPMI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
+{
+  return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
+}
+
+/**
+  * @brief  Enable loopback mode
+  * @rmtoll CR           LPBK          LL_SWPMI_EnableLoopback
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
+}
+
+/**
+  * @brief  Disable loopback mode
+  * @rmtoll CR           LPBK          LL_SWPMI_DisableLoopback
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
+}
+
+/**
+  * @brief  Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
+  * @note   SWP bus stays in the ACTIVATED state as long as there is a communication
+  *         with the slave, either in transmission or in reception. The SWP bus switches back
+  *         to the SUSPENDED state as soon as there is no more transmission or reception
+  *         activity, after 7 idle bits.
+  * @rmtoll CR           SWPACT        LL_SWPMI_Activate
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
+{
+  /* In order to activate SWP again, the software must clear DEACT bit*/
+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
+
+  /* Set SWACT bit */
+  SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
+}
+
+/**
+  * @brief  Check if Single wire protocol bus is in ACTIVATED state.
+  * @rmtoll CR           SWPACT        LL_SWPMI_Activate
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT));
+}
+
+/**
+  * @brief  Deactivate immediately Single wire protocol bus (immediate transition to
+  *         DEACTIVATED state)
+  * @rmtoll CR           SWPACT        LL_SWPMI_Deactivate
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
+}
+
+/**
+  * @brief  Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
+  *         state if no resume from slave)
+  * @rmtoll CR           DEACT         LL_SWPMI_RequestDeactivation
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
+}
+
+/**
+  * @brief  Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
+  * @rmtoll BRR          BR            LL_SWPMI_SetBitRatePrescaler
+  * @param  SWPMIx SWPMI Instance
+  * @param  BitRatePrescaler A number between Min_Data=0 and Max_Data=63
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
+{
+  WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
+}
+
+/**
+  * @brief  Get Bitrate prescaler
+  * @rmtoll BRR          BR            LL_SWPMI_GetBitRatePrescaler
+  * @param  SWPMIx SWPMI Instance
+  * @retval A number between Min_Data=0 and Max_Data=63
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
+{
+  return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
+}
+
+/**
+  * @brief  Set SWP Voltage Class
+  * @rmtoll OR           CLASS         LL_SWPMI_SetVoltageClass
+  * @param  SWPMIx SWPMI Instance
+  * @param  VoltageClass This parameter can be one of the following values:
+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
+{
+  MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
+}
+
+/**
+  * @brief  Get SWP Voltage Class
+  * @rmtoll OR           CLASS         LL_SWPMI_GetVoltageClass
+  * @param  SWPMIx SWPMI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
+{
+  return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the last word of the frame under reception has arrived in SWPMI_RDR.
+  * @rmtoll ISR          RXBFF         LL_SWPMI_IsActiveFlag_RXBF
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF));
+}
+
+/**
+  * @brief  Check if Frame transmission buffer has been emptied
+  * @rmtoll ISR          TXBEF         LL_SWPMI_IsActiveFlag_TXBE
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF));
+}
+
+/**
+  * @brief  Check if CRC error in reception has been detected
+  * @rmtoll ISR          RXBERF        LL_SWPMI_IsActiveFlag_RXBER
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF));
+}
+
+/**
+  * @brief  Check if Overrun in reception has been detected
+  * @rmtoll ISR          RXOVRF        LL_SWPMI_IsActiveFlag_RXOVR
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF));
+}
+
+/**
+  * @brief  Check if underrun error in transmission has been detected
+  * @rmtoll ISR          TXUNRF        LL_SWPMI_IsActiveFlag_TXUNR
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF));
+}
+
+/**
+  * @brief  Check if Receive data register not empty (it means that Received data is ready
+  *         to be read in the SWPMI_RDR register)
+  * @rmtoll ISR          RXNE          LL_SWPMI_IsActiveFlag_RXNE
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE));
+}
+
+/**
+  * @brief  Check if Transmit data register is empty (it means that Data written in transmit
+  *         data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
+  * @rmtoll ISR          TXE           LL_SWPMI_IsActiveFlag_TXE
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE));
+}
+
+/**
+  * @brief  Check if Both transmission and reception are completed and SWP is switched to
+  *         the SUSPENDED state
+  * @rmtoll ISR          TCF           LL_SWPMI_IsActiveFlag_TC
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF));
+}
+
+/**
+  * @brief  Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
+  *         state
+  * @rmtoll ISR          SRF           LL_SWPMI_IsActiveFlag_SR
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF));
+}
+
+/**
+  * @brief  Check if SWP bus is in SUSPENDED or DEACTIVATED state
+  * @rmtoll ISR          SUSP          LL_SWPMI_IsActiveFlag_SUSP
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP));
+}
+
+/**
+  * @brief  Check if SWP bus is in DEACTIVATED state
+  * @rmtoll ISR          DEACTF        LL_SWPMI_IsActiveFlag_DEACT
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF));
+}
+
+/**
+  * @brief  Clear receive buffer full flag
+  * @rmtoll ICR          CRXBFF        LL_SWPMI_ClearFlag_RXBF
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
+{
+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
+}
+
+/**
+  * @brief  Clear transmit buffer empty flag
+  * @rmtoll ICR          CTXBEF        LL_SWPMI_ClearFlag_TXBE
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
+{
+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
+}
+
+/**
+  * @brief  Clear receive CRC error flag
+  * @rmtoll ICR          CRXBERF       LL_SWPMI_ClearFlag_RXBER
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
+{
+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
+}
+
+/**
+  * @brief  Clear receive overrun error flag
+  * @rmtoll ICR          CRXOVRF       LL_SWPMI_ClearFlag_RXOVR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
+{
+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
+}
+
+/**
+  * @brief  Clear transmit underrun error flag
+  * @rmtoll ICR          CTXUNRF       LL_SWPMI_ClearFlag_TXUNR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
+{
+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
+}
+
+/**
+  * @brief  Clear transfer complete flag
+  * @rmtoll ICR          CTCF          LL_SWPMI_ClearFlag_TC
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
+{
+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
+}
+
+/**
+  * @brief  Clear slave resume flag
+  * @rmtoll ICR          CSRF          LL_SWPMI_ClearFlag_SR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
+{
+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Slave resume interrupt
+  * @rmtoll IER          SRIE          LL_SWPMI_EnableIT_SR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
+}
+
+/**
+  * @brief  Enable Transmit complete interrupt
+  * @rmtoll IER          TCIE          LL_SWPMI_EnableIT_TC
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
+}
+
+/**
+  * @brief  Enable Transmit interrupt
+  * @rmtoll IER          TIE           LL_SWPMI_EnableIT_TX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
+}
+
+/**
+  * @brief  Enable Receive interrupt
+  * @rmtoll IER          RIE           LL_SWPMI_EnableIT_RX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
+}
+
+/**
+  * @brief  Enable Transmit underrun error interrupt
+  * @rmtoll IER          TXUNRIE       LL_SWPMI_EnableIT_TXUNR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
+}
+
+/**
+  * @brief  Enable Receive overrun error interrupt
+  * @rmtoll IER          RXOVRIE       LL_SWPMI_EnableIT_RXOVR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
+}
+
+/**
+  * @brief  Enable Receive CRC error interrupt
+  * @rmtoll IER          RXBERIE       LL_SWPMI_EnableIT_RXBER
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
+}
+
+/**
+  * @brief  Enable Transmit buffer empty interrupt
+  * @rmtoll IER          TXBEIE        LL_SWPMI_EnableIT_TXBE
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
+}
+
+/**
+  * @brief  Enable Receive buffer full interrupt
+  * @rmtoll IER          RXBFIE        LL_SWPMI_EnableIT_RXBF
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
+}
+
+/**
+  * @brief  Disable Slave resume interrupt
+  * @rmtoll IER          SRIE          LL_SWPMI_DisableIT_SR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
+}
+
+/**
+  * @brief  Disable Transmit complete interrupt
+  * @rmtoll IER          TCIE          LL_SWPMI_DisableIT_TC
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
+}
+
+/**
+  * @brief  Disable Transmit interrupt
+  * @rmtoll IER          TIE           LL_SWPMI_DisableIT_TX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
+}
+
+/**
+  * @brief  Disable Receive interrupt
+  * @rmtoll IER          RIE           LL_SWPMI_DisableIT_RX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
+}
+
+/**
+  * @brief  Disable Transmit underrun error interrupt
+  * @rmtoll IER          TXUNRIE       LL_SWPMI_DisableIT_TXUNR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
+}
+
+/**
+  * @brief  Disable Receive overrun error interrupt
+  * @rmtoll IER          RXOVRIE       LL_SWPMI_DisableIT_RXOVR
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
+}
+
+/**
+  * @brief  Disable Receive CRC error interrupt
+  * @rmtoll IER          RXBERIE       LL_SWPMI_DisableIT_RXBER
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
+}
+
+/**
+  * @brief  Disable Transmit buffer empty interrupt
+  * @rmtoll IER          TXBEIE        LL_SWPMI_DisableIT_TXBE
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
+}
+
+/**
+  * @brief  Disable Receive buffer full interrupt
+  * @rmtoll IER          RXBFIE        LL_SWPMI_DisableIT_RXBF
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
+}
+
+/**
+  * @brief  Check if Slave resume interrupt is enabled
+  * @rmtoll IER          SRIE          LL_SWPMI_IsEnabledIT_SR
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE));
+}
+
+/**
+  * @brief  Check if Transmit complete interrupt is enabled
+  * @rmtoll IER          TCIE          LL_SWPMI_IsEnabledIT_TC
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE));
+}
+
+/**
+  * @brief  Check if Transmit interrupt is enabled
+  * @rmtoll IER          TIE           LL_SWPMI_IsEnabledIT_TX
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE));
+}
+
+/**
+  * @brief  Check if Receive interrupt is enabled
+  * @rmtoll IER          RIE           LL_SWPMI_IsEnabledIT_RX
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE));
+}
+
+/**
+  * @brief  Check if Transmit underrun error interrupt is enabled
+  * @rmtoll IER          TXUNRIE       LL_SWPMI_IsEnabledIT_TXUNR
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE));
+}
+
+/**
+  * @brief  Check if Receive overrun error interrupt is enabled
+  * @rmtoll IER          RXOVRIE       LL_SWPMI_IsEnabledIT_RXOVR
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE));
+}
+
+/**
+  * @brief  Check if Receive CRC error interrupt is enabled
+  * @rmtoll IER          RXBERIE       LL_SWPMI_IsEnabledIT_RXBER
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE));
+}
+
+/**
+  * @brief  Check if Transmit buffer empty interrupt is enabled
+  * @rmtoll IER          TXBEIE        LL_SWPMI_IsEnabledIT_TXBE
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE));
+}
+
+/**
+  * @brief  Check if Receive buffer full interrupt is enabled
+  * @rmtoll IER          RXBFIE        LL_SWPMI_IsEnabledIT_RXBF
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA mode for reception
+  * @rmtoll CR           RXDMA         LL_SWPMI_EnableDMAReq_RX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
+}
+
+/**
+  * @brief  Disable DMA mode for reception
+  * @rmtoll CR           RXDMA         LL_SWPMI_DisableDMAReq_RX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
+}
+
+/**
+  * @brief  Check if DMA mode for reception is enabled
+  * @rmtoll CR           RXDMA         LL_SWPMI_IsEnabledDMAReq_RX
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA));
+}
+
+/**
+  * @brief  Enable DMA mode for transmission
+  * @rmtoll CR           TXDMA         LL_SWPMI_EnableDMAReq_TX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
+}
+
+/**
+  * @brief  Disable DMA mode for transmission
+  * @rmtoll CR           TXDMA         LL_SWPMI_DisableDMAReq_TX
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
+}
+
+/**
+  * @brief  Check if DMA mode for transmission is enabled
+  * @rmtoll CR           TXDMA         LL_SWPMI_IsEnabledDMAReq_TX
+  * @param  SWPMIx SWPMI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
+{
+  return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TDR          TD            LL_SWPMI_DMA_GetRegAddr\n
+  *         RDR          RD            LL_SWPMI_DMA_GetRegAddr
+  * @param  SWPMIx SWPMI Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr = 0;
+
+  if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t)&(SWPMIx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t)&(SWPMIx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Retrieve number of data bytes present in payload of received frame
+  * @rmtoll RFL          RFL           LL_SWPMI_GetReceiveFrameLength
+  * @param  SWPMIx SWPMI Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1F
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
+{
+  return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
+}
+
+/**
+  * @brief  Transmit Data Register
+  * @rmtoll TDR          TD            LL_SWPMI_TransmitData32
+  * @param  SWPMIx SWPMI Instance
+  * @param  TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
+{
+  WRITE_REG(SWPMIx->TDR, TxData);
+}
+
+/**
+  * @brief  Receive Data Register
+  * @rmtoll RDR          RD            LL_SWPMI_ReceiveData32
+  * @param  SWPMIx SWPMI Instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
+{
+  return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
+}
+
+/**
+  * @brief  Enable SWP Transceiver Bypass
+  * @note   The external interface for SWPMI is SWPMI_IO
+  *         (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
+  * @rmtoll OR           TBYP          LL_SWPMI_EnableTXBypass
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
+{
+  CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
+}
+
+/**
+  * @brief  Disable SWP Transceiver Bypass
+  * @note   SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
+  *         function on GPIOs. This configuration is selected to connect an external transceiver
+  * @rmtoll OR           TBYP          LL_SWPMI_DisableTXBypass
+  * @param  SWPMIx SWPMI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
+{
+  SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
+ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
+void        LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (SWPMI1) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_SWPMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h
new file mode 100755
index 0000000..409db3d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h
@@ -0,0 +1,1610 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_system.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SYSTEM LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+      (+) Access to VREFBUF registers
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_SYSTEM_H
+#define __STM32L4xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+
+/* Defines used for position in the register */
+#define DBGMCU_REVID_POSITION         (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
+
+/**
+ * @brief Power-down in Run mode Flash key
+ */
+#define FLASH_PDKEY1                  ((uint32_t)0x04152637U) /*!< Flash power down key1 */
+#define FLASH_PDKEY2                  ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                                   to unlock the RUN_PD bit in FLASH_ACR */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+* @{
+*/
+#define LL_SYSCFG_REMAP_FLASH              0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000              */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
+#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
+#if defined(FMC_Bank1_R)
+#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
+#endif /* FMC_Bank1_R */
+#define LL_SYSCFG_REMAP_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000                 */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+  * @{
+  */
+#define LL_SYSCFG_BANKMODE_BANK1           0x00000000U               /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 
+                                                                      and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
+#define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_MEMRMP_FB_MODE     /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
+                                                                      and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
+/**
+  * @}
+  */
+
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(I2C2)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
+#endif /* I2C2 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(I2C4)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4    SYSCFG_CFGR1_I2C4_FMP     /*!< Enable Fast Mode Plus on I2C4 pins */
+#endif /* I2C4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               0U                        /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               1U                        /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               2U                        /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               3U                        /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               4U                        /*!< EXTI PORT E                        */
+#if defined(GPIOF)
+#define LL_SYSCFG_EXTI_PORTF               5U                        /*!< EXTI PORT F                        */
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG               6U                        /*!< EXTI PORT G                        */
+#endif /* GPIOG */
+#define LL_SYSCFG_EXTI_PORTH               7U                        /*!< EXTI PORT H                        */
+#if defined(GPIOI)
+#define LL_SYSCFG_EXTI_PORTI               8U                        /*!< EXTI PORT I                        */
+#endif /* GPIOI */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16U | 0U)  /* !< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16U | 0U)  /* !< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16U | 0U)  /* !< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16U | 0U)  /* !< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16U | 1U)  /* !< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16U | 1U)  /* !< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16U | 1U)  /* !< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16U | 1U)  /* !< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16U | 2U)  /* !< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16U | 2U)  /* !< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16U | 2U)  /* !< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16U | 2U)  /* !< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16U | 3U)  /* !< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16U | 3U)  /* !< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16U | 3U)  /* !< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16U | 3U)  /* !< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal 
+                                                                   with Break Input of TIM1/8/15/16/17                           */
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection 
+                                                                   with TIM1/8/15/16/17 Break Input 
+                                                                   and also the PVDE and PLS bits of the Power Control Interface */
+#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY    SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal 
+                                                                   with Break Input of TIM1/8/15/16/17                           */
+#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 
+                                                                   with Break Input of TIM1/15/16/17                             */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
+  * @{
+  */
+#define LL_SYSCFG_SRAM2WRP_PAGE0           SYSCFG_SWPR_PAGE0  /*!< SRAM2 Write protection page 0  */
+#define LL_SYSCFG_SRAM2WRP_PAGE1           SYSCFG_SWPR_PAGE1  /*!< SRAM2 Write protection page 1  */
+#define LL_SYSCFG_SRAM2WRP_PAGE2           SYSCFG_SWPR_PAGE2  /*!< SRAM2 Write protection page 2  */
+#define LL_SYSCFG_SRAM2WRP_PAGE3           SYSCFG_SWPR_PAGE3  /*!< SRAM2 Write protection page 3  */
+#define LL_SYSCFG_SRAM2WRP_PAGE4           SYSCFG_SWPR_PAGE4  /*!< SRAM2 Write protection page 4  */
+#define LL_SYSCFG_SRAM2WRP_PAGE5           SYSCFG_SWPR_PAGE5  /*!< SRAM2 Write protection page 5  */
+#define LL_SYSCFG_SRAM2WRP_PAGE6           SYSCFG_SWPR_PAGE6  /*!< SRAM2 Write protection page 6  */
+#define LL_SYSCFG_SRAM2WRP_PAGE7           SYSCFG_SWPR_PAGE7  /*!< SRAM2 Write protection page 7  */
+#define LL_SYSCFG_SRAM2WRP_PAGE8           SYSCFG_SWPR_PAGE8  /*!< SRAM2 Write protection page 8  */
+#define LL_SYSCFG_SRAM2WRP_PAGE9           SYSCFG_SWPR_PAGE9  /*!< SRAM2 Write protection page 9  */
+#define LL_SYSCFG_SRAM2WRP_PAGE10          SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
+#define LL_SYSCFG_SRAM2WRP_PAGE11          SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
+#define LL_SYSCFG_SRAM2WRP_PAGE12          SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
+#define LL_SYSCFG_SRAM2WRP_PAGE13          SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
+#define LL_SYSCFG_SRAM2WRP_PAGE14          SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
+#define LL_SYSCFG_SRAM2WRP_PAGE15          SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
+#if defined(SYSCFG_SWPR_PAGE31)
+#define LL_SYSCFG_SRAM2WRP_PAGE16          SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
+#define LL_SYSCFG_SRAM2WRP_PAGE17          SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
+#define LL_SYSCFG_SRAM2WRP_PAGE18          SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
+#define LL_SYSCFG_SRAM2WRP_PAGE19          SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
+#define LL_SYSCFG_SRAM2WRP_PAGE20          SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
+#define LL_SYSCFG_SRAM2WRP_PAGE21          SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
+#define LL_SYSCFG_SRAM2WRP_PAGE22          SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
+#define LL_SYSCFG_SRAM2WRP_PAGE23          SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
+#define LL_SYSCFG_SRAM2WRP_PAGE24          SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
+#define LL_SYSCFG_SRAM2WRP_PAGE25          SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
+#define LL_SYSCFG_SRAM2WRP_PAGE26          SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
+#define LL_SYSCFG_SRAM2WRP_PAGE27          SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
+#define LL_SYSCFG_SRAM2WRP_PAGE28          SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
+#define LL_SYSCFG_SRAM2WRP_PAGE29          SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
+#define LL_SYSCFG_SRAM2WRP_PAGE30          SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
+#define LL_SYSCFG_SRAM2WRP_PAGE31          SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
+#endif /* SYSCFG_SWPR_PAGE31 */
+#if defined(SYSCFG_SWPR2_PAGE63)
+#define LL_SYSCFG_SRAM2WRP_PAGE32          SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
+#define LL_SYSCFG_SRAM2WRP_PAGE33          SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
+#define LL_SYSCFG_SRAM2WRP_PAGE34          SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
+#define LL_SYSCFG_SRAM2WRP_PAGE35          SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
+#define LL_SYSCFG_SRAM2WRP_PAGE36          SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
+#define LL_SYSCFG_SRAM2WRP_PAGE37          SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
+#define LL_SYSCFG_SRAM2WRP_PAGE38          SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
+#define LL_SYSCFG_SRAM2WRP_PAGE39          SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
+#define LL_SYSCFG_SRAM2WRP_PAGE40          SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
+#define LL_SYSCFG_SRAM2WRP_PAGE41          SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
+#define LL_SYSCFG_SRAM2WRP_PAGE42          SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
+#define LL_SYSCFG_SRAM2WRP_PAGE43          SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
+#define LL_SYSCFG_SRAM2WRP_PAGE44          SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
+#define LL_SYSCFG_SRAM2WRP_PAGE45          SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
+#define LL_SYSCFG_SRAM2WRP_PAGE46          SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
+#define LL_SYSCFG_SRAM2WRP_PAGE47          SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
+#define LL_SYSCFG_SRAM2WRP_PAGE48          SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
+#define LL_SYSCFG_SRAM2WRP_PAGE49          SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
+#define LL_SYSCFG_SRAM2WRP_PAGE50          SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
+#define LL_SYSCFG_SRAM2WRP_PAGE51          SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
+#define LL_SYSCFG_SRAM2WRP_PAGE52          SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
+#define LL_SYSCFG_SRAM2WRP_PAGE53          SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
+#define LL_SYSCFG_SRAM2WRP_PAGE54          SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
+#define LL_SYSCFG_SRAM2WRP_PAGE55          SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
+#define LL_SYSCFG_SRAM2WRP_PAGE56          SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
+#define LL_SYSCFG_SRAM2WRP_PAGE57          SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
+#define LL_SYSCFG_SRAM2WRP_PAGE58          SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
+#define LL_SYSCFG_SRAM2WRP_PAGE59          SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
+#define LL_SYSCFG_SRAM2WRP_PAGE60          SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
+#define LL_SYSCFG_SRAM2WRP_PAGE61          SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
+#define LL_SYSCFG_SRAM2WRP_PAGE62          SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
+#define LL_SYSCFG_SRAM2WRP_PAGE63          SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
+#endif /* SYSCFG_SWPR2_PAGE63 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/
+#if defined(TIM3)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/
+#endif /* TIM5 */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/
+#if defined(TIM7)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/
+#endif /* TIM7 */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/
+#if defined(I2C2)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/
+#endif /* I2C2 */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen*/
+#define LL_DBGMCU_APB1_GRP1_CAN_STOP       DBGMCU_APB1FZR1_DBG_CAN_STOP    /*!< The bxCAN receive registers are frozen*/
+#if defined(CAN2)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1FZR1_DBG_CAN2_STOP   /*!< The bxCAN2 receive registers are frozen*/
+#endif /* CAN2 */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+  * @{
+  */
+#if defined(I2C4)
+#define LL_DBGMCU_APB1_GRP2_I2C4_STOP      DBGMCU_APB1FZR2_DBG_I2C4_STOP   /*!< The I2C4 SMBus timeout is frozen*/
+#endif /* I2C4 */
+#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP    DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ_DBG_TIM1_STOP     /*!< The counter clock of TIM1 is stopped when the core is halted*/
+#if defined(TIM8)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ_DBG_TIM8_STOP     /*!< The counter clock of TIM8 is stopped when the core is halted*/
+#endif /* TIM8 */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ_DBG_TIM15_STOP    /*!< The counter clock of TIM15 is stopped when the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ_DBG_TIM16_STOP    /*!< The counter clock of TIM16 is stopped when the core is halted*/
+#if defined(TIM17)
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ_DBG_TIM17_STOP    /*!< The counter clock of TIM17 is stopped when the core is halted*/
+#endif /* TIM17 */
+/**
+  * @}
+  */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
+  * @{
+  */
+#define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+
+/**
+  * @brief  Set memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
+  * @param  Memory This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
+}
+
+/**
+  * @brief  Get memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
+}
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/**
+  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
+  * @param  Bank This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
+}
+
+/**
+  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
+}
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+
+/**
+  * @brief  Firewall protection enabled
+  * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_EnableFirewall
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
+}
+
+/**
+  * @brief  Check if Firewall protection is enabled or not
+  * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_IsEnabledFirewall
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
+{
+  return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
+}
+
+/**
+  * @brief  Enable I/O analog switch voltage booster.
+  * @note   When voltage booster is enabled, I/O analog switches are supplied
+  *         by a dedicated voltage booster, from VDD power domain. This is
+  *         the recommended configuration with low VDDA voltage operation.
+  * @note   The I/O analog switch voltage booster is relevant for peripherals
+  *         using I/O in analog input: ADC, COMP, OPAMP.
+  *         However, COMP and OPAMP inputs have a high impedance and
+  *         voltage booster do not impact performance significantly.
+  *         Therefore, the voltage booster is mainly intended for
+  *         usage with ADC.
+  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Disable I/O analog switch voltage booster.
+  * @note   When voltage booster is enabled, I/O analog switches are supplied
+  *         by a dedicated voltage booster, from VDD power domain. This is
+  *         the recommended configuration with low VDDA voltage operation.
+  * @note   The I/O analog switch voltage booster is relevant for peripherals
+  *         using I/O in analog input: ADC, COMP, OPAMP.
+  *         However, COMP and OPAMP inputs have a high impedance and
+  *         voltage booster do not impact performance significantly.
+  *         Therefore, the voltage booster is mainly intended for
+  *         usage with ADC.
+  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Invalid operation Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Underflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Overflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Input denormal Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Inexact Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Invalid operation Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Underflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Overflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Input denormal Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Inexact Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+  * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
+{
+  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
+}
+
+/**
+  * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
+{
+  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
+}
+
+/**
+  * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
+{
+  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
+}
+
+/**
+  * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
+{
+  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
+}
+
+/**
+  * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
+{
+  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
+}
+
+/**
+  * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
+{
+  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
+}
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
+}
+
+/**
+  * @brief  Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
+  * automatically cleared at the end of the SRAM2 erase operation.)
+  * @note This bit is write-protected: setting this bit is possible only after the
+  *       correct key sequence is written in the SYSCFG_SKR register as described in 
+  *       the Reference Manual.
+  * @rmtoll SYSCFG_SCSR  SRAM2ER       LL_SYSCFG_EnableSRAM2Erase
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
+{
+  /* Starts a hardware SRAM2 erase operation*/
+  SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
+}
+
+/**
+  * @brief  Check if SRAM2 erase operation is on going
+  * @rmtoll SYSCFG_SCSR  SRAM2BSY      LL_SYSCFG_IsSRAM2EraseOngoing
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
+{
+  return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
+}
+
+/**
+  * @brief  Set connections to TIM1/8/15/16/17 Break inputs
+  * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
+}
+
+/**
+  * @brief  Get connections to TIM1/8/15/16/17 Break inputs
+  * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
+}
+
+/**
+  * @brief  Check if SRAM2 parity error detected
+  * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
+{
+  return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
+}
+
+/**
+  * @brief  Clear SRAM2 parity error flag
+  * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
+{
+  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
+}
+
+/**
+  * @brief  Enable SRAM2 page write protection for Pages in range 0 to 31
+  * @note Write protection is cleared only by a system reset
+  * @rmtoll SYSCFG_SWPR  PxWP         LL_SYSCFG_EnableSRAM2PageWRP_0_31
+  * @param  SRAM2WRP This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+/* Legacy define */
+#define LL_SYSCFG_EnableSRAM2PageWRP    LL_SYSCFG_EnableSRAM2PageWRP_0_31
+__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
+{
+  SET_BIT(SYSCFG->SWPR, SRAM2WRP);
+}
+
+#if defined(SYSCFG_SWPR2_PAGE63)
+/**
+  * @brief  Enable SRAM2 page write protection for Pages in range 32 to 63
+  * @note Write protection is cleared only by a system reset
+  * @rmtoll SYSCFG_SWPR2 PxWP          LL_SYSCFG_EnableSRAM2PageWRP_32_63
+  * @param  SRAM2WRP This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
+  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
+{
+  SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
+}
+#endif /* SYSCFG_SWPR2_PAGE63 */
+
+/**
+  * @brief  SRAM2 page write protection lock prior to erase
+  * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockSRAM2WRP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
+{
+  /* Writing a wrong key reactivates the write protection */
+  WRITE_REG(SYSCFG->SKR, 0x00);
+}
+
+/**
+  * @brief  SRAM2 page write protection unlock prior to erase
+  * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockSRAM2WRP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
+{
+  /* unlock the write protection of the SRAM2ER bit */
+  WRITE_REG(SYSCFG->SKR, 0xCA);
+  WRITE_REG(SYSCFG->SKR, 0x53);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Set Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
+  * @param  PinAssignment This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+  * @brief  Get Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group2 peripherals)
+  * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group2 peripherals)
+  * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @}
+  */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
+  * @{
+  */
+
+/**
+  * @brief  Enable Internal voltage reference
+  * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_Enable(void)
+{
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+  * @brief  Disable Internal voltage reference
+  * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_Disable(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+  * @brief  Enable high impedance (VREF+pin is high impedance)
+  * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
+{
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+  * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
+  * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+  * @brief  Set the Voltage reference scale
+  * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
+  * @param  Scale This parameter can be one of the following values:
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
+{
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
+}
+
+/**
+  * @brief  Get the Voltage reference scale
+  * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+  */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
+}
+
+/**
+  * @brief  Check if Voltage reference buffer is ready
+  * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
+{
+  return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
+}
+
+/**
+  * @brief  Get the trimming code for VREFBUF calibration
+  * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
+  * @retval Between 0 and 0x3F
+  */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
+{
+  return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
+}
+
+/**
+  * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
+  * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
+  * @param  Value Between 0 and 0x3F
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
+{
+  WRITE_REG(VREFBUF->CCR, Value);
+}
+
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @brief  Enable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Disable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Check if Prefetch buffer is enabled
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
+}
+
+/**
+  * @brief  Enable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Disable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Enable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Disable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Enable Instruction cache reset
+  * @note  bit can be written only when the instruction cache is disabled
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Disable Instruction cache reset
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Enable Data cache reset
+  * @note bit can be written only when the data cache is disabled
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+  * @brief  Disable Data cache reset
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+  * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
+  * @note Flash memory can be put in power-down mode only when the code is executed
+  *       from RAM
+  * @note Flash must not be accessed when power down is enabled
+  * @note Flash must not be put in power-down while a program or an erase operation
+  *       is on-going
+  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
+{
+  /* Following values must be written consecutively to unlock the RUN_PD bit in
+     FLASH_ACR */
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+  SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+  * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
+  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
+{
+  /* Following values must be written consecutively to unlock the RUN_PD bit in
+     FLASH_ACR */
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+  * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
+  * @note Flash must not be put in power-down while a program or an erase operation
+  *       is on-going
+  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+  * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
+  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c
new file mode 100755
index 0000000..ca7cfed
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c
@@ -0,0 +1,1369 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_tim.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   TIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_tim.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
+
+/** @addtogroup TIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+                                   || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+                                      || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+                                       || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                               || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+                                     || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+                                      || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
+                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
+                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+                                       || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+                                          || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+                                        || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+                                          || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+                                        || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+                                                  || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+  * @{
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup TIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set TIMx registers to their reset values.
+  * @param  TIMx Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: invalid TIMx instance
+  */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+
+  if (TIMx == TIM1)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+  }
+  else if (TIMx == TIM2)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+  }
+#if defined(TIM3)
+  else if (TIMx == TIM3)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+  }
+#endif
+#if defined(TIM4)
+  else if (TIMx == TIM4)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+  }
+#endif
+#if defined(TIM5)
+  else if (TIMx == TIM5)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+  }
+#endif
+  else if (TIMx == TIM6)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+  }
+#if defined (TIM7)
+  else if (TIMx == TIM7)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+  }
+#endif
+#if defined(TIM8)
+  else if (TIMx == TIM8)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+  }
+#endif
+  else if (TIMx == TIM15)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
+  }
+  else if (TIMx == TIM16)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+  }
+#if defined(TIM17)
+  else if (TIMx == TIM17)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+  }
+#endif
+  else
+  {
+    result = ERROR;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the time base unit configuration data structure
+  *         to their default values.
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+  * @retval None
+  */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
+  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
+  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
+  TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
+}
+
+/**
+  * @brief  Configure the TIMx time base unit.
+  * @param  TIMx Timer Instance
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  uint32_t tmpcr1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+  }
+
+  /* Write to TIMx CR1 */
+  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+  /* Set the Autoreload value */
+  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+  /* Set the Prescaler value */
+  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter value (if applicable) immediately */
+  LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the TIMx output channel configuration data
+  *         structure to their default values.
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+  * @retval None
+  */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
+  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
+  TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
+  TIM_OC_InitStruct->CompareValue = 0x00000000U;
+  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
+  TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
+  TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
+  TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+  * @brief  Configure the TIMx output channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = OC1Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = OC2Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = OC3Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = OC4Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH5:
+      result = OC5Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH6:
+      result = OC6Config(TIMx, TIM_OC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the TIMx input channel configuration data
+  *         structure to their default values.
+  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+  * @retval None
+  */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the TIMx input channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = IC1Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = IC2Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = IC3Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = IC4Config(TIMx, TIM_IC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Fills each TIM_EncoderInitStruct field with its default value
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+  * @retval None
+  */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  /* Set the default configuration */
+  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
+  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
+  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the encoder interface of the timer instance.
+  * @param  TIMx Timer Instance
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  uint32_t tmpccmr1 = 0U;
+  uint32_t tmpccer = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Configure TI1 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+  /* Configure TI2 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Set encoder mode */
+  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the TIMx Hall sensor interface configuration data
+  *         structure to their default values.
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+  * @retval None
+  */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+  /* Set the default configuration */
+  TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
+  TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
+  TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
+  TIM_HallSensorInitStruct->CommutationDelay  = 0U;
+}
+
+/**
+  * @brief  Configure the Hall sensor interface of the timer instance.
+  * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+  *       to the TI1 input channel
+  * @note TIMx slave mode controller is configured in reset mode.
+          Selected internal trigger is TI1F_ED.
+  * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+  * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+  *       between 2 changes on the inputs. It gives information about motor speed.
+  * @note Channel 2 is configured in output PWM 2 mode.
+  * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+  * @note OC2REF is selected as trigger output on TRGO.
+  * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+  *       when TIMx operates in Hall sensor interface mode.
+  * @param  TIMx Timer Instance
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+  uint32_t tmpcr2 = 0U;
+  uint32_t tmpccmr1 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpsmcr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+  assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+  /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+  tmpcr2 |= TIM_CR2_TI1S;
+
+  /* OC2REF signal is used as trigger output (TRGO) */
+  tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+  /* Configure the slave mode controller */
+  tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+  tmpsmcr |= LL_TIM_TS_TI1F_ED;
+  tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+  /* Configure input channel 1 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+  tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+  /* Configure input channel 2 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
+  tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx SMCR */
+  LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  /* Write to TIMx CCR2 */
+  LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the Break and Dead Time configuration data structure
+  *         to their default values.
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+  * @retval None
+  */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
+  TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
+  TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
+  TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00U;
+  TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
+  TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
+  TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
+  TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
+  TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
+  TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
+  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+  * @brief  Configure the Break and Dead Time feature of the timer instance.
+  * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+  *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it 
+  *  can be necessary to configure all of them during the first write access to
+  *  the TIMx_BDTR register.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @param  TIMx Timer Instance
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Break and Dead Time is initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  uint32_t tmpbdtr = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+  
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+  the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+  if (IS_TIM_ADVANCED_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+  }
+
+  if (IS_TIM_BKIN2_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+    assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+    assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+    
+    /* Set the BREAK2 input related BDTR bit-fields */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+  }
+  
+  /* Set TIMx_BDTR */
+  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+  
+  return SUCCESS;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ *  @brief   Private functions
+  * @{
+  */
+/**
+  * @brief  Configure the TIMx output channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+  /* Set the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 5.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr3 = 0U;
+  uint32_t tmpccer = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+  /* Disable the Channel 5: Reset the CC5E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CCMR3 register value */
+  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+  }
+
+  /* Write to TIMx CCMR3 */
+  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 6.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr3 = 0U;
+  uint32_t tmpccer = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+  /* Disable the Channel 5: Reset the CC6E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CCMR3 register value */
+  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CCMR3 */
+  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC3E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+  return SUCCESS;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h
new file mode 100755
index 0000000..0556e17
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h
@@ -0,0 +1,5028 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_tim.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_TIM_H
+#define __STM32L4xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U,   /* 6: TIMx_CH4  */
+  0x3CU,   /* 7: TIMx_CH5  */
+  0x3CU    /* 8: TIMx_CH6  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U,            /* 6: OC4M, OC4FE, OC4PE */
+  0U,            /* 7: OC5M, OC5FE, OC5PE */
+  8U             /* 8: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U,            /* 6: CC4S, IC4PSC, IC4F */
+  0U,            /* 7: - NA */
+  0U             /* 8: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U,           /* 6: CC4P */
+  16U,           /* 7: CC5P */
+  20U            /* 8: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U,            /* 6: OIS4 */
+  8U,            /* 7: OIS5 */
+  10U            /* 8: OIS6 */
+};
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE            POSITION_VAL(Source)
+
+/* Generic bit definitions for TIMx_OR2 register */
+#define TIMx_OR2_BKINE     TIM1_OR2_BKINE     /*!< BRK BKIN input enable */
+#define TIMx_OR2_BKCOMP1E  TIM1_OR2_BKCMP1E   /*!< BRK COMP1 enable */
+#define TIMx_OR2_BKCOMP2E  TIM1_OR2_BKCMP2E   /*!< BRK COMP2 enable */
+#if defined(DFSDM1_Channel0)
+#define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */
+#endif /* DFSDM1_Channel0 */
+#define TIMx_OR2_BKINP     TIM1_OR2_BKINP     /*!< BRK BKIN input polarity */
+#define TIMx_OR2_BKCOMP1P  TIM1_OR2_BKCMP1P   /*!< BRK COMP1 input polarity */
+#define TIMx_OR2_BKCOMP2P  TIM1_OR2_BKCMP2P   /*!< BRK COMP2 input polarity */
+#define TIMx_OR2_ETRSEL    TIM1_OR2_ETRSEL    /*!< TIMx ETR source selection */
+
+/* Generic bit definitions for TIMx_OR3 register */
+#define TIMx_OR3_BK2INE    TIM1_OR3_BK2INE      /*!< BRK2 BKIN2 input enable */
+#define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E    /*!< BRK2 COMP1 enable */
+#define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E    /*!< BRK2 COMP2 enable */
+#if defined(DFSDM1_Channel0)
+#define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /*!< BRK2 DFSDM1_BREAK[1] enable */
+#endif /* DFSDM1_Channel0 */
+#define TIMx_OR3_BK2INP    TIM1_OR3_BK2INP      /*!< BRK2 BKIN2 input polarity */
+#define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P    /*!< BRK2 COMP1 input polarity */
+#define TIMx_OR3_BK2COMP2P  TIM1_OR3_BK2CMP2P   /*!< BRK2 COMP2 input polarity */
+
+/* Remap mask definitions */
+#define TIMx_OR1_RMP_SHIFT 16U
+#define TIMx_OR1_RMP_MASK  0x0000FFFFU
+#if defined(ADC3)
+#define TIM1_OR1_RMP_MASK  ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
+#else
+#define TIM1_OR1_RMP_MASK  ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
+#endif /* ADC3 */
+#define TIM2_OR1_RMP_MASK  ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
+#define TIM3_OR1_RMP_MASK  (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+#define TIM8_OR1_RMP_MASK  ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
+#define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+#define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+#define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7FU)
+#define DT_DELAY_2 ((uint8_t)0x3FU)
+#define DT_DELAY_3 ((uint8_t)0x1FU)
+#define DT_DELAY_4 ((uint8_t)0x1FU)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00U)
+#define DT_RANGE_2 ((uint8_t)0x80U)
+#define DT_RANGE_3 ((uint8_t)0xC0U)
+#define DT_RANGE_4 ((uint8_t)0xE0U)
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+*/
+#if defined(DFSDM1_Channel0)
+#define TIMx_OR2_BKDFBK0E   TIMx_OR2_BKDF1BK0E
+#define TIMx_OR3_BK2DFBK1E  TIMx_OR3_BK2DF1BK1E
+#endif /* DFSDM1_Channel0 */
+/**
+@endcond
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+    (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+     ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+     ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+
+  uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   This parameter must be a number between 0x00 and 0xFF.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/** 
+  * @brief  BDTR (Break and Dead Time) structure definition 
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+  
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+  
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+  
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
+                                            has been written, their content is frozen until the next reset.*/ 
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+  
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not. 
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+  
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+  
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not. 
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+  
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+  
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+  
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+  * @{
+  */
+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */ 
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                       /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
+#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+  * @{
+  */
+#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                              /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1              TIM_SMCR_SMS_0                    /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X2_TI2              TIM_SMCR_SMS_1                    /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X4_TI12             (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges                                                                                                                                                                   depending on the level of the other input l */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+  * @{
+  */
+#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                      /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                    /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                    /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                  /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                    /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                  /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                  /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)  /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
+  * @{
+  */
+#define LL_TIM_ETRSOURCE_LEGACY                0x00000000U                                                 /*!< ETR legacy mode */
+#define LL_TIM_ETRSOURCE_COMP1                 TIM1_OR2_ETRSEL_0                                 /*!< COMP1 output connected to ETR input */
+#define LL_TIM_ETRSOURCE_COMP2                 TIM1_OR2_ETRSEL_1                                 /*!< COMP2 output connected to ETR input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+  * @{
+  */
+#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+  * @{
+  */
+#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+  * @{
+  */
+#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
+  * @{
+  */
+#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
+#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
+  * @{
+  */
+#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_OR2_BKINE      /*!< BKIN input from AF controller */
+#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_OR2_BKCMP1E    /*!< internal signal: COMP1 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_OR2_BKCMP2E    /*!< internal signal: COMP2 output */
+#define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_OR2_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
+  * @{
+  */
+#define LL_TIM_BKIN_POLARITY_LOW               TIM1_OR2_BKINP          /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_OR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_OR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR3           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_OR3 register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP  TIM1 External Trigger ADC1 Remap
+  * @{
+  */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_NC   TIM1_OR1_RMP_MASK                                                /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK)                    /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK)                    /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK)                      /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
+/**
+  * @}
+  */
+
+#if defined(ADC3)
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP  TIM1 External Trigger ADC3 Remap
+  * @{
+  */
+#define LL_TIM_TIM1_ETR_ADC3_RMP_NC   TIM1_OR1_RMP_MASK                                                /*!< TIM1_ETR is not connected to ADC3 analog watchdog  x*/
+#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK)                    /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK)                    /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK)                      /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */
+/**
+  * @}
+  */
+#endif /* ADC3 */
+
+/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM1_TI1_RMP_GPIO  TIM1_OR1_RMP_MASK                                                    /*!< TIM1 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK)                               /*!< TIM1 input capture 1 is connected to COMP1 output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP  TIM2 Internal Trigger1 Remap
+  * @{
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO  TIM2_OR1_RMP_MASK                                              /*!< TIM2_ITR1 is connected to TIM8_TRGO */
+#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK)                        /*!< TIM2_ITR1 is connected to OTG_FS SOF */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define LL_TIM_TIM2_ITR1_RMP_NONE          0x00000000U                                                 /* !< No internal trigger on TIM2_ITR1 */
+#define LL_TIM_TIM2_ITR1_RMP_USB_SOF       TIM2_OR1_ITR1_RMP                                           /* !< TIM2_ITR1 is connected to USB SOF */
+#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
+       /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK                                                     /*!< TIM2_ETR is connected to GPIO */
+#define LL_TIM_TIM2_ETR_RMP_LSE  (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK)                               /*!< TIM2_ETR is connected to LSE  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 External Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI4_RMP_GPIO        TIM2_OR1_RMP_MASK                                              /*!< TIM2 input capture 4 is connected to GPIO */
+#define LL_TIM_TIM2_TI4_RMP_COMP1       (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK)                       /*!< TIM2 input capture 4 is connected to COMP1_OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP2       (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK)                       /*!< TIM2 input capture 4 is connected to COMP2_OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK)                         /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
+/**
+  * @}
+  */
+
+#if defined(TIM3)
+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI1_RMP_GPIO         TIM3_OR1_RMP_MASK                                             /*!< TIM3 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM3_TI1_RMP_COMP1        (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK)                      /*!< TIM3 input capture 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP2        (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK)                      /*!< TIM3 input capture 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2  (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK)                        /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */
+/**
+  * @}
+  */
+#endif /* TIM3 */
+
+#if defined(TIM8)
+/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP  TIM8 External Trigger ADC2 Remap
+  * @{
+  */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_NC   TIM8_OR1_RMP_MASK                                                /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK)                    /*!< TIM8_ETR is connected to ADC2 analog watchdog */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK)                    /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK)                      /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP  TIM8 External Trigger ADC3 Remap
+  * @{
+  */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_NC   TIM8_OR1_RMP_MASK                                                /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK)                    /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK)                    /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK)                      /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM8_TI1_RMP_GPIO  TIM8_OR1_RMP_MASK                                                    /*!< TIM8 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK)                               /*!< TIM8 input capture 1 is connected to COMP2 output */
+/**
+  * @}
+  */
+#endif /* TIM8 */
+
+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK                                                   /*!< TIM15 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_LSE  (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK)                             /*!< TIM15 input capture 1 is connected to LSE */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_ENCODERMODE  TIM15 ENCODERMODE
+  * @{
+  */
+#define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK                                      /*!< No redirection*/
+#define LL_TIM_TIM15_ENCODERMODE_TIM2          (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK)         /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#define LL_TIM_TIM15_ENCODERMODE_TIM3          (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK)         /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/
+#define LL_TIM_TIM15_ENCODERMODE_TIM4          (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK)           /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK                                                   /*!< TIM16 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_LSI  (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)                           /*!< TIM16 input capture 1 is connected to LSI */
+#define LL_TIM_TIM16_TI1_RMP_LSE  (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)                           /*!< TIM16 input capture 1 is connected to LSE */
+#define LL_TIM_TIM16_TI1_RMP_RTC  (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)     /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
+#if defined TIM16_OR1_TI1_RMP_2
+#define LL_TIM_TIM16_TI1_RMP_MSI     (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK)                           /*!< TIM16 input capture 1 is connected to MSI */
+#define LL_TIM_TIM16_TI1_RMP_HSE_32  (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)     /*!< TIM16 input capture 1 is connected to HSE/32 */
+#define LL_TIM_TIM16_TI1_RMP_MCO     (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)     /*!< TIM16 input capture 1 is connected to MCO */
+#endif
+/**
+  * @}
+  */
+
+#if defined(TIM17)
+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM17_TI1_RMP_GPIO   TIM17_OR1_RMP_MASK                                                 /*!< TIM17 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM17_TI1_RMP_MSI    (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK)                         /*!< TIM17 input capture 1 is connected to MSI */
+#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK)                         /*!< TIM17 input capture 1 is connected to HSE/32 */
+#define LL_TIM_TIM17_TI1_RMP_MCO    (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK)                           /*!< TIM17 input capture 1 is connected to MCO */
+/**
+  * @}
+  */
+#endif /* TIM17 */
+
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+  * @{
+  */
+#define LL_TIM_OCREF_CLR_INT_NC     0x00000000U         /*!< OCREF_CLR_INT is not connected */
+#define LL_TIM_OCREF_CLR_INT_ETR    TIM_SMCR_OCCS       /*!< OCREF_CLR_INT is connected to ETRF */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+*/
+#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
+/**
+@endcond
+  */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+  * @{
+  */
+/**
+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+  *        to TIMx_CNT register bit 31)
+  * @param  __CNT__ Counter value
+  * @retval UIF status bit
+  */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+    ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
+      (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
+      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
+      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
+       0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+   ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+     (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+          / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+           + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+  * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+  * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note For advanced timer instances RepetitionCounter can be up to 65535.
+  * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+  * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR5, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+  * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+  * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR5));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+  * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+  * @brief  Select on which reference signal the OC5REF is combined to.
+  * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the combined 3-phase PWM mode.
+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+  * @param  TIMx Timer instance
+  * @param  GroupCH5 This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_GROUPCH5_NONE
+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+  * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can be used for ADC synchronization.
+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+  * @param  TIMx Timer Instance
+  * @param  ADCSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO2_RESET
+  *         @arg @ref LL_TIM_TRGO2_ENABLE
+  *         @arg @ref LL_TIM_TRGO2_UPDATE
+  *         @arg @ref LL_TIM_TRGO2_CC1F
+  *         @arg @ref LL_TIM_TRGO2_OC1
+  *         @arg @ref LL_TIM_TRGO2_OC2
+  *         @arg @ref LL_TIM_TRGO2_OC3
+  *         @arg @ref LL_TIM_TRGO2_OC4
+  *         @arg @ref LL_TIM_TRGO2_OC5
+  *         @arg @ref LL_TIM_TRGO2_OC6
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @brief  Select the external trigger (ETR) input source.
+  * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports ETR source selection.
+  * @rmtoll OR2          ETRSEL        LL_TIM_SetETRSource
+  * @param  TIMx Timer instance
+  * @param  ETRSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETRSOURCE_LEGACY
+  *         @arg @ref LL_TIM_ETRSOURCE_COMP1
+  *         @arg @ref LL_TIM_ETRSOURCE_COMP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+
+  MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Configure the break input.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+}
+
+/**
+  * @brief  Enable the break 2 function.
+  * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Disable the break  2 function.
+  * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+}
+
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+}
+
+/**
+  * @brief  Enable the signals connected to the designated timer break input.
+  * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll OR2          BKINE         LL_TIM_EnableBreakInputSource\n
+  *         OR2          BKCMP1E       LL_TIM_EnableBreakInputSource\n
+  *         OR2          BKCMP2E       LL_TIM_EnableBreakInputSource\n
+  *         OR2          BKDFBK0E      LL_TIM_EnableBreakInputSource\n
+  *         OR3          BKINE         LL_TIM_EnableBreakInputSource\n
+  *         OR3          BKCMP1E       LL_TIM_EnableBreakInputSource\n
+  *         OR3          BKCMP2E       LL_TIM_EnableBreakInputSource\n
+  *         OR3          BKDFBK0E      LL_TIM_EnableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+  SET_BIT(*pReg , Source);
+}
+
+/**
+  * @brief  Disable the signals connected to the designated timer break input.
+  * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll OR2          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         OR2          BKCMP1E       LL_TIM_DisableBreakInputSource\n
+  *         OR2          BKCMP2E       LL_TIM_DisableBreakInputSource\n
+  *         OR2          BKDFBK0E      LL_TIM_DisableBreakInputSource\n
+  *         OR3          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         OR3          BKCMP1E       LL_TIM_DisableBreakInputSource\n
+  *         OR3          BKCMP2E       LL_TIM_DisableBreakInputSource\n
+  *         OR3          BKDFBK0E      LL_TIM_DisableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+  CLEAR_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Set the polarity of the break signal for the timer break input.
+  * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll OR2          BKINE         LL_TIM_SetBreakInputSourcePolarity\n
+  *         OR2          BKCMP1E       LL_TIM_SetBreakInputSourcePolarity\n
+  *         OR2          BKCMP2E       LL_TIM_SetBreakInputSourcePolarity\n
+  *         OR2          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
+  *         OR3          BKINE         LL_TIM_SetBreakInputSourcePolarity\n
+  *         OR3          BKCMP1E       LL_TIM_SetBreakInputSourcePolarity\n
+  *         OR3          BKCMP2E       LL_TIM_SetBreakInputSourcePolarity\n
+  *         OR3          BKINP         LL_TIM_SetBreakInputSourcePolarity
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+                                                        uint32_t Polarity)
+{
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+  MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE)));
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  @if STM32L486xx
+  * @rmtoll TIM1_OR1    ETR_ADC1_RMP      LL_TIM_SetRemap\n
+  *         TIM1_OR1    ETR_ADC3_RMP      LL_TIM_SetRemap\n
+  *         TIM1_OR1    TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM8_OR1    ETR_ADC2_RMP      LL_TIM_SetRemap\n
+  *         TIM8_OR1    ETR_ADC3_RMP      LL_TIM_SetRemap\n
+  *         TIM8_OR1    TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM2_OR1    ITR1_RMP          LL_TIM_SetRemap\n
+  *         TIM2_OR1    TI4_RMP           LL_TIM_SetRemap\n
+  *         TIM2_OR1    TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM3_OR1    TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM15_OR1   TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM15_OR1   ENCODER_MODE      LL_TIM_SetRemap\n
+  *         TIM16_OR1   TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM17_OR1   TI1_RMP           LL_TIM_SetRemap
+  @endif
+  @if STM32L443xx
+  * @rmtoll TIM1_OR1    ETR_ADC1_RMP      LL_TIM_SetRemap\n
+  *         TIM1_OR1    ETR_ADC3_RMP      LL_TIM_SetRemap\n
+  *         TIM1_OR1    TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM2_OR1    ITR1_RMP          LL_TIM_SetRemap\n
+  *         TIM2_OR1    TI4_RMP           LL_TIM_SetRemap\n
+  *         TIM2_OR1    TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM15_OR1   TI1_RMP           LL_TIM_SetRemap\n
+  *         TIM15_OR1   ENCODER_MODE      LL_TIM_SetRemap\n
+  *         TIM16_OR1   TI1_RMP           LL_TIM_SetRemap\n
+  @endif
+  * @param  TIMx Timer instance
+  * @param  Remap Remap param depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of OR registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  @if STM32L486xx
+  *         TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
+  *
+  *            . . ADC1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
+  *
+  *            . . ADC3_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
+  *
+  *         TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
+  *
+  *            ITR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+  *
+  *            . . ETR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
+  *
+  *            . . TI4_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
+  *
+  *         TIM3: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
+  *
+  *         TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
+  *
+  *            . . ADC1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
+  *
+  *            . . ADC3_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
+  *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
+  *
+  *         TIM15: any combination of TI1_RMP, ENCODER_MODE where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
+  *
+  *            . . ENCODER_MODE can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
+  *
+  *         TIM16: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
+  *
+  *         TIM17: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
+   @endif
+  @if STM32L443xx
+  *         TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
+  *
+  *            . . ADC1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
+  *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
+  *
+  *         TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
+  *
+  *            ITR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
+  *
+  *            . . ETR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
+  *
+  *            . . TI4_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
+  *
+  *         TIM15: any combination of TI1_RMP, ENCODER_MODE where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
+  *
+  *            . . ENCODER_MODE can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
+  *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
+  *
+  *         TIM16: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
+  @endif
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+  * @{
+  */
+/**
+  * @brief  Set the OCREF clear input source
+  * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+  * @note This function can only be used in Output compare and PWM modes.
+  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
+  * @param  TIMx Timer instance
+  * @param  OCRefClearInputSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_NC
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+}
+
+/**
+  * @brief  Clear the break 2 interrupt flag (B2IF).
+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Clear the system break interrupt flag (SBIF).
+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @brief  Generate break 2 event.
+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_TIM_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c
new file mode 100755
index 0000000..211b7cd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_usart.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   USART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_usart.h"
+#include "stm32l4xx_ll_rcc.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @addtogroup USART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+  * @{
+  */
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \
+                                    && ((__VALUE__) <= 0x0000FFFFU))
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+                                    || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+                                       || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \
+                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+                                      || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize USART registers (Registers restored to their default values).
+  * @param  USARTx USART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are de-initialized
+  *          - ERROR: USART registers are not de-initialized
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+
+  if (USARTx == USART1)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+  }
+  else if (USARTx == USART2)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+  }
+#if defined(USART3)
+  else if (USARTx == USART3)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+  }
+#endif /* USART3 */
+#if defined(UART4)
+  else if (USARTx == UART4)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+  }
+#endif /* UART4 */
+#if defined(UART5)
+  else if (USARTx == UART5)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+  }
+#endif /* UART5 */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize USART registers according to the specified
+  *         parameters in USART_InitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  USARTx USART Instance
+  * @param  USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR1 Configuration ---------------------
+     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+     */
+    MODIFY_REG(USARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+    /*---------------------------- USART CR2 Configuration ---------------------
+     * Configure USARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+     */
+    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+    /*---------------------------- USART CR3 Configuration ---------------------
+     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+     */
+    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- USART BRR Configuration ---------------------
+     * Retrieve Clock frequency used for USART Peripheral
+     */
+    if (USARTx == USART1)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+    }
+    else if (USARTx == USART2)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+    }
+#if defined(USART3)
+    else if (USARTx == USART3)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+    }
+#endif /* USART3 */
+#if defined(UART4)
+    else if (USARTx == UART4)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+    }
+#endif /* UART4 */
+#if defined(UART5)
+    else if (USARTx == UART5)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+    }
+#endif /* UART5 */
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+
+    /* Configure the USART Baud Rate :
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (USART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_USART_SetBaudRate(USARTx,
+                           periphclk,
+                           USART_InitStruct->OverSampling,
+                           USART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR(USARTx->BRR));
+    }
+  }
+  /* Endif (=> USART not in Disabled state => return ERROR) */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+  * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+  /* Set USART_InitStruct fields to default values */
+  USART_InitStruct->BaudRate            = 9600U;
+  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+  * @brief  Initialize USART Clock related settings according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  USARTx USART Instance
+  * @param  USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *         that contains the Clock configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check USART Instance and Clock signal output parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR2 Configuration -----------------------*/
+    /* If Clock signal has to be output */
+    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+    {
+      /* Deactivate Clock signal delivery :
+       * - Disable Clock Output:        USART_CR2_CLKEN cleared
+       */
+      LL_USART_DisableSCLKOutput(USARTx);
+    }
+    else
+    {
+      /* Ensure USART instance is USART capable */
+      assert_param(IS_USART_INSTANCE(USARTx));
+
+      /* Check clock related parameters */
+      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+      /*---------------------------- USART CR2 Configuration -----------------------
+       * Configure USARTx CR2 (Clock signal related bits) with parameters:
+       * - Enable Clock Output:         USART_CR2_CLKEN set
+       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+       */
+      MODIFY_REG(USARTx->CR2,
+                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+    }
+  }
+  /* Else (USART not in Disabled state => return ERROR */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+  * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *                               whose fields will be set to default values.
+  * @retval None
+  */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  /* Set LL_USART_ClockInitStruct fields with default values */
+  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h
new file mode 100755
index 0000000..9fc806d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h
@@ -0,0 +1,3716 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_usart.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_USART_H
+#define __STM32L4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
+#define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise detected flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
+#endif
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data register not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data register empty flag */
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  register uint32_t usartdiv = 0x0U;
+  register uint32_t brrtemp = 0x0U;
+
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+  register uint32_t usartdiv = 0x0U;
+  register uint32_t brrresult = 0x0U;
+
+  usartdiv = USARTx->BRR;
+
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    if ((usartdiv & 0xFFF7U) != 0U)
+    {
+      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+      brrresult = (PeriphClk * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = PeriphClk / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NF            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+}
+
+/**
+  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+}
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
+  * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT));
+}
+#endif
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NCF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+#endif
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Enable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Enable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Disable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE));
+}
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr = 0U;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = Value & 0x1FFU;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data flush
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data flush
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c
new file mode 100755
index 0000000..d31a3b1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c
@@ -0,0 +1,2399 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_usb.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   USB Low Layer HAL module driver.
+  *   
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+  
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @defgroup USB_LL USB Low Layer
+  * @brief Low layer module for USB_FS and USB_OTG_FS drivers
+  * @{
+  */
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+      
+/** @addtogroup STM32L4xx_LL_USB_DRIVER
+  * @{
+  */
+
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined (USB_OTG_FS)
+/** @defgroup USB_LL_Private_Functions USB Low Layer Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup LL_USB_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+/*==============================================================================
+    USB OTG FS peripheral available on STM32L475xx, STM32L476xx, STM32L485xx and 
+    STM32L486xx devices 
+==============================================================================*/
+#if defined (USB_OTG_FS)
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx: USB Instance
+  * @param  cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(cfg);
+
+  /* Select FS Embedded PHY */
+  USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+  
+  /* Reset after a PHY select and set Host mode */
+  USB_CoreReset(USBx);
+  
+  /* Deactivate the power down*/
+  USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx: Selected device
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+   
+/**
+  * @brief  USB_SetCurrentMode : Set functional mode
+  * @param  USBx: Selected device
+  * @param  mode:  current core mode
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_DEVICE_MODE: Peripheral mode
+  *            @arg USB_OTG_HOST_MODE: Host mode
+  *            @arg USB_OTG_DRD_MODE: Dual Role Device mode  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode)
+{
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 
+  
+  if ( mode == USB_HOST_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 
+  }
+  else if ( mode == USB_DEVICE_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 
+  }
+  HAL_Delay(50);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit : Initializes the USB_OTG controller registers 
+  *         for device mode
+  * @param  USBx: Selected device
+  * @param  cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  uint32_t index = 0;
+
+  /*Activate VBUS Sensing B */
+  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  
+  if (cfg.vbus_sensing_enable == 0)
+  {
+    /* Deactivate VBUS Sensing B */
+    USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
+    
+    /* B-peripheral session valid override enable*/ 
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+  }
+   
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0;
+
+  /* Device mode configuration */
+  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
+  
+  /* Set Full speed phy */
+  USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
+
+  /* Flush the FIFOs */
+  USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
+  USB_FlushRxFifo(USBx);
+  
+  /* Clear all pending Device Interrupts */
+  USBx_DEVICE->DIEPMSK = 0;
+  USBx_DEVICE->DOEPMSK = 0;
+  USBx_DEVICE->DAINT = 0xFFFFFFFF;
+  USBx_DEVICE->DAINTMSK = 0;
+  
+  for (index = 0; index < cfg.dev_endpoints; index++)
+  {
+    if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(index)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
+    }
+    else
+    {
+      USBx_INEP(index)->DIEPCTL = 0;
+    }
+    
+    USBx_INEP(index)->DIEPTSIZ = 0;
+    USBx_INEP(index)->DIEPINT  = 0xFF;
+  }
+  
+  for (index = 0; index < cfg.dev_endpoints; index++)
+  {
+    if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(index)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
+    }
+    else
+    {
+      USBx_OUTEP(index)->DOEPCTL = 0;
+    }
+    
+    USBx_OUTEP(index)->DOEPTSIZ = 0;
+    USBx_OUTEP(index)->DOEPINT  = 0xFF;
+  }
+  
+  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+  
+  if (cfg.dma_enable == 1)
+  {
+    /*Set threshold parameters */
+    USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
+    USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
+    
+    index= USBx_DEVICE->DTHRCTL;
+  }
+  
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0;
+  
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xBFFFFFFF;
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == DISABLE)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
+  }
+
+    /* Enable interrupts matching to the Device mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
+                    USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
+                    USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
+
+  if(cfg.Sof_enable)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+  }
+
+  if (cfg.vbus_sensing_enable == ENABLE)
+  {
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
+  * @param  USBx: Selected device
+  * @param  num: FIFO number
+  *         This parameter can be a value from 1 to 15
+            15 means Flush all Tx FIFOs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num)
+{
+  uint32_t count = 0;
+ 
+  USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); 
+ 
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_FlushRxFifo : Flush Rx FIFO
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0;
+  
+  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+  
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register 
+  *         depending the PHY type and the enumeration speed of the device.
+  * @param  USBx: Selected device
+  * @param  speed: device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @retval  Hal status
+  */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
+{
+  USBx_DEVICE->DCFG |= speed;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_GetDevSpeed :Return the  Dev Speed 
+  * @param  USBx: Selected device
+  * @retval speed : device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  */
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint8_t speed = 0;
+  
+  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+  {
+    speed = USB_OTG_SPEED_HIGH;
+  }
+  else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
+           ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
+  {
+    speed = USB_OTG_SPEED_FULL;
+  }
+  else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+  {
+    speed = USB_OTG_SPEED_LOW;
+  }
+  
+  return speed;
+}
+
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  if (ep->is_in == 1)
+  {
+   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
+   
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
+    {
+      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
+    } 
+
+  }
+  else
+  {
+     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
+     
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+       (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
+    } 
+  }
+  return HAL_OK;
+}
+/**
+  * @brief  Activate and configure a dedicated endpoint
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  static __IO uint32_t debug = 0;
+  
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
+    {
+      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
+    } 
+    
+    
+    debug  |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
+    
+   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
+  }
+  else
+  {
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
+      
+      debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
+      debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
+      debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); 
+    } 
+    
+     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+   USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));   
+   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;   
+  }
+  else
+  {
+     USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));     
+     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;      
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize a dedicated endpoint
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+  }
+  else
+  {
+     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; 
+     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint16_t pktcnt = 0;
+  
+  /* IN endpoint */
+  if (ep->is_in == 1)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0)
+    {
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
+      
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 
+        USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); 
+      }       
+    }
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Enable the Tx FIFO Empty Interrupt for this EP */
+        if (ep->xfer_len > 0)
+        {
+          atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK,  1 << ep->num);
+        }
+      }
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
+      {
+        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+      }
+    } 
+    
+    /* EP enable, IN data in FIFO */
+    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);   
+    }    
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */  
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
+      
+    if (ep->xfer_len == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;      
+    }
+    else
+    {
+      pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; 
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ;
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); 
+    }
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
+      {
+        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+      }
+    }
+    /* EP enable */
+    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(dma);
+  
+  /* IN endpoint */
+  if (ep->is_in == 1)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0)
+    {
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      
+      if(ep->xfer_len > ep->maxpacket)
+      {
+        ep->xfer_len = ep->maxpacket;
+      }
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
+    
+    }
+    
+    /* Enable the Tx FIFO Empty Interrupt for this EP */
+    if (ep->xfer_len > 0)
+    {
+	  atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num));
+    }
+    
+    /* EP enable, IN data in FIFO */
+    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);   
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
+      
+    if (ep->xfer_len > 0)
+    {
+      ep->xfer_len = ep->maxpacket;
+    }
+    
+    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
+    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 
+    
+    /* EP enable */
+    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);    
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated 
+  *         with the EP/channel
+  * @param  USBx: Selected device           
+  * @param  src:  pointer to source buffer
+  * @param  ch_ep_num: endpoint or host channel number
+  * @param  len: Number of bytes to write
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(dma);
+  
+  uint32_t count32b= 0 , index= 0;
+  count32b =  (len + 3) / 4;
+  for (index = 0; index < count32b; index++, src += 4)
+  {
+    USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated 
+  *         with the EP/channel
+  * @param  USBx: Selected device  
+  * @param  src: source pointer
+  * @param  ch_ep_num: endpoint or host channel number
+  * @param  len: Number of bytes to read
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval pointer to destination buffer
+  */
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+  uint32_t index=0;
+  uint32_t count32b = (len + 3) / 4;
+  
+  for ( index = 0; index < count32b; index++, dest += 4 )
+  {
+    *(__packed uint32_t *)dest = USBx_DFIFO(0);
+    
+  }
+  return ((void *)dest);
+}
+
+/**
+  * @brief  USB_EPSetStall : set a stall condition over an EP
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
+{
+  if (ep->is_in == 1)
+  {
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
+    {
+      USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 
+    } 
+    USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+  }
+  else
+  {
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 
+    } 
+    USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP
+  * @param  USBx: Selected device
+  * @param  ep: pointer to endpoint structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  if (ep->is_in == 1)
+  {
+    USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+    {
+       USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }    
+  }
+  else
+  {
+    USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }    
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_StopDevice : Stop the USB device mode
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t index;
+  
+  /* Clear Pending interrupt */
+  for (index = 0; index < 15 ; index++)
+  {
+    USBx_INEP(index)->DIEPINT  = 0xFF;
+    USBx_OUTEP(index)->DOEPINT  = 0xFF;
+  }
+  USBx_DEVICE->DAINT = 0xFFFFFFFF;
+  
+  /* Clear interrupt masks */
+  USBx_DEVICE->DIEPMSK  = 0;
+  USBx_DEVICE->DOEPMSK  = 0;
+  USBx_DEVICE->DAINTMSK = 0;
+  
+  /* Flush the FIFO */
+  USB_FlushRxFifo(USBx);
+  USB_FlushTxFifo(USBx ,  0x10 );  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevAddress : Stop the USB device mode
+  * @param  USBx: Selected device
+  * @param  address: new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
+  USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; 
+  HAL_Delay(3);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; 
+  HAL_Delay(3);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+uint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t tmpreg = 0;
+  
+  tmpreg = USBx->GINTSTS;
+  tmpreg &= USBx->GINTMSK;
+  return tmpreg;  
+}
+
+/**
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t tmpreg;
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+  return ((tmpreg & 0xffff0000) >> 16);
+}
+
+/**
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t tmpreg;
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+  return ((tmpreg & 0xFFFF));
+}
+
+/**
+  * @brief  Returns Device OUT EP Interrupt register
+  * @param  USBx: Selected device
+  * @param  epnum: endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device OUT EP Interrupt register
+  */
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+{
+  uint32_t tmpreg;
+  tmpreg  = USBx_OUTEP(epnum)->DOEPINT;
+  tmpreg &= USBx_DEVICE->DOEPMSK;
+  return tmpreg;
+}
+
+/**
+  * @brief  Returns Device IN EP Interrupt register
+  * @param  USBx: Selected device
+  * @param  epnum: endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device IN EP Interrupt register
+  */
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+{
+  uint32_t tmpreg = 0, msk = 0, emp = 0;
+  
+  msk = USBx_DEVICE->DIEPMSK;
+  emp = USBx_DEVICE->DIEPEMPMSK;
+  msk |= ((emp >> epnum) & 0x1) << 7;
+  tmpreg = USBx_INEP(epnum)->DIEPINT & msk;
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ClearInterrupts: clear a USB interrupt
+  * @param  USBx: Selected device
+  * @param  interrupt: interrupt flag
+  * @retval None
+  */
+void  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+  USBx->GINTSTS |= interrupt; 
+}
+
+/**
+  * @brief  Returns USB core mode
+  * @param  USBx: Selected device
+  * @retval return core mode : Host or Device
+  *          This parameter can be one of these values:
+  *           0 : Host 
+  *           1 : Device
+  */
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx->GINTSTS ) & 0x1);
+}
+
+
+/**
+  * @brief  Activate EP0 for Setup transactions
+  * @param  USBx: Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
+{
+  /* Set the MPS of the IN EP based on the enumeration speed */
+  USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+  
+  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+  {
+    USBx_INEP(0)->DIEPCTL |= 3;
+  }
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Prepare the EP0 to start the first control setup
+  * @param  USBx: Selected device
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @param  psetup: pointer to setup packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(psetup);
+
+  USBx_OUTEP(0)->DOEPTSIZ = 0;
+  USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
+  USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
+  USBx_OUTEP(0)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers 
+  *         for Host mode 
+  * @param  USBx: Selected device
+  * @param  cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  uint32_t index = 0;
+  
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0;
+  
+  /* Disable the FS/LS support mode only */
+  if((cfg.speed == USB_OTG_SPEED_FULL)&&
+     (USBx != USB_OTG_FS))
+  {
+    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; 
+  }
+  else
+  {
+    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);  
+  }
+
+  /* Make sure the FIFOs are flushed. */
+  USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
+  USB_FlushRxFifo(USBx);
+
+  /* Clear all pending HC Interrupts */
+  for (index = 0; index < cfg.Host_channels; index++)
+  {
+    USBx_HC(index)->HCINT = 0xFFFFFFFF;
+    USBx_HC(index)->HCINTMSK = 0;
+  }
+  
+  /* Enable VBUS driving */
+  USB_DriveVbus(USBx, 1);
+  
+  HAL_Delay(200);
+  
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0;
+  
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xFFFFFFFF;
+  
+  /* set Rx FIFO size */
+  USBx->GRXFSIZ  = (uint32_t )0x80; 
+  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
+  USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
+  
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == DISABLE)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
+  }
+
+    /* Enable interrupts matching to the Host mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\
+                    USB_OTG_GINTMSK_SOFM             |USB_OTG_GINTSTS_DISCINT|\
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the 
+  *         HCFG register on the PHY type and set the right frame interval
+  * @param  USBx: Selected device
+  * @param  freq: clock frequency
+  *          This parameter can be one of these values:
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock 
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
+{
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+  USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
+  
+  if (freq ==  HCFG_48_MHZ)
+  {
+    USBx_HOST->HFIR = (uint32_t)48000;
+  }
+  else if (freq ==  HCFG_6_MHZ)
+  {
+    USBx_HOST->HFIR = (uint32_t)6000;
+  } 
+  return HAL_OK;  
+}
+
+/**
+* @brief  USB_OTG_ResetPort : Reset Host Port
+  * @param  USBx: Selected device
+  * @retval HAL status
+  * @note   (1)The application must wait at least 10 ms
+  *   before clearing the reset bit.
+  */
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t hprt0 = 0;
+  
+  hprt0 = USBx_HPRT0;
+  
+  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
+    USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+  
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);  
+  HAL_Delay (10);                                /* See Note #1 */
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DriveVbus : activate or de-activate vbus
+  * @param  state: VBUS state
+  *          This parameter can be one of these values:
+  *           0 : VBUS Active 
+  *           1 : VBUS Inactive
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+  __IO uint32_t hprt0 = 0;
+  
+  hprt0 = USBx_HPRT0;
+  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
+                         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+  
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
+  {
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); 
+  }
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
+  {
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); 
+  }
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Return Host Core speed
+  * @param  USBx: Selected device
+  * @retval speed : Host speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  */
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t hprt0 = 0;
+  
+  hprt0 = USBx_HPRT0;
+  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
+}
+
+/**
+  * @brief  Return Host Current Frame number
+  * @param  USBx: Selected device
+  * @retval current frame number
+*/
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
+{
+  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+  * @brief  Initialize a host channel
+  * @param  USBx: Selected device
+  * @param  ch_num : Channel number
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum: Endpoint number
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address: Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed: Current device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @param  ep_type: Endpoint Type
+  *          This parameter can be one of these values:
+  *            @arg EP_TYPE_CTRL: Control type
+  *            @arg EP_TYPE_ISOC: Isochronous type
+  *            @arg EP_TYPE_BULK: Bulk type
+  *            @arg EP_TYPE_INTR: Interrupt type
+  * @param  mps: Max Packet Size
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
+                              uint8_t ch_num,
+                              uint8_t epnum,
+                              uint8_t dev_address,
+                              uint8_t speed,
+                              uint8_t ep_type,
+                              uint16_t mps)
+{
+    
+  /* Clear old interrupt conditions for this host channel. */
+  USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
+  
+  /* Enable channel interrupts required for this transfer. */
+  switch (ep_type) 
+  {
+  case EP_TYPE_CTRL:
+  case EP_TYPE_BULK:
+    
+    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
+                                USB_OTG_HCINTMSK_STALLM |\
+                                USB_OTG_HCINTMSK_TXERRM |\
+                                USB_OTG_HCINTMSK_DTERRM |\
+                                USB_OTG_HCINTMSK_AHBERR |\
+                                USB_OTG_HCINTMSK_NAKM ;
+ 
+    if (epnum & 0x80) 
+    {
+      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+    }
+    break;
+    
+  case EP_TYPE_INTR:
+    
+    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
+                                USB_OTG_HCINTMSK_STALLM |\
+                                USB_OTG_HCINTMSK_TXERRM |\
+                                USB_OTG_HCINTMSK_DTERRM |\
+                                USB_OTG_HCINTMSK_NAKM   |\
+                                USB_OTG_HCINTMSK_AHBERR |\
+                                USB_OTG_HCINTMSK_FRMORM ;    
+    
+    if (epnum & 0x80) 
+    {
+      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+    }
+    
+    break;
+  case EP_TYPE_ISOC:
+    
+    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
+                                USB_OTG_HCINTMSK_ACKM   |\
+                                USB_OTG_HCINTMSK_AHBERR |\
+                                USB_OTG_HCINTMSK_FRMORM ;   
+    
+    if (epnum & 0x80) 
+    {
+      USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);      
+    }
+    break;
+  }
+  
+  /* Enable the top level host channel interrupt. */
+  USBx_HOST->HAINTMSK |= (1 << ch_num);
+  
+  /* Make sure host channel interrupts are enabled. */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+  
+  /* Program the HCCHAR register */
+  USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD)  |\
+                             (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
+                             ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
+                             (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
+                             ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
+                             (mps & USB_OTG_HCCHAR_MPSIZ));
+    
+  if (ep_type == EP_TYPE_INTR)
+  {
+    USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+  }
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Start a transfer over a host channel
+  * @param  USBx: Selected device
+  * @param  hc: pointer to host channel structure
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL state
+  */
+#if defined   (__CC_ARM) /*!< ARM Compiler */
+#pragma O0
+#elif defined (__GNUC__) /*!< GNU Compiler */
+#pragma GCC optimize ("O0")
+#endif /* __CC_ARM */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+  uint8_t  is_oddframe = 0; 
+  uint16_t len_words = 0;   
+  uint16_t num_packets = 0;
+  uint16_t max_hc_pkt_count = 256;
+  uint32_t tmpreg = 0;
+    
+  /* Compute the expected number of packets associated to the transfer */
+  if (hc->xfer_len > 0)
+  {
+    num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
+    
+    if (num_packets > max_hc_pkt_count)
+    {
+      num_packets = max_hc_pkt_count;
+      hc->xfer_len = num_packets * hc->max_packet;
+    }
+  }
+  else
+  {
+    num_packets = 1;
+  }
+  if (hc->ep_is_in)
+  {
+    hc->xfer_len = num_packets * hc->max_packet;
+  }
+  
+  /* Initialize the HCTSIZn register */
+  USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
+    ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
+      (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
+  
+  if (dma)
+  {
+    /* xfer_buff MUST be 32-bits aligned */
+    USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+  }
+  
+  is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
+  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+  USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
+  
+  /* Set host channel enable */
+  tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
+  
+  if (dma == 0) /* Slave mode */
+  {  
+    if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
+    {
+      switch(hc->ep_type) 
+      {
+        /* Non periodic transfer */
+      case EP_TYPE_CTRL:
+      case EP_TYPE_BULK:
+        
+        len_words = (hc->xfer_len + 3) / 4;
+        
+        /* check if there is enough space in FIFO space */
+        if(len_words > (USBx->HNPTXSTS & 0xFFFF))
+        {
+          /* need to process data in nptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+        }
+        break;
+        /* Periodic transfer */
+      case EP_TYPE_INTR:
+      case EP_TYPE_ISOC:
+        len_words = (hc->xfer_len + 3) / 4;
+        /* check if there is enough space in FIFO space */
+        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
+        {
+          /* need to process data in ptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;          
+        }
+        break;
+        
+      default:
+        break;
+      }
+      
+      /* Write packet into the Tx FIFO. */
+      USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
+      hc->xfer_count = hc->xfer_len;
+
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Read all host channel interrupts status
+  * @param  USBx: Selected device
+  * @retval HAL state
+  */
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx_HOST->HAINT) & 0xFFFF);
+}
+
+/**
+  * @brief  Halt a host channel
+  * @param  USBx: Selected device
+  * @param  hc_num: Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
+{
+  uint32_t count = 0;
+  
+  /* Check for space in the request queue to issue the halt. */
+  if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
+  {
+    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+    
+    if ((USBx->HNPTXSTS & 0xFFFF) == 0)
+    {
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do 
+      {
+        if (++count > 1000) 
+        {
+          break;
+        }
+      } 
+      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
+    }
+    else
+    {
+      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
+    }
+  }
+  else
+  {
+    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+    
+    if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
+    {
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do 
+      {
+        if (++count > 1000) 
+        {
+          break;
+        }
+      } 
+      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
+    }
+    else
+    {
+       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initiate Do Ping protocol
+  * @param  USBx: Selected device
+  * @param  hc_num: Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
+{
+  uint8_t  num_packets = 1;
+  uint32_t tmpreg = 0;
+  
+  USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
+                                USB_OTG_HCTSIZ_DOPING;
+  
+  /* Set host channel enable */
+  tmpreg = USBx_HC(ch_num)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(ch_num)->HCCHAR = tmpreg;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Stop Host Core
+  * @param  USBx: Selected device
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint8_t index;
+  uint32_t count = 0;
+  uint32_t value = 0;
+  
+  USB_DisableGlobalInt(USBx);
+  
+    /* Flush FIFO */
+  USB_FlushTxFifo(USBx, 0x10);
+  USB_FlushRxFifo(USBx);
+  
+  /* Flush out any leftover queued requests. */
+  for (index = 0; index <= 15; index++)
+  {
+    value = USBx_HC(index)->HCCHAR;
+    value |=  USB_OTG_HCCHAR_CHDIS;
+    value &= ~USB_OTG_HCCHAR_CHENA;  
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(index)->HCCHAR = value;
+  }
+  
+  /* Halt all channels to put them into a known state. */
+  for (index = 0; index <= 15; index++)
+  {
+    value = USBx_HC(index)->HCCHAR ;
+    value |= USB_OTG_HCCHAR_CHDIS;
+    value |= USB_OTG_HCCHAR_CHENA;  
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(index)->HCCHAR = value;
+    
+    USBx_HC(index)->HCCHAR = value;
+    do 
+    {
+      if (++count > 1000) 
+      {
+        break;
+      }
+    }
+    while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+  }
+
+  /* Clear any pending Host interrupts */  
+  USBx_HOST->HAINT = 0xFFFFFFFF;
+  USBx->GINTSTS = 0xFFFFFFFF;
+  USB_EnableGlobalInt(USBx);
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+  {
+    /* active Remote wakeup signalling */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  /* active Remote wakeup signalling */
+   USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+  return HAL_OK;
+}
+
+#endif /* USB_OTG_FS */
+
+/*==============================================================================
+    USB Device FS peripheral available on STM32L432xx, STM32L433xx, STM32L442xx)
+    and STM32L443xx devices 
+==============================================================================*/
+#if defined (USB)
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx: USB Instance
+  * @param  cfg : pointer to a USB_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(cfg);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
+{
+  uint32_t winterruptmask = 0;
+  
+  /* Set winterruptmask variable */
+  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+    | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+  
+  /* Set interrupt mask */
+  USBx->CNTR |= winterruptmask;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx : Selected device
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
+{
+  uint32_t winterruptmask = 0;
+  
+  /* Set winterruptmask variable */
+  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+    | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+  
+  /* Clear interrupt mask */
+  USBx->CNTR &= ~winterruptmask;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetCurrentMode : Set functional mode
+  * @param  USBx : Selected device
+  * @param  mode :  current core mode
+  *          This parameter can be one of the these values:
+  *            @arg USB_DEVICE_MODE: Peripheral mode mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(mode);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit : Initializes the USB controller registers 
+  *         for device mode
+  * @param  USBx : Selected device
+  * @param  cfg  : pointer to a USB_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(cfg);
+
+  /* Init Device */
+  /*CNTR_FRES = 1*/
+  USBx->CNTR = USB_CNTR_FRES;
+  
+  /*CNTR_FRES = 0*/
+  USBx->CNTR = 0;
+ 
+  /*Clear pending interrupts*/
+  USBx->ISTR = 0;
+  
+  /*Set Btable Address*/
+  USBx->BTABLE = BTABLE_ADDRESS;
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_FlushTxFifo : Flush a Tx FIFO
+  * @param  USBx : Selected device
+  * @param  num : FIFO number
+  *         This parameter can be a value from 1 to 15
+            15 means Flush all Tx FIFOs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num )
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(num);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_FlushRxFifo : Flush Rx FIFO
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  /* initialize Endpoint */
+  switch (ep->type)
+  {
+  case EP_TYPE_CTRL:
+    PCD_SET_EPTYPE(USBx, ep->num, USB_EP_CONTROL);
+    break;
+  case EP_TYPE_BULK:
+    PCD_SET_EPTYPE(USBx, ep->num, USB_EP_BULK);
+    break;
+  case EP_TYPE_INTR:
+    PCD_SET_EPTYPE(USBx, ep->num, USB_EP_INTERRUPT);
+    break;
+  case EP_TYPE_ISOC:
+    PCD_SET_EPTYPE(USBx, ep->num, USB_EP_ISOCHRONOUS);
+    break;
+  default:
+      break;
+  } 
+  
+  PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
+  
+  if (ep->doublebuffer == 0) 
+  {
+    if (ep->is_in)
+    {
+      /*Set the endpoint Transmit buffer address */
+      PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+      /* Configure NAK status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 
+    }
+    else
+    {
+      /*Set the endpoint Receive buffer address */
+      PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+      /*Set the endpoint Receive buffer counter*/
+      PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      /* Configure VALID status for the Endpoint*/
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+    }
+  }
+  /*Double Buffer*/
+  else
+  {
+    /*Set the endpoint as double buffered*/
+    PCD_SET_EP_DBUF(USBx, ep->num);
+    /*Set buffer address for double buffered mode*/
+    PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1);
+    
+    if (ep->is_in==0)
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+      
+      /* Reset value of the data toggle bits for the endpoint out*/
+      PCD_TX_DTOG(USBx, ep->num);
+      
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+    }
+    else
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+      PCD_RX_DTOG(USBx, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  if (ep->doublebuffer == 0) 
+  {
+    if (ep->is_in)
+    {
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 
+    }
+    else
+    {
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+    }
+  }
+  /*Double Buffer*/
+  else
+  { 
+    if (ep->is_in==0)
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+      
+      /* Reset value of the data toggle bits for the endpoint out*/
+      PCD_TX_DTOG(USBx, ep->num);
+      
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+    }
+    else
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+      PCD_RX_DTOG(USBx, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t dma)
+{
+  uint16_t pmabuffer = 0;
+  uint32_t len = ep->xfer_len;
+  
+  /* IN endpoint */
+  if (ep->is_in == 1)
+  {
+    /*Multi packet transfer*/
+    if (ep->xfer_len > ep->maxpacket)
+    {
+      len=ep->maxpacket;
+      ep->xfer_len-=len; 
+    }
+    else
+    {  
+      len=ep->xfer_len;
+      ep->xfer_len =0;
+    }
+    
+    /* configure and validate Tx endpoint */
+    if (ep->doublebuffer == 0) 
+    {
+      USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len);
+      PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+    }
+    else
+    {
+      /* Write the data to the USB endpoint */
+      if (PCD_GET_ENDPOINT(USBx, ep->num)& USB_EP_DTOG_TX)
+      {
+        /* Set the Double buffer counter for pmabuffer1 */
+        PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+        pmabuffer = ep->pmaaddr1;
+      }
+      else
+      {
+        /* Set the Double buffer counter for pmabuffer0 */
+        PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+        pmabuffer = ep->pmaaddr0;
+      }
+      USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len);
+      PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
+    }
+    
+    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
+  }
+  else /* OUT endpoint */
+  {
+    /* Multi packet transfer*/
+    if (ep->xfer_len > ep->maxpacket)
+    {
+      len=ep->maxpacket;
+      ep->xfer_len-=len; 
+    }
+    else
+    {
+      len=ep->xfer_len;
+      ep->xfer_len =0;
+    }
+    
+    /* configure and validate Rx endpoint */
+    if (ep->doublebuffer == 0) 
+    {
+      /*Set RX buffer count*/
+      PCD_SET_EP_RX_CNT(USBx, ep->num, len);
+    }
+    else
+    {
+      /*Set the Double buffer counter*/
+      PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+    }
+    
+    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated 
+  *         with the EP/channel
+  * @param  USBx : Selected device
+  * @param  src :  pointer to source buffer
+  * @param  ch_ep_num : endpoint or host channel number
+  * @param  len : Number of bytes to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(src);
+  UNUSED(ch_ep_num);
+  UNUSED(len);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated 
+  *         with the EP/channel
+  * @param  USBx : Selected device
+  * @param  dest : destination pointer
+  * @param  len : Number of bytes to read
+  * @retval pointer to destination buffer
+  */
+void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(dest);
+  UNUSED(len);
+
+  return ((void *)NULL);
+}
+
+/**
+  * @brief  USB_EPSetStall : set a stall condition over an EP
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep)
+{
+  if (ep->num == 0)
+  {
+    /* This macro sets STALL status for RX & TX*/ 
+    PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); 
+  }
+  else
+  {
+    if (ep->is_in)
+    {
+      PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); 
+    }
+    else
+    {
+      PCD_SET_EP_RX_STATUS(USBx, ep->num , USB_EP_RX_STALL);
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  if (ep->is_in)
+  {
+    PCD_CLEAR_TX_DTOG(USBx, ep->num);
+    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
+  }
+  else
+  {
+    PCD_CLEAR_RX_DTOG(USBx, ep->num);
+    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_StopDevice : Stop the usb device mode
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
+{
+  /* disable all interrupts and force USB reset */
+  USBx->CNTR = USB_CNTR_FRES;
+  
+  /* clear interrupt status register */
+  USBx->ISTR = 0;
+  
+  /* switch-off device */
+  USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevAddress : Stop the usb device mode
+  * @param  USBx : Selected device
+  * @param  address : new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address)
+{
+  if(address == 0) 
+  {
+   /* set device address and enable function */
+   USBx->DADDR = USB_DADDR_EF;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevConnect (USB_TypeDef *USBx)
+{
+  /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
+  USB->BCDR |= USB_BCDR_DPPU;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevDisconnect (USB_TypeDef *USBx)
+{
+  /* Disable DP Pull-Down bit*/
+  USB->BCDR &= ~(USB_BCDR_DPPU);
+   
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+uint32_t  USB_ReadInterrupts (USB_TypeDef *USBx)
+{
+  uint32_t tmpreg = 0;
+  
+  tmpreg = USBx->ISTR;
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+
+  return (0);
+}
+
+/**
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+
+  return (0);
+}
+
+/**
+  * @brief  Returns Device OUT EP Interrupt register
+  * @param  USBx : Selected device
+  * @param  epnum : endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device OUT EP Interrupt register
+  */
+uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(epnum);
+
+  return (0);
+}
+
+/**
+  * @brief  Returns Device IN EP Interrupt register
+  * @param  USBx : Selected device
+  * @param  epnum : endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device IN EP Interrupt register
+  */
+uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(epnum);
+
+  return (0);
+}
+
+/**
+  * @brief  USB_ClearInterrupts: clear a USB interrupt
+  * @param  USBx : Selected device
+  * @param  interrupt : interrupt flag
+  * @retval None
+  */
+void  USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(interrupt);
+}
+
+/**
+  * @brief  Prepare the EP0 to start the first control setup
+  * @param  USBx : Selected device
+  * @param  psetup : pointer to setup packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma ,uint8_t *psetup)
+{
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used 
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(psetup);
+  UNUSED(dma);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
+{
+  USBx->CNTR |= USB_CNTR_RESUME;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
+{
+  USBx->CNTR &= ~(USB_CNTR_RESUME);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Copy a buffer from user memory area to packet memory area (PMA)
+  * @param  USBx : pointer to USB register.
+  * @param  pbUsrBuf : pointer to user memory area.
+  * @param  wPMABufAddr : address into PMA.
+  * @param  wNBytes : number of bytes to be copied.
+  * @retval None
+  */
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = (wNBytes + 1) >> 1;
+  uint32_t i;
+  uint16_t temp1, temp2;
+  uint16_t *pdwVal;
+  pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+
+  for (i = n; i != 0; i--)
+  {
+    temp1 = (uint16_t) * pbUsrBuf;
+    pbUsrBuf++;
+    temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+    *pdwVal++ = temp2;
+    pbUsrBuf++;
+  }
+}
+
+/**
+  * @brief  Copy a buffer from user memory area to packet memory area (PMA)
+  * @param  USBx : pointer to USB register.
+* @param  pbUsrBuf : pointer to user memory area.
+  * @param  wPMABufAddr : address into PMA.
+  * @param  wNBytes : number of bytes to be copied.
+  * @retval None
+  */
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = (wNBytes + 1) >> 1;
+  uint32_t i;
+  uint16_t *pdwVal;
+  pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+  for (i = n; i != 0; i--)
+  {
+    *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+    pbUsrBuf++;
+  }
+}
+#endif /* USB */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#if defined (USB_OTG_FS)
+/** @addtogroup USB_LL_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Reset the USB Core (needed after USB clock settings change)
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0;
+  
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
+  
+  /* Core Soft Reset */
+  count = 0;
+  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+  
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+  
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS */
+
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h
new file mode 100755
index 0000000..9b30b10
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h
@@ -0,0 +1,617 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_usb.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of USB Core HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_USB_H
+#define __STM32L4xx_LL_USB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+      
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL
+  * @{
+  */
+
+/** @addtogroup USB_Core
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  USB Mode definition  
+  */  
+typedef enum 
+{
+   USB_DEVICE_MODE  = 0,
+   USB_HOST_MODE    = 1,
+   USB_DRD_MODE     = 2
+   
+}USB_ModeTypeDef;
+
+#if defined (USB_OTG_FS)
+/** 
+  * @brief  URB States definition  
+  */ 
+typedef enum {
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_NYET,
+  URB_ERROR,
+  URB_STALL
+    
+}USB_OTG_URBStateTypeDef;
+
+/** 
+  * @brief  Host channel States  definition  
+  */ 
+typedef enum {
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,  
+  HC_BBLERR,   
+  HC_DATATGLERR
+    
+}USB_OTG_HCStateTypeDef;
+
+/** 
+  * @brief  PCD Initialization Structure definition  
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;        /*!< Device Endpoints number.
+                                      This parameter depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    
+  
+  uint32_t Host_channels;        /*!< Host Channels number.
+                                      This parameter Depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */       
+
+  uint32_t speed;                /*!< USB Core speed.
+                                      This parameter can be any value of @ref USB_Core_Speed_                */        
+                               
+  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */            
+
+  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
+                                      This parameter can be any value of @ref USB_EP0_MPS_                   */              
+                       
+  uint32_t phy_itface;           /*!< Select the used PHY interface.
+                                      This parameter can be any value of @ref USB_Core_PHY_                  */ 
+                                
+  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */     
+                               
+  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */     
+                          
+  uint32_t lpm_enable;           /*!< Enable or disable Battery charging.                                    */    
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                 */   
+  
+  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ 
+
+  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */      
+  
+  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */   
+  
+}USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;            /*!< Endpoint number
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
+                                
+  uint8_t   is_in;          /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   is_stall;       /*!< Endpoint stall condition
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   type;           /*!< Endpoint type
+                                 This parameter can be any value of @ref USB_EP_Type_                     */ 
+                                
+  uint8_t   data_pid_start; /*!< Initial data PID
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+                                
+  uint8_t   even_odd_frame; /*!< IFrame parity
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+                                
+  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+                                
+  uint32_t  maxpacket;      /*!< Endpoint Max packet size
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
+                                
+  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
+  
+  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
+  
+  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
+
+}USB_OTG_EPTypeDef;
+
+typedef struct
+{
+  uint8_t   dev_addr ;     /*!< USB device address.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */ 
+
+  uint8_t   ch_num;        /*!< Host channel number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_num;        /*!< Endpoint number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_is_in;      /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */ 
+                                
+  uint8_t   speed;         /*!< USB Host speed.
+                                This parameter can be any value of @ref USB_Core_Speed_                    */
+                                
+  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
+  
+  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;       /*!< Endpoint Type.
+                                This parameter can be any value of @ref USB_EP_Type_                       */
+                                
+  uint16_t  max_packet;    /*!< Endpoint Max packet size.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+                                
+  uint8_t   data_pid;      /*!< Initial data PID.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
+  
+  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
+  
+  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
+  
+  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+  
+  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
+  
+  uint32_t  ErrCnt;        /*!< Host channel error count.*/
+  
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. 
+                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ 
+  
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. 
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */ 
+                                             
+}USB_OTG_HCTypeDef;
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+/** 
+  * @brief  USB Initialization Structure definition  
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;        /*!< Device Endpoints number.
+                                      This parameter depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+  
+  uint32_t speed;                /*!< USB Core speed.
+                                      This parameter can be any value of @ref USB_Core_Speed                 */
+  
+  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */              
+  
+  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
+                                      This parameter can be any value of @ref USB_EP0_MPS                    */
+  
+  uint32_t phy_itface;           /*!< Select the used PHY interface.
+                                      This parameter can be any value of @ref USB_Core_PHY                   */
+  
+  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */
+  
+  uint32_t low_power_enable;       /*!< Enable or disable Low Power mode                                      */
+  
+  uint32_t lpm_enable;             /*!< Enable or disable Battery charging.                                  */
+  
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                  */
+} USB_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;            /*!< Endpoint number
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
+  
+  uint8_t   is_in;          /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+  
+  uint8_t   is_stall;       /*!< Endpoint stall condition
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+  
+  uint8_t   type;           /*!< Endpoint type
+                                 This parameter can be any value of @ref USB_EP_Type                      */
+  
+  uint16_t  pmaadress;      /*!< PMA Address
+                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
+  
+  uint16_t  pmaaddr0;       /*!< PMA Address0
+                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
+  
+  uint16_t  pmaaddr1;        /*!< PMA Address1
+                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
+  
+  uint8_t   doublebuffer;    /*!< Double buffer enable
+                                 This parameter can be 0 or 1                                             */
+  
+  uint16_t  tx_fifo_num;    /*!< This parameter is not required by USB Device FS peripheral, it is used 
+                                 only by USB OTG FS peripheral    
+                                 This parameter is added to ensure compatibility across USB peripherals   */
+  
+  uint32_t  maxpacket;      /*!< Endpoint Max packet size
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+  
+  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
+  
+  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
+  
+  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
+
+} USB_EPTypeDef;
+#endif /* USB */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+#if defined (USB_OTG_FS)
+/** @defgroup USB_Core_Mode_ USB Core Mode
+  * @{
+  */
+#define USB_OTG_MODE_DEVICE                    0
+#define USB_OTG_MODE_HOST                      1
+#define USB_OTG_MODE_DRD                       2
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Speed_   USB Core Speed
+  * @{
+  */  
+#define USB_OTG_SPEED_HIGH                     0
+#define USB_OTG_SPEED_HIGH_IN_FULL             1
+#define USB_OTG_SPEED_LOW                      2  
+#define USB_OTG_SPEED_FULL                     3
+/**
+  * @}
+  */
+  
+/** @defgroup USB_Core_PHY_   USB Core PHY
+  * @{
+  */   
+#define USB_OTG_EMBEDDED_PHY                   1
+/**
+  * @}
+  */
+  
+/** @defgroup USB_Core_MPS_   USB Core MPS
+  * @{
+  */
+#define USB_OTG_FS_MAX_PACKET_SIZE           64
+#define USB_OTG_MAX_EP0_SIZE                 64
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency
+  * @{
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
+/**
+  * @}
+  */
+  
+/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval
+  * @{
+  */  
+#define DCFG_FRAME_INTERVAL_80                 0
+#define DCFG_FRAME_INTERVAL_85                 1
+#define DCFG_FRAME_INTERVAL_90                 2
+#define DCFG_FRAME_INTERVAL_95                 3
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP0_MPS_  USB EP0 MPS
+  * @{
+  */
+#define DEP0CTL_MPS_64                         0
+#define DEP0CTL_MPS_32                         1
+#define DEP0CTL_MPS_16                         2
+#define DEP0CTL_MPS_8                          3
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP_Speed_  USB EP Speed
+  * @{
+  */
+#define EP_SPEED_LOW                           0
+#define EP_SPEED_FULL                          1
+#define EP_SPEED_HIGH                          2
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP_Type_  USB EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0
+#define EP_TYPE_ISOC                           1
+#define EP_TYPE_BULK                           2
+#define EP_TYPE_INTR                           3
+#define EP_TYPE_MSK                            3
+/**
+  * @}
+  */
+
+/** @defgroup USB_STS_Defines_   USB STS Defines
+  * @{
+  */
+#define STS_GOUT_NAK                           1
+#define STS_DATA_UPDT                          2
+#define STS_XFER_COMP                          3
+#define STS_SETUP_COMP                         4
+#define STS_SETUP_UPDT                         6
+/**
+  * @}
+  */
+
+/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines
+  * @{
+  */  
+#define HCFG_30_60_MHZ                         0
+#define HCFG_48_MHZ                            1
+#define HCFG_6_MHZ                             2
+/**
+  * @}
+  */
+    
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines
+  * @{
+  */    
+#define HPRT0_PRTSPD_HIGH_SPEED                0
+#define HPRT0_PRTSPD_FULL_SPEED                1
+#define HPRT0_PRTSPD_LOW_SPEED                 2
+/**
+  * @}
+  */  
+   
+#define HCCHAR_CTRL                            0
+#define HCCHAR_ISOC                            1
+#define HCCHAR_BULK                            2
+#define HCCHAR_INTR                            3
+       
+#define HC_PID_DATA0                           0
+#define HC_PID_DATA2                           1
+#define HC_PID_DATA1                           2
+#define HC_PID_SETUP                           3
+
+#define GRXSTS_PKTSTS_IN                       2
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
+#define GRXSTS_PKTSTS_CH_HALTED                7
+    
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))  
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+
+#endif /* USB_OTG_FS */
+
+#if defined (USB)  
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+  * @{
+  */
+#define DEP0CTL_MPS_64                         0
+#define DEP0CTL_MPS_32                         1
+#define DEP0CTL_MPS_16                         2
+#define DEP0CTL_MPS_8                          3
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0
+#define EP_TYPE_ISOC                           1
+#define EP_TYPE_BULK                           2
+#define EP_TYPE_INTR                           3
+#define EP_TYPE_MSK                            3
+/**
+  * @}
+  */ 
+
+#define BTABLE_ADDRESS                         (0x000)
+#endif /* USB */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+#if defined (USB_OTG_FS)
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+    
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))  
+#endif /* USB_OTG_FS */
+
+/* Exported functions --------------------------------------------------------*/
+#if defined (USB_OTG_FS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep ,uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
+void *            USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint32_t          USB_ReadInterrupts (USB_TypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
+void              USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
+void USB_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void USB_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+#endif /* USB */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c
new file mode 100755
index 0000000..57c477b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c
@@ -0,0 +1,730 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_utils.c
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   UTILS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_utils.h"
+#include "stm32l4xx_ll_rcc.h"
+#include "stm32l4xx_ll_system.h"
+#include "stm32l4xx_ll_pwr.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILS_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+  * @{
+  */
+#define UTILS_MAX_FREQUENCY_SCALE1  80000000U        /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  26000000U        /*!< Maximum frequency for system clock at power scale2, in Hz */
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN        4000000U       /*!< Frequency min for PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MAX       16000000U       /*!< Frequency max for PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_OUTPUT_MIN      64000000U       /*!< Frequency min for PLLVCO output, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_MAX     344000000U       /*!< Frequency max for PLLVCO output, in Hz  */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#define UTILS_SCALE1_LATENCY1_FREQ   16000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE1_LATENCY2_FREQ   32000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define UTILS_SCALE1_LATENCY3_FREQ   48000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define UTILS_SCALE1_LATENCY4_FREQ   64000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define UTILS_SCALE2_LATENCY1_FREQ    6000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE2_LATENCY2_FREQ   12000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define UTILS_SCALE2_LATENCY3_FREQ   18000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
+
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
+
+#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+  * @{
+  */
+static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  HCLKFrequency HCLK frequency in Hz
+  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+  /* Use frequency provided in argument */
+  LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on SysTick counter flag
+  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+  *         and use rather osDelay service.
+  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+  *         will configure Systick to 1ms
+  * @param  Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void LL_mDelay(uint32_t Delay)
+{
+  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+  /* Add this code to indicate that local variable is not used */
+  ((void)tmp);
+
+  /* Add a period to guaranty minimum wait */
+  if(Delay < LL_MAX_DELAY)
+  {
+    Delay++;
+  }
+
+  while (Delay)
+  {
+    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+    {
+      Delay--;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_EF_SYSTEM
+  *  @brief    System Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### System Configuration functions #####
+ ===============================================================================
+    [..]
+         System, AHB and APB buses clocks configuration
+
+         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80000000 Hz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+
+             (++)  Table 1. HCLK clock frequency.
+             (++)  +-------------------------------------------------------+
+             (++)  | Latency         |    HCLK clock frequency (MHz)       |
+             (++)  |                 |-------------------------------------|
+             (++)  |                 | voltage range 1  | voltage range 2  |
+             (++)  |                 |      1.2 V       |     1.0 V        |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |
+             (++)  +-------------------------------------------------------+
+  @endinternal
+  * @{
+  */
+
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @retval None
+  */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+  /* HCLK clock frequency */
+  SystemCoreClock = HCLKFrequency;
+}
+
+/**
+  * @brief  This function configures system clock with MSI as clock source of the PLL
+  * @note   The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
+  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLR: ensure that max frequency at 80000000 Hz is reached (PLLVCO_output / PLLR)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t pllfreq = 0U, msi_range = 0U;
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Get the current MSI range */
+    if(LL_RCC_MSI_IsEnabledRangeSelect())
+    {
+      msi_range =  LL_RCC_MSI_GetRange();
+      switch (msi_range)
+      {
+        case LL_RCC_MSIRANGE_0:     /* MSI = 100 KHz  */
+        case LL_RCC_MSIRANGE_1:     /* MSI = 200 KHz  */
+        case LL_RCC_MSIRANGE_2:     /* MSI = 400 KHz  */
+        case LL_RCC_MSIRANGE_3:     /* MSI = 800 KHz  */
+        case LL_RCC_MSIRANGE_4:     /* MSI = 1 MHz    */
+        case LL_RCC_MSIRANGE_5:     /* MSI = 2 MHz    */
+          /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/
+          status = ERROR;
+          break;
+
+        case LL_RCC_MSIRANGE_6:     /* MSI = 4 MHz    */
+        case LL_RCC_MSIRANGE_7:     /* MSI = 8 MHz    */
+        case LL_RCC_MSIRANGE_8:     /* MSI = 16 MHz   */
+        case LL_RCC_MSIRANGE_9:     /* MSI = 24 MHz   */
+        case LL_RCC_MSIRANGE_10:    /* MSI = 32 MHz   */
+        case LL_RCC_MSIRANGE_11:    /* MSI = 48 MHz   */
+        default:
+          break;
+      }
+    }
+    else
+    {
+      msi_range = LL_RCC_MSI_GetRangeAfterStandby();
+      switch (msi_range)
+      {
+        case LL_RCC_MSISRANGE_4:    /* MSI = 1 MHz    */
+        case LL_RCC_MSISRANGE_5:    /* MSI = 2 MHz    */
+          /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
+          status = ERROR;
+          break;
+
+        case LL_RCC_MSISRANGE_7:    /* MSI = 8 MHz    */
+        case LL_RCC_MSISRANGE_6:    /* MSI = 4 MHz    */
+        default:
+          break;
+      }
+    }
+
+    /* Main PLL configuration and activation */
+    if(status != ERROR)
+    {
+      /* Calculate the new PLL output frequency */
+      pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
+                                            UTILS_PLLInitStruct);
+
+      /* Enable MSI if not enabled */
+      if(LL_RCC_MSI_IsReady() != 1U)
+      {
+        LL_RCC_MSI_Enable();
+        while ((LL_RCC_MSI_IsReady() != 1U))
+        {
+          /* Wait for MSI ready */
+        }
+      }
+
+      /* Configure PLL */
+      LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+                                  UTILS_PLLInitStruct->PLLR);
+
+      /* Enable PLL and switch system clock to PLL */
+      status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+    }
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
+  * @note   The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
+  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLR: ensure that max frequency at 80000000 Hz is reach (PLLVCO_output / PLLR)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t pllfreq = 0U;
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+    /* Enable HSI if not enabled */
+    if(LL_RCC_HSI_IsReady() != 1U)
+    {
+      LL_RCC_HSI_Enable();
+      while (LL_RCC_HSI_IsReady() != 1U)
+      {
+        /* Wait for HSI ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+                                UTILS_PLLInitStruct->PLLR);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock with HSE as clock source of the PLL
+  * @note   The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
+  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLR: ensure that max frequency at 80000000 Hz is reached (PLLVCO_output / PLLR)
+  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
+  * @param  HSEBypass This parameter can be one of the following values:
+  *         @arg @ref LL_UTILS_HSEBYPASS_ON
+  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t pllfreq = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+    /* Enable HSE if not enabled */
+    if(LL_RCC_HSE_IsReady() != 1U)
+    {
+      /* Check if need to enable HSE bypass feature or not */
+      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+      {
+        LL_RCC_HSE_EnableBypass();
+      }
+      else
+      {
+        LL_RCC_HSE_DisableBypass();
+      }
+
+      /* Enable HSE */
+      LL_RCC_HSE_Enable();
+      while (LL_RCC_HSE_IsReady() != 1U)
+      {
+        /* Wait for HSE ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+                                UTILS_PLLInitStruct->PLLR);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_LL_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Update number of Flash wait states in line with new frequency and current
+            voltage range.
+  * @param  HCLK_Frequency  HCLK frequency
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Latency has been modified
+  *          - ERROR: Latency cannot be modified
+  */
+static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
+{
+  ErrorStatus status = SUCCESS;
+
+  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
+
+  /* Frequency cannot be equal to 0 */
+  if(HCLK_Frequency == 0U)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+    {
+      if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
+      {
+        /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
+      {
+        /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
+      {
+        /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else
+      {
+        if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
+        {
+          /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
+          latency = LL_FLASH_LATENCY_1;
+        }
+        /* else HCLK_Frequency < 16MHz default LL_FLASH_LATENCY_0 0WS */
+      }
+    }
+    else /* SCALE2 */
+    {
+      if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
+      {
+        /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
+      {
+        /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else
+      {
+        if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
+        {
+          /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
+          latency = LL_FLASH_LATENCY_1;
+        }
+        /* else HCLK_Frequency < 6MHz default LL_FLASH_LATENCY_0 0WS */
+      }
+    }
+
+    LL_FLASH_SetLatency(latency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+       memory by reading the FLASH_ACR register */
+    if(LL_FLASH_GetLatency() != latency)
+    {
+      status = ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @retval PLL output frequency (in Hz)
+  */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+  uint32_t pllfreq = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
+
+  /* Check different PLL parameters according to RM                          */
+  /*  - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz.   */
+  pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1));
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
+
+  /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
+  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+
+  /*  - PLLR: ensure that max frequency at 80000000 Hz is reached                   */
+  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1) * 2);
+  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+  return pllfreq;
+}
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: PLL modification can be done
+  *          - ERROR: PLL is busy
+  */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check if PLL is busy*/
+  if(LL_RCC_PLL_IsReady() != 0U)
+  {
+    /* PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  /* Check if PLLSAI1 is busy*/
+  if(LL_RCC_PLLSAI1_IsReady() != 0U)
+  {
+    /* PLLSAI1 configuration cannot be modified */
+    status = ERROR;
+  }
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+  /* Check if PLLSAI2 is busy*/
+  if(LL_RCC_PLLSAI2_IsReady() != 0U)
+  {
+    /* PLLSAI2 configuration cannot be modified */
+    status = ERROR;
+  }
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+  return status;
+}
+
+/**
+  * @brief  Function to enable PLL and switch system clock to PLL
+  * @param  SYSCLK_Frequency SYSCLK frequency
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: No problem to switch system to PLL
+  *          - ERROR: Problem to switch system to PLL
+  */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t hclk_frequency = 0U;
+
+  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+  /* Calculate HCLK frequency */
+  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(SystemCoreClock < hclk_frequency)
+  {
+    /* Set FLASH latency to highest latency */
+    status = UTILS_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update system clock configuration */
+  if(status == SUCCESS)
+  {
+    /* Enable PLL */
+    LL_RCC_PLL_Enable();
+    LL_RCC_PLL_EnableDomain_SYS();
+    while (LL_RCC_PLL_IsReady() != 1U)
+    {
+      /* Wait for PLL ready */
+    }
+
+    /* Sysclk activation on the main PLL */
+    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+    {
+      /* Wait for system clock switch to PLL */
+    }
+
+    /* Set APB1 & APB2 prescaler*/
+    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+  }
+    
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(SystemCoreClock > hclk_frequency)
+  {
+    /* Set FLASH latency to lowest latency */
+    status = UTILS_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update SystemCoreClock variable */
+  if(status == SUCCESS)
+  {
+    LL_SetSystemCoreClock(hclk_frequency);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h
new file mode 100755
index 0000000..cc76439
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h
@@ -0,0 +1,337 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_utils.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of UTILS LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_UTILS_H
+#define __STM32L4xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 8 and Max_Data = 86
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLR;   /*!< Division for the main system clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#define LL_UTILS_PACKAGETYPE_LQFP64         0x00000000U /*!< LQFP64 package type                      */
+#define LL_UTILS_PACKAGETYPE_WLCSP64        0x00000001U /*!< WLCSP64 package type                     */
+#define LL_UTILS_PACKAGETYPE_LQFP100        0x00000002U /*!< LQFP100 package type                     */
+#define LL_UTILS_PACKAGETYPE_BGA132         0x00000003U /*!< BGA132 package type                      */
+#define LL_UTILS_PACKAGETYPE_LQFP144_CSP72  0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */
+#define LL_UTILS_PACKAGETYPE_UFQFPN32       0x00000008U /*!< UFQFPN32 package type                    */
+#define LL_UTILS_PACKAGETYPE_UFQFPN48       0x0000000AU /*!< UFQFPN48 package type                    */
+#define LL_UTILS_PACKAGETYPE_LQFP48         0x0000000BU /*!< LQFP48 package type                      */
+#define LL_UTILS_PACKAGETYPE_WLCSP49        0x0000000CU /*!< WLCSP49 package type                     */
+#define LL_UTILS_PACKAGETYPE_UFBGA64        0x0000000DU /*!< UFBGA64 package type                     */
+#define LL_UTILS_PACKAGETYPE_UFBGA100       0x0000000EU /*!< UFBGA100 package type                    */
+#define LL_UTILS_PACKAGETYPE_UFBGA169       0x00000010U /*!< UFBGA169 package type                    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+  return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick 
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t HCLKFrequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h
new file mode 100755
index 0000000..19528d2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h
@@ -0,0 +1,342 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of WWDG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_WWDG_H
+#define __STM32L4xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+  * @{
+  */
+
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
+  * @{
+  */
+#define LL_WWDG_CFR_EWI                    WWDG_CFR_EWI
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
+* @{
+*/
+#define LL_WWDG_PRESCALER_1                0x00000000U                                             /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+  * @{
+  */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in WWDG register
+  * @param  __INSTANCE__ WWDG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in WWDG register
+  * @param  __INSTANCE__ WWDG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
+  * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
+  *         then it cannot be disabled again except by a reset.
+  *         This bit is set by software and only cleared by hardware after a reset.
+  *         When WDGA = 1, the watchdog can generate a reset.
+  * @rmtoll CR           WDGA          LL_WWDG_Enable
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+  SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+  * @brief  Checks if Window Watchdog is enabled
+  * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+}
+
+/**
+  * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
+  * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+  *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+  *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+  *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+  * @rmtoll CR           T             LL_WWDG_SetCounter
+  * @param  WWDGx WWDG Instance
+  * @param  Counter 0..0x7F (7 bit counter value)
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+  MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+  * @brief  Return current Watchdog Counter Value (7 bits counter value)
+  * @rmtoll CR           T             LL_WWDG_GetCounter
+  * @param  WWDGx WWDG Instance
+  * @retval 7 bit Watchdog Counter value
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+{
+  return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+  * @brief  Set the time base of the prescaler (WDGTB).
+  * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+  *         is decremented every (4096 x 2expWDGTB) PCLK cycles
+  * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
+  * @param  WWDGx WWDG Instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_WWDG_PRESCALER_1
+  *         @arg @ref LL_WWDG_PRESCALER_2
+  *         @arg @ref LL_WWDG_PRESCALER_4
+  *         @arg @ref LL_WWDG_PRESCALER_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+  * @brief  Return current Watchdog Prescaler Value
+  * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
+  * @param  WWDGx WWDG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_WWDG_PRESCALER_1
+  *         @arg @ref LL_WWDG_PRESCALER_2
+  *         @arg @ref LL_WWDG_PRESCALER_4
+  *         @arg @ref LL_WWDG_PRESCALER_8
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+{
+  return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+  * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+  * @note   This window value defines when write in the WWDG_CR register
+  *         to program Watchdog counter is allowed.
+  *         Watchdog counter value update must occur only when the counter value
+  *         is lower than the Watchdog window register value.
+  *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+  *         (in the control register) is refreshed before the downcounter has reached
+  *         the watchdog window register value.
+  *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
+  *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+  * @rmtoll CFR          W             LL_WWDG_SetWindow
+  * @param  WWDGx WWDG Instance
+  * @param  Window 0x00..0x7F (7 bit Window value)
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+  * @brief  Return current Watchdog Window Value (7 bits value)
+  * @rmtoll CFR          W             LL_WWDG_GetWindow
+  * @param  WWDGx WWDG Instance
+  * @retval 7 bit Watchdog Window value
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+{
+  return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+/**
+  * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+  * @note   This bit is set by hardware when the counter has reached the value 0x40.
+  *         It must be cleared by software by writing 0.
+  *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+  * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+}
+
+/**
+  * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+  * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+  * @{
+  */
+/**
+  * @brief  Enable the Early Wakeup Interrupt.
+  * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
+  *         This interrupt is only cleared by hardware after a reset
+  * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+  * @brief  Check if Early Wakeup Interrupt is enabled
+  * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* WWDG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c
new file mode 100755
index 0000000..4e9cc82
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c
@@ -0,0 +1,362 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.c
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l4xx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 4000000;
+
+  const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
+  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
+                                      4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON , HSION, and PLLON bits */
+  RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00001000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
+  { /* MSISRANGE from RCC_CSR applies */
+    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
+  }
+  else
+  { /* MSIRANGE from RCC_CR applies */
+    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
+  }
+  /*MSI frequency range in HZ*/
+  msirange = MSIRangeTable[msirange];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:  /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C:  /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
+
+      switch (pllsource)
+      {
+        case 0x02:  /* HSI used as PLL clock source */
+          pllvco = (HSI_VALUE / pllm);
+          break;
+
+        case 0x03:  /* HSE used as PLL clock source */
+          pllvco = (HSE_VALUE / pllm);
+          break;
+
+        default:    /* MSI used as PLL clock source */
+          pllvco = (msirange / pllm);
+          break;
+      }
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.c
new file mode 100755
index 0000000..4904e93
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/flash_api.c
@@ -0,0 +1,279 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+#include "mbed_assert.h"
+#include "cmsis.h"
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t Addr)
+{
+    uint32_t page = 0;
+
+    if (Addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
+        /* Bank 1 */
+        page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;
+    } else {
+        /* Bank 2 */
+        page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE;
+    }
+
+    return page;
+}
+
+/**
+  * @brief  Gets the bank of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The bank of a given address
+  */
+static uint32_t GetBank(uint32_t Addr)
+{
+    uint32_t bank = 0;
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) {
+        /* No Bank swap */
+        if (Addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
+            bank = FLASH_BANK_1;
+        } else {
+            bank = FLASH_BANK_2;
+        }
+    } else {
+        /* Bank swap */
+        if (Addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
+            bank = FLASH_BANK_2;
+        } else {
+            bank = FLASH_BANK_1;
+        }
+    }
+#else
+    /* Device like L432KC */
+    bank = FLASH_BANK_1;
+#endif
+
+    return bank;
+}
+
+/** Initialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_init(flash_t *obj)
+{
+    return 0;
+}
+
+/** Uninitialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+/** Erase one sector starting at defined address
+ *
+ * The address should be at sector boundary. This function does not do any check for address alignments
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    uint32_t FirstPage = 0, BankNumber = 0;
+    uint32_t PAGEError = 0;
+    FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
+
+    if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+      /* Clear OPTVERR bit set on virgin samples */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+    /* Get the 1st page to erase */
+    FirstPage = GetPage(address);
+    /* MBED HAL erases 1 page  / sector at a time */
+    /* Get the bank */
+    BankNumber = GetBank(address);
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.Banks       = BankNumber;
+    EraseInitStruct.Page        = FirstPage;
+    EraseInitStruct.NbPages     = 1;
+
+    /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+     you have to make sure that these data are rewritten before they are accessed during code
+     execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+     DCRST and ICRST bits in the FLASH_CR register. */
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
+        status = -1;
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+/** Program one page starting at defined address
+ *
+ * The page should be at page boundary, should not cross multiple sectors.
+ * This function does not do any check for address alignments or if size
+ * is aligned to a page size.
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @param data The data buffer to be programmed
+ * @param size The number of bytes to program
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_program_page(flash_t *obj, uint32_t address,
+        const uint8_t *data, uint32_t size)
+{
+    uint32_t StartAddress = 0;
+    int32_t status = 0;
+
+    if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+        return -1;
+    }
+
+    if ((size % 8) != 0) {
+        /* L4 flash devices can only be programmed 64bits/8 bytes at a time */
+        return -1;
+    }
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
+    /* Program the user Flash area word by word */
+    StartAddress = address;
+
+    /*  HW needs an aligned address to program flash, which data
+     *  parameters doesn't ensure  */
+    if ((uint32_t) data % 4 != 0) {
+        volatile uint64_t data64;
+        while ((address < (StartAddress + size)) && (status == 0)) {
+            for (uint8_t i =0; i < 8; i++) {
+                *(((uint8_t *) &data64) + i) = *(data + i);
+            }
+
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data64)
+                    == HAL_OK) {
+                address = address + 8;
+                data = data + 8;
+            } else {
+                status = -1;
+            }
+        }
+    } else { /*  case where data is aligned, so let's avoid any copy */
+        while ((address < (StartAddress + size)) && (status == 0)) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address,
+                        *((uint64_t*) data))
+                    == HAL_OK) {
+                address = address + 8;
+                data = data + 8;
+            } else {
+                status = -1;
+            }
+        }
+    }
+
+    flash_lock();
+
+    return status;
+}
+
+/** Get sector size
+ *
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return The size of a sector
+ */
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) {
+    /*  considering 1 sector = 1 page */
+    if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+        return MBED_FLASH_INVALID_SIZE;
+    } else {
+        return FLASH_PAGE_SIZE;
+    }
+}
+
+/** Get page size
+ *
+ * @param obj The flash object
+ * @param address The page starting address
+ * @return The size of a page
+ */
+uint32_t flash_get_page_size(const flash_t *obj) {
+    /*  Page size is the minimum programable size, which 8 bytes */
+    return 8;
+}
+
+/** Get start address for the flash region
+ *
+ * @param obj The flash object
+ * @return The start address for the flash region
+ */
+uint32_t flash_get_start_address(const flash_t *obj) {
+    return FLASH_BASE;
+}
+
+/** Get the flash region size
+ *
+ * @param obj The flash object
+ * @return The flash region size
+ */
+uint32_t flash_get_size(const flash_t *obj) {
+    return FLASH_SIZE;
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.c
new file mode 100755
index 0000000..9f63aff
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.c
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis.h"
+#include "gpio_irq_device.h"
+
+// Used to return the index for channels array.
+const exti_lines_t pin_lines_desc[16] = {
+    // EXTI0
+    {.gpio_idx = 0, .irq_index = 0, .irq_n = EXTI0_IRQn}, // pin 0
+    // EXTI1
+    {.gpio_idx = 0, .irq_index = 1, .irq_n = EXTI1_IRQn}, // pin 1
+    // EXTI2
+    {.gpio_idx = 0, .irq_index = 2, .irq_n = EXTI2_IRQn}, // pin 2
+    // EXTI3
+    {.gpio_idx = 0, .irq_index = 3, .irq_n = EXTI3_IRQn}, // pin 3
+    // EXTI4
+    {.gpio_idx = 0, .irq_index = 4, .irq_n = EXTI4_IRQn}, // pin 4
+    // EXTI5_9
+    {.gpio_idx = 0, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 5
+    {.gpio_idx = 1, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 6
+    {.gpio_idx = 2, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 7
+    {.gpio_idx = 3, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 8
+    {.gpio_idx = 4, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 9
+    // EXTI10_15
+    {.gpio_idx = 0, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 10
+    {.gpio_idx = 1, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 11
+    {.gpio_idx = 2, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 12
+    {.gpio_idx = 3, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 13
+    {.gpio_idx = 4, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 14
+    {.gpio_idx = 5, .irq_index = 6, .irq_n = EXTI15_10_IRQn}// pin 15
+};
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.h
new file mode 100755
index 0000000..3390774
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/gpio_irq_device.h
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_IRQ_DEVICE_H
+#define MBED_GPIO_IRQ_DEVICE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stm32l4xx_ll_exti.h"
+
+// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
+#define CHANNEL_NUM (7)
+
+#define EXTI_IRQ0_NUM_LINES 1
+#define EXTI_IRQ1_NUM_LINES 1
+#define EXTI_IRQ2_NUM_LINES 1
+#define EXTI_IRQ3_NUM_LINES 1
+#define EXTI_IRQ4_NUM_LINES 1
+#define EXTI_IRQ5_NUM_LINES 5
+#define EXTI_IRQ6_NUM_LINES 6
+
+// Max pins for one line (max with EXTI10_15)
+#define MAX_PIN_LINE (EXTI_IRQ6_NUM_LINES)
+
+/*  Structure to describe how the HW EXTI lines are defined in this HW */
+typedef struct exti_lines {
+    uint32_t gpio_idx;   // an index entry for each EXIT line
+    uint32_t irq_index;  // the IRQ index
+    IRQn_Type  irq_n;    // the corresponding EXTI IRQn
+} exti_lines_t;
+
+// Used to return the index for channels array.
+extern const exti_lines_t pin_lines_desc[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h
new file mode 100755
index 0000000..8bb6f9c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h
@@ -0,0 +1,95 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_I2C_DEVICE_H
+#define MBED_I2C_DEVICE_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_I2C
+
+#define I2C_IP_VERSION_V2
+
+#define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI)
+
+/*  Family specifc settings for clock source */
+#define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK
+#define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_SYSCLK
+#define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK
+#define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_SYSCLK
+
+/*  Provide the suitable timing depending on requested frequencie */
+static inline uint32_t get_i2c_timing(int hz)
+{
+    uint32_t tim = 0;
+    if (SystemCoreClock == 80000000) {
+        // Common settings: I2C clock = 80 MHz, Analog filter = ON, Digital filter coefficient = 0
+        switch (hz) {
+            case 100000:
+                tim = 0x30C14E6B; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
+                break;
+            case 400000:
+                tim = 0x10D1143A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
+                break;
+            case 1000000:
+                tim = 0x00810E27; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
+                break;
+            default:
+                break;
+        }
+    } else if (SystemCoreClock == 48000000) {
+        // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
+        switch (hz) {
+            case 100000:
+                tim = 0x20A03E55; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
+                break;
+            case 400000:
+                tim = 0x10800C21; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
+                break;
+            case 1000000:
+                tim = 0x00500816; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
+                break;
+            default:
+                break;
+        }
+    }
+    return tim;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // DEVICE_I2C
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pin_device.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pin_device.h
new file mode 100755
index 0000000..b45c56d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pin_device.h
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PIN_DEVICE_H
+#define MBED_PIN_DEVICE_H
+
+#include "cmsis.h"
+#include "stm32l4xx_ll_gpio.h"
+
+extern const uint32_t ll_pin_defines[16];
+
+/* Family specific implementations */
+static inline void stm_pin_DisconnectDebug(PinName pin)
+{
+    /* empty for now */
+}
+
+static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
+{
+    switch (pull_config) {
+        case GPIO_PULLUP:
+            LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
+            break;
+        case GPIO_PULLDOWN:
+            LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
+            break;
+        default:
+            LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_NO);
+            break;
+    }
+}
+
+static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
+{
+    uint32_t ll_pin  = ll_pin_defines[STM_PIN(pin)];
+
+    if (STM_PIN(pin) > 7)
+        LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
+    else
+        LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c
new file mode 100755
index 0000000..708d305
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis.h"
+#include "pwmout_api.h"
+#include "pwmout_device.h"
+
+#ifdef DEVICE_PWMOUT
+
+const pwm_apb_map_t pwm_apb_map_table[] =
+{
+#if defined(TIM2_BASE)
+    {PWM_2, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM3_BASE)
+    {PWM_3, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM4_BASE)
+    {PWM_4, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM5_BASE)
+    {PWM_5, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM1_BASE)
+    {PWM_1, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM8_BASE)
+    {PWM_8, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM15_BASE)
+    {PWM_15, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM16_BASE)
+    {PWM_16, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM17_BASE)
+    {PWM_17, PWMOUT_ON_APB2},
+#endif
+    {(PWMName) 0, PWMOUT_UNKNOWN}
+};
+
+#endif // DEVICE_PWMOUT
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.h
new file mode 100755
index 0000000..0d81dd5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PWMOUT_DEVICE_H
+#define MBED_PWMOUT_DEVICE_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_PWMOUT
+
+typedef enum {
+    PWMOUT_ON_APB1 = 0,
+    PWMOUT_ON_APB2 = 1,
+    PWMOUT_UNKNOWN = 2
+} PwmoutApb;
+
+/*  Structure to describe Timers to APB */
+typedef struct pwm_apb_map {
+    PWMName pwm;   // an index entry for each EXIT line
+    PwmoutApb pwmoutApb;
+} pwm_apb_map_t;
+
+extern const pwm_apb_map_t pwm_apb_map_table[];
+
+#endif // DEVICE_PWMOUT
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.c
new file mode 100755
index 0000000..9e33644
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/serial_device.c
@@ -0,0 +1,868 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "serial_api.h"
+#include "serial_api_hal.h"
+
+#if DEVICE_SERIAL
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include <string.h>
+#include "PeripheralPins.h"
+
+#define UART_NUM (6)
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+UART_HandleTypeDef uart_handlers[UART_NUM];
+
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    
+    // Determine the UART to use (UART_1, UART_2, ...)
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+    obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT(obj_s->uart != (UARTName)NC);
+
+    // Enable USART clock
+    if (obj_s->uart == UART_1) {
+        __HAL_RCC_USART1_FORCE_RESET();
+        __HAL_RCC_USART1_RELEASE_RESET();
+        __HAL_RCC_USART1_CLK_ENABLE();
+        obj_s->index = 0;
+    }
+    if (obj_s->uart == UART_2) {
+        __HAL_RCC_USART2_FORCE_RESET();
+        __HAL_RCC_USART2_RELEASE_RESET();
+        __HAL_RCC_USART2_CLK_ENABLE();
+        obj_s->index = 1;
+    }
+
+#if defined(USART3_BASE)
+    if (obj_s->uart == UART_3) {
+        __HAL_RCC_USART3_FORCE_RESET();
+        __HAL_RCC_USART3_RELEASE_RESET();
+        __HAL_RCC_USART3_CLK_ENABLE();
+        obj_s->index = 2;
+    }
+#endif
+
+#if defined(UART4_BASE)
+    if (obj_s->uart == UART_4) {
+        __HAL_RCC_UART4_FORCE_RESET();
+        __HAL_RCC_UART4_RELEASE_RESET();
+        __HAL_RCC_UART4_CLK_ENABLE();
+        obj_s->index = 3;
+    }
+#endif
+
+#if defined(UART5_BASE)
+    if (obj_s->uart == UART_5) {
+        __HAL_RCC_UART5_FORCE_RESET();
+        __HAL_RCC_UART5_RELEASE_RESET();
+        __HAL_RCC_UART5_CLK_ENABLE();
+        obj_s->index = 4;
+    }
+#endif
+
+#if defined(LPUART1_BASE)
+    if (obj_s->uart == LPUART_1) {
+        __HAL_RCC_LPUART1_FORCE_RESET();
+        __HAL_RCC_LPUART1_RELEASE_RESET();
+        __HAL_RCC_LPUART1_CLK_ENABLE();
+        obj_s->index = 5;
+    }
+#endif
+
+    // Configure UART pins
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    
+    if (tx != NC) {
+        pin_mode(tx, PullUp);
+    }
+    if (rx != NC) {
+        pin_mode(rx, PullUp);
+    }
+
+    // Configure UART
+    obj_s->baudrate = 9600;
+    obj_s->databits = UART_WORDLENGTH_8B;
+    obj_s->stopbits = UART_STOPBITS_1;
+    obj_s->parity   = UART_PARITY_NONE;
+    
+#if DEVICE_SERIAL_FC
+    obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
+#endif
+
+    obj_s->pin_tx = tx;
+    obj_s->pin_rx = rx;
+
+    init_uart(obj);
+
+    // For stdio management
+    if (obj_s->uart == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+      
+    // Reset UART and disable clock
+    if (obj_s->uart == UART_1) {
+        __HAL_RCC_USART1_FORCE_RESET();
+        __HAL_RCC_USART1_RELEASE_RESET();
+        __HAL_RCC_USART1_CLK_DISABLE();
+    }
+
+    if (obj_s->uart == UART_2) {
+        __HAL_RCC_USART2_FORCE_RESET();
+        __HAL_RCC_USART2_RELEASE_RESET();
+        __HAL_RCC_USART2_CLK_DISABLE();
+    }
+
+#if defined(USART3_BASE)
+    if (obj_s->uart == UART_3) {
+        __HAL_RCC_USART3_FORCE_RESET();
+        __HAL_RCC_USART3_RELEASE_RESET();
+        __HAL_RCC_USART3_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART4_BASE)
+    if (obj_s->uart == UART_4) {
+        __HAL_RCC_UART4_FORCE_RESET();
+        __HAL_RCC_UART4_RELEASE_RESET();
+        __HAL_RCC_UART4_CLK_DISABLE();
+    }
+#endif
+
+#if defined(UART5_BASE)
+    if (obj_s->uart == UART_5) {
+        __HAL_RCC_UART5_FORCE_RESET();
+        __HAL_RCC_UART5_RELEASE_RESET();
+        __HAL_RCC_UART5_CLK_DISABLE();
+    }
+#endif
+
+#if defined(LPUART1_BASE)
+    if (obj_s->uart == LPUART_1) {
+        __HAL_RCC_LPUART1_FORCE_RESET();
+        __HAL_RCC_LPUART1_RELEASE_RESET();
+        __HAL_RCC_LPUART1_CLK_DISABLE();
+    }
+#endif
+
+    // Configure GPIOs
+    pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+    serial_irq_ids[obj_s->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+
+    obj_s->baudrate = baudrate;
+    init_uart(obj);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_irq(int id)
+{
+    UART_HandleTypeDef * huart = &uart_handlers[id];
+    
+    if (serial_irq_ids[id] != 0) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
+                irq_handler(serial_irq_ids[id], TxIrq);
+            }
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
+                irq_handler(serial_irq_ids[id], RxIrq);
+                /*  Flag has been cleared when reading the content */
+            }
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) {
+                volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear ORE flag
+            }
+        }
+    }
+}
+
+static void uart1_irq(void)
+{
+    uart_irq(0);
+}
+
+static void uart2_irq(void)
+{
+    uart_irq(1);
+}
+
+#if defined(USART3_BASE)
+static void uart3_irq(void)
+{
+    uart_irq(2);
+}
+#endif
+
+#if defined(UART4_BASE)
+static void uart4_irq(void)
+{
+    uart_irq(3);
+}
+#endif
+
+#if defined(UART5_BASE)
+static void uart5_irq(void)
+{
+    uart_irq(4);
+}
+#endif
+
+#if defined(LPUART1_BASE)
+static void lpuart1_irq(void)
+{
+    uart_irq(5);
+}
+#endif
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+  
+    irq_handler = handler;
+    serial_irq_ids[obj_s->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+
+    if (obj_s->uart == UART_1) {
+        irq_n = USART1_IRQn;
+        vector = (uint32_t)&uart1_irq;
+    }
+
+    if (obj_s->uart == UART_2) {
+        irq_n = USART2_IRQn;
+        vector = (uint32_t)&uart2_irq;
+    }
+#if defined(USART3_BASE)
+    if (obj_s->uart == UART_3) {
+        irq_n = USART3_IRQn;
+        vector = (uint32_t)&uart3_irq;
+    }
+#endif
+#if defined(UART4_BASE)
+    if (obj_s->uart == UART_4) {
+        irq_n = UART4_IRQn;
+        vector = (uint32_t)&uart4_irq;
+    }
+#endif
+
+#if defined(UART5_BASE)
+    if (obj_s->uart == UART_5) {
+        irq_n = UART5_IRQn;
+        vector = (uint32_t)&uart5_irq;
+    }
+#endif
+
+#if defined(LPUART1_BASE)
+    if (obj_s->uart == LPUART_1) {
+        irq_n = LPUART1_IRQn;
+        vector = (uint32_t)&lpuart1_irq;
+    }
+#endif
+
+    if (enable) {
+        if (irq == RxIrq) {
+            __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+        } else { // TxIrq
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+        }
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+
+    } else { // disable
+        int all_disabled = 0;
+        if (irq == RxIrq) {
+            __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+            // Check if TxIrq is disabled too
+            if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) {
+                all_disabled = 1;
+            }
+        } else { // TxIrq
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+            // Check if RxIrq is disabled too
+            if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
+                all_disabled = 1;
+            }
+        }
+
+        if (all_disabled) {
+            NVIC_DisableIRQ(irq_n);
+        }
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_getc(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+    while (!serial_readable(obj));
+    if (obj_s->databits == UART_WORDLENGTH_8B) {
+        return (int)(huart->Instance->RDR & (uint8_t)0xFF);
+    } else {
+        return (int)(huart->Instance->RDR & (uint16_t)0x1FF);
+    }
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+    while (!serial_writable(obj));
+    if (obj_s->databits == UART_WORDLENGTH_8B) {
+        huart->Instance->TDR = (uint8_t)(c & (uint8_t)0xFF);
+    } else {
+        huart->Instance->TDR = (uint16_t)(c & (uint16_t)0x1FF);
+    }
+}
+
+void serial_clear(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+    huart->TxXferCount = 0;
+    huart->RxXferCount = 0;
+}
+
+void serial_break_set(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+    HAL_LIN_SendBreak(huart);
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+/******************************************************************************
+ * LOCAL HELPER FUNCTIONS
+ ******************************************************************************/
+
+/** 
+ * Configure the TX buffer for an asynchronous write serial transaction
+ *
+ * @param obj       The serial object.
+ * @param tx        The buffer for sending.
+ * @param tx_length The number of words to transmit.
+ */
+static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
+{
+    (void)width;
+
+    // Exit if a transmit is already on-going
+    if (serial_tx_active(obj)) {
+        return;
+    }
+
+    obj->tx_buff.buffer = tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+}
+  
+/**
+ * Configure the RX buffer for an asynchronous write serial transaction
+ *
+ * @param obj       The serial object.
+ * @param tx        The buffer for sending.
+ * @param tx_length The number of words to transmit.
+ */
+static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
+{
+    (void)width;
+
+    // Exit if a reception is already on-going
+    if (serial_rx_active(obj)) {
+        return;
+    }
+
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+}
+
+/** 
+ * Configure events
+ *
+ * @param obj    The serial object
+ * @param event  The logical OR of the events to configure
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
+{  
+    struct serial_s *obj_s = SERIAL_S(obj);
+    
+    // Shouldn't have to enable interrupt here, just need to keep track of the requested events.
+    if (enable) {
+        obj_s->events |= event;
+    } else {
+        obj_s->events &= ~event;
+    }
+}
+
+
+/**
+* Get index of serial object TX IRQ, relating it to the physical peripheral.
+*
+* @param obj pointer to serial object
+* @return internal NVIC TX IRQ index of U(S)ART peripheral
+*/
+static IRQn_Type serial_get_irq_n(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    IRQn_Type irq_n;
+
+    switch (obj_s->index) {
+        case 0:
+            irq_n = USART1_IRQn;
+            break;
+
+        case 1:
+            irq_n = USART2_IRQn;
+            break;
+
+        case 2:
+            irq_n = USART3_IRQn;
+            break;
+#if defined(UART4_BASE)
+        case 3:
+            irq_n = UART4_IRQn;
+            break;
+#endif
+#if defined(UART5_BASE)
+        case 4:
+            irq_n = UART5_IRQn;
+            break;
+#endif
+#if defined(LPUART1_BASE)
+        case 5:
+            irq_n = LPUART1_IRQn;
+            break;
+#endif
+
+        default:
+            irq_n = (IRQn_Type)0;
+    }
+    
+    return irq_n;
+}
+
+/******************************************************************************
+ * MBED API FUNCTIONS
+ ******************************************************************************/
+
+/** 
+ * Begin asynchronous TX transfer. The used buffer is specified in the serial
+ * object, tx_buff
+ *
+ * @param obj       The serial object
+ * @param tx        The buffer for sending
+ * @param tx_length The number of words to transmit
+ * @param tx_width  The bit width of buffer word
+ * @param handler   The serial handler
+ * @param event     The logical OR of events to be registered
+ * @param hint      A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, or 0 otherwise
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{    
+    // TODO: DMA usage is currently ignored
+    (void) hint;
+    
+    // Check buffer is ok
+    MBED_ASSERT(tx != (void*)0);
+    MBED_ASSERT(tx_width == 8); // support only 8b width
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
+
+    if (tx_length == 0) {
+        return 0;
+    }
+  
+    // Set up buffer
+    serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
+  
+    // Set up events
+    serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
+    serial_enable_event(obj, event, 1); // Set only the wanted events
+    
+    // Enable interrupt
+    IRQn_Type irq_n = serial_get_irq_n(obj);
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_DisableIRQ(irq_n);
+    NVIC_SetPriority(irq_n, 1);
+    NVIC_SetVector(irq_n, (uint32_t)handler);
+    NVIC_EnableIRQ(irq_n);
+
+    // the following function will enable UART_IT_TXE and error interrupts
+    if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
+        return 0;
+    }
+    
+    return tx_length;
+}
+
+/** 
+ * Begin asynchronous RX transfer (enable interrupt for data collecting)
+ * The used buffer is specified in the serial object, rx_buff
+ *
+ * @param obj        The serial object
+ * @param rx         The buffer for sending
+ * @param rx_length  The number of words to transmit
+ * @param rx_width   The bit width of buffer word
+ * @param handler    The serial handler
+ * @param event      The logical OR of events to be registered
+ * @param handler    The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint       A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+    // TODO: DMA usage is currently ignored
+    (void) hint;
+
+    /* Sanity check arguments */
+    MBED_ASSERT(obj);
+    MBED_ASSERT(rx != (void*)0);
+    MBED_ASSERT(rx_width == 8); // support only 8b width
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+    serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
+    serial_enable_event(obj, event, 1);
+    
+    // set CharMatch
+    obj->char_match = char_match;
+    
+    serial_rx_buffer_set(obj, rx, rx_length, rx_width);
+
+    IRQn_Type irq_n = serial_get_irq_n(obj);
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_DisableIRQ(irq_n);
+    NVIC_SetPriority(irq_n, 0);
+    NVIC_SetVector(irq_n, (uint32_t)handler);
+    NVIC_EnableIRQ(irq_n);
+
+    // following HAL function will enable the RXNE interrupt + error interrupts    
+    HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
+}
+
+/**
+ * Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the TX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj)
+{
+    MBED_ASSERT(obj);
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
+}
+
+/**
+ * Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj)
+{
+    MBED_ASSERT(obj);
+    
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
+        __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+}
+}
+
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear PE flag
+    } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear FE flag
+    } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear NE flag
+    } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear ORE flag
+    }
+}
+
+/**
+ * The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise
+ */
+int serial_irq_handler_asynch(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    volatile int return_event = 0;
+    uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
+    uint8_t i = 0;
+    
+    // TX PART:
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
+        if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+            // Return event SERIAL_EVENT_TX_COMPLETE if requested
+            if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
+                return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
+            }
+        }
+    }
+    
+    // Handle error events
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
+        if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) {
+            return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
+        }
+}
+
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
+        if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) {
+            return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
+        }
+    }
+    
+    if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+        if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) {
+            return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
+        }
+    }
+    
+    HAL_UART_IRQHandler(huart);
+    
+    // Abort if an error occurs
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
+        return return_event;
+    }
+    
+    //RX PART
+    if (huart->RxXferSize != 0) {
+        obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
+    }
+    if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
+        return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
+    }
+    
+    // Check if char_match is present
+    if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+        if (buf != NULL) {
+            for (i = 0; i < obj->rx_buff.pos; i++) {
+                if (buf[i] == obj->char_match) {
+                    obj->rx_buff.pos = i;
+                    return_event |= (SERIAL_EVENT_RX_CHARACTER_MATCH & obj_s->events);
+                    serial_rx_abort_asynch(obj);
+                    break;
+                }
+            }
+        }
+    }
+    
+    return return_event;  
+}
+
+/** 
+ * Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ * flush TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+    __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+    
+    // clear flags
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+    
+    // reset states
+    huart->TxXferCount = 0;
+    // update handle state
+    if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
+        huart->gState = HAL_UART_STATE_BUSY_RX;
+    } else {
+        huart->gState = HAL_UART_STATE_READY;
+    }
+}
+
+/**
+ * Abort the ongoing RX transaction It disables the enabled interrupt for RX and
+ * flush RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    
+    // disable interrupts
+    __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+    __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+    __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+    
+    // clear flags
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear errors flag
+    
+    // reset states
+    huart->RxXferCount = 0;
+    // update handle state
+    if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
+        huart->RxState = HAL_UART_STATE_BUSY_TX;
+    } else {
+        huart->RxState = HAL_UART_STATE_READY;
+    }
+}
+
+#endif
+
+#if DEVICE_SERIAL_FC
+
+/**
+ * Set HW Control Flow
+ * @param obj    The serial object
+ * @param type   The Control Flow type (FlowControlNone, FlowControlRTS, FlowControlCTS, FlowControlRTSCTS)
+ * @param rxflow Pin for the rxflow
+ * @param txflow Pin for the txflow
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+
+    // Determine the UART to use (UART_1, UART_2, ...)
+    UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+    UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+
+    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+    obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
+    MBED_ASSERT(obj_s->uart != (UARTName)NC);
+
+    if(type == FlowControlNone) {
+        // Disable hardware flow control
+      obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
+    }
+    if (type == FlowControlRTS) {
+        // Enable RTS
+        MBED_ASSERT(uart_rts != (UARTName)NC);
+        obj_s->hw_flow_ctl = UART_HWCONTROL_RTS;
+        obj_s->pin_rts = rxflow;
+        // Enable the pin for RTS function
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+    }
+    if (type == FlowControlCTS) {
+        // Enable CTS
+        MBED_ASSERT(uart_cts != (UARTName)NC);
+        obj_s->hw_flow_ctl = UART_HWCONTROL_CTS;
+        obj_s->pin_cts = txflow;
+        // Enable the pin for CTS function
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+    }
+    if (type == FlowControlRTSCTS) {
+        // Enable CTS & RTS
+        MBED_ASSERT(uart_rts != (UARTName)NC);
+        MBED_ASSERT(uart_cts != (UARTName)NC);
+        obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS;
+        obj_s->pin_rts = rxflow;
+        obj_s->pin_cts = txflow;
+        // Enable the pin for CTS function
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+        // Enable the pin for RTS function
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+    }
+    
+    init_uart(obj);
+}
+
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.c
new file mode 100755
index 0000000..d383c9d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_api.c
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
+#endif
+
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
+	int spi_hz = 0;
+
+	/* Get source clock depending on SPI instance */
+    switch ((int)spiobj->spi) {
+        case SPI_1:
+            /* SPI_1. Source CLK is PCKL2 */
+            spi_hz = HAL_RCC_GetPCLK2Freq();
+            break;
+#if defined(SPI2_BASE)
+        case SPI_2:
+#endif
+        case SPI_3:
+            /* SPI_2, SPI_3. Source CLK is PCKL1 */
+            spi_hz = HAL_RCC_GetPCLK1Freq();
+            break;
+        default:
+			error("CLK: SPI instance not set");
+            break;
+    }
+    return spi_hz;
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_device.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_device.h
new file mode 100755
index 0000000..ee6b82c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/TARGET_STM32L4/spi_device.h
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_SPI_DEVICE_H
+#define MBED_SPI_DEVICE_H
+
+#include "stm32l4xx_ll_spi.h"
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/analogout_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/analogout_api.c
new file mode 100755
index 0000000..4dac5ce
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/analogout_api.c
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+#define DAC_RANGE (0xFFF) // 12 bits
+#define DAC_NB_BITS  (12)
+
+static inline void dac_write(dac_t *obj, int value)
+{
+    HAL_DAC_SetValue(&obj->handle, obj->channel, DAC_ALIGN_12B_R, (value & DAC_RANGE));
+    HAL_DAC_Start(&obj->handle, obj->channel);
+}
+
+static inline int dac_read(dac_t *obj)
+{
+    return (int)HAL_DAC_GetValue(&obj->handle, obj->channel);
+}
+
+void analogout_write(dac_t *obj, float value)
+{
+    if (value < 0.0f) {
+        dac_write(obj, 0); // Min value
+    } else if (value > 1.0f) {
+        dac_write(obj, (int)DAC_RANGE); // Max value
+    } else {
+        dac_write(obj, (int)(value * (float)DAC_RANGE));
+    }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
+    dac_write(obj, value >> (16 - DAC_NB_BITS));
+}
+
+float analogout_read(dac_t *obj)
+{
+    uint32_t value = dac_read(obj);
+    return (float)value * (1.0f / (float)DAC_RANGE);
+}
+
+uint16_t analogout_read_u16(dac_t *obj)
+{
+    uint32_t value = dac_read(obj);
+    return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits
+}
+
+#endif // DEVICE_ANALOGOUT
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/can_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/can_api.c
new file mode 100755
index 0000000..b89f628
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/can_api.c
@@ -0,0 +1,654 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "mbed_error.h"
+#include "can_device.h" // Specific to STM32 serie
+#include <math.h>
+#include <string.h>
+
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler irq_handler;
+
+static void can_registers_init(can_t *obj)
+{
+    if (HAL_CAN_Init(&obj->CanHandle) != HAL_OK) {
+        error("Cannot initialize CAN");
+    }
+
+    // Set initial CAN frequency to specified frequency
+    if (can_frequency(obj, obj->hz) != 1) {
+        error("Can frequency could not be set\n");
+    }
+}
+
+void can_init(can_t *obj, PinName rd, PinName td)
+{
+    can_init_freq(obj, rd, td, 100000);
+}
+
+void can_init_freq (can_t *obj, PinName rd, PinName td, int hz)
+{
+    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    CANName can = (CANName)pinmap_merge(can_rd, can_td);
+
+    MBED_ASSERT((int)can != NC);
+
+    if (can == CAN_1) {
+        __HAL_RCC_CAN1_CLK_ENABLE();
+        obj->index = 0;
+    }
+#if defined(CAN2_BASE) && (CAN_NUM == 2)
+    else if (can == CAN_2) {
+        __HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters
+        __HAL_RCC_CAN2_CLK_ENABLE();
+        obj->index = 1;
+    }
+#endif
+    else {
+        return;
+    }
+
+    // Configure the CAN pins
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    pinmap_pinout(td, PinMap_CAN_TD);
+    if (rd != NC) {
+        pin_mode(rd, PullUp);
+    }
+    if (td != NC) {
+        pin_mode(td, PullUp);
+    }
+
+    /*  Use default values for rist init */
+    obj->CanHandle.Instance = (CAN_TypeDef *)can;
+    obj->CanHandle.Init.TTCM = DISABLE;
+    obj->CanHandle.Init.ABOM = DISABLE;
+    obj->CanHandle.Init.AWUM = DISABLE;
+    obj->CanHandle.Init.NART = DISABLE;
+    obj->CanHandle.Init.RFLM = DISABLE;
+    obj->CanHandle.Init.TXFP = DISABLE;
+    obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
+    obj->CanHandle.Init.SJW = CAN_SJW_1TQ;
+    obj->CanHandle.Init.BS1 = CAN_BS1_6TQ;
+    obj->CanHandle.Init.BS2 = CAN_BS2_8TQ;
+    obj->CanHandle.Init.Prescaler = 2;
+
+    /*  Store frequency to be restored in case of reset */
+    obj->hz = hz;
+
+    can_registers_init(obj);
+
+    uint32_t filter_number = (can == CAN_1) ? 0 : 14;
+    can_filter(obj, 0, 0, CANStandard, filter_number);
+}
+
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
+{
+    irq_handler = handler;
+    can_irq_ids[obj->index] = id;
+}
+
+void can_irq_free(can_t *obj)
+{
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+
+    can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
+                  CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
+    can_irq_ids[obj->index] = 0;
+}
+
+void can_free(can_t *obj)
+{
+    CANName can = (CANName) obj->CanHandle.Instance;
+    // Reset CAN and disable clock
+    if (can == CAN_1) {
+        __HAL_RCC_CAN1_FORCE_RESET();
+        __HAL_RCC_CAN1_RELEASE_RESET();
+        __HAL_RCC_CAN1_CLK_DISABLE();
+    }
+#if defined(CAN2_BASE) && (CAN_NUM == 2)
+    if (can == CAN_2) {
+        __HAL_RCC_CAN2_FORCE_RESET();
+        __HAL_RCC_CAN2_RELEASE_RESET();
+        __HAL_RCC_CAN2_CLK_DISABLE();
+    }
+#endif
+}
+
+// The following table is used to program bit_timing. It is an adjustment of the sample
+// point by synchronizing on the start-bit edge and resynchronizing on the following edges.
+// This table has the sampling points as close to 75% as possible (most commonly used).
+// The first value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+    {0x0, 0x0},      // 2,  50%
+    {0x1, 0x0},      // 3,  67%
+    {0x2, 0x0},      // 4,  75%
+    {0x3, 0x0},      // 5,  80%
+    {0x3, 0x1},      // 6,  67%
+    {0x4, 0x1},      // 7,  71%
+    {0x5, 0x1},      // 8,  75%
+    {0x6, 0x1},      // 9,  78%
+    {0x6, 0x2},      // 10, 70%
+    {0x7, 0x2},      // 11, 73%
+    {0x8, 0x2},      // 12, 75%
+    {0x9, 0x2},      // 13, 77%
+    {0x9, 0x3},      // 14, 71%
+    {0xA, 0x3},      // 15, 73%
+    {0xB, 0x3},      // 16, 75%
+    {0xC, 0x3},      // 17, 76%
+    {0xD, 0x3},      // 18, 78%
+    {0xD, 0x4},      // 19, 74%
+    {0xE, 0x4},      // 20, 75%
+    {0xF, 0x4},      // 21, 76%
+    {0xF, 0x5},      // 22, 73%
+    {0xF, 0x6},      // 23, 70%
+    {0xF, 0x7},      // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw)
+{
+    uint32_t    btr;
+    uint16_t    brp = 0;
+    uint32_t    calcbit;
+    uint32_t    bitwidth;
+    int         hit = 0;
+    int         bits;
+
+    bitwidth = (pclk / cclk);
+
+    brp = bitwidth / 0x18;
+    while ((!hit) && (brp < bitwidth / 4)) {
+        brp++;
+        for (bits = 22; bits > 0; bits--) {
+            calcbit = (bits + 3) * (brp + 1);
+            if (calcbit == bitwidth) {
+                hit = 1;
+                break;
+            }
+        }
+    }
+
+    if (hit) {
+        btr = ((timing_pts[bits][1] << CAN_BTR_TS2_Pos) & CAN_BTR_TS2) |
+              ((timing_pts[bits][0] << CAN_BTR_TS1_Pos) & CAN_BTR_TS1) |
+              ((psjw                << CAN_BTR_SJW_Pos) & CAN_BTR_SJW) |
+              ((brp                 << CAN_BTR_BRP_Pos) & CAN_BTR_BRP);
+    } else {
+        btr = 0xFFFFFFFF;
+    }
+
+    return btr;
+
+}
+
+int can_frequency(can_t *obj, int f)
+{
+    int pclk = HAL_RCC_GetPCLK1Freq();
+    int btr = can_speed(pclk, (unsigned int)f, 1);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+    uint32_t tickstart = 0;
+    int status = 1;
+
+    if (btr > 0) {
+        can->MCR |= CAN_MCR_INRQ ;
+        /* Get tick */
+        tickstart = HAL_GetTick();
+        while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+            if ((HAL_GetTick() - tickstart) > 2) {
+                status = 0;
+                break;
+            }
+        }
+        if (status != 0) {
+            /*  Do not erase all BTR registers (e.g. silent mode), only the
+             *  ones calculated in can_speed */
+            can->BTR &= ~(CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_SJW | CAN_BTR_BRP);
+            can->BTR |= btr;
+
+            can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+            /* Get tick */
+            tickstart = HAL_GetTick();
+            while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
+                if ((HAL_GetTick() - tickstart) > 2) {
+                    status = 0;
+                    break;
+                }
+            }
+            if (status == 0) {
+                error("can ESR  0x%04x.%04x + timeout status %d", (can->ESR & 0xFFFF0000) >> 16, (can->ESR & 0xFFFF), status);
+            }
+        } else {
+            error("can init request timeout\n");
+        }
+    } else {
+        status = 0;
+    }
+    return status;
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc)
+{
+    uint32_t  transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+
+    /* Select one empty transmit mailbox */
+    if ((can->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
+        transmitmailbox = 0;
+    } else if ((can->TSR & CAN_TSR_TME1) == CAN_TSR_TME1) {
+        transmitmailbox = 1;
+    } else if ((can->TSR & CAN_TSR_TME2) == CAN_TSR_TME2) {
+        transmitmailbox = 2;
+    } else {
+      return 0;
+    }
+
+    can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+    if (!(msg.format)) {
+      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | msg.type);
+    } else {
+      can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | msg.type);
+    }
+
+    /* Set up the DLC */
+    can->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    can->sTxMailBox[transmitmailbox].TDTR |= (msg.len & (uint8_t)0x0000000F);
+
+    /* Set up the data field */
+    can->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)msg.data[3] << 24) |
+                                            ((uint32_t)msg.data[2] << 16) |
+                                            ((uint32_t)msg.data[1] << 8) |
+                                            ((uint32_t)msg.data[0]));
+    can->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)msg.data[7] << 24) |
+                                            ((uint32_t)msg.data[6] << 16) |
+                                            ((uint32_t)msg.data[5] << 8) |
+                                                ((uint32_t)msg.data[4]));
+    /* Request transmission */
+    can->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+    return 1;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle)
+{
+    //handle is the FIFO number
+
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+
+    // check FPM0 which holds the pending message count in FIFO 0
+    // if no message is pending, return 0
+    if ((can->RF0R & CAN_RF0R_FMP0) == 0) {
+        return 0;
+    }
+
+    /* Get the Id */
+    msg->format = (CANFormat)(((uint8_t)0x04 & can->sFIFOMailBox[handle].RIR) >> 2);
+    if (!msg->format) {
+        msg->id = (uint32_t)0x000007FF & (can->sFIFOMailBox[handle].RIR >> 21);
+    } else {
+        msg->id = (uint32_t)0x1FFFFFFF & (can->sFIFOMailBox[handle].RIR >> 3);
+    }
+
+    msg->type = (CANType)(((uint8_t)0x02 & can->sFIFOMailBox[handle].RIR) >> 1);
+    /* Get the DLC */
+    msg->len = (uint8_t)0x0F & can->sFIFOMailBox[handle].RDTR;
+    /* Get the FMI */
+    // msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDTR >> 8);
+    /* Get the data field */
+    msg->data[0] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDLR;
+    msg->data[1] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 8);
+    msg->data[2] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 16);
+    msg->data[3] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 24);
+    msg->data[4] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDHR;
+    msg->data[5] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 8);
+    msg->data[6] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 16);
+    msg->data[7] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 24);
+
+    /* Release the FIFO */
+    if (handle == CAN_FIFO0) {
+        /* Release FIFO0 */
+        can->RF0R |= CAN_RF0R_RFOM0;
+    } else { /* FIFONumber == CAN_FIFO1 */
+        /* Release FIFO1 */
+        can->RF1R |= CAN_RF1R_RFOM1;
+    }
+
+    return 1;
+}
+
+void can_reset(can_t *obj)
+{
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+
+    /* Reset IP and delete errors */
+    can->MCR |= CAN_MCR_RESET;
+    can->ESR = 0x0;
+
+    /* restore registers state as saved in obj context */
+    can_registers_init(obj);
+}
+
+unsigned char can_rderror(can_t *obj)
+{
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+    return (can->ESR >> 24) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj)
+{
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+    return (can->ESR >> 16) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent)
+{
+    CanMode mode = MODE_NORMAL;
+    /*  Update current state w/ or w/o silent */
+    if(silent) {
+        switch (obj->CanHandle.Init.Mode) {
+            case CAN_MODE_LOOPBACK:
+            case CAN_MODE_SILENT_LOOPBACK:
+                mode = MODE_TEST_SILENT;
+                break;
+            default:
+                mode = MODE_SILENT;
+                break;
+        }
+    } else {
+        switch (obj->CanHandle.Init.Mode) {
+            case CAN_MODE_LOOPBACK:
+            case CAN_MODE_SILENT_LOOPBACK:
+                mode = MODE_TEST_LOCAL;
+                break;
+            default:
+                mode = MODE_NORMAL;
+                break;
+        }
+    }
+
+    can_mode(obj, mode);
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+    int success = 0;
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+
+    can->MCR |= CAN_MCR_INRQ ;
+    while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+    }
+
+    switch (mode) {
+        case MODE_NORMAL:
+            obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
+            can->BTR &= ~(CAN_BTR_SILM | CAN_BTR_LBKM);
+            success = 1;
+            break;
+        case MODE_SILENT:
+            obj->CanHandle.Init.Mode = CAN_MODE_SILENT;
+            can->BTR |= CAN_BTR_SILM;
+            can->BTR &= ~CAN_BTR_LBKM;
+            success = 1;
+            break;
+        case MODE_TEST_GLOBAL:
+        case MODE_TEST_LOCAL:
+            obj->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
+            can->BTR |= CAN_BTR_LBKM;
+            can->BTR &= ~CAN_BTR_SILM;
+            success = 1;
+            break;
+        case MODE_TEST_SILENT:
+            obj->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
+            can->BTR |= (CAN_BTR_SILM | CAN_BTR_LBKM);
+            success = 1;
+            break;
+        default:
+            success = 0;
+            break;
+    }
+
+    can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+    while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
+    }
+
+    return success;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
+{
+    int retval = 0;
+
+    // filter for CANAny format cannot be configured for STM32
+    if ((format == CANStandard) || (format == CANExtended)) {
+        CAN_FilterConfTypeDef  sFilterConfig;
+        sFilterConfig.FilterNumber = handle;
+        sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
+        sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
+
+        if (format == CANStandard) {
+            sFilterConfig.FilterIdHigh = id << 5;
+            sFilterConfig.FilterIdLow =  0x0;
+            sFilterConfig.FilterMaskIdHigh = mask << 5;
+            sFilterConfig.FilterMaskIdLow = 0x0; // allows both remote and data frames
+        } else if (format == CANExtended) {
+            sFilterConfig.FilterIdHigh = id >> 13; // EXTID[28:13]
+            sFilterConfig.FilterIdLow = (0x00FF & (id << 3)) | (1 << 2);  // EXTID[12:0]
+            sFilterConfig.FilterMaskIdHigh = mask >> 13;
+            sFilterConfig.FilterMaskIdLow = (0x00FF & (mask << 3)) | (1 << 2);
+        }
+
+        sFilterConfig.FilterFIFOAssignment = 0;
+        sFilterConfig.FilterActivation = ENABLE;
+        sFilterConfig.BankNumber = 14 + handle;
+
+        HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig);
+        retval = handle;
+    }
+    return retval;
+}
+
+static void can_irq(CANName name, int id)
+{
+    uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+    CAN_HandleTypeDef CanHandle;
+    CanHandle.Instance = (CAN_TypeDef *)name;
+
+    if (__HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_TME)) {
+        tmp1 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_0);
+        tmp2 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_1);
+        tmp3 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_2);
+        if (tmp1) {
+            __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP0);
+        }
+        if (tmp2) {
+            __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP1);
+        }
+        if (tmp3) {
+            __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP2);
+        }
+        if (tmp1 || tmp2 || tmp3) {
+            irq_handler(can_irq_ids[id], IRQ_TX);
+        }
+    }
+
+    tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO0);
+    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP0);
+
+    if ((tmp1 != 0) && tmp2) {
+        irq_handler(can_irq_ids[id], IRQ_RX);
+    }
+
+    tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_EPV);
+    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_EPV);
+    tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
+
+    if (tmp1 && tmp2 && tmp3) {
+        irq_handler(can_irq_ids[id], IRQ_PASSIVE);
+    }
+
+    tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_BOF);
+    tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_BOF);
+    tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
+    if (tmp1 && tmp2 && tmp3) {
+        irq_handler(can_irq_ids[id], IRQ_BUS);
+    }
+
+    tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
+    if (tmp1 && tmp2 && tmp3) {
+        irq_handler(can_irq_ids[id], IRQ_ERROR);
+    }
+}
+
+#if defined(TARGET_STM32F0)
+void CAN_IRQHandler(void)
+{
+    can_irq(CAN_1, 0);
+}
+#elif defined(TARGET_STM32F3)
+void CAN_RX0_IRQHandler(void)
+{
+    can_irq(CAN_1, 0);
+}
+void CAN_TX_IRQHandler(void)
+{
+    can_irq(CAN_1, 0);
+}
+void CAN_SCE_IRQHandler(void)
+{
+    can_irq(CAN_1, 0);
+}
+#else
+void CAN1_RX0_IRQHandler(void)
+{
+    can_irq(CAN_1, 0);
+}
+void CAN1_TX_IRQHandler(void)
+{
+    can_irq(CAN_1, 0);
+}
+void CAN1_SCE_IRQHandler(void)
+{
+    can_irq(CAN_1, 0);
+}
+#if defined(CAN2_BASE) && (CAN_NUM == 2)
+void CAN2_RX0_IRQHandler(void)
+{
+    can_irq(CAN_2, 1);
+}
+void CAN2_TX_IRQHandler(void)
+{
+    can_irq(CAN_2, 1);
+}
+void CAN2_SCE_IRQHandler(void)
+{
+    can_irq(CAN_2, 1);
+}
+#endif // defined(CAN2_BASE) && (CAN_NUM == 2)
+#endif // else
+
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
+{
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    uint32_t ier;
+
+    if ((CANName) can == CAN_1) {
+        switch (type) {
+            case IRQ_RX:
+                ier = CAN_IT_FMP0;
+                irq_n = CAN1_IRQ_RX_IRQN;
+                vector = (uint32_t)&CAN1_IRQ_RX_VECT;
+                break;
+            case IRQ_TX:
+                ier = CAN_IT_TME;
+                irq_n = CAN1_IRQ_TX_IRQN;
+                vector = (uint32_t)&CAN1_IRQ_TX_VECT;
+                break;
+            case IRQ_ERROR:
+                ier = CAN_IT_ERR;
+                irq_n = CAN1_IRQ_ERROR_IRQN;
+                vector = (uint32_t)&CAN1_IRQ_ERROR_VECT;
+                break;
+            case IRQ_PASSIVE:
+                ier = CAN_IT_EPV;
+                irq_n = CAN1_IRQ_PASSIVE_IRQN;
+                vector = (uint32_t)&CAN1_IRQ_PASSIVE_VECT;
+                break;
+            case IRQ_BUS:
+                ier = CAN_IT_BOF;
+                irq_n = CAN1_IRQ_BUS_IRQN;
+                vector = (uint32_t)&CAN1_IRQ_BUS_VECT;
+                break;
+            default:
+                return;
+        }
+    }
+#if defined(CAN2_BASE) && (CAN_NUM == 2)
+    else if ((CANName) can == CAN_2) {
+        switch (type) {
+            case IRQ_RX:
+                ier = CAN_IT_FMP0;
+                irq_n = CAN2_IRQ_RX_IRQN;
+                vector = (uint32_t)&CAN2_IRQ_RX_VECT;
+                break;
+            case IRQ_TX:
+                ier = CAN_IT_TME;
+                irq_n = CAN2_IRQ_TX_IRQN;
+                vector = (uint32_t)&CAN2_IRQ_TX_VECT;
+                break;
+            case IRQ_ERROR:
+                ier = CAN_IT_ERR;
+                irq_n = CAN2_IRQ_ERROR_IRQN;
+                vector = (uint32_t)&CAN2_IRQ_ERROR_VECT;
+                break;
+            case IRQ_PASSIVE:
+                ier = CAN_IT_EPV;
+                irq_n = CAN2_IRQ_PASSIVE_IRQN;
+                vector = (uint32_t)&CAN2_IRQ_PASSIVE_VECT;
+                break;
+            case IRQ_BUS:
+                ier = CAN_IT_BOF;
+                irq_n = CAN2_IRQ_BUS_IRQN;
+                vector = (uint32_t)&CAN2_IRQ_BUS_VECT;
+                break;
+            default:
+                return;
+        }
+    }
+#endif
+    else {
+        return;
+    }
+
+    if (enable) {
+        can->IER |= ier;
+    } else {
+        can->IER &= ~ier;
+    }
+
+    NVIC_SetVector(irq_n, vector);
+    NVIC_EnableIRQ(irq_n);
+}
+
+#endif // DEVICE_CAN
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_api.c
new file mode 100755
index 0000000..60d300d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_api.c
@@ -0,0 +1,159 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "pin_device.h"
+
+extern const uint32_t ll_pin_defines[16];
+
+// Enable GPIO clock and return GPIO base address
+GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) {
+    uint32_t gpio_add = 0;
+    switch (port_idx) {
+        case PortA:
+            gpio_add = GPIOA_BASE;
+            __HAL_RCC_GPIOA_CLK_ENABLE();
+            break;
+        case PortB:
+            gpio_add = GPIOB_BASE;
+            __HAL_RCC_GPIOB_CLK_ENABLE();
+            break;
+#if defined(GPIOC_BASE)
+        case PortC:
+            gpio_add = GPIOC_BASE;
+            __HAL_RCC_GPIOC_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOD_BASE
+        case PortD:
+            gpio_add = GPIOD_BASE;
+            __HAL_RCC_GPIOD_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOE_BASE
+        case PortE:
+            gpio_add = GPIOE_BASE;
+            __HAL_RCC_GPIOE_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOF_BASE
+        case PortF:
+            gpio_add = GPIOF_BASE;
+            __HAL_RCC_GPIOF_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOG_BASE
+        case PortG:
+#if defined TARGET_STM32L4
+            __HAL_RCC_PWR_CLK_ENABLE();
+            HAL_PWREx_EnableVddIO2();
+#endif
+            gpio_add = GPIOG_BASE;
+            __HAL_RCC_GPIOG_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOH_BASE
+        case PortH:
+            gpio_add = GPIOH_BASE;
+            __HAL_RCC_GPIOH_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOI_BASE
+        case PortI:
+            gpio_add = GPIOI_BASE;
+            __HAL_RCC_GPIOI_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOJ_BASE
+        case PortJ:
+            gpio_add = GPIOJ_BASE;
+            __HAL_RCC_GPIOJ_CLK_ENABLE();
+            break;
+#endif
+#if defined GPIOK_BASE
+        case PortK:
+            gpio_add = GPIOK_BASE;
+            __HAL_RCC_GPIOK_CLK_ENABLE();
+            break;
+#endif
+        default:
+            error("Pinmap error: wrong port number.");
+            break;
+    }
+    return (GPIO_TypeDef *) gpio_add;
+}
+
+uint32_t gpio_set(PinName pin) {
+    MBED_ASSERT(pin != (PinName)NC);
+
+    pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+    return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+
+void gpio_init(gpio_t *obj, PinName pin) {
+    obj->pin = pin;
+    if (pin == (PinName)NC) {
+        return;
+    }
+
+    uint32_t port_index = STM_PORT(pin);
+
+    // Enable GPIO clock
+    GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
+
+    // Fill GPIO object structure for future use
+    obj->mask    = gpio_set(pin);
+    obj->gpio  = gpio;
+    obj->ll_pin  = ll_pin_defines[STM_PIN(obj->pin)];
+    obj->reg_in  = &gpio->IDR;
+    obj->reg_set = &gpio->BSRR;
+#ifdef GPIO_IP_WITHOUT_BRR
+    obj->reg_clr = &gpio->BSRR;
+#else
+    obj->reg_clr = &gpio->BRR;
+#endif
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+inline void gpio_dir(gpio_t *obj, PinDirection direction) {
+    if (direction == PIN_INPUT) {
+        LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT);
+    } else {
+        LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT);
+    }
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_irq_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_irq_api.c
new file mode 100755
index 0000000..f9c1f57
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_irq_api.c
@@ -0,0 +1,314 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "gpio_irq_device.h"
+
+#define EDGE_NONE (0)
+#define EDGE_RISE (1)
+#define EDGE_FALL (2)
+#define EDGE_BOTH (3)
+
+
+typedef struct gpio_channel {
+    uint32_t pin_mask;                   // bitmask representing which pins are configured for receiving interrupts
+    uint32_t channel_ids[MAX_PIN_LINE];  // mbed "gpio_irq_t gpio_irq" field of instance
+    GPIO_TypeDef* channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
+    uint32_t channel_pin[MAX_PIN_LINE];  // pin number in port group
+} gpio_channel_t;
+
+static gpio_irq_handler irq_handler;
+
+static gpio_channel_t channels[CHANNEL_NUM] = {
+#ifdef EXTI_IRQ0_NUM_LINES
+    {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ1_NUM_LINES
+    {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ2_NUM_LINES
+    {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ3_NUM_LINES
+    {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ4_NUM_LINES
+    {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ5_NUM_LINES
+    {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ6_NUM_LINES
+    {.pin_mask = 0}
+#endif
+};
+
+static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
+{
+    gpio_channel_t *gpio_channel = &channels[irq_index];
+    uint32_t gpio_idx;
+
+    for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
+        uint32_t current_mask = (1 << gpio_idx);
+
+        if (gpio_channel->pin_mask & current_mask) {
+            // Retrieve the gpio and pin that generate the irq
+            GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
+            uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
+
+            // Clear interrupt flag
+            if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
+                __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
+
+                if (gpio_channel->channel_ids[gpio_idx] == 0) {
+                    continue;
+                }
+
+                // Check which edge has generated the irq
+                if ((gpio->IDR & pin) == 0) {
+                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
+                } else {
+                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
+                }
+                return;
+            }
+        }
+    }
+    error("Unexpected Spurious interrupt, index %d\r\n", irq_index);
+}
+
+
+#ifdef EXTI_IRQ0_NUM_LINES
+// EXTI line 0
+static void gpio_irq0(void)
+{
+    handle_interrupt_in(0, EXTI_IRQ0_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ1_NUM_LINES
+// EXTI line 1
+static void gpio_irq1(void)
+{
+    handle_interrupt_in(1, EXTI_IRQ1_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ2_NUM_LINES
+// EXTI line 2
+static void gpio_irq2(void)
+{
+    handle_interrupt_in(2, EXTI_IRQ2_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ3_NUM_LINES
+// EXTI line 3
+static void gpio_irq3(void)
+{
+    handle_interrupt_in(3, EXTI_IRQ3_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ4_NUM_LINES
+// EXTI line 4
+static void gpio_irq4(void)
+{
+    handle_interrupt_in(4, EXTI_IRQ4_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ5_NUM_LINES
+// EXTI lines 5 to 9
+static void gpio_irq5(void)
+{
+    handle_interrupt_in(5, EXTI_IRQ5_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ6_NUM_LINES
+// EXTI lines 10 to 15
+static void gpio_irq6(void)
+{
+    handle_interrupt_in(6, EXTI_IRQ6_NUM_LINES);
+}
+#endif
+
+extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
+extern void pin_function_gpiomode(PinName pin, uint32_t gpiomode);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    uint32_t vector = 0;
+    uint32_t irq_index;
+    gpio_channel_t *gpio_channel;
+    uint32_t gpio_idx;
+
+    if (pin == NC) return -1;
+
+    /* Enable SYSCFG Clock */
+    __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+    uint32_t port_index  = STM_PORT(pin);
+    uint32_t pin_index  = STM_PIN(pin);
+    irq_index =  pin_lines_desc[pin_index].irq_index;
+
+    switch (irq_index) {
+#ifdef EXTI_IRQ0_NUM_LINES
+        case 0:
+            vector = (uint32_t)&gpio_irq0;
+            break;
+#endif
+#ifdef EXTI_IRQ1_NUM_LINES
+        case 1:
+            vector = (uint32_t)&gpio_irq1;
+            break;
+#endif
+#ifdef EXTI_IRQ2_NUM_LINES
+        case 2:
+            vector = (uint32_t)&gpio_irq2;
+            break;
+#endif
+#ifdef EXTI_IRQ3_NUM_LINES
+        case 3:
+            vector = (uint32_t)&gpio_irq3;
+            break;
+#endif
+#ifdef EXTI_IRQ4_NUM_LINES
+        case 4:
+            vector = (uint32_t)&gpio_irq4;
+            break;
+#endif
+#ifdef EXTI_IRQ5_NUM_LINES
+        case 5:
+            vector = (uint32_t)&gpio_irq5;
+            break;
+#endif
+#ifdef EXTI_IRQ6_NUM_LINES
+        case 6:
+            vector = (uint32_t)&gpio_irq6;
+            break;
+#endif
+        default:
+            error("InterruptIn error: pin not supported.\n");
+            return -1;
+    }
+
+    // Enable GPIO clock
+    GPIO_TypeDef *gpio_add = Set_GPIO_Clock(port_index);
+
+    // Save informations for future use
+    obj->irq_n = pin_lines_desc[pin_index].irq_n;
+    obj->irq_index =  pin_lines_desc[pin_index].irq_index;
+    obj->event = EDGE_NONE;
+    obj->pin = pin;
+
+    gpio_channel = &channels[irq_index];
+    gpio_idx = pin_lines_desc[pin_index].gpio_idx;
+    gpio_channel->pin_mask |= (1 << gpio_idx);
+    gpio_channel->channel_ids[gpio_idx] = id;
+    gpio_channel->channel_gpio[gpio_idx] = gpio_add;
+    gpio_channel->channel_pin[gpio_idx] = pin_index;
+
+    irq_handler = handler;
+
+    // Enable EXTI interrupt
+    NVIC_SetVector(obj->irq_n, vector);
+    gpio_irq_enable(obj);
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    uint32_t gpio_idx = pin_lines_desc[STM_PIN(obj->pin)].gpio_idx;
+    gpio_channel_t *gpio_channel = &channels[obj->irq_index];
+
+    gpio_irq_disable(obj);
+    gpio_channel->pin_mask &= ~(1 << gpio_idx);
+    gpio_channel->channel_ids[gpio_idx] = 0;
+    gpio_channel->channel_gpio[gpio_idx] = 0;
+    gpio_channel->channel_pin[gpio_idx] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    /*  Enable / Disable Edge triggered interrupt and store event */
+    if (event == IRQ_RISE) {
+        if (enable) {
+            LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event |= IRQ_RISE;
+        } else {
+            LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event &= ~IRQ_RISE;
+        }
+    }
+    if (event == IRQ_FALL) {
+        if (enable) {
+            LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event |= IRQ_FALL;
+        } else {
+            LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event &= ~IRQ_FALL;
+        }
+    }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    uint32_t temp = 0;
+    uint32_t port_index = STM_PORT(obj->pin);
+    uint32_t pin_index  = STM_PIN(obj->pin);
+
+    /*  Select Source  */
+    temp = SYSCFG->EXTICR[pin_index >> 2];
+    CLEAR_BIT(temp, (0x0FU) << (4U * (pin_index & 0x03U)));
+    SET_BIT(temp, port_index << (4U * (pin_index & 0x03U)));
+    SYSCFG->EXTICR[pin_index >> 2] = temp;
+
+    LL_EXTI_EnableIT_0_31(1 << pin_index);
+
+    /* Restore previous edge interrupt configuration if applicable */
+    if (obj->event & IRQ_RISE) {
+        LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+    }
+    if (obj->event & IRQ_FALL) {
+        LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+    }
+
+    NVIC_EnableIRQ(obj->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    /* Clear EXTI line configuration */
+    LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+    LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+    LL_EXTI_DisableIT_0_31(1 << STM_PIN(obj->pin));
+    NVIC_DisableIRQ(obj->irq_n);
+    NVIC_ClearPendingIRQ(obj->irq_n);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_object.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_object.h
new file mode 100755
index 0000000..230c8a0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/gpio_object.h
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Note: reg_clr might actually be same as reg_set.
+ * Depends on family whether BRR is available on top of BSRR
+ * if BRR does not exist, family shall define GPIO_IP_WITHOUT_BRR
+ */
+typedef struct {
+    uint32_t mask;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+    PinName  pin;
+    GPIO_TypeDef *gpio;
+    uint32_t ll_pin;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+    if (value) {
+        *obj->reg_set = obj->mask;
+    } else {
+#ifdef GPIO_IP_WITHOUT_BRR
+        *obj->reg_clr = obj->mask << 16;
+#else
+        *obj->reg_clr = obj->mask;
+#endif
+    }
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return obj->pin != (PinName)NC;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/hal_tick_16b.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/hal_tick_16b.c
new file mode 100755
index 0000000..f8e39f5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/hal_tick_16b.c
@@ -0,0 +1,182 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal_tick.h"
+
+// A 16-bit timer is used
+#if TIM_MST_16BIT
+
+#define DEBUG_TICK 0 // Set to 1 to toggle a pin (see below which pin) at each tick
+
+extern TIM_HandleTypeDef TimMasterHandle;
+
+extern volatile uint32_t SlaveCounter;
+extern volatile uint32_t oc_int_part;
+
+volatile uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+#if defined(TARGET_STM32F0)
+void timer_update_irq_handler(void) {
+#else
+void timer_irq_handler(void)
+{
+#endif
+    TimMasterHandle.Instance = TIM_MST;
+
+    // Clear Update interrupt flag
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_UPDATE) == SET) {
+            __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_UPDATE);
+            SlaveCounter++;
+        }
+    }
+
+#if defined(TARGET_STM32F0)
+} // end timer_update_irq_handler function
+// Used for mbed timeout (channel 1) and HAL tick (channel 2)
+void timer_oc_irq_handler(void)
+{
+    TimMasterHandle.Instance = TIM_MST;
+#endif
+
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) {
+            __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+
+                if (oc_int_part > 0) {
+                    oc_int_part--;
+                } else {
+                   us_ticker_irq_handler();
+                }
+        }
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
+
+        if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) {
+            __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+            uint32_t val = __HAL_TIM_GET_COUNTER(&TimMasterHandle);
+            if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+                // Increment HAL variable
+                HAL_IncTick();
+                // Prepare next interrupt
+                __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+                PreviousVal = val;
+#if DEBUG_TICK > 0
+                HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+            }
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+
+    // Update the SystemCoreClock variable
+    SystemCoreClockUpdate();
+
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period        = 0xFFFF;
+    TimMasterHandle.Init.Prescaler     = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+    TimMasterHandle.Init.ClockDivision = 0;
+    TimMasterHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
+#if !defined(TARGET_STM32L0)
+    TimMasterHandle.Init.RepetitionCounter = 0;
+#endif
+#ifdef TIM_AUTORELOAD_PRELOAD_DISABLE
+    TimMasterHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+    HAL_TIM_Base_Init(&TimMasterHandle);
+
+    //LL_TIM_EnableUpdateEvent(TimMasterHandle.Instance);
+
+    // Configure output compare channel 1 for mbed timeout (enabled later when used)
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Configure output compare channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GET_COUNTER(&TimMasterHandle);
+    __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+
+
+
+    // Configure interrupts
+    // Update interrupt used for 32-bit counter
+    // Output compare channel 1 interrupt for mbed timeout
+    // Output compare channel 2 interrupt for HAL tick
+#if defined(TARGET_STM32F0)
+    NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_UP_IRQ);
+    NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
+    NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_OC_IRQ);
+    NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
+#else
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+#endif
+
+    // Enable interrupts
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick
+
+    // Enable timer
+    HAL_TIM_Base_Start(&TimMasterHandle);
+
+    // Freeze timer on stop/breakpoint
+    // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
+    TIM_MST_DBGMCU_FREEZE;
+#endif
+
+#if DEBUG_TICK > 0
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void HAL_SuspendTick(void)
+{
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void HAL_ResumeTick(void)
+{
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+}
+
+#endif // TIM_MST_16BIT
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/hal_tick_32b.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/hal_tick_32b.c
new file mode 100755
index 0000000..7e84f34
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/hal_tick_32b.c
@@ -0,0 +1,152 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal_tick.h"
+
+// A 32-bit timer is used
+#if !TIM_MST_16BIT
+
+#define DEBUG_TICK 0 // Set to 1 to toggle a pin (see below which pin) at each tick
+
+extern TIM_HandleTypeDef TimMasterHandle;
+
+extern void HAL_IncTick(void);
+
+volatile uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void)
+{
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) {
+            __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+            us_ticker_irq_handler();
+        }
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) {
+            __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+            uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+            if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+                // Increment HAL variable
+                HAL_IncTick();
+                // Prepare next interrupt
+                __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+                PreviousVal = val;
+#if DEBUG_TICK > 0
+                HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+            }
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    uint32_t PclkFreq;
+
+    // Get clock configuration
+    // Note: PclkFreq contains here the Latency (not used after)
+    HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq);
+
+    // Get timer clock value
+#if TIM_MST_PCLK == 1
+    PclkFreq = HAL_RCC_GetPCLK1Freq();
+#else
+    PclkFreq = HAL_RCC_GetPCLK2Freq();
+#endif
+
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period          = 0xFFFFFFFF;
+
+    // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx
+#if TIM_MST_PCLK == 1
+    if (RCC_ClkInitStruct.APB1CLKDivider == RCC_HCLK_DIV1) {
+#else
+    if (RCC_ClkInitStruct.APB2CLKDivider == RCC_HCLK_DIV1) {
+#endif
+        TimMasterHandle.Init.Prescaler   = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 us tick
+    } else {
+        TimMasterHandle.Init.Prescaler   = (uint16_t)((PclkFreq * 2) / 1000000) - 1; // 1 us tick
+    }
+
+    TimMasterHandle.Init.ClockDivision     = 0;
+    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
+#if !TARGET_STM32L1
+    TimMasterHandle.Init.RepetitionCounter = 0;
+#endif
+#ifdef TIM_AUTORELOAD_PRELOAD_DISABLE
+    TimMasterHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+    HAL_TIM_OC_Init(&TimMasterHandle);
+
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+
+    // Channel 1 for mbed timeout
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+    // Freeze timer on stop/breakpoint
+    // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
+    TIM_MST_DBGMCU_FREEZE;
+#endif
+
+#if DEBUG_TICK > 0
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void HAL_SuspendTick(void)
+{
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void HAL_ResumeTick(void)
+{
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+}
+
+#endif // !TIM_MST_16BIT
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/i2c_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/i2c_api.c
new file mode 100755
index 0000000..3133086
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/i2c_api.c
@@ -0,0 +1,1148 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "platform/mbed_wait_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "i2c_device.h" // family specific defines
+
+#ifndef DEBUG_STDIO
+#   define DEBUG_STDIO 0
+#endif
+
+#if DEBUG_STDIO
+#   include <stdio.h>
+#   define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
+#else
+#   define DEBUG_PRINTF(...) {}
+#endif
+
+#if DEVICE_I2C_ASYNCH
+    #define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
+#else
+    #define I2C_S(obj) (struct i2c_s *) (obj)
+#endif
+
+/*  Family specific description for I2C */
+#define I2C_NUM (5)
+static I2C_HandleTypeDef* i2c_handles[I2C_NUM];
+
+/* Timeout values are based on core clock and I2C clock.
+   The BYTE_TIMEOUT is computed as twice the number of cycles it would
+   take to send 10 bits over I2C. Most Flags should take less than that.
+   This is for immediate FLAG or ACK check.
+*/
+#define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
+/* Timeout values based on I2C clock.
+   The BYTE_TIMEOUT_US is computed as 3x the time in us it would
+   take to send 10 bits over I2C. Most Flags should take less than that.
+   This is for complete transfers check.
+*/
+#define BYTE_TIMEOUT_US   ((SystemCoreClock / obj_s->hz) * 3 * 10)
+/* Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will
+   not remain stuck if the I2C communication is corrupted. 
+*/
+#define FLAG_TIMEOUT ((int)0x1000)
+
+/* GENERIC INIT and HELPERS FUNCTIONS */
+
+#if defined(I2C1_BASE)
+static void i2c1_irq(void)
+{
+    I2C_HandleTypeDef * handle = i2c_handles[0];
+    HAL_I2C_EV_IRQHandler(handle);
+    HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(I2C2_BASE)
+static void i2c2_irq(void)
+{
+    I2C_HandleTypeDef * handle = i2c_handles[1];
+    HAL_I2C_EV_IRQHandler(handle);
+    HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(I2C3_BASE)
+static void i2c3_irq(void)
+{
+    I2C_HandleTypeDef * handle = i2c_handles[2];
+    HAL_I2C_EV_IRQHandler(handle);
+    HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(I2C4_BASE)
+static void i2c4_irq(void)
+{
+    I2C_HandleTypeDef * handle = i2c_handles[3];
+    HAL_I2C_EV_IRQHandler(handle);
+    HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(FMPI2C1_BASE)
+static void i2c5_irq(void)
+{
+    I2C_HandleTypeDef * handle = i2c_handles[4];
+    HAL_I2C_EV_IRQHandler(handle);
+    HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+
+void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
+    IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
+    /*  default prio in master case is set to 2 */
+    uint32_t prio = 2;
+
+    /* Set up ITs using IRQ and handler tables */
+    NVIC_SetVector(irq_event_n, handler);
+    NVIC_SetVector(irq_error_n, handler);
+
+#if DEVICE_I2CSLAVE
+    /*  Set higher priority to slave device than master.
+     *  In case a device makes use of both master and slave, the
+     *  slave needs higher responsiveness.
+     */
+    if (obj_s->slave) {
+        prio = 1;
+    }
+#endif
+
+    NVIC_SetPriority(irq_event_n, prio);
+    NVIC_SetPriority(irq_error_n, prio);
+    NVIC_EnableIRQ(irq_event_n);
+    NVIC_EnableIRQ(irq_error_n);
+}
+
+void i2c_ev_err_disable(i2c_t *obj) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
+    IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
+
+    HAL_NVIC_DisableIRQ(irq_event_n);
+    HAL_NVIC_DisableIRQ(irq_error_n);
+}
+
+uint32_t i2c_get_irq_handler(i2c_t *obj)
+{
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    uint32_t handler = 0;
+
+    switch (obj_s->index) {
+#if defined(I2C1_BASE)
+        case 0:
+            handler = (uint32_t)&i2c1_irq;
+            break;
+#endif
+#if defined(I2C2_BASE)
+        case 1:
+            handler = (uint32_t)&i2c2_irq;
+            break;
+#endif
+#if defined(I2C3_BASE)
+        case 2:
+            handler = (uint32_t)&i2c3_irq;
+            break;
+#endif
+#if defined(I2C4_BASE)
+        case 3:
+            handler = (uint32_t)&i2c4_irq;
+            break;
+#endif
+#if defined(FMPI2C1_BASE)
+        case 4:
+            handler = (uint32_t)&i2c5_irq;
+            break;
+#endif
+    }
+
+    i2c_handles[obj_s->index] = handle;
+    return handler;
+}
+
+void i2c_hw_reset(i2c_t *obj) {
+    int timeout;
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
+
+    // wait before reset
+    timeout = BYTE_TIMEOUT;
+    while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
+#if defined I2C1_BASE
+    if (obj_s->i2c == I2C_1) {
+        __HAL_RCC_I2C1_FORCE_RESET();
+        __HAL_RCC_I2C1_RELEASE_RESET();
+    }
+#endif
+#if defined I2C2_BASE
+    if (obj_s->i2c == I2C_2) {
+        __HAL_RCC_I2C2_FORCE_RESET();
+        __HAL_RCC_I2C2_RELEASE_RESET();
+    }
+#endif
+#if defined I2C3_BASE
+    if (obj_s->i2c == I2C_3) {
+        __HAL_RCC_I2C3_FORCE_RESET();
+        __HAL_RCC_I2C3_RELEASE_RESET();
+    }
+#endif
+#if defined I2C4_BASE
+    if (obj_s->i2c == I2C_4) {
+        __HAL_RCC_I2C4_FORCE_RESET();
+        __HAL_RCC_I2C4_RELEASE_RESET();
+    }
+#endif
+#if defined FMPI2C1_BASE
+    if (obj_s->i2c == FMPI2C_1) {
+        __HAL_RCC_FMPI2C1_FORCE_RESET();
+        __HAL_RCC_FMPI2C1_RELEASE_RESET();
+    }
+#endif
+}
+
+void i2c_sw_reset(i2c_t *obj)
+{
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    /*  SW reset procedure:
+     *  PE must be kept low during at least 3 APB clock cycles
+     *  in order to perform the software reset.
+     *  This is ensured by writing the following software sequence:
+     *  - Write PE=0
+     *  - Check PE=0
+     *  - Write PE=1.
+     */
+    handle->Instance->CR1 &=  ~I2C_CR1_PE;
+    while(handle->Instance->CR1 & I2C_CR1_PE);
+    handle->Instance->CR1 |=  I2C_CR1_PE;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+
+    struct i2c_s *obj_s = I2C_S(obj);
+
+    // Determine the I2C to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj_s->sda = sda;
+    obj_s->scl = scl;
+
+    obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT(obj_s->i2c != (I2CName)NC);
+
+#if defined I2C1_BASE
+    // Enable I2C1 clock and pinout if not done
+    if (obj_s->i2c == I2C_1) {
+        obj_s->index = 0;
+        __HAL_RCC_I2C1_CLK_ENABLE();
+        // Configure I2C pins
+        obj_s->event_i2cIRQ = I2C1_EV_IRQn;
+        obj_s->error_i2cIRQ = I2C1_ER_IRQn;
+    }
+#endif
+#if defined I2C2_BASE
+    // Enable I2C2 clock and pinout if not done
+    if (obj_s->i2c == I2C_2) {
+        obj_s->index = 1;
+        __HAL_RCC_I2C2_CLK_ENABLE();
+        obj_s->event_i2cIRQ = I2C2_EV_IRQn;
+        obj_s->error_i2cIRQ = I2C2_ER_IRQn;
+    }
+#endif
+#if defined I2C3_BASE
+    // Enable I2C3 clock and pinout if not done
+    if (obj_s->i2c == I2C_3) {
+        obj_s->index = 2;
+        __HAL_RCC_I2C3_CLK_ENABLE();
+        obj_s->event_i2cIRQ = I2C3_EV_IRQn;
+        obj_s->error_i2cIRQ = I2C3_ER_IRQn;
+    }
+#endif
+#if defined I2C4_BASE
+    // Enable I2C3 clock and pinout if not done
+    if (obj_s->i2c == I2C_4) {
+        obj_s->index = 3;
+        __HAL_RCC_I2C4_CLK_ENABLE();
+        obj_s->event_i2cIRQ = I2C4_EV_IRQn;
+        obj_s->error_i2cIRQ = I2C4_ER_IRQn;
+    }
+#endif
+#if defined FMPI2C1_BASE
+    // Enable I2C3 clock and pinout if not done
+    if (obj_s->i2c == FMPI2C_1) {
+        obj_s->index = 4;
+        __HAL_RCC_FMPI2C1_CLK_ENABLE();
+        obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
+        obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
+    }
+#endif
+
+    // Configure I2C pins
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    pin_mode(sda, OpenDrainNoPull);
+    pin_mode(scl, OpenDrainNoPull);
+
+    // I2C configuration
+    // Default hz value used for timeout computation
+    if(!obj_s->hz)
+        obj_s->hz = 100000; // 100 kHz per default
+
+    // Reset to clear pending flags if any
+    i2c_hw_reset(obj);
+    i2c_frequency(obj, obj_s->hz );
+
+#if DEVICE_I2CSLAVE
+    // I2C master by default
+    obj_s->slave = 0;
+    obj_s->pending_slave_tx_master_rx = 0;
+    obj_s->pending_slave_rx_maxter_tx = 0;
+#endif
+
+    // I2C Xfer operation init
+    obj_s->event = 0;
+    obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+#ifdef I2C_IP_VERSION_V2
+    obj_s->pending_start = 0;
+#endif
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    int timeout;
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    // wait before init
+    timeout = BYTE_TIMEOUT;
+    while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
+
+#ifdef I2C_IP_VERSION_V1
+    handle->Init.ClockSpeed      = hz;
+    handle->Init.DutyCycle       = I2C_DUTYCYCLE_2;
+#endif
+#ifdef I2C_IP_VERSION_V2
+    /*  Only predefined timing for below frequencies are supported */
+    MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
+    handle->Init.Timing = get_i2c_timing(hz);
+
+    // Enable the Fast Mode Plus capability
+    if (hz == 1000000) {
+#if defined(I2C1_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C1)
+        if (obj_s->i2c == I2C_1) {
+            HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
+        }
+#endif
+#if defined(I2C2_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C2)
+        if (obj_s->i2c == I2C_2) {
+            HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
+        }
+#endif
+#if defined(I2C3_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C3)
+        if (obj_s->i2c == I2C_3) {
+            HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
+        }
+#endif
+#if defined(I2C4_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C4)
+        if (obj_s->i2c == I2C_4) {
+            HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
+        }
+#endif
+    }
+#endif //I2C_IP_VERSION_V2
+
+    /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
+#if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
+    if (obj_s->i2c == I2C_1) {
+        __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
+    }
+#endif
+#if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
+    if (obj_s->i2c == I2C_2) {
+        __HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
+    }
+#endif
+#if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
+    if (obj_s->i2c == I2C_3) {
+        __HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
+    }
+#endif
+#if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
+    if (obj_s->i2c == I2C_4) {
+        __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
+    }
+#endif
+
+#ifdef I2C_ANALOGFILTER_ENABLE
+    /* Enable the Analog I2C Filter */
+    HAL_I2CEx_AnalogFilter_Config(handle,I2C_ANALOGFILTER_ENABLE);
+#endif
+
+    // I2C configuration
+    handle->Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
+    handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+    handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+    handle->Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;
+    handle->Init.OwnAddress1     = 0;
+    handle->Init.OwnAddress2     = 0;
+    HAL_I2C_Init(handle);
+
+    /*  store frequency for timeout computation */
+    obj_s->hz = hz;
+}
+
+i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
+    /* Aim of the function is to get i2c_s pointer using hi2c pointer */
+    /* Highly inspired from magical linux kernel's "container_of" */
+    /* (which was not directly used since not compatible with IAR toolchain) */
+    struct i2c_s *obj_s;
+    i2c_t *obj;
+
+    obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle));
+    obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c));
+
+    return (obj);
+}
+
+void i2c_reset(i2c_t *obj) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    /*  As recommended in i2c_api.h, mainly send stop */
+    i2c_stop(obj);
+    /* then re-init */
+    i2c_init(obj, obj_s->sda, obj_s->scl);
+}
+
+/*
+ *  UNITARY APIS.
+ *  For very basic operations, direct registers access is needed
+ *  There are 2 different IPs version that need to be supported
+ */
+#ifdef I2C_IP_VERSION_V1
+int i2c_start(i2c_t *obj) {
+
+    int timeout;
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    // Clear Acknowledge failure flag
+    __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
+
+    // Wait the STOP condition has been previously correctly sent
+    // This timeout can be avoid in some specific cases by simply clearing the STOP bit
+    timeout = FLAG_TIMEOUT;
+    while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
+        if ((timeout--) == 0) {
+            return 1;
+        }
+    }
+
+    // Generate the START condition
+    handle->Instance->CR1 |= I2C_CR1_START;
+
+    // Wait the START condition has been correctly sent
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
+        if ((timeout--) == 0) {
+            return 1;
+        }
+    }
+
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
+
+    // Generate the STOP condition
+    i2c->CR1 |= I2C_CR1_STOP;
+
+    /*  In case of mixed usage of the APIs (unitary + SYNC)
+     *  re-init HAL state
+     */
+    if(obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME)
+            i2c_init(obj, obj_s->sda, obj_s->scl);
+
+    return 0;
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+
+    int timeout;
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    if (last) {
+        // Don't acknowledge the last byte
+        handle->Instance->CR1 &= ~I2C_CR1_ACK;
+    } else {
+        // Acknowledge the byte
+        handle->Instance->CR1 |= I2C_CR1_ACK;
+    }
+
+    // Wait until the byte is received
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
+        if ((timeout--) == 0) {
+            return -1;
+        }
+    }
+
+    return (int)handle->Instance->DR;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+
+    int timeout;
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    handle->Instance->DR = (uint8_t)data;
+
+    // Wait until the byte (might be the address) is transmitted
+    timeout = FLAG_TIMEOUT;
+    while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
+            (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
+             (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
+        if ((timeout--) == 0) {
+            return 2;
+        }
+    }
+
+     if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET)
+     {
+         __HAL_I2C_CLEAR_ADDRFLAG(handle);
+     }
+
+    return 1;
+}
+#endif //I2C_IP_VERSION_V1
+#ifdef I2C_IP_VERSION_V2
+
+int i2c_start(i2c_t *obj) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    /*  This I2C IP doesn't  */
+    obj_s->pending_start = 1;
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    int timeout = FLAG_TIMEOUT;
+#if DEVICE_I2CSLAVE
+    if (obj_s->slave) {
+        /*  re-init slave when stop is requested */
+        i2c_init(obj, obj_s->sda, obj_s->scl);
+        return 0;
+    }
+#endif
+    // Disable reload mode
+    handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
+    // Generate the STOP condition
+    handle->Instance->CR2 |= I2C_CR2_STOP;
+
+    timeout = FLAG_TIMEOUT;
+    while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
+        if ((timeout--) == 0) {
+            return I2C_ERROR_BUS_BUSY;
+        }
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
+
+    /* Erase slave address, this wiil be used as a marker
+     * to know when we need to prepare next start */
+    handle->Instance->CR2 &=  ~I2C_CR2_SADD;
+
+    /*
+     * V2 IP is meant for automatic STOP, not user STOP
+     * SW reset the IP state machine before next transaction
+     */
+    i2c_sw_reset(obj);
+
+    /*  In case of mixed usage of the APIs (unitary + SYNC)
+     *  re-init HAL state */
+    if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
+        i2c_init(obj, obj_s->sda, obj_s->scl);
+    }
+
+    return 0;
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    int timeout = FLAG_TIMEOUT;
+    uint32_t tmpreg = handle->Instance->CR2;
+    char data;
+#if DEVICE_I2CSLAVE
+    if (obj_s->slave) {
+        return i2c_slave_read(obj, &data, 1);
+    }
+#endif
+    /* Then send data when there's room in the TX fifo */
+    if ((tmpreg & I2C_CR2_RELOAD) != 0) {
+        while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
+            if ((timeout--) == 0) {
+                DEBUG_PRINTF("timeout in byte_read\r\n");
+                return -1;
+            }
+        }
+    }
+
+    /* Enable reload mode as we don't know how many bytes will be sent */
+    /* and set transfer size to 1 */
+    tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
+    /* Set the prepared configuration */
+    handle->Instance->CR2 = tmpreg;
+
+    timeout = FLAG_TIMEOUT;
+    while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
+        if ((timeout--) == 0) {
+            return -1;
+        }
+    }
+
+    /* Then Get Byte */
+    data = handle->Instance->RXDR;
+
+    if (last) {
+        /* Disable Address Acknowledge */
+        handle->Instance->CR2 |= I2C_CR2_NACK;
+    }
+
+    return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    int timeout = FLAG_TIMEOUT;
+    uint32_t tmpreg = handle->Instance->CR2;
+#if DEVICE_I2CSLAVE
+    if (obj_s->slave) {
+        return i2c_slave_write(obj, (char *) &data, 1);
+    }
+#endif
+    if (obj_s->pending_start) {
+        obj_s->pending_start = 0;
+        //*  First byte after the start is the address */
+        tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD);
+        if (data & 0x01) {
+             tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN;
+        } else {
+             tmpreg |= I2C_CR2_START;
+             tmpreg &= ~I2C_CR2_RD_WRN;
+        }
+        /*  Disable reload first to use it later */
+        tmpreg &= ~I2C_CR2_RELOAD;
+        /*  Disable Autoend */
+        tmpreg &= ~I2C_CR2_AUTOEND;
+        /* Do not set any transfer size for now */
+        tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
+        /* Set the prepared configuration */
+        handle->Instance->CR2 = tmpreg;
+    } else {
+        /* Set the prepared configuration */
+        tmpreg = handle->Instance->CR2;
+
+        /* Then send data when there's room in the TX fifo */
+        if ((tmpreg & I2C_CR2_RELOAD) != 0) {
+            while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
+                if ((timeout--) == 0) {
+                    DEBUG_PRINTF("timeout in byte_write\r\n");
+                    return 2;
+                }
+            }
+        }
+        /*  Enable reload mode as we don't know how many bytes will eb sent */
+        tmpreg |= I2C_CR2_RELOAD;
+         /*  Set transfer size to 1 */
+        tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
+       /* Set the prepared configuration */
+        handle->Instance->CR2 = tmpreg;
+        /*  Prepare next write */
+        timeout = FLAG_TIMEOUT;
+        while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE)) {
+            if ((timeout--) == 0) {
+                return 2;
+            }
+        }
+        /*  Write byte */
+        handle->Instance->TXDR = data;
+    }
+
+    return 1;
+}
+#endif //I2C_IP_VERSION_V2
+
+/*
+ *  SYNC APIS
+ */
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    int count = I2C_ERROR_BUS_BUSY, ret = 0;
+    uint32_t timeout = 0;
+
+    // Trick to remove compiler warning "left and right operands are identical" in some cases
+    uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+    uint32_t op2 = I2C_LAST_FRAME;
+    if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+        if (stop)
+            obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+        else
+            obj_s->XferOperation = I2C_FIRST_FRAME;
+    } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+        (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+        if (stop)
+            obj_s->XferOperation = I2C_LAST_FRAME;
+        else
+            obj_s->XferOperation = I2C_NEXT_FRAME;
+    }
+
+    obj_s->event = 0;
+
+     /* Activate default IRQ handlers for sync mode
+     * which would be overwritten in async mode
+     */
+    i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
+
+    ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
+
+    if(ret == HAL_OK) {
+        timeout = BYTE_TIMEOUT_US * (length + 1);
+        /*  transfer started : wait completion or timeout */
+        while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
+            wait_us(1);
+        }
+
+        i2c_ev_err_disable(obj);
+
+        if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
+            DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
+            /* re-init IP to try and get back in a working state */
+            i2c_init(obj, obj_s->sda, obj_s->scl);
+        } else {
+            count = length;
+        }
+    } else {
+        DEBUG_PRINTF("ERROR in i2c_read:%d\r\n", ret);
+    }
+
+    return count;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    int count = I2C_ERROR_BUS_BUSY, ret = 0;
+    uint32_t timeout = 0;
+
+    // Trick to remove compiler warning "left and right operands are identical" in some cases
+    uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+    uint32_t op2 = I2C_LAST_FRAME;
+    if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+        if (stop)
+            obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+        else
+            obj_s->XferOperation = I2C_FIRST_FRAME;
+    } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+        (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+        if (stop)
+            obj_s->XferOperation = I2C_LAST_FRAME;
+        else
+            obj_s->XferOperation = I2C_NEXT_FRAME;
+    }
+
+    obj_s->event = 0;
+
+    i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
+
+    ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation); 
+
+    if(ret == HAL_OK) {
+        timeout = BYTE_TIMEOUT_US * (length + 1);
+        /*  transfer started : wait completion or timeout */
+        while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
+            wait_us(1);
+        }
+
+        i2c_ev_err_disable(obj);
+
+        if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
+            DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
+            /* re-init IP to try and get back in a working state */
+            i2c_init(obj, obj_s->sda, obj_s->scl);
+         } else {
+            count = length;
+       }
+    } else {
+        DEBUG_PRINTF("ERROR in i2c_read\r\n");
+    }
+
+    return count;
+}
+
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
+    /* Get object ptr based on handler ptr */
+    i2c_t *obj = get_i2c_obj(hi2c);
+    struct i2c_s *obj_s = I2C_S(obj);
+
+#if DEVICE_I2C_ASYNCH
+    /* Handle potential Tx/Rx use case */
+    if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
+        if (obj_s->stop) {
+            obj_s->XferOperation = I2C_LAST_FRAME;
+        } else {
+            obj_s->XferOperation = I2C_NEXT_FRAME;
+        }
+
+        HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t*)obj->rx_buff.buffer , obj->rx_buff.length, obj_s->XferOperation); 
+    }
+    else
+#endif
+    {
+        /* Set event flag */
+        obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
+    }
+}
+
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){
+    /* Get object ptr based on handler ptr */
+    i2c_t *obj = get_i2c_obj(hi2c);
+    struct i2c_s *obj_s = I2C_S(obj);
+
+    /* Set event flag */
+    obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
+}
+
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
+    /* Get object ptr based on handler ptr */
+    i2c_t *obj = get_i2c_obj(hi2c);
+    struct i2c_s *obj_s = I2C_S(obj);
+#if DEVICE_I2CSLAVE
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    uint32_t address = 0;
+    /*  Store address to handle it after reset */
+    if(obj_s->slave)
+        address = handle->Init.OwnAddress1;
+#endif
+
+    DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
+
+    /* re-init IP to try and get back in a working state */
+    i2c_init(obj, obj_s->sda, obj_s->scl);
+
+#if DEVICE_I2CSLAVE
+    /*  restore slave address */
+    if (address != 0) {
+        obj_s->slave = 1;
+        i2c_slave_address(obj, 0, address, 0);
+    }
+#endif
+
+    /* Keep Set event flag */
+    obj_s->event = I2C_EVENT_ERROR;
+}
+
+#if DEVICE_I2CSLAVE
+/* SLAVE API FUNCTIONS */
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    // I2C configuration
+    handle->Init.OwnAddress1     = address;
+    HAL_I2C_Init(handle);
+
+    i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
+
+    HAL_I2C_EnableListen_IT(handle);
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    if (enable_slave) {
+        obj_s->slave = 1;
+        HAL_I2C_EnableListen_IT(handle);
+    } else {
+        obj_s->slave = 0;
+        HAL_I2C_DisableListen_IT(handle);
+    }
+}
+
+// See I2CSlave.h
+#define NoData         0 // the slave has not been addressed
+#define ReadAddressed  1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral   2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
+    /* Get object ptr based on handler ptr */
+    i2c_t *obj = get_i2c_obj(hi2c);
+    struct i2c_s *obj_s = I2C_S(obj);
+
+    /*  Transfer direction in HAL is from Master point of view */
+    if(TransferDirection == I2C_DIRECTION_RECEIVE) {
+        obj_s->pending_slave_tx_master_rx = 1;
+    }
+
+    if(TransferDirection == I2C_DIRECTION_TRANSMIT) {
+        obj_s->pending_slave_rx_maxter_tx = 1;
+    }
+}
+
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){
+    /* Get object ptr based on handler ptr */
+    i2c_t *obj = get_i2c_obj(I2cHandle);
+    struct i2c_s *obj_s = I2C_S(obj);
+    obj_s->pending_slave_tx_master_rx = 0;
+}
+
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){
+    /* Get object ptr based on handler ptr */
+    i2c_t *obj = get_i2c_obj(I2cHandle);
+    struct i2c_s *obj_s = I2C_S(obj);
+    obj_s->pending_slave_rx_maxter_tx = 0;
+}
+
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+    /* restart listening for master requests */
+    HAL_I2C_EnableListen_IT(hi2c);
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+
+    struct i2c_s *obj_s = I2C_S(obj);
+    int retValue = NoData;
+
+     if(obj_s->pending_slave_rx_maxter_tx) {
+         retValue = WriteAddressed;
+     }
+
+     if(obj_s->pending_slave_tx_master_rx) {
+            retValue = ReadAddressed;
+     }
+
+    return (retValue);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    int count = 0;
+    int ret = 0;
+    uint32_t timeout = 0;
+
+    /*  Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
+    ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
+
+    if(ret == HAL_OK) {
+        timeout = BYTE_TIMEOUT_US * (length + 1);
+        while(obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
+            wait_us(1);
+        }
+
+         if(timeout != 0) {
+             count = length;
+         } else {
+             DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
+         }
+    }
+    return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+    int count = 0;
+    int ret = 0;
+    uint32_t timeout = 0;
+
+    /*  Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
+    ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
+
+    if(ret == HAL_OK) {
+        timeout = BYTE_TIMEOUT_US * (length + 1);
+        while(obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
+            wait_us(1);
+        }
+
+         if(timeout != 0) {
+             count = length;
+         } else {
+             DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
+         }
+    }
+
+    return count;
+}
+#endif // DEVICE_I2CSLAVE
+
+#if DEVICE_I2C_ASYNCH
+/* ASYNCH MASTER API FUNCTIONS */
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
+    /* Get object ptr based on handler ptr */
+    i2c_t *obj = get_i2c_obj(hi2c);
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    /* Disable IT. Not always done before calling macro */
+    __HAL_I2C_DISABLE_IT(handle, I2C_IT_ALL);
+    i2c_ev_err_disable(obj);
+
+    /* Set event flag */
+    obj_s->event = I2C_EVENT_ERROR;
+}
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) {
+
+    // TODO: DMA usage is currently ignored by this way
+    (void) hint;
+
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    /* Update object */
+    obj->tx_buff.buffer = (void *)tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = 8;
+
+    obj->rx_buff.buffer = (void *)rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = SIZE_MAX;
+    obj->rx_buff.width = 8;
+
+    obj_s->available_events = event;
+    obj_s->event = 0;
+    obj_s->address = address;
+    obj_s->stop = stop;
+
+    i2c_ev_err_enable(obj, handler);
+
+    /* Set operation step depending if stop sending required or not */
+    if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
+        // Trick to remove compiler warning "left and right operands are identical" in some cases
+        uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+        uint32_t op2 = I2C_LAST_FRAME;
+        if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+            if (stop)
+                obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+            else
+                obj_s->XferOperation = I2C_FIRST_FRAME;
+        } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+            (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+            if (stop)
+                obj_s->XferOperation = I2C_LAST_FRAME;
+            else
+                obj_s->XferOperation = I2C_NEXT_FRAME;
+        }
+
+        if (tx_length > 0) {
+            HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, obj_s->XferOperation);
+        }
+        if (rx_length > 0) {
+            HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t*)rx, rx_length, obj_s->XferOperation);
+        }
+    }
+    else if (tx_length && rx_length) {
+        /* Two steps operation, don't modify XferOperation, keep it for next step */
+        // Trick to remove compiler warning "left and right operands are identical" in some cases
+        uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+        uint32_t op2 = I2C_LAST_FRAME;
+        if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+                HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME);
+        } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+            (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+                HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_NEXT_FRAME);
+        }
+    }
+}
+
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
+
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    HAL_I2C_EV_IRQHandler(handle);
+    HAL_I2C_ER_IRQHandler(handle);
+
+     /*  Return I2C event status */
+    return (obj_s->event & obj_s->available_events);
+}
+
+uint8_t i2c_active(i2c_t *obj) {
+
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    if (handle->State == HAL_I2C_STATE_READY) {
+        return 0;
+    }
+    else {
+        return 1;
+    }
+}
+
+void i2c_abort_asynch(i2c_t *obj) {
+
+    struct i2c_s *obj_s = I2C_S(obj);
+    I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+    /* Abort HAL requires DevAddress, but is not used. Use Dummy */
+    uint16_t Dummy_DevAddress = 0x00;
+
+    HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress);
+}
+
+#endif // DEVICE_I2C_ASYNCH
+
+#endif // DEVICE_I2C
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/lp_ticker.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/lp_ticker.c
new file mode 100755
index 0000000..689833f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/lp_ticker.c
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "device.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "ticker_api.h"
+#include "lp_ticker_api.h"
+#include "rtc_api.h"
+#include "rtc_api_hal.h"
+
+static uint8_t lp_ticker_inited = 0;
+
+void lp_ticker_init(void)
+{
+    if (lp_ticker_inited) return;
+    lp_ticker_inited = 1;
+
+    rtc_init();
+    rtc_set_irq_handler((uint32_t) lp_ticker_irq_handler);
+}
+
+uint32_t lp_ticker_read(void)
+{
+    uint32_t usecs = 0;
+    time_t time = 0;
+
+    lp_ticker_init();
+
+    do {
+        time = rtc_read();
+        usecs = rtc_read_subseconds();
+    } while (time != rtc_read());
+
+    return (time * 1000000) + usecs;
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    uint32_t delta;
+
+    delta = timestamp - lp_ticker_read();
+    rtc_set_wake_up_timer(delta);
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+    NVIC_SetPendingIRQ(RTC_WKUP_IRQn);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    rtc_deactivate_wake_up_timer();
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/mbed_overrides.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/mbed_overrides.c
new file mode 100755
index 0000000..fbdccb8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/mbed_overrides.c
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cmsis.h"
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init()
+{
+    // Update the SystemCoreClock variable.
+    SystemCoreClockUpdate();
+    HAL_Init();
+
+#if TARGET_STM32F7
+    // Enable CPU L1-Cache
+    SCB_EnableICache();
+    SCB_EnableDCache();
+#endif /* TARGET_STM32F7 */
+
+    /* Configure the System clock source, PLL Multiplier and Divider factors,
+       AHB/APBx prescalers and Flash settings */
+    SetSysClock();
+    SystemCoreClockUpdate();
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/mbed_rtx.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/mbed_rtx.h
new file mode 100755
index 0000000..caf605e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/mbed_rtx.h
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_MBED_RTX_H
+#define MBED_MBED_RTX_H
+
+#ifndef INITIAL_SP
+
+#if (defined(TARGET_STM32F051R8) ||\
+     defined(TARGET_STM32F100RB) ||\
+     defined(TARGET_STM32L031K6) ||\
+     defined(TARGET_STM32L053C8) ||\
+     defined(TARGET_STM32L053R8))
+#define INITIAL_SP              (0x20002000UL)
+
+#elif (defined(TARGET_STM32F303K8) ||\
+       defined(TARGET_STM32F334C8) ||\
+       defined(TARGET_STM32F334R8))
+#define INITIAL_SP              (0x20003000UL)
+
+#elif (defined(TARGET_STM32F070RB) ||\
+       defined(TARGET_STM32F072RB) ||\
+       defined(TARGET_STM32F302R8))
+#define INITIAL_SP              (0x20004000UL)
+
+#elif (defined(TARGET_STM32F103RB) ||\
+       defined(TARGET_STM32F103C8) ||\
+       defined(TARGET_STM32L072CZ) ||\
+       defined(TARGET_STM32L073RZ))
+#define INITIAL_SP              (0x20005000UL)
+
+#elif (defined(TARGET_STM32F091RC) ||\
+       defined(TARGET_STM32F410RB) ||\
+       defined(TARGET_STM32L151CC) ||\
+       defined(TARGET_STM32L151RC) ||\
+       defined(TARGET_STM32L152RC))
+#define INITIAL_SP              (0x20008000UL)
+
+#elif defined(TARGET_STM32F303VC)
+#define INITIAL_SP              (0x2000A000UL)
+
+#elif defined(TARGET_STM32L432KC)
+#define INITIAL_SP              (0x20010000UL)
+
+#elif (defined(TARGET_STM32F303RE) ||\
+       defined(TARGET_STM32F303ZE) ||\
+       defined(TARGET_STM32F401VC))
+#define INITIAL_SP              (0x20010000UL)
+
+#elif defined(TARGET_STM32L152RE)
+#define INITIAL_SP              (0x20014000UL)
+
+#elif (defined(TARGET_STM32F401RE) ||\
+       defined(TARGET_STM32L475VG) ||\
+       defined(TARGET_STM32L476RG) ||\
+       defined(TARGET_STM32L476JG) ||\
+       defined(TARGET_STM32L476VG) ||\
+       defined(TARGET_STM32L486RG))
+#define INITIAL_SP              (0x20018000UL)
+
+#elif (defined(TARGET_STM32F207ZG) ||\
+       defined(TARGET_STM32F405RG) ||\
+       defined(TARGET_STM32F407VG) ||\
+       defined(TARGET_STM32F411RE) ||\
+       defined(TARGET_STM32F446RE) ||\
+       defined(TARGET_STM32F446VE) ||\
+       defined(TARGET_STM32F446ZE))
+#define INITIAL_SP              (0x20020000UL)
+
+#elif (defined(TARGET_STM32F429ZI) ||\
+       defined(TARGET_STM32F437VG) ||\
+       defined(TARGET_STM32F439ZI))
+#define INITIAL_SP              (0x20030000UL)
+
+#elif defined(TARGET_STM32F412ZG)
+#define INITIAL_SP              (0x20040000UL)
+
+#elif (defined(TARGET_STM32F413ZH) ||\
+       defined(TARGET_STM32F469NI) ||\
+       defined(TARGET_STM32F746NG) ||\
+       defined(TARGET_STM32F746ZG) ||\
+       defined(TARGET_STM32F756ZG))
+#define INITIAL_SP              (0x20050000UL)
+
+#elif (defined(TARGET_STM32F767ZI) ||\
+       defined(TARGET_STM32F769NI))
+#define INITIAL_SP              (0x20080000UL)
+
+#else
+#error "INITIAL_SP is not defined for this target in the mbed_rtx.h file"
+#endif
+
+#endif // INITIAL_SP
+
+#endif  // MBED_MBED_RTX_H
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/nvic_addr.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/nvic_addr.h
new file mode 100755
index 0000000..023b5fc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/nvic_addr.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef NVIC_ADDR_H
+#define NVIC_ADDR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+    #pragma section=".intvec"
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)__section_begin(".intvec"))
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+    extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__GNUC__)
+    extern uint32_t g_pfnVectors[];
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)g_pfnVectors)
+#else
+    #error "Flash vector address not set for this toolchain"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/pinmap.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/pinmap.c
new file mode 100755
index 0000000..5b9a3fa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/pinmap.c
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+#include "pin_device.h"
+
+extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
+
+const uint32_t ll_pin_defines[16] = {
+    LL_GPIO_PIN_0,
+    LL_GPIO_PIN_1,
+    LL_GPIO_PIN_2,
+    LL_GPIO_PIN_3,
+    LL_GPIO_PIN_4,
+    LL_GPIO_PIN_5,
+    LL_GPIO_PIN_6,
+    LL_GPIO_PIN_7,
+    LL_GPIO_PIN_8,
+    LL_GPIO_PIN_9,
+    LL_GPIO_PIN_10,
+    LL_GPIO_PIN_11,
+    LL_GPIO_PIN_12,
+    LL_GPIO_PIN_13,
+    LL_GPIO_PIN_14,
+    LL_GPIO_PIN_15
+};
+
+/**
+ * Configure pin (mode, speed, output type and pull-up/pull-down)
+ */
+void pin_function(PinName pin, int data)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+
+    // Get the pin informations
+    uint32_t mode  = STM_PIN_FUNCTION(data);
+    uint32_t afnum = STM_PIN_AFNUM(data);
+    uint32_t port = STM_PORT(pin);
+    uint32_t ll_pin  = ll_pin_defines[STM_PIN(pin)];
+    uint32_t ll_mode = 0;
+
+    // Enable GPIO clock
+    GPIO_TypeDef *gpio = Set_GPIO_Clock(port);
+
+    /*  Set default speed to high.
+     *  For most families there are dedicated registers so it is
+     *  not so important, register can be set at any time.
+     *  But for families like F1, speed only applies to output.
+     */
+#if defined (TARGET_STM32F1)
+if (mode == STM_PIN_OUTPUT) {
+#endif
+    LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH);
+#if defined (TARGET_STM32F1)
+}
+#endif
+
+    switch (mode) {
+        case STM_PIN_INPUT:
+            ll_mode = LL_GPIO_MODE_INPUT;
+            break;
+        case STM_PIN_OUTPUT:
+            ll_mode = LL_GPIO_MODE_OUTPUT;
+            break;
+        case STM_PIN_ALTERNATE:
+            ll_mode = LL_GPIO_MODE_ALTERNATE;
+            // In case of ALT function, also set he afnum
+           stm_pin_SetAFPin(gpio, pin, afnum);
+            break;
+        case STM_PIN_ANALOG:
+            ll_mode = LL_GPIO_MODE_ANALOG;
+            break;
+        default:
+            MBED_ASSERT(0);
+            break;
+    }
+    LL_GPIO_SetPinMode(gpio, ll_pin, ll_mode);
+
+#if defined(GPIO_ASCR_ASC0)
+    /*  For families where Analog Control ASC0 register is present */
+    if (STM_PIN_ANALOG_CONTROL(data)) {
+        LL_GPIO_EnablePinAnalogControl(gpio, ll_pin);
+    } else {
+        LL_GPIO_DisablePinAnalogControl(gpio, ll_pin);
+    }
+#endif
+
+    /*  For now by default use Speed HIGH for output or alt modes */
+    if ((mode == STM_PIN_OUTPUT) ||(mode == STM_PIN_ALTERNATE)) {
+    if (STM_PIN_OD(data)) {
+            LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN);
+    } else {
+            LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_PUSHPULL);
+    }
+    }
+
+    stm_pin_PullConfig(gpio, ll_pin, STM_PIN_PUPD(data));
+
+    stm_pin_DisconnectDebug(pin);
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+
+    uint32_t port_index = STM_PORT(pin);
+    uint32_t ll_pin  = ll_pin_defines[STM_PIN(pin)];
+    // Enable GPIO clock
+    GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
+    uint32_t function = LL_GPIO_GetPinMode(gpio, ll_pin);
+
+    if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE))
+    {
+        if ((mode == OpenDrainNoPull) || (mode == OpenDrainPullUp) || (mode == OpenDrainPullDown)) {
+            LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN);
+        } else {
+            LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_PUSHPULL);
+        }
+    }
+
+    if ((mode == OpenDrainPullUp) || (mode == PullUp)) {
+        stm_pin_PullConfig(gpio, ll_pin, GPIO_PULLUP);
+    } else if ((mode == OpenDrainPullDown) || (mode == PullDown)) {
+        stm_pin_PullConfig(gpio, ll_pin, GPIO_PULLDOWN);
+    } else {
+        stm_pin_PullConfig(gpio, ll_pin, GPIO_NOPULL);
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/port_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/port_api.c
new file mode 100755
index 0000000..04c7c8a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/port_api.c
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
+
+// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
+// low nibble  = pin number
+PinName port_pin(PortName port, int pin_n)
+{
+    return (PinName)(pin_n + (port << 4));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    uint32_t port_index = (uint32_t)port;
+
+    // Enable GPIO clock
+    GPIO_TypeDef *gpio =  Set_GPIO_Clock(port_index);
+
+    // Fill PORT object structure for future use
+    obj->port      = port;
+    obj->mask      = mask;
+    obj->direction = dir;
+    obj->reg_in    = &gpio->IDR;
+    obj->reg_out   = &gpio->ODR;
+
+    port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    uint32_t i;
+    obj->direction = dir;
+    for (i = 0; i < 16; i++) { // Process all pins
+        if (obj->mask & (1 << i)) { // If the pin is used
+            if (dir == PIN_OUTPUT) {
+                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+            } else { // PIN_INPUT
+                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+            }
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+    for (i = 0; i < 16; i++) { // Process all pins
+        if (obj->mask & (1 << i)) { // If the pin is used
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj)
+{
+    if (obj->direction == PIN_OUTPUT) {
+        return (*obj->reg_out & obj->mask);
+    } else { // PIN_INPUT
+        return (*obj->reg_in & obj->mask);
+    }
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/pwmout_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/pwmout_api.c
new file mode 100755
index 0000000..552fde0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/pwmout_api.c
@@ -0,0 +1,343 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "pwmout_device.h"
+
+static TIM_HandleTypeDef TimHandle;
+
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+    // Get the peripheral name from the pin and assign it to the object
+    obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    MBED_ASSERT(obj->pwm != (PWMName)NC);
+
+    // Get the functions (timer channel, (non)inverted) from the pin and assign it to the object
+    uint32_t function = pinmap_function(pin, PinMap_PWM);
+    MBED_ASSERT(function != (uint32_t)NC);
+    obj->channel = STM_PIN_CHANNEL(function);
+    obj->inverted = STM_PIN_INVERTED(function);
+
+    // Enable TIM clock
+#if defined(TIM1_BASE)
+    if (obj->pwm == PWM_1){
+        __HAL_RCC_TIM1_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM2_BASE)
+    if (obj->pwm == PWM_2) {
+        __HAL_RCC_TIM2_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM3_BASE)
+    if (obj->pwm == PWM_3) {
+        __HAL_RCC_TIM3_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM4_BASE)
+    if (obj->pwm == PWM_4) {
+        __HAL_RCC_TIM4_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM5_BASE)
+    if (obj->pwm == PWM_5) {
+        __HAL_RCC_TIM5_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM8_BASE)
+    if (obj->pwm == PWM_8) {
+        __HAL_RCC_TIM8_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM9_BASE)
+    if (obj->pwm == PWM_9) {
+        __HAL_RCC_TIM9_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM10_BASE)
+    if (obj->pwm == PWM_10) {
+        __HAL_RCC_TIM10_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM11_BASE)
+    if (obj->pwm == PWM_11) {
+        __HAL_RCC_TIM11_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM12_BASE)
+    if (obj->pwm == PWM_12) {
+        __HAL_RCC_TIM12_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM13_BASE)
+    if (obj->pwm == PWM_13) {
+        __HAL_RCC_TIM13_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM14_BASE)
+    if (obj->pwm == PWM_14) {
+        __HAL_RCC_TIM14_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM15_BASE)
+    if (obj->pwm == PWM_15) {
+        __HAL_RCC_TIM15_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM16_BASE)
+    if (obj->pwm == PWM_16) {
+        __HAL_RCC_TIM16_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM17_BASE)
+    if (obj->pwm == PWM_17) {
+        __HAL_RCC_TIM17_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM18_BASE)
+    if (obj->pwm == PWM_18) {
+        __HAL_RCC_TIM18_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM19_BASE)
+    if (obj->pwm == PWM_19) {
+        __HAL_RCC_TIM19_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM20_BASE)
+    if (obj->pwm == PWM_20) {
+        __HAL_RCC_TIM20_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM21_BASE)
+    if (obj->pwm == PWM_21) {
+        __HAL_RCC_TIM21_CLK_ENABLE();
+    }
+#endif
+#if defined(TIM22_BASE)
+    if (obj->pwm == PWM_22) {
+        __HAL_RCC_TIM22_CLK_ENABLE();
+    }
+#endif
+    // Configure GPIO
+    pinmap_pinout(pin, PinMap_PWM);
+
+    obj->pin = pin;
+    obj->period = 0;
+    obj->pulse = 0;
+    obj->prescaler = 1;
+
+    pwmout_period_us(obj, 20000); // 20 ms per default
+}
+
+void pwmout_free(pwmout_t* obj)
+{
+    // Configure GPIO
+    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void pwmout_write(pwmout_t* obj, float value)
+{
+    TIM_OC_InitTypeDef sConfig;
+    int channel = 0;
+
+    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+    if (value < (float)0.0) {
+        value = 0.0;
+    } else if (value > (float)1.0) {
+        value = 1.0;
+    }
+
+    obj->pulse = (uint32_t)((float)obj->period * value);
+
+    // Configure channels
+    sConfig.OCMode       = TIM_OCMODE_PWM1;
+    sConfig.Pulse        = obj->pulse / obj->prescaler;
+    sConfig.OCPolarity   = TIM_OCPOLARITY_HIGH;
+    sConfig.OCFastMode   = TIM_OCFAST_DISABLE;
+#if defined(TIM_OCIDLESTATE_RESET)
+    sConfig.OCIdleState  = TIM_OCIDLESTATE_RESET;
+#endif
+#if defined(TIM_OCNIDLESTATE_RESET)
+    sConfig.OCNPolarity  = TIM_OCNPOLARITY_HIGH;
+    sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+#endif
+
+    switch (obj->channel) {
+        case 1:
+            channel = TIM_CHANNEL_1;
+            break;
+        case 2:
+            channel = TIM_CHANNEL_2;
+            break;
+        case 3:
+            channel = TIM_CHANNEL_3;
+            break;
+        case 4:
+            channel = TIM_CHANNEL_4;
+            break;
+        default:
+            return;
+    }
+
+    if (HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel) != HAL_OK) {
+        error("Cannot initialize PWM\n");
+    }
+
+#if !defined(PWMOUT_INVERTED_NOT_SUPPORTED)
+    if (obj->inverted) {
+        HAL_TIMEx_PWMN_Start(&TimHandle, channel);
+    } else
+#endif
+    {
+        HAL_TIM_PWM_Start(&TimHandle, channel);
+    }
+}
+
+float pwmout_read(pwmout_t* obj)
+{
+    float value = 0;
+    if (obj->period > 0) {
+        value = (float)(obj->pulse) / (float)(obj->period);
+    }
+    return ((value > (float)1.0) ? (float)(1.0) : (value));
+}
+
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+    pwmout_period_us(obj, ms * 1000);
+}
+
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    uint32_t PclkFreq = 0;
+    uint32_t APBxCLKDivider = RCC_HCLK_DIV1;
+    float dc = pwmout_read(obj);
+    uint8_t i = 0;
+
+    __HAL_TIM_DISABLE(&TimHandle);
+
+    // Get clock configuration
+    // Note: PclkFreq contains here the Latency (not used after)
+    HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq);
+
+    /*  Parse the pwm / apb mapping table to find the right entry */
+    while(pwm_apb_map_table[i].pwm != obj->pwm) {
+        i++;
+    }
+
+    if(pwm_apb_map_table[i].pwm == 0)
+        error("Unknown PWM instance");
+
+    if(pwm_apb_map_table[i].pwmoutApb == PWMOUT_ON_APB1) {
+        PclkFreq = HAL_RCC_GetPCLK1Freq();
+        APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider;
+    } else {
+#if !defined(PWMOUT_APB2_NOT_SUPPORTED)
+        PclkFreq = HAL_RCC_GetPCLK2Freq();
+        APBxCLKDivider = RCC_ClkInitStruct.APB2CLKDivider;
+#endif
+    }
+
+
+    /* By default use, 1us as SW pre-scaler */
+    obj->prescaler = 1;
+    // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx
+    if (APBxCLKDivider == RCC_HCLK_DIV1) {
+        TimHandle.Init.Prescaler = (((PclkFreq) / 1000000)) - 1; // 1 us tick
+    } else {
+        TimHandle.Init.Prescaler = (((PclkFreq * 2) / 1000000)) - 1; // 1 us tick
+    }
+    TimHandle.Init.Period = (us - 1);
+
+    /*  In case period or pre-scalers are out of range, loop-in to get valid values */
+    while ((TimHandle.Init.Period > 0xFFFF) || (TimHandle.Init.Prescaler > 0xFFFF)) {
+        obj->prescaler = obj->prescaler * 2;
+        if (APBxCLKDivider == RCC_HCLK_DIV1) {
+          TimHandle.Init.Prescaler = (((PclkFreq) / 1000000) * obj->prescaler) - 1;
+        } else {
+          TimHandle.Init.Prescaler = (((PclkFreq * 2) / 1000000) * obj->prescaler) - 1;
+        }
+        TimHandle.Init.Period = (us - 1) / obj->prescaler;
+        /*  Period decreases and prescaler increases over loops, so check for
+         *  possible out of range cases */
+        if ((TimHandle.Init.Period < 0xFFFF) && (TimHandle.Init.Prescaler > 0xFFFF)) {
+            error("Cannot initialize PWM\n");
+            break;
+        }
+    }
+
+    TimHandle.Init.ClockDivision = 0;
+    TimHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
+
+    if (HAL_TIM_PWM_Init(&TimHandle) != HAL_OK) {
+        error("Cannot initialize PWM\n");
+    }
+
+    // Save for future use
+    obj->period = us;
+
+    // Set duty cycle again
+    pwmout_write(obj, dc);
+
+    __HAL_TIM_ENABLE(&TimHandle);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+    float value = (float)us / (float)obj->period;
+    pwmout_write(obj, value);
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/rtc_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/rtc_api.c
new file mode 100755
index 0000000..23f7625
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/rtc_api.c
@@ -0,0 +1,338 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#if DEVICE_RTC
+
+#include "rtc_api.h"
+#include "rtc_api_hal.h"
+#include "mbed_error.h"
+#include "mbed_mktime.h"
+
+static RTC_HandleTypeDef RtcHandle;
+
+#if RTC_LSI
+#define RTC_CLOCK LSI_VALUE
+#else
+#define RTC_CLOCK LSE_VALUE
+#endif
+
+#if DEVICE_LOWPOWERTIMER
+#define RTC_ASYNCH_PREDIV ((RTC_CLOCK - 1) / 0x8000)
+#define RTC_SYNCH_PREDIV  (RTC_CLOCK / (RTC_ASYNCH_PREDIV + 1) - 1)
+#else
+#define RTC_ASYNCH_PREDIV (0x007F)
+#define RTC_SYNCH_PREDIV  (RTC_CLOCK / (RTC_ASYNCH_PREDIV + 1) - 1)
+#endif
+
+#if DEVICE_LOWPOWERTIMER
+static void (*irq_handler)(void);
+static void RTC_IRQHandler(void);
+#endif
+
+void rtc_init(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
+
+    RtcHandle.Instance = RTC;
+    RtcHandle.State = HAL_RTC_STATE_RESET;
+
+#if !RTC_LSI
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON;
+    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+    } else {
+        error("Cannot initialize RTC with LSE\n");
+    }
+
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+    PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        error("PeriphClkInitStruct RTC failed with LSE\n");
+    }
+#else /* !RTC_LSI */
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+
+    // Enable LSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+    RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        error("Cannot initialize RTC with LSI\n");
+    }
+
+    __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+    __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+    PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        error("PeriphClkInitStruct RTC failed with LSI\n");
+    }
+#endif /* !RTC_LSI */
+
+    // Enable RTC
+    __HAL_RCC_RTC_ENABLE();
+
+#if TARGET_STM32F1
+    RtcHandle.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
+#else /* TARGET_STM32F1 */
+    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
+    RtcHandle.Init.AsynchPrediv   = RTC_ASYNCH_PREDIV;
+    RtcHandle.Init.SynchPrediv    = RTC_SYNCH_PREDIV;
+    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
+    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
+#endif /* TARGET_STM32F1 */
+
+    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+        error("RTC error: RTC initialization failed.");
+    }
+
+#if DEVICE_LOWPOWERTIMER
+
+#if !RTC_LSI
+    if (!rtc_isenabled())
+#endif /* !RTC_LSI */
+    {
+        rtc_write(0);
+    }
+
+    NVIC_ClearPendingIRQ(RTC_WKUP_IRQn);
+    NVIC_DisableIRQ(RTC_WKUP_IRQn);
+    NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler);
+    NVIC_EnableIRQ(RTC_WKUP_IRQn);
+
+#endif /* DEVICE_LOWPOWERTIMER */
+}
+
+void rtc_free(void)
+{
+#if RTC_LSI
+    // Enable Power clock
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
+
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+
+    // Disable access to Backup domain
+    HAL_PWR_DisableBkUpAccess();
+#endif
+
+    // Disable LSI and LSE clocks
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
+    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
+    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+}
+
+/*
+ ST RTC_DateTypeDef structure
+   WeekDay 1=monday, 2=tuesday, ..., 7=sunday
+   Month   0x1=january, 0x2=february, ..., 0x12=december
+   Date    day of the month 1-31
+   Year    year 0-99
+
+ ST RTC_TimeTypeDef structure
+  Hours           0-12 if the RTC_HourFormat_12 is selected during init
+                  0-23 if the RTC_HourFormat_24 is selected during init
+  Minutes         0-59
+  Seconds         0-59
+  TimeFormat      RTC_HOURFORMAT12_AM/RTC_HOURFORMAT12_PM
+  SubSeconds      time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity
+  SecondFraction  range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+  DayLightSaving  RTC_DAYLIGHTSAVING_SUB1H/RTC_DAYLIGHTSAVING_ADD1H/RTC_DAYLIGHTSAVING_NONE
+  StoreOperation  RTC_STOREOPERATION_RESET/RTC_STOREOPERATION_SET
+
+ struct tm
+   tm_sec      seconds after the minute 0-61
+   tm_min      minutes after the hour 0-59
+   tm_hour     hours since midnight 0-23
+   tm_mday     day of the month 1-31
+   tm_mon      months since January 0-11
+   tm_year     years since 1900
+   tm_wday     days since Sunday 0-6
+   tm_yday     days since January 1 0-365
+   tm_isdst    Daylight Saving Time flag
+*/
+
+/*
+Information about STM32F0, STM32F2, STM32F3, STM32F4, STM32F7, STM32L0, STM32L1, STM32L4:
+BCD format is used to store the date in the RTC. The year is store on 2 * 4 bits.
+Because the first year is reserved to see if the RTC is init, the supposed range is 01-99.
+1st point is to cover the standard range from 1970 to 2038 (limited by the 32 bits of time_t).
+2nd point is to keep the year 1970 and the leap years synchronized.
+
+So by moving it 68 years forward from 1970, it become 1969-2067 which include 1970-2038.
+68 is also a multiple of 4 so it let the leap year synchronized.
+
+Information about STM32F1:
+32bit register is used (no BCD format) for the seconds and a software structure to store dates.
+It is then not a problem to not use shifts.
+*/
+
+time_t rtc_read(void)
+{
+    RTC_DateTypeDef dateStruct = {0};
+    RTC_TimeTypeDef timeStruct = {0};
+    struct tm timeinfo;
+
+    RtcHandle.Instance = RTC;
+
+    // Read actual date and time
+    // Warning: the time must be read first!
+    HAL_RTC_GetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN);
+    HAL_RTC_GetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN);
+
+    // Setup a tm structure based on the RTC
+    /* tm_wday information is ignored by mktime */
+    timeinfo.tm_mon  = dateStruct.Month - 1;
+    timeinfo.tm_mday = dateStruct.Date;
+    timeinfo.tm_year = dateStruct.Year + 68;
+    timeinfo.tm_hour = timeStruct.Hours;
+    timeinfo.tm_min  = timeStruct.Minutes;
+    timeinfo.tm_sec  = timeStruct.Seconds;
+    // Daylight Saving Time information is not available
+    timeinfo.tm_isdst  = -1;
+
+    // Convert to timestamp
+    time_t t = _rtc_mktime(&timeinfo);
+
+    return t;
+}
+
+void rtc_write(time_t t)
+{
+    RTC_DateTypeDef dateStruct = {0};
+    RTC_TimeTypeDef timeStruct = {0};
+
+    RtcHandle.Instance = RTC;
+
+    // Convert the time into a tm
+    struct tm timeinfo;
+    if (_rtc_localtime(t, &timeinfo) == false) {
+        return;
+    }
+
+    // Fill RTC structures
+    if (timeinfo.tm_wday == 0) {
+        dateStruct.WeekDay    = 7;
+    } else {
+        dateStruct.WeekDay    = timeinfo.tm_wday;
+    }
+    dateStruct.Month          = timeinfo.tm_mon + 1;
+    dateStruct.Date           = timeinfo.tm_mday;
+    dateStruct.Year           = timeinfo.tm_year - 68;
+    timeStruct.Hours          = timeinfo.tm_hour;
+    timeStruct.Minutes        = timeinfo.tm_min;
+    timeStruct.Seconds        = timeinfo.tm_sec;
+
+#if !(TARGET_STM32F1)
+    timeStruct.TimeFormat     = RTC_HOURFORMAT_24;
+    timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+    timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
+#endif /* TARGET_STM32F1 */
+
+    // Change the RTC current date/time
+    HAL_RTC_SetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN);
+    HAL_RTC_SetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN);
+}
+
+int rtc_isenabled(void)
+{
+#if !(TARGET_STM32F1)
+    return ( ((RTC->ISR & RTC_ISR_INITS) ==  RTC_ISR_INITS) && ((RTC->ISR & RTC_ISR_RSF) ==  RTC_ISR_RSF) );
+#else /* TARGET_STM32F1 */
+    return ((RTC->CRL & RTC_CRL_RSF) ==  RTC_CRL_RSF);
+#endif /* TARGET_STM32F1 */
+}
+
+#if DEVICE_LOWPOWERTIMER
+
+static void RTC_IRQHandler(void)
+{
+    /*  Update HAL state */
+    HAL_RTCEx_WakeUpTimerIRQHandler(&RtcHandle);
+    /* In case of registered handler, call it. */
+    if (irq_handler) {
+        irq_handler();
+    }
+}
+
+void rtc_set_irq_handler(uint32_t handler)
+{
+    irq_handler = (void (*)(void))handler;
+}
+
+uint32_t rtc_read_subseconds(void)
+{
+    return 1000000.f * ((double)(RTC_SYNCH_PREDIV - RTC->SSR) / (RTC_SYNCH_PREDIV + 1));
+}
+
+void rtc_set_wake_up_timer(uint32_t delta)
+{
+    uint32_t wake_up_counter = delta / (2000000 / RTC_CLOCK);
+
+    if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, wake_up_counter,
+                                    RTC_WAKEUPCLOCK_RTCCLK_DIV2) != HAL_OK) {
+        error("Set wake up timer failed\n");
+    }
+}
+
+void rtc_deactivate_wake_up_timer(void)
+{
+    HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle);
+}
+
+void rtc_synchronize(void)
+{
+    HAL_RTC_WaitForSynchro(&RtcHandle);
+}
+#endif /* DEVICE_LOWPOWERTIMER */
+
+#endif /* DEVICE_RTC */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/rtc_api_hal.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/rtc_api_hal.h
new file mode 100755
index 0000000..14a3454
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/rtc_api_hal.h
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+*******************************************************************************
+* Copyright (c) 2016, STMicroelectronics
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+*    this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+*    this list of conditions and the following disclaimer in the documentation
+*    and/or other materials provided with the distribution.
+* 3. Neither the name of STMicroelectronics nor the names of its contributors
+*    may be used to endorse or promote products derived from this software
+*    without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+*/
+
+#ifndef MBED_RTC_API_HAL_H
+#define MBED_RTC_API_HAL_H
+
+#include <stdint.h>
+#include "rtc_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Extend rtc_api.h
+ */
+
+/** Set the given function as handler of wakeup timer event.
+ *
+ * @param handler    The function to set as handler
+ */
+void rtc_set_irq_handler(uint32_t handler);
+
+/** Read the subsecond register.
+ *
+ * @return The remaining time as microseconds (0-999999)
+ */
+uint32_t rtc_read_subseconds(void);
+
+/** Program a wake up timer event in delta microseconds.
+ *
+ * @param delta    The time to wait
+ */
+void rtc_set_wake_up_timer(uint32_t delta);
+
+/** Disable the wake up timer event.
+ *
+ * The wake up timer use auto reload, you have to deactivate it manually.
+ */
+void rtc_deactivate_wake_up_timer(void);
+
+/** Synchronise the RTC shadow registers.
+ *
+ * Must be called after a deepsleep.
+ */
+void rtc_synchronize(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/serial_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/serial_api.c
new file mode 100755
index 0000000..5d6167b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/serial_api.c
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "serial_api.h"
+#include "serial_api_hal.h"
+#include "PeripheralPins.h"
+
+#if DEVICE_SERIAL
+
+void init_uart(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    huart->Instance = (USART_TypeDef *)(obj_s->uart);
+
+    huart->Init.BaudRate     = obj_s->baudrate;
+    huart->Init.WordLength   = obj_s->databits;
+    huart->Init.StopBits     = obj_s->stopbits;
+    huart->Init.Parity       = obj_s->parity;
+#if DEVICE_SERIAL_FC
+    huart->Init.HwFlowCtl    = obj_s->hw_flow_ctl;
+#else
+    huart->Init.HwFlowCtl    = UART_HWCONTROL_NONE;
+#endif
+    huart->Init.OverSampling = UART_OVERSAMPLING_16;
+    huart->TxXferCount       = 0;
+    huart->TxXferSize        = 0;
+    huart->RxXferCount       = 0;
+    huart->RxXferSize        = 0;
+
+    if (obj_s->pin_rx == NC) {
+        huart->Init.Mode = UART_MODE_TX;
+    } else if (obj_s->pin_tx == NC) {
+        huart->Init.Mode = UART_MODE_RX;
+    } else {
+        huart->Init.Mode = UART_MODE_TX_RX;
+    }
+
+    if (HAL_UART_Init(huart) != HAL_OK) {
+        error("Cannot initialize UART\n");
+    }
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+
+    switch (parity) {
+        case ParityOdd:
+            obj_s->parity = UART_PARITY_ODD;
+            break;
+        case ParityEven:
+            obj_s->parity = UART_PARITY_EVEN;
+            break;
+        default: // ParityNone
+        case ParityForced0: // unsupported!
+        case ParityForced1: // unsupported!
+            obj_s->parity = UART_PARITY_NONE;
+            break;
+    }
+
+    switch (data_bits) {
+        case 9:
+            MBED_ASSERT(parity == UART_PARITY_NONE);
+            obj_s->databits = UART_WORDLENGTH_9B;
+            break;
+        default:
+        case 8:
+            if (parity != UART_PARITY_NONE) {
+                obj_s->databits = UART_WORDLENGTH_9B;
+            } else {
+                obj_s->databits = UART_WORDLENGTH_8B;
+            }
+            break;
+#if defined UART_WORDLENGTH_7B
+        case 7:
+            if (parity != UART_PARITY_NONE) {
+                obj_s->databits = UART_WORDLENGTH_8B;
+            } else {
+                obj_s->databits = UART_WORDLENGTH_7B;
+            }
+            break;
+#endif
+    }
+
+    if (stop_bits == 2) {
+        obj_s->stopbits = UART_STOPBITS_2;
+    } else {
+        obj_s->stopbits = UART_STOPBITS_1;
+    }
+
+    init_uart(obj);
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_readable(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+    /*  To avoid a target blocking case, let's check for
+     *  possible OVERRUN error and discard it
+     */
+    if(__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE)) {
+        __HAL_UART_CLEAR_OREFLAG(huart);
+    }
+    // Check if data is received
+    return (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) ? 1 : 0;
+}
+
+int serial_writable(serial_t *obj)
+{
+    struct serial_s *obj_s = SERIAL_S(obj);
+    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+    // Check if data is transmitted
+    return (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) ? 1 : 0;
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    (void)obj;
+}
+
+#endif /* DEVICE_SERIAL */
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/serial_api_hal.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/serial_api_hal.h
new file mode 100755
index 0000000..e4a1892
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/serial_api_hal.h
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+*******************************************************************************
+* Copyright (c) 2016, STMicroelectronics
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+*    this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+*    this list of conditions and the following disclaimer in the documentation
+*    and/or other materials provided with the distribution.
+* 3. Neither the name of STMicroelectronics nor the names of its contributors
+*    may be used to endorse or promote products derived from this software
+*    without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+*/
+
+#ifndef MBED_SERIAL_API_HAL_H
+#define MBED_SERIAL_API_HAL_H
+
+#include "serial_api.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Extend serial_api.h
+ */
+
+#if DEVICE_SERIAL_ASYNCH
+    #define SERIAL_S(obj) (&((obj)->serial))
+#else
+    #define SERIAL_S(obj) (obj)
+#endif
+
+extern UART_HandleTypeDef uart_handlers[];
+
+
+/** Initialize and configure the UART peripheral
+ *
+ * @param obj       The serial object containing the configuration
+ */
+void init_uart(serial_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/sleep.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/sleep.c
new file mode 100755
index 0000000..d41edfe
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/sleep.c
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+#include "us_ticker_api.h"
+#include "sleep_api.h"
+#include "rtc_api_hal.h"
+#include "hal_tick.h"
+#include "mbed_critical.h"
+
+extern void HAL_SuspendTick(void);
+extern void HAL_ResumeTick(void);
+
+void hal_sleep(void)
+{
+    // Disable IRQs
+    core_util_critical_section_enter();
+
+    // Stop HAL tick to avoid to exit sleep in 1ms
+    HAL_SuspendTick();
+    // Request to enter SLEEP mode
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+    // Restart HAL tick
+    HAL_ResumeTick();
+
+    // Enable IRQs
+    core_util_critical_section_exit();
+}
+
+void hal_deepsleep(void)
+{
+    // Disable IRQs
+    core_util_critical_section_enter();
+
+    // Stop HAL tick
+    HAL_SuspendTick();
+    uint32_t EnterTimeUS = us_ticker_read();
+
+    // Request to enter STOP mode with regulator in low power mode
+#if TARGET_STM32L4
+    int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
+    int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
+    
+    if (!pwrClockEnabled) {
+        __HAL_RCC_PWR_CLK_ENABLE();
+    }
+    if (lowPowerModeEnabled) {
+        HAL_PWREx_DisableLowPowerRunMode();
+    }
+    
+    HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
+    
+    if (lowPowerModeEnabled) {
+        HAL_PWREx_EnableLowPowerRunMode();
+    }
+    if (!pwrClockEnabled) {
+        __HAL_RCC_PWR_CLK_DISABLE();
+    }
+#else /* TARGET_STM32L4 */
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+#endif /* TARGET_STM32L4 */
+
+    // Restart HAL tick
+    HAL_ResumeTick();
+
+    // Enable IRQs
+    core_util_critical_section_exit();
+
+    // After wake-up from STOP reconfigure the PLL
+    SetSysClock();
+
+    TIM_HandleTypeDef TimMasterHandle;
+    TimMasterHandle.Instance = TIM_MST;
+    __HAL_TIM_SET_COUNTER(&TimMasterHandle, EnterTimeUS);
+
+#if DEVICE_LOWPOWERTIMER
+    rtc_synchronize();
+#endif
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/stm32_assert.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/stm32_assert.h
new file mode 100755
index 0000000..45aa52f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/stm32_assert.h
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef STM32_ASSERT_H
+#define STM32_ASSERT_H
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #include "mbed_assert.h"
+  #define assert_param(expr) MBED_ASSERT(expr)
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/stm_spi_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/stm_spi_api.c
new file mode 100755
index 0000000..9294fda
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/stm_spi_api.c
@@ -0,0 +1,692 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+#include <stdbool.h>
+#include <math.h>
+#include <string.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "spi_device.h"
+
+#if DEVICE_SPI_ASYNCH
+    #define SPI_INST(obj)    ((SPI_TypeDef *)(obj->spi.spi))
+#else
+    #define SPI_INST(obj)    ((SPI_TypeDef *)(obj->spi))
+#endif
+
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
+#endif
+
+#ifndef DEBUG_STDIO
+#   define DEBUG_STDIO 0
+#endif
+
+#if DEBUG_STDIO
+#   include <stdio.h>
+#   define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
+#else
+#   define DEBUG_PRINTF(...) {}
+#endif
+
+/* Consider 10ms as the default timeout for sending/receving 1 byte */
+#define TIMEOUT_1_BYTE 10
+
+void init_spi(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    __HAL_SPI_DISABLE(handle);
+
+    DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
+    if (HAL_SPI_Init(handle) != HAL_OK) {
+        error("Cannot initialize SPI");
+    }
+
+    /* In case of standard 4 wires SPI,PI can be kept enabled all time
+     * and SCK will only be generated during the write operations. But in case
+     * of 3 wires, it should be only enabled during rd/wr unitary operations,
+     * which is handled inside STM32 HAL layer.
+     */
+    if (handle->Init.Direction  == SPI_DIRECTION_2LINES) {
+        __HAL_SPI_ENABLE(handle);
+    }
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // Determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+    spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT(spiobj->spi != (SPIName)NC);
+
+#if defined SPI1_BASE
+    // Enable SPI clock
+    if (spiobj->spi == SPI_1) {
+        __HAL_RCC_SPI1_CLK_ENABLE();
+        spiobj->spiIRQ = SPI1_IRQn;
+    }
+#endif
+
+#if defined SPI2_BASE
+    if (spiobj->spi == SPI_2) {
+        __HAL_RCC_SPI2_CLK_ENABLE();
+        spiobj->spiIRQ = SPI2_IRQn;
+    }
+#endif
+
+#if defined SPI3_BASE
+    if (spiobj->spi == SPI_3) {
+        __HAL_RCC_SPI3_CLK_ENABLE();
+        spiobj->spiIRQ = SPI3_IRQn;
+    }
+#endif
+
+#if defined SPI4_BASE
+    if (spiobj->spi == SPI_4) {
+        __HAL_RCC_SPI4_CLK_ENABLE();
+        spiobj->spiIRQ = SPI4_IRQn;
+    }
+#endif
+
+#if defined SPI5_BASE
+    if (spiobj->spi == SPI_5) {
+        __HAL_RCC_SPI5_CLK_ENABLE();
+        spiobj->spiIRQ = SPI5_IRQn;
+    }
+#endif
+
+#if defined SPI6_BASE
+    if (spiobj->spi == SPI_6) {
+        __HAL_RCC_SPI6_CLK_ENABLE();
+        spiobj->spiIRQ = SPI6_IRQn;
+    }
+#endif
+
+    // Configure the SPI pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    spiobj->pin_miso = miso;
+    spiobj->pin_mosi = mosi;
+    spiobj->pin_sclk = sclk;
+    spiobj->pin_ssel = ssel;
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    } else {
+        handle->Init.NSS = SPI_NSS_SOFT;
+    }
+
+    /* Fill default value */
+    handle->Instance = SPI_INST(obj);
+    handle->Init.Mode              = SPI_MODE_MASTER;
+    handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
+
+    if (miso != NC) {
+        handle->Init.Direction     = SPI_DIRECTION_2LINES;
+    } else {
+       handle->Init.Direction      = SPI_DIRECTION_1LINE;
+    }
+
+    handle->Init.CLKPhase          = SPI_PHASE_1EDGE;
+    handle->Init.CLKPolarity       = SPI_POLARITY_LOW;
+    handle->Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLE;
+    handle->Init.CRCPolynomial     = 7;
+    handle->Init.DataSize          = SPI_DATASIZE_8BIT;
+    handle->Init.FirstBit          = SPI_FIRSTBIT_MSB;
+    handle->Init.TIMode            = SPI_TIMODE_DISABLE;
+
+    init_spi(obj);
+}
+
+void spi_free(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    DEBUG_PRINTF("spi_free\r\n");
+
+    __HAL_SPI_DISABLE(handle);
+    HAL_SPI_DeInit(handle);
+
+#if defined SPI1_BASE
+    // Reset SPI and disable clock
+    if (spiobj->spi == SPI_1) {
+        __HAL_RCC_SPI1_FORCE_RESET();
+        __HAL_RCC_SPI1_RELEASE_RESET();
+        __HAL_RCC_SPI1_CLK_DISABLE();
+    }
+#endif
+#if defined SPI2_BASE
+    if (spiobj->spi == SPI_2) {
+        __HAL_RCC_SPI2_FORCE_RESET();
+        __HAL_RCC_SPI2_RELEASE_RESET();
+        __HAL_RCC_SPI2_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI3_BASE
+    if (spiobj->spi == SPI_3) {
+        __HAL_RCC_SPI3_FORCE_RESET();
+        __HAL_RCC_SPI3_RELEASE_RESET();
+        __HAL_RCC_SPI3_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI4_BASE
+    if (spiobj->spi == SPI_4) {
+        __HAL_RCC_SPI4_FORCE_RESET();
+        __HAL_RCC_SPI4_RELEASE_RESET();
+        __HAL_RCC_SPI4_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI5_BASE
+    if (spiobj->spi == SPI_5) {
+        __HAL_RCC_SPI5_FORCE_RESET();
+        __HAL_RCC_SPI5_RELEASE_RESET();
+        __HAL_RCC_SPI5_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI6_BASE
+    if (spiobj->spi == SPI_6) {
+        __HAL_RCC_SPI6_FORCE_RESET();
+        __HAL_RCC_SPI6_RELEASE_RESET();
+        __HAL_RCC_SPI6_CLK_DISABLE();
+    }
+#endif
+
+    // Configure GPIOs
+    pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    if (handle->Init.NSS != SPI_NSS_SOFT) {
+        pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    }
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
+
+    // Save new values
+    handle->Init.DataSize          = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
+
+    switch (mode) {
+        case 0:
+            handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+            handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+            break;
+        case 1:
+            handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+            handle->Init.CLKPhase = SPI_PHASE_2EDGE;
+            break;
+        case 2:
+            handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
+            handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+            break;
+        default:
+            handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
+            handle->Init.CLKPhase = SPI_PHASE_2EDGE;
+            break;
+    }
+
+    if (handle->Init.NSS != SPI_NSS_SOFT) {
+        handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
+    }
+
+    handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
+
+    init_spi(obj);
+}
+
+/*
+ * Only the IP clock input is family dependant so it computed
+ * separately in spi_get_clock_freq
+ */
+extern int spi_get_clock_freq(spi_t *obj);
+
+static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
+                                                    SPI_BAUDRATEPRESCALER_4,
+                                                    SPI_BAUDRATEPRESCALER_8,
+                                                    SPI_BAUDRATEPRESCALER_16,
+                                                    SPI_BAUDRATEPRESCALER_32,
+                                                    SPI_BAUDRATEPRESCALER_64,
+                                                    SPI_BAUDRATEPRESCALER_128,
+                                                    SPI_BAUDRATEPRESCALER_256};
+
+void spi_frequency(spi_t *obj, int hz) {
+    struct spi_s *spiobj = SPI_S(obj);
+    int spi_hz = 0;
+    uint8_t prescaler_rank = 0;
+    uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1;
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */
+    spi_hz = spi_get_clock_freq(obj) / 2;
+
+    /* Define pre-scaler in order to get highest available frequency below requested frequency */
+    while ((spi_hz > hz) && (prescaler_rank < last_index)) {
+        spi_hz = spi_hz / 2;
+        prescaler_rank++;
+    }
+
+    /*  Use the best fit pre-scaler */
+    handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank];
+
+    /*  In case maximum pre-scaler still gives too high freq, raise an error */
+    if (spi_hz > hz) {
+        DEBUG_PRINTF("WARNING: lowest SPI freq (%d)  higher than requested (%d)\r\n", spi_hz, hz);
+    }
+
+    DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz);
+
+    init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj)
+{
+    int status;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // Check if data is received
+    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline int ssp_writeable(spi_t *obj)
+{
+    int status;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // Check if data is transmitted
+    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline int ssp_busy(spi_t *obj)
+{
+    int status;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
+    return status;
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    if (handle->Init.Direction == SPI_DIRECTION_1LINE) {
+        return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE);
+    }
+
+#if defined(LL_SPI_RX_FIFO_TH_HALF)
+    /*  Configure the default data size */
+    if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+        LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF);
+    } else {
+        LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER);
+    }
+#endif
+
+    /*  Here we're using LL which means direct registers access
+     *  There is no error management, so we may end up looping
+     *  infinitely here in case of faulty device for insatnce,
+     *  but this will increase performances significantly
+     */
+
+    /* Wait TXE flag to transmit data */
+    while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj)));
+
+    if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+        LL_SPI_TransmitData16(SPI_INST(obj), value);
+    } else {
+        LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value);
+    }
+
+    /* Then wait RXE flag before reading */
+    while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj)));
+
+    if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+        return LL_SPI_ReceiveData16(SPI_INST(obj));
+    } else {
+        return LL_SPI_ReceiveData8(SPI_INST(obj));
+    }
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    int total = (tx_length > rx_length) ? tx_length : rx_length;
+    int i = 0;
+    if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
+        for (i = 0; i < total; i++) {
+            char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+            char in = spi_master_write(obj, out);
+            if (i < rx_length) {
+                rx_buffer[i] = in;
+            }
+        }
+    } else {
+        /* In case of 1 WIRE only, first handle TX, then Rx */
+        if (tx_length != 0) {
+            if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) {
+                /*  report an error */
+                total = 0;
+            }
+        }
+        if (rx_length != 0) {
+            if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) {
+                /*  report an error */
+                total = 0;
+            }
+        }
+    }
+
+    return total;
+}
+
+// new function F4HDK
+int spi_master_transfer_2(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
+{
+    //uint16_t size;
+    uint16_t ret;
+    //int Rx = 0;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    //size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1;
+	
+	if (tx_length<rx_length) {
+		tx_length = rx_length;
+	}
+	
+    /*  Use 10ms timeout */
+    ret = HAL_SPI_TransmitReceive(handle,tx,rx,tx_length,3); //3
+
+    //if(ret == HAL_OK) {
+    //    return Rx;
+    //} else {
+    //    DEBUG_PRINTF("SPI inst=0x%8X ERROR in write\r\n", (int)handle->Instance);
+    //    return -1;
+    //}
+	return 0;
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    while (!ssp_readable(obj));
+    if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+        return LL_SPI_ReceiveData16(SPI_INST(obj));
+    } else {
+        return LL_SPI_ReceiveData8(SPI_INST(obj));
+    }
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    SPI_TypeDef *spi = SPI_INST(obj);
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    while (!ssp_writeable(obj));
+    if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
+        // Force 8-bit access to the data register
+        uint8_t *p_spi_dr = 0;
+        p_spi_dr = (uint8_t *) & (spi->DR);
+        *p_spi_dr = (uint8_t)value;
+    } else { // SPI_DATASIZE_16BIT
+        spi->DR = (uint16_t)value;
+    }
+}
+
+int spi_busy(spi_t *obj)
+{
+    return ssp_busy(obj);
+}
+
+#ifdef DEVICE_SPI_ASYNCH
+typedef enum {
+    SPI_TRANSFER_TYPE_NONE = 0,
+    SPI_TRANSFER_TYPE_TX = 1,
+    SPI_TRANSFER_TYPE_RX = 2,
+    SPI_TRANSFER_TYPE_TXRX = 3,
+} transfer_type_t;
+
+
+/// @returns the number of bytes transferred, or `0` if nothing transferred
+static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
+    // the HAL expects number of transfers instead of number of bytes
+    // so for 16 bit transfer width the count needs to be halved
+    size_t words;
+
+    DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
+
+    obj->spi.transfer_type = transfer_type;
+
+    if (is16bit) {
+        words = length / 2;
+    } else {
+        words = length;
+    }
+
+    // enable the interrupt
+    IRQn_Type irq_n = spiobj->spiIRQ;
+    NVIC_DisableIRQ(irq_n);
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_SetPriority(irq_n, 1);
+    NVIC_EnableIRQ(irq_n);
+
+    // enable the right hal transfer
+    int rc = 0;
+    switch(transfer_type) {
+        case SPI_TRANSFER_TYPE_TXRX:
+            rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
+            break;
+        case SPI_TRANSFER_TYPE_TX:
+            rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
+            break;
+        case SPI_TRANSFER_TYPE_RX:
+            // the receive function also "transmits" the receive buffer so in order
+            // to guarantee that 0xff is on the line, we explicitly memset it here
+            memset(rx, SPI_FILL_WORD, length);
+            rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
+            break;
+        default:
+            length = 0;
+    }
+
+    if (rc) {
+        DEBUG_PRINTF("SPI: RC=%u\n", rc);
+        length = 0;
+    }
+
+    return length;
+}
+
+// asynchronous API
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // TODO: DMA usage is currently ignored
+    (void) hint;
+
+    // check which use-case we have
+    bool use_tx = (tx != NULL && tx_length > 0);
+    bool use_rx = (rx != NULL && rx_length > 0);
+    bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
+
+    // don't do anything, if the buffers aren't valid
+    if (!use_tx && !use_rx)
+        return;
+
+    // copy the buffers to the SPI object
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = is16bit ? 16 : 8;
+
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+    obj->rx_buff.width = obj->tx_buff.width;
+
+    obj->spi.event = event;
+
+    DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
+
+    // register the thunking handler
+    IRQn_Type irq_n = spiobj->spiIRQ;
+    NVIC_SetVector(irq_n, (uint32_t)handler);
+
+    // enable the right hal transfer
+    if (use_tx && use_rx) {
+        // we cannot manage different rx / tx sizes, let's use smaller one
+        size_t size = (tx_length < rx_length)? tx_length : rx_length;
+        if(tx_length != rx_length) {
+            DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
+            obj->tx_buff.length = size;
+            obj->rx_buff.length = size;
+        }
+        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
+    } else if (use_tx) {
+        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
+    } else if (use_rx) {
+        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
+    }
+}
+
+inline uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+    int event = 0;
+
+    // call the CubeF4 handler, this will update the handle
+    HAL_SPI_IRQHandler(&obj->spi.handle);
+
+    if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
+        // When HAL SPI is back to READY state, check if there was an error
+        int error = obj->spi.handle.ErrorCode;
+        if(error != HAL_SPI_ERROR_NONE) {
+            // something went wrong and the transfer has definitely completed
+            event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+
+            if (error & HAL_SPI_ERROR_OVR) {
+                // buffer overrun
+                event |= SPI_EVENT_RX_OVERFLOW;
+            }
+        } else {
+            // else we're done
+            event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+       }
+       // enable the interrupt
+       NVIC_DisableIRQ(obj->spi.spiIRQ);
+       NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
+    }
+
+
+    return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
+
+    switch(state) {
+        case HAL_SPI_STATE_RESET:
+        case HAL_SPI_STATE_READY:
+        case HAL_SPI_STATE_ERROR:
+            return 0;
+        default:
+            return 1;
+    }
+}
+
+void spi_abort_asynch(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // disable interrupt
+    IRQn_Type irq_n = spiobj->spiIRQ;
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_DisableIRQ(irq_n);
+
+    // clean-up
+    __HAL_SPI_DISABLE(handle);
+    HAL_SPI_DeInit(handle);
+    HAL_SPI_Init(handle);
+    __HAL_SPI_ENABLE(handle);
+}
+
+#endif //DEVICE_SPI_ASYNCH
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/trng_api.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/trng_api.c
new file mode 100755
index 0000000..f77f2b3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/trng_api.c
@@ -0,0 +1,100 @@
+/*
+ *  Hardware entropy collector for the STM32 families
+ *
+ *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ */
+
+#if defined(DEVICE_TRNG)
+
+#include <stdlib.h>
+#include "cmsis.h"
+#include "trng_api.h"
+#include "mbed_error.h"
+#include "mbed_critical.h"
+
+static uint8_t users = 0;
+
+void trng_init(trng_t *obj)
+{
+    uint32_t dummy;
+
+    /*  We're only supporting a single user of RNG */
+    if (core_util_atomic_incr_u8(&users, 1) > 1 ) {
+        error("Only 1 RNG instance supported\r\n");
+    }
+
+#if defined(TARGET_STM32L4)
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+    /*Select PLLQ output as RNG clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+#endif
+
+    /* RNG Peripheral clock enable */
+    __HAL_RCC_RNG_CLK_ENABLE();
+
+    /* Initialize RNG instance */
+    obj->handle.Instance = RNG;
+    obj->handle.State = HAL_RNG_STATE_RESET;
+    obj->handle.Lock = HAL_UNLOCKED;
+
+    HAL_RNG_Init(&obj->handle);
+
+    /* first random number generated after setting the RNGEN bit should not be used */
+    HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy);
+}
+
+void trng_free(trng_t *obj)
+{
+    /*Disable the RNG peripheral */
+    HAL_RNG_DeInit(&obj->handle);
+    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
+    __HAL_RCC_RNG_CLK_DISABLE();
+
+    users = 0;
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    int ret = 0;
+    volatile uint8_t random[4];
+    *output_length = 0;
+
+    /* Get Random byte */
+    while ((*output_length < length) && (ret ==0)) {
+        if ( HAL_RNG_GenerateRandomNumber(&obj->handle, (uint32_t *)random ) != HAL_OK) {
+                ret = -1;
+        } else {
+            for (uint8_t i =0; (i < 4) && (*output_length < length) ; i++) {
+                *output++ = random[i];
+                *output_length += 1;
+                random[i] = 0;
+            }
+        }
+    }
+
+    /* Just be extra sure that we didn't do it wrong */
+    if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) {
+        ret = -1;
+    }
+
+    return( ret );
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/us_ticker_16b.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/us_ticker_16b.c
new file mode 100755
index 0000000..1197783
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/us_ticker_16b.c
@@ -0,0 +1,191 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "hal_tick.h"
+
+// A 16-bit timer is used
+#if TIM_MST_16BIT
+
+TIM_HandleTypeDef TimMasterHandle;
+
+volatile uint32_t SlaveCounter = 0;
+volatile uint32_t oc_int_part = 0;
+
+void us_ticker_init(void)
+{
+    /* NOTE: assuming that HAL tick has already been initialized! */
+}
+
+uint32_t us_ticker_read()
+{
+    uint16_t cntH_old, cntH, cntL;
+    do {
+        cntH_old = SlaveCounter;
+        /* SlaveCounter needs to be checked before AND after we read the
+         * current counter TIM_MST->CNT, in case it wraps around.
+         * there are 2 possible cases of wrap around
+         * 1) in case this function is interrupted by timer_irq_handler and
+         *    the SlaveCounter is updated. In that case we will loop again.
+         * 2) in case this function is called from interrupt context during
+         * wrap-around condtion. That would prevent/delay the timer_irq_handler
+         * from being called so we need to locally check the FLAG_UPDATE and
+         * update the cntH accordingly. The SlaveCounter variable itself will
+         * be updated in the interrupt handler just after ...
+         */
+        if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+            cntH_old += 1;
+        }
+        cntL = TIM_MST->CNT;
+        cntH = SlaveCounter;
+        if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+            cntH += 1;
+        }
+    } while(cntH_old != cntH);
+    // Glue the upper and lower part together to get a 32 bit timer
+    return (uint32_t)(cntH << 16 | cntL);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    // NOTE: This function must be called with interrupts disabled to keep our
+    //       timer interrupt setup atomic
+
+    // Set new output compare value
+    __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, timestamp & 0xFFFF);
+    // Ensure the compare event starts clear
+    __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+    // Enable IT
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+
+    /* Set the number of timer wrap-around loops before the actual timestamp
+     * is reached.  If the calculated delta time is more than halfway to the
+     * next compare event, check to see if a compare event has already been
+     * set, and if so, add one to the wrap-around count.  This is done to
+     * ensure the correct wrap count is used in the corner cases where the
+     * 16 bit counter passes the compare value during the process of
+     * configuring this interrupt.
+     *
+     * Assumption: The time to execute this function is less than 32ms
+     *             (otherwise incorrect behaviour could result)
+     *
+     * Consider the following corner cases:
+     * 1) timestamp is 1 us in the future:
+     *      oc_int_part = 0 initially
+     *      oc_int_part left at 0 because ((delta - 1) & 0xFFFF) < 0x8000
+     *      Compare event should happen in 1 us and us_ticker_irq_handler()
+     *      called
+     * 2) timestamp is 0x8000 us in the future:
+     *      oc_int_part = 0 initially
+     *      oc_int_part left at 0 because ((delta - 1) & 0xFFFF) < 0x8000
+     *      There should be no possibility of the CC1 flag being set yet
+     *      (see assumption above).  When the compare event does occur in
+     *      32768 us, us_ticker_irq_handler() will be called
+     * 3) timestamp is 0x8001 us in the future:
+     *      oc_int_part = 0 initially
+     *      ((delta - 1) & 0xFFFF) >= 0x8000 but there should be no
+     *      possibility of the CC1 flag being set yet (see assumption above),
+     *      so oc_int_part will be left at 0, and when the compare event
+     *      does occur in 32769 us, us_ticker_irq_handler() will be called
+     * 4) timestamp is 0x10000 us in the future:
+     *      oc_int_part = 0 initially
+     *      ((delta - 1) & 0xFFFF) >= 0x8000
+     *      There are two subcases:
+     *      a) The timer counter has not incremented past the compare
+     *          value while setting up the interrupt.  In this case, the
+     *          CC1 flag will not be set, so oc_int_part will be
+     *          left at 0, and when the compare event occurs in 65536 us,
+     *          us_ticker_irq_handler() will be called
+     *      b) The timer counter has JUST incremented past the compare
+     *          value.  In this case, the CC1 flag will be set, so
+     *          oc_int_part will be incremented to 1, and the interrupt will
+     *          occur immediately after this function returns, where
+     *          oc_int_part will decrement to 0 without calling
+     *          us_ticker_irq_handler().  Then about 65536 us later, the
+     *          compare event will occur again, and us_ticker_irq_handler()
+     *          will be called
+     * 5) timestamp is 0x10001 us in the future:
+     *      oc_int_part = 1 initially
+     *      oc_int_part left at 1 because ((delta - 1) & 0xFFFF) < 0x8000
+     *      CC1 flag will not be set (see assumption above).  In 1 us the
+     *      compare event will cause an interrupt, where oc_int_part will be
+     *      decremented to 0 without calling us_ticker_irq_handler().  Then
+     *      about 65536 us later, the compare event will occur again, and
+     *      us_ticker_irq_handler() will be called
+     * 6) timestamp is 0x18000 us in the future:
+     *      oc_int_part = 1 initially
+     *      oc_int_part left at 1 because ((delta - 1) & 0xFFFF) < 0x8000
+     *      There should be no possibility of the CC1 flag being set yet
+     *      (see assumption above).  When the compare event does occur in
+     *      32768 us, oc_int_part will be decremented to 0 without calling
+     *      us_ticker_irq_handler().  Then about 65536 us later, the
+     *      compare event will occur again, and us_ticker_irq_handler() will
+     *      be called
+     * 7) timestamp is 0x18001 us in the future:
+     *      oc_int_part = 1 initially
+     *      ((delta - 1) & 0xFFFF) >= 0x8000 but there should be no
+     *      possibility of the CC1 flag being set yet (see assumption above),
+     *      so oc_int_part will be left at 1, and when the compare event
+     *      does occur in 32769 us, oc_int_part will be decremented to 0
+     *      without calling us_ticker_irq_handler().  Then about 65536 us
+     *      later, the compare event will occur again, and
+     *      us_ticker_irq_handler() will be called
+     *
+     * delta - 1 is used because the timer compare event happens on the
+     * counter incrementing to match the compare value, and it won't occur
+     * immediately when the compare value is set to the current counter
+     * value.
+     */
+    uint32_t current_time = us_ticker_read();
+    uint32_t delta = timestamp - current_time;
+    /* Note: The case of delta <= 0 is handled in MBED upper layer */
+    oc_int_part = (delta - 1) >> 16;
+    if ( ((delta - 1) & 0xFFFF) >= 0x8000 &&
+         __HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET ) {
+        ++oc_int_part;
+        /* NOTE: Instead of incrementing oc_int_part here, we could clear
+         *       the CC1 flag, but then you'd have to wait to ensure the
+         *       interrupt is knocked down before returning and reenabling
+         *       interrupts.  Since this is a rare case, it's not worth it
+         *       to try and optimize it, and it keeps the code simpler and
+         *       safer to just do this increment instead.
+         */
+    }
+
+}
+
+void us_ticker_fire_interrupt(void)
+{
+    /* When firing the event, the number of 16 bits counter wrap-ups (oc_int)
+     * must be re-initialized */
+    oc_int_part = 0;
+    HAL_TIM_GenerateEvent(&TimMasterHandle, TIM_EVENTSOURCE_CC1);
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void us_ticker_disable_interrupt(void)
+{
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void us_ticker_clear_interrupt(void)
+{
+    __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+}
+
+#endif // TIM_MST_16BIT
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/us_ticker_32b.c b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/us_ticker_32b.c
new file mode 100755
index 0000000..b642413
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/TARGET_STM/us_ticker_32b.c
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "hal_tick.h"
+
+// A 32-bit timer is used
+#if !TIM_MST_16BIT
+
+TIM_HandleTypeDef TimMasterHandle;
+
+void us_ticker_init(void)
+{
+    /* NOTE: assuming that HAL tick has already been initialized! */
+}
+
+uint32_t us_ticker_read()
+{
+    return TIM_MST->CNT;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    // NOTE: This function must be called with interrupts disabled to keep our
+    //       timer interrupt setup atomic
+
+    // disable IT while we are handling the correct timestamp
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+    // Set new output compare value
+    __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp);
+    // Enable IT
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_fire_interrupt(void)
+{
+    LL_TIM_GenerateEvent_CC1(TimMasterHandle.Instance);
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void us_ticker_disable_interrupt(void)
+{
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void us_ticker_clear_interrupt(void)
+{
+    __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+}
+
+#endif // !TIM_MST_16BIT
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/targets.json
new file mode 100755
index 0000000..e42a817
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/targets/targets.json
@@ -0,0 +1,3442 @@
+{
+    "Target": {
+        "core": null,
+        "default_toolchain": "ARM",
+        "supported_toolchains": null,
+        "extra_labels": [],
+        "is_disk_virtual": false,
+        "macros": [],
+        "device_has": [],
+        "features": [],
+        "detect_code": [],
+        "public": false,
+        "default_lib": "std",
+        "bootloader_supported": false
+    },
+    "Super_Target": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "features_add": ["UVISOR", "BLE", "CLIENT", "IPV4", "IPV6"],
+        "supported_toolchains": ["ARM"]
+    },
+    "CM4_UARM": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "default_toolchain": "uARM",
+        "public": false,
+        "supported_toolchains": ["uARM"],
+        "default_lib": "small"
+    },
+    "CM4_ARM": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "public": false,
+        "supported_toolchains": ["ARM"]
+    },
+    "CM4F_UARM": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "uARM",
+        "public": false,
+        "supported_toolchains": ["uARM"],
+        "default_lib": "small"
+    },
+    "CM4F_ARM": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "public": false,
+        "supported_toolchains": ["ARM"]
+    },
+    "LPCTarget": {
+        "inherits": ["Target"],
+        "post_binary_hook": {"function": "LPCTargetCode.lpc_patch"},
+        "public": false
+    },
+    "LPC11C24": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_name": "LPC11C24FBD48/301"
+    },
+    "LPC1114": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC1114FN28/102"
+    },
+    "LPC11U24": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "detect_code": ["1040"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC11U24FBD48/401"
+    },
+    "OC_MBUINO": {
+        "inherits": ["LPC11U24"],
+        "macros": ["TARGET_LPC11U24", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "extra_labels": ["NXP", "LPC11UXX"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2"]
+    },
+    "LPC11U24_301": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "extra_labels": ["NXP", "LPC11UXX"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_name": "LPC11U24FHI33/301"
+    },
+    "LPC11U34_421": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+	"default_lib": "small",
+        "device_name": "LPC11U34FBD48/311"
+    },
+    "MICRONFCBOARD": {
+        "inherits": ["LPC11U34_421"],
+        "macros_add": ["LPC11U34_421", "APPNEARME_MICRONFCBOARD"],
+        "extra_labels_add": ["APPNEARME_MICRONFCBOARD"],
+        "release_versions": ["2"],
+        "device_name": "LPC11U34FBD48/311"
+    },
+    "LPC11U35_401": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC11U35FBD48/401"
+    },
+    "LPC11U35_501": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC11U35FHI33/501"
+    },
+    "LPC11U35_501_IBDAP": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "device_name": "LPC11U35FHI33/501"
+    },
+    "XADOW_M0": {
+        "inherits": ["LPC11U35_501"]
+    },
+    "LPC11U35_Y5_MBUG": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "device_name": "LPC11U35FHI33/501"
+    },
+    "LPC11U37_501": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "default_lib": "small",
+        "device_name": "LPC11U37FBD64/501"
+    },
+    "LPCCAPPUCCINO": {
+        "inherits": ["LPC11U37_501"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "device_name": "LPC11U37FBD64/501"
+    },
+    "ARCH_GPRS": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "inherits": ["LPCTarget"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC11U37FBD64/501"
+    },
+    "LPC11U68": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11U6X"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"],
+        "inherits": ["LPCTarget"],
+        "detect_code": ["1168"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC11U68JBD100"
+    },
+    "LPC1347": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M3",
+        "extra_labels": ["NXP", "LPC13XX"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2"],
+        "device_name": "LPC1347FBD48"
+    },
+    "LPC1549": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M3",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC15XX"],
+        "supported_toolchains": ["uARM", "GCC_CR", "GCC_ARM", "IAR"],
+        "inherits": ["LPCTarget"],
+        "detect_code": ["1549"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC1549JBD64"
+    },
+    "LPC1768": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M3",
+        "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "detect_code": ["1010"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "release_versions": ["2", "5"],
+        "features": ["LWIP"],
+        "device_name": "LPC1768",
+        "bootloader_supported": true
+    },
+    "LPC1769": {
+        "inherits": ["LPC1768"],
+        "device_name": "LPC1769"
+    },
+    "ARCH_PRO": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "extra_labels": ["NXP", "LPC176X"],
+        "macros": ["TARGET_LPC1768"],
+        "inherits": ["LPCTarget"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "release_versions": ["2", "5"],
+        "features": ["LWIP"],
+        "device_name": "LPC1768",
+        "bootloader_supported": true
+    },
+    "UBLOX_C027": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "extra_labels": ["NXP", "LPC176X"],
+        "config": {
+            "modem_is_on_board": {
+                "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD"
+            },
+            "modem_data_connection_type": {
+                "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD_UART"
+            }
+        },
+        "macros": ["TARGET_LPC1768"],
+        "inherits": ["LPCTarget"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "release_versions": ["2", "5"],
+        "features": ["LWIP"],
+        "device_name": "LPC1768",
+        "bootloader_supported": true
+    },
+    "XBED_LPC1768": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
+        "macros": ["TARGET_LPC1768"],
+        "detect_code": ["1010"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_name": "LPC1768"
+    },
+    "LPC810": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC81X"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
+        "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "device_name": "LPC810M021FN8"
+    },
+    "LPC812": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC81X"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
+        "inherits": ["LPCTarget"],
+        "detect_code": ["1050"],
+        "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC812M101JDH20"
+    },
+    "LPC824": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC82X"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["uARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "inherits": ["LPCTarget"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC824M201JDH20"
+    },
+    "SSCI824": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC82X"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["uARM", "GCC_ARM"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"]
+    },
+    "MCU_LPC4088": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M4F",
+        "extra_labels": ["NXP", "LPC408X"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "GCC_CR", "GCC_ARM", "IAR"],
+        "post_binary_hook": {
+            "function": "LPC4088Code.binary_hook"
+        },
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "features": ["LWIP"],
+        "device_name": "LPC4088FBD144"
+    },
+    "LPC4088": {
+        "inherits": ["MCU_LPC4088"],
+        "release_versions": ["2", "5"]
+    },
+    "LPC4088_DM": {
+        "inherits": ["MCU_LPC4088"],
+        "release_versions": ["2", "5"]
+    },
+    "LPC4330_M4": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M4F",
+        "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
+        "supported_toolchains": ["ARM", "GCC_CR", "IAR", "GCC_ARM"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_name": "LPC4330"
+    },
+    "LPC4330_M0": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M0",
+        "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
+        "supported_toolchains": ["ARM", "GCC_CR", "IAR"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
+    },
+    "LPC4337": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M4F",
+        "extra_labels": ["NXP", "LPC43XX", "LPC4337"],
+        "supported_toolchains": ["ARM"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2"],
+        "device_name": "LPC4337"
+    },
+    "LPC1800": {
+        "inherits": ["LPCTarget"],
+        "core": "Cortex-M3",
+        "extra_labels": ["NXP", "LPC43XX"],
+        "public": false,
+        "supported_toolchains": ["ARM", "GCC_CR", "IAR"]
+    },
+    "LPC11U37H_401": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC11UXX"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR"],
+        "inherits": ["LPCTarget"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "LPC11U37HFBD64/401"
+    },
+    "ELEKTOR_COCORICO": {
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "extra_labels": ["NXP", "LPC81X"],
+        "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
+        "inherits": ["LPCTarget"],
+        "is_disk_virtual": true,
+        "detect_code": ["C000"],
+        "default_lib": "small",
+        "device_name": "LPC812M101JDH16"
+    },
+    "KL05Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "extra_labels": ["Freescale", "KLXX"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "inherits": ["Target"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "MKL05Z32xxx4"
+    },
+    "KL25Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "extra_labels": ["Freescale", "KLXX"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "inherits": ["Target"],
+        "detect_code": ["0200"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name": "MKL25Z128xxx4"
+    },
+    "KL26Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "extra_labels": ["Freescale", "KLXX"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "inherits": ["Target"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_name": "MKL26Z128xxx4"
+    },
+    "KL46Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "extra_labels": ["Freescale", "KLXX", "FLASH_CMSIS_ALGO"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "inherits": ["Target"],
+        "detect_code": ["0220"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "MKL46Z256xxx4",
+        "bootloader_supported": true
+    },
+    "K20D50M": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "extra_labels": ["Freescale", "K20XX"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "detect_code": ["0230"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2"],
+        "device_name": "MK20DX128xxx5"
+    },
+    "TEENSY3_1": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "extra_labels": ["Freescale", "K20XX", "K20DX256"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["GCC_ARM", "ARM"],
+        "post_binary_hook": {
+            "function": "TEENSY3_1Code.binary_hook",
+            "toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
+        },
+        "detect_code": ["0230"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2"],
+        "device_name": "MK20DX256xxx7"
+    },
+    "MCU_K22F512": {
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K22F", "MCU_K22F512", "FRDM", "KPSDK_MCUS", "KPSDK_CODE"],
+        "is_disk_virtual": true,
+        "public": false,
+        "macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["0231"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_name": "MK22DN512xxx5"
+    },
+    "K22F": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_K22F512"],
+        "release_versions": ["2", "5"],
+        "extra_labels_add": ["FRDM"]
+    },
+    "KL27Z": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0+",
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "macros": ["CPU_MKL27Z64VLH4", "FSL_RTOS_MBED"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "supported_form_factors": ["ARDUINO"],
+        "is_disk_virtual": true,
+        "default_toolchain": "ARM",
+        "detect_code": ["0261"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "default_lib": "std",
+        "release_versions": ["2"],
+        "device_name": "MKL27Z64xxx4"
+    },
+    "KL43Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "macros": ["CPU_MKL43Z256VLH4", "FSL_RTOS_MBED"],
+        "is_disk_virtual": true,
+        "inherits": ["Target"],
+        "detect_code": ["0262"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name": "MKL43Z256xxx4"
+    },
+    "KL82Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "macros": ["CPU_MKL82Z128VLK7", "FSL_RTOS_MBED"],
+        "is_disk_virtual": true,
+        "inherits": ["Target"],
+        "detect_code": ["0218"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "release_versions": ["2", "5"],
+        "device_name": "MKL82Z128xxx7"
+    },
+    "USENSE": {
+        "inherits": ["KL82Z"],
+        "device_has_add": ["LOWPOWERTIMER"],
+        "extra_labels_remove": ["FRDM"],
+        "supported_form_factors": []
+    },
+    "KW24D": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["0250"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "MKW24D512xxx5",
+        "bootloader_supported": true
+    },
+    "KW41Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["0201"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name": "MKW41Z512xxx4"
+    },
+    "MCU_K24F1M": {
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K24F", "KPSDK_MCUS", "KPSDK_CODE"],
+        "is_disk_virtual": true,
+        "public": false,
+        "macros": ["CPU_MK24FN1M0VDC12", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "device_name": "MK24FN1M0xxx12"
+    },
+    "RO359B": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_K24F1M"],
+        "detect_code": ["1022"],
+        "release_versions": ["2", "5"]
+    },
+    "K64F": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["0240"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
+        "features": ["LWIP", "STORAGE"],
+        "release_versions": ["2", "5"],
+        "device_name": "MK64FN1M0xxx12",
+        "bootloader_supported": true
+    },
+    "MTS_GAMBIT": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
+        "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_name": "MK64FN1M0xxx12"
+    },
+    "HEXIWEAR": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K64F"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
+        "is_disk_virtual": true,
+        "default_toolchain": "ARM",
+        "detect_code": ["0214"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "default_lib": "std",
+        "release_versions": ["2", "5"],
+        "device_name": "MK64FN1M0xxx12"
+    },
+    "K66F": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["0311"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "MK66FN2M0xxx18",
+        "bootloader_supported": true
+    },
+    "K82F": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["0217"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "release_versions": ["2", "5"],
+        "device_name": "MK82FN256xxx15"
+    },
+    "UBRIDGE": {
+        "inherits": ["K82F"],
+        "extra_labels_remove": ["FRDM"],
+        "supported_form_factors": []
+    },
+    "FAMILY_STM32": {
+        "inherits": ["Target"],
+        "public": false,
+        "extra_labels": ["STM"],
+        "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
+    },
+    "LPC54114": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54114_M4", "LPCXpresso"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["1054"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name" : "LPC54114J256BD64"
+    },
+    "LPC546XX": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_LPC54618J512ET180", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["1056"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name" : "LPC54618J512ET180"
+    },
+    "NUCLEO_F030R8": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M0",
+        "extra_labels_add": ["STM32F0", "STM32F030R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0725"],
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["SERIAL_FC"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32F030R8"
+    },
+    "NUCLEO_F031K6": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels_add": ["STM32F0", "STM32F031K6"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0791"],
+        "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["SERIAL_FC"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32F031K6"
+    },
+    "NUCLEO_F042K6": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0",
+        "default_toolchain": "uARM",
+        "extra_labels_add": ["STM32F0", "STM32F042K6"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0785"],
+        "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["CAN", "SERIAL_FC"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32F042K6"
+    },
+    "NUCLEO_F070RB": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M0",
+        "extra_labels_add": ["STM32F0", "STM32F070RB"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0755"],
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F070RB"
+    },
+    "NUCLEO_F072RB": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M0",
+        "extra_labels_add": ["STM32F0", "STM32F072RB"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0730"],
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F072RB"
+    },
+    "NUCLEO_F091RC": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M0",
+        "extra_labels_add": ["STM32F0", "STM32F091RC"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0750"],
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F091RC"
+    },
+    "NUCLEO_F103RB": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M3",
+        "extra_labels_add": ["STM32F1", "STM32F103RB"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "clock_source_usb": {
+                "help": "In case of HSI clock source, to get 48 Mhz USB, SYSCLK has to be reduced from 64 to 48 MHz (set 0 for the max SYSCLK value)",
+                "value": "0",
+                "macro_name": "CLOCK_SOURCE_USB"
+            }
+        },
+        "detect_code": ["0700"],
+        "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F103RB"
+    },
+    "NUCLEO_F207ZG": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M3",
+        "extra_labels_add": ["STM32F2", "STM32F207ZG"],
+        "config": {
+            "d11_configuration": {
+                "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+                "value": "PA_7",
+                "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0835"],
+        "macros_add": ["USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F207ZG"
+    },
+    "NUCLEO_F302R8": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F3", "STM32F302x8", "STM32F302R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0705"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32F302R8"
+    },
+    "NUCLEO_F303K8": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"],
+        "macros_add": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0775"],
+        "default_lib": "small",
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
+        "release_versions": ["2"],
+        "device_name": "STM32F303K8"
+    },
+    "NUCLEO_F303RE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303RE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0745"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F303RE"
+    },
+    "NUCLEO_F303ZE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303ZE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0747"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F303ZE"
+    },
+    "NUCLEO_F334R8": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F3", "STM32F334x8", "STM32F334R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0735"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32F334R8"
+    },
+    "NUCLEO_F401RE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401RE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0720"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F401RE"
+    },
+    "NUCLEO_F410RB": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F410RB","STM32F410xB", "STM32F410Rx"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0744"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F410RB"
+    },
+    "NUCLEO_F411RE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+        "detect_code": ["0740"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "clock_source_usb": {
+                "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 100 to 96 MHz (set 0 for the max SYSCLK value)",
+                "value": "0",
+                "macro_name": "CLOCK_SOURCE_USB"
+            }
+        },
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F411RE"
+    },
+    "NUCLEO_F412ZG": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0826"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F412ZG",
+        "bootloader_supported": true
+    },
+    "DISCO_F413ZH": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F413xx", "STM32F413ZH", "STM32F413xH"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0743"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F413ZH"
+    },
+    "ELMO_F411RE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "uARM",
+        "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+        "detect_code": ["----"],
+        "device_has_add": [],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32F411RE"
+    },
+    "NUCLEO_F429ZI": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "config": {
+            "d11_configuration": {
+                "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+                "value": "PA_7",
+                "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "clock_source_usb": {
+                "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+                "value": "1",
+                "macro_name": "CLOCK_SOURCE_USB"
+            }
+        },
+        "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "detect_code": ["0796"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F429ZI",
+        "bootloader_supported": true
+    },
+    "NUCLEO_F439ZI": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "config": {
+            "d11_configuration": {
+                "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+                "value": "PA_7",
+                "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "clock_source_usb": {
+                "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+                "value": "1",
+                "macro_name": "CLOCK_SOURCE_USB"
+            }
+        },
+        "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "STM32F439xI"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "detect_code": ["0797"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name" : "STM32F439ZI",
+        "bootloader_supported": true
+    },
+    "NUCLEO_F446RE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446RE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0777"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F446RE",
+        "bootloader_supported": true
+    },
+    "NUCLEO_F446ZE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446ZE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0778"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F446ZE"
+    },
+    "B96B_F446VE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446VE"],
+        "detect_code": ["0840"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name":"STM32F446VE"
+    },
+    "NUCLEO_F746ZG": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M7F",
+        "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746ZG"],
+        "config": {
+            "d11_configuration": {
+                "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+                "value": "PA_7",
+                "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "macros_add": ["USBHOST_OTHER"],
+        "supported_form_factors": ["ARDUINO"],
+        "detect_code": ["0816"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F746ZG"
+    },
+    "NUCLEO_F756ZG": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M7F",
+        "extra_labels_add": ["STM32F7", "STM32F756", "STM32F756xG", "STM32F756ZG"],
+        "config": {
+            "d11_configuration": {
+                "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+                "value": "PA_7",
+                "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
+        "supported_form_factors": ["ARDUINO"],
+        "detect_code": ["0819"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F756ZG"
+    },
+    "NUCLEO_F767ZI": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M7FD",
+        "extra_labels_add": ["STM32F7", "STM32F767", "STM32F767xI", "STM32F767ZI"],
+        "config": {
+            "d11_configuration": {
+                "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+                "value": "PA_7",
+                "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "supported_form_factors": ["ARDUINO"],
+        "macros_add": ["USBHOST_OTHER"],
+        "detect_code": ["0818"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F767ZI"
+    },
+    "NUCLEO_L011K4": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M0+",
+        "extra_labels_add": ["STM32L0", "STM32L011K4"],
+        "supported_toolchains": ["uARM"],
+        "default_toolchain": "uARM",
+        "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0780"],
+        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32L011K4"
+    },
+    "NUCLEO_L031K6": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M0+",
+        "extra_labels_add": ["STM32L0", "STM32L031K6"],
+        "default_toolchain": "uARM",
+        "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0790"],
+        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32L031K6"
+    },
+    "NUCLEO_L053R8": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M0+",
+        "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0715"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32L053R8"
+    },
+    "NUCLEO_L073RZ": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M0+",
+        "extra_labels_add": ["STM32L0", "STM32L073RZ", "STM32L073xx"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0760"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L073RZ"
+    },
+    "NUCLEO_L152RE": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M3",
+        "extra_labels_add": ["STM32L1", "STM32L152RE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0710"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L152RE"
+    },
+    "NUCLEO_L432KC": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L432xC", "STM32L432KC"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0770"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "CAN", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L432KC"
+    },
+    "NUCLEO_L476RG": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L476RG", "STM32L476xG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0765"],
+        "macros_add": ["USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L476RG",
+        "bootloader_supported": true
+    },
+    "SILICA_SENSOR_NODE": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "GCC_ARM",
+        "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476JG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0766"],
+        "macros_add": ["USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["5"],
+        "device_name": "STM32L476JG"
+    },
+    "NUCLEO_L486RG": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0827"],
+        "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L486RG"
+    },
+    "ARCH_MAX": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+        "program_cycle_s": 2,
+        "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
+        "device_has_add": ["ANALOGOUT"],
+        "release_versions": ["2"],
+        "device_name": "STM32F407VG"
+    },
+    "DISCO_F051R8": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M0",
+        "extra_labels_add": ["STM32F0", "STM32F051", "STM32F051R8"],
+        "supported_toolchains": ["GCC_ARM"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["SERIAL_FC"],
+        "device_name": "STM32F051R8"
+    },
+    "DISCO_F100RB": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M3",
+        "extra_labels_add": ["STM32F1", "STM32F100RB"],
+        "supported_toolchains": ["GCC_ARM"],
+        "device_has_add": [],
+        "device_name": "STM32F100RB"
+    },
+    "DISCO_F303VC": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F3", "STM32F303", "STM32F303xC", "STM32F303VC"],
+        "macros_add": ["RTC_LSI=1"],
+        "supported_toolchains": ["GCC_ARM"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
+        "device_name": "STM32F303VC"
+    },
+    "DISCO_F334C8": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F3", "STM32F334x8","STM32F334C8"],
+        "macros_add": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0810"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32F334C8"
+    },
+    "DISCO_F407VG": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+        "macros_add": ["USB_STM_HAL"],
+        "device_has_add": ["ANALOGOUT"],
+        "device_name": "STM32F407VG"
+    },
+    "DISCO_F429ZI": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xI", "STM32F429xx"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "clock_source_usb": {
+                "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+                "value": "1",
+                "macro_name": "CLOCK_SOURCE_USB"
+            }
+        },
+        "macros_add": ["RTC_LSI=1", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F429ZI"
+    },
+    "DISCO_F469NI": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F469", "STM32F469NI", "STM32F469xI", "STM32F469xx"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0788"],
+        "macros_add": ["USB_STM_HAL"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F469NI"
+    },
+    "DISCO_L053C8": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M0+",
+        "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
+        "macros": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32L053C8"
+    },
+    "DISCO_L072CZ_LRWAN1": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M0+",
+        "extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xx"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "macros": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0833"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L072CZ"
+    },
+    "DISCO_F746NG": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M7F",
+        "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746NG"],
+        "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0815"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F746NG"
+    },
+    "DISCO_F769NI": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M7FD",
+        "extra_labels_add": ["STM32F7", "STM32F769", "STM32F769xI", "STM32F769NI"],
+        "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0817"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F769NI"
+    },
+    "DISCO_L475VG_IOT01A": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "supported_form_factors": ["ARDUINO"],
+        "detect_code": ["0764"],
+        "macros_add": ["USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L475VG"
+    },
+    "DISCO_L476VG": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0820"],
+        "macros_add": ["USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L476VG",
+        "bootloader_supported": true
+    },
+    "MTS_MDOT_F405RG": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F405RG"],
+        "is_disk_virtual": true,
+        "macros_add": ["HSE_VALUE=26000000"],
+        "device_has_add": ["ANALOGOUT"],
+        "release_versions": ["2"],
+        "device_name": "STM32F405RG"
+    },
+    "MTS_MDOT_F411RE": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F411RE"],
+        "macros_add": ["HSE_VALUE=26000000", "USE_PLL_HSE_EXTC=0", "VECT_TAB_OFFSET=0x00010000"],
+        "post_binary_hook": {
+            "function": "MTSCode.combine_bins_mts_dot",
+            "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+        },
+        "device_has_add": [],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F411RE"
+    },
+    "MTS_DRAGONFLY_F411RE": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F411RE"],
+        "config": {
+            "modem_is_on_board": {
+                "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD"
+            },
+            "modem_data_connection_type": {
+                "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD_UART"
+            }
+        },
+        "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000", "RTC_LSI=1"],
+        "post_binary_hook": {
+            "function": "MTSCode.combine_bins_mts_dragonfly",
+            "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+        },
+        "device_has_add": [],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F411RE"
+    },
+    "XDOT_L151CC": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M3",
+        "default_toolchain": "ARM",
+        "extra_labels_add": ["STM32L1", "STM32L151CC"],
+        "config": {
+            "hse_value": {
+            "value": "24000000",
+            "macro_name": "HSE_VALUE"
+            }
+        },
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "device_has_add": ["ANALOGOUT", "FLASH"],
+        "release_versions": ["5"],
+        "device_name": "STM32L151CC",
+        "bootloader_supported": true
+    },
+    "FF1705_L151CC": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["XDOT_L151CC"],
+        "detect_code": ["8080"]
+    },
+    "MOTE_L152RC": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M3",
+        "default_toolchain": "uARM",
+        "extra_labels_add": ["STM32L1", "STM32L152RC"],
+        "macros": ["RTC_LSI=1"],
+        "detect_code": ["4100"],
+        "device_has_add": ["ANALOGOUT"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "STM32L152RC"
+    },
+    "DISCO_F401VC": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "GCC_ARM",
+        "extra_labels_add": ["STM32F4", "STM32F401", "STM32F401xC", "STM32F401VC"],
+        "supported_toolchains": ["GCC_ARM"],
+        "device_has_add": [],
+        "device_name": "STM32F401VC"
+    },
+    "UBLOX_EVK_ODIN_W2": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI"],
+        "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
+        "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH"],
+        "device_has_remove": ["RTC", "SLEEP"],
+        "features": ["LWIP"],
+        "release_versions": ["5"],
+        "device_name": "STM32F439ZI",
+        "bootloader_supported": true,
+        "config": {
+            "usb_tx": {
+                "help": "Value: D8(default) or D1",
+                "value": "D8"
+            },
+            "usb_rx": {
+                "help": "Value: D2(default) or D0",
+                "value": "D2"
+            },
+            "stdio_uart": {
+                "help": "Value: UART_1(default) or UART_3",
+                "value": "UART_1",
+                "macro_name": "STDIO_UART"
+            }
+        }
+    },
+    "UBLOX_C030": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "extra_labels_add": ["STM32F4", "STM32F437", "STM32F437VG", "STM32F437xx", "STM32F437xG"],
+        "config": {
+            "modem_is_on_board": {
+                "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD"
+            },
+            "modem_data_connection_type": {
+                "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD_UART"
+            }
+        },
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
+        "device_has_add": ["ANALOGOUT", "SERIAL_FC", "TRNG", "FLASH"],
+        "features": ["LWIP"],
+        "public": false,
+        "device_name": "STM32F437VG",
+        "bootloader_supported": true
+    },
+    "UBLOX_C030_U201": {
+        "inherits": ["UBLOX_C030"],
+        "release_versions": ["5"]
+    },
+    "UBLOX_C030_N211": {
+        "inherits": ["UBLOX_C030"],
+        "release_versions": ["5"]
+    },
+    "NZ32_SC151": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M3",
+        "default_toolchain": "uARM",
+        "program_cycle_s": 1.5,
+        "extra_labels_add": ["STM32L1", "STM32L151RC"],
+        "macros": ["RTC_LSI=1"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+        "device_has_add": ["ANALOGOUT"],
+        "default_lib": "small",
+        "device_name": "STM32L151RC"
+    },
+    "MCU_NRF51": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0",
+        "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
+        "macros": ["NRF51", "TARGET_NRF51822", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "MERGE_BOOTLOADER": false,
+        "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "GCC_ARM"],
+        "public": false,
+        "MERGE_SOFT_DEVICE": true,
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "boot": "s130_nrf51_1.0.0_bootloader.hex",
+                "name": "s130_nrf51_1.0.0_softdevice.hex",
+                "offset": 114688
+            },
+            {
+                "boot": "s110_nrf51822_8.0.0_bootloader.hex",
+                "name": "s110_nrf51822_8.0.0_softdevice.hex",
+                "offset": 98304
+            },
+            {
+                "boot": "s110_nrf51822_7.1.0_bootloader.hex",
+                "name": "s110_nrf51822_7.1.0_softdevice.hex",
+                "offset": 90112
+            },
+            {
+                "boot": "s110_nrf51822_7.0.0_bootloader.hex",
+                "name": "s110_nrf51822_7.0.0_softdevice.hex",
+                "offset": 90112
+            },
+            {
+                "boot": "s110_nrf51822_6.0.0_bootloader.hex",
+                "name": "s110_nrf51822_6.0.0_softdevice.hex",
+                "offset": 81920
+            }
+        ],
+        "detect_code": ["1070"],
+        "post_binary_hook": {
+            "function": "MCU_NRF51Code.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM"]
+        },
+        "program_cycle_s": 6,
+        "features": ["BLE"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
+    },
+    "MCU_NRF51_16K_BASE": {
+        "inherits": ["MCU_NRF51"],
+        "extra_labels_add": ["MCU_NORDIC_16K", "MCU_NRF51_16K"],
+        "macros_add": ["TARGET_MCU_NORDIC_16K", "TARGET_MCU_NRF51_16K"],
+        "public": false,
+        "default_lib": "small"
+    },
+    "MCU_NRF51_16K_BOOT_BASE": {
+        "inherits": ["MCU_NRF51_16K_BASE"],
+        "MERGE_BOOTLOADER": true,
+        "extra_labels_add": ["MCU_NRF51_16K_BOOT"],
+        "macros_add": ["TARGET_MCU_NRF51_16K_BOOT", "TARGET_OTA_ENABLED"],
+        "public": false
+    },
+    "MCU_NRF51_16K_OTA_BASE": {
+        "inherits": ["MCU_NRF51_16K_BASE"],
+        "public": false,
+        "extra_labels_add": ["MCU_NRF51_16K_OTA"],
+        "macros_add": ["TARGET_MCU_NRF51_16K_OTA", "TARGET_OTA_ENABLED"],
+        "MERGE_SOFT_DEVICE": false
+    },
+    "MCU_NRF51_16K": {
+        "inherits": ["MCU_NRF51_16K_BASE"],
+        "extra_labels_add": ["MCU_NRF51_16K_S130"],
+        "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+        "public": false
+    },
+    "MCU_NRF51_S110": {
+        "extra_labels_add": ["MCU_NRF51_16K_S110"],
+        "macros_add": ["TARGET_MCU_NRF51_16K_S110"],
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "name": "s110_nrf51822_8.0.0_softdevice.hex",
+                "boot": "s110_nrf51822_8.0.0_bootloader.hex",
+                "offset": 98304
+            },
+            {
+                "name": "s110_nrf51822_7.1.0_softdevice.hex",
+                "boot": "s110_nrf51822_7.1.0_bootloader.hex",
+                "offset": 90112
+            }
+        ],
+        "public": false
+    },
+    "MCU_NRF51_16K_S110": {
+        "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BASE"],
+        "public": false
+    },
+    "MCU_NRF51_16K_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT_BASE"],
+        "extra_labels_add": ["MCU_NRF51_16K_S130"],
+        "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+        "public": false
+    },
+    "MCU_NRF51_16K_BOOT_S110": {
+        "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BOOT_BASE"],
+        "public": false
+    },
+    "MCU_NRF51_16K_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA_BASE"],
+        "extra_labels_add": ["MCU_NRF51_16K_S130"],
+        "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+        "public": false
+    },
+    "MCU_NRF51_16K_OTA_S110": {
+        "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_OTA_BASE"],
+        "public": false
+    },
+    "MCU_NRF51_32K": {
+        "inherits": ["MCU_NRF51"],
+        "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
+        "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
+        "public": false
+    },
+    "MCU_NRF51_32K_BOOT": {
+        "inherits": ["MCU_NRF51_32K"],
+        "MERGE_BOOTLOADER": true,
+        "extra_labels_add": ["MCU_NRF51_32K_BOOT"],
+        "macros_add": ["TARGET_MCU_NRF51_32K_BOOT", "TARGET_OTA_ENABLED"],
+        "public": false
+    },
+    "MCU_NRF51_32K_OTA": {
+        "inherits": ["MCU_NRF51_32K"],
+        "public": false,
+        "extra_labels_add": ["MCU_NRF51_32K_OTA"],
+        "macros_add": ["TARGET_MCU_NRF51_32K_OTA", "TARGET_OTA_ENABLED"],
+        "MERGE_SOFT_DEVICE": false
+    },
+    "NRF51822": {
+        "inherits": ["MCU_NRF51_16K"],
+        "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+        "macros_add": ["TARGET_NRF51822_MKIT"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "NRF51822_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+        "macros_add": ["TARGET_NRF51822_MKIT"]
+    },
+    "NRF51822_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+        "macros_add": ["TARGET_NRF51822_MKIT"]
+    },
+    "ARCH_BLE": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "ARCH_BLE_BOOT": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["ARCH_BLE"],
+        "macros_add": ["TARGET_ARCH_BLE"]
+    },
+    "ARCH_BLE_OTA": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["ARCH_BLE"],
+        "macros_add": ["TARGET_ARCH_BLE"]
+    },
+    "ARCH_LINK": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K"],
+        "extra_labels_add": ["ARCH_BLE"],
+        "macros_add": ["TARGET_ARCH_BLE"]
+    },
+    "ARCH_LINK_BOOT": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
+        "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
+    },
+    "ARCH_LINK_OTA": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
+        "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
+    },
+    "SEEED_TINY_BLE": {
+        "inherits": ["MCU_NRF51_16K"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "SEEED_TINY_BLE_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["SEEED_TINY_BLE"],
+        "macros_add": ["TARGET_SEEED_TINY_BLE"]
+    },
+    "SEEED_TINY_BLE_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["SEEED_TINY_BLE"],
+        "macros_add": ["TARGET_SEEED_TINY_BLE"]
+    },
+    "HRM1017": {
+        "inherits": ["MCU_NRF51_16K"],
+        "macros_add": ["TARGET_NRF_LFCLK_RC"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "HRM1017_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["HRM1017"],
+        "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
+    },
+    "HRM1017_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["HRM1017"],
+        "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
+    },
+    "RBLAB_NRF51822": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "RBLAB_NRF51822_BOOT": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["RBLAB_NRF51822"],
+        "macros_add": ["TARGET_RBLAB_NRF51822"]
+    },
+    "RBLAB_NRF51822_OTA": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["RBLAB_NRF51822"],
+        "macros_add": ["TARGET_RBLAB_NRF51822"]
+    },
+    "RBLAB_BLENANO": {
+        "inherits": ["MCU_NRF51_16K"],
+        "release_versions": ["2"]
+    },
+    "RBLAB_BLENANO_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["RBLAB_BLENANO"],
+        "macros_add": ["TARGET_RBLAB_BLENANO"]
+    },
+    "RBLAB_BLENANO_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["RBLAB_BLENANO"],
+        "macros_add": ["TARGET_RBLAB_BLENANO"]
+    },
+    "NRF51822_Y5_MBUG": {
+        "inherits": ["MCU_NRF51_16K"]
+    },
+    "WALLBOT_BLE": {
+        "inherits": ["MCU_NRF51_16K"],
+        "release_versions": ["2"]
+    },
+    "WALLBOT_BLE_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["WALLBOT_BLE"],
+        "macros_add": ["TARGET_WALLBOT_BLE"]
+    },
+    "WALLBOT_BLE_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["WALLBOT_BLE"],
+        "macros_add": ["TARGET_WALLBOT_BLE"]
+    },
+    "DELTA_DFCM_NNN40": {
+        "inherits": ["MCU_NRF51_32K"],
+        "program_cycle_s": 10,
+        "macros_add": ["TARGET_NRF_LFCLK_RC"],
+        "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "DELTA_DFCM_NNN40_BOOT": {
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "program_cycle_s": 10,
+        "extra_labels_add": ["DELTA_DFCM_NNN40"],
+        "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
+    },
+    "DELTA_DFCM_NNN40_OTA": {
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "program_cycle_s": 10,
+        "extra_labels_add": ["DELTA_DFCM_NNN40"],
+        "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
+    },
+    "DELTA_DFCM_NNN50": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_name": "nRF51822_xxAC"
+    },
+    "DELTA_DFCM_NNN50_BOOT": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "extra_labels_add": ["DELTA_DFCM_NNN50"],
+        "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+    },
+    "DELTA_DFCM_NNN50_OTA": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "extra_labels_add": ["DELTA_DFCM_NNN50"],
+        "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+    },
+    "NRF51_DK_LEGACY": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K"],
+        "extra_labels_add": ["NRF51_DK"]
+    },
+    "NRF51_DK_BOOT": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "extra_labels_add": ["NRF51_DK"],
+        "macros_add": ["TARGET_NRF51_DK"]
+    },
+    "NRF51_DK_OTA": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "extra_labels_add": ["NRF51_DK"],
+        "macros_add": ["TARGET_NRF51_DK"]
+    },
+    "NRF51_DONGLE_LEGACY": {
+        "inherits": ["MCU_NRF51_32K"],
+        "extra_labels_add": ["NRF51_DONGLE"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "NRF51_DONGLE_BOOT": {
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "extra_labels_add": ["NRF51_DONGLE"],
+        "macros_add": ["TARGET_NRF51_DONGLE"]
+    },
+    "NRF51_DONGLE_OTA": {
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "extra_labels_add": ["NRF51_DONGLE"],
+        "macros_add": ["TARGET_NRF51_DONGLE"]
+    },
+    "NRF51_MICROBIT": {
+        "inherits": ["MCU_NRF51_16K_S110"],
+        "macros_add": ["TARGET_NRF_LFCLK_RC"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "NRF51_MICROBIT_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT_S110"],
+        "extra_labels_add": ["NRF51_MICROBIT"],
+        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+    },
+    "NRF51_MICROBIT_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA_S110"],
+        "extra_labels_add": ["NRF51_MICROBIT"],
+        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+    },
+    "NRF51_MICROBIT_B": {
+        "inherits": ["MCU_NRF51_16K"],
+        "extra_labels_add": ["NRF51_MICROBIT"],
+        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"],
+        "release_versions": ["2"]
+    },
+    "NRF51_MICROBIT_B_BOOT": {
+        "inherits": ["MCU_NRF51_16K_BOOT"],
+        "extra_labels_add": ["NRF51_MICROBIT"],
+        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+    },
+    "NRF51_MICROBIT_B_OTA": {
+        "inherits": ["MCU_NRF51_16K_OTA"],
+        "extra_labels_add": ["NRF51_MICROBIT"],
+        "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+    },
+    "MTM_MTCONNECT04S": {
+        "inherits": ["MCU_NRF51_32K"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "MTM_MTCONNECT04S_BOOT": {
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "extra_labels_add": ["MTM_CONNECT04S"],
+        "macros_add": ["TARGET_MTM_CONNECT04S"]
+    },
+    "MTM_MTCONNECT04S_OTA": {
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "extra_labels_add": ["MTM_CONNECT04S"],
+        "macros_add": ["TARGET_MTM_CONNECT04S"]
+    },
+    "TY51822R3": {
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
+        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "detect_code": ["1019"],
+        "release_versions": ["2", "5"],
+        "overrides": {"uart_hwfc": 0},
+        "device_name": "nRF51822_xxAA"
+    },
+    "TY51822R3_BOOT": {
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "extra_labels_add": ["TY51822R3"],
+        "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
+    },
+    "TY51822R3_OTA": {
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "extra_labels_add": ["NRF51_DK"],
+        "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
+    },
+    "ARM_MPS2_Target": {
+        "inherits": ["Target"],
+        "public": false,
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
+    },
+    "ARM_MPS2_M0": {
+        "inherits": ["ARM_MPS2_Target"],
+        "core": "Cortex-M0",
+        "supported_toolchains": ["ARM"],
+        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
+        "macros": ["CMSDK_CM0", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+        "release_versions": ["2"]
+    },
+    "ARM_MPS2_M0P": {
+        "inherits": ["ARM_MPS2_Target"],
+        "core": "Cortex-M0+",
+        "supported_toolchains": ["ARM"],
+        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0P"],
+        "macros": ["CMSDK_CM0plus"],
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+        "release_versions": ["2"]
+    },
+    "ARM_MPS2_M1": {
+        "inherits": ["ARM_MPS2_Target"],
+        "core": "Cortex-M1",
+        "supported_toolchains": ["ARM"],
+        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M1"],
+        "macros": ["CMSDK_CM1"],
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
+    },
+    "ARM_MPS2_M3": {
+        "inherits": ["ARM_MPS2_Target"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM"],
+        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M3"],
+        "macros": ["CMSDK_CM3"],
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+        "release_versions": ["2"]
+    },
+    "ARM_MPS2_M4": {
+        "inherits": ["ARM_MPS2_Target"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM"],
+        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M4"],
+        "macros": ["CMSDK_CM4"],
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+        "release_versions": ["2"]
+    },
+    "ARM_MPS2_M7": {
+        "inherits": ["ARM_MPS2_Target"],
+        "core": "Cortex-M7",
+        "supported_toolchains": ["ARM"],
+        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M7"],
+        "macros": ["CMSDK_CM7"],
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+        "release_versions": ["2"]
+    },
+    "ARM_IOTSS_Target": {
+        "inherits": ["Target"],
+        "public": false,
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
+    },
+    "ARM_IOTSS_BEID": {
+        "inherits": ["ARM_IOTSS_Target"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM"],
+        "extra_labels": ["ARM_SSG", "IOTSS", "IOTSS_BEID"],
+        "macros": ["CMSDK_BEID"],
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+        "release_versions": ["2"]
+    },
+     "ARM_CM3DS_MPS2": {
+        "inherits": ["ARM_IOTSS_Target"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
+        "macros": ["CMSDK_CM3DS"],
+        "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC"],
+        "release_versions": ["2", "5"],
+        "copy_method": "mps2",
+        "reset_method": "reboot.txt"
+    },
+    "ARM_BEETLE_SOC": {
+        "inherits": ["ARM_IOTSS_Target"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "default_toolchain": "ARM",
+        "extra_labels": ["ARM_SSG", "BEETLE"],
+        "macros": ["CMSDK_BEETLE", "WSF_MS_PER_TICK=20", "WSF_TOKEN_ENABLED=FALSE", "WSF_TRACE_ENABLED=TRUE", "WSF_ASSERT_ENABLED=FALSE", "WSF_PRINTF_MAX_LEN=128", "ASIC", "CONFIG_HOST_REV=0x20", "CONFIG_ALLOW_DEEP_SLEEP=FALSE", "HCI_VS_TARGET", "CONFIG_ALLOW_SETTING_WRITE=TRUE", "WSF_MAX_HANDLERS=20", "NO_LEDS"],
+        "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI"],
+        "features": ["BLE"],
+        "release_versions": ["2", "5"]
+    },
+    "RZ_A1H": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-A9",
+        "program_cycle_s": 2,
+        "extra_labels": ["RENESAS", "MBRZA1H"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "inherits": ["Target"],
+        "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "features": ["LWIP"],
+        "release_versions": ["2"]
+    },
+    "VK_RZ_A1H": {
+        "inherits": ["Target"],
+        "core": "Cortex-A9",
+        "extra_labels": ["RENESAS", "VKRZA1H"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "default_toolchain": "ARM",
+        "program_cycle_s": 2,
+        "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "features": ["LWIP"],
+        "default_lib": "std",
+        "release_versions": ["2"]
+    },
+    "MAXWSNENV": {
+        "inherits": ["Target"],
+        "core": "Cortex-M3",
+        "macros": ["__SYSTEM_HFX=24000000"],
+        "extra_labels": ["Maxim", "MAX32610"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+        "features": ["BLE"],
+        "release_versions": ["2", "5"]
+    },
+    "MAX32600MBED": {
+        "inherits": ["Target"],
+        "core": "Cortex-M3",
+        "macros": ["__SYSTEM_HFX=24000000"],
+        "extra_labels": ["Maxim", "MAX32600"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
+    "MAX32620HSP": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "extra_labels": ["Maxim", "MAX32620"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "features": ["BLE"],
+        "release_versions": ["2", "5"]
+    },
+    "MAX32625MBED": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
+        "extra_labels": ["Maxim", "MAX32625"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
+    "MAX32625NEXPAQ": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
+        "extra_labels": ["Maxim", "MAX32625"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
+    "MAX32630FTHR": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132", "BLE_HCI_UART", "OPEN_DRAIN_LEDS"],
+        "extra_labels": ["Maxim", "MAX32630"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+		"features": ["BLE"],
+        "release_versions": ["2", "5"]
+    },
+    "EFM32": {
+        "inherits": ["Target"],
+        "extra_labels": ["Silicon_Labs", "EFM32"],
+        "public": false
+    },
+    "EFM32GG990F1024": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
+        "core": "Cortex-M3",
+        "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "device_name": "EFM32GG990F1024",
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFM32GG_STK3700": {
+        "inherits": ["EFM32GG990F1024"],
+        "progen": {"target": "efm32gg-stk"},
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "forced_reset_timeout": 2,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "48000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "21000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PF7",
+                "macro_name": "EFM_BC_EN"
+            }
+        }
+    },
+    "EFM32LG990F256": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
+        "core": "Cortex-M3",
+        "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "device_name": "EFM32LG990F256",
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFM32LG_STK3600": {
+        "inherits": ["EFM32LG990F256"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "forced_reset_timeout": 2,
+        "device_name": "EFM32LG990F256",
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "48000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "21000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PF7",
+                "macro_name": "EFM_BC_EN"
+            }
+        }
+    },
+    "EFM32WG990F256": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
+        "core": "Cortex-M4F",
+        "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "device_name": "EFM32WG990F256",
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFM32WG_STK3800": {
+        "inherits": ["EFM32WG990F256"],
+        "progen": {"target": "efm32wg-stk"},
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "forced_reset_timeout": 2,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "48000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "21000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PF7",
+                "macro_name": "EFM_BC_EN"
+            }
+        }
+    },
+    "EFM32ZG222F32": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+        "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "EFM32ZG222F32",
+        "public": false
+    },
+    "EFM32ZG_STK3200": {
+        "inherits": ["EFM32ZG222F32"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "forced_reset_timeout": 2,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "24000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "21000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PA9",
+                "macro_name": "EFM_BC_EN"
+            }
+        }
+    },
+    "EFM32HG322F64": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
+        "core": "Cortex-M0+",
+        "default_toolchain": "uARM",
+        "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+        "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
+        "default_lib": "small",
+        "release_versions": ["2"],
+        "device_name": "EFM32HG322F64",
+        "public": false
+    },
+    "EFM32HG_STK3400": {
+        "inherits": ["EFM32HG322F64"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "forced_reset_timeout": 2,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "24000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "21000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PA9",
+                "macro_name": "EFM_BC_EN"
+            }
+        }
+    },
+    "EFM32PG1B100F256GM32": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
+        "core": "Cortex-M4F",
+        "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "device_name": "EFM32PG1B100F256GM32",
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFM32PG_STK3401": {
+        "inherits": ["EFM32PG1B100F256GM32"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "forced_reset_timeout": 2,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "40000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "32000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "cmuHFRCOFreq_32M0Hz",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PA5",
+                "macro_name": "EFM_BC_EN"
+            }
+        }
+    },
+    "EFR32MG1P132F256GM48": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
+        "core": "Cortex-M4F",
+        "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "device_name": "EFR32MG1P132F256GM48",
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFR32MG1P233F256GM48": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
+        "core": "Cortex-M4F",
+        "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFR32MG1_BRD4150": {
+        "inherits": ["EFR32MG1P132F256GM48"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "forced_reset_timeout": 2,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "38400000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "32000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "cmuHFRCOFreq_32M0Hz",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PA5",
+                "macro_name": "EFM_BC_EN"
+            }
+        },
+        "public": false
+    },
+    "TB_SENSE_1": {
+        "inherits": ["EFR32MG1P233F256GM48"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "forced_reset_timeout": 5,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "38400000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "32000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "cmuHFRCOFreq_32M0Hz",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            }
+        }
+    },
+    "EFM32PG12B500F1024GL125": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
+        "core": "Cortex-M4F",
+        "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFM32PG12_STK3402": {
+        "inherits": ["EFM32PG12B500F1024GL125"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "forced_reset_timeout": 2,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "40000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "32000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "cmuHFRCOFreq_32M0Hz",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PA5",
+                "macro_name": "EFM_BC_EN"
+            }
+        }
+    },
+	"EFR32MG12P332F1024GL125": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"],
+        "core": "Cortex-M4F",
+        "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "public": false,
+        "bootloader_supported": true
+    },
+	"TB_SENSE_12": {
+        "inherits": ["EFR32MG12P332F1024GL125"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "forced_reset_timeout": 5,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "38400000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "32000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "cmuHFRCOFreq_32M0Hz",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            }
+        }
+    },
+    "WIZWIKI_W7500": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0",
+        "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+        "inherits": ["Target"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
+    "WIZWIKI_W7500P": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0",
+        "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+        "inherits": ["Target"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
+    "WIZWIKI_W7500ECO": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0",
+        "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
+    "SAMR21G18A": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0+",
+        "macros": ["__SAMR21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMR21"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "release_versions": ["2"],
+        "device_name": "ATSAMR21G18A"
+    },
+    "SAMD21J18A": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0+",
+        "macros": ["__SAMD21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "release_versions": ["2"],
+        "device_name": "ATSAMD21J18A"
+    },
+    "SAMD21G18A": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0+",
+        "macros": ["__SAMD21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "release_versions": ["2"],
+        "device_name": "ATSAMD21G18A"
+    },
+    "SAML21J18A": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0+",
+        "macros": ["__SAML21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+        "extra_labels": ["Atmel", "SAM_CortexM0P", "SAML21"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "device_name": "ATSAML21J18A"
+    },
+    "SAMG55J19": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "extra_labels": ["Atmel", "SAM_CortexM4", "SAMG55"],
+        "macros": ["__SAMG55J19__", "BOARD=75", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+        "default_toolchain": "ARM",
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "default_lib": "std",
+        "device_name": "ATSAMG55J19"
+    },
+    "MCU_NRF51_UNIFIED": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0",
+        "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
+        "macros": [
+            "NRF51",
+            "TARGET_NRF51822",
+            "BLE_STACK_SUPPORT_REQD",
+            "SOFTDEVICE_PRESENT",
+            "S130",
+            "TARGET_MCU_NRF51822",
+            "CMSIS_VECTAB_VIRTUAL",
+            "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+            "NO_SYSTICK",
+            "MBED_TICKLESS"
+        ],
+        "MERGE_BOOTLOADER": false,
+        "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5", "SDK11"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "public": false,
+        "MERGE_SOFT_DEVICE": true,
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "boot": "",
+                "name": "s130_nrf51_2.0.0_softdevice.hex",
+                "offset": 110592
+            }
+        ],
+        "detect_code": ["1070"],
+        "post_binary_hook": {
+            "function": "MCU_NRF51Code.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+        },
+        "program_cycle_s": 6,
+        "features": ["BLE"],
+        "config": {
+            "lf_clock_src": {
+                "value": "NRF_LF_SRC_XTAL",
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+            },
+            "uart_hwfc": {
+                "help": "Value: 1 for enable, 0 for disable",
+                "value": 1,
+                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
+            }
+        },
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
+    },
+    "MCU_NRF51_32K_UNIFIED": {
+        "inherits": ["MCU_NRF51_UNIFIED"],
+        "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
+        "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
+        "public": false
+    },
+    "NRF51_DK": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "NRF51_DONGLE": {
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "progen": {"target": "nrf51-dongle"},
+        "device_has": ["I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"]
+    },
+    "MCU_NRF52": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
+        "device_has": ["STCLK_OFF_DURING_SLEEP"],
+        "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "public": false,
+        "detect_code": ["1101"],
+        "program_cycle_s": 6,
+        "MERGE_SOFT_DEVICE": true,
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "boot": "",
+                "name": "s132_nrf52_2.0.0_softdevice.hex",
+                "offset": 114688
+            }
+        ],
+        "post_binary_hook": {
+            "function": "MCU_NRF51Code.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+        },
+        "MERGE_BOOTLOADER": false,
+        "features": ["BLE"],
+        "config": {
+            "lf_clock_src": {
+                "value": "NRF_LF_SRC_XTAL",
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+            },
+            "uart_hwfc": {
+                "help": "Value: 1 for enable, 0 for disable",
+                "value": 1,
+                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
+            }
+        }
+    },
+    "NRF52_DK": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "device_name": "nRF52832_xxAA"
+    },
+    "UBLOX_EVA_NINA": {
+        "inherits": ["MCU_NRF52"],
+        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "overrides": {"uart_hwfc": 0},
+        "device_name": "nRF52832_xxAA"
+    },
+    "UBLOX_EVK_NINA_B1": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "device_name": "nRF52832_xxAA"
+    },
+    "DELTA_DFBM_NQ620": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
+        "config": {
+            "lf_clock_rc_calib_timer_interval": {
+                "value": 16,
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL"
+            },
+            "lf_clock_rc_calib_mode_config": {
+                "value": 0,
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG"
+            }
+        },
+        "device_name": "nRF52832_xxAA"
+    },
+    "MCU_NRF52840": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has": ["STCLK_OFF_DURING_SLEEP"],	    
+        "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "public": false,
+        "detect_code": ["1101"],
+        "program_cycle_s": 6,
+        "MERGE_SOFT_DEVICE": true,
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "boot": "",
+                "name": "s140_nrf52840_5.0.0-1.alpha_softdevice.hex",
+                "offset": 135168
+            }
+        ],
+        "bootloader_select_index": 0,
+        "post_binary_hook": {
+            "function": "MCU_NRF51Code.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+        },
+        "MERGE_BOOTLOADER": false,
+        "features": ["BLE"],
+        "config": {
+            "lf_clock_src": {
+                "value": "NRF_LF_SRC_XTAL",
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+            },
+            "uart_hwfc": {
+                "help": "Value: 1 for enable, 0 for disable",
+                "value": 1,
+                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
+            }
+        }
+    },
+    "NRF52840_DK": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52840"],
+        "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
+        "device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
+        "release_versions": ["2", "5"],
+        "device_name": "nRF52840_xxAA"
+    },
+    "BLUEPILL_F103C8": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M3",
+        "default_toolchain": "GCC_ARM",
+        "extra_labels_add": ["STM32F1", "STM32F103C8"],
+        "supported_toolchains": ["GCC_ARM"],
+        "device_has_add": [],
+        "device_has_remove": ["RTC", "STDIO_MESSAGES"]
+    },
+    "NUMAKER_PFM_NUC472": {
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED", "FLASH_CMSIS_ALGO"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
+                "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+                "value": "GPIO_DBCTL_DBCLKSEL_16"
+            }
+        },
+        "inherits": ["Target"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH"],
+        "features": ["LWIP"],
+        "release_versions": ["5"],
+        "device_name": "NUC472HI8AE",
+        "bootloader_supported": true
+    },
+    "NCS36510": {
+        "inherits": ["Target"],
+        "core": "Cortex-M3",
+        "extra_labels": ["ONSEMI"],
+        "config": {
+            "mac-addr-low": {
+                "help": "Lower 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
+                "value": "0xFFFFFFFF"
+            },
+            "mac-addr-high": {
+                "help": "Higher 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
+                "value": "0xFFFFFFFF"
+            },
+            "32KHz-clk-trim": {
+                "help": "32KHz clock trim",
+                "value": "0x39"
+            },
+            "32MHz-clk-trim": {
+                "help": "32MHz clock trim",
+                "value": "0x17"
+            },
+            "rssi-trim": {
+                "help": "RSSI trim",
+                "value": "0x3D"
+            },
+            "txtune-trim": {
+                "help": "TX tune trim",
+                "value": "0xFFFFFFFF"
+            }
+        },
+        "OUTPUT_EXT": "hex",
+        "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
+        "macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG", "SPISLAVE"],
+        "release_versions": ["2", "5"]
+    },
+    "NUMAKER_PFM_M453": {
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "extra_labels": ["NUVOTON", "M451", "NUMAKER_PFM_M453", "FLASH_CMSIS_ALGO"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+                "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+                "value": "GPIO_DBCTL_DBCLKSEL_16"
+            }
+        },
+        "inherits": ["Target"],
+        "progen": {"target": "numaker-pfm-m453"},
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "M453VG6AE",
+        "bootloader_supported": true
+    },
+    "NUMAKER_PFM_NANO130": {
+        "core": "Cortex-M0",
+        "default_toolchain": "ARM",
+        "extra_labels": ["NUVOTON", "NANO100", "NANO130KE3BN"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K",
+                "value": "GPIO_DBCLKSRC_IRC10K"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
+                "value": "GPIO_DBCLKSEL_16"
+            }
+        },
+        "inherits": ["Target"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "release_versions": ["5"],
+        "device_name": "NANO130KE3BN"
+    },
+    "HI2110": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0",
+        "default_toolchain": "GCC_ARM",
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "extra_labels": ["ublox"],
+        "macros": ["TARGET_PROCESSOR_FAMILY_BOUDICA", "BOUDICA_SARA", "NDEBUG=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "public": false,
+        "target_overrides": {
+            "*": {
+                "core.stdio-flush-at-exit": false
+            }
+        },
+        "device_has": ["INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "STDIO_MESSAGES"],
+        "default_lib": "std",
+        "release_versions": ["5"]
+   },
+    "SARA_NBIOT": {
+        "inherits": ["HI2110"],
+        "extra_labels": ["ublox", "HI2110"],
+        "public": false
+    },
+    "SARA_NBIOT_EVK": {
+        "inherits": ["SARA_NBIOT"],
+        "extra_labels": ["ublox", "HI2110", "SARA_NBIOT"]
+    },
+    "REALTEK_RTL8195AM": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M3",
+        "default_toolchain": "GCC_ARM",
+        "inherits": ["Target"],
+        "detect_code": ["4600"],
+        "extra_labels": ["Realtek", "AMEBA", "RTL8195A"],
+        "macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "TRNG", "EMAC", "FLASH"],
+        "features": ["LWIP"],
+        "post_binary_hook": {
+            "function": "RTL8195ACode.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+        },
+        "release_versions": ["5"]
+    },
+    "VBLUNO51_LEGACY": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K"],
+        "extra_labels_add": ["VBLUNO51"]
+    },
+    "VBLUNO51_BOOT": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_BOOT"],
+        "extra_labels_add": ["VBLUNO51"],
+        "macros_add": ["TARGET_VBLUNO51"]
+    },
+    "VBLUNO51_OTA": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_OTA"],
+        "extra_labels_add": ["VBLUNO51"],
+        "macros_add": ["TARGET_VBLUNO51"]
+    },
+    "VBLUNO51": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2"],
+        "device_name": "nRF51822_xxAC"
+    },
+    "VBLUNO52": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "macros_add": ["BOARD_PCA10040", "BOARD_VBLUNO52", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2"],
+        "device_name": "nRF52832_xxAA"
+    },
+    "NUMAKER_PFM_M487": {
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+                "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+                "value": "GPIO_DBCTL_DBCLKSEL_16"
+            },
+            "usb-device-hsusbd": {
+                "help": "Select high-speed USB device or not",
+                "value": 1
+            },
+            "ctrl01-enable": {
+                "help": "Enable control_01",
+                "value": 0
+            }
+        },
+        "inherits": ["Target"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH", "CAN"],
+        "features": ["LWIP"],
+        "release_versions": ["5"],
+        "device_name": "M487JIDAE",
+        "bootloader_supported": true
+    },
+    "TMPM066": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0",
+        "is_disk_virtual": true,
+        "extra_labels": ["TOSHIBA"],
+        "macros": ["__TMPM066__", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"],
+        "device_name": "TMPM066FWUG",
+        "detect_code": ["7011"],
+        "release_versions": ["5"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/.mbedignore b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/.mbedignore
new file mode 100755
index 0000000..f59ec20
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/.mbedignore
@@ -0,0 +1 @@
+*
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/__init__.py
new file mode 100755
index 0000000..1fa8431
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/__init__.py
@@ -0,0 +1,16 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/__init__.pyc
new file mode 100755
index 0000000..89c6c28
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/__init__.py
new file mode 100755
index 0000000..d297f06
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/__init__.py
@@ -0,0 +1,448 @@
+from urllib2 import urlopen, URLError
+from bs4 import BeautifulSoup
+from os.path import join, dirname, basename
+from os import makedirs
+from errno import EEXIST
+from threading import Thread
+from Queue import Queue
+from re import compile, sub
+from sys import stderr, stdout
+from itertools import takewhile
+import argparse
+from json import dump, load
+from zipfile import ZipFile
+from tempfile import gettempdir
+import warnings
+from distutils.version import LooseVersion
+
+warnings.filterwarnings("ignore")
+
+from fuzzywuzzy import process
+
+RootPackURL = "http://www.keil.com/pack/index.idx"
+
+LocalPackDir = dirname(__file__)
+LocalPackIndex = join(LocalPackDir, "index.json")
+LocalPackAliases = join(LocalPackDir, "aliases.json")
+
+
+protocol_matcher = compile("\w*://")
+def strip_protocol(url) :
+    return protocol_matcher.sub("", str(url))
+
+def largest_version(content) :
+    return sorted([t['version'] for t in content.package.releases('release')],
+                  reverse=True, key=lambda v: LooseVersion(v))[0]
+
+def do_queue(Class, function, interable) :
+    q = Queue()
+    threads = [Class(q, function) for each in range(20)]
+    for each in threads :
+        each.setDaemon(True)
+        each.start()
+    for thing in interable :
+        q.put(thing)
+    q.join()
+
+class Reader (Thread) :
+    def __init__(self, queue, func) :
+        Thread.__init__(self)
+        self.queue = queue
+        self.func = func
+    def run(self) :
+        while True :
+            url = self.queue.get()
+            self.func(url)
+            self.queue.task_done()
+
+
+class Cache () :
+    """ The Cache object is the only relevant API object at the moment
+
+    Constructing the Cache object does not imply any caching.
+    A user of the API must explicitly call caching functions.
+
+    :param silent: A boolean that, when True, significantly reduces the printing of this Object
+    :type silent: bool
+    :param no_timeouts: A boolean that, when True, disables the default connection timeout and low speed timeout for downloading things.
+    :type no_timeouts: bool
+    """
+    def __init__ (self, silent, no_timeouts) :
+        self.silent = silent
+        self.counter = 0
+        self.total = 1
+        self._index = {}
+        self._aliases = {}
+        self.urls = None
+        self.no_timeouts = no_timeouts
+        self.data_path = gettempdir()
+
+    def display_counter (self, message) :
+        stdout.write("{} {}/{}\r".format(message, self.counter, self.total))
+        stdout.flush()
+
+    def cache_file (self, url) :
+        """Low level interface to caching a single file.
+
+        :param url: The URL to cache.
+        :type url: str
+        :rtype: None
+        """
+        if not self.silent : print("Caching {}...".format(url))
+        dest = join(self.data_path, strip_protocol(url))
+        try :
+            makedirs(dirname(dest))
+        except OSError as exc :
+            if exc.errno == EEXIST : pass
+            else : raise
+        try:
+            with open(dest, "wb+") as fd :
+                fd.write(urlopen(url).read())
+        except URLError as e:
+            stderr.write(e.reason)
+        self.counter += 1
+        self.display_counter("Caching Files")
+
+    def pdsc_to_pack (self, url) :
+        """Find the URL of the specified pack file described by a PDSC.
+
+        The PDSC is assumed to be cached and is looked up in the cache by its URL.
+
+        :param url: The url used to look up the PDSC.
+        :type url: str
+        :return: The url of the PACK file.
+        :rtype: str
+        """
+        content = self.pdsc_from_cache(url)
+        new_url = content.package.url.get_text()
+        if not new_url.endswith("/") :
+            new_url = new_url + "/"
+        return (new_url + content.package.vendor.get_text() + "." +
+                content.package.find('name').get_text() + "." +
+                largest_version(content) + ".pack")
+
+    def cache_pdsc_and_pack (self, url) :
+        self.cache_file(url)
+        try :
+            self.cache_file(self.pdsc_to_pack(url))
+        except AttributeError :
+            stderr.write("[ ERROR ] {} does not appear to be a conforming .pdsc file\n".format(url))
+            self.counter += 1
+
+    def get_urls(self):
+        """Extract the URLs of all know PDSC files.
+
+        Will pull the index from the internet if it is not cached.
+
+        :return: A list of all PDSC URLs
+        :rtype: [str]
+        """
+        if not self.urls :
+            try : root_data = self.pdsc_from_cache(RootPackURL)
+            except IOError : root_data = self.cache_and_parse(RootPackURL)
+            self.urls = ["/".join([pdsc.get('url').strip("/"),
+                                   pdsc.get('name').strip("/")])
+                         for pdsc in root_data.find_all("pdsc")]
+        return self.urls
+
+    def _extract_dict(self, device, filename, pack) :
+        to_ret = dict(pdsc_file=filename, pack_file=pack)
+        try : to_ret["memory"] = dict([(m["id"], dict(start=m["start"],
+                                                      size=m["size"]))
+                                       for m in device("memory")])
+        except (KeyError, TypeError, IndexError) as e : pass
+        try: algorithms = device("algorithm")
+        except:
+            try: algorithms = device.parent("algorithm")
+            except: pass
+        else:
+            if not algorithms:
+                try: algorithms = device.parent("algorithm")
+                except: pass
+        try : to_ret["algorithm"] = dict([(algo.get("name").replace('\\','/'),
+                                           dict(start=algo["start"],
+                                                size=algo["size"],
+                                                ramstart=algo.get("ramstart",None),
+                                                ramsize=algo.get("ramsize",None),
+                                                default=algo.get("default",1)))
+                                       for algo in algorithms])
+        except (KeyError, TypeError, IndexError) as e: pass
+        try: to_ret["debug"] = device.parent.parent.debug["svd"]
+        except (KeyError, TypeError, IndexError) as e : pass
+        try: to_ret["debug"] = device.parent.debug["svd"]
+        except (KeyError, TypeError, IndexError) as e : pass
+        try: to_ret["debug"] = device.debug["svd"]
+        except (KeyError, TypeError, IndexError) as e : pass
+
+        to_ret["compile"] = {}
+        try: compile_l1 = device.parent("compile")
+        except (KeyError, TypeError, IndexError) as e : compile_l1 = []
+        try: compile_l2 = device.parent.parent("compile")
+        except (KeyError, TypeError, IndexError) as e : compile_l2 = []
+        compile = compile_l2 + compile_l1
+        for c in compile:
+            try: to_ret["compile"]["header"] = c["header"]
+            except (KeyError, TypeError, IndexError) as e : pass
+            try: to_ret["compile"]["define"] =  c["define"]
+            except (KeyError, TypeError, IndexError) as e : pass
+
+        try: to_ret["core"] = device.parent.processor['dcore']
+        except (KeyError, TypeError, IndexError) as e : pass
+        try: to_ret["core"] = device.parent.parent.processor['dcore']
+        except (KeyError, TypeError, IndexError) as e : pass
+
+        to_ret["processor"] = {}
+        try: proc_l1 = device("processor")
+        except (KeyError, TypeError, IndexError) as e: proc_l1 = []
+        try: proc_l2 = device.parent("processor")
+        except (KeyError, TypeError, IndexError) as e: proc_l2 = []
+        try: proc_l3 = device.parent.parent("processor")
+        except (KeyError, TypeError, IndexError) as e: proc_l3 = []
+        proc = proc_l3 + proc_l2 + proc_l1
+        for p in proc:
+            try: to_ret["processor"]["fpu"] = p['dfpu']
+            except (KeyError, TypeError, IndexError) as e: pass
+            try: to_ret["processor"]["endianness"] = p['dendian']
+            except (KeyError, TypeError, IndexError) as e: pass
+            try: to_ret["processor"]["clock"] = p['dclock']
+            except (KeyError, TypeError, IndexError) as e: pass
+
+        try: to_ret["vendor"] = device.parent['dvendor']
+        except (KeyError, TypeError, IndexError) as e: pass
+        try: to_ret["vendor"] = device.parent.parent['dvendor']
+        except (KeyError, TypeError, IndexError) as e: pass
+
+        if not to_ret["processor"]:
+            del to_ret["processor"]
+
+        if not to_ret["compile"]:
+            del to_ret["compile"]
+
+        to_ret['debug-interface'] = []
+
+        return to_ret
+
+    def _generate_index_helper(self, d) :
+        try :
+            pack = self.pdsc_to_pack(d)
+            self._index.update(dict([(dev['dname'], self._extract_dict(dev, d, pack)) for dev in
+                                    (self.pdsc_from_cache(d)("device"))]))
+        except AttributeError as e :
+            stderr.write("[ ERROR ] file {}\n".format(d))
+            print(e)
+        self.counter += 1
+        self.display_counter("Generating Index")
+
+    def _generate_aliases_helper(self, d) :
+        try :
+            mydict = []
+            for dev in self.pdsc_from_cache(d)("board"):
+                try :
+                    mydict.append((dev['name'], dev.mounteddevice['dname']))
+                except (KeyError, TypeError, IndexError) as e:
+                    pass
+            self._aliases.update(dict(mydict))
+        except (AttributeError, TypeError) as e :
+            pass
+        self.counter += 1
+        self.display_counter("Scanning for Aliases")
+
+    def get_flash_algorthim_binary(self, device_name, all=False) :
+        """Retrieve the flash algorithm file for a particular part.
+
+        Assumes that both the PDSC and the PACK file associated with that part are in the cache.
+
+        :param device_name: The exact name of a device
+        :param all: Return an iterator of all flash algos for this device
+        :type device_name: str
+        :return: A file-like object that, when read, is the ELF file that describes the flashing algorithm
+        :return: A file-like object that, when read, is the ELF file that describes the flashing algorithm.
+                 When "all" is set to True then an iterator for file-like objects is returned
+        :rtype: ZipExtFile or ZipExtFile iterator if all is True
+        """
+        device = self.index[device_name]
+        pack = self.pack_from_cache(device)
+        algo_itr = (pack.open(path) for path in device['algorithm'].keys())
+        return algo_itr if all else algo_itr.next()
+
+    def get_svd_file(self, device_name) :
+        """Retrieve the flash algorithm file for a particular part.
+
+        Assumes that both the PDSC and the PACK file associated with that part are in the cache.
+
+        :param device_name: The exact name of a device
+        :type device_name: str
+        :return: A file-like object that, when read, is the ELF file that describes the flashing algorithm
+        :rtype: ZipExtFile
+        """
+        device = self.index[device_name]
+        pack = self.pack_from_cache(device)
+        return pack.open(device['debug'])
+
+    def generate_index(self) :
+        self._index = {}
+        self.counter = 0
+        do_queue(Reader, self._generate_index_helper, self.get_urls())
+        with open(LocalPackIndex, "wb+") as out:
+            self._index["version"] = "0.1.0"
+            dump(self._index, out)
+        stdout.write("\n")
+
+    def generate_aliases(self) :
+        self._aliases = {}
+        self.counter = 0
+        do_queue(Reader, self._generate_aliases_helper, self.get_urls())
+        with open(LocalPackAliases, "wb+") as out:
+            dump(self._aliases, out)
+        stdout.write("\n")
+
+    def find_device(self, match) :
+        choices = process.extract(match, self.index.keys(), limit=len(self.index))
+        choices = sorted([(v, k) for k, v in choices], reverse=True)
+        if choices : choices = list(takewhile(lambda t: t[0] == choices[0][0], choices))
+        return [(v, self.index[v]) for k,v in choices]
+
+    def dump_index_to_file(self, file) :
+        with open(file, "wb+") as out:
+            dump(self.index, out)
+
+    @property
+    def index(self) :
+        """An index of most of the important data in all cached PDSC files.
+
+        :Example:
+
+        >>> from ArmPackManager import Cache
+        >>> a = Cache()
+        >>> a.index["LPC1768"]
+        {u'algorithm': {u'RAMsize': u'0x0FE0',
+                u'RAMstart': u'0x10000000',
+                u'name': u'Flash/LPC_IAP_512.FLM',
+                u'size': u'0x80000',
+                u'start': u'0x00000000'},
+         u'compile': [u'Device/Include/LPC17xx.h', u'LPC175x_6x'],
+         u'debug': u'SVD/LPC176x5x.svd',
+         u'pdsc_file': u'http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc',
+         u'memory': {u'IRAM1': {u'size': u'0x8000', u'start': u'0x10000000'},
+                     u'IRAM2': {u'size': u'0x8000', u'start': u'0x2007C000'},
+                     u'IROM1': {u'size': u'0x80000', u'start': u'0x00000000'}}}
+
+
+        """
+        if not self._index :
+            with open(LocalPackIndex) as i :
+                self._index = load(i)
+        return self._index
+    @property
+    def aliases(self) :
+        """An index of most of the important data in all cached PDSC files.
+
+        :Example:
+
+        >>> from ArmPackManager import Cache
+        >>> a = Cache()
+        >>> a.index["LPC1768"]
+        {u'algorithm': {u'RAMsize': u'0x0FE0',
+                u'RAMstart': u'0x10000000',
+                u'name': u'Flash/LPC_IAP_512.FLM',
+                u'size': u'0x80000',
+                u'start': u'0x00000000'},
+         u'compile': [u'Device/Include/LPC17xx.h', u'LPC175x_6x'],
+         u'debug': u'SVD/LPC176x5x.svd',
+         u'pdsc_file': u'http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc',
+         u'memory': {u'IRAM1': {u'size': u'0x8000', u'start': u'0x10000000'},
+                     u'IRAM2': {u'size': u'0x8000', u'start': u'0x2007C000'},
+                     u'IROM1': {u'size': u'0x80000', u'start': u'0x00000000'}}}
+
+
+        """
+        if not self._aliases :
+            with open(LocalPackAliases) as i :
+                self._aliases = load(i)
+        return self._aliases
+
+    def cache_everything(self) :
+        """Cache every PACK and PDSC file known.
+
+        Generates an index afterwards.
+
+        .. note:: This process may use 4GB of drive space and take upwards of 10 minutes to complete.
+        """
+        self.cache_pack_list(self.get_urls())
+        self.generate_index()
+        self.generate_aliases()
+
+    def cache_descriptors(self) :
+        """Cache every PDSC file known.
+
+        Generates an index afterwards.
+
+        .. note:: This process may use 11MB of drive space and take upwards of 1 minute.
+        """
+        self.cache_descriptor_list(self.get_urls())
+        self.generate_index()
+        self.generate_aliases()
+
+    def cache_descriptor_list(self, list) :
+        """Cache a list of PDSC files.
+
+        :param list: URLs of PDSC files to cache.
+        :type list: [str]
+        """
+        self.total = len(list)
+        self.display_counter("Caching Files")
+        do_queue(Reader, self.cache_file, list)
+        stdout.write("\n")
+
+    def cache_pack_list(self, list) :
+        """Cache a list of PACK files, referenced by their PDSC URL
+
+        :param list: URLs of PDSC files to cache.
+        :type list: [str]
+        """
+        self.total = len(list) * 2
+        self.display_counter("Caching Files")
+        do_queue(Reader, self.cache_pdsc_and_pack, list)
+        stdout.write("\n")
+
+    def pdsc_from_cache(self, url) :
+        """Low level inteface for extracting a PDSC file from the cache.
+
+        Assumes that the file specified is a PDSC file and is in the cache.
+
+        :param url: The URL of a PDSC file.
+        :type url: str
+        :return: A parsed representation of the PDSC file.
+        :rtype: BeautifulSoup
+        """
+        dest = join(self.data_path, strip_protocol(url))
+        with open(dest, "r") as fd :
+            return BeautifulSoup(fd, "html.parser")
+
+    def pack_from_cache(self, device) :
+        """Low level inteface for extracting a PACK file from the cache.
+
+        Assumes that the file specified is a PACK file and is in the cache.
+
+        :param url: The URL of a PACK file.
+        :type url: str
+        :return: A parsed representation of the PACK file.
+        :rtype: ZipFile
+        """
+        return ZipFile(join(self.data_path,
+                            strip_protocol(device['pack_file'])))
+
+    def gen_dict_from_cache() :
+        pdsc_files = pdsc_from_cache(RootPackUrl)
+
+    def cache_and_parse(self, url) :
+        """A low level shortcut that Caches and Parses a PDSC file.
+
+        :param url: The URL of the PDSC file.
+        :type url: str
+        :return: A parsed representation of the PDSC file.
+        :rtype: BeautifulSoup
+        """
+        self.cache_file(url)
+        return self.pdsc_from_cache(url)
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/__init__.pyc
new file mode 100755
index 0000000..f41e7a6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/aliases.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/aliases.json
new file mode 100755
index 0000000..557a37f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/aliases.json
@@ -0,0 +1 @@
+{"nRF51 PCA10028": "nRF51422_xxAC", "SAM4L-EK": "ATSAM4LC4C", "Apollo1 EVB": "APOLLO512-KBR", "NuTiny-SDK-M451": "M453VG6AE", "NuTiny-SDK-M0518": "M0518SD2AE", "STM32L073Z-EVAL": "STM32L073VZ", "TLE9879 EvalKit": "TLE9879QXA40", "STM32F401C-Discovery": "STM32F401VC", "NuTiny-SDK-M051": "M0516LDE", "Z32F0640100KITG": "Z32F06410AES", "SAMD51-XPRO": "ATSAMD51P20A", "NuTiny-SDK-NANO112": "NANO112VC2AN", "XMC4500 Relax Kit": "XMC4500-F100x1024", "TWR-K22F120M": "MK22FN512xxx12", "MCB1200": "LPC1227FBD64/301", "DB-MAX71637": "MAX71637", "XMC 2Go": "XMC1100-Q024x0064", "STM32H743I-EVAL": "STM32H743XI", "NUCLEO-L152RE": "STM32L152RE", "TWR-KV10Z32": "MKV10Z32xxx7", "XMC4800 Automation Board": "XMC4800-E196x2048", "FRDM-KW40Z": "MKW40Z160xxx4", "NuTiny-SDK-NM1200": "NM1200LBAE", "TWR-K70F120M": "MK70FN1M0xxx12", "STM32F769I-Discovery": "STM32F769NIHx", "TWR-KE18F": "MKE18F512xxx16", "MCBSTM32F400": "STM32F407IG", "SAML21-XPRO": "ATSAML21J18A", "STM32F030-Discovery": "STM32F030R8", "SAMA5D2-XULT": "ATSAMA5D27", "Apollo EVK": "APOLLO512-KBR", "NuTiny-SDK-NUC505": "NUC505YO13Y", "NuTiny-SDK-M058S": "M058SSAN", "TRK-KEA8": "SKEAZN8xxx4", "MCB1700": "LPC1758", "V2M-MPS2": "CMSDK_CM7", "MCB54110": "LPC54114J256BD64", "LPC1788-32 Developers Kit": "LPC1788", "Z32F1280100KITG": "Z32F12811ARS", "NuTiny-SDK-NUC472": "NUC472HI8AE", "EFM32GG-DK3750": "EFM32GG990F1024", "Colibri-VF50": "MVF50NN15xxxx40", "MCBSTM32F200": "STM32F207IG", "EVAL-ADuCM322EBZ": "ADuCM322", "FRDM-KL25Z": "MKL25Z128xxx4", "SN32F707B Starter Kit Rev1_0": "SN32F70*B", "NUCLEO-F446RE": "STM32F446RE", "NuTiny-SDK-NANO103": "NANO103SD3AE", "MCBNUC1xx": "NUC140VE3AN", "MCB11C14": "LPC11C14FBD48/301", "FRDM-KL02Z": "MKL02Z32xxx4", "Colibri-iMX7": "MCIMX7D7", "NuTiny-SDK-Mini55": "Mini54XZAE", "NuTiny-SDK-Mini57": "Mini57TDE", "SAM3S-EK": "ATSAM3S4C", "SF2_DEV_KIT": "M2S050", "NuTiny-SDK-NANO100BN": "NANO130KE3BN", "NuTiny-SDK-Mini58": "Mini58LDE", "uVision Simulator": "ARMCM0", "FRDM-K28F": "MK28FN2M0xxx15", "TRK-KEA64": "SKEAZN64xxx2", "XMC1200 Boot Kit": "XMC1201-T038x0200", "N5 Starter Kit": "nRF51422_xxAA", "Core031C_Board": "MM32x031", "EFM32HG-SLSTK3400A": "EFM32HG322F64", "EVAL-ADuCM320EBZ": "ADuCM320", "ADSP-CM419F EZ-BOARD M4": "ADSP-CM419F-BCZ_M4", "NOVPEK-iMX7": "MCIMX7D7", "XMC4700 Relax Kit": "XMC4700-F144x2048", "SAMG55-XPRO": "ATSAMG55J19", "Fixed Virtual Platform": "ARMCA5", "SAMHA1G16A-XPRO": "ATSAMHA1G16A", "FRDM-KE06Z": "MKE06Z128xxx4", "NUCLEO-F072RB": "STM32F072RB", "NuTiny-SDK-NUC100": "NUC100VE3DN", "MCBTMPM360": "TMPM362F10FG", "NuTiny-SDK-NUC121": "NUC121SC2AE", "NuTiny-SDK-NUC029AE": "NUC029FAE", "NuTiny-SDK-M0564": "M0564VG4AE", "V2M-MPS2 (IoT)": "IOTKit_ARMv8MML", "ADuCM4050 EZ-KIT": "ADuCM4050", "FRDM-K20D50M": "MK20DX128xxx5", "STM32756G-EVAL": "STM32F756NGHx", "SAM4L-XPRO": "ATSAM4LC4C", "FRDM-KL43Z": "MKL43Z256xxx4", "nRF52 PCA10036": "nRF52832_xxAA", "TWR-KV11Z75M": "MKV11Z128xxx7", "NuTiny-SDK-NUC029AN": "NUC029TAN", "TWR-VF65GS10": "MVF61NS15xxxx50", "TWR-KM34Z50": "MKM34Z128xxx5", "STM32L-Discovery": "STM32L152RB", "AC30M1464 MINI B/D": "AC30M1464", "IMX7-PHYBOARD-ZETA": "MCIMX7D7", "XMC1100 Boot Kit": "XMC1100-T038x0064", "TWR-KV46F150M": "MKV46F256xxx16", "Koala EVM": "STM32F429II", "EFM32WG-STK3800": "EFM32WG990F256", "MCB1313": "LPC1313FBD48", "NuTiny-SDK-M480": "M487JIDAE", "TWR-K65F180M": "MK65FN2M0xxx18", "EB_TMPM369FDFG": "TMPM369FDFG", "TS-R-IN32M3-EC": "R-IN32M3-EC", "XMC4300 Relax Kit": "XMC4300-F100x256", "LPCXpresso54114": "LPC54114J256BD64", "STM32F429I-Discovery": "STM32F429ZI", "Colibri-VF61": "MVF61NN15xxxx50", "NUCLEO-F091RC": "STM32F091RC", "SAMV71-XULTRA": "ATSAMV71Q21", "FRDM-KW41Z": "MKW41Z512xxx4", "TWR-KL43Z48M": "MKL43Z256xxx4", "STM32373C-EVAL": "STM32F373VC", "QN908XDK": "QN9080A", "STM32F746G-Discovery": "STM32F746NGHx", "TWR-K24F120M": "MK24FN256xxx12", "nRF52 PCA10040": "nRF52832_xxAA", "MCBSTM32C": "STM32F107VC", "FRDM-KL03Z": "MKL03Z32xxx4", "MCBSTM32E": "STM32F103ZG", "NUCLEO-F401RE": "STM32F401RE", "SF2_EVAL_KIT": "M2S025", "STM32303C-EVAL": "STM32F303VC", "AC33MA384A MINI B/D": "AC33MA384A", "SAML22-XPRO": "ATSAML22N18A", "XMC4800 Relax EtherCAT Kit": "XMC4800-F144x2048", "iMX7-Dual-COM": "MCIMX7D7", "TRK-KEA128": "SKEAZ128xxx4", "SAM4S-EK": "SAM4S16C", "TWR-K20D50M": "MK20DX128xxx5", "STM32F3-Discovery": "STM32F303VC", "LPCXpresso1125": "LPC1125JBD48/303", "STM32F4-Discovery": "STM32F407VG", "CMSIS_RTOS_Tutorial": "STM32F103RB", "SAM3X-EK": "ATSAM3X8H", "SF2_ADV_DEV_KIT": "M2S150", "SN32F760 Starter Kit Rev1_1": "SN32F76*", "Core103R_Board": "MM32x103", "NuTiny-SDK-Mini51": "Mini54LDE", "Apollo2 EVB": "AMAPH1KK-KBR", "FRDM-KE04Z": "MKE04Z8xxx4", "NuTiny-SDK-NUC123": "NUC123SD4AN0", "TWR-KL28Z72M": "MKL28Z512xxx7", "Apollo2 EVK": "AMAPH1KK-KBR", "LPC4330-Xplorer": "LPC4330", "NuTiny-SDK-NUC126": "NUC126VG4AE", "MCBTMPM330": "TMPM330FDFG", "NUCLEO-L476RG": "STM32L476RG", "STM32F334-Discovery": "STM32F334C8", "MCB1800": "LPC1850", "EFM32GG-STK3700": "EFM32GG990F1024", "GD32150C-START": "GD32F150C8", "AC33GA256 MINI B/D": "AC33GA256", "TS-R-IN32M3-CL": "R-IN32M3-CL", "TS-R-IN32M3-CEC": "R-IN32M3-EC", "EVAL-ADuCM320iQSPZ": "ADuCM320i", "AC33M8128/6128 MINI B/D": "AC33M8128", "SAM4S-XPRO": "ATSAM4SD32C", "STM32L053-Discovery": "STM32L053C8", "TWR-KM34Z50MV3": "MKM34Z128Axxx5", "PAC52XX EVK": "PAC52XX", "XMC4500 CPU Board - General Purpose (CPU_45A)": "XMC4500-F144x1024", "NuTiny-SDK-NUC122": "NUC122SD2AN", "Z32F3840100KITG": "Z32F38412ALS", "LPCXpresso54608": "LPC54608J512BD208", "MCIMX7ULP-EVK": "MCIMX7U5", "LPC824 LPCXpresso": "LPC824M201JHI33", "STM32439I-EVAL": "STM32F439NI", "EFM32TG-STK3300": "EFM32TG840F32", "AC33M4064/3064 MINI B/D": "AC33M4064", "NUCLEO-F030R8": "STM32F030R8", "NuTiny-SDK-NUC131": "NUC131SD2AE", "DK-TM4C129x": "TM4C129XNCZAD", "STM32F769I-EVAL": "STM32F769NIHx", "SF2_STARTER_KIT": "M2S010", "nRF51 PCA20006": "nRF51822_xxaa", "TS-R-IN32M4-CL2": "R-IN32M4-CL2", "MCIMX6SX-SABRE": "MCIMX6X1", "EVAL-ADICUP3029": "ADuCM3029", "SAM4C-EK": "ATSAM4C16C", "MCB1500": "LPC1549JBD100", "TWR-KW21D256": "MKW21D256xxx5", "STM32L476G-EVAL": "STM32L476ZG", "MCIMX7D-SABRE": "MCIMX7D7", "STM32F051-Discovery": "STM32F051R8", "NUCLEO-L053R8": "STM32L053R8", "FRDM-K64F": "MK64FN1M0VLL12", "TLE9869 EvalKit": "TLE9869QXA20", "NuTiny-SDK-NUC240": "NUC240VE3AE", "LPC84x LPCXpresso": "LPC845M301JBD64", "S32K144-EVB": "S32K144UAT0xxxx", "SAMD20-XPRO": "ATSAMD20J18", "SN32F770 Starter Kit Rev1_0": "SN32F70*B", "SAM4E-EK": "SAM4E16C", "MCB1343": "LPC1343FBD48", "LinkIt 7687 development board": "MT7687F", "XMC4500 CPU Board - General Purpose (CPU_45B)": "XMC4500-E144x1024", "SAM3N-EK": "ATSAM3N4C", "LinkIt 2523 development board": "MT2523x", "SAM3U-EK": "ATSAM3U4E", "ADSP-CM419F EZ-BOARD M0": "ADSP-CM419F-BCZ_M0", "ADuCM3029 EZ-KIT": "ADuCM3029", "NuTiny-SDK-NUC200": "NUC220VE3AN", "FRDM-KL82Z": "MKL81Z128xxx7", "XMC1300 Boot Kit": "XMC1302-T038x0200", "Bulb Board": "S6E1A12B0A", "MCBTMPM395": "TMPM395FWAXBG", "STM32F072-Discovery": "STM32F072RB", "BMSKTOPASM369": "TMPM369FDFG", "LPCXpresso54102": "LPC54102J512BD64", "NuTiny-SDK-NANO100AN": "NANO100VD3AN", "TWR-K60D100M": "MK60DN512xxx10", "TWR-K20D72M": "MK20DX256xxx7", "nRF51 PCA10031": "nRF51422_xxAC", "EK-TM4C1294XL": "TM4C1294NCPDT", "SK-FM3-176PMC-ETHERNET": "MB9BFD18T", "LPC4088-32 Developers Kit": "LPC4088FET208", "FRDM-KW36": "MKW36A512xxx4", "TLE984x Eval.Board": "TLE9844QX", "XMC4500 Relax Lite Kit": "XMC4500-F100x1024", "iMX6-SoloX-COM": "MCIMX6X4", "SAME70-XPLD": "ATSAME70Q21", "LPCXpresso11U68": "LPC11U68JBD100", "XMC4400 CPU Board - General Purpose  (CPU_44A)": "XMC4400-F100x512", "NUCLEO-F103RB": "STM32F103RB", "EFM32ZG-STK3200": "EFM32ZG222F32", "XMC1400 Boot Kit": "XMC1402-Q040x0128", "MCBTWRK60": "MK60DN512xxx10", "MCB9B500": "MB9BF506R", "Z32F0642100KITG": "Z32F06423AKE", "ADSP-CM419F EZ-BOARD": "ADSP-CM419F", "LPC812 LPCXpresso": "LPC812M101JDH20", "TWR-KL82Z72M": "MKL82Z128xxx7", "SN32F100 Starter Kit": "SN32F10*", "NuTiny-SDK-M0519": "M0519VE3AE", "TWR-K64F120M": "MK64FN1M0xxx12", "MCB4300": "LPC4350", "XMC4200 CPU Board - Actuator  (CPU_42A)": "XMC4200-F64x256", "EVAL-ADuCM360MKZ": "ADuCM360"}
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/index.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/index.json
new file mode 100755
index 0000000..f9c50df
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/index.json
@@ -0,0 +1 @@
+{"S6E2H16E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H16G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKE16F512xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKE16F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1290NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC029LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC120LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMA5D26": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D26.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D27": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D27.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D24": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D24.svd", "processor": {"fpu": "DP_FPU"}}, "S6E2H16F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMA5D22": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D22.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D23": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D23.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F417IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMA5D21": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D21.svd", "processor": {"fpu": "DP_FPU"}}, "MB9BF317S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG390F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG390F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF317T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MK24FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK24F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "AMAPH1KK-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NANO130SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F423RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MK60DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "N572P072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "MB9BF106R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF415N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF106N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F722RC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMC21J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4300-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4300_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4300c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4300_series/Include/XMC4300.h", "define": "XMC4300_F100x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x0FFC0"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4300.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM383FSEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "AC30M1364": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG230F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG230F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F109F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM383FWEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F411RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LM3S6422": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6422.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S6420": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6420.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S2965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC100RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S600": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s600.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD09C13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD09_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD09\\ATSAMD09C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK22FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM066FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M066.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F412VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO100ND2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "XMC1201-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Mini57EDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F105RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF328S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF328T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK26FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK26F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11U24FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TLE9879QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MKV11Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV11Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M452LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L451CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1402-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK02FN64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK02F12810.h", "define": "MK02FN64xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK02F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "XMC1301-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKS20FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKS20F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF529T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "Z32F06410AES": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF166R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF529S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "GD32F150G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG232F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG232F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK63FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK63F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC230VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F150G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMA5D28": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D28.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F071RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO130KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LPC11U35FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMv8MML_DSP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MKL46Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL46Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M4TKRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32LG295F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG295F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC18S50": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "TLE9844QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9844.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xF000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "ATSAML21E18B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21E18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF128S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM395FWAXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM395_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9BF128T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK22DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S308": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s308.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "nRF51422_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "ATSAM3A8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3A8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "nRF51422_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F722IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F722IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TM4C1237H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM061FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M061.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F756NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32HG220F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F767IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1202-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK52DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK52D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG220F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F767II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7661BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L496RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG220F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ARMSC000": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMSC000/Include/ARMSC000.h", "define": "ARMSC000"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC000.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM462F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK82FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK82F25615.h", "define": "MK82FN256xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK82F25615.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MKE04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": "0x400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE04Z1284.h", "define": "MKE04Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKE04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129DNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32L475RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F766J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "S6E2CC8J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TM4C1230C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1230C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F121E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F121E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32L031C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L031C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5G36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F410CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAML22G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1292NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ISD9160": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "EZR32WG230F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L486VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32WG230F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK22F25612.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1102LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1115JET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV30F64xxx10": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV30F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MK20DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F446ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F302CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F446ZC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1301-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG990F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG990F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MKE14Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE14Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKE16F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE16F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F303VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F777BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG295F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG295F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1236D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1236D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32WG230F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1102UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG330F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG330F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL05Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM376FDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MAX71617": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71616": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "NANO120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32TG230F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG230F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1100-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AFB42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Z32F06423EKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TLE9873QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9873.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100AFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0xAFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM342FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM342_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00009000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM380FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TLE9845QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9845.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xB000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG942F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG942F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK64FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO130SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9BF429S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "GD32F407IE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TLE9867QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "M452VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM4F122H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC200SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32LG330F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG330F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1778": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F122H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F411RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1774": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1777": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1776": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F411CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L100R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC240SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2C29H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG390F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG390F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5752": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5752.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M4TKVG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NM1120XB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "Mini54ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "MT2523x": {"core": "Cortex-M4", "vendor": "MediaTek:129", "algorithm": {"tools/keil/mt2523/2523_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x04008000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.5.0.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt2523/Include/mt2523.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x00400000"}, "IRAM2": {"start": "0x04008000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00400000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "208000000"}}, "S6E2DH5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC11A12FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "ATSAMD21G16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F378VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA1J14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1J14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LM4F111E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F111E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA1J14B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1J14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TMPM373FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M373.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M058LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F469BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1346FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2412": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2412.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "MK30DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ARMv8MML_DSP_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM067FWQG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M067.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC220LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG822F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG822F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C129XNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129XNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMR21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F108F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C58J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M2S050": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "S6E2C3AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L486JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F407VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32G880F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G880F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G880F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F407VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX7D2": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D2_A7.svd", "processor": {"fpu": "SP_FPU"}}, "MCIMX7D5": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D5_A7.svd", "processor": {"fpu": "SP_FPU"}}, "MCIMX7D7": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D7_A7.svd", "processor": {"fpu": "SP_FPU"}}, "NANO112LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32LG895F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG895F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG990F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG990F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG980F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG980F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAME70J21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "TLE9842QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9842.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0x8000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC1317FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC131LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F479AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC4088FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC130LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F100RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1120TB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAML22G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F479ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M452RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMA5D35": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D35.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAM3U1C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "TM4C1231H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D36": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "GD32F450VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S2911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F038C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG895F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG895F1024"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG895F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EZR32WG330F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11U12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F412RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M052ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F469ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC442KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EFM32G290F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G290F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G290F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1232D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1232D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "Mini55TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC844M201JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "NM1200ZBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F423VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L433CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK22FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M052ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F190T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC230SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV71N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV71N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFM32LG990F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG990F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L432KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L432KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK11DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK11D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L051K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L081CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL28Z512xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_KL28.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MKL28Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF112R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM368FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11C22FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKS22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKS22F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32LG230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO102SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "NUC472VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "S6E2C38H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NM1120FC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "XMC1302-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4104-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF314R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMC20G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG942F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG942F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK50DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMD21E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAM4SD32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD32B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L443RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F302ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG900F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG900F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F706J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F112E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F112E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG942F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG942F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DH5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF105N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451MRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAMD09D14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD09_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD09\\ATSAMD09D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM367FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F150R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L476ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F228F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L476ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F100ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "GD32F150R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5D56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5791": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5791.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF464K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1937": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1937.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F121H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F121H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF464L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG890F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG890F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG980F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG980F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "TM4C123FH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123FH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F210E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F210E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1114FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C1AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC11E67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4315": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4317": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4310": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "ATSAM3S2C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM4F232H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4313": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "ATSAMD21J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2B93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2b93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S1968": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1968.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF528T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF528S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32G880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G880F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1823EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK22FN512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F51212.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151UC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M451MRD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L462VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF341L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF341M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF341N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF465K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1224FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LPC11E11FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC126VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MVF62NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF62NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF406R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F102CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF406N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M0518SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1225FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S5P36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5P31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C18H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NANO120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EFM32G842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G842F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F413RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32JG12B500F512GL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F512GL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC120RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "S6E2C19L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAME54P19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKL02Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "Generic_NUC400_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TM4C1294KCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1294KCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1402-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F401RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32GG840F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG840F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFR32BG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F707BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4700-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9BN2": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2HE4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L431KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L431KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9BN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC100VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "Generic_NUC200_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F051T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1120EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMDA0E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MBL/Include/ARMv8MBL.h", "define": "ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "Mini52TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "XMC1301-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G200F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32G/EFM32G200F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO120SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "SN32F765J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51J19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKW21D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5P3B": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1768": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1769": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM366FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1763": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "Mini52FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F101C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1766": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1767": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32GG380F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG380F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1765": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S5747": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5747.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_CM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L475JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC220SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11U35FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F378CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF467M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1785": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1786": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1787": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U2C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x000020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x000004000"}, "IRAM2": {"start": "0x20080000", "size": "0x000004000"}, "IROM1": {"start": "0x00080000", "size": "0x000020000"}}, "debug": "SVD/SAM3U/ATSAM3U2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32L063R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1788": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC4200-Q48x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMHA1G14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00010000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.0.0.pack", "compile": {"header": "Device/SAMHA1/Include/samha1.h", "define": "__SAMHA1G16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000200"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/SAMHA1/ATSAMHA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "N572F072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "MCIMX7U5": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U5_A7.svd", "processor": {"fpu": "SP_FPU"}}, "NUC121ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MCIMX7U3": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U3_A7.svd", "processor": {"fpu": "SP_FPU"}}, "STM32L071RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F121C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F121C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG940F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG940F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F131H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F131H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L071RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM376FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32H743VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L471RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC100RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L471RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC240SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F091CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC442KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "LPC11U34FHN33/311": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC220LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9AFB41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F412CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32LG980F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG980F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1114FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123BE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM367FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11C24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG360F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG360F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L071V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG350F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG350F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F215VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F215VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S1F11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK65FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK65F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4LS8A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC812M101JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "M452VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F479ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF315R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9AF312K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32HG321F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG321F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11E14FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG12B500F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK20FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451MLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F778AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMC21J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini51LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC11A14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1G21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1g21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L053C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMR21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S37": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "S6E2D55GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L053C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S30": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1231H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32W108CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F756IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TM4C1231H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK10FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F413CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32LG230F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F207VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC20J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMV71N21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMV71N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMV71N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV71N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ARMCM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM372FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG890F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG890F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F231E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F231E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM3N1C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9879QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L021K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM368FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F301C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK21DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK21DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F301C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "S6E1A11B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAM4LC8A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3748": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3748.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4LC8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF321K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM037FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M037.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKL26Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2GK6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F437ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV42F128xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV42F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F437ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1517JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "NUC120LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2H14F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1403-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54606J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EFM32TG110F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1237E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M0518SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMC21E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6X4": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC1112FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6X1": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X3": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "S6E2D35GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32G232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G232F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1200TBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1401-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C5AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F103ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC20N18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20N/ATSAMC20N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF512R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S3634": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C123AE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123AE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2GM6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L051T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2GM6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini51LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F103V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF512N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S1850": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1850.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG280F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG280F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20N17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20N/ATSAMC20N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4320": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4323": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4322": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4325": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F302CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1654": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1655": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1656": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO110SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EFM32GG940F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG940F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51422_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F1653": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5K31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD51J18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F777VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "Mini57TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG880F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG880F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ADSP-CM419F-BCZ_M4": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "0", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M4/CM41x_M4_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.pdsc", "memory": {"IROM2": {"start": "0x11001000", "size": "0x000FF000"}, "IRAM1": {"start": "0x10000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20010000", "size": "0x00018000"}, "IROM1": {"start": "0x11000000", "size": "0x00001000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S5G56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1404-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADSP-CM419F-BCZ_M0": {"core": "Cortex-M0", "vendor": "Analog Devices:1", "algorithm": {}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x200F0000", "size": "0x00008000"}}, "debug": "SVD/CM41x_M0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F446VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F227F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F446VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F412RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM367FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC200SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F245J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3A4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3A4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMD11C13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F229F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG895F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG895F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "Z32F12811ARS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C28J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F417ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC4072FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC11E36FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3S2B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "NUC120RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG232F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG232F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C59H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F1251": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1252": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1253": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x7C00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG225F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG225F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF465L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "Mini51TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAM4CMP32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMP32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F302C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32PG1B200F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1402-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5C31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F302C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C129LNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129LNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM462F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4400-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1301-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DF5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM370FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG395F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG395F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M485KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TLE9867QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "LM4F131E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F131E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO112VC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "NM1820EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C123GE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C29J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4LC2C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG895F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG895F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L433RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG880F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG880F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK40DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SKEAZN16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO110KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9AF311K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM366FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG840F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG840F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M451MRC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "Mini58LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L071C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M052LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M052LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M0519SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC131SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD10D13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4088FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL04Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G280F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F773S": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F773T": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G210F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G210F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G210F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MAX71637": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71636": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "STM32F030CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG840F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG840F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM440_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "LM4F111B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F111B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD11D14AM": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE18F512xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKE18F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD11D14AS": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21N18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21N/ATSAMC21N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0519VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C1294NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A04UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAME51J18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "TM4C129CNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1403-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F122E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F122E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S9L71": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l71.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Z32F12811ATS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG380F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG380F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMS70J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC11U35FET48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "AC33MA384A": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33MA384A/Flashloader/AC33Mx384A_384.flm": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33MA384A\\Core\\include\\AC33Mx384A.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33MA384A\\SVD\\AC33Mx384A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "M0564LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32HG308F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG308F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1549JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M052ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L151RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3X4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "LPC11E67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG890F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M481LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD21G18AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G28J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F732VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL16Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G230F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F078CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3826": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s3826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKE02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKE02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L471QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC43S20": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32LG980F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG980F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F405ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S9B95": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b95.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F405ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S9B96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32G230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G230F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK21DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L051R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4108-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L051R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F303RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F048G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F303RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM33Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF114R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "PAC5250": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H46F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2D35J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG895F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG895F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG880F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG880F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM461_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L452VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG222F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54616J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAME70Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70Q21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L452VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9GN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9gn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1231C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1231C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG825F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG825F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F303R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M0516LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF312R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F303R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC230RC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F469NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32LG890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC1224FBD64/121": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC4104-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1302-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F722ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMDA0J14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD64/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F746VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M451MSD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "GD32F130K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F407ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F407ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM365FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M365.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5G31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "CMSDK_CM0plus": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM0plus/Include/CMSDK_CM0plus.h", "define": "CMSDK_CM0plus"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0plus.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "GD32F130K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1510LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC54S616J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F302R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L073VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F302R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C129DNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F246J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6Y1": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y0": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32L073VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F779NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F427IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F072CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF524K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF524L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF524M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF466N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMR21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5B91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5b91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DL13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "NM1820ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF466R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG995F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG995F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC442VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EZR32WG330F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4C16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MK21FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG995F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG995F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG842F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG842F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "ATSAME53N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "TM4C123GH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG220F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF164K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F072C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123ZD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32GG232F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG232F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L073V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD10C13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF116T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAM4SA16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SA16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG290F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG290F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F030K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF568M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC845M301JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MB9BF404R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C4AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF404N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4800-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9DN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11E12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2G36J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2G36H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKM14Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F758F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1958": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1958.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "M4LEDLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG842F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG842F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51802_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32L475ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKV10Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV10Z1287.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "DS_CM3": {"core": "Cortex-M3", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.1.0.0.pack", "compile": {"header": "Device/DS_CM3/Include/DS_CM3.h", "define": "DS_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.pdsc", "memory": {}, "debug": "SVD/DS_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF428T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LPC4330": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "SN32F774T": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F774S": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ARMv8MML_DSP_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MKL04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F132H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F132H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051R4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F415OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F051R6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV46F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV46F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F358VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32G200F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G200F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1225FBD64/321": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S8738": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8738.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "nRF51824_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "MKV10Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV10Z1287.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "STM32F038K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S8733": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8733.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L152C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF366R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9AFA44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M452LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32TG840F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG840F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4800-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "NANO100SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S8933": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8933.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NM1823ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S8930": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8930.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C19J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG232F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG232F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC123SD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TM4C129ENCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1345FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MCIMX7S5": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S5_A7.svd", "processor": {"fpu": "SP_FPU"}}, "STM32F205VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG232F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG232F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MCIMX7S3": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S3_A7.svd", "processor": {"fpu": "SP_FPU"}}, "ATSAM3U4E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M451VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M052ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1112FHI33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM4050": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADuCM4x50.FLM": {"default": "1", "ramsize": null, "size": "0x7F000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.1.0.0.pack", "compile": {"header": "Include/ADuCM4050.h", "define": "__ADUCM4050__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x7F000"}}, "debug": "SVD/ADuCM4050.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "52000000"}}, "LPC54607J256BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EZR32HG220F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1100FBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32HG220F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1850": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F236J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32HG320F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM4": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "EZR32HG220F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM0": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM0/Include/CMSDK_CM0.h", "define": "CMSDK_CM0"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TLE9861QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9861.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "CMSDK_CM3": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM3/Include/CMSDK_CM3.h", "define": "CMSDK_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF416T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "GD32F450IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32PG1B100F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F450IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M058LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F450II": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG900F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG900F256"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG900F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF121J": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B120J_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xJ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG290F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG290F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKV31F128xxx10": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV31F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NUC140RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1401-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK10FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF416R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM4F130C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F130C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3N00B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N00A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "S6E2G38H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2G38J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2HG4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54S618J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NM1820LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC4108-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5762": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5762.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKW41Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F038F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70J21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NANO100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "M481SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32ZG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG942F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG942F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG290F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG290F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK24FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK24F25612.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1225FBD48/321": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "ATSAME54N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L051C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKL15Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M2S005": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LPC11U34FBD48/311": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM374FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M374.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E1A12B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG230F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG230F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1403-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S57": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC43S50": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F429BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC140LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9AF141M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC4500-F144x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F767VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1202-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F413MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L485JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L485xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F413MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM3S1B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32L443CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32WG330F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKE02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG330F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F303C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAME51J19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EZR32WG330F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14F512xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKE14F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG390F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG390F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F091RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4088FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMV71Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV71Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F102RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G890F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G890F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G890F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2276": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2276.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2678": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2678.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1233C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1233C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM475FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54S616J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "TLE9844-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9844_2.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xF000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4700-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "ADuCM320i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320i.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M0516ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC1517JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32TG232F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG232F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F072RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2CC9L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F150C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33M6128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LPC1343FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2GK8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A12FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32JG1B200F256GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F150C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F415RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32LG895F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG895F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F071VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF565K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC120LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100NE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9AF344N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1120DC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "nRF51822_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F410T8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TLE9877QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF322L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF322M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ISD9360": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "M4TKLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKL46Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL46Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L062K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L062xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L062x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32HG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MKL24Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S3654": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U14FET48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S3651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M485SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "HT32F1251B": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0G14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF115R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAME70Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F103T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5U91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5u91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H46E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F103T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F437VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F101R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "S6E2DH5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F101R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LM3S1651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM330FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F437VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A02UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54S608J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NUC122ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "NUC131LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM384FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M384.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9AFA41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11C12FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L031G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L031G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C2AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MK53DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1104UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F225J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L073CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011G3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1114LVFHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NUC130RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32GG995F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG995F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F410RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9792": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9792.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG880F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG880F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM366FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F437II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4SP32A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4SP_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4SP/sam4sp.h", "define": "__SAM4SP32A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4SP/ATSAM4SP32A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG980F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG980F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK12DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK12D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F415ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9AF156R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1316FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK60FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC11U14FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F247F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827YB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L162RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L162RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32HG310F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG310F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMR21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF467R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F103ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C123GH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9AF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM068FWXBG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M068.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Z32F06410AKS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM330FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "AC33M8128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32H753ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32WG360F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG360F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F768F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK80FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK82F25615.h", "define": "MK82FN256xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK80F25615.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "NANO100SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TM4C1297NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1297NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F745IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F745IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "IOTKit_ARMv8MBL": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MBL/Include/IOTKit_ARMv8MBL.h", "define": "IOTKit_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "NUC200SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK20DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC824M201JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG12P431F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NANO100SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "M451YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F777ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM343FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM343_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S815": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s815.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L475VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMG51N18": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51N18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3N26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s3n26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG890F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG890F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG942F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG942F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129CNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC20E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32L151RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F103RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF405R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F107RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M4TKVE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L082KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F107RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C28H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF156N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "SKEAZN32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "SN32F759F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF405N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L082KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1115FET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F358CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFA31N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TMPM362F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M362.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG842F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG842F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG280F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG280F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM4S16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMG54J19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "NUC472HG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EFR32BG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32HG220F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF429T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "M052LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F378RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L152R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M481SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC100LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKV58F1M0xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x2F000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00100000"}}, "debug": "SVD/MKV58F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "HT32F52220": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "AC33GA256": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33GA256/Flashloader/AC33GA256_CDFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33GA256\\Core\\include\\AC33GA256.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33GA256\\SVD\\AC33GA256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32JG12B500F1024IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11A11FHN33/001": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1435": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005C00"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1435.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TMPM341FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM341_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "S6E2C2AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG360F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG360F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL33Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL33Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F217IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG350F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG350F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini54TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "TM4C123AH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123AH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H46G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C39H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NM1320LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1320_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1320_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1320_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NM1320AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO103SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1202-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4800-E196x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM364F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M364.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ARMCM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC812M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F413RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F038G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC120VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK20DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C3AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L053R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L053R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1549JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M0564RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F450ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F091CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450ZI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F405OE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MKL43Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMHA1G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00010000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.0.0.pack", "compile": {"header": "Device/SAMHA1/Include/samha1.h", "define": "__SAMHA1G16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMHA1/ATSAMHA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG222F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F450ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M2S010": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "XMC1302-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "nRF51801_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "NUC240VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L475QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK70FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG295F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG295F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G26J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L072RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF321M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF321L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM4F110C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F110C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L475QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK20DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO120LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MKE02Z64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C1236H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1236H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1112FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F767VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC1112FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F301R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC824M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F301R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L072RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAME51N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L051T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF116S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC54101J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E1A12C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32MG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG332F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG332F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32L152RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "NUC240SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC54114J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32GG295F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG295F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM333FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32LG330F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF218S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF218T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H743BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MB9AF131N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F423CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NUC126LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG825F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG825F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKE02Z32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L152R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M0519LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F706BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F303C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG995F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG995F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1232C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1232C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MVF50NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMC20J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D55GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM3X4E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "LPC4078FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M0518LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F031K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32HG108F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG108F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ARMCM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "NANO112SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "AC30M1332": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4S2A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S2B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S2C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "NANO120KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TMPM37AFSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M37A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF118S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF118T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC4078FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F058C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F746VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F031E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC200LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6633": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6633.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32GG380F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG380F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF121M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKE18F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE18F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG990F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG990F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C38L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG995F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG995F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F170R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF141N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F469NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF141L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L021F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3S1A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LPC54606J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAM3S1C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKL26Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "N572F065": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\N572F065_v3.svd", "processor": {"clock": "48000000"}}, "LPC844M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "S6E2H44F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F105V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L4A6ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H44E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54113J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MT7687F": {"core": "Cortex-M4", "vendor": "MediaTek:129", "algorithm": {"tools/keil/mt7687/7687_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.5.0.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt7687/Include/mt7687.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x00100000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00200000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "192000000"}}, "MKW35Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO103LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG395F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG395F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NM1200LBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11E36FHN33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC21E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L031F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO120KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32L031F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "BlueNRG-1": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STBlueNRG1.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x28000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.1.1.1.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x28000"}}, "debug": "SVD/BlueNRG1.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MCIMX7D3": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D3_A7.svd", "processor": {"fpu": "SP_FPU"}}, "NANO120SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9BF564L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO100ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9BF564K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9AFA31M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF156M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "R-IN32M3-EC": {"core": "Cortex-M3", "vendor": "Renesas:117", "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_EC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "AC33M4064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C123BH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1402-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F398VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4800-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKL14Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B200F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC122LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "STM32H753II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TM4C1299KCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1299KCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F756J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF312L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO130SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "HT32F1755": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini54XFHC": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKW20Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW20Z4.h", "define": "MKW20Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW20Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L052T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1224FBD48/121": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "TM4C1233E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4350": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F767BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4353": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO102LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "LPC4357": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "EFM32LG940F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG940F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKV42F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV42F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC54101J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4502-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F767BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1100FAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM343F10XBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM343_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV42F64xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV42F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MKM14Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F401VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54616J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F423MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKL34Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL34Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6G1": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G0": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G3": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC4327": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MB9BF366K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC505YLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "S6E2C58L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKS20FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKS20F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F120H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F120H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1138": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1138.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK60FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK60FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "EZR32LG230F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK21DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1133": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1133.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "APOLLO512-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32G842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G842F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK50DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F030F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMCM23": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "QN9083A": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "QN9083C": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC845M301JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAMC20G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG842F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG842F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKV56F512xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00080000"}}, "debug": "SVD/MKV56F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "NANO120LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "LM4F211E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F211E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U35FHI33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F745VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F745VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32JG1B200F128GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F217ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F217ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2533": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2533.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F733IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32LG395F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG395F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL26Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM367FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F110E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F110E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L471VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "LM3S1R21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21J16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG942F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG942F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK28FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x1FFC0000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK28F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "LPC11U34FBD48/421": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MCIMX6Y2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32BG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32HG322F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG322F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M452LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32ZG210F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC220VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1100-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC4402-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini51FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAMC20E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G232F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1F16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4402-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C4AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMG51G18": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51G18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L083VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G280F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G280F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G280F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F231H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F231H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM073FSDUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M073.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F405ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32ZG210F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32HG308F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG308F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32GG940F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG940F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "AU9110LF3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/AU9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}, "Flash/AU9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/AU9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM4LS4A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4LS4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS4B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1547JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "STM32F469AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L083VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG230F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG230F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "NANO103ZD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1225FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "TMPM332FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32G230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G230F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54607J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "MKL24Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L152C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083B": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "Mini58ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG390F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG390F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF421L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C1299NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1299NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M453VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4N8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM4N8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L162QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32PG12B500F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1313FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11A14FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG840F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG840F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54S606J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "XMC4500-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1764": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2D55J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F048T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S8938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F207ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "PAC5220": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D31": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "NUC029FAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC029_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC029AE\\Include\\NUC029FAE.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NUC029AE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "PAC5223": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120EC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1202-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKV10Z16xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P16_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MKW21Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F427VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32G280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G280F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M453RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9AF131M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF131L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F427VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3U1E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1313FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF131K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9BFD17S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "XMC1404-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S800": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4078FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BFD17T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO102LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MKW22D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4LC4A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF567R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4LC4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG222F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK64FN1M0VLL12": {"core": "Cortex-M4", "vendor": "Freescale:78", "algorithm": {"addon_cmsis/Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.2.2.0.pack", "compile": {"header": "platform/devices/fsl_device_registers.h", "define": "CPU_MK64FN1M0VLL12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "platform\\devices\\MK64F12\\MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F446MC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC4078FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M4LEDRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKL25Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC43S70": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "MB9BF567N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF567M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NM1330LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKM33Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "M058SZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "M482LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F215ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "M484SIDAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11U23FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG995F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG995F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F215ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FDH20/002": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G290F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA0G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1313FBD48/01": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L452CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L452CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF117S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "M453YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L152C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM4F110H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F110H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1114FHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK22FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9D90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF617S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF617T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H753XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAMC20J17AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1301-Q040x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Mini57FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11U37FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F101T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32WG895F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG895F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VE3DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAME53J20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NUC100VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L431VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG309F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG309F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F070F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M451VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L031E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM13Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM13Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L031E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG280F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG280F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "QN9080A": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "QN9080C": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9080B": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54102J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1402-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U13FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKL43Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1512": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF518T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC11U36FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1100-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF155N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF518S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32GG895F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG895F1024"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG895F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L031K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK30DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L031K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM34Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32JG1B200F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "MKV58F512xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00080000"}}, "debug": "SVD/MKV58F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S6952": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6952.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4CP16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF155R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMG55G19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL27Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL27Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMR21E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF521M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6V7": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32GG880F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG880F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6V2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "M453LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF521K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF142N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM072FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M072.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1520RD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC4367": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "ARMCM33_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EFM32WG330F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG330F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM372FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2CC8H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1R26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG330F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG330F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL36Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK21DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F042K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G222F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U35FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFB44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E1A11C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1112FHN24/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1751": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1114FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMCM33": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ADuCM361": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD\\ADuCM361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "MKL17Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL17Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG990F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG990F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F212E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F212E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM390FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM39x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG290F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG290F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG280F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG280F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "N571P032": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N571E000.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\N571P032_v3.svd", "processor": {"clock": "23000000"}}, "TMPM367FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO130KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "M483SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L152QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5956": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5956.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F757F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MVF51NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NN151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S5951": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5951.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF315M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32G890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G890F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MCIMX6Y7": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "XMC1404-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC125ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM4E8E": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG230F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK02FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK02F12810.h", "define": "MK02FN64xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK02F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM4F112C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F112C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U24FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F102C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF124M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMCA9": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCA9/Include/ARMCA9.h", "define": "ARMCA9"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EFM32TG842F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG842F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG332F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG332F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG1B200F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F102C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME53J19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32GG900F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG900F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini55LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M481LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1201-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F415VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "Z32F06423AKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF305N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F746ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F746ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TM4C1230H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1230H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK20DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC822M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "NUC130VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S5737": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5737.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV31F512xxx12": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKV31F51212.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4N16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1111FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG840F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG840F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG230F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG230F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK66F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32FG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123ZC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM4F122C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F122C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMCA7": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCA7/Include/ARMCA7.h", "define": "ARMCA7"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM361F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MVF50NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "LPC11U34FHN33/421": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKE15Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE15Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MVF60NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "S6E2C18J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1115JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1402-Q048x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9843QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9843.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xB000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "EFM32ZG222F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F413VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAML21J17B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG222F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32LG230F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S9B92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAML21J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF116M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC220LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO110RE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MK12DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK12D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F779AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F756BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E14FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F098CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM36BFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "PAC5210": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC126RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFR32MG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MKW24D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW24D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV71Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMV71Q21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMV71Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EZR32WG230F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF616S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F303VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK70FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF616T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "nRF52832_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32WG230F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG230F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F410C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF618T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC120RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L452RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1342FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L452RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF618S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAME51N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC11E68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32LG995F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG995F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32JG1B100F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM366FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "M452RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4E16E": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAM4E16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1547JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32G800F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G800F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G800F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S67": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1232H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1232H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F105RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9AF154M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF154N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO102ZB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "ATSAM4S4B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S4A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54608J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "TM4C129ENCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG110F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG110F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "AC30M1464": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1530VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L081KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F031G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF154R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11C14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6ZXR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZXR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C32E": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32E_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4C32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW40Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW40Z4.h", "define": "MKW40Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW40Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L073RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L021D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "version": "0.1.0", "STM32L073RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M453VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG980F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG980F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BFD18S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1114FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG295F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG295F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BFD18T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL33Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL33Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110RD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAMD20J14": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J15": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BFD16T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S2D93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s2d93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F131C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F131C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1332": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini51XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BFD16S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMD20J17": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK11DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK11D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD21J16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1520RC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD21J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF506N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF506R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E17B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21J18AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1519JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MB9BF566L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG230F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG230F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MKE04Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE04Z1284.h", "define": "MKE04Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE04Z1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L476RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ARMCM0P": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus.h", "define": "ARMCM0P"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MB9BF329T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32F429NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4C4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C49J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1751": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1751.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK60DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF314M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK11DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK11DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC4504-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L431CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG390F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG390F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4337": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32L151CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF428S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "XMC1404-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11A13FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F232E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M452LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L475ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "Mini54XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F239F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4370": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "EFM32TG210F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F705BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM320": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L041K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO130KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9BF105R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF568R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1100-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1233H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F268F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112LVFHI33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF568N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F358RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F217VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MKL13Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL13Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMSC300": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMSC300/Include/ARMSC300.h", "define": "ARMSC300"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F765BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK30DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "M451RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TMPM380FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC4076FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1404-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA1G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C129EKCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129EKCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L486QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2GM8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469AE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC442JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TMPM367FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L011K3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC100LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L011K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG210F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1439": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1439.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2DF5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MK20FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L011D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG940F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG940F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMHA1G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00010000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.0.0.pack", "compile": {"header": "Device/SAMHA1/Include/samha1.h", "define": "__SAMHA1G16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMHA1/ATSAMHA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51822_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F412ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32WG230F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKL82Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL82Z7.h", "define": "MKL82Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFA000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL82Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S10": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32PG1B200F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F205RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1810": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "NUC505DS13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "LPC1812": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1813": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1815": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1817": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L162RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L475VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD10D14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2U93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s2u93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "NM1120TC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM036FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M036.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NM1520LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAML22J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1231D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4088FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F707F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F439NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F439NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC20J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC130LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM4F121B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F121B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F111C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F111C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NM1120XC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC029TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "Mini54FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC1124JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x08000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C5AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MK53DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1402-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MVF50NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S9C97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9c97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F098RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM440_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "STM32F767NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO110RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TMPM462F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MVF60NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "XMC4504-F144x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3S8B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F101VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM074FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M074.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1302-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK20DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32LG230F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "Mini58TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F101VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EZR32WG230F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG360F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG360F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32LG280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF368R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF368M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF368N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M2S025": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "Mini57XDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF304N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ADuCM3027": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.2.0.0.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "ATSAMC21N17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21N/ATSAMC21N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1311FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC240LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32GG390F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG390F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M4TKRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM3S1635": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1635.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM3029": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.2.0.0.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "STM32F100VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MKW21Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F130H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F130H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F100VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "SN32F7651BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1313FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F439BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "Mini54TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LM3S8730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F110B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F110B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9G97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9g97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C123BH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D34": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D34.svd", "processor": {"fpu": "DP_FPU"}}, "EFM32ZG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC130RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO130KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "S6E2C5AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1201-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG330F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG330F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini51TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "EFM32ZG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F373C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG330F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG330F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GM8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F072VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G28H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAML21E16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9BF505R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "nRF52832_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3X8E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "STM32L433VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4CMS8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9877QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD20J18": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF115M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMC20G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMD20J16": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "Mini55ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F072V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL04Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M058SSAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F413VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M487SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF168N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF168M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F405VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9BF168R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAME70N21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFM32HG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F407VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "TMPM475FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EZR32WG230F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4N8A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32WG332F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG332F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32H753VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EZR32WG230F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM383FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F301K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1960": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1960.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L496ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F301K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F769BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF412R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMA5D33": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D33.svd", "processor": {"fpu": "DP_FPU"}}, "NUC123ZC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "XMC4200-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG110F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF412N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAML22N18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL16Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F769BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9AFA32L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA32M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA32N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F423ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMC21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKW01Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW01Z4.h", "define": "MKW01Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKW01Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F120B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F120B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M484SGAAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S817": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s817.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "M453VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "HT32F1765": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC812M101JTB16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32L151R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM366FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF122K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3S4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S4B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S4A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3N1B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L162VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMG54G19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F334C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF144M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF144L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F107VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F334C4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5K36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32GG890F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG890F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L462CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO100NC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S1N11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "R-IN32M4-CL2": {"core": "Cortex-M4", "vendor": "Renesas:117", "algorithm": {"Flash/R-IN32M4_MX25L6433F.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M4_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.1.0.1.pack", "compile": {"header": "Device/Include/RIN32M4.h", "define": "RIN32M4_CL2"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M4_CL2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F429NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC240LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F302K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M058LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2C39L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S301": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s301.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S300": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s300.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F439AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG320F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2HE4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKV44F128xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV44F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "TM4C1236E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1236E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1316FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1114FBD48/323": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NM1120ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD51N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M452VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC123ZD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MK60DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC505DSA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "MKM38Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM38Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472HI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TMPM369FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKV30F128xxx10": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV30F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4800-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32LG395F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG395F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4312": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NUC505YO13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "MKM33Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1825": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F755J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54628J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54628.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LPC1820": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1823": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1822": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F205VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK51DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9781": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9781.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL16Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1B21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1b21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S617": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s617.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1100-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F212H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1100-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32HG322F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG322F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM4F132C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F132C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L071K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC121SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM3U4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MB9BF367M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF367N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F411CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NUC123LD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32G840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G840F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L041F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F042G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LPC1857": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO112SB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "ARMCM4": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM7": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM0": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM0/Include/ARMCM0.h", "define": "ARMCM0"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM3": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM3/Include/ARMCM3.h", "define": "ARMCM3"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC1853": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32G840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G840F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1N16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F723VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC845M301JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "CMSDK_CM7": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L151R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF505N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG380F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG380F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2CCAH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L071KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "S6E2GH8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ADSP-CM419F": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.1.2.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x11080000", "size": "0x00080000"}, "IRAM1": {"start": "0x200F0000", "size": "0x00008000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x11000000", "size": "0x00080000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L071KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC18S57": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKL36Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EZR32LG230F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6537": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6537.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9997": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9997.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F746NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32LG230F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746NE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S2110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF114L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L072VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NANO100KC3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAM3N1A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1E14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F103C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKL26Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F211H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F211H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG840F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG840F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKV11Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV11Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32G890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G890F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L083CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM4F230E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F230E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54101J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L083CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F769F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "XMC1402-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54113J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F373RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F101V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC54618J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "S6E2DH5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F048C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1125JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL27Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL27Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C18L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1626": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1626.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG222F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF144N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC200LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F479VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L072V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFR32FG12P231F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMG55J19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9D96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC20J18AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B100F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "NUC472JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "MK22FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C1231E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC131SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC4104-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAML21E15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2D35GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MVF50NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "GD32F130C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "GD32F130C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG53G19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E13FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG108F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F190R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32WG330F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3Z26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s3z26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F190R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD51G18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51G18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "GD32F450VI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG108F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3N0B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF522M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3N0A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF522K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TLE9867QXW20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L4A6VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "M451SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG230F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG230F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF132L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32HG309F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG309F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF132K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL13Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL13Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG110F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M0519SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC4400-F64x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC4500-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC442RI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "M0564RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF504R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM470FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F405RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F768AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M0564VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF504N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKV46F128xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV46F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NUC120VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F405RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2C38J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F405RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG900F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG900F256"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG900F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM330FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L451VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1301-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32HG310F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG310F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S5R36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F777II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMC20E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF316M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL05Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG53N19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "M052LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32GG395F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG395F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F765VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL17Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL17Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG940F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG940F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32G222F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G222F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L433CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1232E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1232E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD51J20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LM4F120E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F120E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32PG12B500F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L100C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F302ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC4074FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F235J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1403-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S310": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s310.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MK20DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S316": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s316.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S317": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s317.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LPC11E37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S315": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s315.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MK22DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF415R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMDA1G14B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1G14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "NM1827UB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMDA1G14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG842F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG842F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1114FBD48/333": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F207IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "M452SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L011E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM341FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM341_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "NUC121LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TLE9842-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9842_2.FLM": {"default": "1", "ramsize": null, "size": "0xA000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0x9000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1226FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "EFM32TG822F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG822F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG210F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2HE4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD21E16BU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG842F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG842F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F030C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG110F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1833": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1830": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF316R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1837": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11D14FBD100/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11D14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC18S30": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW36Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM461_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S37": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MK51DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK11DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK11DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "XMC1402-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L100RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL14Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF117T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F437IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "nRF52840_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\nrf52840.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F745ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1200-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32JG12B500F1024GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "AMAPH1KK-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F446ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F101C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32LG940F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG940F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKW41Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F412VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO110SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F410R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4700-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM370FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F407RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L041G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442RG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "NANO102ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "LM3S818": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s818.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F101ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "ATSAMG54N19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F042F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MM32x031": {"core": "Cortex-M0", "vendor": "MindMotion:132", "algorithm": {"Flash/MM32x031_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.1.0.0.pack", "compile": {"header": "Device/Include/MM32x031.h", "define": "MM32x031"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/MM32x031.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F405OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32BG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S2671": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2671.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1315FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC4333": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F429ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M451MSC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M0519LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L083RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK11DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK11DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F401CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NUC120VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK65FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK65F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Generic_Mini51_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F042T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042T4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1342FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKM32Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM32Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L083RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NANO112RB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "TMPM46BF10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM46B_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}, "IRAM2": {"start": "0x20080000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M46B.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F479BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S5Y36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s5y36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9790": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9790.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMS70Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NUC120RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L052C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F411VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM470FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L021G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1302-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L052C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG320F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG320F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L471ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L471ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC11U14FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG230F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1317FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKM33Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1202-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M483KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S828": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s828.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G880F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAME53N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "HT32F52352": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FE00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF366N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF500N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF366L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF366M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG330F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG330F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MVF60NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF306N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F107F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F766BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC832M101FDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F078VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF306R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "CMSDK_CM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4_FP.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S1C26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4700-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM383FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L051C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK60FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "XMC4500-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9879QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F101T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9AF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L476MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5C36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1112JHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9BN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE06Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE06Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE06Z4.h", "define": "MKE06Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE06Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9BF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NM1120DB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM462F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DF5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S5D91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO130SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EFM32LG360F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG360F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F417VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "M4LEDLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "AC30M1432": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C48H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1827": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF324L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1100-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32PG1B100F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF324K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC220SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG890F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG890F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1230E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1230E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2DF5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4CMS32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMS32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMDA1E15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAME53J18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME53J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32LG390F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG390F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG12B500F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2H44G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1202-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M487JIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32JG12B500F1024IL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG390F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG390F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LPC54113J128BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKW36A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114LVFHN24/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1100DBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1302-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M058SFAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1518JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LPC54605J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "Mini54LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32L431RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L431RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32LG332F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG332F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M058ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32JG1B200F256IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF414R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L451RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF414N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMS70Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "SN32F226J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L486RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TLE9877QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "M452YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M451MLC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC120LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TMPM333FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1301-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL43Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM333FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG295F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG295F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NM1100XBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG942F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG942F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F030RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD51G19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51G19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKE15Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE15Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32HG321F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG321F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF124L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L4A6AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF124K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF514N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF514R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAM4N16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SN32F767BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKV44F64xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV44F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "M0564LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKL03Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL03Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKS22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKS22F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NM1200TAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NM1530VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L063C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKE14F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE14F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC123LD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TM4C123BH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F328C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "Mini58FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F745ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM4F212H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MK21DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK21DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32LG295F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG295F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1519JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MK30DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S1165": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1165.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F030R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1162": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1162.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2HE6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO112RC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "SN32F768BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S9U92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9U90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9U96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G222F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G222F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G222F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4400-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MKL17Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL17Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5662": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5662.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L011D3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MVF61NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NN151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "STM32L476QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L476QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML22J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA1G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F100ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMDA1G15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F429IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L052R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F401CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC811M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00002000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32L162ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG225F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG225F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3S8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32L052R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F777NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7652BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC200LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32H753BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32PG1B200F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4078FBD100": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3J26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3j26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3U2E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U2E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F765II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S8630": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8630.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Generic_Nano100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "NUC505DLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "LPC1110FD20": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x1000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0400"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L496VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4CMS4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F765IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7741J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52331": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV71J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "S6E2C39J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "SKEAZN64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C1237D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ISD9130": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "MB9BF365L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF365K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG880F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG880F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9871QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9871.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF155M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "Mini52ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "EFM32WG840F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG840F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M058SLAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S102": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s102.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S101": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "S6E2D55G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL27Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL27Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M0516ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC54114J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK40DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x0008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC120LD2DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC122SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "M453VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC100LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2CC8L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4CMP16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "Mini51ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC1227FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "M451LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F401RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F207IC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5D51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F207IF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F401RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32WG395F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG395F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108HB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TLE9869QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9869.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1302-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F439ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC220LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L152ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD21E16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TMPM369FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF112L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF112M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF112K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC844M201JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAM4CP16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16B_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M2S090": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LM3S812": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52342": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52341": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFE00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG980F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG980F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC140RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MVF60NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "XMC1302-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NANO120LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "NUC120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M4TKLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M054LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NM1520LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "MB9BF165K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMDA1E16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF165L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3H6FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.0.0.pack", "compile": {"header": "Device/Include/TMPM3H6.h", "define": "TMPM3H6FWFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C1237H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG108F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG360F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG360F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G17B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAML21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG990F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG990F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG990F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "R-IN32M3-CL": {"core": "Cortex-M3", "vendor": "Renesas:117", "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_CL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54101J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F031C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F12365": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M451MLD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "S6E2CCAJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12366": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F52231": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52230": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x7C00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1Z16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s1z16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C1AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4S8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1226FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "NM1200LAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32F413ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32JG1B200F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F417ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9BF521L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L152ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54S608J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ARMCM33_DSP_FP_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F334R4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F334R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4100-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4S8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32PG12B500F512GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F512GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C59J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD51P20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32GG332F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG332F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00002000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL03Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F427AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32JG12B500F1024GL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F070CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2939": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2939.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51P19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M0516ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF515N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF515R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG330F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G842F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M482LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M451LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM3S5P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5C51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG380F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG380F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5632": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F303ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L443VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKL02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F150C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM411F20XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM41xA_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM41xB_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM411_unitB.h", "define": "TMPM411F20XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20008000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54102J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK20DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMC21J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TMPM330FDWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32LG395F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG395F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M483SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F746BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F746BE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC100LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2GK8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4800-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L476VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD20E18": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E17": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4076FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD20E15": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E14": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM3S3W26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s3w26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF468M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF468N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAML21J18B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C29L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F733VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM330FYWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF565L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F469ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC810M021FN8": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x00001000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "Mini52XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC140RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32LG842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5T36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s5t36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2CC9H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TM4C1290NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKV10Z32xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P32_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "STM32F756ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC122SC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "ATSAM3N2A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F237F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1621": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1621.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1150": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1150.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1625": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1625.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF417S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1315FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S8530": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8530.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF417T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S8538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG842F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG842F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M487KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F248F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKV44F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV44F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L462RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF166L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L011G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U24FET48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32HG320F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF322K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA1E14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1E14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F765ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M0516ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC4072FET80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32LG332F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG332F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M0516LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F767ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F767ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32ZG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG380F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG380F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F105VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4700-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "ISD9361": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9300_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9300_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9300_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "S6E2D55JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1D21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD20G17": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M482SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S1D26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ATSAMD20G16": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F212H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMV71J21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMV71J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMV71J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV71J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F446RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1301-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1302-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L475RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML22N17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G840F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV56F1M0xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x2F000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00100000"}}, "debug": "SVD/MKV56F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "STM32F769II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L475RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "IOTKit_ARMv8MML": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MML/Include/IOTKit_ARMv8MML.h", "define": "IOTKit_ARMv8MML"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1J16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1J11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC122LC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "EFM32HG210F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG210F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S2616": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2616.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1823LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC812M101JD20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F439BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32LG330F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4500-E144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG330F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL03Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL27Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL27Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21G16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M2S150": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "STM32L071VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TLE9843-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9843_2.FLM": {"default": "1", "ramsize": null, "size": "0xD000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1101LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L051K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC126LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKW35A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK11DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK11D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2DH5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO100LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "NUC123LC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4LS2C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS2B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS2A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F098VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C49L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32H743ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAMDA0J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S328": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s328.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LPC11U37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini51XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG230F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG110F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC472KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EZR32LG230F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG380F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG380F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S801": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s801.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32ZG110F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S808": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s808.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG230F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F22366": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC11U14FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM360": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD\\ADuCM360.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F303K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F072R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F230H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F230H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1237E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF364K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF364L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F215RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F215RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM369FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F723IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M452RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "nRF52810_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf52810.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "APOLLO256-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F723IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF114M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54S618J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F469II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC120LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F150K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5P56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H14G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F150K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2H14E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F150K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F469IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKL33Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL33Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F469IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG232F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG232F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "ATSAMA5D44": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D44.svd", "processor": {"fpu": "DP_FPU"}}, "S6E2C49H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4A6QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D41": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D41.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D42": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D42.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D43": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D43.svd", "processor": {"fpu": "DP_FPU"}}, "EFM32GG290F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG290F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "M0516LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "HT32F52243": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52241": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L072KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F705J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F429II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11U24FHI33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L433RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4LC2B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC2A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC472VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "GD32F190C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TM4C123BH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21E15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK64FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1114JHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G290F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130F4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32LG942F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG942F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M481ZIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM36BF10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040800"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S9971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG825F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG825F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF111K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F405RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MK12DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK12D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1201-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AC33M3064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S2948": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2948.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9D81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F407ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO110RC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F407ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32WG330F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32WG330F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM470FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32W108C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F103R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1816": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1816.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MVF61NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NS151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "STM32F107VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM343FEXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM343_768.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC240LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EZR32WG230F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG295F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG295F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32L041C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD10C14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1549JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M054LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C129XKCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129XKCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF416S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1112FD20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF468R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9AF342M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "SN32F249F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F410TB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG108F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32LG330F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E16": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF416N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EZR32LG330F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG108F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ML630Q466": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "algorithm": {"Flash/ML630Q466.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/ML630Q466.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ML630Q464": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "algorithm": {"Flash/ML630Q464.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/ML630Q464.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2CC9J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F051K8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F051K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4074FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F051K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1330LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1330_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF217T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF217S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC122ZC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "LM4F232H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKW31Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S6965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000B800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1402-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF516N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L151V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F103RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF516T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF516S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF516R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F103RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1518JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "XMC1201-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1548JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LM4F210H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F210H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-T038x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF418S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2C28L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM4F111H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F111H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M451VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF418T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S32K144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"addon_cmsis/Flash/S32K144_P512_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.0.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K144HFT0VLLT"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "platform/devices/S32K144/S32K144.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "ATSAML22N16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22N16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "S6E2G26H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM4F112H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54605J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LM3S1637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Z32F38412ALS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F3841.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F3841.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F3841.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MK10DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F112H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54618J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F429VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini52TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC1112LVFHN24/003": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG395F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG395F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG232F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG232F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL36Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108CZ": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_192.FLM": {"default": "1", "ramsize": null, "size": "0x30000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x08000000", "size": "0x30000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1202-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Generic_NUC100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC845M301JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFM32LG890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP256_2KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34Z7.h", "define": "MKM34Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKM34Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32WG280F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG280F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4C8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F779II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32PG1B200F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK21FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L073CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG990F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG990F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG225F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG225F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL15Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG330F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG330F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK66F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2HG6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F413CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2C2AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMC20J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AFA41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL25Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL25Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1W16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s1w16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F733ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "GD32F170C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5656": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5656.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F238F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114LVFHN24/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F170C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F779BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1202-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2793": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2793.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1401-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "CMSDK_ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MBL/Include/CMSDK_ARMv8MBL.h", "define": "CMSDK_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F469VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C58H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "S6E2C3AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S628": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s628.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F042C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NUC120LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "APOLLO512-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1201-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1403-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G200F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G200F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1752": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "APOLLO256-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1756": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1754": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L152RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011F3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1759": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1758": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L011F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F207VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ARMCM23_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LM3S5739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F102C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE06Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE06Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE06Z4.h", "define": "MKE06Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE06Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5732": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5732.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMCA5": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCA5/Include/ARMCA5.h", "define": "ARMCA5"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M0518LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F078RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MK22FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM4F132E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F132E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SKEAZN8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/SKEAZN84.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S8962": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8962.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4LEDRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F413ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO100KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F469AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F407VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F723ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "S6E2D35JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E37FBD48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5G51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA1J16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LM3S2730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3S2A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S2739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK21DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C19H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF329S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32F318K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1227FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S6618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M054ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M054ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC126RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF167R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F373V8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U36FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F2755": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM366FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2139": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2139.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "TM4C1230D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1230D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF167N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF167M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S6100": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "S6E2GH6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2GH6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F412ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG108F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC834M101FHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAM3X8H": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8H.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "MKL15Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DF5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "IOTKit_CM23": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_CM23/Include/IOTKit_CM23.h", "define": "IOTKit_CM23"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F101VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "ATSAM3X8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1292NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12345": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M0516LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6753": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6753.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F373VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MKL17Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL17Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FDH20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M054ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F407IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F52253": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F407IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC1115FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK22F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG320F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF318S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF318T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL05Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG332F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SD16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAMD21E15BU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E15BU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GH8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF216T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC11C14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF216S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MK10DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK50DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MM32x103": {"core": "Cortex-M3", "vendor": "MindMotion:132", "algorithm": {"Flash/MM32x103_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MM32x103.h", "define": "MM32x103_MD"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/MM32x103.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MB9BF129S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LM3S618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1821FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF129T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LM3S2950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S613": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s613.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S612": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s612.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF517S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF517T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9D92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S615": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s615.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L486ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F479NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK27FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x1FFC0000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK27F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "STM32F103VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S1627": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1627.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3SD8B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3SD8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAMC21J17AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M451MRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ARMCM33_DSP_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "S6E2CCAL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG332F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG332F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C1AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4A6RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF316S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKW21D256xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF316T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9L97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKL33Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL33Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1401-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF500R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M481ZGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32JG1B200F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722VC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1824FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F722VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "GD32F405VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMS70Q21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "TMPM475FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L052T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF305R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "GD32F405VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMC21J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F038E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M482SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM4F120C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F120C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG290F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG290F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11E14FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1294NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5R31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C59L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S5C56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG980F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG980F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G232F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK21FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32WG380F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG380F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK21FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4CMP8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM361FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LPC11U12FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV31F256xxx12": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV31F25612.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L496QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21G17AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE14Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1302-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2GK6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32FG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF467N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM3N4B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x06000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3N/ATSAM3N4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123GH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1607": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1607.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK50DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1114FN28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MWPR1516xxx": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKPR1516_P16KB.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MWPR1516.h", "define": "MWPR1516xxx"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MWPR1516.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F302VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F769NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1402-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "M058ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1548JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M453RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF367R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33_FP": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "NUC120RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32HG320F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4400-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54S606J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EFM32LG940F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG940F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G18": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L496AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK10DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK10DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini51ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAMD20G15": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G14": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21E19A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E19A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF522L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1100-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "ATSAMD21G15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM375FSDMG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M375.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3N0C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1J15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LPC11E66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG12B500F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F765NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM4E8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1202-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG822F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG822F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L041C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKE04Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE04Z1284.h", "define": "MKE04Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE04Z1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1311FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32HG320F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini52XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMS70N21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100ND3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "SN32F767F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F732ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM4F130E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F130E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1345FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM363F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M363.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S5651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F732IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5652": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5652.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F429VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "CMSDK_ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S2608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1404-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG110F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM369FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF51NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NS151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S8971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8970": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8970.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKW30Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW30Z4.h", "define": "MKW30Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW30Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120ZC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1317FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F205ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MKW31Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "NM1100XAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG230F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "LPC1113FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC822M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F479NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F439VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32LG995F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG995F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1343FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F439VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32GG280F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG280F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F437AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ISD9341": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "MKL16Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ISD9340": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "Generic_M051_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L083V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123FE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123FE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F190RB": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F732RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S6938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini52ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F318C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAME54P20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LM3S1H11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1H16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMV70N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC1347FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2410": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2410.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}}
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/pack_manager.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/pack_manager.py
new file mode 100755
index 0000000..c9c52bc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/arm_pack_manager/pack_manager.py
@@ -0,0 +1,191 @@
+import argparse
+from os.path import basename
+from tools.arm_pack_manager import Cache
+from os.path import basename, join, dirname, exists
+from os import makedirs
+from itertools import takewhile
+from fuzzywuzzy import process
+from tools.arm_pack_manager import Cache
+
+parser = argparse.ArgumentParser(description='A Handy little utility for keeping your cache of pack files up to date.')
+subparsers = parser.add_subparsers(title="Commands")
+
+def subcommand(name, *args, **kwargs):
+    def subcommand(command):
+        subparser = subparsers.add_parser(name, **kwargs)
+
+        for arg in args:
+            arg = dict(arg)
+            opt = arg['name']
+            del arg['name']
+
+            if isinstance(opt, basestring):
+                subparser.add_argument(opt, **arg)
+            else:
+                subparser.add_argument(*opt, **arg)
+
+        subparser.add_argument("-v", "--verbose", action="store_true", dest="verbose", help="Verbose diagnostic output")
+        subparser.add_argument("-vv", "--very_verbose", action="store_true", dest="very_verbose", help="Very verbose diagnostic output")
+        subparser.add_argument("--no-timeouts", action="store_true", help="Remove all timeouts and try to download unconditionally")
+        subparser.add_argument("--and", action="store_true", dest="intersection", help="combine search terms as if with an and")
+        subparser.add_argument("--or", action="store_false", dest="intersection", help="combine search terms as if with an or")
+        subparser.add_argument("--union", action="store_false", dest="intersection", help="combine search terms as if with a set union")
+        subparser.add_argument("--intersection", action="store_true", dest="intersection", help="combine search terms as if with a set intersection")
+        
+        def thunk(parsed_args):
+            cache = Cache(not parsed_args.verbose, parsed_args.no_timeouts)
+            argv = [arg['dest'] if 'dest' in arg else arg['name'] for arg in args]
+            argv = [(arg if isinstance(arg, basestring) else arg[-1]).strip('-')
+                    for arg in argv]
+            argv = {arg: vars(parsed_args)[arg] for arg in argv
+                    if vars(parsed_args)[arg] is not None}
+
+            return command(cache, **argv)
+
+        subparser.set_defaults(command=thunk)
+        return command
+    return subcommand
+
+def user_selection (message, options) :
+    print(message)
+    for choice, index in zip(options, range(len(options))) :
+        print("({}) {}".format(index, choice))
+    pick = None
+    while pick is None :
+        stdout.write("please select an integer from 0 to {} or \"all\"".format(len(options)-1))
+        input = raw_input()
+        try :
+            if input == "all" :
+                pick = options
+            else :
+                pick = [options[int(input)]]
+        except ValueError :
+            print("I did not understand your input")
+    return pick
+
+def fuzzy_find(matches, urls) :
+    choices = {}
+    for match in matches :
+        for key, value in process.extract(match, urls, limit=None) :
+            choices.setdefault(key, 0)
+            choices[key] += value
+    choices = sorted([(v, k) for k, v in choices.iteritems()], reverse=True)
+    if not choices : return []
+    elif len(choices) == 1 : return [choices[0][1]]
+    elif choices[0][0] > choices[1][0] : choices = choices[:1]
+    else : choices = list(takewhile(lambda t: t[0] == choices[0][0], choices))
+    return [v for k,v in choices]
+
+@subcommand('cache',
+            dict(name='matches', nargs="*",
+                 help="a bunch of things to search for in part names"),
+            dict(name=['-e','--everything'], action="store_true",
+                 help="download everything possible"),
+            dict(name=['-d','--descriptors'], action="store_true",
+                 help="download all descriptors"),
+            dict(name=["-b","--batch"], action="store_true",
+                 help="don't ask for user input and assume download all"),
+            help="Cache a group of PACK or PDSC files")
+def command_cache (cache, matches, everything=False, descriptors=False, batch=False, verbose= False, intersection=True) :
+    if everything :
+        cache.cache_everything()
+        return True
+    if descriptors :
+        cache.cache_descriptors()
+        return True
+    if not matches :
+        print("No action specified nothing to do")
+    else :
+        urls = cache.get_urls()
+        if intersection :
+            choices = fuzzy_find(matches, map(basename, urls))
+        else :
+            choices = sum([fuzzy_find([m], map(basename, urls)) for m in matches], [])
+        if not batch and len(choices) > 1 :
+            choices = user_selection("Please select a file to cache", choices)
+        to_download = []
+        for choice in choices :
+            for url in urls :
+                if choice in url :
+                    to_download.append(url)
+        cache.cache_pack_list(to_download)
+        return True
+
+
+@subcommand('find-part',
+            dict(name='matches', nargs="+", help="words to match to processors"),
+            dict(name=['-l',"--long"], action="store_true",
+                 help="print out part details with part"),
+            dict(name=['-p', '--parts-only'], action="store_false", dest="print_aliases"),
+            dict(name=['-a', '--aliases-only'], action="store_false", dest="print_parts"),
+            help="Find a Part and it's description within the cache")
+def command_find_part (cache, matches, long=False, intersection=True,
+                       print_aliases=True, print_parts=True) :
+    if long :
+        import pprint
+        pp = pprint.PrettyPrinter()
+    parts = cache.index
+    if intersection :
+        choices = fuzzy_find(matches, parts.keys())
+        aliases = fuzzy_find(matches, cache.aliases.keys())
+    else :
+        choices = sum([fuzzy_find([m], parts.keys()) for m in matches], [])
+        aliases = sum([fuzzy_find([m], cache.aliases.keys()) for m in matches], [])
+    if print_parts:
+        for part in choices :
+            print part
+            if long :
+                pp.pprint(cache.index[part])
+    if print_aliases:
+        for alias in aliases :
+            print alias
+            if long :
+                pp.pprint(cache.index[cache.aliases[alias]])
+
+@subcommand('dump-parts',
+            dict(name='out', help='directory to dump to'),
+            dict(name='parts', nargs='+', help='parts to dump'),
+            help='Create a directory with an index.json describing the part and all of their associated flashing algorithms.'
+)
+def command_dump_parts (cache, out, parts, intersection=False) :
+    index = {}
+    if intersection :
+        for part in fuzzy_find(parts, cache.index):
+            index.update(cache.index[part])
+    else :
+        for part in parts :
+            index.update(dict(cache.find_device(part)))
+    for n, p in index.iteritems() :
+        try :
+            if not exists(join(out, dirname(p['algorithm']['file']))) :
+                makedirs(join(out, dirname(p['algorithm']['file'])))
+            with open(join(out, p['algorithm']['file']), "wb+") as fd :
+                fd.write(cache.get_flash_algorthim_binary(n).read())
+        except KeyError:
+            print("[Warning] {} does not have an associated flashing algorithm".format(n))
+    with open(join(out, "index.json"), "wb+") as fd :
+        dump(index,fd)
+
+
+@subcommand('cache-part',
+            dict(name='matches', nargs="+", help="words to match to devices"),
+            help='Cache PACK files associated with the parts matching the provided words')
+def command_cache_part (cache, matches, intersection=True) :
+    index = cache.index
+    if intersection :
+        choices = fuzzy_find(matches, index.keys())
+        aliases = fuzzy_find(matches, cache.aliases.keys())
+    else :
+        choices = sum([fuzzy_find([m], index.keys()) for m in matches], [])
+        aliases = sum([fuzzy_find([m], cache.aliases.keys()) for m in matches], [])
+    urls = set([index[c]['pdsc_file'] for c in choices])
+    urls += set([index[cache.aliasse[a]] for a in aliases])
+    cache.cache_pack_list(list(urls))
+
+def get_argparse() :
+    return parser
+
+def main() :
+    args = parser.parse_args()
+    args.command(args)
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build.py
new file mode 100755
index 0000000..1d0282a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build.py
@@ -0,0 +1,249 @@
+#! /usr/bin/env python2
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+LIBRARIES BUILD
+"""
+import sys
+from time import time
+from os.path import join, abspath, dirname
+
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+
+from tools.toolchains import TOOLCHAINS, TOOLCHAIN_CLASSES, TOOLCHAIN_PATHS
+from tools.toolchains import mbedToolchain
+from tools.targets import TARGET_NAMES, TARGET_MAP
+from tools.options import get_default_options_parser
+from tools.options import extract_profile
+from tools.options import extract_mcus
+from tools.build_api import build_library, build_mbed_libs, build_lib
+from tools.build_api import mcu_toolchain_matrix
+from tools.build_api import print_build_results
+from tools.settings import CPPCHECK_CMD, CPPCHECK_MSG_FORMAT
+from utils import argparse_filestring_type, args_error
+from tools.settings import CPPCHECK_CMD, CPPCHECK_MSG_FORMAT, CLI_COLOR_MAP
+from utils import argparse_filestring_type, argparse_dir_not_parent
+
+if __name__ == '__main__':
+    start = time()
+
+    # Parse Options
+    parser = get_default_options_parser()
+
+    parser.add_argument("--source", dest="source_dir", type=argparse_filestring_type,
+                        default=None, help="The source (input) directory", action="append")
+
+    parser.add_argument("--build", dest="build_dir", type=argparse_dir_not_parent(ROOT),
+                      default=None, help="The build (output) directory")
+
+    parser.add_argument("--no-archive", dest="no_archive", action="store_true",
+                      default=False, help="Do not produce archive (.ar) file, but rather .o")
+
+    # Extra libraries
+    parser.add_argument("-r", "--rtos",
+                      action="store_true",
+                      dest="rtos",
+                      default=False,
+                      help="Compile the rtos")
+
+    parser.add_argument("--rpc",
+                      action="store_true",
+                      dest="rpc",
+                      default=False,
+                      help="Compile the rpc library")
+
+    parser.add_argument("-u", "--usb",
+                      action="store_true",
+                      dest="usb",
+                      default=False,
+                      help="Compile the USB Device library")
+
+    parser.add_argument("-d", "--dsp",
+                      action="store_true",
+                      dest="dsp",
+                      default=False,
+                      help="Compile the DSP library")
+
+    parser.add_argument( "--cpputest",
+                      action="store_true",
+                      dest="cpputest_lib",
+                      default=False,
+                      help="Compiles 'cpputest' unit test library (library should be on the same directory level as mbed repository)")
+
+    parser.add_argument("-D",
+                      action="append",
+                      dest="macros",
+                      help="Add a macro definition")
+
+    parser.add_argument("-S", "--supported-toolchains",
+                      action="store_true",
+                      dest="supported_toolchains",
+                      default=False,
+                      help="Displays supported matrix of MCUs and toolchains")
+
+    parser.add_argument('-f', '--filter',
+                      dest='general_filter_regex',
+                      default=None,
+                      help='For some commands you can use filter to filter out results')
+
+    parser.add_argument("-j", "--jobs", type=int, dest="jobs",
+                      default=0, help="Number of concurrent jobs. Default: 0/auto (based on host machine's number of CPUs)")
+    parser.add_argument("-N", "--artifact-name", dest="artifact_name",
+                      default=None, help="The built project's name")
+
+    parser.add_argument("-v", "--verbose",
+                      action="store_true",
+                      dest="verbose",
+                      default=False,
+                      help="Verbose diagnostic output")
+
+    parser.add_argument("--silent",
+                      action="store_true",
+                      dest="silent",
+                      default=False,
+                      help="Silent diagnostic output (no copy, compile notification)")
+
+    parser.add_argument("-x", "--extra-verbose-notifications",
+                      action="store_true",
+                      dest="extra_verbose_notify",
+                      default=False,
+                      help="Makes compiler more verbose, CI friendly.")
+
+    options = parser.parse_args()
+
+    # Only prints matrix of supported toolchains
+    if options.supported_toolchains:
+        print mcu_toolchain_matrix(platform_filter=options.general_filter_regex)
+        exit(0)
+
+
+    # Get target list
+    targets = extract_mcus(parser, options) if options.mcu else TARGET_NAMES
+
+    # Get toolchains list
+    toolchains = options.tool if options.tool else TOOLCHAINS
+
+    if options.source_dir and not options.build_dir:
+        args_error(parser, "argument --build is required by argument --source")
+
+    if options.color:
+        # This import happens late to prevent initializing colorization when we don't need it
+        import colorize
+        if options.verbose:
+            notify = mbedToolchain.print_notify_verbose
+        else:
+            notify = mbedToolchain.print_notify
+        notify = colorize.print_in_color_notifier(CLI_COLOR_MAP, notify)
+    else:
+        notify = None
+
+    # Get libraries list
+    libraries = []
+
+    # Additional Libraries
+    if options.rpc:
+        libraries.extend(["rpc"])
+    if options.usb:
+        libraries.append("usb")
+    if options.dsp:
+        libraries.extend(["dsp"])
+    if options.cpputest_lib:
+        libraries.extend(["cpputest"])
+
+    # Build results
+    failures = []
+    successes = []
+    skipped = []
+
+    for toolchain in toolchains:
+        if not TOOLCHAIN_CLASSES[toolchain].check_executable():
+            search_path = TOOLCHAIN_PATHS[toolchain] or "No path set"
+            args_error(parser, "Could not find executable for %s.\n"
+                               "Currently set search path: %s"
+                       % (toolchain, search_path))
+
+    for toolchain in toolchains:
+        for target in targets:
+            tt_id = "%s::%s" % (toolchain, target)
+            if toolchain not in TARGET_MAP[target].supported_toolchains:
+                # Log this later
+                print "%s skipped: toolchain not supported" % tt_id
+                skipped.append(tt_id)
+            else:
+                try:
+                    mcu = TARGET_MAP[target]
+                    profile = extract_profile(parser, options, toolchain)
+                    if options.source_dir:
+                        lib_build_res = build_library(options.source_dir, options.build_dir, mcu, toolchain,
+                                                    extra_verbose=options.extra_verbose_notify,
+                                                    verbose=options.verbose,
+                                                    silent=options.silent,
+                                                    jobs=options.jobs,
+                                                    clean=options.clean,
+                                                    archive=(not options.no_archive),
+                                                    macros=options.macros,
+                                                    name=options.artifact_name,
+                                                    build_profile=profile)
+                    else:
+                        lib_build_res = build_mbed_libs(mcu, toolchain,
+                                                    extra_verbose=options.extra_verbose_notify,
+                                                    verbose=options.verbose,
+                                                    silent=options.silent,
+                                                    jobs=options.jobs,
+                                                    clean=options.clean,
+                                                        macros=options.macros,
+                                                        build_profile=profile)
+
+                    for lib_id in libraries:
+                        build_lib(lib_id, mcu, toolchain,
+                                extra_verbose=options.extra_verbose_notify,
+                                verbose=options.verbose,
+                                silent=options.silent,
+                                clean=options.clean,
+                                macros=options.macros,
+                                    jobs=options.jobs,
+                                    build_profile=profile)
+                    if lib_build_res:
+                        successes.append(tt_id)
+                    else:
+                        skipped.append(tt_id)
+                except Exception, e:
+                    if options.verbose:
+                        import traceback
+                        traceback.print_exc(file=sys.stdout)
+                        sys.exit(1)
+                    failures.append(tt_id)
+                    print e
+
+
+    # Write summary of the builds
+    print
+    print "Completed in: (%.2f)s" % (time() - start)
+    print
+
+    for report, report_name in [(successes, "Build successes:"),
+                                (skipped, "Build skipped:"),
+                                (failures, "Build failures:"),
+                               ]:
+        if report:
+            print print_build_results(report, report_name),
+
+    if failures:
+        sys.exit(1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_api.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_api.py
new file mode 100755
index 0000000..790b1bc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_api.py
@@ -0,0 +1,1415 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+import tempfile
+import datetime
+import uuid
+from types import ListType
+from shutil import rmtree
+from os.path import join, exists, dirname, basename, abspath, normpath, splitext
+from os.path import relpath
+from os import linesep, remove, makedirs
+from time import time
+from intelhex import IntelHex
+from json import load, dump
+
+from tools.utils import mkdir, run_cmd, run_cmd_ext, NotSupportedException,\
+    ToolException, InvalidReleaseTargetException, intelhex_offset
+from tools.paths import MBED_CMSIS_PATH, MBED_TARGETS_PATH, MBED_LIBRARIES,\
+    MBED_HEADER, MBED_DRIVERS, MBED_PLATFORM, MBED_HAL, MBED_CONFIG_FILE,\
+    MBED_LIBRARIES_DRIVERS, MBED_LIBRARIES_PLATFORM, MBED_LIBRARIES_HAL,\
+    BUILD_DIR
+from tools.targets import TARGET_NAMES, TARGET_MAP
+from tools.libraries import Library
+from tools.toolchains import TOOLCHAIN_CLASSES
+from jinja2 import FileSystemLoader
+from jinja2.environment import Environment
+from tools.config import Config
+
+RELEASE_VERSIONS = ['2', '5']
+
+def prep_report(report, target_name, toolchain_name, id_name):
+    """Setup report keys
+
+    Positional arguments:
+    report - the report to fill
+    target_name - the target being used
+    toolchain_name - the toolchain being used
+    id_name - the name of the executable or library being built
+    """
+    if not target_name in report:
+        report[target_name] = {}
+
+    if not toolchain_name in report[target_name]:
+        report[target_name][toolchain_name] = {}
+
+    if not id_name in report[target_name][toolchain_name]:
+        report[target_name][toolchain_name][id_name] = []
+
+def prep_properties(properties, target_name, toolchain_name, vendor_label):
+    """Setup test properties
+
+    Positional arguments:
+    properties - the dict to fill
+    target_name - the target the test is targeting
+    toolchain_name - the toolchain that will compile the test
+    vendor_label - the vendor
+    """
+    if not target_name in properties:
+        properties[target_name] = {}
+
+    if not toolchain_name in properties[target_name]:
+        properties[target_name][toolchain_name] = {}
+
+    properties[target_name][toolchain_name]["target"] = target_name
+    properties[target_name][toolchain_name]["vendor"] = vendor_label
+    properties[target_name][toolchain_name]["toolchain"] = toolchain_name
+
+def create_result(target_name, toolchain_name, id_name, description):
+    """Create a result dictionary
+
+    Positional arguments:
+    target_name - the target being built for
+    toolchain_name - the toolchain doing the building
+    id_name - the name of the executable or library being built
+    description - a human readable description of what's going on
+    """
+    cur_result = {}
+    cur_result["target_name"] = target_name
+    cur_result["toolchain_name"] = toolchain_name
+    cur_result["id"] = id_name
+    cur_result["description"] = description
+    cur_result["elapsed_time"] = 0
+    cur_result["output"] = ""
+
+    return cur_result
+
+def add_result_to_report(report, result):
+    """Add a single result to a report dictionary
+
+    Positional arguments:
+    report - the report to append to
+    result - the result to append
+    """
+    result["date"] = datetime.datetime.utcnow().isoformat()
+    result["uuid"] = str(uuid.uuid1())
+    target = result["target_name"]
+    toolchain = result["toolchain_name"]
+    id_name = result['id']
+    result_wrap = {0: result}
+    report[target][toolchain][id_name].append(result_wrap)
+
+def get_config(src_paths, target, toolchain_name):
+    """Get the configuration object for a target-toolchain combination
+
+    Positional arguments:
+    src_paths - paths to scan for the configuration files
+    target - the device we are building for
+    toolchain_name - the string that identifies the build tools
+    """
+    # Convert src_paths to a list if needed
+    if type(src_paths) != ListType:
+        src_paths = [src_paths]
+
+    # Pass all params to the unified prepare_resources()
+    toolchain = prepare_toolchain(src_paths, None, target, toolchain_name)
+
+    # Scan src_path for config files
+    resources = toolchain.scan_resources(src_paths[0])
+    for path in src_paths[1:]:
+        resources.add(toolchain.scan_resources(path))
+
+    # Update configuration files until added features creates no changes
+    prev_features = set()
+    while True:
+        # Update the configuration with any .json files found while scanning
+        toolchain.config.add_config_files(resources.json_files)
+
+        # Add features while we find new ones
+        features = set(toolchain.config.get_features())
+        if features == prev_features:
+            break
+
+        for feature in features:
+            if feature in resources.features:
+                resources += resources.features[feature]
+
+        prev_features = features
+    toolchain.config.validate_config()
+    if toolchain.config.has_regions:
+        _ = list(toolchain.config.regions)
+
+    cfg, macros = toolchain.config.get_config_data()
+    features = toolchain.config.get_features()
+    return cfg, macros, features
+
+def is_official_target(target_name, version):
+    """ Returns True, None if a target is part of the official release for the
+    given version. Return False, 'reason' if a target is not part of the
+    official release for the given version.
+
+    Positional arguments:
+    target_name - Name if the target (ex. 'K64F')
+    version - The release version string. Should be a string contained within
+              RELEASE_VERSIONS
+    """
+
+    result = True
+    reason = None
+    target = TARGET_MAP[target_name]
+
+    if hasattr(target, 'release_versions') \
+       and version in target.release_versions:
+        if version == '2':
+            # For version 2, either ARM or uARM toolchain support is required
+            required_toolchains = set(['ARM', 'uARM'])
+
+            if not len(required_toolchains.intersection(
+                    set(target.supported_toolchains))) > 0:
+                result = False
+                reason = ("Target '%s' must support " % target.name) + \
+                    ("one of the folowing toolchains to be included in the") + \
+                    ((" mbed 2.0 official release: %s" + linesep) %
+                     ", ".join(required_toolchains)) + \
+                    ("Currently it is only configured to support the ") + \
+                    ("following toolchains: %s" %
+                     ", ".join(target.supported_toolchains))
+
+        elif version == '5':
+            # For version 5, ARM, GCC_ARM, and IAR toolchain support is required
+            required_toolchains = set(['ARM', 'GCC_ARM', 'IAR'])
+            required_toolchains_sorted = list(required_toolchains)
+            required_toolchains_sorted.sort()
+            supported_toolchains = set(target.supported_toolchains)
+            supported_toolchains_sorted = list(supported_toolchains)
+            supported_toolchains_sorted.sort()
+
+            if not required_toolchains.issubset(supported_toolchains):
+                result = False
+                reason = ("Target '%s' must support " % target.name) + \
+                    ("ALL of the folowing toolchains to be included in the") + \
+                    ((" mbed OS 5.0 official release: %s" + linesep) %
+                     ", ".join(required_toolchains_sorted)) + \
+                    ("Currently it is only configured to support the ") + \
+                    ("following toolchains: %s" %
+                     ", ".join(supported_toolchains_sorted))
+
+            elif not target.default_lib == 'std':
+                result = False
+                reason = ("Target '%s' must set the " % target.name) + \
+                    ("'default_lib' to 'std' to be included in the ") + \
+                    ("mbed OS 5.0 official release." + linesep) + \
+                    ("Currently it is set to '%s'" % target.default_lib)
+
+        else:
+            result = False
+            reason = ("Target '%s' has set an invalid release version of '%s'" %
+                      version) + \
+                ("Please choose from the following release versions: %s" %
+                 ', '.join(RELEASE_VERSIONS))
+
+    else:
+        result = False
+        if not hasattr(target, 'release_versions'):
+            reason = "Target '%s' " % target.name
+            reason += "does not have the 'release_versions' key set"
+        elif not version in target.release_versions:
+            reason = "Target '%s' does not contain the version '%s' " % \
+                     (target.name, version)
+            reason += "in its 'release_versions' key"
+
+    return result, reason
+
+def transform_release_toolchains(toolchains, version):
+    """ Given a list of toolchains and a release version, return a list of
+    only the supported toolchains for that release
+
+    Positional arguments:
+    toolchains - The list of toolchains
+    version - The release version string. Should be a string contained within
+              RELEASE_VERSIONS
+    """
+    if version == '5':
+        return ['ARM', 'GCC_ARM', 'IAR']
+    else:
+        return toolchains
+
+
+def get_mbed_official_release(version):
+    """ Given a release version string, return a tuple that contains a target
+    and the supported toolchains for that release.
+    Ex. Given '2', return (('LPC1768', ('ARM', 'GCC_ARM')),
+                           ('K64F', ('ARM', 'GCC_ARM')), ...)
+
+    Positional arguments:
+    version - The version string. Should be a string contained within
+              RELEASE_VERSIONS
+    """
+
+    mbed_official_release = (
+        tuple(
+            tuple(
+                [
+                    TARGET_MAP[target].name,
+                    tuple(transform_release_toolchains(
+                        TARGET_MAP[target].supported_toolchains, version))
+                ]
+            ) for target in TARGET_NAMES \
+            if (hasattr(TARGET_MAP[target], 'release_versions')
+                and version in TARGET_MAP[target].release_versions)
+        )
+    )
+
+    for target in mbed_official_release:
+        is_official, reason = is_official_target(target[0], version)
+
+        if not is_official:
+            raise InvalidReleaseTargetException(reason)
+
+    return mbed_official_release
+
+def add_regions_to_profile(profile, config, toolchain_class):
+    """Add regions to the build profile, if there are any.
+
+    Positional Arguments:
+    profile - the profile to update
+    config - the configuration object that owns the region
+    toolchain_class - the class of the toolchain being used
+    """
+    if not profile:
+        return
+    regions = list(config.regions)
+    for region in regions:
+        for define in [(region.name.upper() + "_ADDR", region.start),
+                       (region.name.upper() + "_SIZE", region.size)]:
+            profile["common"].append("-D%s=0x%x" %  define)
+    active_region = [r for r in regions if r.active][0]
+    for define in [("MBED_APP_START", active_region.start),
+                   ("MBED_APP_SIZE", active_region.size)]:
+        profile["ld"].append(toolchain_class.make_ld_define(*define))
+
+    print("Using regions in this build:")
+    for region in regions:
+        print("  Region %s size 0x%x, offset 0x%x"
+              % (region.name, region.size, region.start))
+
+
+def prepare_toolchain(src_paths, build_dir, target, toolchain_name,
+                      macros=None, clean=False, jobs=1,
+                      notify=None, silent=False, verbose=False,
+                      extra_verbose=False, config=None,
+                      app_config=None, build_profile=None):
+    """ Prepares resource related objects - toolchain, target, config
+
+    Positional arguments:
+    src_paths - the paths to source directories
+    target - ['LPC1768', 'LPC11U24', etc.]
+    toolchain_name - ['ARM', 'uARM', 'GCC_ARM', 'GCC_CR']
+
+    Keyword arguments:
+    macros - additional macros
+    clean - Rebuild everything if True
+    jobs - how many compilers we can run at once
+    notify - Notify function for logs
+    silent - suppress printing of progress indicators
+    verbose - Write the actual tools command lines used if True
+    extra_verbose - even more output!
+    config - a Config object to use instead of creating one
+    app_config - location of a chosen mbed_app.json file
+    build_profile - a list of mergeable build profiles
+    """
+
+    # We need to remove all paths which are repeated to avoid
+    # multiple compilations and linking with the same objects
+    src_paths = [src_paths[0]] + list(set(src_paths[1:]))
+
+    # If the configuration object was not yet created, create it now
+    config = config or Config(target, src_paths, app_config=app_config)
+    target = config.target
+    try:
+        cur_tc = TOOLCHAIN_CLASSES[toolchain_name]
+    except KeyError:
+        raise KeyError("Toolchain %s not supported" % toolchain_name)
+
+    profile = {'c': [], 'cxx': [], 'common': [], 'asm': [], 'ld': []}
+    for contents in build_profile or []:
+        for key in profile:
+            profile[key].extend(contents[toolchain_name][key])
+
+    if config.has_regions:
+        add_regions_to_profile(profile, config, cur_tc)
+
+    toolchain = cur_tc(target, notify, macros, silent, build_dir=build_dir,
+                       extra_verbose=extra_verbose, build_profile=profile)
+
+    toolchain.config = config
+    toolchain.jobs = jobs
+    toolchain.build_all = clean
+    toolchain.VERBOSE = verbose
+
+    return toolchain
+
+def merge_region_list(region_list, destination, padding=b'\xFF'):
+    """Merege the region_list into a single image
+
+    Positional Arguments:
+    region_list - list of regions, which should contain filenames
+    destination - file name to write all regions to
+    padding - bytes to fill gapps with
+    """
+    merged = IntelHex()
+
+    print("Merging Regions:")
+
+    for region in region_list:
+        if region.active and not region.filename:
+            raise ToolException("Active region has no contents: No file found.")
+        if region.filename:
+            print("  Filling region %s with %s" % (region.name, region.filename))
+            part = intelhex_offset(region.filename, offset=region.start)
+            part_size = (part.maxaddr() - part.minaddr()) + 1
+            if part_size > region.size:
+                raise ToolException("Contents of region %s does not fit"
+                                    % region.name)
+            merged.merge(part)
+            pad_size = region.size - part_size
+            if pad_size > 0 and region != region_list[-1]:
+                print("  Padding region %s with 0x%x bytes" % (region.name, pad_size))
+                merged.puts(merged.maxaddr() + 1, padding * pad_size)
+
+    if not exists(dirname(destination)):
+        makedirs(dirname(destination))
+    print("Space used after regions merged: 0x%x" %
+          (merged.maxaddr() - merged.minaddr() + 1))
+    with open(destination, "wb+") as output:
+        merged.tofile(output, format='bin')
+
+def scan_resources(src_paths, toolchain, dependencies_paths=None,
+                   inc_dirs=None, base_path=None, collect_ignores=False):
+    """ Scan resources using initialized toolcain
+
+    Positional arguments
+    src_paths - the paths to source directories
+    toolchain - valid toolchain object
+    dependencies_paths - dependency paths that we should scan for include dirs
+    inc_dirs - additional include directories which should be added to
+               the scanner resources
+    """
+
+    # Scan src_path
+    resources = toolchain.scan_resources(src_paths[0], base_path=base_path,
+                                         collect_ignores=collect_ignores)
+    for path in src_paths[1:]:
+        resources.add(toolchain.scan_resources(path, base_path=base_path,
+                                               collect_ignores=collect_ignores))
+
+    # Scan dependency paths for include dirs
+    if dependencies_paths is not None:
+        for path in dependencies_paths:
+            lib_resources = toolchain.scan_resources(path)
+            resources.inc_dirs.extend(lib_resources.inc_dirs)
+
+    # Add additional include directories if passed
+    if inc_dirs:
+        if type(inc_dirs) == ListType:
+            resources.inc_dirs.extend(inc_dirs)
+        else:
+            resources.inc_dirs.append(inc_dirs)
+
+    # Load resources into the config system which might expand/modify resources
+    # based on config data
+    resources = toolchain.config.load_resources(resources)
+
+    # Set the toolchain's configuration data
+    toolchain.set_config_data(toolchain.config.get_config_data())
+
+    if  (hasattr(toolchain.target, "release_versions") and
+            "5" not in toolchain.target.release_versions and
+            "rtos" in toolchain.config.lib_config_data):
+        if "Cortex-A" in toolchain.target.core:
+            raise NotSupportedException(
+                ("%s Will be supported in mbed OS 5.6. "
+                    "To use the %s, please checkout the mbed OS 5.4 release branch. "
+                    "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice "
+                    "for more information") % (toolchain.target.name, toolchain.target.name))
+        else:
+            raise NotSupportedException("Target does not support mbed OS 5")
+
+    return resources
+
+def build_project(src_paths, build_path, target, toolchain_name,
+                  libraries_paths=None, linker_script=None,
+                  clean=False, notify=None, verbose=False, name=None,
+                  macros=None, inc_dirs=None, jobs=1, silent=False,
+                  report=None, properties=None, project_id=None,
+                  project_description=None, extra_verbose=False, config=None,
+                  app_config=None, build_profile=None, stats_depth=None):
+    """ Build a project. A project may be a test or a user program.
+
+    Positional arguments:
+    src_paths - a path or list of paths that contain all files needed to build
+                the project
+    build_path - the directory where all of the object files will be placed
+    target - the MCU or board that the project will compile for
+    toolchain_name - the name of the build tools
+
+    Keyword arguments:
+    libraries_paths - The location of libraries to include when linking
+    linker_script - the file that drives the linker to do it's job
+    clean - Rebuild everything if True
+    notify - Notify function for logs
+    verbose - Write the actual tools command lines used if True
+    name - the name of the project
+    macros - additional macros
+    inc_dirs - additional directories where include files may be found
+    jobs - how many compilers we can run at once
+    silent - suppress printing of progress indicators
+    report - a dict where a result may be appended
+    properties - UUUUHHHHH beats me
+    project_id - the name put in the report
+    project_description - the human-readable version of what this thing does
+    extra_verbose - even more output!
+    config - a Config object to use instead of creating one
+    app_config - location of a chosen mbed_app.json file
+    build_profile - a dict of flags that will be passed to the compiler
+    stats_depth - depth level for memap to display file/dirs
+    """
+
+    # Convert src_path to a list if needed
+    if type(src_paths) != ListType:
+        src_paths = [src_paths]
+    # Extend src_paths wiht libraries_paths
+    if libraries_paths is not None:
+        src_paths.extend(libraries_paths)
+        inc_dirs.extend(map(dirname, libraries_paths))
+
+    if clean and exists(build_path):
+        rmtree(build_path)
+    mkdir(build_path)
+
+    toolchain = prepare_toolchain(
+        src_paths, build_path, target, toolchain_name, macros=macros,
+        clean=clean, jobs=jobs, notify=notify, silent=silent, verbose=verbose,
+        extra_verbose=extra_verbose, config=config, app_config=app_config,
+        build_profile=build_profile)
+
+    # The first path will give the name to the library
+    name = (name or toolchain.config.name or
+            basename(normpath(abspath(src_paths[0]))))
+    toolchain.info("Building project %s (%s, %s)" %
+                   (name, toolchain.target.name, toolchain_name))
+
+    # Initialize reporting
+    if report != None:
+        start = time()
+        # If project_id is specified, use that over the default name
+        id_name = project_id.upper() if project_id else name.upper()
+        description = project_description if project_description else name
+        vendor_label = toolchain.target.extra_labels[0]
+        prep_report(report, toolchain.target.name, toolchain_name, id_name)
+        cur_result = create_result(toolchain.target.name, toolchain_name,
+                                   id_name, description)
+        if properties != None:
+            prep_properties(properties, toolchain.target.name, toolchain_name,
+                            vendor_label)
+
+    try:
+        # Call unified scan_resources
+        resources = scan_resources(src_paths, toolchain, inc_dirs=inc_dirs)
+
+        # Change linker script if specified
+        if linker_script is not None:
+            resources.linker_script = linker_script
+
+        # Compile Sources
+        objects = toolchain.compile_sources(resources, resources.inc_dirs)
+        resources.objects.extend(objects)
+
+        # Link Program
+        if toolchain.config.has_regions:
+            res, _ = toolchain.link_program(resources, build_path, name + "_application")
+            region_list = list(toolchain.config.regions)
+            region_list = [r._replace(filename=res) if r.active else r
+                           for r in region_list]
+            res = join(build_path, name) + ".bin"
+            merge_region_list(region_list, res)
+        else:
+            res, _ = toolchain.link_program(resources, build_path, name)
+
+        memap_instance = getattr(toolchain, 'memap_instance', None)
+        memap_table = ''
+        if memap_instance:
+            # Write output to stdout in text (pretty table) format
+            memap_table = memap_instance.generate_output('table', stats_depth)
+
+            if not silent:
+                print memap_table
+
+            # Write output to file in JSON format
+            map_out = join(build_path, name + "_map.json")
+            memap_instance.generate_output('json', stats_depth, map_out)
+
+            # Write output to file in CSV format for the CI
+            map_csv = join(build_path, name + "_map.csv")
+            memap_instance.generate_output('csv-ci', stats_depth, map_csv)
+
+        resources.detect_duplicates(toolchain)
+
+        if report != None:
+            end = time()
+            cur_result["elapsed_time"] = end - start
+            cur_result["output"] = toolchain.get_output() + memap_table
+            cur_result["result"] = "OK"
+            cur_result["memory_usage"] = memap_instance.mem_report
+            cur_result["bin"] = res
+            cur_result["elf"] = splitext(res)[0] + ".elf"
+            cur_result.update(toolchain.report)
+
+            add_result_to_report(report, cur_result)
+
+        return res
+
+    except Exception as exc:
+        if report != None:
+            end = time()
+
+            if isinstance(exc, NotSupportedException):
+                cur_result["result"] = "NOT_SUPPORTED"
+            else:
+                cur_result["result"] = "FAIL"
+
+            cur_result["elapsed_time"] = end - start
+
+            toolchain_output = toolchain.get_output()
+            if toolchain_output:
+                cur_result["output"] += toolchain_output
+
+            add_result_to_report(report, cur_result)
+
+        # Let Exception propagate
+        raise
+
+def build_library(src_paths, build_path, target, toolchain_name,
+                  dependencies_paths=None, name=None, clean=False,
+                  archive=True, notify=None, verbose=False, macros=None,
+                  inc_dirs=None, jobs=1, silent=False, report=None,
+                  properties=None, extra_verbose=False, project_id=None,
+                  remove_config_header_file=False, app_config=None,
+                  build_profile=None):
+    """ Build a library
+
+    Positional arguments:
+    src_paths - a path or list of paths that contain all files needed to build
+                the library
+    build_path - the directory where all of the object files will be placed
+    target - the MCU or board that the project will compile for
+    toolchain_name - the name of the build tools
+
+    Keyword arguments:
+    dependencies_paths - The location of libraries to include when linking
+    name - the name of the library
+    clean - Rebuild everything if True
+    archive - whether the library will create an archive file
+    notify - Notify function for logs
+    verbose - Write the actual tools command lines used if True
+    macros - additional macros
+    inc_dirs - additional directories where include files may be found
+    jobs - how many compilers we can run at once
+    silent - suppress printing of progress indicators
+    report - a dict where a result may be appended
+    properties - UUUUHHHHH beats me
+    extra_verbose - even more output!
+    project_id - the name that goes in the report
+    remove_config_header_file - delete config header file when done building
+    app_config - location of a chosen mbed_app.json file
+    build_profile - a dict of flags that will be passed to the compiler
+    """
+
+    # Convert src_path to a list if needed
+    if type(src_paths) != ListType:
+        src_paths = [src_paths]
+
+    # Build path
+    if archive:
+        # Use temp path when building archive
+        tmp_path = join(build_path, '.temp')
+        mkdir(tmp_path)
+    else:
+        tmp_path = build_path
+
+    # Clean the build directory
+    if clean and exists(tmp_path):
+        rmtree(tmp_path)
+    mkdir(tmp_path)
+
+    # Pass all params to the unified prepare_toolchain()
+    toolchain = prepare_toolchain(
+        src_paths, build_path, target, toolchain_name, macros=macros,
+        clean=clean, jobs=jobs, notify=notify, silent=silent,
+        verbose=verbose, extra_verbose=extra_verbose, app_config=app_config,
+        build_profile=build_profile)
+
+    # The first path will give the name to the library
+    if name is None:
+        name = basename(normpath(abspath(src_paths[0])))
+    toolchain.info("Building library %s (%s, %s)" %
+                   (name, toolchain.target.name, toolchain_name))
+
+    # Initialize reporting
+    if report != None:
+        start = time()
+        # If project_id is specified, use that over the default name
+        id_name = project_id.upper() if project_id else name.upper()
+        description = name
+        vendor_label = toolchain.target.extra_labels[0]
+        prep_report(report, toolchain.target.name, toolchain_name, id_name)
+        cur_result = create_result(toolchain.target.name, toolchain_name,
+                                   id_name, description)
+        cur_result['type'] = 'library'
+        if properties != None:
+            prep_properties(properties, toolchain.target.name, toolchain_name,
+                            vendor_label)
+
+    for src_path in src_paths:
+        if not exists(src_path):
+            error_msg = "The library source folder does not exist: %s", src_path
+            if report != None:
+                cur_result["output"] = error_msg
+                cur_result["result"] = "FAIL"
+                add_result_to_report(report, cur_result)
+            raise Exception(error_msg)
+
+    try:
+        # Call unified scan_resources
+        resources = scan_resources(src_paths, toolchain,
+                                   dependencies_paths=dependencies_paths,
+                                   inc_dirs=inc_dirs)
+
+
+        # Copy headers, objects and static libraries - all files needed for
+        # static lib
+        toolchain.copy_files(resources.headers, build_path, resources=resources)
+        toolchain.copy_files(resources.objects, build_path, resources=resources)
+        toolchain.copy_files(resources.libraries, build_path,
+                             resources=resources)
+        toolchain.copy_files(resources.json_files, build_path,
+                             resources=resources)
+        if resources.linker_script:
+            toolchain.copy_files(resources.linker_script, build_path,
+                                 resources=resources)
+
+        if resources.hex_files:
+            toolchain.copy_files(resources.hex_files, build_path,
+                                 resources=resources)
+
+        # Compile Sources
+        objects = toolchain.compile_sources(resources, resources.inc_dirs)
+        resources.objects.extend(objects)
+
+        if archive:
+            toolchain.build_library(objects, build_path, name)
+
+        if remove_config_header_file:
+            config_header_path = toolchain.get_config_header()
+            if config_header_path:
+                remove(config_header_path)
+
+        if report != None:
+            end = time()
+            cur_result["elapsed_time"] = end - start
+            cur_result["output"] = toolchain.get_output()
+            cur_result["result"] = "OK"
+
+
+            add_result_to_report(report, cur_result)
+        return True
+
+    except Exception as exc:
+        if report != None:
+            end = time()
+
+            if isinstance(exc, ToolException):
+                cur_result["result"] = "FAIL"
+            elif isinstance(exc, NotSupportedException):
+                cur_result["result"] = "NOT_SUPPORTED"
+
+            cur_result["elapsed_time"] = end - start
+
+            toolchain_output = toolchain.get_output()
+            if toolchain_output:
+                cur_result["output"] += toolchain_output
+
+            add_result_to_report(report, cur_result)
+
+        # Let Exception propagate
+        raise
+
+######################
+### Legacy methods ###
+######################
+
+def mbed2_obj_path(target_name, toolchain_name):
+    real_tc_name = TOOLCHAIN_CLASSES[toolchain_name].__name__
+    return join("TARGET_" + target_name, "TOOLCHAIN_" + real_tc_name)
+
+def build_lib(lib_id, target, toolchain_name, verbose=False,
+              clean=False, macros=None, notify=None, jobs=1, silent=False,
+              report=None, properties=None, extra_verbose=False,
+              build_profile=None):
+    """ Legacy method for building mbed libraries
+
+    Positional arguments:
+    lib_id - the library's unique identifier
+    target - the MCU or board that the project will compile for
+    toolchain_name - the name of the build tools
+
+    Keyword arguments:
+    clean - Rebuild everything if True
+    verbose - Write the actual tools command lines used if True
+    macros - additional macros
+    notify - Notify function for logs
+    jobs - how many compilers we can run at once
+    silent - suppress printing of progress indicators
+    report - a dict where a result may be appended
+    properties - UUUUHHHHH beats me
+    extra_verbose - even more output!
+    build_profile - a dict of flags that will be passed to the compiler
+    """
+    lib = Library(lib_id)
+    if not lib.is_supported(target, toolchain_name):
+        print('Library "%s" is not yet supported on target %s with toolchain %s'
+              % (lib_id, target.name, toolchain_name))
+        return False
+
+    # We need to combine macros from parameter list with macros from library
+    # definition
+    lib_macros = lib.macros if lib.macros else []
+    if macros:
+        macros.extend(lib_macros)
+    else:
+        macros = lib_macros
+
+    src_paths = lib.source_dir
+    build_path = lib.build_dir
+    dependencies_paths = lib.dependencies
+    inc_dirs = lib.inc_dirs
+    inc_dirs_ext = lib.inc_dirs_ext
+
+    if type(src_paths) != ListType:
+        src_paths = [src_paths]
+
+    # The first path will give the name to the library
+    name = basename(src_paths[0])
+
+    if report != None:
+        start = time()
+        id_name = name.upper()
+        description = name
+        vendor_label = target.extra_labels[0]
+        cur_result = None
+        prep_report(report, target.name, toolchain_name, id_name)
+        cur_result = create_result(target.name, toolchain_name, id_name,
+                                   description)
+
+        if properties != None:
+            prep_properties(properties, target.name, toolchain_name,
+                            vendor_label)
+
+    for src_path in src_paths:
+        if not exists(src_path):
+            error_msg = "The library source folder does not exist: %s", src_path
+
+            if report != None:
+                cur_result["output"] = error_msg
+                cur_result["result"] = "FAIL"
+                add_result_to_report(report, cur_result)
+
+            raise Exception(error_msg)
+
+    try:
+        # Toolchain instance
+        # Create the desired build directory structure
+        bin_path = join(build_path, mbed2_obj_path(target.name, toolchain_name))
+        mkdir(bin_path)
+        tmp_path = join(build_path, '.temp', mbed2_obj_path(target.name,
+                                                            toolchain_name))
+        mkdir(tmp_path)
+
+        toolchain = prepare_toolchain(
+            src_paths, tmp_path, target, toolchain_name, macros=macros,
+            notify=notify, silent=silent, extra_verbose=extra_verbose,
+            build_profile=build_profile, jobs=jobs, clean=clean)
+
+        toolchain.info("Building library %s (%s, %s)" %
+                       (name.upper(), target.name, toolchain_name))
+
+        # Take into account the library configuration (MBED_CONFIG_FILE)
+        config = toolchain.config
+        config.add_config_files([MBED_CONFIG_FILE])
+
+        # Scan Resources
+        resources = []
+        for src_path in src_paths:
+            resources.append(toolchain.scan_resources(src_path))
+
+        # Add extra include directories / files which are required by library
+        # This files usually are not in the same directory as source files so
+        # previous scan will not include them
+        if inc_dirs_ext is not None:
+            for inc_ext in inc_dirs_ext:
+                resources.append(toolchain.scan_resources(inc_ext))
+
+        # Dependencies Include Paths
+        dependencies_include_dir = []
+        if dependencies_paths is not None:
+            for path in dependencies_paths:
+                lib_resources = toolchain.scan_resources(path)
+                dependencies_include_dir.extend(lib_resources.inc_dirs)
+                dependencies_include_dir.extend(map(dirname, lib_resources.inc_dirs))
+
+        if inc_dirs:
+            dependencies_include_dir.extend(inc_dirs)
+
+        # Add other discovered configuration data to the configuration object
+        for res in resources:
+            config.load_resources(res)
+        toolchain.set_config_data(toolchain.config.get_config_data())
+
+
+        # Copy Headers
+        for resource in resources:
+            toolchain.copy_files(resource.headers, build_path,
+                                 resources=resource)
+
+        dependencies_include_dir.extend(
+            toolchain.scan_resources(build_path).inc_dirs)
+
+        # Compile Sources
+        objects = []
+        for resource in resources:
+            objects.extend(toolchain.compile_sources(resource, dependencies_include_dir))
+
+        needed_update = toolchain.build_library(objects, bin_path, name)
+
+        if report != None and needed_update:
+            end = time()
+            cur_result["elapsed_time"] = end - start
+            cur_result["output"] = toolchain.get_output()
+            cur_result["result"] = "OK"
+
+            add_result_to_report(report, cur_result)
+        return True
+
+    except Exception:
+        if report != None:
+            end = time()
+            cur_result["result"] = "FAIL"
+            cur_result["elapsed_time"] = end - start
+
+            toolchain_output = toolchain.get_output()
+            if toolchain_output:
+                cur_result["output"] += toolchain_output
+
+            add_result_to_report(report, cur_result)
+
+        # Let Exception propagate
+        raise
+
+# We do have unique legacy conventions about how we build and package the mbed
+# library
+def build_mbed_libs(target, toolchain_name, verbose=False,
+                    clean=False, macros=None, notify=None, jobs=1, silent=False,
+                    report=None, properties=None, extra_verbose=False,
+                    build_profile=None):
+    """ Function returns True is library was built and false if building was
+    skipped
+
+    Positional arguments:
+    target - the MCU or board that the project will compile for
+    toolchain_name - the name of the build tools
+
+    Keyword arguments:
+    verbose - Write the actual tools command lines used if True
+    clean - Rebuild everything if True
+    macros - additional macros
+    notify - Notify function for logs
+    jobs - how many compilers we can run at once
+    silent - suppress printing of progress indicators
+    report - a dict where a result may be appended
+    properties - UUUUHHHHH beats me
+    extra_verbose - even more output!
+    build_profile - a dict of flags that will be passed to the compiler
+    """
+
+    if report != None:
+        start = time()
+        id_name = "MBED"
+        description = "mbed SDK"
+        vendor_label = target.extra_labels[0]
+        cur_result = None
+        prep_report(report, target.name, toolchain_name, id_name)
+        cur_result = create_result(target.name, toolchain_name, id_name,
+                                   description)
+
+        if properties != None:
+            prep_properties(properties, target.name, toolchain_name,
+                            vendor_label)
+
+    # Check toolchain support
+    if toolchain_name not in target.supported_toolchains:
+        supported_toolchains_text = ", ".join(target.supported_toolchains)
+        print('%s target is not yet supported by toolchain %s' %
+              (target.name, toolchain_name))
+        print('%s target supports %s toolchain%s' %
+              (target.name, supported_toolchains_text, 's'
+               if len(target.supported_toolchains) > 1 else ''))
+
+        if report != None:
+            cur_result["result"] = "SKIP"
+            add_result_to_report(report, cur_result)
+
+        return False
+
+    try:
+        # Source and Build Paths
+        build_target = join(MBED_LIBRARIES, "TARGET_" + target.name)
+        build_toolchain = join(MBED_LIBRARIES, mbed2_obj_path(target.name, toolchain_name))
+        mkdir(build_toolchain)
+
+        # Toolchain
+        tmp_path = join(MBED_LIBRARIES, '.temp', mbed2_obj_path(target.name, toolchain_name))
+        mkdir(tmp_path)
+
+        toolchain = prepare_toolchain(
+            [""], tmp_path, target, toolchain_name, macros=macros,verbose=verbose,
+            notify=notify, silent=silent, extra_verbose=extra_verbose,
+            build_profile=build_profile, jobs=jobs, clean=clean)
+
+        # Take into account the library configuration (MBED_CONFIG_FILE)
+        config = toolchain.config
+        config.add_config_files([MBED_CONFIG_FILE])
+        toolchain.set_config_data(toolchain.config.get_config_data())
+
+        # CMSIS
+        toolchain.info("Building library %s (%s, %s)" %
+                       ('CMSIS', target.name, toolchain_name))
+        cmsis_src = MBED_CMSIS_PATH
+        resources = toolchain.scan_resources(cmsis_src)
+
+        toolchain.copy_files(resources.headers, build_target)
+        toolchain.copy_files(resources.linker_script, build_toolchain)
+        toolchain.copy_files(resources.bin_files, build_toolchain)
+
+        objects = toolchain.compile_sources(resources, tmp_path)
+        toolchain.copy_files(objects, build_toolchain)
+
+        # mbed
+        toolchain.info("Building library %s (%s, %s)" %
+                       ('MBED', target.name, toolchain_name))
+
+        # Common Headers
+        toolchain.copy_files([MBED_HEADER], MBED_LIBRARIES)
+        library_incdirs = [dirname(MBED_LIBRARIES), MBED_LIBRARIES]
+
+        for dir, dest in [(MBED_DRIVERS, MBED_LIBRARIES_DRIVERS),
+                          (MBED_PLATFORM, MBED_LIBRARIES_PLATFORM),
+                          (MBED_HAL, MBED_LIBRARIES_HAL)]:
+            resources = toolchain.scan_resources(dir)
+            toolchain.copy_files(resources.headers, dest)
+            library_incdirs.append(dest)
+
+        # Target specific sources
+        hal_src = MBED_TARGETS_PATH
+        hal_implementation = toolchain.scan_resources(hal_src)
+        toolchain.copy_files(hal_implementation.headers +
+                             hal_implementation.hex_files +
+                             hal_implementation.libraries +
+                             [MBED_CONFIG_FILE],
+                             build_target, resources=hal_implementation)
+        toolchain.copy_files(hal_implementation.linker_script, build_toolchain)
+        toolchain.copy_files(hal_implementation.bin_files, build_toolchain)
+        incdirs = toolchain.scan_resources(build_target).inc_dirs
+        objects = toolchain.compile_sources(hal_implementation,
+                                            library_incdirs + incdirs)
+        toolchain.copy_files(objects, build_toolchain)
+
+        # Common Sources
+        mbed_resources = None
+        for dir in [MBED_DRIVERS, MBED_PLATFORM, MBED_HAL]:
+            mbed_resources += toolchain.scan_resources(dir)
+
+        objects = toolchain.compile_sources(mbed_resources,
+                                            library_incdirs + incdirs)
+
+        # A number of compiled files need to be copied as objects as opposed to
+        # way the linker search for symbols in archives. These are:
+        #   - mbed_retarget.o: to make sure that the C standard lib symbols get
+        #                 overridden
+        #   - mbed_board.o: mbed_die is weak
+        #   - mbed_overrides.o: this contains platform overrides of various
+        #                       weak SDK functions
+        #   - mbed_main.o: this contains main redirection
+        separate_names, separate_objects = ['mbed_retarget.o', 'mbed_board.o',
+                                            'mbed_overrides.o', 'mbed_main.o', 'mbed_sdk_boot.o'], []
+
+        for obj in objects:
+            for name in separate_names:
+                if obj.endswith(name):
+                    separate_objects.append(obj)
+
+        for obj in separate_objects:
+            objects.remove(obj)
+
+        toolchain.build_library(objects, build_toolchain, "mbed")
+
+        for obj in separate_objects:
+            toolchain.copy_files(obj, build_toolchain)
+
+        if report != None:
+            end = time()
+            cur_result["elapsed_time"] = end - start
+            cur_result["output"] = toolchain.get_output()
+            cur_result["result"] = "OK"
+
+            add_result_to_report(report, cur_result)
+
+        return True
+
+    except Exception as exc:
+        if report != None:
+            end = time()
+            cur_result["result"] = "FAIL"
+            cur_result["elapsed_time"] = end - start
+
+            toolchain_output = toolchain.get_output()
+            if toolchain_output:
+                cur_result["output"] += toolchain_output
+
+            cur_result["output"] += str(exc)
+
+            add_result_to_report(report, cur_result)
+
+        # Let Exception propagate
+        raise
+
+
+def get_unique_supported_toolchains(release_targets=None):
+    """ Get list of all unique toolchains supported by targets
+
+    Keyword arguments:
+    release_targets - tuple structure returned from get_mbed_official_release().
+                      If release_targets is not specified, then it queries all
+                      known targets
+    """
+    unique_supported_toolchains = []
+
+    if not release_targets:
+        for target in TARGET_NAMES:
+            for toolchain in TARGET_MAP[target].supported_toolchains:
+                if toolchain not in unique_supported_toolchains:
+                    unique_supported_toolchains.append(toolchain)
+    else:
+        for target in release_targets:
+            for toolchain in target[1]:
+                if toolchain not in unique_supported_toolchains:
+                    unique_supported_toolchains.append(toolchain)
+
+    if "ARM" in unique_supported_toolchains:
+        unique_supported_toolchains.append("ARMC6")
+
+    return unique_supported_toolchains
+
+def mcu_toolchain_list(release_version='5'):
+    """  Shows list of toolchains
+
+    """
+
+    if isinstance(release_version, basestring):
+        # Force release_version to lowercase if it is a string
+        release_version = release_version.lower()
+    else:
+        # Otherwise default to printing all known targets and toolchains
+        release_version = 'all'
+
+
+    version_release_targets = {}
+    version_release_target_names = {}
+
+    for version in RELEASE_VERSIONS:
+        version_release_targets[version] = get_mbed_official_release(version)
+        version_release_target_names[version] = [x[0] for x in
+                                                 version_release_targets[
+                                                     version]]
+
+    if release_version in RELEASE_VERSIONS:
+        release_targets = version_release_targets[release_version]
+    else:
+        release_targets = None
+
+    unique_supported_toolchains = get_unique_supported_toolchains(
+        release_targets)
+    columns = ["mbed OS %s" % x for x in RELEASE_VERSIONS] + unique_supported_toolchains
+    return "\n".join(columns)
+
+
+def mcu_target_list(release_version='5'):
+    """  Shows target list
+
+    """
+
+    if isinstance(release_version, basestring):
+        # Force release_version to lowercase if it is a string
+        release_version = release_version.lower()
+    else:
+        # Otherwise default to printing all known targets and toolchains
+        release_version = 'all'
+
+
+    version_release_targets = {}
+    version_release_target_names = {}
+
+    for version in RELEASE_VERSIONS:
+        version_release_targets[version] = get_mbed_official_release(version)
+        version_release_target_names[version] = [x[0] for x in
+                                                 version_release_targets[
+                                                     version]]
+
+    if release_version in RELEASE_VERSIONS:
+        release_targets = version_release_targets[release_version]
+    else:
+        release_targets = None
+
+    target_names = []
+
+    if release_targets:
+        target_names = [x[0] for x in release_targets]
+    else:
+        target_names = TARGET_NAMES
+
+    return "\n".join(target_names)
+
+
+def mcu_toolchain_matrix(verbose_html=False, platform_filter=None,
+                         release_version='5'):
+    """  Shows target map using prettytable
+
+    Keyword arguments:
+    verbose_html - emit html instead of a simple table
+    platform_filter - remove results that match the string
+    release_version - get the matrix for this major version number
+    """
+    # Only use it in this function so building works without extra modules
+    from prettytable import PrettyTable
+
+    if isinstance(release_version, basestring):
+        # Force release_version to lowercase if it is a string
+        release_version = release_version.lower()
+    else:
+        # Otherwise default to printing all known targets and toolchains
+        release_version = 'all'
+
+
+    version_release_targets = {}
+    version_release_target_names = {}
+
+    for version in RELEASE_VERSIONS:
+        version_release_targets[version] = get_mbed_official_release(version)
+        version_release_target_names[version] = [x[0] for x in
+                                                 version_release_targets[
+                                                     version]]
+
+    if release_version in RELEASE_VERSIONS:
+        release_targets = version_release_targets[release_version]
+    else:
+        release_targets = None
+
+    unique_supported_toolchains = get_unique_supported_toolchains(
+        release_targets)
+    prepend_columns = ["Target"] + ["mbed OS %s" % x for x in RELEASE_VERSIONS]
+
+    # All tests status table print
+    columns = prepend_columns + unique_supported_toolchains
+    table_printer = PrettyTable(columns)
+    # Align table
+    for col in columns:
+        table_printer.align[col] = "c"
+    table_printer.align["Target"] = "l"
+
+    perm_counter = 0
+    target_counter = 0
+
+    target_names = []
+
+    if release_targets:
+        target_names = [x[0] for x in release_targets]
+    else:
+        target_names = TARGET_NAMES
+
+    for target in sorted(target_names):
+        if platform_filter is not None:
+            # FIlter out platforms using regex
+            if re.search(platform_filter, target) is None:
+                continue
+        target_counter += 1
+
+        row = [target]  # First column is platform name
+
+        for version in RELEASE_VERSIONS:
+            if target in version_release_target_names[version]:
+                text = "Supported"
+            else:
+                text = "-"
+            row.append(text)
+
+        for unique_toolchain in unique_supported_toolchains:
+            if (unique_toolchain in TARGET_MAP[target].supported_toolchains or
+                (unique_toolchain == "ARMC6" and
+                 "ARM" in TARGET_MAP[target].supported_toolchains)):
+                text = "Supported"
+                perm_counter += 1
+            else:
+                text = "-"
+
+            row.append(text)
+        table_printer.add_row(row)
+
+    result = table_printer.get_html_string() if verbose_html \
+             else table_printer.get_string()
+    result += "\n"
+    result += "Supported targets: %d\n"% (target_counter)
+    if target_counter == 1:
+        result += "Supported toolchains: %d"% (perm_counter)
+    return result
+
+
+def get_target_supported_toolchains(target):
+    """ Returns target supported toolchains list
+
+    Positional arguments:
+    target - the target to get the supported toolchains of
+    """
+    return TARGET_MAP[target].supported_toolchains if target in TARGET_MAP \
+        else None
+
+
+def print_build_results(result_list, build_name):
+    """ Generate result string for build results
+
+    Positional arguments:
+    result_list - the list of results to print
+    build_name - the name of the build we are printing result for
+    """
+    result = ""
+    if len(result_list) > 0:
+        result += build_name + "\n"
+        result += "\n".join(["  * %s" % f for f in result_list])
+        result += "\n"
+    return result
+
+def print_build_memory_usage(report):
+    """ Generate result table with memory usage values for build results
+    Aggregates (puts together) reports obtained from self.get_memory_summary()
+
+    Positional arguments:
+    report - Report generated during build procedure.
+    """
+    from prettytable import PrettyTable
+    columns_text = ['name', 'target', 'toolchain']
+    columns_int = ['static_ram', 'total_flash']
+    table = PrettyTable(columns_text + columns_int)
+
+    for col in columns_text:
+        table.align[col] = 'l'
+
+    for col in columns_int:
+        table.align[col] = 'r'
+
+    for target in report:
+        for toolchain in report[target]:
+            for name in report[target][toolchain]:
+                for dlist in report[target][toolchain][name]:
+                    for dlistelem in dlist:
+                        # Get 'memory_usage' record and build table with
+                        # statistics
+                        record = dlist[dlistelem]
+                        if 'memory_usage' in record and record['memory_usage']:
+                            # Note that summary should be in the last record of
+                            # 'memory_usage' section. This is why we are
+                            # grabbing last "[-1]" record.
+                            row = [
+                                record['description'],
+                                record['target_name'],
+                                record['toolchain_name'],
+                                record['memory_usage'][-1]['summary'][
+                                    'static_ram'],
+                                record['memory_usage'][-1]['summary'][
+                                    'total_flash'],
+                            ]
+                            table.add_row(row)
+
+    result = "Memory map breakdown for built projects (values in Bytes):\n"
+    result += table.get_string(sortby='name')
+    return result
+
+def write_build_report(build_report, template_filename, filename):
+    """Write a build report to disk using a template file
+
+    Positional arguments:
+    build_report - a report generated by the build system
+    template_filename - a file that contains the template for the style of build
+                        report
+    filename - the location on disk to write the file to
+    """
+    build_report_failing = []
+    build_report_passing = []
+
+    for report in build_report:
+        if len(report["failing"]) > 0:
+            build_report_failing.append(report)
+        else:
+            build_report_passing.append(report)
+
+    env = Environment(extensions=['jinja2.ext.with_'])
+    env.loader = FileSystemLoader('ci_templates')
+    template = env.get_template(template_filename)
+
+    with open(filename, 'w+') as placeholder:
+        placeholder.write(template.render(
+            failing_builds=build_report_failing,
+            passing_builds=build_report_passing))
+
+
+def merge_build_data(filename, toolchain_report, app_type):
+    path_to_file = dirname(abspath(filename))
+    try:
+        build_data = load(open(filename))
+    except (IOError, ValueError):
+        build_data = {'builds': []}
+    for tgt in toolchain_report.values():
+        for tc in tgt.values():
+            for project in tc.values():
+                for build in project:
+                    try:
+                        build[0]['elf'] = relpath(build[0]['elf'], path_to_file)
+                        build[0]['bin'] = relpath(build[0]['bin'], path_to_file)
+                    except KeyError:
+                        pass
+                    if 'type' not in build[0]:
+                        build[0]['type'] = app_type
+                    build_data['builds'].append(build[0])
+    dump(build_data, open(filename, "wb"), indent=4, separators=(',', ': '))
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_api.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_api.pyc
new file mode 100755
index 0000000..87aced4
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_api.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_everything.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_everything.py
new file mode 100755
index 0000000..a782dd2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_everything.py
@@ -0,0 +1,239 @@
+#! /usr/bin/env python
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import sys
+from time import time
+from os.path import join, abspath, dirname, normpath
+from optparse import OptionParser
+import json
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.build_api import build_library
+from tools.build_api import write_build_report
+from tools.targets import TARGET_MAP, TARGET_NAMES
+from tools.toolchains import TOOLCHAINS
+from tools.test_exporters import ReportExporter, ResultExporterType
+from tools.test_api import find_tests, build_tests, test_spec_from_test_builds
+from tools.build_release import OFFICIAL_MBED_LIBRARY_BUILD
+
+if __name__ == '__main__':
+    try:
+        parser = OptionParser()
+        
+        parser.add_option("--source", dest="source_dir",
+                          default=None, help="The source (input) directory (for sources other than tests). Defaults to current directory.", action="append")
+                          
+        parser.add_option("--build", dest="build_dir",
+                          default=None, help="The build (output) directory")
+        
+        parser.add_option('-c', '--clean',
+                          dest='clean',
+                          metavar=False,
+                          action="store_true",
+                          help='Clean the build directory')
+        
+        parser.add_option('-a', '--all', dest="all", default=False, action="store_true",
+                          help="Build every target (including unofficial targets) and with each of the supported toolchains")
+                          
+        parser.add_option('-o', '--official', dest="official_only", default=False, action="store_true",
+                          help="Build using only the official toolchain for each target")
+                          
+        parser.add_option("-D", "",
+                          action="append",
+                          dest="macros",
+                          help="Add a macro definition")
+                          
+        parser.add_option("-j", "--jobs", type="int", dest="jobs",
+                          default=0, help="Number of concurrent jobs. Default: 0/auto (based on host machine's number of CPUs)")
+                          
+        parser.add_option("-v", "--verbose", action="store_true", dest="verbose",
+                          default=False, help="Verbose diagnostic output")
+                          
+        parser.add_option("-t", "--toolchains", dest="toolchains", help="Use toolchains names separated by comma")
+
+        parser.add_option("-p", "--platforms", dest="platforms", default="", help="Build only for the platform namesseparated by comma")
+
+        parser.add_option("", "--config", action="store_true", dest="list_config",
+                          default=False, help="List the platforms and toolchains in the release in JSON")
+        
+        parser.add_option("", "--test-spec", dest="test_spec",
+                          default=None, help="Destination path for a test spec file that can be used by the Greentea automated test tool")
+
+        parser.add_option("", "--build-report-junit", dest="build_report_junit", help="Output the build results to an junit xml file")
+        
+        parser.add_option("--continue-on-build-fail", action="store_true", dest="continue_on_build_fail",
+                          default=False, help="Continue trying to build all tests if a build failure occurs")
+
+        options, args = parser.parse_args()
+        
+        # Get set of valid targets
+        all_platforms = set(TARGET_NAMES)
+        bad_platforms = set()
+        platforms = set()
+        if options.platforms != "":
+            platforms = set(options.platforms.split(","))
+            bad_platforms = platforms.difference(all_platforms)
+            platforms = platforms.intersection(all_platforms)
+        elif options.all:
+            platforms = all_platforms
+        else:
+            platforms = set(x[0] for x in OFFICIAL_MBED_LIBRARY_BUILD)
+            bad_platforms = platforms.difference(all_platforms)
+            platforms = platforms.intersection(all_platforms)
+        
+        for bad_platform in bad_platforms:
+            print "Platform '%s' is not a valid platform. Skipping." % bad_platform
+        
+        if options.platforms:
+            print "Limiting build to the following platforms: %s" % ",".join(platforms)
+        
+        # Get set of valid toolchains
+        all_toolchains = set(TOOLCHAINS)
+        bad_toolchains = set()
+        toolchains = set()
+        
+        if options.toolchains:
+            toolchains = set(options.toolchains.split(","))
+            bad_toolchains = toolchains.difference(all_toolchains)
+            toolchains = toolchains.intersection(all_toolchains)
+        else:
+            toolchains = all_toolchains
+        
+        for bad_toolchain in bad_toolchains:
+            print "Toolchain '%s' is not a valid toolchain. Skipping." % bad_toolchain
+        
+        if options.toolchains:
+            print "Limiting build to the following toolchains: %s" % ",".join(toolchains)
+        
+        build_config = {}
+        
+        for platform in platforms:
+            target = TARGET_MAP[platform]
+            
+            if options.official_only:
+                default_toolchain = getattr(target, 'default_toolchain', 'ARM')
+                build_config[platform] = list(toolchains.intersection(set([default_toolchain])))
+            else:
+                build_config[platform] = list(toolchains.intersection(set(target.supported_toolchains)))
+        
+        if options.list_config:
+            print json.dumps(build_config, indent=4)
+            sys.exit(0)
+        
+        # Ensure build directory is set
+        if not options.build_dir:
+            print "[ERROR] You must specify a build path"
+            sys.exit(1)
+        
+        # Default base source path is the current directory
+        base_source_paths = options.source_dir
+        if not base_source_paths:
+            base_source_paths = ['.']
+        
+        
+        start = time()    
+        build_report = {}
+        build_properties = {}
+        test_builds = {}
+        total_build_success = True
+
+        for target_name, target_toolchains in build_config.iteritems():
+            target = TARGET_MAP[target_name]
+            
+            for target_toolchain in target_toolchains:
+                library_build_success = True
+                
+                try:
+                    build_directory = join(options.build_dir, target_name, target_toolchain)
+                    # Build sources
+                    build_library(base_source_paths, build_directory, target, target_toolchain,
+                                                    jobs=options.jobs,
+                                                    clean=options.clean,
+                                                    report=build_report,
+                                                    properties=build_properties,
+                                                    name="mbed-os",
+                                                    macros=options.macros,
+                                                    verbose=options.verbose,
+                                                    archive=False)
+                except Exception, e:
+                    library_build_success = False
+                    print "Failed to build library"
+                    print e
+                    
+                if options.continue_on_build_fail or library_build_success:
+                    # Build all the tests
+                    all_tests = find_tests(base_source_paths[0], target_name, toolchain_name)
+                    test_build_success, test_build = build_tests(all_tests, [build_directory], build_directory, target, target_toolchain,
+                            clean=options.clean,
+                            report=build_report,
+                            properties=build_properties,
+                            macros=options.macros,
+                            verbose=options.verbose,
+                            jobs=options.jobs,
+                            continue_on_build_fail=options.continue_on_build_fail)
+                            
+                    if not test_build_success:
+                        total_build_success = False
+                        print "Failed to build some tests, check build log for details"
+                    
+                    test_builds.update(test_build)
+                else:
+                    total_build_success = False
+                    break
+            
+        # If a path to a test spec is provided, write it to a file
+        if options.test_spec:
+            test_spec_data = test_spec_from_test_builds(test_builds)
+            
+            # Create the target dir for the test spec if necessary
+            # mkdir will not create the dir if it already exists
+            test_spec_dir = dirname(options.test_spec)
+            if test_spec_dir:
+                mkdir(test_spec_dir)
+            
+            try:
+                with open(options.test_spec, 'w') as f:
+                    f.write(json.dumps(test_spec_data, indent=2))
+            except IOError, e:
+                print "[ERROR] Error writing test spec to file"
+                print e
+        
+        # If a path to a JUnit build report spec is provided, write it to a file
+        if options.build_report_junit:
+            report_exporter = ReportExporter(ResultExporterType.JUNIT)
+            report_exporter.report_to_file(build_report, options.build_report_junit, test_suite_properties=build_properties)
+
+        print "\n\nCompleted in: (%.2f)s" % (time() - start)
+
+        print_report_exporter = ReportExporter(ResultExporterType.PRINT, package="build")
+        status = print_report_exporter.report(build_report)
+
+        if status:
+            sys.exit(0)
+        else:
+            sys.exit(1)
+    
+    except KeyboardInterrupt, e:
+        print "\n[CTRL+c] exit"
+    except Exception,e:
+        import traceback
+        traceback.print_exc(file=sys.stdout)
+        print "[ERROR] %s" % str(e)
+        sys.exit(1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_release.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_release.py
new file mode 100755
index 0000000..bb24eea
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_release.py
@@ -0,0 +1,198 @@
+#! /usr/bin/env python
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import sys
+from time import time
+from os.path import join, abspath, dirname, normpath
+from optparse import OptionParser
+import json
+from shutil import copy
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.build_api import build_mbed_libs
+from tools.build_api import write_build_report
+from tools.build_api import get_mbed_official_release
+from tools.options import extract_profile
+from tools.targets import TARGET_MAP, TARGET_NAMES
+from tools.test_exporters import ReportExporter, ResultExporterType
+from tools.test_api import SingleTestRunner
+from tools.test_api import singletest_in_cli_mode
+from tools.paths import TEST_DIR, MBED_LIBRARIES
+from tools.tests import TEST_MAP
+
+OFFICIAL_MBED_LIBRARY_BUILD = get_mbed_official_release('2')
+
+if __name__ == '__main__':
+    parser = OptionParser()
+    parser.add_option('-o', '--official', dest="official_only", default=False, action="store_true",
+                      help="Build using only the official toolchain for each target")
+    parser.add_option("-j", "--jobs", type="int", dest="jobs",
+                      default=1, help="Number of concurrent jobs (default 1). Use 0 for auto based on host machine's number of CPUs")
+    parser.add_option("-v", "--verbose", action="store_true", dest="verbose",
+                      default=False, help="Verbose diagnostic output")
+    parser.add_option("-t", "--toolchains", dest="toolchains", help="Use toolchains names separated by comma")
+
+    parser.add_option("--profile", dest="profile", action="append", default=[])
+
+    parser.add_option("-p", "--platforms", dest="platforms", default="", help="Build only for the platform namesseparated by comma")
+
+    parser.add_option("-L", "--list-config", action="store_true", dest="list_config",
+                      default=False, help="List the platforms and toolchains in the release in JSON")
+
+    parser.add_option("", "--report-build", dest="report_build_file_name", help="Output the build results to an junit xml file")
+
+    parser.add_option("", "--build-tests", dest="build_tests", help="Build all tests in the given directories (relative to /libraries/tests)")
+
+
+    options, args = parser.parse_args()
+
+
+
+    if options.list_config:
+        print json.dumps(OFFICIAL_MBED_LIBRARY_BUILD, indent=4)
+        sys.exit()
+
+    start = time()
+    build_report = {}
+    build_properties = {}
+
+    platforms = None
+    if options.platforms != "":
+        platforms = set(options.platforms.split(","))
+
+    if options.build_tests:
+        # Get all paths
+        directories = options.build_tests.split(',')
+        for i in range(len(directories)):
+            directories[i] = normpath(join(TEST_DIR, directories[i]))
+
+        test_names = []
+
+        for test_id in TEST_MAP.keys():
+            # Prevents tests with multiple source dirs from being checked
+            if isinstance( TEST_MAP[test_id].source_dir, basestring):
+                test_path = normpath(TEST_MAP[test_id].source_dir)
+                for directory in directories:
+                    if directory in test_path:
+                        test_names.append(test_id)
+
+        mut_counter = 1
+        mut = {}
+        test_spec = {
+            "targets": {}
+        }
+
+        if options.toolchains:
+            print "Only building using the following toolchains: %s" % (options.toolchains)
+
+        for target_name, toolchain_list in OFFICIAL_MBED_LIBRARY_BUILD:
+            toolchains = None
+            if platforms is not None and not target_name in platforms:
+                print("Excluding %s from release" % target_name)
+                continue
+
+            if target_name not in TARGET_NAMES:
+                print "Target '%s' is not a valid target. Excluding from release"
+                continue
+
+            if options.official_only:
+                toolchains = (getattr(TARGET_MAP[target_name], 'default_toolchain', 'ARM'),)
+            else:
+                toolchains = toolchain_list
+
+            if options.toolchains:
+                toolchainSet = set(toolchains)
+                toolchains = toolchainSet.intersection(set((options.toolchains).split(',')))
+
+            mut[str(mut_counter)] = {
+                "mcu": target_name
+            }
+
+            mut_counter += 1
+
+            test_spec["targets"][target_name] = toolchains
+
+        single_test = SingleTestRunner(_muts=mut,
+                                       _parser=parser,
+                                       _opts=options,
+                                       _opts_report_build_file_name=options.report_build_file_name,
+                                       _test_spec=test_spec,
+                                       _opts_test_by_names=",".join(test_names),
+                                       _opts_verbose=options.verbose,
+                                       _opts_only_build_tests=True,
+                                       _opts_suppress_summary=True,
+                                       _opts_jobs=options.jobs,
+                                       _opts_include_non_automated=True,
+                                       _opts_build_report=build_report,
+                                       _opts_build_properties=build_properties)
+        # Runs test suite in CLI mode
+        test_summary, shuffle_seed, test_summary_ext, test_suite_properties_ext, new_build_report, new_build_properties = single_test.execute()
+    else:
+        for target_name, toolchain_list in OFFICIAL_MBED_LIBRARY_BUILD:
+            if platforms is not None and not target_name in platforms:
+                print("Excluding %s from release" % target_name)
+                continue
+
+            if target_name not in TARGET_NAMES:
+                print "Target '%s' is not a valid target. Excluding from release"
+                continue
+
+            if options.official_only:
+                toolchains = (getattr(TARGET_MAP[target_name], 'default_toolchain', 'ARM'),)
+            else:
+                toolchains = toolchain_list
+
+            if options.toolchains:
+                print "Only building using the following toolchains: %s" % (options.toolchains)
+                toolchainSet = set(toolchains)
+                toolchains = toolchainSet.intersection(set((options.toolchains).split(',')))
+
+            for toolchain in toolchains:
+                id = "%s::%s" % (target_name, toolchain)
+
+                profile = extract_profile(parser, options, toolchain)
+
+                try:
+                    built_mbed_lib = build_mbed_libs(TARGET_MAP[target_name],
+                                                     toolchain,
+                                                     verbose=options.verbose,
+                                                     jobs=options.jobs,
+                                                     report=build_report,
+                                                     properties=build_properties,
+                                                     build_profile=profile)
+
+                except Exception, e:
+                    print str(e)
+
+    # copy targets.json file as part of the release
+    copy(join(dirname(abspath(__file__)), '..', 'targets', 'targets.json'), MBED_LIBRARIES)
+
+    # Write summary of the builds
+    if options.report_build_file_name:
+        file_report_exporter = ReportExporter(ResultExporterType.JUNIT, package="build")
+        file_report_exporter.report_to_file(build_report, options.report_build_file_name, test_suite_properties=build_properties)
+
+    print "\n\nCompleted in: (%.2f)s" % (time() - start)
+
+    print_report_exporter = ReportExporter(ResultExporterType.PRINT, package="build")
+    status = print_report_exporter.report(build_report)
+
+    if not status:
+        sys.exit(1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_travis.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_travis.py
new file mode 100755
index 0000000..0982ee1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/build_travis.py
@@ -0,0 +1,330 @@
+#!/usr/bin/env python2
+
+"""
+Travis-CI build script
+
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import os
+import sys
+
+################################################################################
+# Configure builds here
+# "libs" can contain "dsp", "usb"
+
+build_list = (
+    { "target": "LPC1768",           "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "LPC11U24",          "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "OC_MBUINO",         "toolchains": "GCC_ARM", "libs": []  },
+
+    { "target": "LPC11U24_301",      "toolchains": "GCC_ARM", "libs": [] },
+
+    { "target": "B96B_F446VE",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L053R8",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L152RE",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F030R8",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F031K6",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F042K6",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F070RB",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F072RB",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F091RC",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F103RB",     "toolchains": "GCC_ARM" },
+    { "target": "NUCLEO_F207ZG",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F302R8",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F303K8",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F303RE",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F303ZE",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F334R8",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F401RE",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F410RB",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F411RE",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F412ZG",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L432KC",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L476RG",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L011K4",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L031K6",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_L073RZ",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NUCLEO_F429ZI",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F446RE",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F446ZE",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F746ZG",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_F767ZI",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+
+    { "target": "MOTE_L152RC",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "ELMO_F411RE",       "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "MTS_MDOT_F405RG",   "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "MTS_MDOT_F411RE",   "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "MTS_DRAGONFLY_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "ARCH_MAX",          "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "DISCO_F051R8",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_F303VC",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_F334C8",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_F401VC",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "DISCO_F407VG",      "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "DISCO_F413ZH",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_F429ZI",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_F469NI",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_F746NG",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_F769NI",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DISCO_L475VG_IOT01A", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "DISCO_L476VG",        "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "DISCO_L072CZ_LRWAN1", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+
+    { "target": "LPC1114",           "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "LPC11U35_401",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "UBLOX_C027",        "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "LPC11U35_501",      "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "LPC11U68",          "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "LPC11U37H_401",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "KL05Z",             "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "KL25Z",             "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "KL27Z",             "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "KL43Z",             "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "KL46Z",             "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "K20D50M",           "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "TEENSY3_1",         "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "K64F",              "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "K22F",              "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "LPC4088",           "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "ARCH_PRO",          "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "LPC1549",           "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NRF51822",          "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "DELTA_DFCM_NNN40",  "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NRF51_DK",          "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "NRF51_MICROBIT",    "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "EFM32ZG_STK3200",   "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "EFM32HG_STK3400",   "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "EFM32LG_STK3600",   "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "EFM32GG_STK3700",   "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "EFM32WG_STK3800",   "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "EFM32PG_STK3401",   "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "MAXWSNENV",    "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "MAX32600MBED", "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "MAX32620HSP",  "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "SAMR21G18A",  "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "SAMD21J18A",  "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "SAMD21G18A",  "toolchains": "GCC_ARM", "libs": ["dsp"] },
+    { "target": "SAML21J18A",  "toolchains": "GCC_ARM", "libs": ["dsp"] },
+
+    { "target": "NUMAKER_PFM_NUC472",   "toolchains": "GCC_ARM",    "libs": ["dsp", "usb"] },
+    { "target": "NUMAKER_PFM_M453",     "toolchains": "GCC_ARM",    "libs": ["dsp", "usb"] },
+    { "target": "NUMAKER_PFM_M487",     "toolchains": "GCC_ARM",    "libs": ["dsp", "usb"] },
+ )
+
+################################################################################
+# Configure example test building (linking against external mbed SDK libraries)
+
+linking_list = [
+    {"target": "LPC1768",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_15", "MBED_16", "MBED_17"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "K64F",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "K22F",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "KL43Z",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_F446RE",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_F446ZE",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_F401RE",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"], 
+             }
+    },
+    {"target": "NUCLEO_F411RE",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_F412ZG",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+             }
+    },
+    {"target": "NUCLEO_F429ZI",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_F207ZG",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_F746ZG",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_F767ZI",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUCLEO_L476RG",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+             }
+    },
+    {"target": "DISCO_F429ZI",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+             }
+    },
+    {"target": "DISCO_F407VG",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+     {"target": "DISCO_F413ZH",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               }
+     },
+    {"target": "NUCLEO_F303ZE",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+             }
+    },
+    {"target": "DISCO_L475VG_IOT01A",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "DISCO_L476VG",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "DISCO_L072CZ_LRWAN1",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+              }
+    },
+    {"target": "NUMAKER_PFM_NUC472",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUMAKER_PFM_M453",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     },
+    {"target": "NUMAKER_PFM_M487",
+     "toolchains": "GCC_ARM",
+     "tests": {""     : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
+               "usb"  : ["USB_1", "USB_2" ,"USB_3"],
+               }
+     }
+    ]
+
+################################################################################
+
+# Driver
+
+def run_builds(dry_run):
+    for build in build_list:
+        toolchain_list = build["toolchains"]
+        if type(toolchain_list) != type([]): toolchain_list = [toolchain_list]
+        for toolchain in toolchain_list:
+            cmdline = "python tools/build.py -m %s -t %s -j 4 -c --silent "% (build["target"], toolchain)
+            libs = build.get("libs", [])
+            if libs:
+                cmdline = cmdline + " ".join(["--" + l for l in libs])
+            print "Executing: " + cmdline
+            if not dry_run:
+                if os.system(cmdline) != 0:
+                    sys.exit(1)
+
+
+def run_test_linking(dry_run):
+    """ Function run make.py commands to build and link simple mbed SDK
+        tests against few libraries to make sure there are no simple linking errors.
+    """
+    for link in linking_list:
+        toolchain_list = link["toolchains"]
+        if type(toolchain_list) != type([]):
+            toolchain_list = [toolchain_list]
+        for toolchain in toolchain_list:
+            tests = link["tests"]
+            # Call make.py for each test group for particular library
+            for test_lib in tests:
+                test_names = tests[test_lib]
+                test_lib_switch = "--" + test_lib if test_lib else ""
+                cmdline = "python tools/make.py -m %s -t %s -c --silent %s -n %s " % (link["target"], toolchain, test_lib_switch, ",".join(test_names))
+                print "Executing: " + cmdline
+                if not dry_run:
+                    if os.system(cmdline) != 0:
+                        sys.exit(1)
+
+def run_test_testsuite(dry_run):
+    cmdline = "python tools/singletest.py --version"
+    print "Executing: " + cmdline
+    if not dry_run:
+        if os.system(cmdline) != 0:
+            sys.exit(1)
+
+if __name__ == "__main__":
+    run_builds("-s" in sys.argv)
+    run_test_linking("-s" in sys.argv)
+    run_test_testsuite("-s" in sys.argv)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/check_release.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/check_release.json
new file mode 100755
index 0000000..9db3fb6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/check_release.json
@@ -0,0 +1,18 @@
+{
+  "config" : {
+    "mbed_repo_path" : "C:/Users/annbri01/Work/Mercurial"
+  },
+  "test_list" : [
+    { 
+      "name" : "test_compile_mbed_lib",
+      "lib" : "mbed"
+    },
+    {
+      "name" : "test_compile_mbed_dev",
+      "lib" : "mbed-dev"
+    }
+  ],
+  "target_list" : [],
+  "ignore_list" : []
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/check_release.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/check_release.py
new file mode 100755
index 0000000..4d940fb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/check_release.py
@@ -0,0 +1,530 @@
+# Script to check a new mbed 2 release by compiling a set of specified test apps 
+# for all currently supported platforms. Each test app must include an mbed library.
+# This can either be the pre-compiled version 'mbed' or the source version 'mbed-dev'.
+#
+# Setup:
+# 1. Set up your global .hgrc file
+# 
+#    If you don't already have a .hgrc file in your $HOME directory, create one there.
+#    Then add the following section:
+# 
+#    [auth]
+#    x.prefix = *
+#    x.username = <put your mbed org username here>
+#    x.password = <put your mbed org password here>
+#
+#    This has 2 purposes, the first means you don't get prompted for your password 
+#    whenever you run hg commands on the commandline. The second is that this script
+#    reads these details in order to fully automate the Mercurial commands.
+# 
+# Edit "check_release.json". This has the following structure:
+#{
+#  "config" : {
+#    "mbed_repo_path" : "C:/Users/annbri01/Work/Mercurial"
+#  },
+#  "test_list" : [
+#    {
+#        "name" : "test_compile_mbed_lib",
+#        "lib" : "mbed"
+#    },
+#    {
+#        "name" : "test_compile_mbed_dev",
+#        "lib" : "mbed-dev"
+#    }
+#  ],
+#  "target_list" : []
+#}
+#
+# The mbed_repo_path field should be changed to point to where your local
+# working directory is for Mercurial repositories.
+# For each test app you wish to run, add an entry to the test list. The example
+# above has 2 test apps  
+#     "test_compile_mbed_lib" and "test_compile_mbed_dev"
+# The lib field in each says which type of mbed 2 library the app contains.
+# These test apps MUST be available as repos in the user's online Mercurial area.
+# The target_list allows the user to override the set of targets/platforms used 
+# for the compilation.
+# E.g to just compile for 2 targets, K64F and K22F :
+# "target_list" : ["K64F", "K22F"]
+#
+# Run the script from the mbed-os directory as follows:
+# > python tools/check_release.py 
+#
+# It will look for local clones of the test app repos. If they don't exist
+# it will clone them. It will then read the latest versions of mbed and mbed-dev
+# (an assumption is made that both of these are already cloned in your Mercurial area).
+# The lib files within the test apps are then updated to the corresponding version in 
+# the associated lib itself. The test apps are then committed and pushed back to the users
+# fork.
+# The test apps will then be compiled for all supported targets and a % result output at 
+# the end.
+#
+# Uses the online compiler API at https://mbed.org/handbook/Compile-API
+# Based on the example from https://mbed.org/teams/mbed/code/mbed-API-helper/
+ 
+ 
+import os, getpass, sys, json, time, requests, logging
+from os.path import dirname, abspath, basename, join
+import argparse
+import subprocess
+import re
+import hglib
+import argparse
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.build_api import get_mbed_official_release
+
+OFFICIAL_MBED_LIBRARY_BUILD = get_mbed_official_release('2')
+
+def get_compilation_failure(messages):
+    """ Reads the json formatted 'messages' and checks for compilation errors.
+        If there is a genuine compilation error then there should be a new 
+        message containing a severity field = Error and an accompanying message 
+        with the compile error text. Any other combination is considered an 
+        internal compile engine failure 
+    Args:
+    messages - json formatted text returned by the online compiler API.
+    
+    Returns:
+    Either "Error" or "Internal" to indicate an actual compilation error or an 
+    internal IDE API fault.
+
+    """
+    for m in messages:
+        # Get message text if it exists
+        try:
+            message = m['message']
+            message = message + "\n"
+        except KeyError:
+            # Skip this message as it has no 'message' field
+            continue
+                 
+        # Get type of message text
+        try:
+            msg_type = m['type']
+        except KeyError:
+            # Skip this message as it has no 'type' field
+            continue
+        
+        if msg_type == 'error' or msg_type == 'tool_error':
+            rel_log.error(message)
+            return "Error"
+        else: 
+            rel_log.debug(message)
+
+    return "Internal"
+                 
+def invoke_api(payload, url, auth, polls, begin="start/"):
+    """ Sends an API command request to the online IDE. Waits for a task completed 
+        response before returning the results.
+
+    Args:
+    payload - Configuration parameters to be passed to the API
+    url - THe URL for the online compiler API
+    auth - Tuple containing authentication credentials
+    polls - Number of times to poll for results
+    begin - Default value = "start/", start command to be appended to URL
+    
+    Returns:
+    result - True/False indicating the success/failure of the compilation
+    fail_type - the failure text if the compilation failed, else None
+    """
+
+    # send task to api
+    rel_log.debug(url + begin + "| data: " + str(payload))
+    r = requests.post(url + begin, data=payload, auth=auth)
+    rel_log.debug(r.request.body)
+    
+    if r.status_code != 200:
+        rel_log.error("HTTP code %d reported.", r.status_code)
+        return False, "Internal"
+
+    response = r.json()
+    rel_log.debug(response)
+    uuid = response['result']['data']['task_id']
+    rel_log.debug("Task accepted and given ID: %s", uuid)
+    result = False
+    fail_type = None
+    
+    # It currently seems to take the onlide IDE API ~30s to process the compile
+    # request and provide a response. Set the poll time to half that in case it 
+    # does manage to compile quicker.
+    poll_delay = 15
+    rel_log.debug("Running with a poll for response delay of: %ss", poll_delay)
+
+    # poll for output
+    for check in range(polls):
+        time.sleep(poll_delay)
+        
+        try:
+            r = requests.get(url + "output/%s" % uuid, auth=auth)
+            
+        except ConnectionError:
+            return "Internal"
+
+        response = r.json()
+
+        data = response['result']['data']
+        if data['task_complete']:
+            # Task completed. Now determine the result. Should be one of :
+            # 1) Successful compilation
+            # 2) Failed compilation with an error message
+            # 3) Internal failure of the online compiler            
+            result = bool(data['compilation_success'])
+            if result:
+                rel_log.info("COMPILATION SUCCESSFUL\n")
+            else:
+                # Did this fail due to a genuine compilation error or a failue of 
+                # the api itself ?
+                rel_log.info("COMPILATION FAILURE\n")
+                fail_type = get_compilation_failure(data['new_messages'])
+            break
+    else:
+        rel_log.info("COMPILATION FAILURE\n")
+        
+    if not result and fail_type == None:
+        fail_type = "Internal"
+        
+    return result, fail_type
+
+
+def build_repo(target, program, user, pw, polls=25, 
+               url="https://developer.mbed.org/api/v2/tasks/compiler/"):
+    """ Wrapper for sending an API command request to the online IDE. Sends a 
+        build request.
+
+    Args:
+    target - Target to be built
+    program - Test program to build
+    user - mbed username
+    pw - mbed password
+    polls - Number of times to poll for results
+    url - THe URL for the online compiler API
+    
+    Returns:
+    result - True/False indicating the success/failure of the compilation
+    fail_type - the failure text if the compilation failed, else None
+    """
+    payload = {'clean':True, 'target':target, 'program':program}
+    auth = (user, pw)
+    return invoke_api(payload, url, auth, polls)
+
+def run_cmd(command, exit_on_failure=False):
+    """ Passes a command to the system and returns a True/False result once the 
+        command has been executed, indicating success/failure. Commands are passed
+        as a list of tokens. 
+        E.g. The command 'git remote -v' would be passed in as ['git', 'remote', '-v']
+
+    Args:
+    command - system command as a list of tokens
+    exit_on_failure - If True exit the program on failure (default = False)
+    
+    Returns:
+    result - True/False indicating the success/failure of the command
+    """
+    rel_log.debug('[Exec] %s', ' '.join(command))
+    return_code = subprocess.call(command, shell=True)
+    
+    if return_code:
+        rel_log.warning("The command '%s' failed with return code: %s",  
+                        (' '.join(command), return_code))
+        if exit_on_failure:
+            sys.exit(1)
+    
+    return return_code
+
+def run_cmd_with_output(command, exit_on_failure=False):
+    """ Passes a command to the system and returns a True/False result once the 
+        command has been executed, indicating success/failure. If the command was 
+        successful then the output from the command is returned to the caller.
+        Commands are passed as a list of tokens. 
+        E.g. The command 'git remote -v' would be passed in as ['git', 'remote', '-v']
+
+    Args:
+    command - system command as a list of tokens
+    exit_on_failure - If True exit the program on failure (default = False)
+    
+    Returns:
+    result - True/False indicating the success/failure of the command
+    output - The output of the command if it was successful, else empty string
+    """
+    rel_log.debug('[Exec] %s', ' '.join(command))
+    returncode = 0
+    output = ""
+    try:
+        output = subprocess.check_output(command, shell=True)
+    except subprocess.CalledProcessError as e:
+        rel_log.warning("The command '%s' failed with return code: %s", 
+                        (' '.join(command), e.returncode))
+        returncode = e.returncode
+        if exit_on_failure:
+            sys.exit(1)
+    return returncode, output
+
+def upgrade_test_repo(test, user, library, ref, repo_path):
+    """ Upgrades a local version of a test repo to the latest version of its 
+        embedded library.
+        If the test repo is not present in the user area specified in the json 
+        config file, then it will first be cloned. 
+    Args:
+    test - Mercurial test repo name
+    user - Mercurial user name
+    library - library name
+    ref - SHA corresponding to the latest version of the library
+    repo_path - path to the user's repo area
+    
+    Returns:
+    updated - True if library was updated, False otherwise
+    """
+    rel_log.info("Updating test repo: '%s' to SHA: %s", test, ref)
+    cwd = os.getcwd()
+
+    repo = "https://" + user + '@developer.mbed.org/users/' + user + '/code/' + test 
+
+    # Clone the repo if it doesn't already exist
+    path = abspath(repo_path + '/' + test)
+    if not os.path.exists(path):
+        rel_log.info("Test repo doesn't exist, cloning...")
+        os.chdir(abspath(repo_path))        
+        clone_cmd = ['hg', 'clone', repo]
+        run_cmd(clone_cmd, exit_on_failure=True)
+    
+    os.chdir(path)
+
+    client = hglib.open(path)        
+
+    lib_file = library + '.lib'    
+    if os.path.isfile(lib_file):
+        # Rename command will fail on some OS's if the target file already exist,
+        # so ensure if it does, it is deleted first.
+        bak_file = library + '_bak' 
+        if os.path.isfile(bak_file):
+            os.remove(bak_file)
+        
+        os.rename(lib_file, bak_file)
+    else:
+        rel_log.error("Failure to backup lib file prior to updating.")
+        return False
+    
+    # mbed 2 style lib file contains one line with the following format
+    # e.g. https://developer.mbed.org/users/<user>/code/mbed-dev/#156823d33999
+    exp = 'https://developer.mbed.org/users/' + user + '/code/' + library + '/#[A-Za-z0-9]+'
+    lib_re = re.compile(exp)
+    updated = False
+
+    # Scan through mbed-os.lib line by line, looking for lib version and update 
+    # it if found
+    with open(bak_file, 'r') as ip, open(lib_file, 'w') as op:
+        for line in ip:
+
+            opline = line
+            
+            regexp = lib_re.match(line)
+            if regexp:
+                opline = 'https://developer.mbed.org/users/' + user + '/code/' + library + '/#' + ref
+                updated = True
+    
+            op.write(opline)
+
+    if updated:
+
+        # Setup the default commit message
+        commit_message = '"Updating ' + library + ' to ' + ref + '"' 
+ 
+        # Setup and run the commit command. Need to use the rawcommand in the hglib
+        # for this in order to pass the string value to the -m option. run_cmd using 
+        # subprocess does not like this syntax.
+        try:
+            client.rawcommand(['commit','-m '+commit_message, lib_file])
+
+            cmd = ['hg', 'push', '-f', repo]
+            run_cmd(cmd, exit_on_failure=True)
+            
+        except:
+            rel_log.info("Lib file already up to date and thus nothing to commit")
+                            
+    os.chdir(cwd)
+    return updated
+
+def get_sha(repo_path, library):
+    """ Gets the latest SHA for the library specified. The library is assumed to be
+        located at the repo_path. If a SHA cannot be obtained this script will exit.
+
+    Args:
+    library - library name
+    repo_path - path to the user's repo area
+    
+    Returns:
+    sha - last commit SHA
+    """
+    cwd = os.getcwd()
+    sha = None
+    os.chdir(abspath(repo_path + '/' + library))
+    
+    cmd = ['hg', 'log', '-l', '1']
+    ret, output = run_cmd_with_output(cmd, exit_on_failure=True)
+    
+    # Output should contain a 4 line string of the form:
+    # changeset:   135:176b8275d35d
+    # tag:         tip
+    # user:        <>
+    # date:        Thu Feb 02 16:02:30 2017 +0000
+    # summary:     Release 135 of the mbed library
+    # All we want is the changeset string after version number
+    
+    lines = output.split('\n')
+    fields = lines[0].split(':')
+    sha = fields[2]
+    
+    os.chdir(cwd)
+    return sha
+
+def get_latest_library_versions(repo_path):
+    """ Returns the latest library versions (SHAs) for 'mbed' and 'mbed-dev'. 
+    If the SHAs cannot be obtained this script will exit.
+
+    Args:
+    repo_path - path to the user's repo area
+    
+    Returns:
+    mbed - last commit SHA for mbed library
+    mbed_dev - last commit SHA for mbed_dev library
+    
+    """
+
+    mbed = get_sha(repo_path, 'mbed')
+    mbed_dev = get_sha(repo_path, 'mbed-dev')
+
+    return mbed, mbed_dev
+
+def log_results(lst, title):
+    if len(lst) == 0:
+        rel_log.info("%s - None", title)
+    else:        
+        for entry in lst:
+            rel_log.info("%s - Test: %s, Target: %s", title, entry[0], entry[1])                
+
+
+if __name__ == '__main__':
+
+    parser = argparse.ArgumentParser(description=__doc__,
+                                     formatter_class=argparse.RawDescriptionHelpFormatter)
+    parser.add_argument('-l', '--log-level', 
+                        help="Level for providing logging output", 
+                        default='INFO')
+    args = parser.parse_args()
+
+    default = getattr(logging, 'INFO')
+    level = getattr(logging, args.log_level.upper(), default)
+        
+    # Set logging level
+    logging.basicConfig(level=level)
+    rel_log = logging.getLogger("check-release")
+    
+    # Read configuration data
+    with open(os.path.join(os.path.dirname(__file__), "check_release.json")) as config:
+        json_data = json.load(config)
+     
+    supported_targets = []
+
+    if len(json_data["target_list"]) > 0:
+        # Compile user supplied subset of targets
+        supported_targets = json_data["target_list"]
+    else:        
+        # Get a list of the officially supported mbed-os 2 targets
+        for tgt in OFFICIAL_MBED_LIBRARY_BUILD:
+            supported_targets.append(tgt[0])
+
+    ignore_list = []
+
+    if len(json_data["ignore_list"]) > 0:
+        # List of tuples of (test, target) to be ignored in this test
+        ignore_list = json_data["ignore_list"]
+
+    config = json_data["config"]
+    test_list = json_data["test_list"]
+    repo_path = config["mbed_repo_path"]
+    tests = []
+
+    # get username
+    cmd = ['hg', 'config', 'auth.x.username']
+    ret, output = run_cmd_with_output(cmd, exit_on_failure=True)
+    output = output.split('\n')
+    user = output[0]
+    
+    # get password
+    cmd = ['hg', 'config', 'auth.x.password']
+    ret, output = run_cmd_with_output(cmd, exit_on_failure=True)
+    output = output.split('\n')
+    password = output[0]
+    
+    mbed, mbed_dev = get_latest_library_versions(repo_path)
+
+    if not mbed or not mbed_dev:
+        rel_log.error("Could not obtain latest versions of library files!!")
+        exit(1)
+        
+    rel_log.info("Latest mbed lib version = %s", mbed)
+    rel_log.info("Latest mbed-dev lib version = %s", mbed_dev)    
+  
+    # First update test repos to latest versions of their embedded libraries
+    for test in test_list:
+        tests.append(test['name'])
+        upgrade_test_repo(test['name'], user, test['lib'], 
+                          mbed if test['lib'] == "mbed" else mbed_dev, 
+                          repo_path)
+
+    total = len(supported_targets) * len(tests)
+    current = 0
+    retries = 10
+    passes = 0
+    failures = []
+    skipped = []
+    
+    # Compile each test for each supported target
+    for test in tests:
+        for target in supported_targets:
+            
+            combo = [test, target]
+            
+            if combo in ignore_list:
+                rel_log.info("SKIPPING TEST: %s, TARGET: %s", test, target)
+                total -= 1   
+                skipped.append(combo)
+                continue
+                
+            current += 1
+            for retry in range(0, retries):
+                rel_log.info("COMPILING (%d/%d): TEST %s, TARGET: %s , attempt %u\n", current, total, test, target,  retry)
+                result, mesg = build_repo(target, test, user, password)
+                if not result:
+                    if mesg == 'Internal':
+                        # Internal compiler error thus retry
+                        continue
+                    else:
+                        # Actual error thus move on to next compilation
+                        failures.append(combo)
+                        break
+                                    
+                passes += (int)(result)
+                break
+            else:
+                rel_log.error("Compilation failed due to internal errors.")
+                rel_log.error("Skipping test/target combination.")
+                total -= 1   
+                skipped.append(combo)
+                
+    rel_log.info(" SUMMARY OF COMPILATION RESULTS")                
+    rel_log.info(" ------------------------------")                
+    rel_log.info(" NUMBER OF TEST APPS: %d, NUMBER OF TARGETS: %d", 
+                 len(tests), len(supported_targets))   
+    log_results(failures, " FAILED")
+    log_results(skipped, " SKIPPED")
+
+    # Output a % pass rate, indicate a failure if not 100% successful
+    pass_rate = (float(passes) / float(total)) * 100.0
+    rel_log.info(" PASS RATE %.1f %%\n", pass_rate)
+    sys.exit(not (pass_rate == 100))
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/colorize.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/colorize.py
new file mode 100755
index 0000000..6207012
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/colorize.py
@@ -0,0 +1,80 @@
+# mbed SDK
+# Copyright (c) 2016 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+""" This python file is responsible for generating colorized notifiers.
+"""
+
+import sys
+import re
+from colorama import init, Fore, Back, Style
+init()
+
+COLORS = {
+    'none' : "",
+    'default' : Style.RESET_ALL,
+
+    'black'   : Fore.BLACK,
+    'red'     : Fore.RED,
+    'green'   : Fore.GREEN,
+    'yellow'  : Fore.YELLOW,
+    'blue'    : Fore.BLUE,
+    'magenta' : Fore.MAGENTA,
+    'cyan'    : Fore.CYAN,
+    'white'   : Fore.WHITE,
+
+    'on_black'   : Back.BLACK,
+    'on_red'     : Back.RED,
+    'on_green'   : Back.GREEN,
+    'on_yellow'  : Back.YELLOW,
+    'on_blue'    : Back.BLUE,
+    'on_magenta' : Back.MAGENTA,
+    'on_cyan'    : Back.CYAN,
+    'on_white'   : Back.WHITE,
+}
+
+COLOR_MATCHER = re.compile(r"(\w+)(\W+on\W+\w+)?")
+def colorstring_to_escapecode(color_string):
+    """ Convert a color string from a string into an ascii escape code that
+    will print that color on the terminal.
+
+    Positional arguments:
+    color_string - the string to parse
+    """
+    match = re.match(COLOR_MATCHER, color_string)
+    if match:
+        return COLORS[match.group(1)] + \
+            (COLORS[match.group(2).strip().replace(" ", "_")]
+             if match.group(2) else "")
+    else:
+        return COLORS['default']
+
+
+def print_in_color_notifier(color_map, print_fn):
+    """ Wrap a toolchain notifier in a colorizer. This colorizer will wrap
+    notifications in a color if the severity matches a color in the *color_map*.
+    """
+    def wrap(event, silent=False):
+        """The notification function inself"""
+        file_desc = sys.stdout
+        self = event['toolchain']
+        if file_desc.isatty() and 'severity' in event and \
+           event['severity'] in color_map:
+            file_desc.write(colorstring_to_escapecode(
+                color_map[event['severity']]))
+            print_fn(self, event, silent)
+            file_desc.write(colorstring_to_escapecode('default'))
+        else:
+            print_fn(self, event, silent)
+    return wrap
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/__init__.py
new file mode 100755
index 0000000..3840c9e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/__init__.py
@@ -0,0 +1,16 @@
+"""
+mbed SDK
+Copyright (c) 2011-2015 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_base.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_base.py
new file mode 100755
index 0000000..53a4ed2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_base.py
@@ -0,0 +1,69 @@
+"""
+mbed SDK
+Copyright (c) 2011-2015 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+
+"""
+
+import sys
+
+try:
+    from colorama import Fore
+except:
+    pass
+
+COLORAMA = 'colorama' in sys.modules
+
+
+class IOperTestCaseBase():
+    """ Interoperability test case base class
+        @return list of tuple (severity, Description)
+                Example:      (result.append((IOperTestSeverity.INFO, ""))
+    """
+
+    def __init__(self, scope=None):
+        self.PASS = 'PASS'
+        self.INFO = 'INFO'
+        self.ERROR = 'ERROR'
+        self.WARN = 'WARN'
+
+        self.scope = scope   # Default test scope (basic, pedantic, mbed-enabled etc...)
+
+    def test(self, param=None):
+        result = []
+        return result
+
+    def RED(self, text):
+        return self.color_text(text, color=Fore.RED, delim=Fore.RESET) if COLORAMA else text
+
+    def GREEN(self, text):
+        return self.color_text(text, color=Fore.GREEN, delim=Fore.RESET) if COLORAMA else text
+
+    def YELLOW(self, text):
+        return self.color_text(text, color=Fore.YELLOW, delim=Fore.RESET) if COLORAMA else text
+
+    def color_text(self, text, color='', delim=''):
+        return color + text + color + delim
+
+    def COLOR(self, severity, text):
+        colors = {
+            self.PASS : self.GREEN,
+            self.ERROR : self.RED,
+            self.WARN : self.YELLOW
+        }
+        if severity in colors:
+            return colors[severity](text)
+        return text
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_runner.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_runner.py
new file mode 100755
index 0000000..6b5bf57
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_runner.py
@@ -0,0 +1,125 @@
+#!/usr/bin/env python2
+"""
+mbed SDK
+Copyright (c) 2011-2015 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+
+"""
+
+import sys
+import mbed_lstools
+from prettytable import PrettyTable
+
+try:
+    from colorama import init
+except:
+    pass
+
+COLORAMA = 'colorama' in sys.modules
+
+from ioper_base import IOperTestCaseBase
+from ioper_test_fs import IOperTest_FileStructure_Basic
+from ioper_test_fs import IOperTest_FileStructure_MbedEnabled
+from ioper_test_target_id import IOperTest_TargetID_Basic
+from ioper_test_target_id import IOperTest_TargetID_MbedEnabled
+
+
+TEST_LIST = [IOperTest_TargetID_Basic('basic'),
+             IOperTest_TargetID_MbedEnabled('mbed-enabled'),
+             IOperTest_FileStructure_Basic('basic'),
+             IOperTest_FileStructure_MbedEnabled('mbed-enabled'),
+             IOperTestCaseBase('all'),  # Dummy used to add 'all' option
+            ]
+
+
+class IOperTestRunner():
+    """ Calls all i/face interoperability tests
+    """
+
+    def __init__(self, scope=None):
+        """ Test scope:
+            'pedantic' - all
+            'mbed-enabled' - let's try to check if this device is mbed-enabled
+            'basic' - just simple, passive tests (no device flashing)
+        """
+        self.requested_scope = scope    # Test scope given by user
+        self.raw_test_results = {}      # Raw test results, can be used by exporters: { Platform: [test results]} 
+
+        # Test scope definitions
+        self.SCOPE_BASIC = 'basic'                  # Basic tests, sanity checks
+        self.SCOPE_MBED_ENABLED = 'mbed-enabled'    # Let's try to check if this device is mbed-enabled
+        self.SCOPE_PEDANTIC = 'pedantic'            # Extensive tests
+        self.SCOPE_ALL = 'all'                      # All tests, equal to highest scope level
+
+        # This structure will help us sort test scopes so we can include them
+        # e.g. pedantic also includes basic and mbed-enabled tests
+        self.scopes = {self.SCOPE_BASIC : 0,
+                       self.SCOPE_MBED_ENABLED : 1,
+                       self.SCOPE_PEDANTIC : 2,
+                       self.SCOPE_ALL : 99,
+                    }
+
+        if COLORAMA:
+            init()  # colorama.init()
+
+    def run(self):
+        """ Run tests, calculate overall score and print test results
+        """
+        mbeds = mbed_lstools.create()
+        muts_list = mbeds.list_mbeds()
+        test_base = IOperTestCaseBase()
+
+        self.raw_test_results = {}
+        for i, mut in enumerate(muts_list):
+            result = []
+            self.raw_test_results[mut['platform_name']] = []
+
+            print "MBEDLS: Detected %s, port: %s, mounted: %s"% (mut['platform_name'],
+                                                                 mut['serial_port'],
+                                                                 mut['mount_point'])
+            print "Running interoperability test suite, scope '%s'" % (self.requested_scope)
+            for test_case in TEST_LIST:
+                if self.scopes[self.requested_scope] >= self.scopes[test_case.scope]:
+                    res = test_case.test(param=mut)
+                    result.extend(res)
+                    self.raw_test_results[mut['platform_name']].extend(res)
+
+            columns = ['Platform', 'Test Case', 'Result', 'Scope', 'Description']
+            pt = PrettyTable(columns)
+            for col in columns:
+                pt.align[col] = 'l'
+
+            for tr in result:
+                severity, tr_name, tr_scope, text = tr
+                tr = (test_base.COLOR(severity, mut['platform_name']),
+                      test_base.COLOR(severity, tr_name),
+                      test_base.COLOR(severity, severity),
+                      test_base.COLOR(severity, tr_scope),
+                      test_base.COLOR(severity, text))
+                pt.add_row(list(tr))
+            print pt.get_string(border=True, sortby='Result')
+            if i + 1 < len(muts_list):
+                print
+        return self.raw_test_results
+
+def get_available_oper_test_scopes():
+    """ Get list of available test scopes
+    """
+    scopes = set()
+    for oper_test in TEST_LIST:
+        if oper_test.scope is not None:
+            scopes.add(oper_test.scope)
+    return list(scopes)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_test_fs.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_test_fs.py
new file mode 100755
index 0000000..945855d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_test_fs.py
@@ -0,0 +1,69 @@
+"""
+mbed SDK
+Copyright (c) 2011-2015 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+
+"""
+
+import os.path
+from ioper_base import IOperTestCaseBase
+
+
+class IOperTest_FileStructure(IOperTestCaseBase):
+
+    def __init__(self, scope=None):
+        IOperTestCaseBase.__init__(self, scope)
+
+    def if_file_exist(self, fname, fail_severity=None):
+        file_path = os.path.join(self.param['mount_point'], fname)
+        exist = os.path.isfile(file_path)
+        tr_name = "FILE_EXIST(%s)" % fname.upper()
+        if exist:
+            self.result.append((self.PASS, tr_name, self.scope, "File '%s' exists" % file_path))
+        else:
+            self.result.append((fail_severity if fail_severity else self.ERROR, tr_name, self.scope, "File '%s' not found" % file_path))
+
+    def test(self, param=None):
+        self.result = []
+        if param:
+            pass
+        return self.result
+
+
+class IOperTest_FileStructure_Basic(IOperTest_FileStructure):
+    def __init__(self, scope=None):
+        IOperTest_FileStructure.__init__(self, scope)
+
+    def test(self, param=None):
+        self.param = param
+        self.result = []
+        if param:
+            self.if_file_exist('mbed.htm', self.ERROR)
+        return self.result
+
+
+class IOperTest_FileStructure_MbedEnabled(IOperTest_FileStructure):
+    def __init__(self, scope=None):
+        IOperTest_FileStructure.__init__(self, scope)
+
+    def test(self, param=None):
+        self.param = param
+        self.result = []
+        if param:
+            self.if_file_exist('mbed.htm', self.ERROR)
+            self.if_file_exist('DETAILS.TXT', self.ERROR)
+            self.if_file_exist('FAIL.TXT', self.INFO)
+        return self.result
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_test_target_id.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_test_target_id.py
new file mode 100755
index 0000000..55fa0d1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/compliance/ioper_test_target_id.py
@@ -0,0 +1,111 @@
+"""
+mbed SDK
+Copyright (c) 2011-2015 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+
+"""
+
+from ioper_base import IOperTestCaseBase
+
+
+class IOperTest_TargetID(IOperTestCaseBase):
+    """ tests related to target_id value
+    """
+
+    def __init__(self, scope=None):
+        IOperTestCaseBase.__init__(self, scope)
+        self.TARGET_ID_LEN = 24
+
+    def test_target_id_format(self, target_id, target_id_name):
+        # Expected length == 24, eg. "02400203D94B0E7724B7F3CF"
+        result = []
+        target_id_len = len(target_id) if target_id else 0
+        if target_id_len == self.TARGET_ID_LEN:
+            result.append((self.PASS, "TARGET_ID_LEN", self.scope, "%s '%s' is %d chars long " % (target_id_name, target_id, target_id_len)))
+            result.append((self.INFO, "FW_VER_STR", self.scope, "%s Version String is %s.%s.%s " % (target_id_name,
+                                                                                      target_id[0:4],
+                                                                                      target_id[4:8],
+                                                                                      target_id[8:24],
+                                                                                      )))
+        else:
+            result.append((self.ERROR, "TARGET_ID_LEN", self.scope, "%s '%s' is %d chars long. Expected %d chars" % (target_id_name, target_id, target_id_len, self.TARGET_ID_LEN)))
+        return result
+
+    def test_decode_target_id(self, target_id, target_id_name):
+        result = []
+        target_id_len = len(target_id) if target_id else 0
+        if target_id_len >= 4:
+            result.append((self.INFO, "FW_VEN_CODE", self.scope, "%s Vendor Code is '%s'" % (target_id_name, target_id[0:2])))
+            result.append((self.INFO, "FW_PLAT_CODE", self.scope, "%s Platform Code is '%s'" % (target_id_name, target_id[2:4])))
+            result.append((self.INFO, "FW_VER", self.scope, "%s Firmware Version is '%s'" % (target_id_name, target_id[4:8])))
+            result.append((self.INFO, "FW_HASH_SEC", self.scope, "%s Hash of secret is '%s'" % (target_id_name, target_id[8:24])))
+        return result
+
+    def test(self, param=None):
+        result = []
+        if param:
+            pass
+        return result
+
+
+class IOperTest_TargetID_Basic(IOperTest_TargetID):
+    """ Basic interoperability tests checking TargetID compliance
+    """
+
+    def __init__(self, scope=None):
+        IOperTest_TargetID.__init__(self, scope)
+
+    def test(self, param=None):
+        result = []
+
+        if param:
+            result.append((self.PASS, "TARGET_ID", self.scope, "TargetID '%s' found" % param['target_id']))
+
+            # Check if target name can be decoded with mbed-ls
+            if param['platform_name']:
+                result.append((self.PASS, "TARGET_ID_DECODE", self.scope, "TargetID '%s' decoded as '%s'" % (param['target_id'][0:4], param['platform_name'])))
+            else:
+                result.append((self.ERROR, "TARGET_ID_DECODE", self.scope, "TargetID '%s'... not decoded" % (param['target_id'] if param['target_id'] else '')))
+
+            # Test for USBID and mbed.htm consistency
+            if param['target_id_mbed_htm'] == param['target_id_usb_id']:
+                result.append((self.PASS, "TARGET_ID_MATCH", self.scope, "TargetID (USBID) and TargetID (mbed.htm) match"))
+            else:
+                text = "TargetID (USBID) and TargetID (mbed.htm) don't match: '%s' != '%s'" % (param['target_id_usb_id'], param['target_id_mbed_htm'])
+                result.append((self.WARN, "TARGET_ID_MATCH", self.scope, text))
+        else:
+            result.append((self.ERROR, "TARGET_ID", self.scope, "TargetID not found"))
+        return result
+
+class IOperTest_TargetID_MbedEnabled(IOperTest_TargetID):
+    """ Basic interoperability tests checking TargetID compliance
+    """
+
+    def __init__(self, scope=None):
+        IOperTest_TargetID.__init__(self, scope)
+
+    def test(self, param=None):
+        result = []
+
+        if param:
+            # Target ID tests:
+            result += self.test_target_id_format(param['target_id_usb_id'], "TargetId (USBID)")
+            result += self.test_target_id_format(param['target_id_mbed_htm'], "TargetId (mbed.htm)")
+
+            # Some extra info about TargetID itself
+            result += self.test_decode_target_id(param['target_id_usb_id'], "TargetId (USBID)")
+            result += self.test_decode_target_id(param['target_id_mbed_htm'], "TargetId (mbed.htm)")
+        return result
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/__init__.py
new file mode 100755
index 0000000..e6d888f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/__init__.py
@@ -0,0 +1,952 @@
+"""
+mbed SDK
+Copyright (c) 2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from copy import deepcopy
+import os
+from os.path import dirname, abspath, exists, join
+import sys
+from collections import namedtuple
+from os.path import splitext, relpath
+from intelhex import IntelHex
+from jinja2 import FileSystemLoader, StrictUndefined
+from jinja2.environment import Environment
+# Implementation of mbed configuration mechanism
+from tools.utils import json_file_to_dict, intelhex_offset
+from tools.arm_pack_manager import Cache
+from tools.targets import CUMULATIVE_ATTRIBUTES, TARGET_MAP, \
+    generate_py_target, get_resolution_order
+
+# Base class for all configuration exceptions
+class ConfigException(Exception):
+    """Config system only exception. Makes it easier to distinguish config
+    errors"""
+    pass
+
+class ConfigParameter(object):
+    """This class keeps information about a single configuration parameter"""
+
+    def __init__(self, name, data, unit_name, unit_kind):
+        """Construct a ConfigParameter
+
+        Positional arguments:
+        name - the name of the configuration parameter
+        data - the data associated with the configuration parameter
+        unit_name - the unit (target/library/application) that defines this
+                    parameter
+        unit_ kind - the kind of the unit ("target", "library" or "application")
+        """
+        self.name = self.get_full_name(name, unit_name, unit_kind,
+                                       allow_prefix=False)
+        self.defined_by = self.get_display_name(unit_name, unit_kind)
+        self.set_value(data.get("value", None), unit_name, unit_kind)
+        self.help_text = data.get("help", None)
+        self.required = data.get("required", False)
+        self.macro_name = data.get("macro_name", "MBED_CONF_%s" %
+                                   self.sanitize(self.name.upper()))
+        self.config_errors = []
+
+    @staticmethod
+    def get_full_name(name, unit_name, unit_kind, label=None,
+                      allow_prefix=True):
+        """Return the full (prefixed) name of a parameter. If the parameter
+        already has a prefix, check if it is valid
+
+        Positional arguments:
+        name - the simple (unqualified) name of the parameter
+        unit_name - the unit (target/library/application) that defines this
+                    parameter
+        unit_kind - the kind of the unit ("target", "library" or "application")
+
+        Keyword arguments:
+        label - the name of the label in the 'target_config_overrides' section
+        allow_prefix - True to allow the original name to have a prefix, False
+                       otherwise
+        """
+        if name.find('.') == -1: # the name is not prefixed
+            if unit_kind == "target":
+                prefix = "target."
+            elif unit_kind == "application":
+                prefix = "app."
+            else:
+                prefix = unit_name + '.'
+            return prefix + name
+        # The name has a prefix, so check if it is valid
+        if not allow_prefix:
+            raise ConfigException("Invalid parameter name '%s' in '%s'" %
+                                  (name, ConfigParameter.get_display_name(
+                                      unit_name, unit_kind, label)))
+        temp = name.split(".")
+        # Check if the parameter syntax is correct (must be
+        # unit_name.parameter_name)
+        if len(temp) != 2:
+            raise ConfigException("Invalid parameter name '%s' in '%s'" %
+                                  (name, ConfigParameter.get_display_name(
+                                      unit_name, unit_kind, label)))
+        prefix = temp[0]
+        # Check if the given parameter prefix matches the expected prefix
+        if (unit_kind == "library" and prefix != unit_name) or \
+           (unit_kind == "target" and prefix != "target"):
+            raise ConfigException(
+                "Invalid prefix '%s' for parameter name '%s' in '%s'" %
+                (prefix, name, ConfigParameter.get_display_name(
+                    unit_name, unit_kind, label)))
+        return name
+
+    @staticmethod
+    def get_display_name(unit_name, unit_kind, label=None):
+        """Return the name displayed for a unit when interrogating the origin
+        and the last set place of a parameter
+
+        Positional arguments:
+        unit_name - the unit (target/library/application) that defines this
+                    parameter
+        unit_kind - the kind of the unit ("target", "library" or "application")
+
+        Keyword arguments:
+        label - the name of the label in the 'target_config_overrides' section
+        """
+        if unit_kind == "target":
+            return "target:" + unit_name
+        elif unit_kind == "application":
+            return "application%s" % ("[%s]" % label if label else "")
+        else: # library
+            return "library:%s%s" % (unit_name, "[%s]" % label if label else "")
+
+    @staticmethod
+    def sanitize(name):
+        """ "Sanitize" a name so that it is a valid C macro name. Currently it
+        simply replaces '.' and '-' with '_'.
+
+        Positional arguments:
+        name - the name to make into a valid C macro
+        """
+        return name.replace('.', '_').replace('-', '_')
+
+    def set_value(self, value, unit_name, unit_kind, label=None):
+        """ Sets a value for this parameter, remember the place where it was
+        set.  If the value is a Boolean, it is converted to 1 (for True) or
+        to 0 (for False).
+
+        Positional arguments:
+        value - the value of the parameter
+        unit_name - the unit (target/library/application) that defines this
+                   parameter
+        unit_kind - the kind of the unit ("target", "library" or "application")
+
+        Keyword arguments:
+        label - the name of the label in the 'target_config_overrides' section
+               (optional)
+        """
+        self.value = int(value) if isinstance(value, bool) else value
+        self.set_by = self.get_display_name(unit_name, unit_kind, label)
+
+    def __str__(self):
+        """Return the string representation of this configuration parameter
+
+        Arguments: None
+        """
+        if self.value is not None:
+            return '%s = %s (macro name: "%s")' % \
+                (self.name, self.value, self.macro_name)
+        else:
+            return '%s has no value' % self.name
+
+    def get_verbose_description(self):
+        """Return a verbose description of this configuration parameter as a
+        string
+
+        Arguments: None
+        """
+        desc = "Name: %s%s\n" % \
+               (self.name, " (required parameter)" if self.required else "")
+        if self.help_text:
+            desc += "    Description: %s\n" % self.help_text
+        desc += "    Defined by: %s\n" % self.defined_by
+        if not self.value:
+            return desc + "    No value set"
+        desc += "    Macro name: %s\n" % self.macro_name
+        desc += "    Value: %s (set by %s)" % (self.value, self.set_by)
+        return desc
+
+class ConfigMacro(object):
+    """ A representation of a configuration macro. It handles both macros
+    without a value (MACRO) and with a value (MACRO=VALUE)
+    """
+    def __init__(self, name, unit_name, unit_kind):
+        """Construct a ConfigMacro object
+
+        Positional arguments:
+        name - the macro's name
+        unit_name - the location where the macro was defined
+        unit_kind - the type of macro this is
+        """
+        self.name = name
+        self.defined_by = ConfigParameter.get_display_name(unit_name, unit_kind)
+        if name.find("=") != -1:
+            tmp = name.split("=")
+            if len(tmp) != 2:
+                raise ValueError("Invalid macro definition '%s' in '%s'" %
+                                 (name, self.defined_by))
+            self.macro_name = tmp[0]
+            self.macro_value = tmp[1]
+        else:
+            self.macro_name = name
+            self.macro_value = None
+
+class ConfigCumulativeOverride(object):
+    """Representation of overrides for cumulative attributes"""
+    def __init__(self, name, additions=None, removals=None, strict=False):
+        """Construct a ConfigCumulativeOverride object
+
+        Positional arguments:
+        name - the name of the config file this came from ?
+
+        Keyword arguments:
+        additions - macros to add to the overrides
+        removals - macros to remove from the overrides
+        strict - Boolean indicating that attempting to remove from an override
+                 that does not exist should error
+        """
+        self.name = name
+        if additions:
+            self.additions = set(additions)
+        else:
+            self.additions = set()
+        if removals:
+            self.removals = set(removals)
+        else:
+            self.removals = set()
+        self.strict = strict
+
+    def remove_cumulative_overrides(self, overrides):
+        """Extend the list of override removals.
+
+        Positional arguments:
+        overrides - a list of names that, when the override is evaluated, will
+                    be removed
+        """
+        for override in overrides:
+            if override in self.additions:
+                raise ConfigException(
+                    "Configuration conflict. The %s %s both added and removed."
+                    % (self.name[:-1], override))
+
+        self.removals |= set(overrides)
+
+    def add_cumulative_overrides(self, overrides):
+        """Extend the list of override additions.
+
+        Positional arguments:
+        overrides - a list of a names that, when the override is evaluated, will
+                    be added to the list
+        """
+        for override in overrides:
+            if override in self.removals or \
+               (self.strict and override not in self.additions):
+                raise ConfigException(
+                    "Configuration conflict. The %s %s both added and removed."
+                    % (self.name[:-1], override))
+
+        self.additions |= set(overrides)
+
+    def strict_cumulative_overrides(self, overrides):
+        """Remove all overrides that are not the specified ones
+
+        Positional arguments:
+        overrides - a list of names that will replace the entire attribute when
+                    this override is evaluated.
+        """
+        self.remove_cumulative_overrides(self.additions - set(overrides))
+        self.add_cumulative_overrides(overrides)
+        self.strict = True
+
+    def update_target(self, target):
+        """Update the attributes of a target based on this override"""
+        setattr(target, self.name,
+                list((set(getattr(target, self.name, []))
+                      | self.additions) - self.removals))
+
+
+def _process_config_parameters(data, params, unit_name, unit_kind):
+    """Process a "config_parameters" section in either a target, a library,
+    or the application.
+
+    Positional arguments:
+    data - a dictionary with the configuration parameters
+    params - storage for the discovered configuration parameters
+    unit_name - the unit (target/library/application) that defines this
+                parameter
+    unit_kind - the kind of the unit ("target", "library" or "application")
+    """
+    for name, val in data.items():
+        full_name = ConfigParameter.get_full_name(name, unit_name, unit_kind)
+        # If the parameter was already defined, raise an error
+        if full_name in params:
+            raise ConfigException(
+                "Parameter name '%s' defined in both '%s' and '%s'" %
+                (name, ConfigParameter.get_display_name(unit_name, unit_kind),
+                 params[full_name].defined_by))
+        # Otherwise add it to the list of known parameters
+        # If "val" is not a dictionary, this is a shortcut definition,
+        # otherwise it is a full definition
+        params[full_name] = ConfigParameter(name, val if isinstance(val, dict)
+                                            else {"value": val}, unit_name,
+                                            unit_kind)
+    return params
+
+
+def _process_macros(mlist, macros, unit_name, unit_kind):
+    """Process a macro definition and check for incompatible duplicate
+    definitions.
+
+    Positional arguments:
+    mlist - list of macro names to process
+    macros - dictionary with currently discovered macros
+    unit_name - the unit (library/application) that defines this macro
+    unit_kind - the kind of the unit ("library" or "application")
+    """
+    for mname in mlist:
+        macro = ConfigMacro(mname, unit_name, unit_kind)
+        if (macro.macro_name in macros) and \
+           (macros[macro.macro_name].name != mname):
+            # Found an incompatible definition of the macro in another module,
+            # so raise an error
+            full_unit_name = ConfigParameter.get_display_name(unit_name,
+                                                              unit_kind)
+            raise ConfigException(
+                ("Macro '%s' defined in both '%s' and '%s'"
+                 % (macro.macro_name, macros[macro.macro_name].defined_by,
+                    full_unit_name)) +
+                " with incompatible values")
+        macros[macro.macro_name] = macro
+
+
+def check_dict_types(dict, type_dict, dict_loc):
+    for key, value in dict.iteritems():
+        if not isinstance(value, type_dict[key]):
+            raise ConfigException("The value of %s.%s is not of type %s" %
+                                  (dict_loc, key, type_dict[key].__name__))
+
+Region = namedtuple("Region", "name start size active filename")
+
+class Config(object):
+    """'Config' implements the mbed configuration mechanism"""
+
+    # Libraries and applications have different names for their configuration
+    # files
+    __mbed_app_config_name = "mbed_app.json"
+    __mbed_lib_config_name = "mbed_lib.json"
+
+    # Allowed keys in configuration dictionaries, and their types
+    # (targets can have any kind of keys, so this validation is not applicable
+    # to them)
+    __allowed_keys = {
+        "library": {"name": str, "config": dict, "target_overrides": dict,
+                    "macros": list, "__config_path": str},
+        "application": {"config": dict, "target_overrides": dict,
+                        "macros": list, "__config_path": str,
+                        "artifact_name": str}
+    }
+
+    __unused_overrides = set(["target.bootloader_img", "target.restrict_size",
+                              "target.mbed_app_start", "target.mbed_app_size"])
+
+    # Allowed features in configurations
+    __allowed_features = [
+        "UVISOR", "BLE", "CLIENT", "IPV4", "LWIP", "COMMON_PAL", "STORAGE", "NANOSTACK",
+        # Nanostack configurations
+        "LOWPAN_BORDER_ROUTER", "LOWPAN_HOST", "LOWPAN_ROUTER", "NANOSTACK_FULL", "THREAD_BORDER_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER", "ETHERNET_HOST"
+        ]
+
+    def __init__(self, tgt, top_level_dirs=None, app_config=None):
+        """Construct a mbed configuration
+
+        Positional arguments:
+        target - the name of the mbed target used for this configuration
+                 instance
+
+        Keyword argumets:
+        top_level_dirs - a list of top level source directories (where
+                         mbed_app_config.json could be found)
+        app_config - location of a chosen mbed_app.json file
+
+        NOTE: Construction of a Config object will look for the application
+        configuration file in top_level_dirs. If found once, it'll parse it.
+        top_level_dirs may be None (in this case, the constructor will not
+        search for a configuration file).
+        """
+        config_errors = []
+        self.app_config_location = app_config
+        if self.app_config_location is None:
+            for directory in top_level_dirs or []:
+                full_path = os.path.join(directory, self.__mbed_app_config_name)
+                if os.path.isfile(full_path):
+                    if self.app_config_location is not None:
+                        raise ConfigException("Duplicate '%s' file in '%s' and '%s'"
+                                              % (self.__mbed_app_config_name,
+                                                 self.app_config_location, full_path))
+                    else:
+                        self.app_config_location = full_path
+        try:
+            self.app_config_data = json_file_to_dict(self.app_config_location) \
+                                   if self.app_config_location else {}
+        except ValueError as exc:
+            self.app_config_data = {}
+            config_errors.append(
+                ConfigException("Could not parse mbed app configuration from %s"
+                                % self.app_config_location))
+
+        # Check the keys in the application configuration data
+        unknown_keys = set(self.app_config_data.keys()) - \
+                       set(self.__allowed_keys["application"].keys())
+        if unknown_keys:
+            raise ConfigException("Unknown key(s) '%s' in %s" %
+                                  (",".join(unknown_keys),
+                                   self.__mbed_app_config_name))
+        check_dict_types(self.app_config_data, self.__allowed_keys["application"],
+                         "app-config")
+        # Update the list of targets with the ones defined in the application
+        # config, if applicable
+        self.lib_config_data = {}
+        # Make sure that each config is processed only once
+        self.processed_configs = {}
+        if isinstance(tgt, basestring):
+            if tgt in TARGET_MAP:
+                self.target = TARGET_MAP[tgt]
+            else:
+                self.target = generate_py_target(
+                    self.app_config_data.get("custom_targets", {}), tgt)
+
+        else:
+            self.target = tgt
+        self.target = deepcopy(self.target)
+        self.target_labels = self.target.labels
+
+        self.cumulative_overrides = {key: ConfigCumulativeOverride(key)
+                                     for key in CUMULATIVE_ATTRIBUTES}
+
+        self._process_config_and_overrides(self.app_config_data, {}, "app",
+                                           "application")
+        self.config_errors = config_errors
+
+    def add_config_files(self, flist):
+        """Add configuration files
+
+        Positional arguments:
+        flist - a list of files to add to this configuration
+        """
+        for config_file in flist:
+            if not config_file.endswith(self.__mbed_lib_config_name):
+                continue
+            full_path = os.path.normpath(os.path.abspath(config_file))
+            # Check that we didn't already process this file
+            if self.processed_configs.has_key(full_path):
+                continue
+            self.processed_configs[full_path] = True
+            # Read the library configuration and add a "__full_config_path"
+            # attribute to it
+            try:
+                cfg = json_file_to_dict(config_file)
+            except ValueError as exc:
+                sys.stderr.write(str(exc) + "\n")
+                continue
+
+            cfg["__config_path"] = full_path
+
+            if "name" not in cfg:
+                raise ConfigException(
+                    "Library configured at %s has no name field." % full_path)
+            # If there's already a configuration for a module with the same
+            # name, exit with error
+            if self.lib_config_data.has_key(cfg["name"]):
+                raise ConfigException(
+                    "Library name '%s' is not unique (defined in '%s' and '%s')"
+                    % (cfg["name"], full_path,
+                       self.lib_config_data[cfg["name"]]["__config_path"]))
+            self.lib_config_data[cfg["name"]] = cfg
+
+    @property
+    def has_regions(self):
+        """Does this config have regions defined?"""
+        if 'target_overrides' in self.app_config_data:
+            target_overrides = self.app_config_data['target_overrides'].get(
+                self.target.name, {})
+            return ('target.bootloader_img' in target_overrides or
+                    'target.restrict_size' in target_overrides or
+                    'target.mbed_app_start' in target_overrides or
+                    'target.mbed_app_size' in target_overrides)
+        else:
+            return False
+
+    @property
+    def regions(self):
+        """Generate a list of regions from the config"""
+        if not self.target.bootloader_supported:
+            raise ConfigException("Bootloader not supported on this target.")
+        if not hasattr(self.target, "device_name"):
+            raise ConfigException("Bootloader not supported on this target: "
+                                  "targets.json `device_name` not specified.")
+        cache = Cache(False, False)
+        if self.target.device_name not in cache.index:
+            raise ConfigException("Bootloader not supported on this target: "
+                                  "targets.json `device_name` not found in "
+                                  "arm_pack_manager index.")
+        cmsis_part = cache.index[self.target.device_name]
+        target_overrides = self.app_config_data['target_overrides'].get(
+            self.target.name, {})
+        if  (('target.bootloader_img' in target_overrides or
+              'target.restrict_size' in target_overrides) and
+             ('target.mbed_app_start' in target_overrides or
+              'target.mbed_app_size' in target_overrides)):
+            raise ConfigException(
+                "target.bootloader_img and target.restirct_size are "
+                "incompatible with target.mbed_app_start and "
+                "target.mbed_app_size")
+        try:
+            rom_size = int(cmsis_part['memory']['IROM1']['size'], 0)
+            rom_start = int(cmsis_part['memory']['IROM1']['start'], 0)
+        except KeyError:
+            raise ConfigException("Not enough information in CMSIS packs to "
+                                  "build a bootloader project")
+        if  ('target.bootloader_img' in target_overrides or
+             'target.restrict_size' in target_overrides):
+            return self._generate_booloader_build(target_overrides,
+                                                  rom_start, rom_size)
+        elif ('target.mbed_app_start' in target_overrides or
+              'target.mbed_app_size' in target_overrides):
+            return self._generate_linker_overrides(target_overrides,
+                                                   rom_start, rom_size)
+        else:
+            raise ConfigException(
+                "Bootloader build requested but no bootlader configuration")
+
+    def _generate_booloader_build(self, target_overrides, rom_start, rom_size):
+        start = 0
+        if 'target.bootloader_img' in target_overrides:
+            basedir = abspath(dirname(self.app_config_location))
+            filename = join(basedir, target_overrides['target.bootloader_img'])
+            if not exists(filename):
+                raise ConfigException("Bootloader %s not found" % filename)
+            part = intelhex_offset(filename, offset=rom_start)
+            if part.minaddr() != rom_start:
+                raise ConfigException("bootloader executable does not "
+                                      "start at 0x%x" % rom_start)
+            part_size = (part.maxaddr() - part.minaddr()) + 1
+            yield Region("bootloader", rom_start + start, part_size, False,
+                         filename)
+            start += part_size
+        if 'target.restrict_size' in target_overrides:
+            new_size = int(target_overrides['target.restrict_size'], 0)
+            yield Region("application", rom_start + start, new_size, True, None)
+            start += new_size
+            yield Region("post_application", rom_start +start, rom_size - start,
+                         False, None)
+        else:
+            yield Region("application", rom_start + start, rom_size - start,
+                         True, None)
+        if start > rom_size:
+            raise ConfigException("Not enough memory on device to fit all "
+                                  "application regions")
+
+    @property
+    def report(self):
+        return {'app_config': self.app_config_location,
+                'library_configs': map(relpath, self.processed_configs.keys())}
+
+    @staticmethod
+    def _generate_linker_overrides(target_overrides, rom_start, rom_size):
+        if 'target.mbed_app_start' in target_overrides:
+            start = int(target_overrides['target.mbed_app_start'], 0)
+        else:
+            start = rom_start
+        if 'target.mbed_app_size' in target_overrides:
+            size = int(target_overrides['target.mbed_app_size'], 0)
+        else:
+            size = (rom_size + rom_start) - start
+        if start < rom_start:
+            raise ConfigException("Application starts before ROM")
+        if size + start > rom_size + rom_start:
+            raise ConfigException("Application ends after ROM")
+        yield Region("application", start, size, True, None)
+
+    def _process_config_and_overrides(self, data, params, unit_name, unit_kind):
+        """Process "config_parameters" and "target_config_overrides" into a
+        given dictionary
+
+        Positional arguments:
+        data - the configuration data of the library/appliation
+        params - storage for the discovered configuration parameters
+        unit_name - the unit (library/application) that defines this parameter
+        unit_kind - the kind of the unit ("library" or "application")
+        """
+        self.config_errors = []
+        _process_config_parameters(data.get("config", {}), params, unit_name,
+                                   unit_kind)
+        for label, overrides in data.get("target_overrides", {}).items():
+            # If the label is defined by the target or it has the special value
+            # "*", process the overrides
+            if (label == '*') or (label in self.target_labels):
+                # Check for invalid cumulative overrides in libraries
+                if (unit_kind == 'library' and
+                    any(attr.startswith('target.extra_labels') for attr
+                        in overrides.iterkeys())):
+                    raise ConfigException(
+                        "Target override 'target.extra_labels' in " +
+                        ConfigParameter.get_display_name(unit_name, unit_kind,
+                                                         label) +
+                        " is only allowed at the application level")
+
+                # Parse out cumulative overrides
+                for attr, cumulatives in self.cumulative_overrides.iteritems():
+                    if 'target.'+attr in overrides:
+                        key = 'target.' + attr
+                        if not isinstance(overrides[key], list):
+                            raise ConfigException(
+                                "The value of %s.%s is not of type %s" %
+                                (unit_name, "target_overrides." + key,
+                                 "list"))
+                        cumulatives.strict_cumulative_overrides(overrides[key])
+                        del overrides[key]
+
+                    if 'target.'+attr+'_add' in overrides:
+                        key = 'target.' + attr + "_add"
+                        if not isinstance(overrides[key], list):
+                            raise ConfigException(
+                                "The value of %s.%s is not of type %s" %
+                                (unit_name, "target_overrides." + key,
+                                 "list"))
+                        cumulatives.add_cumulative_overrides(overrides[key])
+                        del overrides[key]
+
+                    if 'target.'+attr+'_remove' in overrides:
+                        key = 'target.' + attr + "_remove"
+                        if not isinstance(overrides[key], list):
+                            raise ConfigException(
+                                "The value of %s.%s is not of type %s" %
+                                (unit_name, "target_overrides." + key,
+                                 "list"))
+                        cumulatives.remove_cumulative_overrides(overrides[key])
+                        del overrides[key]
+
+                # Consider the others as overrides
+                for name, val in overrides.items():
+                    # Get the full name of the parameter
+                    full_name = ConfigParameter.get_full_name(name, unit_name,
+                                                              unit_kind, label)
+                    if full_name in params:
+                        params[full_name].set_value(val, unit_name, unit_kind,
+                                                    label)
+                    elif name in self.__unused_overrides:
+                        pass
+                    elif (name.startswith("target.") and
+                          unit_kind is "application"):
+                        _, attribute = name.split(".")
+                        setattr(self.target, attribute, val)
+                    else:
+                        self.config_errors.append(
+                            ConfigException(
+                                "Attempt to override undefined parameter" +
+                                (" '%s' in '%s'"
+                                 % (full_name,
+                                    ConfigParameter.get_display_name(unit_name,
+                                                                     unit_kind,
+                                                                     label)))))
+
+        for cumulatives in self.cumulative_overrides.itervalues():
+            cumulatives.update_target(self.target)
+
+        return params
+
+    def get_target_config_data(self):
+        """Read and interpret configuration data defined by targets.
+
+        We consider the resolution order for our target and sort it by level
+        reversed, so that we first look at the top level target (the parent),
+        then its direct children, then the children of those children and so on,
+        until we reach self.target
+        TODO: this might not work so well in some multiple inheritance scenarios
+        At each step, look at two keys of the target data:
+          - config_parameters: used to define new configuration parameters
+          - config_overrides: used to override already defined configuration
+                              parameters
+
+        Arguments: None
+        """
+        params, json_data = {}, self.target.json_data
+        resolution_order = [e[0] for e
+                            in sorted(
+                                self.target.resolution_order,
+                                key=lambda e: e[1], reverse=True)]
+        for tname in resolution_order:
+            # Read the target data directly from its description
+            target_data = json_data[tname]
+            # Process definitions first
+            _process_config_parameters(target_data.get("config", {}), params,
+                                       tname, "target")
+            # Then process overrides
+            for name, val in target_data.get("overrides", {}).items():
+                full_name = ConfigParameter.get_full_name(name, tname, "target")
+                # If the parameter name is not defined or if there isn't a path
+                # from this target to the target where the parameter was defined
+                # in the target inheritance tree, raise an error We need to use
+                # 'defined_by[7:]' to remove the "target:" prefix from
+                # defined_by
+                rel_names = [tgt for tgt, _ in
+                             get_resolution_order(self.target.json_data, tname,
+                                                  [])]
+                if full_name in self.__unused_overrides:
+                    continue
+                if (full_name not in params) or \
+                   (params[full_name].defined_by[7:] not in rel_names):
+                    raise ConfigException(
+                        "Attempt to override undefined parameter '%s' in '%s'"
+                        % (name,
+                           ConfigParameter.get_display_name(tname, "target")))
+                # Otherwise update the value of the parameter
+                params[full_name].set_value(val, tname, "target")
+        return params
+
+    def get_lib_config_data(self):
+        """ Read and interpret configuration data defined by libraries. It is
+        assumed that "add_config_files" above was already called and the library
+        configuration data exists in self.lib_config_data
+
+        Arguments: None
+        """
+        all_params, macros = {}, {}
+        for lib_name, lib_data in self.lib_config_data.items():
+            unknown_keys = (set(lib_data.keys()) -
+                            set(self.__allowed_keys["library"].keys()))
+            if unknown_keys:
+                raise ConfigException("Unknown key(s) '%s' in %s" %
+                                      (",".join(unknown_keys), lib_name))
+            check_dict_types(lib_data, self.__allowed_keys["library"], lib_name)
+            all_params.update(self._process_config_and_overrides(lib_data, {},
+                                                                 lib_name,
+                                                                 "library"))
+            _process_macros(lib_data.get("macros", []), macros, lib_name,
+                            "library")
+        return all_params, macros
+
+    def get_app_config_data(self, params, macros):
+        """ Read and interpret the configuration data defined by the target. The
+        target can override any configuration parameter, as well as define its
+        own configuration data.
+
+        Positional arguments.
+        params - the dictionary with configuration parameters found so far (in
+                 the target and in libraries)
+        macros - the list of macros defined in the configuration
+        """
+        app_cfg = self.app_config_data
+        # The application can have a "config_parameters" and a
+        # "target_config_overrides" section just like a library
+        self._process_config_and_overrides(app_cfg, params, "app",
+                                           "application")
+        # The application can also defined macros
+        _process_macros(app_cfg.get("macros", []), macros, "app",
+                        "application")
+
+    def get_config_data(self):
+        """ Return the configuration data in two parts: (params, macros)
+        params - a dictionary with mapping a name to a ConfigParam
+        macros - the list of macros defined with "macros" in libraries and in
+                 the application (as ConfigMacro instances)
+
+        Arguments: None
+        """
+        all_params = self.get_target_config_data()
+        lib_params, macros = self.get_lib_config_data()
+        all_params.update(lib_params)
+        self.get_app_config_data(all_params, macros)
+        return all_params, macros
+
+    @staticmethod
+    def _check_required_parameters(params):
+        """Check that there are no required parameters without a value
+
+        Positional arguments:
+        params - the list of parameters to check
+
+        NOTE: This function does not return. Instead, it throws a
+        ConfigException when any of the required parameters are missing values
+        """
+        for param in params.values():
+            if param.required and (param.value is None):
+                raise ConfigException("Required parameter '" + param.name +
+                                      "' defined by '" + param.defined_by +
+                                      "' doesn't have a value")
+
+    @staticmethod
+    def parameters_to_macros(params):
+        """ Encode the configuration parameters as C macro definitions.
+
+        Positional arguments:
+        params - a dictionary mapping a name to a ConfigParameter
+
+        Return: a list of strings that encode the configuration parameters as
+        C pre-processor macros
+        """
+        return ['%s=%s' % (m.macro_name, m.value) for m in params.values()
+                if m.value is not None]
+
+    @staticmethod
+    def config_macros_to_macros(macros):
+        """ Return the macro definitions generated for a dictionary of
+        ConfigMacros (as returned by get_config_data).
+
+        Positional arguments:
+        params - a dictionary mapping a name to a ConfigMacro instance
+
+        Return: a list of strings that are the C pre-processor macros
+        """
+        return [m.name for m in macros.values()]
+
+    @staticmethod
+    def config_to_macros(config):
+        """Convert the configuration data to a list of C macros
+
+        Positional arguments:
+        config - configuration data as (ConfigParam instances, ConfigMacro
+                 instances) tuple (as returned by get_config_data())
+        """
+        params, macros = config[0], config[1]
+        Config._check_required_parameters(params)
+        return Config.config_macros_to_macros(macros) + \
+            Config.parameters_to_macros(params)
+
+    def get_config_data_macros(self):
+        """ Convert a Config object to a list of C macros
+
+        Arguments: None
+        """
+        return self.config_to_macros(self.get_config_data())
+
+    def get_features(self):
+        """ Extract any features from the configuration data
+
+        Arguments: None
+        """
+        params, _ = self.get_config_data()
+        self._check_required_parameters(params)
+        self.cumulative_overrides['features']\
+            .update_target(self.target)
+
+        for feature in self.target.features:
+            if feature not in self.__allowed_features:
+                raise ConfigException(
+                    "Feature '%s' is not a supported features" % feature)
+
+        return self.target.features
+
+    def validate_config(self):
+        """ Validate configuration settings. This either returns True or
+        raises an exception
+
+        Arguments: None
+        """
+        if self.config_errors:
+            raise self.config_errors[0]
+        return True
+
+
+    @property
+    def name(self):
+        if "artifact_name" in self.app_config_data:
+            return self.app_config_data["artifact_name"]
+        else:
+            return None
+
+    def load_resources(self, resources):
+        """ Load configuration data from a Resources instance and expand it
+        based on defined features.
+
+        Positional arguments:
+        resources - the resources object to load from and expand
+        """
+        # Update configuration files until added features creates no changes
+        prev_features = set()
+        self.validate_config()
+        while True:
+            # Add/update the configuration with any .json files found while
+            # scanning
+            self.add_config_files(resources.json_files)
+
+            # Add features while we find new ones
+            features = set(self.get_features())
+            if features == prev_features:
+                break
+
+            for feature in features:
+                if feature in resources.features:
+                    resources.add(resources.features[feature])
+
+            prev_features = features
+        self.validate_config()
+
+        return resources
+
+    @staticmethod
+    def config_to_header(config, fname=None):
+        """ Convert the configuration data to the content of a C header file,
+        meant to be included to a C/C++ file. The content is returned as a
+        string.
+
+        Positional arguments:
+        config - configuration data as (ConfigParam instances, ConfigMacro
+                 instances) tuple (as returned by get_config_data())
+
+        Keyword arguments:
+        fname -  also write the content is to the file called "fname".
+                 WARNING: if 'fname' names an existing file, it will be
+                 overwritten!
+        """
+        params, macros = config[0] or {}, config[1] or {}
+        Config._check_required_parameters(params)
+        params_with_values = [p for p in params.values() if p.value is not None]
+        ctx = {
+            "cfg_params" : [(p.macro_name, str(p.value), p.set_by)
+                            for p in params_with_values],
+            "macros": [(m.macro_name, str(m.macro_value or ""), m.defined_by)
+                       for m in macros.values()],
+            "name_len":  max([len(m.macro_name) for m in macros.values()] +
+                             [len(m.macro_name) for m in params_with_values]
+                             + [0]),
+            "val_len" : max([len(str(m.value)) for m in params_with_values] +
+                            [len(m.macro_value or "") for m in macros.values()]
+                            + [0]),
+        }
+        jinja_loader = FileSystemLoader(dirname(abspath(__file__)))
+        jinja_environment = Environment(loader=jinja_loader,
+                                        undefined=StrictUndefined)
+        header_data = jinja_environment.get_template("header.tmpl").render(ctx)
+        # If fname is given, write "header_data" to it
+        if fname:
+            with open(fname, "w+") as file_desc:
+                file_desc.write(header_data)
+        return header_data
+
+    def get_config_data_header(self, fname=None):
+        """ Convert a Config instance to the content of a C header file, meant
+        to be included to a C/C++ file. The content is returned as a string.
+
+        Keyword arguments:
+        fname - also write the content to the file called "fname".
+                WARNING: if 'fname' names an existing file, it will be
+                overwritten!
+        """
+        return self.config_to_header(self.get_config_data(), fname)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/__init__.pyc
new file mode 100755
index 0000000..f780e09
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/header.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/header.tmpl
new file mode 100755
index 0000000..83c9adc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/config/header.tmpl
@@ -0,0 +1,44 @@
+/*
+ * mbed SDK
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// Automatically generated configuration file.
+// DO NOT EDIT, content will be overwritten.
+
+#ifndef __MBED_CONFIG_DATA__
+#define __MBED_CONFIG_DATA__
+
+{% if cfg_params -%}
+// Configuration parameters
+{% for name, value, set_by in cfg_params -%}
+{% if value is not none -%}
+#define {{name.ljust(name_len)}} {{value.ljust(val_len)}} // set by {{set_by}}
+{%- endif %}
+{% endfor %}
+{%- endif -%}
+
+{%- if macros -%}
+// Macros
+{% for name, value, set_by in macros -%}
+{% if value is not none -%}
+#define {{name.ljust(name_len)}} {{value.ljust(val_len)}} // defined by {{set_by}}
+{%- else -%}
+#define {{name.ljust(name_len + val_len + 1)}} // defined by {{set_by}}
+{%- endif %}
+{% endfor %}
+{%- endif %}
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/__init__.py
new file mode 100755
index 0000000..1fa8431
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/__init__.py
@@ -0,0 +1,16 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/__init__.pyc
new file mode 100755
index 0000000..9331698
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/rpc/RPCClasses.h b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/rpc/RPCClasses.h
new file mode 100755
index 0000000..ab90b53
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/rpc/RPCClasses.h
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_CLASSES_H
+#define MBED_CLASSES_H
+
+#include "rpc.h"
+
+namespace mbed {
+
+{{classes}}
+
+}
+
+#endif
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/rpc/class.cpp b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/rpc/class.cpp
new file mode 100755
index 0000000..f783198
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/rpc/class.cpp
@@ -0,0 +1,24 @@
+class Rpc{{name}} : public RPC {
+public:
+    Rpc{{name}}({{cons_proto}}) : RPC(name), o({{cons_call}}) {}
+
+    {{methods}}
+
+    virtual const struct rpc_method *get_rpc_methods() {
+        static const rpc_method rpc_methods[] = {
+            {{rpc_methods}},
+            RPC_METHOD_SUPER(RPC)
+        };
+        return rpc_methods;
+    }
+    static struct rpc_class *get_rpc_class() {
+        static const rpc_function funcs[] = {
+            {"new", rpc_function_caller<const char*, {{cons_type}}, &RPC::construct<Rpc{{name}}, {{cons_type}}> >},
+            RPC_METHOD_END
+        };
+        static rpc_class c = {"{{name}}", funcs, NULL};
+        return &c;
+    }
+private:
+    {{name}} o;
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/support.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/support.py
new file mode 100755
index 0000000..7af3774
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/support.py
@@ -0,0 +1,27 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from tools.targets import TARGETS
+
+DEFAULT_SUPPORT = {}
+CORTEX_ARM_SUPPORT = {}
+
+for target in TARGETS:
+    DEFAULT_SUPPORT[target.name] = target.supported_toolchains
+
+    if target.core.startswith('Cortex'):
+        CORTEX_ARM_SUPPORT[target.name] = [t for t in target.supported_toolchains
+                                           if (t=='ARM' or t=='uARM')]
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/support.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/support.pyc
new file mode 100755
index 0000000..e6197b6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/data/support.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/default_settings.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/default_settings.py
new file mode 100755
index 0000000..756b043
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/default_settings.py
@@ -0,0 +1,45 @@
+"""
+mbed SDK
+Copyright (c) 2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from os.path import join, abspath, dirname
+
+#ROOT = abspath(join(dirname(__file__), "."))
+
+##############################################################################
+# Build System Settings
+##############################################################################
+#BUILD_DIR = abspath(join(ROOT, "build"))
+
+# ARM
+#ARM_PATH = "C:/Program Files/ARM"
+
+# GCC ARM
+#GCC_ARM_PATH = ""
+
+# GCC CodeRed
+#GCC_CR_PATH = "C:/code_red/RedSuite_4.2.0_349/redsuite/Tools/bin"
+
+# IAR
+#IAR_PATH = "C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0/arm"
+
+# Goanna static analyser. Please overload it in private_settings.py
+#GOANNA_PATH = "c:/Program Files (x86)/RedLizards/Goanna Central 3.2.3/bin"
+
+#BUILD_OPTIONS = []
+
+# mbed.org username
+#MBED_ORG_USER = ""
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/detect_targets.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/detect_targets.py
new file mode 100755
index 0000000..b9aa80d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/detect_targets.py
@@ -0,0 +1,130 @@
+#! /usr/bin/env python2
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import sys
+import os
+import re
+
+ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.options import get_default_options_parser
+
+# Check: Extra modules which are required by core test suite
+from tools.utils import check_required_modules
+check_required_modules(['prettytable'])
+
+# Imports related to mbed build api
+from tools.build_api import mcu_toolchain_matrix
+from tools.test_api import get_autodetected_MUTS_list
+from tools.test_api import get_module_avail
+from argparse import ArgumentParser
+
+try:
+    import mbed_lstools
+except:
+    pass
+
+def main():
+    """Entry Point"""
+    try:
+        # Parse Options
+        parser = ArgumentParser()
+
+        parser.add_argument("-S", "--supported-toolchains",
+                            action="store_true",
+                            dest="supported_toolchains",
+                            default=False,
+                            help="Displays supported matrix of"
+                            " targets and toolchains")
+
+        parser.add_argument('-f', '--filter',
+                            dest='general_filter_regex',
+                            default=None,
+                            help='Filter targets')
+
+        parser.add_argument("-v", "--verbose",
+                            action="store_true",
+                            dest="verbose",
+                            default=False,
+                            help="Verbose diagnostic output")
+
+        options = parser.parse_args()
+
+        # Only prints matrix of supported toolchains
+        if options.supported_toolchains:
+            print mcu_toolchain_matrix(
+                platform_filter=options.general_filter_regex)
+            exit(0)
+
+        # If auto_detect attribute is present, we assume other auto-detection
+        # parameters like 'toolchains_filter' are also set.
+        muts = get_autodetected_MUTS_list()
+
+        mcu_filter = options.general_filter_regex or ".*"
+
+        count = 0
+        for mut in muts.values():
+            if re.match(mcu_filter, mut['mcu']):
+                interface_version = get_interface_version(mut['disk'])
+                print ""
+                print "[mbed] Detected %s, port %s, mounted %s, interface version %s:" % \
+                        (mut['mcu'], mut['port'], mut['disk'], interface_version)
+                                    
+                print "[mbed] Supported toolchains for %s" % mut['mcu']
+                print mcu_toolchain_matrix(platform_filter=mut['mcu'])
+                count += 1
+
+        if count == 0:
+            print "[mbed] No mbed targets were detected on your system."
+
+    except KeyboardInterrupt:
+        print "\n[CTRL+c] exit"
+    except Exception as exc:
+        import traceback
+        traceback.print_exc(file=sys.stdout)
+        print "[ERROR] %s" % str(exc)
+        sys.exit(1)
+        
+def get_interface_version(mount_point):
+    """ Function returns interface version from the target mounted on the specified mount point
+    
+        mount_point can be acquired via the following:
+            muts = get_autodetected_MUTS_list()
+            for mut in muts.values():
+                mount_point = mut['disk']
+                    
+        @param mount_point Name of disk where platform is connected to host machine.
+    """
+    if get_module_avail('mbed_lstools'):
+        try :
+            mbeds = mbed_lstools.create()
+            details_txt = mbeds.get_details_txt(mount_point)
+            
+            if 'Interface Version' in details_txt:
+                return details_txt['Interface Version']
+            
+            elif 'Version' in details_txt:
+                return details_txt['Version']
+            
+        except :
+            return 'unknown'
+        
+    return 'unknown'
+
+if __name__ == '__main__':
+    main()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/__init__.py
new file mode 100755
index 0000000..1fa8431
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/__init__.py
@@ -0,0 +1,16 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/dsp_fir.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/dsp_fir.py
new file mode 100755
index 0000000..f62c2b4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/dsp_fir.py
@@ -0,0 +1,89 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from numpy import sin, arange, pi
+from scipy.signal import lfilter, firwin
+from pylab import figure, plot, grid, show
+
+#------------------------------------------------
+# Create a signal for demonstration.
+#------------------------------------------------
+# 320 samples of (1000Hz + 15000 Hz) at 48 kHz
+sample_rate = 48000.
+nsamples = 320
+
+F_1KHz = 1000.
+A_1KHz = 1.0
+
+F_15KHz = 15000.
+A_15KHz = 0.5
+
+t = arange(nsamples) / sample_rate
+signal = A_1KHz * sin(2*pi*F_1KHz*t) + A_15KHz*sin(2*pi*F_15KHz*t)
+
+#------------------------------------------------
+# Create a FIR filter and apply it to signal.
+#------------------------------------------------
+# The Nyquist rate of the signal.
+nyq_rate = sample_rate / 2.
+
+# The cutoff frequency of the filter: 6KHz
+cutoff_hz = 6000.0
+
+# Length of the filter (number of coefficients, i.e. the filter order + 1)
+numtaps = 29
+
+# Use firwin to create a lowpass FIR filter
+fir_coeff = firwin(numtaps, cutoff_hz/nyq_rate)
+
+# Use lfilter to filter the signal with the FIR filter
+filtered_signal = lfilter(fir_coeff, 1.0, signal)
+
+#------------------------------------------------
+# Plot the original and filtered signals.
+#------------------------------------------------
+
+# The first N-1 samples are "corrupted" by the initial conditions
+warmup = numtaps - 1
+
+# The phase delay of the filtered signal
+delay = (warmup / 2) / sample_rate
+
+figure(1)
+# Plot the original signal
+plot(t, signal)
+
+# Plot the filtered signal, shifted to compensate for the phase delay
+plot(t-delay, filtered_signal, 'r-')
+
+# Plot just the "good" part of the filtered signal.  The first N-1
+# samples are "corrupted" by the initial conditions.
+plot(t[warmup:]-delay, filtered_signal[warmup:], 'g', linewidth=4)
+
+grid(True)
+
+show()
+
+#------------------------------------------------
+# Print values
+#------------------------------------------------
+def print_values(label, values):
+    var = "float32_t %s[%d]" % (label, len(values))
+    print "%-30s = {%s}" % (var, ', '.join(["%+.10f" % x for x in values]))
+
+print_values('signal', signal)
+print_values('fir_coeff', fir_coeff)
+print_values('filtered_signal', filtered_signal)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/intel_hex_utils.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/intel_hex_utils.py
new file mode 100755
index 0000000..c60e9c4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/intel_hex_utils.py
@@ -0,0 +1,31 @@
+from intelhex import IntelHex
+from cStringIO import StringIO
+
+
+def sections(h):
+    start, last_address = None, None
+    for a in h.addresses():
+        if last_address is None:
+            start, last_address = a, a
+            continue
+
+        if a > last_address + 1:
+            yield (start, last_address)
+            start = a
+
+        last_address = a
+
+    if start:
+        yield (start, last_address)
+
+
+def print_sections(h):
+    for s in sections(h):
+        print "[0x%08X - 0x%08X]" % s
+
+
+def decode(record):
+    h = IntelHex()
+    f = StringIO(record)
+    h.loadhex(f)
+    h.dump()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/rpc_classes.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/rpc_classes.py
new file mode 100755
index 0000000..46fd902
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/rpc_classes.py
@@ -0,0 +1,190 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import join
+from jinja2 import Template
+
+from tools.paths import TOOLS_DATA, MBED_RPC
+
+RPC_TEMPLATES_PATH = join(TOOLS_DATA, "rpc")
+
+RPC_TEMPLATE = "RPCClasses.h"
+CLASS_TEMPLATE = "class.cpp"
+RPC_CLASSES_PATH = join(MBED_RPC, RPC_TEMPLATE)
+
+
+def get_template(name):
+    return Template(open(join(RPC_TEMPLATES_PATH, name)).read())
+
+
+def write_rpc_classes(classes):
+    template = get_template(RPC_TEMPLATE)
+    open(RPC_CLASSES_PATH, "w").write(template.render({"classes":classes}))
+
+
+RPC_CLASSES = (
+    {
+        "name": "DigitalOut",
+        "cons_args": ["PinName"],
+        "methods": [
+            (None , "write", ["int"]),
+            ("int", "read" , []),
+        ]
+    },
+    {
+        "name": "DigitalIn",
+        "cons_args": ["PinName"],
+        "methods": [
+            ("int", "read" , []),
+        ]
+    },
+    {
+        "name": "DigitalInOut",
+        "cons_args": ["PinName"],
+        "methods": [
+            ("int", "read"  , []),
+            (None , "write" , ["int"]),
+            (None , "input" , []),
+            (None , "output", []),
+        ]
+    },
+    {
+        "name": "AnalogIn",
+        "required": "ANALOGIN",
+        "cons_args": ["PinName"],
+        "methods": [
+            ("float"         , "read"    , []),
+            ("unsigned short", "read_u16", []),
+        ]
+    },
+    {
+        "name": "AnalogOut",
+        "required": "ANALOGOUT",
+        "cons_args": ["PinName"],
+        "methods": [
+            ("float", "read"     , []),
+            (None   , "write"    , ["float"]),
+            (None   , "write_u16", ["unsigned short"]),
+        ]
+    },
+    {
+        "name": "PwmOut",
+        "required": "PWMOUT",
+        "cons_args": ["PinName"],
+        "methods": [
+            ("float", "read"         , []),
+            (None   , "write"        , ["float"]),
+            (None   , "period"       , ["float"]),
+            (None   , "period_ms"    , ["int"]),
+            (None   , "pulsewidth"   , ["float"]),
+            (None   , "pulsewidth_ms", ["int"]),
+        ]
+    },
+    {
+        "name": "SPI",
+        "required": "SPI",
+        "cons_args": ["PinName", "PinName", "PinName"],
+        "methods": [
+            (None , "format"   , ["int", "int"]),
+            (None , "frequency", ["int"]),
+            ("int", "write"    , ["int"]),
+        ]
+    },
+    {
+        "name": "Serial",
+        "required": "SERIAL",
+        "cons_args": ["PinName", "PinName"],
+        "methods": [
+            (None , "baud"     , ["int"]),
+            ("int", "readable" , []),
+            ("int", "writeable", []),
+            ("int", "putc"     , ["int"]),
+            ("int", "getc"     , []),
+            ("int", "puts"     , ["const char *"]),
+        ]
+    },
+    {
+        "name": "Timer",
+        "cons_args": [],
+        "methods": [
+            (None   , "start"  , []),
+            (None   , "stop"   , []),
+            (None   , "reset"  , []),
+            ("float", "read"   , []),
+            ("int"  , "read_ms", []),
+            ("int"  , "read_us", []),
+        ]
+    }
+)
+
+
+def get_args_proto(args_types, extra=None):
+    args = ["%s a%d" % (s, n) for n, s in enumerate(args_types)]
+    if extra:
+        args.extend(extra)
+    return ', '.join(args)
+
+
+def get_args_call(args):
+    return ', '.join(["a%d"    % (n)    for n in range(len(args))])
+
+
+classes = []
+class_template = get_template(CLASS_TEMPLATE)
+
+for c in RPC_CLASSES:
+    c_args = c['cons_args']
+    data = {
+        'name': c['name'],
+        'cons_type': ', '.join(c_args + ['const char*']),
+        "cons_proto": get_args_proto(c_args, ["const char *name=NULL"]),
+        "cons_call": get_args_call(c_args)
+    }
+
+    c_name = "Rpc" +  c['name']
+
+    methods = []
+    rpc_methods = []
+    for r, m, a in c['methods']:
+        ret_proto = r if r else "void"
+        args_proto = "void"
+
+        ret_defin = "return " if r else ""
+        args_defin = ""
+
+        if a:
+            args_proto = get_args_proto(a)
+            args_defin = get_args_call(a)
+
+        proto = "%s %s(%s)"   % (ret_proto, m, args_proto)
+        defin = "{%so.%s(%s);}" % (ret_defin, m, args_defin)
+        methods.append("%s %s" % (proto, defin))
+
+        rpc_method_type = [r] if r else []
+        rpc_method_type.append(c_name)
+        rpc_method_type.extend(a)
+        rpc_methods.append('{"%s", rpc_method_caller<%s, &%s::%s>}' % (m, ', '.join(rpc_method_type), c_name, m))
+
+    data['methods'] = "\n    ".join(methods)
+    data['rpc_methods'] = ",\n            ".join(rpc_methods)
+
+    class_decl = class_template.render(data)
+    if 'required' in c:
+        class_decl = "#if DEVICE_%s\n%s\n#endif" % (c['required'], class_decl)
+
+    classes.append(class_decl)
+
+write_rpc_classes('\n\n'.join(classes))
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/syms.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/syms.py
new file mode 100755
index 0000000..2fdbd2d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/dev/syms.py
@@ -0,0 +1,75 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+Utility to find which libraries could define a given symbol
+"""
+from argparse import ArgumentParser
+from os.path import join, splitext
+from os import walk
+from subprocess import Popen, PIPE
+
+
+OBJ_EXT = ['.o', '.a', '.ar']
+
+
+def find_sym_in_lib(sym, obj_path):
+    contain_symbol = False
+
+    out = Popen(["nm", "-C", obj_path], stdout=PIPE, stderr=PIPE).communicate()[0]
+    for line in out.splitlines():
+            tokens = line.split()
+            n = len(tokens)
+            if n == 2:
+                sym_type = tokens[0]
+                sym_name = tokens[1]
+            elif n == 3:
+                sym_type = tokens[1]
+                sym_name = tokens[2]
+            else:
+                continue
+
+            if sym_type == "U":
+                # This object is using this symbol, not defining it
+                continue
+
+            if sym_name == sym:
+                contain_symbol = True
+
+    return contain_symbol
+
+
+def find_sym_in_path(sym, dir_path):
+    for root, _, files in walk(dir_path):
+        for file in files:
+
+            _, ext = splitext(file)
+            if ext not in OBJ_EXT: continue
+
+            path = join(root, file)
+            if find_sym_in_lib(sym, path):
+                print path
+
+
+if __name__ == '__main__':
+    parser = ArgumentParser(description='Find Symbol')
+    parser.add_argument('-s', '--sym',  required=True,
+                        help='The symbol to be searched')
+    parser.add_argument('-p', '--path',  required=True,
+                        help='The path where to search')
+    args = parser.parse_args()
+
+    find_sym_in_path(args.sym, args.path)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/.hgignore b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/.hgignore
new file mode 100755
index 0000000..c309ef5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/.hgignore
@@ -0,0 +1,22 @@
+syntax: regexp
+\.hgignore$
+\.git$
+\.svn$
+\.orig$
+\.msub$
+\.meta$
+\.ctags
+\.uvproj$
+\.uvopt$
+\.project$
+\.cproject$
+\.launch$
+\.project$
+\.cproject$
+\.launch$
+Makefile$
+\.ewp$
+\.eww$
+\.htm$
+Debug$
+.settings$
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/.mbed b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/.mbed
new file mode 100755
index 0000000..e87b56d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/.mbed
@@ -0,0 +1 @@
+ROOT=.
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/GettingStarted.html b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/GettingStarted.html
new file mode 100755
index 0000000..9fce79c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/GettingStarted.html
@@ -0,0 +1,16 @@
+<!DOCTYPE HTML>
+<html lang="en-US">
+    <head>
+        <meta charset="UTF-8">
+        <meta http-equiv="refresh"
+              content="1;url="https://os.mbed.com/docs/v5.6/tools/exporting.html>
+        <script type="text/javascript">
+            window.location.href = "https://os.mbed.com/docs/v5.6/tools/exporting.html/"
+        </script>
+        <title>Page Redirection</title>
+    </head>
+    <body>
+        If you are not redirected automatically, please follow the
+        <a href='https://os.mbed.com/docs/v5.6/tools/exporting.html/'>link to the online exporter documentation</a>
+    </body>
+</html>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/__init__.py
new file mode 100755
index 0000000..501be59
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/__init__.py
@@ -0,0 +1,360 @@
+"""The generic interface for all exporters.
+"""
+# mbed SDK
+# Copyright (c) 2011-2016 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import sys
+from os.path import join, abspath, dirname, exists
+from os.path import basename, relpath, normpath, splitext
+from os import makedirs, walk
+import copy
+from shutil import rmtree, copyfile
+import zipfile
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.build_api import prepare_toolchain
+from tools.build_api import scan_resources
+from tools.toolchains import Resources
+from tools.export import lpcxpresso, ds5_5, iar, makefile
+from tools.export import embitz, coide, kds, simplicity, atmelstudio, mcuxpresso
+from tools.export import sw4stm32, e2studio, zip, cmsis, uvision, cdt, vscode
+from tools.export import gnuarmeclipse
+from tools.export import qtcreator
+from tools.targets import TARGET_NAMES
+
+EXPORTERS = {
+    'uvision5': uvision.Uvision,
+    'uvision': uvision.Uvision,
+    'lpcxpresso': lpcxpresso.LPCXpresso,
+    'gcc_arm': makefile.GccArm,
+    'make_gcc_arm': makefile.GccArm,
+    'make_armc5': makefile.Armc5,
+    'make_armc6': makefile.Armc6,
+    'make_iar': makefile.IAR,
+    'ds5_5': ds5_5.DS5_5,
+    'iar': iar.IAR,
+    'embitz' : embitz.EmBitz,
+    'coide' : coide.CoIDE,
+    'kds' : kds.KDS,
+    'simplicityv3' : simplicity.SimplicityV3,
+    'atmelstudio' : atmelstudio.AtmelStudio,
+    'sw4stm32'    : sw4stm32.Sw4STM32,
+    'e2studio' : e2studio.E2Studio,
+    'eclipse_gcc_arm'  : cdt.EclipseGcc,
+    'eclipse_iar'      : cdt.EclipseIAR,
+    'eclipse_armc5'    : cdt.EclipseArmc5,
+    'gnuarmeclipse': gnuarmeclipse.GNUARMEclipse,
+    'mcuxpresso': mcuxpresso.MCUXpresso,
+    'qtcreator': qtcreator.QtCreator,
+    'vscode_gcc_arm' : vscode.VSCodeGcc,
+    'vscode_iar' : vscode.VSCodeIAR,
+    'vscode_armc5' : vscode.VSCodeArmc5
+}
+
+ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN = """
+Sorry, the target %s is not currently supported on the %s toolchain.
+Please refer to <a href='/handbook/Exporting-to-offline-toolchains' target='_blank'>Exporting to offline toolchains</a> for more information.
+"""
+
+ERROR_MESSAGE_NOT_EXPORT_LIBS = """
+To export this project please <a href='http://mbed.org/compiler/?import=http://mbed.org/users/mbed_official/code/mbed-export/k&mode=lib' target='_blank'>import the export version of the mbed library</a>.
+"""
+
+def mcu_ide_list():
+    """Shows list of exportable ides 
+
+    """
+    supported_ides = sorted(EXPORTERS.keys())
+    return "\n".join(supported_ides)
+
+
+def mcu_ide_matrix(verbose_html=False):
+    """Shows target map using prettytable
+
+    Keyword argumets:
+    verbose_html - print the matrix in html format
+    """
+    supported_ides = sorted(EXPORTERS.keys())
+    # Only use it in this function so building works without extra modules
+    from prettytable import PrettyTable, ALL
+
+    # All tests status table print
+    table_printer = PrettyTable(["Platform"] + supported_ides)
+    # Align table
+    for col in supported_ides:
+        table_printer.align[col] = "c"
+    table_printer.align["Platform"] = "l"
+
+    perm_counter = 0
+    for target in sorted(TARGET_NAMES):
+        row = [target]  # First column is platform name
+        for ide in supported_ides:
+            text = "-"
+            if EXPORTERS[ide].is_target_supported(target):
+                if verbose_html:
+                    text = "&#10003;"
+                else:
+                    text = "x"
+                perm_counter += 1
+            row.append(text)
+        table_printer.add_row(row)
+
+    table_printer.border = True
+    table_printer.vrules = ALL
+    table_printer.hrules = ALL
+    # creates a html page in a shorter format suitable for readme.md
+    if verbose_html:
+        result = table_printer.get_html_string()
+    else:
+        result = table_printer.get_string()
+    result += "\n"
+    result += "Total IDEs: %d\n"% (len(supported_ides))
+    if verbose_html:
+        result += "<br>"
+    result += "Total platforms: %d\n"% (len(TARGET_NAMES))
+    if verbose_html:
+        result += "<br>"
+    result += "Total permutations: %d"% (perm_counter)
+    if verbose_html:
+        result = result.replace("&amp;", "&")
+    return result
+
+
+def get_exporter_toolchain(ide):
+    """ Return the exporter class and the toolchain string as a tuple
+
+    Positional arguments:
+    ide - the ide name of an exporter
+    """
+    return EXPORTERS[ide], EXPORTERS[ide].TOOLCHAIN
+
+
+def rewrite_basepath(file_name, resources, export_path, loc):
+    """ Replace the basepath of filename with export_path
+
+    Positional arguments:
+    file_name - the absolute path to a file
+    resources - the resources object that the file came from
+    export_path - the final destination of the file after export
+    """
+    new_f = join(loc, relpath(file_name, resources.file_basepath[file_name]))
+    resources.file_basepath[new_f] = export_path
+    return new_f
+
+
+def subtract_basepath(resources, export_path, loc=""):
+    """ Rewrite all of the basepaths with the export_path
+
+    Positional arguments:
+    resources - the resource object to rewrite the basepaths of
+    export_path - the final destination of the resources with respect to the
+      generated project files
+    """
+    keys = ['s_sources', 'c_sources', 'cpp_sources', 'hex_files',
+            'objects', 'libraries', 'inc_dirs', 'headers', 'linker_script',
+            'lib_dirs']
+    for key in keys:
+        vals = getattr(resources, key)
+        if isinstance(vals, set):
+            vals = list(vals)
+        if isinstance(vals, list):
+            new_vals = []
+            for val in vals:
+                new_vals.append(rewrite_basepath(val, resources, export_path,
+                                                 loc))
+            if isinstance(getattr(resources, key), set):
+                setattr(resources, key, set(new_vals))
+            else:
+                setattr(resources, key, new_vals)
+        elif vals:
+            setattr(resources, key, rewrite_basepath(vals, resources,
+                                                     export_path, loc))
+
+
+def generate_project_files(resources, export_path, target, name, toolchain, ide,
+                           macros=None):
+    """Generate the project files for a project
+
+    Positional arguments:
+    resources - a Resources object containing all of the files needed to build
+      this project
+    export_path - location to place project files
+    name - name of the project
+    toolchain - a toolchain class that corresponds to the toolchain used by the
+      IDE or makefile
+    ide - IDE name to export to
+
+    Optional arguments:
+    macros - additional macros that should be defined within the exported
+      project
+    """
+    exporter_cls, _ = get_exporter_toolchain(ide)
+    exporter = exporter_cls(target, export_path, name, toolchain,
+                            extra_symbols=macros, resources=resources)
+    exporter.generate()
+    files = exporter.generated_files
+    return files, exporter
+
+
+def zip_export(file_name, prefix, resources, project_files, inc_repos):
+    """Create a zip file from an exported project.
+
+    Positional Parameters:
+    file_name - the file name of the resulting zip file
+    prefix - a directory name that will prefix the entire zip file's contents
+    resources - a resources object with files that must be included in the zip
+    project_files - a list of extra files to be added to the root of the prefix
+      directory
+    """
+    with zipfile.ZipFile(file_name, "w") as zip_file:
+        for prj_file in project_files:
+            zip_file.write(prj_file, join(prefix, basename(prj_file)))
+        for loc, res in resources.iteritems():
+            to_zip = (
+                res.headers + res.s_sources + res.c_sources +\
+                res.cpp_sources + res.libraries + res.hex_files + \
+                [res.linker_script] + res.bin_files + res.objects + \
+                res.json_files + res.lib_refs + res.lib_builds)
+            if inc_repos:
+                for directory in res.repo_dirs:
+                    for root, _, files in walk(directory):
+                        for repo_file in files:
+                            source = join(root, repo_file)
+                            to_zip.append(source)
+                            res.file_basepath[source] = res.base_path
+                to_zip += res.repo_files
+            for source in to_zip:
+                if source:
+                    zip_file.write(
+                        source,
+                        join(prefix, loc,
+                             relpath(source, res.file_basepath[source])))
+            for source in res.lib_builds:
+                target_dir, _ = splitext(source)
+                dest = join(prefix, loc,
+                            relpath(target_dir, res.file_basepath[source]),
+                            ".bld", "bldrc")
+                zip_file.write(source, dest)
+
+
+
+def export_project(src_paths, export_path, target, ide, libraries_paths=None,
+                   linker_script=None, notify=None, verbose=False, name=None,
+                   inc_dirs=None, jobs=1, silent=False, extra_verbose=False,
+                   config=None, macros=None, zip_proj=None, inc_repos=False,
+                   build_profile=None, app_config=None):
+    """Generates a project file and creates a zip archive if specified
+
+    Positional Arguments:
+    src_paths - a list of paths from which to find source files
+    export_path - a path specifying the location of generated project files
+    target - the mbed board/mcu for which to generate the executable
+    ide - the ide for which to generate the project fields
+
+    Keyword Arguments:
+    libraries_paths - paths to additional libraries
+    linker_script - path to the linker script for the specified target
+    notify - function is passed all events, and expected to handle notification
+      of the user, emit the events to a log, etc.
+    verbose - assigns the notify function to toolchains print_notify_verbose
+    name - project name
+    inc_dirs - additional include directories
+    jobs - number of threads
+    silent - silent build - no output
+    extra_verbose - assigns the notify function to toolchains
+      print_notify_verbose
+    config - toolchain's config object
+    macros - User-defined macros
+    zip_proj - string name of the zip archive you wish to creat (exclude arg
+     if you do not wish to create an archive
+    """
+
+    # Convert src_path to a list if needed
+    if isinstance(src_paths, dict):
+        paths = sum(src_paths.values(), [])
+    elif isinstance(src_paths, list):
+        paths = src_paths[:]
+    else:
+        paths = [src_paths]
+
+    # Extend src_paths wit libraries_paths
+    if libraries_paths is not None:
+        paths.extend(libraries_paths)
+
+    if not isinstance(src_paths, dict):
+        src_paths = {"": paths}
+
+    # Export Directory
+    if not exists(export_path):
+        makedirs(export_path)
+
+    _, toolchain_name = get_exporter_toolchain(ide)
+
+    # Pass all params to the unified prepare_resources()
+    toolchain = prepare_toolchain(
+        paths, "", target, toolchain_name, macros=macros, jobs=jobs,
+        notify=notify, silent=silent, verbose=verbose,
+        extra_verbose=extra_verbose, config=config, build_profile=build_profile,
+        app_config=app_config)
+    # The first path will give the name to the library
+    toolchain.RESPONSE_FILES = False
+    if name is None:
+        name = basename(normpath(abspath(src_paths[0])))
+
+    # Call unified scan_resources
+    resource_dict = {loc: scan_resources(path, toolchain, inc_dirs=inc_dirs, collect_ignores=True)
+                     for loc, path in src_paths.iteritems()}
+    resources = Resources()
+    toolchain.build_dir = export_path
+    config_header = toolchain.get_config_header()
+    resources.headers.append(config_header)
+    resources.file_basepath[config_header] = dirname(config_header)
+
+    if zip_proj:
+        subtract_basepath(resources, ".")
+        for loc, res in resource_dict.iteritems():
+            temp = copy.deepcopy(res)
+            subtract_basepath(temp, ".", loc)
+            resources.add(temp)
+    else:
+        for _, res in resource_dict.iteritems():
+            resources.add(res)
+
+    # Change linker script if specified
+    if linker_script is not None:
+        resources.linker_script = linker_script
+
+    files, exporter = generate_project_files(resources, export_path,
+                                             target, name, toolchain, ide,
+                                             macros=macros)
+    files.append(config_header)
+    if zip_proj:
+        for resource in resource_dict.values():
+            for label, res in resource.features.iteritems():
+                if label not in toolchain.target.features:
+                    resource.add(res)
+        if isinstance(zip_proj, basestring):
+            zip_export(join(export_path, zip_proj), name, resource_dict,
+                       files + list(exporter.static_files), inc_repos)
+        else:
+            zip_export(zip_proj, name, resource_dict,
+                       files + list(exporter.static_files), inc_repos)
+    else:
+        for static_file in exporter.static_files:
+            if not exists(join(export_path, basename(static_file))):
+                copyfile(static_file, join(export_path, basename(static_file)))
+
+    return exporter
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/__init__.pyc
new file mode 100755
index 0000000..008f035
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/__init__.py
new file mode 100755
index 0000000..f123810
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/__init__.py
@@ -0,0 +1,85 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import uuid
+from os.path import splitext, basename, dirname
+
+from tools.export.exporters import Exporter, deprecated_exporter
+
+
+@deprecated_exporter
+class AtmelStudio(Exporter):
+    NAME = 'AtmelStudio'
+    TOOLCHAIN = 'GCC_ARM'
+
+    TARGETS = [
+        'SAMD21J18A',
+        'SAMR21G18A',
+        'SAMD21G18A',
+        'SAML21J18A',
+        'SAMG55J19',
+    ]
+
+    DOT_IN_RELATIVE_PATH = True
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    @classmethod
+    def is_target_supported(cls, maybe_supported):
+        return maybe_supported in cls.TARGETS
+
+    def generate(self):
+
+        source_files = []
+        dirs = []
+        for r_type in ['s_sources', 'c_sources', 'cpp_sources']:
+            r = getattr(self.resources, r_type)
+            if r:
+                for source in r:
+                    source_files.append(source[2:])
+                    dirs.append(dirname(source[2:]))
+
+        source_folders = []
+        for e in dirs:
+            if e and e not in source_folders:
+                source_folders.append(e)
+
+        libraries = []
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            libraries.append(l[3:])
+		
+        solution_uuid = '{' + str(uuid.uuid4()) + '}'
+        project_uuid = '{' + str(uuid.uuid4()) + '}'
+
+        ctx = {
+            'target': self.target,
+            'name': self.project_name,
+            'source_files': source_files,
+            'source_folders': source_folders,
+            'object_files': self.resources.objects,
+            'include_paths': self.resources.inc_dirs,
+            'library_paths': self.resources.lib_dirs,
+            'linker_script': self.resources.linker_script,
+            'libraries': libraries,
+            'symbols': self.toolchain.get_symbols(),
+            'solution_uuid': solution_uuid.upper(),
+            'project_uuid': project_uuid.upper()
+        }
+        ctx.update(self.flags)
+        target = self.target.lower()
+        self.gen_file('atmelstudio/atsln.tmpl', ctx, '%s.atsln' % self.project_name)
+        self.gen_file('atmelstudio/cppproj.tmpl', ctx, '%s.cppproj' % self.project_name)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/__init__.pyc
new file mode 100755
index 0000000..8305966
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/atsln.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/atsln.tmpl
new file mode 100755
index 0000000..3c8ea50
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/atsln.tmpl
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Atmel Studio Solution File, Format Version 11.00
+Project("{{solution_uuid}}") = "{{name}}", "{{name}}.cppproj", "{{project_uuid}}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{{project_uuid}}.Debug|ARM.ActiveCfg = Debug|ARM
+		{{project_uuid}}.Debug|ARM.Build.0 = Debug|ARM
+		{{project_uuid}}.Release|ARM.ActiveCfg = Release|ARM
+		{{project_uuid}}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/cppproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/cppproj.tmpl
new file mode 100755
index 0000000..8af3212
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/atmelstudio/cppproj.tmpl
@@ -0,0 +1,176 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>6.2</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{{project_uuid}}</ProjectGuid>
+    <avrdevice>AT{{target}}</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>AtmelStudio6_2</AssemblyName>
+    <Name>AtmelStudio6_2</Name>
+    <RootNamespace>AtmelStudio6_2</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress />
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue />
+    <BootSegment>2</BootSegment>
+    <eraseonlaunchrule>1</eraseonlaunchrule>
+    <AsfFrameworkConfig>
+      <framework-data xmlns="">
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+</framework-data>
+    </AsfFrameworkConfig>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+      {% for s in symbols %}<Value>{{s}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      {% for i in include_paths %}<Value>../{{i}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>{{c_flags|join(" ")}} {{common_flags|join(" ")}} -MMD -MP</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+      {% for s in symbols %}<Value>{{s}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      {% for i in include_paths %}<Value>../{{i}}</Value> 
+      {% endfor %}
+   </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize for size (-Os)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>{{cxx_flags|join(" ")}} {{common_flags|join(" ")}} -MMD -MP</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.miscellaneous.LinkerFlags>{% for p in library_paths %}-L../{{p}} {% endfor %} {% for f in object_files %}../{{f}} {% endfor %} {% for lib in libraries %}-l{{lib}} {% endfor %} -T../{{linker_script}} {{ld_flags|join(" ")}} {{common_flags|join(" ")}}</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      {% for i in include_paths %}<Value>../{{i}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+</ArmGccCpp>
+    </ToolchainSettings>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+      {% for s in symbols %}<Value>{{s}}</Value>
+      {% endfor %}
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      {% for i in include_paths %}<Value>../{{i}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize (-O1)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>{{c_flags|join(" ")}} {{common_flags|join(" ")}} -MMD -MP</armgcc.compiler.miscellaneous.OtherFlags>    
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+      {% for s in symbols %}<Value>{{s}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      {% for i in include_paths %}<Value>../{{i}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize (-O1)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.DebugLevel>Maximum (-g3)</armgcccpp.compiler.optimization.DebugLevel>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>{{cxx_flags|join(" ")}} {{common_flags|join(" ")}} -MMD -MP</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.miscellaneous.LinkerFlags>{% for p in library_paths %}-L../{{p}} {% endfor %} {% for f in object_files %}../{{f}} {% endfor %} {% for lib in libraries %}-l{{lib}} {% endfor %} -T../{{linker_script}} {{ld_flags|join(" ")}} {{common_flags|join(" ")}}</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      {% for i in include_paths %}<Value>../{{i}}</Value> 
+      {% endfor %}
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+  </PropertyGroup>
+  <ItemGroup>
+    {% for f in source_folders %}<Folder Include="{{f}}" />
+    {% endfor %}
+    {% for s in source_files %}<Compile Include="{{s}}">
+      <SubType>compile</SubType>
+    </Compile>
+    {% endfor %}
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/.cproject.tmpl
new file mode 100755
index 0000000..53cd29c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/.cproject.tmpl
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="0.936619452">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.936619452" moduleId="org.eclipse.cdt.core.settings" name="Default">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration buildProperties="" description="" id="0.936619452" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="0.936619452." name="/" resourcePath="">
+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.957782855" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.957782855.1870418474" name=""/>
+							<builder arguments="-j" command="make" id="org.eclipse.cdt.build.core.settings.default.builder.1415080330" incrementalBuildTarget="" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.445325914" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.302788810" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1008027188" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath">
+									{% for p in include_paths %}
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/{{p}}}&quot;"/>
+								    {% endfor %}
+								</option>
+								<option id="org.eclipse.cdt.build.core.settings.holder.symbols.1670933615" superClass="org.eclipse.cdt.build.core.settings.holder.symbols" valueType="definedSymbols">
+									{% for symbol in asm_symbols %}
+                                    <listOptionValue builtIn="false" value="{{symbol}}"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.775336684" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.162714252" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1406944528" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath">
+									{% for p in include_paths %}
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/{{p}}}&quot;"/>
+								    {% endfor %}
+								</option>
+								<option id="org.eclipse.cdt.build.core.settings.holder.symbols.496389156" superClass="org.eclipse.cdt.build.core.settings.holder.symbols" valueType="definedSymbols">
+									{% for symbol in c_symbols %}
+                                    <listOptionValue builtIn="false" value="{{symbol}}"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.869095164" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.460204758" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<option id="org.eclipse.cdt.build.core.settings.holder.incpaths.867151072" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath">
+									{% for p in include_paths %}
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/{{p}}}&quot;"/>
+								    {% endfor %}
+								</option>
+								<option id="org.eclipse.cdt.build.core.settings.holder.symbols.1395532696" superClass="org.eclipse.cdt.build.core.settings.holder.symbols" valueType="definedSymbols">
+									{% for symbol in c_symbols %}
+                                    <listOptionValue builtIn="false" value="{{symbol}}"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1704200665" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}.null.1423711414" name="{{name}}"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="0.936619452">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Default">
+			<resource resourceType="PROJECT" workspacePath="/mbed-os-example-blinky"/>
+		</configuration>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/.project.tmpl
new file mode 100755
index 0000000..ce4e268
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/.project.tmpl
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/__init__.py
new file mode 100755
index 0000000..29b9fdd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/__init__.py
@@ -0,0 +1,55 @@
+import re
+
+from os.path import join, exists
+from os import makedirs
+
+from tools.export.makefile import Makefile, GccArm, Armc5, IAR
+
+class Eclipse(Makefile):
+    """Generic Eclipse project. Intended to be subclassed by classes that
+    specify a type of Makefile.
+    """
+    def generate(self):
+        """Generate Makefile, .cproject & .project Eclipse project file,
+        py_ocd_settings launch file, and software link .p2f file
+        """
+        super(Eclipse, self).generate()
+        starting_dot = re.compile(r'(^[.]/|^[.]$)')
+        ctx = {
+            'name': self.project_name,
+            'elf_location': join('BUILD',self.project_name)+'.elf',
+            'c_symbols': self.toolchain.get_symbols(),
+            'asm_symbols': self.toolchain.get_symbols(True),
+            'target': self.target,
+            'include_paths': [starting_dot.sub('%s/' % self.project_name, inc) for inc in self.resources.inc_dirs],
+            'load_exe': str(self.LOAD_EXE).lower()
+        }
+
+        if not exists(join(self.export_dir,'eclipse-extras')):
+            makedirs(join(self.export_dir,'eclipse-extras'))
+
+
+        self.gen_file('cdt/pyocd_settings.tmpl', ctx,
+                      join('eclipse-extras',
+                           '{target}_pyocd_{project}_settings.launch'.format(target=self.target,
+                                                                             project=self.project_name)))
+        self.gen_file('cdt/necessary_software.tmpl', ctx,
+                      join('eclipse-extras','necessary_software.p2f'))
+
+        self.gen_file('cdt/.cproject.tmpl', ctx, '.cproject')
+        self.gen_file('cdt/.project.tmpl', ctx, '.project')
+
+
+class EclipseGcc(Eclipse, GccArm):
+    LOAD_EXE = True
+    NAME = "Eclipse-GCC-ARM"
+
+class EclipseArmc5(Eclipse, Armc5):
+    LOAD_EXE = False
+    NAME = "Eclipse-Armc5"
+
+class EclipseIAR(Eclipse, IAR):
+    LOAD_EXE = True
+    NAME = "Eclipse-IAR"
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/__init__.pyc
new file mode 100755
index 0000000..6569338
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/necessary_software.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/necessary_software.tmpl
new file mode 100755
index 0000000..8807d07
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/necessary_software.tmpl
@@ -0,0 +1,11 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<?p2f version='1.0.0'?>
+<p2f version='1.0.0'>
+  <ius size='1'>
+    <iu id='ilg.gnuarmeclipse.debug.gdbjtag.pyocd.feature.group' name='GNU ARM C/C++ PyOCD Debugging' version='1.1.1.201606210758'>
+      <repositories size='1'>
+        <repository location='http://gnuarmeclipse.sourceforge.net/updates'/>
+      </repositories>
+    </iu>
+  </ius>
+</p2f>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/pyocd_settings.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/pyocd_settings.tmpl
new file mode 100755
index 0000000..67d0ed4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cdt/pyocd_settings.tmpl
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerBoardId" value=""/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="1000000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="${pyocd_path}/${pyocd_executable}"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerFlashFastVerify" value="false"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerHaltAtHardFault" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerOverrideTarget" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerStepIntoInterrutps" value="false"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerTargetName" value=""/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.gdbServerUseGdbSyscalls" value="false"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PyOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="{{load_exe}}"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="{{load_exe}}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="{{elf_location}}"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="{{name}}"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/{{name}}"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/__init__.py
new file mode 100755
index 0000000..2bf62ff
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/__init__.py
@@ -0,0 +1,154 @@
+import os
+from os.path import sep, join, exists
+from itertools import groupby
+from xml.etree.ElementTree import Element, tostring
+import ntpath
+import re
+import json
+
+from tools.arm_pack_manager import Cache
+from tools.targets import TARGET_MAP
+from tools.export.exporters import Exporter, TargetNotSupportedException
+
+class fileCMSIS():
+    """CMSIS file class.
+
+    Encapsulates information necessary for files in cpdsc project file"""
+    file_types = {'.cpp': 'sourceCpp', '.c': 'sourceC', '.s': 'sourceAsm',
+                  '.obj': 'object', '.o': 'object', '.lib': 'library',
+                  '.ar': 'linkerScript', '.h': 'header', '.sct': 'linkerScript'}
+
+    def __init__(self, loc, name):
+        #print loc
+        _, ext = os.path.splitext(loc)
+        self.type = self.file_types[ext.lower()]
+        self.loc = loc
+        self.name = name
+
+
+class DeviceCMSIS():
+    """CMSIS Device class
+
+    Encapsulates target information retrieved by arm-pack-manager"""
+
+    CACHE = Cache(True, False)
+    def __init__(self, target):
+        target_info = self.check_supported(target)
+        if not target_info:
+            raise TargetNotSupportedException("Target not supported in CMSIS pack")
+        self.url = target_info['pdsc_file']
+        self.pack_url, self.pack_id = ntpath.split(self.url)
+        self.dname = target_info["_cpu_name"]
+        self.core = target_info["_core"]
+        self.dfpu = target_info['processor']['fpu']
+        self.debug, self.dvendor = self.vendor_debug(target_info['vendor'])
+        self.dendian = target_info['processor'].get('endianness','Little-endian')
+        self.debug_svd = target_info.get('debug', '')
+        self.compile_header = target_info['compile']['header']
+        self.target_info = target_info
+
+    @staticmethod
+    def check_supported(target):
+        t = TARGET_MAP[target]
+        try:
+            cpu_name = t.device_name
+            target_info = DeviceCMSIS.CACHE.index[cpu_name]
+        # Target does not have device name or pdsc file
+        except:
+            try:
+                # Try to find the core as a generic CMSIS target
+                cpu_name = DeviceCMSIS.cpu_cmsis(t.core)
+                target_info = DeviceCMSIS.CACHE.index[cpu_name]
+            except:
+                return False
+        target_info["_cpu_name"] = cpu_name
+        target_info["_core"] = t.core
+        return target_info
+
+    def vendor_debug(self, vendor):
+        """Reads the vendor from a PDSC <dvendor> tag.
+        This tag contains some additional numeric information that is meaningless
+        for our purposes, so we use a regex to filter.
+
+        Positional arguments:
+        Vendor - information in <dvendor> tag scraped from ArmPackManager
+
+        Returns a tuple of (debugger, vendor)
+        """
+        reg = "([\w\s]+):?\d*?"
+        m = re.search(reg, vendor)
+        vendor_match = m.group(1) if m else None
+        debug_map ={
+            'STMicroelectronics':'ST-Link',
+            'Silicon Labs':'J-LINK',
+            'Nuvoton':'NULink'
+        }
+        return debug_map.get(vendor_match, "CMSIS-DAP"), vendor_match
+
+    @staticmethod
+    def cpu_cmsis(cpu):
+        """
+        Transforms information from targets.json to the way the generic cores are named
+        in CMSIS PDSC files.
+        Ex:
+        Cortex-M4F => ARMCM4_FP, Cortex-M0+ => ARMCM0P
+        Returns formatted CPU
+        """
+        cpu = cpu.replace("Cortex-","ARMC")
+        cpu = cpu.replace("+","P")
+        cpu = cpu.replace("F","_FP")
+        return cpu
+
+
+class CMSIS(Exporter):
+    NAME = 'cmsis'
+    TOOLCHAIN = 'ARM'
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return cls.TOOLCHAIN in target.supported_toolchains
+
+    def make_key(self, src):
+        """turn a source file into its group name"""
+        key = src.name.split(sep)[0]
+        if key == ".":
+            key = os.path.basename(os.path.realpath(self.export_dir))
+        return key
+
+    def group_project_files(self, sources, root_element):
+        """Recursively group the source files by their encompassing directory"""
+
+        data = sorted(sources, key=self.make_key)
+        for group, files in groupby(data, self.make_key):
+            new_srcs = []
+            for f in list(files):
+                spl = f.name.split(sep)
+                if len(spl) <= 2:
+                    file_element = Element('file',
+                                           attrib={
+                                               'category':f.type,
+                                               'name': f.loc})
+                    root_element.append(file_element)
+                else:
+                    f.name = os.path.join(*spl[1:])
+                    new_srcs.append(f)
+            if new_srcs:
+                group_element = Element('group',attrib={'name':group})
+                root_element.append(self.group_project_files(new_srcs,
+                                                        group_element))
+        return root_element
+
+    def generate(self):
+        srcs = self.resources.headers + self.resources.s_sources + \
+               self.resources.c_sources + self.resources.cpp_sources + \
+               self.resources.objects + self.resources.libraries + \
+               [self.resources.linker_script]
+        srcs = [fileCMSIS(src, src) for src in srcs if src]
+        ctx = {
+            'name': self.project_name,
+            'project_files': tostring(self.group_project_files(srcs, Element('files'))),
+            'device': DeviceCMSIS(self.target),
+            'date': ''
+        }
+        self.gen_file('cmsis/cpdsc.tmpl', ctx, 'project.cpdsc')
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/__init__.pyc
new file mode 100755
index 0000000..bb69223
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/cpdsc.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/cpdsc.tmpl
new file mode 100755
index 0000000..f63efe6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/cmsis/cpdsc.tmpl
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<package xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="PACK.xsd">
+  <vendor>Keil</vendor>
+  <name>{{name}}</name>
+  <description>Exported mbed project.</description>
+  <url>{{device.url}}</url>
+
+  <releases>
+    <release version="5.20.0.2">Generated</release>
+  </releases>
+  <create>
+    <project name="{{name}}" documentation="">
+      <target Dendian="{{device.dendian}}" Dfpu="{{device.dfpu}}" Dname="{{device.dname}}" Dvendor="{{device.dvendor}}">
+        <output debug="1" name="{{name}}" type="exe"/>
+        <debugProbe name="{{device.debug}}" protocol="jtag"/>
+      </target>
+      {{project_files}}
+    </project>
+  </create>
+</package>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/__init__.py
new file mode 100755
index 0000000..99a7938
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/__init__.py
@@ -0,0 +1,111 @@
+"""
+mbed SDK
+Copyright (c) 2014-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import splitext, basename
+
+from tools.export.exporters import Exporter, deprecated_exporter
+
+
+@deprecated_exporter
+class CoIDE(Exporter):
+    NAME = 'CoIDE'
+    TOOLCHAIN = 'GCC_ARM'
+
+    TARGETS = [
+        'KL25Z',
+        'KL05Z',
+        'LPC1768',
+        'ARCH_PRO',
+        'ARCH_MAX',
+        'UBLOX_C027',
+        'NUCLEO_L053R8',
+        'NUCLEO_L152RE',
+        'NUCLEO_F030R8',
+        'NUCLEO_F042K6',
+        'NUCLEO_F070RB',
+        'NUCLEO_F072RB',
+        'NUCLEO_F091RC',
+        'NUCLEO_F103RB',
+        'NUCLEO_F302R8',
+        'NUCLEO_F303K8',
+        'NUCLEO_F303RE',
+        'NUCLEO_F334R8',
+        'NUCLEO_F401RE',
+        'NUCLEO_F410RB',
+        'NUCLEO_F411RE',
+        'NUCLEO_F446RE',
+        'DISCO_L053C8',
+        'DISCO_F051R8',
+        'DISCO_F100RB',
+        'DISCO_F303VC',
+        'DISCO_F334C8',
+        'DISCO_F401VC',
+        'DISCO_F407VG',
+        'DISCO_F429ZI',
+        'MTS_MDOT_F405RG',
+        'MTS_MDOT_F411RE',
+        'MOTE_L152RC',
+        'NZ32_SC151',
+    ]
+
+    # seems like CoIDE currently supports only one type
+    FILE_TYPES = {
+        'c_sources':'1',
+        'cpp_sources':'1',
+        's_sources':'1'
+    }
+    FILE_TYPES2 = {
+        'headers':'1'
+    }
+
+    def generate(self):
+        self.resources.win_to_unix()
+        source_files = []
+        for r_type, n in CoIDE.FILE_TYPES.iteritems():
+            for file in getattr(self.resources, r_type):
+                source_files.append({
+                    'name': basename(file), 'type': n, 'path': file
+                })
+        header_files = []
+        for r_type, n in CoIDE.FILE_TYPES2.iteritems():
+            for file in getattr(self.resources, r_type):
+                header_files.append({
+                    'name': basename(file), 'type': n, 'path': file
+                })
+
+        libraries = []
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            libraries.append(l[3:])
+
+        if self.resources.linker_script is None:
+            self.resources.linker_script = ''
+            
+        ctx = {
+            'name': self.project_name,
+            'source_files': source_files,
+            'header_files': header_files,
+            'include_paths': self.resources.inc_dirs,
+            'scatter_file': self.resources.linker_script,
+            'library_paths': self.resources.lib_dirs,
+            'object_files': self.resources.objects,
+            'libraries': libraries,
+            'symbols': self.toolchain.get_symbols()
+        }
+        target = self.target.lower()
+
+        # Project file
+        self.gen_file('coide/%s.coproj.tmpl' % target, ctx, '%s.coproj' % self.project_name)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/__init__.pyc
new file mode 100755
index 0000000..54b9191
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/arch_max.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/arch_max.coproj.tmpl
new file mode 100755
index 0000000..a9824a6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/arch_max.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="344" chipName="STM32F407VG" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00100000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0001FE78" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00010000" startValue="0x10000000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="CMSIS-DAP"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_1024.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/arch_pro.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/arch_pro.coproj.tmpl
new file mode 100755
index 0000000..687d38e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/arch_pro.coproj.tmpl
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="7" manufacturerName="NXP" chipId="165" chipName="LPC1768" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="0"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="--specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %}; {% for p in library_paths %}-L{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x00000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00008000" startValue="0x10000000"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00008000" startValue="0x2007C000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="CMSIS-DAP"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="LPC17xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f051r8.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f051r8.coproj.tmpl
new file mode 100755
index 0000000..ee4100b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f051r8.coproj.tmpl
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="Release" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="249" chipName="STM32F051R8" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./STM32F05xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Target name="Debug" isCurrent="0">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="249" chipName="STM32F051R8" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./STM32F05xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f100rb.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f100rb.coproj.tmpl
new file mode 100755
index 0000000..f289ff5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f100rb.coproj.tmpl
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="Release" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="257" chipName="STM32F100RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001E30" startValue="0x200001D0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f10x_md_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Target name="Debug" isCurrent="0">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="257" chipName="STM32F100RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001E30" startValue="0x200001D0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f10x_md_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f303vc.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f303vc.coproj.tmpl
new file mode 100755
index 0000000..fbe5820
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f303vc.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="520" chipName="STM32F303VC" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00040000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00009E78" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00002000" startValue="0x10000000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f3xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f334c8.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f334c8.coproj.tmpl
new file mode 100755
index 0000000..d7dd7ec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f334c8.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F411RE" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00002E78" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00001000" startValue="0x10000000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f3xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f401vc.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f401vc.coproj.tmpl
new file mode 100755
index 0000000..8056335
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f401vc.coproj.tmpl
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="Release" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="502" chipName="STM32F401VC" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00040000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x000FE6C" startValue="0x20000194"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_256.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Target name="Debug" isCurrent="0">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="502" chipName="STM32F401VC" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00040000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x000FE6C" startValue="0x20000194"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_256.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f407vg.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f407vg.coproj.tmpl
new file mode 100755
index 0000000..fbde49a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f407vg.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="344" chipName="STM32F407VG" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00100000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0001FE78" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00010000" startValue="0x10000000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_1024.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f429zi.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f429zi.coproj.tmpl
new file mode 100755
index 0000000..cff2c62
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_f429zi.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="775" chipName="STM32F429ZI" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00200000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0002FE54" startValue="0x200001AC"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00010000" startValue="0x10000000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f4xx_2048.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_l053c8.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_l053c8.coproj.tmpl
new file mode 100755
index 0000000..8857942
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/disco_l053c8.coproj.tmpl
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="Release" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="878" chipName="STM32L053C8T6" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32l0xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Target name="Debug" isCurrent="0">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="878" chipName="STM32L053C8T6" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32l0xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/kl05z.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/kl05z.coproj.tmpl
new file mode 100755
index 0000000..3127e47
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/kl05z.coproj.tmpl
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="4" manufacturerName="Freescale" chipId="49" chipName="MKL05Z32VFM4" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="0"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="--specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x00000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001000" startValue="0x1FFFF000"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="CMSIS-DAP"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="KLxx_32_PRG_NO_CFG.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/kl25z.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/kl25z.coproj.tmpl
new file mode 100755
index 0000000..7a9b745
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/kl25z.coproj.tmpl
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="4" manufacturerName="Freescale" chipId="86" chipName="MKL25Z128VLK4" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="0"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="--specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x00000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001000" startValue="0x1FFFF000"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="CMSIS-DAP"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="KLxx_128_PRG_NO_CFG.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/lpc1768.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/lpc1768.coproj.tmpl
new file mode 100755
index 0000000..687d38e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/lpc1768.coproj.tmpl
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="7" manufacturerName="NXP" chipId="165" chipName="LPC1768" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="0"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="--specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %}; {% for p in library_paths %}-L{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x00000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00008000" startValue="0x10000000"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00008000" startValue="0x2007C000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="CMSIS-DAP"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="LPC17xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mote_l152rc.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mote_l152rc.coproj.tmpl
new file mode 100755
index 0000000..91ec35e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mote_l152rc.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 2.0.1" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="932" chipName="STM32L152RCT6" boardId="" boardName="" coreId="3" coreName="Cortex M3"/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00040000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00007EC4" startValue="0x2000013C"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32l1xx_256.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mts_mdot_f405rg.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mts_mdot_f405rg.coproj.tmpl
new file mode 100755
index 0000000..a73727f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mts_mdot_f405rg.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.7" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="342" chipName="STM32F405RG" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="0"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="--specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00100000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0001FF44" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00010000" startValue="0x10000000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="STM32F4xx_1024.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mts_mdot_f411re.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mts_mdot_f411re.coproj.tmpl
new file mode 100755
index 0000000..adcd169
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/mts_mdot_f411re.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.7" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F411RE" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="0"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="--specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0001FE68" startValue="0x20000198"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f030r8.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f030r8.coproj.tmpl
new file mode 100755
index 0000000..f6e121f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f030r8.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="438" chipName="STM32F030R8T6" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f05xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f042k6.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f042k6.coproj.tmpl
new file mode 100755
index 0000000..8d150d0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f042k6.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="577" chipName="STM32F042K6" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00007FFF" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001740" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f05xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f070rb.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f070rb.coproj.tmpl
new file mode 100755
index 0000000..9756fd2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f070rb.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="480" chipName="STM32F070RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00003F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f07xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f072rb.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f072rb.coproj.tmpl
new file mode 100755
index 0000000..3687c43
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f072rb.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="480" chipName="STM32F072RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00003F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f07xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f091rc.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f091rc.coproj.tmpl
new file mode 100755
index 0000000..e77d738
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f091rc.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="847" chipName="STM32F091RC" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00040000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00007F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f09x_256.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f103rb.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f103rb.coproj.tmpl
new file mode 100755
index 0000000..ce2c8fd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f103rb.coproj.tmpl
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="Release" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="310" chipName="STM32F103RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00004F14" startValue="0x200000EC"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./STM32F10x_MD_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Target name="Debug" isCurrent="0">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="310" chipName="STM32F103RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00004F14" startValue="0x200000EC"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./STM32F10x_MD_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f302r8.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f302r8.coproj.tmpl
new file mode 100755
index 0000000..56d6cc7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f302r8.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="511" chipName="STM32F302RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00003E78" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f3xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f303re.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f303re.coproj.tmpl
new file mode 100755
index 0000000..0995181
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f303re.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="517" chipName="STM32F303RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00003E78" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f3xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f334r8.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f334r8.coproj.tmpl
new file mode 100755
index 0000000..d7dd7ec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f334r8.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F411RE" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00002E78" startValue="0x20000188"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00001000" startValue="0x10000000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f3xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f401re.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f401re.coproj.tmpl
new file mode 100755
index 0000000..ffc886f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f401re.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F401RE" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00017E6C" startValue="0x20000194"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f410rb.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f410rb.coproj.tmpl
new file mode 100755
index 0000000..92f3917
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f410rb.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F410RB" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00020000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00007E38" startValue="0x200001C8"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_128.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f411re.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f411re.coproj.tmpl
new file mode 100755
index 0000000..fb222fb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f411re.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F411RE" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0001FE68" startValue="0x20000198"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f446re.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f446re.coproj.tmpl
new file mode 100755
index 0000000..91bbd30
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_f446re.coproj.tmpl
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="Debug" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F446RE" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0001FE68" startValue="0x20000198"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Target name="Release" isCurrent="0">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F446RE" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x0001FE68" startValue="0x20000198"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_l053r8.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_l053r8.coproj.tmpl
new file mode 100755
index 0000000..fd18d26
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_l053r8.coproj.tmpl
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="Release" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="882" chipName="STM32L053R8T6" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32l0xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Target name="Debug" isCurrent="0">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="882" chipName="STM32L053R8T6" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="0"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00010000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00001F40" startValue="0x200000C0"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32l0xx_64.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_l152re.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_l152re.coproj.tmpl
new file mode 100755
index 0000000..cb98166
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nucleo_l152re.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="561" chipName="STM32L152RD" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00013EC4" startValue="0x2000013C"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32l1xx_384.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nz32_sc151.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nz32_sc151.coproj.tmpl
new file mode 100755
index 0000000..7341c95
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/nz32_sc151.coproj.tmpl
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="9" manufacturerName="ST" chipId="546" chipName="STM32L151RC" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Option name="FPU" value="1"/>
+        <Option name="SupportCPlusplus" value="1"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="1"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00040000" startValue="0x08000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00007EC4" startValue="0x2000013C"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32l1xx_384.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/ublox_c027.coproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/ublox_c027.coproj.tmpl
new file mode 100755
index 0000000..687d38e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/coide/ublox_c027.coproj.tmpl
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project version="2G - 1.7.5" name="{{name}}">
+  <Target name="{{name}}" isCurrent="1">
+    <Device manufacturerId="7" manufacturerName="NXP" chipId="165" chipName="LPC1768" boardId="" boardName=""/>
+    <BuildOption>
+      <Compile>
+        <Option name="OptimizationLevel" value="4"/>
+        <Option name="UseFPU" value="0"/>
+        <Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
+        <Includepaths>
+          {% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
+        </Includepaths>
+        <DefinedSymbols>
+          {% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
+        </DefinedSymbols>
+      </Compile>
+      <Link useDefault="0">
+        <Option name="DiscardUnusedSection" value="0"/>
+        <Option name="UserEditLinkder" value=""/>
+        <Option name="UseMemoryLayout" value="0"/>
+        <Option name="LTO" value="0"/>
+        <Option name="IsNewStartupCode" value="1"/>
+        <Option name="Library" value="Not use C Library"/>
+        <Option name="nostartfiles" value="0"/>
+        <Option name="UserEditLinker" value="--specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
+        ${project.path}/{{file}}; {% endfor %}; {% for p in library_paths %}-L{{p}}; {% endfor %}"/>
+        <LinkedLibraries>
+          {% for lib in libraries %}
+          <Libset dir="" libs="{{lib}}"/>
+          {% endfor %}
+          <Libset dir="" libs="stdc++"/>
+          <Libset dir="" libs="supc++"/>
+          <Libset dir="" libs="m"/>
+          <Libset dir="" libs="gcc"/>
+          <Libset dir="" libs="c"/>
+          <Libset dir="" libs="nosys"/>
+        </LinkedLibraries>
+        <MemoryAreas debugInFlashNotRAM="1">
+          <Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x00000000"/>
+          <Memory name="IRAM1" type="ReadWrite" size="0x00008000" startValue="0x10000000"/>
+          <Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
+          <Memory name="IRAM2" type="ReadWrite" size="0x00008000" startValue="0x2007C000"/>
+        </MemoryAreas>
+        <LocateLinkFile path="{{scatter_file}}" type="0"/>
+      </Link>
+      <Output>
+        <Option name="OutputFileType" value="0"/>
+        <Option name="Path" value="./"/>
+        <Option name="Name" value="{{name}}"/>
+        <Option name="HEX" value="1"/>
+        <Option name="BIN" value="1"/>
+      </Output>
+      <User>
+        <UserRun name="Run#1" type="Before" checked="0" value=""/>
+        <UserRun name="Run#1" type="After" checked="0" value=""/>
+      </User>
+    </BuildOption>
+    <DebugOption>
+      <Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="CMSIS-DAP"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
+      <Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
+      <Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="LPC17xx_512.elf"/>
+    </DebugOption>
+    <ExcludeFile/>
+  </Target>
+  <Components path="./"/>
+  <Files>
+    {% for file in source_files %}
+    <File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+    {% for file in header_files %}
+    <File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
+    {% endfor %}
+  </Files>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/__init__.py
new file mode 100755
index 0000000..377f4fe
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/__init__.py
@@ -0,0 +1,71 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import basename
+
+from tools.export.exporters import Exporter
+
+
+class DS5_5(Exporter):
+    NAME = 'DS5'
+
+    TARGETS = [
+        'LPC1768',
+        'LPC11U24',
+        'LPC812',
+        'UBLOX_C027',
+        'ARCH_PRO',
+        'RZ_A1H',
+        'VK_RZ_A1H',
+    ]
+
+    USING_MICROLIB = [
+        'LPC812',
+    ]
+
+    FILE_TYPES = {
+        'c_sources':'1',
+        'cpp_sources':'8',
+        's_sources':'2'
+    }
+
+    TOOLCHAIN = "ARM"
+
+    def get_toolchain(self):
+        return 'uARM' if (self.target in self.USING_MICROLIB) else 'ARM'
+
+    def generate(self):
+        source_files = []
+        for r_type, n in DS5_5.FILE_TYPES.iteritems():
+            for file in getattr(self.resources, r_type):
+                source_files.append({
+                    'name': basename(file), 'type': n, 'path': file
+                })
+
+        ctx = {
+            'name': self.project_name,
+            'include_paths': self.resources.inc_dirs,
+            'scatter_file': self.resources.linker_script,
+            'object_files': self.resources.objects + self.resources.libraries,
+            'source_files': source_files,
+            'symbols': self.toolchain.get_symbols()
+        }
+        target = self.target.lower()
+
+        # Project file
+        self.gen_file('ds5_5/%s.project.tmpl' % target, ctx, '.project')
+        self.gen_file('ds5_5/%s.cproject.tmpl' % target, ctx, '.cproject')
+        self.gen_file('ds5_5/%s.launch.tmpl' % target, ctx, 'ds5_%s.launch' % target)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/__init__.pyc
new file mode 100755
index 0000000..2e2a870
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.cproject.tmpl
new file mode 100755
index 0000000..5a5fff4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.cproject.tmpl
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.debug.1293445387" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576..2093450286" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_lpc1768/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.2019880438" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.518028859" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.incpath.337015821" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1479931161" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-M3" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.defmac.278202630" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+                                {% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+								{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.982666453" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1990808204" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1188306347" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1673465082" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-M3" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-M3" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+    								{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.731120140" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.751106089">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.751106089." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.531116686" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.751106089..723232367" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_lpc1768/Release}" id="com.arm.toolchain.baremetal.builder.2017314066" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.920331842" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.487140164" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<option id="com.arm.tool.c.compiler.option.defmac.813110551" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+									{% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.79502875" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.192669519" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1423278729" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.1149702455" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.2130902749" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.710017326" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="ds5_lpc1768.com.arm.eclipse.build.project.baremetal.exe.579849103" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/ds5_lpc1768"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.cpp.compiler.input.1990808204">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.c.compiler.input.982666453">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.launch.tmpl
new file mode 100755
index 0000000..74bc964
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.launch.tmpl
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_lpc1768/Build/ds5_lpc1768.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-M3 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC1768"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.project.tmpl
new file mode 100755
index 0000000..4f892f3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/arch_pro.project.tmpl
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_lpc1768</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_lpc1768/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.cproject.tmpl
new file mode 100755
index 0000000..32adc51
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.cproject.tmpl
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator;com.arm.eclipse.builder.armcc.error" id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postannouncebuildStep="" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;" preannouncebuildStep="" prebuildStep="">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777." name="/" resourcePath="">
+						<toolChain errorParsers="com.arm.eclipse.builder.armcc.error" id="com.arm.toolchain.baremetal.exe.debug.1781361929" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform binaryParser="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777..1121504975" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_lpc11u24/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.1955892657" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.1694050615" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool command="armcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="" id="com.arm.tool.cpp.compiler.baremetal.exe.debug.1642314243" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.targetcpu.235324898" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-M0" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.incpath.1328570024" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.51293980" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.2068563074" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool command="armasm" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="" id="com.arm.tool.assembler.1597855725" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1268314117" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-M0" valueType="string"/>
+							</tool>
+							<tool command="armlink" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="" id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-M0" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+									{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.1693045804" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.855323040" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027..61103736" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_lpc11u24/Release}" id="com.arm.toolchain.baremetal.builder.155956859" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.8403098" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.724046879" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<inputType id="com.arm.tool.c.compiler.input.2054513225" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1205595081" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1688115594" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.901819873" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.730137058" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.1880062119" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="test.com.arm.eclipse.build.project.baremetal.exe.683746772" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777;com.arm.eclipse.build.config.baremetal.exe.debug.1914396777.;com.arm.tool.cpp.compiler.baremetal.exe.debug.1642314243;com.arm.tool.cpp.compiler.input.2068563074">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777;com.arm.eclipse.build.config.baremetal.exe.debug.1914396777.;com.arm.tool.cpp.compiler.baremetal.exe.debug.1642314243;com.arm.tool.c.compiler.input.51293980">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.launch.tmpl
new file mode 100755
index 0000000..868cba3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.launch.tmpl
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_lpc11u24/Build/ds5_lpc11u24.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-M0 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC11U24"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.project.tmpl
new file mode 100755
index 0000000..8ad8f0a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc11u24.project.tmpl
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_lpc11u24</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_lpc11u24/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.cproject.tmpl
new file mode 100755
index 0000000..5a5fff4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.cproject.tmpl
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.debug.1293445387" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576..2093450286" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_lpc1768/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.2019880438" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.518028859" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.incpath.337015821" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1479931161" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-M3" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.defmac.278202630" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+                                {% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+								{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.982666453" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1990808204" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1188306347" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1673465082" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-M3" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-M3" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+    								{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.731120140" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.751106089">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.751106089." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.531116686" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.751106089..723232367" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_lpc1768/Release}" id="com.arm.toolchain.baremetal.builder.2017314066" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.920331842" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.487140164" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<option id="com.arm.tool.c.compiler.option.defmac.813110551" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+									{% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.79502875" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.192669519" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1423278729" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.1149702455" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.2130902749" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.710017326" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="ds5_lpc1768.com.arm.eclipse.build.project.baremetal.exe.579849103" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/ds5_lpc1768"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.cpp.compiler.input.1990808204">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.c.compiler.input.982666453">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.launch.tmpl
new file mode 100755
index 0000000..74bc964
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.launch.tmpl
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_lpc1768/Build/ds5_lpc1768.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-M3 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC1768"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.project.tmpl
new file mode 100755
index 0000000..4f892f3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc1768.project.tmpl
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_lpc1768</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_lpc1768/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.cproject.tmpl
new file mode 100755
index 0000000..96f0dc9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.cproject.tmpl
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator;com.arm.eclipse.builder.armcc.error" id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postannouncebuildStep="" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;" preannouncebuildStep="" prebuildStep="">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777." name="/" resourcePath="">
+						<toolChain errorParsers="com.arm.eclipse.builder.armcc.error" id="com.arm.toolchain.baremetal.exe.debug.1781361929" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform binaryParser="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777..1121504975" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_lpc812/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.1955892657" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.1694050615" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool command="armcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="" id="com.arm.tool.cpp.compiler.baremetal.exe.debug.1642314243" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.targetcpu.235324898" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-M0" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.incpath.1328570024" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.51293980" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.2068563074" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool command="armasm" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="" id="com.arm.tool.assembler.1597855725" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1268314117" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-M0" valueType="string"/>
+							</tool>
+							<tool command="armlink" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="" id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-M0" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+									{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.1693045804" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.855323040" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.1532514027..61103736" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_lpc812/Release}" id="com.arm.toolchain.baremetal.builder.155956859" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.8403098" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.724046879" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<inputType id="com.arm.tool.c.compiler.input.2054513225" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1205595081" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1688115594" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.901819873" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.730137058" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.1880062119" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="test.com.arm.eclipse.build.project.baremetal.exe.683746772" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777;com.arm.eclipse.build.config.baremetal.exe.debug.1914396777.;com.arm.tool.cpp.compiler.baremetal.exe.debug.1642314243;com.arm.tool.cpp.compiler.input.2068563074">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1914396777;com.arm.eclipse.build.config.baremetal.exe.debug.1914396777.;com.arm.tool.cpp.compiler.baremetal.exe.debug.1642314243;com.arm.tool.c.compiler.input.51293980">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.launch.tmpl
new file mode 100755
index 0000000..57ab0ba
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.launch.tmpl
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_lpc812/Build/ds5_lpc812.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-M0 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC812"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.project.tmpl
new file mode 100755
index 0000000..2e9c358
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/lpc812.project.tmpl
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_lpc812</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_lpc812/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.cproject.tmpl
new file mode 100755
index 0000000..44e66ca
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.cproject.tmpl
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.debug.1293445387" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576..2093450286" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_rz_a1h/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.2019880438" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.518028859" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.incpath.337015821" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1479931161" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-A9" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.defmac.278202630" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+                                {% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+								{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.982666453" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1990808204" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1188306347" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1673465082" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-A9" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-A9" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+    								{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.731120140" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.751106089">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.751106089." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.531116686" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.751106089..723232367" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_rz_a1h/Release}" id="com.arm.toolchain.baremetal.builder.2017314066" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.920331842" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.487140164" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<option id="com.arm.tool.c.compiler.option.defmac.813110551" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+									{% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.79502875" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.192669519" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1423278729" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.1149702455" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.2130902749" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.710017326" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="ds5_rz_a1h.com.arm.eclipse.build.project.baremetal.exe.579849103" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/ds5_rz_a1h"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.cpp.compiler.input.1990808204">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.c.compiler.input.982666453">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.launch.tmpl
new file mode 100755
index 0000000..a4bee75
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.launch.tmpl
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_rz_a1h/Build/ds5_rz_a1h.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-A9 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC1768"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.project.tmpl
new file mode 100755
index 0000000..eee5209
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/rz_a1h.project.tmpl
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_rz_a1h</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_rz_a1h/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.cproject.tmpl
new file mode 100755
index 0000000..5a5fff4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.cproject.tmpl
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.debug.1293445387" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576..2093450286" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_lpc1768/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.2019880438" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.518028859" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.incpath.337015821" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1479931161" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-M3" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.defmac.278202630" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+                                {% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+								{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.982666453" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1990808204" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1188306347" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1673465082" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-M3" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-M3" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+    								{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.731120140" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.751106089">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.751106089." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.531116686" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.751106089..723232367" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_lpc1768/Release}" id="com.arm.toolchain.baremetal.builder.2017314066" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.920331842" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.487140164" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<option id="com.arm.tool.c.compiler.option.defmac.813110551" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+									{% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.79502875" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.192669519" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1423278729" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.1149702455" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.2130902749" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.710017326" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="ds5_lpc1768.com.arm.eclipse.build.project.baremetal.exe.579849103" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/ds5_lpc1768"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.cpp.compiler.input.1990808204">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.c.compiler.input.982666453">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.launch.tmpl
new file mode 100755
index 0000000..74bc964
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.launch.tmpl
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_lpc1768/Build/ds5_lpc1768.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-M3 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC1768"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.project.tmpl
new file mode 100755
index 0000000..4f892f3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/ublox_c027.project.tmpl
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_lpc1768</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_lpc1768/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.cproject.tmpl
new file mode 100755
index 0000000..04a6254
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.cproject.tmpl
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.debug.1293445387" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576..2093450286" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_vk_rz_a1h/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.2019880438" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.518028859" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.incpath.337015821" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1479931161" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-A9" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.defmac.278202630" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+                                {% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+								{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.982666453" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1990808204" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1188306347" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1673465082" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-A9" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-A9" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+    								{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.731120140" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.751106089">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.751106089." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.531116686" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.751106089..723232367" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_vk_rz_a1h/Release}" id="com.arm.toolchain.baremetal.builder.2017314066" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.920331842" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.487140164" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<option id="com.arm.tool.c.compiler.option.defmac.813110551" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+									{% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.79502875" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.192669519" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1423278729" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.1149702455" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.2130902749" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.710017326" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="ds5_vk_rz_a1h.com.arm.eclipse.build.project.baremetal.exe.579849103" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/ds5_vk_rz_a1h"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.cpp.compiler.input.1990808204">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.c.compiler.input.982666453">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.launch.tmpl
new file mode 100755
index 0000000..4978e95
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.launch.tmpl
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_vk_rz_a1h/Build/ds5_vk_rz_a1h.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-A9 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC1768"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.project.tmpl
new file mode 100755
index 0000000..ad56948
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/ds5_5/vk_rz_a1h.project.tmpl
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_vk_rz_a1h</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_vk_rz_a1h/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/.cproject.tmpl
new file mode 100755
index 0000000..d873230
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/.cproject.tmpl
@@ -0,0 +1,414 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+<!-- Generated by the GNU ARM Eclipse exporter from an mBed project. -->
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}
+		<cconfiguration id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}" moduleId="org.eclipse.cdt.core.settings" name="{{opts['name']}}">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.{{opts['parent_id']}}" cleanCommand="${cross_rm} -rf" description="" id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}" name="{{opts['name']}}" parent="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['parent_id']}}">
+					<folderInfo id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}." name="/" resourcePath="">
+						<toolChain id="com.renesas.cdt.managedbuild.gnuarm.toolchain.elf.{{opts['id']}}.{{u.id}}" name="GCC ARM Embedded" superClass="com.renesas.cdt.managedbuild.gnuarm.toolchain.elf.{{opts['parent_id']}}">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.{{u.id}}" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.{{opts['common']['arm.target.family']}}" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.{{opts['common']['arm.target.arch']}}" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.{{u.id}}" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.{{opts['common']['arm.target.instructionset']}}" valueType="enumerated"/>
+							{% if opts['common']['arm.target.thumbinterwork'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.thumbinterwork.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.thumbinterwork" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['arm.target.endianness'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness.{{opts['common']['arm.target.endianness']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.abi'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.{{u.id}}" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.{{opts['common']['arm.target.fpu.abi']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.unit'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.{{u.id}}" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.{{opts['common']['arm.target.fpu.unit']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.unalignedaccess'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess.{{opts['common']['arm.target.unalignedaccess']}}" valueType="enumerated"/>
+							{% endif %}
+
+							{% if opts['common']['optimization.level'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.{{opts['common']['optimization.level']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['optimization.messagelength'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.{{u.id}}" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.signedchar'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.{{u.id}}" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.functionsections'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.{{u.id}}" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.datasections'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.{{u.id}}" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nocommon'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nocommon.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nocommon" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.noinlinefunctions'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.noinlinefunctions.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.noinlinefunctions" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.freestanding'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nobuiltin'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.spconstant'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.spconstant.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.spconstant" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.PIC'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.PIC.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.PIC" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nomoveloopinvariants'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants.{{u.id}}" name="Disable loop invariant move (-fno-move-loop-invariants)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.other'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.other" value="{{opts['common']['optimization.other']}}" valueType="string"/>
+							{% endif %}
+
+							{% if opts['common']['warnings.syntaxonly'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.syntaxonly.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.syntaxonly" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pedantic'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedantic.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedantic" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pedanticerrors'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedanticerrors.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedanticerrors" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.nowarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.nowarn.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.nowarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.unused'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.unused.{{u.id}}" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.unused" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.uninitialized'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.uninitialized.{{u.id}}" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.uninitialized" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.allwarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.{{u.id}}" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.extrawarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn.{{u.id}}" name="Enable extra warnings (-Wextra)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.missingdeclaration'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.missingdeclaration.{{u.id}}" name="Warn on undeclared global function (-Wmissing-declaration)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.missingdeclaration" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.conversion'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.conversion.{{u.id}}" name="Warn on implicit conversions (-Wconversion)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.conversion" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pointerarith'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pointerarith.{{u.id}}" name="Warn if pointer arithmetic (-Wpointer-arith)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pointerarith" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.padded'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.padded.{{u.id}}" name="Warn if padding is included (-Wpadded)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.padded" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.shadow'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.shadow.{{u.id}}" name="Warn if shadowed variable (-Wshadow)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.shadow" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.logicalop'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.logicalop.{{u.id}}" name="Warn if suspicious logical ops (-Wlogical-op)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.logicalop" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.agreggatereturn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.agreggatereturn.{{u.id}}" name="Warn if struct is returned (-Wagreggate-return)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.agreggatereturn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.floatequal'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.floatequal.{{u.id}}" name="Warn if floats are compared as equal (-Wfloat-equal)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.floatequal" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.toerrors'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.toerrors.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.toerrors" value="true" valueType="boolean"/>
+							{% endif %}
+							
+							{% if opts['common']['warnings.other'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.other" value="{{opts['common']['warnings.other']}}" valueType="string"/>
+							{% endif %}
+
+							{% if opts['common']['debugging.level'] != 'none' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.{{u.id}}" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.{{opts['common']['debugging.level']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['debugging.format'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.{{u.id}}" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.{{opts['common']['debugging.format']}}"  valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['debugging.prof'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['debugging.gprof'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="true" valueType="boolean"/>
+							{% endif %}
+
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.{{u.id}}" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.{{u.id}}" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.{{u.id}}" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.{{u.id}}" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.{{u.id}}" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.{{u.id}}" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.{{u.id}}" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.{{u.id}}" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.{{u.id}}" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.{{u.id}}" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.{{u.id}}" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.{{u.id}}" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/{{name}}}/BUILD/{{opts['name']}}" cleanBuildTarget="mbedclean" id="ilg.gnuarmeclipse.managedbuild.cross.builder.{{u.id}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.{{u.id}}" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								{% if opts['as']['usepreprocessor'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.{{u.id}}" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['as']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['as']['defines'] %}
+									<listOptionValue builtIn="false" value='{{s|replace("\"", "\\\"")|escape}}' />
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.files.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['as']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.otherwarnings.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.otherwarnings" value="{{opts['as']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['as']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['as']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other.{{u.id}}" name="Other assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other" value="{{opts['as']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.{{opts['uid']['tool_c_compiler']}}" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								{% if opts['c']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['c']['defines'] %}
+									<listOptionValue builtIn="false" value='{{s|replace("\"", "\\\"")|escape}}'/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.{{u.id}}" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['c']['compiler.std'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+								{% if opts['c']['otheroptimizations'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otheroptimizations.{{u.id}}" name="Other optimization flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otheroptimizations" useByScannerDiscovery="true" value="{{opts['c']['otheroptimizations']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['warnings.missingprototypes'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.missingprototypes.{{u.id}}" name="Warn if a global function has no prototype (-Wmissing-prototypes)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.missingprototypes" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['warnings.strictprototypes'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.strictprototypes.{{u.id}}" name="Warn if a function has no arg type (-Wstrict-prototypes)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.strictprototypes" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['warnings.badfunctioncast'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.badfunctioncast.{{u.id}}" name="Warn if wrong cast  (-Wbad-function-cast)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.badfunctioncast" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otherwarnings.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otherwarnings" value="{{opts['c']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" value="{{opts['c']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.{{opts['uid']['tool_c_compiler_input']}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}}" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								{% if opts['cpp']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['nostdincpp'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdincpp.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdincpp" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['cpp']['defines'] %}
+									<listOptionValue builtIn="false" value='{{s|replace("\"", "\\\"")|escape}}'/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.{{u.id}}" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['cpp']['compiler.std'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.{{opts['cpp']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+
+								{% if opts['cpp']['optimization.noexceptions'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.{{u.id}}" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nortti'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.{{u.id}}" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nousecxaatexit'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit.{{u.id}}" name="Do not use _cxa_atexit() (-fno-use-cxa-atexit)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nothreadsafestatics'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics.{{u.id}}" name="Do not use thread-safe statics (-fno-threadsafe-statics)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['otheroptimizations'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otheroptimizations.{{u.id}}" name="Other optimization flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otheroptimizations" useByScannerDiscovery="true" value="{{opts['cpp']['otheroptimizations']}}" valueType="string"/>
+								{% endif %}
+
+								{% if opts['cpp']['warnabi'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warnabi.{{u.id}}" name="Warn on ABI violations (-Wabi)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warnabi" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.ctordtorprivacy'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.ctordtorprivacy.{{u.id}}" name="Warn on class privacy (-Wctor-dtor-privacy)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.ctordtorprivacy" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.noexcept'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.noexcept.{{u.id}}" name="Warn on no-except expressions (-Wnoexcept)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.noexcept" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.nonvirtualdtor'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.nonvirtualdtor.{{u.id}}" name="Warn on virtual destructors (-Wnon-virtual-dtor)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.nonvirtualdtor" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.strictnullsentinel'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.strictnullsentinel.{{u.id}}" name="Warn on uncast NULL (-Wstrict-null-sentinel)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.strictnullsentinel" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.signpromo'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.signpromo.{{u.id}}" name="Warn on sign promotion (-Wsign-promo)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.signpromo" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warneffc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warneffc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warneffc" value="true" valueType="boolean"/>
+								{% endif %}								
+								{% if opts['cpp']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otherwarnings.{{u.id}}" name="Other warning flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otherwarnings" useByScannerDiscovery="true" value="{{opts['cpp']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+
+								{% if opts['cpp']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" value="{{opts['cpp']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.{{opts['uid']['tool_cpp_compiler_input']}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.{{u.id}}" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.{{u.id}}" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{opts['ld']['script']}}&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.{{u.id}}" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+									{% for path in opts['ld']['library_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+									{% for lib in opts['ld']['user_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+									{% for lib in opts['ld']['system_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+									{% for path in opts['ld']['object_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['ld']['gcsections'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.{{u.id}}" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								{% endif %}
+
+								{% if opts['ld']['nostart'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.{{u.id}}" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nodeflibs'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nostdlibs'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.flags.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.flags" valueType="stringList">
+									{% for opt in opts['ld']['flags'] %}
+									<listOptionValue builtIn="false" value="{{opt}}"/>
+									{% endfor %}
+								</option>
+
+								{% if opts['ld']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="{{opts['ld']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.{{u.id}}" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.{{u.id}}" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.{{u.id}}" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.{{u.id}}" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.{{u.id}}" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.{{u.id}}" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.{{u.id}}" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.{{u.id}}" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.{{u.id}}" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.{{u.id}}" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="{{opts['common']['excluded_folders']}}" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}_emb.com.renesas.cdt.managedbuild.gnuarm.target.elf.{{u.id}}" name="Executable" projectType="com.renesas.cdt.managedbuild.gnuarm.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}};com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}.;com.renesas.cdt.managedbuild.gnuarm.tool.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}};com.renesas.cdt.managedbuild.gnuarm.tool.cpp.compiler.input.{{opts['uid']['tool_cpp_compiler_input']}}">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		{% endfor %}
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}};com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}.;com.renesas.cdt.managedbuild.gnuarm.tool.c.compiler.{{opts['uid']['tool_c_compiler']}};com.renesas.cdt.managedbuild.gnuarm.tool.c.compiler.input.{{opts['uid']['tool_c_compiler_input']}}">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/.gdbinit.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/.gdbinit.tmpl
new file mode 100755
index 0000000..a59f78c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/.gdbinit.tmpl
@@ -0,0 +1,29 @@
+define hook-step
+mon cortex_a maskisr on
+end
+
+define hook-stepi
+mon cortex_a maskisr on
+end
+
+define hook-next
+mon cortex_a maskisr on
+end
+
+define hook-nexti
+mon cortex_a maskisr on
+end
+
+define hook-finish
+mon cortex_a maskisr on
+end
+
+define hook-stop
+mon cortex_a maskisr off
+end
+
+define hook-kill
+mon reset init
+end
+
+set mem inaccessible-by-default off
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/__init__.py
new file mode 100755
index 0000000..dbd0ff8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/__init__.py
@@ -0,0 +1,48 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from tools.export.gnuarmeclipse import GNUARMEclipse
+
+class E2Studio(GNUARMEclipse):
+    NAME = 'e2 studio'
+    TOOLCHAIN = 'GCC_ARM'
+
+    TARGETS = [
+        'RZ_A1H',
+        'VK_RZ_A1H',
+    ]
+
+    # override
+    def generate(self):
+
+        jinja_ctx = self.collect_tmpl_vars()
+            
+        print
+        print 'Create a e2 studio C++ managed project'
+        print 'Project name: {0}'.format(self.project_name)
+        print 'Target: {0}'.format(self.toolchain.target.name)
+        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
+
+        self.gen_file('e2studio/.cproject.tmpl', jinja_ctx, '.cproject', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('e2studio/.gdbinit.tmpl', jinja_ctx, '.gdbinit')
+        self.gen_file('e2studio/launch.tmpl', jinja_ctx, '%s OpenOCD.launch' % self.project_name, trim_blocks=True, lstrip_blocks=True)
+
+        self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx, '.project', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore')
+        self.gen_file('gnuarmeclipse/makefile.targets.tmpl', jinja_ctx, 'makefile.targets', trim_blocks=True, lstrip_blocks=True)
+
+        print
+        print 'Done. Import the project located at \'{0}\' in e2 studio.'.format(self.project_name)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/__init__.pyc
new file mode 100755
index 0000000..c1a19de
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/launch.tmpl
new file mode 100755
index 0000000..2524c4d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/e2studio/launch.tmpl
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f board/renesas_gr-peach.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\{{name}}.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="{{name}}"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.renesas.cdt.managedbuild.gnuarm.toolchain.base.264627759"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/{{name}}"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/__init__.py
new file mode 100755
index 0000000..577ccec
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/__init__.py
@@ -0,0 +1,89 @@
+"""
+mbed SDK
+Copyright (c) 2014-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import splitext, basename
+from tools.targets import TARGET_MAP
+from tools.export.exporters import Exporter, apply_supported_whitelist
+
+
+POST_BINARY_WHITELIST = set([
+    "TEENSY3_1Code.binary_hook",
+    "LPCTargetCode.lpc_patch",
+    "LPC4088Code.binary_hook"
+])
+
+
+class EmBitz(Exporter):
+    NAME = 'EmBitz'
+    TOOLCHAIN = 'GCC_ARM'
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    FILE_TYPES = {
+        'headers': 'h',
+        'c_sources': 'c',
+        's_sources': 'a',
+        'cpp_sources': 'cpp'
+    }
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return apply_supported_whitelist(
+            cls.TOOLCHAIN, POST_BINARY_WHITELIST, target)
+
+    @staticmethod
+    def _remove_symbols(sym_list):
+        return [s for s in sym_list if not s.startswith("-D")]
+
+    def generate(self):
+        self.resources.win_to_unix()
+        source_files = []
+        for r_type, n in self.FILE_TYPES.iteritems():
+            for file in getattr(self.resources, r_type):
+                source_files.append({
+                    'name': file, 'type': n
+                })
+
+        libraries = []
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            libraries.append(l[3:])
+
+
+        if self.resources.linker_script is None:
+            self.resources.linker_script = ''
+
+        ctx = {
+            'name': self.project_name,
+            'target': self.target,
+            'toolchain': self.toolchain.name,
+            'source_files': source_files,
+            'include_paths': self.resources.inc_dirs,
+            'script_file': self.resources.linker_script,
+            'library_paths': self.resources.lib_dirs,
+            'libraries': libraries,
+            'symbols': self.toolchain.get_symbols(),
+            'object_files': self.resources.objects,
+            'sys_libs': self.toolchain.sys_libs,
+            'cc_org': (self.flags['common_flags'] +
+                       self._remove_symbols(self.flags['c_flags'])),
+            'ld_org': self.flags['ld_flags'],
+            'cppc_org': (self.flags['common_flags'] +
+                         self._remove_symbols(self.flags['cxx_flags']))
+        }
+
+        self.gen_file('embitz/eix.tmpl', ctx, '%s.eix' % self.project_name)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/__init__.pyc
new file mode 100755
index 0000000..da68022
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/eix.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/eix.tmpl
new file mode 100755
index 0000000..2bf5b0b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/embitz/eix.tmpl
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<Project emblocks_ix="1.0.0" name="{{name}}">
+    <Target name="{{name}}" target="{{target}}">
+        <Source name="mbed.org" version="1.0.0">
+            <Toolchain name="{{toolchain}}"/>
+            <CC>
+                {% for s in cc_org %}<Switch name="{{s}}"/>
+                {% endfor %}
+            </CC>
+            <CPPC>
+                {% for s in cppc_org %}<Switch name="{{s}}"/>
+                {% endfor %}
+            </CPPC>
+            <Symbols>
+                {% for s in symbols %}<Symbol name="{{s}}"/>
+                {% endfor %}
+            </Symbols>
+            <LD>
+                {% for s in ld_org %}<Switch name="{{s}}"/>
+                {% endfor %}
+            </LD>
+            <Addobjects>
+                {% for s in object_files %}<Addobject name="{{s}}"/>
+                {% endfor %}
+            </Addobjects>
+            <Syslibs>
+                {% for s in sys_libs %}<Library name="{{s}}"/>
+                {% endfor %}
+            </Syslibs>
+            <Scriptfile path="{{script_file}}"/>
+        </Source>
+        <Assembler>
+        </Assembler>
+        <Compiler>
+            <Includepaths>
+                {% for s in include_paths %}<Includepath path="{{s}}"/>
+                {% endfor %}
+            </Includepaths>
+            <Symbols>
+            </Symbols>
+        </Compiler>
+        <Linker>
+            <Libraries>
+                {% for s in libraries %}<Library name="{{s}}"/>
+                {% endfor %}
+            </Libraries>
+            <Librarypaths>
+                {% for s in library_paths %}<Librarypath path="{{s}}"/>
+                {% endfor %}
+            </Librarypaths>
+        </Linker>
+        <Files>
+            {% for f in source_files %}<File  name="{{f.name}}" type="{{f.type}}"/>
+            {% endfor %}
+        </Files>
+    </Target>
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/exporters.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/exporters.py
new file mode 100755
index 0000000..149bc78
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/exporters.py
@@ -0,0 +1,228 @@
+"""Just a template for subclassing"""
+import os
+from abc import abstractmethod, ABCMeta
+import logging
+from os.path import join, dirname, relpath, basename, realpath, normpath
+from itertools import groupby
+from jinja2 import FileSystemLoader, StrictUndefined
+from jinja2.environment import Environment
+import copy
+
+from tools.targets import TARGET_MAP
+
+
+class TargetNotSupportedException(Exception):
+    """Indicates that an IDE does not support a particular MCU"""
+    pass
+
+class ExporterTargetsProperty(object):
+    """ Exporter descriptor for TARGETS
+    TARGETS as class attribute for backward compatibility
+    (allows: if in Exporter.TARGETS)
+    """
+    def __init__(self, func):
+        self.func = func
+    def __get__(self, inst, cls):
+        return self.func(cls)
+
+def deprecated_exporter(CLS):
+    old_init = CLS.__init__
+    old_name = CLS.NAME
+    def __init__(*args, **kwargs):
+        print("==================== DEPRECATION NOTICE ====================")
+        print("The exporter %s is no longer maintained, and deprecated." % old_name)
+        print("%s will be removed from mbed OS for the mbed OS 5.6 release." % old_name)
+        old_init(*args, **kwargs)
+    CLS.__init__ = __init__
+    CLS.NAME = "%s (DEPRECATED)" % old_name
+    return CLS
+
+class Exporter(object):
+    """Exporter base class
+
+    This class is meant to be extended by individual exporters, and provides a
+    few helper methods for implementing an exporter with either jinja2 or
+    progen.
+    """
+    __metaclass__ = ABCMeta
+    TEMPLATE_DIR = dirname(__file__)
+    DOT_IN_RELATIVE_PATH = False
+    NAME = None
+    TARGETS = set()
+    TOOLCHAIN = None
+
+
+    def __init__(self, target, export_dir, project_name, toolchain,
+                 extra_symbols=None, resources=None):
+        """Initialize an instance of class exporter
+        Positional arguments:
+        target        - the target mcu/board for this project
+        export_dir    - the directory of the exported project files
+        project_name  - the name of the project
+        toolchain     - an instance of class toolchain
+
+        Keyword arguments:
+        extra_symbols - a list of extra macros for the toolchain
+        resources     - an instance of class Resources
+        """
+        self.export_dir = export_dir
+        self.target = target
+        self.project_name = project_name
+        self.toolchain = toolchain
+        jinja_loader = FileSystemLoader(os.path.dirname(os.path.abspath(__file__)))
+        self.jinja_environment = Environment(loader=jinja_loader)
+        self.resources = resources
+        self.generated_files = []
+        self.static_files = (
+            join(self.TEMPLATE_DIR, "GettingStarted.html"),
+            join(self.TEMPLATE_DIR, ".mbed"),
+        )
+        self.builder_files_dict = {}
+        self.add_config()
+
+    def get_toolchain(self):
+        """A helper getter function that we should probably eliminate"""
+        return self.TOOLCHAIN
+
+    def add_config(self):
+        """Add the containgin directory of mbed_config.h to include dirs"""
+        config = self.toolchain.get_config_header()
+        if config:
+            self.resources.inc_dirs.append(
+                dirname(relpath(config,
+                                self.resources.file_basepath[config])))
+
+    @property
+    def flags(self):
+        """Returns a dictionary of toolchain flags.
+        Keys of the dictionary are:
+        cxx_flags    - c++ flags
+        c_flags      - c flags
+        ld_flags     - linker flags
+        asm_flags    - assembler flags
+        common_flags - common options
+        """
+        config_header = self.toolchain.get_config_header()
+        flags = {key + "_flags": copy.deepcopy(value) for key, value
+                 in self.toolchain.flags.iteritems()}
+        asm_defines = self.toolchain.get_compile_options(
+            self.toolchain.get_symbols(for_asm=True),
+            filter(None, self.resources.inc_dirs),
+            for_asm=True)
+        c_defines = ["-D" + symbol for symbol in self.toolchain.get_symbols()]
+        flags['asm_flags'] += asm_defines
+        flags['c_flags'] += c_defines
+        flags['cxx_flags'] += c_defines
+        if config_header:
+            config_header = relpath(config_header,
+                                    self.resources.file_basepath[config_header])
+            flags['c_flags'] += self.toolchain.get_config_option(config_header)
+            flags['cxx_flags'] += self.toolchain.get_config_option(
+                config_header)
+        return flags
+
+    def get_source_paths(self):
+        """Returns a list of the directories where source files are contained"""
+        source_keys = ['s_sources', 'c_sources', 'cpp_sources', 'hex_files',
+                       'objects', 'libraries']
+        source_files = []
+        for key in source_keys:
+            source_files.extend(getattr(self.resources, key))
+        return list(set([os.path.dirname(src) for src in source_files]))
+
+    def gen_file(self, template_file, data, target_file, **kwargs):
+        """Generates a project file from a template using jinja"""
+        jinja_loader = FileSystemLoader(
+            os.path.dirname(os.path.abspath(__file__)))
+        jinja_environment = Environment(loader=jinja_loader,
+                                        undefined=StrictUndefined, **kwargs)
+
+        template = jinja_environment.get_template(template_file)
+        target_text = template.render(data)
+
+        target_path = join(self.export_dir, target_file)
+        logging.debug("Generating: %s", target_path)
+        open(target_path, "w").write(target_text)
+        self.generated_files += [target_path]
+
+    def make_key(self, src):
+        """From a source file, extract group name
+        Positional Arguments:
+        src - the src's location
+        """
+        rel_path = relpath(src, self.resources.file_basepath[src])
+        path_list = os.path.normpath(rel_path).split(os.sep)
+        assert len(path_list) >= 1
+        if len(path_list) == 1:
+            key = self.project_name
+        else:
+            key = path_list[0]
+        return key
+
+    def group_project_files(self, sources):
+        """Group the source files by their encompassing directory
+        Positional Arguments:
+        sources - array of source locations
+
+        Returns a dictionary of {group name: list of source locations}
+        """
+        data = sorted(sources, key=self.make_key)
+        return {k: list(g) for k,g in groupby(data, self.make_key)}
+
+    @staticmethod
+    def build(project_name, log_name='build_log.txt', cleanup=True):
+        """Invoke exporters build command within a subprocess.
+        This method is assumed to be executed at the same level as exporter
+        project files and project source code.
+        See uvision/__init__.py, iar/__init__.py, and makefile/__init__.py for
+        example implemenation.
+
+        Positional Arguments:
+        project_name - the name of the project to build; often required by
+        exporter's build command.
+
+        Keyword Args:
+        log_name - name of the build log to create. Written and printed out,
+        deleted if cleanup = True
+        cleanup - a boolean dictating whether exported project files and
+        build log are removed after build
+
+        Returns -1 on failure and 0 on success
+        """
+        raise NotImplemented("Implement in derived Exporter class.")
+
+    @abstractmethod
+    def generate(self):
+        """Generate an IDE/tool specific project file"""
+        raise NotImplemented("Implement a generate function in Exporter child class")
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        """Query support for a particular target
+
+        NOTE: override this method if your exporter does not provide a static list of targets
+
+        Positional Arguments:
+        target_name - the name of the target.
+        """
+        target = TARGET_MAP[target_name]
+        return bool(set(target.resolution_order_names).intersection(set(cls.TARGETS))) \
+            and cls.TOOLCHAIN in target.supported_toolchains
+
+
+    @classmethod
+    def all_supported_targets(cls):
+        return [t for t in TARGET_MAP.keys() if cls.is_target_supported(t)]
+
+
+def apply_supported_whitelist(compiler, whitelist, target):
+    """Generate a list of supported targets for a given compiler and post-binary hook
+    white-list."""
+    if compiler not in target.supported_toolchains:
+        return False
+    if not hasattr(target, "post_binary_hook"):
+        return True
+    if target.post_binary_hook['function'] in whitelist:
+        return True
+    else:
+        return False
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/exporters.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/exporters.pyc
new file mode 100755
index 0000000..9a537c0
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/exporters.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/.cproject.tmpl
new file mode 100755
index 0000000..721e261
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/.cproject.tmpl
@@ -0,0 +1,414 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+<!-- Generated by the GNU ARM Eclipse exporter from an mBed project. -->
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}}">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}}" moduleId="org.eclipse.cdt.core.settings" name="{{opts['name']}}">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.{{opts['parent_id']}}" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}}" name="{{opts['name']}}" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['parent_id']}}">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}}." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.{{opts['id']}}.{{u.id}}" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.{{opts['parent_id']}}">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.{{u.id}}" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.{{opts['common']['arm.target.family']}}" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.{{opts['common']['arm.target.arch']}}" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.{{u.id}}" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.{{opts['common']['arm.target.instructionset']}}" valueType="enumerated"/>
+							{% if opts['common']['arm.target.thumbinterwork'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.thumbinterwork.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.thumbinterwork" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['arm.target.endianness'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness.{{opts['common']['arm.target.endianness']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.abi'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.{{u.id}}" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.{{opts['common']['arm.target.fpu.abi']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.unit'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.{{u.id}}" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.{{opts['common']['arm.target.fpu.unit']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.unalignedaccess'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess.{{opts['common']['arm.target.unalignedaccess']}}" valueType="enumerated"/>
+							{% endif %}
+
+							{% if opts['common']['optimization.level'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.{{opts['common']['optimization.level']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['optimization.messagelength'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.{{u.id}}" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.signedchar'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.{{u.id}}" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.functionsections'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.{{u.id}}" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.datasections'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.{{u.id}}" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nocommon'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nocommon.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nocommon" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.noinlinefunctions'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.noinlinefunctions.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.noinlinefunctions" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.freestanding'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nobuiltin'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.spconstant'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.spconstant.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.spconstant" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.PIC'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.PIC.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.PIC" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nomoveloopinvariants'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants.{{u.id}}" name="Disable loop invariant move (-fno-move-loop-invariants)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.other'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.other" value="{{opts['common']['optimization.other']}}" valueType="string"/>
+							{% endif %}
+
+							{% if opts['common']['warnings.syntaxonly'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.syntaxonly.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.syntaxonly" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pedantic'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedantic.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedantic" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pedanticerrors'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedanticerrors.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedanticerrors" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.nowarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.nowarn.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.nowarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.unused'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.unused.{{u.id}}" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.unused" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.uninitialized'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.uninitialized.{{u.id}}" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.uninitialized" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.allwarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.{{u.id}}" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.extrawarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn.{{u.id}}" name="Enable extra warnings (-Wextra)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.missingdeclaration'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.missingdeclaration.{{u.id}}" name="Warn on undeclared global function (-Wmissing-declaration)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.missingdeclaration" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.conversion'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.conversion.{{u.id}}" name="Warn on implicit conversions (-Wconversion)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.conversion" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pointerarith'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pointerarith.{{u.id}}" name="Warn if pointer arithmetic (-Wpointer-arith)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pointerarith" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.padded'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.padded.{{u.id}}" name="Warn if padding is included (-Wpadded)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.padded" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.shadow'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.shadow.{{u.id}}" name="Warn if shadowed variable (-Wshadow)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.shadow" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.logicalop'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.logicalop.{{u.id}}" name="Warn if suspicious logical ops (-Wlogical-op)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.logicalop" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.agreggatereturn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.agreggatereturn.{{u.id}}" name="Warn if struct is returned (-Wagreggate-return)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.agreggatereturn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.floatequal'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.floatequal.{{u.id}}" name="Warn if floats are compared as equal (-Wfloat-equal)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.floatequal" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.toerrors'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.toerrors.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.toerrors" value="true" valueType="boolean"/>
+							{% endif %}
+							
+							{% if opts['common']['warnings.other'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.other" value="{{opts['common']['warnings.other']}}" valueType="string"/>
+							{% endif %}
+
+							{% if opts['common']['debugging.level'] != 'none' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.{{u.id}}" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.{{opts['common']['debugging.level']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['debugging.format'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.{{u.id}}" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.{{opts['common']['debugging.format']}}"  valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['debugging.prof'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['debugging.gprof'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="true" valueType="boolean"/>
+							{% endif %}
+
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.{{u.id}}" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.{{u.id}}" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.{{u.id}}" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.{{u.id}}" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.{{u.id}}" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.{{u.id}}" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.{{u.id}}" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.{{u.id}}" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.{{u.id}}" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.{{u.id}}" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.{{u.id}}" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.{{u.id}}" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/{{name}}}/BUILD/{{opts['name']}}" cleanBuildTarget="mbedclean" id="ilg.gnuarmeclipse.managedbuild.cross.builder.{{u.id}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.{{u.id}}" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								{% if opts['as']['usepreprocessor'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.{{u.id}}" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['as']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['as']['defines'] %}
+									<listOptionValue builtIn="false" value="{{s|replace("\"", "\\\"")|escape}}"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.files.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['as']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.otherwarnings.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.otherwarnings" value="{{opts['as']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['as']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['as']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other.{{u.id}}" name="Other assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other" value="{{opts['as']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.{{opts['uid']['tool_c_compiler']}}" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								{% if opts['c']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['c']['defines'] %}
+									<listOptionValue builtIn="false" value="{{s|replace("\"", "\\\"")|escape}}"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.{{u.id}}" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['c']['compiler.std'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+								{% if opts['c']['otheroptimizations'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otheroptimizations.{{u.id}}" name="Other optimization flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otheroptimizations" useByScannerDiscovery="true" value="{{opts['c']['otheroptimizations']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['warnings.missingprototypes'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.missingprototypes.{{u.id}}" name="Warn if a global function has no prototype (-Wmissing-prototypes)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.missingprototypes" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['warnings.strictprototypes'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.strictprototypes.{{u.id}}" name="Warn if a function has no arg type (-Wstrict-prototypes)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.strictprototypes" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['warnings.badfunctioncast'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.badfunctioncast.{{u.id}}" name="Warn if wrong cast  (-Wbad-function-cast)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.badfunctioncast" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otherwarnings.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otherwarnings" value="{{opts['c']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" value="{{opts['c']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.{{opts['uid']['tool_c_compiler_input']}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}}" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								{% if opts['cpp']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['nostdincpp'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdincpp.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdincpp" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['cpp']['defines'] %}
+									<listOptionValue builtIn="false" value="{{s|replace("\"", "\\\"")|escape}}"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.{{u.id}}" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['cpp']['compiler.std'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.{{opts['cpp']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+
+								{% if opts['cpp']['optimization.noexceptions'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.{{u.id}}" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nortti'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.{{u.id}}" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nousecxaatexit'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit.{{u.id}}" name="Do not use _cxa_atexit() (-fno-use-cxa-atexit)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nothreadsafestatics'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics.{{u.id}}" name="Do not use thread-safe statics (-fno-threadsafe-statics)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['otheroptimizations'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otheroptimizations.{{u.id}}" name="Other optimization flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otheroptimizations" useByScannerDiscovery="true" value="{{opts['cpp']['otheroptimizations']}}" valueType="string"/>
+								{% endif %}
+
+								{% if opts['cpp']['warnabi'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warnabi.{{u.id}}" name="Warn on ABI violations (-Wabi)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warnabi" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.ctordtorprivacy'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.ctordtorprivacy.{{u.id}}" name="Warn on class privacy (-Wctor-dtor-privacy)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.ctordtorprivacy" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.noexcept'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.noexcept.{{u.id}}" name="Warn on no-except expressions (-Wnoexcept)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.noexcept" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.nonvirtualdtor'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.nonvirtualdtor.{{u.id}}" name="Warn on virtual destructors (-Wnon-virtual-dtor)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.nonvirtualdtor" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.strictnullsentinel'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.strictnullsentinel.{{u.id}}" name="Warn on uncast NULL (-Wstrict-null-sentinel)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.strictnullsentinel" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.signpromo'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.signpromo.{{u.id}}" name="Warn on sign promotion (-Wsign-promo)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.signpromo" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warneffc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warneffc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warneffc" value="true" valueType="boolean"/>
+								{% endif %}								
+								{% if opts['cpp']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otherwarnings.{{u.id}}" name="Other warning flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otherwarnings" useByScannerDiscovery="true" value="{{opts['cpp']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+
+								{% if opts['cpp']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" value="{{opts['cpp']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.{{opts['uid']['tool_cpp_compiler_input']}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.{{u.id}}" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.{{u.id}}" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{opts['ld']['script']}}&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.{{u.id}}" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+									{% for path in opts['ld']['library_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+									{% for lib in opts['ld']['user_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+									{% for lib in opts['ld']['system_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+									{% for path in opts['ld']['object_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['ld']['gcsections'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.{{u.id}}" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								{% endif %}
+
+								{% if opts['ld']['nostart'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.{{u.id}}" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nodeflibs'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nostdlibs'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.flags.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.flags" valueType="stringList">
+									{% for opt in opts['ld']['flags'] %}
+									<listOptionValue builtIn="false" value="{{opt}}"/>
+									{% endfor %}
+								</option>
+
+								{% if opts['ld']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="{{opts['ld']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.{{u.id}}" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.{{u.id}}" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.{{u.id}}" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.{{u.id}}" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.{{u.id}}" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.{{u.id}}" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.{{u.id}}" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.{{u.id}}" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.{{u.id}}" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.{{u.id}}" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="{{opts['common']['excluded_folders']}}" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}.ilg.gnuarmeclipse.managedbuild.cross.target.elf.{{u.id}}" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}};ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}}.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}};ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.{{opts['uid']['tool_cpp_compiler_input']}}">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		{% endfor %}
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}};ilg.gnuarmeclipse.managedbuild.cross.config.elf.{{opts['id']}}.{{opts['uid']['config']}}.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.{{opts['uid']['tool_c_compiler']}};ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.{{opts['uid']['tool_c_compiler_input']}}">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/.project.tmpl
new file mode 100755
index 0000000..cc88934
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/.project.tmpl
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Generated by the GNU ARM Eclipse exporter from an mBed project. -->
+<projectDescription>
+	<name>{{name}}</name>
+	<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-GNU-ARM-Eclipse</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/NOTES.md b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/NOTES.md
new file mode 100755
index 0000000..6c3068e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/NOTES.md
@@ -0,0 +1,488 @@
+# GNU ARM Eclipse
+
+The [GNU ARM Eclipse](http://gnuarmeclipse.github.io) is an open source project that includes a family of Eclipse plug-ins and tools for multi-platform embedded ARM development, based on GNU toolchains. The project is hosted on [GitHub](https://github.com/gnuarmeclipse).
+
+This exporter aims to create managed GNU ARM Eclipse projects, ready to build, and with as many options properly identified and set in the Eclipse C/C++ Build -> Settings page.
+
+## Build plug-in configuration options
+
+All options are prefixed by `ilg.gnuarmeclipse.managedbuild.cross.option.`.
+
+### Target Processor 
+
+- `arm.target.family` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m3** '-mcpu=cortex-m3'
+    - cortex-m0 '-mcpu=%s'
+    - cortex-m0-small-multiply '-mcpu=%s'
+    - cortex-m0plus '-mcpu=%s'
+    - cortex-m0plus-small-multiply '-mcpu=%s'
+    - cortex-m1 '-mcpu=%s'
+    - cortex-m1-small-multiply '-mcpu=%s'
+    - cortex-m4 '-mcpu=%s'
+    - cortex-m7 '-mcpu=%s'
+
+- `arm.target.architecture` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.none** ''
+    - armv6-m '-march=%s'
+    - armv7-m '-march=%s'
+
+- `arm.target.instructionset` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb** '-mthumb'
+    - arm '-marm'
+    
+- `arm.target.thumbinterwork` bool
+    - true `-mthumb-interwork`
+
+- `arm.target.endianness` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness.default**
+    - little `-mlittle-endian`
+    - big `-mbig-endian`
+
+- `arm.target.fpu.abi` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.default**
+    - soft '-mfloat-abi=soft'
+    - softfp '-mfloat-abi=softfp'
+    - hard '-mfloat-abi=hard'
+
+- `arm.target.fpu.unit` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.default**
+    - fpv4spd16 '-mfpu=fpv4-sp-d16'
+    - fpv5d16 '-mfpu=fpv5-d16'
+    - fpv5spd16 '-mfpu=fpv5-sp-d16'
+    - ...
+
+- `arm.target.unalignedaccess`
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess.default**
+    - enabled '-munaligned-access'
+    - disabled '-mno-unaligned-access'
+
+- `target.other` string
+
+### Optimization
+
+- `optimization.level` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.more** '-O2'
+    - none '-O0'
+    - optimize '-O1'
+    - most '-O3'
+    - size '-Os'
+    - debug '-Og'
+
+- `optimization.messagelength` bool
+    - **false** ''
+    - true '-fmessage-length=0'
+
+- `optimization.signedchar` bool
+    - **false**
+    - true '-fsigned-char'
+
+- `optimization.functionsections` bool
+    - **false**
+    - true '-ffunction-sections'
+
+- `optimization.datasections` bool
+    - **false**
+    - true '-fdata-sections'
+
+- `optimization.nocommon` bool
+    - **false**
+    - true '-fno-common'
+
+- `optimization.noinlinefunctions` bool
+    - **false** ''
+    - true '-fno-inline-functions'
+
+- `optimization.freestanding` bool
+    - **false** ''
+    - true '-ffreestanding'
+
+- `optimization.nobuiltin` bool
+    - **false** ''
+    - true '-fno-builtin'
+
+- `optimization.spconstant` bool
+    - **false** ''
+    - true '-fsingle-precision-constant'
+
+- `optimization.PIC` bool
+    - **false** ''
+    - true '-fPIC'
+
+- `optimization.lto` bool
+    - **false** ''
+    - true '-flto'
+
+- `optimization.nomoveloopinvariants` bool
+    - **false** ''
+    - true '-fno-move-loop-invariants'
+
+- `optimization.other` string
+
+- `` bool
+    - **false** ''
+    - true ''
+
+### Warnings
+
+- `warnings.syntaxonly` bool
+    - **false** ''
+    - true '-fsyntax-only'
+
+- `warnings.pedantic` bool
+    - **false** ''
+    - true '-pedantic'
+
+- `warnings.pedanticerrors` bool
+    - **false** ''
+    - true '-pedantic-errors'
+
+- `warnings.nowarn` bool
+    - **false** ''
+    - true '-w'
+
+- `warnings.unused` bool
+    - **false** ''
+    - true '-Wunused'
+
+- `warnings.uninitialized` bool
+    - **false** ''
+    - true '-Wuninitialized'
+
+- `warnings.allwarn` bool
+    - **false** ''
+    - true '-Wall'
+
+- `warnings.extrawarn` bool
+    - **false** ''
+    - true '-Wextra'
+
+- `warnings.missingdeclaration` bool
+    - **false** ''
+    - true '-Wmissing-declarations'
+
+- `warnings.conversion` bool
+    - **false** ''
+    - true '-Wconversion'
+
+- `warnings.pointerarith` bool
+    - **false** ''
+    - true '-Wpointer-arith'
+
+- `warnings.padded` bool
+    - **false** ''
+    - true '-Wpadded'
+
+- `warnings.shadow` bool
+    - **false** ''
+    - true '-Wshadow'
+
+- `warnings.logicalop` bool
+    - **false** ''
+    - true '-Wlogical-op'
+
+- `warnings.agreggatereturn` bool
+    - **false** ''
+    - true '-Waggregate-return'
+
+- `warnings.floatequal` bool
+    - **false** ''
+    - true '-Wfloat-equal'
+
+- `warnings.toerrors` bool
+    - **false** ''
+    - true '-Werror'
+
+- `warnings.other` string
+
+### Debugging
+
+- `debugging.level` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default** '-g'
+    - none ''
+    - minimal '-g1'
+    - max '-g3'
+
+- `debugging.format` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.default** ''
+    - gdb '-ggdb'
+    - stabs '-gstabs'
+    - stabsplus '-gstabs+'
+    - dwarf2 '-gdwarf-2'
+    - dwarf3 '-gdwarf-3'
+    - dwarf4 '-gdwarf-4'
+    - dwarf5 '-gdwarf-5'
+
+- `debugging.prof` bool
+    - **false** ''
+    - true '-p'
+
+- `debugging.gprof` bool
+    - **false** ''
+    - true '-pg'
+
+- `debugging.other` string
+
+
+### Compiler common options
+
+- `verbose` bool
+    - **false** ''
+    - true '-v'
+
+- `savetemps` bool
+    - **false** ''
+    - true '--save-temps'
+
+- `nostdinc` bool
+    - **false** ''
+    - true '-nostdinc'
+
+- `asmlisting` bool
+    - **false** ''
+    - true '-Wa,-adhlns="$@.lst"'
+
+- `preprocessor.preprocessonly` bool
+    - **false** ''
+    - true '-E'
+
+- `dirs.include.files`
+    - '-include%s'
+
+- `compiler.other` string
+
+### Linker common options
+
+- `mapfilename` string
+    - '-Wl,-Map,"${BuildArtifactFileBaseName}.map"'
+
+- `linker.scriptfile`
+    - '-T %s'
+
+- `cref` bool
+    - **false** ''
+    - true '-Xlinker --cref'
+
+- `printmap` bool
+    - **false** ''
+    - true '-Xlinker --print-map'
+
+- `linker.nostart` bool
+    - **false** ''
+    - true '-nostartfiles'
+
+- `linker.nodeflibs` bool
+    - **false** ''
+    - true '-nodefaultlibs'
+
+- `linker.nostdlibs` bool
+    - **false** ''
+    - true '-nostdlib'
+
+- `linker.gcsections` bool
+    - **false** ''
+    - true '-Xlinker --gc-sections'
+
+- `linker.printgcsections` bool
+    - **false** ''
+    - true '-Xlinker --print-gc-sections'
+
+- `linker.strip` bool
+    - **false** ''
+    - true '-s'
+
+- `linker.other` string
+
+- `linker.usenewlibnano` bool
+    - **false** ''
+    - true '--specs=nano.specs'
+
+- `linker.useprintffloat` bool
+    - **false** ''
+    - true '-u \_printf\_float'
+
+- `linker.usescanffloat` bool
+    - **false** ''
+    - true '-u \_scanf\_float'
+
+
+### Cross ARM GNU Assembler
+
+#### Preprocessor
+
+- `nostdinc` bool
+    - **false** ''
+    - true '-nostdinc'
+
+#### Includes
+
+#### Warnings
+
+#### Miscellaneous
+
+- `verbose` bool
+    - **false** ''
+    - true '-v'
+
+- `assembler.other` string
+
+### Cross ARM GNU C Compiler
+
+#### Preprocessor
+
+- `nostdinc` bool
+    - **false** ''
+    - true '-nostdinc'
+
+#### Includes
+
+#### Optimization
+
+- `c.compiler.std` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.default** ''
+    - ansi '-ansi'
+    - c90 '-std=c90' (c89)
+    - gnu90 '-std=gnu90' (gnu89)
+    - c99 '-std=c99' (c9x)
+    - gnu99 '-std=gnu99' (gnu9x)
+    - c11 '-std=c11' (c1x)
+    - gnu11 '-std=gnu11' (gnu1x)
+
+#### Warnings
+
+- `c.compiler.warning.missingprototypes` bool
+    - **false** ''
+    - true '-Wmissing-prototypes'
+
+- `c.compiler.warning.strictprototypes` bool
+    - **false** ''
+    - true '-Wstrict-prototypes'
+
+- `c.compiler.warning.badfunctioncast` bool
+    - **false** ''
+    - true '-Wbad-function-cast'
+
+#### Miscellaneous
+
+- `verbose` bool
+    - **false** ''
+    - true '-v'
+
+- `c.compiler.other` string
+
+### Cross ARM GNU C++ Compiler
+
+#### Preprocessor
+
+- `nostdinc` bool
+    - **false** ''
+    - true '-nostdinc'
+
+- `nostdincpp` bool
+    - **false** ''
+    - true '-nostdinc++'
+
+#### Includes
+
+#### Optimization
+
+- `cpp.compiler.std` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.default** ''
+    - ansi (-ansi)
+    - cpp98 '-std=c++98' (c++03)
+    - gnucpp98 '-std=gnu++98' (gnu++03)
+    - cpp0x '-std=c++0x'
+    - gnucpp0x '-std=gnu++0x'
+    - cpp11 '-std=c++11'
+    - gnucpp11 '-std=gnu++11'
+    - cpp1y '-std=c++1y'
+    - gnucpp1y '-std=gnu++1y'
+    - cpp14 '-std=c++14'
+    - gnucpp1 4'-std=gnu++14'
+    - cpp1z '-std=c++1z'
+    - gnucpp1z '-std=gnu++1z'
+
+- `cpp.compiler.abiversion` enumerated
+    - **ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.abiversion.0** '-fabi-version=0'
+    - default ''
+    - 1 '-fabi-version=1'
+    - 2 '-fabi-version=2'
+    - 3 '-fabi-version=3'
+    - 4 '-fabi-version=4'
+    - 5 '-fabi-version=5'
+    - 6 '-fabi-version=6'
+
+- `cpp.compiler.noexceptions` bool
+    - **false** ''
+    - true '-fno-exceptions'
+
+- `cpp.compiler.nortti` bool
+    - **false** ''
+    - true '-fno-rtti'
+
+- `cpp.compiler.nousecxaatexit` bool
+    - **false** ''
+    - true '-fno-use-cxa-atexit'
+
+- `cpp.compiler.nothreadsafestatics` bool
+    - **false** ''
+    - true '-fno-threadsafe-statics'
+
+
+#### Warnings
+
+- `cpp.compiler.warnabi` bool
+    - **false** '-Wabi'
+
+- `cpp.compiler.warning.ctordtorprivacy` bool
+    - **false** '-Wctor-dtor-privacy'
+
+- `cpp.compiler.warning.noexcept` bool
+    - **false** '-Wnoexcept'
+
+- `cpp.compiler.warning.nonvirtualdtor` bool
+    - **false** '-Wnon-virtual-dtor'
+
+- `cpp.compiler.warning.strictnullsentinel` bool
+    - **false** '-Wstrict-null-sentinel'
+
+- `cpp.compiler.warning.signpromo` bool
+    - **false** '-Wsign-promo'
+
+- `cpp.compiler.warneffc` bool
+    - **false** ''
+    - true '-Weffc++'
+
+#### Miscellaneous
+
+- `verbose` bool
+    - **false** ''
+    - true '-v'
+
+- `cpp.compiler.other` string
+
+### Cross ARM GNU C++ Linker
+
+#### General
+
+- `cpp.linker.nostart`
+    - **false** ''
+    - true '-nostartfiles'
+
+- `cpp.linker.nodeflibs`
+    - **false** ''
+    - true '-nodefaultlibs'
+
+- `cpp.linker.nostdlibs`
+    - **false** ''
+    - true '-nostdlib'
+
+#### Libraries
+
+#### Miscellaneous
+
+
+## Template
+
+- `` bool
+    - **false** ''
+    - true ''
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/__init__.py
new file mode 100755
index 0000000..5d4dcc8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/__init__.py
@@ -0,0 +1,975 @@
+"""
+mbed SDK
+Copyright (c) 2011-2017 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Title: GNU ARM Eclipse (http://gnuarmeclipse.github.io) exporter.
+
+Description: Creates a managed build project that can be imported by 
+the GNU ARM Eclipse plug-ins.
+
+Author: Liviu Ionescu <ilg@livius.net>
+"""
+
+import os
+import copy
+import tempfile
+import shutil
+import copy
+
+from subprocess import call, Popen, PIPE
+from os.path import splitext, basename, relpath, dirname, exists, join, dirname
+from random import randint
+from json import load
+
+from tools.export.exporters import Exporter, apply_supported_whitelist
+from tools.options import list_profiles
+from tools.targets import TARGET_MAP
+from tools.utils import NotSupportedException
+from tools.build_api import prepare_toolchain
+
+# =============================================================================
+
+
+class UID:
+    """
+    Helper class, used to generate unique ids required by .cproject symbols.
+    """
+    @property
+    def id(self):
+        return "%0.9u" % randint(0, 999999999)
+
+# Global UID generator instance.
+# Passed to the template engine, and referred as {{u.id}}.
+# Each invocation generates a new number.
+u = UID()
+
+# =============================================================================
+
+
+POST_BINARY_WHITELIST = set([
+    "TEENSY3_1Code.binary_hook",
+    "MCU_NRF51Code.binary_hook",
+    "LPCTargetCode.lpc_patch",
+    "LPC4088Code.binary_hook"
+])
+
+class GNUARMEclipse(Exporter):
+    NAME = 'GNU ARM Eclipse'
+    TOOLCHAIN = 'GCC_ARM'
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return apply_supported_whitelist(
+            cls.TOOLCHAIN, POST_BINARY_WHITELIST, target)
+
+    # override
+    @property
+    def flags(self):
+        """Returns a dictionary of toolchain flags.
+        Keys of the dictionary are:
+        cxx_flags    - c++ flags
+        c_flags      - c flags
+        ld_flags     - linker flags
+        asm_flags    - assembler flags
+        common_flags - common options
+
+        The difference from the parent function is that it does not
+        add macro definitions, since they are passed separately.
+        """
+
+        config_header = self.toolchain.get_config_header()
+        flags = {key + "_flags": copy.deepcopy(value) for key, value
+                 in self.toolchain.flags.iteritems()}
+        if config_header:
+            config_header = relpath(config_header,
+                                    self.resources.file_basepath[config_header])
+            flags['c_flags'] += self.toolchain.get_config_option(config_header)
+            flags['cxx_flags'] += self.toolchain.get_config_option(
+                config_header)
+        return flags
+
+    def toolchain_flags(self, toolchain):
+        """Returns a dictionary of toolchain flags.
+        Keys of the dictionary are:
+        cxx_flags    - c++ flags
+        c_flags      - c flags
+        ld_flags     - linker flags
+        asm_flags    - assembler flags
+        common_flags - common options
+
+        The difference from the above is that it takes a parameter.
+        """
+
+        # Note: use the config options from the currently selected toolchain.
+        config_header = self.toolchain.get_config_header()
+
+        flags = {key + "_flags": copy.deepcopy(value) for key, value
+                 in toolchain.flags.iteritems()}
+        if config_header:
+            config_header = relpath(config_header,
+                                    self.resources.file_basepath[config_header])
+            header_options = self.toolchain.get_config_option(config_header)
+            flags['c_flags'] += header_options
+            flags['cxx_flags'] += header_options
+        return flags
+
+    def validate_resources(self):
+        if not self.resources.linker_script:
+            raise NotSupportedException("No linker script found.")
+
+    def create_jinja_ctx(self):
+
+        self.validate_resources()
+
+        self.resources.win_to_unix()
+
+        # TODO: use some logger to display additional info if verbose
+
+        libraries = []
+        # print 'libraries'
+        # print self.resources.libraries
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            libraries.append(l[3:])
+
+        self.system_libraries = [
+            'stdc++', 'supc++', 'm', 'c', 'gcc', 'nosys'
+        ]
+
+        # Read in all profiles, we'll extract compiler options.
+        profiles = self.get_all_profiles()
+
+        profile_ids = [s.lower() for s in profiles]
+        profile_ids.sort()
+
+        # TODO: get the list from existing .cproject
+        build_folders = [s.capitalize() for s in profile_ids]
+        build_folders.append('BUILD')
+        # print build_folders
+
+        objects = [self.filter_dot(s) for s in self.resources.objects]
+        for bf in build_folders:
+            objects = [o for o in objects if not o.startswith(bf + '/')]
+        # print 'objects'
+        # print objects
+
+        self.compute_exclusions()
+
+        self.include_path = [
+            self.filter_dot(s) for s in self.resources.inc_dirs]
+        print 'Include folders: {0}'.format(len(self.include_path))
+
+        self.as_defines = self.toolchain.get_symbols(True)
+        self.c_defines = self.toolchain.get_symbols()
+        self.cpp_defines = self.c_defines
+        print 'Symbols: {0}'.format(len(self.c_defines))
+
+        self.ld_script = self.filter_dot(
+            self.resources.linker_script)
+        print 'Linker script: {0}'.format(self.ld_script)
+
+        self.options = {}
+        for id in profile_ids:
+
+            # There are 4 categories of options, a category common too
+            # all tools and a specific category for each of the tools.
+            opts = {}
+            opts['common'] = {}
+            opts['as'] = {}
+            opts['c'] = {}
+            opts['cpp'] = {}
+            opts['ld'] = {}
+
+            opts['id'] = id
+            opts['name'] = opts['id'].capitalize()
+
+            print
+            print 'Build configuration: {0}'.format(opts['name'])
+
+            profile = profiles[id]
+
+            # A small hack, do not bother with src_path again,
+            # pass an empty string to avoid crashing.
+            src_paths = ['']
+            target_name = self.toolchain.target.name
+            toolchain = prepare_toolchain(
+                src_paths, "", target_name, self.TOOLCHAIN, build_profile=[profile])
+
+            # Hack to fill in build_dir
+            toolchain.build_dir = self.toolchain.build_dir
+
+            flags = self.toolchain_flags(toolchain)
+
+            print 'Common flags:', ' '.join(flags['common_flags'])
+            print 'C++ flags:', ' '.join(flags['cxx_flags'])
+            print 'C flags:', ' '.join(flags['c_flags'])
+            print 'ASM flags:', ' '.join(flags['asm_flags'])
+            print 'Linker flags:', ' '.join(flags['ld_flags'])
+
+            # Most GNU ARM Eclipse options have a parent,
+            # either debug or release.
+            if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']:
+                opts['parent_id'] = 'debug'
+            else:
+                opts['parent_id'] = 'release'
+
+            self.process_options(opts, flags)
+
+            opts['as']['defines'] = self.as_defines
+            opts['c']['defines'] = self.c_defines
+            opts['cpp']['defines'] = self.cpp_defines
+
+            opts['common']['include_paths'] = self.include_path
+            opts['common']['excluded_folders'] = '|'.join(
+                self.excluded_folders)
+
+            opts['ld']['library_paths'] = [
+                self.filter_dot(s) for s in self.resources.lib_dirs]
+
+            opts['ld']['object_files'] = objects
+            opts['ld']['user_libraries'] = libraries
+            opts['ld']['system_libraries'] = self.system_libraries
+            opts['ld']['script'] = join(id.capitalize(),
+                                        "linker-script-%s.ld" % id)
+            opts['cpp_cmd'] = '"{}"'.format(toolchain.preproc[0]) + " " + " ".join(toolchain.preproc[1:])
+
+            # Unique IDs used in multiple places.
+            # Those used only once are implemented with {{u.id}}.
+            uid = {}
+            uid['config'] = u.id
+            uid['tool_c_compiler'] = u.id
+            uid['tool_c_compiler_input'] = u.id
+            uid['tool_cpp_compiler'] = u.id
+            uid['tool_cpp_compiler_input'] = u.id
+
+            opts['uid'] = uid
+
+            self.options[id] = opts
+
+        jinja_ctx = {
+            'name': self.project_name,
+            'ld_script': self.ld_script,
+
+            # Compiler & linker command line options
+            'options': self.options,
+
+            # Must be an object with an `id` property, which
+            # will be called repeatedly, to generate multiple UIDs.
+            'u': u,
+        }
+        return jinja_ctx
+
+    # override
+    def generate(self):
+        """
+        Generate the .project and .cproject files.
+        """
+        jinja_ctx = self.create_jinja_ctx()
+
+        print
+        print 'Create a GNU ARM Eclipse C++ managed project'
+        print 'Project name: {0}'.format(self.project_name)
+        print 'Target: {0}'.format(self.toolchain.target.name)
+        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
+
+        self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx,
+                      '.project', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('gnuarmeclipse/.cproject.tmpl', jinja_ctx,
+                      '.cproject', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('gnuarmeclipse/makefile.targets.tmpl', jinja_ctx,
+                      'makefile.targets', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore')
+
+        print
+        print 'Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name)
+
+    # override
+    @staticmethod
+    def build(project_name, log_name="build_log.txt", cleanup=True):
+        """
+        Headless build an Eclipse project.
+
+        The following steps are performed:
+        - a temporary workspace is created, 
+        - the project is imported,
+        - a clean build of all configurations is performed and 
+        - the temporary workspace is removed.
+
+        The build results are in the Debug & Release folders.
+
+        All executables (eclipse & toolchain) must be in the PATH.
+
+        The general method to start a headless Eclipse build is:
+
+        $ eclipse \
+        --launcher.suppressErrors \
+        -nosplash \
+        -application org.eclipse.cdt.managedbuilder.core.headlessbuild \
+        -data /path/to/workspace \
+        -import /path/to/project \
+        -cleanBuild "project[/configuration] | all"
+        """
+
+        # TODO: possibly use the log file.
+
+        # Create a temporary folder for the workspace.
+        tmp_folder = tempfile.mkdtemp()
+
+        cmd = [
+            'eclipse',
+            '--launcher.suppressErrors',
+            '-nosplash',
+            '-application org.eclipse.cdt.managedbuilder.core.headlessbuild',
+            '-data', tmp_folder,
+            '-import', os.getcwd(),
+            '-cleanBuild', project_name
+        ]
+
+        p = Popen(' '.join(cmd), shell=True, stdout=PIPE, stderr=PIPE)
+        out, err = p.communicate()
+        ret_code = p.returncode
+        stdout_string = "=" * 10 + "STDOUT" + "=" * 10 + "\n"
+        err_string = "=" * 10 + "STDERR" + "=" * 10 + "\n"
+        err_string += err
+
+        ret_string = "SUCCESS\n"
+        if ret_code != 0:
+            ret_string += "FAILURE\n"
+
+        print "%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string)
+
+        if log_name:
+            # Write the output to the log file
+            with open(log_name, 'w+') as f:
+                f.write(stdout_string)
+                f.write(out)
+                f.write(err_string)
+                f.write(ret_string)
+
+        # Cleanup the exported and built files
+        if cleanup:
+            if exists(log_name):
+                os.remove(log_name)
+            os.remove('.project')
+            os.remove('.cproject')
+            if exists('Debug'):
+                shutil.rmtree('Debug')
+            if exists('Release'):
+                shutil.rmtree('Release')
+            if exists('makefile.targets'):
+                os.remove('makefile.targets')
+
+        # Always remove the temporary folder.
+        if exists(tmp_folder):
+            shutil.rmtree(tmp_folder)
+
+        if ret_code == 0:
+            # Return Success
+            return 0
+
+        # Seems like something went wrong.
+        return -1
+
+   # -------------------------------------------------------------------------
+
+    @staticmethod
+    def get_all_profiles():
+        tools_path = dirname(dirname(dirname(__file__)))
+        file_names = [join(tools_path, "profiles", fn) for fn in os.listdir(
+            join(tools_path, "profiles")) if fn.endswith(".json")]
+
+        # print file_names
+
+        profile_names = [basename(fn).replace(".json", "")
+                         for fn in file_names]
+        # print profile_names
+
+        profiles = {}
+
+        for fn in file_names:
+            content = load(open(fn))
+            profile_name = basename(fn).replace(".json", "")
+            profiles[profile_name] = content
+
+        return profiles
+
+    # -------------------------------------------------------------------------
+    # Process source files/folders exclusions.
+
+    def compute_exclusions(self):
+        """
+        With the project root as the only source folder known to CDT,
+        based on the list of source files, compute the folders to not
+        be included in the build.
+
+        The steps are:
+        - get the list of source folders, as dirname(source_file)
+        - compute the top folders (subfolders of the project folder)
+        - iterate all subfolders and add them to a tree, with all 
+        nodes markes as 'not used'
+        - iterate the source folders and mark them as 'used' in the
+        tree, including all intermediate nodes
+        - recurse the tree and collect all unused folders; descend
+        the hierarchy only for used nodes
+        """
+        source_folders = [self.filter_dot(s) for s in set(dirname(
+            src) for src in self.resources.c_sources + self.resources.cpp_sources + self.resources.s_sources)]
+
+        self.excluded_folders = set(self.resources.ignored_dirs) - set(self.resources.inc_dirs)
+        print 'Source folders: {0}, with {1} exclusions'.format(len(source_folders), len(self.excluded_folders))
+
+
+    # -------------------------------------------------------------------------
+
+    @staticmethod
+    def filter_dot(str):
+        """
+        Remove the './' prefix, if present.
+        This function assumes that resources.win_to_unix()
+        replaced all windows backslashes with slashes.
+        """
+        if str == None:
+            return None
+        if str[:2] == './':
+            return str[2:]
+        return str
+
+    # -------------------------------------------------------------------------
+
+    def dump_tree(self, nodes, depth=0):
+        for k in nodes.keys():
+            node = nodes[k]
+            parent_name = node['parent'][
+                'name'] if 'parent' in node.keys() else ''
+            print '  ' * depth, node['name'], node['is_used'], parent_name
+            if len(node['children'].keys()) != 0:
+                self.dump_tree(node['children'], depth + 1)
+
+    def dump_paths(self, nodes, depth=0):
+        for k in nodes.keys():
+            node = nodes[k]
+            parts = []
+            while True:
+                parts.insert(0, node['name'])
+                if 'parent' not in node:
+                    break
+                node = node['parent']
+            path = '/'.join(parts)
+            print path, nodes[k]['is_used']
+            self.dump_paths(nodes[k]['children'], depth + 1)
+
+    # -------------------------------------------------------------------------
+
+    def process_options(self, opts, flags_in):
+        """
+        CDT managed projects store lots of build options in separate
+        variables, with separate IDs in the .cproject file.
+        When the CDT build is started, all these options are brought
+        together to compose the compiler and linker command lines.
+
+        Here the process is reversed, from the compiler and linker
+        command lines, the options are identified and various flags are
+        set to control the template generation process.
+
+        Once identified, the options are removed from the command lines.
+
+        The options that were not identified are options that do not 
+        have CDT equivalents and will be passed in the 'Other options' 
+        categories.
+
+        Although this process does not have a very complicated logic,
+        given the large number of explicit configuration options
+        used by the GNU ARM Eclipse managed build plug-in, it is tedious...
+        """
+
+        # Make a copy of the flags, to be one by one removed after processing.
+        flags = copy.deepcopy(flags_in)
+
+        if False:
+            print
+            print 'common_flags', flags['common_flags']
+            print 'asm_flags', flags['asm_flags']
+            print 'c_flags', flags['c_flags']
+            print 'cxx_flags', flags['cxx_flags']
+            print 'ld_flags', flags['ld_flags']
+
+        # Initialise the 'last resort' options where all unrecognised
+        # options will be collected.
+        opts['as']['other'] = ''
+        opts['c']['other'] = ''
+        opts['cpp']['other'] = ''
+        opts['ld']['other'] = ''
+
+        MCPUS = {
+            'Cortex-M0': {'mcpu': 'cortex-m0', 'fpu_unit': None},
+            'Cortex-M0+': {'mcpu': 'cortex-m0plus', 'fpu_unit': None},
+            'Cortex-M1': {'mcpu': 'cortex-m1', 'fpu_unit': None},
+            'Cortex-M3': {'mcpu': 'cortex-m3', 'fpu_unit': None},
+            'Cortex-M4': {'mcpu': 'cortex-m4', 'fpu_unit': None},
+            'Cortex-M4F': {'mcpu': 'cortex-m4', 'fpu_unit': 'fpv4spd16'},
+            'Cortex-M7': {'mcpu': 'cortex-m7', 'fpu_unit': None},
+            'Cortex-M7F': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv4spd16'},
+            'Cortex-M7FD': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv5d16'},
+            'Cortex-A9': {'mcpu': 'cortex-a9', 'fpu_unit': 'vfpv3'}
+        }
+
+        # Remove options that are supplied by CDT
+        self.remove_option(flags['common_flags'], '-c')
+        self.remove_option(flags['common_flags'], '-MMD')
+
+        # As 'plan B', get the CPU from the target definition.
+        core = self.toolchain.target.core
+
+        opts['common']['arm.target.family'] = None
+
+        # cortex-m0, cortex-m0-small-multiply, cortex-m0plus,
+        # cortex-m0plus-small-multiply, cortex-m1, cortex-m1-small-multiply,
+        # cortex-m3, cortex-m4, cortex-m7.
+        str = self.find_options(flags['common_flags'], '-mcpu=')
+        if str != None:
+            opts['common']['arm.target.family'] = str[len('-mcpu='):]
+            self.remove_option(flags['common_flags'], str)
+            self.remove_option(flags['ld_flags'], str)
+        else:
+            if core not in MCPUS:
+                raise NotSupportedException(
+                    'Target core {0} not supported.'.format(core))
+            opts['common']['arm.target.family'] = MCPUS[core]['mcpu']
+
+        opts['common']['arm.target.arch'] = 'none'
+        str = self.find_options(flags['common_flags'], '-march=')
+        arch = str[len('-march='):]
+        archs = {'armv6-m': 'armv6-m', 'armv7-m': 'armv7-m', 'armv7-a': 'armv7-a'}
+        if arch in archs:
+            opts['common']['arm.target.arch'] = archs[arch]
+            self.remove_option(flags['common_flags'], str)
+
+        opts['common']['arm.target.instructionset'] = 'thumb'
+        if '-mthumb' in flags['common_flags']:
+            self.remove_option(flags['common_flags'], '-mthumb')
+            self.remove_option(flags['ld_flags'], '-mthumb')
+        elif '-marm' in flags['common_flags']:
+            opts['common']['arm.target.instructionset'] = 'arm'
+            self.remove_option(flags['common_flags'], '-marm')
+            self.remove_option(flags['ld_flags'], '-marm')
+
+        opts['common']['arm.target.thumbinterwork'] = False
+        if '-mthumb-interwork' in flags['common_flags']:
+            opts['common']['arm.target.thumbinterwork'] = True
+            self.remove_option(flags['common_flags'], '-mthumb-interwork')
+
+        opts['common']['arm.target.endianness'] = None
+        if '-mlittle-endian' in flags['common_flags']:
+            opts['common']['arm.target.endianness'] = 'little'
+            self.remove_option(flags['common_flags'], '-mlittle-endian')
+        elif '-mbig-endian' in flags['common_flags']:
+            opts['common']['arm.target.endianness'] = 'big'
+            self.remove_option(flags['common_flags'], '-mbig-endian')
+
+        opts['common']['arm.target.fpu.unit'] = None
+        # default, fpv4spd16, fpv5d16, fpv5spd16
+        str = self.find_options(flags['common_flags'], '-mfpu=')
+        if str != None:
+            fpu = str[len('-mfpu='):]
+            fpus = {
+                'fpv4-sp-d16': 'fpv4spd16',
+                'fpv5-d16': 'fpv5d16',
+                'fpv5-sp-d16': 'fpv5spd16'
+            }
+            if fpu in fpus:
+                opts['common']['arm.target.fpu.unit'] = fpus[fpu]
+
+                self.remove_option(flags['common_flags'], str)
+                self.remove_option(flags['ld_flags'], str)
+        if opts['common']['arm.target.fpu.unit'] == None:
+            if core not in MCPUS:
+                raise NotSupportedException(
+                    'Target core {0} not supported.'.format(core))
+            if MCPUS[core]['fpu_unit']:
+                opts['common'][
+                    'arm.target.fpu.unit'] = MCPUS[core]['fpu_unit']
+
+        # soft, softfp, hard.
+        str = self.find_options(flags['common_flags'], '-mfloat-abi=')
+        if str != None:
+            opts['common']['arm.target.fpu.abi'] = str[
+                len('-mfloat-abi='):]
+            self.remove_option(flags['common_flags'], str)
+            self.remove_option(flags['ld_flags'], str)
+
+        opts['common']['arm.target.unalignedaccess'] = None
+        if '-munaligned-access' in flags['common_flags']:
+            opts['common']['arm.target.unalignedaccess'] = 'enabled'
+            self.remove_option(flags['common_flags'], '-munaligned-access')
+        elif '-mno-unaligned-access' in flags['common_flags']:
+            opts['common']['arm.target.unalignedaccess'] = 'disabled'
+            self.remove_option(flags['common_flags'], '-mno-unaligned-access')
+
+        # Default optimisation level for Release.
+        opts['common']['optimization.level'] = '-Os'
+
+        # If the project defines an optimisation level, it is used
+        # only for the Release configuration, the Debug one used '-Og'.
+        str = self.find_options(flags['common_flags'], '-O')
+        if str != None:
+            levels = {
+                '-O0': 'none', '-O1': 'optimize', '-O2': 'more',
+                '-O3': 'most', '-Os': 'size', '-Og': 'debug'
+            }
+            if str in levels:
+                opts['common']['optimization.level'] = levels[str]
+                self.remove_option(flags['common_flags'], str)
+
+        include_files = []
+        for all_flags in [flags['common_flags'], flags['c_flags'], flags['cxx_flags']]:
+            while '-include' in all_flags:
+                ix = all_flags.index('-include')
+                str = all_flags[ix + 1]
+                if str not in include_files:
+                    include_files.append(str)
+                self.remove_option(all_flags, '-include')
+                self.remove_option(all_flags, str)
+
+        opts['common']['include_files'] = include_files
+
+        if '-ansi' in flags['c_flags']:
+            opts['c']['compiler.std'] = '-ansi'
+            self.remove_option(flags['c_flags'], str)
+        else:
+            str = self.find_options(flags['c_flags'], '-std')
+            std = str[len('-std='):]
+            c_std = {
+                'c90': 'c90', 'c89': 'c90', 'gnu90': 'gnu90', 'gnu89': 'gnu90',
+                'c99': 'c99', 'c9x': 'c99', 'gnu99': 'gnu99', 'gnu9x': 'gnu98',
+                'c11': 'c11', 'c1x': 'c11', 'gnu11': 'gnu11', 'gnu1x': 'gnu11'
+            }
+            if std in c_std:
+                opts['c']['compiler.std'] = c_std[std]
+                self.remove_option(flags['c_flags'], str)
+
+        if '-ansi' in flags['cxx_flags']:
+            opts['cpp']['compiler.std'] = '-ansi'
+            self.remove_option(flags['cxx_flags'], str)
+        else:
+            str = self.find_options(flags['cxx_flags'], '-std')
+            std = str[len('-std='):]
+            cpp_std = {
+                'c++98': 'cpp98', 'c++03': 'cpp98',
+                'gnu++98': 'gnucpp98', 'gnu++03': 'gnucpp98',
+                'c++0x': 'cpp0x', 'gnu++0x': 'gnucpp0x',
+                'c++11': 'cpp11', 'gnu++11': 'gnucpp11',
+                'c++1y': 'cpp1y', 'gnu++1y': 'gnucpp1y',
+                'c++14': 'cpp14', 'gnu++14': 'gnucpp14',
+                'c++1z': 'cpp1z', 'gnu++1z': 'gnucpp1z',
+            }
+            if std in cpp_std:
+                opts['cpp']['compiler.std'] = cpp_std[std]
+                self.remove_option(flags['cxx_flags'], str)
+
+        # Common optimisation options.
+        optimization_options = {
+            '-fmessage-length=0': 'optimization.messagelength',
+            '-fsigned-char': 'optimization.signedchar',
+            '-ffunction-sections': 'optimization.functionsections',
+            '-fdata-sections': 'optimization.datasections',
+            '-fno-common': 'optimization.nocommon',
+            '-fno-inline-functions': 'optimization.noinlinefunctions',
+            '-ffreestanding': 'optimization.freestanding',
+            '-fno-builtin': 'optimization.nobuiltin',
+            '-fsingle-precision-constant': 'optimization.spconstant',
+            '-fPIC': 'optimization.PIC',
+            '-fno-move-loop-invariants': 'optimization.nomoveloopinvariants',
+        }
+
+        for option in optimization_options:
+            opts['common'][optimization_options[option]] = False
+            if option in flags['common_flags']:
+                opts['common'][optimization_options[option]] = True
+                self.remove_option(flags['common_flags'], option)
+
+        # Common warning options.
+        warning_options = {
+            '-fsyntax-only': 'warnings.syntaxonly',
+            '-pedantic': 'warnings.pedantic',
+            '-pedantic-errors': 'warnings.pedanticerrors',
+            '-w': 'warnings.nowarn',
+            '-Wunused': 'warnings.unused',
+            '-Wuninitialized': 'warnings.uninitialized',
+            '-Wall': 'warnings.allwarn',
+            '-Wextra': 'warnings.extrawarn',
+            '-Wmissing-declarations': 'warnings.missingdeclaration',
+            '-Wconversion': 'warnings.conversion',
+            '-Wpointer-arith': 'warnings.pointerarith',
+            '-Wpadded': 'warnings.padded',
+            '-Wshadow': 'warnings.shadow',
+            '-Wlogical-op': 'warnings.logicalop',
+            '-Waggregate-return': 'warnings.agreggatereturn',
+            '-Wfloat-equal': 'warnings.floatequal',
+            '-Werror': 'warnings.toerrors',
+        }
+
+        for option in warning_options:
+            opts['common'][warning_options[option]] = False
+            if option in flags['common_flags']:
+                opts['common'][warning_options[option]] = True
+                self.remove_option(flags['common_flags'], option)
+
+        # Common debug options.
+        debug_levels = {
+            '-g': 'default',
+            '-g1': 'minimal',
+            '-g3': 'max',
+        }
+        opts['common']['debugging.level'] = 'none'
+        for option in debug_levels:
+            if option in flags['common_flags']:
+                opts['common'][
+                    'debugging.level'] = debug_levels[option]
+                self.remove_option(flags['common_flags'], option)
+
+        debug_formats = {
+            '-ggdb': 'gdb',
+            '-gstabs': 'stabs',
+            '-gstabs+': 'stabsplus',
+            '-gdwarf-2': 'dwarf2',
+            '-gdwarf-3': 'dwarf3',
+            '-gdwarf-4': 'dwarf4',
+            '-gdwarf-5': 'dwarf5',
+        }
+
+        opts['common']['debugging.format'] = ''
+        for option in debug_levels:
+            if option in flags['common_flags']:
+                opts['common'][
+                    'debugging.format'] = debug_formats[option]
+                self.remove_option(flags['common_flags'], option)
+
+        opts['common']['debugging.prof'] = False
+        if '-p' in flags['common_flags']:
+            opts['common']['debugging.prof'] = True
+            self.remove_option(flags['common_flags'], '-p')
+
+        opts['common']['debugging.gprof'] = False
+        if '-pg' in flags['common_flags']:
+            opts['common']['debugging.gprof'] = True
+            self.remove_option(flags['common_flags'], '-gp')
+
+        # Assembler options.
+        opts['as']['usepreprocessor'] = False
+        while '-x' in flags['asm_flags']:
+            ix = flags['asm_flags'].index('-x')
+            str = flags['asm_flags'][ix + 1]
+
+            if str == 'assembler-with-cpp':
+                opts['as']['usepreprocessor'] = True
+            else:
+                # Collect all other assembler options.
+                opts['as']['other'] += ' -x ' + str
+
+            self.remove_option(flags['asm_flags'], '-x')
+            self.remove_option(flags['asm_flags'], 'assembler-with-cpp')
+
+        opts['as']['nostdinc'] = False
+        if '-nostdinc' in flags['asm_flags']:
+            opts['as']['nostdinc'] = True
+            self.remove_option(flags['asm_flags'], '-nostdinc')
+
+        opts['as']['verbose'] = False
+        if '-v' in flags['asm_flags']:
+            opts['as']['verbose'] = True
+            self.remove_option(flags['asm_flags'], '-v')
+
+        # C options.
+        opts['c']['nostdinc'] = False
+        if '-nostdinc' in flags['c_flags']:
+            opts['c']['nostdinc'] = True
+            self.remove_option(flags['c_flags'], '-nostdinc')
+
+        opts['c']['verbose'] = False
+        if '-v' in flags['c_flags']:
+            opts['c']['verbose'] = True
+            self.remove_option(flags['c_flags'], '-v')
+
+        warning_options = {
+            '-Wmissing-prototypes': 'warnings.missingprototypes',
+            '-Wstrict-prototypes': 'warnings.strictprototypes',
+            '-Wbad-function-cast': 'warnings.badfunctioncast',
+        }
+
+        for option in warning_options:
+            opts['c'][warning_options[option]] = False
+            if option in flags['common_flags']:
+                opts['c'][warning_options[option]] = True
+                self.remove_option(flags['common_flags'], option)
+
+        # C++ options.
+        opts['cpp']['nostdinc'] = False
+        if '-nostdinc' in flags['cxx_flags']:
+            opts['cpp']['nostdinc'] = True
+            self.remove_option(flags['cxx_flags'], '-nostdinc')
+
+        opts['cpp']['nostdincpp'] = False
+        if '-nostdinc++' in flags['cxx_flags']:
+            opts['cpp']['nostdincpp'] = True
+            self.remove_option(flags['cxx_flags'], '-nostdinc++')
+
+        optimization_options = {
+            '-fno-exceptions': 'optimization.noexceptions',
+            '-fno-rtti': 'optimization.nortti',
+            '-fno-use-cxa-atexit': 'optimization.nousecxaatexit',
+            '-fno-threadsafe-statics': 'optimization.nothreadsafestatics',
+        }
+
+        for option in optimization_options:
+            opts['cpp'][optimization_options[option]] = False
+            if option in flags['cxx_flags']:
+                opts['cpp'][optimization_options[option]] = True
+                self.remove_option(flags['cxx_flags'], option)
+            if option in flags['common_flags']:
+                opts['cpp'][optimization_options[option]] = True
+                self.remove_option(flags['common_flags'], option)
+
+        warning_options = {
+            '-Wabi': 'warnabi',
+            '-Wctor-dtor-privacy': 'warnings.ctordtorprivacy',
+            '-Wnoexcept': 'warnings.noexcept',
+            '-Wnon-virtual-dtor': 'warnings.nonvirtualdtor',
+            '-Wstrict-null-sentinel': 'warnings.strictnullsentinel',
+            '-Wsign-promo': 'warnings.signpromo',
+            '-Weffc++': 'warneffc',
+        }
+
+        for option in warning_options:
+            opts['cpp'][warning_options[option]] = False
+            if option in flags['cxx_flags']:
+                opts['cpp'][warning_options[option]] = True
+                self.remove_option(flags['cxx_flags'], option)
+            if option in flags['common_flags']:
+                opts['cpp'][warning_options[option]] = True
+                self.remove_option(flags['common_flags'], option)
+
+        opts['cpp']['verbose'] = False
+        if '-v' in flags['cxx_flags']:
+            opts['cpp']['verbose'] = True
+            self.remove_option(flags['cxx_flags'], '-v')
+
+        # Linker options.
+        linker_options = {
+            '-nostartfiles': 'nostart',
+            '-nodefaultlibs': 'nodeflibs',
+            '-nostdlib': 'nostdlibs',
+        }
+
+        for option in linker_options:
+            opts['ld'][linker_options[option]] = False
+            if option in flags['ld_flags']:
+                opts['ld'][linker_options[option]] = True
+                self.remove_option(flags['ld_flags'], option)
+
+        opts['ld']['gcsections'] = False
+        if '-Wl,--gc-sections' in flags['ld_flags']:
+            opts['ld']['gcsections'] = True
+            self.remove_option(flags['ld_flags'], '-Wl,--gc-sections')
+
+        opts['ld']['flags'] = []
+        to_remove = []
+        for opt in flags['ld_flags']:
+            if opt.startswith('-Wl,--wrap,'):
+                opts['ld']['flags'].append(
+                    '--wrap=' + opt[len('-Wl,--wrap,'):])
+                to_remove.append(opt)
+        for opt in to_remove:
+            self.remove_option(flags['ld_flags'], opt)
+
+        # Other tool remaining options are separated by category.
+        opts['as']['otherwarnings'] = self.find_options(
+            flags['asm_flags'], '-W')
+
+        opts['c']['otherwarnings'] = self.find_options(
+            flags['c_flags'], '-W')
+        opts['c']['otheroptimizations'] = self.find_options(flags[
+            'c_flags'], '-f')
+
+        opts['cpp']['otherwarnings'] = self.find_options(
+            flags['cxx_flags'], '-W')
+        opts['cpp']['otheroptimizations'] = self.find_options(
+            flags['cxx_flags'], '-f')
+
+        # Other common remaining options are separated by category.
+        opts['common']['optimization.other'] = self.find_options(
+            flags['common_flags'], '-f')
+        opts['common']['warnings.other'] = self.find_options(
+            flags['common_flags'], '-W')
+
+        # Remaining common flags are added to each tool.
+        opts['as']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + \
+            ' '.join(flags['asm_flags'])
+        opts['c']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + ' '.join(flags['c_flags'])
+        opts['cpp']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + \
+            ' '.join(flags['cxx_flags'])
+        opts['ld']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + ' '.join(flags['ld_flags'])
+
+        if len(self.system_libraries) > 0:
+            opts['ld']['other'] += ' -Wl,--start-group '
+            opts['ld'][
+                'other'] += ' '.join('-l' + s for s in self.system_libraries)
+            opts['ld']['other'] += ' -Wl,--end-group '
+
+        # Strip all 'other' flags, since they might have leading spaces.
+        opts['as']['other'] = opts['as']['other'].strip()
+        opts['c']['other'] = opts['c']['other'].strip()
+        opts['cpp']['other'] = opts['cpp']['other'].strip()
+        opts['ld']['other'] = opts['ld']['other'].strip()
+
+        if False:
+            print
+            print opts
+
+            print
+            print 'common_flags', flags['common_flags']
+            print 'asm_flags', flags['asm_flags']
+            print 'c_flags', flags['c_flags']
+            print 'cxx_flags', flags['cxx_flags']
+            print 'ld_flags', flags['ld_flags']
+
+    @staticmethod
+    def find_options(lst, option):
+        tmp = [str for str in lst if str.startswith(option)]
+        if len(tmp) > 0:
+            return tmp[0]
+        else:
+            return None
+
+    @staticmethod
+    def find_options(lst, prefix):
+        other = ''
+        opts = [str for str in lst if str.startswith(prefix)]
+        if len(opts) > 0:
+            for opt in opts:
+                other += ' ' + opt
+                GNUARMEclipse.remove_option(lst, opt)
+        return other.strip()
+
+    @staticmethod
+    def remove_option(lst, option):
+        if option in lst:
+            lst.remove(option)
+
+# =============================================================================
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/__init__.pyc
new file mode 100755
index 0000000..202fa6d
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/makefile.targets.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/makefile.targets.tmpl
new file mode 100755
index 0000000..af439f2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/makefile.targets.tmpl
@@ -0,0 +1,13 @@
+# DO NOT REMOVE! Generated by the GNU ARM Eclipse exporter from an mBed project.
+
+mbedclean:
+	$(RM) $(OBJS)
+	$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
+	$(RM) $(SECONDARY_FLASH)$(SECONDARY_SIZE) {{name}}.* linker-script-*.ld
+	-@echo ' '
+
+{% for config, data in options.iteritems() %}
+linker-script-{{config}}.ld: ../{{ld_script}}
+	{{data.cpp_cmd}} {{data.ld.other}} $< -o $@
+{{name}}.elf: linker-script-{{config}}.ld
+{% endfor %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/mbedignore.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/mbedignore.tmpl
new file mode 100755
index 0000000..175b967
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/gnuarmeclipse/mbedignore.tmpl
@@ -0,0 +1,3 @@
+{%- for config in options.values() -%}
+{{config.name}}/*
+{% endfor -%}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/__init__.py
new file mode 100755
index 0000000..641c142
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/__init__.py
@@ -0,0 +1,197 @@
+import os
+from os.path import sep, join, exists
+from collections import namedtuple
+from subprocess import Popen, PIPE
+import shutil
+import re
+import sys
+
+from tools.targets import TARGET_MAP
+from tools.export.exporters import Exporter, TargetNotSupportedException
+import json
+from tools.export.cmsis import DeviceCMSIS
+from tools.utils import NotSupportedException
+from multiprocessing import cpu_count
+
+
+def _supported(mcu, iar_targets):
+    if "IAR" not in mcu.supported_toolchains:
+        return False
+    if hasattr(mcu, 'device_name') and mcu.device_name in iar_targets:
+        return True
+    if mcu.name in iar_targets:
+        return True
+    return False
+
+
+_iar_defs = os.path.join(
+    os.path.dirname(os.path.abspath(__file__)), 'iar_definitions.json')
+
+with open(_iar_defs, 'r') as f:
+    _GUI_OPTIONS = json.load(f)
+
+
+class IAR(Exporter):
+    NAME = 'iar'
+    TOOLCHAIN = 'IAR'
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return _supported(target, _GUI_OPTIONS.keys())
+
+
+    def iar_groups(self, grouped_src):
+        """Return a namedtuple of group info
+        Positional Arguments:
+        grouped_src: dictionary mapping a group(str) to sources
+            within it (list of file names)
+        Relevant part of IAR template
+        {% for group in groups %}
+	    <group>
+	        <name>group.name</name>
+	        {% for file in group.files %}
+	        <file>
+	        <name>$PROJ_DIR${{file}}</name>
+	        </file>
+	        {% endfor %}
+	    </group>
+	    {% endfor %}
+        """
+        IARgroup = namedtuple('IARgroup', ['name','files'])
+        groups = []
+        for name, files in grouped_src.items():
+            groups.append(IARgroup(name,files))
+        return groups
+
+    def iar_device(self):
+        """Retrieve info from iar_definitions.json"""
+        tgt = TARGET_MAP[self.target]
+        device_name = (tgt.device_name if hasattr(tgt, "device_name") else
+                       tgt.name)
+        device_info = _GUI_OPTIONS[device_name]
+        iar_defaults ={
+            "OGChipSelectEditMenu": "",
+            "CoreVariant": '',
+            "GFPUCoreSlave": '',
+            "GFPUCoreSlave2": 40,
+            "GBECoreSlave": 35,
+            "GBECoreSlave2": '',
+            "FPU2": 0,
+            "NrRegs": 0,
+            "NEON": '',
+            "CExtraOptionsCheck": 0,
+            "CExtraOptions": "",
+            "CMSISDAPJtagSpeedList": 0,
+        }
+
+        iar_defaults.update(device_info)
+        IARdevice = namedtuple('IARdevice', iar_defaults.keys())
+        return IARdevice(**iar_defaults)
+
+    def format_file(self, file):
+        """Make IAR compatible path"""
+        return join('$PROJ_DIR$',file)
+
+    def format_src(self, srcs):
+        """Group source files"""
+        grouped = self.group_project_files(srcs)
+        for group, files in grouped.items():
+            grouped[group] = [self.format_file(src) for src in files]
+        return grouped
+
+    def generate(self):
+        """Generate the .eww, .ewd, and .ewp files"""
+        if not self.resources.linker_script:
+            raise NotSupportedException("No linker script found.")
+        srcs = self.resources.headers + self.resources.s_sources + \
+               self.resources.c_sources + self.resources.cpp_sources + \
+               self.resources.objects + self.resources.libraries
+        flags = self.flags
+        c_flags = list(set(flags['common_flags']
+                                    + flags['c_flags']
+                                    + flags['cxx_flags']))
+        # Flags set in template to be set by user in IDE
+        template = ["--vla", "--no_static_destruction"]
+        # Flag invalid if set in template
+        # Optimizations are also set in template
+        invalid_flag = lambda x: x in template or re.match("-O(\d|time|n|hz?)", x)
+        flags['c_flags'] = [flag for flag in c_flags if not invalid_flag(flag)]
+
+        try:
+            debugger = DeviceCMSIS(self.target).debug.replace('-','').upper()
+        except TargetNotSupportedException:
+            debugger = "CMSISDAP"
+
+        ctx = {
+            'name': self.project_name,
+            'groups': self.iar_groups(self.format_src(srcs)),
+            'linker_script': self.format_file(self.resources.linker_script),
+            'include_paths': [self.format_file(src) for src in self.resources.inc_dirs],
+            'device': self.iar_device(),
+            'ewp': sep+self.project_name + ".ewp",
+            'debugger': debugger
+        }
+        ctx.update(flags)
+
+        self.gen_file('iar/eww.tmpl', ctx, self.project_name + ".eww")
+        self.gen_file('iar/ewd.tmpl', ctx, self.project_name + ".ewd")
+        self.gen_file('iar/ewp.tmpl', ctx, self.project_name + ".ewp")
+
+    @staticmethod
+    def build(project_name, log_name="build_log.txt", cleanup=True):
+        """ Build IAR project """
+        # > IarBuild [project_path] -build [project_name]
+        proj_file = project_name + ".ewp"
+        cmd = ["IarBuild", proj_file, '-build', project_name]
+
+        # IAR does not support a '0' option to automatically use all
+        # available CPUs, so we use Python's multiprocessing library
+        # to detect the number of CPUs available
+        cpus_available = cpu_count()
+        jobs = cpus_available if cpus_available else None
+
+        # Only add the parallel flag if we're using more than one CPU
+        if jobs:
+            cmd += ['-parallel', str(jobs)]
+
+        # Build the project
+        p = Popen(cmd, stdout=PIPE, stderr=PIPE)
+        out, err = p.communicate()
+        ret_code = p.returncode
+
+        out_string = "=" * 10 + "STDOUT" + "=" * 10 + "\n"
+        out_string += out
+        out_string += "=" * 10 + "STDERR" + "=" * 10 + "\n"
+        out_string += err
+
+        if ret_code == 0:
+            out_string += "SUCCESS"
+        else:
+            out_string += "FAILURE"
+
+        print out_string
+
+        if log_name:
+            # Write the output to the log file
+            with open(log_name, 'w+') as f:
+                f.write(out_string)
+
+        # Cleanup the exported and built files
+        if cleanup:
+            os.remove(project_name + ".ewp")
+            os.remove(project_name + ".ewd")
+            os.remove(project_name + ".eww")
+            # legacy output file location
+            if exists('.build'):
+                shutil.rmtree('.build')
+            if exists('BUILD'):
+                shutil.rmtree('BUILD')
+
+        if ret_code !=0:
+            # Seems like something went wrong.
+            return -1
+        else:
+            return 0
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/__init__.pyc
new file mode 100755
index 0000000..5f004ab
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/ewd.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/ewd.tmpl
new file mode 100755
index 0000000..debef36
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/ewd.tmpl
@@ -0,0 +1,1638 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>{{name}}</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>{{device.CExtraOptionsCheck}}</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state>{{device.CExtraOptions}}</state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>7.70.1.11471</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>{{debugger}}_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>7.70.1.11471</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDebuggerExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAllMTBOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreNrOfCores</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreMaster</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCMulticorePort</name>
+          <state>53461</state>
+        </option>
+        <option>
+          <name>OCMulticoreWorkspace</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveProject</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveConfiguration</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadExtraImage</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAttachSlave</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CADI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCadiMemory</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Fast Model</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCADILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCADILogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CMSISDAP_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>4</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>CMSISDAPDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPJtagSpeedList</name>
+          <version>0</version>
+          <state>{{device.CMSISDAPJtagSpeedList}}</state>
+        </option>
+        <option>
+          <name>CMSISDAPBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSFERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CMSISDAPProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCCMSISDAPUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCMSISDAPUsbSerialNoSelect</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSFERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPreferETB</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetTraceSettingsList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetTraceSizeList</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>FlashBoardPathSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIjetUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCIjetUsbSerialNoSelect</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>5</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSFERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkDeviceName</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCSTLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchSFERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCSTLinkUsbSerialNoSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkDAPNumber</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>TIFET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCMSPFetResetList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetTargetVccTypeDefault</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetTargetVoltage</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CCMSPFetVCCDefault</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCMSPFetTargetSettlingtime</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetRadioJtagSpeedType</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCMSPFetConnection</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetUsbComPort</name>
+          <state>Automatic</state>
+        </option>
+        <option>
+          <name>CCMSPFetAllowAccessToBSL</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMSPFetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCMSPFetRadioEraseFlash</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>5</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCXds100BreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100DoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100UpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCXds100CatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchSFERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100CpuClockEdit</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100SwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100SwoClockEdit</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCXds100HWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100ResetList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100UsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100UsbSerialNoSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100JtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceRadio</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCXds100ProbeList</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/ewp.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/ewp.tmpl
new file mode 100755
index 0000000..cf5b7f0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/ewp.tmpl
@@ -0,0 +1,976 @@
+<?xml version="1.0" encoding="utf-8"?>
+<project>
+	<fileVersion>2</fileVersion>
+	<configuration>
+		<name>{{name}}</name>
+		<toolchain>
+			<name>ARM</name>
+		</toolchain>
+		<debug>1</debug>
+		<settings>
+			<name>General</name>
+			<archiveVersion>3</archiveVersion>
+      <data>
+        <version>24</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ExePath</name>
+          <state>$PROJ_DIR$\BUILD\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>$PROJ_DIR$\BUILD\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>$PROJ_DIR$\BUILD\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>No specifier a, A.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.0.159</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.80.2.11970</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>{{device.OGChipSelectEditMenu}}</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>24</version>
+          <state>{{device.GBECoreSlave}}</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>24</version>
+          <state>{{device.CoreVariant}}</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>{{device.FPU2}}</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>{{device.NrRegs}}</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>{{device.NEON}}</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>24</version>
+          <state>{{device.GFPUCoreSlave2}}</state>
+        </option>
+      </data>
+		</settings>
+		<settings>
+			<name>ICCARM</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>31</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>CCOptimizationNoSizeConstraints</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCDefines</name>
+					<state></state>
+				</option>
+				<option>
+					<name>CCPreprocFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCPreprocComments</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCPreprocLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListCFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListCMnemonics</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListCMessages</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListAssFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListAssSource</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCEnableRemarks</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCDiagSuppress</name>
+					<state>Pa050,Pa084,Pa093,Pa082</state>
+				</option>
+				<option>
+					<name>CCDiagRemark</name>
+					<state></state>
+				</option>
+				<option>
+					<name>CCDiagWarning</name>
+					<state></state>
+				</option>
+				<option>
+					<name>CCDiagError</name>
+					<state></state>
+				</option>
+				<option>
+					<name>CCObjPrefix</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCAllowList</name>
+					<version>1</version>
+					<state>1111110</state>
+				</option>
+				<option>
+					<name>CCDebugInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IEndianMode</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IProcessor</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IExtraOptionsCheck</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IExtraOptions</name>
+					{% for flag in c_flags %}
+					<state>{{flag}}</state>
+					{% endfor %}
+				</option>
+				<option>
+					<name>CCLangConformance</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSignedPlainChar</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCRequirePrototypes</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMultibyteSupport</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCDiagWarnAreErr</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCompilerRuntimeInfo</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IFpuProcessor</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OutputFile</name>
+					<state>$FILE_BNAME$.o</state>
+				</option>
+				<option>
+					<name>CCLibConfigHeader</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>PreInclude</name>
+					<state></state>
+				</option>
+				<option>
+					<name>CompilerMisraOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCIncludePath2</name>
+					{% for file in include_paths %}
+					<state>{{file}}</state>
+					{% endfor %}
+				</option>
+				<option>
+					<name>CCStdIncCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCodeSection</name>
+					<state>.text</state>
+				</option>
+				<option>
+					<name>IInterwork2</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IProcessorMode2</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCOptLevel</name>
+					<state>3</state>
+				</option>
+				<option>
+					<name>CCOptStrategy</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCOptLevelSlave</name>
+					<state>3</state>
+				</option>
+				<option>
+					<name>CompilerMisraRules98</name>
+					<version>0</version>
+					<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+				</option>
+				<option>
+					<name>CompilerMisraRules04</name>
+					<version>0</version>
+					<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+				</option>
+				<option>
+					<name>CCPosIndRopi</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCPosIndRwpi</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCPosIndNoDynInit</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IccLang</name>
+					<state>2</state>
+				</option>
+				<option>
+					<name>IccCDialect</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IccAllowVLA</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IccCppDialect</name>
+					<state>2</state>
+				</option>
+				<option>
+					<name>IccExceptions</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IccRTTI</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IccStaticDestr</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IccCppInlineSemantics</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IccCmsis</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IccFloatSemantics</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCNoLiteralPool</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCOptStrategySlave</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCGuardCalls</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>AARM</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>9</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>AObjPrefix</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AEndian</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>ACaseSensitivity</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>MacroChars</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AWarnEnable</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AWarnWhat</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AWarnOne</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AWarnRange1</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AWarnRange2</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ADebug</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AltRegisterNames</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ADefines</name>
+					<state></state>
+				</option>
+				<option>
+					<name>AList</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AListHeader</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AListing</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>Includes</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MacDefs</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MacExps</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>MacExec</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OnlyAssed</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MultiLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>PageLengthCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>PageLength</name>
+					<state>80</state>
+				</option>
+				<option>
+					<name>TabSpacing</name>
+					<state>8</state>
+				</option>
+				<option>
+					<name>AXRef</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AXRefDefines</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AXRefInternal</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AXRefDual</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AProcessor</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AFpuProcessor</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AOutputFile</name>
+					<state>$FILE_BNAME$.o</state>
+				</option>
+				<option>
+					<name>AMultibyteSupport</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ALimitErrorsCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ALimitErrorsEdit</name>
+					<state>100</state>
+				</option>
+				<option>
+					<name>AIgnoreStdInclude</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AUserIncludes</name>
+					<state></state>
+				</option>
+				<option>
+					<name>AExtraOptionsCheckV2</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AExtraOptionsV2</name>
+					{% for flag in asm_flags %}
+					<state>{{flag}}</state>
+					{% endfor %}
+				</option>
+				<option>
+					<name>AsmNoLiteralPool</name>
+					<state>0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>OBJCOPY</name>
+			<archiveVersion>0</archiveVersion>
+			<data>
+				<version>1</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OOCOutputFormat</name>
+					<version>2</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCOutputOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OOCOutputFile</name>
+					<state>name.srec</state>
+				</option>
+				<option>
+					<name>OOCCommandLineProducer</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OOCObjCopyEnable</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>CUSTOM</name>
+			<archiveVersion>3</archiveVersion>
+			<data>
+				<extensions></extensions>
+				<cmdline></cmdline>
+			</data>
+		</settings>
+		<settings>
+			<name>BICOMP</name>
+			<archiveVersion>0</archiveVersion>
+			<data></data>
+		</settings>
+		<settings>
+			<name>BUILDACTION</name>
+			<archiveVersion>1</archiveVersion>
+			<data>
+				<prebuild></prebuild>
+				<postbuild></postbuild>
+			</data>
+		</settings>
+		<settings>
+			<name>ILINK</name>
+			<archiveVersion>0</archiveVersion>
+			<data>
+				<version>16</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>IlinkOutputFile</name>
+					<state>name.out</state>
+				</option>
+				<option>
+					<name>IlinkLibIOConfig</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>XLinkMisraHandler</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkInputFileSlave</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkDebugInfoEnable</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkKeepSymbols</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkRawBinaryFile</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkRawBinarySymbol</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkRawBinarySegment</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkRawBinaryAlign</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkDefines</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkConfigDefines</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkMapFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogInitialization</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogModule</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogSection</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogVeneer</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkIcfOverride</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkIcfFile</name>
+					<state>{{linker_script}}</state>
+				</option>
+				<option>
+					<name>IlinkIcfFileSlave</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkEnableRemarks</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkSuppressDiags</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkTreatAsRem</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkTreatAsWarn</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkTreatAsErr</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkWarningsAreErrors</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkUseExtraOptions</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkExtraOptions</name>
+					{% for flag in ld_flags %}
+					<state>{{flag}}</state>
+					{% endfor %}
+				</option>
+				<option>
+					<name>IlinkLowLevelInterfaceSlave</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkAutoLibEnable</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkAdditionalLibs</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkOverrideProgramEntryLabel</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkProgramEntryLabelSelect</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkProgramEntryLabel</name>
+					<state>__iar_program_start</state>
+				</option>
+				<option>
+					<name>DoFill</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>FillerByte</name>
+					<state>0xFF</state>
+				</option>
+				<option>
+					<name>FillerStart</name>
+					<state>0x0</state>
+				</option>
+				<option>
+					<name>FillerEnd</name>
+					<state>0x0</state>
+				</option>
+				<option>
+					<name>CrcSize</name>
+					<version>0</version>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcAlign</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcPoly</name>
+					<state>0x11021</state>
+				</option>
+				<option>
+					<name>CrcCompl</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CrcBitOrder</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CrcInitialValue</name>
+					<state>0x0</state>
+				</option>
+				<option>
+					<name>DoCrc</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkBE8Slave</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkBufferedTerminalOutput</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkStdoutInterfaceSlave</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcFullSize</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkIElfToolPostProcess</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogAutoLibSelect</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogRedirSymbols</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkLogUnusedFragments</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkCrcReverseByteOrder</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkCrcUseAsInput</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkOptInline</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkOptExceptionsAllow</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkOptExceptionsForce</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkCmsis</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkOptMergeDuplSections</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkOptUseVfe</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IlinkOptForceVfe</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkStackAnalysisEnable</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkStackControlFile</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IlinkStackCallGraphFile</name>
+					<state></state>
+				</option>
+				<option>
+					<name>CrcAlgorithm</name>
+					<version>0</version>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcUnitSize</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IlinkThreadsSlave</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>IARCHIVE</name>
+			<archiveVersion>0</archiveVersion>
+			<data>
+				<version>0</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>IarchiveInputs</name>
+					<state></state>
+				</option>
+				<option>
+					<name>IarchiveOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IarchiveOutput</name>
+					<state>###Unitialized###</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>BILINK</name>
+			<archiveVersion>0</archiveVersion>
+			<data></data>
+		</settings>
+	</configuration>
+	{% for group in groups %}
+	<group>
+	    <name>{{group.name}}</name>
+	    {% for file in group.files %}
+	    <file>
+	        <name>{{file}}</name>
+	    </file>
+	    {% endfor %}
+	</group>
+	{% endfor %}
+</project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/eww.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/eww.tmpl
new file mode 100755
index 0000000..6f51c62
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/eww.tmpl
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="utf-8"?>
+<workspace>
+	<project>
+		<path>$WS_DIR${{ewp}}</path>
+	</project>
+	<batchBuild></batchBuild>
+</workspace>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/iar_definitions.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/iar_definitions.json
new file mode 100755
index 0000000..461daa5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/iar/iar_definitions.json
@@ -0,0 +1,241 @@
+{
+    "STM32L476VG": {
+        "OGChipSelectEditMenu": "STM32L476VG\tST STM32L476VG"
+    },
+    "LPC11U24FBD48/401": {
+        "OGChipSelectEditMenu": "LPC11U24FBD64_401\tNXP LPC11U24FBD64_401"
+    },
+    "STM32F207ZG": {
+         "OGChipSelectEditMenu": "STM32F207ZG\tST STM32F207ZG"
+    },
+    "STM32F334R8": {
+        "OGChipSelectEditMenu": "STM32F334x8\tST STM32F334x8"
+    },
+    "STM32F302R8": {
+        "OGChipSelectEditMenu": "STM32F302x8\tST STM32F302x8"
+    },
+    "EFM32LG990F256": {
+        "OGChipSelectEditMenu": "EFM32LG990F256\tSiliconLaboratories EFM32LG990F256"
+    },
+    "STM32F042K6": {
+        "OGChipSelectEditMenu": "STM32F042x6\tST STM32F042x6"
+    },
+    "STM32L476RG": {
+        "OGChipSelectEditMenu": "STM32L476RG\tST STM32L476RG"
+    },
+    "STM32L486RG": {
+        "OGChipSelectEditMenu": "STM32L486RG\tST STM32L486RG"
+    },
+    "STM32L476JG": {
+        "OGChipSelectEditMenu": "STM32L476JG\tST STM32L476JG"
+    },
+    "STM32L011K4": {
+        "OGChipSelectEditMenu": "STM32L011x4\tST STM32L011x4"
+    },
+    "EFM32WG990F256": {
+        "OGChipSelectEditMenu": "EFM32WG990F256\tSiliconLaboratories EFM32WG990F256"
+    },
+    "STM32F401RE": {
+        "OGChipSelectEditMenu": "STM32F401xE\tST STM32F401xE"
+    },
+    "STM32F070RB": {
+        "OGChipSelectEditMenu": "STM32F070RB\tST STM32F070RB"
+    },
+    "MK22DN512xxx5": {
+        "OGChipSelectEditMenu": "MK22DN512xxx5\tNXP MK22DN512xxx5"
+    },
+    "MK24FN1M0xxx12": {
+        "OGChipSelectEditMenu": "MK24FN1M0xxx12\tNXP MK24FN1M0xxx12"
+    },
+    "MK64FN1M0xxx12": {
+        "OGChipSelectEditMenu": "MK64FN1M0xxx12\tNXP MK64FN1M0xxx12"
+    },
+    "MK66FN2M0xxx18": {
+        "OGChipSelectEditMenu": "MK66FN2M0xxx18\tNXP MK66FN2M0xxx18"
+    },
+    "MK82FN256xxx15": {
+        "OGChipSelectEditMenu": "MK82FN256xxx15\tNXP MK82FN256xxx15"
+    },
+    "MKL27Z64xxx4": {
+        "OGChipSelectEditMenu": "MKL27Z64xxx4\tNXP MKL27Z64xxx4"
+    },
+    "MKL43Z256xxx4": {
+        "OGChipSelectEditMenu": "MKL43Z256xxx4\tNXP MKL43Z256xxx4"
+    },
+    "MKL82Z128xxx7": {
+        "OGChipSelectEditMenu": "MKL82Z128xxx7\tNXP MKL82Z128xxx7"
+    },
+    "MKW24D512xxx5": {
+        "OGChipSelectEditMenu": "MKW24D512xxx5\tNXP MKW24D512xxx5"
+    },
+    "MKW41Z512xxx4": {
+        "OGChipSelectEditMenu": "MKW41Z512xxx4\tNXP MKW41Z512xxx4"
+    },
+    "LPC54114J256BD64": {
+        "OGChipSelectEditMenu": "LPC54114J256_M4\tNXP LPC54114J256_M4"
+    },
+    "LPC54618J512ET180": {
+        "OGChipSelectEditMenu": "LPC54618J512\tNXP LPC54618J512"
+    },
+    "STM32F072RB": {
+        "OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB"
+    },
+    "nRF51822_xxAA": {
+        "OGChipSelectEditMenu": "nRF51822-QFAA\tNordicSemi nRF51822-QFAA",
+        "CExtraOptionsCheck": 1,
+        "CExtraOptions": "--drv_vector_table_base=0x0",
+        "CMSISDAPJtagSpeedList": 10
+    },
+    "EFM32GG990F1024": {
+        "OGChipSelectEditMenu": "EFM32GG990F1024\tSiliconLaboratories EFM32GG990F1024"
+    },
+    "MKL46Z256xxx4": {
+        "OGChipSelectEditMenu": "MKL46Z256xxx4\tFreescale MKL46Z256xxx4"
+    },
+    "STM32F030R8": {
+        "OGChipSelectEditMenu": "STM32F030x8\tST STM32F030x8"
+    },
+    "EFM32ZG222F32": {
+        "OGChipSelectEditMenu": "EFM32ZG220F32\tSiliconLaboratories EFM32ZG220F32"
+    },
+    "STM32F303RE": {
+        "OGChipSelectEditMenu": "STM32F303xE\tST STM32F303xE"
+    },
+    "STM32L152RE": {
+        "OGChipSelectEditMenu": "STM32L152xE\tST STM32L152xE"
+    },
+    "STM32F439ZI": {
+        "OGChipSelectEditMenu": "STM32F439ZI\tST STM32F439ZI"
+    },
+    "LPC1768": {
+        "OGChipSelectEditMenu": "LPC1768\tNXP LPC1768"
+    },
+    "LPC1769": {
+        "OGChipSelectEditMenu": "LPC1769\tNXP LPC1769"
+    },
+    "STM32F446RE": {
+        "OGChipSelectEditMenu": "STM32F446RE\tST STM32F446RE"
+    },
+    "STM32L072CZ": {
+        "OGChipSelectEditMenu": "STM32L072CZ\tST STM32L072CZ"
+    },
+    "STM32L073RZ": {
+        "OGChipSelectEditMenu": "STM32L073RZ\tST STM32L073RZ"
+    },
+    "STM32F746ZG": {
+        "OGChipSelectEditMenu": "STM32F746ZG\tST STM32F746ZG",
+        "GBECoreSlave": 41,
+        "CoreVariant": 41,
+        "FPU2": 6,
+        "NrRegs": 1
+    },
+    "STM32F767ZI": {
+        "OGChipSelectEditMenu": "STM32F767ZI\tST STM32F767ZI",
+        "GBECoreSlave": 41,
+        "CoreVariant": 41,
+        "FPU2": 7,
+        "NrRegs": 1
+    },
+    "MKL43Z256xxx4": {
+        "OGChipSelectEditMenu": "MKL43Z256xxx4\tFreescale MKL43Z256xxx4"
+    },
+    "LPC812M101JDH20": {
+        "OGChipSelectEditMenu": "LPC812M101\tNXP LPC812M101"
+    },
+    "STM32F746NG": {
+        "OGChipSelectEditMenu": "STM32F746NG\tST STM32F746NG",
+        "GBECoreSlave": 41,
+        "CoreVariant": 41,
+        "FPU2": 6,
+        "NrRegs": 1
+    },
+    "STM32F411RE": {
+        "OGChipSelectEditMenu": "STM32F411RE\tST STM32F411RE"
+    },
+    "STM32L053C8": {
+        "OGChipSelectEditMenu": "STM32L053x8\tST STM32L053x8"
+    },
+    "STM32L031K6": {
+        "OGChipSelectEditMenu": "STM32L031x6\tST STM32L031x6"
+    },
+    "EFM32HG322F64": {
+        "OGChipSelectEditMenu": "EFM32HG322F64\tSiliconLaboratories EFM32HG322F64"
+    },
+    "MK20DX256xxx7": {
+        "OGChipSelectEditMenu": "MK20DX256xxx7\tFreescale MK20DX256xxx7"
+    },
+    "STM32F446ZE": {
+        "OGChipSelectEditMenu": "STM32F446ZE\tST STM32F446ZE"
+    },
+    "MK22DN512xxx5": {
+        "OGChipSelectEditMenu": "MK22FN512xxx12\tFreescale MK22FN512xxx12"
+    },
+    "STM32F303K8": {
+        "OGChipSelectEditMenu": "STM32F303x8\tST STM32F303x8"
+    },
+    "STM32F405RG": {
+        "OGChipSelectEditMenu": "STM32F405RG\tST STM32F405RG"
+    },
+    "MK20DX128xxx5": {
+        "OGChipSelectEditMenu": "MK20DX128xxx5\tFreescale MK20DX128xxx5"
+    },
+    "MKL25Z128xxx4": {
+        "OGChipSelectEditMenu": "MKL25Z128xxx4\tFreescale MKL25Z128xxx4"
+    },
+    "STM32F429ZI": {
+        "OGChipSelectEditMenu": "STM32F429ZI\tST STM32F429ZI"
+    },
+    "STM32F103RB": {
+        "OGChipSelectEditMenu": "STM32F103xB\tST STM32F103xB"
+    },
+    "STM32F091RC": {
+        "OGChipSelectEditMenu": "STM32F091RC\tST STM32F091RC"
+    },
+    "RZ_A1H": {
+        "OGChipSelectEditMenu": "R7S721001\tRenesas R7S721001",
+        "CoreVariant": 37,
+        "GFPUCoreSlave": 37,
+        "GBECoreSlave": 37,
+        "NEON":1
+    },
+    "VK_RZ_A1H": {
+        "OGChipSelectEditMenu": "R7S721000\tRenesas R7S721000",
+        "CoreVariant": 37,
+        "GFPUCoreSlave": 37,
+        "GBECoreSlave": 37,
+        "NEON":1
+    },
+    "MKL05Z32xxx4": {
+        "OGChipSelectEditMenu": "MKL05Z32xxx4\tFreescale MKL05Z32xxx4"
+    },
+    "STM32F031K6": {
+        "OGChipSelectEditMenu": "STM32F031x6\tST STM32F031x6"
+    },
+    "MAX32600MBED": {
+        "OGChipSelectEditMenu": "MAX32600x85\tMaxim MAX32600x85"
+    },
+    "STM32F407VG": {
+        "OGChipSelectEditMenu": "STM32F407VG\tST STM32F407VG"
+    },
+    "nRF52832_xxAA":{
+        "OGChipSelectEditMenu": "nRF52832-xxAA\tNordicSemi nRF52832-xxAA",
+        "CExtraOptionsCheck": 1,
+        "CExtraOptions": "--drv_vector_table_base=0x0",
+        "CMSISDAPJtagSpeedList": 10
+    },
+    "NCS36510":{
+        "OGChipSelectEditMenu": "NCS36510\tONSemiconductor NCS36510"
+    },
+    "NUC472HI8AE": {
+        "OGChipSelectEditMenu": "NUC400AE series\tNuvoton NUC400AE series (NUC442AE,NUC472AE)"
+    },
+    "M453VG6AE": {
+        "OGChipSelectEditMenu": "M451AE series\tNuvoton M451AE series (M451AE,M452AE,M453AE,M451MAE)"
+    },
+    "nRF52840_xxAA":{
+        "OGChipSelectEditMenu": "nRF52840_xxAA\tNordicSemi nRF52840_xxAA",
+        "CExtraOptionsCheck": 1,
+        "CExtraOptions": "--drv_vector_table_base=0x0",
+        "CMSISDAPJtagSpeedList": 10
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/__init__.py
new file mode 100755
index 0000000..6df777a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/__init__.py
@@ -0,0 +1,49 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import splitext, basename
+
+from tools.export.exporters import Exporter, deprecated_exporter
+
+
+@deprecated_exporter
+class KDS(Exporter):
+    NAME = 'Kinetis Design Studio'
+    TOOLCHAIN = 'GCC_ARM'
+
+    TARGETS = [
+        'K64F',
+        'HEXIWEAR',
+        'K22F',
+    ]
+
+    def generate(self):
+        libraries = []
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            libraries.append(l[3:])
+
+        ctx = {
+            'name': self.project_name,
+            'include_paths': self.resources.inc_dirs,
+            'linker_script': self.resources.linker_script,
+            'object_files': self.resources.objects,
+            'libraries': libraries,
+            'symbols': self.toolchain.get_symbols()
+        }
+        self.gen_file('kds/%s_project.tmpl' % self.target.lower(), ctx, '.project')
+        self.gen_file('kds/%s_cproject.tmpl' % self.target.lower(), ctx, '.cproject')
+        self.gen_file('kds/launch.tmpl', ctx, '%s.launch' % self.project_name)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/__init__.pyc
new file mode 100755
index 0000000..6f80d01
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/hexiwear_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/hexiwear_cproject.tmpl
new file mode 100755
index 0000000..18aa0fb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/hexiwear_cproject.tmpl
@@ -0,0 +1,306 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1221610645" name="Cross ARM GCC" nonInternalBuilderId="ilg.gnuarmeclipse.managedbuild.cross.builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1271983492" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1681866628" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1550050553" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2126138943" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1492840277" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1058622512" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1583945235" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.gdb" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1089911925" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.77844367" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.softfp" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.353876552" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1308049896" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="Custom" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.560926624" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.660978974" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1169416449" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1545312724" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.2106299868" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.880150025" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.1449434602" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1638755745" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1500383066" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1422858690" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.1453349108" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.918192766" name="Disable builtin (-fno-builtin)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other.845411621" name="Other debugging flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other" value="" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.2076910080" name="Generate prof information (-p)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.1002876099" name="Generate gprof information (-pg)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.371856963" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.2090214221" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/{{name}}}/Debug" cleanBuildTarget="clean" command="${cross_make}" id="org.eclipse.cdt.build.core.internal.builder.2045347460" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.774448198" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.874144438" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1457752231" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.1240528565" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.645447748" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.655157579" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1298012181" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.26057600" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1551083554" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1601945676" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.73762833" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.1541205451" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.2072412260" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.default" valueType="enumerated"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1882430856" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.339583643" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1999194416" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+					<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.344980185" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.727573047" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+								{% if libraries %}
+									{% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                {% endif %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.828171482" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/{{linker_script}}}"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.310068762" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+                                    {% for lib in libraries %}
+                                    <listOptionValue builtIn="false" value="{{lib}}"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.460736806" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.30848869" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs" valueType="string"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1081415325" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1216251638" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1820796904" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.70927688" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.721327636" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.625552450" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.263758416" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1024069673" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1043375284" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1671601569" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.171400698" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1102568395" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787" name="Release" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release.765163102" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1271983492" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.size" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1681866628" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1550050553" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2126138943" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1492840277" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1058622512" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1583945235" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.gdb" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1089911925" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.77844367" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.softfp" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.353876552" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1308049896" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="Custom" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.560926624" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.660978974" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1169416449" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1545312724" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.2106299868" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.880150025" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.1449434602" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1638755745" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1500383066" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1422858690" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.1453349108" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.918192766" name="Disable builtin (-fno-builtin)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other.845411621" name="Other debugging flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other" value="" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.2076910080" name="Generate prof information (-p)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.1002876099" name="Generate gprof information (-pg)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.371856963" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.2090214221" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/{{name}}}/Debug" cleanBuildTarget="clean" command="${cross_make}" id="org.eclipse.cdt.build.core.internal.builder.2045347460" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.774448198" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.874144438" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1457752231" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.1240528565" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.645447748" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.655157579" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1298012181" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.26057600" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1551083554" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1601945676" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.73762833" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.1541205451" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.2072412260" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.default" valueType="enumerated"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1882430856" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.339583643" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1999194416" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+					<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.344980185" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.727573047" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+								{% if libraries %}
+									{% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+	                            {% endif %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.828171482" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/{{linker_script}}}"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.310068762" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+	                                {% for lib in libraries %}
+	                                <listOptionValue builtIn="false" value="{{lib}}"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.460736806" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+	                                {% for path in object_files %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+	                            </option>
+	                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.30848869" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs" valueType="string"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1081415325" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1216251638" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1820796904" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.70927688" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.721327636" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.625552450" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.263758416" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1024069673" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1043375284" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1671601569" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.171400698" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1102568395" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}.ilg.gnuarmeclipse.managedbuild.cross.target.elf.829438011" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.307634730;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1070359138">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1300731881;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.690792246">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/hexiwear_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/hexiwear_project.tmpl
new file mode 100755
index 0000000..1ab5ab3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/hexiwear_project.tmpl
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}</name>
+	<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-KDS</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k22f_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k22f_cproject.tmpl
new file mode 100755
index 0000000..18aa0fb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k22f_cproject.tmpl
@@ -0,0 +1,306 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1221610645" name="Cross ARM GCC" nonInternalBuilderId="ilg.gnuarmeclipse.managedbuild.cross.builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1271983492" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1681866628" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1550050553" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2126138943" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1492840277" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1058622512" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1583945235" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.gdb" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1089911925" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.77844367" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.softfp" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.353876552" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1308049896" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="Custom" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.560926624" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.660978974" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1169416449" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1545312724" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.2106299868" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.880150025" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.1449434602" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1638755745" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1500383066" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1422858690" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.1453349108" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.918192766" name="Disable builtin (-fno-builtin)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other.845411621" name="Other debugging flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other" value="" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.2076910080" name="Generate prof information (-p)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.1002876099" name="Generate gprof information (-pg)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.371856963" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.2090214221" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/{{name}}}/Debug" cleanBuildTarget="clean" command="${cross_make}" id="org.eclipse.cdt.build.core.internal.builder.2045347460" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.774448198" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.874144438" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1457752231" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.1240528565" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.645447748" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.655157579" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1298012181" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.26057600" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1551083554" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1601945676" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.73762833" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.1541205451" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.2072412260" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.default" valueType="enumerated"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1882430856" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.339583643" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1999194416" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+					<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.344980185" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.727573047" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+								{% if libraries %}
+									{% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                {% endif %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.828171482" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/{{linker_script}}}"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.310068762" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+                                    {% for lib in libraries %}
+                                    <listOptionValue builtIn="false" value="{{lib}}"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.460736806" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.30848869" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs" valueType="string"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1081415325" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1216251638" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1820796904" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.70927688" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.721327636" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.625552450" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.263758416" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1024069673" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1043375284" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1671601569" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.171400698" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1102568395" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787" name="Release" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release.765163102" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1271983492" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.size" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1681866628" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1550050553" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2126138943" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1492840277" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1058622512" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1583945235" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.gdb" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1089911925" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.77844367" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.softfp" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.353876552" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1308049896" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="Custom" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.560926624" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.660978974" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1169416449" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1545312724" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.2106299868" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.880150025" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.1449434602" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1638755745" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1500383066" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1422858690" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.1453349108" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.918192766" name="Disable builtin (-fno-builtin)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other.845411621" name="Other debugging flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other" value="" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.2076910080" name="Generate prof information (-p)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.1002876099" name="Generate gprof information (-pg)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.371856963" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.2090214221" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/{{name}}}/Debug" cleanBuildTarget="clean" command="${cross_make}" id="org.eclipse.cdt.build.core.internal.builder.2045347460" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.774448198" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.874144438" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1457752231" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.1240528565" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.645447748" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.655157579" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1298012181" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.26057600" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1551083554" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1601945676" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.73762833" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.1541205451" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.2072412260" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.default" valueType="enumerated"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1882430856" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.339583643" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1999194416" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+					<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.344980185" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.727573047" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+								{% if libraries %}
+									{% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+	                            {% endif %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.828171482" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/{{linker_script}}}"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.310068762" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+	                                {% for lib in libraries %}
+	                                <listOptionValue builtIn="false" value="{{lib}}"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.460736806" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+	                                {% for path in object_files %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+	                            </option>
+	                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.30848869" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs" valueType="string"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1081415325" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1216251638" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1820796904" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.70927688" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.721327636" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.625552450" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.263758416" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1024069673" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1043375284" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1671601569" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.171400698" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1102568395" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}.ilg.gnuarmeclipse.managedbuild.cross.target.elf.829438011" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.307634730;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1070359138">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1300731881;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.690792246">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k22f_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k22f_project.tmpl
new file mode 100755
index 0000000..1ab5ab3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k22f_project.tmpl
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}</name>
+	<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-KDS</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k64f_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k64f_cproject.tmpl
new file mode 100755
index 0000000..18aa0fb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k64f_cproject.tmpl
@@ -0,0 +1,306 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1221610645" name="Cross ARM GCC" nonInternalBuilderId="ilg.gnuarmeclipse.managedbuild.cross.builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1271983492" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1681866628" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1550050553" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2126138943" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1492840277" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1058622512" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1583945235" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.gdb" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1089911925" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.77844367" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.softfp" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.353876552" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1308049896" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="Custom" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.560926624" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.660978974" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1169416449" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1545312724" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.2106299868" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.880150025" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.1449434602" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1638755745" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1500383066" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1422858690" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.1453349108" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.918192766" name="Disable builtin (-fno-builtin)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other.845411621" name="Other debugging flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other" value="" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.2076910080" name="Generate prof information (-p)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.1002876099" name="Generate gprof information (-pg)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.371856963" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.2090214221" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/{{name}}}/Debug" cleanBuildTarget="clean" command="${cross_make}" id="org.eclipse.cdt.build.core.internal.builder.2045347460" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.774448198" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.874144438" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1457752231" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.1240528565" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.645447748" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.655157579" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1298012181" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.26057600" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1551083554" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1601945676" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.73762833" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.1541205451" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.2072412260" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.default" valueType="enumerated"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1882430856" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.339583643" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1999194416" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+					<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.344980185" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.727573047" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+								{% if libraries %}
+									{% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                {% endif %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.828171482" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/{{linker_script}}}"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.310068762" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+                                    {% for lib in libraries %}
+                                    <listOptionValue builtIn="false" value="{{lib}}"/>
+                                    {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.460736806" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.30848869" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs" valueType="string"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1081415325" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1216251638" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1820796904" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.70927688" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.721327636" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.625552450" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.263758416" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1024069673" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1043375284" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1671601569" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.171400698" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1102568395" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787" name="Release" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release.765163102" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1271983492" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.size" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1681866628" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1550050553" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2126138943" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1492840277" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1058622512" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1583945235" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.gdb" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1089911925" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.77844367" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.softfp" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.353876552" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1308049896" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="Custom" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.560926624" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.660978974" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1169416449" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1545312724" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.2106299868" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.880150025" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.1449434602" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1638755745" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1500383066" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1422858690" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.1453349108" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.918192766" name="Disable builtin (-fno-builtin)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other.845411621" name="Other debugging flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.other" value="" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.2076910080" name="Generate prof information (-p)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.1002876099" name="Generate gprof information (-pg)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="false" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.371856963" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.2090214221" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/{{name}}}/Debug" cleanBuildTarget="clean" command="${cross_make}" id="org.eclipse.cdt.build.core.internal.builder.2045347460" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.774448198" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.874144438" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1457752231" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.1240528565" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.645447748" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.655157579" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1298012181" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.26057600" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1551083554" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" valueType="includePath">
+	                                {% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1601945676" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+	                              {% for s in symbols %}
+	                                <listOptionValue builtIn="false" value="{{s}}"/>
+	                              {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.73762833" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.1541205451" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.2072412260" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.default" valueType="enumerated"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1882430856" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.339583643" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1999194416" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+					<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.344980185" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.727573047" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+								{% if libraries %}
+									{% for path in include_paths %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+	                            {% endif %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.828171482" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/{{linker_script}}}"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.310068762" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+	                                {% for lib in libraries %}
+	                                <listOptionValue builtIn="false" value="{{lib}}"/>
+	                                {% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.460736806" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+	                                {% for path in object_files %}
+	                                    <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+	                                {% endfor %}
+	                            </option>
+	                            <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.30848869" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs" valueType="string"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1081415325" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1216251638" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1820796904" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.70927688" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.721327636" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.625552450" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.263758416" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1024069673" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1043375284" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1671601569" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.171400698" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1102568395" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}.ilg.gnuarmeclipse.managedbuild.cross.target.elf.829438011" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1023327076;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.247734571">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.307634730;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1070359138">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.248936164;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.2029463372">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1382253787.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1300731881;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.690792246">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k64f_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k64f_project.tmpl
new file mode 100755
index 0000000..1ab5ab3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/k64f_project.tmpl
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}</name>
+	<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-KDS</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/launch.tmpl
new file mode 100755
index 0000000..1fe8bbd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/kds/launch.tmpl
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/openocd"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f kinetis.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="1"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\{{name}}.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="{{name}}"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.637912026"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/{{name}}"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/__init__.py
new file mode 100755
index 0000000..263a5f7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/__init__.py
@@ -0,0 +1,61 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import splitext, basename
+
+from tools.export.exporters import Exporter, deprecated_exporter
+
+@deprecated_exporter
+class LPCXpresso(Exporter):
+    NAME = 'LPCXpresso'
+    TOOLCHAIN = 'GCC_ARM'
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    TARGETS = [
+        'LPC1768',
+        'LPC4088',
+        'LPC4088_DM',
+        'LPC4330_M4',
+        'LPC1114',
+        'LPC11U35_401',
+        'LPC11U35_501',
+        'UBLOX_C027',
+        'ARCH_PRO',
+        'LPC1549',
+        'LPC11U68',
+        'LPCCAPPUCCINO',
+        'LPC824',
+        'LPC11U37H_401',
+    ]
+
+    def generate(self):
+        libraries = []
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            libraries.append(l[3:])
+
+        ctx = {
+            'name': self.project_name,
+            'include_paths': self.resources.inc_dirs,
+            'linker_script': self.resources.linker_script,
+            'object_files': self.resources.objects,
+            'libraries': libraries,
+            'symbols': self.toolchain.get_symbols()
+        }
+        ctx.update(self.flags)
+        self.gen_file('lpcxpresso/%s_project.tmpl' % self.target.lower(), ctx, '.project')
+        self.gen_file('lpcxpresso/%s_cproject.tmpl' % self.target.lower(), ctx, '.cproject')
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/__init__.pyc
new file mode 100755
index 0000000..4ff756e
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/arch_pro_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/arch_pro_cproject.tmpl
new file mode 100755
index 0000000..291569d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/arch_pro_cproject.tmpl
@@ -0,0 +1,79 @@
+{% extends "lpcxpresso/cproject_cortexm3_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc176x.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1768&lt;/name&gt;&#13;
+&lt;family&gt;LPC17xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/arch_pro_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/arch_pro_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/arch_pro_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_common.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_common.tmpl
new file mode 100755
index 0000000..344782f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_common.tmpl
@@ -0,0 +1,1850 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        <cconfiguration id="com.crt.advproject.config.exe.debug.2019491857">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.2019491857" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.2019491857" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
+                    <folderInfo id="com.crt.advproject.config.exe.debug.2019491857." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.debug.305863439" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1056224942" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Debug}" id="com.crt.advproject.builder.exe.debug.921640983" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+                            <tool id="com.crt.advproject.cpp.exe.debug.88038757" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
+                                <option id="com.crt.advproject.cpp.arch.91244724" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.{% block core %}{% endblock %}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.509442564" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.347637870" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1100343989" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c {{cxx_flags|join(" ")}} {{common_flags|join(" ")}}" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.1011871574" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1370967818" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.debug.529082641" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
+                                <option id="com.crt.advproject.gcc.arch.1733119111" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.{{ self.core() }}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.570577864" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.784082637" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.1824535269" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.1521041525" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c {{c_flags|join(" ")}} {{common_flags|join(" ")}}" valueType="string"/>
+
+                                <option id="gnu.c.compiler.option.include.paths.1293117680" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.input.205113874" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.debug.1277199919" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
+                                <option id="com.crt.advproject.gas.arch.1079400011" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.{{ self.core() }}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1976113150" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.1501250871" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c {{asm_flags|join(" ")}} {{common_flags|join(" ")}} -D__NEWLIB__  -DDEBUG -D__CODE_RED " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.473313643" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.910682278" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.debug.1997879384" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug">
+                                <option id="com.crt.advproject.link.cpp.arch.93048844" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.{{ self.core() }}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1932742266" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.1663456123"
+                                        name="Linker script"
+                                        superClass="com.crt.advproject.link.cpp.script"
+                                        value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1404088829" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.851870479" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1647176917" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.286729066" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+
+                                <option id="gnu.cpp.link.option.paths.504050220" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                   {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.libs.1301785862" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    {% for lib in libraries %}
+                                    <listOptionValue builtIn="false" value="{{lib}}"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.userobjs.433052051" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.1671719885" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.debug.1712095989" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug"/>
+                        </toolChain>
+                    </folderInfo>
+                    <fileInfo id="com.crt.advproject.config.exe.debug.2019491857.src/{% block startup_file %}{% endblock %}" name="{{ self.startup_file() }}" rcbsApplicability="disable" resourcePath="src/{{ self.startup_file() }}" toolsToInvoke="com.crt.advproject.gcc.exe.debug.529082641.1914238712">
+                        <tool id="com.crt.advproject.gcc.exe.debug.529082641.1914238712" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.529082641">
+                            <option id="gnu.c.compiler.option.optimization.flags.316755676" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                            <inputType id="com.crt.advproject.compiler.input.627153917" superClass="com.crt.advproject.compiler.input"/>
+                        </tool>
+                    </fileInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+        <cconfiguration id="com.crt.advproject.config.exe.release.1977230950">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.release.1977230950" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Release build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.release.1977230950" name="Release" parent="com.crt.advproject.config.exe.release" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; #checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;">
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.756613197" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release.1775167776" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Release}" id="com.crt.advproject.builder.exe.release.600748344" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.822772966" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release">
+                                <option id="com.crt.advproject.cpp.arch.2116463586" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.{{ self.core() }}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.189747400" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.874410253" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1338090461" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c {{cxx_flags|join(" ")}} {{common_flags|join(" ")}}" valueType="string"/>
+                                <option id="gnu.cpp.compiler.option.optimization.flags.475225500" name="Other optimization flags" superClass="gnu.cpp.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.17539784" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1172589171" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.563782464" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release">
+                                <option id="com.crt.advproject.gcc.arch.538870649" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.{{ self.core() }}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.486202735" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.966879133" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.740543529" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.2015545820" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c {{c_flags|join(" ")}} {{common_flags|join(" ")}}" valueType="string"/>
+                                <option id="gnu.c.compiler.option.optimization.flags.675461365" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                                <inputType id="com.crt.advproject.compiler.input.1938378962" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.579950187" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release">
+                                <option id="com.crt.advproject.gas.arch.1401271875" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.{{ self.core() }}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1024544278" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.637466836" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c {{asm_flags|join(" ")}} {{common_flags|join(" ")}} -D__NEWLIB__  -DNDEBUG -D__CODE_RED " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.492600365" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.812068162" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.1927521706" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release">
+                                <option id="com.crt.advproject.link.cpp.arch.1449152453" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.{{ self.core() }}" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1116035810" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.653073282" name="Linker script" superClass="com.crt.advproject.link.cpp.script" value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1855989551" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.1541555749" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1799120411" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.259007915" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+                                <option id="gnu.cpp.link.option.libs.6254811" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    <listOptionValue builtIn="false" value="mbed"/>
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.paths.813959094" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.userobjs.1313579148" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.486207182" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.release.1417379956" name="MCU Linker" superClass="com.crt.advproject.link.exe.release"/>
+                        </toolChain>
+                    </folderInfo>
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950.180082224" name="/" resourcePath="mbed">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.1962091265" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release" unusedChildren="">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.930589045" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release.822772966">
+                                
+                                <option id="gnu.cpp.compiler.option.include.paths.1413630517" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1706370613" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.536058616" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release.563782464">
+                                <inputType id="com.crt.advproject.compiler.input.1565281352" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.607817423" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release.579950187">
+                                <inputType id="com.crt.advproject.assembler.input.21606274" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.941965043" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release.1927521706"/>
+                            <tool id="com.crt.advproject.link.exe.release.1836661645" name="MCU Linker" superClass="com.crt.advproject.link.exe.release.1417379956"/>
+                        </toolChain>
+                    </folderInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+    </storageModule>
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        <project id="{{name}}.com.crt.advproject.projecttype.exe.609645090" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>
+    </storageModule>
+    <storageModule moduleId="com.crt.config">
+        <projectStorage>{% block cpu_config %}{% endblock %}</projectStorage>
+    </storageModule>
+</cproject>
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_cortexm0_common.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_cortexm0_common.tmpl
new file mode 100755
index 0000000..1635ee2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_cortexm0_common.tmpl
@@ -0,0 +1,3 @@
+{% extends "lpcxpresso/cproject_common.tmpl" %}
+
+{% block core %}cm0{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_cortexm3_common.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_cortexm3_common.tmpl
new file mode 100755
index 0000000..6ebc79f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/cproject_cortexm3_common.tmpl
@@ -0,0 +1,3 @@
+{% extends "lpcxpresso/cproject_common.tmpl" %}
+
+{% block core %}cm3{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1114_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1114_cproject.tmpl
new file mode 100755
index 0000000..42b25d0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1114_cproject.tmpl
@@ -0,0 +1,48 @@
+{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc11xx.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_32K_4K.cfx" property_3="NXP" property_4="LPC1114FN/102" property_count="5" version="60100"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1114FN/102" flash_driver="LPC11_12_13_32K_4K.cfx" match_id="0x0A40902B,0x1A40902B" name="LPC1114FN/102" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1114FN/102&lt;/name&gt;&#13;
+&lt;family&gt;LPC11xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc4" location="0x10000000" size="0x1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART" determined="infoFile" id="UART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO0" determined="infoFile" id="GPIO0" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO1" determined="infoFile" id="GPIO1" location="0x50010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO2" determined="infoFile" id="GPIO2" location="0x50020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO3" determined="infoFile" id="GPIO3" location="0x50030000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11xx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1114_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1114_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1114_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_401_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_401_cproject.tmpl
new file mode 100755
index 0000000..5d67143
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_401_cproject.tmpl
@@ -0,0 +1,51 @@
+{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc11xx.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/401" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC11U35/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/401" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC11U35/401&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_401_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_401_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_401_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_501_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_501_cproject.tmpl
new file mode 100755
index 0000000..28c3ad0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_501_cproject.tmpl
@@ -0,0 +1,51 @@
+{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc11xx.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/501" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC11U35/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/501" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC11U35/501&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_501_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_501_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u35_501_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u37h_401_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u37h_401_cproject.tmpl
new file mode 100755
index 0000000..614f61f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u37h_401_cproject.tmpl
@@ -0,0 +1,51 @@
+{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc11xx.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U37H/401" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC11U37H/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U37H/401" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC11U37H/401&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u37h_401_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u37h_401_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u37h_401_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u68_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u68_cproject.tmpl
new file mode 100755
index 0000000..3c37890
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u68_cproject.tmpl
@@ -0,0 +1,60 @@
+{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}startup_LPC11U68.cpp{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11U6x_256K.cfx" property_3="NXP" property_4="LPC11U68" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;&lt;info chip="LPC11U68" flash_driver="LPC11U6x_256K.cfx" match_id="0x0" name="LPC11U68" stub="crt_emu_cm3_gen"&gt;&#13;&lt;chip&gt;&#13;&lt;name&gt;&#13;LPC11U68&lt;/name&gt;&#13;
+&lt;family&gt;&#13;LPC11U6x&lt;/family&gt;&#13;
+&lt;vendor&gt;&#13;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram0_32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram1_2" location="0x20000000" size="0x800"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram2USB_2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMATRIGMUX" determined="infoFile" id="DMATRIGMUX" location="0x40028000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART4" determined="infoFile" id="USART4" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT0" determined="infoFile" id="GINT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT1" determined="infoFile" id="GINT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x4006c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x40070000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART3" determined="infoFile" id="USART3" location="0x40074000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT0" determined="infoFile" id="SCT0" location="0x5000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT1" determined="infoFile" id="SCT1" location="0x5000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0xa0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PINT" determined="infoFile" id="PINT" location="0xa0004000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u68_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u68_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc11u68_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1549_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1549_cproject.tmpl
new file mode 100755
index 0000000..5180552
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1549_cproject.tmpl
@@ -0,0 +1,69 @@
+{% extends "lpcxpresso/cproject_cortexm3_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc15xx.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC15xx_256K.cfx" property_3="NXP" property_4="LPC1549" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1549" connectscript="LPC15RunBootRomConnect.scp" flash_driver="LPC15xx_256K.cfx" match_id="0x0" name="LPC1549" resetscript="LPC15RunBootRomReset.scp" stub="crt_emu_cm3_gen"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1549&lt;/name&gt;&#13;
+&lt;family&gt;LPC15xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram0_16" location="0x2000000" size="0x4000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram1_16" location="0x2004000" size="0x4000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram2_4" location="0x2008000" size="0x1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC15_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC15_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC15_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC15_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x1c000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x1c004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x1c00c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x1c010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT0" determined="infoFile" id="SCT0" location="0x1c018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT1" determined="infoFile" id="SCT1" location="0x1c01c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT2" determined="infoFile" id="SCT2" location="0x1c020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT3" determined="infoFile" id="SCT3" location="0x1c024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC0" determined="infoFile" id="ADC0" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" determined="infoFile" id="DAC" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ACMP" determined="infoFile" id="ACMP" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="INMUX" determined="infoFile" id="INMUX" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40028000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SWM" determined="infoFile" id="SWM" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI1" determined="infoFile" id="SPI1" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40050000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" determined="infoFile" id="QEI" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40074000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC1" determined="infoFile" id="ADC1" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MRT" determined="infoFile" id="MRT" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PINT" determined="infoFile" id="PINT" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT0" determined="infoFile" id="GINT0" location="0x400a8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT1" determined="infoFile" id="GINT1" location="0x400ac000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RIT" determined="infoFile" id="RIT" location="0x400b4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCTIPU" determined="infoFile" id="SCTIPU" location="0x400b8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="C-CAN0" determined="infoFile" id="C-CAN0" location="0x400f0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x400f8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1549_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1549_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1549_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1768_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1768_cproject.tmpl
new file mode 100755
index 0000000..291569d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1768_cproject.tmpl
@@ -0,0 +1,79 @@
+{% extends "lpcxpresso/cproject_cortexm3_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc176x.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1768&lt;/name&gt;&#13;
+&lt;family&gt;LPC17xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1768_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1768_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc1768_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_cproject.tmpl
new file mode 100755
index 0000000..35ffa7c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_cproject.tmpl
@@ -0,0 +1,1922 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        <cconfiguration id="com.crt.advproject.config.exe.debug.2019491857">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.2019491857" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.2019491857" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
+                    <folderInfo id="com.crt.advproject.config.exe.debug.2019491857." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.debug.305863439" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1056224942" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Debug}" id="com.crt.advproject.builder.exe.debug.921640983" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+                            <tool id="com.crt.advproject.cpp.exe.debug.88038757" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
+								<option id="com.crt.advproject.cpp.arch.91244724" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.509442564" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.347637870" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1100343989" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.1011871574" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+								<option id="com.crt.advproject.cpp.fpu.192009095" name="Floating point" superClass="com.crt.advproject.cpp.fpu" value="com.crt.advproject.cpp.fpu.fpv4" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1370967818" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.debug.529082641" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
+								<option id="com.crt.advproject.gcc.arch.1733119111" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.570577864" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.784082637" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.1824535269" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.1521041525" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions " valueType="string"/>
+
+                                <option id="gnu.c.compiler.option.include.paths.1293117680" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+								<option id="com.crt.advproject.gcc.fpu.759979004" name="Floating point" superClass="com.crt.advproject.gcc.fpu" value="com.crt.advproject.gcc.fpu.fpv4" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.compiler.input.205113874" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.debug.1277199919" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
+								<option id="com.crt.advproject.gas.arch.1079400011" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1976113150" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.1501250871" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__NEWLIB__  -DDEBUG -D__CODE_RED {% for s in symbols %}-D{{s}} {% endfor %} " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.473313643" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+								<option id="com.crt.advproject.gas.fpu.478766821" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.910682278" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.debug.1997879384" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug">
+								<option id="com.crt.advproject.link.cpp.arch.93048844" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1932742266" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.1663456123"
+                                        name="Linker script"
+                                        superClass="com.crt.advproject.link.cpp.script"
+                                        value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1404088829" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.851870479" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1647176917" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.286729066" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+
+                                <option id="gnu.cpp.link.option.paths.504050220" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                   {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.libs.1301785862" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    {% for lib in libraries %}
+                                    <listOptionValue builtIn="false" value="{{lib}}"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.userobjs.433052051" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+				<option id="com.crt.advproject.link.cpp.fpu.1448877425" name="Floating point" superClass="com.crt.advproject.link.cpp.fpu" value="com.crt.advproject.link.cpp.fpu.fpv4" valueType="enumerated"/>
+
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.1671719885" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.debug.1712095989" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug"/>
+                        </toolChain>
+                    </folderInfo>
+                    <fileInfo id="com.crt.advproject.config.exe.debug.2019491857.src/cr_startup_lpc176x.c" name="cr_startup_lpc176x.c" rcbsApplicability="disable" resourcePath="src/cr_startup_lpc176x.c" toolsToInvoke="com.crt.advproject.gcc.exe.debug.529082641.1914238712">
+                        <tool id="com.crt.advproject.gcc.exe.debug.529082641.1914238712" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.529082641">
+                            <option id="gnu.c.compiler.option.optimization.flags.316755676" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                            <inputType id="com.crt.advproject.compiler.input.627153917" superClass="com.crt.advproject.compiler.input"/>
+                        </tool>
+                    </fileInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+        <cconfiguration id="com.crt.advproject.config.exe.release.1977230950">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.release.1977230950" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Release build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.release.1977230950" name="Release" parent="com.crt.advproject.config.exe.release" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; #checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;">
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.756613197" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release.1775167776" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Release}" id="com.crt.advproject.builder.exe.release.600748344" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.822772966" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release">
+                                <option id="com.crt.advproject.cpp.arch.2116463586" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.189747400" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.874410253" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1338090461" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+                                <option id="gnu.cpp.compiler.option.optimization.flags.475225500" name="Other optimization flags" superClass="gnu.cpp.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.17539784" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1172589171" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.563782464" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release">
+                                <option id="com.crt.advproject.gcc.arch.538870649" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.486202735" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.966879133" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.740543529" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.2015545820" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions " valueType="string"/>
+                                <option id="gnu.c.compiler.option.optimization.flags.675461365" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                                <inputType id="com.crt.advproject.compiler.input.1938378962" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.579950187" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release">
+                                <option id="com.crt.advproject.gas.arch.1401271875" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1024544278" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.637466836" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__NEWLIB__  -DNDEBUG -D__CODE_RED {% for s in symbols %}-D{{s}} {% endfor %} " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.492600365" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.812068162" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.1927521706" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release">
+                                <option id="com.crt.advproject.link.cpp.arch.1449152453" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1116035810" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.653073282" name="Linker script" superClass="com.crt.advproject.link.cpp.script" value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1855989551" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.1541555749" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1799120411" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.259007915" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+                                <option id="gnu.cpp.link.option.libs.6254811" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    <listOptionValue builtIn="false" value="mbed"/>
+                                    <listOptionValue builtIn="false" value="capi"/>
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.paths.813959094" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.userobjs.1313579148" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.486207182" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.release.1417379956" name="MCU Linker" superClass="com.crt.advproject.link.exe.release"/>
+                        </toolChain>
+                    </folderInfo>
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950.180082224" name="/" resourcePath="mbed">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.1962091265" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release" unusedChildren="">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.930589045" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release.822772966">
+                                
+                                <option id="gnu.cpp.compiler.option.include.paths.1413630517" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1706370613" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.536058616" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release.563782464">
+                                <inputType id="com.crt.advproject.compiler.input.1565281352" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.607817423" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release.579950187">
+                                <inputType id="com.crt.advproject.assembler.input.21606274" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.941965043" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release.1927521706"/>
+                            <tool id="com.crt.advproject.link.exe.release.1836661645" name="MCU Linker" superClass="com.crt.advproject.link.exe.release.1417379956"/>
+                        </toolChain>
+                    </folderInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+    </storageModule>
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        <project id="{{name}}.com.crt.advproject.projecttype.exe.609645090" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>
+    </storageModule>
+    <storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC177x_8x_407x_8x_512.cfx" property_3="NXP" property_4="LPC4088" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4088" flash_driver="LPC177x_8x_407x_8x_512.cfx" match_id="0x481D3F47" name="LPC4088" stub="crt_emu_cm3_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4088&lt;/name&gt;&#13;
+&lt;family&gt;LPC407x_8x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc64" location="0x10000000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph32" location="0x20000000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x200000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x20080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x20084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x20088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x2008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x20090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO" id="GPIO" location="0x20098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x2009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART0" id="UART0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM0" id="PWM0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM1" id="PWM1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="COMPARATOR" id="COMPARATOR" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOINT" id="GPIOINT" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAFRAM" id="CANAFRAM" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAF" id="CANAF" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CCAN" id="CCAN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN1" id="CAN1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN2" id="CAN2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x4008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART2" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART3" id="UART3" location="0x4009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART4" id="UART4" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S" id="I2S" location="0x400a8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP2" id="SSP2" location="0x400ac000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400b8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x400fc000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpc407x_8x_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;</projectStorage>
+    </storageModule>
+</cproject>
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_dm_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_dm_cproject.tmpl
new file mode 100755
index 0000000..35ffa7c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_dm_cproject.tmpl
@@ -0,0 +1,1922 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        <cconfiguration id="com.crt.advproject.config.exe.debug.2019491857">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.2019491857" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.2019491857" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
+                    <folderInfo id="com.crt.advproject.config.exe.debug.2019491857." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.debug.305863439" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1056224942" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Debug}" id="com.crt.advproject.builder.exe.debug.921640983" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+                            <tool id="com.crt.advproject.cpp.exe.debug.88038757" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
+								<option id="com.crt.advproject.cpp.arch.91244724" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.509442564" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.347637870" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1100343989" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.1011871574" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+								<option id="com.crt.advproject.cpp.fpu.192009095" name="Floating point" superClass="com.crt.advproject.cpp.fpu" value="com.crt.advproject.cpp.fpu.fpv4" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1370967818" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.debug.529082641" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
+								<option id="com.crt.advproject.gcc.arch.1733119111" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.570577864" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.784082637" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.1824535269" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.1521041525" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions " valueType="string"/>
+
+                                <option id="gnu.c.compiler.option.include.paths.1293117680" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+								<option id="com.crt.advproject.gcc.fpu.759979004" name="Floating point" superClass="com.crt.advproject.gcc.fpu" value="com.crt.advproject.gcc.fpu.fpv4" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.compiler.input.205113874" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.debug.1277199919" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
+								<option id="com.crt.advproject.gas.arch.1079400011" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1976113150" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.1501250871" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__NEWLIB__  -DDEBUG -D__CODE_RED {% for s in symbols %}-D{{s}} {% endfor %} " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.473313643" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+								<option id="com.crt.advproject.gas.fpu.478766821" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.910682278" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.debug.1997879384" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug">
+								<option id="com.crt.advproject.link.cpp.arch.93048844" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm4" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1932742266" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.1663456123"
+                                        name="Linker script"
+                                        superClass="com.crt.advproject.link.cpp.script"
+                                        value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1404088829" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.851870479" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1647176917" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.286729066" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+
+                                <option id="gnu.cpp.link.option.paths.504050220" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                   {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.libs.1301785862" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    {% for lib in libraries %}
+                                    <listOptionValue builtIn="false" value="{{lib}}"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.userobjs.433052051" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+				<option id="com.crt.advproject.link.cpp.fpu.1448877425" name="Floating point" superClass="com.crt.advproject.link.cpp.fpu" value="com.crt.advproject.link.cpp.fpu.fpv4" valueType="enumerated"/>
+
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.1671719885" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.debug.1712095989" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug"/>
+                        </toolChain>
+                    </folderInfo>
+                    <fileInfo id="com.crt.advproject.config.exe.debug.2019491857.src/cr_startup_lpc176x.c" name="cr_startup_lpc176x.c" rcbsApplicability="disable" resourcePath="src/cr_startup_lpc176x.c" toolsToInvoke="com.crt.advproject.gcc.exe.debug.529082641.1914238712">
+                        <tool id="com.crt.advproject.gcc.exe.debug.529082641.1914238712" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.529082641">
+                            <option id="gnu.c.compiler.option.optimization.flags.316755676" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                            <inputType id="com.crt.advproject.compiler.input.627153917" superClass="com.crt.advproject.compiler.input"/>
+                        </tool>
+                    </fileInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+        <cconfiguration id="com.crt.advproject.config.exe.release.1977230950">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.release.1977230950" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Release build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.release.1977230950" name="Release" parent="com.crt.advproject.config.exe.release" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; #checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;">
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.756613197" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release.1775167776" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Release}" id="com.crt.advproject.builder.exe.release.600748344" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.822772966" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release">
+                                <option id="com.crt.advproject.cpp.arch.2116463586" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.189747400" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.874410253" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1338090461" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+                                <option id="gnu.cpp.compiler.option.optimization.flags.475225500" name="Other optimization flags" superClass="gnu.cpp.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.17539784" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1172589171" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.563782464" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release">
+                                <option id="com.crt.advproject.gcc.arch.538870649" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.486202735" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.966879133" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.740543529" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.2015545820" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions " valueType="string"/>
+                                <option id="gnu.c.compiler.option.optimization.flags.675461365" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                                <inputType id="com.crt.advproject.compiler.input.1938378962" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.579950187" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release">
+                                <option id="com.crt.advproject.gas.arch.1401271875" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1024544278" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.637466836" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__NEWLIB__  -DNDEBUG -D__CODE_RED {% for s in symbols %}-D{{s}} {% endfor %} " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.492600365" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.812068162" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.1927521706" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release">
+                                <option id="com.crt.advproject.link.cpp.arch.1449152453" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1116035810" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.653073282" name="Linker script" superClass="com.crt.advproject.link.cpp.script" value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1855989551" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.1541555749" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1799120411" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.259007915" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+                                <option id="gnu.cpp.link.option.libs.6254811" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    <listOptionValue builtIn="false" value="mbed"/>
+                                    <listOptionValue builtIn="false" value="capi"/>
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.paths.813959094" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.userobjs.1313579148" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.486207182" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.release.1417379956" name="MCU Linker" superClass="com.crt.advproject.link.exe.release"/>
+                        </toolChain>
+                    </folderInfo>
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950.180082224" name="/" resourcePath="mbed">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.1962091265" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release" unusedChildren="">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.930589045" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release.822772966">
+                                
+                                <option id="gnu.cpp.compiler.option.include.paths.1413630517" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1706370613" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.536058616" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release.563782464">
+                                <inputType id="com.crt.advproject.compiler.input.1565281352" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.607817423" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release.579950187">
+                                <inputType id="com.crt.advproject.assembler.input.21606274" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.941965043" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release.1927521706"/>
+                            <tool id="com.crt.advproject.link.exe.release.1836661645" name="MCU Linker" superClass="com.crt.advproject.link.exe.release.1417379956"/>
+                        </toolChain>
+                    </folderInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+    </storageModule>
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        <project id="{{name}}.com.crt.advproject.projecttype.exe.609645090" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>
+    </storageModule>
+    <storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC177x_8x_407x_8x_512.cfx" property_3="NXP" property_4="LPC4088" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4088" flash_driver="LPC177x_8x_407x_8x_512.cfx" match_id="0x481D3F47" name="LPC4088" stub="crt_emu_cm3_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4088&lt;/name&gt;&#13;
+&lt;family&gt;LPC407x_8x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc64" location="0x10000000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph32" location="0x20000000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x200000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x20080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x20084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x20088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x2008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x20090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO" id="GPIO" location="0x20098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x2009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART0" id="UART0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM0" id="PWM0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM1" id="PWM1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="COMPARATOR" id="COMPARATOR" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOINT" id="GPIOINT" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAFRAM" id="CANAFRAM" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAF" id="CANAF" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CCAN" id="CCAN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN1" id="CAN1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN2" id="CAN2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x4008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART2" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART3" id="UART3" location="0x4009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART4" id="UART4" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S" id="I2S" location="0x400a8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP2" id="SSP2" location="0x400ac000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400b8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x400fc000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpc407x_8x_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;</projectStorage>
+    </storageModule>
+</cproject>
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_dm_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_dm_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_dm_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4088_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4330_m4_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4330_m4_cproject.tmpl
new file mode 100755
index 0000000..bd1f896
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4330_m4_cproject.tmpl
@@ -0,0 +1,1924 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        <cconfiguration id="com.crt.advproject.config.exe.debug.2019491857">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.2019491857" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.2019491857" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
+                    <folderInfo id="com.crt.advproject.config.exe.debug.2019491857." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.debug.305863439" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1056224942" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Debug}" id="com.crt.advproject.builder.exe.debug.921640983" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+                            <tool id="com.crt.advproject.cpp.exe.debug.88038757" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
+                                <option id="com.crt.advproject.cpp.arch.91244724" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.509442564" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.347637870" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1100343989" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.1011871574" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1370967818" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.debug.529082641" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
+                                <option id="com.crt.advproject.gcc.arch.1733119111" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.570577864" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.784082637" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.1824535269" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.1521041525" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+
+                                <option id="gnu.c.compiler.option.include.paths.1293117680" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.input.205113874" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.debug.1277199919" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
+                                <option id="com.crt.advproject.gas.arch.1079400011" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1976113150" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.1501250871" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__NEWLIB__  -DDEBUG -D__CODE_RED " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.473313643" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.910682278" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.debug.1997879384" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug">
+                                <option id="com.crt.advproject.link.cpp.arch.93048844" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1932742266" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.1663456123"
+                                        name="Linker script"
+                                        superClass="com.crt.advproject.link.cpp.script"
+                                        value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1404088829" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.851870479" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1647176917" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.286729066" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+
+                                <option id="gnu.cpp.link.option.paths.504050220" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                   {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.libs.1301785862" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    {% for lib in libraries %}
+                                    <listOptionValue builtIn="false" value="{{lib}}"/>
+                                    {% endfor %}
+                                </option>
+
+                                <option id="gnu.cpp.link.option.userobjs.433052051" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.1671719885" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.debug.1712095989" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug"/>
+                        </toolChain>
+                    </folderInfo>
+                    <fileInfo id="com.crt.advproject.config.exe.debug.2019491857.src/cr_startup_lpc43xx.c" name="cr_startup_lpc43xx.c" rcbsApplicability="disable" resourcePath="src/cr_startup_lpc43xx.c" toolsToInvoke="com.crt.advproject.gcc.exe.debug.529082641.1914238712">
+                        <tool id="com.crt.advproject.gcc.exe.debug.529082641.1914238712" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.529082641">
+                            <option id="gnu.c.compiler.option.optimization.flags.316755676" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                            <inputType id="com.crt.advproject.compiler.input.627153917" superClass="com.crt.advproject.compiler.input"/>
+                        </tool>
+                    </fileInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+        <cconfiguration id="com.crt.advproject.config.exe.release.1977230950">
+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.release.1977230950" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                <externalSettings/>
+                <extensions>
+                    <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                    <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                </extensions>
+            </storageModule>
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Release build" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.release.1977230950" name="Release" parent="com.crt.advproject.config.exe.release" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; #checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;">
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950." name="/" resourcePath="">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.756613197" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release.1775167776" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <builder buildPath="${workspace_loc:/{{name}}/Release}" id="com.crt.advproject.builder.exe.release.600748344" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.822772966" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release">
+                                <option id="com.crt.advproject.cpp.arch.2116463586" name="Architecture" superClass="com.crt.advproject.cpp.arch" value="com.crt.advproject.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.cpp.thumb.189747400" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.compiler.option.preprocessor.def.874410253" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.cpp.compiler.option.other.other.1338090461" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+                                <option id="gnu.cpp.compiler.option.optimization.flags.475225500" name="Other optimization flags" superClass="gnu.cpp.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+
+                                <option id="gnu.cpp.compiler.option.include.paths.17539784" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1172589171" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.563782464" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release">
+                                <option id="com.crt.advproject.gcc.arch.538870649" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gcc.thumb.486202735" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.gcc.hdrlib.966879133" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.newlib" valueType="enumerated"/>
+                                <option id="gnu.c.compiler.option.preprocessor.def.symbols.740543529" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+                                    <listOptionValue builtIn="false" value="__NEWLIB__"/>
+                                    <listOptionValue builtIn="false" value="__CODE_RED"/>
+                                    <listOptionValue builtIn="false" value="CPP_USE_HEAP"/>
+                                  {% for s in symbols %}
+                                    <listOptionValue builtIn="false" value="{{s}}"/>
+                                  {% endfor %}
+                                </option>
+                                <option id="gnu.c.compiler.option.misc.other.2015545820" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti" valueType="string"/>
+                                <option id="gnu.c.compiler.option.optimization.flags.675461365" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-Os" valueType="string"/>
+                                <inputType id="com.crt.advproject.compiler.input.1938378962" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.579950187" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release">
+                                <option id="com.crt.advproject.gas.arch.1401271875" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.gas.thumb.1024544278" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+                                <option id="gnu.both.asm.option.flags.crt.637466836" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__NEWLIB__  -DNDEBUG -D__CODE_RED " valueType="string"/>
+                                <option id="com.crt.advproject.gas.hdrlib.492600365" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.newlib" valueType="enumerated"/>
+                                <inputType id="com.crt.advproject.assembler.input.812068162" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.1927521706" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release">
+                                <option id="com.crt.advproject.link.cpp.arch.1449152453" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm3" valueType="enumerated"/>
+                                <option id="com.crt.advproject.link.cpp.thumb.1116035810" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb" value="true" valueType="boolean"/>
+                                <option id="com.crt.advproject.link.cpp.script.653073282" name="Linker script" superClass="com.crt.advproject.link.cpp.script" value="&quot;${workspace_loc:/${ProjName}/{{linker_script}}}&quot;" valueType="string"/>
+                                <option id="com.crt.advproject.link.cpp.manage.1855989551" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage" value="false" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.nostdlibs.1541555749" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+                                <option id="gnu.cpp.link.option.other.1799120411" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other" valueType="stringList">
+                                    <listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                </option>
+                                <option id="com.crt.advproject.link.cpp.hdrlib.259007915" name="Use C library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlib.semihost" valueType="enumerated"/>
+                                <option id="gnu.cpp.link.option.libs.6254811" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+                                    <listOptionValue builtIn="false" value="mbed"/>
+                                    <listOptionValue builtIn="false" value="capi"/>
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.paths.813959094" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <option id="gnu.cpp.link.option.userobjs.1313579148" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+                                    {% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.486207182" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+                                    <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+                                    <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+                                </inputType>
+                            </tool>
+                            <tool id="com.crt.advproject.link.exe.release.1417379956" name="MCU Linker" superClass="com.crt.advproject.link.exe.release"/>
+                        </toolChain>
+                    </folderInfo>
+                    <folderInfo id="com.crt.advproject.config.exe.release.1977230950.180082224" name="/" resourcePath="mbed">
+                        <toolChain id="com.crt.advproject.toolchain.exe.release.1962091265" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.release" unusedChildren="">
+                            <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.release" name="ARM-based MCU (Release)" superClass="com.crt.advproject.platform.exe.release"/>
+                            <tool id="com.crt.advproject.cpp.exe.release.930589045" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.release.822772966">
+                                
+                                <option id="gnu.cpp.compiler.option.include.paths.1413630517" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+                                    {% for path in include_paths %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+                                </option>
+                                
+                                <inputType id="com.crt.advproject.compiler.cpp.input.1706370613" superClass="com.crt.advproject.compiler.cpp.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gcc.exe.release.536058616" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.release.563782464">
+                                <inputType id="com.crt.advproject.compiler.input.1565281352" superClass="com.crt.advproject.compiler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.gas.exe.release.607817423" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release.579950187">
+                                <inputType id="com.crt.advproject.assembler.input.21606274" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+                            </tool>
+                            <tool id="com.crt.advproject.link.cpp.exe.release.941965043" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.release.1927521706"/>
+                            <tool id="com.crt.advproject.link.exe.release.1836661645" name="MCU Linker" superClass="com.crt.advproject.link.exe.release.1417379956"/>
+                        </toolChain>
+                    </folderInfo>
+                    <sourceEntries>
+                        <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+                    </sourceEntries>
+                </configuration>
+            </storageModule>
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            <storageModule moduleId="scannerConfiguration">
+                <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="false" filePath=""/>
+                        <parser enabled="false"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="com.crt.advproject.specsFile">
+                        <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="makefileGenerator">
+                        <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                    <buildOutputProvider>
+                        <openAction enabled="true" filePath=""/>
+                        <parser enabled="true"/>
+                    </buildOutputProvider>
+                    <scannerInfoProvider id="specsFile">
+                        <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                        <parser enabled="true"/>
+                    </scannerInfoProvider>
+                </profile>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gcc.exe.release.536058616;com.crt.advproject.compiler.input.1565281352">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gas.exe.release.579950187;com.crt.advproject.assembler.input.812068162">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.gcc.exe.release.563782464;com.crt.advproject.compiler.input.1938378962">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.gas.exe.release.607817423;com.crt.advproject.assembler.input.21606274">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.;com.crt.advproject.cpp.exe.release.822772966;com.crt.advproject.compiler.cpp.input.1172589171">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+                <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1977230950;com.crt.advproject.config.exe.release.1977230950.180082224;com.crt.advproject.cpp.exe.release.930589045;com.crt.advproject.compiler.cpp.input.1706370613">
+                    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfileCPP"/>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-c++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file} " command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="com.crt.advproject.GASManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="false" filePath=""/>
+                            <parser enabled="false"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="com.crt.advproject.specsFile">
+                            <runAction arguments="-x assembler-with-cpp -E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="makefileGenerator">
+                            <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                    <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+                        <buildOutputProvider>
+                            <openAction enabled="true" filePath=""/>
+                            <parser enabled="true"/>
+                        </buildOutputProvider>
+                        <scannerInfoProvider id="specsFile">
+                            <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+                            <parser enabled="true"/>
+                        </scannerInfoProvider>
+                    </profile>
+                </scannerConfigBuildInfo>
+            </storageModule>
+        </cconfiguration>
+    </storageModule>
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        <project id="{{name}}.com.crt.advproject.projecttype.exe.609645090" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>
+    </storageModule>
+    <storageModule moduleId="com.crt.config">
+        <projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC4330" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC4330" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC4330" package="LPC43_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC4330&lt;/name&gt;&#13;
+&lt;family&gt;LPC43xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC4x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;</projectStorage>
+    </storageModule>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4330_m4_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4330_m4_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc4330_m4_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc824_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc824_cproject.tmpl
new file mode 100755
index 0000000..57343e0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc824_cproject.tmpl
@@ -0,0 +1,53 @@
+{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}startup_LPC824_CR.cpp{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;
+&lt;Properties property_0="" property_2="LPC800_32.cfx" property_3="NXP" property_4="LPC824" property_count="5" version="70200"/&gt;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC824" flash_driver="LPC800_32.cfx" match_id="0x0" name="LPC824" stub="crt_emu_cm3_gen"&gt;&lt;chip&gt;&lt;name&gt;LPC824&lt;/name&gt;
+&lt;family&gt;LPC82x&lt;/family&gt;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;
+&lt;reset board="None" core="Real" sys="Real"/&gt;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;
+&lt;memory id="RAM" type="RAM"/&gt;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;
+&lt;memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/&gt;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40000000"/&gt;
+&lt;peripheralInstance derived_from="MRT" determined="infoFile" id="MRT" location="0x40004000"/&gt;
+&lt;peripheralInstance derived_from="WKT" determined="infoFile" id="WKT" location="0x40008000"/&gt;
+&lt;peripheralInstance derived_from="SWM" determined="infoFile" id="SWM" location="0x4000c000"/&gt;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40020000"/&gt;
+&lt;peripheralInstance derived_from="CMP" determined="infoFile" id="CMP" location="0x40024000"/&gt;
+&lt;peripheralInstance derived_from="DMATRIGMUX" determined="infoFile" id="DMATRIGMUX" location="0x40028000"/&gt;
+&lt;peripheralInstance derived_from="INPUTMUX" determined="infoFile" id="INPUTMUX" location="0x4002c000"/&gt;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x40040000"/&gt;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;
+&lt;peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40050000"/&gt;
+&lt;peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x40054000"/&gt;
+&lt;peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40058000"/&gt;
+&lt;peripheralInstance derived_from="SPI1" determined="infoFile" id="SPI1" location="0x4005c000"/&gt;
+&lt;peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40064000"/&gt;
+&lt;peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x40068000"/&gt;
+&lt;peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x4006c000"/&gt;
+&lt;peripheralInstance derived_from="I2C2" determined="infoFile" id="I2C2" location="0x40070000"/&gt;
+&lt;peripheralInstance derived_from="I2C3" determined="infoFile" id="I2C3" location="0x40074000"/&gt;
+&lt;peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x50000000"/&gt;
+&lt;peripheralInstance derived_from="SCT" determined="infoFile" id="SCT" location="0x50004000"/&gt;
+&lt;peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x50008000"/&gt;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0xa0000000"/&gt;
+&lt;peripheralInstance derived_from="PIN-INT" determined="infoFile" id="PIN-INT" location="0xa0004000"/&gt;
+&lt;/chip&gt;
+&lt;processor&gt;&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;
+&lt;family&gt;Cortex-M&lt;/family&gt;
+&lt;/processor&gt;
+&lt;link href="LPC82x_peripheral.xme" show="embed" type="simple"/&gt;
+&lt;/info&gt;
+&lt;/infoList&gt;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc824_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc824_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpc824_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpccappuccino_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpccappuccino_cproject.tmpl
new file mode 100755
index 0000000..0fce520
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpccappuccino_cproject.tmpl
@@ -0,0 +1,51 @@
+{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc11xx.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U37/501" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC11U37/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U37/501" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC11U37/501&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpccappuccino_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpccappuccino_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/lpccappuccino_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/project_common.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/project_common.tmpl
new file mode 100755
index 0000000..42ef438
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/project_common.tmpl
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+    <name>{{name}}</name>
+    <comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red</comment>
+    <projects>
+    </projects>
+    <buildSpec>
+        <buildCommand>
+            <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+            <triggers>clean,full,incremental,</triggers>
+            <arguments>
+                <dictionary>
+                    <key>?name?</key>
+                    <value></value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.append_environment</key>
+                    <value>true</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+                    <value>all</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.buildArguments</key>
+                    <value></value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.buildCommand</key>
+                    <value>make</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.buildLocation</key>
+                    <value>${workspace_loc:/{{name}}/Debug}</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+                    <value>clean</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.contents</key>
+                    <value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+                    <value>false</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+                    <value>true</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+                    <value>true</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+                    <value>all</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.stopOnError</key>
+                    <value>true</value>
+                </dictionary>
+                <dictionary>
+                    <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+                    <value>true</value>
+                </dictionary>
+            </arguments>
+        </buildCommand>
+        <buildCommand>
+            <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+            <triggers>full,incremental,</triggers>
+            <arguments>
+            </arguments>
+        </buildCommand>
+    </buildSpec>
+    <natures>
+        <nature>org.eclipse.cdt.core.cnature</nature>
+        <nature>org.eclipse.cdt.core.ccnature</nature>
+        <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+        <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+    </natures>
+</projectDescription>
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/ublox_c027_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/ublox_c027_cproject.tmpl
new file mode 100755
index 0000000..291569d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/ublox_c027_cproject.tmpl
@@ -0,0 +1,79 @@
+{% extends "lpcxpresso/cproject_cortexm3_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc176x.c{% endblock %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1768&lt;/name&gt;&#13;
+&lt;family&gt;LPC17xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/ublox_c027_project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/ublox_c027_project.tmpl
new file mode 100755
index 0000000..8b0351e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/lpcxpresso/ublox_c027_project.tmpl
@@ -0,0 +1 @@
+{% extends "lpcxpresso/project_common.tmpl" %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/Makefile.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/Makefile.tmpl
new file mode 100755
index 0000000..2c7240d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/Makefile.tmpl
@@ -0,0 +1,165 @@
+# This file was automagically generated by mbed.org. For more information, 
+# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
+
+###############################################################################
+# Boiler-plate
+
+# cross-platform directory manipulation
+ifeq ($(shell echo $$OS),$$OS)
+    MAKEDIR = if not exist "$(1)" mkdir "$(1)"
+    RM = rmdir /S /Q "$(1)"
+else
+    MAKEDIR = '$(SHELL)' -c "mkdir -p \"$(1)\""
+    RM = '$(SHELL)' -c "rm -rf \"$(1)\""
+endif
+
+OBJDIR := BUILD
+# Move to the build directory
+ifeq (,$(filter $(OBJDIR),$(notdir $(CURDIR))))
+.SUFFIXES:
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
+MAKETARGET = '$(MAKE)' --no-print-directory -C $(OBJDIR) -f '$(mkfile_path)' \
+		'SRCDIR=$(CURDIR)' $(MAKECMDGOALS)
+.PHONY: $(OBJDIR) clean
+all:
+	+@$(call MAKEDIR,$(OBJDIR))
+	+@$(MAKETARGET)
+$(OBJDIR): all
+Makefile : ;
+% :: $(OBJDIR) ; :
+clean :
+	$(call RM,$(OBJDIR))
+{% block target_clean -%}
+{% endblock %}
+else
+
+# trick rules into thinking we are in the root, when we are in the bulid dir
+VPATH = {{vpath|join(" ")}}
+
+# Boiler-plate
+###############################################################################
+# Project settings
+
+PROJECT := {{name}}
+
+
+# Project settings
+###############################################################################
+# Objects and Paths
+
+{% for obj in to_be_compiled %}OBJECTS += {{obj}}
+{% endfor %}
+{% for obj in object_files %} SYS_OBJECTS += {{obj}}
+{% endfor %}
+{% for path in include_paths %}INCLUDE_PATHS += -I{{path}}
+{% endfor %}
+LIBRARY_PATHS :={% for p in library_paths %} {{user_library_flag}}{{p}} {% endfor %}
+LIBRARIES :={% for lib in libraries %} {{lib}} {% endfor %}
+LINKER_SCRIPT ?= {{linker_script}}
+{%- block additional_variables -%}{% endblock %}
+
+# Objects and Paths
+###############################################################################
+# Tools and Flags
+
+AS      = {{asm_cmd}}
+CC      = {{cc_cmd}}
+CPP     = {{cppc_cmd}}
+LD      = {{ld_cmd}}
+ELF2BIN = {{elf2bin_cmd}}
+{% if pp_cmd -%}
+PREPROC = {{pp_cmd}}
+{%- endif %}
+{% if hex_files %}
+SREC_CAT = srec_cat
+{%- endif %}
+{%- block additional_executables -%}{%- endblock %}
+
+{% for flag in c_flags %}C_FLAGS += {{flag}}
+{% endfor %}
+{% for flag in cxx_flags %}CXX_FLAGS += {{flag}}
+{% endfor %}
+{% for flag in asm_flags %}ASM_FLAGS += {{flag}}
+{% endfor %}
+
+LD_FLAGS :={%- block ld_flags -%} {{ld_flags|join(" ")}} {% endblock %}
+LD_SYS_LIBS :={%- block sys_libs -%} {{ld_sys_libs|join(" ")}} {% endblock %}
+
+# Tools and Flags
+###############################################################################
+# Rules
+
+.PHONY: all lst size
+
+{% if hex_files -%}
+all: $(PROJECT).bin $(PROJECT)-combined.hex size
+{% else %}
+all: $(PROJECT).bin $(PROJECT).hex size
+{% endif %}
+
+.s.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Assemble: $(notdir $<)"
+  {% if needs_asm_preproc %}
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -E -o $(@:.o=.E.s) $<
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $(@:.o=.E.s)
+  {% else %}
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+  {% endif %}
+
+
+.S.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Assemble: $(notdir $<)"
+  {% if needs_asm_preproc %}
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -E -o $(@:.o=.E.s) $<
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $(@:.o=.E.s)
+  {% else %}
+	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+  {% endif %}
+
+.c.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Compile: $(notdir $<)"
+	@$(CC) $(C_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+
+.cpp.o:
+	+@$(call MAKEDIR,$(dir $@))
+	+@echo "Compile: $(notdir $<)"
+	@$(CPP) $(CXX_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+
+{% if pp_cmd %}
+$(PROJECT).link_script{{link_script_ext}}: $(LINKER_SCRIPT)
+	@$(PREPROC) $< -o $@
+{% endif %}
+
+{% block target_project_elf %}
+$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) {% if pp_cmd -%} $(PROJECT).link_script{{link_script_ext}} {% else%} $(LINKER_SCRIPT) {% endif %}
+	+@echo "link: $(notdir $@)"
+	@$(LD) $(LD_FLAGS) {{link_script_option}} $(filter-out %.o, $^) $(LIBRARY_PATHS) --output $@ $(filter %.o, $^) $(LIBRARIES) $(LD_SYS_LIBS)
+{% endblock %}
+
+$(PROJECT).bin: $(PROJECT).elf
+{%- block elf2bin -%}{%- endblock %}
+{% if not hex_files %}	+@echo "===== bin file ready to flash: $(OBJDIR)/$@ =====" {% endif %}
+
+$(PROJECT).hex: $(PROJECT).elf
+{%- block elf2hex -%}{%- endblock %}
+
+{% if hex_files %}
+$(PROJECT)-combined.hex: $(PROJECT).hex
+	+@echo "NOTE: the $(SREC_CAT) binary is required to be present in your PATH. Please see http://srecord.sourceforge.net/ for more information."
+	$(SREC_CAT) {% for f in hex_files %}{{f}} {% endfor %} -intel $(PROJECT).hex -intel -o $(PROJECT)-combined.hex -intel --line-length=44
+	+@echo "===== hex file ready to flash: $(OBJDIR)/$@ ====="
+{% endif %}
+# Rules
+###############################################################################
+# Dependencies
+
+DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
+-include $(DEPS)
+endif
+
+# Dependencies
+###############################################################################
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/__init__.py
new file mode 100755
index 0000000..cab9226
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/__init__.py
@@ -0,0 +1,268 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import splitext, basename, relpath, join, abspath, dirname,\
+    exists
+from os import remove
+import sys
+from subprocess import check_output, CalledProcessError, Popen, PIPE
+import shutil
+from jinja2.exceptions import TemplateNotFound
+from tools.export.exporters import Exporter, apply_supported_whitelist
+from tools.utils import NotSupportedException
+from tools.targets import TARGET_MAP
+
+
+class Makefile(Exporter):
+    """Generic Makefile template that mimics the behavior of the python build
+    system
+    """
+
+    DOT_IN_RELATIVE_PATH = True
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    PREPROCESS_ASM = False
+
+    POST_BINARY_WHITELIST = set([
+        "MCU_NRF51Code.binary_hook",
+        "TEENSY3_1Code.binary_hook",
+        "LPCTargetCode.lpc_patch",
+        "LPC4088Code.binary_hook"
+    ])
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return apply_supported_whitelist(
+            cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target)
+
+    def generate(self):
+        """Generate the makefile
+
+        Note: subclasses should not need to override this method
+        """
+        if not self.resources.linker_script:
+            raise NotSupportedException("No linker script found.")
+
+        self.resources.win_to_unix()
+
+        to_be_compiled = [splitext(src)[0] + ".o" for src in
+                          self.resources.s_sources +
+                          self.resources.c_sources +
+                          self.resources.cpp_sources]
+
+        libraries = [self.prepare_lib(basename(lib)) for lib
+                     in self.resources.libraries]
+        sys_libs = [self.prepare_sys_lib(lib) for lib
+                    in self.toolchain.sys_libs]
+
+        ctx = {
+            'name': self.project_name,
+            'to_be_compiled': to_be_compiled,
+            'object_files': self.resources.objects,
+            'include_paths': list(set(self.resources.inc_dirs)),
+            'library_paths': self.resources.lib_dirs,
+            'linker_script': self.resources.linker_script,
+            'libraries': libraries,
+            'ld_sys_libs': sys_libs,
+            'hex_files': self.resources.hex_files,
+            'vpath': (["../../.."]
+                      if (basename(dirname(dirname(self.export_dir)))
+                          == "projectfiles")
+                      else [".."]),
+            'cc_cmd': " ".join(["\'" + part + "\'" for part
+                                in ([basename(self.toolchain.cc[0])] +
+                                    self.toolchain.cc[1:])]),
+            'cppc_cmd': " ".join(["\'" + part + "\'" for part
+                                  in ([basename(self.toolchain.cppc[0])] +
+                                      self.toolchain.cppc[1:])]),
+            'asm_cmd': " ".join(["\'" + part + "\'" for part
+                                in ([basename(self.toolchain.asm[0])] +
+                                    self.toolchain.asm[1:])]),
+            'ld_cmd': "\'" + basename(self.toolchain.ld[0]) + "\'",
+            'elf2bin_cmd': "\'" + basename(self.toolchain.elf2bin) + "\'",
+            'link_script_ext': self.toolchain.LINKER_EXT,
+            'link_script_option': self.LINK_SCRIPT_OPTION,
+            'user_library_flag': self.USER_LIBRARY_FLAG,
+            'needs_asm_preproc': self.PREPROCESS_ASM,
+        }
+
+        if hasattr(self.toolchain, "preproc"):
+            ctx['pp_cmd'] = " ".join(["\'" + part + "\'" for part
+                                      in ([basename(self.toolchain.preproc[0])] +
+                                          self.toolchain.preproc[1:] + 
+                                          self.toolchain.ld[1:])])
+        else:
+            ctx['pp_cmd'] = None
+
+        for key in ['include_paths', 'library_paths', 'linker_script',
+                    'hex_files']:
+            if isinstance(ctx[key], list):
+                ctx[key] = [ctx['vpath'][0] + "/" + t for t in ctx[key]]
+            else:
+                ctx[key] = ctx['vpath'][0] + "/" + ctx[key]
+        if "../." not in ctx["include_paths"]:
+            ctx["include_paths"] += ['../.']
+        for key in ['include_paths', 'library_paths', 'hex_files',
+                    'to_be_compiled']:
+            ctx[key] = sorted(ctx[key])
+        ctx.update(self.format_flags())
+
+        for templatefile in \
+            ['makefile/%s_%s.tmpl' % (self.TEMPLATE,
+                                      self.target.lower())] + \
+            ['makefile/%s_%s.tmpl' % (self.TEMPLATE,
+                                      label.lower()) for label
+             in self.toolchain.target.extra_labels] +\
+            ['makefile/%s.tmpl' % self.TEMPLATE]:
+            try:
+                self.gen_file(templatefile, ctx, 'Makefile')
+                break
+            except TemplateNotFound:
+                pass
+        else:
+            raise NotSupportedException("This make tool is in development")
+
+    def format_flags(self):
+        """Format toolchain flags for Makefile"""
+        flags = {}
+        for k, v in self.flags.iteritems():
+            if k in ['asm_flags', 'c_flags', 'cxx_flags']:
+                flags[k] = map(lambda x: x.replace('"', '\\"'), v)
+            else:
+                flags[k] = v
+
+        return flags
+
+    @staticmethod
+    def build(project_name, log_name="build_log.txt", cleanup=True):
+        """ Build Make project """
+        # > Make -j
+        cmd = ["make", "-j"]
+
+        # Build the project
+        p = Popen(cmd, stdout=PIPE, stderr=PIPE)
+        out, err = p.communicate()
+        ret_code = p.returncode
+
+        out_string = "=" * 10 + "STDOUT" + "=" * 10 + "\n"
+        out_string += out
+        out_string += "=" * 10 + "STDERR" + "=" * 10 + "\n"
+        out_string += err
+
+        if ret_code == 0:
+            out_string += "SUCCESS"
+        else:
+            out_string += "FAILURE"
+
+        print out_string
+
+        if log_name:
+            # Write the output to the log file
+            with open(log_name, 'w+') as f:
+                f.write(out_string)
+
+        # Cleanup the exported and built files
+        if cleanup:
+            remove("Makefile")
+            remove(log_name)
+            # legacy .build directory cleaned if exists
+            if exists('.build'):
+                shutil.rmtree('.build')
+            if exists('BUILD'):
+                shutil.rmtree('BUILD')
+
+        if ret_code != 0:
+            # Seems like something went wrong.
+            return -1
+        else:
+            return 0
+
+
+class GccArm(Makefile):
+    """GCC ARM specific makefile target"""
+    NAME = 'Make-GCC-ARM'
+    TEMPLATE = 'make-gcc-arm'
+    TOOLCHAIN = "GCC_ARM"
+    LINK_SCRIPT_OPTION = "-T"
+    USER_LIBRARY_FLAG = "-L"
+
+    @staticmethod
+    def prepare_lib(libname):
+        if "lib" == libname[:3]:
+            libname = libname[3:-2]
+        return "-l" + libname
+
+    @staticmethod
+    def prepare_sys_lib(libname):
+        return "-l" + libname
+
+
+class Arm(Makefile):
+    """ARM Compiler generic makefile target"""
+    LINK_SCRIPT_OPTION = "--scatter"
+    USER_LIBRARY_FLAG = "--userlibpath "
+    TEMPLATE = 'make-arm'
+
+    @staticmethod
+    def prepare_lib(libname):
+        return libname
+
+    @staticmethod
+    def prepare_sys_lib(libname):
+        return libname
+
+    def generate(self):
+        if self.resources.linker_script:
+            new_script = self.toolchain.correct_scatter_shebang(
+                self.resources.linker_script)
+            if new_script is not self.resources.linker_script:
+                self.resources.linker_script = new_script
+                self.generated_files.append(new_script)
+        return super(Arm, self).generate()
+
+class Armc5(Arm):
+    """ARM Compiler 5 (armcc) specific makefile target"""
+    NAME = 'Make-ARMc5'
+    TOOLCHAIN = "ARM"
+    PREPROCESS_ASM = True
+
+class Armc6(Arm):
+    """ARM Compiler 6 (armclang) specific generic makefile target"""
+    NAME = 'Make-ARMc6'
+    TOOLCHAIN = "ARMC6"
+
+
+class IAR(Makefile):
+    """IAR specific makefile target"""
+    NAME = 'Make-IAR'
+    TEMPLATE = 'make-iar'
+    TOOLCHAIN = "IAR"
+    LINK_SCRIPT_OPTION = "--config"
+    USER_LIBRARY_FLAG = "-L"
+
+    @staticmethod
+    def prepare_lib(libname):
+        if "lib" == libname[:3]:
+            libname = libname[3:]
+        return "-l" + splitext(libname)[0]
+
+    @staticmethod
+    def prepare_sys_lib(libname):
+        if "lib" == libname[:3]:
+            libname = libname[3:]
+        return "-l" + splitext(libname)[0]
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/__init__.pyc
new file mode 100755
index 0000000..49df138
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-arm.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-arm.tmpl
new file mode 100755
index 0000000..eac6a51
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-arm.tmpl
@@ -0,0 +1,9 @@
+{% extends "makefile/Makefile.tmpl" %}
+
+{% block elf2bin %}
+	$(ELF2BIN) --bin --output $@ $< 
+{%- endblock %}
+
+{% block elf2hex %}
+	$(ELF2BIN) --i32 --output $@ $< 
+{%- endblock %}
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-gcc-arm.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-gcc-arm.tmpl
new file mode 100755
index 0000000..5231c65
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-gcc-arm.tmpl
@@ -0,0 +1,11 @@
+{% extends "makefile/Makefile.tmpl" %}
+
+{%- block sys_libs -%} -Wl,--start-group {{ld_sys_libs|join(" ")}} {{libraries|join(" ")}} -Wl,--end-group {%- endblock -%}
+
+{% block elf2bin %}
+	$(ELF2BIN) -O binary $< $@
+{%- endblock %}
+
+{% block elf2hex %}
+	$(ELF2BIN) -O ihex $< $@
+{%- endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-iar.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-iar.tmpl
new file mode 100755
index 0000000..30a2058
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/makefile/make-iar.tmpl
@@ -0,0 +1,9 @@
+{% extends "makefile/Makefile.tmpl" %}
+
+{% block elf2bin %}
+	$(ELF2BIN) --bin $< $@
+{%- endblock %}
+
+{% block elf2hex %}
+	$(ELF2BIN) --ihex $< $@
+{%- endblock %}
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/.cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/.cproject.tmpl
new file mode 100755
index 0000000..f405c51
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/.cproject.tmpl
@@ -0,0 +1,278 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}
+		<cconfiguration id="com.crt.advproject.config.exe.{{opts['id']}}.{{opts['uid']['config']}}">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.{{opts['id']}}.{{opts['uid']['config']}}" moduleId="org.eclipse.cdt.core.settings" name="{{opts['name']}}">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="{{opts['name']}} build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.{{opts['id']}}.{{opts['uid']['config']}}" name="{{opts['name']}}" parent="com.crt.advproject.config.exe.{{opts['id']}}" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot; ; arm-none-eabi-objcopy -v -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;">
+					<folderInfo id="com.crt.advproject.config.exe.{{opts['id']}}.{{opts['uid']['config']}}" name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.exe.{{opts['id']}}.{{u.id}}" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.{{opts['parent_id']}}">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.{{opts['id']}}.{{u.id}}" name="ARM-based MCU ({{opts['name']}})" superClass="com.crt.advproject.platform.exe.{{opts['id']}}"/>
+							<builder buildPath="${workspace_loc:/{{name}}}/{{opts['name']}}" cleanBuildTarget="mbedclean" id="com.crt.advproject.builder.exe.{{opts['id']}}.{{u.id}}" incrementalBuildTarget="{{opts['ld']['script']}} all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.crt.advproject.builder.exe.{{opts['id']}}"/>
+
+							<tool id="com.crt.advproject.cpp.exe.{{opts['id']}}.{{opts['uid']['tool_cpp_compiler']}}" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.{{opts['id']}}">
+								<option id="com.crt.advproject.cpp.specs.{{u.id}}" name="Specs" superClass="com.crt.advproject.cpp.specs"  value="com.crt.advproject.cpp.specs.newlibnano" valueType="enumerated"/>
+								<option id="com.crt.advproject.cpp.arch.{{u.id}}" name="Architecture" superClass="com.crt.advproject.cpp.arch"  value="com.crt.advproject.cpp.target.{{opts['common']['arm.target.family_nxp']}}" valueType="enumerated"/>
+                                {% if opts['common']['optimization.level'] != '' %}
+							    <option id="com.crt.advproject.cpp.exe.{{opts['id']}}.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="com.crt.advproject.cpp.exe.{{opts['id']}}.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.{{opts['common']['optimization.level']}}" valueType="enumerated"/>
+                                {% endif %}
+								<option id="gnu.cpp.compiler.option.optimization.flags.{{u.id}}" superClass="gnu.cpp.compiler.option.optimization.flags" useByScannerDiscovery="false" value="{{opts['cpp']['otheroptimizations']}} {{opts['common']['optimization.other']}}" valueType="string"/>
+								{% if opts['cpp']['compiler.std'] %}
+								<option id="com.crt.advproject.cpp.misc.dialect.{{u.id}}" name="Language standard" superClass="com.crt.advproject.cpp.misc.dialect" useByScannerDiscovery="true" value="com.crt.advproject.misc.dialect.{{opts['cpp']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+
+								<option id="gnu.cpp.compiler.option.preprocessor.def.{{u.id}}" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def"  valueType="definedSymbols">
+									{% for s in opts['cpp']['defines'] %}
+									<listOptionValue builtIn="false" value="{{s|replace("\"", "\\\"")|escape}}"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.cpp.compiler.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths"  valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.cpp.compiler.option.include.files.{{u.id}}" name="Include files (-include)" superClass="gnu.cpp.compiler.option.include.files"  valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+
+                                {% if opts['common']['warnings.syntaxonly'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.syntax.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.syntax" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.pedantic'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.pedantic.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.pedantic" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.pedanticerrors'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.pedantic.error.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.pedantic.error" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.nowarn'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.nowarn.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.nowarn" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.allwarn'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.allwarn.{{u.id}}" name="Enable all common warnings (-Wall)" superClass="gnu.cpp.compiler.option.warnings.allwarn" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.extrawarn'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.extrawarn.{{u.id}}" name="Enable extra warnings (-Wextra)" superClass="gnu.cpp.compiler.option.warnings.extrawarn" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.toerrors'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.toerrors.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.toerrors" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.conversion'] %}
+                                <option id="gnu.cpp.compiler.option.warnings.wconversion.{{u.id}}" name="Warn on implicit conversions (-Wconversion)" superClass="gnu.cpp.compiler.option.warnings.wconversion" value="true" valueType="boolean"/>
+                                {% endif %}
+
+                                {% if opts['common']['optimization.lto'] %}
+								<option id="com.crt.advproject.cpp.lto.{{u.id}}" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.cpp.lto" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['optimization.lto_objects'] %}
+								<option id="com.crt.advproject.cpp.lto.fat.{{u.id}}" name="Fat lto objects (-ffat-lto-objects)" superClass="com.crt.advproject.cpp.lto.fat" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                {% endif %}
+
+								{% if opts['cpp']['verbose'] %}
+   								<option id="gnu.cpp.compiler.option.other.verbose.{{u.id}}" name="Verbose (-v)" superClass="gnu.cpp.compiler.option.other.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['arm.target.fpu.unit_nxp'] %}
+   								<option id="com.crt.advproject.cpp.fpu.{{u.id}}" name="Floating point" superClass="com.crt.advproject.cpp.fpu" useByScannerDiscovery="false" value="com.crt.advproject.cpp.fpu.{{opts['common']['arm.target.fpu.unit_nxp']}}" valueType="enumerated"/>
+                                {% endif %}
+								<option id="gnu.cpp.compiler.option.other.other.{{u.id}}" superClass="gnu.cpp.compiler.option.other.other" useByScannerDiscovery="false" value="-c {{opts['cpp']['other']}} {{opts['common']['warnings.other']}}" valueType="string"/>
+								<inputType id="com.crt.advproject.compiler.cpp.input.{{opts['uid']['tool_cpp_compiler_input']}}" superClass="com.crt.advproject.compiler.cpp.input"/>
+							</tool>
+
+							<tool id="com.crt.advproject.gcc.exe.{{opts['id']}}.{{opts['uid']['tool_c_compiler']}}" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.{{opts['id']}}">
+								<option id="com.crt.advproject.gcc.hdrlib.{{u.id}}" name="Library headers" superClass="com.crt.advproject.gcc.hdrlib"  value="com.crt.advproject.gcc.hdrlib.newlibnano" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.specs.{{u.id}}" name="Specs" superClass="com.crt.advproject.gcc.specs"  value="com.crt.advproject.gcc.specs.newlibnano" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.arch.{{u.id}}" name="Architecture" superClass="com.crt.advproject.gcc.arch"  value="com.crt.advproject.gcc.target.{{opts['common']['arm.target.family_nxp']}}" valueType="enumerated"/>
+                                {% if opts['common']['optimization.level'] != '' %}
+								<option id="com.crt.advproject.gcc.exe.{{opts['id']}}.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.{{opts['id']}}.option.optimization.level" useByScannerDiscovery="false" value="gnu.c.optimization.level.{{opts['common']['optimization.level']}}" valueType="enumerated"/>
+                                {% endif %}
+								<option id="gnu.c.compiler.option.optimization.flags.{{u.id}}" superClass="gnu.c.compiler.option.optimization.flags" useByScannerDiscovery="false" value="{{opts['c']['otheroptimizations']}} {{opts['common']['optimization.other']}}" valueType="string"/>
+
+								{% if opts['c']['compiler.std'] %}
+								<option id="com.crt.advproject.c.misc.dialect.{{u.id}}" name="Language standard" superClass="com.crt.advproject.c.misc.dialect" useByScannerDiscovery="true" value="com.crt.advproject.misc.dialect.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+								<option id="gnu.c.compiler.option.preprocessor.def.symbols.{{u.id}}" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols"  valueType="definedSymbols">
+									{% for s in opts['c']['defines'] %}
+										<listOptionValue builtIn="false" value="{{s|replace("\"", "\\\"")|escape}}"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.c.compiler.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths"  valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.c.compiler.option.include.files.{{u.id}}" name="Include files (-include)" superClass="gnu.c.compiler.option.include.files"  valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+
+                                {% if opts['common']['warnings.syntaxonly'] %}
+                                <option id="gnu.c.compiler.option.warnings.syntax.{{u.id}}" superClass="gnu.c.compiler.option.warnings.syntax" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.pedantic'] %}
+                                <option id="gnu.c.compiler.option.warnings.pedantic.{{u.id}}" superClass="gnu.c.compiler.option.warnings.pedantic" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.pedanticerrors'] %}
+                                <option id="gnu.c.compiler.option.warnings.pedantic.error.{{u.id}}" superClass="gnu.c.compiler.option.warnings.pedantic.error" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.nowarn'] %}
+                                <option id="gnu.c.compiler.option.warnings.nowarn.{{u.id}}" superClass="gnu.c.compiler.option.warnings.nowarn" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.allwarn'] %}
+                                <option id="gnu.c.compiler.option.warnings.allwarn.{{u.id}}" name="Enable all common warnings (-Wall)" superClass="gnu.c.compiler.option.warnings.allwarn" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.extrawarn'] %}
+                                <option id="gnu.c.compiler.option.warnings.extrawarn.{{u.id}}" name="Enable extra warnings (-Wextra)" superClass="gnu.c.compiler.option.warnings.extrawarn" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.toerrors'] %}
+                                <option id="gnu.c.compiler.option.warnings.toerrors.{{u.id}}" superClass="gnu.c.compiler.option.warnings.toerrors" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['warnings.conversion'] %}
+                                <option id="gnu.c.compiler.option.warnings.wconversion.{{u.id}}" name="Warn on implicit conversions (-Wconversion)" superClass="gnu.c.compiler.option.warnings.wconversion" value="true" valueType="boolean"/>
+                                {% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="gnu.c.compiler.option.misc.verbose.{{u.id}}" name="Verbose (-v)" superClass="gnu.c.compiler.option.misc.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['arm.target.fpu.unit_nxp'] %}
+								<option id="com.crt.advproject.gcc.fpu.{{u.id}}" name="Floating point" superClass="com.crt.advproject.gcc.fpu" useByScannerDiscovery="false" value="com.crt.advproject.gcc.fpu.{{opts['common']['arm.target.fpu.unit_nxp']}}" valueType="enumerated"/>
+                                {% endif %}
+
+                                {% if opts['common']['optimization.lto'] %}
+								<option id="com.crt.advproject.gcc.lto.{{u.id}}" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.gcc.lto" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                {% endif %}
+                                {% if opts['common']['optimization.lto_objects'] %}
+								<option id="com.crt.advproject.gcc.lto.fat.{{u.id}}" name="Fat lto objects (-ffat-lto-objects)" superClass="com.crt.advproject.gcc.lto.fat" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                {% endif %}
+
+								<option id="gnu.c.compiler.option.misc.other.{{u.id}}" superClass="gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="-c {{opts['c']['other']}} {{opts['common']['warnings.other']}}" valueType="string"/>
+								<inputType id="com.crt.advproject.compiler.input.{{opts['uid']['tool_c_compiler']}}" superClass="com.crt.advproject.compiler.input"/>
+							</tool>
+
+							<tool id="com.crt.advproject.gas.exe.{{opts['id']}}.{{u.id}}" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.{{opts['id']}}">
+								<option id="com.crt.advproject.gas.hdrlib.{{u.id}}" name="Library headers" superClass="com.crt.advproject.gas.hdrlib"  value="com.crt.advproject.gas.hdrlib.newlibnano" valueType="enumerated"/>
+								<option id="com.crt.advproject.gas.specs.{{u.id}}" name="Specs" superClass="com.crt.advproject.gas.specs"  value="com.crt.advproject.gas.specs.newlibnano" valueType="enumerated"/>
+								<option id="com.crt.advproject.gas.arch.{{u.id}}" name="Architecture" superClass="com.crt.advproject.gas.arch"  value="com.crt.advproject.gas.target.{{opts['common']['arm.target.family_nxp']}}" valueType="enumerated"/>
+								<option id="gnu.both.asm.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths"  valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.{{u.id}}" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+                                {% if opts['common']['arm.target.fpu.unit_nxp'] %}
+								<option id="com.crt.advproject.gas.fpu.{{u.id}}" name="Floating point" superClass="com.crt.advproject.gas.fpu" useByScannerDiscovery="false" value="com.crt.advproject.gas.fpu.{{opts['common']['arm.target.fpu.unit_nxp']}}" valueType="enumerated"/>
+                                {% endif %}
+								<option id="gnu.both.asm.option.flags.crt.{{u.id}}" superClass="gnu.both.asm.option.flags.crt" useByScannerDiscovery="false" value="-c {{opts['as']['other']}}" valueType="string"/>
+								{% if opts['as']['verbose'] %}
+								<option id="gnu.both.asm.option.version.{{u.id}}" superClass="gnu.both.asm.option.version" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+                                {% endif %}
+								<inputType id="com.crt.advproject.assembler.input.{{u.id}}" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+							</tool>
+
+							<tool commandLinePattern="${COMMAND} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS} ${FLAGS}" id="com.crt.advproject.link.cpp.exe.{{opts['id']}}.{{u.id}}" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.{{opts['id']}}">
+								<option defaultValue="com.crt.advproject.heapAndStack.lpcXpressoStyle.cpp" id="com.crt.advproject.link.memory.heapAndStack.style.cpp.{{u.id}}" name="Heap and Stack placement" superClass="com.crt.advproject.link.memory.heapAndStack.style.cpp" useByScannerDiscovery="false" value="com.crt.advproject.heapAndStack.lpcXpressoStyle.cpp" valueType="enumerated"/>
+								<option id="com.crt.advproject.link.memory.heapAndStack.cpp.{{u.id}}" name="Heap and Stack options" superClass="com.crt.advproject.link.memory.heapAndStack.cpp" useByScannerDiscovery="false" value="&amp;Heap:Default;Post Data;Default&amp;Stack:Default;End;Default" valueType="string"/>
+								<option id="com.crt.advproject.link.cpp.multicore.master.{{u.id}}" name="Multicore master" superClass="com.crt.advproject.link.cpp.multicore.master" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.cpp.multicore.master.userobjs.{{u.id}}" name="Slave Objects (not visible)" superClass="com.crt.advproject.link.cpp.multicore.master.userobjs" useByScannerDiscovery="false" valueType="userObjs"/>
+								<option id="com.crt.advproject.link.cpp.arch.{{u.id}}" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" useByScannerDiscovery="false" value="com.crt.advproject.link.cpp.target.{{opts['common']['arm.target.family_nxp']}}" valueType="enumerated"/>
+								<option id="gnu.cpp.link.option.paths.{{u.id}}" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" useByScannerDiscovery="false">
+									{% for path in opts['ld']['library_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.cpp.link.option.libs.{{u.id}}" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" useByScannerDiscovery="false" valueType="libs">
+                                    {% for lib in opts['ld']['user_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+									{% for lib in opts['ld']['system_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.cpp.link.option.userobjs.{{u.id}}" name="Other objects" superClass="gnu.cpp.link.option.userobjs" useByScannerDiscovery="false">
+									{% for path in opts['ld']['object_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+
+								<option id="gnu.cpp.link.option.other.{{u.id}}" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other"  useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+									<listOptionValue builtIn="false" value="-print-memory-usage"/>
+                                    {% if opts['ld']['gcsections'] %}
+                                    <listOptionValue builtIn="false" value="--gc-sections"/>
+                                    {% endif %}
+									{% for opt in opts['ld']['flags'] %}
+									<listOptionValue builtIn="false" value="{{opt}}"/>
+									{% endfor %}
+								</option>
+
+								{% if opts['ld']['nostart'] %}
+								<option id="gnu.cpp.link.option.nostart.{{u.id}}" name="Do not use standard start files (-nostartfiles)" superClass="gnu.cpp.link.option.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nodeflibs'] %}
+								<option id="gnu.cpp.link.option.nodeflibs.{{u.id}}" name="Do not use default libraries (-nodefaultlibs)" superClass="gnu.cpp.link.option.nodeflibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nostdlibs'] %}
+								<option id="gnu.cpp.link.option.nostdlibs.{{u.id}}" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['other'] != '' %}
+								<option id="gnu.cpp.link.option.flags.{{u.id}}" superClass="gnu.cpp.link.option.flags" useByScannerDiscovery="false"  value="{{opts['ld']['other']}}" valueType="string"/>
+								{% endif %}
+
+                                {% if opts['common']['optimization.lto'] %}
+								<option id="com.crt.advproject.link.cpp.lto.{{u.id}}" superClass="com.crt.advproject.link.cpp.lto" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+
+								<option id="com.crt.advproject.link.cpp.script.{{u.id}}" name="Linker script" superClass="com.crt.advproject.link.cpp.script" useByScannerDiscovery="false" value="${ProjDirPath}/{{opts['name']}}/{{opts['ld']['script']}}"  valueType="string"/>
+
+                                <option id="com.crt.advproject.link.cpp.multicore.slave.{{u.id}}" name="Multicore configuration" superClass="com.crt.advproject.link.cpp.multicore.slave" useByScannerDiscovery="false"/>
+                                {% if opts['common']['arm.target.fpu.unit_nxp'] %}
+								<option id="com.crt.advproject.link.cpp.fpu.{{u.id}}" name="Floating point" superClass="com.crt.advproject.link.cpp.fpu" useByScannerDiscovery="false" value="com.crt.advproject.link.cpp.fpu.{{opts['common']['arm.target.fpu.unit_nxp']}}" valueType="enumerated"/>
+                                {% endif %}
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.{{u.id}}" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+
+							<tool id="com.crt.advproject.link.exe.{{opts['id']}}.{{u.id}}" name="MCU Linker" superClass="com.crt.advproject.link.exe.{{opts['id']}}"/>
+
+                            </toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="{{opts['common']['excluded_folders']}}" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}.com.crt.advproject.projecttype.exe.{{u.id}}" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.crt.config">
+		<projectStorage>{% block cpu_config %}{% endblock %}</projectStorage>
+	</storageModule>
+	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
+		<sdkName>{% block sdk_name %}{% endblock %}</sdkName>
+		<sdkVersion>{% block sdk_version %}{% endblock %}</sdkVersion>
+	</storageModule>
+	<storageModule moduleId="com.crt.advproject"/>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/.project.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/.project.tmpl
new file mode 100755
index 0000000..cc88934
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/.project.tmpl
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Generated by the GNU ARM Eclipse exporter from an mBed project. -->
+<projectDescription>
+	<name>{{name}}</name>
+	<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-GNU-ARM-Eclipse</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/K64F_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/K64F_cproject.tmpl
new file mode 100755
index 0000000..4c26364
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/K64F_cproject.tmpl
@@ -0,0 +1,98 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_3="NXP" property_4="MK64FN1M0xxx12" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="MK64FN1M0xxx12" name="MK64FN1M0xxx12"&gt;&lt;chip&gt;&lt;name&gt;MK64FN1M0xxx12&lt;/name&gt;&#13;
+&lt;family&gt;K6x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP&lt;/vendor&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" size="1024" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" size="256" type="RAM"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" driver="FTFE_4K.cfx" id="PROGRAM_FLASH" location="0x0" size="0x100000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="SRAM_UPPER" location="0x20000000" size="0x30000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="SRAM_LOWER" location="0x1fff0000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="FLEX_RAM" location="0x14000000" size="0x1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FTFE_FlashConfig" id="FTFE_FlashConfig" location="0x400"/&gt;&#13;
+&lt;peripheralInstance derived_from="AIPS0" id="AIPS0" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="AIPS1" id="AIPS1" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="AXBS" id="AXBS" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA" id="DMA" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FB" id="FB" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSMPU" id="SYSMPU" location="0x4000D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FMC" id="FMC" location="0x4001F000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FTFE" id="FTFE" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMAMUX" id="DMAMUX" location="0x40021000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN0" id="CAN0" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RNG" id="RNG" location="0x40029000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" id="SPI0" location="0x4002C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI1" id="SPI1" location="0x4002D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI2" id="SPI2" location="0x400AC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S0" id="I2S0" location="0x4002F000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x40032000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USBDCD" id="USBDCD" location="0x40035000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PDB0" id="PDB0" location="0x40036000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PIT" id="PIT" location="0x40037000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FTM0" id="FTM0" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FTM1" id="FTM1" location="0x40039000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FTM2" id="FTM2" location="0x4003A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FTM3" id="FTM3" location="0x400B9000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x4003B000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x400BB000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x4003D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RFVBAT" id="RFVBAT" location="0x4003E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPTMR0" id="LPTMR0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RFSYS" id="RFSYS" location="0x40041000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SIM" id="SIM" location="0x40047000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PORTA" id="PORTA" location="0x40049000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PORTB" id="PORTB" location="0x4004A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PORTC" id="PORTC" location="0x4004B000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PORTD" id="PORTD" location="0x4004C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PORTE" id="PORTE" location="0x4004D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WDOG" id="WDOG" location="0x40052000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EWM" id="EWM" location="0x40061000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CMT" id="CMT" location="0x40062000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCG" id="MCG" location="0x40064000"/&gt;&#13;
+&lt;peripheralInstance derived_from="OSC" id="OSC" location="0x40065000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x40066000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x40067000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x400E6000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART0" id="UART0" location="0x4006A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x4006B000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART2" id="UART2" location="0x4006C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART3" id="UART3" location="0x4006D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART4" id="UART4" location="0x400EA000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART5" id="UART5" location="0x400EB000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB0" id="USB0" location="0x40072000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CMP0" id="CMP0" location="0x40073000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CMP1" id="CMP1" location="0x40073008"/&gt;&#13;
+&lt;peripheralInstance derived_from="CMP2" id="CMP2" location="0x40073010"/&gt;&#13;
+&lt;peripheralInstance derived_from="VREF" id="VREF" location="0x40074000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LLWU" id="LLWU" location="0x4007C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMC" id="PMC" location="0x4007D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SMC" id="SMC" location="0x4007E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RCM" id="RCM" location="0x4007F000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDHC" id="SDHC" location="0x400B1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ENET" id="ENET" location="0x400C0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC0" id="DAC0" location="0x400CC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC1" id="DAC1" location="0x400CD000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOA" id="GPIOA" location="0x400FF000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOB" id="GPIOB" location="0x400FF040"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOC" id="GPIOC" location="0x400FF080"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOD" id="GPIOD" location="0x400FF0C0"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOE" id="GPIOE" location="0x400FF100"/&gt;&#13;
+&lt;peripheralInstance derived_from="SystemControl" id="SystemControl" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SysTick" id="SysTick" location="0xE000E010"/&gt;&#13;
+&lt;peripheralInstance derived_from="NVIC" id="NVIC" location="0xE000E100"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCM" id="MCM" location="0xE0080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAU" id="CAU" location="0xE0081000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="MK64F12_internal_peripheral.xml" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
+
+{% block sdk_name %}SDK_2.x_FRDM-K64F{% endblock %}
+{% block sdk_version %}2.2.0{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC11U37H_401_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC11U37H_401_cproject.tmpl
new file mode 100755
index 0000000..8de3327
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC11U37H_401_cproject.tmpl
@@ -0,0 +1,46 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_2="LPC11_12_13_128K_8K.cfx" property_3="NXP" property_4="LPC11U37H/401" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC11U37H/401" flash_driver="LPC11_12_13_128K_8K.cfx" match_id="0x0" name="LPC11U37H/401" stub="crt_emu_lpc11_13_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC11U37H/401&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash128" location="0x0" size="0x20000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamIoh2" location="0x20000000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC1549_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC1549_cproject.tmpl
new file mode 100755
index 0000000..55a4667
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC1549_cproject.tmpl
@@ -0,0 +1,63 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_2="LPC15xx_256K.cfx" property_3="NXP" property_4="LPC1549" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC1549" connectscript="LPC15RunBootRomConnect.scp" flash_driver="LPC15xx_256K.cfx" match_id="0x0" name="LPC1549" resetscript="LPC15RunBootRomReset.scp" stub="crt_emu_cm3_gen"&gt;&lt;chip&gt;&lt;name&gt;LPC1549&lt;/name&gt;&#13;
+&lt;family&gt;LPC15xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram0_16" location="0x2000000" size="0x4000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram1_16" location="0x2004000" size="0x4000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram2_4" location="0x2008000" size="0x1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x1c000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA" id="DMA" location="0x1c004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x1c00c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x1c010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT0" id="SCT0" location="0x1c018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT1" id="SCT1" location="0x1c01c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT2" id="SCT2" location="0x1c020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT3" id="SCT3" location="0x1c024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ACMP" id="ACMP" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="INMUX" id="INMUX" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40028000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SWM" id="SWM" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" id="PMU" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART1" id="USART1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" id="SPI0" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI1" id="SPI1" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x40050000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40074000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MRT" id="MRT" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PINT" id="PINT" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT0" id="GINT0" location="0x400a8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT1" id="GINT1" location="0x400ac000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RIT" id="RIT" location="0x400b4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCTIPU" id="SCTIPU" location="0x400b8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400f0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x400f8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC15xx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC54114_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC54114_cproject.tmpl
new file mode 100755
index 0000000..8ab537c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC54114_cproject.tmpl
@@ -0,0 +1,87 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="None" property_2="LPC5411x_256K.cfx" property_3="NXP" property_4="LPC54114J256" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC54114J256" flash_driver="LPC5411x_256K.cfx" match_id="0x0" name="LPC54114J256" stub="crt_emu_cm3_gen"&gt;&lt;chip&gt;&lt;name&gt;LPC54114J256&lt;/name&gt;&#13;
+&lt;family&gt;LPC5411x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram0_64" location="0x20000000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram1_64" location="0x20010000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram2_32" location="0x20020000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamX_32" location="0x4000000" size="0x8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x40001000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT0" id="GINT0" location="0x40002000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT1" id="GINT1" location="0x40003000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PINT" id="PINT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="INPUT-MUX" id="INPUT-MUX" location="0x40005000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" id="CT32B0" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" id="CT32B1" location="0x40009000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MRT" id="MRT" location="0x4000d000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UTICK" id="UTICK" location="0x4000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B2" id="CT32B2" location="0x40028000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B3" id="CT32B3" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B4" id="CT32B4" location="0x40049000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA" id="DMA" location="0x40082000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x40084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT" id="SCT" location="0x40085000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" id="SPI0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM1" id="FLEXCOMM1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI1" id="SPI1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART1" id="USART1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI2" id="SPI2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM2" id="FLEXCOMM2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM3" id="FLEXCOMM3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C3" id="I2C3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART3" id="USART3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI3" id="SPI3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM4" id="FLEXCOMM4" location="0x4008a000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI4" id="SPI4" location="0x4008a000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART4" id="USART4" location="0x4008a000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C4" id="I2C4" location="0x4008a000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MAILBOX" id="MAILBOX" location="0x4008b000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO" id="GPIO" location="0x4008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMIC" id="DMIC" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC-ENGINE" id="CRC-ENGINE" location="0x40095000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C6" id="I2C6" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART7" id="USART7" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI6" id="SPI6" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C5" id="I2C5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI5" id="SPI5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI7" id="SPI7" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM5" id="FLEXCOMM5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART6" id="USART6" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART5" id="USART5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C7" id="I2C7" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM6" id="FLEXCOMM6" location="0x40097000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S0" id="I2S0" location="0x40097000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S1" id="I2S1" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM7" id="FLEXCOMM7" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x400a0000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC5411x_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC546XX_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC546XX_cproject.tmpl
new file mode 100755
index 0000000..bb2a0d6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC546XX_cproject.tmpl
@@ -0,0 +1,106 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_3="NXP" property_4="LPC54608J512" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC54608J512" name="LPC54608J512"&gt;&lt;chip&gt;&lt;name&gt;LPC54608J512&lt;/name&gt;&#13;
+&lt;family&gt;LPC546xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP&lt;/vendor&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" size="512" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" size="200" type="RAM"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" driver="LPC5460x_512K.cfx" id="PROGRAM_FLASH" location="0x0" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="SRAM_0_1_2_3" location="0x20000000" size="0x28000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="SRAMX" location="0x4000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="USB_RAM" location="0x40100000" size="0x2000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x40001000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT0" id="GINT0" location="0x40002000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT1" id="GINT1" location="0x40003000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PINT" id="PINT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="INPUTMUX" id="INPUTMUX" location="0x40005000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CTIMER0" id="CTIMER0" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CTIMER1" id="CTIMER1" location="0x40009000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CTIMER2" id="CTIMER2" location="0x40028000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CTIMER3" id="CTIMER3" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CTIMER4" id="CTIMER4" location="0x40049000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MRT0" id="MRT0" location="0x4000D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UTICK0" id="UTICK0" location="0x4000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="OTPC" id="OTPC" location="0x40015000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x4002C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RIT" id="RIT" location="0x4002D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FMC" id="FMC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SMARTCARD0" id="SMARTCARD0" location="0x40036000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SMARTCARD1" id="SMARTCARD1" location="0x40037000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ASYNC_SYSCON" id="ASYNC_SYSCON" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPIFI0" id="SPIFI0" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x40081000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA0" id="DMA0" location="0x40082000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x40083000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB0" id="USB0" location="0x40084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT0" id="SCT0" location="0x40085000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" id="SPI0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI1" id="SPI1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI2" id="SPI2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI3" id="SPI3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI4" id="SPI4" location="0x4008A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI5" id="SPI5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI6" id="SPI6" location="0x40097000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI7" id="SPI7" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI8" id="SPI8" location="0x40099000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI9" id="SPI9" location="0x4009A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM1" id="FLEXCOMM1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM2" id="FLEXCOMM2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM3" id="FLEXCOMM3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM4" id="FLEXCOMM4" location="0x4008A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM5" id="FLEXCOMM5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM6" id="FLEXCOMM6" location="0x40097000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM7" id="FLEXCOMM7" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM8" id="FLEXCOMM8" location="0x40099000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLEXCOMM9" id="FLEXCOMM9" location="0x4009A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C3" id="I2C3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C4" id="I2C4" location="0x4008A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C5" id="I2C5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C6" id="I2C6" location="0x40097000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C7" id="I2C7" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C8" id="I2C8" location="0x40099000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C9" id="I2C9" location="0x4009A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART1" id="USART1" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART3" id="USART3" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART4" id="USART4" location="0x4008A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART5" id="USART5" location="0x40096000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART6" id="USART6" location="0x40097000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART7" id="USART7" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART8" id="USART8" location="0x40099000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART9" id="USART9" location="0x4009A000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO" id="GPIO" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMIC0" id="DMIC0" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ENET" id="ENET" location="0x40092000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USBHSD" id="USBHSD" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC_ENGINE" id="CRC_ENGINE" location="0x40095000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S0" id="I2S0" location="0x40097000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S1" id="I2S1" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDIF" id="SDIF" location="0x4009B000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN0" id="CAN0" location="0x4009D000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN1" id="CAN1" location="0x4009E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USBFSH" id="USBFSH" location="0x400A2000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USBHSH" id="USBHSH" location="0x400A3000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC54608_internal_peripheral.xml" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
+
+{% block sdk_name %}SDK_2.x_LPCXpresso54608{% endblock %}
+{% block sdk_version %}2.2.0{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC824_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC824_cproject.tmpl
new file mode 100755
index 0000000..f635ba3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/LPC824_cproject.tmpl
@@ -0,0 +1,51 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_2="LPC800_32.cfx" property_3="NXP" property_4="LPC824" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC824" flash_driver="LPC800_32.cfx" match_id="0x0" name="LPC824" stub="crt_emu_cm3_gen"&gt;&lt;chip&gt;&lt;name&gt;LPC824&lt;/name&gt;&#13;
+&lt;family&gt;LPC82x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MRT" id="MRT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WKT" id="WKT" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SWM" id="SWM" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" id="PMU" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CMP" id="CMP" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMATRIGMUX" id="DMATRIGMUX" location="0x40028000"/&gt;&#13;
+&lt;peripheralInstance derived_from="INPUTMUX" id="INPUTMUX" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x40050000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x40054000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" id="SPI0" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI1" id="SPI1" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40064000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART1" id="USART1" location="0x40068000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x4006c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x40070000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C3" id="I2C3" location="0x40074000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT" id="SCT" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA" id="DMA" location="0x50008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0xa0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PIN-INT" id="PIN-INT" location="0xa0004000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC82x_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/__init__.py
new file mode 100755
index 0000000..6d21949
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/__init__.py
@@ -0,0 +1,742 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Title: MCUXpresso exporter.
+
+Description: Creates a managed build project that can be imported by
+the MCUXpresso IDE from NXP
+
+Based on GNU ARM Eclipse Exporter from Liviu Ionescu <ilg@livius.net>
+modified for MCUXpresso by Johannes Stratmann <jojos62@online.de>
+"""
+
+import copy
+import tempfile
+import shutil
+
+from subprocess import Popen, PIPE
+from os import getcwd, remove
+from os.path import splitext, basename, exists
+from random import randint
+
+from tools.export.gnuarmeclipse import GNUARMEclipse, UID
+from tools.export.exporters import apply_supported_whitelist
+from tools.targets import TARGET_MAP
+from tools.utils import NotSupportedException
+from tools.build_api import prepare_toolchain
+
+
+# =============================================================================
+
+
+POST_BINARY_WHITELIST = set([
+    "TEENSY3_1Code.binary_hook",
+    "MCU_NRF51Code.binary_hook",
+    "LPCTargetCode.lpc_patch",
+    "LPC4088Code.binary_hook"
+])
+
+class MCUXpresso(GNUARMEclipse):
+    NAME = 'MCUXpresso'
+    TOOLCHAIN = 'GCC_ARM'
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        # targes suppoerted when .cproject templatefile exists
+        if exists(cls.TEMPLATE_DIR + '/mcuxpresso/' + target_name + '_cproject.tmpl'):
+            target = TARGET_MAP[target_name]
+            return apply_supported_whitelist(
+                cls.TOOLCHAIN, POST_BINARY_WHITELIST, target)
+        else:
+            return False
+
+    # override
+    def generate(self):
+        """
+        Generate the .project and .cproject files.
+        """
+        if not self.resources.linker_script:
+            raise NotSupportedException("No linker script found.")
+
+        print
+        print 'Create a GNU ARM Eclipse C++ managed project'
+        print 'Project name: {0}'.format(self.project_name)
+        print 'Target: {0}'.format(self.toolchain.target.name)
+        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
+
+        self.resources.win_to_unix()
+
+        # TODO: use some logger to display additional info if verbose
+
+        self.libraries = []
+        # print 'libraries'
+        # print self.resources.libraries
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            self.libraries.append(l[3:])
+
+        self.system_libraries = [
+            'stdc++', 'supc++', 'm', 'c', 'gcc', 'nosys'
+        ]
+
+        # Read in all profiles, we'll extract compiler options.
+        profiles = self.get_all_profiles()
+
+        profile_ids = [s.lower() for s in profiles]
+        profile_ids.sort()
+
+        # TODO: get the list from existing .cproject
+        build_folders = [s.capitalize() for s in profile_ids]
+        build_folders.append('BUILD')
+        # print build_folders
+
+        objects = [self.filter_dot(s) for s in self.resources.objects]
+        for bf in build_folders:
+            objects = [o for o in objects if not o.startswith(bf + '/')]
+        # print 'objects'
+        # print objects
+
+        self.compute_exclusions()
+
+        self.include_path = [
+            self.filter_dot(s) for s in self.resources.inc_dirs]
+        print 'Include folders: {0}'.format(len(self.include_path))
+
+        self.as_defines = self.toolchain.get_symbols(True)
+        self.c_defines = self.toolchain.get_symbols()
+        self.cpp_defines = self.c_defines
+        print 'Symbols: {0}'.format(len(self.c_defines))
+
+        self.ld_script = self.filter_dot(
+            self.resources.linker_script)
+        print 'Linker script: {0}'.format(self.ld_script)
+
+        self.options = {}
+        profile_ids.remove('develop')
+        for id in profile_ids:
+
+            # There are 4 categories of options, a category common too
+            # all tools and a specific category for each of the tools.
+            opts = {}
+            opts['common'] = {}
+            opts['as'] = {}
+            opts['c'] = {}
+            opts['cpp'] = {}
+            opts['ld'] = {}
+
+            opts['id'] = id
+            opts['name'] = opts['id'].capitalize()
+
+            print
+            print 'Build configuration: {0}'.format(opts['name'])
+
+            profile = profiles[id]
+
+            # A small hack, do not bother with src_path again,
+            # pass an empty string to avoid crashing.
+            src_paths = ['']
+            target_name = self.toolchain.target.name
+            toolchain = prepare_toolchain(
+                src_paths, "", target_name, self.TOOLCHAIN, build_profile=[profile])
+
+            # Hack to fill in build_dir
+            toolchain.build_dir = self.toolchain.build_dir
+
+            flags = self.toolchain_flags(toolchain)
+
+            print 'Common flags:', ' '.join(flags['common_flags'])
+            print 'C++ flags:', ' '.join(flags['cxx_flags'])
+            print 'C flags:', ' '.join(flags['c_flags'])
+            print 'ASM flags:', ' '.join(flags['asm_flags'])
+            print 'Linker flags:', ' '.join(flags['ld_flags'])
+
+            # Most GNU ARM Eclipse options have a parent,
+            # either debug or release.
+            if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']:
+                opts['parent_id'] = 'debug'
+            else:
+                opts['parent_id'] = 'release'
+
+            self.process_options(opts, flags)
+
+            opts['as']['defines'] = self.as_defines
+            opts['c']['defines'] = self.c_defines
+            opts['cpp']['defines'] = self.cpp_defines
+
+            opts['common']['include_paths'] = self.include_path
+            opts['common']['excluded_folders'] = '|'.join(
+                self.excluded_folders)
+            self.excluded_folders = [item.replace("\\", "/") for item in self.excluded_folders]
+
+            opts['ld']['library_paths'] = [
+                self.filter_dot(s) for s in self.resources.lib_dirs]
+
+            opts['ld']['object_files'] = objects
+            opts['ld']['user_libraries'] = self.libraries
+            opts['ld']['system_libraries'] = self.system_libraries
+            opts['ld']['script'] = "linker-script-%s.ld" % id
+            opts['cpp_cmd'] = " ".join(toolchain.preproc)
+
+            # Unique IDs used in multiple places.
+            # Those used only once are implemented with {{u.id}}.
+            u = UID()
+            uid = {}
+            uid['config'] = u.id
+            uid['tool_c_compiler'] = u.id
+            uid['tool_c_compiler_input'] = u.id
+            uid['tool_cpp_compiler'] = u.id
+            uid['tool_cpp_compiler_input'] = u.id
+
+            opts['uid'] = uid
+
+            self.options[id] = opts
+
+        jinja_ctx = {
+            'name': self.project_name,
+            'ld_script': self.ld_script,
+
+            # Compiler & linker command line options
+            'options': self.options,
+
+            # Must be an object with an `id` property, which
+            # will be called repeatedly, to generate multiple UIDs.
+            'u': u,
+        }
+
+        self.gen_file('mcuxpresso/.project.tmpl', jinja_ctx,
+                      '.project', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('mcuxpresso/{0}_cproject.tmpl'.format(target_name), jinja_ctx,
+                      '.cproject', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('mcuxpresso/makefile.targets.tmpl', jinja_ctx,
+                      'makefile.targets', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('mcuxpresso/mbedignore.tmpl', jinja_ctx, '.mbedignore')
+
+        print
+        print 'Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name)
+
+    # override
+    @staticmethod
+    def build(project_name, log_name="build_log.txt", cleanup=True):
+        """
+        Headless build an Eclipse project.
+
+        The following steps are performed:
+        - a temporary workspace is created,
+        - the project is imported,
+        - a clean build of all configurations is performed and
+        - the temporary workspace is removed.
+
+        The build results are in the Debug & Release folders.
+
+        All executables (eclipse & toolchain) must be in the PATH.
+
+        The general method to start a headless Eclipse build is:
+
+        $ eclipse \
+        --launcher.suppressErrors \
+        -nosplash \
+        -application org.eclipse.cdt.managedbuilder.core.headlessbuild \
+        -data /path/to/workspace \
+        -import /path/to/project \
+        -cleanBuild "project[/configuration] | all"
+        """
+
+        # TODO: possibly use the log file.
+
+        # Create a temporary folder for the workspace.
+        tmp_folder = tempfile.mkdtemp()
+
+        cmd = [
+            'mcuxpressoide',
+            '--launcher.suppressErrors',
+            '-nosplash',
+            '-application org.eclipse.cdt.managedbuilder.core.headlessbuild',
+            '-data', tmp_folder,
+            '-import', getcwd(),
+            '-cleanBuild', project_name
+        ]
+
+        p = Popen(' '.join(cmd), shell=True, stdout=PIPE, stderr=PIPE)
+        out, err = p.communicate()
+        ret_code = p.returncode
+        stdout_string = "=" * 10 + "STDOUT" + "=" * 10 + "\n"
+        err_string = "=" * 10 + "STDERR" + "=" * 10 + "\n"
+        err_string += err
+        success = any(l.startswith("Finished building target:") for l in out.split("\n"))
+
+        if success:
+            ret_string = "SUCCESS\n"
+        else:
+            ret_string = "FAILURE: build returned %s \n" % ret_code
+
+        print "%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string)
+
+        if log_name:
+            # Write the output to the log file
+            with open(log_name, 'w+') as f:
+                f.write(stdout_string)
+                f.write(out)
+                f.write(err_string)
+                f.write(ret_string)
+
+        # Cleanup the exported and built files
+        if cleanup:
+            if exists(log_name):
+                remove(log_name)
+            remove('.project')
+            remove('.cproject')
+            if exists('Debug'):
+                shutil.rmtree('Debug')
+            if exists('Release'):
+                shutil.rmtree('Release')
+            if exists('makefile.targets'):
+                remove('makefile.targets')
+
+        # Always remove the temporary folder.
+        if exists(tmp_folder):
+            shutil.rmtree(tmp_folder)
+
+        return not(success)
+
+
+    # -------------------------------------------------------------------------
+
+    def process_options(self, opts, flags_in):
+        """
+        CDT managed projects store lots of build options in separate
+        variables, with separate IDs in the .cproject file.
+        When the CDT build is started, all these options are brought
+        together to compose the compiler and linker command lines.
+
+        Here the process is reversed, from the compiler and linker
+        command lines, the options are identified and various flags are
+        set to control the template generation process.
+
+        Once identified, the options are removed from the command lines.
+
+        The options that were not identified are options that do not
+        have CDT equivalents and will be passed in the 'Other options'
+        categories.
+
+        Although this process does not have a very complicated logic,
+        given the large number of explicit configuration options
+        used by the GNU ARM Eclipse managed build plug-in, it is tedious...
+        """
+
+        # Make a copy of the flags, to be one by one removed after processing.
+        flags = copy.deepcopy(flags_in)
+
+        if False:
+            print
+            print 'common_flags', flags['common_flags']
+            print 'asm_flags', flags['asm_flags']
+            print 'c_flags', flags['c_flags']
+            print 'cxx_flags', flags['cxx_flags']
+            print 'ld_flags', flags['ld_flags']
+
+        # Initialise the 'last resort' options where all unrecognised
+        # options will be collected.
+        opts['as']['other'] = ''
+        opts['c']['other'] = ''
+        opts['cpp']['other'] = ''
+        opts['ld']['other'] = ''
+
+        MCPUS = {
+            'Cortex-M0': {'mcpu': 'cortex-m0', 'fpu_unit': None},
+            'Cortex-M0+': {'mcpu': 'cortex-m0plus', 'fpu_unit': None},
+            'Cortex-M1': {'mcpu': 'cortex-m1', 'fpu_unit': None},
+            'Cortex-M3': {'mcpu': 'cortex-m3', 'fpu_unit': None},
+            'Cortex-M4': {'mcpu': 'cortex-m4', 'fpu_unit': None},
+            'Cortex-M4F': {'mcpu': 'cortex-m4', 'fpu_unit': 'fpv4spd16'},
+            'Cortex-M7': {'mcpu': 'cortex-m7', 'fpu_unit': None},
+            'Cortex-M7F': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv4spd16'},
+            'Cortex-M7FD': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv5d16'},
+            'Cortex-A9': {'mcpu': 'cortex-a9', 'fpu_unit': 'vfpv3'}
+        }
+
+        MCPU_NXP = {
+            'cortex-m7' : 'cm7',
+            'cortex-m4' : 'cm4',
+            'cortex-m3' : 'cm3',
+            'cortex-m1' : 'cm1',
+            'cortex-m0' : 'cm0',
+            'cortex-m0.small-multiply' : 'cm0.smallmul',
+            'cortex-m0plus' : 'cm0plus',
+            'cortex-m0plus.small-multiply' : 'cm0plus.smallmul'
+        }
+
+        # Remove options that are supplied by CDT
+        self.remove_option(flags['common_flags'], '-c')
+        self.remove_option(flags['common_flags'], '-MMD')
+
+        # As 'plan B', get the CPU from the target definition.
+        core = self.toolchain.target.core
+
+        opts['common']['arm.target.family'] = None
+
+        # cortex-m0, cortex-m0-small-multiply, cortex-m0plus,
+        # cortex-m0plus-small-multiply, cortex-m1, cortex-m1-small-multiply,
+        # cortex-m3, cortex-m4, cortex-m7.
+        str = self.find_options(flags['common_flags'], '-mcpu=')
+        if str != None:
+            opts['common']['arm.target.family'] = str[len('-mcpu='):]
+            opts['common']['arm.target.family_nxp'] = MCPU_NXP[str[len('-mcpu='):]]
+            self.remove_option(flags['common_flags'], str)
+            self.remove_option(flags['ld_flags'], str)
+        else:
+            if core not in MCPUS:
+                raise NotSupportedException(
+                    'Target core {0} not supported.'.format(core))
+            opts['common']['arm.target.family'] = MCPUS[core]['mcpu']
+
+        opts['common']['arm.target.arch'] = 'none'
+        str = self.find_options(flags['common_flags'], '-march=')
+        arch = str[len('-march='):]
+        archs = {'armv6-m': 'armv6-m', 'armv7-m': 'armv7-m', 'armv7-a': 'armv7-a'}
+        if arch in archs:
+            opts['common']['arm.target.arch'] = archs[arch]
+            self.remove_option(flags['common_flags'], str)
+
+        opts['common']['arm.target.instructionset'] = 'thumb'
+        if '-mthumb' in flags['common_flags']:
+            self.remove_option(flags['common_flags'], '-mthumb')
+            self.remove_option(flags['ld_flags'], '-mthumb')
+        elif '-marm' in flags['common_flags']:
+            opts['common']['arm.target.instructionset'] = 'arm'
+            self.remove_option(flags['common_flags'], '-marm')
+            self.remove_option(flags['ld_flags'], '-marm')
+
+        opts['common']['arm.target.thumbinterwork'] = False
+        if '-mthumb-interwork' in flags['common_flags']:
+            opts['common']['arm.target.thumbinterwork'] = True
+            self.remove_option(flags['common_flags'], '-mthumb-interwork')
+
+        opts['common']['arm.target.endianness'] = None
+        if '-mlittle-endian' in flags['common_flags']:
+            opts['common']['arm.target.endianness'] = 'little'
+            self.remove_option(flags['common_flags'], '-mlittle-endian')
+        elif '-mbig-endian' in flags['common_flags']:
+            opts['common']['arm.target.endianness'] = 'big'
+            self.remove_option(flags['common_flags'], '-mbig-endian')
+
+        opts['common']['arm.target.fpu.unit'] = None
+        opts['common']['arm.target.fpu.unit_nxp'] = None
+        # default, fpv4spd16, fpv5d16, fpv5spd16
+        str = self.find_options(flags['common_flags'], '-mfpu=')
+        if str != None:
+            fpu = str[len('-mfpu='):]
+            fpus = {
+                'fpv4-sp-d16': 'fpv4spd16',
+                'fpv5-d16': 'fpv5d16',
+                'fpv5-sp-d16': 'fpv5spd16'
+            }
+            fpus_nxp = {
+                'fpv4-sp-d16': 'fpv4',
+                'fpv5-d16': 'fpv5dp',
+                'fpv5-sp-d16': 'fpv5sp'
+            }
+            if fpu in fpus:
+                opts['common']['arm.target.fpu.unit'] = fpus[fpu]
+                opts['common']['arm.target.fpu.unit_nxp'] = fpus_nxp[fpu]
+
+                self.remove_option(flags['common_flags'], str)
+                self.remove_option(flags['ld_flags'], str)
+        if opts['common']['arm.target.fpu.unit'] == None:
+            if core not in MCPUS:
+                raise NotSupportedException(
+                    'Target core {0} not supported.'.format(core))
+            if MCPUS[core]['fpu_unit']:
+                opts['common'][
+                    'arm.target.fpu.unit'] = MCPUS[core]['fpu_unit']
+
+        # soft, softfp, hard.
+        str = self.find_options(flags['common_flags'], '-mfloat-abi=')
+        if str != None:
+            opts['common']['arm.target.fpu.abi'] = str[
+                len('-mfloat-abi='):]
+            self.remove_option(flags['common_flags'], str)
+            self.remove_option(flags['ld_flags'], str)
+            if opts['common']['arm.target.fpu.abi'] == 'hard':
+                opts['common']['arm.target.fpu.unit_nxp'] += '.hard'
+
+        # Default optimisation level for Release.
+        opts['common']['optimization.level'] = '-Os'
+
+        # If the project defines an optimisation level, it is used
+        # only for the Release configuration, the Debug one used '-Og'.
+        str = self.find_options(flags['common_flags'], '-O')
+        if str != None:
+            levels = {
+                '-O0': 'none', '-O1': 'optimize', '-O2': 'more',
+                '-O3': 'most', '-Os': 'size', '-Og': 'debug'
+            }
+            if str in levels:
+                opts['common']['optimization.level'] = levels[str]
+                self.remove_option(flags['common_flags'], str)
+
+        include_files = []
+        for all_flags in [flags['common_flags'], flags['c_flags'], flags['cxx_flags']]:
+            while '-include' in all_flags:
+                ix = all_flags.index('-include')
+                str = all_flags[ix + 1]
+                if str not in include_files:
+                    include_files.append(str)
+                self.remove_option(all_flags, '-include')
+                self.remove_option(all_flags, str)
+
+        opts['common']['include_files'] = include_files
+
+        if '-ansi' in flags['c_flags']:
+            opts['c']['compiler.std'] = '-ansi'
+            self.remove_option(flags['c_flags'], str)
+        else:
+            str = self.find_options(flags['c_flags'], '-std')
+            std = str[len('-std='):]
+            c_std = {
+                'c90': 'c90', 'c89': 'c90', 'gnu90': 'gnu90', 'gnu89': 'gnu90',
+                'c99': 'c99', 'c9x': 'c99', 'gnu99': 'gnu99', 'gnu9x': 'gnu98',
+                'c11': 'c11', 'c1x': 'c11', 'gnu11': 'gnu11', 'gnu1x': 'gnu11'
+            }
+            if std in c_std:
+                opts['c']['compiler.std'] = c_std[std]
+                self.remove_option(flags['c_flags'], str)
+
+        if '-ansi' in flags['cxx_flags']:
+            opts['cpp']['compiler.std'] = '-ansi'
+            self.remove_option(flags['cxx_flags'], str)
+        else:
+            str = self.find_options(flags['cxx_flags'], '-std')
+            std = str[len('-std='):]
+            cpp_std = {
+                'c++98': 'cpp98', 'c++03': 'cpp03',
+                'gnu++98': 'gnupp98', 'gnu++03': 'gnupp03',
+                'c++0x': 'cpp03', 'gnu++0x': 'gnupp03',
+                'c++11': 'cpp11', 'gnu++11': 'gnupp11',
+                'c++1y': 'cpp11', 'gnu++1y': 'gnupp11',
+                'c++14': 'cpp14', 'gnu++14': 'gnupp14',
+                'c++1z': 'cpp1z', 'gnu++1z': 'gnupp1z',
+            }
+            if std in cpp_std:
+                opts['cpp']['compiler.std'] = cpp_std[std]
+                self.remove_option(flags['cxx_flags'], str)
+
+        # Common optimisation options.
+        optimization_options = {
+            '-flto': 'optimization.lto',
+            '--ffat-lto-objects': 'optimization.lto_objects'
+        }
+        for option in optimization_options:
+            opts['common'][optimization_options[option]] = False
+            if option in flags['common_flags']:
+                opts['common'][optimization_options[option]] = True
+                self.remove_option(flags['common_flags'], option)
+
+        # Common warning options.
+        warning_options = {
+            '-fsyntax-only': 'warnings.syntaxonly',
+            '-pedantic': 'warnings.pedantic',
+            '-pedantic-errors': 'warnings.pedanticerrors',
+            '-w': 'warnings.nowarn',
+            '-Wall': 'warnings.allwarn',
+            '-Wextra': 'warnings.extrawarn',
+            '-Wconversion': 'warnings.conversion',
+            '-Werror': 'warnings.toerrors',
+        }
+
+        for option in warning_options:
+            opts['common'][warning_options[option]] = False
+            if option in flags['common_flags']:
+                opts['common'][warning_options[option]] = True
+                self.remove_option(flags['common_flags'], option)
+
+        # Common debug options.
+        debug_levels = {
+            '-g': 'default',
+            '-g1': 'minimal',
+            '-g3': 'max',
+        }
+        opts['common']['debugging.level'] = 'none'
+        for option in debug_levels:
+            if option in flags['common_flags']:
+                opts['common'][
+                    'debugging.level'] = debug_levels[option]
+                self.remove_option(flags['common_flags'], option)
+
+
+        opts['common']['debugging.prof'] = False
+        if '-p' in flags['common_flags']:
+            opts['common']['debugging.prof'] = True
+            self.remove_option(flags['common_flags'], '-p')
+
+        opts['common']['debugging.gprof'] = False
+        if '-pg' in flags['common_flags']:
+            opts['common']['debugging.gprof'] = True
+            self.remove_option(flags['common_flags'], '-gp')
+
+        # Assembler options.
+        opts['as']['usepreprocessor'] = False
+        while '-x' in flags['asm_flags']:
+            ix = flags['asm_flags'].index('-x')
+            str = flags['asm_flags'][ix + 1]
+
+            if str == 'assembler-with-cpp':
+                opts['as']['usepreprocessor'] = True
+            else:
+                # Collect all other assembler options.
+                opts['as']['other'] += ' -x ' + str
+
+            self.remove_option(flags['asm_flags'], '-x')
+            self.remove_option(flags['asm_flags'], 'assembler-with-cpp')
+
+        opts['as']['nostdinc'] = False
+        if '-nostdinc' in flags['asm_flags']:
+            opts['as']['nostdinc'] = True
+            self.remove_option(flags['asm_flags'], '-nostdinc')
+
+        opts['as']['verbose'] = False
+        if '-v' in flags['asm_flags']:
+            opts['as']['verbose'] = True
+            self.remove_option(flags['asm_flags'], '-v')
+
+        # C options.
+        opts['c']['nostdinc'] = False
+        if '-nostdinc' in flags['c_flags']:
+            opts['c']['nostdinc'] = True
+            self.remove_option(flags['c_flags'], '-nostdinc')
+
+        opts['c']['verbose'] = False
+        if '-v' in flags['c_flags']:
+            opts['c']['verbose'] = True
+            self.remove_option(flags['c_flags'], '-v')
+
+
+        # C++ options.
+        opts['cpp']['nostdinc'] = False
+        if '-nostdinc' in flags['cxx_flags']:
+            opts['cpp']['nostdinc'] = True
+            self.remove_option(flags['cxx_flags'], '-nostdinc')
+
+        opts['cpp']['nostdincpp'] = False
+        if '-nostdinc++' in flags['cxx_flags']:
+            opts['cpp']['nostdincpp'] = True
+            self.remove_option(flags['cxx_flags'], '-nostdinc++')
+
+        optimization_options = {
+            '-fno-exceptions': 'optimization.noexceptions',
+            '-fno-rtti': 'optimization.nortti',
+            '-fno-use-cxa-atexit': 'optimization.nousecxaatexit',
+            '-fno-threadsafe-statics': 'optimization.nothreadsafestatics',
+        }
+
+        for option in optimization_options:
+            opts['cpp'][optimization_options[option]] = False
+            if option in flags['cxx_flags']:
+                opts['cpp'][optimization_options[option]] = True
+            if option in flags['common_flags']:
+                opts['cpp'][optimization_options[option]] = True
+
+        opts['cpp']['verbose'] = False
+        if '-v' in flags['cxx_flags']:
+            opts['cpp']['verbose'] = True
+            self.remove_option(flags['cxx_flags'], '-v')
+
+        # Linker options.
+        linker_options = {
+            '-nostartfiles': 'nostart',
+            '-nodefaultlibs': 'nodeflibs',
+            '-nostdlib': 'nostdlibs',
+        }
+
+        for option in linker_options:
+            opts['ld'][linker_options[option]] = False
+            if option in flags['ld_flags']:
+                opts['ld'][linker_options[option]] = True
+                self.remove_option(flags['ld_flags'], option)
+
+        opts['ld']['gcsections'] = False
+        if '-Wl,--gc-sections' in flags['ld_flags']:
+            opts['ld']['gcsections'] = True
+            self.remove_option(flags['ld_flags'], '-Wl,--gc-sections')
+
+        opts['ld']['flags'] = []
+        to_remove = []
+        for opt in flags['ld_flags']:
+            if opt.startswith('-Wl,--wrap,'):
+                opts['ld']['flags'].append(
+                    '--wrap=' + opt[len('-Wl,--wrap,'):])
+                to_remove.append(opt)
+        for opt in to_remove:
+            self.remove_option(flags['ld_flags'], opt)
+
+        # Other tool remaining options are separated by category.
+        opts['as']['otherwarnings'] = self.find_options(
+            flags['asm_flags'], '-W')
+
+        opts['c']['otherwarnings'] = self.find_options(
+            flags['c_flags'], '-W')
+        opts['c']['otheroptimizations'] = self.find_options(flags[
+            'c_flags'], '-f')
+
+        opts['cpp']['otherwarnings'] = self.find_options(
+            flags['cxx_flags'], '-W')
+        opts['cpp']['otheroptimizations'] = self.find_options(
+            flags['cxx_flags'], '-f')
+
+        # Other common remaining options are separated by category.
+        opts['common']['optimization.other'] = self.find_options(
+            flags['common_flags'], '-f')
+        opts['common']['warnings.other'] = self.find_options(
+            flags['common_flags'], '-W')
+
+        # Remaining common flags are added to each tool.
+        opts['as']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + \
+            ' '.join(flags['asm_flags'])
+        opts['c']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + ' '.join(flags['c_flags'])
+        opts['cpp']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + \
+            ' '.join(flags['cxx_flags'])
+        opts['ld']['other'] += ' ' + \
+            ' '.join(flags['common_flags']) + ' ' + ' '.join(flags['ld_flags'])
+
+        if len(self.system_libraries) > 0:
+            opts['ld']['other'] += ' -Wl,--start-group '
+            opts['ld'][
+                'other'] += ' '.join('-l' + s for s in self.system_libraries) + ' '
+            opts['ld'][
+                'other'] += ' '.join('-l' + s for s in self.libraries)
+            opts['ld']['other'] += ' -Wl,--end-group '
+
+        # Strip all 'other' flags, since they might have leading spaces.
+        opts['as']['other'] = opts['as']['other'].strip()
+        opts['c']['other'] = opts['c']['other'].strip()
+        opts['cpp']['other'] = opts['cpp']['other'].strip()
+        opts['ld']['other'] = opts['ld']['other'].strip()
+
+        if False:
+            print
+            print opts
+
+            print
+            print 'common_flags', flags['common_flags']
+            print 'asm_flags', flags['asm_flags']
+            print 'c_flags', flags['c_flags']
+            print 'cxx_flags', flags['cxx_flags']
+            print 'ld_flags', flags['ld_flags']
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/__init__.pyc
new file mode 100755
index 0000000..ed02432
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/arch_pro_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/arch_pro_cproject.tmpl
new file mode 100755
index 0000000..89aad77
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/arch_pro_cproject.tmpl
@@ -0,0 +1,77 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1768&lt;/name&gt;&#13;
+&lt;family&gt;LPC17xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc1114_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc1114_cproject.tmpl
new file mode 100755
index 0000000..ce5be68
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc1114_cproject.tmpl
@@ -0,0 +1,46 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_32K_4K.cfx" property_3="NXP" property_4="LPC1114FN/102" property_count="5" version="60100"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1114FN/102" flash_driver="LPC11_12_13_32K_4K.cfx" match_id="0x0A40902B,0x1A40902B" name="LPC1114FN/102" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1114FN/102&lt;/name&gt;&#13;
+&lt;family&gt;LPC11xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc4" location="0x10000000" size="0x1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART" determined="infoFile" id="UART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO0" determined="infoFile" id="GPIO0" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO1" determined="infoFile" id="GPIO1" location="0x50010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO2" determined="infoFile" id="GPIO2" location="0x50020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO3" determined="infoFile" id="GPIO3" location="0x50030000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11xx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u35_401_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u35_401_cproject.tmpl
new file mode 100755
index 0000000..6d94414
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u35_401_cproject.tmpl
@@ -0,0 +1,49 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/401" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC11U35/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/401" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC11U35/401&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u35_501_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u35_501_cproject.tmpl
new file mode 100755
index 0000000..b192690
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u35_501_cproject.tmpl
@@ -0,0 +1,49 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/501" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC11U35/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/501" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC11U35/501&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u68_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u68_cproject.tmpl
new file mode 100755
index 0000000..f42f9b2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc11u68_cproject.tmpl
@@ -0,0 +1,58 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11U6x_256K.cfx" property_3="NXP" property_4="LPC11U68" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;&lt;info chip="LPC11U68" flash_driver="LPC11U6x_256K.cfx" match_id="0x0" name="LPC11U68" stub="crt_emu_cm3_gen"&gt;&#13;&lt;chip&gt;&#13;&lt;name&gt;&#13;LPC11U68&lt;/name&gt;&#13;
+&lt;family&gt;&#13;LPC11U6x&lt;/family&gt;&#13;
+&lt;vendor&gt;&#13;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram0_32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram1_2" location="0x20000000" size="0x800"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="Ram2USB_2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMATRIGMUX" determined="infoFile" id="DMATRIGMUX" location="0x40028000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART4" determined="infoFile" id="USART4" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT0" determined="infoFile" id="GINT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GINT1" determined="infoFile" id="GINT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x4006c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x40070000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART3" determined="infoFile" id="USART3" location="0x40074000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT0" determined="infoFile" id="SCT0" location="0x5000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT1" determined="infoFile" id="SCT1" location="0x5000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0xa0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PINT" determined="infoFile" id="PINT" location="0xa0004000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc1768_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc1768_cproject.tmpl
new file mode 100755
index 0000000..89aad77
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc1768_cproject.tmpl
@@ -0,0 +1,77 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1768&lt;/name&gt;&#13;
+&lt;family&gt;LPC17xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4088_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4088_cproject.tmpl
new file mode 100755
index 0000000..13c6366
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4088_cproject.tmpl
@@ -0,0 +1,72 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC177x_8x_407x_8x_512.cfx" property_3="NXP" property_4="LPC4088" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4088" flash_driver="LPC177x_8x_407x_8x_512.cfx" match_id="0x481D3F47" name="LPC4088" stub="crt_emu_cm3_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4088&lt;/name&gt;&#13;
+&lt;family&gt;LPC407x_8x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc64" location="0x10000000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph32" location="0x20000000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x200000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x20080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x20084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x20088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x2008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x20090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO" id="GPIO" location="0x20098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x2009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART0" id="UART0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM0" id="PWM0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM1" id="PWM1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="COMPARATOR" id="COMPARATOR" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOINT" id="GPIOINT" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAFRAM" id="CANAFRAM" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAF" id="CANAF" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CCAN" id="CCAN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN1" id="CAN1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN2" id="CAN2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x4008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART2" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART3" id="UART3" location="0x4009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART4" id="UART4" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S" id="I2S" location="0x400a8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP2" id="SSP2" location="0x400ac000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400b8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x400fc000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpc407x_8x_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4088_dm_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4088_dm_cproject.tmpl
new file mode 100755
index 0000000..13c6366
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4088_dm_cproject.tmpl
@@ -0,0 +1,72 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC177x_8x_407x_8x_512.cfx" property_3="NXP" property_4="LPC4088" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4088" flash_driver="LPC177x_8x_407x_8x_512.cfx" match_id="0x481D3F47" name="LPC4088" stub="crt_emu_cm3_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4088&lt;/name&gt;&#13;
+&lt;family&gt;LPC407x_8x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc64" location="0x10000000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph32" location="0x20000000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x200000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x20080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x20084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x20088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x2008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" id="CRC" location="0x20090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO" id="GPIO" location="0x20098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x2009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART0" id="UART0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM0" id="PWM0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM1" id="PWM1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="COMPARATOR" id="COMPARATOR" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOINT" id="GPIOINT" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAFRAM" id="CANAFRAM" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAF" id="CANAF" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CCAN" id="CCAN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN1" id="CAN1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN2" id="CAN2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x4008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART2" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART3" id="UART3" location="0x4009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" id="I2C2" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART4" id="UART4" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S" id="I2S" location="0x400a8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP2" id="SSP2" location="0x400ac000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400b8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x400fc000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpc407x_8x_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4330_m4_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4330_m4_cproject.tmpl
new file mode 100755
index 0000000..91de9a8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpc4330_m4_cproject.tmpl
@@ -0,0 +1,77 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC4330" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC4330" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC4330" package="LPC43_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC4330&lt;/name&gt;&#13;
+&lt;family&gt;LPC43xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC4x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC43_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpccappuccino_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpccappuccino_cproject.tmpl
new file mode 100755
index 0000000..1d18842
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/lpccappuccino_cproject.tmpl
@@ -0,0 +1,49 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U37/501" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC11U37/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U37/501" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC11U37/501&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/makefile.targets.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/makefile.targets.tmpl
new file mode 100755
index 0000000..d5455fb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/makefile.targets.tmpl
@@ -0,0 +1,13 @@
+# DO NOT REMOVE! Generated by the MCUXpresso exporter from an mBed project.
+
+mbedclean:
+	$(RM) $(OBJS)
+	$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(C_DEPS)$(CPP_DEPS)
+	$(RM) $(EXECUTABLES) {{name}}.* linker-script-*.ld
+	-@echo ' '
+
+{% for config, data in options.iteritems() %}
+linker-script-{{config}}.ld: ../{{ld_script}}
+	{{data.cpp_cmd}} {{data.ld.other}} $< -o $@
+{{name}}.elf: linker-script-{{config}}.ld
+{% endfor %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/mbedignore.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/mbedignore.tmpl
new file mode 100755
index 0000000..175b967
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/mbedignore.tmpl
@@ -0,0 +1,3 @@
+{%- for config in options.values() -%}
+{{config.name}}/*
+{% endfor -%}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/ublox_c027_cproject.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/ublox_c027_cproject.tmpl
new file mode 100755
index 0000000..89aad77
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/mcuxpresso/ublox_c027_cproject.tmpl
@@ -0,0 +1,77 @@
+{% extends "mcuxpresso/.cproject.tmpl" %}
+
+{% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1768&lt;/name&gt;&#13;
+&lt;family&gt;LPC17xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
+&lt;peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;{% endblock %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/__init__.py
new file mode 100755
index 0000000..b10fbcf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/__init__.py
@@ -0,0 +1,65 @@
+"""
+mbed SDK
+Copyright (c) 2014-2017 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import splitext, basename
+from tools.targets import TARGET_MAP
+from tools.export.exporters import Exporter
+from tools.export.makefile import GccArm
+
+class QtCreator(GccArm):
+    NAME = 'QtCreator'
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    def generate(self):
+        self.resources.win_to_unix()
+
+        defines         = [] # list of tuples ('D'/'U', [key, value]) (value is optional)
+        forced_includes = [] # list of strings
+        sources         = [] # list of strings
+        include_paths   = [] # list of strings
+
+        next_is_include = False
+        for f in self.flags['c_flags'] + self.flags['cxx_flags']:
+            f=f.strip()
+            if next_is_include:
+                forced_includes.append(f)
+                next_is_include = False
+                continue
+            if f.startswith('-D'):
+                defines.append(('D', f[2:].split('=', 1)))
+            elif f.startswith('-U'):
+                defines.append(('U', [f[2:]]))
+            elif f == "-include":
+                next_is_include = True
+
+        for r_type in ['headers', 'c_sources', 's_sources', 'cpp_sources']:
+            sources.extend(getattr(self.resources, r_type))
+
+        include_paths = self.resources.inc_dirs
+
+        ctx = {
+            'defines': defines,
+            'forced_includes': forced_includes,
+            'sources': sources,
+            'include_paths': self.resources.inc_dirs
+            }
+
+        for ext in ['creator', 'files', 'includes', 'config']:
+            self.gen_file('qtcreator/%s.tmpl' % ext, ctx, "%s.%s" % (self.project_name, ext))
+
+        # finally, generate the Makefile
+        super(QtCreator, self).generate()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/__init__.pyc
new file mode 100755
index 0000000..b9e5f27
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/config.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/config.tmpl
new file mode 100755
index 0000000..00b6cd6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/config.tmpl
@@ -0,0 +1,6 @@
+{%  for d in defines -%}
+{% if d[0] == 'D' %}#define {% else %}#undef{% endif %} {{ d[1]|join(' ')}}
+{%  endfor %}
+{%  for i in forced_includes -%}
+#include "{{i}}"
+{%  endfor %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/creator.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/creator.tmpl
new file mode 100755
index 0000000..e94cbbd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/creator.tmpl
@@ -0,0 +1 @@
+[General]
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/files.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/files.tmpl
new file mode 100755
index 0000000..1b034bb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/files.tmpl
@@ -0,0 +1,3 @@
+{% for s in sources -%}
+{{s}}
+{% endfor %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/includes.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/includes.tmpl
new file mode 100755
index 0000000..3b6b875
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/qtcreator/includes.tmpl
@@ -0,0 +1,3 @@
+{% for i in include_paths -%}
+{{i}}
+{% endfor %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/__init__.py
new file mode 100755
index 0000000..8319e58
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/__init__.py
@@ -0,0 +1,196 @@
+"""
+mbed SDK
+Copyright (c) 2014-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import split,splitext, basename
+
+from tools.export.exporters import Exporter, deprecated_exporter
+
+class Folder:
+    def __init__(self, name):
+        self.name = name
+        self.children = []
+
+    def contains(self, folderName):
+        for child in self.children:
+            if child.name == folderName:
+                return True
+        return False
+
+    def __str__(self):
+        retval = self.name + " "
+        if len(self.children) > 0:
+            retval += "[ "
+            for child in self.children:
+                retval += child.__str__()
+            retval += " ]"
+
+        return retval
+
+    def findChild(self, folderName):
+        for child in self.children:
+            if child.name == folderName:
+                return child
+        return None
+
+    def addChild(self, folderName):
+        if folderName == '':
+            return None
+
+        if not self.contains(folderName):
+            self.children.append(Folder(folderName))
+
+        return self.findChild(folderName)
+
+@deprecated_exporter
+class SimplicityV3(Exporter):
+    NAME = 'SimplicityV3'
+    TOOLCHAIN = 'GCC_ARM'
+
+    TARGETS = [
+        'EFM32GG_STK3700',
+        'EFM32ZG_STK3200',
+        'EFM32LG_STK3600',
+        'EFM32WG_STK3800',
+        'EFM32HG_STK3400',
+        'EFM32PG_STK3401'
+    ]
+
+    PARTS = {
+        'EFM32GG_STK3700': 'com.silabs.mcu.si32.efm32.efm32gg.efm32gg990f1024',
+        'EFM32ZG_STK3200': 'com.silabs.mcu.si32.efm32.efm32zg.efm32zg222f32',
+        'EFM32LG_STK3600': 'com.silabs.mcu.si32.efm32.efm32lg.efm32lg990f256',
+        'EFM32WG_STK3800': 'com.silabs.mcu.si32.efm32.efm32wg.efm32wg990f256',
+        'EFM32HG_STK3400': 'com.silabs.mcu.si32.efm32.efm32hg.efm32hg322f64',
+        'EFM32PG_STK3401': 'com.silabs.mcu.si32.efm32.efm32pg1b.efm32pg1b200f256gm48'
+    }
+
+    KITS = {
+        'EFM32GG_STK3700': 'com.silabs.kit.si32.efm32.efm32gg.stk3700',
+        'EFM32ZG_STK3200': 'com.silabs.kit.si32.efm32.efm32zg.stk3200',
+        'EFM32LG_STK3600': 'com.silabs.kit.si32.efm32.efm32lg.stk3600',
+        'EFM32WG_STK3800': 'com.silabs.kit.si32.efm32.efm32wg.stk3800',
+        'EFM32HG_STK3400': 'com.silabs.kit.si32.efm32.efm32hg.slstk3400a',
+		'EFM32PG_STK3401': 'com.silabs.kit.si32.efm32.efm32pg.slstk3401a'
+    }
+
+    FILE_TYPES = {
+        'c_sources':'1',
+        'cpp_sources':'1',
+        's_sources':'1'
+    }
+
+    EXCLUDED_LIBS = [
+        'm',
+        'c',
+        'gcc',
+        'nosys',
+        'supc++',
+        'stdc++'
+    ]
+
+    DOT_IN_RELATIVE_PATH = False
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    orderedPaths = Folder("Root")
+
+    def check_and_add_path(self, path):
+        levels = path.split('/')
+        base = self.orderedPaths
+        for level in levels:
+            if base.contains(level):
+                base = base.findChild(level)
+            else:
+                base.addChild(level)
+                base = base.findChild(level)
+
+
+    def generate(self):
+        # "make" wants Unix paths
+        self.resources.win_to_unix()
+
+        main_files = []
+
+        EXCLUDED_LIBS = [
+            'm',
+            'c',
+            'gcc',
+            'nosys',
+            'supc++',
+            'stdc++'
+        ]
+
+        for r_type in ['s_sources', 'c_sources', 'cpp_sources']:
+            r = getattr(self.resources, r_type)
+            if r:
+                for source in r:
+                    self.check_and_add_path(split(source)[0])
+
+                    if not ('/' in source):
+                        main_files.append(source)
+
+        libraries = []
+        for lib in self.resources.libraries:
+            l, _ = splitext(basename(lib))
+            if l[3:] not in EXCLUDED_LIBS:
+                libraries.append(l[3:])
+
+        defines = []
+        for define in self.toolchain.get_symbols():
+            if '=' in define:
+                keyval = define.split('=')
+                defines.append( (keyval[0], keyval[1]) )
+            else:
+                defines.append( (define, '') )
+
+        self.check_and_add_path(split(self.resources.linker_script)[0])
+
+        ctx = {
+            'name': self.project_name,
+            'main_files': main_files,
+            'recursiveFolders': self.orderedPaths,
+            'object_files': self.resources.objects,
+            'include_paths': self.resources.inc_dirs,
+            'library_paths': self.resources.lib_dirs,
+            'linker_script': self.resources.linker_script,
+            'libraries': libraries,
+            'defines': defines,
+            'part': self.PARTS[self.target],
+            'kit': self.KITS[self.target],
+            'loopcount': 0
+        }
+        ctx.update(self.flags)
+
+        ## Strip main folder from include paths because ssproj is not capable of handling it
+        if '.' in ctx['include_paths']:
+            ctx['include_paths'].remove('.')
+            ctx['include_root'] = True
+
+        '''
+        Suppress print statements
+        print('\n')
+        print(self.target)
+        print('\n')
+        print(ctx)
+        print('\n')
+        print(self.orderedPaths)
+        for path in self.orderedPaths.children:
+            print(path.name + "\n")
+            for bpath in path.children:
+                print("\t" + bpath.name + "\n")
+        '''
+
+        self.gen_file('simplicity/slsproj.tmpl', ctx, '%s.slsproj' % self.project_name)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/__init__.pyc
new file mode 100755
index 0000000..c99024c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/slsproj.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/slsproj.tmpl
new file mode 100755
index 0000000..2a319c2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/simplicity/slsproj.tmpl
@@ -0,0 +1,149 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project xmlns:model="http://www.silabs.com/sls/IDE.ecore" name="{{ name }}" kitCompatibility="{{ kit }}"
+																		  partCompatibility="{{ part }}"
+																		  toolchainCompatibility="com.silabs.ide.si32.gcc:4.8.3.20131129"
+																		  sdkCompatibility="com.silabs.sdk.si32.efm32"
+																		  propertyScope="project"
+																		  contentRoot=".">
+{# Hierarchically include all folders into the project #}
+  {%- for child in recursiveFolders.children recursive %}
+  <folder name="{{ child.name }}" uri="{{ child.name }}" includeAllFiles="true" includeAllFolders="true">
+    {%- if child.children -%}
+    {{ loop(child.children) }}
+    {%- endif %}
+  </folder>
+  {%- endfor %}
+
+{# Include all source files not belonging to a subfolder separately #}
+  {%- for file in main_files -%}
+  <file name = "{{ file }}" uri = "file:./{{ file }}" partCompatibility = ""/>
+  {%- endfor %}
+  {%- if include_root %}
+  <file name = "mbed_config.h" uri = "file:./mbed_config.h" partCompatibility = ""/>
+  {%- endif %}
+
+  <sourceFolder></sourceFolder>
+  <model:property key="cppProjectCommon.languageId" value="org.eclipse.cdt.core.g++"/>
+  <model:property key="projectCommon.buildArtifactType" value="EXE"/>
+  <configuration name="com.silabs.ide.si32.gcc.debug#com.silabs.ide.si32.gcc:4.8.3.20131129" label="GNU ARM v4.8.3 - Debug" stockConfigCompatibility="com.silabs.ide.toolchain.core.debug">
+    <model:description></model:description>
+{# Add all include paths to the managed build compiler, paths relative to project #}
+    {%- if include_root %}
+    <includePath languageCompatibility="c cpp" uri="."/>
+    {%- endif %}
+    {%- for path in include_paths %}
+    <includePath languageCompatibility="c cpp" uri="studio:/project/{{ path }}/"/>
+    {%- endfor %}
+{# Add all mbed-defined #Defines for the preprocessor #}
+    {%- for define, value in defines %}
+    <macroDefinition languageCompatibility="c cpp" name="{{ define }}" value="{{ value }}"/>
+    {%- endfor %}
+{# Include all standard libraries that mbed requires #}
+    <macroDefinition languageCompatibility="c cpp" name="DEBUG" value="1"/>
+    <libraryFile languageCompatibility="c" name="stdc++"/>
+    <libraryFile languageCompatibility="c" name="supc++"/>
+    <libraryFile languageCompatibility="c" name="m"/>
+    <libraryFile languageCompatibility="c" name="nosys"/>
+    <libraryFile languageCompatibility="c" name="c"/>
+    <libraryFile languageCompatibility="c" name="gcc"/>
+{# Include exported libraries #}
+    {%- for library in libraries %}
+    <libraryFile languageCompatibility="c cpp" name="{{ library }}"/>
+    {%- endfor %}
+{# Add library search paths #}
+    {%- for path in library_paths %}
+    <libraryPath languageCompatibility="c cpp" uri="studio:/project/{{ path }}/"/>
+    {%- endfor %}
+{# Add in separate object files if needed #}
+    {%- if object_files %}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base" optionId="gnu.cpp.link.option.userobjs" value="
+    {%- for file in object_files -%}
+    ${workspace_loc:/${ProjName}/{{ file }}}{% if not loop.last %} {% endif %}
+    {%- endfor -%}"/>
+    {%- endif %}
+{# Manually override linker ordering #}
+    {%- if libraries %}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.category.ordering.selection" value="
+    {%- if object_files -%}
+    {%- for file in object_files -%}
+    ${workspace_loc:/${ProjName}/{{ file }}};
+    {%- endfor -%}
+    {%- endif -%}
+    {%- for library in libraries -%}
+    ${-l{{ library }}}{% if not loop.last %};{% endif %}
+    {%- endfor -%}"/>
+    {%- endif %}
+{# Define mbed-specific linker file #}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.exe" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.usescript" value="true"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.exe" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.script" value="${workspace_loc:/${ProjName}/{{ linker_script }}}"/>
+{# Make sure to wrap main in order to get clock initialization done right #}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base" optionId="gnu.c.link.option.ldflags" value="{{ld_flags|join(" ")}}"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base" optionId="gnu.cpp.link.option.flags" value="{{ld_flags|join(" ")}}"/>
+{# For debug build, don't apply optimizations #}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.compiler.base" optionId="gnu.c.compiler.option.optimization.level" value="gnu.c.optimization.level.none"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.compiler.base" optionId="gnu.c.compiler.option.misc.other" value="-c {{common_flags|join(" ")}} {{c_flags|join(" ")}}"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base" optionId="gnu.cpp.compiler.option.optimization.level" value="gnu.cpp.compiler.optimization.level.none"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base" optionId="gnu.cpp.compiler.option.other.other" value="-c {{common_flags|join(" ")}} {{cxx_flags|join(" ")}}"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.misc.dialect" value="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.misc.dialect.default"/>
+  </configuration>
+  <configuration name="com.silabs.ide.si32.gcc.release#com.silabs.ide.si32.gcc:4.8.3.20131129" label="GNU ARM v4.8.3 - Release" stockConfigCompatibility="com.silabs.ide.toolchain.core.release">
+    <model:description></model:description>
+{# Add all include paths to the managed build compiler, paths relative to project #}
+    {%- if include_root %}
+    <includePath languageCompatibility="c cpp" uri="."/>
+    {%- endif %}
+    {%- for path in include_paths %}
+    <includePath languageCompatibility="c cpp" uri="studio:/project/{{ path }}/"/>
+    {%- endfor %}
+{# Add all mbed-defined #Defines for the preprocessor #}
+    {%- for define, value in defines %}
+    <macroDefinition languageCompatibility="c cpp" name="{{ define }}" value="{{ value }}"/>
+    {%- endfor %}
+{# Include all standard libraries that mbed requires #}
+    <libraryFile languageCompatibility="c" name="stdc++"/>
+    <libraryFile languageCompatibility="c" name="supc++"/>
+    <libraryFile languageCompatibility="c" name="m"/>
+    <libraryFile languageCompatibility="c" name="nosys"/>
+    <libraryFile languageCompatibility="c" name="c"/>
+    <libraryFile languageCompatibility="c" name="gcc"/>
+{# Include exported libraries #}
+    {%- for library in libraries %}
+    <libraryFile languageCompatibility="c cpp" name="{{ library }}"/>
+    {%- endfor %}
+{# Add library search paths #}
+    {%- for path in library_paths %}
+    <libraryPath languageCompatibility="c cpp" uri="studio:/project/{{ path }}/"/>
+    {%- endfor %}
+{# Add in separate object files if needed #}
+    {%- if object_files %}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base" optionId="gnu.cpp.link.option.userobjs" value="
+    {%- for file in object_files -%}
+    ${workspace_loc:/${ProjName}/{{ file }}}{% if not loop.last %} {% endif %}
+    {%- endfor -%}"/>
+    {%- endif %}
+{# Manually override linker ordering #}
+    {%- if libraries %}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.category.ordering.selection" value="
+    {%- if object_files -%}
+    {%- for file in object_files -%}
+    ${workspace_loc:/${ProjName}/{{ file }}};
+    {%- endfor -%}
+    {%- endif -%}
+    {%- for library in libraries -%}{% if not loop.last %};{% endif %}
+    ${-l{{ library }}}
+    {%- endfor -%}"/>
+    {%- endif %}
+{# Define mbed-specific linker file #}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.exe" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.usescript" value="true"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.exe" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.script" value="${workspace_loc:/${ProjName}/{{ linker_script }}}"/>
+{# Make sure to wrap main in order to get clock initialization done right #}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base" optionId="gnu.c.link.option.ldflags" value="{{ld_flags|join(" ")}}"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base" optionId="gnu.cpp.link.option.flags" value="{{ld_flags|join(" ")}}"/>
+{# Use optimize for size on release build #}
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.compiler.base" optionId="gnu.c.compiler.option.optimization.level" value="gnu.c.optimization.level.size"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.compiler.base" optionId="gnu.c.compiler.option.misc.other" value="-c {{common_flags|join(" ")}} {{c_flags|join(" ")}}"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base" optionId="gnu.cpp.compiler.option.optimization.level" value="gnu.cpp.compiler.optimization.level.size"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base" optionId="gnu.cpp.compiler.option.other.other" value="-c {{common_flags|join(" ")}} {{cxx_flags|join(" ")}}"/>
+    <toolOption toolId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base" optionId="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.misc.dialect" value="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.misc.dialect.default"/>
+  </configuration>
+</project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/__init__.py
new file mode 100755
index 0000000..d9fd0cf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/__init__.py
@@ -0,0 +1,526 @@
+"""
+mbed SDK
+Copyright (c) 2011-2017 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from os.path import splitext, basename, join
+from tools.utils import mkdir
+from tools.export.gnuarmeclipse import GNUARMEclipse
+from tools.export.gnuarmeclipse import UID
+from tools.build_api import prepare_toolchain
+from sys import flags, platform
+
+# Global random number generator instance.
+u = UID()
+
+
+class Sw4STM32(GNUARMEclipse):
+    """
+    Sw4STM32 class
+    """
+    NAME = 'Sw4STM32'
+    TOOLCHAIN = 'GCC_ARM'
+
+    BOARDS = {
+        'B96B_F446VE':
+        {
+            'name': 'B96B-F446VE',
+            'mcuId': 'STM32F446VETx'
+        },
+        'DISCO_F051R8':
+        {
+            'name': 'STM32F0DISCOVERY',
+            'mcuId': 'STM32F051R8Tx'
+        },
+        'DISCO_F303VC':
+        {
+            'name': 'STM32F3DISCOVERY',
+            'mcuId': 'STM32F303VCTx'
+        },
+        'DISCO_F334C8':
+        {
+            'name': 'STM32F3348DISCOVERY',
+            'mcuId': 'STM32F334C8Tx'
+        },
+        'DISCO_F401VC':
+        {
+            'name': 'STM32F401C-DISCO',
+            'mcuId': 'STM32F401VCTx'
+        },
+        'DISCO_F407VG':
+        {
+            'name': 'STM32F4DISCOVERY',
+            'mcuId': 'STM32F407VGTx'
+        },
+        'DISCO_F413ZH':
+        {
+            'name': 'DISCO_F413',
+            'mcuId': 'STM32F413ZHTx'
+        },
+        'DISCO_F429ZI':
+        {
+            'name': 'STM32F429I-DISCO',
+            'mcuId': 'STM32F429ZITx'
+        },
+        'DISCO_F469NI':
+        {
+            'name': 'DISCO-F469NI',
+            'mcuId': 'STM32F469NIHx'
+        },
+        'DISCO_F746NG':
+        {
+            'name': 'STM32F746G-DISCO',
+            'mcuId': 'STM32F746NGHx'
+        },
+        'DISCO_F769NI':
+        {
+            'name': 'DISCO-F769NI',
+            'mcuId': 'STM32F769NIHx'
+        },
+        'DISCO_L053C8':
+        {
+            'name': 'STM32L0538DISCOVERY',
+            'mcuId': 'STM32L053C8Tx'
+        },
+        'DISCO_L072CZ_LRWAN1':
+        {
+            'name': 'DISCO-L072CZ-LRWAN1',
+            'mcuId': 'STM32L072CZTx'
+        },
+        'DISCO_L475VG_IOT01A':
+        {
+            'name': 'STM32L475G-DISCO',
+            'mcuId': 'STM32L475VGTx'
+        },
+        'DISCO_L476VG':
+        {
+            'name': 'STM32L476G-DISCO',
+            'mcuId': 'STM32L476VGTx'
+        },
+        'NUCLEO_F030R8':
+        {
+            'name': 'NUCLEO-F030R8',
+            'mcuId': 'STM32F030R8Tx'
+        },
+        'NUCLEO_F031K6':
+        {
+            'name': 'NUCLEO-F031K6',
+            'mcuId': 'STM32F031K6Tx'
+        },
+        'NUCLEO_F042K6':
+        {
+            'name': 'NUCLEO-F042K6',
+            'mcuId': 'STM32F042K6Tx'
+        },
+        'NUCLEO_F070RB':
+        {
+            'name': 'NUCLEO-F070RB',
+            'mcuId': 'STM32F070RBTx'
+        },
+        'NUCLEO_F072RB':
+        {
+            'name': 'NUCLEO-F072RB',
+            'mcuId': 'STM32F072RBTx'
+        },
+        'NUCLEO_F091RC':
+        {
+            'name': 'NUCLEO-F091RC',
+            'mcuId': 'STM32F091RCTx'
+        },
+        'NUCLEO_F103RB':
+        {
+            'name': 'NUCLEO-F103RB',
+            'mcuId': 'STM32F103RBTx'
+        },
+        'NUCLEO_F207ZG':
+        {
+            'name': 'NUCLEO-F207ZG',
+            'mcuId': 'STM32F207ZGTx'
+        },
+        'NUCLEO_F302R8':
+        {
+            'name': 'NUCLEO-F302R8',
+            'mcuId': 'STM32F302R8Tx'
+        },
+        'NUCLEO_F303K8':
+        {
+            'name': 'NUCLEO-F303K8',
+            'mcuId': 'STM32F303K8Tx'
+        },
+        'NUCLEO_F303RE':
+        {
+            'name': 'NUCLEO-F303RE',
+            'mcuId': 'STM32F303RETx'
+        },
+        'NUCLEO_F303ZE':
+        {
+            'name': 'NUCLEO-F303ZE',
+            'mcuId': 'STM32F303ZETx'
+        },
+        'NUCLEO_F334R8':
+        {
+            'name': 'NUCLEO-F334R8',
+            'mcuId': 'STM32F334R8Tx'
+        },
+        'NUCLEO_F401RE':
+        {
+            'name': 'NUCLEO-F401RE',
+            'mcuId': 'STM32F401RETx'
+        },
+        'NUCLEO_F410RB':
+        {
+            'name': 'NUCLEO-F410RB',
+            'mcuId': 'STM32F410RBTx'
+        },
+        'NUCLEO_F411RE':
+        {
+            'name': 'NUCLEO-F411RE',
+            'mcuId': 'STM32F411RETx'
+        },
+        'NUCLEO_F429ZI':
+        {
+            'name': 'NUCLEO-F429ZI',
+            'mcuId': 'STM32F429ZITx'
+        },
+        'NUCLEO_F446RE':
+        {
+            'name': 'NUCLEO-F446RE',
+            'mcuId': 'STM32F446RETx'
+        },
+        'NUCLEO_F446ZE':
+        {
+            'name': 'NUCLEO-F446ZE',
+            'mcuId': 'STM32F446ZETx'
+        },
+        'NUCLEO_F746ZG':
+        {
+            'name': 'NUCLEO-F746ZG',
+            'mcuId': 'STM32F746ZGTx'
+        },
+        'NUCLEO_F767ZI':
+        {
+            'name': 'NUCLEO-F767ZI',
+            'mcuId': 'STM32F767ZITx'
+        },
+        'NUCLEO_L011K4':
+        {
+            'name': 'NUCLEO-L011K4',
+            'mcuId': 'STM32L011K4Tx'
+        },
+        'NUCLEO_L031K6':
+        {
+            'name': 'NUCLEO-L031K6',
+            'mcuId': 'STM32L031K6Tx'
+        },
+        'NUCLEO_L053R8':
+        {
+            'name': 'NUCLEO-L053R8',
+            'mcuId': 'STM32L053R8Tx'
+        },
+        'NUCLEO_L073RZ':
+        {
+            'name': 'NUCLEO-L073RZ',
+            'mcuId': 'STM32L073RZTx'
+        },
+        'NUCLEO_L152RE':
+        {
+            'name': 'NUCLEO-L152RE',
+            'mcuId': 'STM32L152RETx'
+        },
+        'NUCLEO_L432KC':
+        {
+            'name': 'NUCLEO-L432KC',
+            'mcuId': 'STM32L432KCUx'
+        },
+        'NUCLEO_L476RG':
+        {
+            'name': 'NUCLEO-L476RG',
+            'mcuId': 'STM32L476RGTx'
+        },
+        'NUCLEO_L486RG':
+        {
+            'name': 'NUCLEO-L486RG',
+            'mcuId': 'STM32L486RGTx'
+        },
+    }
+
+    TARGETS = BOARDS.keys()
+
+    def __gen_dir(self, dir_name):
+        """
+        Method that creates directory
+        """
+        settings = join(self.export_dir, dir_name)
+        mkdir(settings)
+
+    def get_fpu_hardware(self, fpu_unit):
+        """
+        Convert fpu unit name into hardware name.
+        """
+        hw = ''
+        fpus = {
+            'fpv4spd16': 'fpv4-sp-d16',
+            'fpv5d16': 'fpv5-d16',
+            'fpv5spd16': 'fpv5-sp-d16'
+        }
+        if fpu_unit in fpus:
+            hw = fpus[fpu_unit]
+        return hw
+
+    def process_sw_options(self, opts, flags_in):
+        """
+        Process System Workbench specific options.
+
+        System Workbench for STM32 has some compile options, which are not recognized by the GNUARMEclipse exporter.
+        Those are handled in this method.
+        """
+        opts['c']['preprocess'] = False
+        if '-E' in flags_in['c_flags']:
+            opts['c']['preprocess'] = True
+        opts['cpp']['preprocess'] = False
+        if '-E' in flags_in['cxx_flags']:
+            opts['cpp']['preprocess'] = True
+        opts['c']['slowflashdata'] = False
+        if '-mslow-flash-data' in flags_in['c_flags']:
+            opts['c']['slowflashdata'] = True
+        opts['cpp']['slowflashdata'] = False
+        if '-mslow-flash-data' in flags_in['cxx_flags']:
+            opts['cpp']['slowflashdata'] = True
+        if opts['common']['optimization.messagelength']:
+            opts['common']['optimization.other'] += ' -fmessage-length=0'
+        if opts['common']['optimization.signedchar']:
+            opts['common']['optimization.other'] += ' -fsigned-char'
+        if opts['common']['optimization.nocommon']:
+            opts['common']['optimization.other'] += ' -fno-common'
+        if opts['common']['optimization.noinlinefunctions']:
+            opts['common']['optimization.other'] += ' -fno-inline-functions'
+        if opts['common']['optimization.freestanding']:
+            opts['common']['optimization.other'] += ' -ffreestanding'
+        if opts['common']['optimization.nobuiltin']:
+            opts['common']['optimization.other'] += ' -fno-builtin'
+        if opts['common']['optimization.spconstant']:
+            opts['common']['optimization.other'] += ' -fsingle-precision-constant'
+        if opts['common']['optimization.nomoveloopinvariants']:
+            opts['common']['optimization.other'] += ' -fno-move-loop-invariants'
+        if opts['common']['warnings.unused']:
+            opts['common']['warnings.other'] += ' -Wunused'
+        if opts['common']['warnings.uninitialized']:
+            opts['common']['warnings.other'] += ' -Wuninitialized'
+        if opts['common']['warnings.missingdeclaration']:
+            opts['common']['warnings.other'] += ' -Wmissing-declarations'
+        if opts['common']['warnings.pointerarith']:
+            opts['common']['warnings.other'] += ' -Wpointer-arith'
+        if opts['common']['warnings.padded']:
+            opts['common']['warnings.other'] += ' -Wpadded'
+        if opts['common']['warnings.shadow']:
+            opts['common']['warnings.other'] += ' -Wshadow'
+        if opts['common']['warnings.logicalop']:
+            opts['common']['warnings.other'] += ' -Wlogical-op'
+        if opts['common']['warnings.agreggatereturn']:
+            opts['common']['warnings.other'] += ' -Waggregate-return'
+        if opts['common']['warnings.floatequal']:
+            opts['common']['warnings.other'] += ' -Wfloat-equal'
+        opts['ld']['strip'] = False
+        if '-s' in flags_in['ld_flags']:
+            opts['ld']['strip'] = True
+        opts['ld']['shared'] = False
+        if '-shared' in flags_in['ld_flags']:
+            opts['ld']['shared'] = True
+        opts['ld']['soname'] = ''
+        opts['ld']['implname'] = ''
+        opts['ld']['defname'] = ''
+        for item in flags_in['ld_flags']:
+            if item.startswith('-Wl,-soname='):
+                opts['ld']['soname'] = item[len('-Wl,-soname='):]
+            if item.startswith('-Wl,--out-implib='):
+                opts['ld']['implname'] = item[len('-Wl,--out-implib='):]
+            if item.startswith('-Wl,--output-def='):
+                opts['ld']['defname'] = item[len('-Wl,--output-def='):]
+        opts['common']['arm.target.fpu.hardware'] = self.get_fpu_hardware(
+            opts['common']['arm.target.fpu.unit'])
+        opts['common']['debugging.codecov'] = False
+        if '-fprofile-arcs' in flags_in['common_flags'] and '-ftest-coverage' in flags_in['common_flags']:
+            opts['common']['debugging.codecov'] = True
+        # Passing linker options to linker with '-Wl,'-prefix.
+        for index in range(len(opts['ld']['flags'])):
+            item = opts['ld']['flags'][index]
+            if not item.startswith('-Wl,'):
+                opts['ld']['flags'][index] = '-Wl,' + item
+        # Strange System Workbench feature: If first parameter in Other flags is a
+        # define (-D...), Other flags will be replaced by defines and other flags
+        # are completely ignored. Moving -D parameters to defines.
+        for compiler in ['c', 'cpp', 'as']:
+            tmpList = opts[compiler]['other'].split(' ')
+            otherList = []
+            for item in tmpList:
+                if item.startswith('-D'):
+                    opts[compiler]['defines'].append(str(item[2:]))
+                else:
+                    otherList.append(item)
+            opts[compiler]['other'] = ' '.join(otherList)
+        # Assembler options
+        for as_def in opts['as']['defines']:
+            if '=' in as_def:
+                opts['as']['other'] += ' --defsym ' + as_def
+            else:
+                opts['as']['other'] += ' --defsym ' + as_def + '=1'
+
+    def generate(self):
+        """
+        Generate the .project and .cproject files.
+        """
+        options = {}
+
+        if not self.resources.linker_script:
+            raise NotSupportedException("No linker script found.")
+
+        print ('\nCreate a System Workbench for STM32 managed project')
+        print ('Project name: {0}'.format(self.project_name))
+        print ('Target:       {0}'.format(self.toolchain.target.name))
+        print ('Toolchain:    {0}'.format(self.TOOLCHAIN) + '\n')
+
+        self.resources.win_to_unix()
+
+        config_header = self.filter_dot(self.toolchain.get_config_header())
+
+        libraries = []
+        for lib in self.resources.libraries:
+            library, _ = splitext(basename(lib))
+            libraries.append(library[3:])
+
+        self.system_libraries = [
+            'stdc++', 'supc++', 'm', 'c', 'gcc', 'nosys'
+        ]
+
+        profiles = self.get_all_profiles()
+        self.as_defines = [s.replace('"', '&quot;')
+                           for s in self.toolchain.get_symbols(True)]
+        self.c_defines = [s.replace('"', '&quot;')
+                          for s in self.toolchain.get_symbols()]
+        self.cpp_defines = self.c_defines
+        print 'Symbols: {0}'.format(len(self.c_defines))
+
+        self.include_path = []
+        for s in self.resources.inc_dirs:
+            self.include_path.append("../" + self.filter_dot(s))
+        print ('Include folders: {0}'.format(len(self.include_path)))
+
+        self.compute_exclusions()
+
+        print ('Exclude folders: {0}'.format(len(self.excluded_folders)))
+
+        ld_script = self.filter_dot(self.resources.linker_script)
+        print ('Linker script:   {0}'.format(ld_script))
+
+        lib_dirs = [self.filter_dot(s) for s in self.resources.lib_dirs]
+
+        preproc_cmd = basename(self.toolchain.preproc[0]) + " " + " ".join(self.toolchain.preproc[1:])
+
+        for id in ['debug', 'release']:
+            opts = {}
+            opts['common'] = {}
+            opts['as'] = {}
+            opts['c'] = {}
+            opts['cpp'] = {}
+            opts['ld'] = {}
+
+            opts['id'] = id
+            opts['name'] = opts['id'].capitalize()
+
+            # TODO: Add prints to log or console in verbose mode.
+            #print ('\nBuild configuration: {0}'.format(opts['name']))
+
+            profile = profiles[id]
+
+            # A small hack, do not bother with src_path again,
+            # pass an empty string to avoid crashing.
+            src_paths = ['']
+            toolchain = prepare_toolchain(
+                src_paths, "", self.toolchain.target.name, self.TOOLCHAIN, build_profile=[profile])
+
+            # Hack to fill in build_dir
+            toolchain.build_dir = self.toolchain.build_dir
+
+            flags = self.toolchain_flags(toolchain)
+
+            # TODO: Add prints to log or console in verbose mode.
+            # print 'Common flags:', ' '.join(flags['common_flags'])
+            # print 'C++ flags:', ' '.join(flags['cxx_flags'])
+            # print 'C flags:', ' '.join(flags['c_flags'])
+            # print 'ASM flags:', ' '.join(flags['asm_flags'])
+            # print 'Linker flags:', ' '.join(flags['ld_flags'])
+
+            # Most GNU ARM Eclipse options have a parent,
+            # either debug or release.
+            if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']:
+                opts['parent_id'] = 'debug'
+            else:
+                opts['parent_id'] = 'release'
+
+            self.process_options(opts, flags)
+
+            opts['c']['defines'] = self.c_defines
+            opts['cpp']['defines'] = self.cpp_defines
+            opts['as']['defines'] = self.as_defines
+
+            self.process_sw_options(opts, flags)
+
+            opts['ld']['library_paths'] = [
+                self.filter_dot(s) for s in self.resources.lib_dirs]
+
+            opts['ld']['user_libraries'] = libraries
+            opts['ld']['system_libraries'] = self.system_libraries
+            opts['ld']['script'] = "linker-script-" + id + ".ld"
+
+            # Unique IDs used in multiple places.
+            uid = {}
+            uid['config'] = u.id
+            uid['tool_c_compiler'] = u.id
+            uid['tool_c_compiler_input'] = u.id
+            uid['tool_cpp_compiler'] = u.id
+            uid['tool_cpp_compiler_input'] = u.id
+
+            opts['uid'] = uid
+
+            options[id] = opts
+
+        ctx = {
+            'name': self.project_name,
+            'platform': platform,
+            'include_paths': self.include_path,
+            'config_header': config_header,
+            'exclude_paths': '|'.join(self.excluded_folders),
+            'ld_script': ld_script,
+            'library_paths': lib_dirs,
+            'object_files': self.resources.objects,
+            'libraries': libraries,
+            'board_name': self.BOARDS[self.target.upper()]['name'],
+            'mcu_name': self.BOARDS[self.target.upper()]['mcuId'],
+            'cpp_cmd': preproc_cmd,
+            'options': options,
+            # id property of 'u' will generate new random identifier every time
+            # when called.
+            'u': u
+        }
+
+        self.__gen_dir('.settings')
+        self.gen_file('sw4stm32/language_settings_commom.tmpl',
+                      ctx, '.settings/language.settings.xml')
+        self.gen_file('sw4stm32/project_common.tmpl', ctx, '.project')
+        self.gen_file('sw4stm32/cproject_common.tmpl', ctx, '.cproject')
+        self.gen_file('sw4stm32/makefile.targets.tmpl', ctx,
+                      'makefile.targets', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('sw4stm32/launch.tmpl', ctx, self.project_name +
+                      ' ' + options['debug']['name'] + '.launch')
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/__init__.pyc
new file mode 100755
index 0000000..b9f8326
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/cproject_common.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/cproject_common.tmpl
new file mode 100755
index 0000000..8453f73
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/cproject_common.tmpl
@@ -0,0 +1,315 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		{% for cfg_id in options %}
+		{% set opts = options[cfg_id] %}
+		<cconfiguration id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}" moduleId="org.eclipse.cdt.core.settings" name="{{opts['name']}}">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}-{{cfg_id}}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.{{cfg_id}}" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}" name="{{opts['name']}}" parent="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}" postannouncebuildStep="Generating binary and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${ProjName}.bin&quot; &amp;&amp; arm-none-eabi-size -B &quot;${BuildArtifactFileName}&quot; &amp;&amp; make ldclean" preannouncebuildStep="Creating makefile.defs:" prebuildStep="echo &quot;export PREPROC_CMD = ${openstm32_compiler_path}/${compiler_prefix}cpp -E -P&quot; &gt; ${ProjDirPath}/makefile.defs">
+					<folderInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}." name="/" resourcePath="">
+						<toolChain id="fr.ac6.managedbuild.toolchain.gnu.cross.exe.{{cfg_id}}.{{u.id}}" name="Ac6 STM32 MCU GCC" superClass="fr.ac6.managedbuild.toolchain.gnu.cross.exe.{{cfg_id}}">
+							<option id="fr.ac6.managedbuild.option.gnu.cross.mcu.{{u.id}}" name="Mcu" superClass="fr.ac6.managedbuild.option.gnu.cross.mcu" value="{{mcu_name}}" valueType="string"/>
+							<option id="fr.ac6.managedbuild.option.gnu.cross.board.{{u.id}}" name="Board" superClass="fr.ac6.managedbuild.option.gnu.cross.board" value="{{board_name}}" valueType="string"/>
+							{% if opts['common']['arm.target.fpu.hardware'] %}
+							<option id="fr.ac6.managedbuild.option.gnu.cross.fpu.{{u.id}}" name="Floating point hardware" superClass="fr.ac6.managedbuild.option.gnu.cross.fpu" value="fr.ac6.managedbuild.option.gnu.cross.fpu.{{opts['common']['arm.target.fpu.hardware']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.abi'] %}
+							<option id="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{u.id}}" name="Floating-point ABI" superClass="fr.ac6.managedbuild.option.gnu.cross.floatabi" value="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{opts['common']['arm.target.fpu.abi']}}" valueType="enumerated"/>
+							{% endif %}
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="fr.ac6.managedbuild.targetPlatform.gnu.cross.{{u.id}}" isAbstract="false" osList="all" superClass="fr.ac6.managedbuild.targetPlatform.gnu.cross"/>
+							<builder buildPath="${workspace_loc:/{{name}}}/{{opts['name']}}" id="fr.ac6.managedbuild.builder.gnu.cross.{{u.id}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="fr.ac6.managedbuild.builder.gnu.cross"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{opts['uid']['tool_c_compiler']}}" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler">
+								{% if cfg_id == 'debug' %}
+								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.c.optimization.level.more" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+								{% else %}
+								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.c.optimization.level.most" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+								{% endif %}
+								<option id="gnu.c.compiler.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									{% for path in include_paths %}
+									<listOptionValue builtIn="false" value="&quot;{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.c.compiler.option.preprocessor.def.symbols.{{u.id}}" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									{% for s in opts['c']['defines'] %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+									{% endfor %}
+								</option>
+								{% if config_header %}
+								<option id="gnu.c.compiler.option.include.files.{{u.id}}" name="Include files (-include)" superClass="gnu.c.compiler.option.include.files" useByScannerDiscovery="false" valueType="includeFiles">
+									<listOptionValue builtIn="false" value="${ProjDirPath}/{{config_header}}"/>
+								</option>
+								{% endif %}
+								{% if 'compiler.std' in opts['c'] %}
+								{% if opts['c']['compiler.std'] == '-ansi' %}
+								<option id="gnu.c.compiler.option.misc.ansi.{{u.id}}" name="Support ANSI programs (-ansi)" superClass="gnu.c.compiler.option.misc.ansi" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% elif opts['c']['compiler.std'] %}
+								<option id="gnu.c.compiler.option.dialect.std.{{u.id}}" superClass="gnu.c.compiler.option.dialect.std" value="gnu.c.compiler.dialect.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.dialect.std.{{u.id}}" name="Language standard" superClass="gnu.c.compiler.option.dialect.std" useByScannerDiscovery="true" value="gnu.c.compiler.dialect.c99" valueType="enumerated"/>
+								{% endif %}
+								{% endif %}
+								{% if opts['common']['warnings.pedantic'] %}
+								<option id="gnu.c.compiler.option.warnings.pedantic.{{u.id}}" name="Pedantic (-pedantic)" superClass="gnu.c.compiler.option.warnings.pedantic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.pedanticerrors'] %}
+								<option id="gnu.c.compiler.option.warnings.pedantic.error.{{u.id}}" name="Pedantic warnings as errors (-pedantic-errors)" superClass="gnu.c.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['nostdinc'] %}
+								<option id="gnu.c.compiler.option.preprocessor.nostdinc.{{u.id}}" name="Do not search system directories (-nostdinc)" superClass="gnu.c.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['preprocess'] %}
+								<option id="gnu.c.compiler.option.preprocessor.preprocess.{{u.id}}" name="Preprocess only (-E)" superClass="gnu.c.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}								
+								{% if opts['common']['warnings.syntaxonly'] %}
+								<option id="gnu.c.compiler.option.warnings.syntax.{{u.id}}" name="Check syntax only (-fsyntax-only)" superClass="gnu.c.compiler.option.warnings.syntax" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.nowarn'] %}
+								<option id="gnu.c.compiler.option.warnings.nowarn.{{u.id}}" name="Inhibit all warnings (-w)" superClass="gnu.c.compiler.option.warnings.nowarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.extrawarn'] %}
+								<option id="gnu.c.compiler.option.warnings.extrawarn.{{u.id}}" name="Extra warnings (-Wextra)" superClass="gnu.c.compiler.option.warnings.extrawarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.toerrors'] %}
+								<option id="gnu.c.compiler.option.warnings.toerrors.{{u.id}}" name="Warnings as errors (-Werror)" superClass="gnu.c.compiler.option.warnings.toerrors" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.conversion'] %}
+								<option id="gnu.c.compiler.option.warnings.wconversion.{{u.id}}" name="Implicit conversion warnings (-Wconversion)" superClass="gnu.c.compiler.option.warnings.wconversion" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.prof'] %}
+								<option id="gnu.c.compiler.option.debugging.prof.{{u.id}}" name="Generate prof information (-p)" superClass="gnu.c.compiler.option.debugging.prof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.gprof'] %}
+								<option id="gnu.c.compiler.option.debugging.gprof.{{u.id}}" name="Generate gprof information (-pg)" superClass="gnu.c.compiler.option.debugging.gprof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.codecov'] %}
+								<option id="gnu.c.compiler.option.debugging.codecov.{{u.id}}" superClass="gnu.c.compiler.option.debugging.codecov" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="gnu.c.compiler.option.misc.verbose.{{u.id}}" name="Verbose (-v)" superClass="gnu.c.compiler.option.misc.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.PIC'] %}
+								<option id="gnu.c.compiler.option.misc.pic.{{u.id}}" name="Position Independent Code (-fPIC)" superClass="gnu.c.compiler.option.misc.pic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.datasections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.fdata.{{u.id}}" name="Place the data in their own section (-fdata-sections)" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.fdata" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.functionsections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction.{{u.id}}" name="Place the function in their own section (-ffunction-sections)" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['otheroptimizations'] != '' or opts['common']['optimization.other'] != '' %}
+								<option id="gnu.c.compiler.option.optimization.flags.{{u.id}}" superClass="gnu.c.compiler.option.optimization.flags" useByScannerDiscovery="false" value="{{opts['c']['otheroptimizations']}} {{opts['common']['optimization.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['other'] != '' or opts['c']['otherwarnings'] != '' or opts['common']['warnings.other'] != '' %}
+								<option id="fr.ac6.managedbuid.gnu.c.compiler.option.misc.other.{{u.id}}" name="Other flags" superClass="fr.ac6.managedbuid.gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="{{opts['c']['other']}} {{opts['c']['otherwarnings']}} {{opts['common']['warnings.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['slowflashdata'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.pcrop.{{u.id}}" name="No data reads in code memory (-mslow-flash-data) " superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.pcrop" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{opts['uid']['tool_c_compiler_input']}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
+							</tool>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}}" name="MCU G++ Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler">
+								{% if cfg_id == 'debug' %}
+								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
+								{% else %}
+								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.cpp.optimization.level.most" valueType="enumerated"/>
+								<option id="gnu.cpp.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.none" valueType="enumerated"/>
+								{% endif %}
+								<option id="gnu.cpp.compiler.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+									{% for path in include_paths %}
+									<listOptionValue builtIn="false" value="&quot;{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.cpp.compiler.option.preprocessor.def.{{u.id}}" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+								{% for s in opts['cpp']['defines'] %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+								{% endfor %}
+								</option>
+								{% if config_header %}
+								<option id="gnu.cpp.compiler.option.include.files.{{u.id}}" name="Include files (-include)" superClass="gnu.cpp.compiler.option.include.files" useByScannerDiscovery="false" valueType="includeFiles">
+									<listOptionValue builtIn="false" value="${ProjDirPath}/{{config_header}}"/>
+								</option>
+								{% endif %}
+								{% if 'compiler.std' in opts['cpp'] %}
+								{% if opts['cpp']['compiler.std'] %}
+								<option id="gnu.cpp.compiler.option.dialect.std.{{u.id}}" name="Language standard" superClass="gnu.cpp.compiler.option.dialect.std" useByScannerDiscovery="true" value="gnu.cpp.compiler.dialect.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+								{% endif %}
+								{% if opts['common']['warnings.pedantic'] %}
+								<option id="gnu.cpp.compiler.option.warnings.pedantic.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.pedantic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.pedanticerrors'] %}
+								<option id="gnu.cpp.compiler.option.warnings.pedantic.error.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['nostdinc'] %}
+								<option id="gnu.cpp.compiler.option.preprocessor.nostdinc.{{u.id}}" superClass="gnu.cpp.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['preprocess'] %}
+								<option id="gnu.cpp.compiler.option.preprocessor.preprocess.{{u.id}}" superClass="gnu.cpp.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.syntaxonly'] %}
+								<option id="gnu.cpp.compiler.option.warnings.syntax.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.syntax" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.nowarn'] %}
+								<option id="gnu.cpp.compiler.option.warnings.nowarn.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.nowarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="gnu.cpp.compiler.option.warnings.allwarn.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.allwarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% if opts['common']['warnings.extrawarn'] %}
+								<option id="gnu.cpp.compiler.option.warnings.extrawarn.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.extrawarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.toerrors'] %}
+								<option id="gnu.cpp.compiler.option.warnings.toerrors.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.toerrors" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}							
+								{% if opts['common']['warnings.conversion'] %}
+								<option id="gnu.cpp.compiler.option.warnings.wconversion.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.wconversion" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.prof'] %}
+								<option id="gnu.cpp.compiler.option.debugging.prof.{{u.id}}" superClass="gnu.cpp.compiler.option.debugging.prof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.gprof'] %}
+								<option id="gnu.cpp.compiler.option.debugging.gprof.{{u.id}}" superClass="gnu.cpp.compiler.option.debugging.gprof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.codecov'] %}
+								<option id="gnu.cpp.compiler.option.debugging.codecov.{{u.id}}" superClass="gnu.cpp.compiler.option.debugging.codecov" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="gnu.cpp.compiler.option.other.verbose.{{u.id}}" superClass="gnu.cpp.compiler.option.other.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.PIC'] %}
+								<option id="gnu.cpp.compiler.option.other.pic.{{u.id}}" superClass="gnu.cpp.compiler.option.other.pic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.datasections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.fdata.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.fdata" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.functionsections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction.{{u.id}}" name="Place the function in their own section (-ffunction-sections)" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['otheroptimizations'] != '' or opts['common']['optimization.other'] != '' %}
+								<option id="gnu.cpp.compiler.option.optimization.flags.{{u.id}}" superClass="gnu.cpp.compiler.option.optimization.flags" useByScannerDiscovery="false" value="{{opts['cpp']['otheroptimizations']}} {{opts['common']['optimization.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['cpp']['other'] != '' or opts['cpp']['otherwarnings'] != '' or opts['common']['warnings.other'] != '' %}
+								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.misc.other.{{u.id}}" name="Other flags" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.misc.other" useByScannerDiscovery="false" value="{{opts['cpp']['other']}} {{opts['cpp']['otherwarnings']}} {{opts['common']['warnings.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['cpp']['slowflashdata'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.pcrop.{{u.id}}" name="No data reads in code memory (-mslow-flash-data) " superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.pcrop" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.{{opts['uid']['tool_cpp_compiler_input']}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s"/>
+							</tool>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.{{u.id}}" name="MCU G++ Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker">
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script.{{u.id}}" name="Linker Script (-T)" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script" value="${ProjDirPath}/{{opts['name']}}/{{opts['ld']['script']}}" valueType="string"/>
+								{% if opts['ld']['flags'] != '' or opts['ld']['other'] != '' %}
+								<option id="gnu.cpp.link.option.flags.{{u.id}}" name="Linker flags" superClass="gnu.cpp.link.option.flags" value="{{ opts['ld']['flags']|join(' ') }} {{opts['ld']['other']}}" valueType="string"/>
+								{% endif %}
+								<option id="gnu.cpp.link.option.userobjs.{{u.id}}" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+									{% for path in object_files %}
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="gnu.cpp.link.option.libs.{{u.id}}" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+									{% for lib in libraries %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+								</option>
+								{% if opts['ld']['nostart'] %}
+								<option id="gnu.cpp.link.option.nostart.{{u.id}}" name="Do not use standard start files (-nostartfiles)" superClass="gnu.cpp.link.option.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nodeflibs'] %}
+								<option id="gnu.cpp.link.option.nodeflibs.{{u.id}}" superClass="gnu.cpp.link.option.nodeflibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nostdlibs'] %}
+								<option id="gnu.cpp.link.option.nostdlibs.{{u.id}}" superClass="gnu.cpp.link.option.nostdlibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['strip'] %}
+								<option id="gnu.cpp.link.option.strip.{{u.id}}" superClass="gnu.cpp.link.option.strip" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['shared'] %}
+								<option id="gnu.cpp.link.option.shared.{{u.id}}" superClass="gnu.cpp.link.option.shared" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['soname'] != '' %}
+								<option id="gnu.cpp.link.option.soname.{{u.id}}" superClass="gnu.cpp.link.option.soname" useByScannerDiscovery="false" value="{{opts['ld']['soname']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['ld']['implname'] != '' %}
+								<option id="gnu.cpp.link.option.implname.{{u.id}}" superClass="gnu.cpp.link.option.implname" useByScannerDiscovery="false" value="{{opts['ld']['implname']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['ld']['defname'] != '' %}
+								<option id="gnu.cpp.link.option.defname.{{u.id}}" superClass="gnu.cpp.link.option.defname" useByScannerDiscovery="false" value="{{opts['ld']['defname']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['common']['debugging.prof'] %}
+								<option id="gnu.cpp.link.option.debugging.prof.{{u.id}}" superClass="gnu.cpp.link.option.debugging.prof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.gprof'] %}
+								<option id="gnu.cpp.link.option.debugging.gprof.{{u.id}}" superClass="gnu.cpp.link.option.debugging.gprof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.codecov'] %}
+								<option id="gnu.cpp.link.option.debugging.codecov.{{u.id}}" superClass="gnu.cpp.link.option.debugging.codecov" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.{{u.id}}" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+								<option id="gnu.cpp.link.option.paths.{{u.id}}" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+									{% for path in library_paths %}
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+							</tool>
+							<tool id="fr.ac6.managedbuild.tool.gnu.archiver.{{u.id}}" name="MCU GCC Archiver" superClass="fr.ac6.managedbuild.tool.gnu.archiver"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.assembler.{{u.id}}" name="MCU GCC Assembler" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler">
+								<option id="gnu.both.asm.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
+									{% for path in include_paths %}
+									<listOptionValue builtIn="false" value="&quot;{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['as']['other'] != '' or opts['as']['otherwarnings'] != '' %}
+								<option id="gnu.both.asm.option.flags.{{u.id}}" superClass="gnu.both.asm.option.flags" useByScannerDiscovery="false" value="{{opts['as']['other']}} {{opts['as']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% for item in opts['as']['otherwarnings'] %}
+								{% if item == '-W' %}
+								<option id="gnu.both.asm.option.warnings.nowarn.{{u.id}}" superClass="gnu.both.asm.option.warnings.nowarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% endfor %}
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.{{u.id}}" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.assembler.input.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler.input"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="{{exclude_paths}}" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}.fr.ac6.managedbuild.target.gnu.cross.exe.{{u.id}}" name="Executable" projectType="fr.ac6.managedbuild.target.gnu.cross.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}};fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}}.;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{opts['uid']['tool_c_compiler']}};fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{opts['uid']['tool_c_compiler_input']}}">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}};fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}}.;fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}};fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.{{opts['uid']['tool_cpp_compiler_input']}}">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/language_settings_commom.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/language_settings_commom.tmpl
new file mode 100755
index 0000000..99566a5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/language_settings_commom.tmpl
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	{% for cfg_id in options %}
+	{% set opts = options[cfg_id] %}
+	<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}" name="{{opts['name']}}">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
+			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1025524915312781673" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+	{% endfor %}
+</project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/launch.tmpl
new file mode 100755
index 0000000..efba7bd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/launch.tmpl
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="fr.ac6.mcu.debug.config.launchConfigurationType">
+<stringAttribute key="DEBBUGER_BOARD_NAME" value="{{board_name}}"/>
+<stringAttribute key="DEBBUGER_MCU_NAME" value="{{mcu_name}}"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_DEVICE" value="ST-Link"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_DEVICE_SHAREABLE_ALLOWED" value="false"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_INTERFACE" value="SWD"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_INTERFACE_FREQUENCY" value="4000000.0"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_LOW_POWER_MODE_ALLOWED" value="true"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_RESET_MODE" value="connect_under_reset"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_STOP_WATCHDOG_THEN_HALTED_ALLOWED" value="true"/>
+<booleanAttribute key="fr.ac6.mcu.ide.OPENOCD_GENERATOR_OPTION" value="false"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_NAME" value="&quot;${openstm32_openocd_path}{% if platform == 'win32' %}\{% else %}/{% endif %}openocd{% if platform == 'win32' %}.exe{% endif %}&quot;"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_OTHER_OPTIONS" value=""/>
+{% set cfg_id = 'debug' %}
+{% set opts = options[cfg_id] %}
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_SCRIPT" value="{{opts['name']}}{% if platform == 'win32' %}\{% else %}/{% endif %}{{name}} {{opts['name']}}.cfg"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_SCRIPT_CHOICE" value="automated"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_SCRIPT_IS_LEGACY" value="false"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="monitor reset halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${openstm32_compiler_path}{% if platform == 'win32' %}\{% else %}/{% endif %}arm-none-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="{{opts['name']}}{% if platform == 'win32' %}\{% else %}/{% endif %}{{name}}-{{cfg_id}}.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="{{name}}"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/{{name}}"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
+<listEntry value="org.eclipse.debug.ui.launchGroup.{{cfg_id}}"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="fr.ac6.mcu.debug.launching.MCUGdbProcessFactory"/>
+</launchConfiguration>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/makefile.targets.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/makefile.targets.tmpl
new file mode 100755
index 0000000..da87905
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/makefile.targets.tmpl
@@ -0,0 +1,16 @@
+# DO NOT REMOVE! Generated by the SW4STM32 exporter from the mbed project.
+
+PREPROC_CMD ?= {{cpp_cmd}}
+
+ldclean:
+{% for config, opts in options.iteritems() %}
+	$(RM) {{opts['ld']['script']}}
+{% endfor %}
+
+{% for config, opts in options.iteritems() %}
+{{opts['ld']['script']}}: ../{{ld_script}}
+	$(PREPROC_CMD) {{opts.ld.other}} $< -o $@
+
+{{name}}-{{config}}.elf: {{opts['ld']['script']}}
+
+{% endfor %}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/project_common.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/project_common.tmpl
new file mode 100755
index 0000000..2e0378c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/sw4stm32/project_common.tmpl
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>fr.ac6.mcu.ide.core.MCUProjectNature</nature>
+	</natures>
+</projectDescription>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/__init__.py
new file mode 100755
index 0000000..8382bae
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/__init__.py
@@ -0,0 +1,271 @@
+import os
+from os.path import sep, normpath, join, exists
+import ntpath
+import copy
+from collections import namedtuple
+import shutil
+from subprocess import Popen, PIPE
+import re
+
+from tools.arm_pack_manager import Cache
+from tools.targets import TARGET_MAP
+from tools.export.exporters import Exporter, apply_supported_whitelist
+from tools.export.cmsis import DeviceCMSIS
+
+cache_d = False
+
+
+class DeviceUvision(DeviceCMSIS):
+    """Uvision Device class, inherits CMSIS Device class
+
+    Encapsulates information necessary for uvision project targets"""
+    def __init__(self, target):
+        DeviceCMSIS.__init__(self, target)
+        dev_format = "$$Device:{0}${1}"
+        self.svd = ''
+        if self.debug_svd:
+            self.svd = dev_format.format(self.dname, self.debug_svd)
+        self.reg_file = dev_format.format(self.dname, self.compile_header)
+        self.debug_interface = self.uv_debug()
+        self.flash_dll = self.generate_flash_dll()
+
+    def uv_debug(self):
+        """Return a namedtuple of information about uvision debug settings"""
+        UVDebug = namedtuple('UVDebug',['bin_loc','core_flag', 'key'])
+
+        # CortexMXn => pCMX
+        cpu = self.core.replace("Cortex-", "C")
+        cpu = cpu.replace("+", "")
+        cpu = cpu.replace("F", "")
+        cpu_flag = "p"+cpu
+
+        # Locations found in Keil_v5/TOOLS.INI
+        debuggers = {"st-link": ('STLink\\ST-LINKIII-KEIL_SWO.dll', 'ST-LINKIII-KEIL_SWO'),
+                     "j-link":('Segger\\JL2CM3.dll', 'JL2CM3'),
+                     "cmsis-dap":('BIN\\CMSIS_AGDI.dll', 'CMSIS_AGDI'),
+                     "nulink":('NULink\\Nu_Link.dll','Nu_Link')}
+        res = debuggers[self.debug.lower()]
+        binary = res[0]
+        key = res[1]
+
+        return UVDebug(binary, cpu_flag, key)
+
+    def generate_flash_dll(self):
+        '''Flash DLL string from uvision
+        S = SW/JTAG Clock ID
+        C = CPU index in JTAG chain
+        P = Access Port
+        For the Options for Target -> Debug tab -> settings -> "Flash" tab in the dialog:
+        FD = RAM Start for Flash Functions
+        FC = RAM Size for Flash Functions
+        FN = Number of Flash types
+        FF = Flash File Name (without an extension)
+        FS = Start Address of the Flash Device
+        FL = Size of the Flash Device
+        FP = Full path to the Device algorithm (RTE)
+
+        Necessary to flash some targets. Info gathered from algorithms field of pdsc file.
+        '''
+        fl_count = 0
+        def get_mem_no_x(mem_str):
+            mem_reg = "\dx(\w+)"
+            m = re.search(mem_reg, mem_str)
+            return m.group(1) if m else None
+
+        RAMS = [(get_mem_no_x(info["start"]), get_mem_no_x(info["size"]))
+                for mem, info in self.target_info["memory"].items() if "RAM" in mem]
+        format_str = "UL2CM3(-S0 -C0 -P0 -FD{ramstart}"+" -FC{ramsize} "+"-FN{num_algos} {extra_flags})"
+        ramstart = ''
+        #Default according to Keil developer
+        ramsize = '1000'
+        if len(RAMS)>=1:
+            ramstart = RAMS[0][0]
+        extra_flags = []
+        for name, info in self.target_info["algorithm"].items():
+            if not name or not info:
+                continue
+            if int(info["default"])==0:
+                continue
+            name_reg = "\w*/([\w_]+)\.flm"
+            m = re.search(name_reg, name.lower())
+            fl_name = m.group(1) if m else None
+            name_flag = "-FF" + str(fl_count) + fl_name
+
+            start, size = get_mem_no_x(info["start"]), get_mem_no_x(info["size"])
+            rom_start_flag = "-FS"+str(fl_count)+str(start)
+            rom_size_flag = "-FL" + str(fl_count) + str(size)
+
+            if info["ramstart"] is not None and info["ramsize"] is not None:
+                ramstart = get_mem_no_x(info["ramstart"])
+                ramsize = get_mem_no_x(info["ramsize"])
+
+            path_flag = "-FP" + str(fl_count) + "($$Device:"+self.dname+"$"+name+")"
+
+            extra_flags.extend([name_flag, rom_start_flag, rom_size_flag, path_flag])
+            fl_count += 1
+
+        extra = " ".join(extra_flags)
+        return format_str.format(ramstart=ramstart,
+                                 ramsize=ramsize,
+                                 extra_flags=extra, num_algos=fl_count)
+
+
+class Uvision(Exporter):
+    """Keil Uvision class
+
+    This class encapsulates information to be contained in a Uvision
+    project file (.uvprojx).
+    The needed information can be viewed in uvision.tmpl
+    """
+    NAME = 'uvision5'
+    TOOLCHAIN = 'ARM'
+
+    POST_BINARY_WHITELIST = set([
+        "MCU_NRF51Code.binary_hook",
+        "TEENSY3_1Code.binary_hook",
+        "LPCTargetCode.lpc_patch",
+        "LPC4088Code.binary_hook",
+        "MTSCode.combine_bins_mts_dot",
+        "MTSCode.combine_bins_mts_dragonfly",
+        "NCS36510TargetCode.ncs36510_addfib"
+    ])
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return apply_supported_whitelist(
+            cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target) and\
+            DeviceCMSIS.check_supported(target_name)
+
+    #File associations within .uvprojx file
+    file_types = {'.cpp': 8, '.c': 1, '.s': 2,
+                  '.obj': 3, '.o': 3, '.lib': 4,
+                  '.ar': 4, '.h': 5, '.hpp': 5, '.sct': 4}
+
+    def uv_files(self, files):
+        """An generator containing Uvision specific information about project files
+        Positional Arguments:
+        files - the location of source files
+
+        .uvprojx XML for project file:
+        <File>
+            <FileType>{{file.type}}</FileType>
+            <FileName>{{file.name}}</FileName>
+            <FilePath>{{file.loc}}</FilePath>
+        </File>
+        """
+        for loc in files:
+            #Encapsulates the information necessary for template entry above
+            UVFile = namedtuple('UVFile', ['type','loc','name'])
+            _, ext = os.path.splitext(loc)
+            if ext.lower() in self.file_types:
+                type = self.file_types[ext.lower()]
+                name = ntpath.basename(normpath(loc))
+                yield UVFile(type, loc, name)
+
+    def format_flags(self):
+        """Format toolchain flags for Uvision"""
+        flags = copy.deepcopy(self.flags)
+        # to be preprocessed with armcc
+        asm_flag_string = (
+            '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' +
+            ",".join(filter(lambda f: f.startswith("-D"), flags['asm_flags'])))
+        flags['asm_flags'] = asm_flag_string
+        # All non-asm flags are in one template field
+        c_flags = list(set(flags['c_flags'] + flags['cxx_flags'] +flags['common_flags']))
+        ld_flags = list(set(flags['ld_flags'] ))
+        # These flags are in template to be set by user i n IDE
+        template = ["--no_vla", "--cpp", "--c99"]
+        # Flag is invalid if set in template
+        # Optimizations are also set in the template
+        invalid_flag = lambda x: x in template or re.match("-O(\d|time)", x) 
+        flags['c_flags'] = [flag.replace('"','\\"') for flag in c_flags if not invalid_flag(flag)]
+        flags['c_flags'] = " ".join(flags['c_flags'])
+        flags['ld_flags'] = " ".join(flags['ld_flags'])
+        return flags
+
+    def format_src(self, srcs):
+        """Make sources into the named tuple for use in the template"""
+        grouped = self.group_project_files(srcs)
+        for group, files in grouped.items():
+            grouped[group] = sorted(list(self.uv_files(files)),
+                                    key=lambda (_, __, name): name.lower())
+        return grouped
+
+    @staticmethod
+    def format_fpu(core):
+        """Generate a core's FPU string"""
+        if core.endswith("FD"):
+            return "FPU3(DFPU)"
+        elif core.endswith("F"):
+            return "FPU2"
+        else:
+            return ""
+
+    def generate(self):
+        """Generate the .uvproj file"""
+        cache = Cache(True, False)
+        if cache_d:
+            cache.cache_descriptors()
+
+        srcs = self.resources.headers + self.resources.s_sources + \
+               self.resources.c_sources + self.resources.cpp_sources + \
+               self.resources.objects + self.resources.libraries
+        ctx = {
+            'name': self.project_name,
+            # project_files => dict of generators - file group to generator of
+            # UVFile tuples defined above
+            'project_files': sorted(list(self.format_src(srcs).iteritems()),
+                                    key=lambda (group, _): group.lower()),
+            'linker_script':self.toolchain.correct_scatter_shebang(
+                self.resources.linker_script),
+            'include_paths': '; '.join(self.resources.inc_dirs).encode('utf-8'),
+            'device': DeviceUvision(self.target),
+        }
+        self.generated_files.append(ctx['linker_script'])
+        core = ctx['device'].core
+        ctx['cputype'] = core.rstrip("FD")
+        if core.endswith("FD"):
+            ctx['fpu_setting'] = 3
+        elif core.endswith("F"):
+            ctx['fpu_setting'] = 2
+        else:
+            ctx['fpu_setting'] = 1
+        ctx['fputype'] = self.format_fpu(core)
+        ctx.update(self.format_flags())
+        self.gen_file('uvision/uvision.tmpl', ctx, self.project_name+".uvprojx")
+        self.gen_file('uvision/uvision_debug.tmpl', ctx, self.project_name + ".uvoptx")
+
+    @staticmethod
+    def build(project_name, log_name='build_log.txt', cleanup=True):
+        """ Build Uvision project """
+        # > UV4 -r -j0 -o [log_name] [project_name].uvprojx
+        proj_file = project_name + ".uvprojx"
+        cmd = ['UV4', '-r', '-j0', '-o', log_name, proj_file]
+
+        # Build the project
+        p = Popen(cmd, stdout=PIPE, stderr=PIPE)
+        out, err = p.communicate()
+        ret_code = p.returncode
+
+        # Print the log file to stdout
+        with open(log_name, 'r') as f:
+            print f.read()
+
+        # Cleanup the exported and built files
+        if cleanup:
+            os.remove(log_name)
+            os.remove(project_name+".uvprojx")
+            os.remove(project_name+".uvoptx")
+            # legacy .build directory cleaned if exists
+            if exists('.build'):
+                shutil.rmtree('.build')
+            if exists('BUILD'):
+                shutil.rmtree('BUILD')
+
+        # Returns 0 upon success, 1 upon a warning, and neither upon an error
+        if ret_code != 0 and ret_code != 1:
+            # Seems like something went wrong.
+            return -1
+        else:
+            return 0
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/__init__.pyc
new file mode 100755
index 0000000..b829a7f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/uvision.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/uvision.tmpl
new file mode 100755
index 0000000..49c708c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/uvision.tmpl
@@ -0,0 +1,438 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>{{name}}</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>{{device.dname}}</Device>
+          <Vendor>{{device.dvendor}}</Vendor>
+          <PackID>{{device.pack_id}}</PackID>
+          <PackURL>{{device.pack_url}}</PackURL>
+          <Cpu>CPUTYPE("{{cputype}}") {{fputype}}</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>{{device.flash_dll}}</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>{{device.reg_file}}</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>{{device.svd}}</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\BUILD\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\BUILD\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments> </SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-{{device.debug_interface.core_flag}}</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>0</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>{{device.debug_interface.bin_loc}}</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>0</Capability>
+            <DriverSelection>-1</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"{{device.core.replace("D","").replace("F","")}}"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>{{fpu_setting}}</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              {
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0</StartAddress>
+                <Size>0</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0</StartAddress>
+                <Size>0</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x1fffe000</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>0</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>{{c_flags}}</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>{{include_paths}}</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>0</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls>{{asm_flags}}</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>{{include_paths}}</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>0</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0</TextAddressRange>
+            <DataAddressRange>0</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>{{linker_script}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>{{ld_flags}}</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group, files in project_files %}
+        <Group>
+            <GroupName>{{group}}</GroupName>
+            <Files>
+                {% for file in files %}
+                <File>
+                    <FileType>{{file.type}}</FileType>
+                    <FileName>{{file.name}}</FileName>
+                    <FilePath>{{file.loc}}</FilePath>
+                </File>
+                {% endfor %}
+            </Files>
+         </Group>
+         {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/uvision_debug.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/uvision_debug.tmpl
new file mode 100755
index 0000000..60bd1e6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/uvision/uvision_debug.tmpl
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+	<SchemaVersion>1.0</SchemaVersion>
+	<Target>
+		<TargetName>{{name}}</TargetName>
+		<ToolsetNumber>0x4</ToolsetNumber>
+		<ToolsetName>ARM-ADS</ToolsetName>
+		<TargetOption>
+			<DebugOpt>
+				<uSim>0</uSim>
+				<uTrg>1</uTrg>
+				<nTsel>11</nTsel>
+				<pMon>{{device.debug_interface.bin_loc}}</pMon>
+			</DebugOpt>
+			<TargetDriverDllRegistry>
+				<SetRegEntry>
+					<Number>0</Number>
+					<Key>{{device.debug_interface.key}}</Key>
+					<Name>{{device.flash_dll}}</Name>
+				</SetRegEntry>
+			</TargetDriverDllRegistry>
+		</TargetOption>
+	</Target>
+</ProjectOpt>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/__init__.py
new file mode 100755
index 0000000..86804ff
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/__init__.py
@@ -0,0 +1,98 @@
+# mbed SDK
+# Copyright (c) 2011-2016 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from os.path import join, exists, realpath, relpath, basename, isfile, splitext
+from os import makedirs, listdir
+import json
+
+from tools.export.makefile import Makefile, GccArm, Armc5, IAR
+
+class VSCode(Makefile):
+    """Generic VSCode project. Intended to be subclassed by classes that
+    specify a type of Makefile.
+    """
+    def generate(self):
+        """Generate Makefile and VSCode launch and task files
+        """
+        super(VSCode, self).generate()
+        ctx = {
+            'name': self.project_name,
+            'elf_location': join('BUILD', self.project_name)+'.elf',
+            'c_symbols': self.toolchain.get_symbols(),
+            'asm_symbols': self.toolchain.get_symbols(True),
+            'target': self.target,
+            'include_paths': self.resources.inc_dirs,
+            'load_exe': str(self.LOAD_EXE).lower()
+        }
+
+        if not exists(join(self.export_dir, '.vscode')):
+            makedirs(join(self.export_dir, '.vscode'))
+
+        self.gen_file('vscode/tasks.tmpl', ctx,
+                      join('.vscode', 'tasks.json'))
+        self.gen_file('vscode/launch.tmpl', ctx,
+                      join('.vscode', 'launch.json'))
+        self.gen_file('vscode/settings.tmpl', ctx,
+                      join('.vscode', 'settings.json'))
+
+        # So.... I want all .h and .hpp files in self.resources.inc_dirs
+        all_directories = []
+
+        for directory in self.resources.inc_dirs:
+            if not directory:
+                continue
+
+            if directory == ".":
+                all_directories.append("${workspaceRoot}/*")
+            else:
+                all_directories.append(directory.replace("./", "${workspaceRoot}/") + "/*")
+
+        cpp_props = {
+            "configurations": [
+                {
+                    "name": "Windows",
+                    "includePath": [x.replace("/", "\\") for x in all_directories],
+                    "defines": [symbol for symbol in self.toolchain.get_symbols()]
+                },
+                {
+                    "name": "Mac",
+                    "includePath": all_directories,
+                    "defines": [symbol for symbol in self.toolchain.get_symbols()]
+                },
+                {
+                    "name": "Linux",
+                    "includePath": all_directories,
+                    "defines": [symbol for symbol in self.toolchain.get_symbols()]
+                }
+            ]
+        }
+
+        with open(join(self.export_dir, '.vscode', 'c_cpp_properties.json'), 'w') as outfile:
+            json.dump(cpp_props, outfile, indent=4, separators=(',', ': '))
+
+
+class VSCodeGcc(VSCode, GccArm):
+    LOAD_EXE = True
+    NAME = "VSCode-GCC-ARM"
+
+class VSCodeArmc5(VSCode, Armc5):
+    LOAD_EXE = True
+    NAME = "VSCode-Armc5"
+
+class VSCodeIAR(VSCode, IAR):
+    LOAD_EXE = True
+    NAME = "VSCode-IAR"
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/__init__.pyc
new file mode 100755
index 0000000..795501c
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/launch.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/launch.tmpl
new file mode 100755
index 0000000..8808142
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/launch.tmpl
@@ -0,0 +1,64 @@
+{
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "name": "C++ Launch",
+            "type": "cppdbg",
+            "request": "launch",
+            "program": "${workspaceRoot}/BUILD/${workspaceRootFolderName}.elf",
+            "args": [],
+            "stopAtEntry": true,
+            "cwd": "${workspaceRoot}",
+            "environment": [],
+            "externalConsole": false,
+            "debugServerArgs": "",
+            "serverLaunchTimeout": 20000,
+            "filterStderr": true,
+            "filterStdout": false,
+            "serverStarted": "GDB\\ server\\ started",
+            "preLaunchTask": "make",
+            "setupCommands": [
+                { "text": "-target-select remote localhost:3333", "description": "connect to target", "ignoreFailures": false },
+                { "text": "-file-exec-and-symbols ${workspaceRoot}/BUILD/${workspaceRootFolderName}.elf", "description": "load file", "ignoreFailures": false},
+                { "text": "-interpreter-exec console \"monitor endian little\"", "ignoreFailures": false },
+                { "text": "-interpreter-exec console \"monitor reset\"", "ignoreFailures": false },
+                { "text": "-interpreter-exec console \"monitor halt\"", "ignoreFailures": false },
+                { "text": "-interpreter-exec console \"monitor arm semihosting enable\"", "ignoreFailures": false },
+                { "text": "-target-download", "description": "flash target", "ignoreFailures": false }
+            ],
+            "logging": {
+                "moduleLoad": true,
+                "trace": true,
+                "engineLogging": true,
+                "programOutput": true,
+                "exceptions": true
+            },
+            "linux": {
+                "MIMode": "gdb",
+                "MIDebuggerPath": "/usr/bin/arm-none-eabi-gdb",
+                "debugServerPath": "pyocd-gdbserver"
+            },
+            "osx": {
+                "MIMode": "gdb",
+                "MIDebuggerPath": "/usr/local/bin/arm-none-eabi-gdb",
+                "debugServerPath": "pyocd-gdbserver"
+            },
+            "windows": {
+                "preLaunchTask": "make.exe",
+                "MIMode": "gdb",
+                "MIDebuggerPath": "C:\\Program Files (x86)\\GNU Tools ARM Embedded\\4.9 2015q3\\bin\\arm-none-eabi-gdb.exe",
+                "debugServerPath": "pyocd-gdbserver.exe",
+                "setupCommands": [
+                    { "text": "-environment-cd ${workspaceRoot}\\BUILD" },
+                    { "text": "-target-select remote localhost:3333", "description": "connect to target", "ignoreFailures": false },
+                    { "text": "-file-exec-and-symbols ${workspaceRootFolderName}.elf", "description": "load file", "ignoreFailures": false},
+                    { "text": "-interpreter-exec console \"monitor endian little\"", "ignoreFailures": false },
+                    { "text": "-interpreter-exec console \"monitor reset\"", "ignoreFailures": false },
+                    { "text": "-interpreter-exec console \"monitor halt\"", "ignoreFailures": false },
+                    { "text": "-interpreter-exec console \"monitor arm semihosting enable\"", "ignoreFailures": false },
+                    { "text": "-target-download", "description": "flash target", "ignoreFailures": false }
+                ]
+            }
+        }
+    ]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/settings.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/settings.tmpl
new file mode 100755
index 0000000..d13263e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/settings.tmpl
@@ -0,0 +1,5 @@
+// Place your settings in this file to overwrite default and user settings.
+{
+    "C_Cpp.addWorkspaceRootToIncludePath": false,
+    "C_Cpp.intelliSenseEngine": "Tag Parser"
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/tasks.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/tasks.tmpl
new file mode 100755
index 0000000..dbfa7aa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/vscode/tasks.tmpl
@@ -0,0 +1,30 @@
+{
+    // See https://go.microsoft.com/fwlink/?LinkId=733558
+    // for the documentation about the tasks.json format
+    "version": "0.1.0",
+    "name": "make",
+    "isShellCommand": true,
+    "showOutput": "always",
+    "problemMatcher": {
+        "owner": "cpp",
+        "fileLocation": ["relative", "${workspaceRoot}/mbed-os"],
+        "pattern": {
+            "regexp": "^(.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+            "file": 1,
+            "line": 2,
+            "column": 3,
+            "severity": 4,
+            "message": 5
+        }
+    },
+    "args": ["-j"],
+    "linux": {
+        "command": "make"
+    },
+    "osx": {
+        "command": "make"
+    },
+    "windows": {
+        "command": "make.exe"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/zip/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/zip/__init__.py
new file mode 100755
index 0000000..f2d9a19
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/zip/__init__.py
@@ -0,0 +1,44 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import basename
+
+from tools.export.exporters import Exporter
+
+
+class ZIP(Exporter):
+    NAME = 'ZIP'
+
+    TARGETS = [
+    ]
+
+    USING_MICROLIB = [
+    ]
+
+    FILE_TYPES = {
+        'c_sources':'1',
+        'cpp_sources':'8',
+        's_sources':'2'
+    }
+
+    TOOLCHAIN = 'ARM'
+
+    def get_toolchain(self):
+        return 'uARM' if (self.target in self.USING_MICROLIB) else 'ARM'
+
+    def generate(self):
+        return True
+        
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/zip/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/zip/__init__.pyc
new file mode 100755
index 0000000..7a541be
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/export/zip/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/c_blob_mbed.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/c_blob_mbed.tmpl
new file mode 100755
index 0000000..a101725
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/c_blob_mbed.tmpl
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "flash_data.h"
+#include "platform/mbed_critical.h"
+
+// This file is automatically generated
+
+#if DEVICE_FLASH
+
+// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
+static uint32_t FLASH_ALGO[] = {
+    {{algo.format_algo_data(4, 8, "c")}}
+};
+
+static const flash_algo_t flash_algo_config = {
+    .init = {{'0x%x' % algo.symbols['Init']}},
+    .uninit = {{'0x%x' % algo.symbols['UnInit']}},
+    .erase_sector = {{'0x%x' % algo.symbols['EraseSector']}},
+    .program_page = {{'0x%x' % algo.symbols['ProgramPage']}},
+    .static_base = {{'0x%x' % algo.rw_start}},
+    .algo_blob = FLASH_ALGO
+};
+
+static const sector_info_t sectors_info[] = {
+{%- for start, size  in algo.sector_sizes %}
+    {{ "{0x%x, 0x%x}" % (start + algo.flash_start, size) }}, 
+{%- endfor %}
+};
+
+static const flash_target_config_t flash_target_config = {
+    .page_size  = {{'0x%x' % algo.page_size}},
+    .flash_start = {{'0x%x' % algo.flash_start}},
+    .flash_size = {{'0x%x' % algo.flash_size}},
+    .sectors = sectors_info,
+    .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
+};
+
+void flash_set_target_config(flash_t *obj)
+{
+    obj->flash_algo = &flash_algo_config;
+    obj->target_config = &flash_target_config;
+}
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/extract.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/extract.py
new file mode 100755
index 0000000..a64ef2c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/extract.py
@@ -0,0 +1,107 @@
+#!/usr/bin/env python
+"""
+ mbed
+ Copyright (c) 2017-2017 ARM Limited
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+     http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+"""
+
+from __future__ import print_function
+import sys
+import os
+import argparse
+from os.path import join, abspath, dirname
+from flash_algo import PackFlashAlgo
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), "..", ".."))
+sys.path.insert(0, ROOT)
+
+from tools.targets import TARGETS
+from tools.arm_pack_manager import Cache
+
+TEMPLATE_PATH = "c_blob_mbed.tmpl"
+
+
+def main():
+    """Generate flash algorithms"""
+    parser = argparse.ArgumentParser(description='Flash generator')
+    parser.add_argument("--rebuild_all", action="store_true",
+                        help="Rebuild entire cache")
+    parser.add_argument("--rebuild_descriptors", action="store_true",
+                        help="Rebuild descriptors")
+    parser.add_argument("--target", default=None,
+                        help="Name of target to generate algo for")
+    parser.add_argument("--all", action="store_true",
+                        help="Build all flash algos for devcies")
+    args = parser.parse_args()
+
+    cache = Cache(True, True)
+    if args.rebuild_all:
+        cache.cache_everything()
+        print("Cache rebuilt")
+        return
+
+    if args.rebuild_descriptors:
+        cache.cache_descriptors()
+        print("Descriptors rebuilt")
+        return
+
+    if args.target is None:
+        device_and_filenames = [(target.device_name, target.name) for target
+                                in TARGETS if hasattr(target, "device_name")]
+    else:
+        device_and_filenames = [(args.target, args.target.replace("/", "-"))]
+
+    try:
+        os.mkdir("output")
+    except OSError:
+        # Directory already exists
+        pass
+
+    for device, filename in device_and_filenames:
+        dev = cache.index[device]
+        binaries = cache.get_flash_algorthim_binary(device, all=True)
+        algos = [PackFlashAlgo(binary.read()) for binary in binaries]
+        filtered_algos = algos if args.all else filter_algos(dev, algos)
+        for idx, algo in enumerate(filtered_algos):
+            file_name = ("%s_%i.c" % (filename, idx)
+                         if args.all or len(filtered_algos) != 1
+                         else "%s.c" % filename)
+            output_path = join("output", file_name)
+            algo.process_template(TEMPLATE_PATH, output_path)
+        print("%s: %s      \r" % (device, filename))
+
+
+def filter_algos(dev, algos):
+    if "memory" not in dev:
+        return algos
+    if "IROM1" not in dev["memory"]:
+        return algos
+    if "IROM2" in dev["memory"]:
+        return algos
+
+    rom_rgn = dev["memory"]["IROM1"]
+    try:
+        start = int(rom_rgn["start"], 0)
+        size = int(rom_rgn["size"], 0)
+    except ValueError:
+        return algos
+
+    matching_algos = [algo for algo in algos if 
+                      algo.flash_start == start and algo.flash_size == size]
+    return matching_algos if len(matching_algos) == 1 else algos
+
+
+if __name__ == '__main__':
+    main()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/flash_algo.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/flash_algo.py
new file mode 100755
index 0000000..814a0c8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/flash_algo/flash_algo.py
@@ -0,0 +1,359 @@
+#!/usr/bin/env python
+"""
+ mbed
+ Copyright (c) 2017-2017 ARM Limited
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+     http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+"""
+
+from __future__ import print_function
+import os
+import struct
+import binascii
+import argparse
+import logging
+import StringIO
+import jinja2
+from collections import namedtuple
+from itertools import count
+
+from elftools.common.py3compat import bytes2str
+from elftools.elf.elffile import ELFFile
+from elftools.elf.sections import SymbolTableSection
+
+logger = logging.getLogger(__name__)
+logger.addHandler(logging.NullHandler())
+
+
+def main():
+    parser = argparse.ArgumentParser(description="Algo Extracter")
+    parser.add_argument("input", help="File to extract flash algo from")
+    parser.add_argument("template", default="py_blob.tmpl",
+                        help="Template to use")
+    parser.add_argument("output", help="Output file")
+    args = parser.parse_args()
+
+    with open(args.input, "rb") as file_handle:
+        data = file_handle.read()
+    algo = PackFlashAlgo(data)
+    algo.process_template(args.template, args.output)
+
+
+class PackFlashAlgo(object):
+    """
+    Class to wrap a flash algo
+
+    This class is intended to provide easy access to the information
+    provided by a flash algorithm, such as symbols and the flash
+    algorithm itself.
+    """
+
+    REQUIRED_SYMBOLS = set([
+        "Init",
+        "UnInit",
+        "EraseSector",
+        "ProgramPage",
+    ])
+
+    EXTRA_SYMBOLS = set([
+        "BlankCheck",
+        "EraseChip",
+        "Verify",
+    ])
+
+    def __init__(self, data):
+        """Construct a PackFlashAlgorithm from an ElfFileSimple"""
+        self.elf = ElfFileSimple(data)
+        self.flash_info = PackFlashInfo(self.elf)
+
+        self.flash_start = self.flash_info.start
+        self.flash_size = self.flash_info.size
+        self.page_size = self.flash_info.page_size
+        self.sector_sizes = self.flash_info.sector_info_list
+
+        symbols = {}
+        symbols.update(_extract_symbols(self.elf, self.REQUIRED_SYMBOLS))
+        symbols.update(_extract_symbols(self.elf, self.EXTRA_SYMBOLS,
+                                        default=0xFFFFFFFF))
+        self.symbols = symbols
+
+        sections_to_find = (
+            ("PrgCode", "SHT_PROGBITS"),
+            ("PrgData", "SHT_PROGBITS"),
+            ("PrgData", "SHT_NOBITS"),
+        )
+
+        ro_rw_zi = _find_sections(self.elf, sections_to_find)
+        ro_rw_zi = _algo_fill_zi_if_missing(ro_rw_zi)
+        error_msg = _algo_check_for_section_problems(ro_rw_zi)
+        if error_msg is not None:
+            raise Exception(error_msg)
+
+        sect_ro, sect_rw, sect_zi = ro_rw_zi
+        self.ro_start = sect_ro["sh_addr"]
+        self.ro_size = sect_ro["sh_size"]
+        self.rw_start = sect_rw["sh_addr"]
+        self.rw_size = sect_rw["sh_size"]
+        self.zi_start = sect_zi["sh_addr"]
+        self.zi_size = sect_zi["sh_size"]
+
+        self.algo_data = _create_algo_bin(ro_rw_zi)
+
+    def format_algo_data(self, spaces, group_size, fmt):
+        """"
+        Return a string representing algo_data suitable for use in a template
+
+        The string is intended for use in a template.
+
+        :param spaces: The number of leading spaces for each line
+        :param group_size: number of elements per line (element type
+            depends of format)
+        :param fmt: - format to create - can be either "hex" or "c"
+        """
+        padding = " " * spaces
+        if fmt == "hex":
+            blob = binascii.b2a_hex(self.algo_data)
+            line_list = []
+            for i in xrange(0, len(blob), group_size):
+                line_list.append('"' + blob[i:i + group_size] + '"')
+            return ("\n" + padding).join(line_list)
+        elif fmt == "c":
+            blob = self.algo_data[:]
+            pad_size = 0 if len(blob) % 4 == 0 else 4 - len(blob) % 4
+            blob = blob + "\x00" * pad_size
+            integer_list = struct.unpack("<" + "L" * (len(blob) / 4), blob)
+            line_list = []
+            for pos in range(0, len(integer_list), group_size):
+                group = ["0x%08x" % value for value in
+                         integer_list[pos:pos + group_size]]
+                line_list.append(", ".join(group))
+            return (",\n" + padding).join(line_list)
+        else:
+            raise Exception("Unsupported format %s" % fmt)
+
+    def process_template(self, template_path, output_path, data_dict=None):
+        """
+        Generate output from the supplied template
+
+        All the public methods and fields of this class can be accessed from
+        the template via "algo".
+
+        :param template_path: Relative or absolute file path to the template
+        :param output_path: Relative or absolute file path to create
+        :param data_dict: Additional data to use when generating
+        """
+        if data_dict is None:
+            data_dict = {}
+        else:
+            assert isinstance(data_dict, dict)
+            data_dict = dict(data_dict)
+        assert "algo" not in data_dict, "algo already set by user data"
+        data_dict["algo"] = self
+
+        with open(template_path) as file_handle:
+            template_text = file_handle.read()
+
+        template = jinja2.Template(template_text)
+        target_text = template.render(data_dict)
+
+        with open(output_path, "wb") as file_handle:
+            file_handle.write(target_text)
+
+
+def _extract_symbols(simple_elf, symbols, default=None):
+    """Fill 'symbols' field with required flash algo symbols"""
+    to_ret = {}
+    for symbol in symbols:
+        if symbol not in simple_elf.symbols:
+            if default is not None:
+                to_ret[symbol] = default
+                continue
+            raise Exception("Missing symbol %s" % symbol)
+        to_ret[symbol] = simple_elf.symbols[symbol].value
+    return to_ret
+
+
+def _find_sections(elf, name_type_pairs):
+    """Return a list of sections the same length and order of the input list"""
+    sections = [None] * len(name_type_pairs)
+    for section in elf.iter_sections():
+        section_name = bytes2str(section.name)
+        section_type = section["sh_type"]
+        for i, name_and_type in enumerate(name_type_pairs):
+            if name_and_type != (section_name, section_type):
+                continue
+            if sections[i] is not None:
+                raise Exception("Elf contains duplicate section %s attr %s" %
+                                (section_name, section_type))
+            sections[i] = section
+    return sections
+
+
+def _algo_fill_zi_if_missing(ro_rw_zi):
+    """Create an empty zi section if it is missing"""
+    s_ro, s_rw, s_zi = ro_rw_zi
+    if s_rw is None:
+        return ro_rw_zi
+    if s_zi is not None:
+        return ro_rw_zi
+    s_zi = {
+        "sh_addr": s_rw["sh_addr"] + s_rw["sh_size"],
+        "sh_size": 0
+    }
+    return s_ro, s_rw, s_zi
+
+
+def _algo_check_for_section_problems(ro_rw_zi):
+    """Return a string describing any errors with the layout or None if good"""
+    s_ro, s_rw, s_zi = ro_rw_zi
+    if s_ro is None:
+        return "RO section is missing"
+    if s_rw is None:
+        return "RW section is missing"
+    if s_zi is None:
+        return "ZI section is missing"
+    if s_ro["sh_addr"] != 0:
+        return "RO section does not start at address 0"
+    if s_ro["sh_addr"] + s_ro["sh_size"] != s_rw["sh_addr"]:
+        return "RW section does not follow RO section"
+    if s_rw["sh_addr"] + s_rw["sh_size"] != s_zi["sh_addr"]:
+        return "ZI section does not follow RW section"
+    return None
+
+
+def _create_algo_bin(ro_rw_zi):
+    """Create a binary blob of the flash algo which can execute from ram"""
+    sect_ro, sect_rw, sect_zi = ro_rw_zi
+    algo_size = sect_ro["sh_size"] + sect_rw["sh_size"] + sect_zi["sh_size"]
+    algo_data = bytearray(algo_size)
+    for section in (sect_ro, sect_rw):
+        start = section["sh_addr"]
+        size = section["sh_size"]
+        data = section.data()
+        assert len(data) == size
+        algo_data[start:start + size] = data
+    return algo_data
+
+
+class PackFlashInfo(object):
+    """Wrapper class for the non-executable information in an FLM file"""
+
+    FLASH_DEVICE_STRUCT = "<H128sHLLLLBxxxLL"
+    FLASH_SECTORS_STRUCT = "<LL"
+    FLASH_SECTORS_STRUCT_SIZE = struct.calcsize(FLASH_SECTORS_STRUCT)
+    SECTOR_END = 0xFFFFFFFF
+
+    def __init__(self, elf_simple):
+        dev_info = elf_simple.symbols["FlashDevice"]
+        info_start = dev_info.value
+        info_size = struct.calcsize(self.FLASH_DEVICE_STRUCT)
+        data = elf_simple.read(info_start, info_size)
+        values = struct.unpack(self.FLASH_DEVICE_STRUCT, data)
+
+        self.version = values[0]
+        self.name = values[1].strip("\x00")
+        self.type = values[2]
+        self.start = values[3]
+        self.size = values[4]
+        self.page_size = values[5]
+        self.value_empty = values[7]
+        self.prog_timeout_ms = values[8]
+        self.erase_timeout_ms = values[9]
+
+        sector_gen = self._sector_and_sz_itr(elf_simple,
+                                             info_start + info_size)
+        self.sector_info_list = list(sector_gen)
+
+    def __str__(self):
+        desc = ""
+        desc += "Flash Device:" + os.linesep
+        desc += "  name=%s" % self.name + os.linesep
+        desc += "  version=0x%x" % self.version + os.linesep
+        desc += "  type=%i" % self.type + os.linesep
+        desc += "  start=0x%x" % self.start + os.linesep
+        desc += "  size=0x%x" % self.size + os.linesep
+        desc += "  page_size=0x%x" % self.page_size + os.linesep
+        desc += "  value_empty=0x%x" % self.value_empty + os.linesep
+        desc += "  prog_timeout_ms=%i" % self.prog_timeout_ms + os.linesep
+        desc += "  erase_timeout_ms=%i" % self.erase_timeout_ms + os.linesep
+        desc += "  sectors:" + os.linesep
+        for sector_start, sector_size in self.sector_info_list:
+            desc += ("    start=0x%x, size=0x%x" %
+                     (sector_start, sector_size) + os.linesep)
+        return desc
+
+    def _sector_and_sz_itr(self, elf_simple, data_start):
+        """Iterator which returns starting address and sector size"""
+        for entry_start in count(data_start, self.FLASH_SECTORS_STRUCT_SIZE):
+            data = elf_simple.read(entry_start, self.FLASH_SECTORS_STRUCT_SIZE)
+            size, start = struct.unpack(self.FLASH_SECTORS_STRUCT, data)
+            start_and_size = start, size
+            if start_and_size == (self.SECTOR_END, self.SECTOR_END):
+                return
+            yield start_and_size
+
+
+SymbolSimple = namedtuple("SymbolSimple", "name, value, size")
+
+
+class ElfFileSimple(ELFFile):
+    """Wrapper for elf object which allows easy access to symbols and rom"""
+
+    def __init__(self, data):
+        """Construct a ElfFileSimple from bytes or a bytearray"""
+        super(ElfFileSimple, self).__init__(StringIO.StringIO(data))
+        self.symbols = self._read_symbol_table()
+
+    def _read_symbol_table(self):
+        """Read the symbol table into the field "symbols" for easy use"""
+        section = self.get_section_by_name(b".symtab")
+        if not section:
+            raise Exception("Missing symbol table")
+
+        if not isinstance(section, SymbolTableSection):
+            raise Exception("Invalid symbol table section")
+
+        symbols = {}
+        for symbol in section.iter_symbols():
+            name_str = bytes2str(symbol.name)
+            if name_str in symbols:
+                logging.debug("Duplicate symbol %s", name_str)
+            symbols[name_str] = SymbolSimple(name_str, symbol["st_value"],
+                                             symbol["st_size"])
+        return symbols
+
+    def read(self, addr, size):
+        """Read program data from the elf file
+
+        :param addr: physical address (load address) to read from
+        :param size: number of bytes to read
+        :return: Requested data or None if address is unmapped
+        """
+        for segment in self.iter_segments():
+            seg_addr = segment["p_paddr"]
+            seg_size = min(segment["p_memsz"], segment["p_filesz"])
+            if addr >= seg_addr + seg_size:
+                continue
+            if addr + size <= seg_addr:
+                continue
+            # There is at least some overlap
+
+            if addr >= seg_addr and addr + size <= seg_addr + seg_size:
+                # Region is fully contained
+                data = segment.data()
+                start = addr - seg_addr
+                return data[start:start + size]
+
+
+if __name__ == '__main__':
+    main()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/get_config.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/get_config.py
new file mode 100755
index 0000000..ceda6d5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/get_config.py
@@ -0,0 +1,92 @@
+#! /usr/bin/env python2
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+"""
+import sys
+from os.path import isdir, abspath, dirname, join
+from os import _exit
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.utils import args_error
+from tools.options import get_default_options_parser
+from tools.options import extract_mcus
+from tools.build_api import get_config
+from config import Config
+from utils import argparse_filestring_type
+try:
+    import tools.private_settings as ps
+except:
+    ps = object()
+
+if __name__ == '__main__':
+    # Parse Options
+    parser = get_default_options_parser(add_clean=False, add_options=False)
+    parser.add_argument("--source", dest="source_dir", type=argparse_filestring_type, required=True,
+                        default=[], help="The source (input) directory", action="append")
+    parser.add_argument("--prefix", dest="prefix", action="append",
+                      default=[], help="Restrict listing to parameters that have this prefix")
+    parser.add_argument("-v", "--verbose", action="store_true", dest="verbose",
+                      default=False, help="Verbose diagnostic output")
+
+    options = parser.parse_args()
+
+    # Target
+    if options.mcu is None :
+        args_error(parser, "argument -m/--mcu is required")
+    target = extract_mcus(parser, options)[0]
+
+    # Toolchain
+    if options.tool is None:
+        args_error(parser, "argument -t/--toolchain is required")
+    toolchain = options.tool[0]
+
+    options.prefix = options.prefix or [""]
+
+    try:
+        params, macros, features = get_config(options.source_dir, target, toolchain)
+        if not params and not macros:
+            print "No configuration data available."
+            _exit(0)
+        if params:
+            print "Configuration parameters"
+            print "------------------------"
+            for p in sorted(params):
+                for s in options.prefix:
+                    if p.startswith(s):
+                        print(str(params[p]) if not options.verbose else params[p].get_verbose_description())
+                        break
+            print ""
+
+        print "Macros"
+        print "------"
+        if macros:
+            print 'Defined with "macros":', Config.config_macros_to_macros(macros)
+        print "Generated from configuration parameters:", Config.parameters_to_macros(params)
+
+    except KeyboardInterrupt, e:
+        print "\n[CTRL+c] exit"
+    except Exception,e:
+        if options.verbose:
+            import traceback
+            traceback.print_exc(file=sys.stdout)
+        else:
+            print "[ERROR] %s" % str(e)
+
+        sys.exit(1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/git_hooks/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/git_hooks/__init__.py
new file mode 100755
index 0000000..e69de29
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/git_hooks/find_duplicates.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/git_hooks/find_duplicates.py
new file mode 100755
index 0000000..4053199
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/git_hooks/find_duplicates.py
@@ -0,0 +1,26 @@
+from os import walk
+from os.path import join, abspath, dirname, basename, splitext
+import sys
+
+ROOT = abspath(join(dirname(__file__), "..", ".."))
+sys.path.insert(0, ROOT)
+
+from tools.toolchains.gcc import GCC_ARM
+from tools.targets import TARGET_MAP
+from argparse import ArgumentParser
+
+if __name__ == "__main__":
+    parser = ArgumentParser("Find duplicate file names within a directory structure")
+    parser.add_argument("dirs", help="Directories to search for duplicate file names"
+                        , nargs="*")
+    parser.add_argument("--silent", help="Supress printing of filenames, just return number of duplicates", action="store_true")
+    args = parser.parse_args()
+
+    toolchain = GCC_ARM(TARGET_MAP["K64F"])
+
+    resources = sum([toolchain.scan_resources(d) for d in args.dirs], None)
+
+    scanned_files = {}
+
+    exit(resources.detect_duplicates(toolchain))
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/hooks.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/hooks.py
new file mode 100755
index 0000000..ad1a32d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/hooks.py
@@ -0,0 +1,214 @@
+""" Configurable hooks in the build system. Can be used by various platforms
+to customize the build process.
+"""
+
+################################################################################
+# Hooks for the various parts of the build process
+
+# Internal mapping of hooks per tool
+_HOOKS = {}
+
+# Internal mapping of running hooks
+_RUNNING_HOOKS = {}
+
+# Available hook types
+_HOOK_TYPES = ["binary", "compile", "link", "assemble"]
+
+# Available hook steps
+_HOOK_STEPS = ["pre", "replace", "post"]
+
+# Hook the given function. Use this function as a decorator
+def hook_tool(function):
+    """Decorate a function as a tool that may be hooked"""
+    tool = function.__name__
+    tool_flag = "_" + tool + "_done"
+    def wrapper(t_self, *args, **kwargs):
+        """The hooked function itself"""
+        # if a hook for this tool is already running, it's most likely
+        # coming from a derived class, so don't hook the super class version
+        if _RUNNING_HOOKS.get(tool, False):
+            return function(t_self, *args, **kwargs)
+        _RUNNING_HOOKS[tool] = True
+        # If this tool isn't hooked, return original function
+        if not _HOOKS.has_key(tool):
+            res = function(t_self, *args, **kwargs)
+            _RUNNING_HOOKS[tool] = False
+            return res
+        tooldesc = _HOOKS[tool]
+        setattr(t_self, tool_flag, False)
+        # If there is a replace hook, execute the replacement instead
+        if tooldesc.has_key("replace"):
+            res = tooldesc["replace"](t_self, *args, **kwargs)
+        # If the replacement has set the "done" flag, exit now
+        # Otherwise continue as usual
+        if getattr(t_self, tool_flag, False):
+            _RUNNING_HOOKS[tool] = False
+            return res
+        # Execute pre-function before main function if specified
+        if tooldesc.has_key("pre"):
+            tooldesc["pre"](t_self, *args, **kwargs)
+        # Execute the main function now
+        res = function(t_self, *args, **kwargs)
+        # Execute post-function after main function if specified
+        if tooldesc.has_key("post"):
+            post_res = tooldesc["post"](t_self, *args, **kwargs)
+            _RUNNING_HOOKS[tool] = False
+            return post_res or res
+        else:
+            _RUNNING_HOOKS[tool] = False
+            return res
+    return wrapper
+
+class Hook(object):
+    """A compiler class that may be hooked"""
+    def __init__(self, target, toolchain):
+        _HOOKS.clear()
+        self._cmdline_hooks = {}
+        self.toolchain = toolchain
+        target.init_hooks(self, toolchain)
+
+    # Hook various functions directly
+    @staticmethod
+    def _hook_add(hook_type, hook_step, function):
+        """Add a hook to a compile function
+
+        Positional arguments:
+        hook_type - one of the _HOOK_TYPES
+        hook_step - one of the _HOOK_STEPS
+        function - the function to add to the list of hooks
+        """
+        if hook_type not in _HOOK_TYPES or hook_step not in _HOOK_STEPS:
+            return False
+        if hook_type not in _HOOKS:
+            _HOOKS[hook_type] = {}
+        _HOOKS[hook_type][hook_step] = function
+        return True
+
+    def hook_add_compiler(self, hook_step, function):
+        """Add a hook to the compiler
+
+        Positional Arguments:
+        hook_step - one of the _HOOK_STEPS
+        function - the function to add to the list of hooks
+        """
+        return self._hook_add("compile", hook_step, function)
+
+    def hook_add_linker(self, hook_step, function):
+        """Add a hook to the linker
+
+        Positional Arguments:
+        hook_step - one of the _HOOK_STEPS
+        function - the function to add to the list of hooks
+        """
+        return self._hook_add("link", hook_step, function)
+
+    def hook_add_assembler(self, hook_step, function):
+        """Add a hook to the assemble
+
+        Positional Arguments:
+        hook_step - one of the _HOOK_STEPS
+        function - the function to add to the list of hooks
+        """
+        return self._hook_add("assemble", hook_step, function)
+
+    def hook_add_binary(self, hook_step, function):
+        """Add a hook to the elf to binary tool
+
+        Positional Arguments:
+        hook_step - one of the _HOOK_STEPS
+        function - the function to add to the list of hooks
+        """
+        return self._hook_add("binary", hook_step, function)
+
+    # Hook command lines
+    def _hook_cmdline(self, hook_type, function):
+        """Add a hook to a command line function
+
+        Positional arguments:
+        hook_type - one of the _HOOK_TYPES
+        function - the function to add to the list of hooks
+        """
+        if hook_type not in _HOOK_TYPES:
+            return False
+        self._cmdline_hooks[hook_type] = function
+        return True
+
+    def hook_cmdline_compiler(self, function):
+        """Add a hook to the compiler command line
+
+        Positional arguments:
+        function - the function to call
+        """
+        return self._hook_cmdline("compile", function)
+
+    def hook_cmdline_linker(self, function):
+        """Add a hook to the linker command line
+
+        Positional arguments:
+        function - the function to call
+        """
+        return self._hook_cmdline("link", function)
+
+    def hook_cmdline_assembler(self, function):
+        """Add a hook to the assembler command line
+
+        Positional arguments:
+        function - the function to call
+        """
+        return self._hook_cmdline("assemble", function)
+
+    def hook_cmdline_binary(self, function):
+        """Add a hook to the elf to bin tool command line
+
+        Positional arguments:
+        function - the function to call
+        """
+        return self._hook_cmdline("binary", function)
+
+    # Return the command line after applying the hook
+    def _get_cmdline(self, hook_type, cmdline):
+        """Get the command line after running all hooks
+
+        Positional arguments:
+        hook_type - one of the _HOOK_TYPES
+        cmdline - the initial command line
+        """
+        if self._cmdline_hooks.has_key(hook_type):
+            cmdline = self._cmdline_hooks[hook_type](
+                self.toolchain.__class__.__name__, cmdline)
+        return cmdline
+
+    def get_cmdline_compiler(self, cmdline):
+        """Get the compiler command line after running all hooks
+
+        Positional arguments:
+        cmdline - the initial command line
+        """
+        return self._get_cmdline("compile", cmdline)
+
+    def get_cmdline_linker(self, cmdline):
+        """Get the linker command line after running all hooks
+
+        Positional arguments:
+        cmdline - the initial command line
+        """
+        return self._get_cmdline("link", cmdline)
+
+    def get_cmdline_assembler(self, cmdline):
+        """Get the assmebler command line after running all hooks
+
+        Positional arguments:
+        cmdline - the initial command line
+        """
+        return self._get_cmdline("assemble", cmdline)
+
+    def get_cmdline_binary(self, cmdline):
+        """Get the binary command line after running all hooks
+
+        Positional arguments:
+        cmdline - the initial command line
+        """
+        return self._get_cmdline("binary", cmdline)
+
+################################################################################
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/hooks.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/hooks.pyc
new file mode 100755
index 0000000..a2a0f9f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/hooks.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/__init__.py
new file mode 100755
index 0000000..eab2a21
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/__init__.py
@@ -0,0 +1,67 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from host_registry import HostRegistry
+
+# Host test supervisors
+from echo import EchoTest
+from rtc_auto import RTCTest
+from stdio_auto import StdioTest
+from hello_auto import HelloTest
+from detect_auto import DetectPlatformTest
+from default_auto import DefaultAuto
+from dev_null_auto import DevNullTest
+from wait_us_auto import WaitusTest
+from tcpecho_server_auto import TCPEchoServerTest
+from udpecho_server_auto import UDPEchoServerTest
+from tcpecho_client_auto import TCPEchoClientTest
+from udpecho_client_auto import UDPEchoClientTest
+from wfi_auto import WFITest
+from serial_nc_rx_auto import SerialNCRXTest
+from serial_nc_tx_auto import SerialNCTXTest
+from serial_complete_auto import SerialCompleteTest
+
+# Populate registry with supervising objects
+HOSTREGISTRY = HostRegistry()
+HOSTREGISTRY.register_host_test("echo", EchoTest())
+HOSTREGISTRY.register_host_test("default", DefaultAuto())
+HOSTREGISTRY.register_host_test("rtc_auto", RTCTest())
+HOSTREGISTRY.register_host_test("hello_auto", HelloTest())
+HOSTREGISTRY.register_host_test("stdio_auto", StdioTest())
+HOSTREGISTRY.register_host_test("detect_auto", DetectPlatformTest())
+HOSTREGISTRY.register_host_test("default_auto", DefaultAuto())
+HOSTREGISTRY.register_host_test("wait_us_auto", WaitusTest())
+HOSTREGISTRY.register_host_test("dev_null_auto", DevNullTest())
+HOSTREGISTRY.register_host_test("tcpecho_server_auto", TCPEchoServerTest())
+HOSTREGISTRY.register_host_test("udpecho_server_auto", UDPEchoServerTest())
+HOSTREGISTRY.register_host_test("tcpecho_client_auto", TCPEchoClientTest())
+HOSTREGISTRY.register_host_test("udpecho_client_auto", UDPEchoClientTest())
+HOSTREGISTRY.register_host_test("wfi_auto", WFITest())
+HOSTREGISTRY.register_host_test("serial_nc_rx_auto", SerialNCRXTest())
+HOSTREGISTRY.register_host_test("serial_nc_tx_auto", SerialNCTXTest())
+HOSTREGISTRY.register_host_test("serial_complete_auto", SerialCompleteTest())
+
+###############################################################################
+# Functional interface for test supervisor registry
+###############################################################################
+
+
+def get_host_test(ht_name):
+    return HOSTREGISTRY.get_host_test(ht_name)
+
+def is_host_test(ht_name):
+    return HOSTREGISTRY.is_host_test(ht_name)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/default_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/default_auto.py
new file mode 100755
index 0000000..0883d79
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/default_auto.py
@@ -0,0 +1,36 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from sys import stdout
+
+class DefaultAuto():
+    """ Simple, basic host test's test runner waiting for serial port
+        output from MUT, no supervision over test running in MUT is executed.
+    """
+    def test(self, selftest):
+        result = selftest.RESULT_SUCCESS
+        try:
+            while True:
+                c = selftest.mbed.serial_read(512)
+                if c is None:
+                    return selftest.RESULT_IO_SERIAL
+                stdout.write(c)
+                stdout.flush()
+        except KeyboardInterrupt, _:
+            selftest.notify("\r\n[CTRL+C] exit")
+            result = selftest.RESULT_ERROR
+        return result
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/detect_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/detect_auto.py
new file mode 100755
index 0000000..2999946
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/detect_auto.py
@@ -0,0 +1,55 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+
+class DetectPlatformTest():
+    PATTERN_MICRO_NAME = "Target '(\w+)'"
+    re_detect_micro_name = re.compile(PATTERN_MICRO_NAME)
+
+    def test(self, selftest):
+        result = True
+
+        c = selftest.mbed.serial_readline() # {{start}} preamble
+        if c is None:
+           return selftest.RESULT_IO_SERIAL
+
+        selftest.notify(c.strip())
+        selftest.notify("HOST: Detecting target name...")
+
+        c = selftest.mbed.serial_readline()
+        if c is None:
+            return selftest.RESULT_IO_SERIAL
+        selftest.notify(c.strip())
+
+        # Check for target name
+        m = self.re_detect_micro_name.search(c)
+        if m and len(m.groups()):
+            micro_name = m.groups()[0]
+            micro_cmp = selftest.mbed.options.micro == micro_name
+            result = result and micro_cmp
+            selftest.notify("HOST: MUT Target name '%s', expected '%s'... [%s]"% (micro_name,
+                selftest.mbed.options.micro,
+                "OK" if micro_cmp else "FAIL"))
+
+        for i in range(0, 2):
+            c = selftest.mbed.serial_readline()
+            if c is None:
+               return selftest.RESULT_IO_SERIAL
+            selftest.notify(c.strip())
+
+        return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/dev_null_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/dev_null_auto.py
new file mode 100755
index 0000000..4538f6d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/dev_null_auto.py
@@ -0,0 +1,50 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+class DevNullTest():
+
+    def check_readline(self, selftest, text):
+        """ Reads line from serial port and checks if text was part of read string
+        """
+        result = False
+        c = selftest.mbed.serial_readline()
+        if c and text in c:
+            result = True
+        return result
+
+    def test(self, selftest):
+        result = True
+        # Test should print some text and later stop printing
+        # 'MBED: re-routing stdout to /null'
+        res = self.check_readline(selftest, "re-routing stdout to /null")
+        if not res:
+            # We haven't read preamble line
+            result = False
+        else:
+            # Check if there are printed characters
+            str = ''
+            for i in range(3):
+                c = selftest.mbed.serial_read(32)
+                if c is None:
+                    return selftest.RESULT_IO_SERIAL
+                else:
+                    str += c
+                if len(str) > 0:
+                    result = False
+                    break
+            selftest.notify("Received %d bytes: %s"% (len(str), str))
+        return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/echo.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/echo.py
new file mode 100755
index 0000000..75e534f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/echo.py
@@ -0,0 +1,59 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import uuid
+from sys import stdout
+
+class EchoTest():
+
+    # Test parameters
+    TEST_SERIAL_BAUDRATE = 115200
+    TEST_LOOP_COUNT = 50
+
+    def test(self, selftest):
+        """ This host test will use mbed serial port with
+            baudrate 115200 to perform echo test on that port.
+        """
+        # Custom initialization for echo test
+        selftest.mbed.init_serial_params(serial_baud=self.TEST_SERIAL_BAUDRATE)
+        selftest.mbed.init_serial()
+
+        # Test function, return True or False to get standard test notification on stdout
+        selftest.mbed.flush()
+        selftest.notify("HOST: Starting the ECHO test")
+        result = True
+        
+        """ This ensures that there are no parasites left in the serial buffer.
+        """
+        for i in range(0, 2):
+            selftest.mbed.serial_write("\n")
+            c = selftest.mbed.serial_readline()
+            
+        for i in range(0, self.TEST_LOOP_COUNT):
+            TEST_STRING = str(uuid.uuid4()) + "\n"
+            selftest.mbed.serial_write(TEST_STRING)
+            c = selftest.mbed.serial_readline()
+            if c is None:
+                return selftest.RESULT_IO_SERIAL
+            if c.strip() != TEST_STRING.strip():
+                selftest.notify('HOST: "%s" != "%s"'% (c, TEST_STRING))
+                result = False
+            else:
+                sys.stdout.write('.')
+                stdout.flush()
+        return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/echo_flow_control.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/echo_flow_control.py
new file mode 100755
index 0000000..7ea11e9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/echo_flow_control.py
@@ -0,0 +1,48 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from host_test import Test
+
+
+class EchoTest(Test):
+    def __init__(self):
+        Test.__init__(self)
+        self.mbed.init_serial()
+        self.mbed.extra_serial.rtscts = True
+        self.mbed.reset()
+
+    def test(self):
+        self.mbed.flush()
+        self.notify("Starting the ECHO test")
+        TEST="longer serial test"
+        check = True
+        for i in range(1, 100):
+            self.mbed.extra_serial.write(TEST + "\n")
+            l = self.mbed.extra_serial.readline().strip()
+            if not l: continue
+
+            if l != TEST:
+                check = False
+                self.notify('"%s" != "%s"' % (l, TEST))
+            else:
+                if (i % 10) == 0:
+                    self.notify('.')
+
+        return check
+
+
+if __name__ == '__main__':
+    EchoTest().run()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/BroadcastReceive.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/BroadcastReceive.py
new file mode 100755
index 0000000..2e846ca
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/BroadcastReceive.py
@@ -0,0 +1,25 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+
+BROADCAST_PORT = 58083
+
+s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+s.bind(('0.0.0.0', BROADCAST_PORT))
+
+while True:
+    print s.recvfrom(256)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/BroadcastSend.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/BroadcastSend.py
new file mode 100755
index 0000000..0a5f8c3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/BroadcastSend.py
@@ -0,0 +1,30 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+from time import sleep, time
+
+BROADCAST_PORT = 58083
+
+s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+s.bind(('', 0))
+s.setsockopt(socket.SOL_SOCKET, socket.SO_BROADCAST, 1)
+
+while True:
+    print "Broadcasting..."
+    data = 'Hello World: ' + repr(time()) + '\n'
+    s.sendto(data, ('<broadcast>', BROADCAST_PORT))
+    sleep(1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/MulticastReceive.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/MulticastReceive.py
new file mode 100755
index 0000000..9001f40
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/MulticastReceive.py
@@ -0,0 +1,31 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+import struct
+
+MCAST_GRP = '224.1.1.1'
+MCAST_PORT = 5007
+
+sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM, socket.IPPROTO_UDP)
+sock.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1)
+sock.bind(('', MCAST_PORT))
+mreq = struct.pack("4sl", socket.inet_aton(MCAST_GRP), socket.INADDR_ANY)
+
+sock.setsockopt(socket.IPPROTO_IP, socket.IP_ADD_MEMBERSHIP, mreq)
+
+while True:
+    print sock.recv(10240)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/MulticastSend.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/MulticastSend.py
new file mode 100755
index 0000000..8efd453
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/MulticastSend.py
@@ -0,0 +1,30 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+from time import sleep, time
+
+MCAST_GRP = '224.1.1.1'
+MCAST_PORT = 5007
+
+sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM, socket.IPPROTO_UDP)
+sock.setsockopt(socket.IPPROTO_IP, socket.IP_MULTICAST_TTL, 2)
+
+while True:
+    print "Multicast to group: %s\n" % MCAST_GRP
+    data = 'Hello World: ' + repr(time()) + '\n'
+    sock.sendto(data, (MCAST_GRP, MCAST_PORT))
+    sleep(1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/TCPEchoClient.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/TCPEchoClient.py
new file mode 100755
index 0000000..dfa9bfd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/TCPEchoClient.py
@@ -0,0 +1,28 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+
+ECHO_SERVER_ADDRESS = "10.2.202.45"
+ECHO_PORT = 7
+
+s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+s.connect((ECHO_SERVER_ADDRESS, ECHO_PORT))
+
+s.sendall('Hello, world')
+data = s.recv(1024)
+s.close()
+print 'Received', repr(data)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/TCPEchoServer.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/TCPEchoServer.py
new file mode 100755
index 0000000..1324edb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/TCPEchoServer.py
@@ -0,0 +1,30 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+
+s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+s.bind(('', 7))
+s.listen(1)
+
+while True:
+    conn, addr = s.accept()
+    print 'Connected by', addr
+    while True:
+        data = conn.recv(1024)
+        if not data: break
+        conn.sendall(data)
+    conn.close()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/UDPEchoClient.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/UDPEchoClient.py
new file mode 100755
index 0000000..6a6cf8c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/UDPEchoClient.py
@@ -0,0 +1,28 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+
+ECHO_SERVER_ADDRESS = '10.2.202.45'
+ECHO_PORT = 7
+
+sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+
+sock.sendto("Hello World\n", (ECHO_SERVER_ADDRESS, ECHO_PORT))
+response = sock.recv(256)
+sock.close()
+
+print response
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/UDPEchoServer.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/UDPEchoServer.py
new file mode 100755
index 0000000..3850348
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/UDPEchoServer.py
@@ -0,0 +1,27 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+
+ECHO_PORT = 7
+
+sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+sock.bind(('', ECHO_PORT))
+
+while True:
+    data, address = sock.recvfrom(256)
+    print "datagram from", address
+    sock.sendto(data, address)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/__init__.py
new file mode 100755
index 0000000..10e7e1d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/example/__init__.py
@@ -0,0 +1,16 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/hello_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/hello_auto.py
new file mode 100755
index 0000000..69b39bf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/hello_auto.py
@@ -0,0 +1,34 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+class HelloTest():
+    HELLO_WORLD = "Hello World"
+
+    def test(self, selftest):
+        c = selftest.mbed.serial_readline()
+        if c is None:
+           return selftest.RESULT_IO_SERIAL
+        selftest.notify("Read %d bytes:"% len(c))
+        selftest.notify(c.strip())
+
+        result = True
+        # Because we can have targetID here let's try to decode
+        if len(c) < len(self.HELLO_WORLD):
+            result = False
+        else:
+            result = self.HELLO_WORLD in c
+        return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_registry.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_registry.py
new file mode 100755
index 0000000..d523848
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_registry.py
@@ -0,0 +1,36 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+class HostRegistry:
+    """ Class stores registry with host tests and objects representing them
+    """ 
+    HOST_TESTS = {} # host_test_name -> host_test_ojbect
+
+    def register_host_test(self, ht_name, ht_object):
+        if ht_name not in self.HOST_TESTS:
+            self.HOST_TESTS[ht_name] = ht_object
+    
+    def unregister_host_test(self):
+        if ht_name in HOST_TESTS:
+            self.HOST_TESTS[ht_name] = None
+
+    def get_host_test(self, ht_name):
+        return self.HOST_TESTS[ht_name] if ht_name in self.HOST_TESTS else None
+
+    def is_host_test(self, ht_name):
+        return ht_name in self.HOST_TESTS
+        
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_test.py
new file mode 100755
index 0000000..fe611cb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_test.py
@@ -0,0 +1,426 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+# Check if 'serial' module is installed
+try:
+    from serial import Serial
+except ImportError, e:
+    print "Error: Can't import 'serial' module: %s"% e
+    exit(-1)
+
+import os
+import re
+import types
+from sys import stdout
+from time import sleep, time
+from optparse import OptionParser
+
+import host_tests_plugins
+
+# This is a little tricky. We need to add upper directory to path so
+# we can find packages we want from the same level as other files do
+import sys
+sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), '../..')))
+from tools.test_api import get_autodetected_MUTS_list
+from tools.test_api import get_module_avail
+
+
+class Mbed:
+    """ Base class for a host driven test
+    """
+    def __init__(self):
+        parser = OptionParser()
+
+        parser.add_option("-m", "--micro",
+                          dest="micro",
+                          help="The target microcontroller",
+                          metavar="MICRO")
+
+        parser.add_option("-p", "--port",
+                          dest="port",
+                          help="The serial port of the target mbed",
+                          metavar="PORT")
+
+        parser.add_option("-d", "--disk",
+                          dest="disk",
+                          help="The target disk path",
+                          metavar="DISK_PATH")
+
+        parser.add_option("-f", "--image-path",
+                          dest="image_path",
+                          help="Path with target's image",
+                          metavar="IMAGE_PATH")
+
+        parser.add_option("-c", "--copy",
+                          dest="copy_method",
+                          help="Copy method selector",
+                          metavar="COPY_METHOD")
+
+        parser.add_option("-C", "--program_cycle_s",
+                          dest="program_cycle_s",
+                          help="Program cycle sleep. Define how many seconds you want wait after copying bianry onto target",
+                          type="float",
+                          metavar="COPY_METHOD")
+
+        parser.add_option("-t", "--timeout",
+                          dest="timeout",
+                          help="Timeout",
+                          metavar="TIMEOUT")
+
+        parser.add_option("-r", "--reset",
+                          dest="forced_reset_type",
+                          help="Forces different type of reset")
+
+        parser.add_option("-R", "--reset-timeout",
+                          dest="forced_reset_timeout",
+                          metavar="NUMBER",
+                          type="int",
+                          help="When forcing a reset using option -r you can set up after reset timeout in seconds")
+
+        parser.add_option('', '--auto',
+                          dest='auto_detect',
+                          metavar=False,
+                          action="store_true",
+                          help='Use mbed-ls module to detect all connected mbed devices')
+
+        (self.options, _) = parser.parse_args()
+
+        self.DEFAULT_RESET_TOUT = 0
+        self.DEFAULT_TOUT = 10
+
+        if self.options.port is None:
+            raise Exception("The serial port of the target mbed have to be provided as command line arguments")
+
+        # Options related to copy / reset mbed device
+        self.port = self.options.port
+        self.disk = self.options.disk
+        self.image_path = self.options.image_path.strip('"')
+        self.copy_method = self.options.copy_method
+        self.program_cycle_s = float(self.options.program_cycle_s)
+
+        self.serial = None
+        self.serial_baud = 9600
+        self.serial_timeout = 1
+
+        self.timeout = self.DEFAULT_TOUT if self.options.timeout is None else self.options.timeout
+        print 'MBED: Instrumentation: "%s" and disk: "%s"' % (self.port, self.disk)
+
+    def init_serial_params(self, serial_baud=9600, serial_timeout=1):
+        """ Initialize port parameters.
+            This parameters will be used by self.init_serial() function to open serial port
+        """
+        self.serial_baud = serial_baud
+        self.serial_timeout = serial_timeout
+
+    def init_serial(self, serial_baud=None, serial_timeout=None):
+        """ Initialize serial port.
+            Function will return error is port can't be opened or initialized
+        """
+        # Overload serial port configuration from default to parameters' values if they are specified
+        serial_baud = serial_baud if serial_baud is not None else self.serial_baud
+        serial_timeout = serial_timeout if serial_timeout is not None else self.serial_timeout
+
+        if get_module_avail('mbed_lstools') and self.options.auto_detect:
+            # Ensure serial port is up-to-date (try to find it 60 times)
+            found = False
+
+            for i in range(0, 60):
+                print('Looking for %s with MBEDLS' % self.options.micro)
+                muts_list = get_autodetected_MUTS_list(platform_name_filter=[self.options.micro])
+
+                if 1 in muts_list:
+                    mut = muts_list[1]
+                    self.port = mut['port']
+                    found = True
+                    break
+                else:
+                    sleep(3)
+
+            if not found:
+                return False
+
+        # Clear serial port
+        if self.serial:
+            self.serial.close()
+            self.serial = None
+
+        # We will pool for serial to be re-mounted if it was unmounted after device reset
+        result = self.pool_for_serial_init(serial_baud, serial_timeout) # Blocking
+
+        # Port can be opened
+        if result:
+            self.flush()
+        return result
+
+    def pool_for_serial_init(self, serial_baud, serial_timeout, pooling_loops=40, init_delay=0.5, loop_delay=0.25):
+        """ Functions pools for serial port readiness
+        """
+        result = True
+        last_error = None
+        # This loop is used to check for serial port availability due to
+        # some delays and remounting when devices are being flashed with new software.
+        for i in range(pooling_loops):
+            sleep(loop_delay if i else init_delay)
+            try:
+                self.serial = Serial(self.port, baudrate=serial_baud, timeout=serial_timeout)
+            except Exception as e:
+                result = False
+                last_error = "MBED: %s"% str(e)
+                stdout.write('.')
+                stdout.flush()
+            else:
+                print "...port ready!"
+                result = True
+                break
+        if not result and last_error:
+            print last_error
+        return result
+
+    def set_serial_timeout(self, timeout):
+        """ Wraps self.mbed.serial object timeout property
+        """
+        result = None
+        if self.serial:
+            self.serial.timeout = timeout
+            result = True
+        return result
+
+    def serial_read(self, count=1):
+        """ Wraps self.mbed.serial object read method
+        """
+        result = None
+        if self.serial:
+            try:
+                result = self.serial.read(count)
+            except:
+                result = None
+        return result
+
+    def serial_readline(self, timeout=5):
+        """ Wraps self.mbed.serial object read method to read one line from serial port
+        """
+        result = ''
+        start = time()
+        while (time() - start) < timeout:
+            if self.serial:
+                try:
+                    c = self.serial.read(1)
+                    result += c
+                except Exception as e:
+                    print "MBED: %s"% str(e)
+                    result = None
+                    break
+                if c == '\n':
+                    break
+        return result
+
+    def serial_write(self, write_buffer):
+        """ Wraps self.mbed.serial object write method
+        """
+        result = None
+        if self.serial:
+            try:
+                result = self.serial.write(write_buffer)
+            except:
+               result = None
+        return result
+
+    def reset_timeout(self, timeout):
+        """ Timeout executed just after reset command is issued
+        """
+        for n in range(0, timeout):
+            sleep(1)
+
+    def reset(self):
+        """ Calls proper reset plugin to do the job.
+            Please refer to host_test_plugins functionality
+        """
+        # Flush serials to get only input after reset
+        self.flush()
+        if self.options.forced_reset_type:
+            result = host_tests_plugins.call_plugin('ResetMethod', self.options.forced_reset_type, disk=self.disk)
+        else:
+            result = host_tests_plugins.call_plugin('ResetMethod', 'default', serial=self.serial)
+        # Give time to wait for the image loading
+        reset_tout_s = self.options.forced_reset_timeout if self.options.forced_reset_timeout is not None else self.DEFAULT_RESET_TOUT
+        self.reset_timeout(reset_tout_s)
+        return result
+
+    def copy_image(self, image_path=None, disk=None, copy_method=None):
+        """ Closure for copy_image_raw() method.
+            Method which is actually copying image to mbed
+        """
+        # Set closure environment
+        image_path = image_path if image_path is not None else self.image_path
+        disk = disk if disk is not None else self.disk
+        copy_method = copy_method if copy_method is not None else self.copy_method
+        # Call proper copy method
+        result = self.copy_image_raw(image_path, disk, copy_method)
+        return result
+
+    def copy_image_raw(self, image_path=None, disk=None, copy_method=None):
+        """ Copy file depending on method you want to use. Handles exception
+            and return code from shell copy commands.
+        """
+        # image_path - Where is binary with target's firmware
+        if copy_method is not None:
+            # We override 'default' method with 'shell' method
+            if copy_method == 'default':
+                copy_method = 'shell'
+        else:
+            copy_method = 'shell'
+
+        result = host_tests_plugins.call_plugin('CopyMethod', copy_method, image_path=image_path, destination_disk=disk, program_cycle_s=self.program_cycle_s, target_mcu=self.options.micro)
+        return result;
+
+    def flush(self):
+        """ Flush serial ports
+        """
+        result = False
+        if self.serial:
+            self.serial.flushInput()
+            self.serial.flushOutput()
+            result = True
+        return result
+
+
+class HostTestResults:
+    """ Test results set by host tests
+    """
+    def __init__(self):
+        self.RESULT_SUCCESS = 'success'
+        self.RESULT_FAILURE = 'failure'
+        self.RESULT_ERROR = 'error'
+        self.RESULT_IO_SERIAL = 'ioerr_serial'
+        self.RESULT_NO_IMAGE = 'no_image'
+        self.RESULT_IOERR_COPY = "ioerr_copy"
+        self.RESULT_PASSIVE = "passive"
+        self.RESULT_NOT_DETECTED = "not_detected"
+        self.RESULT_MBED_ASSERT = "mbed_assert"
+
+
+import tools.host_tests as host_tests
+
+
+class Test(HostTestResults):
+    """ Base class for host test's test runner
+    """
+    # Select default host_test supervision (replaced after autodetection)
+    test_supervisor = host_tests.get_host_test("default")
+
+    def __init__(self):
+        self.mbed = Mbed()
+
+    def detect_test_config(self, verbose=False):
+        """ Detects test case configuration
+        """
+        result = {}
+        while True:
+            line = self.mbed.serial_readline()
+            if "{start}" in line:
+                self.notify("HOST: Start test...")
+                break
+            else:
+                # Detect if this is property from TEST_ENV print
+                m = re.search('{([\w_]+);([\w\d\+ ]+)}}', line[:-1])
+                if m and len(m.groups()) == 2:
+                    # This is most likely auto-detection property
+                    result[m.group(1)] = m.group(2)
+                    if verbose:
+                        self.notify("HOST: Property '%s' = '%s'"% (m.group(1), m.group(2)))
+                else:
+                    # We can check if this is TArget Id in mbed specific format
+                    m2 = re.search('^([\$]+)([a-fA-F0-9]+)', line[:-1])
+                    if m2 and len(m2.groups()) == 2:
+                        if verbose:
+                            target_id = m2.group(1) + m2.group(2)
+                            self.notify("HOST: TargetID '%s'"% target_id)
+                            self.notify(line[len(target_id):-1])
+                    else:
+                        self.notify("HOST: Unknown property: %s"% line.strip())
+        return result
+
+    def run(self):
+        """ Test runner for host test. This function will start executing
+            test and forward test result via serial port to test suite
+        """
+        # Copy image to device
+        self.notify("HOST: Copy image onto target...")
+        result = self.mbed.copy_image()
+        if not result:
+            self.print_result(self.RESULT_IOERR_COPY)
+
+        # Initialize and open target's serial port (console)
+        self.notify("HOST: Initialize serial port...")
+        result = self.mbed.init_serial()
+        if not result:
+            self.print_result(self.RESULT_IO_SERIAL)
+
+        # Reset device
+        self.notify("HOST: Reset target...")
+        result = self.mbed.reset()
+        if not result:
+            self.print_result(self.RESULT_IO_SERIAL)
+
+        # Run test
+        try:
+            CONFIG = self.detect_test_config(verbose=True) # print CONFIG
+
+            if "host_test_name" in CONFIG:
+                if host_tests.is_host_test(CONFIG["host_test_name"]):
+                    self.test_supervisor = host_tests.get_host_test(CONFIG["host_test_name"])
+            result = self.test_supervisor.test(self)    #result = self.test()
+
+            if result is not None:
+                self.print_result(result)
+            else:
+                self.notify("HOST: Passive mode...")
+        except Exception, e:
+            print str(e)
+            self.print_result(self.RESULT_ERROR)
+
+    def setup(self):
+        """ Setup and check if configuration for test is
+            correct. E.g. if serial port can be opened.
+        """
+        result = True
+        if not self.mbed.serial:
+            result = False
+            self.print_result(self.RESULT_IO_SERIAL)
+        return result
+
+    def notify(self, message):
+        """ On screen notification function
+        """
+        print message
+        stdout.flush()
+
+    def print_result(self, result):
+        """ Test result unified printing function
+        """
+        self.notify("\r\n{{%s}}\r\n{{end}}" % result)
+
+
+class DefaultTestSelector(Test):
+    """ Test class with serial port initialization
+    """
+    def __init__(self):
+        HostTestResults.__init__(self)
+        Test.__init__(self)
+
+if __name__ == '__main__':
+    DefaultTestSelector().run()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/__init__.py
new file mode 100755
index 0000000..c05241a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/__init__.py
@@ -0,0 +1,80 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import host_test_registry
+
+# This plugins provide 'flashing' methods to host test scripts
+import module_copy_mbed
+import module_copy_shell
+import module_copy_silabs
+
+try:
+    import module_copy_smart
+except:
+    pass
+
+#import module_copy_firefox
+import module_copy_mps2
+
+# Plugins used to reset certain platform
+import module_reset_mbed
+import module_reset_silabs
+import module_reset_mps2
+
+
+# Plugin registry instance
+HOST_TEST_PLUGIN_REGISTRY = host_test_registry.HostTestRegistry()
+
+# Static plugin registration
+# Some plugins are commented out if they are not stable or not commonly used
+HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_mbed.load_plugin())
+HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_shell.load_plugin())
+
+try:
+    HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_smart.load_plugin())
+except:
+    pass
+
+HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_reset_mbed.load_plugin())
+#HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_firefox.load_plugin())
+
+# Extra platforms support
+HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_mps2.load_plugin())
+HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_reset_mps2.load_plugin())
+HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_silabs.load_plugin())
+HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_reset_silabs.load_plugin())
+
+# TODO: extend plugin loading to files with name module_*.py loaded ad-hoc
+
+###############################################################################
+# Functional interface for host test plugin registry
+###############################################################################
+def call_plugin(type, capability, *args, **kwargs):
+    """ Interface to call plugin registry functional way
+    """
+    return HOST_TEST_PLUGIN_REGISTRY.call_plugin(type, capability, *args, **kwargs)
+
+def get_plugin_caps(type):
+    """ Returns list of all capabilities for plugin family with the same type.
+        If there are no capabilities empty list is returned
+    """
+    return HOST_TEST_PLUGIN_REGISTRY.get_plugin_caps(type)
+
+def print_plugin_info():
+    """ Prints plugins' information in user friendly way
+    """
+    print HOST_TEST_PLUGIN_REGISTRY
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/host_test_plugins.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/host_test_plugins.py
new file mode 100755
index 0000000..ee60950
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/host_test_plugins.py
@@ -0,0 +1,119 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from os import access, F_OK
+from sys import stdout
+from time import sleep
+from subprocess import call
+
+
+class HostTestPluginBase:
+    """ Base class for all plug-ins used with host tests.
+    """
+    ###########################################################################
+    # Interface:
+    ###########################################################################
+
+    ###########################################################################
+    # Interface attributes defining plugin name, type etc.
+    ###########################################################################
+    name = "HostTestPluginBase" # Plugin name, can be plugin class name
+    type = "BasePlugin"         # Plugin type: ResetMethod, Copymethod etc.
+    capabilities = []           # Capabilities names: what plugin can achieve
+                                # (e.g. reset using some external command line tool)
+    stable = False              # Determine if plugin is stable and can be used
+
+    ###########################################################################
+    # Interface methods
+    ###########################################################################
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        return False
+
+    def execute(self, capabilitity, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability e.g. may directly just call some command line
+            program or execute building pythonic function
+        """
+        return False
+
+    ###########################################################################
+    # Interface helper methods - overload only if you need to have custom behaviour
+    ###########################################################################
+    def print_plugin_error(self, text):
+        """ Function prints error in console and exits always with False
+        """
+        print "Plugin error: %s::%s: %s"% (self.name, self.type, text)
+        return False
+
+    def print_plugin_info(self, text, NL=True):
+        """ Function prints notification in console and exits always with True
+        """
+        if NL:
+            print "Plugin info: %s::%s: %s"% (self.name, self.type, text)
+        else:
+            print "Plugin info: %s::%s: %s"% (self.name, self.type, text),
+        return True
+
+    def print_plugin_char(self, char):
+        """ Function prints char on stdout
+        """
+        stdout.write(char)
+        stdout.flush()
+        return True
+
+    def check_mount_point_ready(self, destination_disk, init_delay=0.2, loop_delay=0.25):
+        """ Checks if destination_disk is ready and can be accessed by e.g. copy commands
+            @init_delay - Initial delay time before first access check
+            @loop_delay - pooling delay for access check
+        """
+        if not access(destination_disk, F_OK):
+            self.print_plugin_info("Waiting for mount point '%s' to be ready..."% destination_disk, NL=False)
+            sleep(init_delay)
+            while not access(destination_disk, F_OK):
+                sleep(loop_delay)
+                self.print_plugin_char('.')
+
+    def check_parameters(self, capabilitity, *args, **kwargs):
+        """ This function should be ran each time we call execute()
+            to check if none of the required parameters is missing.
+        """
+        missing_parameters = []
+        for parameter in self.required_parameters:
+            if parameter not in kwargs:
+                missing_parameters.append(parameter)
+        if len(missing_parameters) > 0:
+            self.print_plugin_error("execute parameter(s) '%s' missing!"% (', '.join(parameter)))
+            return False
+        return True
+
+    def run_command(self, cmd, shell=True):
+        """ Runs command from command line.
+        """
+        result = True
+        ret = 0
+        try:
+            ret = call(cmd, shell=shell)
+            if ret:
+                self.print_plugin_error("[ret=%d] Command: %s"% (int(ret), cmd))
+                return False
+        except Exception as e:
+            result = False
+            self.print_plugin_error("[ret=%d] Command: %s"% (int(ret), cmd))
+            self.print_plugin_error(str(e))
+        return result
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/host_test_registry.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/host_test_registry.py
new file mode 100755
index 0000000..5237b9a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/host_test_registry.py
@@ -0,0 +1,89 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+class HostTestRegistry:
+    """ Simple class used to register and store
+        host test plugins for further usage
+    """
+    # Here we actually store all the plugins
+    PLUGINS = {}    # 'Plugin Name' : Plugin Object
+
+    def print_error(self, text):
+        print "Plugin load failed. Reason: %s"% text
+
+    def register_plugin(self, plugin):
+        """ Registers and stores plugin inside registry for further use.
+            Method also calls plugin's setup() function to configure plugin if needed.
+
+            Note: Different groups of plugins may demand different extra parameter. Plugins
+            should be at least for one type of plugin configured with the same parameters
+            because we do not know which of them will actually use particular parameter.
+        """
+        # TODO:
+        # - check for unique caps for specified type
+        if plugin.name not in self.PLUGINS:
+            if plugin.setup(): # Setup plugin can be completed without errors
+                self.PLUGINS[plugin.name] = plugin
+                return True
+            else:
+                self.print_error("%s setup failed"% plugin.name)
+        else:
+            self.print_error("%s already loaded"% plugin.name)
+        return False
+
+    def call_plugin(self, type, capability, *args, **kwargs):
+        """ Execute plugin functionality respectively to its purpose
+        """
+        for plugin_name in self.PLUGINS:
+            plugin = self.PLUGINS[plugin_name]
+            if plugin.type == type and capability in plugin.capabilities:
+                return plugin.execute(capability, *args, **kwargs)
+        return False
+
+    def get_plugin_caps(self, type):
+        """ Returns list of all capabilities for plugin family with the same type.
+            If there are no capabilities empty list is returned
+        """
+        result = []
+        for plugin_name in self.PLUGINS:
+            plugin = self.PLUGINS[plugin_name]
+            if plugin.type == type:
+                result.extend(plugin.capabilities)
+        return sorted(result)
+
+    def load_plugin(self, name):
+        """ Used to load module from
+        """
+        mod = __import__("module_%s"% name)
+        return mod
+
+    def __str__(self):
+        """ User friendly printing method to show hooked plugins
+        """
+        from prettytable import PrettyTable
+        column_names = ['name', 'type', 'capabilities', 'stable']
+        pt = PrettyTable(column_names)
+        for column in column_names:
+            pt.align[column] =  'l'
+        for plugin_name in sorted(self.PLUGINS.keys()):
+            name  = self.PLUGINS[plugin_name].name
+            type  = self.PLUGINS[plugin_name].type
+            stable = self.PLUGINS[plugin_name].stable
+            capabilities  = ', '.join(self.PLUGINS[plugin_name].capabilities)
+            row = [name, type, capabilities, stable]
+            pt.add_row(row)
+        return pt.get_string()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_firefox.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_firefox.py
new file mode 100755
index 0000000..360835e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_firefox.py
@@ -0,0 +1,76 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from os.path import join, basename
+from host_test_plugins import HostTestPluginBase
+
+
+class HostTestPluginCopyMethod_Firefox(HostTestPluginBase):
+
+    def file_store_firefox(self, file_path, dest_disk):
+        try:
+            from selenium import webdriver
+            profile = webdriver.FirefoxProfile()
+            profile.set_preference('browser.download.folderList', 2) # custom location
+            profile.set_preference('browser.download.manager.showWhenStarting', False)
+            profile.set_preference('browser.download.dir', dest_disk)
+            profile.set_preference('browser.helperApps.neverAsk.saveToDisk', 'application/octet-stream')
+            # Launch browser with profile and get file
+            browser = webdriver.Firefox(profile)
+            browser.get(file_path)
+            browser.close()
+        except:
+            return False
+        return True
+
+    # Plugin interface
+    name = 'HostTestPluginCopyMethod_Firefox'
+    type = 'CopyMethod'
+    capabilities = ['firefox']
+    required_parameters = ['image_path', 'destination_disk']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        try:
+            from selenium import webdriver
+        except ImportError, e:
+            self.print_plugin_error("Error: firefox copy method requires selenium library. %s"% e)
+            return False
+        return True
+
+    def execute(self, capabilitity, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capabilitity, *args, **kwargs) is True:
+            image_path = kwargs['image_path']
+            destination_disk = kwargs['destination_disk']
+            # Prepare correct command line parameter values
+            image_base_name = basename(image_path)
+            destination_path = join(destination_disk, image_base_name)
+            if capabilitity == 'firefox':
+                self.file_store_firefox(image_path, destination_path)
+        return result
+
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginCopyMethod_Firefox()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_mbed.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_mbed.py
new file mode 100755
index 0000000..913ff3c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_mbed.py
@@ -0,0 +1,78 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from shutil import copy
+from host_test_plugins import HostTestPluginBase
+from time import sleep
+
+
+class HostTestPluginCopyMethod_Mbed(HostTestPluginBase):
+
+    def generic_mbed_copy(self, image_path, destination_disk):
+        """ Generic mbed copy method for "mbed enabled" devices.
+            It uses standard python shuitl function to copy
+            image_file (target specific binary) to device's disk.
+        """
+        result = True
+        if not destination_disk.endswith('/') and not destination_disk.endswith('\\'):
+            destination_disk += '/'
+        try:
+            copy(image_path, destination_disk)
+        except Exception, e:
+            self.print_plugin_error("shutil.copy('%s', '%s')"% (image_path, destination_disk))
+            self.print_plugin_error("Error: %s"% str(e))
+            result = False
+        return result
+
+    # Plugin interface
+    name = 'HostTestPluginCopyMethod_Mbed'
+    type = 'CopyMethod'
+    stable = True
+    capabilities = ['shutil', 'default']
+    required_parameters = ['image_path', 'destination_disk', 'program_cycle_s']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        return True
+
+    def execute(self, capability, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capability, *args, **kwargs) is True:
+            # Capability 'default' is a dummy capability
+            if capability == 'shutil':
+                image_path = kwargs['image_path']
+                destination_disk = kwargs['destination_disk']
+                program_cycle_s = kwargs['program_cycle_s']
+                # Wait for mount point to be ready
+                self.check_mount_point_ready(destination_disk)  # Blocking
+                result = self.generic_mbed_copy(image_path, destination_disk)
+
+                # Allow mbed to cycle
+                sleep(program_cycle_s)
+
+        return result
+
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginCopyMethod_Mbed()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_mps2.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_mps2.py
new file mode 100755
index 0000000..bcfe1d7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_mps2.py
@@ -0,0 +1,150 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+import os, shutil
+from os.path import join
+from host_test_plugins import HostTestPluginBase
+from time import sleep
+
+
+class HostTestPluginCopyMethod_MPS2(HostTestPluginBase):
+
+    # MPS2 specific flashing / binary setup funcitons
+    def mps2_set_board_image_file(self, disk, images_cfg_path, image0file_path, image_name='images.txt'):
+        """ This function will alter image cfg file.
+            Main goal of this function is to change number of images to 1, comment all
+            existing image entries and append at the end of file new entry with test path.
+            @return True when all steps succeed.
+        """
+        MBED_SDK_TEST_STAMP = 'test suite entry'
+        image_path = join(disk, images_cfg_path, image_name)
+        new_file_lines = [] # New configuration file lines (entries)
+
+        # Check each line of the image configuration file
+        try:
+            with open(image_path, 'r') as file:
+                for line in file:
+                    if re.search('^TOTALIMAGES', line):
+                        # Check number of total images, should be 1
+                        new_file_lines.append(re.sub('^TOTALIMAGES:[\t ]*[\d]+', 'TOTALIMAGES: 1', line))
+                    elif re.search('; - %s[\n\r]*$'% MBED_SDK_TEST_STAMP, line):
+                        # Look for test suite entries and remove them
+                        pass    # Omit all test suite entries
+                    elif re.search('^IMAGE[\d]+FILE', line):
+                        # Check all image entries and mark the ';'
+                        new_file_lines.append(';' + line)   # Comment non test suite lines
+                    else:
+                        # Append line to new file
+                        new_file_lines.append(line)
+        except IOError as e:
+            return False
+
+        # Add new image entry with proper commented stamp
+        new_file_lines.append('IMAGE0FILE: %s    ; - %s\r\n'% (image0file_path, MBED_SDK_TEST_STAMP))
+
+        # Write all lines to file
+        try:
+            with open(image_path, 'w') as file:
+                for line in new_file_lines:
+                    file.write(line),
+        except IOError:
+            return False
+
+        return True
+
+    def mps2_select_core(self, disk, mobo_config_name=""):
+        """ Function selects actual core
+        """
+        # TODO: implement core selection
+        pass
+
+    def mps2_switch_usb_auto_mounting_after_restart(self, disk, usb_config_name=""):
+        """ Function alters configuration to allow USB MSD to be mounted after restarts
+        """
+        # TODO: implement USB MSD restart detection
+        pass
+
+    def copy_file(self, file, disk):
+        if not file:
+            return
+            
+        _, ext = os.path.splitext(file)
+        ext = ext.lower()
+        dfile = disk + "/SOFTWARE/mbed" + ext
+        
+        if os.path.isfile(dfile):
+            print('Remove old binary %s' % dfile)
+            os.remove(dfile)
+
+        shutil.copy(file, dfile)
+        return True
+        
+    def touch_file(self, file):
+        """ Touch file and set timestamp to items
+        """
+        tfile = file+'.tmp'
+        fhandle = open(tfile, 'a')
+        try:
+            fhandle.close()
+        finally:
+            os.rename(tfile, file)
+            return True
+
+    # Plugin interface
+    name = 'HostTestPluginCopyMethod_MPS2'
+    type = 'CopyMethod'
+    capabilities = ['mps2-copy']
+    required_parameters = ['image_path', 'destination_disk']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        return True
+
+    def execute(self, capabilitity, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capabilitity, *args, **kwargs) is True:
+            file = kwargs['image_path']
+            disk = kwargs['destination_disk']
+            
+            """ Add a delay in case there a test just finished
+                Prevents interface firmware hiccups
+            """
+            sleep(20)
+            if capabilitity == 'mps2-copy' and self.copy_file(file, disk):
+                sleep(3)
+                if self.touch_file(disk + 'reboot.txt'):
+                    """ Add a delay after the board was rebooted.
+                        The actual reboot time is 20 seconds, but using 15 seconds
+                        allows us to open the COM port and save a board reset.
+                        This also prevents interface firmware hiccups.
+                    """
+                    sleep(7)
+                    result = True
+                    
+        return result
+
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginCopyMethod_MPS2()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_shell.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_shell.py
new file mode 100755
index 0000000..18ca062
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_shell.py
@@ -0,0 +1,74 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import os
+from os.path import join, basename
+from host_test_plugins import HostTestPluginBase
+from time import sleep
+
+
+class HostTestPluginCopyMethod_Shell(HostTestPluginBase):
+
+    # Plugin interface
+    name = 'HostTestPluginCopyMethod_Shell'
+    type = 'CopyMethod'
+    stable = True
+    capabilities = ['shell', 'cp', 'copy', 'xcopy']
+    required_parameters = ['image_path', 'destination_disk', 'program_cycle_s']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        return True
+
+    def execute(self, capability, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capability, *args, **kwargs) is True:
+            image_path = kwargs['image_path']
+            destination_disk = kwargs['destination_disk']
+            program_cycle_s = kwargs['program_cycle_s']
+            # Wait for mount point to be ready
+            self.check_mount_point_ready(destination_disk)  # Blocking
+            # Prepare correct command line parameter values
+            image_base_name = basename(image_path)
+            destination_path = join(destination_disk, image_base_name)
+            if capability == 'shell':
+                if os.name == 'nt': capability = 'copy'
+                elif os.name == 'posix': capability = 'cp'
+            if capability == 'cp' or capability == 'copy' or capability == 'copy':
+                copy_method = capability
+                cmd = [copy_method, image_path, destination_path]
+                if os.name == 'posix':
+                    result = self.run_command(cmd, shell=False)
+                    result = self.run_command(["sync"])
+                else:
+                    result = self.run_command(cmd)
+
+            # Allow mbed to cycle
+            sleep(program_cycle_s)
+
+        return result
+
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginCopyMethod_Shell()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_silabs.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_silabs.py
new file mode 100755
index 0000000..494bcf4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_silabs.py
@@ -0,0 +1,67 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from host_test_plugins import HostTestPluginBase
+from time import sleep
+
+
+class HostTestPluginCopyMethod_Silabs(HostTestPluginBase):
+
+    # Plugin interface
+    name = 'HostTestPluginCopyMethod_Silabs'
+    type = 'CopyMethod'
+    capabilities = ['eACommander', 'eACommander-usb']
+    required_parameters = ['image_path', 'destination_disk', 'program_cycle_s']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        self.EACOMMANDER_CMD = 'eACommander.exe'
+        return True
+
+    def execute(self, capabilitity, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capabilitity, *args, **kwargs) is True:
+            image_path = kwargs['image_path']
+            destination_disk = kwargs['destination_disk']
+            program_cycle_s = kwargs['program_cycle_s']
+            if capabilitity == 'eACommander':
+                cmd = [self.EACOMMANDER_CMD,
+                       '--serialno', destination_disk,
+                       '--flash', image_path,
+                       '--resettype', '2', '--reset']
+                result = self.run_command(cmd)
+            elif capabilitity == 'eACommander-usb':
+                cmd = [self.EACOMMANDER_CMD,
+                       '--usb', destination_disk,
+                       '--flash', image_path]
+                result = self.run_command(cmd)
+
+            # Allow mbed to cycle
+            sleep(program_cycle_s)
+
+        return result
+
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginCopyMethod_Silabs()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_smart.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_smart.py
new file mode 100755
index 0000000..486382b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_copy_smart.py
@@ -0,0 +1,118 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import os
+import sys
+from os.path import join, basename, exists, abspath, dirname
+from time import sleep
+from host_test_plugins import HostTestPluginBase
+
+sys.path.append(abspath(join(dirname(__file__), "../../../")))
+import tools.test_api
+
+class HostTestPluginCopyMethod_Smart(HostTestPluginBase):
+
+    # Plugin interface
+    name = 'HostTestPluginCopyMethod_Smart'
+    type = 'CopyMethod'
+    stable = True
+    capabilities = ['smart']
+    required_parameters = ['image_path', 'destination_disk', 'target_mcu']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        return True
+
+    def execute(self, capability, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capability, *args, **kwargs) is True:
+            image_path = kwargs['image_path']
+            destination_disk = kwargs['destination_disk']
+            target_mcu = kwargs['target_mcu']
+            # Wait for mount point to be ready
+            self.check_mount_point_ready(destination_disk)  # Blocking
+            # Prepare correct command line parameter values
+            image_base_name = basename(image_path)
+            destination_path = join(destination_disk, image_base_name)
+            if capability == 'smart':
+                if os.name == 'posix':
+                    cmd = ['cp', image_path, destination_path]
+                    result = self.run_command(cmd, shell=False)
+
+                    cmd = ['sync']
+                    result = self.run_command(cmd, shell=False)
+                elif os.name == 'nt':
+                    cmd = ['copy', image_path, destination_path]
+                    result = self.run_command(cmd, shell=True)
+
+                # Give the OS and filesystem time to settle down
+                sleep(3)
+
+                platform_name_filter = [target_mcu]
+                muts_list = {}
+
+                remount_complete = False
+
+                for i in range(0, 60):
+                    print('Looking for %s with MBEDLS' % target_mcu)
+                    muts_list = tools.test_api.get_autodetected_MUTS_list(platform_name_filter=platform_name_filter)
+
+                    if 1 in muts_list:
+                        mut = muts_list[1]
+                        destination_disk = mut['disk']
+                        destination_path = join(destination_disk, image_base_name)
+
+                        if mut['mcu'] == 'LPC1768' or mut['mcu'] == 'LPC11U24':
+                            if exists(destination_disk) and exists(destination_path):
+                                remount_complete = True
+                                break;
+                        else:
+                            if exists(destination_disk) and not exists(destination_path):
+                                remount_complete = True
+                                break;
+
+                    sleep(1)
+
+                if remount_complete:
+                    print('Remount complete')
+                else:
+                    print('Remount FAILED')
+
+                    if exists(destination_disk):
+                        print('Disk exists')
+                    else:
+                        print('Disk does not exist')
+
+                    if exists(destination_path):
+                        print('Image exists')
+                    else:
+                        print('Image does not exist')
+
+                    result = None
+
+
+        return result
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginCopyMethod_Smart()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_mbed.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_mbed.py
new file mode 100755
index 0000000..0390d84
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_mbed.py
@@ -0,0 +1,72 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from host_test_plugins import HostTestPluginBase
+
+
+class HostTestPluginResetMethod_Mbed(HostTestPluginBase):
+
+    def safe_sendBreak(self, serial):
+        """ Wraps serial.sendBreak() to avoid serial::serialposix.py exception on Linux
+            Traceback (most recent call last):
+              File "make.py", line 189, in <module>
+                serial.sendBreak()
+              File "/usr/lib/python2.7/dist-packages/serial/serialposix.py", line 511, in sendBreak
+                termios.tcsendbreak(self.fd, int(duration/0.25))
+            error: (32, 'Broken pipe')
+        """
+        result = True
+        try:
+            serial.sendBreak()
+        except:
+            # In linux a termios.error is raised in sendBreak and in setBreak.
+            # The following setBreak() is needed to release the reset signal on the target mcu.
+            try:
+                serial.setBreak(False)
+            except:
+                result = False
+        return result
+
+    # Plugin interface
+    name = 'HostTestPluginResetMethod_Mbed'
+    type = 'ResetMethod'
+    stable = True
+    capabilities = ['default']
+    required_parameters = ['serial']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        return True
+
+    def execute(self, capabilitity, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capabilitity, *args, **kwargs) is True:
+            if capabilitity == 'default':
+                serial = kwargs['serial']
+                result = self.safe_sendBreak(serial)
+        return result
+
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginResetMethod_Mbed()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_mps2.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_mps2.py
new file mode 100755
index 0000000..40ff267
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_mps2.py
@@ -0,0 +1,78 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import os
+from host_test_plugins import HostTestPluginBase
+from time import sleep
+
+# Note: This plugin is not fully functional, needs improvements
+
+class HostTestPluginResetMethod_MPS2(HostTestPluginBase):
+    """ Plugin used to reset ARM_MPS2 platform
+    Supports:
+         reboot.txt   - startup from standby state, reboots when in run mode.
+         shutdown.txt - shutdown from run mode.
+         reset.txt    - reset FPGA during run mode.
+    """
+    def touch_file(self, file):
+        """ Touch file and set timestamp to items
+        """
+        tfile = file+'.tmp'
+        fhandle = open(tfile, 'a')
+        try:
+            fhandle.close()
+        finally:
+            os.rename(tfile, file)
+            return True
+
+    # Plugin interface
+    name = 'HostTestPluginResetMethod_MPS2'
+    type = 'ResetMethod'
+    capabilities = ['mps2-reboot', 'mps2-reset']
+    required_parameters = ['disk']
+
+    def setup(self, *args, **kwargs):
+        """ Prepare / configure plugin to work.
+            This method can receive plugin specific parameters by kwargs and
+            ignore other parameters which may affect other plugins.
+        """
+        return True
+
+    def execute(self, capabilitity, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        return True
+        result = False
+        if self.check_parameters(capabilitity, *args, **kwargs) is True:
+            disk = kwargs['disk']
+            
+            if capabilitity == 'mps2-reboot' and self.touch_file(disk + 'reboot.txt'):
+                sleep(20)
+                result = True
+
+            elif capabilitity == 'mps2-reset' and self.touch_file(disk + 'reboot.txt'):
+                sleep(20)
+                result = True
+
+        return result
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginResetMethod_MPS2()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_silabs.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_silabs.py
new file mode 100755
index 0000000..2c05cb2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/host_tests_plugins/module_reset_silabs.py
@@ -0,0 +1,66 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from host_test_plugins import HostTestPluginBase
+
+
+class HostTestPluginResetMethod_SiLabs(HostTestPluginBase):
+
+    # Plugin interface
+    name = 'HostTestPluginResetMethod_SiLabs'
+    type = 'ResetMethod'
+    stable = True
+    capabilities = ['eACommander', 'eACommander-usb']
+    required_parameters = ['disk']
+
+    def setup(self, *args, **kwargs):
+        """ Configure plugin, this function should be called before plugin execute() method is used.
+        """
+        # Note you need to have eACommander.exe on your system path!
+        self.EACOMMANDER_CMD = 'eACommander.exe'
+        return True
+
+    def execute(self, capabilitity, *args, **kwargs):
+        """ Executes capability by name.
+            Each capability may directly just call some command line
+            program or execute building pythonic function
+        """
+        result = False
+        if self.check_parameters(capabilitity, *args, **kwargs) is True:
+            disk = kwargs['disk'].rstrip('/\\')
+
+            if capabilitity == 'eACommander':
+                # For this copy method 'disk' will be 'serialno' for eACommander command line parameters
+                # Note: Commands are executed in the order they are specified on the command line
+                cmd = [self.EACOMMANDER_CMD,
+                       '--serialno', disk,
+                       '--resettype', '2', '--reset',]
+                result = self.run_command(cmd)
+            elif capabilitity == 'eACommander-usb':
+                # For this copy method 'disk' will be 'usb address' for eACommander command line parameters
+                # Note: Commands are executed in the order they are specified on the command line
+                cmd = [self.EACOMMANDER_CMD,
+                       '--usb', disk,
+                       '--resettype', '2', '--reset',]
+                result = self.run_command(cmd)
+        return result
+
+
+def load_plugin():
+    """ Returns plugin available in this module
+    """
+    return HostTestPluginResetMethod_SiLabs()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/mbedrpc.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/mbedrpc.py
new file mode 100755
index 0000000..ffbdef4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/mbedrpc.py
@@ -0,0 +1,225 @@
+# mbedRPC.py - mbed RPC interface for Python
+#
+##Copyright (c) 2010 ARM Ltd
+##
+##Permission is hereby granted, free of charge, to any person obtaining a copy
+##of this software and associated documentation files (the "Software"), to deal
+##in the Software without restriction, including without limitation the rights
+##to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+##copies of the Software, and to permit persons to whom the Software is
+##furnished to do so, subject to the following conditions:
+## 
+##The above copyright notice and this permission notice shall be included in
+##all copies or substantial portions of the Software.
+## 
+##THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+##IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+##FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+##AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+##LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+##OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+##THE SOFTWARE.
+#
+# Example:
+# >from mbedRPC import*
+# >mbed = SerialRPC("COM5",9600)
+# >myled = DigitalOut(mbed,"myled") <--- Where the text in quotations matches your RPC pin definition's second parameter, in this case it could be RpcDigitalOut myled(LED1,"myled");
+# >myled.write(1)
+# >
+
+import serial, urllib2, time
+
+# mbed super class
+class mbed:
+    def __init__(self):
+        print("This will work as a demo but no transport mechanism has been selected")
+
+    def rpc(self, name, method, args):
+        print("Superclass method not overridden")
+
+
+# Transport mechanisms, derived from mbed
+class SerialRPC(mbed):
+    def __init__(self, port, baud):
+        self.ser = serial.Serial(port)
+        self.ser.setBaudrate(baud)
+
+    def rpc(self, name, method, args):
+        # creates the command to be sent serially - /name/method arg1 arg2 arg3 ... argN
+        str = "/" + name + "/" + method + " " + " ".join(args) + "\n"
+        # prints the command being executed
+        print str
+        # writes the command to serial
+        self.ser.write(str)
+        # strips trailing characters from the line just written
+        ret_val = self.ser.readline().strip()
+        return ret_val
+
+
+class HTTPRPC(mbed):
+    def __init__(self, ip):
+        self.host = "http://" + ip
+
+    def rpc(self, name, method, args):
+        response = urllib2.urlopen(self.host + "/rpc/" + name + "/" + method + "%20" + "%20".join(args))
+        return response.read().strip()
+
+
+# generic mbed interface super class
+class mbed_interface():
+    # initialize an mbed interface with a transport mechanism and pin name
+    def __init__(self, this_mbed, mpin):
+        self.mbed = this_mbed
+        if isinstance(mpin, str):
+            self.name = mpin
+
+    def __del__(self):
+        r = self.mbed.rpc(self.name, "delete", [])
+
+    def new(self, class_name, name, pin1, pin2 = "", pin3 = ""):
+        args = [arg for arg in [pin1,pin2,pin3,name] if arg != ""]
+        r = self.mbed.rpc(class_name, "new", args)
+
+    # generic read
+    def read(self):
+        r = self.mbed.rpc(self.name, "read", [])
+        return int(r)
+
+
+# for classes that need write functionality - inherits from the generic reading interface
+class mbed_interface_write(mbed_interface):
+    def __init__(self, this_mbed, mpin):
+        mbed_interface.__init__(self, this_mbed, mpin)
+
+    # generic write
+    def write(self, value):
+        r = self.mbed.rpc(self.name, "write", [str(value)])
+
+
+# mbed interfaces
+class DigitalOut(mbed_interface_write):
+    def __init__(self, this_mbed, mpin):
+        mbed_interface_write.__init__(self, this_mbed, mpin)
+
+
+class AnalogIn(mbed_interface):
+    def __init__(self, this_mbed, mpin):
+        mbed_interface.__init__(self, this_mbed, mpin)
+
+    def read_u16(self):
+        r = self.mbed.rpc(self.name, "read_u16", [])
+        return int(r)
+
+
+class AnalogOut(mbed_interface_write):
+    def __init__(self, this_mbed, mpin):
+        mbed_interface_write.__init__(self, this_mbed, mpin)
+
+    def write_u16(self, value):
+        self.mbed.rpc(self.name, "write_u16", [str(value)])
+
+    def read(self):
+        r = self.mbed.rpc(self.name, "read", [])
+        return float(r)
+
+
+class DigitalIn(mbed_interface):
+    def __init__(self, this_mbed, mpin):
+        mbed_interface.__init__(self, this_mbed, mpin)
+
+
+class PwmOut(mbed_interface_write):
+    def __init__(self, this_mbed, mpin):
+        mbed_interface_write.__init__(self, this_mbed, mpin)
+
+    def read(self):
+        r = self.mbed.rpc(self.name, "read", [])
+        return r
+
+    def period(self, value):
+        self.mbed.rpc(self.name, "period", [str(value)])
+
+    def period_ms(self, value):
+        self.mbed.rpc(self.name, "period_ms", [str(value)])
+
+    def period_us(self, value):
+        self.mbed.rpc(self.name, "period_us", [str(value)])
+
+    def pulsewidth(self, value):
+        self.mbed.rpc(self.name, "pulsewidth", [str(value)])
+
+    def pulsewidth_ms(self, value):
+        self.mbed.rpc(self.name, "pulsewidth_ms", [str(value)])
+
+    def pulsewidth_us(self, value):
+        self.mbed.rpc(self.name, "pulsewidth_us", [str(value)])
+
+
+class RPCFunction(mbed_interface):
+    def __init__(self, this_mbed, name):
+        mbed_interface.__init__(self, this_mbed, name)
+
+    def run(self, input):
+        r = self.mbed.rpc(self.name, "run", [input])
+        return r
+
+
+class RPCVariable(mbed_interface_write):
+    def __init__(self, this_mbed, name):
+        mbed_interface_write.__init__(self, this_mbed, name)
+
+    def read(self):
+        r = self.mbed.rpc(self.name, "read", [])
+        return r
+
+class Timer(mbed_interface):
+    def __init__(self, this_mbed, name):
+        mbed_interface.__init__(self, this_mbed, name)
+
+    def start(self):
+        r = self.mbed.rpc(self.name, "start", [])
+
+    def stop(self):
+        r = self.mbed.rpc(self.name, "stop", [])
+
+    def reset(self):
+        r = self.mbed.rpc(self.name, "reset", [])
+
+    def read(self):
+        r = self.mbed.rpc(self.name, "read", [])
+        return float(re.search('\d+\.*\d*', r).group(0))
+
+    def read_ms(self):
+        r = self.mbed.rpc(self.name, "read_ms", [])
+        return float(re.search('\d+\.*\d*', r).group(0))
+
+    def read_us(self):
+        r = self.mbed.rpc(self.name, "read_us", [])
+        return float(re.search('\d+\.*\d*', r).group(0))
+
+# Serial
+class Serial():
+    def __init__(self, this_mbed, tx, rx=""):
+        self.mbed = this_mbed
+        if isinstance(tx, str):
+            self.name = tx
+
+    def __del__(self):
+        r = self.mbed.rpc(self.name, "delete", [])
+
+    def baud(self, value):
+        r = self.mbed.rpc(self.name, "baud", [str(value)])
+
+    def putc(self, value):
+        r = self.mbed.rpc(self.name, "putc", [str(value)])
+
+    def puts(self, value):
+        r = self.mbed.rpc(self.name, "puts", ["\"" + str(value) + "\""])
+
+    def getc(self):
+        r = self.mbed.rpc(self.name, "getc", [])
+        return int(r)
+
+
+def wait(s):
+    time.sleep(s)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/midi.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/midi.py
new file mode 100755
index 0000000..67f34ea
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/midi.py
@@ -0,0 +1,72 @@
+from __future__ import print_function
+import sys
+import re
+import time
+import mido
+from mido import Message
+
+
+def test_midi_in(port):
+	expected_messages_count=0
+	while expected_messages_count < 7:
+		for message in port.iter_pending():
+			if message.type in ('note_on', 'note_off', 'program_change', 'sysex'):
+				yield message
+				expected_messages_count+=1
+		time.sleep(0.1)
+
+def test_midi_loopback(input_port):
+	expected_messages_count=0
+	while expected_messages_count < 1:
+		for message in input_port.iter_pending():
+			print('Test MIDI OUT loopback received {}'.format(message.hex()))
+			expected_messages_count+=1
+
+def test_midi_out_loopback(output_port,input_port):
+	print("Test MIDI OUT loopback")
+	output_port.send(Message('program_change', program=1))
+	test_midi_loopback(input_port)
+
+	output_port.send(Message('note_on', note=21))
+	test_midi_loopback(input_port)
+
+	output_port.send(Message('note_off', note=21))
+	test_midi_loopback(input_port)
+
+	output_port.send(Message('sysex', data=[0x7E,0x7F,0x09,0x01]))
+	test_midi_loopback(input_port)
+
+	output_port.send(Message('sysex', data=[0x7F,0x7F,0x04,0x01,0x7F,0x7F]))
+	test_midi_loopback(input_port)
+
+	output_port.send(Message('sysex', data=[0x41,0x10,0x42,0x12,0x40,0x00,0x7F,0x00,0x41]))
+	test_midi_loopback(input_port)
+
+	output_port.send(Message('sysex', data=[0x41,0x10,0x42,0x12,0x40,0x00,0x04,0x7F,0x3D]))
+	test_midi_loopback(input_port)
+
+portname=""
+
+while portname=="":
+	print("Wait for MIDI IN plug ...")
+	for name in mido.get_input_names():
+		matchObj = re.match( r'Mbed', name)
+
+		if matchObj:
+			portname=name
+	time.sleep( 1 )
+
+try:
+	input_port = mido.open_input(portname)
+	output_port = mido.open_output(portname)
+	
+	print('Using {}'.format(input_port))
+
+	print("Test MIDI IN")
+
+	for message in test_midi_in(input_port):
+		print('Test MIDI IN received {}'.format(message.hex()))
+
+	test_midi_out_loopback(output_port,input_port)
+except KeyboardInterrupt:
+    pass
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/net_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/net_test.py
new file mode 100755
index 0000000..01b4541
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/net_test.py
@@ -0,0 +1,27 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from host_test import Test, Simple
+from sys import stdout
+
+class NETTest(Simple):
+    def __init__(self):
+        Test.__init__(self)
+        self.mbed.init_serial(115200)
+        self.mbed.reset()
+
+if __name__ == '__main__':
+    NETTest().run()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/rpc.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/rpc.py
new file mode 100755
index 0000000..84b85d2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/rpc.py
@@ -0,0 +1,56 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from host_test import Test
+from mbedrpc import SerialRPC, DigitalOut, DigitalIn, pin
+
+
+class RpcTest(Test):
+    def test(self):
+        self.notify("RPC Test")
+        s = SerialRPC(self.mbed.port, debug=True)
+
+        self.notify("Init remote objects")
+
+        p_out = pin("p10")
+        p_in  = pin("p11")
+
+        if hasattr(self.mbed.options, 'micro'):
+            if self.mbed.options.micro == 'M0+':
+                print "Freedom Board: PTA12 <-> PTC4"
+                p_out = pin("PTA12")
+                p_in  = pin("PTC4")
+
+        self.output = DigitalOut(s, p_out);
+        self.input = DigitalIn(s, p_in);
+
+        self.check = True
+        self.write_read_test(1)
+        self.write_read_test(0)
+        return self.check
+
+    def write_read_test(self, v):
+        self.notify("Check %d" % v)
+        self.output.write(v)
+        if self.input.read() != v:
+            self.notify("ERROR")
+            self.check = False
+        else:
+            self.notify("OK")
+
+
+if __name__ == '__main__':
+    RpcTest().run()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/rtc_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/rtc_auto.py
new file mode 100755
index 0000000..d267936
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/rtc_auto.py
@@ -0,0 +1,50 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+from time import time, strftime, gmtime
+
+class RTCTest():
+    PATTERN_RTC_VALUE = "\[(\d+)\] \[(\d+-\d+-\d+ \d+:\d+:\d+ [AaPpMm]{2})\]"
+    re_detect_rtc_value = re.compile(PATTERN_RTC_VALUE)
+
+    def test(self, selftest):
+        test_result = True
+        start = time()
+        sec_prev = 0
+        for i in range(0, 5):
+            # Timeout changed from default: we need to wait longer for some boards to start-up
+            c = selftest.mbed.serial_readline(timeout=10)
+            if c is None:
+                return selftest.RESULT_IO_SERIAL
+            selftest.notify(c.strip())
+            delta = time() - start
+            m = self.re_detect_rtc_value.search(c)
+            if m and len(m.groups()):
+                sec = int(m.groups()[0])
+                time_str = m.groups()[1]
+                correct_time_str = strftime("%Y-%m-%d %H:%M:%S %p", gmtime(float(sec)))
+                single_result = time_str == correct_time_str and sec > 0 and sec > sec_prev
+                test_result = test_result and single_result
+                result_msg = "OK" if single_result else "FAIL"
+                selftest.notify("HOST: [%s] [%s] received time %+d sec after %.2f sec... %s"% (sec, time_str, sec - sec_prev, delta, result_msg))
+                sec_prev = sec
+            else:
+                test_result = False
+                break
+            start = time()
+        return selftest.RESULT_SUCCESS if test_result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_complete_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_complete_auto.py
new file mode 100755
index 0000000..e130ff9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_complete_auto.py
@@ -0,0 +1,43 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import uuid
+import time
+import string
+from sys import stdout
+
+class SerialCompleteTest():
+
+    def test(self, selftest):
+        strip_chars = string.whitespace + "\0"
+        out_str = selftest.mbed.serial_readline()
+        selftest.notify("HOST: " + out_str)
+
+        if not out_str:
+            selftest.notify("HOST: No output detected")
+            return selftest.RESULT_IO_SERIAL
+
+        out_str_stripped = out_str.strip(strip_chars)
+
+        if out_str_stripped != "123456789":
+            selftest.notify("HOST: Unexpected output. '123456789' Expected. but received '%s'" % out_str_stripped)
+            return selftest.RESULT_FAILURE
+
+        else:
+            return selftest.RESULT_SUCCESS
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_nc_rx_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_nc_rx_auto.py
new file mode 100755
index 0000000..59975db
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_nc_rx_auto.py
@@ -0,0 +1,87 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import uuid
+import time
+import string
+from sys import stdout
+
+class SerialNCRXTest():
+
+    def test(self, selftest):
+        selftest.mbed.flush();
+        # Wait 0.5 seconds to ensure mbed is listening
+        time.sleep(0.5)
+
+        #handshake with target to sync test start
+        selftest.mbed.serial_write("S");
+
+        strip_chars = string.whitespace + "\0"
+
+        out_str = selftest.mbed.serial_readline()
+
+        if not out_str:
+            selftest.notify("HOST: No output detected")
+            return selftest.RESULT_IO_SERIAL
+
+        out_str_stripped = out_str.strip(strip_chars)
+
+        if out_str_stripped != "RX OK - Start NC test":
+            selftest.notify("HOST: Unexpected output. Expected 'RX OK - Expected' but received '%s'" % out_str_stripped)
+            return selftest.RESULT_FAILURE
+
+        # Wait 0.5 seconds to ensure mbed is listening
+        time.sleep(0.5)
+
+        selftest.mbed.serial_write("E");
+
+        strip_chars = string.whitespace + "\0"
+
+        out_str = selftest.mbed.serial_readline()
+
+        if not out_str:
+            selftest.notify("HOST: No output detected")
+            return selftest.RESULT_IO_SERIAL
+
+        out_str_stripped = out_str.strip(strip_chars)
+
+        if out_str_stripped != "RX OK - Expected":
+            selftest.notify("HOST: Unexpected output. Expected 'RX OK - Expected' but received '%s'" % out_str_stripped)
+            return selftest.RESULT_FAILURE
+
+        # Wait 0.5 seconds to ensure mbed is listening
+        time.sleep(0.5)
+
+        # Send character, mbed shouldn't receive
+        selftest.mbed.serial_write("U");
+
+        out_str = selftest.mbed.serial_readline()
+
+        # If no characters received, pass the test
+        if not out_str:
+            selftest.notify("HOST: No further output detected")
+            return selftest.RESULT_SUCCESS
+        else:
+            out_str_stripped = out_str.strip(strip_chars)
+
+            if out_str_stripped == "RX OK - Unexpected":
+                selftest.notify("HOST: Unexpected output returned indicating RX still functioning")
+            else:
+                selftest.notify("HOST: Extraneous output '%s' detected indicating unknown error" % out_str_stripped)
+
+            return selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_nc_tx_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_nc_tx_auto.py
new file mode 100755
index 0000000..707c476
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/serial_nc_tx_auto.py
@@ -0,0 +1,62 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import uuid
+import time
+import string
+from sys import stdout
+
+class SerialNCTXTest():
+
+    def test(self, selftest):
+        selftest.mbed.flush();
+        # Wait 0.5 seconds to ensure mbed is listening
+        time.sleep(0.5)
+
+        selftest.mbed.serial_write("S");
+
+        strip_chars = string.whitespace + "\0"
+
+        out_str = selftest.mbed.serial_readline()
+        selftest.notify("HOST: " + out_str)
+
+        if not out_str:
+            selftest.notify("HOST: No output detected")
+            return selftest.RESULT_IO_SERIAL
+
+        out_str_stripped = out_str.strip(strip_chars)
+
+        if out_str_stripped != "TX OK - Expected":
+            selftest.notify("HOST: Unexpected output. Expected 'TX OK - Expected' but received '%s'" % out_str_stripped)
+            return selftest.RESULT_FAILURE
+
+        out_str = selftest.mbed.serial_readline()
+
+        # If no characters received, pass the test
+        if not out_str:
+            selftest.notify("HOST: No further output detected")
+            return selftest.RESULT_SUCCESS
+        else:
+            out_str_stripped = out_str.strip(strip_chars)
+
+            if out_str_stripped == "TX OK - Unexpected":
+                selftest.notify("HOST: Unexpected output returned indicating TX still functioning")
+            else:
+                selftest.notify("HOST: Extraneous output '%s' detected indicating unknown error" % out_str_stripped)
+
+            return selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/stdio_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/stdio_auto.py
new file mode 100755
index 0000000..1fe1890
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/stdio_auto.py
@@ -0,0 +1,56 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+import random
+from time import time
+
+class StdioTest():
+    PATTERN_INT_VALUE = "Your value was: (-?\d+)"
+    re_detect_int_value = re.compile(PATTERN_INT_VALUE)
+
+    def test(self, selftest):
+        test_result = True
+
+        c = selftest.mbed.serial_readline() # {{start}} preamble
+        if c is None:
+            return selftest.RESULT_IO_SERIAL
+        selftest.notify(c)
+
+        for i in range(0, 10):
+            random_integer = random.randint(-99999, 99999)
+            selftest.notify("HOST: Generated number: " + str(random_integer))
+            start = time()
+            selftest.mbed.serial_write(str(random_integer) + "\n")
+
+            serial_stdio_msg = selftest.mbed.serial_readline()
+            if serial_stdio_msg is None:
+                return selftest.RESULT_IO_SERIAL
+            delay_time = time() - start
+            selftest.notify(serial_stdio_msg.strip())
+
+            # Searching for reply with scanned values
+            m = self.re_detect_int_value.search(serial_stdio_msg)
+            if m and len(m.groups()):
+                int_value = m.groups()[0]
+                int_value_cmp = random_integer == int(int_value)
+                test_result = test_result and int_value_cmp
+                selftest.notify("HOST: Number %s read after %.3f sec ... [%s]"% (int_value, delay_time, "OK" if int_value_cmp else "FAIL"))
+            else:
+                test_result = False
+                break
+        return selftest.RESULT_SUCCESS if test_result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_client.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_client.py
new file mode 100755
index 0000000..6122a1c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_client.py
@@ -0,0 +1,57 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import socket
+import string, random
+from time import time
+
+from mbed_settings import SERVER_ADDRESS
+
+ECHO_PORT = 7
+
+LEN_PACKET = 127
+N_PACKETS = 5000
+TOT_BITS = float(LEN_PACKET * N_PACKETS * 8) * 2
+MEGA = float(1024 * 1024)
+UPDATE_STEP = (N_PACKETS/10)
+
+class TCP_EchoClient:
+    def __init__(self, host):
+        self.s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+        self.s.connect((host, ECHO_PORT))
+        self.packet = ''.join(random.choice(string.ascii_uppercase + string.digits) for _ in range(LEN_PACKET))
+
+    def __packet(self):
+        # Comment out the checks when measuring the throughput
+        # self.packet = ''.join(random.choice(string.ascii_uppercase + string.digits) for _ in range(LEN_PACKET))
+        self.s.send(self.packet)
+        data = self.s.recv(LEN_PACKET)
+        # assert self.packet == data, "packet error:\n%s\n%s\n" % (self.packet, data)
+
+    def test(self):
+        start = time()
+        for i in range(N_PACKETS):
+            if (i % UPDATE_STEP) == 0: print '%.2f%%' % ((float(i)/float(N_PACKETS)) * 100.)
+            self.__packet()
+        t = time() - start
+        print 'Throughput: (%.2f)Mbits/s' % ((TOT_BITS / t)/MEGA)
+
+    def __del__(self):
+        self.s.close()
+
+while True:
+    e = TCP_EchoClient(SERVER_ADDRESS)
+    e.test()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_client_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_client_auto.py
new file mode 100755
index 0000000..fe915a1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_client_auto.py
@@ -0,0 +1,87 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import socket
+from sys import stdout
+from SocketServer import BaseRequestHandler, TCPServer
+
+class TCPEchoClient_Handler(BaseRequestHandler):
+    def handle(self):
+        """ One handle per connection
+        """
+        print "HOST: Connection received...",
+        count = 1;
+        while True:
+            data = self.request.recv(1024)
+            if not data: break
+            self.request.sendall(data)
+            if '{{end}}' in str(data):
+                print
+                print str(data)
+            else:
+                if not count % 10:
+                    sys.stdout.write('.')
+                count += 1
+            stdout.flush()
+
+class TCPEchoClientTest():
+    def send_server_ip_port(self, selftest, ip_address, port_no):
+        """ Set up network host. Reset target and and send server IP via serial to Mbed
+        """
+        c = selftest.mbed.serial_readline() # 'TCPCllient waiting for server IP and port...'
+        if c is None:
+            self.print_result(selftest.RESULT_IO_SERIAL)
+            return
+
+        selftest.notify(c.strip())
+        selftest.notify("HOST: Sending server IP Address to target...")
+
+        connection_str = ip_address + ":" + str(port_no) + "\n"
+        selftest.mbed.serial_write(connection_str)
+        selftest.notify(connection_str)
+
+        # Two more strings about connection should be sent by MBED
+        for i in range(0, 2):
+            c = selftest.mbed.serial_readline()
+            if c is None:
+                selftest.print_result(self.RESULT_IO_SERIAL)
+                return
+            selftest.notify(c.strip())
+
+    def test(self, selftest):
+        # We need to discover SERVEP_IP and set up SERVER_PORT
+        # Note: Port 7 is Echo Protocol:
+        #
+        # Port number rationale:
+        #
+        # The Echo Protocol is a service in the Internet Protocol Suite defined
+        # in RFC 862. It was originally proposed for testing and measurement
+        # of round-trip times[citation needed] in IP networks.
+        #
+        # A host may connect to a server that supports the Echo Protocol using
+        # the Transmission Control Protocol (TCP) or the User Datagram Protocol
+        # (UDP) on the well-known port number 7. The server sends back an
+        # identical copy of the data it received.
+        SERVER_IP = str(socket.gethostbyname(socket.getfqdn()))
+        SERVER_PORT = 7
+
+        # Returning none will suppress host test from printing success code
+        server = TCPServer((SERVER_IP, SERVER_PORT), TCPEchoClient_Handler)
+        print "HOST: Listening for TCP connections: " + SERVER_IP + ":" + str(SERVER_PORT)
+        self.send_server_ip_port(selftest, SERVER_IP, SERVER_PORT)
+        server.serve_forever()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server.py
new file mode 100755
index 0000000..e98da63
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server.py
@@ -0,0 +1,50 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from SocketServer import BaseRequestHandler, TCPServer
+from time import time
+
+from mbed_settings import LOCALHOST
+
+MAX_INDEX = 126
+MEGA = float(1024 * 1024)
+
+class TCP_EchoHandler(BaseRequestHandler):
+    def handle(self):
+        print "\nconnection received"
+        start = time()
+        bytes = 0
+        index = 0
+        while True:
+            data = self.request.recv(1024)
+            if not data: break
+
+            bytes += len(data)
+            for n in map(ord, data):
+                if n != index:
+                    print "data error %d != %d" % (n , index)
+                index += 1
+                if index > MAX_INDEX:
+                    index = 0
+
+            self.request.sendall(data)
+        t = time() - start
+        b = float(bytes * 8) * 2
+        print "Throughput: (%.2f)Mbits/s" % ((b/t)/MEGA)
+
+server = TCPServer((LOCALHOST, 7), TCP_EchoHandler)
+print "listening for connections"
+server.serve_forever()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server_auto.py
new file mode 100755
index 0000000..8bc0e30
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server_auto.py
@@ -0,0 +1,84 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+import sys
+import uuid
+import socket
+from sys import stdout
+
+class TCPEchoServerTest():
+    ECHO_SERVER_ADDRESS = ""
+    ECHO_PORT = 0
+    ECHO_LOOPs = 100
+    s = None # Socket
+
+    PATTERN_SERVER_IP = "Server IP Address is (\d+).(\d+).(\d+).(\d+):(\d+)"
+    re_detect_server_ip = re.compile(PATTERN_SERVER_IP)
+
+    def test(self, selftest):
+        result = False
+        c = selftest.mbed.serial_readline()
+        if c is None:
+            return selftest.RESULT_IO_SERIAL
+        selftest.notify(c)
+
+        m = self.re_detect_server_ip.search(c)
+        if m and len(m.groups()):
+            self.ECHO_SERVER_ADDRESS = ".".join(m.groups()[:4])
+            self.ECHO_PORT = int(m.groups()[4]) # must be integer for socket.connect method
+            selftest.notify("HOST: TCP Server found at: " + self.ECHO_SERVER_ADDRESS + ":" + str(self.ECHO_PORT))
+
+            # We assume this test fails so can't send 'error' message to server
+            try:
+                self.s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+                self.s.connect((self.ECHO_SERVER_ADDRESS, self.ECHO_PORT))
+            except Exception, e:
+                self.s = None
+                selftest.notify("HOST: Socket error: %s"% e)
+                return selftest.RESULT_ERROR
+
+            print 'HOST: Sending %d echo strings...'% self.ECHO_LOOPs,
+            for i in range(0, self.ECHO_LOOPs):
+                TEST_STRING = str(uuid.uuid4())
+                try:
+                    self.s.sendall(TEST_STRING)
+                    data = self.s.recv(128)
+                except Exception, e:
+                    self.s = None
+                    selftest.notify("HOST: Socket error: %s"% e)
+                    return selftest.RESULT_ERROR
+
+                received_str = repr(data)[1:-1]
+                if TEST_STRING == received_str: # We need to cut not needed single quotes from the string
+                    sys.stdout.write('.')
+                    stdout.flush()
+                    result = True
+                else:
+                    print "Expected: "
+                    print "'%s'"% TEST_STRING
+                    print "received: "
+                    print "'%s'"% received_str
+                    result = False
+                    break
+
+            if self.s is not None:
+                self.s.close()
+        else:
+            selftest.notify("HOST: TCP Server not found")
+            result = False
+        return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server_loop.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server_loop.py
new file mode 100755
index 0000000..cc11ed0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/tcpecho_server_loop.py
@@ -0,0 +1,40 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+# Be sure that the tools directory is in the search path
+import sys
+from os.path import join, abspath, dirname
+ROOT = abspath(join(dirname(__file__), "..", ".."))
+sys.path.insert(0, ROOT)
+
+from mbed_settings import LOCALHOST
+from SocketServer import BaseRequestHandler, TCPServer
+
+
+class TCP_EchoHandler(BaseRequestHandler):
+    def handle(self):
+        print "\nHandle connection from:", self.client_address
+        while True:
+            data = self.request.recv(1024)
+            if not data: break
+            self.request.sendall(data)
+        self.request.close()
+        print "socket closed"
+
+if __name__ == '__main__':
+    server = TCPServer((LOCALHOST, 7), TCP_EchoHandler)
+    print "listening for connections on:", (LOCALHOST, 7)
+    server.serve_forever()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udp_link_layer_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udp_link_layer_auto.py
new file mode 100755
index 0000000..cb0578f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udp_link_layer_auto.py
@@ -0,0 +1,145 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+"""
+How to use:
+make.py -m LPC1768 -t ARM -d E:\ -n NET_14
+udp_link_layer_auto.py -p COM20 -d E:\ -t 10
+"""
+
+import re
+import uuid
+import socket
+import thread
+from sys import stdout
+from time import time, sleep
+from host_test import DefaultTest
+from SocketServer import BaseRequestHandler, UDPServer
+
+
+# Received datagrams (with time)
+dict_udp_recv_datagrams = dict()
+
+# Sent datagrams (with time)
+dict_udp_sent_datagrams = dict()
+
+
+class UDPEchoClient_Handler(BaseRequestHandler):
+    def handle(self):
+        """ One handle per connection
+        """
+        _data, _socket = self.request
+        # Process received datagram
+        data_str = repr(_data)[1:-1]
+        dict_udp_recv_datagrams[data_str] = time()
+
+
+def udp_packet_recv(threadName, server_ip, server_port):
+    """ This function will receive packet stream from mbed device
+    """
+    server = UDPServer((server_ip, server_port), UDPEchoClient_Handler)
+    print "[UDP_COUNTER] Listening for connections... %s:%d"% (server_ip, server_port)
+    server.serve_forever()
+
+
+class UDPEchoServerTest(DefaultTest):
+    ECHO_SERVER_ADDRESS = ""       # UDP IP of datagram bursts
+    ECHO_PORT = 0                  # UDP port for datagram bursts
+    CONTROL_PORT = 23              # TCP port used to get stats from mbed device, e.g. counters
+    s = None                       # Socket
+
+    TEST_PACKET_COUNT = 1000       # how many packets should be send
+    TEST_STRESS_FACTOR = 0.001     # stress factor: 10 ms
+    PACKET_SATURATION_RATIO = 29.9 # Acceptable packet transmission in %
+
+    PATTERN_SERVER_IP = "Server IP Address is (\d+).(\d+).(\d+).(\d+):(\d+)"
+    re_detect_server_ip = re.compile(PATTERN_SERVER_IP)
+
+    def get_control_data(self, command="stat\n"):
+        BUFFER_SIZE = 256
+        try:
+            s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+            s.connect((self.ECHO_SERVER_ADDRESS, self.CONTROL_PORT))
+        except Exception, e:
+            data = None
+        s.send(command)
+        data = s.recv(BUFFER_SIZE)
+        s.close()
+        return data
+
+    def test(self):
+        serial_ip_msg = self.mbed.serial_readline()
+        if serial_ip_msg is None:
+            return self.RESULT_IO_SERIAL
+        stdout.write(serial_ip_msg)
+        stdout.flush()
+        # Searching for IP address and port prompted by server
+        m = self.re_detect_server_ip.search(serial_ip_msg)
+        if m and len(m.groups()):
+            self.ECHO_SERVER_ADDRESS = ".".join(m.groups()[:4])
+            self.ECHO_PORT = int(m.groups()[4]) # must be integer for socket.connect method
+            self.notify("HOST: UDP Server found at: " + self.ECHO_SERVER_ADDRESS + ":" + str(self.ECHO_PORT))
+
+        # Open client socket to burst datagrams to UDP server in mbed
+        try:
+            self.s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+        except Exception, e:
+            self.s = None
+            self.notify("HOST: Error: %s"% e)
+            return self.RESULT_ERROR
+
+        # UDP replied receiver works in background to get echoed datagrams
+        SERVER_IP = str(socket.gethostbyname(socket.getfqdn()))
+        SERVER_PORT = self.ECHO_PORT + 1
+        thread.start_new_thread(udp_packet_recv, ("Thread-udp-recv", SERVER_IP, SERVER_PORT))
+        sleep(0.5)
+
+        # Burst part
+        for no in range(self.TEST_PACKET_COUNT):
+            TEST_STRING = str(uuid.uuid4())
+            payload = str(no) + "__" + TEST_STRING
+            self.s.sendto(payload, (self.ECHO_SERVER_ADDRESS, self.ECHO_PORT))
+            dict_udp_sent_datagrams[payload] = time()
+            sleep(self.TEST_STRESS_FACTOR)
+
+        if self.s is not None:
+            self.s.close()
+
+        # Wait 5 seconds for packets to come
+        result = True
+        self.notify("HOST: Test Summary:")
+        for d in range(5):
+            sleep(1.0)
+            summary_datagram_success = (float(len(dict_udp_recv_datagrams)) / float(self.TEST_PACKET_COUNT)) * 100.0
+            self.notify("HOST: Datagrams received after +%d sec: %.3f%% (%d / %d), stress=%.3f ms"% (d,
+                                                                                                     summary_datagram_success,
+                                                                                                     len(dict_udp_recv_datagrams),
+                                                                                                     self.TEST_PACKET_COUNT,
+                                                                                                     self.TEST_STRESS_FACTOR))
+            result = result and (summary_datagram_success >= self.PACKET_SATURATION_RATIO)
+            stdout.flush()
+
+        # Getting control data from test
+        self.notify("...")
+        self.notify("HOST: Mbed Summary:")
+        mbed_stats = self.get_control_data()
+        self.notify(mbed_stats)
+        return self.RESULT_SUCCESS if result else self.RESULT_FAILURE
+
+
+if __name__ == '__main__':
+    UDPEchoServerTest().run()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_client.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_client.py
new file mode 100755
index 0000000..af32601
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_client.py
@@ -0,0 +1,55 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from socket import socket, AF_INET, SOCK_DGRAM
+import string, random
+from time import time
+
+from mbed_settings import CLIENT_ADDRESS
+
+ECHO_PORT = 7
+
+LEN_PACKET = 127
+N_PACKETS = 5000
+TOT_BITS = float(LEN_PACKET * N_PACKETS * 8) * 2
+MEGA = float(1024 * 1024)
+UPDATE_STEP = (N_PACKETS/10)
+
+class UDP_EchoClient:
+    s = socket(AF_INET, SOCK_DGRAM)
+
+    def __init__(self, host):
+        self.host = host
+        self.packet = ''.join(random.choice(string.ascii_uppercase + string.digits) for _ in range(LEN_PACKET))
+
+    def __packet(self):
+        # Comment out the checks when measuring the throughput
+        # packet = ''.join(random.choice(string.ascii_uppercase + string.digits) for _ in range(LEN_PACKET))
+        UDP_EchoClient.s.sendto(packet, (self.host, ECHO_PORT))
+        data = UDP_EchoClient.s.recv(LEN_PACKET)
+        # assert packet == data, "packet error:\n%s\n%s\n" % (packet, data)
+
+    def test(self):
+        start = time()
+        for i in range(N_PACKETS):
+            if (i % UPDATE_STEP) == 0: print '%.2f%%' % ((float(i)/float(N_PACKETS)) * 100.)
+            self.__packet()
+        t = time() - start
+        print 'Throughput: (%.2f)Mbits/s' % ((TOT_BITS / t)/MEGA)
+
+while True:
+    e = UDP_EchoClient(CLIENT_ADDRESS)
+    e.test()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_client_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_client_auto.py
new file mode 100755
index 0000000..7896127
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_client_auto.py
@@ -0,0 +1,77 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import socket
+from sys import stdout
+from SocketServer import BaseRequestHandler, UDPServer
+
+class UDPEchoClient_Handler(BaseRequestHandler):
+    def handle(self):
+        """ One handle per connection
+        """
+        data, socket = self.request
+        socket.sendto(data, self.client_address)
+        if '{{end}}' in data:
+            print
+            print data
+        else:
+            sys.stdout.write('.')
+        stdout.flush()
+
+class UDPEchoClientTest():
+
+    def send_server_ip_port(self, selftest, ip_address, port_no):
+        c = selftest.mbed.serial_readline() # 'UDPCllient waiting for server IP and port...'
+        if c is None:
+            selftest.print_result(selftest.RESULT_IO_SERIAL)
+            return
+        selftest.notify(c.strip())
+
+        selftest.notify("HOST: Sending server IP Address to target...")
+        connection_str = ip_address + ":" + str(port_no) + "\n"
+        selftest.mbed.serial_write(connection_str)
+
+        c = selftest.mbed.serial_readline() # 'UDPCllient waiting for server IP and port...'
+        if c is None:
+            self.print_result(selftest.RESULT_IO_SERIAL)
+            return
+        selftest.notify(c.strip())
+        return selftest.RESULT_PASSIVE
+
+    def test(self, selftest):
+        # We need to discover SERVEP_IP and set up SERVER_PORT
+        # Note: Port 7 is Echo Protocol:
+        #
+        # Port number rationale:
+        #
+        # The Echo Protocol is a service in the Internet Protocol Suite defined
+        # in RFC 862. It was originally proposed for testing and measurement
+        # of round-trip times[citation needed] in IP networks.
+        #
+        # A host may connect to a server that supports the Echo Protocol using
+        # the Transmission Control Protocol (TCP) or the User Datagram Protocol
+        # (UDP) on the well-known port number 7. The server sends back an
+        # identical copy of the data it received.
+        SERVER_IP = str(socket.gethostbyname(socket.getfqdn()))
+        SERVER_PORT = 7
+
+        # Returning none will suppress host test from printing success code
+        server = UDPServer((SERVER_IP, SERVER_PORT), UDPEchoClient_Handler)
+        print "HOST: Listening for UDP connections..."
+        self.send_server_ip_port(selftest, SERVER_IP, SERVER_PORT)
+        server.serve_forever()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_server.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_server.py
new file mode 100755
index 0000000..7f7e899
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_server.py
@@ -0,0 +1,29 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from SocketServer import BaseRequestHandler, UDPServer
+from mbed_settings import SERVER_ADDRESS
+
+class UDP_EchoHandler(BaseRequestHandler):
+    def handle(self):
+        data, socket = self.request
+        print "client:", self.client_address
+        print "data:", data
+        socket.sendto(data, self.client_address)
+
+server = UDPServer((SERVER_ADDRESS, 7195), UDP_EchoHandler)
+print "listening for connections"
+server.serve_forever()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_server_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_server_auto.py
new file mode 100755
index 0000000..a7ee026
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/udpecho_server_auto.py
@@ -0,0 +1,68 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+import sys
+import uuid
+from sys import stdout
+from socket import socket, AF_INET, SOCK_DGRAM
+
+class UDPEchoServerTest():
+    ECHO_SERVER_ADDRESS = ""
+    ECHO_PORT = 0
+    s = None # Socket
+
+    PATTERN_SERVER_IP = "Server IP Address is (\d+).(\d+).(\d+).(\d+):(\d+)"
+    re_detect_server_ip = re.compile(PATTERN_SERVER_IP)
+
+    def test(self, selftest):
+        result = True
+        serial_ip_msg = selftest.mbed.serial_readline()
+        if serial_ip_msg is None:
+            return selftest.RESULT_IO_SERIAL
+        selftest.notify(serial_ip_msg)
+        # Searching for IP address and port prompted by server
+        m = self.re_detect_server_ip.search(serial_ip_msg)
+        if m and len(m.groups()):
+            self.ECHO_SERVER_ADDRESS = ".".join(m.groups()[:4])
+            self.ECHO_PORT = int(m.groups()[4]) # must be integer for socket.connect method
+            selftest.notify("HOST: UDP Server found at: " + self.ECHO_SERVER_ADDRESS + ":" + str(self.ECHO_PORT))
+
+            # We assume this test fails so can't send 'error' message to server
+            try:
+                self.s = socket(AF_INET, SOCK_DGRAM)
+            except Exception, e:
+                self.s = None
+                selftest.notify("HOST: Socket error: %s"% e)
+                return selftest.RESULT_ERROR
+
+            for i in range(0, 100):
+                TEST_STRING = str(uuid.uuid4())
+                self.s.sendto(TEST_STRING, (self.ECHO_SERVER_ADDRESS, self.ECHO_PORT))
+                data = self.s.recv(len(TEST_STRING))
+                received_str = repr(data)[1:-1]
+                if TEST_STRING != received_str:
+                    result = False
+                    break
+                sys.stdout.write('.')
+                stdout.flush()
+        else:
+            result = False
+
+        if self.s is not None:
+            self.s.close()
+        return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/wait_us_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/wait_us_auto.py
new file mode 100755
index 0000000..2ab66a3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/wait_us_auto.py
@@ -0,0 +1,69 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from time import time
+
+class WaitusTest():
+    """ This test is reading single characters from stdio
+        and measures time between their occurrences.
+    """
+    TICK_LOOP_COUNTER = 13
+    TICK_LOOP_SUCCESSFUL_COUNTS = 10
+    DEVIATION = 0.10    # +/-10%
+
+    def test(self, selftest):
+        test_result = True
+        # First character to start test (to know after reset when test starts)
+        if selftest.mbed.set_serial_timeout(None) is None:
+            return selftest.RESULT_IO_SERIAL
+        c = selftest.mbed.serial_read(1)
+        if c is None:
+            return selftest.RESULT_IO_SERIAL
+        if c == '$': # target will printout TargetID e.g.: $$$$1040e649d5c09a09a3f6bc568adef61375c6
+            #Read additional 39 bytes of TargetID
+            if selftest.mbed.serial_read(39) is None:
+                return selftest.RESULT_IO_SERIAL
+            c = selftest.mbed.serial_read(1) # Re-read first 'tick'
+            if c is None:
+                return selftest.RESULT_IO_SERIAL
+        start_serial_pool = time()
+        start = time()
+
+        success_counter = 0
+
+        for i in range(0, self.TICK_LOOP_COUNTER):
+            c = selftest.mbed.serial_read(1)
+            if c is None:
+                return selftest.RESULT_IO_SERIAL
+            delta = time() - start
+            deviation = abs(delta - 1)
+            # Round values
+            delta = round(delta, 2)
+            deviation = round(deviation, 2)
+            # Check if time measurements are in given range
+            deviation_ok = True if delta > 0 and deviation <= self.DEVIATION else False
+            success_counter = success_counter+1 if deviation_ok else 0
+            msg = "OK" if deviation_ok else "FAIL"
+            selftest.notify("%s in %.2f sec (%.2f) [%s]"% (c, delta, deviation, msg))
+            start = time()
+            if success_counter >= self.TICK_LOOP_SUCCESSFUL_COUNTS:
+                break
+        measurement_time = time() - start_serial_pool
+        selftest.notify("Consecutive OK timer reads: %d"% success_counter)
+        selftest.notify("Completed in %.2f sec" % (measurement_time))
+        test_result = True if success_counter >= self.TICK_LOOP_SUCCESSFUL_COUNTS else False
+        return selftest.RESULT_SUCCESS if test_result else selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/wfi_auto.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/wfi_auto.py
new file mode 100755
index 0000000..a62c432
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/host_tests/wfi_auto.py
@@ -0,0 +1,45 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import uuid
+import time
+from sys import stdout
+
+class WFITest():
+
+    def test(self, selftest):
+        c = selftest.mbed.serial_readline()
+
+        if c == None:
+            selftest.notify("HOST: No output detected")
+            return selftest.RESULT_IO_SERIAL
+
+        if c.strip() != "0":
+            selftest.notify("HOST: Unexpected output. Expected '0' but received '%s'" % c.strip())
+            return selftest.RESULT_FAILURE
+
+        # Wait 10 seconds to allow serial prints (indicating failure)
+        selftest.mbed.set_serial_timeout(10)
+
+        # If no characters received, pass the test
+        if not selftest.mbed.serial_readline():
+            selftest.notify("HOST: No further output detected")
+            return selftest.RESULT_SUCCESS
+        else:
+            selftest.notify("HOST: Extra output detected")
+            return selftest.RESULT_FAILURE
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/libraries.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/libraries.py
new file mode 100755
index 0000000..abd5b85
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/libraries.py
@@ -0,0 +1,98 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from tools.paths import MBED_LIBRARIES,\
+    MBED_RPC, RPC_LIBRARY, USB, USB_LIBRARIES, \
+    DSP_ABSTRACTION, DSP_CMSIS, DSP_LIBRARIES,\
+    CPPUTEST_SRC,\
+    CPPUTEST_PLATFORM_SRC, CPPUTEST_TESTRUNNER_SCR, CPPUTEST_LIBRARY,\
+    CPPUTEST_INC, CPPUTEST_PLATFORM_INC, CPPUTEST_TESTRUNNER_INC,\
+    CPPUTEST_INC_EXT
+from tools.data.support import DEFAULT_SUPPORT
+from tools.tests import TEST_MBED_LIB
+
+
+LIBRARIES = [
+    # RPC
+    {
+        "id": "rpc",
+        "source_dir": MBED_RPC,
+        "build_dir": RPC_LIBRARY,
+        "dependencies": [MBED_LIBRARIES],
+    },
+
+    # USB Device libraries
+    {
+        "id": "usb",
+        "source_dir": USB,
+        "build_dir": USB_LIBRARIES,
+        "dependencies": [MBED_LIBRARIES],
+    },
+
+    # DSP libraries
+    {
+        "id": "dsp",
+        "source_dir": [DSP_ABSTRACTION, DSP_CMSIS],
+        "build_dir": DSP_LIBRARIES,
+        "dependencies": [MBED_LIBRARIES]
+    },
+
+    # Unit Testing library
+    {
+        "id": "cpputest",
+        "source_dir": [CPPUTEST_SRC, CPPUTEST_PLATFORM_SRC,
+                       CPPUTEST_TESTRUNNER_SCR],
+        "build_dir": CPPUTEST_LIBRARY,
+        "dependencies": [MBED_LIBRARIES],
+        'inc_dirs': [CPPUTEST_INC, CPPUTEST_PLATFORM_INC,
+                     CPPUTEST_TESTRUNNER_INC, TEST_MBED_LIB],
+        'inc_dirs_ext': [CPPUTEST_INC_EXT],
+        'macros': ["CPPUTEST_USE_MEM_LEAK_DETECTION=0",
+                   "CPPUTEST_USE_STD_CPP_LIB=0", "CPPUTEST=1"],
+    },
+]
+
+
+LIBRARY_MAP = dict([(library['id'], library) for library in LIBRARIES])
+
+
+class Library(object):
+    """A library representation that allows for querying of support"""
+    def __init__(self, lib_id):
+        lib = LIBRARY_MAP[lib_id]
+        self.supported = lib.get("supported", DEFAULT_SUPPORT)
+        self.dependencies = lib.get("dependencies", None)
+        # Include dirs required by library build
+        self.inc_dirs = lib.get("inc_dirs", None)
+        # Include dirs required by others to use with this library
+        self.inc_dirs_ext = lib.get("inc_dirs_ext", None)
+        # Additional macros you want to define when building library
+        self.macros = lib.get("macros", None)
+
+        self.source_dir = lib["source_dir"]
+        self.build_dir = lib["build_dir"]
+
+    def is_supported(self, target, toolchain):
+        """Check if a target toolchain combination is supported
+
+        Positional arguments:
+        target - the MCU or board
+        toolchain - the compiler
+        """
+        if not hasattr(self, 'supported'):
+            return True
+        return (target.name in self.supported) and \
+            (toolchain in self.supported[target.name])
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/libraries.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/libraries.pyc
new file mode 100755
index 0000000..05d81a6
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/libraries.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/make.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/make.py
new file mode 100755
index 0000000..060a6bc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/make.py
@@ -0,0 +1,344 @@
+#! /usr/bin/env python2
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+TEST BUILD & RUN
+"""
+import sys
+import json
+from time import sleep
+from shutil import copy
+from os.path import join, abspath, dirname
+from json import load, dump
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.utils import args_error
+from tools.utils import NotSupportedException
+from tools.paths import BUILD_DIR
+from tools.paths import MBED_LIBRARIES
+from tools.paths import RPC_LIBRARY
+from tools.paths import USB_LIBRARIES
+from tools.paths import DSP_LIBRARIES
+from tools.tests import TESTS, Test, TEST_MAP
+from tools.tests import TEST_MBED_LIB
+from tools.tests import test_known, test_name_known
+from tools.targets import TARGET_MAP
+from tools.options import get_default_options_parser
+from tools.options import extract_profile
+from tools.options import extract_mcus
+from tools.build_api import build_project
+from tools.build_api import mcu_toolchain_matrix
+from tools.build_api import mcu_toolchain_list
+from tools.build_api import mcu_target_list
+from tools.build_api import merge_build_data
+from utils import argparse_filestring_type
+from utils import argparse_many
+from utils import argparse_dir_not_parent
+from tools.toolchains import mbedToolchain, TOOLCHAIN_CLASSES, TOOLCHAIN_PATHS
+from tools.settings import CLI_COLOR_MAP
+
+if __name__ == '__main__':
+    # Parse Options
+    parser = get_default_options_parser(add_app_config=True)
+    group = parser.add_mutually_exclusive_group(required=False)
+    group.add_argument(
+        "-p",
+        type=argparse_many(test_known),
+        dest="program",
+        help="The index of the desired test program: [0-%d]" % (len(TESTS)-1))
+
+    group.add_argument(
+        "-n",
+        type=argparse_many(test_name_known),
+        dest="program",
+        help="The name of the desired test program")
+
+    parser.add_argument(
+        "-j", "--jobs",
+        type=int,
+        dest="jobs",
+        default=0,
+        help="Number of concurrent jobs. Default: 0/auto (based on host machine's number of CPUs)")
+
+    parser.add_argument(
+        "-v", "--verbose",
+        action="store_true",
+        dest="verbose",
+        default=False,
+        help="Verbose diagnostic output")
+
+    parser.add_argument(
+        "--silent",
+        action="store_true",
+        dest="silent",
+        default=False,
+        help="Silent diagnostic output (no copy, compile notification)")
+
+    parser.add_argument(
+        "-D",
+        action="append",
+        dest="macros",
+        help="Add a macro definition")
+
+    group.add_argument(
+        "-S", "--supported-toolchains",
+        dest="supported_toolchains",
+        default=False,
+        const="matrix",
+        choices=["matrix", "toolchains", "targets"],
+        nargs="?",
+        help="Displays supported matrix of MCUs and toolchains")
+
+    parser.add_argument(
+        '-f', '--filter',
+        dest='general_filter_regex',
+        default=None,
+        help='For some commands you can use filter to filter out results')
+
+    parser.add_argument(
+        "--stats-depth",
+        type=int,
+        dest="stats_depth",
+        default=2,
+        help="Depth level for static memory report")
+
+    # Local run
+    parser.add_argument("--automated", action="store_true", dest="automated",
+                      default=False, help="Automated test")
+    parser.add_argument("--host", dest="host_test",
+                      default=None, help="Host test")
+    parser.add_argument("--extra", dest="extra",
+                      default=None, help="Extra files")
+    parser.add_argument("--peripherals", dest="peripherals",
+                      default=None, help="Required peripherals")
+    parser.add_argument("--dep", dest="dependencies",
+                      default=None, help="Dependencies")
+    parser.add_argument("--source", dest="source_dir", type=argparse_filestring_type,
+                       default=None, help="The source (input) directory", action="append")
+    parser.add_argument("--duration", type=int, dest="duration",
+                      default=None, help="Duration of the test")
+    parser.add_argument("--build", dest="build_dir", type=argparse_dir_not_parent(ROOT),
+                      default=None, help="The build (output) directory")
+    parser.add_argument("-N", "--artifact-name", dest="artifact_name",
+                      default=None, help="The built project's name")
+    parser.add_argument("-d", "--disk", dest="disk",
+                      default=None, help="The mbed disk")
+    parser.add_argument("-s", "--serial", dest="serial",
+                      default=None, help="The mbed serial port")
+    parser.add_argument("-b", "--baud", type=int, dest="baud",
+                      default=None, help="The mbed serial baud rate")
+    group.add_argument("-L", "--list-tests", action="store_true", dest="list_tests",
+                      default=False, help="List available tests in order and exit")
+
+    # Ideally, all the tests with a single "main" thread can be run with, or
+    # without the usb, dsp
+    parser.add_argument("--rpc",
+                      action="store_true", dest="rpc",
+                      default=False, help="Link with RPC library")
+
+    parser.add_argument("--usb",
+                      action="store_true",
+                      dest="usb",
+                      default=False,
+                      help="Link with USB Device library")
+
+    parser.add_argument("--dsp",
+                      action="store_true",
+                      dest="dsp",
+                      default=False,
+                      help="Link with DSP library")
+
+    parser.add_argument("--testlib",
+                      action="store_true",
+                      dest="testlib",
+                      default=False,
+                      help="Link with mbed test library")
+
+    parser.add_argument("--build-data",
+                        dest="build_data",
+                        default=None,
+                        help="Dump build_data to this file")
+
+    # Specify a different linker script
+    parser.add_argument("-l", "--linker", dest="linker_script",
+                      type=argparse_filestring_type,
+                      default=None, help="use the specified linker script")
+
+    options = parser.parse_args()
+
+    # Only prints matrix of supported toolchains
+    if options.supported_toolchains:
+        if options.supported_toolchains == "matrix":
+            print mcu_toolchain_matrix(platform_filter=options.general_filter_regex)
+        elif options.supported_toolchains == "toolchains":
+            toolchain_list = mcu_toolchain_list()
+            # Only print the lines that matter
+            for line in toolchain_list.split("\n"):
+                if not "mbed" in line:
+                    print line
+        elif options.supported_toolchains == "targets":
+            print mcu_target_list()
+        exit(0)
+
+    # Print available tests in order and exit
+    if options.list_tests is True:
+        print '\n'.join(map(str, sorted(TEST_MAP.values())))
+        sys.exit()
+
+    # force program to "0" if a source dir is specified
+    if options.source_dir is not None:
+        p = 0
+    else:
+    # Program Number or name
+        p = options.program
+
+    # If 'p' was set via -n to list of numbers make this a single element integer list
+    if type(p) != type([]):
+        p = [p]
+
+    # Target
+    if options.mcu is None :
+        args_error(parser, "argument -m/--mcu is required")
+    mcu = extract_mcus(parser, options)[0]
+
+    # Toolchain
+    if options.tool is None:
+        args_error(parser, "argument -t/--tool is required")
+    toolchain = options.tool[0]
+
+    if (options.program is None) and (not options.source_dir):
+        args_error(parser, "one of -p, -n, or --source is required")
+
+    if options.source_dir and not options.build_dir:
+        args_error(parser, "argument --build is required when argument --source is provided")
+
+
+    if options.color:
+        # This import happens late to prevent initializing colorization when we don't need it
+        import colorize
+        if options.verbose:
+            notify = mbedToolchain.print_notify_verbose
+        else:
+            notify = mbedToolchain.print_notify
+        notify = colorize.print_in_color_notifier(CLI_COLOR_MAP, notify)
+    else:
+        notify = None
+
+    if not TOOLCHAIN_CLASSES[toolchain].check_executable():
+        search_path = TOOLCHAIN_PATHS[toolchain] or "No path set"
+        args_error(parser, "Could not find executable for %s.\n"
+                           "Currently set search path: %s"
+                           %(toolchain,search_path))
+
+    # Test
+    build_data_blob = {} if options.build_data else None
+    for test_no in p:
+        test = Test(test_no)
+        if options.automated is not None:    test.automated = options.automated
+        if options.dependencies is not None: test.dependencies = options.dependencies
+        if options.host_test is not None:    test.host_test = options.host_test;
+        if options.peripherals is not None:  test.peripherals = options.peripherals;
+        if options.duration is not None:     test.duration = options.duration;
+        if options.extra is not None:        test.extra_files = options.extra
+
+        if not test.is_supported(mcu, toolchain):
+            print 'The selected test is not supported on target %s with toolchain %s' % (mcu, toolchain)
+            sys.exit()
+
+        # Linking with extra libraries
+        if options.rpc:      test.dependencies.append(RPC_LIBRARY)
+        if options.usb:      test.dependencies.append(USB_LIBRARIES)
+        if options.dsp:      test.dependencies.append(DSP_LIBRARIES)
+        if options.testlib:  test.dependencies.append(TEST_MBED_LIB)
+
+        build_dir = join(BUILD_DIR, "test", mcu, toolchain, test.id)
+        if options.source_dir is not None:
+            test.source_dir = options.source_dir
+            build_dir = options.source_dir
+
+        if options.build_dir is not None:
+            build_dir = options.build_dir
+
+        try:
+            bin_file = build_project(test.source_dir, build_dir, mcu, toolchain,
+                                     set(test.dependencies),
+                                     linker_script=options.linker_script,
+                                     clean=options.clean,
+                                     verbose=options.verbose,
+                                     notify=notify,
+                                     report=build_data_blob,
+                                     silent=options.silent,
+                                     macros=options.macros,
+                                     jobs=options.jobs,
+                                     name=options.artifact_name,
+                                     app_config=options.app_config,
+                                     inc_dirs=[dirname(MBED_LIBRARIES)],
+                                     build_profile=extract_profile(parser,
+                                                                   options,
+                                                                   toolchain),
+                                     stats_depth=options.stats_depth)
+            print 'Image: %s'% bin_file
+
+            if options.disk:
+                # Simple copy to the mbed disk
+                copy(bin_file, options.disk)
+
+            if options.serial:
+                # Import pyserial: https://pypi.python.org/pypi/pyserial
+                from serial import Serial
+
+                sleep(TARGET_MAP[mcu].program_cycle_s)
+
+                serial = Serial(options.serial, timeout = 1)
+                if options.baud:
+                    serial.setBaudrate(options.baud)
+
+                serial.flushInput()
+                serial.flushOutput()
+
+                try:
+                    serial.sendBreak()
+                except:
+                    # In linux a termios.error is raised in sendBreak and in setBreak.
+                    # The following setBreak() is needed to release the reset signal on the target mcu.
+                    try:
+                        serial.setBreak(False)
+                    except:
+                        pass
+
+                while True:
+                    c = serial.read(512)
+                    sys.stdout.write(c)
+                    sys.stdout.flush()
+
+        except KeyboardInterrupt, e:
+            print "\n[CTRL+c] exit"
+        except NotSupportedException as e:
+            print "\nCould not compile for %s: %s" % (mcu, str(e))
+        except Exception,e:
+            if options.verbose:
+                import traceback
+                traceback.print_exc(file=sys.stdout)
+            else:
+                print "[ERROR] %s" % str(e)
+
+            sys.exit(1)
+    if options.build_data:
+        merge_build_data(options.build_data, build_data_blob, "application")
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/make.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/make.pyc
new file mode 100755
index 0000000..61843fa
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/make.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/memap.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/memap.py
new file mode 100755
index 0000000..a2efd0e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/memap.py
@@ -0,0 +1,747 @@
+#!/usr/bin/env python
+
+"""Memory Map File Analyser for ARM mbed"""
+
+import sys
+import os
+import re
+import csv
+import json
+import argparse
+from copy import deepcopy
+from prettytable import PrettyTable
+
+from utils import argparse_filestring_type, \
+    argparse_lowercase_hyphen_type, argparse_uppercase_type
+
+RE_ARMCC = re.compile(
+    r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$')
+RE_IAR = re.compile(
+    r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s'
+    r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$')
+
+RE_CMDLINE_FILE_IAR = re.compile(r'^#\s+(.+\.o)')
+RE_LIBRARY_IAR = re.compile(r'^(.+\.a)\:.+$')
+RE_OBJECT_LIBRARY_IAR = re.compile(r'^\s+(.+\.o)\s.*')
+
+RE_OBJECT_FILE_GCC = re.compile(r'^(.+\/.+\.o)$')
+RE_LIBRARY_OBJECT_GCC = re.compile(r'^.+\/lib(.+\.a)\((.+\.o)\)$')
+RE_STD_SECTION_GCC = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$')
+RE_FILL_SECTION_GCC = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$')
+
+RE_OBJECT_ARMCC = re.compile(r'(.+\.(l|ar))\((.+\.o)\)')
+
+
+class MemapParser(object):
+    """An object that represents parsed results, parses the memory map files,
+    and writes out different file types of memory results
+    """
+
+    print_sections = ('.text', '.data', '.bss')
+
+    misc_flash_sections = ('.interrupts', '.flash_config')
+
+    other_sections = ('.interrupts_ram', '.init', '.ARM.extab',
+                      '.ARM.exidx', '.ARM.attributes', '.eh_frame',
+                      '.init_array', '.fini_array', '.jcr', '.stab',
+                      '.stabstr', '.ARM.exidx', '.ARM')
+
+    # sections to print info (generic for all toolchains)
+    sections = ('.text', '.data', '.bss', '.heap', '.stack')
+
+    def __init__(self):
+        """ General initialization
+        """
+
+        # list of all modules and their sections
+        self.modules = dict()       # full list - doesn't change with depth
+        self.short_modules = dict() # short version with specific depth
+
+        # sections must be defined in this order to take irrelevant out
+        self.all_sections = self.sections + self.other_sections + \
+                            self.misc_flash_sections + ('unknown', 'OUTPUT')
+
+        # Memory report (sections + summary)
+        self.mem_report = []
+
+        # Just the memory summary section
+        self.mem_summary = dict()
+
+        self.subtotal = dict()
+
+        self.misc_flash_mem = 0
+
+        # Modules passed to the linker on the command line
+        # this is a dict because modules are looked up by their basename
+        self.cmd_modules = {}
+
+
+    def module_add(self, object_name, size, section):
+        """ Adds a module / section to the list
+
+        Positional arguments:
+        object_name - name of the entry to add
+        size - the size of the module being added
+        section - the section the module contributes to
+        """
+
+        if not object_name or not size or not section:
+            return
+
+        if object_name in self.modules:
+            self.modules[object_name].setdefault(section, 0)
+            self.modules[object_name][section] += size
+            return
+
+        obj_split = os.sep + os.path.basename(object_name)
+        for module_path, contents in self.modules.items():
+            if module_path.endswith(obj_split) or module_path == object_name:
+                contents.setdefault(section, 0)
+                contents[section] += size
+                return
+
+        new_module = {section: size}
+        self.modules[object_name] = new_module
+
+    def module_replace(self, old_object, new_object):
+        """ Replaces an object name with a new one
+        """
+        if old_object in self.modules:
+            self.modules[new_object] = self.modules[old_object]
+            del self.modules[old_object]
+
+    def check_new_section_gcc(self, line):
+        """ Check whether a new section in a map file has been detected (only
+        applies to gcc)
+
+        Positional arguments:
+        line - the line to check for a new section
+        """
+
+        for i in self.all_sections:
+            if line.startswith(i):
+                # should name of the section (assuming it's a known one)
+                return i
+
+        if line.startswith('.'):
+            return 'unknown'     # all others are classified are unknown
+        else:
+            return False         # everything else, means no change in section
+
+
+    def parse_object_name_gcc(self, line):
+        """ Parse a path to object file
+
+        Positional arguments:
+        txt - the path to parse the object and module name from
+        """
+
+        line = line.replace('\\', '/')
+        test_re_mbed_os_name = re.match(RE_OBJECT_FILE_GCC, line)
+
+        if test_re_mbed_os_name:
+
+            object_name = test_re_mbed_os_name.group(1)
+
+            # corner case: certain objects are provided by the GCC toolchain
+            if 'arm-none-eabi' in line:
+                return '[lib]/misc/' + object_name
+            return object_name
+
+        else:
+
+            test_re_obj_name = re.match(RE_LIBRARY_OBJECT_GCC, line)
+
+            if test_re_obj_name:
+                object_name = test_re_obj_name.group(1) + '/' + \
+                              test_re_obj_name.group(2)
+
+                return '[lib]/' + object_name
+
+            else:
+                print "Unknown object name found in GCC map file: %s" % line
+                return '[misc]'
+
+    def parse_section_gcc(self, line):
+        """ Parse data from a section of gcc map file
+
+        examples:
+                        0x00004308       0x7c ./BUILD/K64F/GCC_ARM/mbed-os/hal/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.o
+         .text          0x00000608      0x198 ./BUILD/K64F/GCC_ARM/mbed-os/core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/HAL_CM4.o
+
+        Positional arguments:
+        line - the line to parse a section from
+        """
+
+        is_fill = re.match(RE_FILL_SECTION_GCC, line)
+        if is_fill:
+            o_name = '[fill]'
+            o_size = int(is_fill.group(2), 16)
+            return [o_name, o_size]
+
+        is_section = re.match(RE_STD_SECTION_GCC, line)
+        if is_section:
+            o_size = int(is_section.group(2), 16)
+            if o_size:
+                o_name = self.parse_object_name_gcc(is_section.group(3))
+                return [o_name, o_size]
+
+        return ["", 0]
+
+    def parse_map_file_gcc(self, file_desc):
+        """ Main logic to decode gcc map files
+
+        Positional arguments:
+        file_desc - a stream object to parse as a gcc map file
+        """
+
+        current_section = 'unknown'
+
+        with file_desc as infile:
+            for line in infile:
+                if line.startswith('Linker script and memory map'):
+                    current_section = "unknown"
+                    break
+
+            for line in infile:
+                next_section = self.check_new_section_gcc(line)
+
+                if next_section == "OUTPUT":
+                    break
+                elif next_section:
+                    current_section = next_section
+
+                object_name, object_size = self.parse_section_gcc(line)
+
+                self.module_add(object_name, object_size, current_section)
+
+        common_prefix = os.path.dirname(os.path.commonprefix([
+            o for o in self.modules.keys() if (o.endswith(".o") and not o.startswith("[lib]"))]))
+        new_modules = {}
+        for name, stats in self.modules.items():
+            if name.startswith("[lib]"):
+                new_modules[name] = stats
+            elif name.endswith(".o"):
+                new_modules[os.path.relpath(name, common_prefix)] = stats
+            else:
+                new_modules[name] = stats
+        self.modules = new_modules
+
+    def parse_object_name_armcc(self, line):
+        """ Parse object file
+
+        Positional arguments:
+        line - the line containing the object or library
+        """
+
+        # simple object (not library)
+        if line[-2] == '.' and line[-1] == 'o':
+            return line
+
+        else:
+            is_obj = re.match(RE_OBJECT_ARMCC, line)
+            if is_obj:
+                object_name = os.path.basename(is_obj.group(1)) + '/' + is_obj.group(3)
+                return '[lib]/' + object_name
+            else:
+                print "Malformed input found when parsing ARMCC map: %s" % line
+                return '[misc]'
+
+
+
+    def parse_section_armcc(self, line):
+        """ Parse data from an armcc map file
+
+        Examples of armcc map file:
+            Base_Addr    Size         Type   Attr      Idx    E Section Name        Object
+            0x00000000   0x00000400   Data   RO        11222    RESET               startup_MK64F12.o
+            0x00000410   0x00000008   Code   RO        49364  * !!!main             c_w.l(__main.o)
+
+        Positional arguments:
+        line - the line to parse the section data from
+        """
+
+        test_re_armcc = re.match(RE_ARMCC, line)
+
+        if test_re_armcc:
+
+            size = int(test_re_armcc.group(2), 16)
+
+            if test_re_armcc.group(4) == 'RO':
+                section = '.text'
+            else:
+                if test_re_armcc.group(3) == 'Data':
+                    section = '.data'
+                elif test_re_armcc.group(3) == 'Zero':
+                    section = '.bss'
+                else:
+                    print "Malformed input found when parsing armcc map: %s" %\
+                          line
+
+            # check name of object or library
+            object_name = self.parse_object_name_armcc(\
+                test_re_armcc.group(6))
+
+            return [object_name, size, section]
+
+        else:
+            return ["", 0, ""]
+
+    def parse_object_name_iar(self, object_name):
+        """ Parse object file
+
+        Positional arguments:
+        line - the line containing the object or library
+        """
+
+        # simple object (not library)
+        if object_name.endswith(".o"):
+            try:
+                return self.cmd_modules[object_name]
+            except KeyError:
+                return object_name
+        else:
+            return '[misc]'
+
+
+    def parse_section_iar(self, line):
+        """ Parse data from an IAR map file
+
+        Examples of IAR map file:
+         Section             Kind        Address     Size  Object
+         .intvec             ro code  0x00000000    0x198  startup_MK64F12.o [15]
+         .rodata             const    0x00000198      0x0  zero_init3.o [133]
+         .iar.init_table     const    0x00008384     0x2c  - Linker created -
+         Initializer bytes   const    0x00000198     0xb2  <for P3 s0>
+         .data               inited   0x20000000     0xd4  driverAtmelRFInterface.o [70]
+         .bss                zero     0x20000598    0x318  RTX_Conf_CM.o [4]
+         .iar.dynexit        uninit   0x20001448    0x204  <Block tail>
+           HEAP              uninit   0x20001650  0x10000  <Block tail>
+
+        Positional_arguments:
+        line - the line to parse section data from
+        """
+
+        test_re_iar = re.match(RE_IAR, line)
+
+        if test_re_iar:
+
+            size = int(test_re_iar.group(4), 16)
+
+            if (test_re_iar.group(2) == 'const' or
+                test_re_iar.group(2) == 'ro code'):
+                section = '.text'
+            elif (test_re_iar.group(2) == 'zero' or
+                  test_re_iar.group(2) == 'uninit'):
+                if test_re_iar.group(1)[0:4] == 'HEAP':
+                    section = '.heap'
+                elif test_re_iar.group(1)[0:6] == 'CSTACK':
+                    section = '.stack'
+                else:
+                    section = '.bss' #  default section
+
+            elif test_re_iar.group(2) == 'inited':
+                section = '.data'
+            else:
+                print "Malformed input found when parsing IAR map: %s" % line
+
+            # lookup object in dictionary and return module name
+            object_name = self.parse_object_name_iar(test_re_iar.group(5))
+
+            return [object_name, size, section]
+
+        else:
+            return ["", 0, ""] # no valid entry
+
+    def parse_map_file_armcc(self, file_desc):
+        """ Main logic to decode armc5 map files
+
+        Positional arguments:
+        file_desc - a file like object to parse as an armc5 map file
+        """
+
+        with file_desc as infile:
+
+            # Search area to parse
+            for line in infile:
+                if line.startswith('    Base Addr    Size'):
+                    break
+
+            # Start decoding the map file
+            for line in infile:
+                self.module_add(*self.parse_section_armcc(line))
+
+        common_prefix = os.path.dirname(os.path.commonprefix([
+            o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))]))
+        new_modules = {}
+        for name, stats in self.modules.items():
+            if name == "anon$$obj.o" or name.startswith("[lib]"):
+                new_modules[name] = stats
+            elif name.endswith(".o"):
+                new_modules[os.path.relpath(name, common_prefix)] = stats
+            else:
+                new_modules[name] = stats
+        self.modules = new_modules
+
+
+
+    def check_new_library_iar(self, line):
+        """
+        Searches for libraries and returns name. Example:
+        m7M_tls.a: [43]
+
+        """
+
+
+        test_address_line = re.match(RE_LIBRARY_IAR, line)
+
+        if test_address_line:
+            return test_address_line.group(1)
+        else:
+            return ""
+
+    def check_new_object_lib_iar(self, line):
+        """
+        Searches for objects within a library section and returns name. Example:
+        rt7M_tl.a: [44]
+            ABImemclr4.o                 6
+            ABImemcpy_unaligned.o      118
+            ABImemset48.o               50
+            I64DivMod.o                238
+            I64DivZer.o                  2
+
+        """
+
+        test_address_line = re.match(RE_OBJECT_LIBRARY_IAR, line)
+
+        if test_address_line:
+            return test_address_line.group(1)
+        else:
+            return ""
+
+    def parse_iar_command_line(self, lines):
+        """Parse the files passed on the command line to the iar linker
+
+        Positional arguments:
+        lines -- an iterator over the lines within a file
+        """
+        for line in lines:
+            if line.startswith("*"):
+                break
+            is_cmdline_file = RE_CMDLINE_FILE_IAR.match(line)
+            if is_cmdline_file:
+                full_path = is_cmdline_file.group(1)
+                self.cmd_modules[os.path.basename(full_path)] = full_path
+
+        common_prefix = os.path.dirname(os.path.commonprefix(self.cmd_modules.values()))
+        self.cmd_modules = {s: os.path.relpath(f, common_prefix)
+                            for s, f in self.cmd_modules.items()}
+
+
+    def parse_map_file_iar(self, file_desc):
+        """ Main logic to decode IAR map files
+
+        Positional arguments:
+        file_desc - a file like object to parse as an IAR map file
+        """
+
+        with file_desc as infile:
+            self.parse_iar_command_line(infile)
+
+            for line in infile:
+                if line.startswith('  Section  '):
+                    break
+
+            for line in infile:
+                self.module_add(*self.parse_section_iar(line))
+
+                if line.startswith('*** MODULE SUMMARY'): # finish section
+                    break
+
+            current_library = ""
+            for line in infile:
+
+                library = self.check_new_library_iar(line)
+
+                if library:
+                    current_library = library
+
+                object_name = self.check_new_object_lib_iar(line)
+
+                if object_name and current_library:
+                    temp = '[lib]' + '/'+ current_library + '/'+ object_name
+                    self.module_replace(object_name, temp)
+
+
+    def reduce_depth(self, depth):
+        """
+        populates the short_modules attribute with a truncated module list
+
+        (1) depth = 1:
+        main.o
+        mbed-os
+
+        (2) depth = 2:
+        main.o
+        mbed-os/test.o
+        mbed-os/drivers
+
+        """
+        if depth == 0 or depth == None:
+            self.short_modules = deepcopy(self.modules)
+        else:
+            self.short_modules = dict()
+            for module_name, v in self.modules.items():
+                split_name = module_name.split('/')
+                if split_name[0] == '':
+                    split_name = split_name[1:]
+                new_name = "/".join(split_name[:depth])
+                self.short_modules.setdefault(new_name, {})
+                for section_idx, value in v.items():
+                    self.short_modules[new_name].setdefault(section_idx, 0)
+                    self.short_modules[new_name][section_idx] += self.modules[module_name][section_idx]
+
+
+    export_formats = ["json", "csv-ci", "table"]
+
+    def generate_output(self, export_format, depth, file_output=None):
+        """ Generates summary of memory map data
+
+        Positional arguments:
+        export_format - the format to dump
+
+        Keyword arguments:
+        file_desc - descriptor (either stdout or file)
+        depth - directory depth on report
+
+        Returns: generated string for the 'table' format, otherwise None
+        """
+
+        self.reduce_depth(depth)
+        self.compute_report()
+
+        try:
+            if file_output:
+                file_desc = open(file_output, 'wb')
+            else:
+                file_desc = sys.stdout
+        except IOError as error:
+            print "I/O error({0}): {1}".format(error.errno, error.strerror)
+            return False
+
+        to_call = {'json': self.generate_json,
+                   'csv-ci': self.generate_csv,
+                   'table': self.generate_table}[export_format]
+        output = to_call(file_desc)
+
+        if file_desc is not sys.stdout:
+            file_desc.close()
+
+        return output
+
+    def generate_json(self, file_desc):
+        """Generate a json file from a memory map
+
+        Positional arguments:
+        file_desc - the file to write out the final report to
+        """
+        file_desc.write(json.dumps(self.mem_report, indent=4))
+        file_desc.write('\n')
+
+        return None
+
+    def generate_csv(self, file_desc):
+        """Generate a CSV file from a memoy map
+
+        Positional arguments:
+        file_desc - the file to write out the final report to
+        """
+        csv_writer = csv.writer(file_desc, delimiter=',',
+                                quoting=csv.QUOTE_MINIMAL)
+
+        csv_module_section = []
+        csv_sizes = []
+        for i in sorted(self.short_modules):
+            for k in self.print_sections:
+                csv_module_section += [i+k]
+                csv_sizes += [self.short_modules[i][k]]
+
+        csv_module_section += ['static_ram']
+        csv_sizes += [self.mem_summary['static_ram']]
+
+        csv_module_section += ['total_flash']
+        csv_sizes += [self.mem_summary['total_flash']]
+
+        csv_writer.writerow(csv_module_section)
+        csv_writer.writerow(csv_sizes)
+
+        return None
+
+    def generate_table(self, file_desc):
+        """Generate a table from a memoy map
+
+        Returns: string of the generated table
+        """
+        # Create table
+        columns = ['Module']
+        columns.extend(self.print_sections)
+
+        table = PrettyTable(columns)
+        table.align["Module"] = "l"
+        for col in self.print_sections:
+            table.align[col] = 'r'
+
+        for i in list(self.print_sections):
+            table.align[i] = 'r'
+
+        for i in sorted(self.short_modules):
+            row = [i]
+
+            for k in self.print_sections:
+                row.append(self.short_modules[i][k])
+
+            table.add_row(row)
+
+        subtotal_row = ['Subtotals']
+        for k in self.print_sections:
+            subtotal_row.append(self.subtotal[k])
+
+        table.add_row(subtotal_row)
+
+        output = table.get_string()
+        output += '\n'
+
+        output += "Total Static RAM memory (data + bss): %s bytes\n" % \
+                        str(self.mem_summary['static_ram'])
+        output += "Total Flash memory (text + data): %s bytes\n" % \
+                        str(self.mem_summary['total_flash'])
+
+        return output
+
+    toolchains = ["ARM", "ARM_STD", "ARM_MICRO", "GCC_ARM", "GCC_CR", "IAR"]
+
+    def compute_report(self):
+        """ Generates summary of memory usage for main areas
+        """
+        for k in self.sections:
+            self.subtotal[k] = 0
+
+        for i in self.short_modules:
+            for k in self.sections:
+                self.short_modules[i].setdefault(k, 0)
+                self.subtotal[k] += self.short_modules[i][k]
+
+        self.mem_summary = {
+            'static_ram': (self.subtotal['.data'] + self.subtotal['.bss']),
+            'total_flash': (self.subtotal['.text'] + self.subtotal['.data']),
+        }
+
+        self.mem_report = []
+        for i in sorted(self.short_modules):
+            self.mem_report.append({
+                "module":i,
+                "size":{
+                    k: self.short_modules[i][k] for k in self.print_sections
+                }
+            })
+
+        self.mem_report.append({
+            'summary': self.mem_summary
+        })
+
+    def parse(self, mapfile, toolchain):
+        """ Parse and decode map file depending on the toolchain
+
+        Positional arguments:
+        mapfile - the file name of the memory map file
+        toolchain - the toolchain used to create the file
+        """
+
+        result = True
+        try:
+            with open(mapfile, 'r') as file_input:
+                if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"):
+                    self.parse_map_file_armcc(file_input)
+                elif toolchain == "GCC_ARM" or toolchain == "GCC_CR":
+                    self.parse_map_file_gcc(file_input)
+                elif toolchain == "IAR":
+                    self.parse_map_file_iar(file_input)
+                else:
+                    result = False
+
+        except IOError as error:
+            print "I/O error({0}): {1}".format(error.errno, error.strerror)
+            result = False
+        return result
+
+def main():
+    """Entry Point"""
+
+    version = '0.4.0'
+
+    # Parser handling
+    parser = argparse.ArgumentParser(
+        description="Memory Map File Analyser for ARM mbed\nversion %s" %
+        version)
+
+    parser.add_argument(
+        'file', type=argparse_filestring_type, help='memory map file')
+
+    parser.add_argument(
+        '-t', '--toolchain', dest='toolchain',
+        help='select a toolchain used to build the memory map file (%s)' %
+        ", ".join(MemapParser.toolchains),
+        required=True,
+        type=argparse_uppercase_type(MemapParser.toolchains, "toolchain"))
+
+    parser.add_argument(
+        '-d', '--depth', dest='depth', type=int,
+        help='specify directory depth level to display report', required=False)
+
+    parser.add_argument(
+        '-o', '--output', help='output file name', required=False)
+
+    parser.add_argument(
+        '-e', '--export', dest='export', required=False, default='table',
+        type=argparse_lowercase_hyphen_type(MemapParser.export_formats,
+                                            'export format'),
+        help="export format (examples: %s: default)" %
+        ", ".join(MemapParser.export_formats))
+
+    parser.add_argument('-v', '--version', action='version', version=version)
+
+    # Parse/run command
+    if len(sys.argv) <= 1:
+        parser.print_help()
+        sys.exit(1)
+
+    args = parser.parse_args()
+
+    # Create memap object
+    memap = MemapParser()
+
+    # Parse and decode a map file
+    if args.file and args.toolchain:
+        if memap.parse(args.file, args.toolchain) is False:
+            sys.exit(0)
+
+    if args.depth is None:
+        depth = 2  # default depth level
+    else:
+        depth = args.depth
+
+    returned_string = None
+    # Write output in file
+    if args.output != None:
+        returned_string = memap.generate_output(args.export, \
+            depth, args.output)
+    else: # Write output in screen
+        returned_string = memap.generate_output(args.export, depth)
+
+    if args.export == 'table' and returned_string:
+        print returned_string
+
+    sys.exit(0)
+
+if __name__ == "__main__":
+    main()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/memap.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/memap.pyc
new file mode 100755
index 0000000..411e188
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/memap.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/misc/find_c_includes.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/misc/find_c_includes.py
new file mode 100755
index 0000000..e24c6d1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/misc/find_c_includes.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python
+
+import os
+import re
+
+def main(path='.', pattern=r'#include\s+"([^"]*\.(?:c|cpp))"'):
+    pattern = re.compile(pattern)
+
+    for root, dirs, files in os.walk(path, followlinks=True):
+        for file in files:
+            with open(os.path.join(root, file)) as f:
+                for line in f.read().splitlines():
+                    m = re.search(pattern, line)
+                    if m:
+                        print os.path.relpath(os.path.join(root, m.group(1)))
+
+
+if __name__ == "__main__":
+    import sys
+    main(*sys.argv[1:])
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/misc/remove-device-h.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/misc/remove-device-h.py
new file mode 100755
index 0000000..bbed161
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/misc/remove-device-h.py
@@ -0,0 +1,216 @@
+import json
+import os
+import stat
+import re
+from collections import OrderedDict
+from subprocess import Popen
+
+git_processes = []
+
+class MyJSONEncoder(json.JSONEncoder):
+    def __init__(self, *args, **kwargs):
+        super(MyJSONEncoder, self).__init__(*args, **kwargs)
+        self.current_indent = 0
+        self.current_indent_str = ""
+
+
+    def encode(self, o):
+        #Special Processing for lists
+        if isinstance(o, (list, tuple)):
+            primitives_only = True
+            for item in o:
+                if isinstance(item, (list, tuple, dict)):
+                    primitives_only = False
+                    break
+            output = []
+            if primitives_only:
+                for item in o:
+                    output.append(json.dumps(item))
+                return "[" + ", ".join(output) + "]"
+            else:
+                self.current_indent += self.indent
+                self.current_indent_str = " " * self.current_indent
+                for item in o:
+                    output.append(self.current_indent_str + self.encode(item))
+                self.current_indent -= self.indent
+                self.current_indent_str = " " * self.current_indent
+                return "[\n" + ",\n".join(output) + "\n" + self.current_indent_str + "]"
+        elif isinstance(o, dict):
+            primitives_only = True
+            for item in o.values():
+                if isinstance(item, (list, tuple, dict)):
+                    primitives_only = False
+                    break
+            output = []
+            if primitives_only and len(o) < 3:
+                for key, value in o.iteritems():
+                    output.append(json.dumps(key) + ": " + self.encode(value))
+                return "{" + ", ".join(output) + "}"
+            else:
+                self.current_indent += self.indent
+                self.current_indent_str = " " * self.current_indent
+                for key, value in o.iteritems():
+                    output.append(self.current_indent_str + json.dumps(key) + ": " + self.encode(value))
+                self.current_indent -= self.indent
+                self.current_indent_str = " " * self.current_indent
+                return "{\n" + ",\n".join(output) + "\n" + self.current_indent_str + "}"
+        else:
+            return json.dumps(o)
+
+def load(path):
+    with open(path, 'r') as f :
+        return json.load(f, object_pairs_hook=OrderedDict)
+
+def dump(path, obj):
+    with os.fdopen(os.open(path, os.O_WRONLY | os.O_CREAT, stat.S_IRUSR | stat.S_IWUSR), 'w') as f :
+        os.chmod(path, stat.S_IRUSR | stat.S_IWUSR)
+        f.write(MyJSONEncoder(indent=4).encode(obj))
+        f.write(u'\n')
+        f.truncate()
+
+def find(stem, path) :
+    for root, directories, files in os.walk(path, followlinks=True) :
+        [dir for dir in directories if dir[0] != '.']
+        if (stem_match(stem,os.path.basename(os.path.normpath(root))) and
+            "device.h" in files) :
+            return os.path.join(root, "device.h")
+
+def find_all_devices(path, verbose=False) :
+    for root, directories, files in os.walk(path, followlinks=True) :
+        [dir for dir in directories if dir[0] != '.']
+        if "device.h" in files :
+            if verbose : print("[VERBOSE] found a device.h file in {}".format(root))
+            yield os.path.join(root, "device.h")
+
+mbed_matcher = re.compile('mbed', re.IGNORECASE)
+def stem_match(stem, thing) :
+    return (stem in thing or
+            re.sub(mbed_matcher, '', stem) in thing)
+
+attr_matcher = re.compile('^#define\W+DEVICE_(\w+)\W+1.*$')
+def parse_attributes(path) :
+    with open(path) as input :
+        for line in input :
+            m = re.match(attr_matcher, line)
+            if m: yield m.group(1)
+
+remove_matcher = re.compile('^#define\W+DEVICE_(\w+)\W+[10].*$')
+def remove_attributes(path) :
+    with open(path) as input :
+        remainder = filter(lambda l: not re.match(remove_matcher, l), input)
+    with open(path,"wb") as output :
+        output.truncate(0)
+        output.write("// The 'provides' section in 'target.json' is now used"+
+                     " to create the device's hardware preprocessor switches.\n")
+        output.write("// Check the 'provides' section of the target description"+
+                     " in 'targets.json' for more details.\n")
+        output.writelines(remainder)
+
+def user_select(things, message) :
+    print(message)
+    for thing, number in zip(things, range(len(things))):
+        print("{} : {}".format(number, thing))
+    selection = None
+    while selection is None :
+        print("please select an integer [0..{}] or specify all".format(len(things) - 1))
+        try :
+            i = raw_input()
+            if i == "all" :
+                selection = "all"
+            else :
+                selection = int(i)
+                if (selection > len(things) or
+                    selection < 0) :
+                    print("selection {} out of range".format(selection))
+                    selection = None
+        except (ValueError, SyntaxError) :
+            print("selection not understood")
+    if selection == "all" :
+        return things
+    else :
+        return [things[selection]]
+
+target_matcher = re.compile("TARGET_")
+def strip_target(str) :
+    return re.sub(target_matcher, "", str)
+
+def add_to_targets(targets, device_file, verbose=False, remove=False) :
+    if verbose : print("[VERBOSE] trying target {}".format(device_file))
+    device = strip_target(os.path.basename(os.path.normpath(os.path.dirname(device_file))))
+    if not device :
+        print("[WARNING] device {} did not have an associated device.h".format(device))
+    else :
+        possible_matches = set([key for key in targets.keys() if stem_match(device, key)])
+        for key, value in targets.iteritems() :
+            for alt in value['extra_labels'] if 'extra_labels' in value else [] :
+                if stem_match(device, alt) : possible_matches.add(key)
+            for alt in value['extra_labels_add'] if 'extra_labels_add' in value else [] :
+                if stem_match(device, alt) : possible_matches.add(key)
+        possible_matches = list(possible_matches)
+        for match in possible_matches :
+            if device == match : possible_matches = [match]
+        if not possible_matches :
+            print("[WARNING] device {} did not have an associated entry in targets.json".format(device))
+            return None
+        elif len(possible_matches) > 1 :
+            message = ("possible matches for file {}".format(device_file))
+            target = user_select(possible_matches, message)
+        else :
+            target = possible_matches
+        attrs = list(parse_attributes(device_file))
+        if attrs :
+            for t in target :
+                targets[t]["device_has"] = sorted(list(set(targets[t].setdefault("device_has",[]) + attrs)))
+                if verbose : print("[VERBOSE] target {} now device_has {}".format(t, attrs))
+            if remove is True:
+                remove_attributes(device_file)
+
+if __name__ == '__main__' :
+    import argparse
+    parser = argparse.ArgumentParser(description='A helpful little script for converting' +
+                                     ' device.h files to parts of the targets.json file')
+    parser.add_argument('-a', '--all', action='store_true',
+                        help='find and convert all available device.h files in the'+
+                        ' directory tree starting at the current directory')
+    parser.add_argument('-f', '--file', nargs='+', help='specify an individual file to '+
+                        'convert from device.h format to a piece of targets.json')
+    parser.add_argument('-t', '--target', nargs='+', help='specify an individual target'+
+                        ' to convert from device.h format to a piece of targets.json')
+    parser.add_argument('-v', '--verbose', action='store_true',
+                        help="print out every target that is updated in the targets.json")
+    parser.add_argument('-r', '--rm', action='store_true',
+                        help="remove the used attributes from a device.h file")
+    args = parser.parse_args()
+    if not args.target and not args.file and not args.all :
+        print("[WARNING] no action specified; auto-formatting targets.json")
+
+    targets_file_name = os.path.join(os.curdir, "hal", "targets.json")
+    try :
+        targets = load(targets_file_name)
+    except OSError :
+        print("[ERROR] did not find targets.json where I expected it {}".format(targets_file_name))
+        exit(1)
+    except ValueError :
+        print("[ERROR] invalid json found in {}".format(targets_file_name))
+        exit(2)
+
+    if args.target :
+        for target in args.target :
+            device_file = find(target, os.curdir)
+            if device_file :
+                add_to_targets(targets, device_file, verbose=args.verbose, remove=args.rm)
+            else :
+                print("[WARNING] could not locate a device file for target {}".format(target))
+
+    if args.file :
+        for file in args.file :
+            add_to_targets(targets, file, verbose=args.verbose, remove=args.rm)
+
+    if args.all :
+        for file in find_all_devices(os.curdir, verbose=args.verbose) :
+            add_to_targets(targets, file, verbose=args.verbose, remove=args.rm)
+
+    dump(targets_file_name, targets)
+
+    for process in git_processes :
+        process.wait()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/options.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/options.py
new file mode 100755
index 0000000..8cfec66
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/options.py
@@ -0,0 +1,145 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from json import load
+from os.path import join, dirname
+from os import listdir
+from argparse import ArgumentParser, ArgumentTypeError
+from tools.toolchains import TOOLCHAINS
+from tools.targets import TARGET_NAMES, Target, update_target_data
+from tools.utils import argparse_force_uppercase_type, \
+    argparse_lowercase_hyphen_type, argparse_many, \
+    argparse_filestring_type, args_error, argparse_profile_filestring_type,\
+    argparse_deprecate
+
+FLAGS_DEPRECATION_MESSAGE = "Please use the --profile argument instead.\n"\
+                            "Documentation may be found in "\
+                            "docs/Toolchain_Profiles.md"
+
+def get_default_options_parser(add_clean=True, add_options=True,
+                               add_app_config=False):
+    """Create a new options parser with the default compiler options added
+
+    Keyword arguments:
+    add_clean - add the clean argument?
+    add_options - add the options argument?
+    """
+    parser = ArgumentParser()
+
+    targetnames = TARGET_NAMES
+    targetnames.sort()
+    toolchainlist = list(TOOLCHAINS)
+    toolchainlist.sort()
+
+    parser.add_argument("-m", "--mcu",
+                        help=("build for the given MCU (%s)" %
+                              ', '.join(targetnames)),
+                        metavar="MCU")
+
+    parser.add_argument("-t", "--tool",
+                        help=("build using the given TOOLCHAIN (%s)" %
+                              ', '.join(toolchainlist)),
+                        metavar="TOOLCHAIN",
+                        type=argparse_many(
+                            argparse_force_uppercase_type(
+                                toolchainlist, "toolchain")))
+
+    parser.add_argument("--color",
+                        help="print Warnings, and Errors in color",
+                        action="store_true", default=False)
+
+    parser.add_argument("--cflags",
+                        type=argparse_deprecate(FLAGS_DEPRECATION_MESSAGE),
+                        help="Deprecated. " + FLAGS_DEPRECATION_MESSAGE)
+
+    parser.add_argument("--asmflags",
+                        type=argparse_deprecate(FLAGS_DEPRECATION_MESSAGE),
+                        help="Deprecated. " + FLAGS_DEPRECATION_MESSAGE)
+
+    parser.add_argument("--ldflags",
+                        type=argparse_deprecate(FLAGS_DEPRECATION_MESSAGE),
+                        help="Deprecated. " + FLAGS_DEPRECATION_MESSAGE)
+
+    if add_clean:
+        parser.add_argument("-c", "--clean", action="store_true", default=False,
+                            help="clean the build directory")
+
+    if add_options:
+        parser.add_argument("--profile", dest="profile", action="append",
+                            type=argparse_profile_filestring_type,
+                            help="Build profile to use. Can be either path to json" \
+                            "file or one of the default one ({})".format(", ".join(list_profiles())),
+                            default=[])
+    if add_app_config:
+        parser.add_argument("--app-config", default=None, dest="app_config",
+                            type=argparse_filestring_type,
+                            help="Path of an app configuration file (Default is to look for 'mbed_app.json')")
+
+    return parser
+
+def list_profiles():
+    """Lists available build profiles
+
+    Checks default profile directory (mbed-os/tools/profiles/) for all the json files and return list of names only
+    """
+    return [fn.replace(".json", "") for fn in listdir(join(dirname(__file__), "profiles")) if fn.endswith(".json")]
+
+def extract_profile(parser, options, toolchain, fallback="develop"):
+    """Extract a Toolchain profile from parsed options
+
+    Positional arguments:
+    parser - parser used to parse the command line arguments
+    options - The parsed command line arguments
+    toolchain - the toolchain that the profile should be extracted for
+    """
+    profiles = []
+    filenames = options.profile or [join(dirname(__file__), "profiles",
+                                         fallback + ".json")]
+    for filename in filenames:
+        contents = load(open(filename))
+        if toolchain not in contents:
+            args_error(parser, ("argument --profile: toolchain {} is not"
+                                " supported by profile {}").format(toolchain,
+                                                                   filename))
+        profiles.append(contents)
+
+    return profiles
+
+def mcu_is_enabled(parser, mcu):
+    if "Cortex-A" in TARGET_MAP[mcu].core:
+        args_error(
+            parser,
+            ("%s Will be supported in mbed OS 5.6. "
+             "To use the %s, please checkout the mbed OS 5.4 release branch. "
+             "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice "
+             "for more information") % (mcu, mcu))
+    return True
+    
+def extract_mcus(parser, options):
+    try:
+        if options.source_dir:
+            for source_dir in options.source_dir:
+                Target.add_extra_targets(source_dir)
+            update_target_data()
+    except KeyError:
+        pass
+    targetnames = TARGET_NAMES
+    targetnames.sort()
+    try:
+        return argparse_many(argparse_force_uppercase_type(targetnames, "MCU"))(options.mcu)
+    except ArgumentTypeError as exc:
+        args_error(parser, "argument -m/--mcu: {}".format(str(exc)))
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/options.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/options.pyc
new file mode 100755
index 0000000..e799542
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/paths.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/paths.py
new file mode 100755
index 0000000..c8e745b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/paths.py
@@ -0,0 +1,87 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from os.path import join
+from os import getenv
+
+# Conventions about the directory structure
+from tools.settings import ROOT, BUILD_DIR
+
+# Allow overriding some of the build parameters using environment variables
+BUILD_DIR = getenv("MBED_BUILD_DIR") or BUILD_DIR
+
+# Embedded Libraries Sources
+LIB_DIR = join(ROOT, "features/unsupported")
+
+TOOLS = join(ROOT, "tools")
+TOOLS_DATA = join(TOOLS, "data")
+TOOLS_BOOTLOADERS = join(TOOLS, "bootloaders")
+
+# mbed libraries
+MBED_HEADER = join(ROOT, "mbed.h")
+MBED_DRIVERS = join(ROOT, "drivers")
+MBED_PLATFORM = join(ROOT, "platform")
+MBED_HAL = join(ROOT, "hal")
+
+MBED_CMSIS_PATH = join(ROOT, "cmsis")
+MBED_TARGETS_PATH = join(ROOT, "targets")
+
+MBED_LIBRARIES = join(BUILD_DIR, "mbed")
+MBED_LIBRARIES_DRIVERS = join(MBED_LIBRARIES, "drivers")
+MBED_LIBRARIES_PLATFORM = join(MBED_LIBRARIES, "platform")
+MBED_LIBRARIES_HAL = join(MBED_LIBRARIES, "hal")
+
+MBED_CONFIG_FILE = join(ROOT, "platform/mbed_lib.json")
+
+# Tests
+TEST_DIR = join(LIB_DIR, "tests")
+HOST_TESTS = join(ROOT, "tools", "host_tests")
+
+# mbed RPC
+MBED_RPC = join(LIB_DIR, "rpc")
+
+RPC_LIBRARY = join(BUILD_DIR, "rpc")
+
+# DSP
+DSP = join(LIB_DIR, "dsp")
+DSP_CMSIS = join(DSP, "cmsis_dsp")
+DSP_ABSTRACTION = join(DSP, "dsp")
+DSP_LIBRARIES = join(BUILD_DIR, "dsp")
+
+# USB Device
+USB = join(LIB_DIR, "USBDevice")
+USB_LIBRARIES = join(BUILD_DIR, "usb")
+
+# Export
+EXPORT_DIR = join(BUILD_DIR, "export")
+EXPORT_WORKSPACE = join(EXPORT_DIR, "workspace")
+EXPORT_TMP = join(EXPORT_DIR, ".temp")
+
+# CppUtest library
+CPPUTEST_DIR = join(ROOT, "..")
+CPPUTEST_SRC = join(CPPUTEST_DIR, "cpputest", "src", "CppUTest")
+CPPUTEST_INC = join(CPPUTEST_DIR, "cpputest", "include")
+CPPUTEST_INC_EXT = join(CPPUTEST_DIR, "cpputest", "include", "CppUTest")
+# Platform dependant code is here (for armcc compiler)
+CPPUTEST_PLATFORM_SRC = join(CPPUTEST_DIR, "cpputest", "src", "Platforms",
+                             "armcc")
+CPPUTEST_PLATFORM_INC = join(CPPUTEST_DIR, "cpputest", "include", "Platforms",
+                             "armcc")
+# Function 'main' used to run all compiled UTs
+CPPUTEST_TESTRUNNER_SCR = join(TEST_DIR, "utest", "testrunner")
+CPPUTEST_TESTRUNNER_INC = join(TEST_DIR, "utest", "testrunner")
+
+CPPUTEST_LIBRARY = join(BUILD_DIR, "cpputest")
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/paths.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/paths.pyc
new file mode 100755
index 0000000..eea9d31
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diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/debug.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/debug.json
new file mode 100755
index 0000000..ad4fab3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/debug.json
@@ -0,0 +1,60 @@
+{
+    "GCC_ARM": {
+        "common": ["-c", "-Wall", "-Wextra",
+                   "-Wno-unused-parameter", "-Wno-missing-field-initializers",
+                   "-fmessage-length=0", "-fno-exceptions", "-fno-builtin",
+                   "-ffunction-sections", "-fdata-sections", "-funsigned-char",
+                   "-MMD", "-fno-delete-null-pointer-checks",
+                   "-fomit-frame-pointer", "-O0", "-g3", "-DMBED_DEBUG",
+                   "-DMBED_TRAP_ERRORS_ENABLED=1"],
+        "asm": ["-x", "assembler-with-cpp"],
+        "c": ["-std=gnu99"],
+        "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"],
+        "ld": ["-Wl,--gc-sections", "-Wl,--wrap,main", "-Wl,--wrap,_malloc_r",
+               "-Wl,--wrap,_free_r", "-Wl,--wrap,_realloc_r", "-Wl,--wrap,_memalign_r",
+               "-Wl,--wrap,_calloc_r", "-Wl,--wrap,exit", "-Wl,--wrap,atexit",
+               "-Wl,-n"]
+    },
+    "ARMC6": {
+        "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-g", "-O0",
+                   "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
+                   "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
+                   "-fno-exceptions", "-MMD"],
+        "asm": [],
+        "c": ["-D__ASSERT_MSG", "-std=gnu99"],
+        "cxx": ["-fno-rtti", "-std=gnu++98"],
+        "ld": ["--verbose", "--remove", "--legacyalign", "--no_strict_wchar_size",
+               "--no_strict_enum_size"]
+    },
+    "ARM": {
+        "common": ["-c", "--gnu", "-Otime", "--split_sections",
+                   "--apcs=interwork", "--brief_diagnostics", "--restrict",
+                   "--multibyte_chars", "-O0", "-g", "-DMBED_DEBUG",
+                   "-DMBED_TRAP_ERRORS_ENABLED=1"],
+        "asm": [],
+        "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
+        "cxx": ["--cpp", "--no_rtti", "--no_vla"],
+        "ld": ["--show_full_path"]
+    },
+    "uARM": {
+        "common": ["-c", "--gnu", "-Otime", "--split_sections",
+                   "--apcs=interwork", "--brief_diagnostics", "--restrict",
+                   "--multibyte_chars", "-O0", "-D__MICROLIB", "-g",
+                   "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD", "-DMBED_DEBUG",
+                   "-DMBED_TRAP_ERRORS_ENABLED=1"],
+        "asm": [],
+        "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
+        "cxx": ["--cpp", "--no_rtti", "--no_vla"],
+        "ld": ["--library_type=microlib"]
+    },
+    "IAR": {
+        "common": [
+            "--no_wrap_diagnostics",  "-e",
+            "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-On", "-r", "-DMBED_DEBUG",
+            "-DMBED_TRAP_ERRORS_ENABLED=1"],
+        "asm": [],
+        "c": ["--vla"],
+        "cxx": ["--guard_calls", "--no_static_destruction"],
+        "ld": ["--skip_dynamic_initialization", "--threaded_lib"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/develop.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/develop.json
new file mode 100755
index 0000000..6142485
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/develop.json
@@ -0,0 +1,55 @@
+{
+    "GCC_ARM": {
+        "common": ["-c", "-Wall", "-Wextra",
+                   "-Wno-unused-parameter", "-Wno-missing-field-initializers",
+                   "-fmessage-length=0", "-fno-exceptions", "-fno-builtin",
+                   "-ffunction-sections", "-fdata-sections", "-funsigned-char",
+                   "-MMD", "-fno-delete-null-pointer-checks",
+                   "-fomit-frame-pointer", "-Os"],
+        "asm": ["-x", "assembler-with-cpp"],
+        "c": ["-std=gnu99"],
+        "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"],
+        "ld": ["-Wl,--gc-sections", "-Wl,--wrap,main", "-Wl,--wrap,_malloc_r",
+               "-Wl,--wrap,_free_r", "-Wl,--wrap,_realloc_r", "-Wl,--wrap,_memalign_r",
+               "-Wl,--wrap,_calloc_r", "-Wl,--wrap,exit", "-Wl,--wrap,atexit",
+               "-Wl,-n"]
+    },
+    "ARMC6": {
+        "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Os",
+                   "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
+                   "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
+                   "-fno-exceptions", "-MMD"],
+        "asm": [],
+        "c": ["-D__ASSERT_MSG", "-std=gnu99"],
+        "cxx": ["-fno-rtti", "-std=gnu++98"],
+        "ld": ["--legacyalign", "--no_strict_wchar_size", "--no_strict_enum_size"]
+    },
+    "ARM": {
+        "common": ["-c", "--gnu", "-Otime", "--split_sections",
+                   "--apcs=interwork", "--brief_diagnostics", "--restrict",
+                   "--multibyte_chars", "-O3"],
+        "asm": [],
+        "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
+        "cxx": ["--cpp", "--no_rtti", "--no_vla"],
+        "ld": ["--show_full_path"]
+    },
+    "uARM": {
+        "common": ["-c", "--gnu", "-Otime", "--split_sections",
+                   "--apcs=interwork", "--brief_diagnostics", "--restrict",
+                   "--multibyte_chars", "-O3", "-D__MICROLIB",
+                   "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD"],
+        "asm": [],
+        "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
+        "cxx": ["--cpp", "--no_rtti", "--no_vla"],
+        "ld": ["--library_type=microlib"]
+    },
+    "IAR": {
+        "common": [
+            "--no_wrap_diagnostics", "-e",
+            "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh"],
+        "asm": [],
+        "c": ["--vla"],
+        "cxx": ["--guard_calls", "--no_static_destruction"],
+        "ld": ["--skip_dynamic_initialization", "--threaded_lib"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/release.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/release.json
new file mode 100755
index 0000000..eedbce0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/profiles/release.json
@@ -0,0 +1,55 @@
+{
+    "GCC_ARM": {
+        "common": ["-c", "-Wall", "-Wextra",
+                   "-Wno-unused-parameter", "-Wno-missing-field-initializers",
+                   "-fmessage-length=0", "-fno-exceptions", "-fno-builtin",
+                   "-ffunction-sections", "-fdata-sections", "-funsigned-char",
+                   "-MMD", "-fno-delete-null-pointer-checks",
+                   "-fomit-frame-pointer", "-Os", "-DNDEBUG"],
+        "asm": ["-x", "assembler-with-cpp"],
+        "c": ["-std=gnu99"],
+        "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"],
+        "ld": ["-Wl,--gc-sections", "-Wl,--wrap,main", "-Wl,--wrap,_malloc_r",
+               "-Wl,--wrap,_free_r", "-Wl,--wrap,_realloc_r", "-Wl,--wrap,_memalign_r",
+               "-Wl,--wrap,_calloc_r", "-Wl,--wrap,exit", "-Wl,--wrap,atexit",
+               "-Wl,-n"]
+    },
+    "ARMC6": {
+        "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Oz",
+                   "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
+                   "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
+                   "-fno-exceptions", "-MMD"],
+        "asm": [],
+        "c": ["-D__ASSERT_MSG", "-std=gnu99"],
+        "cxx": ["-fno-rtti", "-std=gnu++98"],
+        "ld": ["--legacyalign", "--no_strict_wchar_size", "--no_strict_enum_size"]
+    },
+    "ARM": {
+        "common": ["-c", "--gnu", "-Ospace", "--split_sections",
+                   "--apcs=interwork", "--brief_diagnostics", "--restrict",
+                   "--multibyte_chars", "-O3", "-DNDEBUG"],
+        "asm": [],
+        "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
+        "cxx": ["--cpp", "--no_rtti", "--no_vla"],
+        "ld": ["--show_full_path"]
+    },
+    "uARM": {
+        "common": ["-c", "--gnu", "-Ospace", "--split_sections",
+                   "--apcs=interwork", "--brief_diagnostics", "--restrict",
+                   "--multibyte_chars", "-O3", "-D__MICROLIB",
+                   "--library_type=microlib", "-DMBED_RTOS_SINGLE_THREAD", "-DNDEBUG"],
+        "asm": [],
+        "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
+        "cxx": ["--cpp", "--no_rtti", "--no_vla"],
+        "ld": ["--library_type=microlib"]
+    },
+    "IAR": {
+        "common": [
+            "--no_wrap_diagnostics", "-e",
+            "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Ohz", "-DNDEBUG"],
+        "asm": [],
+        "c": ["--vla"],
+        "cxx": ["--guard_calls", "--no_static_destruction"],
+        "ld": ["--skip_dynamic_initialization", "--threaded_lib"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/project.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/project.py
new file mode 100755
index 0000000..ff59f5b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/project.py
@@ -0,0 +1,259 @@
+""" The CLI entry point for exporting projects from the mbed tools to any of the
+supported IDEs or project structures.
+"""
+import sys
+from os.path import join, abspath, dirname, exists, basename
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from shutil import move, rmtree
+from argparse import ArgumentParser
+from os.path import normpath, realpath
+
+from tools.paths import EXPORT_DIR, MBED_HAL, MBED_LIBRARIES, MBED_TARGETS_PATH
+from tools.settings import BUILD_DIR
+from tools.export import EXPORTERS, mcu_ide_matrix, mcu_ide_list, export_project, get_exporter_toolchain
+from tools.tests import TESTS, TEST_MAP
+from tools.tests import test_known, test_name_known, Test
+from tools.targets import TARGET_NAMES
+from tools.utils import argparse_filestring_type, argparse_profile_filestring_type, argparse_many, args_error
+from tools.utils import argparse_force_lowercase_type
+from tools.utils import argparse_force_uppercase_type
+from tools.utils import print_large_string
+from tools.utils import NotSupportedException
+from tools.options import extract_profile, list_profiles, extract_mcus
+
+def setup_project(ide, target, program=None, source_dir=None, build=None, export_path=None):
+    """Generate a name, if not provided, and find dependencies
+
+    Positional arguments:
+    ide - IDE or project structure that will soon be exported to
+    target - MCU that the project will build for
+
+    Keyword arguments:
+    program - the index of a test program
+    source_dir - the directory, or directories that contain all of the sources
+    build - a directory that will contain the result of the export
+    """
+    # Some libraries have extra macros (called by exporter symbols) to we need
+    # to pass them to maintain compilation macros integrity between compiled
+    # library and header files we might use with it
+    if source_dir:
+        # --source is used to generate IDE files to toolchain directly
+        # in the source tree and doesn't generate zip file
+        project_dir = export_path or source_dir[0]
+        if program:
+            project_name = TESTS[program]
+        else:
+            project_name = basename(normpath(realpath(source_dir[0])))
+        src_paths = source_dir
+        lib_paths = None
+    else:
+        test = Test(program)
+        if not build:
+            # Substitute the mbed library builds with their sources
+            if MBED_LIBRARIES in test.dependencies:
+                test.dependencies.remove(MBED_LIBRARIES)
+                test.dependencies.append(MBED_HAL)
+                test.dependencies.append(MBED_TARGETS_PATH)
+
+
+        src_paths = [test.source_dir]
+        lib_paths = test.dependencies
+        project_name = "_".join([test.id, ide, target])
+        project_dir = join(EXPORT_DIR, project_name)
+
+    return project_dir, project_name, src_paths, lib_paths
+
+
+def export(target, ide, build=None, src=None, macros=None, project_id=None,
+           zip_proj=False, build_profile=None, export_path=None, silent=False,
+           app_config=None):
+    """Do an export of a project.
+
+    Positional arguments:
+    target - MCU that the project will compile for
+    ide - the IDE or project structure to export to
+
+    Keyword arguments:
+    build - to use the compiled mbed libraries or not
+    src - directory or directories that contain the source to export
+    macros - extra macros to add to the project
+    project_id - the name of the project
+    clean - start from a clean state before exporting
+    zip_proj - create a zip file or not
+
+    Returns an object of type Exporter (tools/exports/exporters.py)
+    """
+    project_dir, name, src, lib = setup_project(ide, target, program=project_id,
+                                                source_dir=src, build=build, export_path=export_path)
+
+    zip_name = name+".zip" if zip_proj else None
+
+    return export_project(src, project_dir, target, ide, name=name,
+                          macros=macros, libraries_paths=lib, zip_proj=zip_name,
+                          build_profile=build_profile, silent=silent,
+                          app_config=app_config)
+
+
+def main():
+    """Entry point"""
+    # Parse Options
+    parser = ArgumentParser()
+
+    targetnames = TARGET_NAMES
+    targetnames.sort()
+    toolchainlist = EXPORTERS.keys()
+    toolchainlist.sort()
+
+    parser.add_argument("-m", "--mcu",
+                        metavar="MCU",
+                        type=str.upper,
+                        help="generate project for the given MCU ({})".format(
+                            ', '.join(targetnames)))
+
+    parser.add_argument("-i",
+                        dest="ide",
+                        type=argparse_force_lowercase_type(
+                            toolchainlist, "toolchain"),
+                        help="The target IDE: %s"% str(toolchainlist))
+
+    parser.add_argument("-c", "--clean",
+                        action="store_true",
+                        default=False,
+                        help="clean the export directory")
+
+    group = parser.add_mutually_exclusive_group(required=False)
+    group.add_argument(
+        "-p",
+        type=test_known,
+        dest="program",
+        help="The index of the desired test program: [0-%s]"% (len(TESTS)-1))
+
+    group.add_argument("-n",
+                       type=test_name_known,
+                       dest="program",
+                       help="The name of the desired test program")
+
+    parser.add_argument("-b",
+                      dest="build",
+                      default=False,
+                      action="store_true",
+                      help="use the mbed library build, instead of the sources")
+
+    group.add_argument("-L", "--list-tests",
+                       action="store_true",
+                       dest="list_tests",
+                       default=False,
+                       help="list available programs in order and exit")
+
+    group.add_argument("-S", "--list-matrix",
+                       dest="supported_ides",
+                       default=False,
+                       const="matrix",
+                       choices=["matrix", "ides"],
+                       nargs="?",
+                       help="displays supported matrix of MCUs and IDEs")
+
+    parser.add_argument("-E",
+                        action="store_true",
+                        dest="supported_ides_html",
+                        default=False,
+                        help="writes tools/export/README.md")
+
+    parser.add_argument("--source",
+                        action="append",
+                        type=argparse_filestring_type,
+                        dest="source_dir",
+                        default=[],
+                        help="The source (input) directory")
+
+    parser.add_argument("-D",
+                        action="append",
+                        dest="macros",
+                        help="Add a macro definition")
+
+    parser.add_argument("--profile", dest="profile", action="append",
+                        type=argparse_profile_filestring_type,
+                        help="Build profile to use. Can be either path to json" \
+                        "file or one of the default one ({})".format(", ".join(list_profiles())),
+                        default=[])
+
+    parser.add_argument("--update-packs",
+                        dest="update_packs",
+                        action="store_true",
+                        default=False)
+    parser.add_argument("--app-config",
+                        dest="app_config",
+                        default=None)
+
+    options = parser.parse_args()
+
+    # Print available tests in order and exit
+    if options.list_tests is True:
+        print '\n'.join([str(test) for test in  sorted(TEST_MAP.values())])
+        sys.exit()
+
+    # Only prints matrix of supported IDEs
+    if options.supported_ides:
+        if options.supported_ides == "matrix":
+            print_large_string(mcu_ide_matrix())
+        elif options.supported_ides == "ides":
+            print mcu_ide_list()
+        exit(0)
+
+    # Only prints matrix of supported IDEs
+    if options.supported_ides_html:
+        html = mcu_ide_matrix(verbose_html=True)
+        try:
+            with open("./export/README.md", "w") as readme:
+                readme.write("Exporter IDE/Platform Support\n")
+                readme.write("-----------------------------------\n")
+                readme.write("\n")
+                readme.write(html)
+        except IOError as exc:
+            print "I/O error({0}): {1}".format(exc.errno, exc.strerror)
+        except:
+            print "Unexpected error:", sys.exc_info()[0]
+            raise
+        exit(0)
+
+    if options.update_packs:
+        from tools.arm_pack_manager import Cache
+        cache = Cache(True, True)
+        cache.cache_descriptors()
+
+    # Target
+    if not options.mcu:
+        args_error(parser, "argument -m/--mcu is required")
+
+    # Toolchain
+    if not options.ide:
+        args_error(parser, "argument -i is required")
+
+    # Clean Export Directory
+    if options.clean:
+        if exists(EXPORT_DIR):
+            rmtree(EXPORT_DIR)
+
+    zip_proj = not bool(options.source_dir)
+
+    if (options.program is None) and (not options.source_dir):
+        args_error(parser, "one of -p, -n, or --source is required")
+    exporter, toolchain_name = get_exporter_toolchain(options.ide)
+    mcu = extract_mcus(parser, options)[0]
+    if not exporter.is_target_supported(mcu):
+        args_error(parser, "%s not supported by %s"%(mcu,options.ide))
+    profile = extract_profile(parser, options, toolchain_name, fallback="debug")
+    if options.clean:
+        rmtree(BUILD_DIR)
+    try:
+        export(mcu, options.ide, build=options.build,
+               src=options.source_dir, macros=options.macros,
+               project_id=options.program, zip_proj=zip_proj,
+               build_profile=profile, app_config=options.app_config)
+    except NotSupportedException as exc:
+        print "[ERROR] %s" % str(exc)
+
+if __name__ == "__main__":
+    main()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/settings.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/settings.py
new file mode 100755
index 0000000..50421b9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/settings.py
@@ -0,0 +1,107 @@
+"""
+mbed SDK
+Copyright (c) 2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from os import getenv
+from os.path import join, abspath, dirname, exists
+import logging
+
+ROOT = abspath(join(dirname(__file__), ".."))
+
+
+##############################################################################
+# Toolchains and Build System Settings
+##############################################################################
+BUILD_DIR = abspath(join(ROOT, "BUILD"))
+
+# ARM Compiler 5
+ARM_PATH = ""
+
+# ARM Compiler 6
+ARMC6_PATH = ""
+
+# GCC ARM
+GCC_ARM_PATH = ""
+
+# GCC CodeRed
+GCC_CR_PATH = ""
+
+# IAR
+IAR_PATH = ""
+
+# Goanna static analyser. Please overload it in mbed_settings.py
+GOANNA_PATH = ""
+
+# cppcheck path (command) and output message format
+CPPCHECK_CMD = ["cppcheck", "--enable=all"]
+CPPCHECK_MSG_FORMAT = ["--template=[{severity}] {file}@{line}: {id}:{message}"]
+
+BUILD_OPTIONS = []
+
+# mbed.org username
+MBED_ORG_USER = ""
+
+CLI_COLOR_MAP = {
+    "warning": "yellow",
+    "error"  : "red"
+}
+
+##############################################################################
+# User Settings (file)
+##############################################################################
+try:
+    # Allow to overwrite the default settings without the need to edit the
+    # settings file stored in the repository
+    from mbed_settings import *
+except ImportError:
+    pass
+
+
+##############################################################################
+# User Settings (env vars)
+##############################################################################
+_ENV_PATHS = ['ARM_PATH', 'GCC_ARM_PATH', 'GCC_CR_PATH', 'IAR_PATH',
+              'ARMC6_PATH']
+
+for _n in _ENV_PATHS:
+    if getenv('MBED_'+_n):
+        if exists(getenv('MBED_'+_n)):
+            globals()[_n] = getenv('MBED_'+_n)
+        else:
+            print "WARNING: MBED_%s set as environment variable but doesn't exist" % _n
+
+
+##############################################################################
+# Test System Settings
+##############################################################################
+SERVER_PORT = 59432
+SERVER_ADDRESS = "10.2.200.94"
+LOCALHOST = "10.2.200.94"
+
+MUTs = {
+    "1" : {"mcu": "LPC1768",
+        "port":"COM41", "disk":'E:\\',
+        "peripherals": ["TMP102", "digital_loop", "port_loop", "analog_loop", "SD"]
+    },
+    "2": {"mcu": "LPC11U24",
+        "port":"COM42", "disk":'F:\\',
+        "peripherals":  ["TMP102", "digital_loop", "port_loop", "SD"]
+    },
+    "3" : {"mcu": "KL25Z",
+        "port":"COM43", "disk":'G:\\',
+        "peripherals":  ["TMP102", "digital_loop", "port_loop", "analog_loop", "SD"]
+    },
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/settings.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/settings.pyc
new file mode 100755
index 0000000..9513842
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/settings.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/singletest.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/singletest.py
new file mode 100755
index 0000000..a07ecd4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/singletest.py
@@ -0,0 +1,265 @@
+#!/usr/bin/env python2
+
+"""
+mbed SDK
+Copyright (c) 2011-2014 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+"""
+
+"""
+File format example: test_spec.json:
+{
+    "targets": {
+        "KL46Z": ["ARM", "GCC_ARM"],
+        "LPC1768": ["ARM", "GCC_ARM", "GCC_CR", "IAR"],
+        "LPC11U24": ["uARM"],
+        "NRF51822": ["ARM"]
+    }
+}
+
+File format example: muts_all.json:
+{
+    "1" : {"mcu": "LPC1768",
+           "port":"COM4",
+           "disk":"J:\\",
+           "peripherals": ["TMP102", "digital_loop", "port_loop", "analog_loop", "SD"]
+    },
+
+    "2" : {"mcu": "KL25Z",
+           "port":"COM7",
+           "disk":"G:\\",
+           "peripherals": ["digital_loop", "port_loop", "analog_loop"]
+    }
+}
+"""
+
+
+# Be sure that the tools directory is in the search path
+import sys
+from os.path import join, abspath, dirname
+
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+
+# Check: Extra modules which are required by core test suite
+from tools.utils import check_required_modules
+check_required_modules(['prettytable', 'serial'])
+
+# Imports related to mbed build api
+from tools.build_api import mcu_toolchain_matrix
+
+# Imports from TEST API
+from tools.test_api import SingleTestRunner
+from tools.test_api import singletest_in_cli_mode
+from tools.test_api import detect_database_verbose
+from tools.test_api import get_json_data_from_file
+from tools.test_api import get_avail_tests_summary_table
+from tools.test_api import get_default_test_options_parser
+from tools.test_api import print_muts_configuration_from_json
+from tools.test_api import print_test_configuration_from_json
+from tools.test_api import get_autodetected_MUTS_list
+from tools.test_api import get_autodetected_TEST_SPEC
+from tools.test_api import get_module_avail
+from tools.test_exporters import ReportExporter, ResultExporterType
+
+
+# Importing extra modules which can be not installed but if available they can extend test suite functionality
+try:
+    import mbed_lstools
+    from tools.compliance.ioper_runner import IOperTestRunner
+    from tools.compliance.ioper_runner import get_available_oper_test_scopes
+except:
+    pass
+
+def get_version():
+    """ Returns test script version
+    """
+    single_test_version_major = 1
+    single_test_version_minor = 5
+    return (single_test_version_major, single_test_version_minor)
+
+
+if __name__ == '__main__':
+    # Command line options
+    parser = get_default_test_options_parser()
+
+    parser.description = """This script allows you to run mbed defined test cases for particular MCU(s) and corresponding toolchain(s)."""
+    parser.epilog = """Example: singletest.py -i test_spec.json -M muts_all.json"""
+
+    opts = parser.parse_args()
+
+    # Print scrip version
+    if opts.version:
+        print parser.description
+        print parser.epilog
+        print "Version %d.%d"% get_version()
+        exit(0)
+
+    if opts.db_url and opts.verbose_test_configuration_only:
+        detect_database_verbose(opts.db_url)
+        exit(0)
+
+    # Print summary / information about automation test status
+    if opts.test_automation_report:
+        print get_avail_tests_summary_table(platform_filter=opts.general_filter_regex)
+        exit(0)
+
+    # Print summary / information about automation test status
+    if opts.test_case_report:
+        test_case_report_cols = ['id',
+                                 'automated',
+                                 'description',
+                                 'peripherals',
+                                 'host_test',
+                                 'duration',
+                                 'source_dir']
+        print get_avail_tests_summary_table(cols=test_case_report_cols,
+                                            result_summary=False,
+                                            join_delim='\n',
+                                            platform_filter=opts.general_filter_regex)
+        exit(0)
+
+    # Only prints matrix of supported toolchains
+    if opts.supported_toolchains:
+        print mcu_toolchain_matrix(platform_filter=opts.general_filter_regex)
+        exit(0)
+
+    test_spec = None
+    MUTs = None
+
+    if hasattr(opts, 'auto_detect') and opts.auto_detect:
+        # If auto_detect attribute is present, we assume other auto-detection
+        # parameters like 'toolchains_filter' are also set.
+        print "MBEDLS: Detecting connected mbed-enabled devices... "
+
+        MUTs = get_autodetected_MUTS_list()
+
+        for mut in MUTs.values():
+            print "MBEDLS: Detected %s, port: %s, mounted: %s"% (mut['mcu_unique'] if 'mcu_unique' in mut else mut['mcu'],
+                                    mut['port'],
+                                    mut['disk'])
+
+        # Set up parameters for test specification filter function (we need to set toolchains per target here)
+        use_default_toolchain = 'default' in opts.toolchains_filter if opts.toolchains_filter is not None else True
+        use_supported_toolchains = 'all' in opts.toolchains_filter if opts.toolchains_filter is not None else False
+        toolchain_filter = opts.toolchains_filter
+        platform_name_filter = opts.general_filter_regex if opts.general_filter_regex is not None else opts.general_filter_regex
+        # Test specification with information about each target and associated toolchain
+        test_spec = get_autodetected_TEST_SPEC(MUTs.values(),
+                                               use_default_toolchain=use_default_toolchain,
+                                               use_supported_toolchains=use_supported_toolchains,
+                                               toolchain_filter=toolchain_filter,
+                                               platform_name_filter=platform_name_filter)
+    else:
+        # Open file with test specification
+        # test_spec_filename tells script which targets and their toolchain(s)
+        # should be covered by the test scenario
+        opts.auto_detect = False
+        test_spec = get_json_data_from_file(opts.test_spec_filename) if opts.test_spec_filename else None
+        if test_spec is None:
+            if not opts.test_spec_filename:
+                parser.print_help()
+            exit(-1)
+
+        # Get extra MUTs if applicable
+        MUTs = get_json_data_from_file(opts.muts_spec_filename) if opts.muts_spec_filename else None
+
+        if MUTs is None:
+            if not opts.muts_spec_filename:
+                parser.print_help()
+            exit(-1)
+
+    if opts.verbose_test_configuration_only:
+        print "MUTs configuration in %s:" % ('auto-detected' if opts.auto_detect else opts.muts_spec_filename)
+        if MUTs:
+            print print_muts_configuration_from_json(MUTs, platform_filter=opts.general_filter_regex)
+        print
+        print "Test specification in %s:" % ('auto-detected' if opts.auto_detect else opts.test_spec_filename)
+        if test_spec:
+            print print_test_configuration_from_json(test_spec)
+        exit(0)
+
+    if get_module_avail('mbed_lstools'):
+        if opts.operability_checks:
+            # Check if test scope is valid and run tests
+            test_scope = get_available_oper_test_scopes()
+            if opts.operability_checks in test_scope:
+                tests = IOperTestRunner(scope=opts.operability_checks)
+                test_results = tests.run()
+
+                # Export results in form of JUnit XML report to separate file
+                if opts.report_junit_file_name:
+                    report_exporter = ReportExporter(ResultExporterType.JUNIT_OPER)
+                    report_exporter.report_to_file(test_results, opts.report_junit_file_name)
+            else:
+                print "Unknown interoperability test scope name: '%s'" % (opts.operability_checks)
+                print "Available test scopes: %s" % (','.join(["'%s'" % n for n in test_scope]))
+
+            exit(0)
+
+    # Verbose test specification and MUTs configuration
+    if MUTs and opts.verbose:
+        print print_muts_configuration_from_json(MUTs)
+    if test_spec and opts.verbose:
+        print print_test_configuration_from_json(test_spec)
+
+    if opts.only_build_tests:
+        # We are skipping testing phase, and suppress summary
+        opts.suppress_summary = True
+
+    single_test = SingleTestRunner(_global_loops_count=opts.test_global_loops_value,
+                                   _test_loops_list=opts.test_loops_list,
+                                   _muts=MUTs,
+                                   _clean=opts.clean,
+                                   _parser=parser,
+                                   _opts=opts,
+                                   _opts_db_url=opts.db_url,
+                                   _opts_log_file_name=opts.log_file_name,
+                                   _opts_report_html_file_name=opts.report_html_file_name,
+                                   _opts_report_junit_file_name=opts.report_junit_file_name,
+                                   _opts_report_build_file_name=opts.report_build_file_name,
+                                   _opts_report_text_file_name=opts.report_text_file_name,
+                                   _test_spec=test_spec,
+                                   _opts_goanna_for_mbed_sdk=opts.goanna_for_mbed_sdk,
+                                   _opts_goanna_for_tests=opts.goanna_for_tests,
+                                   _opts_shuffle_test_order=opts.shuffle_test_order,
+                                   _opts_shuffle_test_seed=opts.shuffle_test_seed,
+                                   _opts_test_by_names=opts.test_by_names,
+                                   _opts_peripheral_by_names=opts.peripheral_by_names,
+                                   _opts_test_only_peripheral=opts.test_only_peripheral,
+                                   _opts_test_only_common=opts.test_only_common,
+                                   _opts_verbose_skipped_tests=opts.verbose_skipped_tests,
+                                   _opts_verbose_test_result_only=opts.verbose_test_result_only,
+                                   _opts_verbose=opts.verbose,
+                                   _opts_firmware_global_name=opts.firmware_global_name,
+                                   _opts_only_build_tests=opts.only_build_tests,
+                                   _opts_parallel_test_exec=opts.parallel_test_exec,
+                                   _opts_suppress_summary=opts.suppress_summary,
+                                   _opts_test_x_toolchain_summary=opts.test_x_toolchain_summary,
+                                   _opts_copy_method=opts.copy_method,
+                                   _opts_mut_reset_type=opts.mut_reset_type,
+                                   _opts_jobs=opts.jobs,
+                                   _opts_waterfall_test=opts.waterfall_test,
+                                   _opts_consolidate_waterfall_test=opts.consolidate_waterfall_test,
+                                   _opts_extend_test_timeout=opts.extend_test_timeout,
+                                   _opts_auto_detect=opts.auto_detect)
+
+    # Runs test suite in CLI mode
+    if (singletest_in_cli_mode(single_test)):
+        exit(0)
+    else:
+        exit(-1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/size.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/size.py
new file mode 100755
index 0000000..0e19ae3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/size.py
@@ -0,0 +1,121 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import sys
+from os.path import join, abspath, dirname, exists, splitext
+from subprocess import Popen, PIPE
+import csv
+from collections import defaultdict
+
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.paths import BUILD_DIR, TOOLS_DATA
+from tools.settings import GCC_ARM_PATH
+from tools.tests import TEST_MAP
+from tools.build_api import build_mbed_libs, build_project
+
+SIZE = join(GCC_ARM_PATH, 'arm-none-eabi-size')
+
+def get_size(path):
+    out = Popen([SIZE, path], stdout=PIPE).communicate()[0]
+    return map(int, out.splitlines()[1].split()[:4])
+
+def get_percentage(before, after):
+    if before == 0:
+        return 0 if after == 0 else 100.0
+    return float(after - before) / float(before) * 100.0
+
+def human_size(val):
+    if val>1024:
+        return "%.0fKb" % (float(val)/1024.0)
+    return "%d" % val
+
+def print_diff(name, before, after):
+    print "%s: (%s -> %s) %.2f%%" % (name, human_size(before) , human_size(after) , get_percentage(before , after))
+
+BENCHMARKS = [
+    ("BENCHMARK_1", "CENV"),
+    ("BENCHMARK_2", "PRINTF"),
+    ("BENCHMARK_3", "FP"),
+    ("BENCHMARK_4", "MBED"),
+    ("BENCHMARK_5", "ALL"),
+]
+BENCHMARK_DATA_PATH = join(TOOLS_DATA, 'benchmarks.csv')
+
+
+def benchmarks():
+    # CSV Data
+    csv_data = csv.writer(open(BENCHMARK_DATA_PATH, 'wb'))
+    csv_data.writerow(['Toolchain', "Target", "Benchmark", "code", "data", "bss", "flash"])
+
+    # Build
+    for toolchain in ['ARM', 'uARM', 'GCC_CR', 'GCC_ARM']:
+        for mcu in ["LPC1768", "LPC11U24"]:
+            # Build Libraries
+            build_mbed_libs(mcu, toolchain)
+
+            # Build benchmarks
+            build_dir = join(BUILD_DIR, "benchmarks", mcu, toolchain)
+            for test_id, title in BENCHMARKS:
+                # Build Benchmark
+                try:
+                    test = TEST_MAP[test_id]
+                    path = build_project(test.source_dir, join(build_dir, test_id),
+                                 mcu, toolchain, test.dependencies)
+                    base, ext = splitext(path)
+                    # Check Size
+                    code, data, bss, flash = get_size(base+'.elf')
+                    csv_data.writerow([toolchain, mcu, title, code, data, bss, flash])
+                except Exception, e:
+                    print "Unable to build %s for toolchain %s targeting %s" % (test_id, toolchain, mcu)
+                    print e
+
+
+def compare(t1, t2, target):
+    if not exists(BENCHMARK_DATA_PATH):
+        benchmarks()
+    else:
+        print "Loading: %s" % BENCHMARK_DATA_PATH
+
+    data = csv.reader(open(BENCHMARK_DATA_PATH, 'rb'))
+
+    benchmarks_data = defaultdict(dict)
+    for (toolchain, mcu, name, code, data, bss, flash) in data:
+        if target == mcu:
+            for t in [t1, t2]:
+                if toolchain == t:
+                    benchmarks_data[name][t] = map(int, (code, data, bss, flash))
+
+    print "%s vs %s for %s" % (t1, t2, target)
+    for name, data in benchmarks_data.iteritems():
+        try:
+            # Check Size
+            code_a, data_a, bss_a, flash_a = data[t1]
+            code_u, data_u, bss_u, flash_u = data[t2]
+
+            print "\n=== %s ===" % name
+            print_diff("code", code_a , code_u)
+            print_diff("data", data_a , data_u)
+            print_diff("bss", bss_a , bss_u)
+            print_diff("flash", flash_a , flash_u)
+        except Exception, e:
+            print "No data for benchmark %s" % (name)
+            print e
+
+
+if __name__ == '__main__':
+    compare("GCC_CR", "LPC1768")
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/synch.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/synch.py
new file mode 100755
index 0000000..e6d209d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/synch.py
@@ -0,0 +1,344 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+One repository to update them all
+On mbed.org the mbed SDK is split up in multiple repositories, this script takes
+care of updating them all.
+"""
+import sys
+from copy import copy
+from os import walk, remove, makedirs, getcwd, rmdir, listdir
+from os.path import join, abspath, dirname, relpath, exists, isfile, normpath, isdir
+from shutil import copyfile
+from optparse import OptionParser
+import re
+import string
+
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.settings import MBED_ORG_PATH, MBED_ORG_USER, BUILD_DIR
+from tools.paths import *
+from tools.utils import run_cmd
+
+MBED_URL = "mbed.org"
+MBED_USER = "mbed_official"
+
+changed = []
+push_remote = True
+quiet = False
+commit_msg = ''
+
+# Code that does have a mirror in the mbed SDK
+# Tuple data: (repo_name, list_of_code_dirs, [team])
+# team is optional - if not specified, the code is published under mbed_official
+OFFICIAL_CODE = {"mbed-dev" : ["cmsis", "drivers", "hal", "platform", "targets", "mbed.h"]}
+
+
+# A list of regular expressions that will be checked against each directory
+# name and skipped if they match.
+IGNORE_DIRS = (
+)
+
+IGNORE_FILES = (
+    'COPYING',
+    '\.md',
+    "\.lib",
+    "\.bld"
+)
+
+def ignore_path(name, reg_exps):
+    for r in reg_exps:
+        if re.search(r, name):
+            return True
+    return False
+
+class MbedRepository:
+    @staticmethod
+    def run_and_print(command, cwd):
+        stdout, _, _ = run_cmd(command, work_dir=cwd, redirect=True)
+        print(stdout)
+
+    def __init__(self, name):
+        self.name = name
+        self.path = join(MBED_ORG_PATH, name)
+        self.url = "http://" + MBED_URL + "/users/" + MBED_ORG_USER + "/code/%s/"
+
+        if not exists(self.path):
+            # Checkout code
+            if not exists(MBED_ORG_PATH):
+                makedirs(MBED_ORG_PATH)
+
+            self.run_and_print(['hg', 'clone', self.url % name], cwd=MBED_ORG_PATH)
+
+        else:
+            # Update
+            self.run_and_print(['hg', 'pull'], cwd=self.path)
+            self.run_and_print(['hg', 'update'], cwd=self.path)
+
+    def publish(self):
+        # The maintainer has to evaluate the changes first and explicitly accept them
+        self.run_and_print(['hg', 'addremove'], cwd=self.path)
+        stdout, _, _ = run_cmd(['hg', 'status'], work_dir=self.path)
+        if stdout == '':
+            print "No changes"
+            return False
+        print stdout
+        if quiet:
+            commit = 'Y'
+        else:
+            commit = raw_input(push_remote and "Do you want to commit and push? Y/N: " or "Do you want to commit? Y/N: ")
+        if commit == 'Y':
+            args = ['hg', 'commit', '-u', MBED_ORG_USER]
+            
+            
+            # NOTE commit_msg should always come from the relevant mbed 2 release text
+            if commit_msg:
+                args = args + ['-m', commit_msg]
+            self.run_and_print(args, cwd=self.path)
+            if push_remote:
+                self.run_and_print(['hg', 'push'], cwd=self.path)
+        return True
+
+# Check if a file is a text file or a binary file
+# Taken from http://code.activestate.com/recipes/173220/
+text_characters = "".join(map(chr, range(32, 127)) + list("\n\r\t\b"))
+_null_trans = string.maketrans("", "")
+def is_text_file(filename):
+    block_size = 1024
+    def istext(s):
+        if "\0" in s:
+            return 0
+
+        if not s:  # Empty files are considered text
+            return 1
+
+        # Get the non-text characters (maps a character to itself then
+        # use the 'remove' option to get rid of the text characters.)
+        t = s.translate(_null_trans, text_characters)
+
+        # If more than 30% non-text characters, then
+        # this is considered a binary file
+        if float(len(t))/len(s) > 0.30:
+            return 0
+        return 1
+    with open(filename) as f:
+        res = istext(f.read(block_size))
+    return res
+
+# Return the line ending type for the given file ('cr' or 'crlf')
+def get_line_endings(f):
+  examine_size = 1024
+  try:
+    tf = open(f, "rb")
+    lines, ncrlf = tf.readlines(examine_size), 0
+    tf.close()
+    for l in lines:
+      if l.endswith("\r\n"):
+        ncrlf = ncrlf + 1
+    return 'crlf' if ncrlf > len(lines) >> 1 else 'cr'
+  except:
+    return 'cr'
+
+# Copy file to destination, but preserve destination line endings if possible
+# This prevents very annoying issues with huge diffs that appear because of
+# differences in line endings
+def copy_with_line_endings(sdk_file, repo_file):
+    if not isfile(repo_file):
+        copyfile(sdk_file, repo_file)
+        return
+    is_text = is_text_file(repo_file)
+    if is_text:
+        sdk_le = get_line_endings(sdk_file)
+        repo_le = get_line_endings(repo_file)
+    if not is_text or sdk_le == repo_le:
+        copyfile(sdk_file, repo_file)
+    else:
+        print "Converting line endings in '%s' to '%s'" % (abspath(repo_file), repo_le)
+        f = open(sdk_file, "rb")
+        data = f.read()
+        f.close()
+        f = open(repo_file, "wb")
+        data = data.replace("\r\n", "\n") if repo_le == 'cr' else data.replace('\n','\r\n')
+        f.write(data)
+        f.close()
+
+def visit_files(path, visit):
+    for root, dirs, files in walk(path):    
+        # Ignore hidden directories
+        for d in copy(dirs):
+            full = join(root, d)
+            if d.startswith('.'):
+                dirs.remove(d)
+            if ignore_path(full, IGNORE_DIRS):
+                print "Skipping '%s'" % full
+                dirs.remove(d)
+
+        for file in files:
+            if ignore_path(file, IGNORE_FILES):
+                continue
+
+            visit(join(root, file))
+
+def visit_dirs(path, visit):
+
+    for root, dirs, files in walk(path, topdown=False):            
+        for d in dirs:
+            full = join(root, d)
+            
+            # We don't want to remove the .hg directory
+            if not '.hg' in full:
+                visit(full)
+
+
+def update_repo(repo_name, sdk_paths, lib=False):
+    repo = MbedRepository(repo_name)
+    
+    # copy files from mbed SDK to mbed_official repository
+    def visit_mbed_sdk(sdk_file):
+
+        # Source files structure is different for the compiled binary lib 
+        # compared to the mbed-dev sources
+        if lib:
+            repo_file = join(repo.path, relpath(sdk_file, sdk_path))            
+        else:
+            repo_file = join(repo.path, sdk_file)
+        repo_dir = dirname(repo_file)
+        if not exists(repo_dir):
+            print("CREATING: %s" % repo_dir)
+            makedirs(repo_dir)
+
+        copy_with_line_endings(sdk_file, repo_file)
+
+    # Go through each path specified in the mbed structure 
+    for sdk_path in sdk_paths:
+
+        if isfile(sdk_path):
+            # Single file so just copy directly across
+            visit_mbed_sdk(sdk_path)
+        else:    
+            visit_files(sdk_path, visit_mbed_sdk)
+
+    def sdk_remove(repo_path):
+        
+        print("REMOVING: %s" % repo_path)
+        
+        # Check if this is an empty directory or a file before determining how to 
+        # delete it. As this function should only be called with a directory list
+        # after being called with a file list, the directory should automatically
+        # be either valid or empty .
+        if isfile(repo_path):
+            remove(repo_path)
+        elif isdir(repo_path) and not listdir(repo_path):
+            rmdir(repo_path)
+        else:
+            print("ERROR: %s is not empty, please remove manually." % repo_path)
+            print listdir(repo_path)
+            exit(1)
+
+    # remove repository files that do not exist in the mbed SDK
+    def visit_lib_repo(repo_path):
+        for sdk_path in sdk_paths:
+            sdk_file = join(sdk_path, relpath(repo_path, repo.path))
+            if not exists(sdk_file):
+                sdk_remove(repo_path)
+
+    # remove repository files that do not exist in the mbed SDK source
+    def visit_repo(repo_path):
+
+        # work out equivalent sdk path from repo file
+        sdk_path = join(getcwd(), relpath(repo_path, repo.path))
+
+        if not exists(sdk_path):
+            sdk_remove(repo_path)
+
+    # Go through each path specified in the mbed structure
+    # Check if there are any files in any of those paths that are no longer part of the SDK
+
+    if lib:
+        visit_files(repo.path, visit_lib_repo)
+        # Now do the same for directories that may need to be removed. This needs to be done
+        # bottom up to ensure any lower nested directories can be deleted first
+        visit_dirs(repo.path, visit_lib_repo)
+        
+    else:
+        visit_files(repo.path, visit_repo)
+
+        # Now do the same for directories that may need to be removed. This needs to be done
+        # bottom up to ensure any lower nested directories can be deleted first
+        visit_dirs(repo.path, visit_repo)
+    
+    if repo.publish():
+        changed.append(repo_name)
+
+
+def update_code(repositories):
+    for repo_name in repositories.keys():
+        sdk_dirs = repositories[repo_name]
+        print '\n=== Updating "%s" ===' % repo_name
+        update_repo(repo_name, sdk_dirs)
+
+
+def update_mbed():
+    update_repo("mbed", [join(BUILD_DIR, "mbed")], lib=True)
+
+def do_sync(options):
+    global push_remote, quiet, commit_msg, changed
+
+    push_remote = not options.nopush
+    quiet = options.quiet
+    commit_msg = options.msg
+    changed = []
+
+    if options.code:
+        update_code(OFFICIAL_CODE)
+
+    if options.mbed:
+        update_mbed()
+
+    if changed:
+        print "Repositories with changes:", changed
+
+    return changed
+
+if __name__ == '__main__':
+    parser = OptionParser()
+
+    parser.add_option("-c", "--code",
+                  action="store_true",  default=False,
+                  help="Update the mbed_official code")
+
+    parser.add_option("-m", "--mbed",
+                  action="store_true",  default=False,
+                  help="Release a build of the mbed library")
+
+    parser.add_option("-n", "--nopush",
+                  action="store_true", default=False,
+                  help="Commit the changes locally only, don't push them")
+
+    parser.add_option("", "--commit_message",
+                  action="store", type="string", default='', dest='msg',
+                  help="Commit message to use for all the commits")
+
+    parser.add_option("-q", "--quiet",
+                  action="store_true", default=False,
+                  help="Don't ask for confirmation before commiting or pushing")
+
+    (options, args) = parser.parse_args()
+
+    do_sync(options)
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/LPC.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/LPC.py
new file mode 100755
index 0000000..6fda63f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/LPC.py
@@ -0,0 +1,50 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+http://www.nxp.com/documents/user_manual/UM10360.pdf
+
+32.3.1.1 Criterion for Valid User Code
+The reserved Cortex-M3 exception vector location 7 (offset 0x1C in the vector table)
+should contain the 2's complement of the check-sum of table entries 0 through 6. This
+causes the checksum of the first 8 table entries to be 0. The boot loader code checksums
+the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is
+transferred to the user code.
+"""
+from struct import unpack, pack
+
+
+def patch(bin_path):
+    with open(bin_path, 'r+b') as bin:
+        # Read entries 0 through 6 (Little Endian 32bits words)
+        vector = [unpack('<I', bin.read(4))[0] for _ in range(7)]
+
+        # location 7 (offset 0x1C in the vector table) should contain the 2's
+        # complement of the check-sum of table entries 0 through 6
+        bin.seek(0x1C)
+        bin.write(pack('<I', (~sum(vector) + 1) & 0xFFFFFFFF))
+
+
+def is_patched(bin_path):
+    with open(bin_path, 'rb') as bin:
+        # The checksum of the first 8 table entries should be 0
+        return (sum([unpack('<I', bin.read(4))[0] for _ in range(8)]) & 0xFFFFFFFF) == 0
+
+
+if __name__ == '__main__':
+    bin_path = "C:/Users/emimon01/releases/emilmont/build/test/LPC1768/ARM/MBED_A1/basic.bin"
+    patch(bin_path)
+    assert is_patched(bin_path), "The file is not patched"
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/LPC.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/LPC.pyc
new file mode 100755
index 0000000..36825eb
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/LPC.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/NCS.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/NCS.py
new file mode 100755
index 0000000..710e48c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/NCS.py
@@ -0,0 +1,241 @@
+"""
+@copyright (c) 2012 ON Semiconductor. All rights reserved.
+ON Semiconductor is supplying this software for use with ON Semiconductor
+processor based microcontrollers only.
+THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
+INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+"""
+
+from __future__ import absolute_import
+from __future__ import print_function
+
+import itertools
+import binascii
+import intelhex
+from tools.config import Config
+
+FIB_BASE = 0x2000
+TRIM_BASE = 0x2800
+FLASH_BASE = 0x3000
+FLASHA_SIZE = 0x52000
+FLASHB_BASE = 0x00102000
+FLASHB_SIZE = 0x52000
+FW_REV = 0x01000100
+
+def ranges(i):
+    for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]):
+        b = list(b)
+        yield b[0][1], b[-1][1]
+
+
+def add_fib_at_start(arginput):
+    input_file = arginput + ".hex"
+    file_name_hex = arginput + ".hex"
+    file_name_bin = arginput + ".bin"
+
+    # Read in hex file
+    input_hex_file = intelhex.IntelHex()
+    input_hex_file.loadhex(input_file)
+    #set padding value to be returned when reading from unspecified address
+    input_hex_file.padding = 0xFF
+    # Create new hex file
+    output_hex_file = intelhex.IntelHex()
+
+    # Get the starting and ending address
+    addresses = input_hex_file.addresses()
+    addresses.sort()
+    start_end_pairs = list(ranges(addresses))
+    regions = len(start_end_pairs)
+
+    if regions == 1:
+        #single range indicating fits within first flash block (<320K)
+        start, end = start_end_pairs[0]
+        print("Memory start 0x%08X, end 0x%08X" % (start, end))
+        # Compute checksum over the range (don't include data at location of crc)
+        size = end - start + 1
+        data = input_hex_file.tobinarray(start=start, size=size)
+        crc32 = binascii.crc32(data) & 0xFFFFFFFF
+    else:
+        #multiple ranges indicating requires both flash blocks (>320K)
+        start, end = start_end_pairs[0]
+        start2, end2 = start_end_pairs[1]
+        print("Region 1: memory start 0x%08X, end 0x%08X" % (start, end))
+        print("Region 2: memory start 0x%08X, end 0x%08X" % (start2, end2))
+        # Compute checksum over the range (don't include data at location of crc)
+        # replace end with end of flash block A
+        end = FLASHA_SIZE - 1
+        size = end - start + 1
+        data = input_hex_file.tobinarray(start=start, size=size)
+
+        # replace start2 with base of flash block B
+        start2 = FLASHB_BASE
+        size2 = end2 - start2 + 1
+        data2 = input_hex_file.tobinarray(start=start2, size=size2)
+
+        #concatenate data and data2 arrays together
+        data.extend(data2)
+        crc32 = binascii.crc32(data) & 0xFFFFFFFF
+
+        #replace size with sum of two memory region sizes
+        size = size + size2
+
+    assert start >= FLASH_BASE, ("Error - start 0x%x less than begining of user\
+    flash area" %start)
+
+    assert regions <= 2, ("Error - more than 2 memory regions found")
+
+    fw_rev = FW_REV
+
+    checksum = (start + size + crc32 + fw_rev) & 0xFFFFFFFF
+
+    print("Writing FIB: base 0x%08X, size 0x%08X, crc32 0x%08X, fw rev 0x%08X,\
+    checksum 0x%08X" % (start, size, crc32, fw_rev, checksum))
+
+#expected initial values used by daplink to validate that it is a valid bin
+#file added as dummy values in this file because the fib area preceeds the
+#application area the bootloader will ignore these dummy values
+#  00 is stack pointer (RAM address)
+#  04 is Reset vector  (FLASH address)
+#  08 NMI_Handler      (FLASH address)
+#  0C HardFault_Handler(FLASH address)
+#  10 dummy
+    dummy_sp = 0x3FFFFC00
+    dummy_reset_vector = 0x00003625
+    dummy_nmi_handler = 0x00003761
+    dummy_hardfault_handler = 0x00003691
+    dummy_blank = 0x00000000
+
+#expected fib structure
+#typedef struct fib{
+    #uint32_t base;     /**< Base offset of firmware, indicating what flash the
+    #                        firmware is in. (will never be 0x11111111) */
+    #uint32_t size;     /**< Size of the firmware */
+    #uint32_t crc;      /**< CRC32 for firmware correctness check */
+    #uint32_t rev;      /**< Revision number */
+    #uint32_t checksum; /**< Check-sum of information block */
+#}fib_t, *fib_pt;
+
+    fib_start = FIB_BASE
+    dummy_fib_size = 20
+    fib_size = 20
+    trim_size = 24
+    user_code_start = FLASH_BASE
+    trim_area_start = TRIM_BASE
+
+    # Write FIB to the file in little endian
+    output_hex_file[fib_start + 0] = (dummy_sp >> 0) & 0xFF
+    output_hex_file[fib_start + 1] = (dummy_sp >> 8) & 0xFF
+    output_hex_file[fib_start + 2] = (dummy_sp >> 16) & 0xFF
+    output_hex_file[fib_start + 3] = (dummy_sp >> 24) & 0xFF
+
+    output_hex_file[fib_start + 4] = (dummy_reset_vector >> 0) & 0xFF
+    output_hex_file[fib_start + 5] = (dummy_reset_vector >> 8) & 0xFF
+    output_hex_file[fib_start + 6] = (dummy_reset_vector >> 16) & 0xFF
+    output_hex_file[fib_start + 7] = (dummy_reset_vector >> 24) & 0xFF
+
+    output_hex_file[fib_start + 8] = (dummy_nmi_handler >> 0) & 0xFF
+    output_hex_file[fib_start + 9] = (dummy_nmi_handler >> 8) & 0xFF
+    output_hex_file[fib_start + 10] = (dummy_nmi_handler >> 16) & 0xFF
+    output_hex_file[fib_start + 11] = (dummy_nmi_handler >> 24) & 0xFF
+
+    output_hex_file[fib_start + 12] = (dummy_hardfault_handler >> 0) & 0xFF
+    output_hex_file[fib_start + 13] = (dummy_hardfault_handler >> 8) & 0xFF
+    output_hex_file[fib_start + 14] = (dummy_hardfault_handler >> 16) & 0xFF
+    output_hex_file[fib_start + 15] = (dummy_hardfault_handler >> 24) & 0xFF
+
+    output_hex_file[fib_start + 16] = (dummy_blank >> 0) & 0xFF
+    output_hex_file[fib_start + 17] = (dummy_blank >> 8) & 0xFF
+    output_hex_file[fib_start + 18] = (dummy_blank >> 16) & 0xFF
+    output_hex_file[fib_start + 19] = (dummy_blank >> 24) & 0xFF
+
+    # Write FIB to the file in little endian
+    output_hex_file[fib_start + 20] = (start >> 0) & 0xFF
+    output_hex_file[fib_start + 21] = (start >> 8) & 0xFF
+    output_hex_file[fib_start + 22] = (start >> 16) & 0xFF
+    output_hex_file[fib_start + 23] = (start >> 24) & 0xFF
+
+    output_hex_file[fib_start + 24] = (size >> 0) & 0xFF
+    output_hex_file[fib_start + 25] = (size >> 8) & 0xFF
+    output_hex_file[fib_start + 26] = (size >> 16) & 0xFF
+    output_hex_file[fib_start + 27] = (size >> 24) & 0xFF
+
+    output_hex_file[fib_start + 28] = (crc32 >> 0) & 0xFF
+    output_hex_file[fib_start + 29] = (crc32 >> 8) & 0xFF
+    output_hex_file[fib_start + 30] = (crc32 >> 16) & 0xFF
+    output_hex_file[fib_start + 31] = (crc32 >> 24) & 0xFF
+
+    output_hex_file[fib_start + 32] = (fw_rev >> 0) & 0xFF
+    output_hex_file[fib_start + 33] = (fw_rev >> 8) & 0xFF
+    output_hex_file[fib_start + 34] = (fw_rev >> 16) & 0xFF
+    output_hex_file[fib_start + 35] = (fw_rev >> 24) & 0xFF
+
+    output_hex_file[fib_start + 36] = (checksum >> 0) & 0xFF
+    output_hex_file[fib_start + 37] = (checksum >> 8) & 0xFF
+    output_hex_file[fib_start + 38] = (checksum >> 16) & 0xFF
+    output_hex_file[fib_start + 39] = (checksum >> 24) & 0xFF
+
+    #pad the rest of the file
+    for i in range(fib_start + dummy_fib_size + fib_size, trim_area_start):
+        output_hex_file[i] = 0xFF
+
+    # Read in configuration data from the config parameter in targets.json
+    configData = Config('NCS36510')
+    paramData = configData.get_target_config_data()
+    for v in paramData.values():
+        if (v.name == "target.mac-addr-high"):
+            mac_addr_high = int(v.value, 16)
+        elif (v.name == "target.mac-addr-low"):
+            mac_addr_low = int(v.value,16)
+        elif (v.name == "target.32KHz-clk-trim"):
+            clk_32k_trim = int(v.value,16)
+        elif (v.name == "target.32MHz-clk-trim"):
+            clk_32m_trim = int(v.value,16)
+        elif (v.name == "target.rssi-trim"):
+            rssi = int(v.value,16)
+        elif (v.name == "target.txtune-trim"):
+            txtune = int(v.value,16)
+        else:
+            print("Not a valid param")
+
+    output_hex_file[trim_area_start + 0] = mac_addr_low & 0xFF
+    output_hex_file[trim_area_start + 1] = (mac_addr_low >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 2] = (mac_addr_low >> 16) & 0xFF
+    output_hex_file[trim_area_start + 3] = (mac_addr_low >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 4] = mac_addr_high & 0xFF
+    output_hex_file[trim_area_start + 5] = (mac_addr_high >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 6] = (mac_addr_high >> 16) & 0xFF
+    output_hex_file[trim_area_start + 7] = (mac_addr_high >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 8] = clk_32k_trim & 0xFF
+    output_hex_file[trim_area_start + 9] = (clk_32k_trim >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 10] = (clk_32k_trim >> 16) & 0xFF
+    output_hex_file[trim_area_start + 11] = (clk_32k_trim >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 12] = clk_32m_trim & 0xFF
+    output_hex_file[trim_area_start + 13] = (clk_32m_trim >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 14] = (clk_32m_trim >> 16) & 0xFF
+    output_hex_file[trim_area_start + 15] = (clk_32m_trim >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 16] = rssi & 0xFF
+    output_hex_file[trim_area_start + 17] = (rssi >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 18] = (rssi >> 16) & 0xFF
+    output_hex_file[trim_area_start + 19] = (rssi >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 20] = txtune & 0xFF
+    output_hex_file[trim_area_start + 21] = (txtune >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 22] = (txtune >> 16) & 0xFF
+    output_hex_file[trim_area_start + 23] = (txtune >> 24) & 0xFF
+
+    # pad the rest of the area with 0xFF
+    for i in range(trim_area_start + trim_size, user_code_start):
+        output_hex_file[i] = 0xFF
+
+    #merge two hex files
+    output_hex_file.merge(input_hex_file, overlap='error')
+
+    # Write out file(s)
+    output_hex_file.tofile(file_name_hex, 'hex')
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/REALTEK_RTL8195AM.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/REALTEK_RTL8195AM.py
new file mode 100755
index 0000000..be99164
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/REALTEK_RTL8195AM.py
@@ -0,0 +1,280 @@
+"""
+Realtek Semiconductor Corp.
+
+RTL8195A elf2bin script
+"""
+
+import sys, array, struct, os, re, subprocess
+import hashlib
+import shutil
+
+from tools.paths import TOOLS_BOOTLOADERS
+from tools.toolchains import TOOLCHAIN_PATHS
+from datetime import datetime
+
+# Constant Variables
+RAM2_RSVD = 0x00000000
+RAM2_VER = 0x8195FFFF00000000
+RAM2_TAG = 0x81950001
+RAM2_SHA = '0'
+
+def write_fixed_width_string(value, width, output):
+        # cut string to list & reverse
+        line = [value[i:i+2] for i in range(0, len(value), 2)]
+        output.write("".join([chr(long(b, 16)) for b in line]))
+
+def write_fixed_width_value(value, width, output):
+        # convert to string
+        line = format(value, '0%dx' % (width))
+        if len(line) > width:
+            print "[ERROR] value 0x%s cannot fit width %d" % (line, width)
+            sys.exit(-1)
+        # cut string to list & reverse
+        line = [line[i:i+2] for i in range(0, len(line), 2)]
+        line.reverse()
+        # convert to write buffer
+        output.write("".join([chr(long(b, 16)) for b in line]))
+
+def append_image_file(image, output):
+    input = open(image, "rb")
+    output.write(input.read())
+    input.close()
+
+def write_padding_bytes(output_name, size):
+    current_size = os.stat(output_name).st_size
+    padcount = size - current_size
+    if padcount < 0:
+        print "[ERROR] image is larger than expected size"
+        sys.exit(-1)
+    output = open(output_name, "ab")
+    output.write('\377' * padcount)
+    output.close()
+
+def sha256_checksum(filename, block_size=65536):
+    sha256 = hashlib.sha256()
+    with open(filename, 'rb') as f:
+        for block in iter(lambda: f.read(block_size), b''):
+            sha256.update(block)
+    return sha256.hexdigest()
+
+def get_version_by_time():
+    secs = int((datetime.now()-datetime(2016,11,1)).total_seconds())
+    return RAM2_VER + secs
+
+# ----------------------------
+#       main function
+# ----------------------------
+def prepend(image, entry, segment, image_ram2, image_ota):
+
+    # parse input arguments
+    output = open(image_ram2, "wb")
+
+    write_fixed_width_value(os.stat(image).st_size, 8, output)
+    write_fixed_width_value(int(entry), 8, output)
+    write_fixed_width_value(int(segment), 8, output)
+
+    RAM2_SHA = sha256_checksum(image)
+    write_fixed_width_value(RAM2_TAG, 8, output)
+    write_fixed_width_value(get_version_by_time(), 16, output)
+    write_fixed_width_string(RAM2_SHA, 64, output)
+    write_fixed_width_value(RAM2_RSVD, 8, output)
+
+    append_image_file(image, output)
+    output.close()
+
+    ota = open(image_ota, "wb")
+    write_fixed_width_value(os.stat(image).st_size, 8, ota)
+    write_fixed_width_value(int(entry), 8, ota)
+    write_fixed_width_value(int(segment), 8, ota)
+    write_fixed_width_value(0xFFFFFFFF, 8, ota)
+    write_fixed_width_value(get_version_by_time(), 16, ota)
+    write_fixed_width_string(RAM2_SHA, 64, ota)
+    write_fixed_width_value(RAM2_RSVD, 8, ota)
+
+    append_image_file(image, ota)
+    ota.close()
+
+def find_symbol(toolchain, mapfile, symbol):
+    ret = None
+
+    HEX = '0x0{,8}(?P<addr>[0-9A-Fa-f]{8})'
+    if toolchain == "GCC_ARM":
+        SYM = re.compile(r'^\s+' + HEX + r'\s+' + symbol + '\r?$')
+    elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]:
+        SYM = re.compile(r'^\s+' + HEX + r'\s+0x[0-9A-Fa-f]{8}\s+Code.*\s+i\.' + symbol + r'\s+.*$')
+    elif toolchain == "IAR":
+        SYM = re.compile(r'^' + symbol + r'\s+' + HEX + '\s+.*$')
+
+    with open(mapfile, 'r') as infile:
+        for line in infile:
+            match = re.match(SYM, line)
+            if match:
+                ret = match.group("addr")
+
+    if not ret:
+        print "[ERROR] cannot find the address of symbol " + symbol
+        return 0
+
+    return int(ret,16) | 1
+
+def parse_load_segment_gcc(image_elf):
+    # Program Headers:
+    #   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+    #   LOAD           0x000034 0x10006000 0x10006000 0x026bc 0x026bc RW  0x8
+    #   LOAD           0x0026f0 0x30000000 0x30000000 0x06338 0x06338 RWE 0x4
+    segment_list = []
+    cmd = os.path.join(TOOLCHAIN_PATHS['GCC_ARM'], 'arm-none-eabi-readelf')
+    cmd = '"' + cmd + '"' + ' -l ' + image_elf
+    for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
+        if not line.startswith("  LOAD"):
+            continue
+        segment = line.split()
+        if len(segment) != 8:
+            continue
+        offset = int(segment[1][2:], 16)
+        addr   = int(segment[2][2:], 16)
+        size   = int(segment[4][2:], 16)
+        if addr != 0 and size != 0:
+            segment_list.append((offset, addr, size))
+    return segment_list
+
+def parse_load_segment_armcc(image_elf):
+    # ====================================
+    #
+    # ** Program header #2
+    #
+    #     Type          : PT_LOAD (1)
+    #     File Offset   : 52 (0x34)
+    #     Virtual Addr  : 0x30000000
+    #     Physical Addr : 0x30000000
+    #     Size in file  : 27260 bytes (0x6a7c)
+    #     Size in memory: 42168 bytes (0xa4b8)
+    #     Flags         : PF_X + PF_W + PF_R + PF_ARM_ENTRY (0x80000007)
+    #     Alignment     : 8
+    #
+    (offset, addr, size) = (0, 0, 0)
+    segment_list = []
+    in_segment = False
+    cmd = os.path.join(TOOLCHAIN_PATHS['ARM'], 'bin', 'fromelf')
+    cmd = '"' + cmd + '"' + ' --text -v --only=none ' + image_elf
+    for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
+        if line == "":
+            pass
+        elif line.startswith("** Program header"):
+            in_segment = True
+        elif in_segment == False:
+            pass
+        elif line.startswith("============"):
+            if addr != 0 and size != 0:
+                segment_list.append((offset, addr, size))
+            in_segment = False
+            (offset, addr, size) = (0, 0, 0)
+        elif line.startswith("    Type"):
+            if not re.match(r'\s+Type\s+:\s+PT_LOAD\s.*$', line):
+                in_segment = False
+        elif line.startswith("    File Offset"):
+            match = re.match(r'^\s+File Offset\s+:\s+(?P<offset>\d+).*$', line)
+            if match:
+                offset = int(match.group("offset"))
+        elif line.startswith("    Virtual Addr"):
+            match = re.match(r'^\s+Virtual Addr\s+:\s+0x(?P<addr>[0-9a-f]+).*$', line)
+            if match:
+                addr = int(match.group("addr"), 16)
+        elif line.startswith("    Size in file"):
+            match = re.match(r'^\s+Size in file\s+:.*\(0x(?P<size>[0-9a-f]+)\).*$', line)
+            if match:
+                size = int(match.group("size"), 16)
+    return segment_list
+
+
+def parse_load_segment_iar(image_elf):
+    #   SEGMENTS:
+    #
+    #      Type Offset    Virtual   Physical File Sz Mem Sz Flags   Align
+    #      ---- ------    -------   -------- ------- ------ -----   -----
+    #   0: load   0x34 0x10006000 0x10006000  0x26bc 0x26bc 0x6  WR   0x8
+    #   1: load 0x26f0 0x30000000 0x30000000  0x6338 0x6338 0x7 XWR   0x4
+    #
+    #   SECTIONS:
+    #
+    #       Name            Type     Addr         Offset    Size Aln Lnk Inf  ESz Flags
+    #       ----            ----     ----         ------    ---- --- --- ---  --- -----
+    #    1: .shstrtab       strtab               0xfc4d8    0x60 0x4
+    #    2: .strtab         strtab               0xfc538  0xbb3f 0x4
+
+    segment_list = []
+    in_segment = False
+    cmd = os.path.join(TOOLCHAIN_PATHS['IAR'], 'bin', 'ielfdumparm')
+    cmd = '"' + cmd + '"' + ' ' + image_elf
+    for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
+        if line.startswith("  SEGMENTS:"):
+            in_segment = True
+        elif in_segment == False:
+            pass
+        elif line.startswith("  SECTIONS:"):
+            break
+        elif re.match(r'^\s+\w+:\s+load\s+.*$', line):
+            segment = line.split()
+            offset = int(segment[2][2:], 16)
+            addr   = int(segment[3][2:], 16)
+            size   = int(segment[5][2:], 16)
+            if addr < 0x10007000:
+                continue
+            if addr != 0 and size != 0:
+                segment_list.append((offset, addr, size))
+    return segment_list
+
+def parse_load_segment(toolchain, image_elf):
+    if toolchain == "GCC_ARM":
+        return parse_load_segment_gcc(image_elf)
+    elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]:
+        return parse_load_segment_armcc(image_elf)
+    elif toolchain == "IAR":
+        return parse_load_segment_iar(image_elf)
+    else:
+        return []
+
+def write_load_segment(image_elf, image_bin, segment):
+    file_elf = open(image_elf, "rb")
+    file_bin = open(image_bin, "wb")
+    for (offset, addr, size) in segment:
+        file_elf.seek(offset)
+        # write image header - size & addr
+        write_fixed_width_value(addr, 8, file_bin)
+        write_fixed_width_value(size, 8, file_bin)
+        # write load segment
+        file_bin.write(file_elf.read(size))
+        delta = size % 4
+        if delta != 0:
+            padding = 4 - delta
+            write_fixed_width_value(0x0, padding * 2, file_bin)
+    file_bin.close()
+    file_elf.close()
+
+# ----------------------------
+#       main function
+# ----------------------------
+def rtl8195a_elf2bin(t_self, image_elf, image_bin):
+    # remove target binary file/path
+    if os.path.isfile(image_bin):
+        os.remove(image_bin)
+    else:
+        shutil.rmtree(image_bin)
+
+    segment = parse_load_segment(t_self.name, image_elf)
+    write_load_segment(image_elf, image_bin, segment)
+
+    image_name = os.path.splitext(image_elf)[0]
+    image_map = image_name + '.map'
+
+    ram2_ent = find_symbol(t_self.name, image_map, "PLAT_Start")
+    ram1_bin = os.path.join(TOOLS_BOOTLOADERS, "REALTEK_RTL8195AM", "ram_1.bin")
+    ram2_bin = image_name + '-ram_2.bin'
+    ota_bin = image_name + '-ota.bin'
+    prepend(image_bin, ram2_ent, len(segment), ram2_bin, ota_bin)
+
+    # write output file
+    output = open(image_bin, "wb")
+    append_image_file(ram1_bin, output)
+    append_image_file(ram2_bin, output)
+    output.close()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/__init__.py
new file mode 100755
index 0000000..fc4b221
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/__init__.py
@@ -0,0 +1,577 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import os
+import binascii
+import struct
+import shutil
+import inspect
+import sys
+from copy import copy
+from inspect import getmro
+from collections import namedtuple, Mapping
+from tools.targets.LPC import patch
+from tools.paths import TOOLS_BOOTLOADERS
+from tools.utils import json_file_to_dict
+
+__all__ = ["target", "TARGETS", "TARGET_MAP", "TARGET_NAMES", "CORE_LABELS",
+           "HookError", "generate_py_target", "Target",
+           "CUMULATIVE_ATTRIBUTES", "get_resolution_order"]
+
+CORE_LABELS = {
+   "Cortex-M0" : ["M0", "CORTEX_M", "LIKE_CORTEX_M0", "CORTEX"],
+   "Cortex-M0+": ["M0P", "CORTEX_M", "LIKE_CORTEX_M0", "CORTEX"],
+   "Cortex-M1" : ["M1", "CORTEX_M", "LIKE_CORTEX_M1", "CORTEX"],
+   "Cortex-M3" : ["M3", "CORTEX_M", "LIKE_CORTEX_M3", "CORTEX"],
+   "Cortex-M4" : ["M4", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M4", "CORTEX"],
+   "Cortex-M4F" : ["M4", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M4", "CORTEX"],
+   "Cortex-M7" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
+   "Cortex-M7F" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
+   "Cortex-M7FD" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
+   "Cortex-A9" : ["A9", "CORTEX_A", "LIKE_CORTEX_A9", "CORTEX"],
+    "Cortex-M23": ["M23", "CORTEX_M", "LIKE_CORTEX_M23", "CORTEX"],
+    "Cortex-M23-NS": ["M23", "CORTEX_M", "LIKE_CORTEX_M23", "CORTEX"],
+    "Cortex-M33": ["M33", "CORTEX_M", "LIKE_CORTEX_M33", "CORTEX"],
+    "Cortex-M33-NS": ["M33", "CORTEX_M", "LIKE_CORTEX_M33", "CORTEX"]
+}
+
+################################################################################
+# Generic Target class that reads and interprets the data in targets.json
+
+class HookError(Exception):
+    """ A simple class that represents all the exceptions associated with
+    hooking
+    """
+    pass
+
+CACHES = {}
+def cached(func):
+    """A simple decorator used for automatically caching data returned by a
+    function
+    """
+    def wrapper(*args, **kwargs):
+        """The wrapped function itself"""
+        if not CACHES.has_key((func.__name__, args)):
+            CACHES[(func.__name__, args)] = func(*args, **kwargs)
+        return CACHES[(func.__name__, args)]
+    return wrapper
+
+
+# Cumulative attributes can have values appended to them, so they
+# need to be computed differently than regular attributes
+CUMULATIVE_ATTRIBUTES = ['extra_labels', 'macros', 'device_has', 'features']
+
+
+def get_resolution_order(json_data, target_name, order, level=0):
+    """ Return the order in which target descriptions are searched for
+    attributes. This mimics the Python 2.2 method resolution order, which
+    is what the old targets.py module used. For more details, check
+    http://makina-corpus.com/blog/metier/2014/python-tutorial-understanding-python-mro-class-search-path
+    The resolution order contains (name, level) tuples, where "name" is the
+    name of the class and "level" is the level in the inheritance hierarchy
+    (the target itself is at level 0, its first parent at level 1, its
+    parent's parent at level 2 and so on)
+    """
+    # the resolution order can't contain duplicate target names
+    if target_name not in [l[0] for l in order]:
+        order.append((target_name, level))
+    parents = json_data[target_name].get("inherits", [])
+    for par in parents:
+        order = get_resolution_order(json_data, par, order, level + 1)
+    return order
+
+
+def target(name, json_data):
+    """Construct a target object"""
+    resolution_order = get_resolution_order(json_data, name, [])
+    resolution_order_names = [tgt for tgt, _ in resolution_order]
+    return Target(name=name,
+                  json_data={key: value for key, value in json_data.items()
+                             if key in resolution_order_names},
+                  resolution_order=resolution_order,
+                  resolution_order_names=resolution_order_names)
+
+def generate_py_target(new_targets, name):
+    """Add one or more new target(s) represented as a Python dictionary
+    in 'new_targets'. It is an error to add a target with a name that
+    already exists.
+    """
+    base_targets = Target.get_json_target_data()
+    for new_target in new_targets.keys():
+        if new_target in base_targets:
+            raise Exception("Attempt to add target '%s' that already exists"
+                            % new_target)
+    total_data = {}
+    total_data.update(new_targets)
+    total_data.update(base_targets)
+    return target(name, total_data)
+
+class Target(namedtuple("Target", "name json_data resolution_order resolution_order_names")):
+    """An object to represent a Target (MCU/Board)"""
+
+    # Default location of the 'targets.json' file
+    __targets_json_location_default = os.path.join(
+        os.path.dirname(os.path.abspath(__file__)), '..', '..', 'targets', 'targets.json')
+
+    # Current/new location of the 'targets.json' file
+    __targets_json_location = None
+
+    # Extra custom targets files
+    __extra_target_json_files = []
+
+    @staticmethod
+    @cached
+    def get_json_target_data():
+        """Load the description of JSON target data"""
+        targets = json_file_to_dict(Target.__targets_json_location or
+                                    Target.__targets_json_location_default)
+
+        for extra_target in Target.__extra_target_json_files:
+            for k, v in json_file_to_dict(extra_target).iteritems():
+                if k in targets:
+                    print 'WARNING: Custom target "%s" cannot replace existing target.' % k
+                else:
+                    targets[k] = v
+
+        return targets
+
+    @staticmethod
+    def add_extra_targets(source_dir):
+        extra_targets_file = os.path.join(source_dir, "custom_targets.json")
+        if os.path.exists(extra_targets_file):
+            Target.__extra_target_json_files.append(extra_targets_file)
+            CACHES.clear()
+
+    @staticmethod
+    def set_targets_json_location(location=None):
+        """Set the location of the targets.json file"""
+        Target.__targets_json_location = (location or
+                                          Target.__targets_json_location_default)
+        Target.__extra_target_json_files = []
+        # Invalidate caches, since the location of the JSON file changed
+        CACHES.clear()
+
+    @staticmethod
+    @cached
+    def get_module_data():
+        """Get the members of this module using Python's "inspect" module"""
+        return dict([(m[0], m[1]) for m in
+                     inspect.getmembers(sys.modules[__name__])])
+
+    @staticmethod
+    def __add_paths_to_progen(data):
+        """Modify the exporter specification ("progen") by changing all
+        "template" keys to full paths
+        """
+        out = {}
+        for key, val in data.items():
+            if isinstance(val, dict):
+                out[key] = Target.__add_paths_to_progen(val)
+            elif key == "template":
+                out[key] = [os.path.join(os.path.dirname(__file__), 'export', v)
+                            for v in val]
+            else:
+                out[key] = val
+        return out
+
+    def __getattr_cumulative(self, attrname):
+        """Look for the attribute in the class and its parents, as defined by
+        the resolution order
+        """
+        tdata = self.json_data
+        # For a cumulative attribute, figure out when it was defined the
+        # last time (in attribute resolution order) then follow the "_add"
+        # and "_remove" data fields
+        for idx, tgt in enumerate(self.resolution_order):
+            # the attribute was defined at this level in the resolution
+            # order
+            if attrname in tdata[tgt[0]]:
+                def_idx = idx
+                break
+        else:
+            raise AttributeError("Attribute '%s' not found in target '%s'"
+                                 % (attrname, self.name))
+        # Get the starting value of the attribute
+        starting_value = (tdata[self.resolution_order[def_idx][0]][attrname]
+                          or [])[:]
+        # Traverse the resolution list in high inheritance to low
+        # inheritance level, left to right order to figure out all the
+        # other classes that change the definition by adding or removing
+        # elements
+        for idx in xrange(self.resolution_order[def_idx][1] - 1, -1, -1):
+            same_level_targets = [tar[0] for tar in self.resolution_order
+                                  if tar[1] == idx]
+            for tar in same_level_targets:
+                data = tdata[tar]
+                # Do we have anything to add ?
+                if data.has_key(attrname + "_add"):
+                    starting_value.extend(data[attrname + "_add"])
+                # Do we have anything to remove ?
+                if data.has_key(attrname + "_remove"):
+                    # Macros can be defined either without a value (MACRO)
+                    # or with a value (MACRO=10). When removing, we specify
+                    # only the name of the macro, without the value. So we
+                    # need to create a mapping between the macro name and
+                    # its value. This will work for extra_labels and other
+                    # type of arrays as well, since they fall into the
+                    # "macros without a value" category (simple definitions
+                    # without a value).
+                    name_def_map = {}
+                    for crtv in starting_value:
+                        if crtv.find('=') != -1:
+                            temp = crtv.split('=')
+                            if len(temp) != 2:
+                                raise ValueError(
+                                    "Invalid macro definition '%s'" % crtv)
+                            name_def_map[temp[0]] = crtv
+                        else:
+                            name_def_map[crtv] = crtv
+                    for element in data[attrname + "_remove"]:
+                        if element not in name_def_map:
+                            raise ValueError(
+                                ("Unable to remove '%s' in '%s.%s' since "
+                                 % (element, self.name, attrname)) +
+                                "it doesn't exist")
+                        starting_value.remove(name_def_map[element])
+        return starting_value
+
+    def __getattr_helper(self, attrname):
+        """Compute the value of a given target attribute"""
+        if attrname in CUMULATIVE_ATTRIBUTES:
+            return self.__getattr_cumulative(attrname)
+        else:
+            tdata = self.json_data
+            starting_value = None
+            for tgt in self.resolution_order:
+                data = tdata[tgt[0]]
+                if data.has_key(attrname):
+                    starting_value = data[attrname]
+                    break
+            else: # Attribute not found
+                raise AttributeError(
+                    "Attribute '%s' not found in target '%s'"
+                    % (attrname, self.name))
+            # 'progen' needs the full path to the template (the path in JSON is
+            # relative to tools/export)
+            if attrname == "progen":
+                return self.__add_paths_to_progen(starting_value)
+            else:
+                return starting_value
+
+    def __getattr__(self, attrname):
+        """ Return the value of an attribute. This function only computes the
+        attribute's value once, then adds it to the instance attributes (in
+        __dict__), so the next time it is returned directly
+        """
+        result = self.__getattr_helper(attrname)
+        self.__dict__[attrname] = result
+        return result
+
+    @staticmethod
+    @cached
+    def get_target(target_name):
+        """ Return the target instance starting from the target name """
+        return target(target_name, Target.get_json_target_data())
+
+
+    @property
+    def program_cycle_s(self):
+        """Special override for program_cycle_s as it's default value depends
+        upon is_disk_virtual
+        """
+        try:
+            return self.__getattr__("program_cycle_s")
+        except AttributeError:
+            return 4 if self.is_disk_virtual else 1.5
+
+    @property
+    def labels(self):
+        """Get all possible labels for this target"""
+        names = copy(self.resolution_order_names)
+        if "Target" in names:
+            names.remove("Target")
+        labels = (names + CORE_LABELS[self.core] + self.extra_labels)
+        # Automatically define UVISOR_UNSUPPORTED if the target doesn't
+        # specifically define UVISOR_SUPPORTED
+        if "UVISOR_SUPPORTED" not in labels:
+            labels.append("UVISOR_UNSUPPORTED")
+        return labels
+
+    def init_hooks(self, hook, toolchain):
+        """Initialize the post-build hooks for a toolchain. For now, this
+        function only allows "post binary" hooks (hooks that are executed
+        after the binary image is extracted from the executable file)
+
+        Positional Arguments:
+        hook - the hook object to add post-binary-hooks to
+        toolchain - the toolchain object for inspection
+        """
+
+        # If there's no hook, simply return
+        try:
+            hook_data = self.post_binary_hook
+        except AttributeError:
+            return
+        # A hook was found. The hook's name is in the format
+        # "classname.functionname"
+        temp = hook_data["function"].split(".")
+        if len(temp) != 2:
+            raise HookError(
+                ("Invalid format for hook '%s' in target '%s'"
+                 % (hook_data["function"], self.name)) +
+                " (must be 'class_name.function_name')")
+        class_name, function_name = temp
+        # "class_name" must refer to a class in this file, so check if the
+        # class exists
+        mdata = self.get_module_data()
+        if not mdata.has_key(class_name) or \
+           not inspect.isclass(mdata[class_name]):
+            raise HookError(
+                ("Class '%s' required by '%s' in target '%s'"
+                 % (class_name, hook_data["function"], self.name)) +
+                " not found in targets.py")
+        # "function_name" must refer to a static function inside class
+        # "class_name"
+        cls = mdata[class_name]
+        if (not hasattr(cls, function_name)) or \
+           (not inspect.isfunction(getattr(cls, function_name))):
+            raise HookError(
+                ("Static function '%s' " % function_name) +
+                ("required by '%s' " % hook_data["function"]) +
+                ("in target '%s' " % self.name) +
+                ("not found in class '%s'" %  class_name))
+        # Check if the hook specification also has toolchain restrictions
+        toolchain_restrictions = set(hook_data.get("toolchains", []))
+        toolchain_labels = set(c.__name__ for c in getmro(toolchain.__class__))
+        if toolchain_restrictions and \
+           not toolchain_labels.intersection(toolchain_restrictions):
+            return
+        # Finally, hook the requested function
+        hook.hook_add_binary("post", getattr(cls, function_name))
+
+################################################################################
+# Target specific code goes in this section
+# This code can be invoked from the target description using the
+# "post_binary_hook" key
+
+class LPCTargetCode(object):
+    """General LPC Target patching code"""
+    @staticmethod
+    def lpc_patch(t_self, resources, elf, binf):
+        """Patch an elf file"""
+        t_self.debug("LPC Patch: %s" % os.path.split(binf)[1])
+        patch(binf)
+
+class LPC4088Code(object):
+    """Code specific to the LPC4088"""
+    @staticmethod
+    def binary_hook(t_self, resources, elf, binf):
+        """Hook to be run after an elf file is built"""
+        if not os.path.isdir(binf):
+            # Regular binary file, nothing to do
+            LPCTargetCode.lpc_patch(t_self, resources, elf, binf)
+            return
+        outbin = open(binf + ".temp", "wb")
+        partf = open(os.path.join(binf, "ER_IROM1"), "rb")
+        # Pad the fist part (internal flash) with 0xFF to 512k
+        data = partf.read()
+        outbin.write(data)
+        outbin.write('\xFF' * (512*1024 - len(data)))
+        partf.close()
+        # Read and append the second part (external flash) in chunks of fixed
+        # size
+        chunksize = 128 * 1024
+        partf = open(os.path.join(binf, "ER_IROM2"), "rb")
+        while True:
+            data = partf.read(chunksize)
+            outbin.write(data)
+            if len(data) < chunksize:
+                break
+        partf.close()
+        outbin.close()
+        # Remove the directory with the binary parts and rename the temporary
+        # file to 'binf'
+        shutil.rmtree(binf, True)
+        os.rename(binf + '.temp', binf)
+        t_self.debug("Generated custom binary file (internal flash + SPIFI)")
+        LPCTargetCode.lpc_patch(t_self, resources, elf, binf)
+
+class TEENSY3_1Code(object):
+    """Hooks for the TEENSY3.1"""
+    @staticmethod
+    def binary_hook(t_self, resources, elf, binf):
+        """Hook that is run after elf is generated"""
+        # This function is referenced by old versions of targets.json and should
+        # be kept for backwards compatibility.
+        pass
+
+class MTSCode(object):
+    """Generic MTS code"""
+    @staticmethod
+    def _combine_bins_helper(target_name, binf):
+        """combine bins with the bootloader for a particular target"""
+        loader = os.path.join(TOOLS_BOOTLOADERS, target_name, "bootloader.bin")
+        target = binf + ".tmp"
+        if not os.path.exists(loader):
+            print "Can't find bootloader binary: " + loader
+            return
+        outbin = open(target, 'w+b')
+        part = open(loader, 'rb')
+        data = part.read()
+        outbin.write(data)
+        outbin.write('\xFF' * (64*1024 - len(data)))
+        part.close()
+        part = open(binf, 'rb')
+        data = part.read()
+        outbin.write(data)
+        part.close()
+        outbin.seek(0, 0)
+        data = outbin.read()
+        outbin.seek(0, 1)
+        crc = struct.pack('<I', binascii.crc32(data) & 0xFFFFFFFF)
+        outbin.write(crc)
+        outbin.close()
+        os.remove(binf)
+        os.rename(target, binf)
+
+    @staticmethod
+    def combine_bins_mts_dot(t_self, resources, elf, binf):
+        """A hook for the MTS MDOT"""
+        MTSCode._combine_bins_helper("MTS_MDOT_F411RE", binf)
+
+    @staticmethod
+    def combine_bins_mts_dragonfly(t_self, resources, elf, binf):
+        """A hoof for the MTS Dragonfly"""
+        MTSCode._combine_bins_helper("MTS_DRAGONFLY_F411RE", binf)
+
+class MCU_NRF51Code(object):
+    """NRF51 Hooks"""
+    @staticmethod
+    def binary_hook(t_self, resources, _, binf):
+        """Hook that merges the soft device with the bin file"""
+        # Scan to find the actual paths of soft device
+        sdf = None
+        for softdevice_and_offset_entry\
+            in t_self.target.EXPECTED_SOFTDEVICES_WITH_OFFSETS:
+            for hexf in resources.hex_files:
+                if hexf.find(softdevice_and_offset_entry['name']) != -1:
+                    t_self.debug("SoftDevice file found %s."
+                                 % softdevice_and_offset_entry['name'])
+                    sdf = hexf
+
+                if sdf is not None:
+                    break
+            if sdf is not None:
+                break
+
+        if sdf is None:
+            t_self.debug("Hex file not found. Aborting.")
+            return
+
+        # Look for bootloader file that matches this soft device or bootloader
+        # override image
+        blf = None
+        if t_self.target.MERGE_BOOTLOADER is True:
+            for hexf in resources.hex_files:
+                if hexf.find(t_self.target.OVERRIDE_BOOTLOADER_FILENAME) != -1:
+                    t_self.debug("Bootloader file found %s."
+                                 % t_self.target.OVERRIDE_BOOTLOADER_FILENAME)
+                    blf = hexf
+                    break
+                elif hexf.find(softdevice_and_offset_entry['boot']) != -1:
+                    t_self.debug("Bootloader file found %s."
+                                 % softdevice_and_offset_entry['boot'])
+                    blf = hexf
+                    break
+
+        # Merge user code with softdevice
+        from intelhex import IntelHex
+        binh = IntelHex()
+        _, ext = os.path.splitext(binf)
+        if ext == ".hex":
+            binh.loadhex(binf)
+        elif ext == ".bin":
+            binh.loadbin(binf, softdevice_and_offset_entry['offset'])
+
+        if t_self.target.MERGE_SOFT_DEVICE is True:
+            t_self.debug("Merge SoftDevice file %s"
+                         % softdevice_and_offset_entry['name'])
+            sdh = IntelHex(sdf)
+            binh.merge(sdh)
+
+        if t_self.target.MERGE_BOOTLOADER is True and blf is not None:
+            t_self.debug("Merge BootLoader file %s" % blf)
+            blh = IntelHex(blf)
+            binh.merge(blh)
+
+        with open(binf.replace(".bin", ".hex"), "w") as fileout:
+            binh.write_hex_file(fileout, write_start_addr=False)
+
+class NCS36510TargetCode:
+    @staticmethod
+    def ncs36510_addfib(t_self, resources, elf, binf):
+        from tools.targets.NCS import add_fib_at_start
+        print("binf ", binf)
+        add_fib_at_start(binf[:-4])
+
+class RTL8195ACode:
+    """RTL8195A Hooks"""
+    @staticmethod
+    def binary_hook(t_self, resources, elf, binf):
+        from tools.targets.REALTEK_RTL8195AM import rtl8195a_elf2bin
+        rtl8195a_elf2bin(t_self, elf, binf)
+################################################################################
+
+# Instantiate all public targets
+def update_target_data():
+    TARGETS[:] = [Target.get_target(tgt) for tgt, obj
+                  in Target.get_json_target_data().items()
+                  if obj.get("public", True)]
+    # Map each target name to its unique instance
+    TARGET_MAP.clear()
+    TARGET_MAP.update(dict([(tgt.name, tgt) for tgt in TARGETS]))
+    TARGET_NAMES[:] = TARGET_MAP.keys()
+
+TARGETS = []
+TARGET_MAP = dict()
+TARGET_NAMES = []
+
+update_target_data()
+
+# Some targets with different name have the same exporters
+EXPORT_MAP = {}
+
+# Detection APIs
+def get_target_detect_codes():
+    """ Returns dictionary mapping detect_code -> platform_name
+    """
+    result = {}
+    for tgt in TARGETS:
+        for detect_code in tgt.detect_code:
+            result[detect_code] = tgt.name
+    return result
+
+def set_targets_json_location(location=None):
+    """Sets the location of the JSON file that contains the targets"""
+    # First instruct Target about the new location
+    Target.set_targets_json_location(location)
+    # Then re-initialize TARGETS, TARGET_MAP and TARGET_NAMES. The
+    # re-initialization does not create new variables, it keeps the old ones
+    # instead. This ensures compatibility with code that does
+    # "from tools.targets import TARGET_NAMES"
+    update_target_data()
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/__init__.pyc
new file mode 100755
index 0000000..2238afb
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/lint.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/lint.py
new file mode 100755
index 0000000..0202d45
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/targets/lint.py
@@ -0,0 +1,277 @@
+"""A linting utility for targets.json
+
+This linting utility may be called as follows:
+python <path-to>/lint.py targets TARGET [TARGET ...]
+
+all targets will be linted
+"""
+
+# mbed SDK
+# Copyright (c) 2017 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from os.path import join, abspath, dirname
+if __name__ == "__main__":
+    import sys
+    ROOT = abspath(join(dirname(__file__), "..", ".."))
+    sys.path.insert(0, ROOT)
+from copy import copy
+from yaml import dump_all
+import argparse
+
+from tools.targets import Target, set_targets_json_location, TARGET_MAP
+
+def must_have_keys(keys, dict):
+    """Require keys in an MCU/Board
+
+    is a generator for errors
+    """
+    for key in keys:
+        if key not in dict:
+            yield "%s not found, and is required" % key
+
+def may_have_keys(keys, dict):
+    """Disable all other keys in an MCU/Board
+
+    is a generator for errors
+    """
+    for key in dict.keys():
+        if key not in keys:
+            yield "%s found, and is not allowed" % key
+
+def check_extra_labels(dict):
+    """Check that extra_labels does not contain any Target names
+
+    is a generator for errors
+    """
+    for label in (dict.get("extra_labels", []) +
+                  dict.get("extra_labels_add", [])):
+        if label in Target.get_json_target_data():
+            yield "%s is not allowed in extra_labels" % label
+
+def check_release_version(dict):
+    """Verify that release version 5 is combined with support for all toolcahins
+
+    is a generator for errors
+    """
+    if  ("release_versions" in dict and
+         "5" in dict["release_versions"] and
+         "supported_toolchains" in dict):
+        for toolc in ["GCC_ARM", "ARM", "IAR"]:
+            if toolc not in dict["supported_toolchains"]:
+                yield ("%s not found in supported_toolchains, and is "
+                       "required by mbed OS 5" % toolc)
+
+def check_inherits(dict):
+    if  ("inherits" in dict and len(dict["inherits"]) > 1):
+        yield "multiple inheritance is forbidden"
+
+DEVICE_HAS_ALLOWED = ["ANALOGIN", "ANALOGOUT", "CAN", "ETHERNET", "EMAC",
+                      "FLASH", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN",
+                      "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT",
+                      "PWMOUT", "RTC", "TRNG","SERIAL", "SERIAL_ASYNCH",
+                      "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE",
+                      "STORAGE", "STCLK_OFF_DURING_SLEEP"]
+def check_device_has(dict):
+    for name in dict.get("device_has", []):
+        if name not in DEVICE_HAS_ALLOWED:
+            yield "%s is not allowed in device_has" % name
+
+MCU_REQUIRED_KEYS = ["release_versions", "supported_toolchains",
+                     "default_lib", "public", "inherits", "device_has"]
+MCU_ALLOWED_KEYS = ["device_has_add", "device_has_remove", "core",
+                    "extra_labels", "features", "features_add",
+                    "features_remove", "bootloader_supported", "device_name",
+                    "post_binary_hook", "default_toolchain", "config",
+                    "extra_labels_add", "extra_labels_remove",
+                    "target_overrides"] + MCU_REQUIRED_KEYS
+def check_mcu(mcu_json, strict=False):
+    """Generate a list of problems with an MCU
+
+    :param: mcu_json the MCU's dict to check
+    :param: strict enforce required keys
+    """
+    errors = list(may_have_keys(MCU_ALLOWED_KEYS, mcu_json))
+    if strict:
+        errors.extend(must_have_keys(MCU_REQUIRED_KEYS, mcu_json))
+    errors.extend(check_extra_labels(mcu_json))
+    errors.extend(check_release_version(mcu_json))
+    errors.extend(check_inherits(mcu_json))
+    errors.extend(check_device_has(mcu_json))
+    if 'public' in mcu_json and mcu_json['public']:
+        errors.append("public must be false")
+    return errors
+
+BOARD_REQUIRED_KEYS = ["inherits"]
+BOARD_ALLOWED_KEYS = ["supported_form_factors", "is_disk_virtual",
+                      "detect_code", "extra_labels", "extra_labels_add",
+                      "extra_labels_remove", "public", "config",
+                      "forced_reset_timeout", "target_overrides"] + BOARD_REQUIRED_KEYS
+def check_board(board_json, strict=False):
+    """Generate a list of problems with an board
+
+    :param: board_json the mcus dict to check
+    :param: strict enforce required keys
+    """
+    errors = list(may_have_keys(BOARD_ALLOWED_KEYS, board_json))
+    if strict:
+        errors.extend(must_have_keys(BOARD_REQUIRED_KEYS, board_json))
+    errors.extend(check_extra_labels(board_json))
+    errors.extend(check_inherits(board_json))
+    return errors
+
+def add_if(dict, key, val):
+    """Add a value to a dict if it's non-empty"""
+    if val:
+        dict[key] = val
+
+def _split_boards(resolution_order, tgt):
+    """Split the resolution order between boards and mcus"""
+    mcus = []
+    boards = []
+    iterable = iter(resolution_order)
+    for name in iterable:
+        mcu_json = tgt.json_data[name]
+        if  (len(list(check_mcu(mcu_json, True))) >
+             len(list(check_board(mcu_json, True)))):
+            boards.append(name)
+        else:
+            mcus.append(name)
+            break
+    mcus.extend(iterable)
+    mcus.reverse()
+    boards.reverse()
+    return mcus, boards
+
+
+MCU_FORMAT_STRING = {1: "MCU (%s) ->",
+                     2: "Family (%s) -> MCU (%s) ->",
+                     3: "Family (%s) -> SubFamily (%s) -> MCU (%s) ->"}
+BOARD_FORMAT_STRING = {1: "Board (%s)",
+                       2: "Module (%s) -> Board (%s)"}
+def _generate_hierarchy_string(mcus, boards):
+    global_errors = []
+    if len(mcus) < 1:
+        global_errors.append("No MCUS found in heirarchy")
+        mcus_string = "??? ->"
+    elif len(mcus) > 3:
+        global_errors.append("No name for targets %s" % ", ".join(mcus[3:]))
+        mcus_string = MCU_FORMAT_STRING[3] % tuple(mcus[:3])
+        for name in mcus[3:]:
+            mcus_string += " ??? (%s) ->" % name
+    else:
+        mcus_string = MCU_FORMAT_STRING[len(mcus)] % tuple(mcus)
+
+    if len(boards) < 1:
+        global_errors.append("no boards found in heirarchy")
+        boards_string = "???"
+    elif len(boards) > 2:
+        global_errors.append("no name for targets %s" % ", ".join(boards[2:]))
+        boards_string = BOARD_FORMAT_STRING[2] % tuple(boards[:2])
+        for name in boards[2:]:
+            boards_string += " -> ??? (%s)" % name
+    else:
+        boards_string = BOARD_FORMAT_STRING[len(boards)] % tuple(boards)
+    return mcus_string + " " + boards_string, global_errors
+
+
+def check_hierarchy(tgt):
+    """Atempts to assign labels to the heirarchy"""
+    resolution_order = copy(tgt.resolution_order_names[:-1])
+    mcus, boards = _split_boards(resolution_order, tgt)
+
+    target_errors = {}
+    hierachy_string, hierachy_errors = _generate_hierarchy_string(mcus, boards)
+    to_ret = {"hierarchy": hierachy_string}
+    add_if(to_ret, "hierarchy errors", hierachy_errors)
+
+    for name in mcus[:-1]:
+        add_if(target_errors, name, list(check_mcu(tgt.json_data[name])))
+    if len(mcus) >= 1:
+        add_if(target_errors, mcus[-1],
+               list(check_mcu(tgt.json_data[mcus[-1]], True)))
+    for name in boards:
+        add_if(target_errors, name, list(check_board(tgt.json_data[name])))
+    if len(boards) >= 1:
+        add_if(target_errors, boards[-1],
+               list(check_board(tgt.json_data[boards[-1]], True)))
+    add_if(to_ret, "target errors", target_errors)
+    return to_ret
+
+PARSER = argparse.ArgumentParser(prog="targets/lint.py")
+SUBPARSERS = PARSER.add_subparsers(title="Commands")
+
+def subcommand(name, *args, **kwargs):
+    def __subcommand(command):
+        kwargs['description'] = command.__doc__
+        subparser = SUBPARSERS.add_parser(name, **kwargs)
+        for arg in args:
+            arg = dict(arg)
+            opt = arg['name']
+            del arg['name']
+
+            if isinstance(opt, basestring):
+                subparser.add_argument(opt, **arg)
+            else:
+                subparser.add_argument(*opt, **arg)
+
+        def _thunk(parsed_args):
+            argv = [arg['dest'] if 'dest' in arg else arg['name']
+                    for arg in args]
+            argv = [(arg if isinstance(arg, basestring)
+                     else arg[-1]).strip('-').replace('-', '_')
+                    for arg in argv]
+            argv = {arg: vars(parsed_args)[arg] for arg in argv
+                    if vars(parsed_args)[arg] is not None}
+
+            return command(**argv)
+
+        subparser.set_defaults(command=_thunk)
+        return command
+    return __subcommand
+
+@subcommand("targets",
+            dict(name="mcus", nargs="+", metavar="MCU",
+                 choices=TARGET_MAP.keys(), type=str.upper))
+def targets_cmd(mcus=[]):
+    """Find and print errors about specific targets"""
+    print dump_all([check_hierarchy(TARGET_MAP[m]) for m in mcus],
+                   default_flow_style=False)
+
+@subcommand("all-targets")
+def all_targets_cmd():
+    """Print all errors about all parts"""
+    print dump_all([check_hierarchy(m) for m in TARGET_MAP.values()],
+                   default_flow_style=False)
+
+@subcommand("orphans")
+def orphans_cmd():
+    """Find and print all orphan targets"""
+    orphans = Target.get_json_target_data().keys()
+    for tgt in TARGET_MAP.values():
+        for name in tgt.resolution_order_names:
+            if name in orphans:
+                orphans.remove(name)
+    if orphans:
+        print dump_all([orphans], default_flow_style=False)
+    return len(orphans)
+
+def main():
+    """entry point"""
+    options = PARSER.parse_args()
+    return options.command(options)
+
+if __name__ == "__main__":
+    sys.exit(main())
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test.py
new file mode 100755
index 0000000..7b4f631
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test.py
@@ -0,0 +1,288 @@
+#! /usr/bin/env python2
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+TEST BUILD & RUN
+"""
+import sys
+import os
+import json
+import fnmatch
+
+ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.config import ConfigException
+from tools.test_api import test_path_to_name, find_tests, get_test_config, print_tests, build_tests, test_spec_from_test_builds
+import tools.test_configs as TestConfig
+from tools.options import get_default_options_parser, extract_profile, extract_mcus
+from tools.build_api import build_project, build_library
+from tools.build_api import print_build_memory_usage
+from tools.build_api import merge_build_data
+from tools.targets import TARGET_MAP
+from tools.utils import mkdir, ToolException, NotSupportedException, args_error
+from tools.test_exporters import ReportExporter, ResultExporterType
+from utils import argparse_filestring_type, argparse_lowercase_type, argparse_many
+from utils import argparse_dir_not_parent
+from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS, TOOLCHAIN_CLASSES
+from tools.settings import CLI_COLOR_MAP
+
+if __name__ == '__main__':
+    try:
+        # Parse Options
+        parser = get_default_options_parser(add_app_config=True)
+
+        parser.add_argument("-D",
+                          action="append",
+                          dest="macros",
+                          help="Add a macro definition")
+
+        parser.add_argument("-j", "--jobs",
+                          type=int,
+                          dest="jobs",
+                          default=0,
+                          help="Number of concurrent jobs. Default: 0/auto (based on host machine's number of CPUs)")
+
+        parser.add_argument("--source", dest="source_dir",
+                          type=argparse_filestring_type,
+                            default=None, help="The source (input) directory (for sources other than tests). Defaults to current directory.", action="append")
+
+        parser.add_argument("--build", dest="build_dir", type=argparse_dir_not_parent(ROOT),
+                          default=None, help="The build (output) directory")
+
+        parser.add_argument("-l", "--list", action="store_true", dest="list",
+                          default=False, help="List (recursively) available tests in order and exit")
+
+        parser.add_argument("-p", "--paths", dest="paths",
+                          type=argparse_many(argparse_filestring_type),
+                          default=None, help="Limit the tests to those within the specified comma separated list of paths")
+
+        format_choices = ["list", "json"]
+        format_default_choice = "list"
+        format_help = "Change the format in which tests are listed. Choices include: %s. Default: %s" % (", ".join(format_choices), format_default_choice)
+        parser.add_argument("-f", "--format", dest="format",
+                            type=argparse_lowercase_type(format_choices, "format"),
+                            default=format_default_choice, help=format_help)
+
+        parser.add_argument("--continue-on-build-fail", action="store_true", dest="continue_on_build_fail",
+                          default=None, help="Continue trying to build all tests if a build failure occurs")
+
+        #TODO validate the names instead of just passing through str
+        parser.add_argument("-n", "--names", dest="names", type=argparse_many(str),
+                          default=None, help="Limit the tests to a comma separated list of names")
+
+        parser.add_argument("--test-config", dest="test_config", type=str,
+                          default=None, help="Test config for a module")
+
+        parser.add_argument("--test-spec", dest="test_spec",
+                          default=None, help="Destination path for a test spec file that can be used by the Greentea automated test tool")
+
+        parser.add_argument("--build-report-junit", dest="build_report_junit",
+                          default=None, help="Destination path for a build report in the JUnit xml format")
+        parser.add_argument("--build-data",
+                            dest="build_data",
+                            default=None,
+                            help="Dump build_data to this file")
+
+        parser.add_argument("-v", "--verbose",
+                          action="store_true",
+                          dest="verbose",
+                          default=False,
+                          help="Verbose diagnostic output")
+
+        parser.add_argument("--stats-depth",
+                            type=int,
+                            dest="stats_depth",
+                            default=2,
+                            help="Depth level for static memory report")
+
+        options = parser.parse_args()
+
+        # Filter tests by path if specified
+        if options.paths:
+            all_paths = options.paths
+        else:
+            all_paths = ["."]
+
+        all_tests = {}
+        tests = {}
+
+        # Target
+        if options.mcu is None :
+            args_error(parser, "argument -m/--mcu is required")
+        mcu = extract_mcus(parser, options)[0]
+
+        # Toolchain
+        if options.tool is None:
+            args_error(parser, "argument -t/--tool is required")
+        toolchain = options.tool[0]
+
+        if not TOOLCHAIN_CLASSES[toolchain].check_executable():
+            search_path = TOOLCHAIN_PATHS[toolchain] or "No path set"
+            args_error(parser, "Could not find executable for %s.\n"
+                               "Currently set search path: %s"
+                       % (toolchain, search_path))
+
+        # Assign config file. Precedence: test_config>app_config
+        # TODO: merge configs if both given
+        if options.test_config:
+            config = get_test_config(options.test_config, mcu)
+            if not config:
+                args_error(parser, "argument --test-config contains invalid path or identifier")
+        elif not options.app_config:
+            config = TestConfig.get_default_config(mcu)
+        else:
+            config = options.app_config
+
+        # Find all tests in the relevant paths
+        for path in all_paths:
+            all_tests.update(find_tests(path, mcu, toolchain,
+                                        app_config=config))
+
+        # Filter tests by name if specified
+        if options.names:
+            all_names = options.names
+            all_names = [x.lower() for x in all_names]
+
+            for name in all_names:
+                if any(fnmatch.fnmatch(testname, name) for testname in all_tests):
+                    for testname, test in all_tests.items():
+                        if fnmatch.fnmatch(testname, name):
+                            tests[testname] = test
+                else:
+                    print "[Warning] Test with name '%s' was not found in the available tests" % (name)
+        else:
+            tests = all_tests
+
+        if options.color:
+            # This import happens late to prevent initializing colorization when we don't need it
+            import colorize
+            if options.verbose:
+                notify = mbedToolchain.print_notify_verbose
+            else:
+                notify = mbedToolchain.print_notify
+            notify = colorize.print_in_color_notifier(CLI_COLOR_MAP, notify)
+        else:
+            notify = None
+
+        if options.list:
+            # Print available tests in order and exit
+            print_tests(tests, options.format)
+            sys.exit(0)
+        else:
+            # Build all tests
+            if not options.build_dir:
+                args_error(parser, "argument --build is required")
+
+            base_source_paths = options.source_dir
+
+            # Default base source path is the current directory
+            if not base_source_paths:
+                base_source_paths = ['.']
+
+            build_report = {}
+            build_properties = {}
+
+            library_build_success = False
+            profile = extract_profile(parser, options, toolchain)
+            try:
+                # Build sources
+                build_library(base_source_paths, options.build_dir, mcu,
+                              toolchain, jobs=options.jobs,
+                              clean=options.clean, report=build_report,
+                              properties=build_properties, name="mbed-build",
+                              macros=options.macros, verbose=options.verbose,
+                              notify=notify, archive=False,
+                              app_config=config,
+                              build_profile=profile)
+
+                library_build_success = True
+            except ToolException, e:
+                # ToolException output is handled by the build log
+                pass
+            except NotSupportedException, e:
+                # NotSupportedException is handled by the build log
+                pass
+            except Exception, e:
+                # Some other exception occurred, print the error message
+                print e
+
+            if not library_build_success:
+                print "Failed to build library"
+            else:
+                # Build all the tests
+
+                test_build_success, test_build = build_tests(tests, [options.build_dir], options.build_dir, mcu, toolchain,
+                        clean=options.clean,
+                        report=build_report,
+                        properties=build_properties,
+                        macros=options.macros,
+                        verbose=options.verbose,
+                        notify=notify,
+                        jobs=options.jobs,
+                        continue_on_build_fail=options.continue_on_build_fail,
+                        app_config=config,
+                        build_profile=profile,
+                        stats_depth=options.stats_depth)
+
+                # If a path to a test spec is provided, write it to a file
+                if options.test_spec:
+                    test_spec_data = test_spec_from_test_builds(test_build)
+
+                    # Create the target dir for the test spec if necessary
+                    # mkdir will not create the dir if it already exists
+                    test_spec_dir = os.path.dirname(options.test_spec)
+                    if test_spec_dir:
+                        mkdir(test_spec_dir)
+
+                    try:
+                        with open(options.test_spec, 'w') as f:
+                            f.write(json.dumps(test_spec_data, indent=2))
+                    except IOError, e:
+                        print "[ERROR] Error writing test spec to file"
+                        print e
+
+            # If a path to a JUnit build report spec is provided, write it to a file
+            if options.build_report_junit:
+                report_exporter = ReportExporter(ResultExporterType.JUNIT, package="build")
+                report_exporter.report_to_file(build_report, options.build_report_junit, test_suite_properties=build_properties)
+
+            # Print memory map summary on screen
+            if build_report:
+                print
+                print print_build_memory_usage(build_report)
+
+            print_report_exporter = ReportExporter(ResultExporterType.PRINT, package="build")
+            status = print_report_exporter.report(build_report)
+            if options.build_data:
+                merge_build_data(options.build_data, build_report, "test")
+
+            if status:
+                sys.exit(0)
+            else:
+                sys.exit(1)
+
+    except KeyboardInterrupt, e:
+        print "\n[CTRL+c] exit"
+    except ConfigException, e:
+        # Catching ConfigException here to prevent a traceback
+        print "[ERROR] %s" % str(e)
+    except Exception,e:
+        import traceback
+        traceback.print_exc(file=sys.stdout)
+        print "[ERROR] %s" % str(e)
+        sys.exit(1)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/build_api/build_api_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/build_api/build_api_test.py
new file mode 100755
index 0000000..9317e5a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/build_api/build_api_test.py
@@ -0,0 +1,227 @@
+"""
+mbed SDK
+Copyright (c) 2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import unittest
+from collections import namedtuple
+from mock import patch, MagicMock
+from tools.build_api import prepare_toolchain, build_project, build_library,\
+    scan_resources
+from tools.toolchains import TOOLCHAINS
+
+"""
+Tests for build_api.py
+"""
+make_mock_target = namedtuple(
+    "Target", "init_hooks name features core supported_toolchains")
+
+class BuildApiTests(unittest.TestCase):
+    """
+    Test cases for Build Api
+    """
+
+    def setUp(self):
+        """
+        Called before each test case
+
+        :return:
+        """
+        self.target = "K64F"
+        self.src_paths = ['.']
+        self.toolchain_name = "ARM"
+        self.build_path = "build_path"
+
+    def tearDown(self):
+        """
+        Called after each test case
+
+        :return:
+        """
+        pass
+
+    @patch('tools.toolchains.arm.ARM_STD.parse_dependencies',
+           return_value=["foo"])
+    @patch('tools.toolchains.mbedToolchain.need_update',
+           side_effect=[i % 2 for i in range(3000)])
+    @patch('os.mkdir')
+    @patch('tools.toolchains.exists', return_value=True)
+    @patch('tools.toolchains.mbedToolchain.dump_build_profile')
+    @patch('tools.utils.run_cmd', return_value=("", "", 0))
+    def test_always_complete_build(self, *_):
+        with MagicMock() as notify:
+            toolchain = prepare_toolchain(self.src_paths, self.build_path, self.target,
+                                          self.toolchain_name, notify=notify)
+
+            res = scan_resources(self.src_paths, toolchain)
+
+            toolchain.RESPONSE_FILES=False
+            toolchain.config_processed = True
+            toolchain.config_file = "junk"
+            toolchain.compile_sources(res)
+
+            assert any('percent' in msg[0] and msg[0]['percent'] == 100.0
+                       for _, msg, _ in notify.mock_calls if msg)
+
+
+    @patch('tools.build_api.Config')
+    def test_prepare_toolchain_app_config(self, mock_config_init):
+        """
+        Test that prepare_toolchain uses app_config correctly
+
+        :param mock_config_init: mock of Config __init__
+        :return:
+        """
+        app_config = "app_config"
+        mock_target = make_mock_target(lambda _, __ : None,
+                                       "Junk", [], "Cortex-M3", TOOLCHAINS)
+        mock_config_init.return_value = namedtuple(
+            "Config", "target has_regions name")(mock_target, False, None)
+
+        prepare_toolchain(self.src_paths, None, self.target, self.toolchain_name,
+                          app_config=app_config)
+
+        mock_config_init.assert_called_once_with(self.target, self.src_paths,
+                                                 app_config=app_config)
+
+    @patch('tools.build_api.Config')
+    def test_prepare_toolchain_no_app_config(self, mock_config_init):
+        """
+        Test that prepare_toolchain correctly deals with no app_config
+
+        :param mock_config_init: mock of Config __init__
+        :return:
+        """
+        mock_target = make_mock_target(lambda _, __ : None,
+                                       "Junk", [], "Cortex-M3", TOOLCHAINS)
+        mock_config_init.return_value = namedtuple(
+            "Config", "target has_regions name")(mock_target, False, None)
+
+        prepare_toolchain(self.src_paths, None, self.target, self.toolchain_name)
+
+        mock_config_init.assert_called_once_with(self.target, self.src_paths,
+                                                 app_config=None)
+
+    @patch('tools.build_api.scan_resources')
+    @patch('tools.build_api.mkdir')
+    @patch('os.path.exists')
+    @patch('tools.build_api.prepare_toolchain')
+    def test_build_project_app_config(self, mock_prepare_toolchain, mock_exists, _, __):
+        """
+        Test that build_project uses app_config correctly
+
+        :param mock_prepare_toolchain: mock of function prepare_toolchain
+        :param mock_exists: mock of function os.path.exists
+        :param _: mock of function mkdir (not tested)
+        :param __: mock of function scan_resources (not tested)
+        :return:
+        """
+        app_config = "app_config"
+        mock_exists.return_value = False
+        mock_prepare_toolchain().link_program.return_value = 1, 2
+        mock_prepare_toolchain().config = namedtuple(
+            "Config", "has_regions name lib_config_data")(None, None, {})
+
+        build_project(self.src_paths, self.build_path, self.target,
+                      self.toolchain_name, app_config=app_config)
+
+        args = mock_prepare_toolchain.call_args
+        self.assertTrue('app_config' in args[1],
+                        "prepare_toolchain was not called with app_config")
+        self.assertEqual(args[1]['app_config'], app_config,
+                         "prepare_toolchain was called with an incorrect app_config")
+
+    @patch('tools.build_api.scan_resources')
+    @patch('tools.build_api.mkdir')
+    @patch('os.path.exists')
+    @patch('tools.build_api.prepare_toolchain')
+    def test_build_project_no_app_config(self, mock_prepare_toolchain, mock_exists, _, __):
+        """
+        Test that build_project correctly deals with no app_config
+
+        :param mock_prepare_toolchain: mock of function prepare_toolchain
+        :param mock_exists: mock of function os.path.exists
+        :param _: mock of function mkdir (not tested)
+        :param __: mock of function scan_resources (not tested)
+        :return:
+        """
+        mock_exists.return_value = False
+        # Needed for the unpacking of the returned value
+        mock_prepare_toolchain().link_program.return_value = 1, 2
+        mock_prepare_toolchain().config = namedtuple(
+            "Config", "has_regions name lib_config_data")(None, None, {})
+
+        build_project(self.src_paths, self.build_path, self.target,
+                      self.toolchain_name)
+
+        args = mock_prepare_toolchain.call_args
+        self.assertTrue('app_config' in args[1],
+                        "prepare_toolchain was not called with app_config")
+        self.assertEqual(args[1]['app_config'], None,
+                         "prepare_toolchain was called with an incorrect app_config")
+
+    @patch('tools.build_api.scan_resources')
+    @patch('tools.build_api.mkdir')
+    @patch('os.path.exists')
+    @patch('tools.build_api.prepare_toolchain')
+    def test_build_library_app_config(self, mock_prepare_toolchain, mock_exists, _, __):
+        """
+        Test that build_library uses app_config correctly
+
+        :param mock_prepare_toolchain: mock of function prepare_toolchain
+        :param mock_exists: mock of function os.path.exists
+        :param _: mock of function mkdir (not tested)
+        :param __: mock of function scan_resources (not tested)
+        :return:
+        """
+        app_config = "app_config"
+        mock_exists.return_value = False
+
+        build_library(self.src_paths, self.build_path, self.target,
+                      self.toolchain_name, app_config=app_config)
+
+        args = mock_prepare_toolchain.call_args
+        self.assertTrue('app_config' in args[1],
+                        "prepare_toolchain was not called with app_config")
+        self.assertEqual(args[1]['app_config'], app_config,
+                         "prepare_toolchain was called with an incorrect app_config")
+
+    @patch('tools.build_api.scan_resources')
+    @patch('tools.build_api.mkdir')
+    @patch('os.path.exists')
+    @patch('tools.build_api.prepare_toolchain')
+    def test_build_library_no_app_config(self, mock_prepare_toolchain, mock_exists, _, __):
+        """
+        Test that build_library correctly deals with no app_config
+
+        :param mock_prepare_toolchain: mock of function prepare_toolchain
+        :param mock_exists: mock of function os.path.exists
+        :param _: mock of function mkdir (not tested)
+        :param __: mock of function scan_resources (not tested)
+        :return:
+        """
+        mock_exists.return_value = False
+
+        build_library(self.src_paths, self.build_path, self.target,
+                      self.toolchain_name)
+
+        args = mock_prepare_toolchain.call_args
+        self.assertTrue('app_config' in args[1],
+                        "prepare_toolchain was not called with app_config")
+        self.assertEqual(args[1]['app_config'], None,
+                         "prepare_toolchain was called with an incorrect app_config")
+
+if __name__ == '__main__':
+    unittest.main()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/lib1/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/lib1/lib2/mbed_lib.json
new file mode 100755
index 0000000..110332c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/lib1/lib2/mbed_lib.json
@@ -0,0 +1,7 @@
+{
+    "name": "lib2",
+    "config": {
+        "p1": "v_p1_lib2",
+        "p2": "v_p2_lib2"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/lib1/mbed_lib.json
new file mode 100755
index 0000000..a85bc4a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/lib1/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib1",
+    "config": {
+        "p1": "v_p1_lib1",
+        "p2": "v_p2_lib1",
+        "p3": "v_p3_lib1"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/mbed_app.json
new file mode 100755
index 0000000..4f823e5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/mbed_app.json
@@ -0,0 +1,8 @@
+{
+    "target_overrides": {
+        "test_target": {
+            "lib1.p1": "v_p1_lib1_app",
+            "lib2.p1": "v_p1_lib2_app"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/targets.json
new file mode 100755
index 0000000..9050d38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": [],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/test_data.json
new file mode 100755
index 0000000..b7a5ff3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/app_override_libs/test_data.json
@@ -0,0 +1,9 @@
+{
+   "test_target": {
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/bootloader_missing/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/bootloader_missing/mbed_app.json
new file mode 100755
index 0000000..c2ba944
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/bootloader_missing/mbed_app.json
@@ -0,0 +1,7 @@
+{
+    "target_overrides": {
+        "K64F": {
+            "target.bootloader_img": "does_not_exists.bin"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/bootloader_missing/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/bootloader_missing/test_data.json
new file mode 100755
index 0000000..8159285
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/bootloader_missing/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "not found"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/compound_inheritance/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/compound_inheritance/targets.json
new file mode 100755
index 0000000..19ad992
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/compound_inheritance/targets.json
@@ -0,0 +1,46 @@
+{
+    "base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0",
+        "config": {
+            "base1_1": "v_base1_1_b1",
+            "base1_2": "v_base1_2_b1",
+            "base1_3": "v_base1_3_b1"
+        }
+    },
+    "left_middle": {
+        "inherits": ["base"],
+        "config": {
+            "derived1": "v_derived1_d1",
+            "derived2": "v_derived2_d1"
+        },
+        "overrides": {
+            "base1_1": "v_base1_1_d1",
+            "base1_2": "v_base1_2_d1"
+        }
+    },
+    "right_middle": {
+        "inherits": ["base"],
+        "config": {
+            "base2_1": "v_base2_1_b2",
+            "base2_2": "v_base2_2_b2"
+        },
+        "overrides": {
+            "base1_2": "v_base1_2_b2"
+        }
+    },
+    "inherits_diamond": {
+        "inherits": ["left_middle", "right_middle"],
+        "config": {
+            "f1_1": "v_f1_1_f",
+            "f1_2": "v_f1_2_f"
+        },
+        "overrides": {
+            "base2_1": "v_base2_1_f",
+            "base1_1": "v_base1_1_f",
+            "derived2": "v_derived2_f",
+            "f1_1": "v_f1_1_f_override"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/compound_inheritance/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/compound_inheritance/test_data.json
new file mode 100755
index 0000000..89871d7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/compound_inheritance/test_data.json
@@ -0,0 +1,20 @@
+{
+    "inherits_diamond": {
+        "target.base1_1": "v_base1_1_f",
+        "target.base1_2": "v_base1_2_b2",
+        "target.base1_3": "v_base1_3_b1",
+        "target.derived1": "v_derived1_d1",
+        "target.derived2": "v_derived2_f",
+        "target.base2_1": "v_base2_1_f",
+        "target.base2_2": "v_base2_2_b2",
+        "target.f1_1": "v_f1_1_f_override",
+        "target.f1_2": "v_f1_2_f"
+    },
+    "right_middle": {
+        "target.base1_1": "v_base1_1_b1",
+        "target.base1_2": "v_base1_2_b2",
+        "target.base1_3": "v_base1_3_b1",
+        "target.base2_1": "v_base2_1_b2",
+        "target.base2_2": "v_base2_2_b2"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/config_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/config_test.py
new file mode 100755
index 0000000..157dcb7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/config_test.py
@@ -0,0 +1,175 @@
+"""
+mbed SDK
+Copyright (c) 2011-2017 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import os
+import sys
+import json
+import pytest
+from mock import patch
+from hypothesis import given
+from hypothesis.strategies import sampled_from
+from os.path import join, isfile, dirname, abspath
+from tools.build_api import get_config
+from tools.targets import set_targets_json_location, Target, TARGET_NAMES
+from tools.config import ConfigException, Config
+
+def compare_config(cfg, expected):
+    """Compare the output of config against a dictionary of known good results
+
+    :param cfg: the configuration to check
+    :param expected: what to expect in that config
+    """
+    try:
+        for k in cfg:
+            if cfg[k].value != expected[k]:
+                return "'%s': expected '%s', got '%s'" % (k, expected[k], cfg[k].value)
+    except KeyError:
+        return "Unexpected key '%s' in configuration data" % k
+    for k in expected:
+        if k not in ["expected_macros", "expected_features"] + cfg.keys():
+            return "Expected key '%s' was not found in configuration data" % k
+    return ""
+
+def data_path(path):
+    """The expected data file for a particular test
+
+    :param path: the path to the test
+    """
+    return join(path, "test_data.json")
+
+def is_test(path):
+    """Does a directory represent a test?
+
+    :param path: the path to the test
+    """
+    return isfile(data_path(path))
+
+root_dir = abspath(dirname(__file__))
+
+@pytest.mark.parametrize("name", filter(lambda d: is_test(join(root_dir, d)),
+                                        os.listdir(root_dir)))
+def test_config(name):
+    """Run a particular configuration test
+
+    :param name: test name (same as directory name)
+    """
+    test_dir = join(root_dir, name)
+    test_data = json.load(open(data_path(test_dir)))
+    targets_json = os.path.join(test_dir, "targets.json")
+    set_targets_json_location(targets_json if isfile(targets_json) else None)
+    for target, expected in test_data.items():
+        try:
+            cfg, macros, features = get_config(test_dir, target, "GCC_ARM")
+            res = compare_config(cfg, expected)
+            assert not(res), res
+            expected_macros = expected.get("expected_macros", None)
+            expected_features = expected.get("expected_features", None)
+
+            if expected_macros is not None:
+                macros = Config.config_macros_to_macros(macros)
+                assert sorted(expected_macros) == sorted(macros)
+            if expected_features is not None:
+                assert sorted(expected_features) == sorted(features)
+        except ConfigException as e:
+            err_msg = e.message
+            if "exception_msg" not in expected:
+                assert not(err_msg), "Unexpected Error: %s" % e
+            else:
+                assert expected["exception_msg"] in err_msg
+
+
+@pytest.mark.parametrize("target", ["K64F"])
+def test_init_app_config(target):
+    """
+    Test that the initialisation correctly uses app_config
+
+    :param target: The target to use
+    """
+    set_targets_json_location()
+    with patch.object(Config, '_process_config_and_overrides'),\
+         patch('tools.config.json_file_to_dict') as mock_json_file_to_dict:
+        app_config = "app_config"
+        mock_return = {'config': {'test': False}}
+        mock_json_file_to_dict.return_value = mock_return
+
+        config = Config(target, app_config=app_config)
+
+        mock_json_file_to_dict.assert_called_with(app_config)
+        assert config.app_config_data == mock_return
+
+
+@pytest.mark.parametrize("target", ["K64F"])
+def test_init_no_app_config(target):
+    """
+    Test that the initialisation works without app config
+
+    :param target: The target to use
+    """
+    set_targets_json_location()
+    with patch.object(Config, '_process_config_and_overrides'),\
+         patch('tools.config.json_file_to_dict') as mock_json_file_to_dict:
+        config = Config(target)
+
+        mock_json_file_to_dict.assert_not_called()
+        assert config.app_config_data == {}
+
+
+@pytest.mark.parametrize("target", ["K64F"])
+def test_init_no_app_config_with_dir(target):
+    """
+    Test that the initialisation works without app config and with a
+    specified top level directory
+
+    :param target: The target to use
+    """
+    set_targets_json_location()
+    with patch.object(Config, '_process_config_and_overrides'),\
+         patch('os.path.isfile') as mock_isfile, \
+         patch('tools.config.json_file_to_dict') as mock_json_file_to_dict:
+        directory = '.'
+        path = os.path.join('.', 'mbed_app.json')
+        mock_return = {'config': {'test': False}}
+        mock_json_file_to_dict.return_value = mock_return
+        mock_isfile.return_value = True
+
+        config = Config(target, [directory])
+
+        mock_isfile.assert_called_with(path)
+        mock_json_file_to_dict.assert_called_once_with(path)
+        assert config.app_config_data == mock_return
+
+
+@pytest.mark.parametrize("target", ["K64F"])
+def test_init_override_app_config(target):
+    """
+    Test that the initialisation uses app_config instead of top_level_dir
+    when both are specified
+
+    :param target: The target to use
+    """
+    set_targets_json_location()
+    with patch.object(Config, '_process_config_and_overrides'),\
+         patch('tools.config.json_file_to_dict') as mock_json_file_to_dict:
+        app_config = "app_config"
+        directory = '.'
+        mock_return = {'config': {'test': False}}
+        mock_json_file_to_dict.return_value = mock_return
+
+        config = Config(target, [directory], app_config=app_config)
+
+        mock_json_file_to_dict.assert_called_once_with(app_config)
+        assert config.app_config_data == mock_return
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/double_define/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/double_define/targets.json
new file mode 100755
index 0000000..2dddbe2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/double_define/targets.json
@@ -0,0 +1,35 @@
+{
+    "first_base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0",
+        "config": {
+            "base1_1": "v_base1_1_b1",
+            "base1_2": "v_base1_2_b1",
+            "base1_3": "v_base1_3_b1"
+        }
+    },
+    "second_base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0",
+        "config": {
+            "base2_1": "v_base2_1_b2",
+            "base2_2": "v_base2_2_b2",
+            "base1_1": "v_base1_1_b2"
+        }
+    },
+    "double_config": {
+        "inherits": ["first_base", "second_base"],
+        "config": {
+            "f1_1": "v_f1_1_f",
+            "f1_2": "v_f1_2_f"
+        },
+        "overrides": {
+            "base2_1": "v_base2_1_f",
+            "base1_1": "v_base1_1_f",
+            "derived2": "v_derived2_f",
+            "f1_1": "v_f1_1_f_override"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/double_define/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/double_define/test_data.json
new file mode 100755
index 0000000..7c01c06
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/double_define/test_data.json
@@ -0,0 +1,10 @@
+{
+    "double_config": {
+        "exception_msg": "Parameter name 'base1_1' defined in both 'target:second_base' and 'target:first_base'"
+    },
+    "second_base": {
+        "target.base2_1": "v_base2_1_b2",
+        "target.base2_2": "v_base2_2_b2",
+        "target.base1_1": "v_base1_1_b2"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/lib1/mbed_lib.json
new file mode 100755
index 0000000..5795978
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/lib1/mbed_lib.json
@@ -0,0 +1,3 @@
+{
+    "name": "lib1"
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/lib2/mbed_lib.json
new file mode 100755
index 0000000..5795978
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/lib2/mbed_lib.json
@@ -0,0 +1,3 @@
+{
+    "name": "lib1"
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/test_data.json
new file mode 100755
index 0000000..65689b1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/duplicate_lib_name/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "Library name 'lib1' is not unique"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/lib1/mbed_lib.json
new file mode 100755
index 0000000..07e6e62
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/lib1/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib1",
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["IPV4"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/mbed_app.json
new file mode 100755
index 0000000..9509bfe
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/mbed_app.json
@@ -0,0 +1,7 @@
+{
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["STORAGE"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/targets.json
new file mode 100755
index 0000000..9050d38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": [],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/test_data.json
new file mode 100755
index 0000000..48c56ee
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_compesition/test_data.json
@@ -0,0 +1,5 @@
+{
+    "test_target": {
+        "expected_features": ["IPV4", "STORAGE"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/lib1/mbed_lib.json
new file mode 100755
index 0000000..07e6e62
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/lib1/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib1",
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["IPV4"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/lib2/mbed_lib.json
new file mode 100755
index 0000000..c635513
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/lib2/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib2",
+    "target_overrides": {
+        "*": {
+            "target.features_remove": ["IPV4"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/mbed_app.json
new file mode 100755
index 0000000..9509bfe
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/mbed_app.json
@@ -0,0 +1,7 @@
+{
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["STORAGE"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/test_data.json
new file mode 100755
index 0000000..b239265
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_conflict/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "Configuration conflict. The feature IPV4 both added and removed." 
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/FEATURE_IPV4/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/FEATURE_IPV4/lib1/mbed_lib.json
new file mode 100755
index 0000000..4ba0309
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/FEATURE_IPV4/lib1/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib1",
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["STORAGE"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/FEATURE_STORAGE/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/FEATURE_STORAGE/lib2/mbed_lib.json
new file mode 100755
index 0000000..73b5776
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/FEATURE_STORAGE/lib2/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib2",
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["UVISOR"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/mbed_app.json
new file mode 100755
index 0000000..56af1f5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/mbed_app.json
@@ -0,0 +1,7 @@
+{
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["IPV4"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/targets.json
new file mode 100755
index 0000000..9050d38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": [],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/test_data.json
new file mode 100755
index 0000000..08885e7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_add/test_data.json
@@ -0,0 +1,5 @@
+{
+    "test_target": {
+        "expected_features": ["IPV4", "STORAGE", "UVISOR"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/FEATURE_IPV4/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/FEATURE_IPV4/lib1/mbed_lib.json
new file mode 100755
index 0000000..4ba0309
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/FEATURE_IPV4/lib1/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib1",
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["STORAGE"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/FEATURE_STORAGE/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/FEATURE_STORAGE/lib2/mbed_lib.json
new file mode 100755
index 0000000..5fd4a81
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/FEATURE_STORAGE/lib2/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib2",
+    "config": {
+        "test": {
+            "value": "BAD"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/mbed_app.json
new file mode 100755
index 0000000..1d926c1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/mbed_app.json
@@ -0,0 +1,8 @@
+{
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["IPV4"],
+            "lib2.test": "GOOD"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/targets.json
new file mode 100755
index 0000000..9050d38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": [],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/test_data.json
new file mode 100755
index 0000000..04be347
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_recursive_complex/test_data.json
@@ -0,0 +1,5 @@
+{
+    "test_target": {
+        "lib2.test": "GOOD"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/lib1/mbed_lib.json
new file mode 100755
index 0000000..415bbe9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/lib1/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib1",
+    "target_overrides": {
+        "*": {
+            "target.features_remove": ["IPV4"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/targets.json
new file mode 100755
index 0000000..e1bd55f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": ["IPV4"],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/test_data.json
new file mode 100755
index 0000000..8fa0d08
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_remove/test_data.json
@@ -0,0 +1,5 @@
+{
+    "test_target": {
+        "expected_features": []
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/mbed_app.json
new file mode 100755
index 0000000..95c895d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/mbed_app.json
@@ -0,0 +1,8 @@
+{
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["UVISOR"],
+            "target.extra_labels_add": ["UVISOR_SUPPORTED"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/targets.json
new file mode 100755
index 0000000..9050d38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": [],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/test_data.json
new file mode 100755
index 0000000..0c29a33
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/feature_uvisor/test_data.json
@@ -0,0 +1,5 @@
+{
+    "test_target": {
+        "expected_features": ["UVISOR"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/FEATURE_STORAGE/FEATURE_IPV4/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/FEATURE_STORAGE/FEATURE_IPV4/lib1/mbed_lib.json
new file mode 100755
index 0000000..4ba0309
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/FEATURE_STORAGE/FEATURE_IPV4/lib1/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib1",
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["STORAGE"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/FEATURE_STORAGE/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/FEATURE_STORAGE/lib2/mbed_lib.json
new file mode 100755
index 0000000..73b5776
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/FEATURE_STORAGE/lib2/mbed_lib.json
@@ -0,0 +1,8 @@
+{
+    "name": "lib2",
+    "target_overrides": {
+        "*": {
+            "target.features_add": ["UVISOR"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/mbed_app.json
new file mode 100755
index 0000000..b4ad583
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/mbed_app.json
@@ -0,0 +1,7 @@
+{
+    "target_overrides": {
+        "*": {
+            "target.features": ["IPV4", "STORAGE"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/test_data.json
new file mode 100755
index 0000000..b31573b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/fetaure_recursive_conflict/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "Configuration conflict. The feature UVISOR both added and removed." 
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/lib1/mbed_lib.json
new file mode 100755
index 0000000..705f737
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/lib1/mbed_lib.json
@@ -0,0 +1,4 @@
+{
+    "name": "lib1",
+    "macros": ["LIB1_1=1", "LIB1_2"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/lib2/mbed_lib.json
new file mode 100755
index 0000000..10b20f8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/lib2/mbed_lib.json
@@ -0,0 +1,4 @@
+{
+    "name": "lib2",
+    "macros": ["LIB2_1=5", "LIB1_2"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/mbed_app.json
new file mode 100755
index 0000000..89eb28c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/mbed_app.json
@@ -0,0 +1,3 @@
+{
+    "macros": ["APP1=10", "APP2", "LIB2_1=10"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/test_data.json
new file mode 100755
index 0000000..e679e6f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_app_macro_define/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "Macro 'LIB2_1' defined in both 'library:lib2' and 'application' with incompatible values"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key/mbed_app.json
new file mode 100755
index 0000000..59cbd29
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key/mbed_app.json
@@ -0,0 +1,3 @@
+{
+    "unknown_key": "dummy_value"
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key/test_data.json
new file mode 100755
index 0000000..564461a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "Unknown key(s)"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key_lib/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key_lib/lib1/mbed_lib.json
new file mode 100755
index 0000000..bd529cf
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key_lib/lib1/mbed_lib.json
@@ -0,0 +1,4 @@
+{
+    "name": "lib1",
+    "unknown_key": "dummy_value"
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key_lib/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key_lib/test_data.json
new file mode 100755
index 0000000..564461a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_key_lib/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "Unknown key(s)"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/lib1/mbed_lib.json
new file mode 100755
index 0000000..705f737
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/lib1/mbed_lib.json
@@ -0,0 +1,4 @@
+{
+    "name": "lib1",
+    "macros": ["LIB1_1=1", "LIB1_2"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/lib2/mbed_lib.json
new file mode 100755
index 0000000..3db0d01
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/lib2/mbed_lib.json
@@ -0,0 +1,4 @@
+{
+    "name": "lib2",
+    "macros": ["LIB2_1=5", "LIB1_2=3"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/mbed_app.json
new file mode 100755
index 0000000..f50a39b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/mbed_app.json
@@ -0,0 +1,3 @@
+{
+    "macros": ["APP1=10", "APP2", "LIB2_1=5"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/test_data.json
new file mode 100755
index 0000000..34835b1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/invalid_lib_macro_define/test_data.json
@@ -0,0 +1,5 @@
+{
+    "K64F": {
+        "exception_msg": "defined in both"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/lib1/mbed_lib.json
new file mode 100755
index 0000000..705f737
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/lib1/mbed_lib.json
@@ -0,0 +1,4 @@
+{
+    "name": "lib1",
+    "macros": ["LIB1_1=1", "LIB1_2"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/lib2/mbed_lib.json
new file mode 100755
index 0000000..10b20f8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/lib2/mbed_lib.json
@@ -0,0 +1,4 @@
+{
+    "name": "lib2",
+    "macros": ["LIB2_1=5", "LIB1_2"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/mbed_app.json
new file mode 100755
index 0000000..f50a39b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/mbed_app.json
@@ -0,0 +1,3 @@
+{
+    "macros": ["APP1=10", "APP2", "LIB2_1=5"]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/targets.json
new file mode 100755
index 0000000..9050d38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": [],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/test_data.json
new file mode 100755
index 0000000..a513dc9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/macro_inheritance/test_data.json
@@ -0,0 +1,5 @@
+{
+    "test_target": {
+        "expected_macros": ["APP1=10", "APP2", "LIB1_1=1","LIB1_2", "LIB2_1=5"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/lib1/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/lib1/lib2/mbed_lib.json
new file mode 100755
index 0000000..117a8c6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/lib1/lib2/mbed_lib.json
@@ -0,0 +1,17 @@
+{
+    "name": "lib2",
+    "config": {
+        "p1": "v_p1_lib2",
+        "p2": "v_p2_lib2"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib2[b1_label]",
+            "p2": "v_p2_lib2[b1_label]"
+        },
+        "b2_label": {
+            "p1": "v_p1_lib2[b2_label]",
+            "p2": "v_p2_lib2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/lib1/mbed_lib.json
new file mode 100755
index 0000000..0481e02
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/lib1/mbed_lib.json
@@ -0,0 +1,16 @@
+{
+    "name": "lib1",
+    "config": {
+        "p1": "v_p1_lib1",
+        "p2": "v_p2_lib1",
+        "p3": "v_p3_lib1"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib1[b1_label]"
+        },
+        "b2_label": {
+            "p2": "v_p2_lib1[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/mbed_app.json
new file mode 100755
index 0000000..3245209
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/mbed_app.json
@@ -0,0 +1,14 @@
+{
+    "config": {
+        "app1": "v_app1",
+        "app2": "v_app2"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "app1": "v_app1[b1_label]"
+        },
+        "b2_label": {
+            "app2": "v_app2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/targets.json
new file mode 100755
index 0000000..d045de8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/targets.json
@@ -0,0 +1,18 @@
+{
+    "base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0"
+    },
+    "b1": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b1_label"]
+    },
+    "b2": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b2_label"]
+    },
+    "both": {
+        "inherits": ["b1", "b2"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/test_data.json
new file mode 100755
index 0000000..df30ae9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs/test_data.json
@@ -0,0 +1,38 @@
+{
+   "base": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1",
+        "lib2.p1": "v_p1_lib2",
+        "lib2.p2": "v_p2_lib2"
+    },
+    "b1": {
+        "app.app1": "v_app1[b1_label]",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1[b1_label]",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1",
+        "lib2.p1": "v_p1_lib2[b1_label]",
+        "lib2.p2": "v_p2_lib2[b1_label]"
+    },
+    "b2": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1",
+        "lib2.p1": "v_p1_lib2[b2_label]",
+        "lib2.p2": "v_p2_lib2[b2_label]"
+    },
+    "both": {
+        "app.app1": "v_app1[b1_label]",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1[b1_label]",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1",
+        "lib2.p1": "v_p1_lib2[b2_label]",
+        "lib2.p2": "v_p2_lib2[b2_label]"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/lib1/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/lib1/lib2/mbed_lib.json
new file mode 100755
index 0000000..117a8c6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/lib1/lib2/mbed_lib.json
@@ -0,0 +1,17 @@
+{
+    "name": "lib2",
+    "config": {
+        "p1": "v_p1_lib2",
+        "p2": "v_p2_lib2"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib2[b1_label]",
+            "p2": "v_p2_lib2[b1_label]"
+        },
+        "b2_label": {
+            "p1": "v_p1_lib2[b2_label]",
+            "p2": "v_p2_lib2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/lib1/mbed_lib.json
new file mode 100755
index 0000000..0481e02
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/lib1/mbed_lib.json
@@ -0,0 +1,16 @@
+{
+    "name": "lib1",
+    "config": {
+        "p1": "v_p1_lib1",
+        "p2": "v_p2_lib1",
+        "p3": "v_p3_lib1"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib1[b1_label]"
+        },
+        "b2_label": {
+            "p2": "v_p2_lib1[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/mbed_app.json
new file mode 100755
index 0000000..809ef1c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/mbed_app.json
@@ -0,0 +1,19 @@
+{
+    "config": {
+        "app1": "v_app1",
+        "app2": "v_app2"
+    },
+    "target_overrides": {
+        "*": {
+            "lib1.p3": "v_p3_lib1_app",
+            "lib1.p1": "v_p1_lib1_app",
+            "lib2.p1": "v_p1_lib2_app"
+        },
+        "b1_label": {
+            "app1": "v_app1[b1_label]"
+        },
+        "b2_label": {
+            "app2": "v_app2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/targets.json
new file mode 100755
index 0000000..d045de8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/targets.json
@@ -0,0 +1,18 @@
+{
+    "base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0"
+    },
+    "b1": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b1_label"]
+    },
+    "b2": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b2_label"]
+    },
+    "both": {
+        "inherits": ["b1", "b2"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/test_data.json
new file mode 100755
index 0000000..46ae967
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_libs_more/test_data.json
@@ -0,0 +1,38 @@
+{
+   "base": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2"
+    },
+    "b1": {
+        "app.app1": "v_app1[b1_label]",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b1_label]"
+    },
+    "b2": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b2_label]"
+    },
+    "both": {
+        "app.app1": "v_app1[b1_label]",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b2_label]"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/lib1/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/lib1/lib2/mbed_lib.json
new file mode 100755
index 0000000..117a8c6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/lib1/lib2/mbed_lib.json
@@ -0,0 +1,17 @@
+{
+    "name": "lib2",
+    "config": {
+        "p1": "v_p1_lib2",
+        "p2": "v_p2_lib2"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib2[b1_label]",
+            "p2": "v_p2_lib2[b1_label]"
+        },
+        "b2_label": {
+            "p1": "v_p1_lib2[b2_label]",
+            "p2": "v_p2_lib2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/lib1/mbed_lib.json
new file mode 100755
index 0000000..0481e02
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/lib1/mbed_lib.json
@@ -0,0 +1,16 @@
+{
+    "name": "lib1",
+    "config": {
+        "p1": "v_p1_lib1",
+        "p2": "v_p2_lib1",
+        "p3": "v_p3_lib1"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib1[b1_label]"
+        },
+        "b2_label": {
+            "p2": "v_p2_lib1[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/mbed_app.json
new file mode 100755
index 0000000..8cd35f9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/mbed_app.json
@@ -0,0 +1,20 @@
+{
+    "config": {
+        "app1": "v_app1",
+        "app2": "v_app2"
+    },
+    "target_overrides": {
+        "*": {
+            "lib1.p3": "v_p3_lib1_app",
+            "lib1.p1": "v_p1_lib1_app",
+            "lib2.p1": "v_p1_lib2_app",
+            "target.par1": "v_par1_target_app"
+        },
+        "b1_label": {
+            "app1": "v_app1[b1_label]"
+        },
+        "b2_label": {
+            "app2": "v_app2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/targets.json
new file mode 100755
index 0000000..1f360cb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/targets.json
@@ -0,0 +1,35 @@
+{
+    "base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0",
+        "config": {
+            "par1": "v_par1_base",
+            "par2": "v_par2_base",
+            "par3": "v_par3_base"
+        }
+    },
+    "b1": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b1_label"],
+        "overrides": {
+            "par1": "v_par1_b1"
+        }
+    },
+    "b2": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b2_label"],
+        "overrides": {
+            "par2": "v_par2_b2"
+        }
+    },
+    "both": {
+        "inherits": ["b1", "b2"],
+        "config": {
+            "par4": "v_par4_both"
+        },
+        "overrides": {
+            "par3": "v_par3_both"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/test_data.json
new file mode 100755
index 0000000..f115f5b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_labels_targets/test_data.json
@@ -0,0 +1,51 @@
+{
+   "base": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_base",
+        "target.par3": "v_par3_base"
+    },
+    "b1": {
+        "app.app1": "v_app1[b1_label]",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b1_label]",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_base",
+        "target.par3": "v_par3_base"
+    },
+    "b2": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b2_label]",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_b2",
+        "target.par3": "v_par3_base"
+    },
+    "both": {
+        "app.app1": "v_app1[b1_label]",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b2_label]",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_b2",
+        "target.par3": "v_par3_both",
+        "target.par4": "v_par4_both"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/lib1/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/lib1/lib2/mbed_lib.json
new file mode 100755
index 0000000..117a8c6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/lib1/lib2/mbed_lib.json
@@ -0,0 +1,17 @@
+{
+    "name": "lib2",
+    "config": {
+        "p1": "v_p1_lib2",
+        "p2": "v_p2_lib2"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib2[b1_label]",
+            "p2": "v_p2_lib2[b1_label]"
+        },
+        "b2_label": {
+            "p1": "v_p1_lib2[b2_label]",
+            "p2": "v_p2_lib2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/lib1/mbed_lib.json
new file mode 100755
index 0000000..0481e02
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/lib1/mbed_lib.json
@@ -0,0 +1,16 @@
+{
+    "name": "lib1",
+    "config": {
+        "p1": "v_p1_lib1",
+        "p2": "v_p2_lib1",
+        "p3": "v_p3_lib1"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib1[b1_label]"
+        },
+        "b2_label": {
+            "p2": "v_p2_lib1[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/mbed_app.json
new file mode 100755
index 0000000..d2f4373
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/mbed_app.json
@@ -0,0 +1,24 @@
+{
+    "config": {
+        "app1": "v_app1",
+        "app2": "v_app2"
+    },
+    "target_overrides": {
+        "*": {
+            "lib1.p3": "v_p3_lib1_app",
+            "lib1.p1": "v_p1_lib1_app",
+            "lib2.p1": "v_p1_lib2_app",
+            "target.par1": "v_par1_target_app"
+        },
+        "b1_label": {
+            "app.app1": "v_app1[b1_label_label]"
+        },
+        "b2_label": {
+            "app2": "v_app2[b2_label]"
+        },
+        "both": {
+            "target.par4": "v_par4_app[both_label]",
+            "lib2.p1": "v_p1_lib2_app[both_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/targets.json
new file mode 100755
index 0000000..1f360cb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/targets.json
@@ -0,0 +1,35 @@
+{
+    "base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0",
+        "config": {
+            "par1": "v_par1_base",
+            "par2": "v_par2_base",
+            "par3": "v_par3_base"
+        }
+    },
+    "b1": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b1_label"],
+        "overrides": {
+            "par1": "v_par1_b1"
+        }
+    },
+    "b2": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b2_label"],
+        "overrides": {
+            "par2": "v_par2_b2"
+        }
+    },
+    "both": {
+        "inherits": ["b1", "b2"],
+        "config": {
+            "par4": "v_par4_both"
+        },
+        "overrides": {
+            "par3": "v_par3_both"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/test_data.json
new file mode 100755
index 0000000..fd853cb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_precidence/test_data.json
@@ -0,0 +1,51 @@
+{
+   "base": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_base",
+        "target.par3": "v_par3_base"
+    },
+    "b1": {
+        "app.app1": "v_app1[b1_label_label]",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b1_label]",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_base",
+        "target.par3": "v_par3_base"
+    },
+    "b2": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app",
+        "lib2.p2": "v_p2_lib2[b2_label]",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_b2",
+        "target.par3": "v_par3_base"
+    },
+    "both": {
+        "app.app1": "v_app1[b1_label_label]",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1_app",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1_app",
+        "lib2.p1": "v_p1_lib2_app[both_label]",
+        "lib2.p2": "v_p2_lib2[b2_label]",
+        "target.par1": "v_par1_target_app",
+        "target.par2": "v_par2_b2",
+        "target.par3": "v_par3_both",
+        "target.par4": "v_par4_app[both_label]"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined/targets.json
new file mode 100755
index 0000000..ae1cf7c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined/targets.json
@@ -0,0 +1,45 @@
+{
+    "first_base_target": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0",
+        "config": {
+            "base1_1": "v_base1_1_b1",
+            "base1_2": "v_base1_2_b1",
+            "base1_3": "v_base1_3_b1"
+        }
+    },
+    "intermediate": {
+        "inherits": ["first_base_target"],
+        "config": {
+            "derived1": "v_derived1_d1",
+            "derived2": "v_derived2_d1"
+        },
+        "overrides": {
+            "base1_1": "v_base1_1_d1",
+            "base1_2": "v_base1_2_d1"
+        }
+    },
+    "second_base_target": {
+        "config": {
+            "base2_1": "v_base2_1_b2",
+            "base2_2": "v_base2_2_b2"
+        },
+        "overrides": {
+            "base1_1": "v_base1_1_b2"
+        }
+    },
+    "should_fail": {
+        "inherits": ["second_base_target", "intermediate"],
+        "config": {
+            "f1_1": "v_f1_1_f",
+            "f1_2": "v_f1_2_f"
+        },
+        "overrides": {
+            "base2_1": "v_base2_1_f",
+            "base1_1": "v_base1_1_f",
+            "derived2": "v_derived2_f",
+            "f1_1": "v_f1_1_f_override"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined/test_data.json
new file mode 100755
index 0000000..f5ca657
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined/test_data.json
@@ -0,0 +1,12 @@
+{
+    "should_fail": {
+        "exception_msg": "Attempt to override undefined parameter 'base1_1' in 'target:second_base_target'"
+    },
+    "intermediate": {
+        "target.base1_1": "v_base1_1_d1",
+        "target.base1_2": "v_base1_2_d1",
+        "target.base1_3": "v_base1_3_b1",
+        "target.derived1": "v_derived1_d1",
+        "target.derived2": "v_derived2_d1"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/lib1/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/lib1/lib2/mbed_lib.json
new file mode 100755
index 0000000..117a8c6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/lib1/lib2/mbed_lib.json
@@ -0,0 +1,17 @@
+{
+    "name": "lib2",
+    "config": {
+        "p1": "v_p1_lib2",
+        "p2": "v_p2_lib2"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib2[b1_label]",
+            "p2": "v_p2_lib2[b1_label]"
+        },
+        "b2_label": {
+            "p1": "v_p1_lib2[b2_label]",
+            "p2": "v_p2_lib2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/lib1/mbed_lib.json
new file mode 100755
index 0000000..0481e02
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/lib1/mbed_lib.json
@@ -0,0 +1,16 @@
+{
+    "name": "lib1",
+    "config": {
+        "p1": "v_p1_lib1",
+        "p2": "v_p2_lib1",
+        "p3": "v_p3_lib1"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "p1": "v_p1_lib1[b1_label]"
+        },
+        "b2_label": {
+            "p2": "v_p2_lib1[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/mbed_app.json
new file mode 100755
index 0000000..d995ff0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/mbed_app.json
@@ -0,0 +1,15 @@
+{
+    "config": {
+        "app1": "v_app1",
+        "app2": "v_app2"
+    },
+    "target_overrides": {
+        "b1_label": {
+            "app1": "v_app1[b1_label]",
+            "app_wrong": "v_dummy"
+        },
+        "b2_label": {
+            "app2": "v_app2[b2_label]"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/targets.json
new file mode 100755
index 0000000..16c687b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/targets.json
@@ -0,0 +1,18 @@
+{
+    "base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0"
+    },
+    "left_intermediate": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b1_label"]
+    },
+    "right_intermediate": {
+        "inherits": ["base"],
+        "extra_labels_add": ["b2_label"]
+    },
+    "both": {
+        "inherits": ["left_intermediate", "right_intermediate"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/test_data.json
new file mode 100755
index 0000000..15c8062
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_undefined_libs/test_data.json
@@ -0,0 +1,26 @@
+{
+   "base": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2",
+        "lib1.p1": "v_p1_lib1",
+        "lib1.p2": "v_p2_lib1",
+        "lib1.p3": "v_p3_lib1",
+        "lib2.p1": "v_p1_lib2",
+        "lib2.p2": "v_p2_lib2"
+    },
+    "left_intermediate": {
+        "exception_msg": "Attempt to override undefined parameter 'app.app_wrong' in 'application[b1_label]"
+    },
+    "right_intermediate": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2[b2_label]",
+        "lib1.p1": "v_p1_lib1",
+        "lib1.p2": "v_p2_lib1[b2_label]",
+        "lib1.p3": "v_p3_lib1",
+        "lib2.p1": "v_p1_lib2[b2_label]",
+        "lib2.p2": "v_p2_lib2[b2_label]"
+    },
+    "both": {
+        "exception_msg": "Attempt to override undefined parameter 'app.app_wrong' in 'application[b1_label]"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/mbed_app.json
new file mode 100755
index 0000000..716165a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/mbed_app.json
@@ -0,0 +1,18 @@
+{
+    "config": {
+        "app1": "v_app1",
+        "app2": "v_app2"
+    },
+    "target_overrides": {
+        "left_intermediate_label": {
+            "app1": "v_app1[left_intermediate_label]"
+        },
+        "right_intermediate_label": {
+            "app2": "v_app2[right_intermediate_label]"
+        },
+        "dummy_label": {
+            "app1": "dummy.app1",
+            "app2": "dummy.app2"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/targets.json
new file mode 100755
index 0000000..3d78e3e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/targets.json
@@ -0,0 +1,18 @@
+{
+    "base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0"
+    },
+    "left_intermediate": {
+        "inherits": ["base"],
+        "extra_labels_add": ["left_intermediate_label"]
+    },
+    "right_intermediate": {
+        "inherits": ["base"],
+        "extra_labels_add": ["right_intermediate_label"]
+    },
+    "both": {
+        "inherits": ["left_intermediate", "right_intermediate"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/test_data.json
new file mode 100755
index 0000000..7fbc15e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/override_with_labels/test_data.json
@@ -0,0 +1,18 @@
+{
+    "left_intermediate": {
+        "app.app1": "v_app1[left_intermediate_label]",
+        "app.app2": "v_app2"
+    },
+    "right_intermediate": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2[right_intermediate_label]"
+    },
+    "both": {
+        "app.app1": "v_app1[left_intermediate_label]",
+        "app.app2": "v_app2[right_intermediate_label]"
+    },
+    "base": {
+        "app.app1": "v_app1",
+        "app.app2": "v_app2"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/lib1/lib2/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/lib1/lib2/mbed_lib.json
new file mode 100755
index 0000000..110332c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/lib1/lib2/mbed_lib.json
@@ -0,0 +1,7 @@
+{
+    "name": "lib2",
+    "config": {
+        "p1": "v_p1_lib2",
+        "p2": "v_p2_lib2"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/lib1/mbed_lib.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/lib1/mbed_lib.json
new file mode 100755
index 0000000..cbdaf70
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/lib1/mbed_lib.json
@@ -0,0 +1,14 @@
+{
+    "name": "lib1",
+    "config": {
+        "p1": "v_p1_lib1",
+        "p2": "v_p2_lib1",
+        "p3": "v_p3_lib1"
+    },
+    "target_overrides": {
+        "K64F": {
+            "p1": "v_p1_lib1[b1_label]",
+            "lib2.p1": "dummy"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/test_data.json
new file mode 100755
index 0000000..1975443
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/parameter_outside_lib/test_data.json
@@ -0,0 +1,5 @@
+{
+   "K64F": {
+        "exception_msg": "Invalid prefix 'lib2' for parameter name 'lib2.p1' in 'library:lib1[K64F]'"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/mbed_app.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/mbed_app.json
new file mode 100755
index 0000000..3c809f7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/mbed_app.json
@@ -0,0 +1,7 @@
+{
+    "target_overrides": {
+        "*": {
+            "target.features": ["IPV4"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/targets.json
new file mode 100755
index 0000000..9050d38
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/targets.json
@@ -0,0 +1,8 @@
+{
+    "test_target": {
+        "core": "Cortex-M0",
+        "extra_labels": [],
+        "features": [],
+        "default_lib": "std"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/test_data.json
new file mode 100755
index 0000000..2639e0b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_features/test_data.json
@@ -0,0 +1,5 @@
+{
+    "test_target": {
+        "expected_features": ["IPV4"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_iheritance/targets.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_iheritance/targets.json
new file mode 100755
index 0000000..1608366
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_iheritance/targets.json
@@ -0,0 +1,42 @@
+{
+    "first_base": {
+        "extra_labels": [],
+        "default_lib": "std",
+        "core": "Cortex-M0",
+        "config": {
+            "base1_1": "v_base1_1_b1",
+            "base1_2": "v_base1_2_b1",
+            "base1_3": "v_base1_3_b1"
+        }
+    },
+    "intermediate": {
+        "inherits": ["first_base"],
+        "config": {
+            "derived1": "v_derived1_d1",
+            "derived2": "v_derived2_d1"
+        },
+        "overrides": {
+            "base1_1": "v_base1_1_d1",
+            "base1_2": "v_base1_2_d1"
+        }
+    },
+    "second_base": {
+        "config": {
+            "base2_1": "v_base2_1_b2",
+            "base2_2": "v_base2_2_b2"
+        }
+    },
+    "inherits_tree": {
+        "inherits": ["second_base", "intermediate"],
+        "config": {
+            "f1_1": "v_f1_1_f",
+            "f1_2": "v_f1_2_f"
+        },
+        "overrides": {
+            "base2_1": "v_base2_1_f",
+            "base1_1": "v_base1_1_f",
+            "derived2": "v_derived2_f",
+            "f1_1": "v_f1_1_f_override"
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_iheritance/test_data.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_iheritance/test_data.json
new file mode 100755
index 0000000..10ba4a7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/config/simple_iheritance/test_data.json
@@ -0,0 +1,25 @@
+{
+    "inherits_tree": {
+        "target.base1_1": "v_base1_1_f",
+        "target.base1_2": "v_base1_2_d1",
+        "target.base1_3": "v_base1_3_b1",
+        "target.derived1": "v_derived1_d1",
+        "target.derived2": "v_derived2_f",
+        "target.base2_1": "v_base2_1_f",
+        "target.base2_2": "v_base2_2_b2",
+        "target.f1_1": "v_f1_1_f_override",
+        "target.f1_2": "v_f1_2_f"
+    },
+    "first_base": {
+        "target.base1_1": "v_base1_1_b1",
+        "target.base1_2": "v_base1_2_b1",
+        "target.base1_3": "v_base1_3_b1"
+    },
+    "intermediate": {
+        "target.base1_1": "v_base1_1_d1",
+        "target.base1_2": "v_base1_2_d1",
+        "target.base1_3": "v_base1_3_b1",
+        "target.derived1": "v_derived1_d1",
+        "target.derived2": "v_derived2_d1"
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/detect_targets_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/detect_targets_test.py
new file mode 100755
index 0000000..be21a32
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/detect_targets_test.py
@@ -0,0 +1,160 @@
+"""
+mbed SDK
+Copyright (c) 2017 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import unittest
+from mock import patch
+from tools.detect_targets import get_interface_version
+
+
+class MbedLsToolsMock():
+    """
+    Mock of mbedls tools
+    """
+    
+    def __init__(self, test_type):
+        self.interface_test_type = test_type
+    
+    def get_details_txt(self, mount_point):
+        return self.details_txt_types[self.interface_test_type];
+    
+    # Static details.txt types.
+    details_txt_types = {    
+        'details_valid_interface_version' : {
+            'Unique ID': '0226000029164e45002f0012706e0006f301000097969900',
+            'HIF ID': '97969900',
+            'Auto Reset': '0',
+            'Automation allowed': '0',
+            'Daplink Mode': 'Interface',
+            'Interface Version': '0240',
+            'Git SHA': 'c765cbb590f57598756683254ca38b211693ae5e',
+            'Local Mods': '0',
+            'USB Interfaces': 'MSD, CDC, HID',
+            'Interface CRC': '0x26764ebf'
+        },
+        'details_valid_version' : {
+            'Version': '0226',
+            'Build':   'Aug 24 2015 17:06:30',
+            'Git Commit SHA': '27a236b9fe39c674a703c5c89655fbd26b8e27e1',
+            'Git Local mods': 'Yes'
+        }, 
+        'details_missing_interface_version' : {
+            'Unique ID': '0226000033514e450044500585d4001de981000097969900',
+            'HIC ID': '97969900',
+            'Auto Reset': '0',
+            'Automation allowed': '0',
+            'Overflow detection': '0',
+            'Daplink Mode': 'Interface',
+            'Git SHA': 'b403a07e3696cee1e116d44cbdd64446e056ce38',
+            'Local Mods': '0',
+            'USB Interfaces': 'MSD, CDC, HID',
+            'Interface CRC': '0x4d98bf7e',
+            'Remount count': '0'
+        },
+        'details_invalid_none' : None
+    }
+
+"""
+Tests for detect_targets.py
+"""
+
+class DetectTargetsTest(unittest.TestCase):
+    """
+    Test cases for Detect Target functionality
+    """
+
+    def setUp(self):
+        """
+        Called before each test case
+
+        :return:
+        """      
+        self.missing_mount_point = None
+        self.mount_point = "D:"
+
+    def tearDown(self):
+        """
+        Nothing to tear down.
+        Called after each test case
+
+        :return:
+        """
+        pass
+    
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_interface_version'))
+    def test_interface_version_valid(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when given a valid Interface Version
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == '0240'
+        
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_version'))
+    def test_version_valid(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when given a valid Version
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == '0226'
+        
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_missing_interface_version'))
+    def test_interface_version_missing_interface_version(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when DETAILS.txt is present
+        but an interface version is not listed.
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == 'unknown'
+        
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_invalid_none'))
+    def test_version_none(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when a valid mount point is supplied
+        but DETAILS.txt is not present.
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+        
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == 'unknown'
+    
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_invalid_none'))
+    def test_interface_version_missing_mount_point(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when no mount point is supplied.
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+        
+        interface_version = get_interface_version(self.missing_mount_point)
+        assert interface_version == 'unknown'
+
+if __name__ == '__main__':
+    unittest.main()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples.json
new file mode 100755
index 0000000..e2b9167
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples.json
@@ -0,0 +1,228 @@
+{ 
+  "update-config" : {
+      "help" : "Update each example repo with a version of mbed-os identified by the tag",
+      "via-fork" : {
+        "help" : "-f cmd line option. Update a fork",
+        "github-user" : "adbridge"          
+      },
+      "via-branch" : {
+        "help" : "-b cmd line option. Update dst branch, created from src branch",
+        "src-branch" : "mbed-os-5.5.0-rc1-oob",
+        "dst-branch" : "mbed-os-5.5.0-rc2-oob"    
+      },
+      "tag" : "mbed-os-5.5.0-rc2"
+  },
+  "examples": [
+    {
+      "name": "mbed-os-example-blinky",
+      "github": "https://github.com/ARMmbed/mbed-os-example-blinky",
+      "mbed": [
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-blinky"
+      ],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : [],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-tls",
+      "github": "https://github.com/ARMmbed/mbed-os-example-tls",
+      "mbed": [
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-benchmark",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-tls-client",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-hashing",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-authcrypt"
+      ],
+      "test-repo-source": "mbed",
+      "features" : [],
+      "targets" : ["K64F", "NUCLEO_F429ZI"],
+      "toolchains" : ["GCC_ARM", "ARM"],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-mesh-minimal",
+      "github":"https://github.com/ARMmbed/mbed-os-example-mesh-minimal",
+      "mbed": [
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-mesh-minimal"
+      ],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["DISCO_F469NI", "DISCO_F746NG", "K64F", "K66F",
+                   "NUCLEO_F429ZI", "NUCLEO_F439ZI", "NUCLEO_F746ZG",
+                   "NUCLEO_F756ZG", "NUCLEO_F767ZI",
+                   "NUMAKER_PFM_NUC472", "UBLOX_EVK_ODIN_W2"],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-ble",
+      "github":"https://github.com/ARMmbed/mbed-os-example-ble",
+      "mbed": [
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Beacon",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-HeartRate",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Thermometer",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-LEDBlinker",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-LED",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-GAPButton",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Button",
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-BatteryLevel"
+      ],
+      "test-repo-source": "mbed",
+      "features" : ["BLE"],
+      "targets" : ["NRF51_DK", "NRF52_DK", "K64F", "NUCLEO_F401RE"],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": false,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-client",
+      "github":"https://github.com/ARMmbed/mbed-os-example-client",
+      "mbed": [
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-client"
+      ],
+      "test-repo-source": "github",
+      "features" : ["LWIP"],
+      "targets" : [],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : false,
+      "export": false,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-sockets",
+      "github":"https://github.com/ARMmbed/mbed-os-example-sockets",
+      "mbed": [
+      ],
+      "test-repo-source": "github",
+      "features" : ["LWIP"],
+      "targets" : [],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-wifi",
+      "github":"https://github.com/ARMmbed/mbed-os-example-wifi",
+      "mbed": [
+      ],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : [],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : false,
+      "export": false,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-uvisor",
+      "github":"https://github.com/ARMmbed/mbed-os-example-uvisor",
+      "mbed": [],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["K64F"],
+      "toolchains" : ["GCC_ARM"],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : false
+    },
+    {
+      "name": "mbed-os-example-uvisor-thread",
+      "github":"https://github.com/ARMmbed/mbed-os-example-uvisor-thread",
+      "mbed": [],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["K64F"],
+      "toolchains" : ["GCC_ARM"],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : false
+    },
+    {
+      "name": "mbed-os-example-uvisor-number-store",
+      "github":"https://github.com/ARMmbed/mbed-os-example-uvisor-number-store",
+      "mbed": [],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["K64F"],
+      "toolchains" : ["GCC_ARM"],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : false
+    },
+    {
+      "name": "mbed-os-example-bootloader",
+      "github":"https://github.com/ARMmbed/mbed-os-example-bootloader",
+      "mbed": [
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-bootloader"
+      ],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["K64F", "NUCLEO_F429ZI", "UBLOX_EVK_ODIN_W2"],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : true
+    },
+    {
+      "name": "mbed-os-example-fat-filesystem",
+      "github":"https://github.com/ARMmbed/mbed-os-example-fat-filesystem",
+      "mbed": [
+          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-fat-filesystem"
+      ],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["K64F"],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : true
+    },
+    {
+      "name": "nanostack-border-router",
+      "github":"https://github.com/ARMmbed/nanostack-border-router",
+      "mbed": [],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["K64F", "K66F", "NUCLEO_F429ZI"],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : false
+    },
+    {
+      "name": "mbed-os-example-cellular",
+      "github":"https://github.com/ARMmbed/mbed-os-example-cellular",
+      "mbed": [],
+      "test-repo-source": "github",
+      "features" : [],
+      "targets" : ["MTS_DRAGONFLY_F411RE"],
+      "toolchains" : [],
+      "exporters": [],
+      "compile" : true,
+      "export": true,
+      "auto-update" : true
+    }
+  ]
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples.py
new file mode 100755
index 0000000..fcc3485
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples.py
@@ -0,0 +1,133 @@
+""" import and bulid a bunch of example programs """
+
+from argparse import ArgumentParser
+import os
+from os.path import dirname, abspath, basename
+import os.path
+import sys
+import subprocess
+import json
+
+ROOT = abspath(dirname(dirname(dirname(dirname(__file__)))))
+sys.path.insert(0, ROOT)
+
+from tools.utils import argparse_force_uppercase_type
+from tools.utils import argparse_many
+from tools.build_api import get_mbed_official_release
+import examples_lib as lib
+from examples_lib import SUPPORTED_TOOLCHAINS, SUPPORTED_IDES
+
+def main():
+    """Entry point"""
+
+    official_targets = get_mbed_official_release("5")
+    official_target_names = [x[0] for x in official_targets]
+
+
+    parser = ArgumentParser()
+    parser.add_argument("-c", dest="config", default="examples.json")
+    parser.add_argument("-e", "--example",
+                        help=("filter the examples used in the script"),
+                        type=argparse_many(lambda x: x),
+                        default=[])
+    subparsers = parser.add_subparsers()
+    import_cmd = subparsers.add_parser("import")
+    import_cmd.set_defaults(fn=do_import)
+    clone_cmd = subparsers.add_parser("clone")
+    clone_cmd.set_defaults(fn=do_clone)
+    deploy_cmd = subparsers.add_parser("deploy")
+    deploy_cmd.set_defaults(fn=do_deploy)
+    version_cmd = subparsers.add_parser("tag")
+    version_cmd.add_argument("tag")
+    version_cmd.set_defaults(fn=do_versionning)
+    compile_cmd = subparsers.add_parser("compile")
+    compile_cmd.set_defaults(fn=do_compile),
+    compile_cmd.add_argument(
+        "toolchains", nargs="*", default=SUPPORTED_TOOLCHAINS,
+        type=argparse_force_uppercase_type(SUPPORTED_TOOLCHAINS,
+                                           "toolchain")),
+    compile_cmd.add_argument("-m", "--mcu",
+                             help=("build for the given MCU (%s)" %
+                                ', '.join(official_target_names)),
+                            metavar="MCU",
+                            type=argparse_many(
+                                argparse_force_uppercase_type(
+                                    official_target_names, "MCU")),
+                            default=official_target_names)
+
+    compile_cmd.add_argument("--profile",
+                             help=("build profile file"),
+                             metavar="profile")
+
+    export_cmd = subparsers.add_parser("export")
+    export_cmd.set_defaults(fn=do_export),
+    export_cmd.add_argument(
+        "ide", nargs="*", default=SUPPORTED_IDES,
+        type=argparse_force_uppercase_type(SUPPORTED_IDES,
+                                           "ide"))
+    export_cmd.add_argument("-m", "--mcu",
+                             help=("build for the given MCU (%s)" %
+                                ', '.join(official_target_names)),
+                            metavar="MCU",
+                            type=argparse_many(
+                                argparse_force_uppercase_type(
+                                    official_target_names, "MCU")),
+                            default=official_target_names)
+    args = parser.parse_args()
+    config = json.load(open(os.path.join(os.path.dirname(__file__),
+                               args.config)))
+
+    all_examples = []
+    for example in config['examples']:
+        all_examples = all_examples + [basename(x['repo']) for x in lib.get_repo_list(example)]
+    examples = [x for x in all_examples if x in args.example] if args.example else all_examples
+    return args.fn(args, config, examples)
+
+
+def do_export(args, config, examples):
+    """Do export and build step"""
+    results = {}
+    results = lib.export_repos(config, args.ide, args.mcu, examples)
+
+    lib.print_summary(results, export=True)
+    failures = lib.get_num_failures(results, export=True)
+    print("Number of failures = %d" % failures)
+    return failures
+
+
+def do_import(_, config, examples):
+    """Do the import step of this process"""
+    lib.source_repos(config, examples)
+    return 0
+
+
+def do_clone(_, config, examples):
+    """Do the clone step of this process"""
+    lib.clone_repos(config, examples)
+    return 0
+
+
+def do_deploy(_, config, examples):
+    """Do the deploy step of this process"""
+    lib.deploy_repos(config, examples)
+    return 0
+
+
+def do_compile(args, config, examples):
+    """Do the compile step"""
+    results = {}
+    results = lib.compile_repos(config, args.toolchains, args.mcu, args.profile, examples)
+    
+    lib.print_summary(results)
+    failures = lib.get_num_failures(results)
+    print("Number of failures = %d" % failures)
+    return failures 
+    
+def do_versionning(args, config, examples):
+    """ Test update the mbed-os to the version specified by the tag """
+    lib.update_mbedos_version(config, args.tag, examples)
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples_lib.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples_lib.py
new file mode 100755
index 0000000..d57aa19
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/examples_lib.py
@@ -0,0 +1,407 @@
+""" Import and bulid a bunch of example programs
+
+    This library includes functions that are shared between the examples.py and
+    the update.py modules.
+
+ """
+import os
+from os.path import dirname, abspath, basename
+import os.path
+import sys
+import subprocess
+from shutil import rmtree
+from sets import Set
+
+ROOT = abspath(dirname(dirname(dirname(dirname(__file__)))))
+sys.path.insert(0, ROOT)
+
+from tools.build_api import get_mbed_official_release
+from tools.targets import TARGET_MAP
+from tools.export import EXPORTERS
+
+SUPPORTED_TOOLCHAINS = ["ARM", "IAR", "GCC_ARM", "ARMC6"]
+SUPPORTED_IDES = [exp for exp in EXPORTERS.keys() if exp != "cmsis" and exp != "zip"]
+
+
+def print_list(lst):
+    """Prints to screen the contents of a list
+
+    Args:
+    lst - a list of any type, to be displayed
+
+    """
+    if lst:
+        for thing in lst:
+            print("# %s" % thing)
+
+
+def print_category(results, index, message):
+    summary = [example for key, summ in results.iteritems()
+               for example in summ[index]]
+    if all(len(s) == 0 for s in summary):
+        return
+    print("#")
+    print("#" * 80)
+    print("# %s" % message)
+    print("#" * 80)
+    split_summ = [s.rsplit(" ", 1) for s in summary]
+
+    print_list(summary)
+
+
+def print_summary(results, export=False):
+    """Prints to screen the results of compiling/exporting combinations of example programs,
+       targets and compile toolchains/IDEs.
+
+    Args:
+    results - results of the compilation stage. See compile_repos() and export_repos()
+              for details of the format.
+
+    """
+
+    print("#"*80)
+    print("# Examples compilation summary")
+    print("#"*80)
+
+    print_category(results, 2, "Passed example combinations")
+
+    second_result = "Failed example combinations" if not export else \
+        "Failed export example combinations"
+
+    print_category(results, 3, second_result)
+
+    if export:
+        print_category(results, 4, "Failed build combinations")
+        print_category(results, 5, "Skipped build combinations")
+
+    print("#")
+    print("#"*80)
+
+def valid_choices(allowed_choices, all_choices):
+    if len(allowed_choices) > 0:
+        return [t for t in all_choices if t in allowed_choices]
+    else:
+        return all_choices
+
+
+def target_cross_toolchain(allowed_targets, allowed_toolchains, features=[]):
+    """Generate pairs of target and toolchains
+
+    Args:
+    allowed_targets - a list of all possible targets
+    allowed_toolchains - a list of all possible toolchains
+
+    Kwargs:
+    features - the features that must be in the features array of a
+               target
+    """
+    for target in allowed_targets:
+        for toolchain in allowed_toolchains:
+            if all(feature in TARGET_MAP[target].features
+                    for feature in features):
+                yield target, toolchain
+
+
+def target_cross_ide(allowed_targets, allowed_ides, features=[], toolchains=[]):
+    """Generate pairs of target and ides
+
+    Args:
+    allowed_targets - a list of all possible targets
+    allowed_ides - a list of all possible IDEs
+
+    Kwargs:
+    features - the features that must be in the features array of a
+               target
+    """
+    for target in allowed_targets:
+        for ide in allowed_ides:
+            if (EXPORTERS[ide].is_target_supported(target) and
+                (not toolchains or EXPORTERS[ide].TOOLCHAIN in toolchains) and
+                all(feature in TARGET_MAP[target].features
+                    for feature in features)):
+                yield target, ide
+
+
+def get_repo_list(example):
+    """ Returns a list of all the repos and their types associated with the
+        specific example in the json config file.
+        If the key 'test-repo-source' is set to 'mbed', then it will return the
+        mbed section as a list. Otherwise, it will return the single github repo.
+        NOTE: This does not currently deal with multiple examples underneath a github
+        sourced exampe repo.
+
+    Args:
+    example - Example for which the repo list is requested
+
+    """
+    repos = []
+    if example['test-repo-source'] == 'mbed':
+        for repo in example['mbed']:
+            repos.append({
+                'repo': repo,
+                'type': 'hg'
+            })
+    else:
+        repos.append({
+            'repo': example['github'],
+            'type': 'git'
+        })
+    return repos
+
+
+def source_repos(config, examples):
+    """ Imports each of the repos and its dependencies (.lib files) associated
+        with the specific examples name from the json config file. Note if
+        there is already a clone of the repo then it will first be removed to
+        ensure a clean, up to date cloning.
+    Args:
+    config - the json object imported from the file.
+
+    """
+    print("\nImporting example repos....\n")
+    for example in config['examples']:
+        for repo_info in get_repo_list(example):
+            name = basename(repo_info['repo'])
+            if name in examples:
+                if os.path.exists(name):
+                    print("'%s' example directory already exists. Deleting..." % name)
+                    rmtree(name)
+
+                subprocess.call(["mbed-cli", "import", repo_info['repo']])
+
+def clone_repos(config, examples , retry = 3):
+    """ Clones each of the repos associated with the specific examples name from the
+        json config file. Note if there is already a clone of the repo then it will first
+        be removed to ensure a clean, up to date cloning.
+    Args:
+    config - the json object imported from the file.
+
+    """
+    print("\nCloning example repos....\n")
+    for example in config['examples']:
+        for repo_info in get_repo_list(example):
+            name = basename(repo_info['repo'])
+            if name in examples:
+                if os.path.exists(name):
+                    print("'%s' example directory already exists. Deleting..." % name)
+                    rmtree(name)
+                for i in range(0, retry):
+                    if subprocess.call([repo_info['type'], "clone", repo_info['repo']]) == 0:
+                        break
+                else:
+                    print("ERROR : unable to clone the repo {}".format(name))
+
+def deploy_repos(config, examples):
+    """ If the example directory exists as provided by the json config file,
+        pull in the examples dependencies by using `mbed-cli deploy`.
+    Args:
+    config - the json object imported from the file.
+
+    """
+    print("\nDeploying example repos....\n")
+    for example in config['examples']:
+        for repo_info in get_repo_list(example):
+            name = basename(repo_info['repo'])
+            if name in examples:
+                if os.path.exists(name):
+                    os.chdir(name)
+                    subprocess.call(["mbed-cli", "deploy"])
+                    os.chdir("..")
+                else:
+                    print("'%s' example directory doesn't exist. Skipping..." % name)
+
+
+def get_num_failures(results, export=False):
+    """ Returns the number of failed compilations from the results summary
+    Args:
+    results - results summary of the compilation stage. See compile_repos() for
+              details of the format.
+    num_failures
+
+    """
+    num_failures = 0
+
+    for key, val in results.iteritems():
+        num_failures = num_failures + len(val[3])
+        if export:
+            num_failures += len(val[4])
+
+    return num_failures
+
+def export_repos(config, ides, targets, examples):
+    """Exports and builds combinations of example programs, targets and IDEs.
+
+        The results are returned in a [key: value] dictionary format:
+            Where key = The example name from the json config file
+            value = a list containing: pass_status, successes, export failures, build_failures,
+            and build_skips
+
+            where pass_status = The overall pass status for the export of the full
+            set of example programs comprising the example suite.
+            IE they must build and export) True if all examples pass, false otherwise
+            successes = list of examples that exported and built (if possible)
+            If the exporter has no build functionality, then it is a pass
+            if exported
+            export_failures = list of examples that failed to export.
+            build_failures = list of examples that failed to build
+            build_skips = list of examples that cannot build
+
+            Both successes and failures contain the example name, target and IDE
+
+            Args:
+            config - the json object imported from the file.
+            ides - List of IDES to export to
+    """
+    results = {}
+    valid_examples = Set(examples)
+    print("\nExporting example repos....\n")
+    for example in config['examples']:
+        example_names = [basename(x['repo']) for x in get_repo_list(example)]
+        common_examples = valid_examples.intersection(Set(example_names))
+        if not common_examples:
+            continue
+        export_failures = []
+        build_failures = []
+        build_skips = []
+        successes = []
+        exported = True
+        pass_status = True
+        if example['export']:
+            for repo_info in get_repo_list(example):
+                example_project_name = basename(repo_info['repo'])
+                os.chdir(example_project_name)
+                # Check that the target, IDE, and features combinations are valid and return a
+                # list of valid combinations to work through
+                for target, ide in target_cross_ide(valid_choices(example['targets'], targets),
+                                                    valid_choices(example['exporters'], ides),
+                                                    example['features'], example['toolchains']):
+                    example_name = "{} {} {}".format(example_project_name, target,
+                                                     ide)
+                    def status(message):
+                        print(message + " %s" % example_name)
+                        sys.stdout.flush()
+
+                    status("Exporting")
+                    proc = subprocess.Popen(["mbed-cli", "export", "-i", ide,
+                                             "-m", target])
+                    proc.wait()
+                    if proc.returncode:
+                        export_failures.append(example_name)
+                        status("FAILURE exporting")
+                    else:
+                        status("SUCCESS exporting")
+                        status("Building")
+                        try:
+                            if EXPORTERS[ide].build(example_project_name):
+                                status("FAILURE building")
+                                build_failures.append(example_name)
+                            else:
+                                status("SUCCESS building")
+                                successes.append(example_name)
+                        except TypeError:
+                            successes.append(example_name)
+                            build_skips.append(example_name)
+                os.chdir("..")
+
+                if len(build_failures+export_failures) > 0:
+                    pass_status= False
+        else:
+            exported = False
+
+        results[example['name']] = [exported, pass_status, successes,
+                                    export_failures, build_failures, build_skips]
+
+    return results
+
+
+def compile_repos(config, toolchains, targets, profile, examples):
+    """Compiles combinations of example programs, targets and compile chains.
+
+       The results are returned in a [key: value] dictionary format:
+       Where key = The example name from the json config file
+             value = a list containing: pass_status, successes, and failures
+
+             where pass_status = The overall pass status for the compilation of the full
+                                 set of example programs comprising the example suite.
+                                 True if all examples pass, false otherwise
+                   successes = list of passing examples.
+                   failures = list of failing examples.
+
+                   Both successes and failures contain the example name, target and compile chain
+
+    Args:
+    config - the json object imported from the file.
+    toolchains - List of toolchains to compile for.
+    results - results of the compilation stage.
+
+    """
+    results = {}
+    valid_examples = Set(examples)
+    print("\nCompiling example repos....\n")
+    for example in config['examples']:
+        example_names = [basename(x['repo']) for x in get_repo_list(example)]
+        common_examples = valid_examples.intersection(Set(example_names))
+        if not common_examples:
+            continue
+        failures = []
+        successes = []
+        compiled = True
+        pass_status = True
+        if example['compile']:
+            for repo_info in get_repo_list(example):
+                name = basename(repo_info['repo'])
+                os.chdir(name)
+
+                # Check that the target, toolchain and features combinations are valid and return a
+                # list of valid combinations to work through
+                for target, toolchain in target_cross_toolchain(valid_choices(example['targets'], targets),
+                                                                valid_choices(example['toolchains'], toolchains),
+                                                                example['features']):
+                    print("Compiling %s for %s, %s" % (name, target, toolchain))
+                    build_command = ["mbed-cli", "compile", "-t", toolchain, "-m", target, "-v"]
+
+                    if profile:
+                        build_command.append("--profile")
+                        build_command.append(profile)
+
+                    proc = subprocess.Popen(build_command)
+
+                    proc.wait()
+                    example_summary = "{} {} {}".format(name, target, toolchain)
+                    if proc.returncode:
+                        failures.append(example_summary)
+                    else:
+                        successes.append(example_summary)
+                os.chdir("..")
+
+            # If there are any compilation failures for the example 'set' then the overall status is fail.
+            if len(failures) > 0:
+                pass_status = False
+        else:
+            compiled = False
+
+        results[example['name']] = [compiled, pass_status, successes, failures]
+
+    return results
+
+
+def update_mbedos_version(config, tag, examples):
+    """ For each example repo identified in the config json object, update the version of
+        mbed-os to that specified by the supplied GitHub tag. This function assumes that each
+        example repo has already been cloned.
+
+    Args:
+    config - the json object imported from the file.
+    tag - GitHub tag corresponding to a version of mbed-os to upgrade to.
+
+    """
+    print("Updating mbed-os in examples to version %s\n" % tag)
+    for example in config['examples']:
+        if example['name'] not in examples:
+            continue
+        for repo_info in get_repo_list(example):
+            update_dir =  basename(repo_info['repo']) + "/mbed-os"
+            print("\nChanging dir to %s\n" % update_dir)
+            os.chdir(update_dir)
+            subprocess.call(["mbed-cli", "update", tag, "--clean"])
+            os.chdir("../..")
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/pr.tmpl b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/pr.tmpl
new file mode 100755
index 0000000..eb7212a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/pr.tmpl
@@ -0,0 +1,4 @@
+Please test this PR
+
+If successful then merge, otherwise provide a known issue.
+Once you get notification of the release being made public then tag Master with {{ tag }} . 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/update.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/update.py
new file mode 100755
index 0000000..75c215e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/examples/update.py
@@ -0,0 +1,511 @@
+#!/usr/bin/env python
+
+# This script is used to update the version of mbed-os used within a specified set of example
+# applications. The list of examples to be updated lives in the examples.json file and is 
+# shared with the examples.py script. Logging is used to provide varying levels of output
+# during execution.
+#
+# There are two modes that can be used:
+# 1) Update the ARMmbed/master branch of the specified example
+# 
+#    This is done by updating a user fork of the example and then raising a pull request
+#    against ARMmbed/master.
+#
+# 2) Update a different ARMmbed branch of the specified example
+#
+#    A branch to update is specified. If it doesn't already exist then it is first created.
+#    This branch will be updated and the change automatically pushed. The new branch will 
+#    be created from the specified source branch.
+#
+# The modes are controlled via configuration data in the json file.
+# E.g.
+# 
+#   "update-config" : {
+#      "help" : "Update each example repo with a version of mbed-os identified by the tag",
+#      "via-fork" : {
+#        "help" : "-f cmd line option. Update a fork",
+#        "github-user" : "adbridge"          
+#      },
+#      "via-branch" : {
+#        "help" : "-b cmd line option. Update dst branch, created from src branch",
+#        "src-branch" : "mbed-os-5.5.0-rc1-oob",
+#        "dst-branch" : "mbed-os-5.5.0-rc2-oob"    
+#      },
+#      "tag" : "mbed-os-5.5.0-rc2"
+#
+#
+# Command usage:
+#
+# update.py -c <config file> - T <github_token> -l <logging level> -f -b 
+#
+# Where:
+# -c <config file> - Optional path to an examples file.
+#                    If not proved the default is 'examples.json'
+# -T <github_token> - GitHub token for secure access (required)
+# -f                 - Update forked repos. This will use the 'github-user' parameter in
+#                      the 'via-fork' section.
+# -b                 - Update branched repos. This will use the "src-branch" and 
+#                      "dst-branch" parameters in the 'via-branch' section. The destination
+#                      branch is created from the source branch (if it doesn't already exist).
+# 
+# The options -f and -b are mutually exlusive. Only one can be specified.
+#
+#
+
+import os
+from os.path import dirname, abspath, basename, join
+import sys
+import logging
+import argparse
+import json
+import subprocess
+import shutil
+import stat
+import re
+from github import Github, GithubException
+from jinja2 import FileSystemLoader, StrictUndefined
+from jinja2.environment import Environment
+
+ROOT = abspath(dirname(dirname(dirname(dirname(__file__)))))
+sys.path.insert(0, ROOT)
+
+import examples_lib as lib
+from examples_lib import SUPPORTED_TOOLCHAINS
+
+userlog = logging.getLogger("Update")
+
+# Set logging level
+userlog.setLevel(logging.DEBUG)
+
+# Everything is output to the log file
+logfile = os.path.join(os.getcwd(), 'update.log')
+fh = logging.FileHandler(logfile)
+fh.setLevel(logging.DEBUG)
+
+# create console handler with a higher log level
+ch = logging.StreamHandler()
+ch.setLevel(logging.INFO)
+
+formatter = logging.Formatter('%(name)s: %(levelname)s - %(message)s')
+ch.setFormatter(formatter)
+fh.setFormatter(formatter)    
+
+# add the handlers to the logger
+userlog.addHandler(fh)
+userlog.addHandler(ch)
+
+def run_cmd(command, exit_on_failure=False):
+    """ Run a system command returning a status result
+    
+    This is just a wrapper for the run_cmd_with_output() function, but
+    only returns the status of the call.
+    
+    Args:
+    command - system command as a list of tokens
+    exit_on_failure - If True exit the program on failure (default = False)
+    
+    Returns:
+    return_code - True/False indicating the success/failure of the command
+    """
+    return_code, _ = run_cmd_with_output(command, exit_on_failure)       
+    return return_code
+
+def run_cmd_with_output(command, exit_on_failure=False):
+    """ Run a system command returning a status result and any command output
+    
+    Passes a command to the system and returns a True/False result once the 
+    command has been executed, indicating success/failure. If the command was 
+    successful then the output from the command is returned to the caller.
+    Commands are passed as a string. 
+    E.g. The command 'git remote -v' would be passed in as "git remote -v"
+
+    Args:
+    command - system command as a string
+    exit_on_failure - If True exit the program on failure (default = False)
+    
+    Returns:
+    return_code - True/False indicating the success/failure of the command
+    output - The output of the command if it was successful, else empty string
+    """
+    text = '[Exec] ' + command
+    userlog.debug(text)
+    returncode = 0
+    output = ""
+    try:
+        output = subprocess.check_output(command, shell=True)
+    except subprocess.CalledProcessError as e:
+        text = "The command " + str(command) + "failed with return code: " + str(e.returncode)
+        userlog.warning(text)
+        returncode = e.returncode
+        if exit_on_failure:
+            sys.exit(1)
+    return returncode, output
+
+
+def rmtree_readonly(directory):
+    """ Deletes a readonly directory tree.
+        
+    Args:
+    directory - tree to delete
+    """
+    def remove_readonly(func, path, _):
+        os.chmod(path, stat.S_IWRITE)
+        func(path)
+
+    shutil.rmtree(directory, onerror=remove_readonly)
+
+def find_all_examples(path):
+    """ Search the path for examples
+    
+    Description:
+    
+    Searches the path specified for sub-example folders, ie those containing an
+    mbed-os.lib file. If found adds the path to the sub-example to a list which is 
+    then returned.
+        
+    Args:
+    path - path to search.
+    examples - (returned) list of paths to example directories.
+
+    """
+    examples = []
+    for root, dirs, files in os.walk(path):
+        if 'mbed-os.lib' in files:
+            examples += [root]
+    
+    return examples
+
+def upgrade_single_example(example, tag, directory, ref):
+    """ Update the mbed-os version for a single example
+    
+    Description:
+    
+    Updates the mbed-os.lib file in the example specified to correspond to the 
+    version specified by the GitHub tag supplied. Also deals with 
+    multiple sub-examples in the GitHub repo, updating them in the same way.
+        
+    Args:
+    example - json example object containing the GitHub repo to update.
+    tag - GitHub tag corresponding to a version of mbed-os to upgrade to.
+    directory - directory path for the example.
+    ref - SHA corresponding to the supplied tag
+    returns - True if the upgrade was successful, False otherwise.
+    
+    """
+    cwd = os.getcwd()
+    os.chdir(directory)
+    
+    return_code = False
+    
+    if os.path.isfile("mbed-os.lib"):
+        # Rename command will fail on some OS's if the target file already exist,
+        # so ensure if it does, it is deleted first.
+        if os.path.isfile("mbed-os.lib_bak"):
+            os.remove("mbed-os.lib_bak")
+        
+        os.rename("mbed-os.lib", "mbed-os.lib_bak")
+    else:
+        userlog.error("Failed to backup mbed-os.lib prior to updating.")
+        return False
+    
+    # mbed-os.lib file contains one line with the following format
+    # e.g. https://github.com/ARMmbed/mbed-os/#0789928ee7f2db08a419fa4a032fffd9bd477aa7
+    lib_re = re.compile('https://github.com/ARMmbed/mbed-os/#[A-Za-z0-9]+')
+    updated = False
+
+    # Scan through mbed-os.lib line by line
+    with open('mbed-os.lib_bak', 'r') as ip, open('mbed-os.lib', 'w') as op:
+        for line in ip:
+
+            opline = line
+            
+            regexp = lib_re.match(line)
+            if regexp:
+                opline = 'https://github.com/ARMmbed/mbed-os/#' + ref
+                updated = True
+    
+            op.write(opline)
+
+    if updated:
+        # Setup and run the git add command
+        cmd = "git add mbed-os.lib"
+        return_code = run_cmd(cmd)
+
+    os.chdir(cwd)
+    return not return_code
+
+def prepare_fork(arm_example):
+    """ Synchronises a cloned fork to ensure it is up to date with the original. 
+
+    Description:
+    
+    This function sets a fork of an ARMmbed repo to be up to date with the 
+    repo it was forked from. It does this by hard resetting to the ARMmbed
+    master branch.    
+        
+    Args:
+    arm_example - Full GitHub repo path for original example 
+    
+    """
+
+    logstr = "In: " + os.getcwd()
+    userlog.debug(logstr)
+
+    for cmd in ["git remote add armmbed " + str(arm_example),
+                "git fetch armmbed",
+                "git reset --hard armmbed/master",
+                "git push -f origin"]:
+        run_cmd(cmd, exit_on_failure=True)
+
+def prepare_branch(src, dst):
+    """ Set up at branch ready for use in updating examples 
+        
+    Description:
+    
+    This function checks whether or not the supplied dst branch exists.
+    If it does not, the branch is created from the src and pushed to the origin.
+    The branch is then switched to.
+    
+    Args:
+    src - branch to create the dst branch from
+    dst - branch to update
+    
+    """
+
+    userlog.debug("Preparing branch: %s", dst)
+
+    # Check if branch already exists or not.
+    # We can use the 'git branch -r' command. This returns all the remote branches for
+    # the current repo.
+    # The output consists of a list of lines of the form:
+    # origin/<branch>
+    # From these we need to extract just the branch names to a list and then check if 
+    # the specified dst exists in that list
+    branches = []
+    cmd = "git branch -r"
+    _, output = run_cmd_with_output(cmd, exit_on_failure=True)
+
+    branches = [line.split('/')[1] for line in output.split('\n') if 'origin' in line and not '->' in line]
+  
+    if not dst in branches:
+        
+        # OOB branch does not exist thus create it, first ensuring we are on 
+        # the src branch and then check it out
+
+        for cmd in ["git checkout " + str(src),
+                    "git checkout -b " + str(dst),
+                    "git push -u origin " + str(dst)]:
+
+            run_cmd(cmd, exit_on_failure=True)
+
+    else: 
+        cmd = "git checkout " + str(dst)
+        run_cmd(cmd, exit_on_failure=True)
+   
+def upgrade_example(github, example, tag, ref, user, src, dst, template):
+    """ Upgrade all versions of mbed-os.lib found in the specified example repo
+    
+    Description:
+    
+    Clone a version of the example specified and upgrade all versions of 
+    mbed-os.lib found within its tree.  The version cloned and how it 
+    is upgraded depends on the user, src and dst settings.
+    1) user == None 
+       The destination branch will be updated with the version of mbed-os 
+       idenfied by the tag. If the destination branch does not exist then it
+       will be created from the source branch.
+
+    2) user != None 
+       The master branch of a fork of the example will be updated with the 
+       version of mbed-os identified by the tag.
+            
+    Args:
+    github - GitHub instance to allow internal git commands to be run
+    example - json example object containing the GitHub repo to update.
+    tag - GitHub tag corresponding to a version of mbed-os to upgrade to.
+    ref - SHA corresponding to the tag
+    user - GitHub user name 
+    src - branch to create the dst branch from
+    dst - branch to update
+    
+    returns True if the upgrade was successful, False otherwise
+    """
+    
+    # If a user has not been specified then branch update will be used and thus
+    # the git user will be ARMmbed.        
+    if not user:
+        user = 'ARMmbed'
+                
+    ret = False
+    userlog.info("Updating example '%s'", example['name'])
+    userlog.debug("User: %s", user)
+    userlog.debug("Src branch: %s", (src or "None"))
+    userlog.debug("Dst branch: %s", (dst or "None"))
+
+    cwd = os.getcwd()
+
+    update_repo = "https://github.com/" + user + '/' + example['name'] 
+    userlog.debug("Update repository: %s", update_repo)
+
+    # Clone the example repo
+    clone_cmd = "git clone " +  str(update_repo)
+    return_code = run_cmd(clone_cmd)
+    
+    if not return_code:
+    
+        # Find all examples
+        example_directories = find_all_examples(example['name'])
+        
+        os.chdir(example['name'])
+        
+        # If the user is ARMmbed then a branch is used.
+        if user == 'ARMmbed':
+            prepare_branch(src, dst)    
+        else:          
+            prepare_fork(example['github'])
+            
+        for example_directory in example_directories:
+            if not upgrade_single_example(example, tag, os.path.relpath(example_directory, example['name']), ref):
+                os.chdir(cwd)
+                return False
+
+        # Setup and run the commit command
+        commit_cmd = "git commit -m \"Updating mbed-os to " + tag + "\""
+        return_code = run_cmd(commit_cmd)
+        if not return_code:
+
+            # Setup and run the push command
+            push_cmd = "git push origin"
+            return_code = run_cmd(push_cmd)
+            
+            if not return_code:
+                # If the user is not ARMmbed then a fork is being used
+                if user != 'ARMmbed': 
+                    
+                    upstream_repo = 'ARMmbed/'+ example['name']
+                    userlog.debug("Upstream repository: %s", upstream_repo)
+                    # Check access to mbed-os repo
+                    try:
+                        repo = github.get_repo(upstream_repo, False)
+
+                    except:
+                        userlog.error("Upstream repo: %s, does not exist - skipping", upstream_repo)
+                        return False
+           
+                    jinja_loader = FileSystemLoader(template)
+                    jinja_environment = Environment(loader=jinja_loader,
+                                                    undefined=StrictUndefined)
+                    pr_body = jinja_environment.get_template("pr.tmpl").render(tag=tag)
+
+                    # Raise a PR from release-candidate to master
+                    user_fork = user + ':master' 
+                    try:
+                        pr = repo.create_pull(title='Updating mbed-os to ' + tag, head=user_fork, base='master', body=pr_body)
+                        ret = True
+                    except GithubException as e:
+                        # Default to False
+                         userlog.error("Pull request creation failed with error: %s", e)
+                else:
+                    ret = True                    
+            else:
+                userlog.error("Git push command failed.")
+        else:
+            userlog.error("Git commit command failed.")
+    else:
+        userlog.error("Git clone %s failed", update_repo)
+
+    os.chdir(cwd)
+    return ret
+
+def create_work_directory(path):
+    """ Create a new directory specified in 'path', overwrite if the directory already 
+        exists.
+        
+    Args:
+    path - directory path to be created. 
+    
+    """
+    if os.path.exists(path):
+        userlog.info("'%s' directory already exists. Deleting...", path)
+        rmtree_readonly(path)
+    
+    os.makedirs(path)
+
+if __name__ == '__main__':
+
+    parser = argparse.ArgumentParser(description=__doc__,
+                                     formatter_class=argparse.RawDescriptionHelpFormatter)
+    parser.add_argument('-c', '--config_file', help="Path to the configuration file (default is 'examples.json')", default='examples.json')
+    parser.add_argument('-T', '--github_token', help="GitHub token for secure access")
+    
+    exclusive = parser.add_mutually_exclusive_group(required=True)
+    exclusive.add_argument('-f', '--fork', help="Update a fork", action='store_true')
+    exclusive.add_argument('-b', '--branch', help="Update a branch", action='store_true')
+    
+    args = parser.parse_args()
+
+    # Load the config file
+    with open(os.path.join(os.path.dirname(__file__), args.config_file)) as config:
+        if not config:
+            userlog.error("Failed to load config file '%s'", args.config_file)
+            sys.exit(1)
+        json_data = json.load(config)
+        
+    # Create working directory
+    create_work_directory('examples')
+
+    github = Github(args.github_token)
+    config = json_data['update-config']
+    tag = config['tag']
+
+    user = None
+    src = "master"
+    dst = None
+
+    if args.fork:
+        user = config['via-fork']['github-user']
+    elif args.branch:
+        src = config['via-branch']['src-branch']
+        dst = config['via-branch']['dst-branch']
+    else:
+        userlog.error("Must specify either -f or -b command line option")
+        exit(1)    
+
+    # Get the github sha corresponding to the specified mbed-os tag
+    cmd = "git rev-list -1 " + tag
+    return_code, ref = run_cmd_with_output(cmd) 
+
+    if return_code:
+        userlog.error("Could not obtain SHA for tag: %s",  tag)
+        sys.exit(1)
+
+    # Loop through the examples
+    failures = []
+    successes = []
+    results = {}
+    template = dirname(abspath(__file__))
+
+    os.chdir('examples')
+
+    for example in json_data['examples']:
+        # Determine if this example should be updated and if so update any found 
+        # mbed-os.lib files. 
+        
+        result = upgrade_example(github, example, tag, ref, user, src, dst, template)
+            
+        if result:
+            successes += [example['name']]
+        else:
+            failures += [example['name']]
+    
+    os.chdir('../')
+    
+    # Finish the script and report the results
+    userlog.info("Finished updating examples")
+    if successes:
+        for success in successes:
+            userlog.info(" SUCCEEDED: %s", success)
+    
+    if failures:
+        for fail in failures:
+            userlog.info(" FAILED: %s", fail)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/arm.map b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/arm.map
new file mode 100755
index 0000000..0ecc1a5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/arm.map
@@ -0,0 +1,47 @@
+Component: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]
+
+==============================================================================
+
+Memory Map of the image
+
+  Image Entry point : 0x0001b0c1
+
+  Load Region LR_IROM1 (Base: 0x0001b000, Size: 0x0000ed04, Max: 0x00025000, ABSOLUTE, COMPRESSED[0x0000e23c])
+
+    Execution Region ER_IROM1 (Base: 0x0001b000, Size: 0x0000e1c4, Max: 0x00025000, ABSOLUTE)
+
+    Base Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x0001b000   0x000000c0   Data   RO         7002    RESET               /common/path/startup/startup.o
+    0x0001b0c0   0x00000008   Code   RO         8820  * !!!main             /installed/libs/../lib/armlib/c_p.l(__main.o)
+    0x0001b26c   0x00000098   Code   RO         6076    .text               /common/path/irqs/irqs.o
+    0x000206a0   0x00000036   Code   RO           27    i._Z9time_funcPN4mbed5TimerEi  /common/path/main.o
+    0x200039b4   0x00000018   Data   RW         8092    .data               /common/path/data/data.o
+    0x20003af8   0x00000198   Zero   RW           57    .bss                /common/path/data/data.o
+
+==============================================================================
+
+Image component sizes
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+       344        368          0         24        408      36188   Object Totals
+         8          0          0          0          0       7596   Library Totals
+
+==============================================================================
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+       352        376          0         24        408      17208   Grand Totals
+       352        376          0         24        408      17208   ELF Image Totals (compressed)
+       352        376          0         24          0          0   ROM Totals
+
+==============================================================================
+
+    Total RO  Size (Code + RO Data)                  352 (   0.35kB)
+    Total RW  Size (RW Data + ZI Data)               432 (   0.43kB)
+    Total ROM Size (Code + RO Data + RW Data)        376 (   0.37kB)
+
+==============================================================================
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/gcc.map b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/gcc.map
new file mode 100755
index 0000000..58ff289
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/gcc.map
@@ -0,0 +1,25 @@
+Archive member included to satisfy reference by file (symbol)
+
+Linker script and memory map
+.text           0x000000000001b000    0x11a30
+ .Vectors       0x000000000001b000       0x98 /common/path/irqs/irqs.o
+                0x000000000001b168       0x36 /common/path/main.o
+                0x000000000001b168                count5(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)
+                0x000000000001b200       0xc0 /common/path/startup/startup.o
+                0x000000000001b200                startup()
+                0x0000000000024020        0x8 /usr/lib/gcc/arm-none-eabi/7.1.0/../../../../arm-none-eabi/lib/armv6-m/libd16M_tlf.a(__main.o)
+
+.data           0x0000000020002ef8      0xac8 load address 0x000000000002ca38
+                0x0000000020002ef8                __data_start__ = .
+ *(vtable)
+ *(.data*)
+                0x0000000020002ef8       0x18 /common/path/data/data.o
+                0x0000000020002ef8                some_global_var
+
+.bss            0x0000000020003a80     0x2050 load address 0x000000000002d5c0
+                0x0000000020003a80                . = ALIGN (0x4)
+                0x0000000020003a80                __bss_start__ = .
+ *(.bss*)
+ .bss.completed.8574
+ .bss.counter   0x0000000020003c08      0x198 /common/path/data.o
+                0x0000000020003c08                some_zero_init_var
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/iar.map b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/iar.map
new file mode 100755
index 0000000..0fc3aae
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/iar.map
@@ -0,0 +1,86 @@
+###############################################################################
+#
+# IAR ELF Linker V7.80.1.28/LNX for ARM                   18/Sep/2017  14:26:09
+# Copyright 2007-2016 IAR Systems AB.
+#
+#    Output file  =  
+#        /common/path/project.elf
+#    Map file     =  
+#        /common/path/project.map
+#    Command line =  
+#        -f
+#        /common/path/.link_files.txt
+#        (-o
+#        --map=/common/path/project.map
+#        /common/path/project.elf
+#        /common/path/main.o
+#        /common/path/startup/startup.o
+#        /common/path/irqs/irqs.o
+#        /common/path/data/data.o
+#
+###############################################################################
+
+*******************************************************************************
+*** RUNTIME MODEL ATTRIBUTES
+***
+
+CppFlavor                     = *
+__CPP_Exceptions              = Disabled
+__CPP_Language                = C++
+__Heap_Handler                = DLMalloc
+__SystemLibrary               = DLib
+__dlib_dynamic_initialization = postponed
+__dlib_has_iterator_debugging = 0
+__dlib_jmp_buf_num_elements   = 8
+
+
+*******************************************************************************
+*** PLACEMENT SUMMARY
+***
+
+"A0":  place at 0x0001b000 { ro section .intvec };
+"P1":  place in [from 0x0001b0c0 to 0x0003ffff] { ro };
+"P2":  place in [from 0x20002ef8 to 0x20007fff] { rw, block HEAP, block CSTACK };
+do not initialize { section .noinit };
+initialize by copy { rw };
+ { section .intvec };
+
+  Section               Kind        Address    Size  Object
+  -------               ----        -------    ----  ------
+"A0":                                          0xc0
+  .intvec               ro code  0x0001b000    0xc0  startup.o [4]
+                               - 0x0001b0c0    0xc0
+
+"P1":                                         0x
+  .text                 ro code  0x0001c753    0x36  main.o [3]
+  .text                 ro code  0x0001cfff    0x98  irqs.o [5]
+  .text                 ro code  0x0001c778     0x8  __main.o [67]
+
+"P2", part 1 of 2:                             0x18
+  P2-1                           0x20002ef8    0x18  <Init block>
+    .data               inited   0x20002fa8    0x18  data.o [6]
+
+"P2", part 2 of 2:                            0x198
+  P2-2                           0x20005388   0x198  <Init block>
+    .bss                  zero   0x20002fa8   0x198  data.o [6]
+
+*******************************************************************************
+*** INIT TABLE
+***
+
+*******************************************************************************
+*** MODULE SUMMARY
+***
+
+d16M_tlf.a: [67]
+    __main.o                          8
+    ------------------------------------------------
+    Total:                            8
+
+    Linker created                             
+---------------------------------------------------
+    Grand Total:                      
+
+*******************************************************************************
+*** ENTRY LIST
+***
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/memap_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/memap_test.py
new file mode 100755
index 0000000..a0c84dd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/memap_test.py
@@ -0,0 +1,210 @@
+"""
+mbed SDK
+Copyright (c) 2017 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import sys
+from os.path import isfile, join
+import json
+
+import pytest
+
+from tools.memap import MemapParser
+from copy import deepcopy
+
+"""
+Tests for test_api.py
+"""
+
+@pytest.fixture
+def memap_parser():
+    """
+    Called before each test case
+
+    :return:
+    """
+    memap_parser = MemapParser()
+
+    memap_parser.modules = {
+        "mbed-os/targets/TARGET/TARGET_MCUS/api/pinmap.o": {
+            ".text": 1,
+            ".data": 2,
+            ".bss": 3,
+            ".heap": 0,
+            ".stack": 0,
+            ".interrupts_ram":0,
+            ".init":0,
+            ".ARM.extab":0,
+            ".ARM.exidx":0,
+            ".ARM.attributes":0,
+            ".eh_frame":0,
+            ".init_array":0,
+            ".fini_array":0,
+            ".jcr":0,
+            ".stab":0,
+            ".stabstr":0,
+            ".ARM.exidx":0,
+            ".ARM":0,
+            ".interrupts":0,
+            ".flash_config":0,
+            "unknown":0,
+            "OUTPUT":0,
+        },
+        "[lib]/libc.a/lib_a-printf.o": {
+            ".text": 4,
+            ".data": 5,
+            ".bss": 6,
+            ".heap": 0,
+            ".stack": 0,
+            ".interrupts_ram":0,
+            ".init":0,
+            ".ARM.extab":0,
+            ".ARM.exidx":0,
+            ".ARM.attributes":0,
+            ".eh_frame":0,
+            ".init_array":0,
+            ".fini_array":0,
+            ".jcr":0,
+            ".stab":0,
+            ".stabstr":0,
+            ".ARM.exidx":0,
+            ".ARM":0,
+            ".interrupts":0,
+            ".flash_config":0,
+            "unknown":0,
+            "OUTPUT":0,
+        },
+        "main.o": {
+            ".text": 7,
+            ".data": 8,
+            ".bss": 0,
+            ".heap": 0,
+            ".stack": 0,
+            ".interrupts_ram":0,
+            ".init":0,
+            ".ARM.extab":0,
+            ".ARM.exidx":0,
+            ".ARM.attributes":0,
+            ".eh_frame":0,
+            ".init_array":0,
+            ".fini_array":0,
+            ".jcr":0,
+            ".stab":0,
+            ".stabstr":0,
+            ".ARM.exidx":0,
+            ".ARM":0,
+            ".interrupts":0,
+            ".flash_config":0,
+            "unknown":0,
+            "OUTPUT":0,
+        },
+        "test.o": {
+            ".text": 0,
+            ".data": 0,
+            ".bss": 0,
+            ".heap": 0,
+            ".stack": 0,
+            ".interrupts_ram":0,
+            ".init":0,
+            ".ARM.extab":0,
+            ".ARM.exidx":0,
+            ".ARM.attributes":0,
+            ".eh_frame":0,
+            ".init_array":0,
+            ".fini_array":0,
+            ".jcr":0,
+            ".stab":0,
+            ".stabstr":0,
+            ".ARM.exidx":0,
+            ".ARM":0,
+            ".interrupts":0,
+            ".flash_config":0,
+            "unknown":0,
+            "OUTPUT":0,
+        },
+    }
+    return memap_parser
+
+
+def generate_test_helper(memap_parser, format, depth, file_output=None):
+    """
+    Helper that tests that the member variables "modules" is
+    unchanged after calling "generate_output"
+
+    :param memap_parser: the parser object
+    :param depth: how much detail to put in the report
+    :param format:  the file type to output
+    :param file_output: the file to output to
+    """
+
+    old_modules = deepcopy(memap_parser.modules)
+
+    memap_parser.generate_output(format, depth, file_output=file_output)
+
+    assert memap_parser.modules == old_modules,\
+        "generate_output modified the 'modules' property"
+
+
+@pytest.mark.parametrize("depth", [1, 2, 20])
+def test_report_computed(memap_parser, depth):
+    """
+    Test that a report and summary are computed
+
+    :param memap_parser: Mocked parser
+    :param depth: the detail of the output
+    """
+
+    memap_parser.generate_output('table', depth)
+
+    # Report is created after generating output
+    assert memap_parser.mem_summary
+    assert memap_parser.mem_report
+
+
+@pytest.mark.parametrize("depth", [1, 2, 20])
+def test_generate_output_table(memap_parser, depth):
+    """
+    Test that an output of type "table" can be generated correctly
+    :param memap_parser: Mocked parser
+    :param depth: the detail of the output
+    """
+    generate_test_helper(memap_parser, 'table', depth)
+
+
+@pytest.mark.parametrize("depth", [1, 2, 20])
+def test_generate_output_json(memap_parser, tmpdir, depth):
+    """
+    Test that an output of type "json" can be generated correctly
+    :param memap_parser: Mocked parser
+    :param tmpdir: a unique location to place an output file
+    :param depth: the detail of the output
+    """
+    file_name = str(tmpdir.join('output.json').realpath())
+    generate_test_helper(memap_parser, 'json', depth, file_name)
+    assert isfile(file_name), "Failed to create json file"
+    json.load(open(file_name))
+
+
+@pytest.mark.parametrize("depth", [1, 2, 20])
+def test_generate_output_csv_ci(memap_parser, tmpdir, depth):
+    """
+    Test ensures that an output of type "csv-ci" can be generated correctly
+
+    :param memap_parser: Mocked parser
+    :param tmpdir: a unique location to place an output file
+    :param depth: the detail of the output
+    """
+    file_name = str(tmpdir.join('output.csv').realpath())
+    generate_test_helper(memap_parser, 'csv-ci', depth, file_name)
+    assert isfile(file_name), "Failed to create csv-ci file"
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/parse_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/parse_test.py
new file mode 100755
index 0000000..51eb9ca
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/memap/parse_test.py
@@ -0,0 +1,61 @@
+import sys
+from io import open
+from os.path import isfile, join, dirname
+import json
+
+import pytest
+
+from tools.memap import MemapParser
+from copy import deepcopy
+
+
+PARSED_ARM_DATA = {
+    "startup/startup.o": {".text": 0xc0},
+    "[lib]/c_p.l/__main.o": {".text": 8},
+    "irqs/irqs.o": {".text": 0x98},
+    "data/data.o": {".data": 0x18, ".bss": 0x198},
+    "main.o": {".text": 0x36},
+}
+
+def test_parse_armcc():
+    memap = MemapParser()
+    memap.parse_map_file_armcc(open(join(dirname(__file__), "arm.map")))
+    assert memap.modules == PARSED_ARM_DATA
+
+PARSED_IAR_GCC_DATA = {
+    "startup/startup.o": {".text": 0xc0},
+    "[lib]/d16M_tlf.a/__main.o": {".text": 8},
+    "irqs/irqs.o": {".text": 0x98},
+    "data/data.o": {".data": 0x18, ".bss": 0x198},
+    "main.o": {".text": 0x36},
+}
+
+def test_parse_iar():
+    memap = MemapParser()
+    memap.parse_map_file_iar(open(join(dirname(__file__), "iar.map")))
+    assert memap.modules == PARSED_IAR_GCC_DATA
+
+def test_parse_gcc():
+    memap = MemapParser()
+    memap.parse_map_file_gcc(open(join(dirname(__file__), "gcc.map")))
+    assert memap.modules == PARSED_IAR_GCC_DATA
+
+
+def test_add_empty_module():
+    memap = MemapParser()
+    old_modules = deepcopy(memap.modules)
+    memap.module_add("", 8, ".data")
+    assert(old_modules == memap.modules)
+    memap.module_add("main.o", 0, ".text")
+    assert(old_modules == memap.modules)
+    memap.module_add("main.o", 8, "")
+    assert(old_modules == memap.modules)
+
+def test_add_full_module():
+    memap = MemapParser()
+    old_modules = deepcopy(memap.modules)
+    memap.module_add("main.o", 8, ".data")
+    assert(old_modules != memap.modules)
+    assert("main.o" in memap.modules)
+    assert(".data" in memap.modules["main.o"])
+    assert(memap.modules["main.o"][".data"] == 8)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/pylint.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/pylint.py
new file mode 100755
index 0000000..cae95ca
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/pylint.py
@@ -0,0 +1,48 @@
+"""A test that all code scores above a 9.25 in pylint"""
+
+import subprocess
+import re
+import os.path
+
+SCORE_REGEXP = re.compile(
+    r'^Your\ code\ has\ been\ rated\ at\ (\-?[0-9\.]+)/10')
+
+TOOLS_ROOT = os.path.dirname(os.path.dirname(__file__))
+
+
+def parse_score(pylint_output):
+    """Parse the score out of pylint's output as a float If the score is not
+    found, return 0.0.
+    """
+    for line in pylint_output.splitlines():
+        match = re.match(SCORE_REGEXP, line)
+        if match:
+            return float(match.group(1))
+    return 0.0
+
+def execute_pylint(filename):
+    """Execute a pylint process and collect it's output
+    """
+    process = subprocess.Popen(
+        ["pylint", filename],
+        stdout=subprocess.PIPE,
+        stderr=subprocess.PIPE
+    )
+    stout, sterr = process.communicate()
+    status = process.poll()
+    return status, stout, sterr
+
+FILES = ["build_api.py", "config.py", "colorize.py", "detect_targets.py",
+         "hooks.py", "libraries.py", "memap.py", "options.py", "paths.py",
+         "targets.py", "test/pylint.py"]
+
+if __name__ == "__main__":
+    for python_module in FILES:
+        _, stdout, stderr = execute_pylint(os.path.join(TOOLS_ROOT,
+                                                        python_module))
+        score = parse_score(stdout)
+        if score < 9.25:
+            print(stdout)
+
+
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/targets/target_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/targets/target_test.py
new file mode 100755
index 0000000..eff7b3f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/targets/target_test.py
@@ -0,0 +1,133 @@
+#!/usr/bin/env python
+"""
+ mbed
+ Copyright (c) 2017-2017 ARM Limited
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+     http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+"""
+import os
+import sys
+import shutil
+import tempfile
+from os.path import join, abspath, dirname
+from contextlib import contextmanager
+import pytest
+
+from tools.targets import TARGETS, TARGET_MAP, Target, update_target_data
+from tools.arm_pack_manager import Cache
+
+
+def test_device_name():
+    """Assert device name is in a pack"""
+    cache = Cache(True, True)
+    named_targets = (target for target in TARGETS if
+                     hasattr(target, "device_name"))
+    for target in named_targets:
+        assert target.device_name in cache.index,\
+            ("Target %s contains invalid device_name %s" %
+             (target.name, target.device_name))
+
+@contextmanager
+def temp_target_file(extra_target, json_filename='custom_targets.json'):
+    """Create an extra targets temp file in a context manager
+
+    :param extra_target: the contents of the extra targets temp file
+    """
+    tempdir = tempfile.mkdtemp()
+    try:
+        targetfile = os.path.join(tempdir, json_filename)
+        with open(targetfile, 'w') as f:
+            f.write(extra_target)
+        yield tempdir
+    finally:
+        # Reset extra targets
+        Target.set_targets_json_location()
+        # Delete temp files
+        shutil.rmtree(tempdir)
+
+def test_add_extra_targets():
+    """Search for extra targets json in a source folder"""
+    test_target_json = """
+    { 
+        "Test_Target": {
+            "inherits": ["Target"]
+        }
+    }
+    """
+    with temp_target_file(test_target_json) as source_dir:
+        Target.add_extra_targets(source_dir=source_dir)
+        update_target_data()
+
+        assert 'Test_Target' in TARGET_MAP
+        assert TARGET_MAP['Test_Target'].core is None, \
+            "attributes should be inherited from Target"
+
+def test_modify_existing_target():
+    """Set default targets file, then override base Target definition"""
+    initial_target_json = """
+    {
+        "Target": {
+            "core": null,
+            "default_toolchain": "ARM",
+            "supported_toolchains": null,
+            "extra_labels": [],
+            "is_disk_virtual": false,
+            "macros": [],
+            "device_has": [],
+            "features": [],
+            "detect_code": [],
+            "public": false,
+            "default_lib": "std",
+            "bootloader_supported": false
+        },
+        "Test_Target": {
+            "inherits": ["Target"],
+            "core": "Cortex-M4",
+            "supported_toolchains": ["ARM"]
+        }
+    }"""
+
+    test_target_json = """
+    { 
+        "Target": {
+            "core": "Cortex-M0",
+            "default_toolchain": "GCC_ARM",
+            "supported_toolchains": null,
+            "extra_labels": [],
+            "is_disk_virtual": false,
+            "macros": [],
+            "device_has": [],
+            "features": [],
+            "detect_code": [],
+            "public": false,
+            "default_lib": "std",
+            "bootloader_supported": true
+        }
+    }
+    """
+
+    with temp_target_file(initial_target_json, json_filename="targets.json") as targets_dir:
+        Target.set_targets_json_location(os.path.join(targets_dir, "targets.json"))
+        update_target_data()
+        assert TARGET_MAP["Test_Target"].core == "Cortex-M4"
+        assert TARGET_MAP["Test_Target"].default_toolchain == 'ARM'
+        assert TARGET_MAP["Test_Target"].bootloader_supported == False
+
+        with temp_target_file(test_target_json) as source_dir:
+            Target.add_extra_targets(source_dir=source_dir)
+            update_target_data()
+
+            assert TARGET_MAP["Test_Target"].core == "Cortex-M4"
+            # The existing target should not be modified by custom targets
+            assert TARGET_MAP["Test_Target"].default_toolchain != 'GCC_ARM'
+            assert TARGET_MAP["Test_Target"].bootloader_supported != True
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/test_api/test_api_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/test_api/test_api_test.py
new file mode 100755
index 0000000..ef3a977
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/test_api/test_api_test.py
@@ -0,0 +1,93 @@
+"""
+mbed SDK
+Copyright (c) 2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import pytest
+from mock import patch
+from tools.targets import set_targets_json_location
+from tools.test_api import find_tests, build_tests
+
+"""
+Tests for test_api.py
+"""
+
+def setUp(self):
+    """
+    Called before each test case
+
+    :return:
+    """
+    self.base_dir = 'base_dir'
+    self.target = "K64F"
+    self.toolchain_name = "ARM"
+
+@pytest.mark.parametrize("base_dir", ["base_dir"])
+@pytest.mark.parametrize("target", ["K64F"])
+@pytest.mark.parametrize("toolchain_name", ["ARM"])
+@pytest.mark.parametrize("app_config", ["app_config", None])
+def test_find_tests_app_config(base_dir, target, toolchain_name, app_config):
+    """
+    Test find_tests for correct use of app_config
+
+    :param base_dir: dummy value for the test base directory
+    :param target: the target to "test" for
+    :param toolchain_name: the toolchain to use for "testing"
+    :param app_config: Application configuration parameter to find tests
+    """
+    set_targets_json_location()
+    with patch('tools.test_api.scan_resources') as mock_scan_resources,\
+         patch('tools.test_api.prepare_toolchain') as mock_prepare_toolchain:
+        mock_scan_resources().inc_dirs.return_value = []
+
+        find_tests(base_dir, target, toolchain_name, app_config=app_config)
+
+        args = mock_prepare_toolchain.call_args
+        assert 'app_config' in args[1],\
+            "prepare_toolchain was not called with app_config"
+        assert args[1]['app_config'] == app_config,\
+            "prepare_toolchain was called with an incorrect app_config"
+
+
+@pytest.mark.parametrize("build_path", ["build_path"])
+@pytest.mark.parametrize("target", ["K64F"])
+@pytest.mark.parametrize("toolchain_name", ["ARM"])
+@pytest.mark.parametrize("app_config", ["app_config", None])
+def test_find_tests_app_config(build_path, target, toolchain_name, app_config):
+    """
+    Test find_tests for correct use of app_config
+
+    :param base_dir: dummy value for the test base directory
+    :param target: the target to "test" for
+    :param toolchain_name: the toolchain to use for "testing"
+    :param app_config: Application configuration parameter to find tests
+    """
+    tests = {'test1': 'test1_path','test2': 'test2_path'}
+    src_paths = ['.']
+    set_targets_json_location()
+    with patch('tools.test_api.scan_resources') as mock_scan_resources,\
+         patch('tools.test_api.build_project') as mock_build_project:
+        mock_build_project.return_value = "build_project"
+        mock_scan_resources().inc_dirs.return_value = []
+
+        build_tests(tests, src_paths, build_path, target, toolchain_name,
+                    app_config=app_config)
+
+        arg_list = mock_build_project.call_args_list
+        for args in arg_list:
+            assert 'app_config' in args[1],\
+                "build_tests was not called with app_config"
+            assert args[1]['app_config'] == app_config,\
+                "build_tests was called with an incorrect app_config"
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/toolchains/api_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/toolchains/api_test.py
new file mode 100755
index 0000000..d98b1ce
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/toolchains/api_test.py
@@ -0,0 +1,196 @@
+"""Tests for the toolchain sub-system"""
+import sys
+import os
+from string import printable
+from copy import deepcopy
+from mock import MagicMock, patch
+from hypothesis import given, settings
+from hypothesis.strategies import text, lists, fixed_dictionaries, booleans
+
+ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..",
+                                    ".."))
+sys.path.insert(0, ROOT)
+
+from tools.toolchains import TOOLCHAIN_CLASSES, LEGACY_TOOLCHAIN_NAMES,\
+    Resources, TOOLCHAIN_PATHS, mbedToolchain
+from tools.targets import TARGET_MAP
+
+def test_instantiation():
+    """Test that all exported toolchain may be instantiated"""
+    for name, tc_class in  TOOLCHAIN_CLASSES.items():
+        cls = tc_class(TARGET_MAP["K64F"])
+        assert name == cls.name or\
+            name == LEGACY_TOOLCHAIN_NAMES[cls.name]
+
+ALPHABET = [char for char in printable if char not in [u'.', u'/']]
+
+@given(fixed_dictionaries({
+    'common': lists(text()),
+    'c': lists(text()),
+    'cxx': lists(text()),
+    'asm': lists(text()),
+    'ld': lists(text())}),
+       lists(text(min_size=1, alphabet=ALPHABET), min_size=1))
+def test_toolchain_profile_c(profile, source_file):
+    """Test that the appropriate profile parameters are passed to the
+    C compiler"""
+    filename = deepcopy(source_file)
+    filename[-1] += ".c"
+    to_compile = os.path.join(*filename)
+    with patch('os.mkdir') as _mkdir:
+        for _, tc_class in TOOLCHAIN_CLASSES.items():
+            toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile)
+            toolchain.inc_md5 = ""
+            toolchain.build_dir = ""
+            toolchain.config = MagicMock(app_config_location=None)
+            for parameter in profile['c'] + profile['common']:
+                assert any(parameter in cmd for cmd in toolchain.cc), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                            parameter)
+            compile_command = toolchain.compile_command(to_compile,
+                                                        to_compile + ".o", [])
+            for parameter in profile['c'] + profile['common']:
+                assert any(parameter in cmd for cmd in compile_command), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                            parameter)
+
+@given(fixed_dictionaries({
+    'common': lists(text()),
+    'c': lists(text()),
+    'cxx': lists(text()),
+    'asm': lists(text()),
+    'ld': lists(text())}),
+       lists(text(min_size=1, alphabet=ALPHABET), min_size=1))
+def test_toolchain_profile_cpp(profile, source_file):
+    """Test that the appropriate profile parameters are passed to the
+    C++ compiler"""
+    filename = deepcopy(source_file)
+    filename[-1] += ".cpp"
+    to_compile = os.path.join(*filename)
+    with patch('os.mkdir') as _mkdir:
+        for _, tc_class in TOOLCHAIN_CLASSES.items():
+            toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile)
+            toolchain.inc_md5 = ""
+            toolchain.build_dir = ""
+            toolchain.config = MagicMock(app_config_location=None)
+            for parameter in profile['cxx'] + profile['common']:
+                assert any(parameter in cmd for cmd in toolchain.cppc), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                            parameter)
+            compile_command = toolchain.compile_command(to_compile,
+                                                        to_compile + ".o", [])
+            for parameter in profile['cxx'] + profile['common']:
+                assert any(parameter in cmd for cmd in compile_command), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                            parameter)
+
+@given(fixed_dictionaries({
+    'common': lists(text()),
+    'c': lists(text()),
+    'cxx': lists(text()),
+    'asm': lists(text()),
+    'ld': lists(text())}),
+       lists(text(min_size=1, alphabet=ALPHABET), min_size=1))
+def test_toolchain_profile_asm(profile, source_file):
+    """Test that the appropriate profile parameters are passed to the
+    Assembler"""
+    filename = deepcopy(source_file)
+    filename[-1] += ".s"
+    to_compile = os.path.join(*filename)
+    with patch('os.mkdir') as _mkdir:
+        for _, tc_class in TOOLCHAIN_CLASSES.items():
+            toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile)
+            toolchain.inc_md5 = ""
+            toolchain.build_dir = ""
+            for parameter in profile['asm']:
+                assert any(parameter in cmd for cmd in toolchain.asm), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
+            compile_command = toolchain.compile_command(to_compile,
+                                                        to_compile + ".o", [])
+            if not compile_command:
+                assert compile_command, to_compile
+            for parameter in profile['asm']:
+                assert any(parameter in cmd for cmd in compile_command), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
+
+    for name, Class in  TOOLCHAIN_CLASSES.items():
+        CLS = Class(TARGET_MAP["K64F"])
+        assert name == CLS.name or name ==  LEGACY_TOOLCHAIN_NAMES[CLS.name]
+
+@given(fixed_dictionaries({
+    'common': lists(text()),
+    'c': lists(text()),
+    'cxx': lists(text()),
+    'asm': lists(text()),
+    'ld': lists(text(min_size=1))}),
+       lists(text(min_size=1, alphabet=ALPHABET), min_size=1))
+def test_toolchain_profile_ld(profile, source_file):
+    """Test that the appropriate profile parameters are passed to the
+    Linker"""
+    filename = deepcopy(source_file)
+    filename[-1] += ".o"
+    to_compile = os.path.join(*filename)
+    with patch('os.mkdir') as _mkdir,\
+         patch('tools.toolchains.mbedToolchain.default_cmd') as _dflt_cmd:
+        for _, tc_class in TOOLCHAIN_CLASSES.items():
+            toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile)
+            toolchain.RESPONSE_FILES = False
+            toolchain.inc_md5 = ""
+            toolchain.build_dir = ""
+            for parameter in profile['ld']:
+                assert any(parameter in cmd for cmd in toolchain.ld), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
+            toolchain.link(to_compile + ".elf", [to_compile], [], [], None)
+            compile_cmd = _dflt_cmd.call_args_list
+            if not compile_cmd:
+                assert compile_cmd, to_compile
+            for parameter in profile['ld']:
+                assert any(parameter in cmd[0][0] for cmd in compile_cmd), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
+
+    for name, Class in  TOOLCHAIN_CLASSES.items():
+        CLS = Class(TARGET_MAP["K64F"])
+        assert name == CLS.name or name ==  LEGACY_TOOLCHAIN_NAMES[CLS.name]
+
+
+@given(lists(text(alphabet=ALPHABET, min_size=1), min_size=1))
+def test_detect_duplicates(filenames):
+    c_sources = [os.path.join(name, "dupe.c") for name in filenames]
+    s_sources = [os.path.join(name, "dupe.s") for name in filenames]
+    cpp_sources = [os.path.join(name, "dupe.cpp") for name in filenames]
+    with MagicMock() as notify:
+        toolchain = TOOLCHAIN_CLASSES["ARM"](TARGET_MAP["K64F"], notify=notify)
+        res = Resources()
+        res.c_sources = c_sources
+        res.s_sources = s_sources
+        res.cpp_sources = cpp_sources
+        assert res.detect_duplicates(toolchain) == 1,\
+            "Not Enough duplicates found"
+
+        _, (notification, _), _ = notify.mock_calls[1]
+        assert "dupe.o" in notification["message"]
+        assert "dupe.s" in notification["message"]
+        assert "dupe.c" in notification["message"]
+        assert "dupe.cpp" in notification["message"]
+
+@given(text(alphabet=ALPHABET + ["/"], min_size=1))
+@given(booleans())
+@given(booleans())
+@settings(max_examples=20)
+def test_path_specified_gcc(gcc_loc, exists_at_loc, exists_in_path):
+    with patch('tools.toolchains.gcc.exists') as _exists:
+        with patch('tools.toolchains.gcc.find_executable') as _find:
+            _exists.return_value = exists_at_loc
+            _find.return_value = exists_in_path
+            TOOLCHAIN_PATHS['GCC_ARM'] = gcc_loc
+            toolchain_class = TOOLCHAIN_CLASSES["GCC_ARM"]
+            found_p = toolchain_class.check_executable()
+            assert found_p == (exists_at_loc or exists_in_path)
+            if exists_at_loc:
+                assert TOOLCHAIN_PATHS['GCC_ARM'] == gcc_loc
+            elif exists_in_path:
+                assert TOOLCHAIN_PATHS['GCC_ARM'] == ''
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/toolchains/arm_support_test.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/toolchains/arm_support_test.py
new file mode 100755
index 0000000..f26935a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test/toolchains/arm_support_test.py
@@ -0,0 +1,65 @@
+"""Tests for the arm toolchain supported checks"""
+import sys
+import os
+from string import printable
+from copy import deepcopy
+from mock import MagicMock, patch
+from hypothesis import given, settings
+from hypothesis.strategies import text, lists, sampled_from
+
+ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..",
+                                    ".."))
+sys.path.insert(0, ROOT)
+
+from tools.toolchains.arm import ARM_STD, ARM_MICRO, ARMC6
+from tools.utils import NotSupportedException
+
+ARMC5_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
+               "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"]
+ARMC6_CORES = ARMC5_CORES + ["Cortex-M23", "Cortex-M23-NS",
+                             "Cortex-M33", "CortexM33-NS"]
+
+CORE_SUF_ALPHA = ["MDFNS02347-+"]
+
+@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])),
+       text(alphabet=CORE_SUF_ALPHA))
+def test_arm_std(supported_toolchains, core):
+    mock_target = MagicMock()
+    mock_target.core = "Cortex-" + core
+    mock_target.supported_toolchains = supported_toolchains
+    try:
+        ARM_STD(mock_target)
+        assert "ARM" in supported_toolchains
+        assert mock_target.core in ARMC5_CORES
+    except NotSupportedException:
+        assert "ARM" not in supported_toolchains or mock_target.core not in ARMC5_CORES
+
+
+@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])),
+       text(alphabet=CORE_SUF_ALPHA))
+def test_arm_micro(supported_toolchains, core):
+    mock_target = MagicMock()
+    mock_target.core = "Cortex-" + core
+    mock_target.supported_toolchains = supported_toolchains
+    try:
+        ARM_MICRO(mock_target)
+        assert "ARM" in supported_toolchains or "uARM" in supported_toolchains
+        assert mock_target.core in ARMC5_CORES
+    except NotSupportedException:
+        assert ("ARM" not in supported_toolchains and "uARM" not in supported_toolchains)\
+            or mock_target.core not in ARMC5_CORES
+
+
+@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])),
+       text(alphabet=CORE_SUF_ALPHA))
+def test_armc6(supported_toolchains, core):
+    mock_target = MagicMock()
+    mock_target.core = "Cortex-" + core
+    mock_target.supported_toolchains = supported_toolchains
+    try:
+        ARMC6(mock_target)
+        assert "ARM" in supported_toolchains or "ARMC6" in supported_toolchains
+        assert mock_target.core in ARMC6_CORES
+    except NotSupportedException:
+        assert ("ARM" not in supported_toolchains and "ARMC6" not in supported_toolchains)\
+            or mock_target.core not in ARMC6_CORES
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_api.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_api.py
new file mode 100755
index 0000000..cc549d7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_api.py
@@ -0,0 +1,2274 @@
+"""
+mbed SDK
+Copyright (c) 2011-2014 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.wirkus@arm.com>
+"""
+
+import os
+import re
+import sys
+import json
+import uuid
+import pprint
+import random
+import argparse
+import datetime
+import threading
+import ctypes
+from types import ListType
+from colorama import Fore, Back, Style
+from prettytable import PrettyTable
+from copy import copy
+
+from time import sleep, time
+from Queue import Queue, Empty
+from os.path import join, exists, basename, relpath
+from threading import Thread, Lock
+from multiprocessing import Pool, cpu_count
+from subprocess import Popen, PIPE
+
+# Imports related to mbed build api
+from tools.tests import TESTS
+from tools.tests import TEST_MAP
+from tools.paths import BUILD_DIR
+from tools.paths import HOST_TESTS
+from tools.utils import ToolException
+from tools.utils import NotSupportedException
+from tools.utils import construct_enum
+from tools.memap import MemapParser
+from tools.targets import TARGET_MAP
+import tools.test_configs as TestConfig
+from tools.test_db import BaseDBAccess
+from tools.build_api import build_project, build_mbed_libs, build_lib
+from tools.build_api import get_target_supported_toolchains
+from tools.build_api import write_build_report
+from tools.build_api import prep_report
+from tools.build_api import prep_properties
+from tools.build_api import create_result
+from tools.build_api import add_result_to_report
+from tools.build_api import prepare_toolchain
+from tools.build_api import scan_resources
+from tools.build_api import get_config
+from tools.libraries import LIBRARIES, LIBRARY_MAP
+from tools.options import extract_profile
+from tools.toolchains import TOOLCHAIN_PATHS
+from tools.toolchains import TOOLCHAINS
+from tools.test_exporters import ReportExporter, ResultExporterType
+from tools.utils import argparse_filestring_type
+from tools.utils import argparse_uppercase_type
+from tools.utils import argparse_lowercase_type
+from tools.utils import argparse_many
+from tools.utils import get_path_depth
+
+import tools.host_tests.host_tests_plugins as host_tests_plugins
+
+try:
+    import mbed_lstools
+    from tools.compliance.ioper_runner import get_available_oper_test_scopes
+except:
+    pass
+
+
+class ProcessObserver(Thread):
+    def __init__(self, proc):
+        Thread.__init__(self)
+        self.proc = proc
+        self.queue = Queue()
+        self.daemon = True
+        self.active = True
+        self.start()
+
+    def run(self):
+        while self.active:
+            c = self.proc.stdout.read(1)
+            self.queue.put(c)
+
+    def stop(self):
+        self.active = False
+        try:
+            self.proc.terminate()
+        except Exception, _:
+            pass
+
+
+class SingleTestExecutor(threading.Thread):
+    """ Example: Single test class in separate thread usage
+    """
+    def __init__(self, single_test):
+        self.single_test = single_test
+        threading.Thread.__init__(self)
+
+    def run(self):
+        start = time()
+        # Execute tests depending on options and filter applied
+        test_summary, shuffle_seed, test_summary_ext, test_suite_properties_ext = self.single_test.execute()
+        elapsed_time = time() - start
+
+        # Human readable summary
+        if not self.single_test.opts_suppress_summary:
+            # prints well-formed summary with results (SQL table like)
+            print self.single_test.generate_test_summary(test_summary, shuffle_seed)
+        if self.single_test.opts_test_x_toolchain_summary:
+            # prints well-formed summary with results (SQL table like)
+            # table shows text x toolchain test result matrix
+            print self.single_test.generate_test_summary_by_target(test_summary, shuffle_seed)
+        print "Completed in %.2f sec"% (elapsed_time)
+
+
+class SingleTestRunner(object):
+    """ Object wrapper for single test run which may involve multiple MUTs
+    """
+    RE_DETECT_TESTCASE_RESULT = None
+
+    # Return codes for test script
+    TEST_RESULT_OK = "OK"
+    TEST_RESULT_FAIL = "FAIL"
+    TEST_RESULT_ERROR = "ERROR"
+    TEST_RESULT_UNDEF = "UNDEF"
+    TEST_RESULT_IOERR_COPY = "IOERR_COPY"
+    TEST_RESULT_IOERR_DISK = "IOERR_DISK"
+    TEST_RESULT_IOERR_SERIAL = "IOERR_SERIAL"
+    TEST_RESULT_TIMEOUT = "TIMEOUT"
+    TEST_RESULT_NO_IMAGE = "NO_IMAGE"
+    TEST_RESULT_MBED_ASSERT = "MBED_ASSERT"
+    TEST_RESULT_BUILD_FAILED = "BUILD_FAILED"
+    TEST_RESULT_NOT_SUPPORTED = "NOT_SUPPORTED"
+
+    GLOBAL_LOOPS_COUNT = 1  # How many times each test should be repeated
+    TEST_LOOPS_LIST = []    # We redefine no.of loops per test_id
+    TEST_LOOPS_DICT = {}    # TEST_LOOPS_LIST in dict format: { test_id : test_loop_count}
+
+    muts = {} # MUTs descriptor (from external file)
+    test_spec = {} # Test specification (from external file)
+
+    # mbed test suite -> SingleTestRunner
+    TEST_RESULT_MAPPING = {"success" : TEST_RESULT_OK,
+                           "failure" : TEST_RESULT_FAIL,
+                           "error" : TEST_RESULT_ERROR,
+                           "ioerr_copy" : TEST_RESULT_IOERR_COPY,
+                           "ioerr_disk" : TEST_RESULT_IOERR_DISK,
+                           "ioerr_serial" : TEST_RESULT_IOERR_SERIAL,
+                           "timeout" : TEST_RESULT_TIMEOUT,
+                           "no_image" : TEST_RESULT_NO_IMAGE,
+                           "end" : TEST_RESULT_UNDEF,
+                           "mbed_assert" : TEST_RESULT_MBED_ASSERT,
+                           "build_failed" : TEST_RESULT_BUILD_FAILED,
+                           "not_supproted" : TEST_RESULT_NOT_SUPPORTED
+    }
+
+    def __init__(self,
+                 _global_loops_count=1,
+                 _test_loops_list=None,
+                 _muts={},
+                 _clean=False,
+                 _parser=None,
+                 _opts=None,
+                 _opts_db_url=None,
+                 _opts_log_file_name=None,
+                 _opts_report_html_file_name=None,
+                 _opts_report_junit_file_name=None,
+                 _opts_report_build_file_name=None,
+                 _opts_report_text_file_name=None,
+                 _opts_build_report={},
+                 _opts_build_properties={},
+                 _test_spec={},
+                 _opts_goanna_for_mbed_sdk=None,
+                 _opts_goanna_for_tests=None,
+                 _opts_shuffle_test_order=False,
+                 _opts_shuffle_test_seed=None,
+                 _opts_test_by_names=None,
+                 _opts_peripheral_by_names=None,
+                 _opts_test_only_peripheral=False,
+                 _opts_test_only_common=False,
+                 _opts_verbose_skipped_tests=False,
+                 _opts_verbose_test_result_only=False,
+                 _opts_verbose=False,
+                 _opts_firmware_global_name=None,
+                 _opts_only_build_tests=False,
+                 _opts_parallel_test_exec=False,
+                 _opts_suppress_summary=False,
+                 _opts_test_x_toolchain_summary=False,
+                 _opts_copy_method=None,
+                 _opts_mut_reset_type=None,
+                 _opts_jobs=None,
+                 _opts_waterfall_test=None,
+                 _opts_consolidate_waterfall_test=None,
+                 _opts_extend_test_timeout=None,
+                 _opts_auto_detect=None,
+                 _opts_include_non_automated=False):
+        """ Let's try hard to init this object
+        """
+        from colorama import init
+        init()
+
+        PATTERN = "\\{(" + "|".join(self.TEST_RESULT_MAPPING.keys()) + ")\\}"
+        self.RE_DETECT_TESTCASE_RESULT = re.compile(PATTERN)
+        # Settings related to test loops counters
+        try:
+            _global_loops_count = int(_global_loops_count)
+        except:
+            _global_loops_count = 1
+        if _global_loops_count < 1:
+            _global_loops_count = 1
+        self.GLOBAL_LOOPS_COUNT = _global_loops_count
+        self.TEST_LOOPS_LIST = _test_loops_list if _test_loops_list else []
+        self.TEST_LOOPS_DICT = self.test_loop_list_to_dict(_test_loops_list)
+
+        self.shuffle_random_seed = 0.0
+        self.SHUFFLE_SEED_ROUND = 10
+
+        # MUT list and test specification storage
+        self.muts = _muts
+        self.test_spec = _test_spec
+
+        # Settings passed e.g. from command line
+        self.opts_db_url = _opts_db_url
+        self.opts_log_file_name = _opts_log_file_name
+        self.opts_report_html_file_name = _opts_report_html_file_name
+        self.opts_report_junit_file_name = _opts_report_junit_file_name
+        self.opts_report_build_file_name = _opts_report_build_file_name
+        self.opts_report_text_file_name = _opts_report_text_file_name
+        self.opts_goanna_for_mbed_sdk = _opts_goanna_for_mbed_sdk
+        self.opts_goanna_for_tests = _opts_goanna_for_tests
+        self.opts_shuffle_test_order = _opts_shuffle_test_order
+        self.opts_shuffle_test_seed = _opts_shuffle_test_seed
+        self.opts_test_by_names = _opts_test_by_names
+        self.opts_peripheral_by_names = _opts_peripheral_by_names
+        self.opts_test_only_peripheral = _opts_test_only_peripheral
+        self.opts_test_only_common = _opts_test_only_common
+        self.opts_verbose_skipped_tests = _opts_verbose_skipped_tests
+        self.opts_verbose_test_result_only = _opts_verbose_test_result_only
+        self.opts_verbose = _opts_verbose
+        self.opts_firmware_global_name = _opts_firmware_global_name
+        self.opts_only_build_tests = _opts_only_build_tests
+        self.opts_parallel_test_exec = _opts_parallel_test_exec
+        self.opts_suppress_summary = _opts_suppress_summary
+        self.opts_test_x_toolchain_summary = _opts_test_x_toolchain_summary
+        self.opts_copy_method = _opts_copy_method
+        self.opts_mut_reset_type = _opts_mut_reset_type
+        self.opts_jobs = _opts_jobs if _opts_jobs is not None else 1
+        self.opts_waterfall_test = _opts_waterfall_test
+        self.opts_consolidate_waterfall_test = _opts_consolidate_waterfall_test
+        self.opts_extend_test_timeout = _opts_extend_test_timeout
+        self.opts_clean = _clean
+        self.opts_parser = _parser
+        self.opts = _opts
+        self.opts_auto_detect = _opts_auto_detect
+        self.opts_include_non_automated = _opts_include_non_automated
+
+        self.build_report = _opts_build_report
+        self.build_properties = _opts_build_properties
+
+        # File / screen logger initialization
+        self.logger = CLITestLogger(file_name=self.opts_log_file_name)  # Default test logger
+
+        # Database related initializations
+        self.db_logger = factory_db_logger(self.opts_db_url)
+        self.db_logger_build_id = None # Build ID (database index of build_id table)
+        # Let's connect to database to set up credentials and confirm database is ready
+        if self.db_logger:
+            self.db_logger.connect_url(self.opts_db_url) # Save db access info inside db_logger object
+            if self.db_logger.is_connected():
+                # Get hostname and uname so we can use it as build description
+                # when creating new build_id in external database
+                (_hostname, _uname) = self.db_logger.get_hostname()
+                _host_location = os.path.dirname(os.path.abspath(__file__))
+                build_id_type = None if self.opts_only_build_tests is None else self.db_logger.BUILD_ID_TYPE_BUILD_ONLY
+                self.db_logger_build_id = self.db_logger.get_next_build_id(_hostname, desc=_uname, location=_host_location, type=build_id_type)
+                self.db_logger.disconnect()
+
+    def dump_options(self):
+        """ Function returns data structure with common settings passed to SingelTestRunner
+            It can be used for example to fill _extra fields in database storing test suite single run data
+            Example:
+            data = self.dump_options()
+            or
+            data_str = json.dumps(self.dump_options())
+        """
+        result = {"db_url" : str(self.opts_db_url),
+                  "log_file_name" :  str(self.opts_log_file_name),
+                  "shuffle_test_order" : str(self.opts_shuffle_test_order),
+                  "shuffle_test_seed" : str(self.opts_shuffle_test_seed),
+                  "test_by_names" :  str(self.opts_test_by_names),
+                  "peripheral_by_names" : str(self.opts_peripheral_by_names),
+                  "test_only_peripheral" :  str(self.opts_test_only_peripheral),
+                  "test_only_common" :  str(self.opts_test_only_common),
+                  "verbose" :  str(self.opts_verbose),
+                  "firmware_global_name" :  str(self.opts_firmware_global_name),
+                  "only_build_tests" :  str(self.opts_only_build_tests),
+                  "copy_method" :  str(self.opts_copy_method),
+                  "mut_reset_type" :  str(self.opts_mut_reset_type),
+                  "jobs" :  str(self.opts_jobs),
+                  "extend_test_timeout" :  str(self.opts_extend_test_timeout),
+                  "_dummy" : ''
+        }
+        return result
+
+    def shuffle_random_func(self):
+        return self.shuffle_random_seed
+
+    def is_shuffle_seed_float(self):
+        """ return true if function parameter can be converted to float
+        """
+        result = True
+        try:
+            float(self.shuffle_random_seed)
+        except ValueError:
+            result = False
+        return result
+
+    # This will store target / toolchain specific properties
+    test_suite_properties_ext = {}  # target : toolchain
+    # Here we store test results
+    test_summary = []
+    # Here we store test results in extended data structure
+    test_summary_ext = {}
+    execute_thread_slice_lock = Lock()
+
+    def execute_thread_slice(self, q, target, toolchains, clean, test_ids, build_report, build_properties):
+        for toolchain in toolchains:
+            tt_id = "%s::%s" % (toolchain, target)
+
+            T = TARGET_MAP[target]
+
+            # print target, toolchain
+            # Test suite properties returned to external tools like CI
+            test_suite_properties = {
+                'jobs': self.opts_jobs,
+                'clean': clean,
+                'target': target,
+                'vendor': T.extra_labels[0],
+                'test_ids': ', '.join(test_ids),
+                'toolchain': toolchain,
+                'shuffle_random_seed': self.shuffle_random_seed
+            }
+
+
+            # print '=== %s::%s ===' % (target, toolchain)
+            # Let's build our test
+            if target not in TARGET_MAP:
+                print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Target platform not found'% (target))
+                continue
+
+            clean_mbed_libs_options = True if self.opts_goanna_for_mbed_sdk or clean or self.opts_clean else None
+
+            profile = extract_profile(self.opts_parser, self.opts, toolchain)
+            stats_depth = self.opts.stats_depth or 2
+
+
+            try:
+                build_mbed_libs_result = build_mbed_libs(T,
+                                                         toolchain,
+                                                         clean=clean_mbed_libs_options,
+                                                         verbose=self.opts_verbose,
+                                                         jobs=self.opts_jobs,
+                                                         report=build_report,
+                                                         properties=build_properties,
+                                                         build_profile=profile)
+
+                if not build_mbed_libs_result:
+                    print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Toolchain %s is not yet supported for this target'% (T.name, toolchain))
+                    continue
+
+            except ToolException:
+                print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building MBED libs for %s using %s'% (target, toolchain))
+                continue
+
+            build_dir = join(BUILD_DIR, "test", target, toolchain)
+
+            test_suite_properties['build_mbed_libs_result'] = build_mbed_libs_result
+            test_suite_properties['build_dir'] = build_dir
+            test_suite_properties['skipped'] = []
+
+            # Enumerate through all tests and shuffle test order if requested
+            test_map_keys = sorted(TEST_MAP.keys())
+
+            if self.opts_shuffle_test_order:
+                random.shuffle(test_map_keys, self.shuffle_random_func)
+                # Update database with shuffle seed f applicable
+                if self.db_logger:
+                    self.db_logger.reconnect();
+                    if self.db_logger.is_connected():
+                        self.db_logger.update_build_id_info(self.db_logger_build_id, _shuffle_seed=self.shuffle_random_func())
+                        self.db_logger.disconnect();
+
+            if self.db_logger:
+                self.db_logger.reconnect();
+                if self.db_logger.is_connected():
+                    # Update MUTs and Test Specification in database
+                    self.db_logger.update_build_id_info(self.db_logger_build_id, _muts=self.muts, _test_spec=self.test_spec)
+                    # Update Extra information in database (some options passed to test suite)
+                    self.db_logger.update_build_id_info(self.db_logger_build_id, _extra=json.dumps(self.dump_options()))
+                    self.db_logger.disconnect();
+
+            valid_test_map_keys = self.get_valid_tests(test_map_keys, target, toolchain, test_ids, self.opts_include_non_automated)
+            skipped_test_map_keys = self.get_skipped_tests(test_map_keys, valid_test_map_keys)
+
+            for skipped_test_id in skipped_test_map_keys:
+                test_suite_properties['skipped'].append(skipped_test_id)
+
+
+            # First pass through all tests and determine which libraries need to be built
+            libraries = []
+            for test_id in valid_test_map_keys:
+                test = TEST_MAP[test_id]
+
+                # Detect which lib should be added to test
+                # Some libs have to compiled like RTOS or ETH
+                for lib in LIBRARIES:
+                    if lib['build_dir'] in test.dependencies and lib['id'] not in libraries:
+                        libraries.append(lib['id'])
+
+
+            clean_project_options = True if self.opts_goanna_for_tests or clean or self.opts_clean else None
+
+            # Build all required libraries
+            for lib_id in libraries:
+                try:
+                    build_lib(lib_id,
+                              T,
+                              toolchain,
+                              verbose=self.opts_verbose,
+                              clean=clean_mbed_libs_options,
+                              jobs=self.opts_jobs,
+                              report=build_report,
+                              properties=build_properties,
+                              build_profile=profile)
+
+                except ToolException:
+                    print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building library %s'% (lib_id))
+                    continue
+
+
+            for test_id in valid_test_map_keys:
+                test = TEST_MAP[test_id]
+
+                test_suite_properties['test.libs.%s.%s.%s'% (target, toolchain, test_id)] = ', '.join(libraries)
+
+                # TODO: move this 2 below loops to separate function
+                INC_DIRS = []
+                for lib_id in libraries:
+                    if 'inc_dirs_ext' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['inc_dirs_ext']:
+                        INC_DIRS.extend(LIBRARY_MAP[lib_id]['inc_dirs_ext'])
+
+                MACROS = []
+                for lib_id in libraries:
+                    if 'macros' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['macros']:
+                        MACROS.extend(LIBRARY_MAP[lib_id]['macros'])
+                MACROS.append('TEST_SUITE_TARGET_NAME="%s"'% target)
+                MACROS.append('TEST_SUITE_TEST_ID="%s"'% test_id)
+                test_uuid = uuid.uuid4()
+                MACROS.append('TEST_SUITE_UUID="%s"'% str(test_uuid))
+
+                # Prepare extended test results data structure (it can be used to generate detailed test report)
+                if target not in self.test_summary_ext:
+                    self.test_summary_ext[target] = {}  # test_summary_ext : toolchain
+                if toolchain not in self.test_summary_ext[target]:
+                    self.test_summary_ext[target][toolchain] = {}    # test_summary_ext : toolchain : target
+
+                tt_test_id = "%s::%s::%s" % (toolchain, target, test_id)    # For logging only
+
+                project_name = self.opts_firmware_global_name if self.opts_firmware_global_name else None
+                try:
+                    path = build_project(test.source_dir, join(build_dir, test_id), T,
+                        toolchain, test.dependencies, clean=clean_project_options,
+                        verbose=self.opts_verbose, name=project_name, macros=MACROS,
+                        inc_dirs=INC_DIRS, jobs=self.opts_jobs, report=build_report,
+                        properties=build_properties, project_id=test_id,
+                        project_description=test.get_description(),
+                        build_profile=profile, stats_depth=stats_depth)
+
+                except Exception, e:
+                    project_name_str = project_name if project_name is not None else test_id
+
+
+                    test_result = self.TEST_RESULT_FAIL
+
+                    if isinstance(e, ToolException):
+                        print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str))
+                        test_result = self.TEST_RESULT_BUILD_FAILED
+                    elif isinstance(e, NotSupportedException):
+                        print self.logger.log_line(self.logger.LogType.INFO, 'The project %s is not supported'% (project_name_str))
+                        test_result = self.TEST_RESULT_NOT_SUPPORTED
+
+
+                    # Append test results to global test summary
+                    self.test_summary.append(
+                        (test_result, target, toolchain, test_id, test.get_description(), 0, 0, '-')
+                    )
+
+                    # Add detailed test result to test summary structure
+                    if test_id not in self.test_summary_ext[target][toolchain]:
+                        self.test_summary_ext[target][toolchain][test_id] = []
+
+                    self.test_summary_ext[target][toolchain][test_id].append({ 0: {
+                        'result' : test_result,
+                        'output' : '',
+                        'target_name' : target,
+                        'target_name_unique': target,
+                        'toolchain_name' : toolchain,
+                        'id' : test_id,
+                        'description' : test.get_description(),
+                        'elapsed_time' : 0,
+                        'duration' : 0,
+                        'copy_method' : None
+                    }})
+                    continue
+
+                if self.opts_only_build_tests:
+                    # With this option we are skipping testing phase
+                    continue
+
+                # Test duration can be increased by global value
+                test_duration = test.duration
+                if self.opts_extend_test_timeout is not None:
+                    test_duration += self.opts_extend_test_timeout
+
+                # For an automated test the duration act as a timeout after
+                # which the test gets interrupted
+                test_spec = self.shape_test_request(target, path, test_id, test_duration)
+                test_loops = self.get_test_loop_count(test_id)
+
+                test_suite_properties['test.duration.%s.%s.%s'% (target, toolchain, test_id)] = test_duration
+                test_suite_properties['test.loops.%s.%s.%s'% (target, toolchain, test_id)] = test_loops
+                test_suite_properties['test.path.%s.%s.%s'% (target, toolchain, test_id)] = path
+
+                # read MUTs, test specification and perform tests
+                handle_results = self.handle(test_spec, target, toolchain, test_loops=test_loops)
+
+                if handle_results is None:
+                    continue
+
+                for handle_result in handle_results:
+                    if handle_result:
+                        single_test_result, detailed_test_results = handle_result
+                    else:
+                        continue
+
+                    # Append test results to global test summary
+                    if single_test_result is not None:
+                        self.test_summary.append(single_test_result)
+
+                    # Add detailed test result to test summary structure
+                    if target not in self.test_summary_ext[target][toolchain]:
+                        if test_id not in self.test_summary_ext[target][toolchain]:
+                            self.test_summary_ext[target][toolchain][test_id] = []
+
+                        append_test_result = detailed_test_results
+
+                        # If waterfall and consolidate-waterfall options are enabled,
+                        # only include the last test result in the report.
+                        if self.opts_waterfall_test and self.opts_consolidate_waterfall_test:
+                            append_test_result = {0: detailed_test_results[len(detailed_test_results) - 1]}
+
+                        self.test_summary_ext[target][toolchain][test_id].append(append_test_result)
+
+            test_suite_properties['skipped'] = ', '.join(test_suite_properties['skipped'])
+            self.test_suite_properties_ext[target][toolchain] = test_suite_properties
+
+        q.put(target + '_'.join(toolchains))
+        return
+
+    def execute(self):
+        clean = self.test_spec.get('clean', False)
+        test_ids = self.test_spec.get('test_ids', [])
+        q = Queue()
+
+        # Generate seed for shuffle if seed is not provided in
+        self.shuffle_random_seed = round(random.random(), self.SHUFFLE_SEED_ROUND)
+        if self.opts_shuffle_test_seed is not None and self.is_shuffle_seed_float():
+            self.shuffle_random_seed = round(float(self.opts_shuffle_test_seed), self.SHUFFLE_SEED_ROUND)
+
+
+        if self.opts_parallel_test_exec:
+            ###################################################################
+            # Experimental, parallel test execution per singletest instance.
+            ###################################################################
+            execute_threads = []    # Threads used to build mbed SDL, libs, test cases and execute tests
+            # Note: We are building here in parallel for each target separately!
+            # So we are not building the same thing multiple times and compilers
+            # in separate threads do not collide.
+            # Inside execute_thread_slice() function function handle() will be called to
+            # get information about available MUTs (per target).
+            for target, toolchains in self.test_spec['targets'].iteritems():
+                self.test_suite_properties_ext[target] = {}
+                t = threading.Thread(target=self.execute_thread_slice, args = (q, target, toolchains, clean, test_ids, self.build_report, self.build_properties))
+                t.daemon = True
+                t.start()
+                execute_threads.append(t)
+
+            for t in execute_threads:
+                q.get() # t.join() would block some threads because we should not wait in any order for thread end
+        else:
+            # Serialized (not parallel) test execution
+            for target, toolchains in self.test_spec['targets'].iteritems():
+                if target not in self.test_suite_properties_ext:
+                    self.test_suite_properties_ext[target] = {}
+
+                self.execute_thread_slice(q, target, toolchains, clean, test_ids, self.build_report, self.build_properties)
+                q.get()
+
+        if self.db_logger:
+            self.db_logger.reconnect();
+            if self.db_logger.is_connected():
+                self.db_logger.update_build_id_info(self.db_logger_build_id, _status_fk=self.db_logger.BUILD_ID_STATUS_COMPLETED)
+                self.db_logger.disconnect();
+
+        return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext, self.build_report, self.build_properties
+
+    def get_valid_tests(self, test_map_keys, target, toolchain, test_ids, include_non_automated):
+        valid_test_map_keys = []
+
+        for test_id in test_map_keys:
+            test = TEST_MAP[test_id]
+            if self.opts_test_by_names and test_id not in self.opts_test_by_names:
+                continue
+
+            if test_ids and test_id not in test_ids:
+                continue
+
+            if self.opts_test_only_peripheral and not test.peripherals:
+                if self.opts_verbose_skipped_tests:
+                    print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target))
+                continue
+
+            if self.opts_peripheral_by_names and test.peripherals and not len([i for i in test.peripherals if i in self.opts_peripheral_by_names]):
+                # We will skip tests not forced with -p option
+                if self.opts_verbose_skipped_tests:
+                    print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target))
+                continue
+
+            if self.opts_test_only_common and test.peripherals:
+                if self.opts_verbose_skipped_tests:
+                    print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral test skipped for target %s'% (target))
+                continue
+
+            if not include_non_automated and not test.automated:
+                if self.opts_verbose_skipped_tests:
+                    print self.logger.log_line(self.logger.LogType.INFO, 'Non automated test skipped for target %s'% (target))
+                continue
+
+            if test.is_supported(target, toolchain):
+                if test.peripherals is None and self.opts_only_build_tests:
+                    # When users are using 'build only flag' and test do not have
+                    # specified peripherals we can allow test building by default
+                    pass
+                elif self.opts_peripheral_by_names and test_id not in self.opts_peripheral_by_names:
+                    # If we force peripheral with option -p we expect test
+                    # to pass even if peripheral is not in MUTs file.
+                    pass
+                elif not self.is_peripherals_available(target, test.peripherals):
+                    if self.opts_verbose_skipped_tests:
+                        if test.peripherals:
+                            print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral %s test skipped for target %s'% (",".join(test.peripherals), target))
+                        else:
+                            print self.logger.log_line(self.logger.LogType.INFO, 'Test %s skipped for target %s'% (test_id, target))
+                    continue
+
+                # The test has made it through all the filters, so add it to the valid tests list
+                valid_test_map_keys.append(test_id)
+
+        return valid_test_map_keys
+
+    def get_skipped_tests(self, all_test_map_keys, valid_test_map_keys):
+        # NOTE: This will not preserve order
+        return list(set(all_test_map_keys) - set(valid_test_map_keys))
+
+    def generate_test_summary_by_target(self, test_summary, shuffle_seed=None):
+        """ Prints well-formed summary with results (SQL table like)
+            table shows text x toolchain test result matrix
+        """
+        RESULT_INDEX = 0
+        TARGET_INDEX = 1
+        TOOLCHAIN_INDEX = 2
+        TEST_INDEX = 3
+        DESC_INDEX = 4
+
+        unique_targets = get_unique_value_from_summary(test_summary, TARGET_INDEX)
+        unique_tests = get_unique_value_from_summary(test_summary, TEST_INDEX)
+        unique_test_desc = get_unique_value_from_summary_ext(test_summary, TEST_INDEX, DESC_INDEX)
+        unique_toolchains = get_unique_value_from_summary(test_summary, TOOLCHAIN_INDEX)
+
+        result = "Test summary:\n"
+        for target in unique_targets:
+            result_dict = {} # test : { toolchain : result }
+            unique_target_toolchains = []
+            for test in test_summary:
+                if test[TARGET_INDEX] == target:
+                    if test[TOOLCHAIN_INDEX] not in unique_target_toolchains:
+                        unique_target_toolchains.append(test[TOOLCHAIN_INDEX])
+                    if test[TEST_INDEX] not in result_dict:
+                        result_dict[test[TEST_INDEX]] = {}
+                    result_dict[test[TEST_INDEX]][test[TOOLCHAIN_INDEX]] = test[RESULT_INDEX]
+
+            pt_cols = ["Target", "Test ID", "Test Description"] + unique_target_toolchains
+            pt = PrettyTable(pt_cols)
+            for col in pt_cols:
+                pt.align[col] = "l"
+            pt.padding_width = 1 # One space between column edges and contents (default)
+
+            for test in unique_tests:
+                if test in result_dict:
+                    test_results = result_dict[test]
+                    if test in unique_test_desc:
+                        row = [target, test, unique_test_desc[test]]
+                        for toolchain in unique_toolchains:
+                            if toolchain in test_results:
+                                row.append(test_results[toolchain])
+                        pt.add_row(row)
+            result += pt.get_string()
+            shuffle_seed_text = "Shuffle Seed: %.*f"% (self.SHUFFLE_SEED_ROUND,
+                                                       shuffle_seed if shuffle_seed else self.shuffle_random_seed)
+            result += "\n%s"% (shuffle_seed_text if self.opts_shuffle_test_order else '')
+        return result
+
+    def generate_test_summary(self, test_summary, shuffle_seed=None):
+        """ Prints well-formed summary with results (SQL table like)
+            table shows target x test results matrix across
+        """
+        success_code = 0    # Success code that can be leter returned to
+        result = "Test summary:\n"
+        # Pretty table package is used to print results
+        pt = PrettyTable(["Result", "Target", "Toolchain", "Test ID", "Test Description",
+                          "Elapsed Time (sec)", "Timeout (sec)", "Loops"])
+        pt.align["Result"] = "l" # Left align
+        pt.align["Target"] = "l" # Left align
+        pt.align["Toolchain"] = "l" # Left align
+        pt.align["Test ID"] = "l" # Left align
+        pt.align["Test Description"] = "l" # Left align
+        pt.padding_width = 1 # One space between column edges and contents (default)
+
+        result_dict = {self.TEST_RESULT_OK : 0,
+                       self.TEST_RESULT_FAIL : 0,
+                       self.TEST_RESULT_ERROR : 0,
+                       self.TEST_RESULT_UNDEF : 0,
+                       self.TEST_RESULT_IOERR_COPY : 0,
+                       self.TEST_RESULT_IOERR_DISK : 0,
+                       self.TEST_RESULT_IOERR_SERIAL : 0,
+                       self.TEST_RESULT_NO_IMAGE : 0,
+                       self.TEST_RESULT_TIMEOUT : 0,
+                       self.TEST_RESULT_MBED_ASSERT : 0,
+                       self.TEST_RESULT_BUILD_FAILED : 0,
+                       self.TEST_RESULT_NOT_SUPPORTED : 0
+        }
+
+        for test in test_summary:
+            if test[0] in result_dict:
+                result_dict[test[0]] += 1
+            pt.add_row(test)
+        result += pt.get_string()
+        result += "\n"
+
+        # Print result count
+        result += "Result: " + ' / '.join(['%s %s' % (value, key) for (key, value) in {k: v for k, v in result_dict.items() if v != 0}.iteritems()])
+        shuffle_seed_text = "Shuffle Seed: %.*f\n"% (self.SHUFFLE_SEED_ROUND,
+                                                    shuffle_seed if shuffle_seed else self.shuffle_random_seed)
+        result += "\n%s"% (shuffle_seed_text if self.opts_shuffle_test_order else '')
+        return result
+
+    def test_loop_list_to_dict(self, test_loops_str):
+        """ Transforms test_id=X,test_id=X,test_id=X into dictionary {test_id : test_id_loops_count}
+        """
+        result = {}
+        if test_loops_str:
+            test_loops = test_loops_str
+            for test_loop in test_loops:
+                test_loop_count = test_loop.split('=')
+                if len(test_loop_count) == 2:
+                    _test_id, _test_loops = test_loop_count
+                    try:
+                        _test_loops = int(_test_loops)
+                    except:
+                        continue
+                    result[_test_id] = _test_loops
+        return result
+
+    def get_test_loop_count(self, test_id):
+        """ This function returns no. of loops per test (deducted by test_id_.
+            If test is not in list of redefined loop counts it will use default value.
+        """
+        result = self.GLOBAL_LOOPS_COUNT
+        if test_id in self.TEST_LOOPS_DICT:
+            result = self.TEST_LOOPS_DICT[test_id]
+        return result
+
+    def delete_file(self, file_path):
+        """ Remove file from the system
+        """
+        result = True
+        resutl_msg = ""
+        try:
+            os.remove(file_path)
+        except Exception, e:
+            resutl_msg = e
+            result = False
+        return result, resutl_msg
+
+    def handle_mut(self, mut, data, target_name, toolchain_name, test_loops=1):
+        """ Test is being invoked for given MUT.
+        """
+        # Get test information, image and test timeout
+        test_id = data['test_id']
+        test = TEST_MAP[test_id]
+        test_description = TEST_MAP[test_id].get_description()
+        image = data["image"]
+        duration = data.get("duration", 10)
+
+        if mut is None:
+            print "Error: No Mbed available: MUT[%s]" % data['mcu']
+            return None
+
+        mcu = mut['mcu']
+        copy_method = mut.get('copy_method')        # Available board configuration selection e.g. core selection etc.
+
+        if self.db_logger:
+            self.db_logger.reconnect()
+
+        selected_copy_method = self.opts_copy_method if copy_method is None else copy_method
+
+        # Tests can be looped so test results must be stored for the same test
+        test_all_result = []
+        # Test results for one test ran few times
+        detailed_test_results = {}  # { Loop_number: { results ... } }
+
+        for test_index in range(test_loops):
+
+            # If mbedls is available and we are auto detecting MUT info,
+            # update MUT info (mounting may changed)
+            if get_module_avail('mbed_lstools') and self.opts_auto_detect:
+                platform_name_filter = [mcu]
+                muts_list = {}
+                found = False
+
+                for i in range(0, 60):
+                    print('Looking for %s with MBEDLS' % mcu)
+                    muts_list = get_autodetected_MUTS_list(platform_name_filter=platform_name_filter)
+
+                    if 1 not in muts_list:
+                        sleep(3)
+                    else:
+                        found = True
+                        break
+
+                if not found:
+                    print "Error: mbed not found with MBEDLS: %s" % data['mcu']
+                    return None
+                else:
+                    mut = muts_list[1]
+
+            disk = mut.get('disk')
+            port = mut.get('port')
+
+            if disk is None or port is None:
+                return None
+
+            target_by_mcu = TARGET_MAP[mut['mcu']]
+            target_name_unique = mut['mcu_unique'] if 'mcu_unique' in mut else mut['mcu']
+            # Some extra stuff can be declared in MUTs structure
+            reset_type = mut.get('reset_type')  # reboot.txt, reset.txt, shutdown.txt
+            reset_tout = mut.get('reset_tout')  # COPY_IMAGE -> RESET_PROC -> SLEEP(RESET_TOUT)
+
+            # When the build and test system were separate, this was relative to a
+            # base network folder base path: join(NETWORK_BASE_PATH, )
+            image_path = image
+
+            # Host test execution
+            start_host_exec_time = time()
+
+            single_test_result = self.TEST_RESULT_UNDEF # single test run result
+            _copy_method = selected_copy_method
+
+            if not exists(image_path):
+                single_test_result = self.TEST_RESULT_NO_IMAGE
+                elapsed_time = 0
+                single_test_output = self.logger.log_line(self.logger.LogType.ERROR, 'Image file does not exist: %s'% image_path)
+                print single_test_output
+            else:
+                # Host test execution
+                start_host_exec_time = time()
+
+                host_test_verbose = self.opts_verbose_test_result_only or self.opts_verbose
+                host_test_reset = self.opts_mut_reset_type if reset_type is None else reset_type
+                host_test_result = self.run_host_test(test.host_test,
+                                                      image_path, disk, port, duration,
+                                                      micro=target_name,
+                                                      verbose=host_test_verbose,
+                                                      reset=host_test_reset,
+                                                      reset_tout=reset_tout,
+                                                      copy_method=selected_copy_method,
+                                                      program_cycle_s=target_by_mcu.program_cycle_s)
+                single_test_result, single_test_output, single_testduration, single_timeout = host_test_result
+
+            # Store test result
+            test_all_result.append(single_test_result)
+            total_elapsed_time = time() - start_host_exec_time   # Test time with copy (flashing) / reset
+            elapsed_time = single_testduration  # TIme of single test case execution after reset
+
+            detailed_test_results[test_index] = {
+                'result' : single_test_result,
+                'output' : single_test_output,
+                'target_name' : target_name,
+                'target_name_unique' : target_name_unique,
+                'toolchain_name' : toolchain_name,
+                'id' : test_id,
+                'description' : test_description,
+                'elapsed_time' : round(elapsed_time, 2),
+                'duration' : single_timeout,
+                'copy_method' : _copy_method,
+            }
+
+            print self.print_test_result(single_test_result, target_name_unique, toolchain_name,
+                                         test_id, test_description, elapsed_time, single_timeout)
+
+            # Update database entries for ongoing test
+            if self.db_logger and self.db_logger.is_connected():
+                test_type = 'SingleTest'
+                self.db_logger.insert_test_entry(self.db_logger_build_id,
+                                                 target_name,
+                                                 toolchain_name,
+                                                 test_type,
+                                                 test_id,
+                                                 single_test_result,
+                                                 single_test_output,
+                                                 elapsed_time,
+                                                 single_timeout,
+                                                 test_index)
+
+            # If we perform waterfall test we test until we get OK and we stop testing
+            if self.opts_waterfall_test and single_test_result == self.TEST_RESULT_OK:
+                break
+
+        if self.db_logger:
+            self.db_logger.disconnect()
+
+        return (self.shape_global_test_loop_result(test_all_result, self.opts_waterfall_test and self.opts_consolidate_waterfall_test),
+                target_name_unique,
+                toolchain_name,
+                test_id,
+                test_description,
+                round(elapsed_time, 2),
+                single_timeout,
+                self.shape_test_loop_ok_result_count(test_all_result)), detailed_test_results
+
+    def handle(self, test_spec, target_name, toolchain_name, test_loops=1):
+        """ Function determines MUT's mbed disk/port and copies binary to
+            target.
+        """
+        handle_results = []
+        data = json.loads(test_spec)
+
+        # Find a suitable MUT:
+        mut = None
+        for id, m in self.muts.iteritems():
+            if m['mcu'] == data['mcu']:
+                mut = m
+                handle_result = self.handle_mut(mut, data, target_name, toolchain_name, test_loops=test_loops)
+                handle_results.append(handle_result)
+
+        return handle_results
+
+    def print_test_result(self, test_result, target_name, toolchain_name,
+                          test_id, test_description, elapsed_time, duration):
+        """ Use specific convention to print test result and related data
+        """
+        tokens = []
+        tokens.append("TargetTest")
+        tokens.append(target_name)
+        tokens.append(toolchain_name)
+        tokens.append(test_id)
+        tokens.append(test_description)
+        separator = "::"
+        time_info = " in %.2f of %d sec" % (round(elapsed_time, 2), duration)
+        result = separator.join(tokens) + " [" + test_result +"]" + time_info
+        return Fore.MAGENTA + result + Fore.RESET
+
+    def shape_test_loop_ok_result_count(self, test_all_result):
+        """ Reformats list of results to simple string
+        """
+        test_loop_count = len(test_all_result)
+        test_loop_ok_result = test_all_result.count(self.TEST_RESULT_OK)
+        return "%d/%d"% (test_loop_ok_result, test_loop_count)
+
+    def shape_global_test_loop_result(self, test_all_result, waterfall_and_consolidate):
+        """ Reformats list of results to simple string
+        """
+        result = self.TEST_RESULT_FAIL
+
+        if all(test_all_result[0] == res for res in test_all_result):
+            result = test_all_result[0]
+        elif waterfall_and_consolidate and any(res == self.TEST_RESULT_OK for res in test_all_result):
+            result = self.TEST_RESULT_OK
+
+        return result
+
+    def run_host_test(self, name, image_path, disk, port, duration,
+                      micro=None, reset=None, reset_tout=None,
+                      verbose=False, copy_method=None, program_cycle_s=None):
+        """ Function creates new process with host test configured with particular test case.
+            Function also is pooling for serial port activity from process to catch all data
+            printed by test runner and host test during test execution
+        """
+
+        def get_char_from_queue(obs):
+            """ Get character from queue safe way
+            """
+            try:
+                c = obs.queue.get(block=True, timeout=0.5)
+            except Empty, _:
+                c = None
+            return c
+
+        def filter_queue_char(c):
+            """ Filters out non ASCII characters from serial port
+            """
+            if ord(c) not in range(128):
+                c = ' '
+            return c
+
+        def get_test_result(output):
+            """ Parse test 'output' data
+            """
+            result = self.TEST_RESULT_TIMEOUT
+            for line in "".join(output).splitlines():
+                search_result = self.RE_DETECT_TESTCASE_RESULT.search(line)
+                if search_result and len(search_result.groups()):
+                    result = self.TEST_RESULT_MAPPING[search_result.groups(0)[0]]
+                    break
+            return result
+
+        def get_auto_property_value(property_name, line):
+            """ Scans auto detection line from MUT and returns scanned parameter 'property_name'
+                Returns string
+            """
+            result = None
+            if re.search("HOST: Property '%s'"% property_name, line) is not None:
+                property = re.search("HOST: Property '%s' = '([\w\d _]+)'"% property_name, line)
+                if property is not None and len(property.groups()) == 1:
+                    result = property.groups()[0]
+            return result
+
+        # print "{%s} port:%s disk:%s"  % (name, port, disk),
+        cmd = ["python",
+               '%s.py'% name,
+               '-d', disk,
+               '-f', '"%s"'% image_path,
+               '-p', port,
+               '-t', str(duration),
+               '-C', str(program_cycle_s)]
+
+        if get_module_avail('mbed_lstools') and self.opts_auto_detect:
+            cmd += ['--auto']
+
+        # Add extra parameters to host_test
+        if copy_method is not None:
+            cmd += ["-c", copy_method]
+        if micro is not None:
+            cmd += ["-m", micro]
+        if reset is not None:
+            cmd += ["-r", reset]
+        if reset_tout is not None:
+            cmd += ["-R", str(reset_tout)]
+
+        if verbose:
+            print Fore.MAGENTA + "Executing '" + " ".join(cmd) + "'" + Fore.RESET
+            print "Test::Output::Start"
+
+        proc = Popen(cmd, stdout=PIPE, cwd=HOST_TESTS)
+        obs = ProcessObserver(proc)
+        update_once_flag = {}   # Stores flags checking if some auto-parameter was already set
+        line = ''
+        output = []
+        start_time = time()
+        while (time() - start_time) < (2 * duration):
+            c = get_char_from_queue(obs)
+            if c:
+                if verbose:
+                    sys.stdout.write(c)
+                c = filter_queue_char(c)
+                output.append(c)
+                # Give the mbed under test a way to communicate the end of the test
+                if c in ['\n', '\r']:
+
+                    # Checking for auto-detection information from the test about MUT reset moment
+                    if 'reset_target' not in update_once_flag and "HOST: Reset target..." in line:
+                        # We will update this marker only once to prevent multiple time resets
+                        update_once_flag['reset_target'] = True
+                        start_time = time()
+
+                    # Checking for auto-detection information from the test about timeout
+                    auto_timeout_val = get_auto_property_value('timeout', line)
+                    if 'timeout' not in update_once_flag and auto_timeout_val is not None:
+                        # We will update this marker only once to prevent multiple time resets
+                        update_once_flag['timeout'] = True
+                        duration = int(auto_timeout_val)
+
+                    # Detect mbed assert:
+                    if 'mbed assertation failed: ' in line:
+                        output.append('{{mbed_assert}}')
+                        break
+
+                    # Check for test end
+                    if '{end}' in line:
+                        break
+                    line = ''
+                else:
+                    line += c
+        end_time = time()
+        testcase_duration = end_time - start_time   # Test case duration from reset to {end}
+
+        c = get_char_from_queue(obs)
+
+        if c:
+            if verbose:
+                sys.stdout.write(c)
+            c = filter_queue_char(c)
+            output.append(c)
+
+        if verbose:
+            print "Test::Output::Finish"
+        # Stop test process
+        obs.stop()
+
+        result = get_test_result(output)
+        return (result, "".join(output), testcase_duration, duration)
+
+    def is_peripherals_available(self, target_mcu_name, peripherals=None):
+        """ Checks if specified target should run specific peripheral test case defined in MUTs file
+        """
+        if peripherals is not None:
+            peripherals = set(peripherals)
+        for id, mut in self.muts.iteritems():
+            # Target MCU name check
+            if mut["mcu"] != target_mcu_name:
+                continue
+            # Peripherals check
+            if peripherals is not None:
+                if 'peripherals' not in mut:
+                    continue
+                if not peripherals.issubset(set(mut['peripherals'])):
+                    continue
+            return True
+        return False
+
+    def shape_test_request(self, mcu, image_path, test_id, duration=10):
+        """ Function prepares JSON structure describing test specification
+        """
+        test_spec = {
+            "mcu": mcu,
+            "image": image_path,
+            "duration": duration,
+            "test_id": test_id,
+        }
+        return json.dumps(test_spec)
+
+
+def get_unique_value_from_summary(test_summary, index):
+    """ Gets list of unique target names
+    """
+    result = []
+    for test in test_summary:
+        target_name = test[index]
+        if target_name not in result:
+            result.append(target_name)
+    return sorted(result)
+
+
+def get_unique_value_from_summary_ext(test_summary, index_key, index_val):
+    """ Gets list of unique target names and return dictionary
+    """
+    result = {}
+    for test in test_summary:
+        key = test[index_key]
+        val = test[index_val]
+        if key not in result:
+            result[key] = val
+    return result
+
+
+def show_json_file_format_error(json_spec_filename, line, column):
+    """ Prints JSON broken content
+    """
+    with open(json_spec_filename) as data_file:
+        line_no = 1
+        for json_line in data_file:
+            if line_no + 5 >= line: # Print last few lines before error
+                print 'Line %d:\t'%line_no + json_line, # Prints line
+            if line_no == line:
+                print ' ' * len('Line %d:'%line_no) + '\t', '-' * (column-1) + '^'
+                break
+            line_no += 1
+
+
+def json_format_error_defect_pos(json_error_msg):
+    """ Gets first error line and column in JSON file format.
+        Parsed from exception thrown by json.loads() string
+    """
+    result = None
+    line, column = 0, 0
+    # Line value search
+    line_search = re.search('line [0-9]+', json_error_msg)
+    if line_search is not None:
+        ls = line_search.group().split(' ')
+        if len(ls) == 2:
+            line = int(ls[1])
+            # Column position search
+            column_search = re.search('column [0-9]+', json_error_msg)
+            if column_search is not None:
+                cs = column_search.group().split(' ')
+                if len(cs) == 2:
+                    column = int(cs[1])
+                    result = [line, column]
+    return result
+
+
+def get_json_data_from_file(json_spec_filename, verbose=False):
+    """ Loads from file JSON formatted string to data structure
+    """
+    result = None
+    try:
+        with open(json_spec_filename) as data_file:
+            try:
+                result = json.load(data_file)
+            except ValueError as json_error_msg:
+                result = None
+                print 'JSON file %s parsing failed. Reason: %s' % (json_spec_filename, json_error_msg)
+                # We can print where error occurred inside JSON file if we can parse exception msg
+                json_format_defect_pos = json_format_error_defect_pos(str(json_error_msg))
+                if json_format_defect_pos is not None:
+                    line = json_format_defect_pos[0]
+                    column = json_format_defect_pos[1]
+                    print
+                    show_json_file_format_error(json_spec_filename, line, column)
+
+    except IOError as fileopen_error_msg:
+        print 'JSON file %s not opened. Reason: %s'% (json_spec_filename, fileopen_error_msg)
+        print
+    if verbose and result:
+        pp = pprint.PrettyPrinter(indent=4)
+        pp.pprint(result)
+    return result
+
+
+def print_muts_configuration_from_json(json_data, join_delim=", ", platform_filter=None):
+    """ Prints MUTs configuration passed to test script for verboseness
+    """
+    muts_info_cols = []
+    # We need to check all unique properties for each defined MUT
+    for k in json_data:
+        mut_info = json_data[k]
+        for mut_property in mut_info:
+            if mut_property not in muts_info_cols:
+                muts_info_cols.append(mut_property)
+
+    # Prepare pretty table object to display all MUTs
+    pt_cols = ["index"] + muts_info_cols
+    pt = PrettyTable(pt_cols)
+    for col in pt_cols:
+        pt.align[col] = "l"
+
+    # Add rows to pretty print object
+    for k in json_data:
+        row = [k]
+        mut_info = json_data[k]
+
+        add_row = True
+        if platform_filter and 'mcu' in mut_info:
+            add_row = re.search(platform_filter, mut_info['mcu']) is not None
+        if add_row:
+            for col in muts_info_cols:
+                cell_val = mut_info[col] if col in mut_info else None
+                if type(cell_val) == ListType:
+                    cell_val = join_delim.join(cell_val)
+                row.append(cell_val)
+            pt.add_row(row)
+    return pt.get_string()
+
+
+def print_test_configuration_from_json(json_data, join_delim=", "):
+    """ Prints test specification configuration passed to test script for verboseness
+    """
+    toolchains_info_cols = []
+    # We need to check all toolchains for each device
+    for k in json_data:
+        # k should be 'targets'
+        targets = json_data[k]
+        for target in targets:
+            toolchains = targets[target]
+            for toolchain in toolchains:
+                if toolchain not in toolchains_info_cols:
+                    toolchains_info_cols.append(toolchain)
+
+    # Prepare pretty table object to display test specification
+    pt_cols = ["mcu"] + sorted(toolchains_info_cols)
+    pt = PrettyTable(pt_cols)
+    for col in pt_cols:
+        pt.align[col] = "l"
+
+    # { target : [conflicted toolchains] }
+    toolchain_conflicts = {}
+    toolchain_path_conflicts = []
+    for k in json_data:
+        # k should be 'targets'
+        targets = json_data[k]
+        for target in targets:
+            target_supported_toolchains = get_target_supported_toolchains(target)
+            if not target_supported_toolchains:
+                target_supported_toolchains = []
+            target_name = target if target in TARGET_MAP else "%s*"% target
+            row = [target_name]
+            toolchains = targets[target]
+
+            for toolchain in sorted(toolchains_info_cols):
+                # Check for conflicts: target vs toolchain
+                conflict = False
+                conflict_path = False
+                if toolchain in toolchains:
+                    if toolchain not in target_supported_toolchains:
+                        conflict = True
+                        if target not in toolchain_conflicts:
+                            toolchain_conflicts[target] = []
+                        toolchain_conflicts[target].append(toolchain)
+                # Add marker inside table about target usage / conflict
+                cell_val = 'Yes' if toolchain in toolchains else '-'
+                if conflict:
+                    cell_val += '*'
+                # Check for conflicts: toolchain vs toolchain path
+                if toolchain in TOOLCHAIN_PATHS:
+                    toolchain_path = TOOLCHAIN_PATHS[toolchain]
+                    if not os.path.isdir(toolchain_path):
+                        conflict_path = True
+                        if toolchain not in toolchain_path_conflicts:
+                            toolchain_path_conflicts.append(toolchain)
+                if conflict_path:
+                    cell_val += '#'
+                row.append(cell_val)
+            pt.add_row(row)
+
+    # generate result string
+    result = pt.get_string()    # Test specification table
+    if toolchain_conflicts or toolchain_path_conflicts:
+        result += "\n"
+        result += "Toolchain conflicts:\n"
+        for target in toolchain_conflicts:
+            if target not in TARGET_MAP:
+                result += "\t* Target %s unknown\n"% (target)
+            conflict_target_list = join_delim.join(toolchain_conflicts[target])
+            sufix = 's' if len(toolchain_conflicts[target]) > 1 else ''
+            result += "\t* Target %s does not support %s toolchain%s\n"% (target, conflict_target_list, sufix)
+
+        for toolchain in toolchain_path_conflicts:
+        # Let's check toolchain configuration
+            if toolchain in TOOLCHAIN_PATHS:
+                toolchain_path = TOOLCHAIN_PATHS[toolchain]
+                if not os.path.isdir(toolchain_path):
+                    result += "\t# Toolchain %s path not found: %s\n"% (toolchain, toolchain_path)
+    return result
+
+
+def get_avail_tests_summary_table(cols=None, result_summary=True, join_delim=',',platform_filter=None):
+    """ Generates table summary with all test cases and additional test cases
+        information using pretty print functionality. Allows test suite user to
+        see test cases
+    """
+    # get all unique test ID prefixes
+    unique_test_id = []
+    for test in TESTS:
+        split = test['id'].split('_')[:-1]
+        test_id_prefix = '_'.join(split)
+        if test_id_prefix not in unique_test_id:
+            unique_test_id.append(test_id_prefix)
+    unique_test_id.sort()
+    counter_dict_test_id_types = dict((t, 0) for t in unique_test_id)
+    counter_dict_test_id_types_all = dict((t, 0) for t in unique_test_id)
+
+    test_properties = ['id',
+                       'automated',
+                       'description',
+                       'peripherals',
+                       'host_test',
+                       'duration'] if cols is None else cols
+
+    # All tests status table print
+    pt = PrettyTable(test_properties)
+    for col in test_properties:
+        pt.align[col] = "l"
+    pt.align['duration'] = "r"
+
+    counter_all = 0
+    counter_automated = 0
+    pt.padding_width = 1 # One space between column edges and contents (default)
+
+    for test_id in sorted(TEST_MAP.keys()):
+        if platform_filter is not None:
+            # FIlter out platforms using regex
+            if re.search(platform_filter, test_id) is None:
+                continue
+        row = []
+        test = TEST_MAP[test_id]
+        split = test_id.split('_')[:-1]
+        test_id_prefix = '_'.join(split)
+
+        for col in test_properties:
+            col_value = test[col]
+            if type(test[col]) == ListType:
+                col_value = join_delim.join(test[col])
+            elif test[col] == None:
+                col_value = "-"
+
+            row.append(col_value)
+        if test['automated'] == True:
+            counter_dict_test_id_types[test_id_prefix] += 1
+            counter_automated += 1
+        pt.add_row(row)
+        # Update counters
+        counter_all += 1
+        counter_dict_test_id_types_all[test_id_prefix] += 1
+    result = pt.get_string()
+    result += "\n\n"
+
+    if result_summary and not platform_filter:
+        # Automation result summary
+        test_id_cols = ['automated', 'all', 'percent [%]', 'progress']
+        pt = PrettyTable(test_id_cols)
+        pt.align['automated'] = "r"
+        pt.align['all'] = "r"
+        pt.align['percent [%]'] = "r"
+
+        percent_progress = round(100.0 * counter_automated / float(counter_all), 1)
+        str_progress = progress_bar(percent_progress, 75)
+        pt.add_row([counter_automated, counter_all, percent_progress, str_progress])
+        result += "Automation coverage:\n"
+        result += pt.get_string()
+        result += "\n\n"
+
+        # Test automation coverage table print
+        test_id_cols = ['id', 'automated', 'all', 'percent [%]', 'progress']
+        pt = PrettyTable(test_id_cols)
+        pt.align['id'] = "l"
+        pt.align['automated'] = "r"
+        pt.align['all'] = "r"
+        pt.align['percent [%]'] = "r"
+        for unique_id in unique_test_id:
+            # print "\t\t%s: %d / %d" % (unique_id, counter_dict_test_id_types[unique_id], counter_dict_test_id_types_all[unique_id])
+            percent_progress = round(100.0 * counter_dict_test_id_types[unique_id] / float(counter_dict_test_id_types_all[unique_id]), 1)
+            str_progress = progress_bar(percent_progress, 75)
+            row = [unique_id,
+                   counter_dict_test_id_types[unique_id],
+                   counter_dict_test_id_types_all[unique_id],
+                   percent_progress,
+                   "[" + str_progress + "]"]
+            pt.add_row(row)
+        result += "Test automation coverage:\n"
+        result += pt.get_string()
+        result += "\n\n"
+    return result
+
+
+def progress_bar(percent_progress, saturation=0):
+    """ This function creates progress bar with optional simple saturation mark
+    """
+    step = int(percent_progress / 2)    # Scale by to (scale: 1 - 50)
+    str_progress = '#' * step + '.' * int(50 - step)
+    c = '!' if str_progress[38] == '.' else '|'
+    if saturation > 0:
+        saturation = saturation / 2
+        str_progress = str_progress[:saturation] + c + str_progress[saturation:]
+    return str_progress
+
+
+def singletest_in_cli_mode(single_test):
+    """ Runs SingleTestRunner object in CLI (Command line interface) mode
+
+        @return returns success code (0 == success) for building and running tests
+    """
+    start = time()
+    # Execute tests depending on options and filter applied
+    test_summary, shuffle_seed, test_summary_ext, test_suite_properties_ext, build_report, build_properties = single_test.execute()
+    elapsed_time = time() - start
+
+    # Human readable summary
+    if not single_test.opts_suppress_summary:
+        # prints well-formed summary with results (SQL table like)
+        print single_test.generate_test_summary(test_summary, shuffle_seed)
+    if single_test.opts_test_x_toolchain_summary:
+        # prints well-formed summary with results (SQL table like)
+        # table shows text x toolchain test result matrix
+        print single_test.generate_test_summary_by_target(test_summary, shuffle_seed)
+
+    print "Completed in %.2f sec"% (elapsed_time)
+    print
+    # Write summary of the builds
+
+    print_report_exporter = ReportExporter(ResultExporterType.PRINT, package="build")
+    status = print_report_exporter.report(build_report)
+
+    # Store extra reports in files
+    if single_test.opts_report_html_file_name:
+        # Export results in form of HTML report to separate file
+        report_exporter = ReportExporter(ResultExporterType.HTML)
+        report_exporter.report_to_file(test_summary_ext, single_test.opts_report_html_file_name, test_suite_properties=test_suite_properties_ext)
+    if single_test.opts_report_junit_file_name:
+        # Export results in form of JUnit XML report to separate file
+        report_exporter = ReportExporter(ResultExporterType.JUNIT)
+        report_exporter.report_to_file(test_summary_ext, single_test.opts_report_junit_file_name, test_suite_properties=test_suite_properties_ext)
+    if single_test.opts_report_text_file_name:
+        # Export results in form of a text file
+        report_exporter = ReportExporter(ResultExporterType.TEXT)
+        report_exporter.report_to_file(test_summary_ext, single_test.opts_report_text_file_name, test_suite_properties=test_suite_properties_ext)
+    if single_test.opts_report_build_file_name:
+        # Export build results as html report to sparate file
+        report_exporter = ReportExporter(ResultExporterType.JUNIT, package="build")
+        report_exporter.report_to_file(build_report, single_test.opts_report_build_file_name, test_suite_properties=build_properties)
+
+    # Returns True if no build failures of the test projects or their dependencies
+    return status
+
+class TestLogger():
+    """ Super-class for logging and printing ongoing events for test suite pass
+    """
+    def __init__(self, store_log=True):
+        """ We can control if logger actually stores log in memory
+            or just handled all log entries immediately
+        """
+        self.log = []
+        self.log_to_file = False
+        self.log_file_name = None
+        self.store_log = store_log
+
+        self.LogType = construct_enum(INFO='Info',
+                                      WARN='Warning',
+                                      NOTIF='Notification',
+                                      ERROR='Error',
+                                      EXCEPT='Exception')
+
+        self.LogToFileAttr = construct_enum(CREATE=1,    # Create or overwrite existing log file
+                                            APPEND=2)    # Append to existing log file
+
+    def log_line(self, LogType, log_line, timestamp=True, line_delim='\n'):
+        """ Log one line of text
+        """
+        log_timestamp = time()
+        log_entry = {'log_type' : LogType,
+                     'log_timestamp' : log_timestamp,
+                     'log_line' : log_line,
+                     '_future' : None
+        }
+        # Store log in memory
+        if self.store_log:
+            self.log.append(log_entry)
+        return log_entry
+
+
+class CLITestLogger(TestLogger):
+    """ Logger used with CLI (Command line interface) test suite. Logs on screen and to file if needed
+    """
+    def __init__(self, store_log=True, file_name=None):
+        TestLogger.__init__(self)
+        self.log_file_name = file_name
+        #self.TIMESTAMP_FORMAT = '%y-%m-%d %H:%M:%S' # Full date and time
+        self.TIMESTAMP_FORMAT = '%H:%M:%S' # Time only
+
+    def log_print(self, log_entry, timestamp=True):
+        """ Prints on screen formatted log entry
+        """
+        ts = log_entry['log_timestamp']
+        timestamp_str = datetime.datetime.fromtimestamp(ts).strftime("[%s] "% self.TIMESTAMP_FORMAT) if timestamp else ''
+        log_line_str = "%(log_type)s: %(log_line)s"% (log_entry)
+        return timestamp_str + log_line_str
+
+    def log_line(self, LogType, log_line, timestamp=True, line_delim='\n'):
+        """ Logs line, if log file output was specified log line will be appended
+            at the end of log file
+        """
+        log_entry = TestLogger.log_line(self, LogType, log_line)
+        log_line_str = self.log_print(log_entry, timestamp)
+        if self.log_file_name is not None:
+            try:
+                with open(self.log_file_name, 'a') as f:
+                    f.write(log_line_str + line_delim)
+            except IOError:
+                pass
+        return log_line_str
+
+
+def factory_db_logger(db_url):
+    """ Factory database driver depending on database type supplied in database connection string db_url
+    """
+    if db_url is not None:
+        from tools.test_mysql import MySQLDBAccess
+        connection_info = BaseDBAccess().parse_db_connection_string(db_url)
+        if connection_info is not None:
+            (db_type, username, password, host, db_name) = BaseDBAccess().parse_db_connection_string(db_url)
+            if db_type == 'mysql':
+                return MySQLDBAccess()
+    return None
+
+
+def detect_database_verbose(db_url):
+    """ uses verbose mode (prints) database detection sequence to check it database connection string is valid
+    """
+    result = BaseDBAccess().parse_db_connection_string(db_url)
+    if result is not None:
+        # Parsing passed
+        (db_type, username, password, host, db_name) = result
+        #print "DB type '%s', user name '%s', password '%s', host '%s', db name '%s'"% result
+        # Let's try to connect
+        db_ = factory_db_logger(db_url)
+        if db_ is not None:
+            print "Connecting to database '%s'..."% db_url,
+            db_.connect(host, username, password, db_name)
+            if db_.is_connected():
+                print "ok"
+                print "Detecting database..."
+                print db_.detect_database(verbose=True)
+                print "Disconnecting...",
+                db_.disconnect()
+                print "done"
+        else:
+            print "Database type '%s' unknown"% db_type
+    else:
+        print "Parse error: '%s' - DB Url error"% (db_url)
+
+
+def get_module_avail(module_name):
+    """ This function returns True if module_name is already imported module
+    """
+    return module_name in sys.modules.keys()
+
+def get_autodetected_MUTS_list(platform_name_filter=None):
+    oldError = None
+    if os.name == 'nt':
+        # Disable Windows error box temporarily
+        oldError = ctypes.windll.kernel32.SetErrorMode(1) #note that SEM_FAILCRITICALERRORS = 1
+
+    mbeds = mbed_lstools.create()
+    detect_muts_list = mbeds.list_mbeds()
+
+    if os.name == 'nt':
+        ctypes.windll.kernel32.SetErrorMode(oldError)
+
+    return get_autodetected_MUTS(detect_muts_list, platform_name_filter=platform_name_filter)
+
+def get_autodetected_MUTS(mbeds_list, platform_name_filter=None):
+    """ Function detects all connected to host mbed-enabled devices and generates artificial MUTS file.
+        If function fails to auto-detect devices it will return empty dictionary.
+
+        if get_module_avail('mbed_lstools'):
+            mbeds = mbed_lstools.create()
+            mbeds_list = mbeds.list_mbeds()
+
+        @param mbeds_list list of mbeds captured from mbed_lstools
+        @param platform_name You can filter 'platform_name' with list of filtered targets from 'platform_name_filter'
+    """
+    result = {}   # Should be in muts_all.json format
+    # Align mbeds_list from mbed_lstools to MUT file format (JSON dictionary with muts)
+    # mbeds_list = [{'platform_name': 'NUCLEO_F302R8', 'mount_point': 'E:', 'target_id': '07050200623B61125D5EF72A', 'serial_port': u'COM34'}]
+    index = 1
+    for mut in mbeds_list:
+        # Filter the MUTS if a filter is specified
+
+        if platform_name_filter and not mut['platform_name'] in platform_name_filter:
+            continue
+
+        # For mcu_unique - we are assigning 'platform_name_unique' value from  mbedls output (if its existing)
+        # if not we  are creating our own unique value (last few chars from platform's target_id).
+        m = {'mcu': mut['platform_name'],
+             'mcu_unique' : mut['platform_name_unique'] if 'platform_name_unique' in mut else "%s[%s]" % (mut['platform_name'], mut['target_id'][-4:]),
+             'port': mut['serial_port'],
+             'disk': mut['mount_point'],
+             'peripherals': []     # No peripheral detection
+             }
+        if index not in result:
+            result[index] = {}
+        result[index] = m
+        index += 1
+    return result
+
+
+def get_autodetected_TEST_SPEC(mbeds_list,
+                               use_default_toolchain=True,
+                               use_supported_toolchains=False,
+                               toolchain_filter=None,
+                               platform_name_filter=None):
+    """ Function detects all connected to host mbed-enabled devices and generates artificial test_spec file.
+        If function fails to auto-detect devices it will return empty 'targets' test_spec description.
+
+        use_default_toolchain - if True add default toolchain to test_spec
+        use_supported_toolchains - if True add all supported toolchains to test_spec
+        toolchain_filter - if [...list of toolchains...] add from all toolchains only those in filter to test_spec
+    """
+    result = {'targets': {} }
+
+    for mut in mbeds_list:
+        mcu = mut['mcu']
+        if platform_name_filter is None or (platform_name_filter and mut['mcu'] in platform_name_filter):
+            if mcu in TARGET_MAP:
+                default_toolchain = TARGET_MAP[mcu].default_toolchain
+                supported_toolchains = TARGET_MAP[mcu].supported_toolchains
+
+                # Decide which toolchains should be added to test specification toolchain pool for each target
+                toolchains = []
+                if use_default_toolchain:
+                    toolchains.append(default_toolchain)
+                if use_supported_toolchains:
+                    toolchains += supported_toolchains
+                if toolchain_filter is not None:
+                    all_toolchains = supported_toolchains + [default_toolchain]
+                    for toolchain in toolchain_filter:
+                        if toolchain in all_toolchains:
+                            toolchains.append(toolchain)
+
+                result['targets'][mcu] = list(set(toolchains))
+    return result
+
+
+def get_default_test_options_parser():
+    """ Get common test script options used by CLI, web services etc.
+    """
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-i', '--tests',
+                        dest='test_spec_filename',
+                        metavar="FILE",
+                        type=argparse_filestring_type,
+                        help='Points to file with test specification')
+
+    parser.add_argument('-M', '--MUTS',
+                        dest='muts_spec_filename',
+                        metavar="FILE",
+                        type=argparse_filestring_type,
+                        help='Points to file with MUTs specification (overwrites settings.py and private_settings.py)')
+
+    parser.add_argument("-j", "--jobs",
+                        dest='jobs',
+                        metavar="NUMBER",
+                        type=int,
+                        help="Define number of compilation jobs. Default value is 1")
+
+    if get_module_avail('mbed_lstools'):
+        # Additional features available when mbed_lstools is installed on host and imported
+        # mbed_lstools allow users to detect connected to host mbed-enabled devices
+        parser.add_argument('--auto',
+                            dest='auto_detect',
+                            action="store_true",
+                            help='Use mbed-ls module to detect all connected mbed devices')
+
+        toolchain_list = list(TOOLCHAINS) + ["DEFAULT", "ALL"]
+        parser.add_argument('--tc',
+                            dest='toolchains_filter',
+                        type=argparse_many(argparse_uppercase_type(toolchain_list, "toolchains")),
+                            help="Toolchain filter for --auto argument. Use toolchains names separated by comma, 'default' or 'all' to select toolchains")
+
+        test_scopes = ','.join(["'%s'" % n for n in get_available_oper_test_scopes()])
+        parser.add_argument('--oper',
+                            dest='operability_checks',
+                            type=argparse_lowercase_type(get_available_oper_test_scopes(), "scopes"),
+                            help='Perform interoperability tests between host and connected mbed devices. Available test scopes are: %s' % test_scopes)
+
+    parser.add_argument('--clean',
+                        dest='clean',
+                        action="store_true",
+                        help='Clean the build directory')
+
+    parser.add_argument('-P', '--only-peripherals',
+                        dest='test_only_peripheral',
+                        default=False,
+                        action="store_true",
+                        help='Test only peripheral declared for MUT and skip common tests')
+
+    parser.add_argument("--profile", dest="profile", action="append",
+                        type=argparse_filestring_type,
+                        default=[])
+
+    parser.add_argument('-C', '--only-commons',
+                        dest='test_only_common',
+                        default=False,
+                        action="store_true",
+                        help='Test only board internals. Skip perpherials tests and perform common tests')
+
+    parser.add_argument('-n', '--test-by-names',
+                        dest='test_by_names',
+                        type=argparse_many(str),
+                        help='Runs only test enumerated it this switch. Use comma to separate test case names')
+
+    parser.add_argument('-p', '--peripheral-by-names',
+                      dest='peripheral_by_names',
+                      type=argparse_many(str),
+                      help='Forces discovery of particular peripherals. Use comma to separate peripheral names')
+
+    copy_methods = host_tests_plugins.get_plugin_caps('CopyMethod')
+    copy_methods_str = "Plugin support: " + ', '.join(copy_methods)
+
+    parser.add_argument('-c', '--copy-method',
+                        dest='copy_method',
+                        type=argparse_uppercase_type(copy_methods, "flash method"),
+                        help="Select binary copy (flash) method. Default is Python's shutil.copy() method. %s"% copy_methods_str)
+
+    reset_methods = host_tests_plugins.get_plugin_caps('ResetMethod')
+    reset_methods_str = "Plugin support: " + ', '.join(reset_methods)
+
+    parser.add_argument('-r', '--reset-type',
+                        dest='mut_reset_type',
+                        default=None,
+                        type=argparse_uppercase_type(reset_methods, "reset method"),
+                        help='Extra reset method used to reset MUT by host test script. %s'% reset_methods_str)
+
+    parser.add_argument('-g', '--goanna-for-tests',
+                        dest='goanna_for_tests',
+                        action="store_true",
+                        help='Run Goanna static analyse tool for tests. (Project will be rebuilded)')
+
+    parser.add_argument('-G', '--goanna-for-sdk',
+                        dest='goanna_for_mbed_sdk',
+                        action="store_true",
+                        help='Run Goanna static analyse tool for mbed SDK (Project will be rebuilded)')
+
+    parser.add_argument('-s', '--suppress-summary',
+                        dest='suppress_summary',
+                        default=False,
+                        action="store_true",
+                        help='Suppresses display of wellformatted table with test results')
+
+    parser.add_argument('-t', '--test-summary',
+                        dest='test_x_toolchain_summary',
+                        default=False,
+                        action="store_true",
+                        help='Displays wellformatted table with test x toolchain test result per target')
+
+    parser.add_argument('-A', '--test-automation-report',
+                        dest='test_automation_report',
+                        default=False,
+                        action="store_true",
+                        help='Prints information about all tests and exits')
+
+    parser.add_argument('-R', '--test-case-report',
+                        dest='test_case_report',
+                        default=False,
+                        action="store_true",
+                        help='Prints information about all test cases and exits')
+
+    parser.add_argument("-S", "--supported-toolchains",
+                        action="store_true",
+                        dest="supported_toolchains",
+                        default=False,
+                        help="Displays supported matrix of MCUs and toolchains")
+
+    parser.add_argument("-O", "--only-build",
+                        action="store_true",
+                        dest="only_build_tests",
+                        default=False,
+                        help="Only build tests, skips actual test procedures (flashing etc.)")
+
+    parser.add_argument('--parallel',
+                        dest='parallel_test_exec',
+                        default=False,
+                        action="store_true",
+                        help='Experimental, you execute test runners for connected to your host MUTs in parallel (speeds up test result collection)')
+
+    parser.add_argument('--config',
+                        dest='verbose_test_configuration_only',
+                        default=False,
+                        action="store_true",
+                        help='Displays full test specification and MUTs configration and exits')
+
+    parser.add_argument('--loops',
+                        dest='test_loops_list',
+                        type=argparse_many(str),
+                        help='Set no. of loops per test. Format: TEST_1=1,TEST_2=2,TEST_3=3')
+
+    parser.add_argument('--global-loops',
+                        dest='test_global_loops_value',
+                        type=int,
+                        help='Set global number of test loops per test. Default value is set 1')
+
+    parser.add_argument('--consolidate-waterfall',
+                        dest='consolidate_waterfall_test',
+                        default=False,
+                        action="store_true",
+                        help='Used with --waterfall argument. Adds only one test to report reflecting outcome of waterfall test.')
+
+    parser.add_argument('-W', '--waterfall',
+                        dest='waterfall_test',
+                        default=False,
+                        action="store_true",
+                        help='Used with --loops or --global-loops arguments. Tests until OK result occurs and assumes test passed')
+
+    parser.add_argument('-N', '--firmware-name',
+                        dest='firmware_global_name',
+                        help='Set global name for all produced projects. Note, proper file extension will be added by buid scripts')
+
+    parser.add_argument('-u', '--shuffle',
+                        dest='shuffle_test_order',
+                        default=False,
+                        action="store_true",
+                        help='Shuffles test execution order')
+
+    parser.add_argument('--shuffle-seed',
+                        dest='shuffle_test_seed',
+                        default=None,
+                        help='Shuffle seed (If you want to reproduce your shuffle order please use seed provided in test summary)')
+
+    parser.add_argument('-f', '--filter',
+                        dest='general_filter_regex',
+                        type=argparse_many(str),
+                        default=None,
+                        help='For some commands you can use filter to filter out results')
+
+    parser.add_argument('--inc-timeout',
+                        dest='extend_test_timeout',
+                        metavar="NUMBER",
+                        type=int,
+                        help='You can increase global timeout for each test by specifying additional test timeout in seconds')
+
+    parser.add_argument('--db',
+                        dest='db_url',
+                        help='This specifies what database test suite uses to store its state. To pass DB connection info use database connection string. Example: \'mysql://username:password@127.0.0.1/db_name\'')
+
+    parser.add_argument('-l', '--log',
+                        dest='log_file_name',
+                        help='Log events to external file (note not all console entries may be visible in log file)')
+
+    parser.add_argument('--report-html',
+                        dest='report_html_file_name',
+                        help='You can log test suite results in form of HTML report')
+
+    parser.add_argument('--report-junit',
+                        dest='report_junit_file_name',
+                        help='You can log test suite results in form of JUnit compliant XML report')
+
+    parser.add_argument("--report-build",
+                        dest="report_build_file_name",
+                        help="Output the build results to a junit xml file")
+
+    parser.add_argument("--report-text",
+                        dest="report_text_file_name",
+                        help="Output the build results to a text file")
+
+    parser.add_argument('--verbose-skipped',
+                        dest='verbose_skipped_tests',
+                        default=False,
+                        action="store_true",
+                        help='Prints some extra information about skipped tests')
+
+    parser.add_argument('-V', '--verbose-test-result',
+                        dest='verbose_test_result_only',
+                        default=False,
+                        action="store_true",
+                        help='Prints test serial output')
+
+    parser.add_argument('-v', '--verbose',
+                        dest='verbose',
+                        default=False,
+                        action="store_true",
+                        help='Verbose mode (prints some extra information)')
+
+    parser.add_argument('--version',
+                        dest='version',
+                        default=False,
+                        action="store_true",
+                        help='Prints script version and exits')
+
+    parser.add_argument('--stats-depth',
+                        dest='stats_depth',
+                        default=2,
+                        type=int,
+                        help="Depth level for static memory report")
+    return parser
+
+def test_path_to_name(path, base):
+    """Change all slashes in a path into hyphens
+    This creates a unique cross-platform test name based on the path
+    This can eventually be overriden by a to-be-determined meta-data mechanism"""
+    name_parts = []
+    head, tail = os.path.split(relpath(path,base))
+    while (tail and tail != "."):
+        name_parts.insert(0, tail)
+        head, tail = os.path.split(head)
+
+    return "-".join(name_parts).lower()
+
+def get_test_config(config_name, target_name):
+    """Finds the path to a test configuration file
+    config_name: path to a custom configuration file OR mbed OS interface "ethernet, wifi_odin, etc"
+    target_name: name of target to determing if mbed OS interface given is valid
+    returns path to config, boolean of whether it is a module or mbed OS interface
+    """
+    # If they passed in a full path
+    if exists(config_name):
+        # This is a module config
+        return config_name
+    # Otherwise find the path to configuration file based on mbed OS interface
+    return TestConfig.get_config_path(config_name, target_name)
+
+def find_tests(base_dir, target_name, toolchain_name, app_config=None):
+    """ Finds all tests in a directory recursively
+    base_dir: path to the directory to scan for tests (ex. 'path/to/project')
+    target_name: name of the target to use for scanning (ex. 'K64F')
+    toolchain_name: name of the toolchain to use for scanning (ex. 'GCC_ARM')
+    options: Compile options to pass to the toolchain (ex. ['debug-info'])
+    app_config - location of a chosen mbed_app.json file
+    """
+
+    tests = {}
+
+    # Prepare the toolchain
+    toolchain = prepare_toolchain([base_dir], None, target_name, toolchain_name,
+                                  silent=True, app_config=app_config)
+
+    # Scan the directory for paths to probe for 'TESTS' folders
+    base_resources = scan_resources([base_dir], toolchain)
+
+    dirs = base_resources.inc_dirs
+    for directory in dirs:
+        subdirs = os.listdir(directory)
+
+        # If the directory contains a subdirectory called 'TESTS', scan it for test cases
+        if 'TESTS' in subdirs:
+            walk_base_dir = join(directory, 'TESTS')
+            test_resources = toolchain.scan_resources(walk_base_dir, base_path=base_dir)
+
+            # Loop through all subdirectories
+            for d in test_resources.inc_dirs:
+
+                # If the test case folder is not called 'host_tests' and it is
+                # located two folders down from the main 'TESTS' folder (ex. TESTS/testgroup/testcase)
+                # then add it to the tests
+                path_depth = get_path_depth(relpath(d, walk_base_dir))
+                if path_depth == 2:
+                    test_group_directory_path, test_case_directory = os.path.split(d)
+                    test_group_directory = os.path.basename(test_group_directory_path)
+
+                    # Check to make sure discoverd folder is not in a host test directory
+                    if test_case_directory != 'host_tests' and test_group_directory != 'host_tests':
+                        test_name = test_path_to_name(d, base_dir)
+                        tests[test_name] = d
+
+    return tests
+
+def print_tests(tests, format="list", sort=True):
+    """Given a dictionary of tests (as returned from "find_tests"), print them
+    in the specified format"""
+    if format == "list":
+        for test_name in sorted(tests.keys()):
+            test_path = tests[test_name]
+            print "Test Case:"
+            print "    Name: %s" % test_name
+            print "    Path: %s" % test_path
+    elif format == "json":
+        print json.dumps(tests, indent=2)
+    else:
+        print "Unknown format '%s'" % format
+        sys.exit(1)
+
+def norm_relative_path(path, start):
+    """This function will create a normalized, relative path. It mimics the
+    python os.path.relpath function, but also normalizes a Windows-syle path
+    that use backslashes to a Unix style path that uses forward slashes."""
+    path = os.path.normpath(path)
+    path = os.path.relpath(path, start)
+    path = path.replace("\\", "/")
+    return path
+
+
+def build_test_worker(*args, **kwargs):
+    """This is a worker function for the parallel building of tests. The `args`
+    and `kwargs` are passed directly to `build_project`. It returns a dictionary
+    with the following structure:
+
+    {
+        'result': `True` if no exceptions were thrown, `False` otherwise
+        'reason': Instance of exception that was thrown on failure
+        'bin_file': Path to the created binary if `build_project` was
+                    successful. Not present otherwise
+        'kwargs': The keyword arguments that were passed to `build_project`.
+                  This includes arguments that were modified (ex. report)
+    }
+    """
+    bin_file = None
+    ret = {
+        'result': False,
+        'args': args,
+        'kwargs': kwargs
+    }
+
+    # Use parent TOOLCHAIN_PATHS variable
+    for key, value in kwargs['toolchain_paths'].iteritems():
+        TOOLCHAIN_PATHS[key] = value
+
+    del kwargs['toolchain_paths']
+
+    try:
+        bin_file = build_project(*args, **kwargs)
+        ret['result'] = True
+        ret['bin_file'] = bin_file
+        ret['kwargs'] = kwargs
+
+    except NotSupportedException, e:
+        ret['reason'] = e
+    except ToolException, e:
+        ret['reason'] = e
+    except KeyboardInterrupt, e:
+        ret['reason'] = e
+    except:
+        # Print unhandled exceptions here
+        import traceback
+        traceback.print_exc(file=sys.stdout)
+
+    return ret
+
+
+def build_tests(tests, base_source_paths, build_path, target, toolchain_name,
+                clean=False, notify=None, verbose=False, jobs=1, macros=None,
+                silent=False, report=None, properties=None,
+                continue_on_build_fail=False, app_config=None,
+                build_profile=None, stats_depth=None):
+    """Given the data structure from 'find_tests' and the typical build parameters,
+    build all the tests
+
+    Returns a tuple of the build result (True or False) followed by the test
+    build data structure"""
+
+    execution_directory = "."
+    base_path = norm_relative_path(build_path, execution_directory)
+
+    target_name = target if isinstance(target, str) else target.name
+    cfg, _, _ = get_config(base_source_paths, target_name, toolchain_name)
+
+    baud_rate = 9600
+    if 'platform.stdio-baud-rate' in cfg:
+        baud_rate = cfg['platform.stdio-baud-rate'].value
+
+    test_build = {
+        "platform": target_name,
+        "toolchain": toolchain_name,
+        "base_path": base_path,
+        "baud_rate": baud_rate,
+        "binary_type": "bootable",
+        "tests": {}
+    }
+
+    result = True
+
+    jobs_count = int(jobs if jobs else cpu_count())
+    p = Pool(processes=jobs_count)
+    results = []
+    for test_name, test_path in tests.iteritems():
+        test_build_path = os.path.join(build_path, test_path)
+        src_path = base_source_paths + [test_path]
+        bin_file = None
+        test_case_folder_name = os.path.basename(test_path)
+
+        args = (src_path, test_build_path, target, toolchain_name)
+        kwargs = {
+            'jobs': 1,
+            'clean': clean,
+            'macros': macros,
+            'name': test_case_folder_name,
+            'project_id': test_name,
+            'report': report,
+            'properties': properties,
+            'verbose': verbose,
+            'app_config': app_config,
+            'build_profile': build_profile,
+            'silent': True,
+            'toolchain_paths': TOOLCHAIN_PATHS,
+            'stats_depth': stats_depth
+        }
+
+        results.append(p.apply_async(build_test_worker, args, kwargs))
+
+    p.close()
+    result = True
+    itr = 0
+    while len(results):
+        itr += 1
+        if itr > 360000:
+            p.terminate()
+            p.join()
+            raise ToolException("Compile did not finish in 10 minutes")
+        else:
+            sleep(0.01)
+            pending = 0
+            for r in results:
+                if r.ready() is True:
+                    try:
+                        worker_result = r.get()
+                        results.remove(r)
+
+                        # Take report from the kwargs and merge it into existing report
+                        if report:
+                            report_entry = worker_result['kwargs']['report'][target_name][toolchain_name]
+                            for test_key in report_entry.keys():
+                                report[target_name][toolchain_name][test_key] = report_entry[test_key]
+
+                        # Set the overall result to a failure if a build failure occurred
+                        if ('reason' in worker_result and
+                            not worker_result['reason'] and
+                            not isinstance(worker_result['reason'], NotSupportedException)):
+                            result = False
+                            break
+
+                        # Adding binary path to test build result
+                        if ('result' in worker_result and
+                            worker_result['result'] and
+                            'bin_file' in worker_result):
+                            bin_file = norm_relative_path(worker_result['bin_file'], execution_directory)
+
+                            test_build['tests'][worker_result['kwargs']['project_id']] = {
+                                "binaries": [
+                                    {
+                                        "path": bin_file
+                                    }
+                                ]
+                            }
+
+                            test_key = worker_result['kwargs']['project_id'].upper()
+                            if report:
+                                print report[target_name][toolchain_name][test_key][0][0]['output'].rstrip()
+                            print 'Image: %s\n' % bin_file
+
+                    except:
+                        if p._taskqueue.queue:
+                            p._taskqueue.queue.clear()
+                            sleep(0.5)
+                        p.terminate()
+                        p.join()
+                        raise
+                else:
+                    pending += 1
+                    if pending >= jobs_count:
+                        break
+
+            # Break as soon as possible if there is a failure and we are not
+            # continuing on build failures
+            if not result and not continue_on_build_fail:
+                if p._taskqueue.queue:
+                    p._taskqueue.queue.clear()
+                    sleep(0.5)
+                p.terminate()
+                break
+
+    p.join()
+
+    test_builds = {}
+    test_builds["%s-%s" % (target_name, toolchain_name)] = test_build
+
+    return result, test_builds
+
+
+def test_spec_from_test_builds(test_builds):
+    return {
+        "builds": test_builds
+    }
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/EthernetInterface.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/EthernetInterface.json
new file mode 100755
index 0000000..69bbac0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/EthernetInterface.json
@@ -0,0 +1,27 @@
+{
+    "config": {
+        "header-file": {
+            "help" : "String for including your driver header file",
+            "value" : "\"EthernetInterface.h\""
+        },
+        "object-construction" : {
+            "value" : "new EthernetInterface()"
+        },
+        "connect-statement" : {
+            "help" : "Must use 'net' variable name",
+            "value" : "((EthernetInterface *)net)->connect()"
+        },
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"195.34.89.241\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "tcp-echo-prefix" : {
+            "help" : "Some servers send a prefix before echoed message",
+            "value" : "\"u-blox AG TCP/UDP test service\\n\""
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/OdinInterface.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/OdinInterface.json
new file mode 100755
index 0000000..3ebac83
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/OdinInterface.json
@@ -0,0 +1,27 @@
+{
+    "config": {
+        "header-file": {
+            "help" : "String for including your driver header file",
+            "value" : "\"OdinWiFiInterface.h\""
+        },
+        "object-construction" : {
+            "value" : "new OdinWiFiInterface()"
+        },
+        "connect-statement" : {
+            "help" : "Must use 'net' variable name",
+            "value" : "((OdinWiFiInterface *)net)->connect(WIFI_SSID, WIFI_PASSWORD)"
+        },
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"195.34.89.241\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "tcp-echo-prefix" : {
+            "help" : "Some servers send a prefix before echoed message",
+            "value" : "\"u-blox AG TCP/UDP test service\\n\""
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/Odin_EthernetInterface.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/Odin_EthernetInterface.json
new file mode 100755
index 0000000..24f48e2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/Odin_EthernetInterface.json
@@ -0,0 +1,32 @@
+{
+    "config": {
+        "header-file": {
+            "help" : "String for including your driver header file",
+            "value" : "\"EthernetInterface.h\""
+        },
+        "object-construction" : {
+            "value" : "new EthernetInterface()"
+        },
+        "connect-statement" : {
+            "help" : "Must use 'net' variable name",
+            "value" : "((EthernetInterface *)net)->connect()"
+        },
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"195.34.89.241\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "tcp-echo-prefix" : {
+            "help" : "Some servers send a prefix before echoed message",
+            "value" : "\"u-blox AG TCP/UDP test service\\n\""
+        }
+    },
+     "target_overrides": {
+         "UBLOX_EVK_ODIN_W2": {
+            "target.device_has_remove": ["EMAC"]
+        }
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/__init__.py
new file mode 100755
index 0000000..85ea5c9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/__init__.py
@@ -0,0 +1,35 @@
+from os.path import dirname, abspath, join
+
+from tools.utils import json_file_to_dict
+
+CONFIG_DIR = dirname(abspath(__file__))
+CONFIG_MAP = json_file_to_dict(join(CONFIG_DIR, "config_paths.json"))
+TARGET_CONFIGS = json_file_to_dict(join(CONFIG_DIR, "target_configs.json"))
+
+def get_valid_configs(target_name):
+    if target_name in TARGET_CONFIGS:
+        target_config = TARGET_CONFIGS[target_name]
+    else:
+        return {}
+
+    config_dict = {}
+    for attr in CONFIG_MAP:
+        if attr in target_config['test_configurations']:
+            config_dict[attr] = CONFIG_MAP[attr]
+    return config_dict
+
+def get_config_path(conf_name, target_name):
+    configs = get_valid_configs(target_name)
+    if configs and conf_name.upper() in configs:
+        return join(CONFIG_DIR, configs[conf_name.upper()])
+    else:
+        return None
+
+def get_default_config(target_name):
+    if target_name in TARGET_CONFIGS:
+        config_name = TARGET_CONFIGS[target_name]['default_test_configuration']
+        if config_name == "NONE":
+            return None
+        return join(CONFIG_DIR, CONFIG_MAP[config_name])
+    else:
+        return None
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/config_paths.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/config_paths.json
new file mode 100755
index 0000000..c543176
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/config_paths.json
@@ -0,0 +1,5 @@
+{
+    "ETHERNET" : "EthernetInterface.json",
+    "ODIN_WIFI" : "OdinInterface.json",
+    "ODIN_ETHERNET" : "Odin_EthernetInterface.json"
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/target_configs.json b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/target_configs.json
new file mode 100755
index 0000000..eaff8b5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_configs/target_configs.json
@@ -0,0 +1,10 @@
+{
+    "UBLOX_EVK_ODIN_W2": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["ODIN_WIFI", "ODIN_ETHERNET"]
+    },
+    "K64F": {
+        "default_test_configuration": "ETHERNET",
+        "test_configurations": ["ETHERNET"]
+    }
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_db.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_db.py
new file mode 100755
index 0000000..2ec301a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_db.py
@@ -0,0 +1,165 @@
+"""
+mbed SDK
+Copyright (c) 2011-2014 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+"""
+
+import re
+import json
+
+
+class BaseDBAccess():
+    """ Class used to connect with test database and store test results
+    """
+    def __init__(self):
+        self.db_object = None
+        self.db_type = None
+        # Connection credentials
+        self.host = None
+        self.user = None
+        self.passwd = None
+        self.db = None
+
+        # Test Suite DB scheme (table names)
+        self.TABLE_BUILD_ID = 'mtest_build_id'
+        self.TABLE_BUILD_ID_STATUS = 'mtest_build_id_status'
+        self.TABLE_BUILD_ID_TYPE = 'mtest_build_id_type'
+        self.TABLE_TARGET = 'mtest_target'
+        self.TABLE_TEST_ENTRY = 'mtest_test_entry'
+        self.TABLE_TEST_ID = 'mtest_test_id'
+        self.TABLE_TEST_RESULT = 'mtest_test_result'
+        self.TABLE_TEST_TYPE = 'mtest_test_type'
+        self.TABLE_TOOLCHAIN = 'mtest_toolchain'
+        # Build ID status PKs
+        self.BUILD_ID_STATUS_STARTED = 1 # Started
+        self.BUILD_ID_STATUS_IN_PROGRESS = 2 # In Progress
+        self.BUILD_ID_STATUS_COMPLETED = 3 #Completed
+        self.BUILD_ID_STATUS_FAILED = 4 # Failed
+        # Build ID type PKs
+        self.BUILD_ID_TYPE_TEST = 1 # Test
+        self.BUILD_ID_TYPE_BUILD_ONLY = 2 # Build Only
+
+    def get_hostname(self):
+        """ Useful when creating build_id in database
+            Function returns (hostname, uname) which can be used as (build_id_name, build_id_desc)
+        """
+        # Get hostname from socket
+        import socket
+        hostname = socket.gethostbyaddr(socket.gethostname())[0]
+        # Get uname from platform resources
+        import platform
+        uname = json.dumps(platform.uname())
+        return (hostname, uname)
+
+    def get_db_type(self):
+        """ Returns database type. E.g. 'mysql', 'sqlLite' etc.
+        """
+        return self.db_type
+
+    def detect_database(self, verbose=False):
+        """ detect database and return VERION data structure or string (verbose=True)
+        """
+        return None
+
+    def parse_db_connection_string(self, str):
+        """ Parsing SQL DB connection string. String should contain:
+            - DB Name, user name, password, URL (DB host), name
+            Function should return tuple with parsed (db_type, username, password, host, db_name) or None if error
+
+            (db_type, username, password, host, db_name) = self.parse_db_connection_string(db_url)
+
+            E.g. connection string: 'mysql://username:password@127.0.0.1/db_name'
+        """
+        result = None
+        if type(str) == type(''):
+            PATTERN = '^([\w]+)://([\w]+):([\w]*)@(.*)/([\w]+)'
+            result = re.match(PATTERN, str)
+            if result is not None:
+                result = result.groups()    # Tuple (db_name, host, user, passwd, db)
+        return result # (db_type, username, password, host, db_name)
+
+    def is_connected(self):
+        """ Returns True if we are connected to database
+        """
+        pass
+
+    def connect(self, host, user, passwd, db):
+        """ Connects to DB and returns DB object
+        """
+        pass
+
+    def connect_url(self, db_url):
+        """ Connects to database using db_url (database url parsing),
+            store host, username, password, db_name
+        """
+        pass
+
+    def reconnect(self):
+        """ Reconnects to DB and returns DB object using stored host name,
+            database name and credentials (user name and password)
+        """
+        pass
+
+    def disconnect(self):
+        """ Close DB connection
+        """
+        pass
+
+    def escape_string(self, str):
+        """ Escapes string so it can be put in SQL query between quotes
+        """
+        pass
+
+    def select_all(self, query):
+        """ Execute SELECT query and get all results
+        """
+        pass
+
+    def insert(self, query, commit=True):
+        """ Execute INSERT query, define if you want to commit
+        """
+        pass
+
+    def get_next_build_id(self, name, desc='', location='', type=None, status=None):
+        """ Insert new build_id (DB unique build like ID number to send all test results)
+        """
+        pass
+
+    def get_table_entry_pk(self, table, column, value, update_db=True):
+        """ Checks for entries in tables with two columns (<TABLE_NAME>_pk, <column>)
+            If update_db is True updates table entry if value in specified column doesn't exist
+        """
+        pass
+
+    def update_table_entry(self, table, column, value):
+        """ Updates table entry if value in specified column doesn't exist
+            Locks table to perform atomic read + update
+        """
+        pass
+
+    def update_build_id_info(self, build_id, **kw):
+        """ Update additional data inside build_id table
+            Examples:
+            db.update_build_is(build_id, _status_fk=self.BUILD_ID_STATUS_COMPLETED, _shuffle_seed=0.0123456789):
+        """
+        pass
+
+    def insert_test_entry(self, build_id, target, toolchain, test_type, test_id, test_result, test_time, test_timeout, test_loop, test_extra=''):
+        """ Inserts test result entry to database. All checks regarding existing
+            toolchain names in DB are performed.
+            If some data is missing DB will be updated
+        """
+        pass
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_exporters.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_exporters.py
new file mode 100755
index 0000000..9da979c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_exporters.py
@@ -0,0 +1,414 @@
+"""
+mbed SDK
+Copyright (c) 2011-2014 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.wirkus@arm.com>
+"""
+
+from tools.utils import construct_enum, mkdir
+from prettytable import PrettyTable
+import os
+
+ResultExporterType = construct_enum(HTML='Html_Exporter',
+                                    JUNIT='JUnit_Exporter',
+                                    JUNIT_OPER='JUnit_Exporter_Interoperability',
+                                    BUILD='Build_Exporter',
+                                    TEXT='Text_Exporter',
+                                    PRINT='Print_Exporter')
+
+
+class ReportExporter():
+    """ Class exports extended test result Python data structure to
+        different formats like HTML, JUnit XML.
+
+    Parameter 'test_result_ext' format:
+
+    u'uARM': {   u'LPC1768': {   'MBED_2': {   0: {   'copy_method': 'shutils.copy()',
+                                                      'duration': 20,
+                                                      'elapsed_time': 1.7929999828338623,
+                                                      'output': 'Host test instrumentation on ...\r\n',
+                                                      'result': 'OK',
+                                                      'target_name': u'LPC1768',
+                                                      'description': 'stdio',
+                                                      'id': u'MBED_2',
+                                                      'toolchain_name': u'uARM'}},
+    """
+    CSS_STYLE = """<style>
+                   .name{
+                    border: 1px solid;
+                    border-radius: 25px;
+                    width: 100px;
+                   }
+                   .tooltip{
+                       position:absolute;
+                       background-color: #F5DA81;
+                       display:none;
+                   }
+                   </style>
+                """
+
+    JAVASCRIPT = """
+                 <script type="text/javascript">
+                 function show (elem) {
+                     elem.style.display = "block";
+                 }
+                 function hide (elem) {
+                     elem.style.display = "";
+                 }
+                 </script>
+                 """
+
+    def __init__(self, result_exporter_type, package="test"):
+        self.result_exporter_type = result_exporter_type
+        self.package = package
+
+    def report(self, test_summary_ext, test_suite_properties=None,
+               print_log_for_failures=True):
+        """ Invokes report depending on exporter_type set in constructor
+        """
+        if self.result_exporter_type == ResultExporterType.HTML:
+            # HTML exporter
+            return self.exporter_html(test_summary_ext, test_suite_properties)
+        elif self.result_exporter_type == ResultExporterType.JUNIT:
+            # JUNIT exporter for results from test suite
+            return self.exporter_junit(test_summary_ext, test_suite_properties)
+        elif self.result_exporter_type == ResultExporterType.JUNIT_OPER:
+            # JUNIT exporter for interoperability test
+            return self.exporter_junit_ioper(test_summary_ext, test_suite_properties)
+        elif self.result_exporter_type == ResultExporterType.PRINT:
+            # JUNIT exporter for interoperability test
+            return self.exporter_print(test_summary_ext, print_log_for_failures=print_log_for_failures)
+        elif self.result_exporter_type == ResultExporterType.TEXT:
+            return self.exporter_text(test_summary_ext)
+        return None
+
+    def report_to_file(self, test_summary_ext, file_name, test_suite_properties=None):
+        """ Stores report to specified file
+        """
+        report = self.report(test_summary_ext, test_suite_properties=test_suite_properties)
+        self.write_to_file(report, file_name)
+
+    def write_to_file(self, report, file_name):
+        if report is not None:
+            dirname = os.path.dirname(file_name)
+            if dirname:
+                mkdir(dirname)
+            with open(file_name, 'w') as f:
+                f.write(report)
+
+    def get_tooltip_name(self, toolchain, target, test_id, loop_no):
+        """ Generate simple unique tool-tip name which can be used.
+            For example as HTML <div> section id attribute.
+        """
+        return "target_test_%s_%s_%s_%s"% (toolchain.lower(), target.lower(), test_id.lower(), loop_no)
+
+    def get_result_div_sections(self, test, test_no):
+        """ Generates separate <DIV> sections which contains test results output.
+        """
+
+        RESULT_COLORS = {'OK': 'LimeGreen',
+                         'FAIL': 'Orange',
+                         'ERROR': 'LightCoral',
+                         'OTHER': 'LightGray',
+                        }
+
+        tooltip_name = self.get_tooltip_name(test['toolchain_name'], test['target_name'], test['id'], test_no)
+        background_color = RESULT_COLORS[test['result'] if test['result'] in RESULT_COLORS else 'OTHER']
+        result_div_style = "background-color: %s"% background_color
+
+        result = """<div class="name" style="%s" onmouseover="show(%s)" onmouseout="hide(%s)">
+                       <center>%s</center>
+                       <div class = "tooltip" id= "%s">
+                       <b>%s</b><br />
+                       <hr />
+                       <b>%s</b> in <b>%.2f sec</b><br />
+                       <hr />
+                       <small>
+                       %s
+                       </small>
+                       </div>
+                    </div>
+                 """% (result_div_style,
+                       tooltip_name,
+                       tooltip_name,
+                       test['result'],
+                       tooltip_name,
+                       test['target_name_unique'],
+                       test['description'],
+                       test['elapsed_time'],
+                       test['output'].replace('\n', '<br />'))
+        return result
+
+    def get_result_tree(self, test_results):
+        """ If test was run in a loop (we got few results from the same test)
+            we will show it in a column to see all results.
+            This function produces HTML table with corresponding results.
+        """
+        result = ''
+        for i, test_result in enumerate(test_results):
+            result += '<table>'
+            test_ids = sorted(test_result.keys())
+            for test_no in test_ids:
+                test = test_result[test_no]
+                result += """<tr>
+                                 <td valign="top">%s</td>
+                             </tr>"""% self.get_result_div_sections(test, "%d_%d" % (test_no, i))
+            result += '</table>'
+        return result
+
+    def get_all_unique_test_ids(self, test_result_ext):
+        """ Gets all unique test ids from all ran tests.
+            We need this to create complete list of all test ran.
+        """
+        result = []
+        targets = test_result_ext.keys()
+        for target in targets:
+            toolchains = test_result_ext[target].keys()
+            for toolchain in toolchains:
+                tests = test_result_ext[target][toolchain].keys()
+                result.extend(tests)
+        return sorted(list(set(result)))
+
+    #
+    # Exporters functions
+    #
+
+    def exporter_html(self, test_result_ext, test_suite_properties=None):
+        """ Export test results in proprietary HTML format.
+        """
+        result = """<html>
+                    <head>
+                        <title>mbed SDK test suite test result report</title>
+                        %s
+                        %s
+                    </head>
+                    <body>
+                 """% (self.CSS_STYLE, self.JAVASCRIPT)
+
+        unique_test_ids = self.get_all_unique_test_ids(test_result_ext)
+        targets = sorted(test_result_ext.keys())
+        result += '<table>'
+        for target in targets:
+            toolchains = sorted(test_result_ext[target].keys())
+            for toolchain in toolchains:
+                result += '<tr>'
+                result += '<td></td>'
+                result += '<td></td>'
+
+                tests = sorted(test_result_ext[target][toolchain].keys())
+                for test in unique_test_ids:
+                    result += """<td align="center">%s</td>"""% test
+                result += """</tr>
+                              <tr>
+                              <td valign="center">%s</td>
+                              <td valign="center"><b>%s</b></td>
+                          """% (toolchain, target)
+
+                for test in unique_test_ids:
+                    test_result = self.get_result_tree(test_result_ext[target][toolchain][test]) if test in tests else ''
+                    result += '<td>%s</td>'% (test_result)
+
+                result += '</tr>'
+        result += '</table>'
+        result += '</body></html>'
+        return result
+
+    def exporter_junit_ioper(self, test_result_ext, test_suite_properties=None):
+        from junit_xml import TestSuite, TestCase
+        test_suites = []
+        test_cases = []
+
+        for platform in sorted(test_result_ext.keys()):
+            # {platform : ['Platform', 'Result', 'Scope', 'Description'])
+            test_cases = []
+            for tr_result in test_result_ext[platform]:
+                result, name, scope, description = tr_result
+
+                classname = 'test.ioper.%s.%s.%s' % (platform, name, scope)
+                elapsed_sec = 0
+                _stdout = description
+                _stderr = ''
+                # Test case
+                tc = TestCase(name, classname, elapsed_sec, _stdout, _stderr)
+                # Test case extra failure / error info
+                if result == 'FAIL':
+                    tc.add_failure_info(description, _stdout)
+                elif result == 'ERROR':
+                    tc.add_error_info(description, _stdout)
+                elif result == 'SKIP' or result == 'NOT_SUPPORTED':
+                    tc.add_skipped_info(description, _stdout)
+
+                test_cases.append(tc)
+            ts = TestSuite("test.suite.ioper.%s" % (platform), test_cases)
+            test_suites.append(ts)
+        return TestSuite.to_xml_string(test_suites)
+
+    def exporter_junit(self, test_result_ext, test_suite_properties=None):
+        """ Export test results in JUnit XML compliant format
+        """
+        from junit_xml import TestSuite, TestCase
+        test_suites = []
+        test_cases = []
+
+        targets = sorted(test_result_ext.keys())
+        for target in targets:
+            toolchains = sorted(test_result_ext[target].keys())
+            for toolchain in toolchains:
+                test_cases = []
+                tests = sorted(test_result_ext[target][toolchain].keys())
+                for test in tests:
+                    test_results = test_result_ext[target][toolchain][test]
+                    for test_res in test_results:
+                        test_ids = sorted(test_res.keys())
+                        for test_no in test_ids:
+                            test_result = test_res[test_no]
+                            name = test_result['description']
+                            classname = '%s.%s.%s.%s'% (self.package, target, toolchain, test_result['id'])
+                            elapsed_sec = test_result['elapsed_time']
+                            _stdout = test_result['output']
+
+                            if 'target_name_unique' in test_result:
+                                _stderr = test_result['target_name_unique']
+                            else:
+                                _stderr = test_result['target_name']
+
+                            # Test case
+                            tc = TestCase(name, classname, elapsed_sec, _stdout, _stderr)
+
+                            # Test case extra failure / error info
+                            message = test_result['result']
+                            if test_result['result'] == 'FAIL':
+                                tc.add_failure_info(message, _stdout)
+                            elif test_result['result'] == 'SKIP' or test_result["result"] == 'NOT_SUPPORTED':
+                                tc.add_skipped_info(message, _stdout)
+                            elif test_result['result'] != 'OK':
+                                tc.add_error_info(message, _stdout)
+
+                            test_cases.append(tc)
+
+                ts = TestSuite("test.suite.%s.%s"% (target, toolchain), test_cases, properties=test_suite_properties[target][toolchain])
+                test_suites.append(ts)
+        return TestSuite.to_xml_string(test_suites)
+
+    def exporter_print_helper(self, array, print_log=False):
+        for item in array:
+            print "  * %s::%s::%s" % (item["target_name"], item["toolchain_name"], item["id"])
+            if print_log:
+                log_lines = item["output"].split("\n")
+                for log_line in log_lines:
+                    print "        %s" % log_line
+
+    def exporter_print(self, test_result_ext, print_log_for_failures=False):
+        """ Export test results in print format.
+        """
+        failures = []
+        skips = []
+        successes = []
+
+        unique_test_ids = self.get_all_unique_test_ids(test_result_ext)
+        targets = sorted(test_result_ext.keys())
+
+        for target in targets:
+            toolchains = sorted(test_result_ext[target].keys())
+            for toolchain in toolchains:
+                tests = sorted(test_result_ext[target][toolchain].keys())
+                for test in tests:
+                    test_runs = test_result_ext[target][toolchain][test]
+                    for test_runner in test_runs:
+                        #test_run = test_result_ext[target][toolchain][test][test_run_number][0]
+                        test_run = test_runner[0]
+                        
+                        if "result" in test_run:
+                            if test_run["result"] == "FAIL":
+                                failures.append(test_run)
+                            elif test_run["result"] == "SKIP" or test_run["result"] == "NOT_SUPPORTED":
+                                skips.append(test_run)
+                            elif test_run["result"] == "OK":
+                                successes.append(test_run)
+                            else:
+                                raise Exception("Unhandled result type: %s" % (test_run["result"]))
+                        else:
+                            raise Exception("'test_run' did not have a 'result' value")
+
+        if successes:
+            print "\n\nBuild successes:"
+            self.exporter_print_helper(successes)
+
+        if skips:
+            print "\n\nBuild skips:"
+            self.exporter_print_helper(skips)
+
+        if failures:
+            print "\n\nBuild failures:"
+            self.exporter_print_helper(failures, print_log=print_log_for_failures)
+            return False
+        else:
+            return True
+
+    def exporter_text(self, test_result_ext):
+        """ Prints well-formed summary with results (SQL table like)
+            table shows target x test results matrix across
+        """
+        success_code = 0    # Success code that can be leter returned to
+        # Pretty table package is used to print results
+        pt = PrettyTable(["Result", "Target", "Toolchain", "Test ID", "Test Description",
+                          "Elapsed Time", "Timeout"])
+        pt.align["Result"] = "l" # Left align
+        pt.align["Target"] = "l" # Left align
+        pt.align["Toolchain"] = "l" # Left align
+        pt.align["Test ID"] = "l" # Left align
+        pt.align["Test Description"] = "l" # Left align
+        pt.padding_width = 1 # One space between column edges and contents (default)
+
+        result_dict = {"OK" : 0,
+                       "FAIL" : 0,
+                       "ERROR" : 0,
+                       "UNDEF" : 0,
+                       "IOERR_COPY" : 0,
+                       "IOERR_DISK" : 0,
+                       "IOERR_SERIAL" : 0,
+                       "TIMEOUT" : 0,
+                       "NO_IMAGE" : 0,
+                       "MBED_ASSERT" : 0,
+                       "BUILD_FAILED" : 0,
+                       "NOT_SUPPORTED" : 0
+        }
+        unique_test_ids = self.get_all_unique_test_ids(test_result_ext)
+        targets = sorted(test_result_ext.keys())
+        for target in targets:
+            toolchains = sorted(test_result_ext[target].keys())
+            for toolchain in toolchains:
+                test_cases = []
+                tests = sorted(test_result_ext[target][toolchain].keys())
+                for test in tests:
+                    test_results = test_result_ext[target][toolchain][test]
+                    for test_res in test_results:
+                        test_ids = sorted(test_res.keys())
+                        for test_no in test_ids:
+                            test_result = test_res[test_no]
+                            result_dict[test_result['result']] += 1
+                            pt.add_row([test_result['result'],
+                                        test_result['target_name'],
+                                        test_result['toolchain_name'],
+                                        test_result['id'],
+                                        test_result['description'],
+                                        test_result['elapsed_time'],
+                                        test_result['duration']])
+        result = pt.get_string()
+        result += "\n"
+
+        # Print result count
+        result += "Result: " + ' / '.join(['%s %s' % (value, key) for (key, value) in {k: v for k, v in result_dict.items() if v != 0}.iteritems()])
+        return result
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_mysql.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_mysql.py
new file mode 100755
index 0000000..4f00ab6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_mysql.py
@@ -0,0 +1,271 @@
+"""
+mbed SDK
+Copyright (c) 2011-2014 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+"""
+
+import re
+import MySQLdb as mdb
+
+# Imports from TEST API
+from tools.test_db import BaseDBAccess
+
+
+class MySQLDBAccess(BaseDBAccess):
+    """ Wrapper for MySQL DB access for common test suite interface
+    """
+    def __init__(self):
+        BaseDBAccess.__init__(self)
+        self.DB_TYPE = 'mysql'
+
+    def detect_database(self, verbose=False):
+        """ detect database and return VERION data structure or string (verbose=True)
+        """
+        query = 'SHOW VARIABLES LIKE "%version%"'
+        rows = self.select_all(query)
+        if verbose:
+            result = []
+            for row in rows:
+                result.append("\t%s: %s"% (row['Variable_name'], row['Value']))
+            result = "\n".join(result)
+        else:
+            result = rows
+        return result
+
+    def parse_db_connection_string(self, str):
+        """ Parsing SQL DB connection string. String should contain:
+            - DB Name, user name, password, URL (DB host), name
+            Function should return tuple with parsed (host, user, passwd, db) or None if error
+            E.g. connection string: 'mysql://username:password@127.0.0.1/db_name'
+        """
+        result = BaseDBAccess().parse_db_connection_string(str)
+        if result is not None:
+            (db_type, username, password, host, db_name) = result
+            if db_type != 'mysql':
+                result = None
+        return result
+
+    def is_connected(self):
+        """ Returns True if we are connected to database
+        """
+        return self.db_object is not None
+
+    def connect(self, host, user, passwd, db):
+        """ Connects to DB and returns DB object
+        """
+        try:
+            self.db_object = mdb.connect(host=host, user=user, passwd=passwd, db=db)
+            # Let's remember connection credentials
+            self.db_type = self.DB_TYPE
+            self.host = host
+            self.user = user
+            self.passwd = passwd
+            self.db = db
+        except mdb.Error, e:
+            print "Error %d: %s"% (e.args[0], e.args[1])
+            self.db_object = None
+            self.db_type = None
+            self.host = None
+            self.user = None
+            self.passwd = None
+            self.db = None
+
+    def connect_url(self, db_url):
+        """ Connects to database using db_url (database url parsing),
+            store host, username, password, db_name
+        """
+        result = self.parse_db_connection_string(db_url)
+        if result is not None:
+            (db_type, username, password, host, db_name) = result
+            if db_type == self.DB_TYPE:
+                self.connect(host, username, password, db_name)
+
+    def reconnect(self):
+        """ Reconnects to DB and returns DB object using stored host name,
+            database name and credentials (user name and password)
+        """
+        self.connect(self.host, self.user, self.passwd, self.db)
+
+    def disconnect(self):
+        """ Close DB connection
+        """
+        if self.db_object:
+            self.db_object.close()
+        self.db_object = None
+        self.db_type = None
+
+    def escape_string(self, str):
+        """ Escapes string so it can be put in SQL query between quotes
+        """
+        con = self.db_object
+        result = con.escape_string(str)
+        return result if result else ''
+
+    def select_all(self, query):
+        """ Execute SELECT query and get all results
+        """
+        con = self.db_object
+        cur = con.cursor(mdb.cursors.DictCursor)
+        cur.execute(query)
+        rows = cur.fetchall()
+        return rows
+
+    def insert(self, query, commit=True):
+        """ Execute INSERT query, define if you want to commit
+        """
+        con = self.db_object
+        cur = con.cursor()
+        cur.execute(query)
+        if commit:
+            con.commit()
+        return cur.lastrowid
+
+    def get_next_build_id(self, name, desc='', location='', type=None, status=None):
+        """ Insert new build_id (DB unique build like ID number to send all test results)
+        """
+        if status is None:
+            status = self.BUILD_ID_STATUS_STARTED
+
+        if type is None:
+            type = self.BUILD_ID_TYPE_TEST
+
+        query = """INSERT INTO `%s` (%s_name, %s_desc, %s_location, %s_type_fk, %s_status_fk)
+                        VALUES ('%s', '%s', '%s', %d, %d)"""% (self.TABLE_BUILD_ID,
+                                                               self.TABLE_BUILD_ID,
+                                                               self.TABLE_BUILD_ID,
+                                                               self.TABLE_BUILD_ID,
+                                                               self.TABLE_BUILD_ID,
+                                                               self.TABLE_BUILD_ID,
+                                                               self.escape_string(name),
+                                                               self.escape_string(desc),
+                                                               self.escape_string(location),
+                                                               type,
+                                                               status)
+        index = self.insert(query) # Provide inserted record PK
+        return index
+
+    def get_table_entry_pk(self, table, column, value, update_db=True):
+        """ Checks for entries in tables with two columns (<TABLE_NAME>_pk, <column>)
+            If update_db is True updates table entry if value in specified column doesn't exist
+        """
+        # TODO: table buffering
+        result = None
+        table_pk = '%s_pk'% table
+        query = """SELECT `%s`
+                     FROM `%s`
+                    WHERE `%s`='%s'"""% (table_pk,
+                                         table,
+                                         column,
+                                         self.escape_string(value))
+        rows = self.select_all(query)
+        if len(rows) == 1:
+            result = rows[0][table_pk]
+        elif len(rows) == 0 and update_db:
+            # Update DB with new value
+            result = self.update_table_entry(table, column, value)
+        return result
+
+    def update_table_entry(self, table, column, value):
+        """ Updates table entry if value in specified column doesn't exist
+            Locks table to perform atomic read + update
+        """
+        result = None
+        con = self.db_object
+        cur = con.cursor()
+        cur.execute("LOCK TABLES `%s` WRITE"% table)
+        table_pk = '%s_pk'% table
+        query = """SELECT `%s`
+                     FROM `%s`
+                    WHERE `%s`='%s'"""% (table_pk,
+                                         table,
+                                         column,
+                                         self.escape_string(value))
+        cur.execute(query)
+        rows = cur.fetchall()
+        if len(rows) == 0:
+            query = """INSERT INTO `%s` (%s)
+                            VALUES ('%s')"""% (table,
+                                               column,
+                                               self.escape_string(value))
+            cur.execute(query)
+            result = cur.lastrowid
+        con.commit()
+        cur.execute("UNLOCK TABLES")
+        return result
+
+    def update_build_id_info(self, build_id, **kw):
+        """ Update additional data inside build_id table
+            Examples:
+            db.update_build_id_info(build_id, _status_fk=self.BUILD_ID_STATUS_COMPLETED, _shuffle_seed=0.0123456789):
+        """
+        if len(kw):
+            con = self.db_object
+            cur = con.cursor()
+            # Prepare UPDATE query
+            # ["`mtest_build_id_pk`=[value-1]", "`mtest_build_id_name`=[value-2]", "`mtest_build_id_desc`=[value-3]"]
+            set_list = []
+            for col_sufix in kw:
+                assign_str = "`%s%s`='%s'"% (self.TABLE_BUILD_ID, col_sufix, self.escape_string(str(kw[col_sufix])))
+                set_list.append(assign_str)
+            set_str = ', '.join(set_list)
+            query = """UPDATE `%s`
+                          SET %s
+                        WHERE `mtest_build_id_pk`=%d"""% (self.TABLE_BUILD_ID,
+                                                          set_str,
+                                                          build_id)
+            cur.execute(query)
+            con.commit()
+
+    def insert_test_entry(self, build_id, target, toolchain, test_type, test_id, test_result, test_output, test_time, test_timeout, test_loop, test_extra=''):
+        """ Inserts test result entry to database. All checks regarding existing
+            toolchain names in DB are performed.
+            If some data is missing DB will be updated
+        """
+        # Get all table FK and if entry is new try to insert new value
+        target_fk = self.get_table_entry_pk(self.TABLE_TARGET, self.TABLE_TARGET + '_name', target)
+        toolchain_fk = self.get_table_entry_pk(self.TABLE_TOOLCHAIN, self.TABLE_TOOLCHAIN + '_name', toolchain)
+        test_type_fk = self.get_table_entry_pk(self.TABLE_TEST_TYPE, self.TABLE_TEST_TYPE + '_name', test_type)
+        test_id_fk = self.get_table_entry_pk(self.TABLE_TEST_ID, self.TABLE_TEST_ID + '_name', test_id)
+        test_result_fk = self.get_table_entry_pk(self.TABLE_TEST_RESULT, self.TABLE_TEST_RESULT + '_name', test_result)
+
+        con = self.db_object
+        cur = con.cursor()
+
+        query = """ INSERT INTO `%s` (`mtest_build_id_fk`,
+                                      `mtest_target_fk`,
+                                      `mtest_toolchain_fk`,
+                                      `mtest_test_type_fk`,
+                                      `mtest_test_id_fk`,
+                                      `mtest_test_result_fk`,
+                                      `mtest_test_output`,
+                                      `mtest_test_time`,
+                                      `mtest_test_timeout`,
+                                      `mtest_test_loop_no`,
+                                      `mtest_test_result_extra`)
+                         VALUES (%d, %d, %d, %d, %d, %d, '%s', %.2f, %.2f, %d, '%s')"""% (self.TABLE_TEST_ENTRY,
+                                                                                          build_id,
+                                                                                          target_fk,
+                                                                                          toolchain_fk,
+                                                                                          test_type_fk,
+                                                                                          test_id_fk,
+                                                                                          test_result_fk,
+                                                                                          self.escape_string(test_output),
+                                                                                          test_time,
+                                                                                          test_timeout,
+                                                                                          test_loop,
+                                                                                          self.escape_string(test_extra))
+        cur.execute(query)
+        con.commit()
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_webapi.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_webapi.py
new file mode 100755
index 0000000..437a719
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/test_webapi.py
@@ -0,0 +1,243 @@
+"""
+mbed SDK
+Copyright (c) 2011-2014 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Author: Przemyslaw Wirkus <Przemyslaw.wirkus@arm.com>
+"""
+
+import sys
+import json
+import optparse
+from flask import Flask
+from os.path import join, abspath, dirname
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+# Imports related to mbed build api
+from tools.utils import construct_enum
+from tools.build_api import mcu_toolchain_matrix
+
+# Imports from TEST API
+from test_api import SingleTestRunner
+from test_api import SingleTestExecutor
+from test_api import get_json_data_from_file
+from test_api import print_muts_configuration_from_json
+from test_api import print_test_configuration_from_json
+from test_api import get_avail_tests_summary_table
+from test_api import get_default_test_options_parser
+
+
+class SingleTestRunnerWebService(SingleTestRunner):
+    def __init__(self):
+        super(SingleTestRunnerWebService, self).__init__()
+
+        # With this lock we should control access to certain resources inside this class
+        self.resource_lock = thread.allocate_lock()
+
+        self.RestRequest = construct_enum(REST_MUTS='muts',
+                                          REST_TEST_SPEC='test_spec',
+                                          REST_TEST_RESULTS='test_results')
+
+    def get_rest_result_template(self, result, command, success_code):
+        """ Returns common part of every web service request
+        """
+        result = {"result" : result,
+                  "command" : command,
+                  "success_code": success_code} # 0 - OK, >0 - Error number
+        return result
+
+    # REST API handlers for Flask framework
+    def rest_api_status(self):
+        """ Returns current test execution status. E.g. running / finished etc.
+        """
+        with self.resource_lock:
+            pass
+
+    def rest_api_config(self):
+        """ Returns configuration passed to SingleTest executor
+        """
+        with self.resource_lock:
+            pass
+
+    def rest_api_log(self):
+        """ Returns current test log """
+        with self.resource_lock:
+            pass
+
+    def rest_api_request_handler(self, request_type):
+        """ Returns various data structures. Both static and mutable during test
+        """
+        result = {}
+        success_code = 0
+        with self.resource_lock:
+            if request_type == self.RestRequest.REST_MUTS:
+                result = self.muts # Returns MUTs
+            elif request_type == self.RestRequest.REST_TEST_SPEC:
+                result = self.test_spec # Returns Test Specification
+            elif request_type == self.RestRequest.REST_TEST_RESULTS:
+                pass # Returns test results
+            else:
+                success_code = -1
+        return json.dumps(self.get_rest_result_template(result, 'request/' + request_type, success_code), indent=4)
+
+
+def singletest_in_webservice_mode():
+    # TODO Implement this web service functionality
+    pass
+
+
+def get_default_test_webservice_options_parser():
+    """ Get test script web service options used by CLI, webservices etc.
+    """
+    parser = get_default_test_options_parser()
+
+    # Things related to web services offered by test suite scripts
+    parser.add_argument('', '--rest-api',
+                        dest='rest_api_enabled',
+                        default=False,
+                        action="store_true",
+                        help='Enables REST API.')
+
+    parser.add_argument('', '--rest-api-port',
+                        dest='rest_api_port_no',
+                        type=int,
+                        help='Sets port for REST API interface')
+
+    return parser
+
+'''
+if __name__ == '__main__':
+    # Command line options
+    parser = get_default_test_options_parser()
+
+    parser.description = """This script allows you to run mbed defined test cases for particular MCU(s) and corresponding toolchain(s)."""
+    parser.epilog = """Example: singletest.py -i test_spec.json -M muts_all.json"""
+
+    (opts, args) = parser.parse_args()
+
+    # Print summary / information about automation test status
+    if opts.test_automation_report:
+        print get_avail_tests_summary_table()
+        exit(0)
+
+    # Print summary / information about automation test status
+    if opts.test_case_report:
+        test_case_report_cols = ['id', 'automated', 'description', 'peripherals', 'host_test', 'duration', 'source_dir']
+        print get_avail_tests_summary_table(cols=test_case_report_cols, result_summary=False, join_delim='\n')
+        exit(0)
+
+    # Only prints matrix of supported toolchains
+    if opts.supported_toolchains:
+        print mcu_toolchain_matrix(platform_filter=opts.general_filter_regex)
+        exit(0)
+
+    # Open file with test specification
+    # test_spec_filename tells script which targets and their toolchain(s)
+    # should be covered by the test scenario
+    test_spec = get_json_data_from_file(opts.test_spec_filename) if opts.test_spec_filename else None
+    if test_spec is None:
+        if not opts.test_spec_filename:
+            parser.print_help()
+        exit(-1)
+
+    # Get extra MUTs if applicable
+    MUTs = get_json_data_from_file(opts.muts_spec_filename) if opts.muts_spec_filename else None
+
+    if MUTs is None:
+        if not opts.muts_spec_filename:
+            parser.print_help()
+        exit(-1)
+
+    # Only prints read MUTs configuration
+    if MUTs and opts.verbose_test_configuration_only:
+        print "MUTs configuration in %s:"% opts.muts_spec_filename
+        print print_muts_configuration_from_json(MUTs)
+        print
+        print "Test specification in %s:"% opts.test_spec_filename
+        print print_test_configuration_from_json(test_spec)
+        exit(0)
+
+    # Verbose test specification and MUTs configuration
+    if MUTs and opts.verbose:
+        print print_muts_configuration_from_json(MUTs)
+    if test_spec and opts.verbose:
+        print print_test_configuration_from_json(test_spec)
+
+    if opts.only_build_tests:
+        # We are skipping testing phase, and suppress summary
+        opts.suppress_summary = True
+
+    single_test = SingleTestRunner(_global_loops_count=opts.test_global_loops_value,
+                                   _test_loops_list=opts.test_loops_list,
+                                   _muts=MUTs,
+                                   _test_spec=test_spec,
+                                   _opts_goanna_for_mbed_sdk=opts.goanna_for_mbed_sdk,
+                                   _opts_goanna_for_tests=opts.goanna_for_tests,
+                                   _opts_shuffle_test_order=opts.shuffle_test_order,
+                                   _opts_shuffle_test_seed=opts.shuffle_test_seed,
+                                   _opts_test_by_names=opts.test_by_names,
+                                   _opts_test_only_peripheral=opts.test_only_peripheral,
+                                   _opts_test_only_common=opts.test_only_common,
+                                   _opts_verbose_skipped_tests=opts.verbose_skipped_tests,
+                                   _opts_verbose_test_result_only=opts.verbose_test_result_only,
+                                   _opts_verbose=opts.verbose,
+                                   _opts_firmware_global_name=opts.firmware_global_name,
+                                   _opts_only_build_tests=opts.only_build_tests,
+                                   _opts_suppress_summary=opts.suppress_summary,
+                                   _opts_test_x_toolchain_summary=opts.test_x_toolchain_summary,
+                                   _opts_copy_method=opts.copy_method
+                                   )
+
+    try:
+        st_exec_thread = SingleTestExecutor(single_test)
+    except KeyboardInterrupt, e:
+        print "\n[CTRL+c] exit"
+    st_exec_thread.start()
+
+    if opts.rest_api_enabled:
+        # Enable REST API
+
+        app = Flask(__name__)
+
+        @app.route('/')
+        def hello_world():
+            return 'Hello World!'
+
+        @app.route('/status')
+        def rest_api_status():
+            return single_test.rest_api_status() # TODO
+
+        @app.route('/config')
+        def rest_api_config():
+            return single_test.rest_api_config() # TODO
+
+        @app.route('/log')
+        def rest_api_log():
+            return single_test.rest_api_log() # TODO
+
+        @app.route('/request/<request_type>') # 'muts', 'test_spec', 'test_results'
+        def rest_api_request_handler(request_type):
+            result = single_test.rest_api_request_handler(request_type) # TODO
+            return result
+
+        rest_api_port = int(opts.rest_api_port_no) if opts.rest_api_port_no else 5555
+        app.debug = False
+        app.run(port=rest_api_port) # Blocking Flask REST API web service
+    else:
+        st_exec_thread.join()
+
+'''
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/tests.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/tests.py
new file mode 100755
index 0000000..4b31665
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/tests.py
@@ -0,0 +1,924 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from tools.paths import *
+from tools.data.support import *
+from argparse import ArgumentTypeError
+from utils import columnate
+
+try:
+    import tools.private_settings as ps
+except:
+    ps = object()
+
+TEST_CMSIS_LIB = join(TEST_DIR, "cmsis", "lib")
+TEST_MBED_LIB = join(TEST_DIR, "mbed", "env")
+
+PERIPHERALS = join(TEST_DIR, "peripherals")
+BENCHMARKS_DIR = join(TEST_DIR, "benchmarks")
+
+SD = join(TEST_DIR, "sd")
+TMP102 = join(PERIPHERALS, 'TMP102')
+AT30TSE75X = join(PERIPHERALS, 'AT30TSE75X')
+
+"""
+Wiring:
+  * Ground:
+    * LPC1*: p1
+    * KL25Z: GND
+
+  * Vout
+    * LPC1*: p40
+    * KL25Z: P3V3
+
+  * TMP102 (I2C):
+      * LPC1*: (SDA=p28 , SCL=p27)
+      * KL25Z: (SDA=PTC9, SCL=PTC8)
+      * MAXWSNENV: (SDA=TP6, SCL=TP5)
+
+  * digital_loop (Digital(In|Out|InOut), InterruptIn):
+      * Arduino headers: (D0 <-> D7)
+      * NUCLEO_*: (D2 <-> D9)
+      * LPC1549: (D2 <-> D7)
+      * LPC1*: (p5   <-> p25 )
+      * KL25Z: (PTA5<-> PTC6)
+      * MAXWSNENV: (TP3 <-> TP4)
+      * MAX32600MBED: (P1_0 <-> P4_7)
+      * VK_RZ_A1H: (P3_2 <-> P5_6)
+
+  * port_loop (Port(In|Out|InOut)):
+      * Arduino headers: (D0 <-> D7), (D1 <-> D6)
+      * LPC1*: (p5   <-> p25), (p6   <-> p26)
+      * KL25Z: (PTA5 <-> PTC6), (PTA4 <-> PTC5)
+      * NUCLEO_F103RB: (PC_6 <-> PB_8), (PC_5 <-> PB_9)
+      * MAXWSNENV: (TP1 <-> TP3), (TP2 <-> TP4)
+      * MAX32600MBED: (P1_0 <-> P4_7), (P1_1 <-> P4_6)
+      * VK_RZ_A1H: (P3_2 <-> P5_6), (P3_7 <-> P5_1)
+
+  * analog_loop (AnalogIn, AnalogOut):
+      * Arduino headers: (A0 <-> A5)
+      * NUCLEO64: (A0 <-> A2)
+      * NUCLEO144: (A0 <-> D13)
+      * LPC1549: (A0 <-> D12)
+      * LPC1*: (p17   <-> p18 )
+      * KL25Z: (PTE30 <-> PTC2)
+
+  * analog_pot (AnalogIn):
+      * Arduino headers: (A0, A1)
+      * VK_RZ_A1H: (AN0, AN1)
+
+  * SD (SPI):
+      * LPC1*: (mosi=p11 , miso=p12 , sclk=p13 , cs=p14 )
+      * KL25Z: (mosi=PTD2, miso=PTD3, sclk=PTD1, cs=PTD0)
+
+  * MMA7660 (I2C):
+      * LPC1*: (SDA=p28 , SCL=p27)
+
+  * i2c_loop:
+      * LPC1768: (p28 <-> p9), (p27 <-> p10)
+      * NUCLEO64: (D14 <-> D3), (D15 <-> D6)
+      * NUCLEO144: (D14 <-> PB_11), (D15 <-> PB_10)
+
+  * i2c_eeprom:
+      * LPC1*: (SDA=p28 , SCL=p27)
+      * KL25Z: (SDA=PTE0, SCL=PTE1)
+      * VK_RZ_A1H:(SDA=P1_1, SCL=P1_0)
+
+  * can_transceiver:
+     * LPC1768: (RX=p9,   TX=p10)
+     * LPC1549: (RX=D9,   TX=D8)
+     * LPC4088: (RX=p9,   TX=p10)
+     * VK_RZ_A1H:(RX=P5_9, TX=P5_10)
+     * NUCLEO_F091RC: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F072RB: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F042K6: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F334R8: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F303RE: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F303K8: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F302R8: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F446RE: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F446ZE: (RX=PA_11, TX=PA_12)
+     * DISCO_F469NI:  (RX=PB_8, TX=PB_9)
+     * DISCO_F4269ZI: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F103RB: (RX=PA_11, TX=PA_12)
+     * NUCLEO_F746ZG: (RX=PA_11, TX=PA_12)
+     * DISCO_F746NG:  (RX=PB_8, TX=PB_9)
+     * DISCO_L475VG_IOT01A:  (RX=PA_11, TX=PA_12)
+     * DISCO_L476VG:  (RX=PA_11, TX=PA_12)
+     * NUCLEO_L476RG: (RX=PA_11, TX=PA_12)
+     * NUCLEO_L432KC: (RX=PA_11, TX=PA_12)
+     * DISCO_F303VC:  (RX=PA_11, TX=PA_12)
+     * NUCLEO_F412ZG: (RX=PA_11, TX=PA_12)
+
+"""
+TESTS = [
+    # Automated MBED tests
+    {
+        "id": "MBED_A1", "description": "Basic",
+        "source_dir": join(TEST_DIR, "mbed", "basic"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+    },
+    {
+        "id": "MBED_A2", "description": "Semihost file system",
+        "source_dir": join(TEST_DIR, "mbed", "file"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "mcu": ["LPC1768", "LPC11U24"]
+    },
+    {
+        "id": "MBED_A3", "description": "C++ STL",
+        "source_dir": join(TEST_DIR, "mbed", "stl"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": False,
+    },
+    {
+        "id": "MBED_A4", "description": "I2C TMP102",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_TMP102"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, TMP102],
+        "automated": True,
+        "peripherals": ["TMP102"]
+    },
+    {
+        "id": "MBED_AT30TSE75X", "description": "I2C Temperature Sensor / EEPROM",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_at30tse75x"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, AT30TSE75X],
+        "automated": False,
+        "peripherals": ["AT30TSE75X"]
+    },
+    {
+        "id": "MBED_A5", "description": "DigitalIn DigitalOut",
+        "source_dir": join(TEST_DIR, "mbed", "digitalin_digitalout"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "peripherals": ["digital_loop"]
+    },
+    {
+        "id": "MBED_A6", "description": "DigitalInOut",
+        "source_dir": join(TEST_DIR, "mbed", "digitalinout"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "peripherals": ["digital_loop"]
+    },
+    {
+        "id": "MBED_A7", "description": "InterruptIn",
+        "source_dir": join(TEST_DIR, "mbed", "interruptin"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "peripherals": ["digital_loop"]
+    },
+    {
+        "id": "MBED_A8", "description": "Analog",
+        "source_dir": join(TEST_DIR, "mbed", "analog"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "peripherals": ["analog_loop"],
+        "mcu": ["LPC1768", "KL25Z", "K64F", "K66F", "K22F", "LPC4088", "LPC1549",
+                "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303K8", "NUCLEO_F303RE", "NUCLEO_F207ZG",
+                "NUCLEO_F334R8", "NUCLEO_F303ZE", "NUCLEO_L053R8", "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_L152RE",
+                "NUCLEO_F410RB", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F429ZI",
+                "DISCO_F407VG", "NUCLEO_F746ZG", "NUCLEO_L476RG",
+                "DISCO_L053C8", "DISCO_F334C8", "DISCO_L475VG_IOT01A", "DISCO_L476VG", "DISCO_F469NI", "DISCO_F429ZI", "DISCO_F769NI",
+                "ARCH_MAX", "MAX32600MBED", "MOTE_L152RC", "B96B_F446VE"]
+    },
+    {
+        "id": "MBED_A9", "description": "Serial Echo at 115200",
+        "source_dir": join(TEST_DIR, "mbed", "echo"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "echo"
+    },
+    {
+        "id": "MBED_A10", "description": "PortOut PortIn",
+        "source_dir": join(TEST_DIR, "mbed", "portout_portin"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "peripherals": ["port_loop"],
+        "supported": DEFAULT_SUPPORT,
+        "automated": True,
+    },
+    {
+        "id": "MBED_A11", "description": "PortInOut",
+        "source_dir": join(TEST_DIR, "mbed", "portinout"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "peripherals": ["port_loop"],
+        "supported": DEFAULT_SUPPORT,
+        "automated": True,
+    },
+    {
+        "id": "MBED_A13", "description": "I2C MMA7660 accelerometer",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_MMA7660"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'MMA7660')],
+        "automated": True,
+        "peripherals": ["MMA7660"]
+    },
+    {
+        "id": "MBED_A14", "description": "I2C Master",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_master"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
+    },
+    {
+        "id": "MBED_A15", "description": "I2C Slave",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_slave"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
+    },
+    {
+        "id": "MBED_A16", "description": "SPI Master",
+        "source_dir": join(TEST_DIR, "mbed", "spi_master"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
+    },
+    {
+        "id": "MBED_A17", "description": "SPI Slave",
+        "source_dir": join(TEST_DIR, "mbed", "spi_slave"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
+    },
+    {
+        "id": "MBED_A18", "description": "Interrupt vector relocation",
+        "source_dir": join(TEST_DIR, "mbed", "vtor_reloc"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
+        "mcu": ["LPC1768"],
+        "automated": True,
+    },
+    {
+        "id": "MBED_A19", "description": "I2C EEPROM read/write test",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_eeprom"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "peripherals": ["24LC256"],
+        "automated": True,
+    },
+    {
+        "id": "MBED_A20", "description": "I2C master/slave test",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_master_slave"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
+        "automated": True,
+        "peripherals": ["i2c_loop"]
+    },
+    {
+        "id": "MBED_A21", "description": "Call function before main (mbed_main)",
+        "source_dir": join(TEST_DIR, "mbed", "call_before_main"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+    },
+    {
+        "id": "MBED_A22", "description": "SPIFI for LPC4088 (test 1)",
+        "source_dir": join(TEST_DIR, "mbed", "spifi1"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "mcu": ["LPC4088","LPC4088_DM"]
+    },
+    {
+        "id": "MBED_A23", "description": "SPIFI for LPC4088 (test 2)",
+        "source_dir": join(TEST_DIR, "mbed", "spifi2"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "mcu": ["LPC4088","LPC4088_DM"]
+    },
+    {
+        "id": "MBED_A24", "description": "Serial echo with RTS/CTS flow control",
+        "source_dir": join(TEST_DIR, "mbed", "echo_flow_control"),
+        "dependencies": [MBED_LIBRARIES],
+        "automated": "True",
+        "host_test": "echo_flow_control",
+        "mcu": ["LPC1768"],
+        "peripherals": ["extra_serial"]
+    },
+    {
+        "id": "MBED_A25", "description": "I2C EEPROM line read/write test",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_eeprom_line"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "peripherals": ["24LC256"],
+        "automated": True,
+    },
+    {
+        "id": "MBED_A26", "description": "AnalogIn potentiometer test",
+        "source_dir": join(TEST_DIR, "mbed", "analog_pot"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "peripherals": ["analog_pot"],
+        "automated": True,
+    },
+    {
+        "id": "MBED_A27", "description": "CAN loopback test",
+        "source_dir": join(TEST_DIR, "mbed", "can_loopback"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "peripherals": ["can_transceiver"],
+        "mcu": ["LPC1549", "LPC1768","B96B_F446VE", "VK_RZ_A1H",
+                "NUCLEO_F091RC", "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F207ZG",
+        "NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE",
+        "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG",
+        "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC",
+        "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG",
+        "DISCO_F413ZH"]
+    },
+    {
+        "id": "MBED_A28", "description": "CAN loopback test",
+        "source_dir": join(TEST_DIR, "mbed", "can_loopback"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "mcu": ["B96B_F446VE",
+                "NUCLEO_F091RC", "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F207ZG",
+        "NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F446RE","NUCLEO_F446ZE",
+        "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG",
+
+        "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC",
+        "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG",
+        "DISCO_F413ZH"]
+    },
+    {
+        "id": "MBED_A29", "description": "i2c_master_slave_asynch",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_master_slave_asynch"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "peripherals": ["i2c_loop"]
+    },
+    {
+        "id": "MBED_A30", "description": "CAN API",
+        "source_dir": join(TEST_DIR, "mbed", "can_api"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "mcu": ["LPC1549", "LPC1768","B96B_F446VE", "VK_RZ_A1H",
+                "NUCLEO_F091RC", "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F207ZG",
+                "NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F303ZE", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE",
+                "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG",
+                "NUCLEO_F429ZI", "NUCLEO_F439ZI", "NUCLEO_F756ZG", "NUCLEO_L486RG",
+                "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC",
+                "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG"]
+    },
+    {
+        "id": "MBED_BLINKY", "description": "Blinky",
+        "source_dir": join(TEST_DIR, "mbed", "blinky"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": False,
+    },
+    {
+        "id": "MBED_BUS", "description": "Blinky BUS",
+        "source_dir": join(TEST_DIR, "mbed", "bus"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": False,
+    },
+
+    {
+        "id": "MBED_BUSOUT", "description": "BusOut",
+        "source_dir": join(TEST_DIR, "mbed", "bus_out"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "exclude_mcu": ["NUCLEO_L011K4"],
+        "automated": True,
+    },
+
+    # Size benchmarks
+    {
+        "id": "BENCHMARK_1", "description": "Size (c environment)",
+        "source_dir": join(BENCHMARKS_DIR, "cenv"),
+        "dependencies": [MBED_LIBRARIES]
+    },
+    {
+        "id": "BENCHMARK_2", "description": "Size (float math)",
+        "source_dir": join(BENCHMARKS_DIR, "float_math"),
+        "dependencies": [MBED_LIBRARIES]
+    },
+    {
+        "id": "BENCHMARK_3", "description": "Size (printf)",
+        "source_dir": join(BENCHMARKS_DIR, "printf"),
+        "dependencies": [MBED_LIBRARIES]
+    },
+    {
+        "id": "BENCHMARK_4", "description": "Size (mbed libs)",
+        "source_dir": join(BENCHMARKS_DIR, "mbed"),
+        "dependencies": [MBED_LIBRARIES]
+    },
+    {
+        "id": "BENCHMARK_5", "description": "Size (all)",
+        "source_dir": join(BENCHMARKS_DIR, "all"),
+        "dependencies": [MBED_LIBRARIES]
+    },
+
+
+    # Not automated MBED tests
+    {
+        "id": "MBED_1", "description": "I2C SRF08",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_SRF08"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'SRF08')],
+        "peripherals": ["SRF08"]
+    },
+    {
+        "id": "MBED_2", "description": "stdio",
+        "source_dir": join(TEST_DIR, "mbed", "stdio"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "stdio_auto"
+    },
+    {
+        "id": "MBED_3", "description": "PortOut",
+        "source_dir": join(TEST_DIR, "mbed", "portout"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_4", "description": "Sleep",
+        "source_dir": join(TEST_DIR, "mbed", "sleep"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "mcu": ["LPC1768", "LPC11U24", "LPC4088","LPC4088_DM","NRF51822", "LPC11U68"]
+    },
+    {
+        "id": "MBED_5", "description": "PWM",
+        "source_dir": join(TEST_DIR, "mbed", "pwm"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB]
+    },
+    {
+        "id": "MBED_6", "description": "SW Reset",
+        "source_dir": join(TEST_DIR, "mbed", "reset"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_7", "description": "stdio  benchmark",
+        "source_dir": join(TEST_DIR, "mbed", "stdio_benchmark"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_8", "description": "SPI",
+        "source_dir": join(TEST_DIR, "mbed", "spi"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_9", "description": "Sleep Timeout",
+        "source_dir": join(TEST_DIR, "mbed", "sleep_timeout"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_10", "description": "Hello World",
+        "source_dir": join(TEST_DIR, "mbed", "hello"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "hello_auto",
+    },
+    {
+        "id": "MBED_11", "description": "Ticker Int",
+        "source_dir": join(TEST_DIR, "mbed", "ticker"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "wait_us_auto",
+    },
+    {
+        "id": "MBED_12", "description": "C++",
+        "source_dir": join(TEST_DIR, "mbed", "cpp"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True
+    },
+    {
+        "id": "MBED_13", "description": "Heap & Stack",
+        "source_dir": join(TEST_DIR, "mbed", "heap_and_stack"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+    },
+    {
+        "id": "MBED_14", "description": "Serial Interrupt",
+        "source_dir": join(TEST_DIR, "mbed", "serial_interrupt"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+    },
+    {
+        "id": "MBED_15", "description": "RPC",
+        "source_dir": join(TEST_DIR, "mbed", "rpc"),
+        "dependencies": [MBED_LIBRARIES, join(LIB_DIR, "rpc"), TEST_MBED_LIB],
+        "automated": False,
+        "mcu": ["LPC1768"]
+    },
+    {
+        "id": "MBED_16", "description": "RTC",
+        "source_dir": join(TEST_DIR, "mbed", "rtc"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "exclude_mcu": ["NRF51822", "NRF51822_BOOT", "NRF51822_OTA", "NRF51822_Y5_MBUG",
+                        "NRF51_DK", "NRF51_DK_BOOT", "NRF51_DK_OTA",
+                        "NRF51_MICROBIT", "NRF51_MICROBIT_B", "NRF51_MICROBIT_BOOT",
+                        "NRF51_MICROBIT_B_BOOT", "NRF51_MICROBIT_B_OTA", "NRF51_MICROBIT_OTA",
+                        "HRM1017", "HRM1017_BOOT", "HRM1701_OTA",
+                        "NUCLEO_L011K4",
+                        "TY51822R3", "TY51822R3_BOOT", "TY51822R3_OTA",
+                        "NRF15_DONGLE", "NRF15_DONGLE_BOOT", "NRF15_DONGLE_OTA",
+                        "ARCH_BLE", "ARCH_BLE_BOOT", "ARCH_BLE_OTA",
+                        "ARCH_LINK", "ARCH_LINK_BOOT", "ARCH_LINK_OTA",
+                        "RBLAB_BLENANO", "RBLAB_BLENANO_BOOT", "RBLAB_BLENANO_OTA",
+                        "RBLAB_NRF51822", "RBLAB_NRF51822_BOOT", "RBLAB_NRF51822_OTA",
+                        "SEEED_TINY_BLE", "SEEED_TINY_BLE_BOOT", "SEEED_TINY_BLE_OTA",
+                        "WALLBOT_BLE", "WALLBOT_BLE_BOOT", "WALLBOT_BLE_OTA",
+                        "DELTA_DFCM_NNN40", "DELTA_DFCM_NNN40_BOOT", "DELTA_DFCM_NNN40_OTA",
+                        "LPC1114"],
+        #"host_test": "rtc_auto",
+    },
+    {
+        "id": "MBED_17", "description": "Serial Interrupt 2",
+        "source_dir": join(TEST_DIR, "mbed", "serial_interrupt_2"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_18", "description": "Local FS Directory",
+        "source_dir": join(TEST_DIR, "mbed", "dir"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_20", "description": "InterruptIn 2",
+        "source_dir": join(TEST_DIR, "mbed", "interruptin_2"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_21", "description": "freopen Stream",
+        "source_dir": join(TEST_DIR, "mbed", "freopen"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_22", "description": "Semihost",
+        "source_dir": join(TEST_DIR, "mbed", "semihost"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        "mcu": ["LPC1768", "LPC11U24"]
+    },
+    {
+        "id": "MBED_23", "description": "Ticker Int us",
+        "source_dir": join(TEST_DIR, "mbed", "ticker_2"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "wait_us_auto"
+    },
+    {
+        "id": "MBED_24", "description": "Timeout Int us",
+        "source_dir": join(TEST_DIR, "mbed", "timeout"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "wait_us_auto"
+    },
+    {
+        "id": "MBED_25", "description": "Time us",
+        "source_dir": join(TEST_DIR, "mbed", "time_us"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "wait_us_auto"
+    },
+    {
+        "id": "MBED_26", "description": "Integer constant division",
+        "source_dir": join(TEST_DIR, "mbed", "div"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+    },
+    {
+        "id": "MBED_27", "description": "SPI ADXL345",
+        "source_dir": join(TEST_DIR, "mbed", "spi_ADXL345"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'ADXL345')],
+        "peripherals": ["ADXL345"]
+    },
+    {
+        "id": "MBED_28", "description": "Interrupt chaining (InterruptManager)",
+        "source_dir": join(TEST_DIR, "mbed", "interrupt_chaining"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+    },
+    {
+        "id": "MBED_29", "description": "CAN network test",
+        "source_dir": join(TEST_DIR, "mbed", "can"),
+        "dependencies": [MBED_LIBRARIES],
+        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "B96B_F446VE", "NUCLEO_F091RC",
+                "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F303RE",
+                "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE", "DISCO_F469NI", "NUCLEO_F207ZG",
+                "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG",
+                "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG",
+                "DISCO_F413ZH"]
+    },
+    {
+        "id": "MBED_30", "description": "CAN network test using interrupts",
+        "source_dir": join(TEST_DIR, "mbed", "can_interrupt"),
+        "dependencies": [MBED_LIBRARIES],
+        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "B96B_F446VE", "NUCLEO_F091RC", "NUCLEO_F207ZG",
+                "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F303RE",
+                "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE", "NUCLEO_F446ZE", "DISCO_F469NI",
+                "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG",
+                "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG",
+                "DISCO_F413ZH"]
+    },
+    {
+        "id": "MBED_31", "description": "PWM LED test",
+        "source_dir": join(TEST_DIR, "mbed", "pwm_led"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_32", "description": "Pin toggling",
+        "source_dir": join(TEST_DIR, "mbed", "pin_toggling"),
+        "dependencies": [MBED_LIBRARIES],
+    },
+    {
+        "id": "MBED_33", "description": "C string operations",
+        "source_dir": join(TEST_DIR, "mbed", "cstring"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": False,
+    },
+    {
+        "id": "MBED_34", "description": "Ticker Two callbacks",
+        "source_dir": join(TEST_DIR, "mbed", "ticker_3"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test": "wait_us_auto"
+    },
+    {
+        "id": "MBED_35", "description": "SPI C12832 display",
+        "source_dir": join(TEST_DIR, "mbed", "spi_C12832"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'C12832')],
+        "peripherals": ["C12832"],
+        "automated": True,
+    },
+    {
+        "id": "MBED_36", "description": "WFI correct behavior",
+        "source_dir": join(TEST_DIR, "mbed", "wfi"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": False
+    },
+    {
+        "id": "MBED_37", "description": "Serial NC RX",
+        "source_dir": join(TEST_DIR, "mbed", "serial_nc_rx"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "exclude_mcu": ["NUCLEO_L011K4"],
+        "automated": True
+    },
+    {
+        "id": "MBED_38", "description": "Serial NC TX",
+        "source_dir": join(TEST_DIR, "mbed", "serial_nc_tx"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "exclude_mcu": ["NUCLEO_L011K4"],
+        "automated": True
+    },
+    {
+        "id": "MBED_39", "description": "Serial Complete",
+        "source_dir": join(TEST_DIR, "mbed", "serial_complete"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": False
+    },
+
+    # USB Tests 
+    # USB device test list
+    {
+        "id": "USB_1", "description": "Mouse",
+        "source_dir": join(TEST_DIR, "usb", "device", "basic"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+    {
+        "id": "USB_2", "description": "Keyboard",
+        "source_dir": join(TEST_DIR, "usb", "device", "keyboard"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+    {
+        "id": "USB_3", "description": "Mouse_Keyboard",
+        "source_dir": join(TEST_DIR, "usb", "device", "keyboard"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+    {
+        "id": "USB_4", "description": "Serial Port",
+        "source_dir": join(TEST_DIR, "usb", "device", "serial"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+    {
+        "id": "USB_5", "description": "Generic HID",
+        "source_dir": join(TEST_DIR, "usb", "device", "raw_hid"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+    {
+        "id": "USB_6", "description": "MIDI",
+        "source_dir": join(TEST_DIR, "usb", "device", "midi"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+    {
+        "id": "USB_7", "description": "AUDIO",
+        "source_dir": join(TEST_DIR, "usb", "device", "audio"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+    {
+        "id": "USB_8", "description": "AUDIO_CB",
+        "source_dir": join(TEST_DIR, "usb", "device", "audio_cb"),
+        "dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
+    },
+
+    # CMSIS DSP
+    {
+        "id": "CMSIS_DSP_1", "description": "FIR",
+        "source_dir": join(TEST_DIR, "dsp", "cmsis", "fir_f32"),
+        "dependencies": [MBED_LIBRARIES, DSP_LIBRARIES],
+    },
+
+    # mbed DSP
+    {
+        "id": "DSP_1", "description": "FIR",
+        "source_dir": join(TEST_DIR, "dsp", "mbed", "fir_f32"),
+        "dependencies": [MBED_LIBRARIES, DSP_LIBRARIES],
+    },
+
+    # KL25Z
+    {
+        "id": "KL25Z_1", "description": "LPTMR",
+        "source_dir": join(TEST_DIR, "KL25Z", "lptmr"),
+        "dependencies": [MBED_LIBRARIES],
+        "supported": CORTEX_ARM_SUPPORT,
+        "mcu": ["KL25Z"],
+    },
+    {
+        "id": "KL25Z_2", "description": "PIT",
+        "source_dir": join(TEST_DIR, "KL25Z", "pit"),
+        "dependencies": [MBED_LIBRARIES],
+        "supported": CORTEX_ARM_SUPPORT,
+        "mcu": ["KL25Z"],
+    },
+    {
+        "id": "KL25Z_3", "description": "TSI Touch Sensor",
+        "source_dir": join(TEST_DIR, "mbed", "tsi"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'TSI')],
+        "mcu": ["KL25Z"],
+    },
+    {
+        "id": "KL25Z_4", "description": "RTC",
+        "source_dir": join(TEST_DIR, "KL25Z", "rtc"),
+        "dependencies": [MBED_LIBRARIES],
+        "mcu": ["KL25Z"],
+    },
+    {
+        "id": "KL25Z_5", "description": "MMA8451Q accelerometer",
+        "source_dir": join(TEST_DIR, "mbed", "i2c_MMA8451Q"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'MMA8451Q')],
+        "mcu": ["KL25Z", "KL05Z", "KL46Z", "K20D50M"],
+        "automated": True,
+        },
+
+    # Examples
+    {
+        "id": "EXAMPLE_1", "description": "/dev/null",
+        "source_dir": join(TEST_DIR, "mbed", "dev_null"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "exclude_mcu": ["NUCLEO_L011K4"],
+        "automated": True,
+        #"host_test" : "dev_null_auto",
+    },
+
+    # CPPUTEST Library provides Unit testing Framework
+    #
+    # To write TESTs and TEST_GROUPs please add CPPUTEST_LIBRARY to 'dependencies'
+    #
+    # This will also include:
+    # 1. test runner - main function with call to CommandLineTestRunner::RunAllTests(ac, av)
+    # 2. Serial console object to print test result on serial port console
+    #
+
+    # Unit testing with cpputest library
+    {
+        "id": "UT_1", "description": "Basic",
+        "source_dir": join(TEST_DIR, "utest", "basic"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+    },
+    {
+        "id": "UT_2", "description": "Semihost file system",
+        "source_dir": join(TEST_DIR, "utest", "semihost_fs"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+        "mcu": ["LPC1768", "LPC11U24"]
+    },
+    {
+        "id": "UT_3", "description": "General tests",
+        "source_dir": join(TEST_DIR, "utest", "general"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+    },
+    {
+        "id": "UT_BUSIO", "description": "BusIn BusOut",
+        "source_dir": join(TEST_DIR, "utest", "bus"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+    },
+    {
+        "id": "UT_I2C_EEPROM_ASYNCH", "description": "I2C Asynch eeprom",
+        "source_dir": join(TEST_DIR, "utest", "i2c_eeprom_asynch"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+    },
+    {
+        "id": "UT_SERIAL_ASYNCH", "description": "Asynch serial test (req 2 serial peripherals)",
+        "source_dir": join(TEST_DIR, "utest", "serial_asynch"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+    },
+    {
+        "id": "UT_SPI_ASYNCH", "description": "Asynch spi test",
+        "source_dir": join(TEST_DIR, "utest", "spi_asynch"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+    },
+    {
+        "id": "UT_LP_TICKER", "description": "Low power ticker test",
+        "source_dir": join(TEST_DIR, "utest", "lp_ticker"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+        "automated": False,
+    },
+
+    # Tests used for target information purposes
+    {
+        "id": "DTCT_1", "description": "Simple detect test",
+        "source_dir": join(TEST_DIR, "mbed", "detect"),
+        "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
+        "automated": True,
+        #"host_test" : "detect_auto",
+    },
+
+]
+
+# Group tests with the same goals into categories
+GROUPS = {
+    "core": ["MBED_A1", "MBED_A2", "MBED_A3", "MBED_A18"],
+    "digital_io": ["MBED_A5", "MBED_A6", "MBED_A7", "MBED_A10", "MBED_A11"],
+    "analog_io": ["MBED_A8"],
+    "i2c": ["MBED_A19", "MBED_A20"],
+    "spi": ["MBED_A12"],
+}
+
+GROUPS["automated"] = [test["id"] for test in TESTS if test.get("automated", False)]
+# Look for 'TEST_GROUPS' in mbed_settings.py and update the GROUPS dictionary
+# with the information in test_groups if found
+try:
+    from mbed_settings import TEST_GROUPS
+except:
+    TEST_GROUPS = {}
+GROUPS.update(TEST_GROUPS)
+
+class Test:
+    DEFAULTS = {
+        #'mcu': None,
+        'description': None,
+        'dependencies': None,
+        'duration': 30,
+        'host_test': 'host_test',
+        'automated': False,
+        'peripherals': None,
+        #'supported': None,
+        'source_dir': None,
+        'extra_files': None
+    }
+    def __init__(self, n):
+        self.n = n
+        self.__dict__.update(Test.DEFAULTS)
+        self.__dict__.update(TESTS[n])
+
+    def is_supported(self, target, toolchain):
+        if hasattr(self, 'mcu') and not target in self.mcu:
+            return False
+        if hasattr(self, 'exclude_mcu') and target in self.exclude_mcu:
+            return False
+        if not hasattr(self, 'supported'):
+            return True
+        return (target in self.supported) and (toolchain in self.supported[target])
+
+    def get_description(self):
+        if self.description:
+            return self.description
+        else:
+            return self.id
+
+    def __cmp__(self, other):
+        return cmp(self.n, other.n)
+
+    def __str__(self):
+        return "[%3d] %s: %s" % (self.n, self.id, self.get_description())
+
+    def __getitem__(self, key):
+        if key == "id": return self.id
+        elif key == "mcu": return self.mcu
+        elif key == "exclude_mcu": return self.exclude_mcu
+        elif key == "dependencies": return self.dependencies
+        elif key == "description": return self.description
+        elif key == "duration": return self.duration
+        elif key == "host_test": return self.host_test
+        elif key == "automated": return self.automated
+        elif key == "peripherals": return self.peripherals
+        elif key == "supported": return self.supported
+        elif key == "source_dir": return self.source_dir
+        elif key == "extra_files": return self.extra_files
+        else:
+            return None
+
+TEST_MAP = dict([(test['id'], Test(i)) for i, test in enumerate(TESTS)])
+
+# parser helpers
+def test_known(string):
+    i = int(string)
+    if i >= 0 and i < len(TESTS):
+        return i
+    else:
+        raise ArgumentTypeError("{0} does not index a test. The accepted range is 0 to {1}\nThe test mapping is:\n{2}".format(i, len(TEST_MAP) - 1, columnate([str(i) + ":" + t['id'] for i,t in zip(range(len(TESTS)), TESTS)])))
+
+def test_name_known(string):
+    if string not in TEST_MAP.keys() and \
+       (getattr(ps, "test_alias", None) is None or \
+        ps.test_alias.get(string, "") not in TEST_MAP.keys()):
+        raise ArgumentTypeError("Program with name '{0}' not found. Supported tests are: \n{1}".format(string, columnate([t['id'] for t in TESTS])))
+
+    return TEST_MAP[string].n
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/tests.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/tests.pyc
new file mode 100755
index 0000000..b57371f
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/tests.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/__init__.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/__init__.py
new file mode 100755
index 0000000..0df5023
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/__init__.py
@@ -0,0 +1,1593 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import re
+import sys
+from os import stat, walk, getcwd, sep, remove
+from copy import copy
+from time import time, sleep
+from types import ListType
+from shutil import copyfile
+from os.path import join, splitext, exists, relpath, dirname, basename, split, abspath, isfile, isdir, normcase
+from itertools import chain
+from inspect import getmro
+from copy import deepcopy
+from abc import ABCMeta, abstractmethod
+from distutils.spawn import find_executable
+
+from multiprocessing import Pool, cpu_count
+from tools.utils import run_cmd, mkdir, rel_path, ToolException, NotSupportedException, split_path, compile_worker
+from tools.settings import MBED_ORG_USER
+import tools.hooks as hooks
+from tools.memap import MemapParser
+from hashlib import md5
+import fnmatch
+
+
+#Disables multiprocessing if set to higher number than the host machine CPUs
+CPU_COUNT_MIN = 1
+CPU_COEF = 1
+
+class LazyDict(dict):
+    def __init__(self):
+        self.eager = {}
+        self.lazy = {}
+
+    def add_lazy(self, key, thunk):
+        if key in self.eager:
+            del self.eager[key]
+        self.lazy[key] = thunk
+
+    def __getitem__(self, key):
+        if  (key not in self.eager
+             and key in self.lazy):
+            self.eager[key] = self.lazy[key]()
+            del self.lazy[key]
+        return self.eager[key]
+
+    def __setitem__(self, key, value):
+        self.eager[key] = value
+
+    def __delitem__(self, key):
+        if key in self.eager:
+            del self.eager[key]
+        else:
+            del self.lazy[key]
+
+    def __contains__(self, key):
+        return key in self.eager or key in self.lazy
+
+    def __iter__(self):
+        return chain(iter(self.eager), iter(self.lazy))
+
+    def __len__(self):
+        return len(self.eager) + len(self.lazy)
+
+    def __str__(self):
+        return "Lazy{%s}" % (
+            ", ".join("%r: %r" % (k, v) for k, v in
+                      chain(self.eager.iteritems(), ((k, "not evaluated")
+                                                     for k in self.lazy))))
+
+    def update(self, other):
+        if isinstance(other, LazyDict):
+            self.eager.update(other.eager)
+            self.lazy.update(other.lazy)
+        else:
+            self.eager.update(other)
+
+    def iteritems(self):
+        """Warning: This forces the evaluation all of the items in this LazyDict
+        that are iterated over."""
+        for k, v in self.eager.iteritems():
+            yield k, v
+        for k in self.lazy.keys():
+            yield k, self[k]
+
+    def apply(self, fn):
+        """Delay the application of a computation to all items of the lazy dict.
+        Does no computation now. Instead the comuptation is performed when a
+        consumer attempts to access a value in this LazyDict"""
+        new_lazy = {}
+        for k, f in self.lazy.iteritems():
+            def closure(f=f):
+                return fn(f())
+            new_lazy[k] = closure
+        for k, v in self.eager.iteritems():
+            def closure(v=v):
+                return fn(v)
+            new_lazy[k] = closure
+        self.lazy = new_lazy
+        self.eager = {}
+
+class Resources:
+    def __init__(self, base_path=None, collect_ignores=False):
+        self.base_path = base_path
+        self.collect_ignores = collect_ignores
+
+        self.file_basepath = {}
+
+        self.inc_dirs = []
+        self.headers = []
+
+        self.s_sources = []
+        self.c_sources = []
+        self.cpp_sources = []
+
+        self.lib_dirs = set([])
+        self.objects = []
+        self.libraries = []
+
+        # mbed special files
+        self.lib_builds = []
+        self.lib_refs = []
+
+        self.repo_dirs = []
+        self.repo_files = []
+
+        self.linker_script = None
+
+        # Other files
+        self.hex_files = []
+        self.bin_files = []
+        self.json_files = []
+
+        # Features
+        self.features = LazyDict()
+        self.ignored_dirs = []
+
+    def __add__(self, resources):
+        if resources is None:
+            return self
+        else:
+            return self.add(resources)
+
+    def __radd__(self, resources):
+        if resources is None:
+            return self
+        else:
+            return self.add(resources)
+
+    def ignore_dir(self, directory):
+        if self.collect_ignores:
+            self.ignored_dirs.append(directory)
+
+    def add(self, resources):
+        for f,p in resources.file_basepath.items():
+            self.file_basepath[f] = p
+
+        self.inc_dirs += resources.inc_dirs
+        self.headers += resources.headers
+
+        self.s_sources += resources.s_sources
+        self.c_sources += resources.c_sources
+        self.cpp_sources += resources.cpp_sources
+
+        self.lib_dirs |= resources.lib_dirs
+        self.objects += resources.objects
+        self.libraries += resources.libraries
+
+        self.lib_builds += resources.lib_builds
+        self.lib_refs += resources.lib_refs
+
+        self.repo_dirs += resources.repo_dirs
+        self.repo_files += resources.repo_files
+
+        if resources.linker_script is not None:
+            self.linker_script = resources.linker_script
+
+        self.hex_files += resources.hex_files
+        self.bin_files += resources.bin_files
+        self.json_files += resources.json_files
+
+        self.features.update(resources.features)
+        self.ignored_dirs += resources.ignored_dirs
+
+        return self
+
+    def _collect_duplicates(self, dupe_dict, dupe_headers):
+        for filename in self.s_sources + self.c_sources + self.cpp_sources:
+            objname, _ = splitext(basename(filename))
+            dupe_dict.setdefault(objname, set())
+            dupe_dict[objname] |= set([filename])
+        for filename in self.headers:
+            headername = basename(filename)
+            dupe_headers.setdefault(headername, set())
+            dupe_headers[headername] |= set([headername])
+        for res in self.features.values():
+            res._collect_duplicates(dupe_dict, dupe_headers)
+        return dupe_dict, dupe_headers
+
+    def detect_duplicates(self, toolchain):
+        """Detect all potential ambiguities in filenames and report them with
+        a toolchain notification
+
+        Positional Arguments:
+        toolchain - used for notifications
+        """
+        count = 0
+        dupe_dict, dupe_headers = self._collect_duplicates(dict(), dict())
+        for objname, filenames in dupe_dict.iteritems():
+            if len(filenames) > 1:
+                count+=1
+                toolchain.tool_error(
+                    "Object file %s.o is not unique! It could be made from: %s"\
+                    % (objname, " ".join(filenames)))
+        for headername, locations in dupe_headers.iteritems():
+            if len(locations) > 1:
+                count+=1
+                toolchain.tool_error(
+                    "Header file %s is not unique! It could be: %s" %\
+                    (headername, " ".join(locations)))
+        return count
+
+
+    def relative_to(self, base, dot=False):
+        for field in ['inc_dirs', 'headers', 's_sources', 'c_sources',
+                      'cpp_sources', 'lib_dirs', 'objects', 'libraries',
+                      'lib_builds', 'lib_refs', 'repo_dirs', 'repo_files',
+                      'hex_files', 'bin_files', 'json_files']:
+            v = [rel_path(f, base, dot) for f in getattr(self, field)]
+            setattr(self, field, v)
+
+        def to_apply(feature, base=base, dot=dot):
+            feature.relative_to(base, dot)
+        self.features.apply(to_apply)
+
+        if self.linker_script is not None:
+            self.linker_script = rel_path(self.linker_script, base, dot)
+
+    def win_to_unix(self):
+        for field in ['inc_dirs', 'headers', 's_sources', 'c_sources',
+                      'cpp_sources', 'lib_dirs', 'objects', 'libraries',
+                      'lib_builds', 'lib_refs', 'repo_dirs', 'repo_files',
+                      'hex_files', 'bin_files', 'json_files']:
+            v = [f.replace('\\', '/') for f in getattr(self, field)]
+            setattr(self, field, v)
+
+        def to_apply(feature):
+            feature.win_to_unix()
+        self.features.apply(to_apply)
+
+        if self.linker_script is not None:
+            self.linker_script = self.linker_script.replace('\\', '/')
+
+    def __str__(self):
+        s = []
+
+        for (label, resources) in (
+                ('Include Directories', self.inc_dirs),
+                ('Headers', self.headers),
+
+                ('Assembly sources', self.s_sources),
+                ('C sources', self.c_sources),
+                ('C++ sources', self.cpp_sources),
+
+                ('Library directories', self.lib_dirs),
+                ('Objects', self.objects),
+                ('Libraries', self.libraries),
+
+                ('Hex files', self.hex_files),
+                ('Bin files', self.bin_files),
+
+                ('Features', self.features),
+            ):
+            if resources:
+                s.append('%s:\n  ' % label + '\n  '.join(resources))
+
+        if self.linker_script:
+            s.append('Linker Script: ' + self.linker_script)
+
+        return '\n'.join(s)
+
+# Support legacy build conventions: the original mbed build system did not have
+# standard labels for the "TARGET_" and "TOOLCHAIN_" specific directories, but
+# had the knowledge of a list of these directories to be ignored.
+LEGACY_IGNORE_DIRS = set([
+    'LPC11U24', 'LPC1768', 'LPC2368', 'LPC4088', 'LPC812', 'KL25Z',
+    'ARM', 'uARM', 'IAR',
+    'GCC_ARM', 'GCC_CS', 'GCC_CR', 'GCC_CW', 'GCC_CW_EWL', 'GCC_CW_NEWLIB',
+    'ARMC6'
+])
+LEGACY_TOOLCHAIN_NAMES = {
+    'ARM_STD':'ARM', 'ARM_MICRO': 'uARM',
+    'GCC_ARM': 'GCC_ARM', 'GCC_CR': 'GCC_CR',
+    'IAR': 'IAR',
+    'ARMC6': 'ARMC6',
+}
+
+
+class mbedToolchain:
+    # Verbose logging
+    VERBOSE = True
+
+    # Compile C files as CPP
+    COMPILE_C_AS_CPP = False
+
+    # Response files for compiling, includes, linking and archiving.
+    # Not needed on posix systems where the typical arg limit is 2 megabytes
+    RESPONSE_FILES = True
+
+    CORTEX_SYMBOLS = {
+        "Cortex-M0" : ["__CORTEX_M0", "ARM_MATH_CM0", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M0+": ["__CORTEX_M0PLUS", "ARM_MATH_CM0PLUS", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M1" : ["__CORTEX_M3", "ARM_MATH_CM1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M3" : ["__CORTEX_M3", "ARM_MATH_CM3", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M4" : ["__CORTEX_M4", "ARM_MATH_CM4", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M4F" : ["__CORTEX_M4", "ARM_MATH_CM4", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M7" : ["__CORTEX_M7", "ARM_MATH_CM7", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M7F" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M7FD" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-A9" : ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT", "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"],
+        "Cortex-M23-NS": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M23": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M33-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__DOMAIN_NS=1", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M33": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+    }
+
+    MBED_CONFIG_FILE_NAME="mbed_config.h"
+
+    PROFILE_FILE_NAME = ".profile"
+
+    __metaclass__ = ABCMeta
+
+    profile_template = {'common':[], 'c':[], 'cxx':[], 'asm':[], 'ld':[]}
+
+    def __init__(self, target, notify=None, macros=None, silent=False,
+                 extra_verbose=False, build_profile=None, build_dir=None):
+        self.target = target
+        self.name = self.__class__.__name__
+
+        # compile/assemble/link/binary hooks
+        self.hook = hooks.Hook(target, self)
+
+        # Toolchain flags
+        self.flags = deepcopy(build_profile or self.profile_template)
+
+        # System libraries provided by the toolchain
+        self.sys_libs = []
+
+        # User-defined macros
+        self.macros = macros or []
+
+        # Macros generated from toolchain and target rules/features
+        self.asm_symbols = None
+        self.cxx_symbols = None
+
+        # Labels generated from toolchain and target rules/features (used for selective build)
+        self.labels = None
+
+        # This will hold the initialized config object
+        self.config = None
+
+        # This will hold the configuration data (as returned by Config.get_config_data())
+        self.config_data = None
+
+        # This will hold the location of the configuration file or None if there's no configuration available
+        self.config_file = None
+
+        # Call guard for "get_config_data" (see the comments of get_config_data for details)
+        self.config_processed = False
+
+        # Non-incremental compile
+        self.build_all = False
+
+        # Build output dir
+        self.build_dir = build_dir
+        self.timestamp = time()
+
+        # Number of concurrent build jobs. 0 means auto (based on host system cores)
+        self.jobs = 0
+
+        # Ignore patterns from .mbedignore files
+        self.ignore_patterns = []
+        self._ignore_regex = re.compile("$^")
+
+        # Pre-mbed 2.0 ignore dirs
+        self.legacy_ignore_dirs = (LEGACY_IGNORE_DIRS | TOOLCHAINS) - set([target.name, LEGACY_TOOLCHAIN_NAMES[self.name]])
+
+        # Output notify function
+        # This function is passed all events, and expected to handle notification of the
+        # user, emit the events to a log, etc.
+        # The API for all notify methods passed into the notify parameter is as follows:
+        # def notify(Event, Silent)
+        # Where *Event* is a dict representing the toolchain event that was generated
+        #            e.g.: a compile succeeded, or a warning was emitted by the compiler
+        #                  or an application was linked
+        #       *Silent* is a boolean
+        if notify:
+            self.notify_fun = notify
+        elif extra_verbose:
+            self.notify_fun = self.print_notify_verbose
+        else:
+            self.notify_fun = self.print_notify
+
+        # Silent builds (no output)
+        self.silent = silent
+
+        # Print output buffer
+        self.output = str()
+
+        # uVisor spepcific rules
+        if 'UVISOR' in self.target.features and 'UVISOR_SUPPORTED' in self.target.extra_labels:
+            self.target.core = re.sub(r"F$", '', self.target.core)
+
+        # Stats cache is used to reduce the amount of IO requests to stat
+        # header files during dependency change. See need_update()
+        self.stat_cache = {}
+
+        # Used by the mbed Online Build System to build in chrooted environment
+        self.CHROOT = None
+
+        # Call post __init__() hooks before the ARM/GCC_ARM/IAR toolchain __init__() takes over
+        self.init()
+
+    # Used for post __init__() hooks
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def init(self):
+        return True
+
+    def get_output(self):
+        return self.output
+
+    def print_notify(self, event, silent=False):
+        """ Default command line notification
+        """
+        msg = None
+
+        if not self.VERBOSE and event['type'] == 'tool_error':
+            msg = event['message']
+
+        elif event['type'] in ['info', 'debug']:
+            msg = event['message']
+
+        elif event['type'] == 'cc':
+            event['severity'] = event['severity'].title()
+            event['file'] = basename(event['file'])
+            msg = '[%(severity)s] %(file)s@%(line)s,%(col)s: %(message)s' % event
+
+        elif event['type'] == 'progress':
+            if 'percent' in event:
+                msg = '{} [{:>5.1f}%]: {}'.format(event['action'].title(),
+                                                  event['percent'],
+                                                  basename(event['file']))
+            else:
+                msg = '{}: {}'.format(event['action'].title(),
+                                      basename(event['file']))
+
+        if msg:
+            if not silent:
+                print msg
+            self.output += msg + "\n"
+
+    def print_notify_verbose(self, event, silent=False):
+        """ Default command line notification with more verbose mode
+        """
+        if event['type'] in ['info', 'debug']:
+            self.print_notify(event, silent=silent) # standard handle
+
+        elif event['type'] == 'cc':
+            event['severity'] = event['severity'].title()
+            event['file'] = basename(event['file'])
+            event['mcu_name'] = "None"
+            event['target_name'] = event['target_name'].upper() if event['target_name'] else "Unknown"
+            event['toolchain_name'] = event['toolchain_name'].upper() if event['toolchain_name'] else "Unknown"
+            msg = '[%(severity)s] %(target_name)s::%(toolchain_name)s::%(file)s@%(line)s: %(message)s' % event
+            if not silent:
+                print msg
+            self.output += msg + "\n"
+
+        elif event['type'] == 'progress':
+            self.print_notify(event) # standard handle
+
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def notify(self, event):
+        """ Little closure for notify functions
+        """
+        event['toolchain'] = self
+        return self.notify_fun(event, self.silent)
+
+    def get_symbols(self, for_asm=False):
+        if for_asm:
+            if self.asm_symbols is None:
+                self.asm_symbols = []
+
+                # Cortex CPU symbols
+                if self.target.core in mbedToolchain.CORTEX_SYMBOLS:
+                    self.asm_symbols.extend(mbedToolchain.CORTEX_SYMBOLS[self.target.core])
+
+                # Add target's symbols
+                self.asm_symbols += self.target.macros
+                # Add extra symbols passed via 'macros' parameter
+                self.asm_symbols += self.macros
+            return list(set(self.asm_symbols))  # Return only unique symbols
+        else:
+            if self.cxx_symbols is None:
+                # Target and Toolchain symbols
+                labels = self.get_labels()
+                self.cxx_symbols = ["TARGET_%s" % t for t in labels['TARGET']]
+                self.cxx_symbols.extend(["TOOLCHAIN_%s" % t for t in labels['TOOLCHAIN']])
+
+                # Cortex CPU symbols
+                if self.target.core in mbedToolchain.CORTEX_SYMBOLS:
+                    self.cxx_symbols.extend(mbedToolchain.CORTEX_SYMBOLS[self.target.core])
+
+                # Symbols defined by the on-line build.system
+                self.cxx_symbols.extend(['MBED_BUILD_TIMESTAMP=%s' % self.timestamp, 'TARGET_LIKE_MBED', '__MBED__=1'])
+                if MBED_ORG_USER:
+                    self.cxx_symbols.append('MBED_USERNAME=' + MBED_ORG_USER)
+
+                # Add target's symbols
+                self.cxx_symbols += self.target.macros
+                # Add target's hardware
+                self.cxx_symbols += ["DEVICE_" + data + "=1" for data in self.target.device_has]
+                # Add target's features
+                self.cxx_symbols += ["FEATURE_" + data + "=1" for data in self.target.features]
+                # Add extra symbols passed via 'macros' parameter
+                self.cxx_symbols += self.macros
+
+                # Form factor variables
+                if hasattr(self.target, 'supported_form_factors'):
+                    self.cxx_symbols.extend(["TARGET_FF_%s" % t for t in self.target.supported_form_factors])
+
+            return list(set(self.cxx_symbols))  # Return only unique symbols
+
+    # Extend the internal list of macros
+    def add_macros(self, new_macros):
+        self.macros.extend(new_macros)
+
+    def get_labels(self):
+        if self.labels is None:
+            toolchain_labels = [c.__name__ for c in getmro(self.__class__)]
+            toolchain_labels.remove('mbedToolchain')
+            self.labels = {
+                'TARGET': self.target.labels,
+                'FEATURE': self.target.features,
+                'TOOLCHAIN': toolchain_labels
+            }
+
+            # This is a policy decision and it should /really/ be in the config system
+            # ATM it's here for backward compatibility
+            if ((("-g" in self.flags['common'] or "-g3" in self.flags['common']) and
+                 "-O0" in self.flags['common']) or
+                ("-r" in self.flags['common'] and
+                 "-On" in self.flags['common'])):
+                self.labels['TARGET'].append("DEBUG")
+            else:
+                self.labels['TARGET'].append("RELEASE")
+        return self.labels
+
+
+    # Determine whether a source file needs updating/compiling
+    def need_update(self, target, dependencies):
+        if self.build_all:
+            return True
+
+        if not exists(target):
+            return True
+
+        target_mod_time = stat(target).st_mtime
+
+        for d in dependencies:
+            # Some objects are not provided with full path and here we do not have
+            # information about the library paths. Safe option: assume an update
+            if not d or not exists(d):
+                return True
+
+            if not self.stat_cache.has_key(d):
+                self.stat_cache[d] = stat(d).st_mtime
+
+            if self.stat_cache[d] >= target_mod_time:
+                return True
+
+        return False
+
+    def is_ignored(self, file_path):
+        """Check if file path is ignored by any .mbedignore thus far"""
+        return self._ignore_regex.match(normcase(file_path))
+
+    def add_ignore_patterns(self, root, base_path, patterns):
+        """Add a series of patterns to the ignored paths
+
+        Positional arguments:
+        root - the directory containing the ignore file
+        base_path - the location that the scan started from
+        patterns - the list of patterns we will ignore in the future
+        """
+        real_base = relpath(root, base_path)
+        if real_base == ".":
+            self.ignore_patterns.extend(normcase(p) for p in patterns)
+        else:
+            self.ignore_patterns.extend(normcase(join(real_base, pat)) for pat in patterns)
+        if self.ignore_patterns:
+            self._ignore_regex = re.compile("|".join(fnmatch.translate(p) for p in self.ignore_patterns))
+
+    # Create a Resources object from the path pointed to by *path* by either traversing a
+    # a directory structure, when *path* is a directory, or adding *path* to the resources,
+    # when *path* is a file.
+    # The parameter *base_path* is used to set the base_path attribute of the Resources
+    # object and the parameter *exclude_paths* is used by the directory traversal to
+    # exclude certain paths from the traversal.
+    def scan_resources(self, path, exclude_paths=None, base_path=None,
+                       collect_ignores=False):
+        self.progress("scan", path)
+
+        resources = Resources(path, collect_ignores=collect_ignores)
+        if not base_path:
+            if isfile(path):
+                base_path = dirname(path)
+            else:
+                base_path = path
+        resources.base_path = base_path
+
+        if isfile(path):
+            self._add_file(path, resources, base_path, exclude_paths=exclude_paths)
+        else:
+            self._add_dir(path, resources, base_path, exclude_paths=exclude_paths)
+        return resources
+
+    # A helper function for scan_resources. _add_dir traverses *path* (assumed to be a
+    # directory) and heeds the ".mbedignore" files along the way. _add_dir calls _add_file
+    # on every file it considers adding to the resources object.
+    def _add_dir(self, path, resources, base_path, exclude_paths=None):
+        """ os.walk(top[, topdown=True[, onerror=None[, followlinks=False]]])
+        When topdown is True, the caller can modify the dirnames list in-place
+        (perhaps using del or slice assignment), and walk() will only recurse into
+        the subdirectories whose names remain in dirnames; this can be used to prune
+        the search, impose a specific order of visiting, or even to inform walk()
+        about directories the caller creates or renames before it resumes walk()
+        again. Modifying dirnames when topdown is False is ineffective, because in
+        bottom-up mode the directories in dirnames are generated before dirpath
+        itself is generated.
+        """
+        labels = self.get_labels()
+        for root, dirs, files in walk(path, followlinks=True):
+            # Check if folder contains .mbedignore
+            if ".mbedignore" in files:
+                with open (join(root,".mbedignore"), "r") as f:
+                    lines=f.readlines()
+                    lines = [l.strip() for l in lines] # Strip whitespaces
+                    lines = [l for l in lines if l != ""] # Strip empty lines
+                    lines = [l for l in lines if not re.match("^#",l)] # Strip comment lines
+                    # Append root path to glob patterns and append patterns to ignore_patterns
+                    self.add_ignore_patterns(root, base_path, lines)
+
+            # Skip the whole folder if ignored, e.g. .mbedignore containing '*'
+            root_path =join(relpath(root, base_path))
+            if  (self.is_ignored(join(root_path,"")) or
+                 self.build_dir == root_path):
+                resources.ignore_dir(root_path)
+                dirs[:] = []
+                continue
+
+            for d in copy(dirs):
+                dir_path = join(root, d)
+                # Add internal repo folders/files. This is needed for exporters
+                if d == '.hg' or d == '.git':
+                    resources.repo_dirs.append(dir_path)
+
+                if ((d.startswith('.') or d in self.legacy_ignore_dirs) or
+                    # Ignore targets that do not match the TARGET in extra_labels list
+                    (d.startswith('TARGET_') and d[7:] not in labels['TARGET']) or
+                    # Ignore toolchain that do not match the current TOOLCHAIN
+                    (d.startswith('TOOLCHAIN_') and d[10:] not in labels['TOOLCHAIN']) or
+                    # Ignore .mbedignore files
+                    self.is_ignored(join(relpath(root, base_path), d,"")) or
+                    # Ignore TESTS dir
+                    (d == 'TESTS')):
+                        resources.ignore_dir(dir_path)
+                        dirs.remove(d)
+                elif d.startswith('FEATURE_'):
+                    # Recursively scan features but ignore them in the current scan.
+                    # These are dynamically added by the config system if the conditions are matched
+                    def closure (dir_path=dir_path, base_path=base_path):
+                        return self.scan_resources(dir_path, base_path=base_path,
+                                                   collect_ignores=resources.collect_ignores)
+                    resources.features.add_lazy(d[8:], closure)
+                    resources.ignore_dir(dir_path)
+                    dirs.remove(d)
+                elif exclude_paths:
+                    for exclude_path in exclude_paths:
+                        rel_path = relpath(dir_path, exclude_path)
+                        if not (rel_path.startswith('..')):
+                            resources.ignore_dir(dir_path)
+                            dirs.remove(d)
+                            break
+
+            # Add root to include paths
+            root = root.rstrip("/")
+            resources.inc_dirs.append(root)
+            resources.file_basepath[root] = base_path
+
+            for file in files:
+                file_path = join(root, file)
+                self._add_file(file_path, resources, base_path)
+
+    # A helper function for both scan_resources and _add_dir. _add_file adds one file
+    # (*file_path*) to the resources object based on the file type.
+    def _add_file(self, file_path, resources, base_path, exclude_paths=None):
+        resources.file_basepath[file_path] = base_path
+
+        if self.is_ignored(relpath(file_path, base_path)):
+            return
+
+        _, ext = splitext(file_path)
+        ext = ext.lower()
+
+        if   ext == '.s':
+            resources.s_sources.append(file_path)
+
+        elif ext == '.c':
+            resources.c_sources.append(file_path)
+
+        elif ext == '.cpp':
+            resources.cpp_sources.append(file_path)
+
+        elif ext == '.h' or ext == '.hpp':
+            resources.headers.append(file_path)
+
+        elif ext == '.o':
+            resources.objects.append(file_path)
+
+        elif ext == self.LIBRARY_EXT:
+            resources.libraries.append(file_path)
+            resources.lib_dirs.add(dirname(file_path))
+
+        elif ext == self.LINKER_EXT:
+            if resources.linker_script is not None:
+                self.info("Warning: Multiple linker scripts detected: %s -> %s" % (resources.linker_script, file_path))
+            resources.linker_script = file_path
+
+        elif ext == '.lib':
+            resources.lib_refs.append(file_path)
+
+        elif ext == '.bld':
+            resources.lib_builds.append(file_path)
+
+        elif basename(file_path) == '.hgignore':
+            resources.repo_files.append(file_path)
+
+        elif basename(file_path) == '.gitignore':
+            resources.repo_files.append(file_path)
+
+        elif ext == '.hex':
+            resources.hex_files.append(file_path)
+
+        elif ext == '.bin':
+            resources.bin_files.append(file_path)
+
+        elif ext == '.json':
+            resources.json_files.append(file_path)
+
+
+    def scan_repository(self, path):
+        resources = []
+
+        for root, dirs, files in walk(path):
+            # Remove ignored directories
+            for d in copy(dirs):
+                if d == '.' or d == '..':
+                    dirs.remove(d)
+
+            for file in files:
+                file_path = join(root, file)
+                resources.append(file_path)
+
+        return resources
+
+    def copy_files(self, files_paths, trg_path, resources=None, rel_path=None):
+        # Handle a single file
+        if type(files_paths) != ListType: files_paths = [files_paths]
+
+        for source in files_paths:
+            if source is None:
+                files_paths.remove(source)
+
+        for source in files_paths:
+            if resources is not None and resources.file_basepath.has_key(source):
+                relative_path = relpath(source, resources.file_basepath[source])
+            elif rel_path is not None:
+                relative_path = relpath(source, rel_path)
+            else:
+                _, relative_path = split(source)
+
+            target = join(trg_path, relative_path)
+
+            if (target != source) and (self.need_update(target, [source])):
+                self.progress("copy", relative_path)
+                mkdir(dirname(target))
+                copyfile(source, target)
+
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def relative_object_path(self, build_path, base_dir, source):
+        source_dir, name, _ = split_path(source)
+
+        obj_dir = join(build_path, relpath(source_dir, base_dir))
+        if obj_dir is not self.prev_dir:
+            self.prev_dir = obj_dir
+            mkdir(obj_dir)
+        return join(obj_dir, name + '.o')
+
+    # Generate response file for all includes.
+    # ARM, GCC, IAR cross compatible
+    def get_inc_file(self, includes):
+        include_file = join(self.build_dir, ".includes_%s.txt" % self.inc_md5)
+        if not exists(include_file):
+            with open(include_file, "wb") as f:
+                cmd_list = []
+                for c in includes:
+                    if c:
+                        c = c.replace("\\", "/")
+                        if self.CHROOT:
+                            c = c.replace(self.CHROOT, '')
+                        cmd_list.append('"-I%s"' % c)
+                string = " ".join(cmd_list)
+                f.write(string)
+        return include_file
+
+    # Generate response file for all objects when linking.
+    # ARM, GCC, IAR cross compatible
+    def get_link_file(self, cmd):
+        link_file = join(self.build_dir, ".link_files.txt")
+        with open(link_file, "wb") as f:
+            cmd_list = []
+            for c in cmd:
+                if c:
+                    c = c.replace("\\", "/")
+                    if self.CHROOT:
+                        c = c.replace(self.CHROOT, '')
+                    cmd_list.append(('"%s"' % c) if not c.startswith('-') else c)
+            string = " ".join(cmd_list)
+            f.write(string)
+        return link_file
+
+    # Generate response file for all objects when archiving.
+    # ARM, GCC, IAR cross compatible
+    def get_arch_file(self, objects):
+        archive_file = join(self.build_dir, ".archive_files.txt")
+        with open(archive_file, "wb") as f:
+            o_list = []
+            for o in objects:
+                o_list.append('"%s"' % o)
+            string = " ".join(o_list).replace("\\", "/")
+            f.write(string)
+        return archive_file
+
+    # THIS METHOD IS BEING CALLED BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def compile_sources(self, resources, inc_dirs=None):
+        # Web IDE progress bar for project build
+        files_to_compile = resources.s_sources + resources.c_sources + resources.cpp_sources
+        self.to_be_compiled = len(files_to_compile)
+        self.compiled = 0
+
+        self.cc_verbose("Macros: "+' '.join(['-D%s' % s for s in self.get_symbols()]))
+
+        inc_paths = resources.inc_dirs
+        if inc_dirs is not None:
+            if isinstance(inc_dirs, list):
+                inc_paths.extend(inc_dirs)
+            else:
+                inc_paths.append(inc_dirs)
+        # De-duplicate include paths
+        inc_paths = set(inc_paths)
+        # Sort include paths for consistency
+        inc_paths = sorted(set(inc_paths))
+        # Unique id of all include paths
+        self.inc_md5 = md5(' '.join(inc_paths)).hexdigest()
+
+        objects = []
+        queue = []
+        work_dir = getcwd()
+        self.prev_dir = None
+
+        # Generate configuration header (this will update self.build_all if needed)
+        self.get_config_header()
+        self.dump_build_profile()
+
+        # Sort compile queue for consistency
+        files_to_compile.sort()
+        for source in files_to_compile:
+            object = self.relative_object_path(
+                self.build_dir, resources.file_basepath[source], source)
+
+            # Queue mode (multiprocessing)
+            commands = self.compile_command(source, object, inc_paths)
+            if commands is not None:
+                queue.append({
+                    'source': source,
+                    'object': object,
+                    'commands': commands,
+                    'work_dir': work_dir,
+                    'chroot': self.CHROOT
+                })
+            else:
+                self.compiled += 1
+                objects.append(object)
+
+        # Use queues/multiprocessing if cpu count is higher than setting
+        jobs = self.jobs if self.jobs else cpu_count()
+        if jobs > CPU_COUNT_MIN and len(queue) > jobs:
+            return self.compile_queue(queue, objects)
+        else:
+            return self.compile_seq(queue, objects)
+
+    # Compile source files queue in sequential order
+    def compile_seq(self, queue, objects):
+        for item in queue:
+            result = compile_worker(item)
+
+            self.compiled += 1
+            self.progress("compile", item['source'], build_update=True)
+            for res in result['results']:
+                self.cc_verbose("Compile: %s" % ' '.join(res['command']), result['source'])
+                self.compile_output([
+                    res['code'],
+                    res['output'],
+                    res['command']
+                ])
+            objects.append(result['object'])
+        return objects
+
+    # Compile source files queue in parallel by creating pool of worker threads
+    def compile_queue(self, queue, objects):
+        jobs_count = int(self.jobs if self.jobs else cpu_count() * CPU_COEF)
+        p = Pool(processes=jobs_count)
+
+        results = []
+        for i in range(len(queue)):
+            results.append(p.apply_async(compile_worker, [queue[i]]))
+        p.close()
+
+        itr = 0
+        while len(results):
+            itr += 1
+            if itr > 180000:
+                p.terminate()
+                p.join()
+                raise ToolException("Compile did not finish in 5 minutes")
+
+            sleep(0.01)
+            pending = 0
+            for r in results:
+                if r._ready is True:
+                    try:
+                        result = r.get()
+                        results.remove(r)
+
+                        self.compiled += 1
+                        self.progress("compile", result['source'], build_update=True)
+                        for res in result['results']:
+                            self.cc_verbose("Compile: %s" % ' '.join(res['command']), result['source'])
+                            self.compile_output([
+                                res['code'],
+                                res['output'],
+                                res['command']
+                            ])
+                        objects.append(result['object'])
+                    except ToolException, err:
+                        if p._taskqueue.queue:
+                            p._taskqueue.queue.clear()
+                            sleep(0.5)
+                        p.terminate()
+                        p.join()
+                        raise ToolException(err)
+                else:
+                    pending += 1
+                    if pending >= jobs_count:
+                        break
+
+        results = None
+        p.join()
+
+        return objects
+
+    # Determine the compile command based on type of source file
+    def compile_command(self, source, object, includes):
+        # Check dependencies
+        _, ext = splitext(source)
+        ext = ext.lower()
+
+        if ext == '.c' or  ext == '.cpp':
+            base, _ = splitext(object)
+            dep_path = base + '.d'
+            try:
+                deps = self.parse_dependencies(dep_path) if (exists(dep_path)) else []
+            except IOError, IndexError:
+                deps = []
+            config_file = ([self.config.app_config_location]
+                           if self.config.app_config_location else [])
+            deps.extend(config_file)
+            if ext == '.cpp' or self.COMPILE_C_AS_CPP:
+                deps.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-cxx"))
+            else:
+                deps.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-c"))
+            if len(deps) == 0 or self.need_update(object, deps):
+                if ext == '.cpp' or self.COMPILE_C_AS_CPP:
+                    return self.compile_cpp(source, object, includes)
+                else:
+                    return self.compile_c(source, object, includes)
+        elif ext == '.s':
+            deps = [source]
+            deps.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-asm"))
+            if self.need_update(object, deps):
+                return self.assemble(source, object, includes)
+        else:
+            return False
+
+        return None
+
+    def parse_dependencies(self, dep_path):
+        """Parse the dependency information generated by the compiler.
+
+        Positional arguments:
+        dep_path -- the path to a file generated by a previous run of the compiler
+
+        Return value:
+        A list of all source files that the dependency file indicated were dependencies
+
+        Side effects:
+        None
+
+        Note: A default implementation is provided for make-like file formats
+        """
+        dependencies = []
+        buff = open(dep_path).readlines()
+        if buff:
+            buff[0] = re.sub('^(.*?)\: ', '', buff[0])
+            for line in buff:
+                filename = line.replace('\\\n', '').strip()
+                if file:
+                    filename = filename.replace('\\ ', '\a')
+                    dependencies.extend(((self.CHROOT if self.CHROOT else '') +
+                                         f.replace('\a', ' '))
+                                        for f in filename.split(" "))
+        return list(filter(None, dependencies))
+
+    def is_not_supported_error(self, output):
+        return "#error directive: [NOT_SUPPORTED]" in output
+
+    @abstractmethod
+    def parse_output(self, output):
+        """Take in compiler output and extract sinlge line warnings and errors from it.
+
+        Positional arguments:
+        output -- a string of all the messages emitted by a run of the compiler
+
+        Return value:
+        None
+
+        Side effects:
+        call self.cc_info or self.notify with a description of the event generated by the compiler
+        """
+        raise NotImplemented
+
+    def compile_output(self, output=[]):
+        _rc = output[0]
+        _stderr = output[1].decode("utf-8")
+        command = output[2]
+
+        # Parse output for Warnings and Errors
+        self.parse_output(_stderr)
+        self.debug("Return: %s"% _rc)
+        for error_line in _stderr.splitlines():
+            self.debug("Output: %s"% error_line)
+
+        # Check return code
+        if _rc != 0:
+            if self.is_not_supported_error(_stderr):
+                raise NotSupportedException(_stderr)
+            else:
+                raise ToolException(_stderr)
+
+    def build_library(self, objects, dir, name):
+        needed_update = False
+        lib = self.STD_LIB_NAME % name
+        fout = join(dir, lib)
+        if self.need_update(fout, objects):
+            self.info("Library: %s" % lib)
+            self.archive(objects, fout)
+            needed_update = True
+
+        return needed_update
+
+    def link_program(self, r, tmp_path, name):
+        needed_update = False
+        ext = 'bin'
+        if hasattr(self.target, 'OUTPUT_EXT'):
+            ext = self.target.OUTPUT_EXT
+
+        if hasattr(self.target, 'OUTPUT_NAMING'):
+            self.var("binary_naming", self.target.OUTPUT_NAMING)
+            if self.target.OUTPUT_NAMING == "8.3":
+                name = name[0:8]
+                ext = ext[0:3]
+
+        # Create destination directory
+        head, tail =  split(name)
+        new_path = join(tmp_path, head)
+        mkdir(new_path)
+
+        filename = name+'.'+ext
+        elf = join(tmp_path, name + '.elf')
+        bin = None if ext is 'elf' else join(tmp_path, filename)
+        map = join(tmp_path, name + '.map')
+
+        r.objects = sorted(set(r.objects))
+        config_file = ([self.config.app_config_location]
+                       if self.config.app_config_location else [])
+        dependencies = r.objects + r.libraries + [r.linker_script] + config_file
+        dependencies.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-ld"))
+        if self.need_update(elf, dependencies):
+            needed_update = True
+            self.progress("link", name)
+            self.link(elf, r.objects, r.libraries, r.lib_dirs, r.linker_script)
+
+        if bin and self.need_update(bin, [elf]):
+            needed_update = True
+            self.progress("elf2bin", name)
+            self.binary(r, elf, bin)
+
+        # Initialize memap and process map file. This doesn't generate output.
+        self.mem_stats(map)
+
+        self.var("compile_succeded", True)
+        self.var("binary", filename)
+
+        return bin, needed_update
+
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def default_cmd(self, command):
+        _stdout, _stderr, _rc = run_cmd(command, work_dir=getcwd(), chroot=self.CHROOT)
+        self.debug("Return: %s"% _rc)
+
+        for output_line in _stdout.splitlines():
+            self.debug("Output: %s"% output_line)
+        for error_line in _stderr.splitlines():
+            self.debug("Errors: %s"% error_line)
+
+        if _rc != 0:
+            for line in _stderr.splitlines():
+                self.tool_error(line)
+            raise ToolException(_stderr)
+
+    ### NOTIFICATIONS ###
+    def info(self, message):
+        self.notify({'type': 'info', 'message': message})
+
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def debug(self, message):
+        if self.VERBOSE:
+            if type(message) is ListType:
+                message = ' '.join(message)
+            message = "[DEBUG] " + message
+            self.notify({'type': 'debug', 'message': message})
+
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def cc_info(self, info=None):
+        if info is not None:
+            info['type'] = 'cc'
+            self.notify(info)
+
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def cc_verbose(self, message, file=""):
+        self.debug(message)
+
+    def progress(self, action, file, build_update=False):
+        msg = {'type': 'progress', 'action': action, 'file': file}
+        if build_update:
+            msg['percent'] = 100. * float(self.compiled) / float(self.to_be_compiled)
+        self.notify(msg)
+
+    def tool_error(self, message):
+        self.notify({'type': 'tool_error', 'message': message})
+
+    def var(self, key, value):
+        self.notify({'type': 'var', 'key': key, 'val': value})
+
+    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
+    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
+    def mem_stats(self, map):
+        """! Creates parser object
+        @param map Path to linker map file to parse and decode
+        @return None
+        """
+        toolchain = self.__class__.__name__
+
+        # Create memap object
+        memap = MemapParser()
+
+        # Parse and decode a map file
+        if memap.parse(abspath(map), toolchain) is False:
+            self.info("Unknown toolchain for memory statistics %s" % toolchain)
+            return None
+
+        # Store the memap instance for later use
+        self.memap_instance = memap
+
+        # Note: memory statistics are not returned.
+        # Need call to generate_output later (depends on depth & output format)
+
+        return None
+
+    # Set the configuration data
+    def set_config_data(self, config_data):
+        self.config_data = config_data
+
+    # Creates the configuration header if needed:
+    # - if there is no configuration data, "mbed_config.h" is not create (or deleted if it exists).
+    # - if there is configuration data and "mbed_config.h" does not exist, it is created.
+    # - if there is configuration data similar to the previous configuration data,
+    #   "mbed_config.h" is left untouched.
+    # - if there is new configuration data, "mbed_config.h" is overriden.
+    # The function needs to be called exactly once for the lifetime of this toolchain instance.
+    # The "config_processed" variable (below) ensures this behaviour.
+    # The function returns the location of the configuration file, or None if there is no
+    # configuration data available (and thus no configuration file)
+    def get_config_header(self):
+        if self.config_processed: # this function was already called, return its result
+            return self.config_file
+        # The config file is located in the build directory
+        self.config_file = join(self.build_dir, self.MBED_CONFIG_FILE_NAME)
+        # If the file exists, read its current content in prev_data
+        if exists(self.config_file):
+            with open(self.config_file, "rt") as f:
+                prev_data = f.read()
+        else:
+            prev_data = None
+        # Get the current configuration data
+        crt_data = self.config.config_to_header(self.config_data) if self.config_data else None
+        # "changed" indicates if a configuration change was detected
+        changed = False
+        if prev_data is not None: # a previous mbed_config.h exists
+            if crt_data is None: # no configuration data, so "mbed_config.h" needs to be removed
+                remove(self.config_file)
+                self.config_file = None # this means "config file not present"
+                changed = True
+            elif crt_data != prev_data: # different content of config file
+                with open(self.config_file, "wt") as f:
+                    f.write(crt_data)
+                changed = True
+        else: # a previous mbed_config.h does not exist
+            if crt_data is not None: # there's configuration data available
+                with open(self.config_file, "wt") as f:
+                    f.write(crt_data)
+                changed = True
+            else:
+                self.config_file = None # this means "config file not present"
+        # If there was a change in configuration, rebuild everything
+        self.build_all = changed
+        # Make sure that this function will only return the location of the configuration
+        # file for subsequent calls, without trying to manipulate its content in any way.
+        self.config_processed = True
+        return self.config_file
+
+    def dump_build_profile(self):
+        """Dump the current build profile and macros into the `.profile` file
+        in the build directory"""
+        for key in ["cxx", "c", "asm", "ld"]:
+            to_dump = (str(self.flags[key]) + str(sorted(self.macros)))
+            if key in ["cxx", "c"]:
+                to_dump += str(self.flags['common'])
+            where = join(self.build_dir, self.PROFILE_FILE_NAME + "-" + key)
+            self._overwrite_when_not_equal(where, to_dump)
+
+    @staticmethod
+    def _overwrite_when_not_equal(filename, content):
+        if not exists(filename) or content != open(filename).read():
+            with open(filename, "wb") as out:
+                out.write(content)
+
+    @staticmethod
+    def generic_check_executable(tool_key, executable_name, levels_up,
+                                 nested_dir=None):
+        """
+        Positional args:
+        tool_key: the key to index TOOLCHAIN_PATHS
+        executable_name: the toolchain's named executable (ex. armcc)
+        levels_up: each toolchain joins the toolchain_path, some
+        variable directories (bin, include), and the executable name,
+        so the TOOLCHAIN_PATH value must be appropriately distanced
+
+        Keyword args:
+        nested_dir: the directory within TOOLCHAIN_PATHS where the executable
+          is found (ex: 'bin' for ARM\bin\armcc (necessary to check for path
+          that will be used by toolchain's compile)
+
+        Returns True if the executable location specified by the user
+        exists and is valid OR the executable can be found on the PATH.
+        Returns False otherwise.
+        """
+        # Search PATH if user did not specify a path or specified path doesn't
+        # exist.
+        if not TOOLCHAIN_PATHS[tool_key] or not exists(TOOLCHAIN_PATHS[tool_key]):
+            exe = find_executable(executable_name)
+            if not exe:
+                return False
+            for level in range(levels_up):
+                # move up the specified number of directories
+                exe = dirname(exe)
+            TOOLCHAIN_PATHS[tool_key] = exe
+        if nested_dir:
+            subdir = join(TOOLCHAIN_PATHS[tool_key], nested_dir,
+                          executable_name)
+        else:
+            subdir = join(TOOLCHAIN_PATHS[tool_key],executable_name)
+        # User could have specified a path that exists but does not contain exe
+        return exists(subdir) or exists(subdir +'.exe')
+
+    @abstractmethod
+    def check_executable(self):
+        """Returns True if the executable (armcc) location specified by the
+         user exists OR the executable can be found on the PATH.
+         Returns False otherwise."""
+        raise NotImplemented
+
+    @abstractmethod
+    def get_config_option(self, config_header):
+        """Generate the compiler option that forces the inclusion of the configuration
+        header file.
+
+        Positional arguments:
+        config_header -- The configuration header that will be included within all source files
+
+        Return value:
+        A list of the command line arguments that will force the inclusion the specified header
+
+        Side effects:
+        None
+        """
+        raise NotImplemented
+
+    @abstractmethod
+    def get_compile_options(self, defines, includes, for_asm=False):
+        """Generate the compiler options from the defines and includes
+
+        Positional arguments:
+        defines -- The preprocessor macros defined on the command line
+        includes -- The include file search paths
+
+        Keyword arguments:
+        for_asm -- generate the assembler options instead of the compiler options
+
+        Return value:
+        A list of the command line arguments that will force the inclusion the specified header
+
+        Side effects:
+        None
+        """
+        raise NotImplemented
+
+    @abstractmethod
+    def assemble(self, source, object, includes):
+        """Generate the command line that assembles.
+
+        Positional arguments:
+        source -- a file path that is the file to assemble
+        object -- a file path that is the destination object
+        includes -- a list of all directories where header files may be found
+
+        Return value:
+        The complete command line, as a list, that would invoke the assembler
+        on the source file, include all the include paths, and generate
+        the specified object file.
+
+        Side effects:
+        None
+
+        Note:
+        This method should be decorated with @hook_tool.
+        """
+        raise NotImplemented
+
+    @abstractmethod
+    def compile_c(self, source, object, includes):
+        """Generate the command line that compiles a C source file.
+
+        Positional arguments:
+        source -- the C source file to compile
+        object -- the destination object file
+        includes -- a list of all the directories where header files may be found
+
+        Return value:
+        The complete command line, as a list, that would invoke the C compiler
+        on the source file, include all the include paths, and generate the
+        specified object file.
+
+        Side effects:
+        None
+
+        Note:
+        This method should be decorated with @hook_tool.
+        """
+        raise NotImplemented
+
+    @abstractmethod
+    def compile_cpp(self, source, object, includes):
+        """Generate the command line that compiles a C++ source file.
+
+        Positional arguments:
+        source -- the C++ source file to compile
+        object -- the destination object file
+        includes -- a list of all the directories where header files may be found
+
+        Return value:
+        The complete command line, as a list, that would invoke the C++ compiler
+        on the source file, include all the include paths, and generate the
+        specified object file.
+
+        Side effects:
+        None
+
+        Note:
+        This method should be decorated with @hook_tool.
+        """
+        raise NotImplemented
+
+    @abstractmethod
+    def link(self, output, objects, libraries, lib_dirs, mem_map):
+        """Run the linker to create an executable and memory map.
+
+        Positional arguments:
+        output -- the file name to place the executable in
+        objects -- all of the object files to link
+        libraries -- all of the required libraries
+        lib_dirs -- where the required libraries are located
+        mem_map -- the location where the memory map file should be stored
+
+        Return value:
+        None
+
+        Side effect:
+        Runs the linker to produce the executable.
+
+        Note:
+        This method should be decorated with @hook_tool.
+        """
+        raise NotImplemented
+
+    @abstractmethod
+    def archive(self, objects, lib_path):
+        """Run the command line that creates an archive.
+
+        Positional arguhments:
+        objects -- a list of all the object files that should be archived
+        lib_path -- the file name of the resulting library file
+
+        Return value:
+        None
+
+        Side effect:
+        Runs the archiving tool to produce the library file.
+
+        Note:
+        This method should be decorated with @hook_tool.
+        """
+        raise NotImplemented
+
+    @abstractmethod
+    def binary(self, resources, elf, bin):
+        """Run the command line that will Extract a simplified binary file.
+
+        Positional arguments:
+        resources -- A resources object (Is not used in any of the toolchains)
+        elf -- the executable file that is to be converted
+        bin -- the file name of the to be created simplified binary file
+
+        Return value:
+        None
+
+        Side effect:
+        Runs the elf2bin tool to produce the simplified binary file.
+
+        Note:
+        This method should be decorated with @hook_tool.
+        """
+        raise NotImplemented
+
+    @staticmethod
+    @abstractmethod
+    def name_mangle(name):
+        """Mangle a name based on the conventional name mangling of this toolchain
+
+        Positional arguments:
+        name -- the name to mangle
+
+        Return:
+        the mangled name as a string
+        """
+        raise NotImplemented
+
+    @staticmethod
+    @abstractmethod
+    def make_ld_define(name, value):
+        """Create an argument to the linker that would define a symbol
+
+        Positional arguments:
+        name -- the symbol to define
+        value -- the value to give the symbol
+
+        Return:
+        The linker flag as a string
+        """
+        raise NotImplemented
+
+    @staticmethod
+    @abstractmethod
+    def redirect_symbol(source, sync, build_dir):
+        """Redirect a symbol at link time to point at somewhere else
+
+        Positional arguments:
+        source -- the symbol doing the pointing
+        sync -- the symbol being pointed to
+        build_dir -- the directory to put "response files" if needed by the toolchain
+
+        Side Effects:
+        Possibly create a file in the build directory
+
+        Return:
+        The linker flag to redirect the symbol, as a string
+        """
+        raise NotImplemented
+
+    # Return the list of macros geenrated by the build system
+    def get_config_macros(self):
+        return self.config.config_to_macros(self.config_data) if self.config_data else []
+
+    @property
+    def report(self):
+        to_ret = {}
+        to_ret['c_compiler'] = {'flags': copy(self.flags['c']),
+                                'symbols': self.get_symbols()}
+        to_ret['cxx_compiler'] = {'flags': copy(self.flags['cxx']),
+                                  'symbols': self.get_symbols()}
+        to_ret['assembler'] = {'flags': copy(self.flags['asm']),
+                               'symbols': self.get_symbols(True)}
+        to_ret['linker'] = {'flags': copy(self.flags['ld'])}
+        to_ret.update(self.config.report)
+        return to_ret
+
+from tools.settings import ARM_PATH, ARMC6_PATH, GCC_ARM_PATH, IAR_PATH
+
+TOOLCHAIN_PATHS = {
+    'ARM': ARM_PATH,
+    'uARM': ARM_PATH,
+    'ARMC6': ARMC6_PATH,
+    'GCC_ARM': GCC_ARM_PATH,
+    'IAR': IAR_PATH
+}
+
+from tools.toolchains.arm import ARM_STD, ARM_MICRO, ARMC6
+from tools.toolchains.gcc import GCC_ARM
+from tools.toolchains.iar import IAR
+
+TOOLCHAIN_CLASSES = {
+    'ARM': ARM_STD,
+    'uARM': ARM_MICRO,
+    'ARMC6': ARMC6,
+    'GCC_ARM': GCC_ARM,
+    'IAR': IAR
+}
+
+TOOLCHAINS = set(TOOLCHAIN_CLASSES.keys())
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/__init__.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/__init__.pyc
new file mode 100755
index 0000000..86aca23
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/__init__.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/arm.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/arm.py
new file mode 100755
index 0000000..4cc46aa
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/arm.py
@@ -0,0 +1,398 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import re
+from copy import copy
+from os.path import join, dirname, splitext, basename, exists
+from os import makedirs, write
+from tempfile import mkstemp
+
+from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS
+from tools.hooks import hook_tool
+from tools.utils import mkdir, NotSupportedException
+
+class ARM(mbedToolchain):
+    LINKER_EXT = '.sct'
+    LIBRARY_EXT = '.ar'
+
+    STD_LIB_NAME = "%s.ar"
+    DIAGNOSTIC_PATTERN  = re.compile('"(?P<file>[^"]+)", line (?P<line>\d+)( \(column (?P<column>\d+)\)|): (?P<severity>Warning|Error|Fatal error): (?P<message>.+)')
+    INDEX_PATTERN  = re.compile('(?P<col>\s*)\^')
+    DEP_PATTERN = re.compile('\S+:\s(?P<file>.+)\n')
+    SHEBANG = "#! armcc -E"
+    SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
+                       "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"]
+
+    @staticmethod
+    def check_executable():
+        """Returns True if the executable (armcc) location specified by the
+         user exists OR the executable can be found on the PATH.
+         Returns False otherwise."""
+        return mbedToolchain.generic_check_executable("ARM", 'armcc', 2, 'bin')
+
+    def __init__(self, target, notify=None, macros=None,
+                 silent=False, extra_verbose=False, build_profile=None,
+                 build_dir=None):
+        mbedToolchain.__init__(self, target, notify, macros, silent,
+                               build_dir=build_dir,
+                               extra_verbose=extra_verbose,
+                               build_profile=build_profile)
+        if target.core not in self.SUPPORTED_CORES:
+            raise NotSupportedException(
+                "this compiler does not support the core %s" % target.core)
+
+        if target.core == "Cortex-M0+":
+            cpu = "Cortex-M0"
+        elif target.core == "Cortex-M4F":
+            cpu = "Cortex-M4.fp"
+        elif target.core == "Cortex-M7FD":
+            cpu = "Cortex-M7.fp.dp"
+        elif target.core == "Cortex-M7F":
+            cpu = "Cortex-M7.fp.sp"
+        else:
+            cpu = target.core
+
+        ARM_BIN = join(TOOLCHAIN_PATHS['ARM'], "bin")
+        ARM_INC = join(TOOLCHAIN_PATHS['ARM'], "include")
+        
+        main_cc = join(ARM_BIN, "armcc")
+
+        self.flags['common'] += ["--cpu=%s" % cpu]
+
+        self.asm = [main_cc] + self.flags['common'] + self.flags['asm']
+        self.cc = [main_cc] + self.flags['common'] + self.flags['c']
+        self.cppc = [main_cc] + self.flags['common'] + self.flags['c'] + self.flags['cxx']
+
+        self.ld = [join(ARM_BIN, "armlink")] + self.flags['ld']
+
+        self.ar = join(ARM_BIN, "armar")
+        self.elf2bin = join(ARM_BIN, "fromelf")
+
+    def parse_dependencies(self, dep_path):
+        dependencies = []
+        for line in open(dep_path).readlines():
+            match = ARM.DEP_PATTERN.match(line)
+            if match is not None:
+                #we need to append chroot, because when the .d files are generated the compiler is chrooted
+                dependencies.append((self.CHROOT if self.CHROOT else '') + match.group('file'))
+        return dependencies
+
+    def parse_output(self, output):
+        msg = None
+        for line in output.splitlines():
+            match = ARM.DIAGNOSTIC_PATTERN.match(line)
+            if match is not None:
+                if msg is not None:
+                    self.cc_info(msg)
+                    msg = None
+                msg = {
+                    'severity': match.group('severity').lower(),
+                    'file': match.group('file'),
+                    'line': match.group('line'),
+                    'col': match.group('column') if match.group('column') else 0,
+                    'message': match.group('message'),
+                    'text': '',
+                    'target_name': self.target.name,
+                    'toolchain_name': self.name
+                }
+            elif msg is not None:
+                # Determine the warning/error column by calculating the ^ position
+                match = ARM.INDEX_PATTERN.match(line)
+                if match is not None:
+                    msg['col'] = len(match.group('col'))
+                    self.cc_info(msg)
+                    msg = None
+                else:
+                    msg['text'] += line+"\n"
+        
+        if msg is not None:
+            self.cc_info(msg)
+
+    def get_dep_option(self, object):
+        base, _ = splitext(object)
+        dep_path = base + '.d'
+        return ["--depend", dep_path]
+
+    def get_config_option(self, config_header):
+        return ['--preinclude=' + config_header]
+
+    def get_compile_options(self, defines, includes, for_asm=False):        
+        opts = ['-D%s' % d for d in defines]
+        if self.RESPONSE_FILES:
+            opts += ['--via', self.get_inc_file(includes)]
+        else:
+            opts += ["-I%s" % i for i in includes]
+
+        if not for_asm:
+            config_header = self.get_config_header()
+            if config_header is not None:
+                opts = opts + self.get_config_option(config_header)
+        return opts
+
+    @hook_tool
+    def assemble(self, source, object, includes):
+        # Preprocess first, then assemble
+        dir = join(dirname(object), '.temp')
+        mkdir(dir)
+        tempfile = join(dir, basename(object) + '.E.s')
+        
+        # Build preprocess assemble command
+        cmd_pre = self.asm + self.get_compile_options(self.get_symbols(True), includes) + ["-E", "-o", tempfile, source]
+
+        # Build main assemble command
+        cmd = self.asm + ["-o", object, tempfile]
+
+        # Call cmdline hook
+        cmd_pre = self.hook.get_cmdline_assembler(cmd_pre)
+        cmd = self.hook.get_cmdline_assembler(cmd)
+       
+        # Return command array, don't execute
+        return [cmd_pre, cmd]
+
+    @hook_tool
+    def compile(self, cc, source, object, includes):
+        # Build compile command
+        cmd = cc + self.get_compile_options(self.get_symbols(), includes)
+        
+        cmd.extend(self.get_dep_option(object))
+            
+        cmd.extend(["-o", object, source])
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_compiler(cmd)
+
+        return [cmd]
+
+    def compile_c(self, source, object, includes):
+        return self.compile(self.cc, source, object, includes)
+
+    def compile_cpp(self, source, object, includes):
+        return self.compile(self.cppc, source, object, includes)
+
+    def correct_scatter_shebang(self, scatter_file):
+        """Correct the shebang at the top of a scatter file.
+
+        Positional arguments:
+        scatter_file -- the scatter file to correct
+
+        Return:
+        The location of the correct scatter file
+
+        Side Effects:
+        This method MAY write a new scatter file to disk
+        """
+        with open(scatter_file, "rb") as input:
+            lines = input.readlines()
+            if  (lines[0].startswith(self.SHEBANG) or
+                 not lines[0].startswith("#!")):
+                return scatter_file
+            else:
+                new_scatter = join(self.build_dir, ".link_script.sct")
+                if self.need_update(new_scatter, [scatter_file]):
+                    with open(new_scatter, "wb") as out:
+                        out.write(self.SHEBANG)
+                        out.write("\n")
+                        out.write("".join(lines[1:]))
+                return new_scatter
+
+    @hook_tool
+    def link(self, output, objects, libraries, lib_dirs, scatter_file):
+        base, _ = splitext(output)
+        map_file = base + ".map"
+        args = ["-o", output, "--info=totals", "--map", "--list=%s" % map_file]
+        args.extend(objects)
+        args.extend(libraries)
+        if lib_dirs:
+            args.extend(["--userlibpath", ",".join(lib_dirs)])
+        if scatter_file:
+            new_scatter = self.correct_scatter_shebang(scatter_file)
+            args.extend(["--scatter", new_scatter])
+
+        cmd_pre = self.ld + args
+        cmd = self.hook.get_cmdline_linker(cmd_pre)
+
+        if self.RESPONSE_FILES:
+            cmd_linker = cmd[0]
+            link_files = self.get_link_file(cmd[1:])
+            cmd = [cmd_linker, '--via', link_files]
+
+        self.cc_verbose("Link: %s" % ' '.join(cmd))
+        self.default_cmd(cmd)
+
+    @hook_tool
+    def archive(self, objects, lib_path):
+        if self.RESPONSE_FILES:
+            param = ['--via', self.get_arch_file(objects)]
+        else:
+            param = objects
+        self.default_cmd([self.ar, '-r', lib_path] + param)
+
+    @hook_tool
+    def binary(self, resources, elf, bin):
+        _, fmt = splitext(bin)
+        bin_arg = {".bin": "--bin", ".hex": "--i32"}[fmt]
+        cmd = [self.elf2bin, bin_arg, '-o', bin, elf]
+        cmd = self.hook.get_cmdline_binary(cmd)
+        self.cc_verbose("FromELF: %s" % ' '.join(cmd))
+        self.default_cmd(cmd)
+
+    @staticmethod
+    def name_mangle(name):
+        return "_Z%i%sv" % (len(name), name)
+
+    @staticmethod
+    def make_ld_define(name, value):
+        return "--predefine=\"-D%s=0x%x\"" % (name, value)
+
+    @staticmethod
+    def redirect_symbol(source, sync, build_dir):
+        if not exists(build_dir):
+            makedirs(build_dir)
+        handle, filename = mkstemp(prefix=".redirect-symbol.", dir=build_dir)
+        write(handle, "RESOLVE %s AS %s\n" % (source, sync))
+        return "--edit=%s" % filename
+
+
+class ARM_STD(ARM):
+    def __init__(self, target, notify=None, macros=None,
+                 silent=False, extra_verbose=False, build_profile=None,
+                 build_dir=None):
+        ARM.__init__(self, target, notify, macros, silent,
+                     build_dir=build_dir, extra_verbose=extra_verbose,
+                     build_profile=build_profile)
+        if "ARM" not in target.supported_toolchains:
+            raise NotSupportedException("ARM compiler support is required for ARM build")
+
+
+class ARM_MICRO(ARM):
+    PATCHED_LIBRARY = False
+    def __init__(self, target, notify=None, macros=None,
+                 silent=False, extra_verbose=False, build_profile=None,
+                 build_dir=None):
+        ARM.__init__(self, target, notify, macros, silent,
+                     build_dir=build_dir, extra_verbose=extra_verbose,
+                     build_profile=build_profile)
+        if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)):
+            raise NotSupportedException("ARM/uARM compiler support is required for ARM build")
+
+class ARMC6(ARM_STD):
+    SHEBANG = "#! armclang -E --target=arm-arm-none-eabi -x c"
+    SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
+                       "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD",
+                       "Cortex-M23", "Cortex-M23-NS", "Cortex-M33",
+                       "CortexM33-NS"]
+    @staticmethod
+    def check_executable():
+        return mbedToolchain.generic_check_executable("ARMC6", "armclang", 1)
+
+    def __init__(self, target, *args, **kwargs):
+        mbedToolchain.__init__(self, target, *args, **kwargs)
+        if target.core not in self.SUPPORTED_CORES:
+            raise NotSupportedException(
+                "this compiler does not support the core %s" % target.core)
+
+        if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)):
+            raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build")
+
+        if target.core.lower().endswith("fd"):
+            self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-2])
+            self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-2])
+        elif target.core.lower().endswith("f"):
+            self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-1])
+            self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-1])
+        elif target.core.lower().endswith("ns"):
+            self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-3])
+            self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-3])
+        else:
+            self.flags['common'].append("-mcpu=%s" % target.core.lower())
+            self.flags['ld'].append("--cpu=%s" % target.core.lower())
+
+        if target.core == "Cortex-M4F":
+            self.flags['common'].append("-mfpu=fpv4-sp-d16")
+            self.flags['common'].append("-mfloat-abi=hard")
+        elif target.core == "Cortex-M7F":
+            self.flags['common'].append("-mfpu=fpv5-sp-d16")
+            self.flags['common'].append("-mfloat-abi=softfp")
+        elif target.core == "Cortex-M7FD":
+            self.flags['common'].append("-mfpu=fpv5-d16")
+            self.flags['common'].append("-mfloat-abi=softfp")
+        elif target.core.startswith("Cortex-M23"):
+            self.flags['common'].append("-march=armv8-m.base")
+        elif target.core.startswith("Cortex-M33"):
+            self.flags['common'].append("-march=armv8-m.main")
+
+        if target.core == "Cortex-M23" or target.core == "Cortex-M33":
+            self.flags['common'].append("-mcmse")
+
+        asm_cpu = {
+            "Cortex-M0+": "Cortex-M0",
+            "Cortex-M4F": "Cortex-M4.fp",
+            "Cortex-M7F": "Cortex-M7.fp.sp",
+            "Cortex-M7FD": "Cortex-M7.fp.dp",
+            "Cortex-M23-NS": "Cortex-M23",
+            "Cortex-M33-NS": "Cortex-M33" }.get(target.core, target.core)
+
+        self.flags['asm'].append("--cpu=%s" % asm_cpu)
+
+        self.cc = ([join(TOOLCHAIN_PATHS["ARMC6"], "armclang")] +
+                   self.flags['common'] + self.flags['c'])
+        self.cppc = ([join(TOOLCHAIN_PATHS["ARMC6"], "armclang")] +
+                     self.flags['common'] + self.flags['cxx'])
+        self.asm = [join(TOOLCHAIN_PATHS["ARMC6"], "armasm")] + self.flags['asm']
+        self.ld = [join(TOOLCHAIN_PATHS["ARMC6"], "armlink")] + self.flags['ld']
+        self.ar = [join(TOOLCHAIN_PATHS["ARMC6"], "armar")]
+        self.elf2bin = join(TOOLCHAIN_PATHS["ARMC6"], "fromelf")
+
+
+    def parse_dependencies(self, dep_path):
+        return mbedToolchain.parse_dependencies(self, dep_path)
+
+    def is_not_supported_error(self, output):
+        return "#error [NOT_SUPPORTED]" in output
+
+    def parse_output(self, output):
+        pass
+
+    def get_config_option(self, config_header):
+        return ["-include", config_header]
+
+    def get_compile_options(self, defines, includes, for_asm=False):
+        opts = ['-D%s' % d for d in defines]
+        opts.extend(["-I%s" % i for i in includes])
+        if for_asm:
+            return ["--cpreproc",
+                    "--cpreproc_opts=%s" % ",".join(self.flags['common'] + opts)]
+        else:
+            config_header = self.get_config_header()
+            if config_header:
+                opts.extend(self.get_config_option(config_header))
+            return opts
+
+    @hook_tool
+    def assemble(self, source, object, includes):
+        cmd_pre = copy(self.asm)
+        cmd_pre.extend(self.get_compile_options(
+            self.get_symbols(True), includes, for_asm=True))
+        cmd_pre.extend(["-o", object, source])
+        return [self.hook.get_cmdline_assembler(cmd_pre)]
+
+    @hook_tool
+    def compile(self, cc, source, object, includes):
+        cmd = copy(cc)
+        cmd.extend(self.get_compile_options(self.get_symbols(), includes))
+        cmd.extend(["-o", object, source])
+        cmd = self.hook.get_cmdline_compiler(cmd)
+        return [cmd]
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/arm.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/arm.pyc
new file mode 100755
index 0000000..f63d75b
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/arm.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/gcc.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/gcc.py
new file mode 100755
index 0000000..5c22263
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/gcc.py
@@ -0,0 +1,294 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import re
+from os.path import join, basename, splitext, dirname, exists
+from distutils.spawn import find_executable
+
+from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS
+from tools.hooks import hook_tool
+
+class GCC(mbedToolchain):
+    LINKER_EXT = '.ld'
+    LIBRARY_EXT = '.a'
+
+    STD_LIB_NAME = "lib%s.a"
+    DIAGNOSTIC_PATTERN = re.compile('((?P<file>[^:]+):(?P<line>\d+):)(\d+:)? (?P<severity>warning|[eE]rror|fatal error): (?P<message>.+)')
+    INDEX_PATTERN  = re.compile('(?P<col>\s*)\^')
+
+    def __init__(self, target,  notify=None, macros=None,
+                 silent=False, extra_verbose=False, build_profile=None,
+                 build_dir=None):
+        mbedToolchain.__init__(self, target, notify, macros, silent,
+                               extra_verbose=extra_verbose,
+                               build_profile=build_profile, build_dir=build_dir)
+
+        tool_path=TOOLCHAIN_PATHS['GCC_ARM']
+        # Add flags for current size setting
+        default_lib = "std"
+        if hasattr(target, "default_lib"):
+            default_lib = target.default_lib
+        elif hasattr(target, "default_build"): # Legacy
+            default_lib = target.default_build
+
+        if default_lib == "small":
+            self.flags["common"].append("-DMBED_RTOS_SINGLE_THREAD")
+            self.flags["ld"].append("--specs=nano.specs")
+
+        if target.core == "Cortex-M0+":
+            cpu = "cortex-m0plus"
+        elif target.core == "Cortex-M4F":
+            cpu = "cortex-m4"
+        elif target.core == "Cortex-M7F":
+            cpu = "cortex-m7"
+        elif target.core == "Cortex-M7FD":
+            cpu = "cortex-m7"
+        elif target.core == "Cortex-M23-NS":
+            cpu = "cortex-m23"
+        elif target.core == "Cortex-M33-NS":
+            cpu = "cortex-m33"
+        else:
+            cpu = target.core.lower()
+
+        self.cpu = ["-mcpu=%s" % cpu]
+        if target.core.startswith("Cortex-M"):
+            self.cpu.append("-mthumb")
+
+        # FPU handling, M7 possibly to have double FPU
+        if target.core == "Cortex-M4F":
+            self.cpu.append("-mfpu=fpv4-sp-d16")
+            self.cpu.append("-mfloat-abi=softfp")
+        elif target.core == "Cortex-M7F":
+            self.cpu.append("-mfpu=fpv5-sp-d16")
+            self.cpu.append("-mfloat-abi=softfp")
+        elif target.core == "Cortex-M7FD":
+            self.cpu.append("-mfpu=fpv5-d16")
+            self.cpu.append("-mfloat-abi=softfp")
+
+        if target.core == "Cortex-A9":
+            self.cpu.append("-mthumb-interwork")
+            self.cpu.append("-marm")
+            self.cpu.append("-march=armv7-a")
+            self.cpu.append("-mfpu=vfpv3")
+            self.cpu.append("-mfloat-abi=hard")
+            self.cpu.append("-mno-unaligned-access")
+
+        if target.core.startswith("Cortex-M23"):
+            self.cpu.append("-march=armv8-m.base")
+        elif target.core.startswith("Cortex-M33"):
+            self.cpu.append("-march=armv8-m.main")
+
+        if target.core == "Cortex-M23" or target.core == "Cortex-M33":
+            self.cpu.append("-mcmse")
+
+        self.flags["common"] += self.cpu
+
+        main_cc = join(tool_path, "arm-none-eabi-gcc")
+        main_cppc = join(tool_path, "arm-none-eabi-g++")
+        self.asm = [main_cc] + self.flags['asm'] + self.flags["common"]
+        self.cc  = [main_cc]
+        self.cppc =[main_cppc]
+        self.cc += self.flags['c'] + self.flags['common']
+        self.cppc += self.flags['cxx'] + self.flags['common']
+
+        self.flags['ld'] += self.cpu
+        self.ld = [join(tool_path, "arm-none-eabi-gcc")] + self.flags['ld']
+        self.sys_libs = ["stdc++", "supc++", "m", "c", "gcc", "nosys"]
+        self.preproc = [join(tool_path, "arm-none-eabi-cpp"), "-E", "-P"]
+
+        self.ar = join(tool_path, "arm-none-eabi-ar")
+        self.elf2bin = join(tool_path, "arm-none-eabi-objcopy")
+
+    def is_not_supported_error(self, output):
+        return "error: #error [NOT_SUPPORTED]" in output
+
+    def parse_output(self, output):
+        # The warning/error notification is multiline
+        msg = None
+        for line in output.splitlines():
+            match = self.DIAGNOSTIC_PATTERN.search(line)
+            if match is not None:
+                if msg is not None:
+                    self.cc_info(msg)
+                    msg = None
+                msg = {
+                    'severity': match.group('severity').lower(),
+                    'file': match.group('file'),
+                    'line': match.group('line'),
+                    'col': 0,
+                    'message': match.group('message'),
+                    'text': '',
+                    'target_name': self.target.name,
+                    'toolchain_name': self.name
+                }
+            elif msg is not None:
+                # Determine the warning/error column by calculating the ^ position
+                match = self.INDEX_PATTERN.match(line)
+                if match is not None:
+                    msg['col'] = len(match.group('col'))
+                    self.cc_info(msg)
+                    msg = None
+                else:
+                    msg['text'] += line+"\n"
+
+        if msg is not None:
+            self.cc_info(msg)
+
+    def get_dep_option(self, object):
+        base, _ = splitext(object)
+        dep_path = base + '.d'
+        return ["-MD", "-MF", dep_path]
+
+    def get_config_option(self, config_header):
+        return ['-include', config_header]
+
+    def get_compile_options(self, defines, includes, for_asm=False):
+        opts = ['-D%s' % d for d in defines]
+        if self.RESPONSE_FILES:
+            opts += ['@%s' % self.get_inc_file(includes)]
+        else:
+            opts += ["-I%s" % i for i in includes]
+
+        if not for_asm:
+            config_header = self.get_config_header()
+            if config_header is not None:
+                opts = opts + self.get_config_option(config_header)
+        return opts
+
+    @hook_tool
+    def assemble(self, source, object, includes):
+        # Build assemble command
+        cmd = self.asm + self.get_compile_options(self.get_symbols(True), includes) + ["-o", object, source]
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_assembler(cmd)
+
+        # Return command array, don't execute
+        return [cmd]
+
+    @hook_tool
+    def compile(self, cc, source, object, includes):
+        # Build compile command
+        cmd = cc + self.get_compile_options(self.get_symbols(), includes)
+
+        cmd.extend(self.get_dep_option(object))
+
+        cmd.extend(["-o", object, source])
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_compiler(cmd)
+
+        return [cmd]
+
+    def compile_c(self, source, object, includes):
+        return self.compile(self.cc, source, object, includes)
+
+    def compile_cpp(self, source, object, includes):
+        return self.compile(self.cppc, source, object, includes)
+
+    @hook_tool
+    def link(self, output, objects, libraries, lib_dirs, mem_map):
+        libs = []
+        for l in libraries:
+            name, _ = splitext(basename(l))
+            libs.append("-l%s" % name[3:])
+        libs.extend(["-l%s" % l for l in self.sys_libs])
+
+        # Preprocess
+        if mem_map:
+            preproc_output = join(dirname(output), ".link_script.ld")
+            cmd = (self.preproc + [mem_map] + self.ld[1:] +
+                   [ "-o", preproc_output])
+            self.cc_verbose("Preproc: %s" % ' '.join(cmd))
+            self.default_cmd(cmd)
+            mem_map = preproc_output
+
+        # Build linker command
+        map_file = splitext(output)[0] + ".map"
+        cmd = self.ld + ["-o", output, "-Wl,-Map=%s" % map_file] + objects + ["-Wl,--start-group"] + libs + ["-Wl,--end-group"]
+        if mem_map:
+            cmd.extend(['-T', mem_map])
+
+        for L in lib_dirs:
+            cmd.extend(['-L', L])
+        cmd.extend(libs)
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_linker(cmd)
+
+        if self.RESPONSE_FILES:
+            # Split link command to linker executable + response file
+            cmd_linker = cmd[0]
+            link_files = self.get_link_file(cmd[1:])
+            cmd = [cmd_linker, "@%s" % link_files]
+
+        # Exec command
+        self.cc_verbose("Link: %s" % ' '.join(cmd))
+        self.default_cmd(cmd)
+
+    @hook_tool
+    def archive(self, objects, lib_path):
+        if self.RESPONSE_FILES:
+            param = ["@%s" % self.get_arch_file(objects)]
+        else:
+            param = objects
+
+        # Exec command
+        self.default_cmd([self.ar, 'rcs', lib_path] + param)
+
+    @hook_tool
+    def binary(self, resources, elf, bin):
+        # Build binary command
+        _, fmt = splitext(bin)
+        bin_arg = {'.bin': 'binary', '.hex': 'ihex'}[fmt]
+        cmd = [self.elf2bin, "-O", bin_arg, elf, bin]
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_binary(cmd)
+
+        # Exec command
+        self.cc_verbose("FromELF: %s" % ' '.join(cmd))
+        self.default_cmd(cmd)
+
+    @staticmethod
+    def name_mangle(name):
+        return "_Z%i%sv" % (len(name), name)
+
+    @staticmethod
+    def make_ld_define(name, value):
+        return "-D%s=0x%x" % (name, value)
+
+    @staticmethod
+    def redirect_symbol(source, sync, build_dir):
+        return "-Wl,--defsym=%s=%s" % (source, sync)
+
+    @staticmethod
+    def check_executable():
+        """Returns True if the executable (arm-none-eabi-gcc) location
+        specified by the user exists OR the executable can be found on the PATH.
+        Returns False otherwise."""
+        if not TOOLCHAIN_PATHS['GCC_ARM'] or not exists(TOOLCHAIN_PATHS['GCC_ARM']):
+            if find_executable('arm-none-eabi-gcc'):
+                TOOLCHAIN_PATHS['GCC_ARM'] = ''
+                return True
+            else:
+                return False
+        else:
+            exec_name = join(TOOLCHAIN_PATHS['GCC_ARM'], 'arm-none-eabi-gcc')
+            return exists(exec_name) or exists(exec_name + '.exe')
+
+class GCC_ARM(GCC):
+    pass
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/gcc.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/gcc.pyc
new file mode 100755
index 0000000..c0e5ca9
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/gcc.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/iar.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/iar.py
new file mode 100755
index 0000000..a3e3bc7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/iar.py
@@ -0,0 +1,243 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import re
+from os import remove
+from os.path import join, splitext, exists
+
+from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS
+from tools.hooks import hook_tool
+
+class IAR(mbedToolchain):
+    LIBRARY_EXT = '.a'
+    LINKER_EXT = '.icf'
+    STD_LIB_NAME = "%s.a"
+
+    DIAGNOSTIC_PATTERN = re.compile('"(?P<file>[^"]+)",(?P<line>[\d]+)\s+(?P<severity>Warning|Error|Fatal error)(?P<message>.+)')
+    INDEX_PATTERN  = re.compile('(?P<col>\s*)\^')
+
+    @staticmethod
+    def check_executable():
+        """Returns True if the executable (arm-none-eabi-gcc) location
+        specified by the user exists OR the executable can be found on the PATH.
+        Returns False otherwise."""
+        return mbedToolchain.generic_check_executable("IAR", 'iccarm', 2, "bin")
+
+    def __init__(self, target, notify=None, macros=None,
+                 silent=False, extra_verbose=False, build_profile=None,
+                 build_dir=None):
+        mbedToolchain.__init__(self, target, notify, macros, silent,
+                               build_dir=build_dir,
+                               extra_verbose=extra_verbose,
+                               build_profile=build_profile)
+        if target.core == "Cortex-M7F" or target.core == "Cortex-M7FD":
+            cpuchoice = "Cortex-M7"
+        elif target.core.startswith("Cortex-M23"):
+            cpuchoice = "8-M.baseline"
+        elif target.core.startswith("Cortex-M33"):
+            cpuchoice = "8-M.mainline"
+        else:
+            cpuchoice = target.core
+
+        # flags_cmd are used only by our scripts, the project files have them already defined,
+        # using this flags results in the errors (duplication)
+        # asm accepts --cpu Core or --fpu FPU, not like c/c++ --cpu=Core
+        asm_flags_cmd = ["--cpu", cpuchoice]
+        # custom c flags
+        c_flags_cmd = ["--cpu", cpuchoice]
+
+        c_flags_cmd.extend([
+            "--thumb", "--dlib_config", "DLib_Config_Full.h"
+        ])
+        # custom c++ cmd flags
+        cxx_flags_cmd = [
+            "--c++", "--no_rtti", "--no_exceptions"
+        ]
+        if target.core == "Cortex-M7FD":
+            asm_flags_cmd += ["--fpu", "VFPv5"]
+            c_flags_cmd.append("--fpu=VFPv5")
+        elif target.core == "Cortex-M7F":
+            asm_flags_cmd += ["--fpu", "VFPv5_sp"]
+            c_flags_cmd.append("--fpu=VFPv5_sp")
+        elif target.core == "Cortex-M23" or target.core == "Cortex-M33":
+            self.flags["asm"] += ["--cmse"]
+
+        IAR_BIN = join(TOOLCHAIN_PATHS['IAR'], "bin")
+        main_cc = join(IAR_BIN, "iccarm")
+
+        self.asm  = [join(IAR_BIN, "iasmarm")] + asm_flags_cmd + self.flags["asm"]
+        self.cc   = [main_cc]
+        self.cppc = [main_cc]
+        self.cc += self.flags["common"] + c_flags_cmd + self.flags["c"]
+        self.cppc += self.flags["common"] + c_flags_cmd + cxx_flags_cmd + self.flags["cxx"]
+        
+        self.ld   = [join(IAR_BIN, "ilinkarm")] + self.flags['ld']
+        self.ar = join(IAR_BIN, "iarchive")
+        self.elf2bin = join(IAR_BIN, "ielftool")
+
+    def parse_dependencies(self, dep_path):
+        return [(self.CHROOT if self.CHROOT else '')+path.strip() for path in open(dep_path).readlines()
+                if (path and not path.isspace())]
+
+    def parse_output(self, output):
+        msg = None
+        for line in output.splitlines():
+            match = IAR.DIAGNOSTIC_PATTERN.match(line)
+            if match is not None:
+                if msg is not None:
+                    self.cc_info(msg)
+                    msg = None
+                msg = {
+                    'severity': match.group('severity').lower(),
+                    'file': match.group('file'),
+                    'line': match.group('line'),
+                    'col': 0,
+                    'message': match.group('message'),
+                    'text': '',
+                    'target_name': self.target.name,
+                    'toolchain_name': self.name
+                }
+            elif msg is not None:
+                # Determine the warning/error column by calculating the ^ position
+                match = IAR.INDEX_PATTERN.match(line)
+                if match is not None:
+                    msg['col'] = len(match.group('col'))
+                    self.cc_info(msg)
+                    msg = None
+                else:
+                    msg['text'] += line+"\n"
+
+        if msg is not None:
+            self.cc_info(msg)
+
+    def get_dep_option(self, object):
+        base, _ = splitext(object)
+        dep_path = base + '.d'
+        return ["--dependencies", dep_path]
+
+    def cc_extra(self, object):
+        base, _ = splitext(object)
+        return ["-l", base + '.s.txt']
+
+    def get_config_option(self, config_header):
+        return ['--preinclude=' + config_header]
+
+    def get_compile_options(self, defines, includes, for_asm=False):
+        opts = ['-D%s' % d for d in defines]
+        if for_asm :
+            return opts
+        if self.RESPONSE_FILES:
+            opts += ['-f', self.get_inc_file(includes)]
+        else:
+            opts += ["-I%s" % i for i in includes]
+
+        config_header = self.get_config_header()
+        if config_header is not None:
+            opts = opts + self.get_config_option(config_header)
+        return opts
+
+    @hook_tool
+    def assemble(self, source, object, includes):
+        # Build assemble command
+        cmd = self.asm + self.get_compile_options(self.get_symbols(True), includes, True) + ["-o", object, source]
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_assembler(cmd)
+
+        # Return command array, don't execute
+        return [cmd]
+
+    @hook_tool
+    def compile(self, cc, source, object, includes):
+        # Build compile command
+        cmd = cc +  self.get_compile_options(self.get_symbols(), includes)
+
+        cmd.extend(self.get_dep_option(object))
+
+        cmd.extend(self.cc_extra(object))
+        
+        cmd.extend(["-o", object, source])
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_compiler(cmd)
+
+        return [cmd]
+
+    def compile_c(self, source, object, includes):
+        return self.compile(self.cc, source, object, includes)
+
+    def compile_cpp(self, source, object, includes):
+        return self.compile(self.cppc, source, object, includes)
+
+    @hook_tool
+    def link(self, output, objects, libraries, lib_dirs, mem_map):
+        # Build linker command
+        map_file = splitext(output)[0] + ".map"
+        cmd = self.ld + [ "-o", output, "--map=%s" % map_file] + objects + libraries
+
+        if mem_map:
+            cmd.extend(["--config", mem_map])
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_linker(cmd)
+
+        if self.RESPONSE_FILES:
+            # Split link command to linker executable + response file
+            cmd_linker = cmd[0]
+            link_files = self.get_link_file(cmd[1:])
+            cmd = [cmd_linker, '-f', link_files]
+
+        # Exec command
+        self.cc_verbose("Link: %s" % ' '.join(cmd))
+        self.default_cmd(cmd)
+
+    @hook_tool
+    def archive(self, objects, lib_path):
+        if self.RESPONSE_FILES:
+            param = ['-f', self.get_arch_file(objects)]
+        else:
+            param = objects
+
+        if exists(lib_path):
+            remove(lib_path)
+
+        self.default_cmd([self.ar, lib_path] + param)
+
+    @hook_tool
+    def binary(self, resources, elf, bin):
+        _, fmt = splitext(bin)
+        bin_arg = {".bin": "--bin", ".hex": "--ihex"}[fmt]
+        # Build binary command
+        cmd = [self.elf2bin, bin_arg, elf, bin]
+
+        # Call cmdline hook
+        cmd = self.hook.get_cmdline_binary(cmd)
+
+        # Exec command
+        self.cc_verbose("FromELF: %s" % ' '.join(cmd))
+        self.default_cmd(cmd)
+
+    @staticmethod
+    def name_mangle(name):
+        return "_Z%i%sv" % (len(name), name)
+
+    @staticmethod
+    def make_ld_define(name, value):
+        return "--config_def %s=0x%x" % (name, value)
+
+    @staticmethod
+    def redirect_symbol(source, sync, build_dir):
+        return "--redirect %s=%s" % (source, sync)
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/iar.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/iar.pyc
new file mode 100755
index 0000000..ca228e8
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/toolchains/iar.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/upload_results.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/upload_results.py
new file mode 100755
index 0000000..f07efb1
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/upload_results.py
@@ -0,0 +1,373 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import sys
+import argparse
+import xml.etree.ElementTree as ET
+import requests
+import urlparse
+
+def create_headers(args):
+    return { 'X-Api-Key':  args.api_key }
+
+def finish_command(command, response):
+    print(command, response.status_code, response.reason)
+    print(response.text)
+
+    if response.status_code < 400:
+        sys.exit(0)
+    else:
+        sys.exit(2)
+
+def create_build(args):
+    build = {}
+    build['buildType'] = args.build_type
+    build['number'] = args.build_number
+    build['source'] = args.build_source
+    build['status'] = 'running'
+
+    r = requests.post(urlparse.urljoin(args.url, "api/builds"), headers=create_headers(args), json=build)
+
+    if r.status_code < 400:
+        if args.property_file_format:
+            print("MBED_BUILD_ID=" + r.text)
+        else:
+            print(r.text)
+
+        sys.exit(0)
+    else:
+        sys.exit(2)
+
+def finish_build(args):
+    data = {}
+    data['status'] = 'completed'
+
+    r = requests.put(urlparse.urljoin(args.url, "api/builds/" + args.build_id), headers=create_headers(args), json=data)
+    finish_command('finish-build', r)
+
+def promote_build(args):
+    data = {}
+    data['buildType'] = 'Release'
+
+    r = requests.put(urlparse.urljoin(args.url, "api/builds/" + args.build_id), headers=create_headers(args), json=data)
+    finish_command('promote-build', r)
+
+def abort_build(args):
+    data = {}
+    data['status'] = 'aborted'
+
+    r = requests.put(urlparse.urljoin(args.url, "api/builds/" + args.build_id), headers=create_headers(args), json=data)
+    finish_command('abort-build', r)
+
+def add_project_runs(args):
+    '''
+    -------------------------------------
+    Notes on 'project_run_data' structure:
+    --------------------------------------
+        'projectRuns' - Tree structure used to keep track of what projects have
+            been logged in different report files. The tree is organized as follows:
+
+            'projectRuns': {                - Root element of tree
+
+                'hostOs': {                 - Host OS on which project was built/tested
+                                                - ex. windows, linux, or mac
+
+                    'platform': {           - Platform for which project was built/tested
+                                              (Corresponds to platform names in targets.py)
+                                                - ex. K64F, LPC1768, NRF51822, etc.
+
+                        'toolchain': {      - Toolchain with which project was built/tested
+                                              (Corresponds to TOOLCHAIN_CLASSES names in toolchains/__init__.py)
+                                                - ex. ARM, uARM, GCC_ARM, etc.
+
+                            'project': {    - Project that was build/tested
+                                              (Corresponds to test id in tests.py or library id in libraries.py)
+                                                - For tests, ex. MBED_A1, MBED_11, DTCT_1 etc.
+                                                - For libraries, ex. MBED, RTX, RTOS, etc.
+
+                            },
+                            ...
+                        },
+                        ...
+                    },
+                    ...
+                }
+            }
+
+        'platforms_set' - Set of all the platform names mentioned in the given report files
+
+        'toolchains_set' - Set of all the toolchain names mentioned in the given report files
+
+        'names_set' - Set of all the project names mentioned in the given report files
+
+        'hostOses_set' - Set of all the host names given (only given by the command line arguments)
+    '''
+
+    project_run_data = {}
+    project_run_data['projectRuns'] = {}
+    project_run_data['platforms_set'] = set()
+    project_run_data['vendors_set'] = set()
+    project_run_data['toolchains_set'] = set()
+    project_run_data['names_set'] = set()
+    project_run_data['hostOses_set'] = set()
+    project_run_data['hostOses_set'].add(args.host_os)
+
+    if args.build_report:
+        add_report(project_run_data, args.build_report, True, args.build_id, args.host_os)
+
+    if args.test_report:
+        add_report(project_run_data, args.test_report, False, args.build_id, args.host_os)
+
+    ts_data = format_project_run_data(project_run_data, args.limit)
+    total_result = True
+    
+    total_parts = len(ts_data)
+    print "Uploading project runs in %d parts" % total_parts
+    
+    for index, data in enumerate(ts_data):
+        r = requests.post(urlparse.urljoin(args.url, "api/projectRuns"), headers=create_headers(args), json=data)
+        print("add-project-runs part %d/%d" % (index + 1, total_parts), r.status_code, r.reason)
+        print(r.text)
+    
+        if r.status_code >= 400:
+            total_result = False
+    
+    if total_result:
+        print "'add-project-runs' completed successfully"
+        sys.exit(0)
+    else:
+        print "'add-project-runs' failed"
+        sys.exit(2)
+
+def prep_ts_data():
+    ts_data = {}
+    ts_data['projectRuns'] = []
+    ts_data['platforms'] = set()
+    ts_data['vendors'] = set()
+    ts_data['toolchains'] = set()
+    ts_data['names'] = set()
+    ts_data['hostOses'] = set()
+    return ts_data
+
+def finish_ts_data(ts_data, project_run_data):
+    ts_data['platforms'] = list(ts_data['platforms'])
+    ts_data['vendors'] = list(ts_data['vendors'])
+    ts_data['toolchains'] = list(ts_data['toolchains'])
+    ts_data['names'] = list(ts_data['names'])
+    ts_data['hostOses'] = list(ts_data['hostOses'])
+    
+    # Add all vendors to every projectRun submission
+    # TODO Either add "vendor" to the "project_run_data"
+    #      or remove "vendor" entirely from the viewer
+    ts_data['vendors'] = list(project_run_data['vendors_set'])
+    
+def format_project_run_data(project_run_data, limit):
+    all_ts_data = []
+    current_limit_count = 0
+    
+    ts_data = prep_ts_data()
+    ts_data['projectRuns'] = []
+
+    for hostOs_name, hostOs in project_run_data['projectRuns'].iteritems():
+        for platform_name, platform in hostOs.iteritems():
+            for toolchain_name, toolchain in platform.iteritems():
+                for project_name, project in toolchain.iteritems():
+                    if current_limit_count >= limit:
+                        finish_ts_data(ts_data, project_run_data)
+                        all_ts_data.append(ts_data)
+                        ts_data = prep_ts_data()
+                        current_limit_count = 0
+                    
+                    ts_data['projectRuns'].append(project)
+                    ts_data['platforms'].add(platform_name)
+                    ts_data['toolchains'].add(toolchain_name)
+                    ts_data['names'].add(project_name)
+                    ts_data['hostOses'].add(hostOs_name)
+                    current_limit_count += 1
+    
+    if current_limit_count > 0:
+        finish_ts_data(ts_data, project_run_data)
+        all_ts_data.append(ts_data)
+    
+    return all_ts_data
+
+def find_project_run(projectRuns, project):
+    keys = ['hostOs', 'platform', 'toolchain', 'project']
+
+    elem = projectRuns
+
+    for key in keys:
+        if not project[key] in elem:
+            return None
+
+        elem = elem[project[key]]
+
+    return elem
+
+def add_project_run(projectRuns, project):
+    keys = ['hostOs', 'platform', 'toolchain']
+
+    elem = projectRuns
+
+    for key in keys:
+        if not project[key] in elem:
+            elem[project[key]] = {}
+
+        elem = elem[project[key]]
+
+    elem[project['project']] = project
+
+def update_project_run_results(project_to_update, project, is_build):
+    if is_build:
+        project_to_update['buildPass'] = project['buildPass']
+        project_to_update['buildResult'] = project['buildResult']
+        project_to_update['buildOutput'] = project['buildOutput']
+    else:
+        project_to_update['testPass'] = project['testPass']
+        project_to_update['testResult'] = project['testResult']
+        project_to_update['testOutput'] = project['testOutput']
+
+def update_project_run(projectRuns, project, is_build):
+    found_project = find_project_run(projectRuns, project)
+    if found_project:
+        update_project_run_results(found_project, project, is_build)
+    else:
+        add_project_run(projectRuns, project)
+
+def add_report(project_run_data, report_file, is_build, build_id, host_os):
+    tree = None
+
+    try:
+        tree = ET.parse(report_file)
+    except:
+        print(sys.exc_info()[0])
+        print('Invalid path to report: %s', report_file)
+        sys.exit(1)
+
+    test_suites = tree.getroot()
+
+    for test_suite in test_suites:
+        platform = ""
+        toolchain = ""
+        vendor = ""
+        for properties in test_suite.findall('properties'):
+            for property in properties.findall('property'):
+                if property.attrib['name'] == 'target':
+                    platform = property.attrib['value']
+                    project_run_data['platforms_set'].add(platform)
+                elif property.attrib['name'] == 'toolchain':
+                    toolchain = property.attrib['value']
+                    project_run_data['toolchains_set'].add(toolchain)
+                elif property.attrib['name'] == 'vendor':
+                    vendor = property.attrib['value']
+                    project_run_data['vendors_set'].add(vendor)
+
+        for test_case in test_suite.findall('testcase'):
+            projectRun = {}
+            projectRun['build'] = build_id
+            projectRun['hostOs'] = host_os
+            projectRun['platform'] = platform
+            projectRun['toolchain'] = toolchain
+            projectRun['project'] = test_case.attrib['classname'].split('.')[-1]
+            projectRun['vendor'] = vendor
+
+            project_run_data['names_set'].add(projectRun['project'])
+
+            should_skip = False
+            skips = test_case.findall('skipped')
+
+            if skips:
+                should_skip = skips[0].attrib['message'] == 'SKIP'
+
+            if not should_skip:
+                system_outs = test_case.findall('system-out')
+
+                output = ""
+                if system_outs:
+                    output = system_outs[0].text
+
+                if is_build:
+                    projectRun['buildOutput'] = output
+                else:
+                    projectRun['testOutput'] = output
+
+                errors = test_case.findall('error')
+                failures = test_case.findall('failure')
+                projectRunPass = None
+                result = None
+
+                if errors:
+                    projectRunPass = False
+                    result = errors[0].attrib['message']
+                elif failures:
+                    projectRunPass = False
+                    result = failures[0].attrib['message']
+                elif skips:
+                    projectRunPass = True
+                    result = skips[0].attrib['message']
+                else:
+                    projectRunPass = True
+                    result = 'OK'
+
+                if is_build:
+                    projectRun['buildPass'] = projectRunPass
+                    projectRun['buildResult'] = result
+                else:
+                    projectRun['testPass'] = projectRunPass
+                    projectRun['testResult'] = result
+
+                update_project_run(project_run_data['projectRuns'], projectRun, is_build)
+
+def main(arguments):
+    # Register and parse command line arguments
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-u', '--url', required=True, help='url to ci site')
+    parser.add_argument('-k', '--api-key', required=True, help='api-key for posting data')
+
+    subparsers = parser.add_subparsers(help='subcommand help')
+
+    create_build_parser = subparsers.add_parser('create-build', help='create a new build')
+    create_build_parser.add_argument('-b', '--build-number', required=True, help='build number')
+    create_build_parser.add_argument('-T', '--build-type', choices=['Nightly', 'Limited', 'Pull_Request', 'Release_Candidate'], required=True, help='type of build')
+    create_build_parser.add_argument('-s', '--build-source', required=True, help='url to source of build')
+    create_build_parser.add_argument('-p', '--property-file-format', action='store_true', help='print result in the property file format')
+    create_build_parser.set_defaults(func=create_build)
+
+    finish_build_parser = subparsers.add_parser('finish-build', help='finish a running build')
+    finish_build_parser.add_argument('-b', '--build-id', required=True, help='build id')
+    finish_build_parser.set_defaults(func=finish_build)
+
+    finish_build_parser = subparsers.add_parser('promote-build', help='promote a build to a release')
+    finish_build_parser.add_argument('-b', '--build-id', required=True, help='build id')
+    finish_build_parser.set_defaults(func=promote_build)
+
+    abort_build_parser = subparsers.add_parser('abort-build', help='abort a running build')
+    abort_build_parser.add_argument('-b', '--build-id', required=True, help='build id')
+    abort_build_parser.set_defaults(func=abort_build)
+
+    add_project_runs_parser = subparsers.add_parser('add-project-runs', help='add project runs to a build')
+    add_project_runs_parser.add_argument('-b', '--build-id', required=True, help='build id')
+    add_project_runs_parser.add_argument('-r', '--build-report', required=False, help='path to junit xml build report')
+    add_project_runs_parser.add_argument('-t', '--test-report', required=False, help='path to junit xml test report')
+    add_project_runs_parser.add_argument('-o', '--host-os', required=True, help='host os on which test was run')
+    add_project_runs_parser.add_argument('-l', '--limit', required=False, type=int, default=1000, help='Limit the number of project runs sent at a time to avoid HTTP errors (default is 1000)')
+    add_project_runs_parser.set_defaults(func=add_project_runs)
+
+    args = parser.parse_args(arguments)
+    args.func(args)
+
+if __name__ == '__main__':
+    main(sys.argv[1:])
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/utils.py b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/utils.py
new file mode 100755
index 0000000..68c9631
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/utils.py
@@ -0,0 +1,531 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import sys
+import inspect
+import os
+import argparse
+import math
+from os import listdir, remove, makedirs
+from shutil import copyfile
+from os.path import isdir, join, exists, split, relpath, splitext, abspath
+from os.path import commonprefix, normpath, dirname
+from subprocess import Popen, PIPE, STDOUT, call
+from math import ceil
+import json
+from collections import OrderedDict
+import logging
+from intelhex import IntelHex
+
+def remove_if_in(lst, thing):
+    if thing in lst:
+        lst.remove(thing)
+
+def compile_worker(job):
+    """Standard task runner used for compiling
+
+    Positional argumets:
+    job - a dict containing a list of commands and the remaining arguments
+          to run_cmd
+    """
+    results = []
+    for command in job['commands']:
+        try:
+            _, _stderr, _rc = run_cmd(command, work_dir=job['work_dir'],
+                                      chroot=job['chroot'])
+        except KeyboardInterrupt:
+            raise ToolException
+
+        results.append({
+            'code': _rc,
+            'output': _stderr,
+            'command': command
+        })
+
+    return {
+        'source': job['source'],
+        'object': job['object'],
+        'commands': job['commands'],
+        'results': results
+    }
+
+def cmd(command, check=True, verbose=False, shell=False, cwd=None):
+    """A wrapper to run a command as a blocking job"""
+    text = command if shell else ' '.join(command)
+    if verbose:
+        print text
+    return_code = call(command, shell=shell, cwd=cwd)
+    if check and return_code != 0:
+        raise Exception('ERROR %d: "%s"' % (return_code, text))
+
+
+def run_cmd(command, work_dir=None, chroot=None, redirect=False):
+    """Run a command in the forground
+
+    Positional arguments:
+    command - the command to run
+
+    Keyword arguments:
+    work_dir - the working directory to run the command in
+    chroot - the chroot to run the command in
+    redirect - redirect the stderr to a pipe to be used later
+    """
+    if chroot:
+        # Conventions managed by the web team for the mbed.org build system
+        chroot_cmd = [
+            '/usr/sbin/chroot', '--userspec=33:33', chroot
+        ]
+        for element in command:
+            chroot_cmd += [element.replace(chroot, '')]
+
+        logging.debug("Running command %s", ' '.join(chroot_cmd))
+        command = chroot_cmd
+        work_dir = None
+
+    try:
+        process = Popen(command, stdout=PIPE,
+                        stderr=STDOUT if redirect else PIPE, cwd=work_dir)
+        _stdout, _stderr = process.communicate()
+    except OSError:
+        print "[OS ERROR] Command: "+(' '.join(command))
+        raise
+
+    return _stdout, _stderr, process.returncode
+
+
+def run_cmd_ext(command):
+    """ A version of run command that checks if the command exists befor running
+
+    Positional arguments:
+    command - the command line you are trying to invoke
+    """
+    assert is_cmd_valid(command[0])
+    process = Popen(command, stdout=PIPE, stderr=PIPE)
+    _stdout, _stderr = process.communicate()
+    return _stdout, _stderr, process.returncode
+
+
+def is_cmd_valid(command):
+    """ Verify that a command exists and is executable
+
+    Positional arguments:
+    command - the command to check
+    """
+    caller = get_caller_name()
+    cmd_path = find_cmd_abspath(command)
+    if not cmd_path:
+        error("%s: Command '%s' can't be found" % (caller, command))
+    if not is_exec(cmd_path):
+        error("%s: Command '%s' resolves to file '%s' which is not executable"
+              % (caller, command, cmd_path))
+    return True
+
+
+def is_exec(path):
+    """A simple check to verify that a path to an executable exists
+
+    Positional arguments:
+    path - the executable
+    """
+    return os.access(path, os.X_OK) or os.access(path+'.exe', os.X_OK)
+
+
+def find_cmd_abspath(command):
+    """ Returns the absolute path to a command.
+        None is returned if no absolute path was found.
+
+    Positional arguhments:
+    command - the command to find the path of
+    """
+    if exists(command) or exists(command + '.exe'):
+        return os.path.abspath(command)
+    if not 'PATH' in os.environ:
+        raise Exception("Can't find command path for current platform ('%s')"
+                        % sys.platform)
+    path_env = os.environ['PATH']
+    for path in path_env.split(os.pathsep):
+        cmd_path = '%s/%s' % (path, command)
+        if exists(cmd_path) or exists(cmd_path + '.exe'):
+            return cmd_path
+
+
+def mkdir(path):
+    """ a wrapped makedirs that only tries to create a directory if it does not
+    exist already
+
+    Positional arguments:
+    path - the path to maybe create
+    """
+    if not exists(path):
+        makedirs(path)
+
+
+def copy_file(src, dst):
+    """ Implement the behaviour of "shutil.copy(src, dst)" without copying the
+    permissions (this was causing errors with directories mounted with samba)
+
+    Positional arguments:
+    src - the source of the copy operation
+    dst - the destination of the copy operation
+    """
+    if isdir(dst):
+        _, base = split(src)
+        dst = join(dst, base)
+    copyfile(src, dst)
+
+
+def delete_dir_files(directory):
+    """ A function that does rm -rf
+
+    Positional arguments:
+    directory - the directory to remove
+    """
+    if not exists(directory):
+        return
+
+    for element in listdir(directory):
+        to_remove = join(directory, element)
+        if not isdir(to_remove):
+            remove(file)
+
+
+def get_caller_name(steps=2):
+    """
+    When called inside a function, it returns the name
+    of the caller of that function.
+
+    Keyword arguments:
+    steps - the number of steps up the stack the calling function is
+    """
+    return inspect.stack()[steps][3]
+
+
+def error(msg):
+    """Fatal error, abort hard
+
+    Positional arguments:
+    msg - the message to print before crashing
+    """
+    print("ERROR: %s" % msg)
+    sys.exit(1)
+
+
+def rel_path(path, base, dot=False):
+    """Relative path calculation that optionaly always starts with a dot
+
+    Positional arguments:
+    path - the path to make relative
+    base - what to make the path relative to
+
+    Keyword arguments:
+    dot - if True, the path will always start with a './'
+    """
+    final_path = relpath(path, base)
+    if dot and not final_path.startswith('.'):
+        final_path = './' + final_path
+    return final_path
+
+
+class ToolException(Exception):
+    """A class representing an exception throw by the tools"""
+    pass
+
+class NotSupportedException(Exception):
+    """A class a toolchain not supporting a particular target"""
+    pass
+
+class InvalidReleaseTargetException(Exception):
+    pass
+
+def split_path(path):
+    """spilt a file name into it's directory name, base name, and extension
+
+    Positional arguments:
+    path - the file name to split
+    """
+    base, has_ext = split(path)
+    name, ext = splitext(has_ext)
+    return base, name, ext
+
+
+def get_path_depth(path):
+    """ Given a path, return the number of directory levels present.
+        This roughly translates to the number of path separators (os.sep) + 1.
+        Ex. Given "path/to/dir", this would return 3
+        Special cases: "." and "/" return 0
+
+    Positional arguments:
+    path - the path to calculate the depth of
+    """
+    normalized_path = normpath(path)
+    path_depth = 0
+    head, tail = split(normalized_path)
+
+    while tail and tail != '.':
+        path_depth += 1
+        head, tail = split(head)
+
+    return path_depth
+
+
+def args_error(parser, message):
+    """Abort with an error that was generated by the arguments to a CLI program
+
+    Positional arguments:
+    parser - the ArgumentParser object that parsed the command line
+    message - what went wrong
+    """
+    parser.error(message)
+    sys.exit(2)
+
+
+def construct_enum(**enums):
+    """ Create your own pseudo-enums
+
+    Keyword arguments:
+    * - a member of the Enum you are creating and it's value
+    """
+    return type('Enum', (), enums)
+
+
+def check_required_modules(required_modules, verbose=True):
+    """ Function checks for Python modules which should be "importable"
+        before test suite can be used.
+        @return returns True if all modules are installed already
+    """
+    import imp
+    not_installed_modules = []
+    for module_name in required_modules:
+        try:
+            imp.find_module(module_name)
+        except ImportError:
+            # We also test against a rare case: module is an egg file
+            try:
+                __import__(module_name)
+            except ImportError as exc:
+                not_installed_modules.append(module_name)
+                if verbose:
+                    print "Error: %s" % exc
+
+    if verbose:
+        if not_installed_modules:
+            print ("Warning: Module(s) %s not installed. Please install " + \
+                   "required module(s) before using this script.")\
+                % (', '.join(not_installed_modules))
+
+    if not_installed_modules:
+        return False
+    else:
+        return True
+
+def dict_to_ascii(dictionary):
+    """ Utility function: traverse a dictionary and change all the strings in
+    the dictionary to ASCII from Unicode. Useful when reading ASCII JSON data,
+    because the JSON decoder always returns Unicode string. Based on
+    http://stackoverflow.com/a/13105359
+
+    Positional arguments:
+    dictionary - The dict that contains some Unicode that should be ASCII
+    """
+    if isinstance(dictionary, dict):
+        return OrderedDict([(dict_to_ascii(key), dict_to_ascii(value))
+                            for key, value in dictionary.iteritems()])
+    elif isinstance(dictionary, list):
+        return [dict_to_ascii(element) for element in dictionary]
+    elif isinstance(dictionary, unicode):
+        return dictionary.encode('ascii')
+    else:
+        return dictionary
+
+def json_file_to_dict(fname):
+    """ Read a JSON file and return its Python representation, transforming all
+    the strings from Unicode to ASCII. The order of keys in the JSON file is
+    preserved.
+
+    Positional arguments:
+    fname - the name of the file to parse
+    """
+    try:
+        with open(fname, "r") as file_obj:
+            return dict_to_ascii(json.load(file_obj,
+                                           object_pairs_hook=OrderedDict))
+    except (ValueError, IOError):
+        sys.stderr.write("Error parsing '%s':\n" % fname)
+        raise
+
+# Wowza, double closure
+def argparse_type(casedness, prefer_hyphen=False):
+    def middle(lst, type_name):
+        def parse_type(string):
+            """ validate that an argument passed in (as string) is a member of
+            the list of possible arguments. Offer a suggestion if the case of
+            the string, or the hyphens/underscores do not match the expected
+            style of the argument.
+            """
+            if prefer_hyphen:
+                newstring = casedness(string).replace("_", "-")
+            else:
+                newstring = casedness(string).replace("-", "_")
+            if string in lst:
+                return string
+            elif string not in lst and newstring in lst:
+                raise argparse.ArgumentTypeError(
+                    "{0} is not a supported {1}. Did you mean {2}?".format(
+                        string, type_name, newstring))
+            else:
+                raise argparse.ArgumentTypeError(
+                    "{0} is not a supported {1}. Supported {1}s are:\n{2}".
+                    format(string, type_name, columnate(lst)))
+        return parse_type
+    return middle
+
+# short cuts for the argparse_type versions
+argparse_uppercase_type = argparse_type(str.upper, False)
+argparse_lowercase_type = argparse_type(str.lower, False)
+argparse_uppercase_hyphen_type = argparse_type(str.upper, True)
+argparse_lowercase_hyphen_type = argparse_type(str.lower, True)
+
+def argparse_force_type(case):
+    """ validate that an argument passed in (as string) is a member of the list
+    of possible arguments after converting it's case.
+    """
+    def middle(lst, type_name):
+        """ The parser type generator"""
+        def parse_type(string):
+            """ The parser type"""
+            for option in lst:
+                if case(string) == case(option):
+                    return option
+            raise argparse.ArgumentTypeError(
+                "{0} is not a supported {1}. Supported {1}s are:\n{2}".
+                format(string, type_name, columnate(lst)))
+        return parse_type
+    return middle
+
+# these two types convert the case of their arguments _before_ validation
+argparse_force_uppercase_type = argparse_force_type(str.upper)
+argparse_force_lowercase_type = argparse_force_type(str.lower)
+
+def argparse_many(func):
+    """ An argument parser combinator that takes in an argument parser and
+    creates a new parser that accepts a comma separated list of the same thing.
+    """
+    def wrap(string):
+        """ The actual parser"""
+        return [func(s) for s in string.split(",")]
+    return wrap
+
+def argparse_filestring_type(string):
+    """ An argument parser that verifies that a string passed in corresponds
+    to a file"""
+    if exists(string):
+        return string
+    else:
+        raise argparse.ArgumentTypeError(
+            "{0}"" does not exist in the filesystem.".format(string))
+
+def argparse_profile_filestring_type(string):
+    """ An argument parser that verifies that a string passed in is either
+    absolute path or a file name (expanded to
+    mbed-os/tools/profiles/<fname>.json) of a existing file"""
+    fpath = join(dirname(__file__), "profiles/{}.json".format(string))
+    if exists(string):
+        return string
+    elif exists(fpath):
+        return fpath
+    else:
+        raise argparse.ArgumentTypeError(
+            "{0} does not exist in the filesystem.".format(string))
+
+def columnate(strings, separator=", ", chars=80):
+    """ render a list of strings as a in a bunch of columns
+
+    Positional arguments:
+    strings - the strings to columnate
+
+    Keyword arguments;
+    separator - the separation between the columns
+    chars - the maximum with of a row
+    """
+    col_width = max(len(s) for s in strings)
+    total_width = col_width + len(separator)
+    columns = math.floor(chars / total_width)
+    output = ""
+    for i, string in zip(range(len(strings)), strings):
+        append = string
+        if i != len(strings) - 1:
+            append += separator
+        if i % columns == columns - 1:
+            append += "\n"
+        else:
+            append = append.ljust(total_width)
+        output += append
+    return output
+
+def argparse_dir_not_parent(other):
+    """fail if argument provided is a parent of the specified directory"""
+    def parse_type(not_parent):
+        """The parser type"""
+        abs_other = abspath(other)
+        abs_not_parent = abspath(not_parent)
+        if abs_not_parent == commonprefix([abs_not_parent, abs_other]):
+            raise argparse.ArgumentTypeError(
+                "{0} may not be a parent directory of {1}".format(
+                    not_parent, other))
+        else:
+            return not_parent
+    return parse_type
+
+def argparse_deprecate(replacement_message):
+    """fail if argument is provided with deprecation warning"""
+    def parse_type(_):
+        """The parser type"""
+        raise argparse.ArgumentTypeError("Deprecated." + replacement_message)
+    return parse_type
+
+def print_large_string(large_string):
+    """ Breaks a string up into smaller pieces before print them
+
+    This is a limitation within Windows, as detailed here:
+    https://bugs.python.org/issue11395
+
+    Positional arguments:
+    large_string - the large string to print
+    """
+    string_limit = 1000
+    large_string_len = len(large_string)
+    num_parts = int(ceil(float(large_string_len) / float(string_limit)))
+    for string_part in range(num_parts):
+        start_index = string_part * string_limit
+        if string_part == num_parts - 1:
+            sys.stdout.write(large_string[start_index:])
+        else:
+            sys.stdout.write(large_string[start_index:
+                                          start_index + string_limit])
+    sys.stdout.write("\n")
+
+def intelhex_offset(filename, offset):
+    """Load a hex or bin file at a particular offset"""
+    _, inteltype = splitext(filename)
+    ih = IntelHex()
+    if inteltype == ".bin":
+        ih.loadbin(filename, offset=offset)
+    elif inteltype == ".hex":
+        ih.loadhex(filename)
+    else:
+        raise ToolException("File %s does not have a known binary file type"
+                            % filename)
+    return ih
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/utils.pyc b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/utils.pyc
new file mode 100755
index 0000000..1cf2a81
Binary files /dev/null and b/NPR_FW_source_2020_06_29/NPR_14/mbed-os/tools/utils.pyc differ
diff --git a/NPR_FW_source_2020_06_29/NPR_14/mbed_config.h b/NPR_FW_source_2020_06_29/NPR_14/mbed_config.h
new file mode 100755
index 0000000..012896d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/mbed_config.h
@@ -0,0 +1,40 @@
+/*
+ * mbed SDK
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// Automatically generated configuration file.
+// DO NOT EDIT, content will be overwritten.
+
+#ifndef __MBED_CONFIG_DATA__
+#define __MBED_CONFIG_DATA__
+
+// Configuration parameters
+#define MBED_CONF_EVENTS_SHARED_STACKSIZE                 1024        // set by library:events
+#define MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE          256         // set by library:drivers
+#define MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE          256         // set by library:drivers
+#define MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE       9600        // set by library:platform
+#define MBED_CONF_EVENTS_SHARED_DISPATCH_FROM_APPLICATION 0           // set by library:events
+#define MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES         0           // set by library:platform
+#define MBED_CONF_EVENTS_PRESENT                          1           // set by library:events
+#define MBED_CONF_RTOS_PRESENT                            1           // set by library:rtos
+#define MBED_CONF_EVENTS_SHARED_EVENTSIZE                 256         // set by library:events
+#define MBED_CONF_PLATFORM_STDIO_BAUD_RATE                9600        // set by library:platform
+#define CLOCK_SOURCE                                      USE_PLL_MSI // set by target:NUCLEO_L432KC
+#define MBED_CONF_EVENTS_SHARED_HIGHPRIO_STACKSIZE        1024        // set by library:events
+#define MBED_CONF_PLATFORM_STDIO_FLUSH_AT_EXIT            1           // set by library:platform
+#define MBED_CONF_EVENTS_SHARED_HIGHPRIO_EVENTSIZE        256         // set by library:events
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/DHCP_ARP.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/DHCP_ARP.cpp
new file mode 100755
index 0000000..190a788
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/DHCP_ARP.cpp
@@ -0,0 +1,737 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "DHCP_ARP.h"
+#include "mbed.h"
+#include "global_variables.h"
+#include "Eth_IPv4.h"
+#include "W5500.h"
+#include "HMI_telnet.h"
+
+// Content : DHCP server (for TDMA clients and point to point config)
+// ARP proxy for "bridged ethernet" emulation. 
+// ARP resolution (a little bit ugly)
+ 
+#define DHCP_ARP_tab_size 32
+#define DHCP_ARP_timeout 360 /*120*/
+static unsigned char DHCP_ARP_MAC[DHCP_ARP_tab_size][6];
+static unsigned long int DHCP_ARP_IP[DHCP_ARP_tab_size];
+static unsigned char DHCP_ARP_status[DHCP_ARP_tab_size];	//		DHCP						ARP
+															// 0:	Free						Free
+															// 1:	allocation in progress		(unused)
+															// 2:	allocated					Valid
+															// 3:	prefered but not allocated	Timeout_1
+static unsigned int DHCP_ARP_date[DHCP_ARP_tab_size];
+
+int compare_IP(unsigned char* IP1, unsigned char* IP2) {
+	int result;
+	int i;
+	result = 1;
+	for (i=0; i<4; i++) {
+		if (IP1[i] != IP2[i]) {
+			result = 0;
+		}
+	}
+	return result;
+}
+
+int compare_MAC(unsigned char* MAC1, unsigned char* MAC2) {
+	int result;
+	int i;
+	result = 1;
+	for (i=0; i<6; i++) {
+		if (MAC1[i] != MAC2[i]) {
+			result = 0;
+		}
+	}
+	return result;
+}
+
+// *** DHCP functions ***
+
+void reset_DHCP_table(LAN_conf_T* LAN_config) {
+	int i;
+	for (i=0; i<DHCP_ARP_tab_size; i++) {
+		DHCP_ARP_status[i] = 0;
+	}
+	
+}
+
+void DHCP_release (LAN_conf_T* LAN_config, unsigned char* client_MAC) {
+	int i;
+	for (i=0; i<DHCP_ARP_tab_size; i++) {
+		if ((compare_MAC( DHCP_ARP_MAC[i], client_MAC)) && (DHCP_ARP_status[i]))  {
+			DHCP_ARP_status[i] = 0;
+		}
+	}
+	
+}
+
+int lookfor_free_LAN_IP (LAN_conf_T* LAN_config, unsigned char* client_MAC, unsigned char* requested_IP, unsigned char* proposed_IP, int req_type) {
+	//req type : like DHCP. 1:discover 3:request
+	int answer=0;
+	int i_previous_alloc = 255;
+	int match_previous_alloc = 0;
+	int i,j;
+	unsigned long int proposed_IP_int = 0xFFFFFFFF;
+	int new_alloc_entry = 0;
+	unsigned char new_status;
+	//unsigned long int requested_IP_int;
+	unsigned long int req_IP_int; 
+	
+	req_IP_int = IP_char2int (requested_IP); 
+		
+	// 1) tests
+	// 1.1) lookfor client MAC in DHCP table
+	for (i=0; i<DHCP_ARP_tab_size; i++) {
+		if ((compare_MAC( DHCP_ARP_MAC[i], client_MAC)) && (DHCP_ARP_status[i]))  {
+			i_previous_alloc  = i;
+		}
+		//printf("MAC_comparison:%i %i\r\n", compare_MAC( LAN_config->DHCP_alloc_MAC[i], client_MAC), i);
+	}
+	//printf ("previous entry with same MAC: %i\r\n", i_previous_alloc);
+	// 1.2)check if matches previous allocation
+	if (i_previous_alloc!=255) {
+		if (DHCP_ARP_IP[i_previous_alloc] == req_IP_int) {
+			match_previous_alloc = 1;
+		} else {
+			match_previous_alloc = 0;
+		}
+		if (match_previous_alloc==1) {// matches previous allocation
+			// total match with previous allocation
+			answer = 1;
+			if (req_type==1) {
+				DHCP_ARP_status[i_previous_alloc] = 1;
+			}
+			if (req_type==3) {
+				DHCP_ARP_status[i_previous_alloc] = 2;
+				DHCP_ARP_date[i_previous_alloc] = GLOBAL_timer.read_us();
+			}
+		} else {
+			//address requested different from previous allocation
+			
+		}
+		//printf ("req matches previous:%i\r\n", match_previous_alloc);
+		
+	}
+	// 1.3) check if requested IP agreed : inside range
+	int requ_IP_inside_range;
+	if ( (req_IP_int >= LAN_config->DHCP_range_start) && (req_IP_int < (LAN_config->DHCP_range_start + LAN_config->DHCP_range_size)) ) {
+		requ_IP_inside_range = 1;
+	} else {
+		requ_IP_inside_range = 0;
+	}
+	//printf("requested ip inside range:%i\r\n", requ_IP_inside_range);
+	// 1.4) chech if requested IP is free (not allocated to another MAC)
+	int req_IP_free = 1;
+	for (i=0; i<DHCP_ARP_tab_size; i++) {
+		if ( (DHCP_ARP_IP[i] == req_IP_int) && (DHCP_ARP_status[i]==2) && (i != i_previous_alloc) ) {
+			req_IP_free = 0;
+		}
+	}
+	// 1.5) synthesis
+	int req_IP_agreed;
+	if ( (requ_IP_inside_range == 1) && (req_IP_free == 1) ) {
+		req_IP_agreed = 1;
+	} else {
+		req_IP_agreed = 0;
+	}
+	// 2.1) free previous DHCP entry
+	if ( (i_previous_alloc!=255) && (match_previous_alloc==0) && (req_IP_agreed==1) ) {
+		DHCP_ARP_status[i_previous_alloc] = 0;
+	}
+	// 2.2) look for unallocated IP
+	unsigned long int IP_tested;
+	int OK_loc;
+	int found_IP = 0;
+	if ( (req_type==1) && (req_IP_agreed==0) && (i_previous_alloc==255) ) {
+		for (i = (LAN_config->DHCP_range_size - 1); i>=0; i--) {
+			IP_tested = LAN_config->DHCP_range_start + i;
+			OK_loc=1;
+			for (j=0; j<DHCP_ARP_tab_size; j++) {
+				if ( (IP_tested == DHCP_ARP_IP[j]) && (DHCP_ARP_status[j]==2) ) { // a améliorer : trop simple
+					OK_loc = 0;
+				}
+			}
+			if (OK_loc == 1) {
+				proposed_IP_int = IP_tested;
+				found_IP = 1;
+			}
+		}
+		if (found_IP == 1) {
+			new_alloc_entry = 1;
+			IP_int2char (proposed_IP_int,proposed_IP);
+			new_status = 1; 
+			answer = 3;
+		}
+		//printf("case 2 new IP needed \r\n");
+	}
+	
+	// 2.3) anwser with previous allocation 
+	if ( (req_type == 1) && (req_IP_agreed==0) && (i_previous_alloc!=255) ) {
+		IP_int2char (DHCP_ARP_IP[i_previous_alloc], proposed_IP);
+		if (req_type == 1) { new_status = 1; }
+		if (req_type == 3) { 
+			new_status = 2; 
+			DHCP_ARP_date[i_previous_alloc] = GLOBAL_timer.read_us();
+		}
+		DHCP_ARP_status [i_previous_alloc] = new_status;
+		answer = 3;
+		//printf("case 3 answer with previous alloc\r\n");
+	}
+	
+	// 2.4) new IP agreed, but do match previous allocation
+	if ( (i_previous_alloc!=255) && (match_previous_alloc==0) && (req_IP_agreed==1) ) {
+		for (i=0; i<4; i++) {
+			proposed_IP [i] = requested_IP[i]; 
+		}
+		new_alloc_entry = 1; 
+		if (req_type == 1) { new_status = 1; }
+		if (req_type == 3) { new_status = 2; }
+		answer = 1;
+		//printf("case 4 new IP ok, do not match previous\r\n");
+	}
+	
+	// 2.5) new IP agreed and matches previous allocation
+	if ( (i_previous_alloc!=255) && (match_previous_alloc==1) && (req_IP_agreed==1) ) {
+		for (i=0; i<4; i++) {
+			proposed_IP [i] = requested_IP[i]; 
+		}
+		if (req_type == 1) { new_status = 1; }
+		if (req_type == 3) { 
+			new_status = 2; 
+			DHCP_ARP_date[i_previous_alloc] = GLOBAL_timer.read_us();
+		}
+		DHCP_ARP_status [i_previous_alloc] = new_status;
+		answer = 1;
+		//printf("case 5 IP requested match previous, and OK\r\n");
+	}
+	
+	// 2.6) new IP agreed, no previous allocation
+	if ( (i_previous_alloc==255) && (req_IP_agreed==1) ) {
+		for (i=0; i<4; i++) {
+			proposed_IP [i] = requested_IP[i]; 
+		}
+		new_alloc_entry = 1;
+		if (req_type == 1) { new_status = 1; }
+		if (req_type == 3) { new_status = 2; }
+		answer = 1;
+		//printf("case 6 IP requested ok, no previous alloc\r\n");
+	}
+
+	// new DHCP entry 
+	int free_DHCP_slot=255;
+	if (new_alloc_entry == 1) {
+		for (i=DHCP_ARP_tab_size-1; i>=0; i--) {
+			if (DHCP_ARP_status[i]!=2) {
+				free_DHCP_slot = i;
+			}
+			//printf("dhcp inside lookfor:%i stat:%i\r\n", i, LAN_config->DHCP_alloc_status[i]);
+		}
+		if (free_DHCP_slot!=255) {
+			DHCP_ARP_status[free_DHCP_slot] = new_status;
+			if (new_status == 2) {DHCP_ARP_date[free_DHCP_slot] = GLOBAL_timer.read_us();}
+			DHCP_ARP_IP[free_DHCP_slot] = IP_char2int(proposed_IP);
+			for (i=0; i<6; i++) {
+				DHCP_ARP_MAC[free_DHCP_slot][i] = client_MAC[i];
+			}
+			//printf("new DHCP entry OK, index %i status %i \r\n", free_DHCP_slot, new_status);
+		}
+	}
+	return answer;
+}
+
+void DHCP_server(LAN_conf_T* LAN_config, W5500_chip* W5500 ) {
+	static unsigned char RX_data[600];//600
+	unsigned char client_MAC[7];
+	unsigned char session_ID[5];
+	unsigned char requested_IP[5]={0,0,0,0,0};
+	unsigned char DHCP_server_IP[5]={0,0,0,0,0};
+	int RX_size, size_UDP, i;
+	unsigned char message_type_client = 0;
+	unsigned char message_type_server;
+	int index_opt_answer=240;
+	static unsigned char DHCP_answer[400];
+	unsigned char proposed_IP[4];
+	int loc_status;
+	
+	
+	RX_size = W5500_read_received_size(W5500, 3); 
+	if (RX_size>0) {
+		
+		size_UDP = W5500_read_UDP_pckt(W5500, 3, RX_data);
+		if (RX_data[8]==1) { // Valid DHCP request
+			
+			// *** DHCP request decoding ***
+			// client mac address read
+			for (i=0; i<6; i++) {
+				client_MAC[i] = RX_data[i+36];
+				//printf("%x:", client_MAC[i]);
+			}
+			// session ID (XID)
+			for (i=0; i<4; i++) {
+				session_ID[i] = RX_data[i+12];
+				//printf("%x:", session_ID[i]);
+			}
+			for (i=0; i<4; i++) {
+				requested_IP[i] = RX_data[i+20];
+			}
+			//printf("\r\n");
+			//printf("\r\nDHCP from client RXs:%d UDPs:%d\r\n", RX_size, size_UDP);
+			// DHCP option read
+			int option_pos;
+			unsigned char option_size;
+			unsigned char option_type;
+			option_pos = 248;
+			do {
+				option_type = RX_data[option_pos];
+				option_size = RX_data[option_pos+1];
+				//printf("option:%d\r\n",option_type);
+				
+				switch (option_type) {
+					case 53 : message_type_client = RX_data[option_pos+2]; break;
+					case 50 :
+						requested_IP[0] = RX_data[option_pos+2];
+						requested_IP[1] = RX_data[option_pos+3];
+						requested_IP[2] = RX_data[option_pos+4];
+						requested_IP[3] = RX_data[option_pos+5];
+						break;
+					case 54 : 
+						DHCP_server_IP[0] = RX_data[option_pos+2];
+						DHCP_server_IP[1] = RX_data[option_pos+3];
+						DHCP_server_IP[2] = RX_data[option_pos+4];
+						DHCP_server_IP[3] = RX_data[option_pos+5];
+						break;
+				} 
+				option_pos = option_pos + option_size + 2;
+			} while ((option_type != 255) && (option_pos < size_UDP));
+			
+			// independant DHCP answer fields
+			for (i=0; i<400; i++ )  {
+				DHCP_answer[i] = 0;
+			}
+			DHCP_answer[0] = 0x02;//answer
+			DHCP_answer[1] = 0x01;
+			DHCP_answer[2] = 0x06;
+			DHCP_answer[3] = 0x00;
+			for (i=0; i<4; i++) {// session ID
+				DHCP_answer[i+4] = session_ID[i];
+			}
+			for (i=0; i<6; i++) {// client MAC
+				DHCP_answer[i+28] = client_MAC[i];
+			}
+			DHCP_answer[236] = 0x63;//magic cookie
+			DHCP_answer[237] = 0x82;
+			DHCP_answer[238] = 0x53;
+			DHCP_answer[239] = 0x63;
+			
+			// decision
+			loc_status = lookfor_free_LAN_IP (LAN_config, client_MAC, requested_IP, proposed_IP, message_type_client);
+			
+			if (message_type_client == 1) { // discover -> offer
+				
+				for (i=0; i<4; i++) { //proposed IP
+					DHCP_answer[i+16] = proposed_IP[i];
+				}
+				
+				message_type_server = 2;
+				DHCP_answer[index_opt_answer]=53; // message type
+				DHCP_answer[index_opt_answer+1]=1;
+				DHCP_answer[index_opt_answer+2]=message_type_server;
+				index_opt_answer = index_opt_answer +3;
+				DHCP_answer[index_opt_answer]=1; // subnet mask
+				DHCP_answer[index_opt_answer+1]=4;
+				IP_int2char (LAN_config->LAN_subnet_mask, (DHCP_answer + index_opt_answer + 2) );
+				index_opt_answer = index_opt_answer +6;
+				if (LAN_config->LAN_def_route_activ == 1) {
+					DHCP_answer[index_opt_answer]=3; // default route
+					DHCP_answer[index_opt_answer+1]=4;
+
+					IP_int2char (LAN_config->LAN_def_route, (DHCP_answer + index_opt_answer + 2) );
+					index_opt_answer = index_opt_answer +6;
+				}
+				if (LAN_config->LAN_DNS_activ == 1) {
+					DHCP_answer[index_opt_answer]=6; // DNS server
+					DHCP_answer[index_opt_answer+1]=4;
+
+					IP_int2char (LAN_config->LAN_DNS_value, (DHCP_answer + index_opt_answer + 2) );
+					index_opt_answer = index_opt_answer +6;
+				}
+				DHCP_answer[index_opt_answer]=51; //Lease Time
+				DHCP_answer[index_opt_answer+1]=4;
+				DHCP_answer[index_opt_answer+2]=0x00;
+				DHCP_answer[index_opt_answer+3]=0x00;//01
+				DHCP_answer[index_opt_answer+4]= (DHCP_ARP_timeout & 0xFF00) >> 8;//0x00
+				//DHCP_answer[index_opt_answer+5]=0x3C;//80
+				DHCP_answer[index_opt_answer+5]= DHCP_ARP_timeout & 0xFF;//DHCP_ARP_timeout
+				index_opt_answer = index_opt_answer +6;
+				DHCP_answer[index_opt_answer]=54; // DHCP server IP
+				DHCP_answer[index_opt_answer+1]=4;
+				IP_int2char (LAN_config->LAN_modem_IP, (DHCP_answer + index_opt_answer + 2) );
+				index_opt_answer = index_opt_answer + 6;
+				//DHCP_answer[index_opt_answer]=26; // Interface MTU
+				//DHCP_answer[index_opt_answer+1]=2;
+				//DHCP_answer[index_opt_answer+2]=0x03;//02
+				//DHCP_answer[index_opt_answer+3]=0xE8;//40
+				//index_opt_answer = index_opt_answer + 4;
+				//DHCP_answer[index_opt_answer]=27; // subnets local
+				//DHCP_answer[index_opt_answer+1]=1;
+				//DHCP_answer[index_opt_answer+2]=0x01;
+				//index_opt_answer = index_opt_answer + 3;
+				DHCP_answer[index_opt_answer]=255;// end
+				index_opt_answer = index_opt_answer + 1;
+				W5500_write_TX_buffer(W5500, 3, DHCP_answer, index_opt_answer, 1);
+			}
+			
+			if ( (message_type_client == 3) && (loc_status !=0 ) )  { // request -> ack
+				for (i=0; i<4; i++) { //proposed IP 
+					DHCP_answer[i+16] = proposed_IP[i];
+				}
+				
+				message_type_server = 5;
+				DHCP_answer[index_opt_answer]=53; // message type
+				DHCP_answer[index_opt_answer+1]=1;
+				DHCP_answer[index_opt_answer+2]=message_type_server;
+				index_opt_answer = index_opt_answer +3;
+				DHCP_answer[index_opt_answer]=1; // subnet mask
+				DHCP_answer[index_opt_answer+1]=4;
+				IP_int2char (LAN_config->LAN_subnet_mask, (DHCP_answer + index_opt_answer + 2) );
+				index_opt_answer = index_opt_answer +6;
+				if (LAN_config->LAN_def_route_activ == 1) {
+					DHCP_answer[index_opt_answer]=3; // default route
+					DHCP_answer[index_opt_answer+1]=4;
+
+					IP_int2char (LAN_config->LAN_def_route, (DHCP_answer + index_opt_answer + 2) );
+					index_opt_answer = index_opt_answer +6;
+				}
+				if (LAN_config->LAN_DNS_activ == 1) {
+					DHCP_answer[index_opt_answer]=6; // DNS server
+					DHCP_answer[index_opt_answer+1]=4;
+
+					IP_int2char (LAN_config->LAN_DNS_value, (DHCP_answer + index_opt_answer + 2) );
+					index_opt_answer = index_opt_answer +6;
+				}
+				DHCP_answer[index_opt_answer]=51; //Lease Time
+				DHCP_answer[index_opt_answer+1]=4;
+				DHCP_answer[index_opt_answer+2]=0x00;
+				DHCP_answer[index_opt_answer+3]=0x00;//01
+				DHCP_answer[index_opt_answer+4]= (DHCP_ARP_timeout & 0xFF00) >> 8;//51
+				DHCP_answer[index_opt_answer+5]= DHCP_ARP_timeout & 0xFF;
+				index_opt_answer = index_opt_answer +6;
+				DHCP_answer[index_opt_answer]=54; // DHCP server IP
+				DHCP_answer[index_opt_answer+1]=4;
+				IP_int2char (LAN_config->LAN_modem_IP, (DHCP_answer + index_opt_answer + 2) );
+				index_opt_answer = index_opt_answer + 6;
+				//DHCP_answer[index_opt_answer]=26; // Interface MTU
+				//DHCP_answer[index_opt_answer+1]=2;
+				//DHCP_answer[index_opt_answer+2]=0x03;//02
+				//DHCP_answer[index_opt_answer+3]=0xE8;//40
+				//index_opt_answer = index_opt_answer + 4;
+				//DHCP_answer[index_opt_answer]=27; // subnets local
+				//DHCP_answer[index_opt_answer+1]=1;
+				//DHCP_answer[index_opt_answer+2]=0x01;
+				//index_opt_answer = index_opt_answer + 3;
+				DHCP_answer[index_opt_answer]=255;// end
+				index_opt_answer = index_opt_answer + 1;
+				W5500_write_TX_buffer(W5500, 3, DHCP_answer, index_opt_answer, 1);
+			}
+			
+			if ( (message_type_client == 3) && (loc_status ==0 ) ) { //request -> NAK
+				//printf ("NAK NAK\r\n");
+				message_type_server = 6; // NAK
+				DHCP_answer[index_opt_answer]=53; // message type
+				DHCP_answer[index_opt_answer+1]=1;
+				DHCP_answer[index_opt_answer+2]=message_type_server;
+				index_opt_answer = index_opt_answer +3;
+				DHCP_answer[index_opt_answer]=255;// end
+				index_opt_answer = index_opt_answer + 1;
+				W5500_write_TX_buffer(W5500, 3, DHCP_answer, index_opt_answer, 1);
+			}
+			
+			if ( message_type_client == 7 ) { // DHCP RELEASE
+				//printf ("DHCP RELEASE\r\n");
+				DHCP_release (LAN_config, client_MAC); 
+			}	
+		}
+	}
+}
+
+void DHCP_ARP_print_entries(void) {
+	int i;
+	unsigned char loc_IP_char[10];
+	for (i=0; i<DHCP_ARP_tab_size; i++) {
+		if (DHCP_ARP_status[i]!=0) {
+			IP_int2char (DHCP_ARP_IP[i], loc_IP_char);
+			HMI_printf ("   %i:stat:%i IP:", i, DHCP_ARP_status[i]);
+			HMI_printf ("%i.%i.%i.%i MAC:", loc_IP_char[0], loc_IP_char[1], loc_IP_char[2], loc_IP_char[3]);
+			HMI_printf("%02X:", DHCP_ARP_MAC[i][0]);
+			HMI_printf("%02X:", DHCP_ARP_MAC[i][1]);
+			HMI_printf("%02X:", DHCP_ARP_MAC[i][2]);
+			HMI_printf("%02X:", DHCP_ARP_MAC[i][3]);
+			HMI_printf("%02X:", DHCP_ARP_MAC[i][4]);
+			HMI_printf("%02X ", DHCP_ARP_MAC[i][5]);
+			HMI_printf("age:%isec\r\n", (GLOBAL_timer.read_us()-DHCP_ARP_date[i])/1000000);
+		}
+	}
+	HMI_printf("\r\nready> ");
+}
+
+// *** ARP proxy and ARP resolver ***
+
+void ARP_proxy (unsigned char* ARP_req_packet, int size) {
+	int answer_needed = 0;
+	int i;
+	int is_inside_subnet = 0;
+	int is_inside_client_range = 0; 
+	unsigned long int ARP_client_IP;
+	unsigned long int ARP_requested_IP;
+	unsigned char ARP_client_MAC[6]; 
+		
+	unsigned char ARP_answ_packet[50] = {
+		0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,	// dest MAC
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	// source MAC
+		0x08, 0x06, 						// Ethtype ARP
+		0x00, 0x01,							// HW type Ethernet
+		0x08, 0x00, 						// protocol IPv4
+		0x06, 								// HW addr size
+		0x04, 								// protocol size
+		0x00, 0x02	 						// ARP opcode "reply"
+	};
+	
+	ARP_client_IP = IP_char2int (ARP_req_packet+28); //in request : client = sender
+	ARP_requested_IP = IP_char2int (ARP_req_packet+38); //in request : server = target
+	for (i=0; i<6; i++) {
+		ARP_client_MAC[i] = ARP_req_packet[22+i]; // in request : client = sender
+	}
+	
+	// determines if modem should reply or not 
+	if (ARP_requested_IP != LAN_conf_applied.LAN_modem_IP) { //only replies to non-modem IP
+	
+		if (is_TDMA_master == 1) { 
+		//TDMA Master (and FDD down) answers to all IP in radio range
+			if ( (ARP_requested_IP >= CONF_radio_IP_start) && (ARP_requested_IP < (CONF_radio_IP_start + CONF_radio_IP_size) ) ) {
+				answer_needed = 1;
+			}
+		}
+		else { //TDMA Slave answers to IP inside subnet, but which dont belong to it's own range
+			if ( (ARP_requested_IP & LAN_conf_applied.LAN_subnet_mask) == (LAN_conf_applied.LAN_modem_IP & LAN_conf_applied.LAN_subnet_mask) ) {
+				is_inside_subnet = 1;
+			}
+			if ( (ARP_requested_IP >= LAN_conf_applied.DHCP_range_start) && (ARP_requested_IP < (LAN_conf_applied.DHCP_range_start + LAN_conf_applied.DHCP_range_size)) ) {
+				is_inside_client_range = 1;
+			}
+			if ( (is_inside_subnet == 1) && (is_inside_client_range == 0) ) {
+				answer_needed = 1;
+			}
+		}
+	}
+	
+	if (answer_needed) {
+		for (i=0; i<6; i++) {				// Destination MAC
+			ARP_answ_packet[i] = ARP_client_MAC[i];
+		}
+		for (i=0; i<6; i++) {				// Source MAC
+			ARP_answ_packet[i+6] = CONF_modem_MAC[i];
+		}
+		for (i=0; i<6; i++) {				// ARP Sender MAC
+			ARP_answ_packet[i+22] = CONF_modem_MAC[i];
+		}
+		//IP_int2char (LAN_config.LAN_modem_IP, (ARP_answ_packet + 28) ); // ARP sender IP
+		IP_int2char (ARP_requested_IP, (ARP_answ_packet + 28) ); // ARP sender IP
+		for (i=0; i<6; i++) {				// ARP Target MAC
+			ARP_answ_packet[i+32] = ARP_client_MAC[i];
+		}
+		IP_int2char (ARP_client_IP, (ARP_answ_packet + 38) ); //ARP target IP
+		
+		W5500_write_TX_buffer(W5500_p1, 0, ARP_answ_packet, 42, 0);
+	}
+}
+
+void ARP_client_request (unsigned long int IP_requested) {
+	unsigned char ARP_packet[50] = {
+		0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,	// dest MAC
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	// source MAC
+		0x08, 0x06, 						// Ethtype ARP
+		0x00, 0x01,							// HW type Ethernet
+		0x08, 0x00, 						// protocol IPv4
+		0x06, 								// HW addr size
+		0x04, 								// protocol size
+		0x00, 0x01	 						// ARP opcode "request"
+	};
+	int i;
+	for (i=0; i<6; i++) { // source MAC
+		ARP_packet[i+6] = CONF_modem_MAC[i];
+	}
+	for (i=0; i<6; i++) { // ARP sender MAC
+		ARP_packet[i+22] = CONF_modem_MAC[i];
+	}
+	IP_int2char (LAN_conf_applied.LAN_modem_IP, (ARP_packet + 28) ); //ARP sender IP
+	for (i=0; i<6; i++) { // target MAC : unknown
+		ARP_packet[i+32] = 0;
+	}
+	IP_int2char (IP_requested, (ARP_packet + 38) ); //ARP Target IP
+	W5500_write_TX_buffer(W5500_p1, 0, ARP_packet, 42, 0);
+}
+
+void ARP_client_answer_treatment (unsigned char* ARP_RX_packet, int size) {
+	unsigned long int ARP_sender_IP;
+	unsigned long int ARP_target_IP;
+	unsigned char ARP_sender_MAC[6];
+	int entry_already_exists = 0;
+	int i_existing_entry = 0;
+	int i_free_entry = 255;
+	int i;
+	
+	ARP_sender_IP = IP_char2int (ARP_RX_packet+28);
+	ARP_target_IP = IP_char2int (ARP_RX_packet+38);
+	for (i=0; i<6; i++) {
+		ARP_sender_MAC[i] = ARP_RX_packet[22+i];
+	}
+	if (ARP_target_IP == LAN_conf_applied.LAN_modem_IP) { //if ARP reply is for us
+		//first look for existing entry
+		//printf("ARP reply is for us IP %X\r\n", ARP_sender_IP);
+		entry_already_exists = 0;
+		for (i=0; i<DHCP_ARP_tab_size; i++) {
+			if (DHCP_ARP_IP[i] == ARP_sender_IP) {
+				entry_already_exists = 1;
+				i_existing_entry = i;
+				//printf ("matches %i\r\n", i);
+			}
+		}
+		if (entry_already_exists == 1) { // replace existing entry
+			//printf("ARP entry already exists %i\r\n", i_existing_entry);
+			for (i=0; i<6; i++) {
+				DHCP_ARP_MAC[i_existing_entry][i] = ARP_sender_MAC[i];
+			}
+			DHCP_ARP_status[i_existing_entry] = 2; // valid entry
+			DHCP_ARP_date[i_existing_entry] = GLOBAL_timer.read_us();
+		} 
+		else { // no entry, lookfor empty slot
+			for (i=DHCP_ARP_tab_size-1; i>=0; i--) {
+				if ( DHCP_ARP_status[i] == 0 ) {
+					i_free_entry = i;
+				}
+			}
+			if (i_free_entry < DHCP_ARP_tab_size) {// free entry exists
+				for (i=0; i<6; i++) {
+					DHCP_ARP_MAC[i_free_entry][i] = ARP_sender_MAC[i];
+				}
+				DHCP_ARP_status[i_free_entry] = 2; // valid entry
+				DHCP_ARP_IP[i_free_entry] = ARP_sender_IP;
+				DHCP_ARP_date[i_free_entry] = GLOBAL_timer.read_us();
+			}
+		}
+	}
+	flush_temp_Eth_buffer (ARP_sender_IP);
+} 
+
+void ARP_RX_packet_treatment (unsigned char* ARP_RX_packet, int size) {
+	unsigned int ARP_protocol_type;
+	unsigned int ARP_opcode;
+	unsigned long int ARP_sender_IP;
+	unsigned long int ARP_target_IP;
+	ARP_protocol_type = ARP_RX_packet[16]*0x100 + ARP_RX_packet[17];
+	ARP_opcode = ARP_RX_packet[20]*0x100 + ARP_RX_packet[21];
+	if ( (ARP_protocol_type == 0x0800) && (ARP_opcode == 0x0001) ) { // request
+		//printf ("ARP request\r\n");
+		ARP_sender_IP = IP_char2int (ARP_RX_packet+28);
+		ARP_target_IP = IP_char2int (ARP_RX_packet+38);
+		if (ARP_sender_IP != ARP_target_IP) {//ignores gratuitous ARP request
+			//printf ("real ARP request\r\n");
+			ARP_proxy(ARP_RX_packet, size);
+		}
+		else {
+			//printf ("gratuitous!\r\n");
+		}
+	}
+	if ( (ARP_protocol_type == 0x0800) && (ARP_opcode == 0x0002) ) { // reply
+		//printf ("ARP reply\r\n");
+		if ( (LAN_conf_applied.DHCP_server_active == 0) || (is_TDMA_master) ){//only active if modem is no DHCP server
+			ARP_client_answer_treatment (ARP_RX_packet, size);
+		}
+	}
+}
+
+void DHCP_ARP_periodic_free_table () {
+	int i;
+	unsigned int loc_age;
+	for (i=0; i<DHCP_ARP_tab_size; i++) {
+		loc_age = GLOBAL_timer.read_us() - DHCP_ARP_date[i];
+		if ( (DHCP_ARP_status[i] == 2) && (loc_age > 1000000 * DHCP_ARP_timeout) ) {
+			DHCP_ARP_status[i] = 3;
+		}
+	}
+}
+
+// *** generic functions ***
+int lookfor_MAC_from_IP (unsigned char* MAC_out, unsigned long int IP_addr) {
+	int result = 0; 
+	int i;
+	int i_found = 300;
+	unsigned int age_loc=0;
+	if ( (LAN_conf_applied.DHCP_server_active == 1) && (is_TDMA_master == 0) ) { //resolution for DHCP
+		i_found = 300;
+		for (i=0; i<DHCP_ARP_tab_size; i++) {
+			if ( (DHCP_ARP_IP[i] == IP_addr) && (DHCP_ARP_status[i] == 2) ) {
+				i_found = i;
+			}
+		}
+		if (i_found < DHCP_ARP_tab_size) {
+			for (i=0; i<6; i++) {
+				MAC_out[i] = DHCP_ARP_MAC[i_found][i];
+			}
+			result = 1;
+		}
+	}
+	else { // resolution for ARP (DHCP not active)
+		i_found = 300;
+		for (i=0; i<DHCP_ARP_tab_size; i++) {
+			if ( (DHCP_ARP_IP[i] == IP_addr) && ( (DHCP_ARP_status[i] == 2) || (DHCP_ARP_status[i] == 3) ) ) {
+				i_found = i;
+			}
+		}
+		if (i_found < DHCP_ARP_tab_size) { // existing entry
+			age_loc = GLOBAL_timer.read_us() - DHCP_ARP_date[i_found];
+			age_loc = age_loc / 1000000;
+			if (age_loc < (DHCP_ARP_timeout / 2) ) {
+				for (i=0; i<6; i++) {
+					MAC_out[i] = DHCP_ARP_MAC[i_found][i];
+				}
+				result = 1;
+			}
+			else if (age_loc < DHCP_ARP_timeout) {
+				for (i=0; i<6; i++) {
+					MAC_out[i] = DHCP_ARP_MAC[i_found][i];
+				}
+				result = 1;
+				ARP_client_request(IP_addr);
+			}
+			else {
+				ARP_client_request(IP_addr); //
+				IP_addr = 0; 
+				result = 0;
+			}
+		}
+		else {//no entry found, send ARP request
+			ARP_client_request(IP_addr); //
+			IP_addr = 0; 
+			result = 0;
+		}
+	}
+	return result;	// 0 if no entry found yet (most often: ARP resolution not yet answered)
+					// 1 if entry present
+}
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/DHCP_ARP.h b/NPR_FW_source_2020_06_29/NPR_14/source/DHCP_ARP.h
new file mode 100755
index 0000000..ef7fe73
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/DHCP_ARP.h
@@ -0,0 +1,46 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2018 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef DHCP_ARP_F4
+#define DHCP_ARP_F4
+
+#include "mbed.h"
+#include "W5500.h"
+#include "global_variables.h"
+
+void reset_DHCP_table(LAN_conf_T* LAN_config);
+
+int lookfor_free_LAN_IP (LAN_conf_T* LAN_config, unsigned char* client_MAC, unsigned char* requested_IP, unsigned char* proposed_IP, int req_type);
+
+void DHCP_server(LAN_conf_T* LAN_config, W5500_chip* W5500);
+
+void DHCP_ARP_print_entries(void);
+
+// *** ARP part *** 
+void ARP_proxy (unsigned char* ARP_RX_packet);
+
+void ARP_client_request (unsigned long int IP);
+
+void ARP_client_answer_treatment (unsigned char* ARP_RX_packet, int size);
+
+void ARP_RX_packet_treatment (unsigned char* ARP_RX_packet, int size);
+
+int lookfor_MAC_from_IP (unsigned char* MAC_out, unsigned long int IP_addr);
+
+void DHCP_ARP_periodic_free_table (void);
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/Eth_IPv4.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/Eth_IPv4.cpp
new file mode 100755
index 0000000..cbfc9bd
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/Eth_IPv4.cpp
@@ -0,0 +1,302 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "Eth_IPv4.h"
+#include "mbed.h"
+#include "global_variables.h"
+#include "L1L2_radio.h"
+#include "DHCP_ARP.h"
+
+static unsigned char temp_Eth_buffer[1600];//temporary buffer waiting for ARP entry
+static unsigned long int temp_Eth_buff_IP;
+static int temp_Eth_buff_size = 0;
+
+unsigned long int IP_char2int(unsigned char* IP_char) {
+	unsigned long int result;
+	result = 0x1000000*IP_char[0] + 0x10000*IP_char[1] + 0x100*IP_char[2] + IP_char[3];
+	return result;
+}
+
+void IP_int2char (unsigned long int IP_int, unsigned char* IP_char) {
+	IP_char[0] = (IP_int & 0xFF000000) / 0x1000000;
+	IP_char[1] = (IP_int & 0x00FF0000) / 0x10000;
+	IP_char[2] = (IP_int & 0x0000FF00) / 0x100;
+	IP_char[3] = (IP_int & 0xFF);
+} 
+
+//static unsigned char match_RTP_value[2][12] = {// FOR TEST ONLY
+//	{0x00, 0x13, 0x3B, 0x73, 0x12, 0xAE},
+//	{0x98, 0xDE, 0xD0, 0x01, 0x2D, 0x09} 
+//}; //first ping test : MAC filter
+
+//void init_RTP_filter(void) {
+//	
+//}
+
+int Eth_RX_dequeue (W5500_chip* W5500) {
+	int answer=0;
+	unsigned char RX_data[1600];//1600
+	unsigned int RX_port=0;
+	unsigned char RX_proto;
+	unsigned long int RX_dest_IP=0;
+	//unsigned char* RX_Eth_pckt;
+	//static int match_RTP_index[12] = {8, 9, 10, 11, 12, 13}; //first ping tests : TX MAC filter
+	
+	static int more_to_read = 0;
+	
+	int RX_size=0;
+	int mac_size=0;
+	//int i;
+	//int match_RTP = 1;
+	unsigned int ethertype;
+	if (*(W5500->interrupt)==0) {
+		W5500_write_byte(W5500, 0x0002, 1, 0xFF);//ack interrupt
+		more_to_read=1;
+	}
+	if ((more_to_read == 1))  { 
+		RX_size = W5500_read_received_size(W5500, 0); 
+		//if (RX_size > DEBUG_max_rx_size_w5500) {//!!!
+		//	DEBUG_max_rx_size_w5500 = RX_size;//!!!
+		//	printf("max buffer:%i\r\n", DEBUG_max_rx_size_w5500);//!!!
+		//}//!!!
+		if (RX_size > 0) {
+			answer=1;
+
+			mac_size = W5500_read_MAC_pckt(W5500, 0, RX_data);
+			if (RX_size > mac_size) {
+				more_to_read = 1;
+			} else {
+				more_to_read = 0;
+			}
+
+			// Check if RTP packet
+			RX_Eth_IPv4_counter++;
+			//match_RTP = 1;
+			//for (i=0; i<=6; i++) {
+			//	if (RX_data[match_RTP_index[i]] != match_RTP_value[is_TDMA_master][i]) {
+			//		match_RTP = 0;
+			//	}
+				
+			//}
+			// FOR FUTURE VIRTUAL CHANNEL 
+			//if (match_RTP==1) {
+			//	W5500_write_TX_buffer(W5500, 2, RX_data+44, mac_size-44, 0);
+			//} 
+			
+			ethertype = RX_data[14]*0x100 + RX_data[15];
+			
+			if (ethertype == 0x0806) { //ARP packet received
+				//printf("ARP packet received!\r\n");
+				if ((is_TDMA_master == 0)||(CONF_master_FDD<2)) {
+					ARP_RX_packet_treatment (RX_data+2, mac_size-2);
+				}
+			}
+			
+			if (ethertype == 0x0800) { // IPv4 packet
+				RX_port = 0;
+				RX_proto = 0;
+				RX_dest_IP = 0;
+				if ( (is_TDMA_master==1) && (CONF_master_FDD == 1) ) {//master down
+					//RX_Eth_pckt = RX_data+2;
+					RX_port = (RX_data[38] << 8) + RX_data[39];
+					RX_proto = RX_data[25];//11 for UDP
+					RX_dest_IP = IP_char2int(RX_data+32);
+				}
+				if ( (RX_proto == 0x11) && (RX_dest_IP == LAN_conf_applied.LAN_modem_IP) && (RX_port == 0x1A3C) ) { // data for FDD down
+					//printf("RX_from_Eth\r\n");
+					FDDdown_RX_pckt_treat(RX_data+44, mac_size-44);
+				} else {
+					//printf("RXeth %i\r\n", mac_size-2);
+					IPv4_to_radio (RX_data+2, mac_size-2);
+					//Eth_pause_frame_TX(10);//!!!
+				}
+			}
+			
+						
+		}
+	}
+	return answer;
+}
+
+void Eth_pause_frame_TX(unsigned int time) {
+	int i;
+	unsigned char pause_frame[70] = {
+		0x01, 0x80, 0xC2, 0x00, 0x00, 0x01,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x88, 0x08, 0x00, 0x01, 0x4E, 0x70,/* 0x17, 0x70 */
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	for (i=0; i<6; i++) {
+		pause_frame[i+6] = CONF_modem_MAC[i];
+	}
+	W5500_write_TX_buffer(W5500_p1, 0, pause_frame, 60, 0); 
+}
+
+void IPv4_to_radio (unsigned char* RX_Eth_frame, int size) {
+	int i;
+	unsigned long int dest_IP_addr;
+	int MAC_dest_match = 1;
+	int is_inside_subnet = 0;
+	int is_inside_client_range = 0; 
+	unsigned char loc_client_ID;
+	int radio_tx_need;
+	for (i=0; i<6; i++) { 
+		if (RX_Eth_frame[i] != CONF_modem_MAC[i]) {
+			MAC_dest_match = 0;
+		}
+	}
+	radio_tx_need = 0;
+	if (MAC_dest_match == 1) {//we only take frame with destination = modem_MAC, not broadcast or multicast
+		dest_IP_addr = IP_char2int(RX_Eth_frame+30); 
+		
+		if ( (is_TDMA_master == 1) && (dest_IP_addr != LAN_conf_applied.LAN_modem_IP) ) { // TDMA Master
+			if ( (dest_IP_addr >= CONF_radio_IP_start) && (dest_IP_addr < (CONF_radio_IP_start + CONF_radio_IP_size) ) ) {
+				loc_client_ID = lookfor_client_ID_from_IP (dest_IP_addr); 
+				//printf ("IP %X is client %i\r\n", dest_IP_addr, loc_client_ID);
+				if (loc_client_ID < 250) {
+					radio_tx_need = 1; 
+					
+				}
+			}
+		}
+		if ( (is_TDMA_master == 0) && (dest_IP_addr != LAN_conf_applied.LAN_modem_IP) ) { // TDMA Client
+			if ( (dest_IP_addr & LAN_conf_applied.LAN_subnet_mask) == (LAN_conf_applied.LAN_modem_IP & LAN_conf_applied.LAN_subnet_mask) ) {
+				is_inside_subnet = 1;
+			}
+			if ( (dest_IP_addr >= LAN_conf_applied.DHCP_range_start) && (dest_IP_addr < (LAN_conf_applied.DHCP_range_start + LAN_conf_applied.DHCP_range_size)) ) {
+				is_inside_client_range = 1;
+			}
+			//printf ("inside subnet:%i inside_DHCP%i\r\n", is_inside_subnet, is_inside_client_range);
+			// inside subnet but outside radio range -> to master
+			if ( (is_inside_subnet == 1) && (is_inside_client_range == 0) ) {
+				loc_client_ID = my_radio_client_ID;
+				radio_tx_need = 1;
+			}
+			// outside subnet and IP gateway active -> to master
+			if ( (is_inside_subnet == 0) && (LAN_conf_applied.LAN_def_route_activ == 1) ) {
+				loc_client_ID = my_radio_client_ID;
+				radio_tx_need = 1;
+			}
+		}
+
+		if ( (radio_tx_need) && (my_client_radio_connexion_state == 2) ) {
+			segment_and_push(RX_Eth_frame + 14, size - 14, loc_client_ID, 0x02); //0x02 is IPv4 access protocol
+			//printf("seg&push %i\r\n", size - 14);
+		}
+	}
+}
+
+void IPv4_from_radio (unsigned char* RX_eth_frame, int RX_size) { //Rx size includes ethernet header
+	unsigned long int dest_IP_addr;
+	unsigned long int LAN_dest_IP;
+	int local_size;
+	int dest_MAC_found;
+	int is_inside_subnet = 0;
+	int is_inside_radio_range = 0;
+	unsigned char loc_client_ID;
+	int i;
+	//dest_IP_addr = IP_char2int(RX_radio_frame+16)
+	int eth_TX_need = 0; 
+	int radio_tx_need = 0;
+	dest_IP_addr = IP_char2int(RX_eth_frame + 30); 
+	
+	local_size = 0x100*RX_eth_frame[16] + RX_eth_frame[17];
+	//printf("size IPv4 : %i\r\n", local_size);
+	
+	//printf (" IPv4 radio RX\r\n");
+	if (is_TDMA_master == 1) { // TDMA Master
+		if ( (dest_IP_addr & LAN_conf_applied.LAN_subnet_mask) == (LAN_conf_applied.LAN_modem_IP & LAN_conf_applied.LAN_subnet_mask) ) {
+			is_inside_subnet = 1;
+		}
+		if ( (dest_IP_addr >= CONF_radio_IP_start) && (dest_IP_addr < (CONF_radio_IP_start + CONF_radio_IP_size) ) ) {
+			is_inside_radio_range = 1;
+		}
+		//printf("IPv4 from R: inside subnet:%i inside_radio:%i\r\n", is_inside_subnet, is_inside_radio_range);
+		// destinated to IP on LAN 
+		if ( (is_inside_subnet == 1) && (is_inside_radio_range == 0) ) {
+			eth_TX_need = 1;
+			LAN_dest_IP = dest_IP_addr;
+		}
+		// destinated to gateway (out of subnet)
+		if ( (is_inside_subnet == 0) && (LAN_conf_applied.LAN_def_route_activ == 1) ) {
+			eth_TX_need = 1;
+			LAN_dest_IP = LAN_conf_applied.LAN_def_route;
+		}
+		//forward to another radio client
+		if (is_inside_radio_range) {
+			loc_client_ID = lookfor_client_ID_from_IP (dest_IP_addr); 
+			if (loc_client_ID < 250) {
+				radio_tx_need = 1;
+			}
+		}
+	}
+	if (is_TDMA_master == 0) { // TDMA client
+		// Checks if dest IP is inside local range
+		if ( (dest_IP_addr >= LAN_conf_applied.DHCP_range_start) && (dest_IP_addr < (LAN_conf_applied.DHCP_range_start + LAN_conf_applied.DHCP_range_size)) ) { 
+			eth_TX_need = 1;
+			LAN_dest_IP = dest_IP_addr;
+		}
+	}
+	// transmit to Ethernet
+	if ( (eth_TX_need) && (local_size < 1510) ) {
+		//printf("IPv4 Eth TX\r\n");
+		for (i=0; i<6; i++) {
+			RX_eth_frame[i+6] = CONF_modem_MAC[i];
+		}
+		RX_eth_frame[12] = 0x08; // Ethertype IPv4
+		RX_eth_frame[13] = 0x00; 
+		dest_MAC_found = lookfor_MAC_from_IP (RX_eth_frame, LAN_dest_IP);
+		if (dest_MAC_found) {		
+			W5500_write_TX_buffer(W5500_p1, 0, RX_eth_frame, local_size + 14, 0); 
+			//RX_radio_IPv4_counter++;
+		}
+		else {
+			temp_Eth_buff_IP = LAN_dest_IP;
+			temp_Eth_buff_size = local_size + 14;
+			memcpy (temp_Eth_buffer, RX_eth_frame, temp_Eth_buff_size); 
+		}
+	}
+	// transmit to radio
+	if (radio_tx_need) {
+		segment_and_push(RX_eth_frame + 14, local_size, loc_client_ID, 0x02); //0x02 is IPv4 access protocol
+		//TX_radio_IPv4_counter++;
+	}
+}
+
+void flush_temp_Eth_buffer(unsigned long int loc_IP) {
+	if (temp_Eth_buff_size > 0) {
+		if (loc_IP == temp_Eth_buff_IP) {
+			lookfor_MAC_from_IP (temp_Eth_buffer, loc_IP); //puts MAC inside Eth
+			W5500_write_TX_buffer(W5500_p1, 0, temp_Eth_buffer, temp_Eth_buff_size, 0); 
+			//RX_radio_IPv4_counter++;
+		}
+		temp_Eth_buff_size = 0;
+	}
+}
+
+unsigned char lookfor_client_ID_from_IP(unsigned long int IP_addr) {
+	unsigned char i, i_found;
+	unsigned long int last_IP;
+	i_found = 250;
+	
+	for (i=0; i<radio_addr_table_size; i++) {
+		last_IP = CONF_radio_addr_table_IP_begin[i] + CONF_radio_addr_table_IP_size[i];
+		if ( (IP_addr >= CONF_radio_addr_table_IP_begin[i]) && (IP_addr < last_IP) ) {
+			i_found = i;
+		}
+	}
+	return i_found;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/Eth_IPv4.h b/NPR_FW_source_2020_06_29/NPR_14/source/Eth_IPv4.h
new file mode 100755
index 0000000..c9c1bb9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/Eth_IPv4.h
@@ -0,0 +1,43 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef Eth_IPv4_F4
+#define Eth_IPv4_F4
+
+#include "mbed.h"
+#include "W5500.h"
+
+unsigned long int IP_char2int(unsigned char* IP_char);
+
+void IP_int2char (unsigned long int IP_int, unsigned char* IP_char);
+
+//void init_RTP_filter(void);
+
+//int PS_read_from_ethernet(W5500_chip* W5500);
+int Eth_RX_dequeue (W5500_chip* W5500);
+
+void Eth_pause_frame_TX(unsigned int time);
+
+void IPv4_to_radio (unsigned char* RX_Eth_frame, int size);
+
+void IPv4_from_radio (unsigned char* RX_eth_frame, int RX_size);
+
+void flush_temp_Eth_buffer(unsigned long int loc_IP);
+
+unsigned char lookfor_client_ID_from_IP(unsigned long int IP_addr);
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/HMI_telnet.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/HMI_telnet.cpp
new file mode 100755
index 0000000..236075d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/HMI_telnet.cpp
@@ -0,0 +1,945 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "HMI_telnet.h"
+#include "mbed.h"
+#include "global_variables.h"
+#include "Eth_IPv4.h"
+#include "signaling.h"
+#include "config_flash.h"
+#include "W5500.h"
+#include "SI4463.h"
+#include "TDMA.h"
+#include "DHCP_ARP.h"
+#include "L1L2_radio.h"
+
+static char current_rx_line[100];
+//static char HMI_out_str[100];
+static int current_rx_line_count = 0;
+static int is_telnet_opened = 0;
+static int echo_ON = 1; 
+static int display_status_ongoing = 0;
+static int display_who_ongoing = 0;
+static int slow_counter = 0;
+
+static unsigned int telnet_last_activity;
+
+int telnet_loop (W5500_chip* W5500) {
+	static unsigned char previous_state = 0;
+	unsigned char RX_data[100];
+	unsigned char TX_data[100];
+	unsigned char current_state;
+	unsigned int timer_snapshot;
+	char loc_char;
+	int RX_size = 0;
+	int i, j;
+	int result;
+
+	result=0;
+	
+	current_state = W5500_read_byte(W5500, 0x0003, 0x05);
+	//printf("state: %x\r\n", current_state);
+	if ((current_state == 0x17) && (previous_state != 0x17)) {
+		W5500_read_long(W5500, 0x000C, 0x05, RX_data, 4);
+		printf("\r\n\r\nnew telnet connexion from %i.%i.%i.%i\r\nserial inactive...\r\n", RX_data[0], RX_data[1], RX_data[2], RX_data[3]);
+		fflush(stdout);
+		//TX_data[0] = 0xFF; //IAC
+		//TX_data[1] = 0xFB; //WILL FB DO FD
+		//TX_data[2] = 1; //echo 1 RTCE 7
+		//TX_data[3] = 0;
+		TX_data[0] = 0xFF; //IAC
+		TX_data[1] = 0xFB; //WILL 
+		TX_data[2] = 0x01; //Echo
+		//TX_data[3] = 0;
+		TX_data[3] = 0xFF; //IAC
+		TX_data[4] = 0xFD; //DO
+		TX_data[5] = 0x03; //Suppr GA 
+		TX_data[6] = 0xFF; //IAC
+		TX_data[7] = 0xFB; //WILL
+		TX_data[8] = 0x03; //Suppr GA 
+		TX_data[9] = 0;
+		strcat((char*)TX_data, "NPR modem\r\nready> ");
+		W5500_write_TX_buffer (W5500, 1, TX_data, 27, 0); //27
+		//HMI_printf("ready>");
+		is_telnet_opened = 1;
+		current_rx_line_count = 0;
+		echo_ON = 1;
+		display_status_ongoing = 0;
+		display_who_ongoing = 0;
+		telnet_last_activity = GLOBAL_timer.read_us();
+	}
+	
+	if (current_state==0x1C) { // close wait to close 
+		W5500_write_byte(W5500, 0x0001, 0x05, 0x10); 
+		printf("telnet connexion closed\r\nready> "); 
+		fflush(stdout);
+		is_telnet_opened = 0;
+		current_rx_line_count = 0;
+		echo_ON = 1;
+		display_status_ongoing = 0;
+		display_who_ongoing = 0;
+	}
+	
+	if (current_state==0x00) { //closed to open
+		W5500_write_byte(W5500, 0x0001, 0x05, 0x01); 
+		//printf("open \r\n");
+		result=1;
+	}
+	
+	if (current_state==0x13) { //opened to listen
+		W5500_write_byte(W5500, 0x0001, 0x05, 0x02); 
+		//printf("listen \r\n");
+	}
+	previous_state = current_state;
+	if (is_telnet_opened) {
+		RX_size = W5500_read_received_size(W5500, 1); 
+		timer_snapshot = GLOBAL_timer.read_us();
+		if ((timer_snapshot - telnet_last_activity) > 300000000) { //300000000
+			//HMI_printf("Telnet inactivity timeout. Force exit.\r\n");
+			W5500_write_byte(W5500_p1, 0x0001, 0x05, 0x08); //close TCP
+			is_telnet_opened = 0;
+			echo_ON = 1;
+			display_status_ongoing = 0;
+			display_who_ongoing = 0;
+			printf("telnet connexion closed\r\nready> "); 
+			fflush(stdout);
+		}
+		//timeout 
+	}
+	if (RX_size > 0) {
+		telnet_last_activity = GLOBAL_timer.read_us();
+		result=1;
+		W5500_read_RX_buffer(W5500, 1, RX_data, RX_size);
+		RX_data[RX_size] = 0;
+		i = 0;
+		j = 0;
+		while (i < RX_size) {
+			loc_char = (char)RX_data[i];
+			//printf("%02X %c\r\n", loc_char, loc_char);
+			if ( (loc_char >= 0x20) && (loc_char <= 0x7E) ) {//displayable char
+				if ( (current_rx_line_count < 98) && (echo_ON) ) {
+					TX_data[j]=RX_data[i];
+					i++;
+					j++;
+					current_rx_line[current_rx_line_count] = loc_char;
+					current_rx_line_count++;
+				} else {
+					i++;
+				}
+			} 
+			else { // special char
+				if (loc_char == 0xFF) {//IAC
+					if (RX_data[i+1] == 244) {//ctrl+C
+						HMI_cancel_current();
+					}
+					i = i + 3;
+				}
+				else if ( ( (loc_char == 0x08) || (loc_char == 0x7F) ) && (echo_ON) ) { //backspace
+					i++;
+					
+					if (current_rx_line_count>0) {
+						current_rx_line_count--;
+						TX_data[j] = 0x08;
+						TX_data[j+1] = 0x20;
+						TX_data[j+2] = 0x08;
+						j=j+3;
+					}
+				}
+				else if ( (loc_char == 0x0D) && (echo_ON) ){ //end of line
+					TX_data[j] = 0x0D;
+					TX_data[j+1] = 0x0A;
+					i++;
+					j = j + 2;
+					current_rx_line[current_rx_line_count] = 0;//null termination
+					current_rx_line_count++;
+					W5500_write_TX_buffer (W5500, 1, TX_data, j, 0);
+					j = 0;
+					HMI_line_parse (current_rx_line, current_rx_line_count);
+					current_rx_line_count = 0;
+				}
+				else if (loc_char == 0x03) { //ctrl + C
+					HMI_cancel_current();
+					//printf("CTRL + C\r\n");
+					i++;
+				} else {
+					i++;
+				}
+			}
+		}
+		if (j > 0) {
+			W5500_write_TX_buffer (W5500, 1, TX_data, j, 0);
+		}
+		//printf("\r\n");
+	}
+	return result;
+}
+
+int serial_term_loop (void) {
+	char loc_char;
+	
+	if (pc.readable()) {
+		loc_char = getc(pc);
+		
+		if (is_telnet_opened == 0) {
+			if ( (loc_char >= 0x20) && (loc_char <= 0x7E) ) {//printable char
+				if ( (current_rx_line_count < 98) && (echo_ON) ) {
+					putc(loc_char, pc);
+					current_rx_line[current_rx_line_count] = loc_char;
+					current_rx_line_count++;
+				}
+			}
+			else {
+				if ( ( (loc_char == 0x08) || (loc_char == 0x7F) ) && (echo_ON) ) {//backspace
+					if (current_rx_line_count>0) {
+						current_rx_line_count--;
+						putc(0x08,pc);
+						putc(0x20,pc);
+						putc(0x08,pc);
+					}
+				}
+				else if ( (loc_char == 0x0D) && (echo_ON) ) {
+					printf("\r\n");
+					current_rx_line[current_rx_line_count] = 0;
+					current_rx_line_count++;
+					HMI_line_parse (current_rx_line, current_rx_line_count);
+					current_rx_line_count = 0;
+				}
+				else if (loc_char == 0x03) {//ctrl + c
+					HMI_cancel_current();
+				}
+			}
+		}
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+void HMI_line_parse (char* RX_text, int RX_text_count) {
+	char* loc_command_str;// [100];
+	char* loc_param1_str;
+	char* loc_param2_str;
+	int command_understood = 0;
+	int temp;
+
+	loc_command_str = strtok (RX_text, " ");
+	loc_param1_str = strtok (NULL, " ");
+	loc_param2_str = strtok (NULL, " ");
+
+	if (loc_command_str) {
+		if (strcmp(loc_command_str, "radio") == 0) {
+			command_understood = 1;
+			if (strcmp(loc_param1_str, "on") == 0) {
+				if (CONF_radio_state_ON_OFF == 0) {
+					RADIO_on(1, 1, 1);
+				}
+				HMI_printf("OK\r\nready> ");
+			}
+			else if (strcmp(loc_param1_str, "off") == 0) {
+				RADIO_off(1);
+				HMI_printf("OK\r\nready> ");
+			}
+			else {
+				HMI_printf("unknown radio command\r\nready> ");
+			}
+		}
+		
+		if (strcmp(loc_command_str, "TX_test") == 0) {
+			command_understood = 1;
+			HMI_TX_test(loc_param1_str);
+		}
+		if ((strcmp(loc_command_str, "status") == 0) || (strcmp(loc_command_str, "s") == 0)) {//display status
+			command_understood = 1;
+			display_status_ongoing = 1;
+			G_downlink_bandwidth_temp = 0;
+			G_uplink_bandwidth_temp = 0;
+			slow_counter = 0;
+			echo_ON = 0;
+			HMI_periodic_call();
+		}
+		if (strcmp(loc_command_str, "display") == 0) {
+			command_understood = 1;
+			if (strcmp(loc_param1_str, "config") == 0) {//display config
+				HMI_display_config();
+			}
+			else if (strcmp(loc_param1_str, "static") == 0) {//display static alloc
+				HMI_display_static();
+			}
+			else if (strcmp(loc_param1_str, "DHCP_ARP") == 0) {//display DHCP_ARP entries
+				DHCP_ARP_print_entries();
+			}
+			else {
+				HMI_printf("unknown display command\r\nready> ");
+			}
+		}
+		if (strcmp(loc_command_str, "set") == 0) {
+			HMI_set_command(loc_param1_str, loc_param2_str);
+			command_understood = 1;
+		}
+		if ((strcmp(loc_command_str, "who") == 0) || (strcmp(loc_command_str, "w") == 0)) {
+			//HMI_print_who();
+			command_understood = 1;
+			display_who_ongoing = 1;
+			slow_counter = 0;
+			echo_ON = 0;
+			HMI_periodic_call();
+		}
+		if (strcmp(loc_command_str, "reboot") == 0) {
+			command_understood = 1;
+			HMI_reboot();
+		}
+		if (strcmp(loc_command_str, "save") == 0) {
+			command_understood = 1;
+
+			RADIO_off_if_necessary(0);
+			temp = NFPR_config_save();
+			RADIO_restart_if_necessary(0, 0, 1);
+			HMI_printf("saved index:%i\r\nready> ", temp);
+		}
+		if (strcmp(loc_command_str, "reset_to_default") == 0) {
+			command_understood = 1;
+			HMI_printf("clearing saved config...\r\n");
+			RADIO_off_if_necessary(0);
+			virt_EEPROM_errase_all();
+			HMI_printf("Done. Now rebooting...\r\n");
+			NVIC_SystemReset();
+		}
+		if (strcmp(loc_command_str, "version") == 0) {
+			command_understood = 1;
+			HMI_printf("firmware: %s\r\nfreq band: %s\r\nready> ", FW_VERSION, FREQ_BAND);
+		}
+		if (strcmp(loc_command_str, "exit") == 0) {
+			command_understood = 1;
+			HMI_exit();
+		}
+		if (command_understood == 0) {
+			HMI_printf("unknown command\r\nready> ");
+		}
+				//Add Help
+		if (strcmp(loc_command_str, "help") == 0) {
+			command_understood = 1;
+			HMI_printf("HELP cmd: help, status (s), display config, display static, display DHCP_ARP,\
+			\r\nset [params], radio, TX_test, who (w), save, reboot, version, reset_to_default, exit\
+			\r\nready> ");
+		}
+	} else {//just a return with nothing
+		HMI_printf("ready> ");
+	}
+}
+
+void HMI_cancel_current(void) {
+	if (echo_ON ==0) {
+		echo_ON = 1;
+		display_status_ongoing = 0;
+		display_who_ongoing = 0;
+		HMI_printf("ready> ");
+	}
+}
+
+int HMI_check_radio_OFF(void) {
+	if (CONF_radio_state_ON_OFF == 1) {
+		HMI_printf("radio must be off for this command\r\nready> ");
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+
+void HMI_TX_test(char* duration_txt) {
+	unsigned int duration;
+	if ( HMI_check_radio_OFF() == 1) {
+		sscanf (duration_txt, "%i", &duration);
+		HMI_printf("reconfiguring radio...\r\n");
+		SI4463_configure_all();
+		wait_ms(50);
+		TDMA_init_all();
+		//SI4463_radio_start();
+		
+		wait_ms(1);
+		G_SI4463->RX_TX_state = 0;
+		SI4463_clear_IT(G_SI4463, 0, 0);
+		wait_ms(10);
+		CONF_radio_state_ON_OFF = 1;
+		SI4463_TX_to_RX_transition();
+		
+		wait_ms(10);
+		CONF_radio_state_ON_OFF = 0;
+		if (is_TDMA_master == 0 ) {
+			my_client_radio_connexion_state = 1;
+			my_radio_client_ID = 0x7E;
+		}
+		wait_ms(50);
+		
+		TDMA_NULL_frame_init(70);
+		HMI_printf("radio transmit test %i seconds...\r\n", duration);
+		duration = duration * 1000; //milliseconds instead of seconds
+		
+		SI4432_TX_test(duration);
+		
+		HMI_printf("ready> ");
+	}
+}
+
+void HMI_reboot(void) {
+	if (is_telnet_opened == 1) {
+		W5500_write_byte(W5500_p1, 0x0001, 0x05, 0x08);
+	}
+	//extern "C" void mbed_reset();
+	NVIC_SystemReset();
+}
+
+void HMI_force_exit(void) {
+	unsigned char IP_loc[8];
+	if (is_telnet_opened == 1) {
+		IP_int2char (LAN_conf_applied.LAN_modem_IP, IP_loc);
+		//HMI_printf("\r\n\r\n\r\nNew IP config... force telnet exit.\r\n");
+		//HMI_printf("\r\n\r\nNew IP config. Open new telnet session with: %i.%i.%i.%i\r\n\r\n", IP_loc[0], IP_loc[1], IP_loc[2], IP_loc[3]);
+		W5500_write_byte(W5500_p1, 0x0001, 0x05, 0x08); //close TCP
+		is_telnet_opened = 0;
+		echo_ON = 1;
+		display_status_ongoing = 0;
+		printf("telnet connexion closed\r\nready> "); 
+		fflush(stdout);
+	}
+}
+
+void HMI_exit(void) {
+	if (is_telnet_opened == 1) {
+		W5500_write_byte(W5500_p1, 0x0001, 0x05, 0x08); //close TCP
+		is_telnet_opened = 0;
+		echo_ON = 1;
+		display_status_ongoing = 0;
+		printf("telnet connexion closed\r\nready> "); 
+		fflush(stdout);
+	} else {
+		printf("exit only valid for telnet\r\nready> ");
+		fflush(stdout);
+	}
+}
+
+static char HMI_yes_no[2][4]={'n','o',0,0, 'y','e','s',0};
+//static char HMI_trans_modes[2][4]={'I','P',0,0,'E','t','h',0};
+static char HMI_master_FDD[3][5]={'n','o',0,0,0,'d','o','w','n',0,'u','p',0,0,0};
+
+void HMI_display_config(void) {
+	unsigned char IP_loc[8];
+
+	HMI_printf("CONFIG:\r\n  callsign: '%s'\r\n  is_master: %s\r\n  MAC: %02X:%02X:%02X:%02X:%02X:%02X\r\n", CONF_radio_my_callsign+2, HMI_yes_no[is_TDMA_master],CONF_modem_MAC[0],CONF_modem_MAC[1],CONF_modem_MAC[2],CONF_modem_MAC[3],CONF_modem_MAC[4],CONF_modem_MAC[5]);
+	HMI_printf("  Eth_mode: %i\r\n", CONF_Eth_mode);
+	HMI_printf("  ext_SRAM: %s\r\n", HMI_yes_no[is_SRAM_ext]);
+	HMI_printf("  frequency: %.3fMHz\r\n  freq_shift: %.3fMHz\r\n  RF_power: %i\r\n  modulation: %i\r\n", ((float)CONF_frequency_HD/1000)+FREQ_RANGE_MIN, (float)CONF_freq_shift/1000, CONF_radio_PA_PWR, CONF_radio_modulation); 
+
+	HMI_printf("  radio_netw_ID: %i\r\n  radio_on_at_start: %s\r\n", CONF_radio_network_ID, HMI_yes_no[CONF_radio_default_state_ON_OFF]);
+	HMI_printf("  telnet active: %s\r\n  telnet routed: %s\r\n", HMI_yes_no[is_telnet_active], HMI_yes_no[is_telnet_routed]);
+	IP_int2char (LAN_conf_saved.LAN_modem_IP, IP_loc);
+	IP_int2char (LAN_conf_saved.LAN_subnet_mask, IP_loc+4);
+	HMI_printf("  modem_IP: %i.%i.%i.%i\r\n  netmask: %i.%i.%i.%i\r\n", IP_loc[0], IP_loc[1],IP_loc[2],IP_loc[3],IP_loc[4],IP_loc[5],IP_loc[6],IP_loc[7]);
+	
+	if (is_TDMA_master == 1) {
+		HMI_printf("  master_FDD: %s\r\n", HMI_master_FDD[CONF_master_FDD]);
+	}
+	
+	
+	if ( (is_TDMA_master == 1) && ( CONF_master_FDD < 2 ) && (CONF_transmission_method==0) ) {//Master FDD down (or no FDD)	
+		IP_int2char (CONF_radio_IP_start, IP_loc);
+		IP_int2char (CONF_radio_IP_start+CONF_radio_IP_size-1, IP_loc+4);
+		HMI_printf("  IP_begin: %i.%i.%i.%i\r\n  master_IP_size: %ld (Last IP: %i.%i.%i.%i)\r\n", IP_loc[0], IP_loc[1],IP_loc[2],IP_loc[3],CONF_radio_IP_size, IP_loc[4],IP_loc[5],IP_loc[6],IP_loc[7]);
+		IP_int2char (LAN_conf_saved.LAN_def_route, IP_loc);	
+		HMI_printf("  def_route_active: %s\r\n  def_route_val: %i.%i.%i.%i\r\n", HMI_yes_no[LAN_conf_saved.LAN_def_route_activ], IP_loc[0],IP_loc[1],IP_loc[2],IP_loc[3]);
+		IP_int2char (LAN_conf_saved.LAN_DNS_value, IP_loc);
+		HMI_printf("  DNS_active: %s\r\n  DNS_value: %i.%i.%i.%i\r\n", HMI_yes_no[LAN_conf_saved.LAN_DNS_activ], IP_loc[0],IP_loc[1],IP_loc[2],IP_loc[3]);
+	}
+	if ( (is_TDMA_master == 1) && (CONF_master_FDD == 2) ) {//Master FDD up
+		IP_int2char (CONF_master_down_IP, IP_loc);
+		HMI_printf("  master_down_IP: %i.%i.%i.%i\r\n",IP_loc[0],IP_loc[1],IP_loc[2],IP_loc[3]);
+	}
+	if (is_TDMA_master == 0) {//client
+		IP_int2char (CONF_radio_IP_start, IP_loc);
+		HMI_printf("  IP_begin: %i.%i.%i.%i\r\n", IP_loc[0], IP_loc[1],IP_loc[2],IP_loc[3]);
+		HMI_printf("  client_req_size: %ld\r\n  DHCP_active: %s\r\n", CONF_radio_IP_size_requested, HMI_yes_no[LAN_conf_saved.DHCP_server_active]);
+	}
+	HMI_printf("ready> ");
+}
+
+void HMI_display_static(void) {
+	
+}
+
+void HMI_set_command(char* loc_param1, char* loc_param2) {
+	int temp;
+	unsigned char temp_uchar;
+	unsigned long int temp_uint;
+	float frequency;
+	//unsigned char previous_freq_band;
+	char DHCP_warning[50];
+	if ((loc_param1) && (loc_param2)) {
+		if (strcmp(loc_param1, "callsign") == 0) {
+			RADIO_off_if_necessary(1);
+			strcpy (CONF_radio_my_callsign+2, loc_param2);
+			CONF_radio_my_callsign[0] = CONF_modem_MAC[4];
+			CONF_radio_my_callsign[1] = CONF_modem_MAC[5];
+			CONF_radio_my_callsign[15] = 0;
+			RADIO_restart_if_necessary(1, 0, 1);
+			HMI_printf("new callsign '%s'\r\nready> ", CONF_radio_my_callsign+2);
+		} 
+		else if (strcmp(loc_param1, "is_master") == 0) {
+			temp_uchar = HMI_yes_no_2int(loc_param2);
+			if ( (temp_uchar==0) || (temp_uchar==1) ) {
+				RADIO_off_if_necessary(1);
+				is_TDMA_master = temp_uchar;
+				RADIO_restart_if_necessary(1, 0, 1);
+				if ( (is_TDMA_master) && (LAN_conf_saved.DHCP_server_active == 1) ) {
+					strcpy (DHCP_warning, " (warning, DHCP inhibited in master mode)"); 
+				} else {
+					strcpy (DHCP_warning, ""); 
+				}
+				HMI_printf("Master '%s'%s\r\nready> ", loc_param2, DHCP_warning);
+			}
+		}
+		else if (strcmp(loc_param1, "telnet_active") == 0) {
+			temp_uchar = HMI_yes_no_2int(loc_param2);
+			if ( (temp_uchar==0) || (temp_uchar==1) ) {
+				if(is_telnet_opened) { HMI_exit(); }
+				is_telnet_active = temp_uchar;
+				HMI_printf("telnet active '%s'\r\nready> ", loc_param2);
+			}
+		}
+		else if (strcmp(loc_param1, "telnet_routed") == 0) {
+			temp_uchar = HMI_yes_no_2int(loc_param2);
+			if ( (temp_uchar==0) || (temp_uchar==1) ) {
+				is_telnet_routed = temp_uchar;
+				//W5500_re_configure_gateway(W5500_p1);
+				HMI_printf("telnet routed '%s'\r\nready> ", loc_param2);
+			}
+		}
+		else if (strcmp(loc_param1, "DNS_active") == 0) {
+			temp_uchar = HMI_yes_no_2int(loc_param2);
+			if ( (temp_uchar==0) || (temp_uchar==1) ) {
+				RADIO_off_if_necessary(1);
+				LAN_conf_saved.LAN_DNS_activ = temp_uchar;
+				RADIO_restart_if_necessary(1, 0, 1);
+				HMI_printf("DNS active '%s'\r\nready> ", loc_param2);
+			}
+		}
+		else if (strcmp(loc_param1, "def_route_active") == 0) {
+			temp_uchar = HMI_yes_no_2int(loc_param2);
+			if ( (temp_uchar==0) || (temp_uchar==1) ) {
+				RADIO_off_if_necessary(1);
+				LAN_conf_saved.LAN_def_route_activ = temp_uchar;
+				//W5500_re_configure_gateway(W5500_p1);
+				RADIO_restart_if_necessary(1, 0, 1);
+				HMI_printf("default route active '%s'\r\nready> ", loc_param2);
+			}
+		}
+		else if (strcmp(loc_param1, "master_FDD") == 0) {
+			if(strcmp(loc_param2,"no") == 0) {
+				CONF_master_FDD = 0;
+				RADIO_off_if_necessary(1);
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+			else if(strcmp(loc_param2,"down") == 0) {
+				CONF_master_FDD = 1;
+				RADIO_off_if_necessary(1);
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+			else if(strcmp(loc_param2,"up") == 0) {
+				CONF_master_FDD = 2;
+				RADIO_off_if_necessary(1);
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+			else {
+				HMI_printf("  wrong value\r\n");
+			}
+			HMI_printf("ready> ");
+		}
+		//else if (strcmp(loc_param1, "trans_method") == 0) {
+		//	if(strcmp(loc_param2,"IP") == 0) {
+		//		CONF_transmission_method = 0;
+		//		RADIO_off_if_necessary(1);
+		//		RADIO_restart_if_necessary(1, 0, 1);
+		//	}
+		//	else if(strcmp(loc_param2,"Eth") == 0) {
+		//		CONF_transmission_method = 1;
+		//		RADIO_off_if_necessary(1);
+		//		RADIO_restart_if_necessary(1, 0, 1);
+		//	}
+		//	else {
+		//		HMI_printf("  wrong value\r\n");
+		//	}
+		//	HMI_printf("ready> ");
+		//}
+		//else if (strcmp(loc_param1, "client_static_IP") == 0) {
+		//	temp_uchar = HMI_yes_no_2int(loc_param2);
+		//	if ( (temp_uchar==0) || (temp_uchar==1) ) {
+		//		RADIO_off_if_necessary(1);
+		//		CONF_radio_static_IP_requested = temp_uchar;
+		//		HMI_printf("client static IP '%s'\r\nready> ", loc_param2);
+		//		RADIO_restart_if_necessary(1, 0, 1);
+		//	}
+		//}
+		else if (strcmp(loc_param1, "radio_on_at_start") == 0) {
+			temp_uchar = HMI_yes_no_2int(loc_param2);
+			if ( (temp_uchar==0) || (temp_uchar==1) ) {
+				CONF_radio_default_state_ON_OFF = temp_uchar;
+				HMI_printf("radio_on_at_start '%s'\r\nready> ", loc_param2);
+			}
+		}
+		else if (strcmp(loc_param1, "DHCP_active") == 0) {
+			temp_uchar = HMI_yes_no_2int(loc_param2);
+			if ( (temp_uchar==0) || (temp_uchar==1) ) {
+				LAN_conf_saved.DHCP_server_active = temp_uchar;
+				if ( (is_TDMA_master) && (LAN_conf_saved.DHCP_server_active == 1) ) {
+					strcpy (DHCP_warning, " (warning, DHCP inhibited in master mode)"); 
+				} else {
+					strcpy (DHCP_warning, ""); 
+				}
+				HMI_printf("DHCP_active: '%s'%s\r\nready> ", loc_param2, DHCP_warning);
+			}
+		}
+		else if (strcmp(loc_param1, "modem_IP") == 0) {
+			temp_uint = HMI_str2IP(loc_param2);
+			if (temp_uint !=0) {
+				RADIO_off_if_necessary(1);
+				LAN_conf_saved.LAN_modem_IP = temp_uint;
+				//HMI_force_exit();
+				//W5500_re_configure();
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+		}
+		else if (strcmp(loc_param1, "netmask") == 0) {
+			temp_uint = HMI_str2IP(loc_param2);
+			if (temp_uint !=0) {
+				RADIO_off_if_necessary(1);
+				LAN_conf_saved.LAN_subnet_mask = temp_uint;
+				//HMI_force_exit();
+				//W5500_re_configure();
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+		}
+		else if (strcmp(loc_param1, "def_route_val") == 0) {
+			temp_uint = HMI_str2IP(loc_param2);
+			if (temp_uint !=0) {
+				RADIO_off_if_necessary(1);
+				LAN_conf_saved.LAN_def_route = temp_uint;
+				//W5500_re_configure_gateway(W5500_p1);
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+		}
+		else if (strcmp(loc_param1, "DNS_value") == 0) {
+			temp_uint = HMI_str2IP(loc_param2);
+			if (temp_uint !=0) {
+				RADIO_off_if_necessary(1);
+				LAN_conf_saved.LAN_DNS_value = temp_uint;
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+		}
+		else if (strcmp(loc_param1, "IP_begin") == 0) {
+			temp_uint = HMI_str2IP(loc_param2);
+			if (temp_uint !=0) {
+				RADIO_off_if_necessary(1);
+				CONF_radio_IP_start = temp_uint;
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+		}
+		else if (strcmp(loc_param1, "master_down_IP") == 0) {
+			temp_uint = HMI_str2IP(loc_param2);
+			if (temp_uint !=0) {
+				RADIO_off_if_necessary(1);
+				CONF_master_down_IP = temp_uint;
+				RADIO_restart_if_necessary(1, 0, 1);
+			}
+		}
+		else if (strcmp(loc_param1, "master_IP_size") == 0) {
+			temp = sscanf (loc_param2, "%ld", &temp_uint);
+			if ( (temp==1) && (temp_uint!=0) ) {
+				RADIO_off_if_necessary(1);
+				CONF_radio_IP_size = temp_uint;
+				RADIO_restart_if_necessary(1, 0, 1);
+				HMI_printf("OK\r\nready> ");
+			}
+			else {
+				HMI_printf("wrong value\r\nready> ");
+			}
+		}
+		else if (strcmp(loc_param1, "client_req_size") == 0) {
+			temp = sscanf (loc_param2, "%ld", &temp_uint);
+			if ( (temp==1) && (temp_uint!=0) ) {
+				RADIO_off_if_necessary(1);
+				CONF_radio_IP_size_requested = temp_uint;
+				RADIO_restart_if_necessary(1, 0, 1);
+				HMI_printf("OK\r\nready> ");
+			}
+			else {
+				HMI_printf("wrong value\r\nready> ");
+			}
+		}
+
+		else if (strcmp(loc_param1, "frequency") == 0) {
+			temp = sscanf (loc_param2, "%f", &frequency);
+			if ( (temp == 1) && (frequency<=FREQ_RANGE_MAX) && (frequency>FREQ_RANGE_MIN) ) {
+				RADIO_off_if_necessary(0);
+				frequency = (frequency - FREQ_RANGE_MIN)*1000 + 0.3; 
+				CONF_frequency_HD = (short int)frequency;
+				//RADIO_compute_freq_params();//REMOVE TEST
+				RADIO_restart_if_necessary(0, 1, 1);
+				HMI_printf("OK\r\nready> ");
+			} else {
+				HMI_printf("wrong freq value\r\nready> ");
+			}
+		}
+		else if (strcmp(loc_param1, "freq_shift") == 0) {
+			temp = sscanf (loc_param2, "%f", &frequency);
+			if ( (temp == 1) && (frequency<=10) && (frequency>=-10) ) {
+				RADIO_off_if_necessary(0);
+				frequency = (frequency*1000);
+				CONF_freq_shift = (short int)frequency;
+				//RADIO_compute_freq_params();//REMOVE TEST
+				//if (CONF_frequency_band == previous_freq_band) {
+				//	RADIO_restart_if_necessary(0, 0, 1);
+				//}else {
+				RADIO_restart_if_necessary(0, 1, 1);
+				//}
+				HMI_printf("OK\r\nready> ");
+			} else {
+				HMI_printf("wrong freq value\r\nready> ");
+			}
+		}
+		else if (strcmp(loc_param1, "RF_power") == 0) {
+			temp_uint = sscanf (loc_param2, "%i", &temp); 
+			if ( (temp_uint == 1) && (temp<128) ) {
+				RADIO_off_if_necessary(0);
+				CONF_radio_PA_PWR = temp;
+				SI4463_set_power(G_SI4463);
+				RADIO_restart_if_necessary(0, 0, 1);
+				HMI_printf("OK\r\nready> ");
+			} else {
+				HMI_printf("error : max RF_power value 127\r\nready> ");
+			}
+		}
+		else if (strcmp(loc_param1, "Eth_mode") == 0) {
+			temp_uint = sscanf (loc_param2, "%i", &temp); 
+			if ( (temp_uint == 1) && (temp <= 7) ) {
+				CONF_Eth_mode = temp;
+				HMI_printf("OK\r\nready> ");
+			} else {
+				HMI_printf("error : max Eth_mode value 7\r\nready> ");
+			}
+		}
+		else if (strcmp(loc_param1, "modulation") == 0) {
+			temp_uint = sscanf (loc_param2, "%i", &temp);
+			temp_uchar = temp;
+			//if ( (temp_uint == 1) && ((temp_uchar==13)||(temp_uchar==14)||(temp_uchar==22)||(temp_uchar==23)||(temp_uchar==24)) ) {
+			if ( (temp_uint == 1) && ( ((temp_uchar>=11)&&(temp_uchar<=14)) || ((temp_uchar>=20)&&(temp_uchar<=24)) ) ) {
+				RADIO_off_if_necessary(1);
+				CONF_radio_modulation = temp_uchar;
+				RADIO_restart_if_necessary(1, 1, 1);
+				HMI_printf("OK\r\nready> ");
+			} else {
+				HMI_printf("wrong modulation value\r\nready> ");
+			}
+		}
+		else if (strcmp(loc_param1, "radio_netw_ID") == 0) {
+			temp_uint = sscanf (loc_param2, "%i", &temp);
+			temp_uchar = temp;
+			if ( (temp_uint == 1) && (temp_uchar <= 15) ) {
+				RADIO_off_if_necessary(1);
+				CONF_radio_network_ID = temp_uchar;
+				RADIO_restart_if_necessary(1, 1, 1);
+				HMI_printf("OK\r\nready> ");
+			} else {
+				HMI_printf("wrong value, 15 max\r\nready> ");
+			}
+		}
+		else {
+			HMI_printf("unknown config param\r\nready> ");
+		}
+	} else {
+		HMI_printf("set command requires 2 param\r\nready> ");
+	}
+}
+
+unsigned long int HMI_str2IP(char* raw_string) {
+	unsigned int IP_char_t[6];
+	unsigned char IP_char[6]; 
+	unsigned long int answer;
+	int i;
+	answer = sscanf(raw_string, "%i.%i.%i.%i", IP_char_t, IP_char_t+1, IP_char_t+2, IP_char_t+3);
+	for (i=0;i<4; i++) {
+		IP_char[i] = IP_char_t[i];
+	}
+	if (answer == 4) {
+		answer = IP_char2int(IP_char);
+		HMI_printf("OK\r\nready> ");
+	} else {
+		HMI_printf("bad IP format\r\nready> ");
+		answer = 0;
+	}
+	return answer;
+}
+
+unsigned char HMI_yes_no_2int(char* raw_string) {
+	unsigned char answer;
+	if (strcmp (raw_string, "yes") == 0) {
+		answer = 1;
+	} 
+	else if (strcmp (raw_string, "no") == 0) {
+		answer = 0;
+	}
+	else {
+		HMI_printf("value must be 'yes' or 'no'\r\nready> ");
+		answer = -1;
+	}
+	return answer;
+}
+
+void HMI_print_who(void) {
+	int i;
+	unsigned int loc_age;
+	unsigned int timer_snapshot;
+	unsigned long int last_IP;
+	unsigned char IP_c[6];
+	char temp_string[50] = {0x1B,0x5B,0x41,0x1B,0x5B,0x41,0x1B,0x5B,0x41,0x1B, 0x5B, 0x41,0x1B, 0x5B, 0x41,0x1B, 0x5B, 0x41,0x1B, 0x5B, 0x41,0x1B, 0x5B, 0x41,0x1B, 0x5B, 0x41,0x1B, 0x5B, 0x41,0x1B, 0x5B, 0x41,0x00};
+
+	if (slow_counter == 0) { temp_string[0] = 0; }
+	HMI_printf ("%s%i Master: ID:127 Callsign:%s\r\n", temp_string, slow_counter, CONF_radio_master_callsign+2);
+	IP_int2char (LAN_conf_applied.LAN_modem_IP, IP_c);
+	HMI_printf ("ME: Callsign:%s ID:%i modem IP:%i.%i.%i.%i\r\n", CONF_radio_my_callsign+2, my_radio_client_ID, IP_c[0], IP_c[1], IP_c[2], IP_c[3]);
+	HMI_printf ("Clients:\r\n");
+	timer_snapshot = GLOBAL_timer.read_us();
+	for (i=0; i<radio_addr_table_size; i++) {
+		
+	}
+	for (i=0; i<radio_addr_table_size; i++) {
+		loc_age = timer_snapshot - CONF_radio_addr_table_date[i];
+		loc_age = loc_age / 1000000;
+		if (is_TDMA_master) {loc_age = 0;} // master : already timeout in state machine
+		//printf ("age:%i ", loc_age);
+		if ( (CONF_radio_addr_table_status[i]) && (loc_age < connexion_timeout) ) {
+			HMI_printf (" ID:%i Callsign:%s ", i, CONF_radio_addr_table_callsign[i]+2);
+			IP_int2char (CONF_radio_addr_table_IP_begin[i], IP_c);
+			HMI_printf ("IP start:%i.%i.%i.%i ", IP_c[0], IP_c[1], IP_c[2], IP_c[3]);
+			last_IP = CONF_radio_addr_table_IP_begin[i] + CONF_radio_addr_table_IP_size[i] - 1;
+			IP_int2char (last_IP, IP_c);
+			HMI_printf ("IP end:%i.%i.%i.%i\r\n", IP_c[0], IP_c[1], IP_c[2], IP_c[3]);
+		} else {
+			HMI_printf ("                                                            \r\n");
+		}
+		
+	}
+	HMI_printf("CTRL+c to exit...\r\n");
+}
+
+void HMI_print_status(void) {
+	static char text_radio_status[3][22] = {
+		"waiting connection",
+		"connected",
+		"connection rejected"
+	};
+	static char text_reject_reason[2][15] = {
+		"IP requested",
+		"clients",
+	};
+	char temp_string[22];
+	float loc_downlink_bw;
+	float loc_uplink_bw;
+	int TA_loc; 
+	temp_string[0]=0x1B;
+	temp_string[1]=0x5B;
+	temp_string[2]=0x41;
+	temp_string[3]=0x1B;
+	temp_string[4]=0x5B;
+	temp_string[5]=0x41;
+	temp_string[6]=0x1B;
+	temp_string[7]=0x5B;
+	temp_string[8]=0x41;
+	temp_string[9]=0x1B;
+	temp_string[10]=0x5B;
+	temp_string[11]=0x41;
+	temp_string[12]=0x1B;
+	temp_string[13]=0x5B;
+	temp_string[14]=0x41;
+	temp_string[15]=0x00;
+	//temp_string[15]=0x1B;
+	//temp_string[16]=0x5B;
+	//temp_string[17]=0x41;
+	//temp_string[18]=0x00;
+	if (slow_counter == 0) { temp_string[0] = 0; }
+	if (is_TDMA_master) {
+		loc_downlink_bw = G_uplink_bandwidth_temp * 0.004;
+		loc_uplink_bw = G_downlink_bandwidth_temp * 0.004;
+		TA_loc = 0;
+	} else {
+		loc_downlink_bw = G_downlink_bandwidth_temp * 0.004;
+		loc_uplink_bw =  G_uplink_bandwidth_temp * 0.004;
+		TA_loc = TDMA_table_TA[my_radio_client_ID];
+	}
+	if (CONF_radio_state_ON_OFF == 0) {
+		HMI_printf("%s   %i status: radio OFF               \r\n", temp_string, slow_counter);
+	}
+	else if (my_client_radio_connexion_state == 0x03) {
+		HMI_printf("%s   %i status: rejected because too many %s \r\n", temp_string, slow_counter, text_reject_reason[G_connect_rejection_reason-2]);
+	} else {
+		HMI_printf("%s   %i status: %s TA:%.1fkm Temp:%idegC   \r\n", temp_string, slow_counter, text_radio_status[my_client_radio_connexion_state-1], 0.15*(float)TA_loc, G_temperature_SI4463);
+	}
+	//HMI_printf("   TX buff filling %i\r\n", (TX_buff_ext_WR_pointer - TX_buff_ext_RD_pointer)*128);//!!!test
+	if ( (is_TDMA_master == 1) && (CONF_master_FDD == 2) ) {
+		HMI_printf("   RX tops from master FDD down %i\r\n", RX_top_FDD_up_counter);
+	} else {
+		HMI_printf("   RX_Eth_IPv4 %i ;TX_radio_IPv4 %i ; RX_radio_IPv4 %i   \r\n", RX_Eth_IPv4_counter, TX_radio_IPv4_counter, RX_radio_IPv4_counter);
+		//HMI_printf("   RX_Eth_IPv4 %i ;TX_radio_IPv4 %i ; RX_radio_IPv4 %i   \r\n", RX_Eth_IPv4_counter, TX_radio_IPv4_counter, (TX_buff_ext_WR_pointer - TX_buff_ext_RD_pointer)*128);//!!!! debug FIFO filling
+	}
+	if ( (is_TDMA_master == 0) && (RSSI_stat_pkt_nb > 0) ) {
+		//HMI_printf("RSSI: %i\r\nCTRL+c to exit...\r\n", (RSSI_total_stat / RSSI_stat_pkt_nb) );
+		HMI_printf("   DOWNLINK - bandwidth:%.1f RSSI:%.1f ERR:%.2f%%    \r\n", loc_downlink_bw, ((float)G_downlink_RSSI/256/2-136), ((float)G_downlink_BER)/500); // /500
+		RSSI_total_stat = 0;
+		RSSI_stat_pkt_nb = 0;
+	} else {
+		HMI_printf("   DOWNLINK - bandwidth: %.1f RSSI:       ERR:      \r\n", loc_downlink_bw);
+		
+	}
+	if ( (is_TDMA_master == 0) && (my_client_radio_connexion_state == 2) ) {
+		HMI_printf("   UPLINK -   bandwidth:%.1f RSSI:%.1f ERR:%.2f%%    \r\nCTRL+c to exit...\r\n", loc_uplink_bw, ((float)G_radio_addr_table_RSSI[my_radio_client_ID]/2-136), ((float)G_radio_addr_table_BER[my_radio_client_ID])/500);
+	} else {
+		HMI_printf("   UPLINK -   bandwidth:%.1f RSSI:     ERR:      \r\nCTRL+c to exit...\r\n", loc_uplink_bw);
+	}
+	G_downlink_bandwidth_temp = 0;
+	G_uplink_bandwidth_temp = 0;
+}
+
+void HMI_periodic_call (void) {
+	if (display_status_ongoing) {
+		HMI_print_status();
+		slow_counter++;
+	}
+	if (display_who_ongoing) {
+		HMI_print_who();
+		slow_counter++;
+	}
+}
+
+void HMI_printf_detail (void) {
+	int size;
+	if (is_telnet_opened) {
+		size = strlen (HMI_out_str);
+		W5500_write_TX_buffer (W5500_p1, 1, (unsigned char*)HMI_out_str, size, 0);
+	}
+	else {
+		printf("%s", HMI_out_str);
+		fflush(stdout);
+	}
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/HMI_telnet.h b/NPR_FW_source_2020_06_29/NPR_14/source/HMI_telnet.h
new file mode 100755
index 0000000..8528161
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/HMI_telnet.h
@@ -0,0 +1,64 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef TELNET_F4
+#define TELNET_F4
+
+#include "mbed.h"
+#include "W5500.h"
+#include "global_variables.h"
+
+#define HMI_printf(param, ...) sprintf (HMI_out_str, param, ##__VA_ARGS__);\
+	HMI_printf_detail();
+
+int telnet_loop(W5500_chip* W5500);
+
+int serial_term_loop (void);
+
+void HMI_line_parse (char* RX_text, int RX_text_count);
+
+void HMI_cancel_current(void);
+
+
+
+int HMI_check_radio_OFF(void);
+
+void HMI_TX_test(char* duration_txt);
+
+void HMI_reboot(void);
+
+void HMI_force_exit(void);
+
+void HMI_exit(void);
+
+void HMI_display_config(void);
+
+void HMI_display_static(void);
+
+void HMI_set_command(char* loc_param1, char* loc_param2);
+
+unsigned long int HMI_str2IP(char* raw_string);
+
+unsigned char HMI_yes_no_2int(char* raw_string);
+
+void HMI_print_who(void);
+
+void HMI_periodic_call(void);
+
+void HMI_printf_detail (void);
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/L1L2_radio.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/L1L2_radio.cpp
new file mode 100755
index 0000000..c67ba37
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/L1L2_radio.cpp
@@ -0,0 +1,759 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "L1L2_radio.h"
+#include "mbed.h"
+#include "global_variables.h"
+#include "W5500.h"
+#include "SI4463.h"
+#include "Eth_IPv4.h"
+#include "TDMA.h"
+#include "signaling.h"
+
+#include "ext_SRAM2.h"
+
+//Timeout SI4463_prepa_TX_1_call;
+
+static unsigned char trash[130];
+
+static unsigned char data_RX[360];//260
+static unsigned char rframe_TX[384];
+
+void FDDup_RX_FIFO_dequeue(void) {
+	int rframe_lgth, i;
+	unsigned char data_temp;
+	unsigned long int timer_snapshot;
+	i = 0;
+	if (RX_FIFO_last_received > RX_FIFO_RD_point) {
+		for (i=0; i<=3; i++) {//4 bytes for timer and RSSI
+			data_RX[i] = RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask];
+			RX_FIFO_RD_point++;
+		}
+		data_temp = RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask];
+		RX_FIFO_RD_point++;
+		rframe_lgth = data_temp + SI4463_offset_size;
+		data_RX[4] = data_temp;
+		
+		for (i=0; i<rframe_lgth; i++) {
+			data_RX[i+5] = RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask];
+			RX_FIFO_RD_point++;
+		}
+		W5500_write_TX_buffer(W5500_p1, 4, data_RX, rframe_lgth+5, 0);
+		timer_snapshot = GLOBAL_timer.read_us();
+		last_rframe_seen = timer_snapshot;
+		//debug_counter++;
+	}
+}
+
+void FDDdown_RX_pckt_treat(unsigned char* in_data, int size) {
+	//puts raw RX radio packet from Ethernet to RX buffer
+	memcpy (RX_FIFO_data, in_data, size+4);
+	RX_FIFO_RD_point = 0;
+	RX_FIFO_last_received = size;
+	radio_RX_FIFO_dequeue(W5500_p1);
+	//debug_counter++;
+}
+
+//static int RX_FRAME_count_debug = 0;
+
+void radio_RX_FIFO_dequeue (W5500_chip* W5500) {
+	static unsigned char ethernet_buffer[radio_addr_table_size][1600]; 
+	static int size_received[radio_addr_table_size]; 
+	static unsigned char prev_seg_counter[radio_addr_table_size];  
+	static unsigned char curr_pkt_counter[radio_addr_table_size];  
+	
+	unsigned char seg_counter;
+	unsigned char pkt_counter;
+	unsigned char is_last_seg;
+	unsigned char client_addr;
+	unsigned char LID;
+	unsigned char protocol;
+	unsigned char protocol_byte;
+	unsigned char client_ID_byte;
+	unsigned char segmenter_byte;
+	//static unsigned char data_RX[260];
+	int TA_local = 100000;
+	int RSSI;
+	int rframe_lgth;
+	int size_w_FEC;
+	int size_wo_FEC;
+	int segment_size;
+	int client_ID_filter;
+	unsigned int loc_micro_BER;
+	unsigned int frame_timer;
+	static int rx_count = 0;
+	unsigned char TDMA_byte; 
+	unsigned char is_downlink;
+	unsigned long int timer_snapshot;
+	//int i;
+	
+	if (RX_FIFO_last_received > RX_FIFO_RD_point) { //something new in RX FIFO
+		timer_snapshot = GLOBAL_timer.read_us();
+		//printf ("something in RX FIFO\r\n");
+		//RX_FRAME_count_debug++;
+		//printf("%i RX:", RX_FRAME_count_debug);
+		//for (i=4; i<10; i++){
+		//	printf("%02X.",RX_FIFO_data[(RX_FIFO_RD_point+i) & RX_FIFO_mask]);
+		//}
+		//printf("\r\n");
+		frame_timer = RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask];
+		RX_FIFO_RD_point++;
+		frame_timer = (0x100 * RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask]) + frame_timer;
+		RX_FIFO_RD_point++;
+		frame_timer = (0x10000 * RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask]) + frame_timer;
+		RX_FIFO_RD_point++;
+		RSSI = RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask];
+		RX_FIFO_RD_point++;
+		rframe_lgth = RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask] + SI4463_offset_size;
+		RX_FIFO_RD_point++;
+		if (rframe_lgth > SI4463_CONF_max_field2_size) {
+			rframe_lgth = SI4463_CONF_max_field2_size;
+		}
+		TDMA_byte = RX_FIFO_data[RX_FIFO_RD_point & RX_FIFO_mask];
+		is_downlink = TDMA_byte & 0x40; 
+		RX_FIFO_RD_point++;
+		client_ID_byte = RX_FIFO_data[ (RX_FIFO_RD_point ) & RX_FIFO_mask]; // +1
+		protocol_byte = RX_FIFO_data[ (RX_FIFO_RD_point + 1) & RX_FIFO_mask]; // +2
+		
+		size_w_FEC = rframe_lgth - 1; 
+		
+		if (is_TDMA_master) {
+			TA_local = TDMA_TA_measure_single_frame(frame_timer, TDMA_byte, client_ID_byte, size_w_FEC);
+			if ( (timer_snapshot-last_rframe_seen) > (CONF_radio_timeout+1000000) ) {
+				last_rframe_seen = timer_snapshot;
+				wait_ms(20);//lets time for client to switch to RX
+				SI4463_prepa_TX_1();
+			}
+		}
+		last_rframe_seen = timer_snapshot;
+
+		// WITH FEC
+		size_wo_FEC = FEC_decode(data_RX, size_w_FEC, &loc_micro_BER);
+		//if (loc_micro_BER>0) {printf("err micro%i\r\n", loc_micro_BER);}
+		radio_save_RSSI_BER (client_ID_byte, is_downlink, RSSI, loc_micro_BER); 
+		//printf("RSSI:%i BER:%i\r\n", RSSI, loc_micro_BER);
+		protocol = 0;
+		if ( size_wo_FEC > 0) { 
+			client_addr = data_RX[0] & 0x7F; //inside FEC, non need to use parity bit
+			if (is_TDMA_master) {
+				LID = client_addr; //client_addr;
+			} else {
+				LID = 0;//only one RX buffer for clients
+			}
+			protocol = data_RX[1];
+			// client ID filter 
+			client_ID_filter = 0;
+			if (is_TDMA_master) {
+				if ( (is_downlink == 0) && (client_addr < radio_addr_table_size) ) {
+					if (CONF_radio_addr_table_status[client_addr]) {
+						client_ID_filter = 1;
+					}
+				}
+				if ( (is_downlink == 0) && (client_addr == 0x7E) ) {
+					client_ID_filter = 1;
+				}
+			}
+			else if ( ( (client_addr == my_radio_client_ID) || (client_addr == 0x7F) ) && (is_downlink) ) {
+				client_ID_filter = 1;
+			}
+			if (client_ID_filter) {
+				/* 
+				if ( (protocol == 0x01) && (LID < radio_addr_table_size) ) { //RAW ETHERNET
+					segment_size = size_wo_FEC - 3;
+					segmenter_byte = data_RX[2];
+					pkt_counter = (segmenter_byte & 0xF0) / 0x10; 
+					is_last_seg = segmenter_byte & 0x08;
+					seg_counter = segmenter_byte & 0x07;
+					//printf("RX seg:%02X\r\n", segmenter_byte);
+					
+					if (seg_counter == 0) {//beginning of a new pkt
+						curr_pkt_counter[LID] = pkt_counter;
+						memcpy (ethernet_buffer[LID], data_RX+3, segment_size);
+						size_received[LID] = segment_size;
+						//printf("1st seg\r\n");
+					} 
+					else if ( (seg_counter == (prev_seg_counter[LID] + 1)) && (pkt_counter == curr_pkt_counter[LID]) ) {
+						//folowing segment
+						memcpy ( (ethernet_buffer[LID]+size_received[LID]), data_RX+3, segment_size);
+						size_received[LID] = size_received[LID] + segment_size;
+						//printf("follow seg\r\n");
+					} 
+					else { //continuity error
+						size_received[LID] = 0;
+					}
+					prev_seg_counter[LID] = seg_counter;
+					
+					if ( (is_last_seg == 0x08) && (size_received[LID] > 0) ) {
+						// Raw Ethernet... Not implemented yet
+					}
+				} */
+				if ( (protocol == 0x02) && (LID < radio_addr_table_size) ) { //IPv4 Access 0x02
+					//printf("IPv4 fr received\r\n");
+					segment_size = size_wo_FEC - 3;
+					segmenter_byte = data_RX[2];
+					pkt_counter = (segmenter_byte & 0xF0) / 0x10; 
+					is_last_seg = segmenter_byte & 0x08;
+					seg_counter = segmenter_byte & 0x07;
+					//printf("RX seg:%02X\r\n", segmenter_byte);
+					
+					if (seg_counter == 0) {//beginning of a new pkt
+						curr_pkt_counter[LID] = pkt_counter;
+						memcpy (ethernet_buffer[LID] + 14, data_RX+3, segment_size);
+						size_received[LID] = segment_size;
+						//printf("1st seg\r\n");
+					} 
+					else if ( (seg_counter == (prev_seg_counter[LID] + 1)) && (pkt_counter == curr_pkt_counter[LID]) ) {
+						//folowing segment
+						memcpy ( (ethernet_buffer[LID] + size_received[LID] +14), data_RX+3, segment_size);
+						size_received[LID] = size_received[LID] + segment_size;
+						//printf("follow seg\r\n");
+					} 
+					else { //continuity error
+						size_received[LID] = 0;
+					}
+					prev_seg_counter[LID] = seg_counter;
+					
+					if ( (is_last_seg == 0x08) && (size_received[LID] > 0) ) {
+						IPv4_from_radio (ethernet_buffer[LID], size_received[LID] + 14);
+						G_downlink_bandwidth_temp = G_downlink_bandwidth_temp + size_received[LID];
+						RX_radio_IPv4_counter++;
+						//printf("pkt full\r\n");
+					}
+				}
+				else if (protocol == 0x1E) {
+					//printf("sig fr received\r\n");
+					signaling_frame_exploitation (data_RX, size_wo_FEC, TA_local);
+				}
+				else if ( (protocol == 0x1F) && (is_TDMA_master == 0) ) {
+					TDMA_slave_alloc_exploitation (data_RX, size_wo_FEC);
+				} 
+				else if (protocol == 0x00) {
+					
+				}
+				else {
+					if (super_debug) {
+						printf("ERR Protocol\r\n");
+					}
+				}
+			}
+		} else {
+			if (super_debug) {
+				printf("FEC error\r\n");
+			}
+		}
+		TDMA_byte_RX_interp (TDMA_byte, client_ID_byte, protocol_byte, frame_timer);
+		rx_count++;
+	}
+}
+
+void radio_signalisation_frame_building(void) {
+	
+}
+
+int FEC_encode2 (unsigned char* data_in, unsigned char* data_out, int size_in) { 
+	int size_out;
+	int size_single_bloc;
+	int size_single_bloc_pl1;
+	unsigned char CRC_1; 
+	unsigned char CRC_2; 
+	unsigned char CRC_3; 
+	unsigned char CRC_4; 
+	unsigned char data_field_1;
+	unsigned char data_field_2;
+	unsigned char data_field_3;
+	unsigned char data_field_4;
+	int i; 
+	CRC_1 = 0;
+	CRC_2 = 0;
+	CRC_3 = 0;
+	CRC_4 = 0;
+	
+	size_single_bloc = size_in/3;
+	if (size_in % 3) {
+		size_single_bloc++;
+	}
+	size_single_bloc_pl1 = size_single_bloc + 1;
+	size_out = 4 * size_single_bloc_pl1; 
+	for (i=0; i<size_single_bloc; i++) {
+		data_field_1 = data_in[i];
+		data_field_2 = data_in[size_single_bloc + i];
+		data_field_3 = data_in[(2*size_single_bloc) + i];
+		data_field_4 = data_field_1 ^ data_field_2 ^ data_field_3; 
+		CRC_1 = CRC_1 ^ data_field_1; 
+		CRC_2 = CRC_2 ^ data_field_2; 
+		CRC_3 = CRC_3 ^ data_field_3; 
+		CRC_4 = CRC_4 ^ data_field_4; 
+		data_out[i] = data_field_1;
+		data_out[size_single_bloc_pl1 + i] = data_field_2;
+		data_out[(2*size_single_bloc_pl1) + i] = data_field_3;
+		data_out[(3*size_single_bloc_pl1) + i] = data_field_4;
+	}
+	data_out[size_single_bloc] = CRC_1;
+	data_out[(2*size_single_bloc) + 1] = CRC_2;
+	data_out[(3*size_single_bloc) + 2] = CRC_3;
+	data_out[(4*size_single_bloc) + 3] = CRC_4;
+	return size_out;
+}
+
+ int FEC_decode(unsigned char* data_out, int size_in, unsigned int* micro_BER) {
+	int size_out; 
+	int size_single_bloc;
+	int size_single_bloc_pl1;
+	unsigned char CRC_check_1;
+	unsigned char CRC_check_2;
+	unsigned char CRC_check_3;
+	unsigned char CRC_check_4;
+	unsigned char data_temp; 
+	unsigned int nb_errors;
+	int i; 
+	size_single_bloc_pl1 = size_in / 4;
+	size_single_bloc = size_single_bloc_pl1 - 1;
+	
+	CRC_check_1 = 0;
+	CRC_check_2 = 0;
+	CRC_check_3 = 0;
+	CRC_check_4 = 0;
+	for (i=0; i<size_single_bloc_pl1; i++) {
+		CRC_check_1 = CRC_check_1 ^ RX_FIFO_data [(RX_FIFO_RD_point + i) & RX_FIFO_mask];
+		CRC_check_2 = CRC_check_2 ^ RX_FIFO_data [(RX_FIFO_RD_point + size_single_bloc_pl1 + i) & RX_FIFO_mask];
+		CRC_check_3 = CRC_check_3 ^ RX_FIFO_data [(RX_FIFO_RD_point + (2*size_single_bloc_pl1) + i) & RX_FIFO_mask];
+		CRC_check_4 = CRC_check_4 ^ RX_FIFO_data [(RX_FIFO_RD_point + (3*size_single_bloc_pl1) + i) & RX_FIFO_mask];
+	}
+	
+	nb_errors = 0;
+	if (CRC_check_1 != 0) { nb_errors++; }// printf("error 1  %X ;", CRC_check_1);}
+	if (CRC_check_2 != 0) { nb_errors++; }// printf("error 2  %X ;", CRC_check_2);}
+	if (CRC_check_3 != 0) { nb_errors++; }// printf("error 3  %X ;", CRC_check_3);}
+	if (CRC_check_4 != 0) { nb_errors++; }// printf("error 4  %X ;", CRC_check_4);}
+	//printf("\r\n");
+	//if (nb_errors>0) {printf("ERR%i\r\n", nb_errors);}
+	
+	(*micro_BER) = nb_errors;
+	
+	if (nb_errors>1) {
+		size_out = 0; //unrecoverable error
+		//printf("unrecoverable\r\n");
+	} else {
+		// OK
+		size_out = 3 * size_single_bloc; 
+		// FIELD 1
+		if (CRC_check_1==0) {//field 1 OK
+			for (i=0; i<size_single_bloc; i++) {
+				data_out[i] = RX_FIFO_data [(RX_FIFO_RD_point + i) & RX_FIFO_mask];
+			}
+		} else {// field 1 corrupted, reconstruction from field 2, 3 and 4
+			for (i=0; i<size_single_bloc; i++) {
+				data_temp = RX_FIFO_data [(RX_FIFO_RD_point + size_single_bloc_pl1 + i) & RX_FIFO_mask]; 
+				data_temp = data_temp ^ RX_FIFO_data [(RX_FIFO_RD_point + (2*size_single_bloc_pl1) + i) & RX_FIFO_mask];
+				data_temp = data_temp ^ RX_FIFO_data [(RX_FIFO_RD_point + (3*size_single_bloc_pl1) + i) & RX_FIFO_mask];
+				data_out[i] = data_temp; 
+			}
+		}
+		// FIELD 2
+		if (CRC_check_2==0) {//field 2 OK
+			for (i=0; i<size_single_bloc; i++) {
+				data_out[size_single_bloc + i] = RX_FIFO_data [(RX_FIFO_RD_point + size_single_bloc_pl1 + i) & RX_FIFO_mask];
+			}
+		} else {// field 2 corrupted, reconstruction from field 1, 3 and 4
+			for (i=0; i<size_single_bloc; i++) {
+				data_temp = RX_FIFO_data [(RX_FIFO_RD_point + i) & RX_FIFO_mask]; //field 1
+				data_temp = data_temp ^ RX_FIFO_data [(RX_FIFO_RD_point + (2*size_single_bloc_pl1) + i) & RX_FIFO_mask]; //field 3
+				data_temp = data_temp ^ RX_FIFO_data [(RX_FIFO_RD_point + (3*size_single_bloc_pl1) + i) & RX_FIFO_mask]; //field 4
+				data_out[size_single_bloc + i] = data_temp; 
+			}
+		}
+		// FIELD 3
+		if (CRC_check_3==0) {//field 3 OK
+			for (i=0; i<size_single_bloc; i++) {
+				data_out[(2*size_single_bloc) + i] = RX_FIFO_data[(RX_FIFO_RD_point + (2*size_single_bloc_pl1) + i) & RX_FIFO_mask];
+			}
+		} else {// field 3 corrupted, reconstruction from field 1, 2 and 4
+			for (i=0; i<size_single_bloc; i++) {
+				data_temp = RX_FIFO_data [(RX_FIFO_RD_point + i) & RX_FIFO_mask]; //field 1
+				data_temp = data_temp ^ RX_FIFO_data [(RX_FIFO_RD_point + size_single_bloc_pl1 + i) & RX_FIFO_mask]; //field 2
+				data_temp = data_temp ^ RX_FIFO_data [(RX_FIFO_RD_point + (3*size_single_bloc_pl1) + i) & RX_FIFO_mask]; //field 4
+				data_out[(2*size_single_bloc) + i] = data_temp; 
+			}
+		}
+	}
+	RX_FIFO_RD_point = RX_FIFO_RD_point + size_in; 
+	return size_out; 
+}
+
+int size_w_FEC_compute (int size_wo_FEC) {
+	int size_w_FEC; 
+	size_w_FEC = size_wo_FEC/3;
+	if ((size_wo_FEC%3) > 0) { size_w_FEC++; }
+	size_w_FEC = 4*size_w_FEC + 4;
+	return size_w_FEC; 
+}
+
+void segment_and_push (unsigned char* data_unsegmented, int total_size, unsigned char client_addr, unsigned char protocol) {
+	static unsigned char packet_counter = 0;
+	unsigned char segment_counter = 0;
+	unsigned char segmenter_byte;
+	unsigned char is_last_segment;
+	int size_wo_FEC;
+	int size_w_FEC;
+	int rframe_length;
+	int size_remaining;
+	int segment_size; 
+	int size_to_send;
+	unsigned char data_wo_FEC[300];
+#ifdef EXT_SRAM_USAGE
+	unsigned char radio_pckt[360];
+#endif
+	int size_sent;
+	unsigned int rsize_needed;
+	unsigned int timer_snapshot;
+	size_remaining = total_size;
+
+	if (size_remaining <63) {
+		size_remaining = 63;
+	}
+	
+	segment_counter = 0;
+	size_sent = 0;
+	rsize_needed = 100 + (total_size * 1.4);
+	if (total_size < 1510) {
+		if (TX_FIFO_full_global(1) == 0) {
+			G_uplink_bandwidth_temp = G_uplink_bandwidth_temp + total_size; 
+			TX_radio_IPv4_counter++;
+			while (size_remaining > 0) {
+				if (size_remaining <= 252) {
+					segment_size = size_remaining; 
+					is_last_segment = 0x08;
+				} else {
+					segment_size = 252;
+					is_last_segment = 0x00;
+				}
+				if (segment_size <63) {
+					size_to_send = 63;
+				} else {
+					size_to_send = segment_size;
+				}
+				timer_snapshot = GLOBAL_timer.read_us();
+				rframe_TX[0] = (timer_snapshot >> 16) & 0xFF;
+			
+				size_wo_FEC = size_to_send + 3; //+ 3 inside FEC header
+				size_w_FEC = size_w_FEC_compute (size_wo_FEC);
+				rframe_length = size_w_FEC + 1 - SI4463_offset_size;
+				if (rframe_length < 0) {rframe_length = 0;}
+				rframe_TX[1] = rframe_length;
+				rframe_TX[2] = 0x01; //TDMA byte
+				
+				segmenter_byte = (packet_counter & 0x0F) * 0x10 + is_last_segment + (segment_counter & 0x07);
+				data_wo_FEC[0] = client_addr + parity_bit_elab[(client_addr&0x7F)]; //client address
+				data_wo_FEC[1] = protocol; //protocol : raw ethernet
+				data_wo_FEC[2] = segmenter_byte; // segmenter byte
+				memcpy(data_wo_FEC+3, (data_unsegmented + size_sent), size_to_send); 
+				size_sent = size_sent + size_to_send;
+				size_w_FEC = FEC_encode2(data_wo_FEC, rframe_TX+3, size_wo_FEC); 
+				TX_FIFO_write_global(rframe_TX, size_w_FEC+3);//3 for timer & length & TDMA_byte
+				size_remaining = size_remaining - segment_size; 
+				segment_counter++;
+				
+			}
+			packet_counter++;
+		} else {
+			//if (super_debug) {
+			//	printf ("FULL last_ready:%08X RD_point:%08X\r\n", TXPS_FIFO->last_ready, TXPS_FIFO->RD_point);
+			//}
+		}
+	}
+}
+
+//unsigned char TX_buff_intern_FIFOdata[42][384];
+//unsigned int TX_buff_intern_WR_pointer=0;
+//unsigned int TX_buff_intern_RD_pointer=0;
+//unsigned int TX_buff_intern_last_ready=0;
+
+void TX_FIFO_write_global(unsigned char* data, int size) {
+	if (is_SRAM_ext == 1) {
+		TX_ext_FIFO_write(data, size);
+	} else {
+		TX_intern_FIFO_write(data, size);
+	}
+}
+
+void TX_intern_FIFO_write(unsigned char* data, int size) {
+	if (size <= 128) {
+		memcpy (TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], data, 128);//size
+		TX_buff_intern_WR_pointer++;
+	}
+	else if (size <= 256) {
+		memcpy (TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], data, 128);
+		TX_buff_intern_WR_pointer++;
+		memcpy (TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], data+128, 128);//size-128
+		TX_buff_intern_WR_pointer++;
+	}
+	else {
+		memcpy (TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], data, 128);
+		TX_buff_intern_WR_pointer++;
+		memcpy (TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], data+128, 128);
+		TX_buff_intern_WR_pointer++;
+		memcpy (TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], data+256, 128);//size-256
+		TX_buff_intern_WR_pointer++;
+	}
+	TX_buff_intern_last_ready = TX_buff_intern_WR_pointer;
+}
+
+void ext_SRAM_write2(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size) {
+	//static unsigned char trash[350];
+	static unsigned char command[6] = {0x02, 0x00, 0x00, 0x00};
+	loc_SPI->cs->write(0);
+	command[3] = address & 0xFF;
+	command[2] = (address & 0xFF00) >> 8;
+	command[1] = (address & 0xFF0000) >> 16;
+	loc_SPI->spi_port->transfer_2 (command, 4, trash, 4);
+	loc_SPI->spi_port->transfer_2 (loc_data, size, trash, size);
+	loc_SPI->cs->write(1);
+}
+
+void TX_ext_FIFO_write(unsigned char* data, int size) {
+	unsigned int loc_address;
+	//printf("size_wr_ext %i\n\r", size);
+	if (size <= 128) {
+		loc_address = (TX_buff_ext_WR_pointer & 1023)*128;
+		ext_SRAM_write2(SPI_SRAM_p, data, loc_address, size);
+		TX_buff_ext_sizes[TX_buff_ext_WR_pointer & 1023] = data[1];
+		TX_buff_ext_WR_pointer++;
+	}
+	else if (size <= 256) {
+		loc_address = (TX_buff_ext_WR_pointer & 1023)*128;
+		ext_SRAM_write2(SPI_SRAM_p, data, loc_address, 128);
+		TX_buff_ext_sizes[TX_buff_ext_WR_pointer & 1023] = data[1];
+		TX_buff_ext_WR_pointer++;
+		loc_address = (TX_buff_ext_WR_pointer & 1023)*128;
+		ext_SRAM_write2(SPI_SRAM_p, data+128, loc_address, size-128);
+		TX_buff_ext_sizes[TX_buff_ext_WR_pointer & 1023] = 0;
+		TX_buff_ext_WR_pointer++;
+	}
+	else {
+		loc_address = (TX_buff_ext_WR_pointer & 1023)*128;
+		ext_SRAM_write2(SPI_SRAM_p, data, loc_address, 128);
+		TX_buff_ext_sizes[TX_buff_ext_WR_pointer & 1023] = data[1];
+		TX_buff_ext_WR_pointer++;
+		loc_address = (TX_buff_ext_WR_pointer & 1023)*128;
+		ext_SRAM_write2(SPI_SRAM_p, data+128, loc_address, 128);
+		TX_buff_ext_sizes[TX_buff_ext_WR_pointer & 1023] = 0;
+		TX_buff_ext_WR_pointer++;
+		loc_address = (TX_buff_ext_WR_pointer & 1023)*128;
+		ext_SRAM_write2(SPI_SRAM_p, data+256, loc_address, size-256);
+		TX_buff_ext_sizes[TX_buff_ext_WR_pointer & 1023] = 0;
+		TX_buff_ext_WR_pointer++;
+	}
+	TX_buff_ext_last_ready = TX_buff_ext_WR_pointer;
+}
+
+int TX_intern_FIFO_get_lastfrzize(void) {
+	int size_loc;
+	size_loc = TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128][1];
+	size_loc = size_loc + 1 + SI4463_offset_size;
+	return size_loc;
+}
+
+int TX_intern_FIFO_read(unsigned char* data) {
+	int size_loc;
+	size_loc = TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128][1];//42
+	size_loc = size_loc + 1 + SI4463_offset_size;
+	size_loc = size_loc + 1;//for timer coarse
+	//printf("sizeread: %i\r\n", size_loc);
+	if (size_loc <= 128) {
+		memcpy(data, TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128], 128);//size_loc
+		TX_buff_intern_RD_pointer++;
+	} 
+	else if (size_loc<=256) {
+		memcpy(data, TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128], 128);
+		TX_buff_intern_RD_pointer++;
+		memcpy(data+128, TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128], 128);//size_loc-128
+		TX_buff_intern_RD_pointer++;
+	}
+	else {
+		memcpy(data, TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128], 128); 
+		TX_buff_intern_RD_pointer++;
+		memcpy(data+128, TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128], 128);
+		TX_buff_intern_RD_pointer++;
+		memcpy(data+256, TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128], 128);//size_loc-256
+		TX_buff_intern_RD_pointer++;
+	}
+	return size_loc;
+}
+
+unsigned int compute_TX_buff_size_global(void) {//for TDMA
+	unsigned int size_loc;
+	if (is_SRAM_ext == 1) {
+		size_loc = (TX_buff_intern_last_ready - TX_buff_intern_RD_pointer);
+		size_loc = size_loc + (TX_buff_ext_last_ready - TX_buff_ext_RD_pointer);
+		size_loc = size_loc/3;
+	} else {
+		size_loc = (TX_buff_intern_last_ready - TX_buff_intern_RD_pointer)/3;
+	}
+	return size_loc;
+}
+
+int TX_FIFO_full_global (int priority) {
+	if (is_SRAM_ext == 1) {
+		return TX_FIFO_full_withSRAM(priority);
+	} else {
+		return TX_FIFO_full_woSRAM(priority);
+	}
+}
+
+int TX_FIFO_full_woSRAM (int priority) {
+	//priority : 1= normal, 0=high priority (signaling)
+	int FIFO_filling;
+	int loc_threshold;
+	FIFO_filling = TX_buff_intern_WR_pointer - TX_buff_intern_RD_pointer;
+	if (priority == 1) {
+		loc_threshold = 110;//low priority
+	} else {
+		loc_threshold = 120;//high priority
+	}
+	if (FIFO_filling > loc_threshold) {//40
+		//printf("FIFO_full!\r\n");
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int TX_FIFO_full_withSRAM (int priority) {
+	int FIFO_filling;
+	int loc_threshold;
+	FIFO_filling = TX_buff_ext_WR_pointer - TX_buff_ext_RD_pointer;
+	if (priority == 1) {
+		loc_threshold = 950;//low priority
+	} else {
+		loc_threshold = 1000;//high priority
+	}
+	if (FIFO_filling > loc_threshold) {//40
+		//printf("FIFO_fullext!\r\n");
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+void ext_SRAM_read2(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size) {
+	static unsigned char command[6] = {0x03, 0x00, 0x00, 0x00};
+	loc_SPI->cs->write(0);
+	command[3] = address & 0xFF;
+	command[2] = (address & 0xFF00) >> 8;
+	command[1] = (address & 0xFF0000) >> 16;
+	loc_SPI->spi_port->transfer_2 (command, 4, trash, 4);
+	loc_SPI->spi_port->transfer_2 (trash, size, loc_data, size);
+	loc_SPI->cs->write(1);
+}
+
+void ext_SRAM_periodic_call(void) {
+	int intern_FIFO_filling;
+	int ext_FIFO_filling;
+	int i, loc_size;
+	int loc_bloc_nb=1;
+	unsigned int loc_address;
+	unsigned int loc_time_int;
+	unsigned char RX_frame_datation;
+	unsigned char loc_time_char;
+	loc_time_int = GLOBAL_timer.read_us();
+	loc_time_char = (loc_time_int >> 16) & 0xFF; 
+	intern_FIFO_filling = TX_buff_intern_WR_pointer - TX_buff_intern_RD_pointer;
+	ext_FIFO_filling = TX_buff_ext_WR_pointer - TX_buff_ext_RD_pointer;
+	while ( (ext_FIFO_filling > 0) && (intern_FIFO_filling <= 9) ) {
+		for (i=1; i<=loc_bloc_nb; i++) {
+			loc_address = (TX_buff_ext_RD_pointer & 1023) *128;
+			ext_SRAM_read2(SPI_SRAM_p, TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], loc_address, 128);
+			
+			if (i==1) {
+				RX_frame_datation = TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128][0];
+				loc_size = TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128][1];
+				loc_size = loc_size + SI4463_offset_size + 2;
+				//printf("size:%i\r\n", loc_size);
+				if (loc_size <= 128) {
+					loc_bloc_nb = 1;
+				} else if (loc_size <= 256) {
+					loc_bloc_nb = 2;
+				} else {
+					loc_bloc_nb = 3;
+				}
+			}
+			
+			//if (TX_buff_ext_sizes[TX_buff_ext_RD_pointer & 1023] > 0) {
+			//	TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128][1] = TX_buff_ext_sizes[TX_buff_ext_RD_pointer & 1023];
+			//}
+			TX_buff_ext_RD_pointer++;
+			//printf("delay %i\r\n", (int)loc_time_char - (int)RX_frame_datation);
+			if ( (loc_time_char - RX_frame_datation) < CONF_Tx_rframe_timeout) {
+			//if (1) {
+				//purge old frames if condition false
+				TX_buff_intern_WR_pointer++;
+			} 
+			//else {
+			//	printf ("purged!\r\n");//!!!
+			//	printf("date1 %i date2 %i\r\n", loc_time_char, RX_frame_datation); 
+			//}
+		}
+		TX_buff_intern_last_ready = TX_buff_intern_WR_pointer;	
+		intern_FIFO_filling = TX_buff_intern_WR_pointer - TX_buff_intern_RD_pointer;
+		ext_FIFO_filling = TX_buff_ext_WR_pointer - TX_buff_ext_RD_pointer;
+	}
+}
+
+
+//void radio_flush_TX_FIFO(void) {
+//	TXPS_FIFO->WR_point = 0;
+//	TXPS_FIFO->RD_point = 0;
+//	TXPS_FIFO->last_ready = 0;
+//}
+
+int ext_SRAM_detect(void) {
+	unsigned char data_1[4] = {0x3C, 0x4A, 0xF3, 0x12};
+	unsigned char data_2[4] = {0xFF, 0xFF, 0xFF, 0xFF};
+	int i; 
+	int sram_detected = 1;
+	ext_SRAM_write2(SPI_SRAM_p, data_1, 2345, 4);
+	ext_SRAM_read2(SPI_SRAM_p, data_2, 2345, 4);
+	for (i=0; i<4; i++) {
+		if (data_2[i] != data_1[i]) {sram_detected = 0;}
+	}
+	return sram_detected;
+}
+
+void radio_flush_TX_FIFO(void) {
+	TX_buff_intern_WR_pointer=0;
+	TX_buff_intern_RD_pointer=0;
+	TX_buff_intern_last_ready=0;
+	TX_buff_ext_WR_pointer=0;
+	TX_buff_ext_RD_pointer=0;
+	TX_buff_ext_last_ready=0;
+}
+
+void radio_save_RSSI_BER (unsigned char client_byte, unsigned char is_downlink, unsigned char RSSI_loc, unsigned int micro_BER) {
+	unsigned char client_ID = 0xF0;
+	client_ID = client_byte & 0x7F;
+	
+	if ( (is_TDMA_master) && (is_downlink == 0) && (parity_bit_check[client_byte]) && (client_ID < radio_addr_table_size) ) {
+		G_radio_addr_table_RSSI[client_ID] = (26 * RSSI_loc) + (0.9 * G_radio_addr_table_RSSI[client_ID]);
+		G_radio_addr_table_BER[client_ID] = (1250 * micro_BER) + (0.9 * G_radio_addr_table_BER[client_ID]);
+		
+	}
+	if ( (is_TDMA_master == 0) && (is_downlink) ) {
+		G_downlink_RSSI = (26 * RSSI_loc) + (0.9 * G_downlink_RSSI);
+		G_downlink_BER = (1250 * micro_BER) + (0.9 * G_downlink_BER);
+	}
+	//if (micro_BER>0) {printf("err save%i %i\r\n", micro_BER, G_downlink_BER);}
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/L1L2_radio.h b/NPR_FW_source_2020_06_29/NPR_14/source/L1L2_radio.h
new file mode 100755
index 0000000..140a9e4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/L1L2_radio.h
@@ -0,0 +1,66 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef L1L2_RADIO_F4
+#define L1L2_RADIO_F4
+
+#include "mbed.h"
+#include "W5500.h"
+#include "global_variables.h"
+#include "ext_SRAM2.h"
+
+void FDDdown_RX_pckt_treat(unsigned char* in_data, int size);
+
+void FDDup_RX_FIFO_dequeue(void);
+
+void radio_RX_FIFO_dequeue (W5500_chip* W5500);
+
+void radio_signalisation_frame_building(void);
+
+//int FEC_encode (unsigned char* data_in, TX_buffer_struct* FIFO_out, int size_in); 
+//#ifdef EXT_SRAM_USAGE
+int FEC_encode2 (unsigned char* data_in, unsigned char* data_out, int size_in);
+//#endif
+int FEC_decode(unsigned char* data_out, int size_in, unsigned int* micro_BER); 
+
+int size_w_FEC_compute (int size_wo_FEC); 
+
+void segment_and_push (unsigned char* data_unsegmented, int total_size, unsigned char client_addr, unsigned char protocol); 
+
+void TX_FIFO_write_global(unsigned char* data, int size);
+void TX_intern_FIFO_write(unsigned char* data, int size);
+void TX_ext_FIFO_write(unsigned char* data, int size);
+
+int TX_intern_FIFO_get_lastfrzize(void);
+
+int TX_intern_FIFO_read(unsigned char* data);
+
+unsigned int compute_TX_buff_size_global(void);
+
+int TX_FIFO_full_global (int priority);
+int TX_FIFO_full_woSRAM (int priority);
+int TX_FIFO_full_withSRAM (int priority);
+
+void ext_SRAM_periodic_call(void);
+
+int ext_SRAM_detect(void);
+
+void radio_flush_TX_FIFO(void);
+
+void radio_save_RSSI_BER (unsigned char client_byte, unsigned char is_downlink, unsigned char RSSI_loc, unsigned int micro_BER);
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463.cpp
new file mode 100755
index 0000000..f791390
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463.cpp
@@ -0,0 +1,1404 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "SI4463.h"
+
+#include "mbed.h"
+#include "global_variables.h"
+#include "TDMA.h"
+#include "HMI_telnet.h"
+#include "L1L2_radio.h"
+ 
+#ifdef FREQ_BAND_2M
+	#include "SI4463_config_20_2m.h"
+	#include "SI4463_config_11_2m.h"
+	#include "SI4463_config_21_2m.h"
+	#include "SI4463_config_12_2m.h"
+	#include "SI4463_config_22_2m.h"
+	#include "SI4463_config_13_2m.h"
+	#include "SI4463_config_23_2m.h"
+	#include "SI4463_config_14_2m.h"
+	#include "SI4463_config_24_2m.h"
+#else 
+	//#include "SI4463_config_10.h"
+	#include "SI4463_config_20.h"
+	//#include "radio_config_Si4463_20.h"
+	#include "SI4463_config_11.h"
+	//#include "radio_config_Si4463_11.h"
+	#include "SI4463_config_21.h"
+	//#include "SI4463_config_21_GMSK.h"
+	//#include "radio_config_Si4463_21.h"
+	#include "SI4463_config_12.h"
+	#include "SI4463_config_22.h"
+	//#include "radio_config_Si4463_22.h"
+	#include "SI4463_config_13.h"
+	//#include "radio_config_Si4463_13.h"
+	#include "SI4463_config_23.h"
+	//#include "radio_config_Si4463_23.h"
+	#include "SI4463_config_14.h"
+	#include "SI4463_config_24.h"
+	//#include "radio_config_Si4463_24.h"
+#endif 
+
+//Timeout SI4463_prepa_TX_1_call;
+Timeout SI4463_prepa_TX_2_call;
+Timeout SI4463_1st_TX_call;
+Timeout SI4463_RX_timeout_call; //2019_04_05
+//Ticker SI4463_temp_check2_call;
+
+//TX_buffer_struct* TX_buff; //data structure currently used to TX
+
+static unsigned char SI_trash[150];
+static unsigned char TX_temp_rframe[384];
+static unsigned char* TX_frame_to_send;
+static unsigned char TX_in_progress = 0;
+static unsigned char TX_test_inprogress = 0;
+//int TX_frame_pointer;
+
+// Low level functions & drivers
+void SI4463_send_command(SI4463_Chip* SI4463, unsigned char* data, int size) {
+	unsigned char loc_RX[30];
+	SI4463->cs->write(0);
+	SI4463->spi->transfer_2(data, size, loc_RX, size);
+	SI4463->cs->write(1);
+	wait_us(1); 
+}
+ 
+int SI4463_CTS_read_answer(SI4463_Chip* SI4463, unsigned char* data, int size, int timeout) {
+	unsigned char loc_RX[10];
+	unsigned char loc_TX[10];
+	int answer;
+	int loops = 0;
+	loc_TX[0] = 0x44;
+	loops = 0;
+	SI4463->cs->write(0);
+	SI4463->spi->transfer_2(loc_TX, 2, loc_RX, 2);
+	while ((loc_RX[1] != 0xFF) && (loops < timeout)) {
+		SI4463->cs->write(1);
+		wait_us(20);
+		SI4463->cs->write(0);
+		SI4463->spi->transfer_2(loc_TX, 2, loc_RX, 2);
+		loops++;
+	}
+	if (size > 0) {
+		SI4463->spi->transfer_2(loc_TX, size, data, size);
+	}
+	SI4463->cs->write(1);
+	wait_us(1);
+	if (loops >= timeout) {
+		answer = 0; 
+	} else {
+		answer =1;
+	}
+	//printf (" loc answer:%i ", answer);
+	return answer;
+}
+
+//** Higher level functions ***
+
+// configures using RADIO_CONFIGURATION_DATA_ARRAY
+
+//int SI4463_configure_from_10(SI4463_Chip* SI4463) {
+//	unsigned char radio_config_data_10[1400] = RADIO_CONFIGURATION_DATA_ARRAY_10;//22
+//	CONF_TDMA_frame_duration = 939000;
+//	CONF_TDMA_slot_duration = 53400;
+//	CONF_reduced_TDMA_slot_duration = 20400; 
+//	CONF_TDMA_slot_margin = 300;
+//	CONF_TR_margain = 1300; 
+//	CONF_TA_margain = 2000;
+//	CONF_preamble_duration_for_decide = 3100; //1090
+//	CONF_long_preamble_duration_for_TA = 3833;//1420
+//	CONF_byte_duration = 143;
+//	CONF_preamble_TX_long = 22;
+//	CONF_preamble_TX_short = 16;
+//	CONF_Tx_rframe_timeout = 30;
+//	CONF_radio_timeout_small = 10000000;//10sec
+//	CONF_signaling_period = 1;
+//	return SI4463_configure_from_h (SI4463, radio_config_data_10);
+//}
+
+int SI4463_configure_from_20(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_20[1250] = RADIO_CONFIGURATION_DATA_ARRAY_20;//22
+	//unsigned char radio_config_data_20[1400] = RADIO_CONFIGURATION_DATA_ARRAY;
+	CONF_TDMA_frame_duration = 560000;
+	CONF_TDMA_slot_duration = 31600;
+	CONF_reduced_TDMA_slot_duration = 12700; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 2670; //1090
+	CONF_long_preamble_duration_for_TA = 3751;//1420
+	CONF_byte_duration = 80;
+	CONF_preamble_TX_long = 20;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 120;//8sec
+	CONF_radio_timeout = 60000000;
+	CONF_radio_timeout_small = 10000000;//10sec previously 20
+	CONF_signaling_period = 2;//4 sec
+	return SI4463_configure_from_h (SI4463, radio_config_data_20);
+}
+
+int SI4463_configure_from_11(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_11[1250] = RADIO_CONFIGURATION_DATA_ARRAY_11;//22
+	//unsigned char radio_config_data_11[1400] = RADIO_CONFIGURATION_DATA_ARRAY;//22
+	CONF_TDMA_frame_duration = 537000;
+	CONF_TDMA_slot_duration = 30250;
+	CONF_reduced_TDMA_slot_duration = 11700; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 1650; //1090
+	CONF_long_preamble_duration_for_TA = 2473;//2292
+	CONF_byte_duration = 80;
+	CONF_preamble_TX_long = 25;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 120;//8sec
+	CONF_radio_timeout = 60000000;
+	CONF_radio_timeout_small = 10000000;//10sec previously 20
+	CONF_signaling_period = 2;//4sec
+	return SI4463_configure_from_h (SI4463, radio_config_data_11);
+}
+
+int SI4463_configure_from_21(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_21[1250] = RADIO_CONFIGURATION_DATA_ARRAY_21;//22
+	//unsigned char radio_config_data_21[1400] = RADIO_CONFIGURATION_DATA_ARRAY;//22
+	CONF_TDMA_frame_duration = 294500;
+	CONF_TDMA_slot_duration = 16300;
+	CONF_reduced_TDMA_slot_duration = 7050; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 1550; //1090
+	CONF_long_preamble_duration_for_TA = 2370;//1420
+	CONF_byte_duration = 30;
+	CONF_preamble_TX_long = 25;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 90;//6 sec
+	CONF_radio_timeout = 60000000;
+	CONF_radio_timeout_small = 5000000;//5sec previously 10sec
+	CONF_signaling_period = 1;//2sec
+	return SI4463_configure_from_h (SI4463, radio_config_data_21);
+}
+
+int SI4463_configure_from_12(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_12[1250] = RADIO_CONFIGURATION_DATA_ARRAY_12;//22
+	CONF_TDMA_frame_duration = 312000;
+	CONF_TDMA_slot_duration = 17300;
+	CONF_reduced_TDMA_slot_duration = 7150; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 1030; //1090
+	CONF_long_preamble_duration_for_TA = 1765;//1420
+	CONF_byte_duration = 45;
+	CONF_preamble_TX_long = 32;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 100;//6sec
+	CONF_radio_timeout = 60000000;
+	CONF_radio_timeout_small = 5000000;//5sec previously 10sec
+	CONF_signaling_period = 1;//2sec
+	return SI4463_configure_from_h (SI4463, radio_config_data_12);
+}
+
+int SI4463_configure_from_22(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_22[1250] = RADIO_CONFIGURATION_DATA_ARRAY_22;//22
+	//unsigned char radio_config_data_22[1400] = RADIO_CONFIGURATION_DATA_ARRAY;
+	CONF_TDMA_frame_duration = 176000;
+	CONF_TDMA_slot_duration = 9480;
+	CONF_reduced_TDMA_slot_duration = 4330; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 890; //1090
+	CONF_long_preamble_duration_for_TA = 1708;//1420
+	CONF_byte_duration = 23;
+	CONF_preamble_TX_long = 32;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 60;//4 sec
+	CONF_radio_timeout = 40000000;
+	CONF_radio_timeout_small = 5000000;//5sec previously 10sec
+	CONF_signaling_period = 1;
+	return SI4463_configure_from_h (SI4463, radio_config_data_22);
+}
+
+int SI4463_configure_from_13(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_13[1250] = RADIO_CONFIGURATION_DATA_ARRAY_13;
+	CONF_TDMA_frame_duration = 197000;
+	CONF_TDMA_slot_duration = 10720;
+	CONF_reduced_TDMA_slot_duration = 4540; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 590; 
+	CONF_long_preamble_duration_for_TA = 1400;
+	CONF_byte_duration = 27;
+	CONF_preamble_TX_long = 42;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 60;//4 sec
+	CONF_radio_timeout = 40000000;
+	CONF_radio_timeout_small = 5000000;//5sec previously 10sec
+	CONF_signaling_period = 1;
+	return SI4463_configure_from_h (SI4463, radio_config_data_13);
+}
+
+int SI4463_configure_from_23(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_23[1250] = RADIO_CONFIGURATION_DATA_ARRAY_23;//23
+	//unsigned char radio_config_data_23[1500] = RADIO_CONFIGURATION_DATA_ARRAY;
+	CONF_TDMA_frame_duration = 117000;
+	CONF_TDMA_slot_duration = 6090;
+	CONF_reduced_TDMA_slot_duration = 3000; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 570;
+	CONF_long_preamble_duration_for_TA = 1365;	
+	CONF_byte_duration = 14;//13.3
+	CONF_preamble_TX_long = 42;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 30;//30!!!
+	CONF_radio_timeout = 30000000;
+	CONF_radio_timeout_small = 5000000;//5sec previously 10sec
+	CONF_signaling_period = 1;
+	return SI4463_configure_from_h (SI4463, radio_config_data_23);
+}
+
+int SI4463_configure_from_14(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_14[1250] = RADIO_CONFIGURATION_DATA_ARRAY_14;//14
+	CONF_TDMA_frame_duration = 130000;
+	CONF_TDMA_slot_duration = 6840;
+	CONF_reduced_TDMA_slot_duration = 3130; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 400; 
+	CONF_long_preamble_duration_for_TA = 1206; 
+	CONF_byte_duration = 16;
+	CONF_preamble_TX_long = 60;
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 30;
+	CONF_radio_timeout = 30000000;
+	CONF_radio_timeout_small = 5000000;//5sec previously 10sec
+	CONF_signaling_period = 1;
+	return SI4463_configure_from_h (SI4463, radio_config_data_14);
+}
+
+int SI4463_configure_from_24(SI4463_Chip* SI4463) {
+	unsigned char radio_config_data_24[1250] = RADIO_CONFIGURATION_DATA_ARRAY_24;//24
+	//unsigned char radio_config_data_24[1500] = RADIO_CONFIGURATION_DATA_ARRAY;//24
+	CONF_TDMA_frame_duration = 81300;//81300
+	CONF_TDMA_slot_duration = 4060;
+	CONF_reduced_TDMA_slot_duration = 2210; 
+	CONF_TDMA_slot_margin = 300;
+	CONF_TR_margain = 1300; 
+	CONF_TA_margain = 2000;
+	CONF_preamble_duration_for_decide = 390; 
+	CONF_long_preamble_duration_for_TA = 1188; 
+	CONF_byte_duration = 8;
+	CONF_preamble_TX_long = 60; 
+	CONF_preamble_TX_short = 16;
+	CONF_Tx_rframe_timeout = 30;
+	CONF_radio_timeout = 30000000;
+	CONF_radio_timeout_small = 5000000;//5sec previously 10sec
+	CONF_signaling_period = 1;
+	return SI4463_configure_from_h (SI4463, radio_config_data_24);
+}
+
+int SI4463_configure_from_h(SI4463_Chip* SI4463, unsigned char* radio_config_data) {
+	
+	int i=0;
+	int answer_loc;
+	int answer;
+	int current_command_length;
+	answer = 1;
+	do {
+		current_command_length = radio_config_data[i];
+		i++;
+		if (current_command_length>0) {
+			SI4463_send_command(SI4463, radio_config_data+i, current_command_length);
+			answer_loc = SI4463_CTS_read_answer(SI4463, SI_trash, 0, 30000);//15000 30000
+			if (answer_loc == 0) {answer = 0;}
+		}
+		
+
+		i = i + current_command_length;
+		//
+	} while ( (current_command_length > 0) && (answer == 1) );
+	wait_ms(5);
+	
+	// specific GLOBAL_CONFIG : SEQUENCER_MODE=GUARANTEED and FIFO_MODE=FIFO_129
+	unsigned char radio_config_bis[10] = {0x11, 0x00, 0x01, 0x03, 0x10}; 
+	SI4463_send_command(SI4463, radio_config_bis, 5);
+	answer_loc = SI4463_CTS_read_answer(SI4463, SI_trash, 0, 800);//200
+	if (answer_loc == 0) {answer = 0;}
+	wait_ms(5);//50
+	
+	// specific Max size field 2 
+	unsigned char radio_config_ter[10] = {0x11, 0x12, 0x02, 0x11, 0x00, 0xFF}; 
+	radio_config_ter[4] = (SI4463_CONF_max_field2_size & 0x1F00 )/ 0x100 ;
+	radio_config_ter[5] = SI4463_CONF_max_field2_size & 0x00FF;
+	SI4463_send_command(SI4463, radio_config_ter, 6);
+	answer_loc = SI4463_CTS_read_answer(SI4463, SI_trash, 0, 800);
+	if (answer_loc == 0) {answer = 0;}
+	wait_ms(5);//50
+	
+	//specific FIFO Threshold
+	unsigned char radio_config_quart[10] = {0x11, 0x12, 0x02, 0x0B, 0x30, 0x64}; 
+	radio_config_quart[4] = SI4463_CONF_TX_FIFO_threshold & 0x7F;// ajout 30 mai
+	radio_config_quart[5] = SI4463_CONF_RX_FIFO_threshold & 0x7F;
+	SI4463_send_command(SI4463, radio_config_quart, 6);
+	answer_loc = SI4463_CTS_read_answer(SI4463, SI_trash, 0, 800);
+	if (answer_loc == 0) {answer = 0;}
+	wait_ms(5);//50
+	
+	//specific SYNC WORD depending on 'radio network ID'
+	unsigned char hash_netID[20] = {0x33, 0x36, 0x39, 0x3c, 0x63, 0x66, 0x69, 0x6c, 0x93, 0x96, 0x99, 0x9c, 0xc3, 0xc6, 0xc9, 0xcc};
+	unsigned char radio_config_quint[12] = {0x11, 0x11, 0x01, 0x03, 0xCC}; 
+	radio_config_quint[4] = hash_netID[CONF_radio_network_ID];
+	SI4463_send_command(SI4463, radio_config_quint, 5);//10
+	answer_loc = SI4463_CTS_read_answer(SI4463, SI_trash, 0, 800);
+	answer_loc = 1;
+	if (answer_loc == 0) {answer = 0;}
+	wait_ms(5);//5
+	
+	//specific power 
+	unsigned char radio_config_sixt[10] = {0x11, 0x22, 0x01, 0x01, 0x7F}; 
+	radio_config_sixt[4] = CONF_radio_PA_PWR & 0x7F;
+	SI4463_send_command(SI4463, radio_config_sixt, 5);
+	answer_loc = SI4463_CTS_read_answer(SI4463, SI_trash, 0, 800);
+	if (answer_loc == 0) {answer = 0;}
+	wait_ms(5);//5
+	
+	return answer;
+}
+
+int SI4463_set_power(SI4463_Chip* SI4463) {
+	int answer, answer_loc;
+	unsigned char radio_config_sixt[10] = {0x11, 0x22, 0x01, 0x01, 0x7F}; 
+	radio_config_sixt[4] = CONF_radio_PA_PWR & 0x7F;
+	SI4463_send_command(SI4463, radio_config_sixt, 5);
+	answer_loc = SI4463_CTS_read_answer(SI4463, SI_trash, 0, 200);
+	if (answer_loc == 0) {answer = 0;}
+	wait_ms(5);
+	return answer;
+}
+
+void SI4463_print_version(SI4463_Chip* SI4463) {
+	int i;
+	unsigned char command [10];
+	unsigned char answer [12];
+	command[0] = 0x01;//part info
+	SI4463_send_command(SI4463, command, 1);
+	SI4463_CTS_read_answer(SI4463, answer, 8, 200);
+	HMI_printf("part info: ");
+	for (i=0; i<8; i++) {
+		HMI_printf("%02X ",answer[i]);
+	}
+	printf("\r\n");
+	
+	command[0] = 0x10;//function info
+	SI4463_send_command(SI4463, command, 1);
+	SI4463_CTS_read_answer(SI4463, answer, 8, 200);
+	HMI_printf("function info: ");
+	for (i=0; i<6; i++) {
+		HMI_printf("%02X ",answer[i]);
+	}
+	printf("\r\n");
+}
+
+void SI4463_FIFO_status(SI4463_Chip* SI4463, int* RX_FIFO_count, int* TX_FIFO_count, int reset) {
+	unsigned char command[10];
+	unsigned char answer[10];
+	command[0] = 0x15;
+	if (reset == 1) {
+		command[1] = 0x03;
+	} else {
+		command[1] = 0x00;
+	}
+	SI4463_send_command (SI4463, command, 2);
+	SI4463_CTS_read_answer (SI4463, answer, 2, 5);
+	*RX_FIFO_count = answer[0];
+	*TX_FIFO_count = answer[1];
+}
+
+// a supprimer
+void SI4463_FIFO_write(SI4463_Chip* SI4463, unsigned char* data, int size) {
+	static unsigned char trash [200];
+	unsigned char command[6];
+	command[0] = 0x66;
+	SI4463->cs->write(0);
+	SI4463->spi->transfer_2 (command, 1, trash, 1);
+	SI4463->spi->transfer_2 (data, size, trash, size);
+	SI4463->cs->write(1);
+	wait_us(1);
+}
+
+void SI4463_FIFO_read (SI4463_Chip* SI4463, unsigned char* data, int size) {
+	unsigned char trash [200]; //static
+	unsigned char command[6];
+	command[0] = 0x77;
+	SI4463->cs->write(0);
+	SI4463->spi->transfer_2 (command, 1, trash, 1);
+	SI4463->spi->transfer_2 (trash, size, data, size);
+	SI4463->cs->write(1);
+	wait_us(1);
+}
+//fin a supprimer
+
+void SI4463_change_state (SI4463_Chip* SI4463, unsigned char new_state) {
+	unsigned char command[6];
+	command[0] = 0x34;
+	command[1] = new_state;
+	SI4463_send_command(SI4463, command, 2);
+	SI4463_CTS_read_answer (SI4463, command, 0, 30);
+}
+
+void SI4463_start_RX (SI4463_Chip* SI4463, unsigned char channel) {
+	static unsigned char command[12] = {0x32, 0, 0, 0, 0, 0x08, 0x08, 0x08};
+	command[1] = channel;
+	SI4463_send_command(SI4463, command, 8);
+	SI4463_CTS_read_answer (SI4463, command, 0, 55);
+}
+
+void SI4463_start_TX (SI4463_Chip* SI4463, unsigned char channel, unsigned int size) {
+	static unsigned char command[12] = {0x31, 0, 0x50, 0, 0, 0, 0};
+	
+	command[1] = channel; 
+	command[3] = (size & 0x1F00) >> 8;
+	command[4] = size & 0xFF;
+	SI4463_send_command(SI4463, command, 8);
+}
+
+void SI4463_read_FRR(SI4463_Chip* SI4463, unsigned char* data) {
+	unsigned char command[8];
+	unsigned char loc_answer[8];
+	int i;
+	command[0] = 0x50;
+	SI4463->cs->write(0);
+	SI4463->spi->transfer_2(command, 5, loc_answer, 5);
+	SI4463->cs->write(1);
+	wait_us(1);
+	for (i=0; i<4; i++) {
+		data[i] = loc_answer[i+1];
+	}
+}
+
+int SI4463_get_state(SI4463_Chip* SI4463) {
+	unsigned char command[8];
+	unsigned char loc_answer[8];
+	command[0] = 0x33;
+	SI4463_send_command(SI4463, command, 1);
+	SI4463_CTS_read_answer (SI4463, loc_answer, 2, 55);//!!! previous 5 / 2020_02_22
+	return loc_answer[0];
+}
+
+void SI4463_clear_IT(SI4463_Chip* SI4463, unsigned char PH_clear, unsigned char modem_clear) {
+	unsigned char command[8];
+	//unsigned char loc_answer[8];
+	
+	command[0] = 0x20; // GET_INT
+	//command[1] = 0x00;
+	command[1] = PH_clear;
+	command[2] = modem_clear;
+	command[3] = 0x00;
+	
+	SI4463_send_command(SI4463, command, 4);
+	//wait_us(20);
+	//SI4463_CTS_read_answer (SI4463, loc_answer, 2, 5);
+	//return loc_answer[0];
+}
+
+void SI4463_set_TX_preamble_length (SI4463_Chip* SI4463, unsigned char preamble_length_val) {
+	unsigned char trash [10];
+	unsigned char command_preamble_length[10] = {0x11, 0x10, 0x01, 0x00, 0x20};
+
+	command_preamble_length [4] = preamble_length_val;
+	SI4463_send_command(G_SI4463, command_preamble_length, 5); 
+	wait_us(20); // !!!
+	SI4463_CTS_read_answer(G_SI4463, trash, 0, 20); 
+}
+
+int SI4463_read_temperature(SI4463_Chip* SI4463) {
+	int temperature; 
+	unsigned char answer_loc [10];
+	unsigned char command_temp_read[10] = {0x14, 0x10, 0xA0};
+	SI4463_send_command(SI4463, command_temp_read, 3);
+	//wait_ms(2);
+	wait_us(20);
+	if (SI4463_CTS_read_answer(SI4463, answer_loc, 6, 2000) ) {
+		temperature = answer_loc[4] * 256 + answer_loc[5];
+		temperature = temperature * 0.2195 - 293;
+	} else {
+		temperature = 0xFFFF;
+	}
+	return temperature;
+}
+
+static int previous_temperature = 300;
+
+void SI4463_periodic_temperature_check(SI4463_Chip* SI4463) {
+	int need_recalibrate;
+	int delta_temperature;
+	int i;
+	
+	//RADIO_off_if_necessary(0);
+	G_temperature_SI4463 = SI4463_read_temperature (SI4463);
+	if (previous_temperature == 300) {
+		previous_temperature = G_temperature_SI4463;
+	}
+	delta_temperature = G_temperature_SI4463 - previous_temperature;
+	if ( ( delta_temperature > 14) || (delta_temperature < -14) ) {
+	//if (1) {
+		need_recalibrate = 1;
+		i = SI4463_configure_all();
+		previous_temperature = G_temperature_SI4463;
+		if (i == 0) {//fail to recalibrate
+			NVIC_SystemReset();
+		}
+	} else {
+		need_recalibrate = 0;
+	}
+	//RADIO_restart_if_necessary(0, need_recalibrate, 0); //0,need,0
+}
+
+static unsigned int RX_size_remaining = 0;
+
+void SI4463_periodic_temperature_check_2(void) {
+	unsigned long int timer_snapshot;
+	int delta_temperature;
+	int i;
+	unsigned char trash [10];
+	timer_snapshot = GLOBAL_timer.read_us();
+	if ( (is_TDMA_master) && (CONF_master_FDD == 2) && (CONF_radio_state_ON_OFF) ) {
+		SI4463_prepa_TX_1_call.attach_us(&SI4463_prepa_TX_1, 500000);//simulates TX transition
+	}
+	else if ( (is_TDMA_master) && (CONF_radio_state_ON_OFF) && ((timer_snapshot-last_rframe_seen) > (CONF_radio_timeout+1000000) ) ) {
+		//if (G_need_temperature_check == 1) {
+			G_need_temperature_check = 0;
+			if (previous_temperature == 300) {
+				previous_temperature = G_temperature_SI4463;
+			}
+			G_temperature_SI4463 = SI4463_read_temperature (G_SI4463);
+			delta_temperature = G_temperature_SI4463 - previous_temperature;
+			if ( ( delta_temperature > 14) || (delta_temperature < -14) ) {
+				previous_temperature = G_temperature_SI4463;
+				G_SI4463->RX_TX_state = 0;
+				//SI4463_change_state(G_SI4463, 0x03); //switch to ready
+				RX_FIFO_WR_point = RX_FIFO_last_received; // rewind WR_pointer to last complete packet
+				//SI4463_FIFO_status(G_SI4463, &toto, &toto, 1); //reset FIFO
+				//SI4463_clear_IT (G_SI4463, 0, 0);
+				i = SI4463_configure_all();
+				if (i == 0) {//fail to recalibrate
+					NVIC_SystemReset();
+				}
+				//SI4463_start_RX(G_SI4463, CONF_radio_frequency);
+				SI4463_start_RX(G_SI4463, CONF_channel_RX);
+				SI4463_clear_IT (G_SI4463, 0, 0);
+				SI4463_CTS_read_answer (G_SI4463, trash, 2, 5);// ADDED 2018 08 25
+				RX_size_remaining = 0;
+				G_SI4463->RX_TX_state = 1; // activate RX HW IRQ
+			}
+		//}
+	}
+}
+
+//void SI4463_temp_check_init(void) {
+//	SI4463_temp_check2_call.attach(&SI4463_periodic_temperature_check_2, 10);//periodic 10 seconds
+//}
+
+void SI4463_FIFO_RX_transfer(unsigned int size) {
+	//unsigned char trash[150]; //static
+
+	int size_to_read;
+
+	if ( ( (RX_FIFO_WR_point & RX_FIFO_mask) +  size) > RX_FIFO_mask) { // to big for 1 step
+		size_to_read = (RX_FIFO_mask + 1 - (RX_FIFO_WR_point & RX_FIFO_mask) );
+		G_SI4463->spi->transfer_2 (SI_trash, size_to_read, RX_FIFO_data + (RX_FIFO_WR_point & RX_FIFO_mask), size_to_read);
+		RX_FIFO_WR_point = RX_FIFO_WR_point + size_to_read; // should become ZERO
+		//second step
+		size_to_read = size - size_to_read; 
+		G_SI4463->spi->transfer_2 (SI_trash, size_to_read, RX_FIFO_data + (RX_FIFO_WR_point & RX_FIFO_mask), size_to_read);
+		RX_FIFO_WR_point = RX_FIFO_WR_point + size_to_read;
+	} else { //1 step is enough
+	
+		G_SI4463->spi->transfer_2 (SI_trash, size, RX_FIFO_data + (RX_FIFO_WR_point & RX_FIFO_mask), size);
+		RX_FIFO_WR_point = RX_FIFO_WR_point + size;
+	}
+
+}
+
+void SI4463_FIFO_TX_transfer(unsigned int size) {
+	//unsigned char trash[150]; //static
+	unsigned char command[5];
+	//int size_to_write;
+	G_SI4463->cs->write(0);
+	command[0] = 0x66;
+	G_SI4463->spi->transfer_2 (command, 1, SI_trash, 1);
+	G_SI4463->spi->transfer_2 (TX_frame_to_send, size, SI_trash, size);
+	TX_frame_to_send = TX_frame_to_send + size;
+	G_SI4463->cs->write(1);
+}
+
+void SI4463_RX_HOP(void) {
+	//G_SI4463->RX_LED->write(1);
+	SI4463_send_command(G_SI4463, CONF_SI4463_freq_conf_RX, 7);
+	wait_us(20);
+	SI4463_CTS_read_answer (G_SI4463, SI_trash, 0, 50);
+	wait_us(20);
+	//G_SI4463->RX_LED->write(0);
+}
+
+void SI4463_TX_HOP(void) {
+	//G_SI4463->RX_LED->write(1);
+	SI4463_send_command(G_SI4463, CONF_SI4463_freq_conf_TX, 9);
+	wait_us(20);
+	SI4463_CTS_read_answer (G_SI4463, SI_trash, 0, 50);
+	wait_us(20);
+	//G_SI4463->RX_LED->write(0);
+}
+
+// High level functions
+
+//static unsigned int RX_size_remaining = 0;
+static unsigned int time_STOP_TX_burst;
+
+void SI4463_RX_IT() {
+	static unsigned char RX_small[10];
+	static unsigned char TX_small[10];
+	
+	static unsigned char FRR[5];
+	static unsigned int RX_timer;
+	static unsigned char RSSI;
+	int IT_SYNC_detected;
+	int IT_FIFO_almost_full;
+	int IT_pckt_RX;
+	//What has been treated
+	int Treated_SYNC_detected;
+	int Treated_FIFO_almost_full;
+	int Treated_pckt_RX;
+	// synthesis
+	int Synth_SYNC_detected;
+	int Synth_FIFO_almost_full;
+	int Synth_pckt_RX;
+	
+	unsigned int size_to_read; 
+	int IT_state;
+	int toto;
+	unsigned int timer_snapshot;
+	int t_rehabilit_interrupt;
+	unsigned char clear_IT_PH;
+	unsigned char clear_IT_modem;
+	
+	Treated_SYNC_detected = 0;
+	Treated_FIFO_almost_full = 0;
+	Treated_pckt_RX = 0;
+	
+	timer_snapshot = GLOBAL_timer.read_us();
+	wait_us(10);//for RSSI propagation (measure at sync detect)
+	do {
+		SI4463_read_FRR (G_SI4463, FRR);
+		IT_SYNC_detected = FRR[1] & 0x01;
+		IT_FIFO_almost_full = FRR[0] & 0x01;
+		IT_pckt_RX = (FRR[0] & 0x10) / 0x10; 
+		Synth_SYNC_detected = IT_SYNC_detected ^ Treated_SYNC_detected; //Xor
+		Synth_FIFO_almost_full = IT_FIFO_almost_full ^ Treated_FIFO_almost_full;
+		Synth_pckt_RX = IT_pckt_RX ^ Treated_pckt_RX;
+		
+		toto = *(G_SI4463->interrupt);
+		if (Synth_SYNC_detected) {//Sync detected
+			RSSI = FRR[2];
+			RX_timer = timer_snapshot - CONF_long_preamble_duration_for_TA;
+			if ( (is_TDMA_master == 1) && (CONF_master_FDD == 2) ) {//Master UP
+				RX_timer = RX_timer - TDMA_slave_last_master_top;
+			}
+			Treated_SYNC_detected = 1;
+			RSSI_total_stat = RSSI_total_stat + RSSI;
+			RSSI_stat_pkt_nb++;
+			G_SI4463->RX_LED->write(1);
+		}
+		
+		if (Synth_FIFO_almost_full || Synth_pckt_RX) { //FIFO full or RX complete
+			if ( (RX_size_remaining == 0) && (Treated_FIFO_almost_full == 0) && (Treated_pckt_RX == 0) ) { //beginning of new packet
+				// read first byte of packet : size
+				TX_small[0] = 0x77;
+				TX_small[1] = toto;
+				G_SI4463->cs->write(0);
+				G_SI4463->spi->transfer_2 (TX_small, 2, RX_small, 2);
+				RX_size_remaining = RX_small[1] + SI4463_offset_size;
+				if (RX_size_remaining > SI4463_CONF_max_field2_size ) {
+					RX_size_remaining = SI4463_CONF_max_field2_size;
+				}
+				if (RX_size_remaining > (SI4463_CONF_RX_FIFO_threshold - 1)) { //too big //+10
+					size_to_read = SI4463_CONF_RX_FIFO_threshold - 1; //+10
+				} else {
+					size_to_read = RX_size_remaining;
+				}
+				if (Synth_pckt_RX) { // force to read all remaining if full packet received
+					size_to_read = RX_size_remaining;
+					G_SI4463->RX_LED->write(0);
+				}
+
+				RX_FIFO_data[RX_FIFO_WR_point & RX_FIFO_mask] = RX_timer & 0xFF; //LSB
+				RX_FIFO_WR_point++;
+				RX_FIFO_data[RX_FIFO_WR_point & RX_FIFO_mask] = (RX_timer & 0xFF00) / 0x100;
+				RX_FIFO_WR_point++;
+				RX_FIFO_data[RX_FIFO_WR_point & RX_FIFO_mask] = (RX_timer & 0xFF0000) / 0x10000; //MSB
+				RX_FIFO_WR_point++;
+				RX_FIFO_data[RX_FIFO_WR_point & RX_FIFO_mask] = RSSI; //RSSI
+				RX_FIFO_WR_point++;
+				RX_FIFO_data[RX_FIFO_WR_point & RX_FIFO_mask] = RX_small[1]; //Size. Warning, with negative offset
+				RX_FIFO_WR_point++;
+				//read remaining
+				SI4463_FIFO_RX_transfer(size_to_read);
+				G_SI4463->cs->write(1);
+				wait_us(1);
+				RX_size_remaining = RX_size_remaining - size_to_read; 
+			} 
+			else { // middle or end of a packet
+				if (RX_size_remaining > SI4463_CONF_RX_FIFO_threshold ) { //too big  //+10 
+					size_to_read = SI4463_CONF_RX_FIFO_threshold ;//+10
+				} else {
+					size_to_read = RX_size_remaining;
+				}
+				if (Synth_pckt_RX) { // force to read all remaining if full packet received
+					size_to_read = RX_size_remaining;
+					G_SI4463->RX_LED->write(0); 
+				}
+				if (RX_size_remaining > 0) { //avoid useless FIFO reading
+					TX_small[0] = 0x77;
+					G_SI4463->cs->write(0);
+					G_SI4463->spi->transfer_2 (TX_small, 1, RX_small, 1);
+					SI4463_FIFO_RX_transfer(size_to_read);
+					G_SI4463->cs->write(1);
+					wait_us(1);
+					RX_size_remaining = RX_size_remaining - size_to_read; 
+				}
+			}
+			if (RX_size_remaining == 0) { //packet is full, 
+				RX_FIFO_last_received = RX_FIFO_WR_point;
+			}
+			Treated_FIFO_almost_full = IT_FIFO_almost_full;
+			Treated_pckt_RX = IT_pckt_RX;
+		}
+		clear_IT_PH = ~(Treated_FIFO_almost_full * 0x01 + Treated_pckt_RX * 0x10);
+		clear_IT_modem = ~(Treated_SYNC_detected * 0x01);
+		SI4463_clear_IT(G_SI4463, clear_IT_PH, clear_IT_modem);
+		// checks if new IT has triggered in the meantime
+		if (IT_SYNC_detected) { //removed 2019_06_16
+			IT_state = 1; // impossible to have immediate new IT
+		} else {
+			t_rehabilit_interrupt = 0;
+			IT_state = G_SI4463->interrupt->read(); 
+			while ( (t_rehabilit_interrupt<18) && (IT_state == 0) ) {
+				wait_us(1);
+				IT_state = G_SI4463->interrupt->read(); 
+				t_rehabilit_interrupt++;
+			}
+		}
+	} while (IT_state == 0);
+	
+}
+
+//static int already_inside_IT = 0;
+
+static int TX_slot_frame_counter=0;
+static int radio_lock_TX_pending = 0;
+
+void SI4463_prepa_TX_1(void) {
+	unsigned long int timer_snapshot;
+	G_SI4463->RX_LED->write(0); 
+	G_PTT_PA_pin->write(1);
+	timer_snapshot = GLOBAL_timer.read_us() + 50000;
+	//if ( (CONF_radio_state_ON_OFF) && (radio_lock_TX_pending == 0) ) {
+	if ( (CONF_radio_state_ON_OFF) ) {
+		radio_lock_TX_pending = 1;
+		G_SI4463->RX_TX_state = 0; //temporary inhibit actions from HW IRQ
+		
+		if ( (is_TDMA_master) && (CONF_master_FDD<2) && (CONF_radio_state_ON_OFF) && (((timer_snapshot-last_rframe_seen)&0x7FFFFFFF) < CONF_radio_timeout) ) {
+		//if ( (is_TDMA_master) && (CONF_radio_state_ON_OFF) ) {
+			SI4463_prepa_TX_1_call.attach_us(&SI4463_prepa_TX_1, CONF_TDMA_frame_duration);//master_TDMA_period
+			//TDMA_top_measure();
+		}
+		SI4463_prepa_TX_2_call.attach_us(&SI4463_prepa_TX_2, 350); //300
+		if (is_TDMA_master) {
+			TDMA_master_allocation();
+		}
+	}
+}
+
+void SI4463_prepa_TX_2(void) {
+	int toto;
+	unsigned int loc_time;
+	unsigned int loc_time_offset;
+	unsigned char trash [10];
+
+	if (CONF_radio_state_ON_OFF) {
+		loc_time = GLOBAL_timer.read_us();
+		if (is_TDMA_master) {
+			loc_time_offset = 530; // 530
+		} else {
+			// //loc_time_offset = (time_next_TX_slave-loc_time) & 0xFFFFFF;
+			loc_time_offset = 530; // 530
+		}
+		time_STOP_TX_burst = (loc_time + loc_time_offset + time_max_TX_burst);// & 0xFFFFFF; 
+		SI4463_1st_TX_call.attach_us(&SI4463_decide_new_TX_or_not, loc_time_offset); 
+		
+		SI4463_change_state(G_SI4463, 0x05); //switch to TX_TUNE (with CTS)
+		RX_FIFO_WR_point = RX_FIFO_last_received; // rewind WR_pointer to last complete packet
+		SI4463_FIFO_status(G_SI4463, &toto, &toto, 1); //reset FIFO (including CTS)
+		TX_slot_frame_counter = 0;
+		SI4463_clear_IT (G_SI4463, 0, 0);//without CTS
+		G_SI4463->RX_TX_state = 2; // activate TX HW IRQ
+		wait_us(20); 
+		SI4463_CTS_read_answer(G_SI4463, trash, 0, 20);
+		SI4463_set_TX_preamble_length(G_SI4463, CONF_preamble_TX_long); 
+	}
+	
+}
+
+void SI4463_TX_to_RX_transition(void) {
+	int toto;
+	unsigned char trash[10];
+	
+	SI4463_FIFO_status(G_SI4463, &toto, &toto, 1); //reset FIFO
+	G_SI4463->RX_TX_state = 0; // temporarly inhibit IRQ
+	radio_lock_TX_pending = 0;
+	
+	if (G_need_temperature_check==1) {
+		SI4463_periodic_temperature_check(G_SI4463);//added 2019_05_31
+		G_need_temperature_check = 0;
+	}
+	SI4463_start_RX(G_SI4463, CONF_channel_RX); // with CTS
+	SI4463_RX_HOP();// with CTS
+	SI4463_clear_IT (G_SI4463, 0, 0);
+	SI4463_CTS_read_answer (G_SI4463, trash, 2, 5);// ADDED 2018 08 25
+	RX_size_remaining = 0;
+	G_PTT_PA_pin->write(0);
+	G_SI4463->RX_TX_state = 1; // activate RX HW IRQ
+	if ( (is_TDMA_master == 0) && (CONF_radio_modulation == 24) ) {
+		SI4463_RX_timeout_call.attach_us(&SI4463_RX_timeout, 10*CONF_TDMA_frame_duration);
+	}
+	TX_in_progress = 0;
+}
+
+void SI4463_RX_timeout (void) {
+	unsigned int timer_snapshot;
+	timer_snapshot = GLOBAL_timer.read_us();
+	if ( (timer_snapshot - last_rframe_seen) > 9*CONF_TDMA_frame_duration) {
+		SI4463_prepa_TX_1();
+		last_rframe_seen = timer_snapshot;
+	}
+}
+
+void Radio_purge_old_frames (void) { 
+	int force_loop_exit = 0;
+	unsigned int loc_size;
+	unsigned char RX_frame_datation;
+	unsigned char loc_time_char;
+	unsigned int loc_time_int;
+	loc_time_int = GLOBAL_timer.read_us();
+	loc_time_char = (loc_time_int >> 16) & 0xFF; 
+	while (force_loop_exit == 0) {
+		if (TX_buff_intern_RD_pointer < TX_buff_intern_last_ready) {//data available in FIFO
+			RX_frame_datation = TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128][0];
+
+			if ( (loc_time_char - RX_frame_datation) > CONF_Tx_rframe_timeout) {//CONF_Tx_rframe_timeout
+				loc_size = TX_buff_intern_FIFOdata[TX_buff_intern_RD_pointer % 128][1];
+				loc_size = loc_size + 2 + SI4463_offset_size;
+				//+2 because timer byte and size byte
+				if (loc_size <= 128) {
+					TX_buff_intern_RD_pointer = TX_buff_intern_RD_pointer + 1;
+				} else if (loc_size <= 256) {
+					TX_buff_intern_RD_pointer = TX_buff_intern_RD_pointer + 2;
+				} else {
+					TX_buff_intern_RD_pointer = TX_buff_intern_RD_pointer + 3;
+				}
+				//printf("purged!\r\n");
+				//printf("date1 %i date2 %i\r\n", loc_time_char, RX_frame_datation); 
+			}
+			else { //packet is recent
+				force_loop_exit = 1;
+			}
+		} 
+		else { //no data available in FIFO
+			force_loop_exit = 1;
+		}
+	}
+}
+
+int TX_test_mode = 0;
+
+
+void SI4463_decide_new_TX_or_not (void) { //decides if new frame must be transmitted, and which frame
+	unsigned int loc_size;
+	unsigned int loc_time;
+	unsigned char TDMA_sync;
+	int delta_end_burst; // >0 not enough time
+
+	int OK_send_PS;
+	int PS_data_available;
+	slave_new_burst_tx_pending = 0;
+	OK_send_PS = 0;
+	PS_data_available = 0;
+	Radio_purge_old_frames();
+	if (TX_buff_intern_RD_pointer < TX_buff_intern_last_ready) {//data available in TXPS
+		PS_data_available = 1;
+		loc_size = TX_intern_FIFO_get_lastfrzize();
+	} else {
+		loc_size = 120; 
+	}
+		
+	loc_time = GLOBAL_timer.read_us();
+	delta_end_burst = loc_time + (loc_size * CONF_byte_duration) + CONF_preamble_duration_for_decide - time_STOP_TX_burst - 50; 
+	if (TX_slot_frame_counter == 0) {
+		delta_end_burst = delta_end_burst + CONF_additional_preamble;
+	}
+	
+	//printf("%i\r\n", delta_end_burst);
+	if (delta_end_burst < 0) { 
+		OK_send_PS = 1;
+	} 
+	
+	if (TX_slot_frame_counter == 0) {
+		TDMA_sync = 1;
+	} else {
+		TDMA_sync = 0;
+	}
+	
+	if (CONF_radio_state_ON_OFF==0) {//radio off check for TX test
+		if (TX_test_inprogress == 1) {
+			TX_frame_to_send = TX_TDMA_intern_data;
+			SI4463_TX_new_frame(TDMA_sync); 
+		} else {
+			SI4463_TX_to_RX_transition();
+		}
+	} 
+	else { //normal operation
+		if (is_TDMA_master) {
+			if (CONF_master_FDD==2) {
+				SI4463_TX_to_RX_transition();//Master FDD up, go immediately to RX
+			}
+			else if (TX_slot_frame_counter == 0) { // systematically send TDMA signaling frame
+				TX_frame_to_send = TX_TDMA_intern_data;
+				TDMA_top_measure();
+				//G_PTT_PA_pin->write(1);
+				if (CONF_master_FDD == 1) {//Master FDD downlink
+					G_FDD_trig_pin->write(1);
+				}
+				SI4463_TX_new_frame(TDMA_sync); 
+				SI4463_set_TX_preamble_length(G_SI4463, CONF_preamble_TX_short);
+				TX_slot_frame_counter++;
+			} 
+			else if (PS_data_available && OK_send_PS) {
+				TX_intern_FIFO_read (TX_temp_rframe);
+				TX_frame_to_send = TX_temp_rframe;
+				SI4463_TX_new_frame(TDMA_sync); 
+				TX_slot_frame_counter++;
+			}
+			else {
+				TX_slot_frame_counter = 0;
+				//G_PTT_PA_pin->write(0);
+				if (CONF_master_FDD == 1) {//Master FDD downlink
+					G_FDD_trig_pin->write(0);
+				}
+				SI4463_TX_to_RX_transition();
+			}
+			
+		} else { // SLAVE
+			if ( (PS_data_available==0) && (TX_slot_frame_counter==0) && (my_client_radio_connexion_state==2) ) {//send a null frame
+				TX_frame_to_send = TX_TDMA_intern_data;
+				SI4463_TX_new_frame(TDMA_sync); 
+				if (TX_slot_frame_counter == 0) {
+					SI4463_set_TX_preamble_length(G_SI4463, CONF_preamble_TX_short);
+				}
+				TX_slot_frame_counter++;
+			} 
+			else if ( (PS_data_available) && (OK_send_PS) ) {
+				TX_intern_FIFO_read (TX_temp_rframe);
+				TX_frame_to_send = TX_temp_rframe;
+				SI4463_TX_new_frame(TDMA_sync); 
+				if (TX_slot_frame_counter == 0) {
+					SI4463_set_TX_preamble_length(G_SI4463, CONF_preamble_TX_short);
+				}
+				TX_slot_frame_counter++;
+			} 
+			else {
+				TX_slot_frame_counter = 0;
+				SI4463_TX_to_RX_transition();
+			}
+		}
+	}
+}
+
+
+static unsigned int TX_size_remaining = 0;
+
+void SI4463_TX_new_frame(unsigned char synchro) {
+	//unsigned char timer_coarse;
+	unsigned int full_packet_size;
+	unsigned int size_to_send;
+	unsigned char trash[10];
+
+	TX_in_progress = 1; 
+	//prefill TX FIFO with small amount of data	
+	TX_frame_to_send++; //1st byte ignored timer coarse
+	TX_size_remaining = TX_frame_to_send[0] + 1 + SI4463_offset_size;
+	full_packet_size = TX_size_remaining; 
+		
+	TX_frame_to_send[1] = TDMA_byte_elaboration(synchro);
+	SI4463_FIFO_TX_transfer(30);
+	TX_size_remaining = TX_size_remaining - 30;
+	
+	//start TX order
+	SI4463_start_TX (G_SI4463, CONF_channel_TX, full_packet_size);
+
+	//FIFO transfer
+	if (TX_size_remaining < 95) { //sent in 1 pass //95 
+		size_to_send = TX_size_remaining;
+	} else {
+		size_to_send = 95; //95 
+	}
+	SI4463_FIFO_TX_transfer(size_to_send);
+	
+	//CTS
+	SI4463_CTS_read_answer (G_SI4463, trash, 0, 55);//TEST previously 5
+	TX_size_remaining = TX_size_remaining - size_to_send;
+}
+
+void SI4463_HW_TX_IT() {
+	static unsigned char FRR[5];
+	int size_to_write;
+	
+	int IT_FIFO_almost_empty;
+	int IT_pckt_sent;
+	int Treated_FIFO_almost_empty;
+	int Treated_pckt_sent;
+	int Synth_FIFO_almost_empty;
+	int Synth_pckt_sent;
+	int IT_state;
+	int t_rehabilit_interrupt;
+	unsigned char clear_IT_PH;
+	
+	Treated_FIFO_almost_empty = 0;
+	Treated_pckt_sent = 0;
+	
+	do {
+		SI4463_read_FRR (G_SI4463, FRR);
+		IT_FIFO_almost_empty = (FRR[0] & 0x02 ) /0x02;
+		IT_pckt_sent = (FRR[0] & 0x20 ) /0x20;
+	
+		Synth_FIFO_almost_empty = IT_FIFO_almost_empty ^ Treated_FIFO_almost_empty;
+		Synth_pckt_sent = IT_pckt_sent ^ Treated_pckt_sent;
+		
+		if (Synth_pckt_sent) {  
+			TX_in_progress = 0;
+			SI4463_decide_new_TX_or_not();
+			Treated_pckt_sent = 1;
+			Treated_FIFO_almost_empty = IT_FIFO_almost_empty; // trick 
+		} 
+		Synth_FIFO_almost_empty = IT_FIFO_almost_empty ^ Treated_FIFO_almost_empty;
+		if (Synth_FIFO_almost_empty) {
+			// FIFO almost empty
+			if (TX_size_remaining > 0) {//more data to send on this packet
+				if (TX_size_remaining > SI4463_CONF_TX_FIFO_threshold) {//not enough space in FIFO for full packet
+					size_to_write = SI4463_CONF_TX_FIFO_threshold;
+				} else {
+					size_to_write = TX_size_remaining;
+				}
+				SI4463_FIFO_TX_transfer (size_to_write);
+				TX_size_remaining = TX_size_remaining - size_to_write;
+			}
+			Treated_FIFO_almost_empty = 1; //even if nothing more to send
+		}
+		
+		clear_IT_PH = ~(Treated_FIFO_almost_empty * 0x02 + Treated_pckt_sent * 0x20);
+		SI4463_clear_IT(G_SI4463, clear_IT_PH, 0x00);
+		//wait_us(25);
+		t_rehabilit_interrupt = 0;
+		IT_state = G_SI4463->interrupt->read(); 
+		while ( (t_rehabilit_interrupt<25) && (IT_state == 0) ) {
+			wait_us(1);
+			IT_state = G_SI4463->interrupt->read(); 
+			t_rehabilit_interrupt++;
+		}
+	} while (IT_state == 0);
+
+}
+
+void SI4463_HW_interrupt() {
+	if ( (G_SI4463->RX_TX_state == 1) && (CONF_radio_state_ON_OFF) ) { //Receive
+		SI4463_RX_IT();
+	}
+	if (G_SI4463->RX_TX_state == 2) { //transmit
+		SI4463_HW_TX_IT();
+	}
+}
+
+int SI4463_configure_all(void) {
+	int answer_loc = 0;
+	int i = 0;
+	G_SI4463->SDN->write(0);
+	wait_ms(10);//100
+	G_SI4463->SDN->write(1);
+	wait_ms(500);//100 20
+	G_SI4463->SDN->write(0);
+	wait_ms(200);//500 20
+	while ( (answer_loc == 0) && (i < 5) ) {
+		i++; 
+		//if (CONF_radio_modulation == 10) {
+		//	answer_loc = SI4463_configure_from_10(G_SI4463);
+		//}
+		if (CONF_radio_modulation == 20) {
+			answer_loc = SI4463_configure_from_20(G_SI4463);
+		}
+		if (CONF_radio_modulation == 11) {
+			answer_loc = SI4463_configure_from_11(G_SI4463);
+		}
+		if (CONF_radio_modulation == 21) {
+			answer_loc = SI4463_configure_from_21(G_SI4463);
+		}
+		if (CONF_radio_modulation == 12) {
+			answer_loc = SI4463_configure_from_12(G_SI4463);
+		}
+		
+		if (CONF_radio_modulation == 22) {
+			answer_loc = SI4463_configure_from_22(G_SI4463);
+		}
+		if (CONF_radio_modulation == 13) {
+			answer_loc = SI4463_configure_from_13(G_SI4463);
+		}
+		if (CONF_radio_modulation == 23) {
+			answer_loc = SI4463_configure_from_23(G_SI4463);
+		}
+		if (CONF_radio_modulation == 14) {
+			answer_loc = SI4463_configure_from_14(G_SI4463);
+		}
+		if (CONF_radio_modulation == 24) {
+			answer_loc = SI4463_configure_from_24(G_SI4463);
+		}
+		RADIO_compute_freq_params();
+	}
+	return answer_loc;
+}
+
+void SI4463_radio_start(void) {
+	if (CONF_radio_state_ON_OFF == 0) {
+		//SI4463_change_state(G_SI4463, 0x03);//change state to ready
+		wait_ms(1);
+		G_SI4463->RX_TX_state = 0;
+		SI4463_clear_IT(G_SI4463, 0, 0);
+		//wait_ms(10);
+		SI4463_CTS_read_answer (G_SI4463, SI_trash, 0, 600);
+		CONF_radio_state_ON_OFF = 1;
+		if ( (is_TDMA_master) && (CONF_master_FDD < 2) ) {
+			SI4463_prepa_TX_1();
+		} else {
+			SI4463_TX_to_RX_transition();
+		}
+		//TDMA_init_all();
+	}
+}
+
+void RADIO_on(int need_disconnect, int need_radio_reconfigure, int HMI_output) {
+	last_rframe_seen = GLOBAL_timer.read_us();
+	wait_ms(50);//10
+	if (need_radio_reconfigure == 1) {
+		if (HMI_output) { HMI_printf("reconfiguring radio...\r\n"); }
+		SI4463_configure_all();
+		if (HMI_output) { HMI_printf("reconfiguring done; starting radio\r\n"); }
+	}
+	if (need_disconnect == 1) {
+		if (is_TDMA_master == 1) {
+			my_client_radio_connexion_state = 2;
+		} else {
+			my_client_radio_connexion_state = 1;
+			my_radio_client_ID = 0x7E;
+		}
+	}
+	TDMA_NULL_frame_init(70);
+	if (need_disconnect == 1) { 
+		TDMA_init_all();
+	}
+	radio_flush_TX_FIFO();// A supprimer!
+	SI4463_radio_start();
+	//need_radio_reconfigure = 0;
+}
+
+void RADIO_off(int need_disconnect) {
+	int toto;
+	CONF_radio_state_ON_OFF = 0;
+	if ( (is_TDMA_master == 0 ) && (need_disconnect == 1) ) {
+		my_client_radio_connexion_state = 1;
+		my_radio_client_ID = 0x7E;
+	}
+	wait_ms(100);//400
+	SI4463_FIFO_status(G_SI4463, &toto, &toto, 1);//tentative 
+	G_SI4463->RX_TX_state = 0;//tentative 
+	G_SI4463->RX_LED->write(0); 
+	wait_us(10);
+	SI4463_change_state(G_SI4463, 0x03);//change state to ready
+	wait_us(10);
+	SI4463_FIFO_status(G_SI4463, &toto, &toto, 1);//tentative 
+	wait_us(10);
+	SI4463_clear_IT (G_SI4463, 0, 0);//tentative 
+	wait_ms(10);
+	RX_FIFO_WR_point = RX_FIFO_last_received; //rewind FIFO pointer
+	G_PTT_PA_pin->write(0);
+	TX_in_progress = 0;
+}
+
+static int RADIO_previous_state;
+
+void RADIO_off_if_necessary(int need_disconnect) {
+	if (CONF_radio_state_ON_OFF == 1) {
+		RADIO_previous_state = 1;
+		RADIO_off(need_disconnect);
+	} else {
+		RADIO_previous_state = 0;
+	}
+}
+
+void RADIO_restart_if_necessary(int need_disconnect, int need_radio_reconfigure, int HMI_output) {
+	if (RADIO_previous_state == 1) {
+		RADIO_on(need_disconnect, need_radio_reconfigure, HMI_output);
+	}
+}
+
+void SI4432_TX_test(unsigned int req_duration) { //duration in ms
+	int toto;
+	unsigned int timer_begin;
+	unsigned int timer_snapshot;
+	unsigned int real_duration;
+	//unsigned char SI4463_state;
+	//unsigned char loc_answer[8];
+	unsigned char trash[4];
+	
+	TX_test_inprogress = 1;
+	
+	TX_frame_to_send = TX_TDMA_intern_data;
+	req_duration = req_duration * 1000; //converts ms to microsec
+	
+	SI4463_FIFO_status(G_SI4463, &toto, &toto, 1); //reset FIFO (including CTS)
+	SI4463_clear_IT (G_SI4463, 0, 0);//without CTS
+	G_SI4463->RX_TX_state = 2; // activate TX HW IRQ
+	wait_us(20); 
+	SI4463_CTS_read_answer(G_SI4463, trash, 0, 20);
+	
+	G_SI4463->RX_TX_state = 2;
+	TDMA_NULL_frame_init(230);
+	SI4463_TX_new_frame(0);
+	timer_begin = GLOBAL_timer.read_us();
+	do {
+		wait_ms(2);
+		timer_snapshot = GLOBAL_timer.read_us();
+		real_duration = (timer_snapshot - timer_begin);
+	} while (real_duration < (req_duration) ) ;
+	TX_test_inprogress = 0;
+	wait_ms(200);
+	RADIO_off(1);
+}
+
+void SI4463_set_frequency(float freq_base, float freq_step) {
+	unsigned char radio_config[15] = {0x11, 0x40, 0x06, 0x00};
+	unsigned int step_size_temp, FC_int, FC_frac_int;
+	//unsigned int i;
+	float FC_int_float, FC_frac_float;
+	
+	//FC_int_float = freq_base / 7.5;
+	FC_int_float = freq_base * SI4463_NOUTDIV / 60;
+	FC_int = (unsigned int)FC_int_float - 1;
+	FC_frac_float = (FC_int_float - (float)FC_int) * 524288;
+	FC_frac_int = (unsigned int)(FC_frac_float);
+	
+	//printf ("\r\nfreq_base %f \r\nfreq step %f\r\n", freq_base, freq_step);
+	//printf ("\r\nFC_int_float %f\r\nFC_int %i\r\nFC_frac_float %f\r\nFC_frac_int%i\r\n", FC_int_float, FC_int, FC_frac_float, FC_frac_int);
+	step_size_temp = (unsigned int)(524288*freq_step/7.5);
+	
+	radio_config [4] = FC_int & 0xFF; 					//FREQ_CONTROL_INTE
+	radio_config [5] = (FC_frac_int & 0xFF0000) >> 16;	//FREQ_CONTROL_FRAC MSB
+	radio_config [6] = (FC_frac_int & 0x00FF00) >> 8; 	// ...
+	radio_config [7] = (FC_frac_int & 0x0000FF);		//FREQ_CONTROL_FRAC LSB
+	radio_config [8] = (step_size_temp & 0xFF00) >> 8;	//FREQ_CONTROL_STEP_SIZE MSB
+	radio_config [9] = step_size_temp & 0x00FF;			//FREQ_CONTROL_STEP_SIZE LSB
+	//for (i=0; i<10; i++) {
+	//	printf("i%i : %02X\r\n", i, radio_config[i]);
+	//}
+	SI4463_send_command(G_SI4463, radio_config, 10);
+	wait_ms(100);// 100us
+	SI4463_CTS_read_answer(G_SI4463, SI_trash, 0, 200);
+	wait_ms(100);// 100us
+}
+
+void RADIO_compute_freq_params() {
+	float freq_local, freq_shift_loc;
+	float loc_freq_float_RX;
+	float loc_freq_float_TX;
+	freq_local = FREQ_RANGE_MIN + ((float)CONF_frequency_HD)/1000;//unit MHz
+	freq_shift_loc = ((float)CONF_freq_shift)/1000;//unit MHz
+	if (is_TDMA_master == 1) {
+		loc_freq_float_RX = freq_local + freq_shift_loc;
+		loc_freq_float_TX = freq_local;//downlink
+		if(CONF_master_FDD == 1) {//artificially disables RX for Master down
+			loc_freq_float_RX = freq_local;
+		}
+	} else {
+		loc_freq_float_RX = freq_local;//downlink
+		loc_freq_float_TX = freq_local + freq_shift_loc;//uplink
+	}
+	unsigned int FC_int, FC_frac_int, VCO_CNT_int;
+	float FC_int_float, FC_frac_float, VCO_CNT_float;
+	
+	//TX frequency
+	//FC_int_float = loc_freq_float_TX / 7.5;
+	FC_int_float = loc_freq_float_TX * SI4463_NOUTDIV / 60;
+	FC_int = (unsigned int)FC_int_float - 1;
+	FC_frac_float = (FC_int_float - (float)FC_int) * 524288;
+	FC_frac_int = (unsigned int)(FC_frac_float);
+	//VCO_CNT_float = loc_freq_float_TX * 256/60 + 0.5;
+	VCO_CNT_float = (loc_freq_float_TX*32/60) * SI4463_NOUTDIV;
+	VCO_CNT_int = (unsigned int)(VCO_CNT_float);
+	CONF_SI4463_freq_conf_TX[0] = 0x37;
+	CONF_SI4463_freq_conf_TX[1] = FC_int & 0xFF; 			//FREQ_CONTROL_INTE
+	CONF_SI4463_freq_conf_TX[2] = (FC_frac_int & 0xFF0000) >> 16;//FREQ_CONTROL_FRAC MSB
+	CONF_SI4463_freq_conf_TX[3] = (FC_frac_int & 0x00FF00) >> 8; 	// ...
+	CONF_SI4463_freq_conf_TX[4] = (FC_frac_int & 0x0000FF);	//FREQ_CONTROL_FRAC LSB
+	CONF_SI4463_freq_conf_TX[5] = (VCO_CNT_int & 0xFF00) >> 8;// VCO CNT MSB
+	CONF_SI4463_freq_conf_TX[6] = (VCO_CNT_int & 0x00FF); 		// VCO CNT LSB
+	CONF_SI4463_freq_conf_TX[7] = 0x00;// PLL settle time MSB
+	CONF_SI4463_freq_conf_TX[8] = 0x64;// PLL settle time LSB (us)
+	
+	//RX frequency
+	//FC_int_float = loc_freq_float_RX / 7.5;
+	FC_int_float = loc_freq_float_RX * SI4463_NOUTDIV / 60;
+	FC_int = (unsigned int)FC_int_float - 1;
+	FC_frac_float = (FC_int_float - (float)FC_int) * 524288;
+	FC_frac_int = (unsigned int)(FC_frac_float);
+	//VCO_CNT_float = loc_freq_float_RX * 256/60 -2 + 0.5;
+	VCO_CNT_float = (loc_freq_float_RX*32/60 - 32/128) * SI4463_NOUTDIV;
+	VCO_CNT_int = (unsigned int)(VCO_CNT_float);
+	CONF_SI4463_freq_conf_RX[0] = 0x36;
+	CONF_SI4463_freq_conf_RX[1] = FC_int & 0xFF; 			//FREQ_CONTROL_INTE
+	CONF_SI4463_freq_conf_RX[2] = (FC_frac_int & 0xFF0000) >> 16;//FREQ_CONTROL_FRAC MSB
+	CONF_SI4463_freq_conf_RX[3] = (FC_frac_int & 0x00FF00) >> 8; 	// ...
+	CONF_SI4463_freq_conf_RX[4] = (FC_frac_int & 0x0000FF);	//FREQ_CONTROL_FRAC LSB
+	CONF_SI4463_freq_conf_RX[5] = (VCO_CNT_int & 0xFF00) >> 8;// VCO CNT MSB
+	CONF_SI4463_freq_conf_RX[6] = (VCO_CNT_int & 0x00FF); 		// VCO CNT LSB
+	
+	CONF_channel_TX = 0;
+	CONF_channel_RX = 0;
+	
+	SI4463_set_frequency(loc_freq_float_TX, 10);
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463.h
new file mode 100755
index 0000000..e9f3f73
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463.h
@@ -0,0 +1,119 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef SI4463_F4
+#define SI4463_F4
+
+#include "mbed.h"
+#include "SI4463.h"
+
+#define SI4463_offset_size 90
+#define SI4463_CONF_RX_FIFO_threshold 90 
+//64
+#define SI4463_CONF_TX_FIFO_threshold 90
+#define SI4463_CONF_max_field2_size 345 
+//63
+
+//#define SI4463_time_byte 8
+//#define SI4463_zero_frame_time 590
+
+struct SI4463_Chip{
+    SPI* spi;
+    DigitalOut* cs;
+	InterruptIn* interrupt;
+	int RX_TX_state; //0:nothing 1:RX 2:TX
+	DigitalOut* RX_LED;
+	DigitalOut* SDN;
+};
+
+int SI4463_CTS_read_answer(SI4463_Chip* SI4463, unsigned char* data, int size, int timeout);
+
+int SI4463_configure_from_22(SI4463_Chip* SI4463);
+int SI4463_configure_from_13(SI4463_Chip* SI4463);
+int SI4463_configure_from_23(SI4463_Chip* SI4463);
+int SI4463_configure_from_14(SI4463_Chip* SI4463);
+int SI4463_configure_from_24(SI4463_Chip* SI4463);
+
+int SI4463_configure_from_h(SI4463_Chip* SI4463, unsigned char* radio_config_data);
+
+int SI4463_set_power(SI4463_Chip* SI4463);
+
+void SI4463_print_version(SI4463_Chip* SI4463);
+
+void SI4463_FIFO_status(SI4463_Chip* SI4463, int* RX_FIFO_count, int* TX_FIFO_count, int reset);
+
+//void SI4463_set_GPIO(SI4463_Chip* SI4463, unsigned char GPIO_st_2, unsigned char GPIO_st_3);
+
+void SI4463_FIFO_write(SI4463_Chip* SI4463, unsigned char* data, int count);
+
+void SI4463_FIFO_read(SI4463_Chip* SI4463, unsigned char* data, int size); 
+
+void SI4463_change_state (SI4463_Chip* SI4463, unsigned char new_state);
+
+void SI4463_start_RX (SI4463_Chip* SI4463, unsigned char channel);
+
+void SI4463_start_TX (SI4463_Chip* SI4463, unsigned char channel, unsigned int size);
+//void SI4463_start_TX (SI4463_Chip* SI4463, unsigned char channel, unsigned int size, unsigned char next_state); 
+void SI4463_start_TX_repeat (SI4463_Chip* SI4463, unsigned char channel, unsigned int size);
+
+void SI4463_read_FRR(SI4463_Chip* SI4463, unsigned char* data);
+
+int SI4463_get_state(SI4463_Chip* SI4463);
+
+//void SI4463_init_RX();
+
+void SI4463_clear_IT(SI4463_Chip* SI4463, unsigned char PH_clear, unsigned char modem_clear);
+
+void SI4463_set_TX_preamble_length (SI4463_Chip* SI4463, unsigned char preamble_length_val);
+
+int SI4463_read_temperature(SI4463_Chip* SI4463);
+
+int check_RSSI_without_packet (void);
+
+void SI4463_periodic_temperature_check(SI4463_Chip* SI4463);
+
+void SI4463_periodic_temperature_check_2(void); 
+
+void SI4463_temp_check_init(void);
+
+void SI4463_prepa_TX_1();
+
+void SI4463_prepa_TX_2();
+
+void SI4463_TX_to_RX_transition(void);
+
+void SI4463_RX_timeout (void);
+
+void SI4463_decide_new_TX_or_not(void);
+
+void SI4463_TX_new_frame(unsigned char synchro);
+
+void SI4463_HW_interrupt();
+
+int SI4463_configure_all(void);
+
+void SI4463_radio_start(void);
+void RADIO_off(int need_disconnect);
+void RADIO_on(int need_disconnect, int need_radio_reconfigure, int HMI_output);
+void RADIO_off_if_necessary(int need_disconnect);
+void RADIO_restart_if_necessary(int need_disconnect, int need_radio_reconfigure, int HMI_output);
+void SI4432_TX_test(unsigned int req_duration);
+
+void SI4463_set_frequency(float freq_base, float freq_step);
+void RADIO_compute_freq_params();
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_11.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_11.h
new file mode 100755
index 0000000..89e29ae
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_11.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_11 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x0D, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xA7, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x00, 0x00, 0x00, 0x23, 0x86, 0xD4, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_11_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_11_2m.h
new file mode 100755
index 0000000..8644c23
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_11_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_11 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xA6, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_12.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_12.h
new file mode 100755
index 0000000..6d1636c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_12.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_12 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x18, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x93, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8C, 0x4A, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_12_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_12_2m.h
new file mode 100755
index 0000000..61707b8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_12_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_12 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x49, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xBA, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCD, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_13.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_13.h
new file mode 100755
index 0000000..60cbad5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_13.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_13 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x9A, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_13_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_13_2m.h
new file mode 100755
index 0000000..1d4d6a6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_13_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_13 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x7A, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xE1, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x02, 0xEB, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_14.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_14.h
new file mode 100755
index 0000000..525c433
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_14.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_14 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x44, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x44, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x76, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_14_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_14_2m.h
new file mode 100755
index 0000000..c41f517
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_14_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_14 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0xCC, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xCD, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x04, 0x61, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_20.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_20.h
new file mode 100755
index 0000000..56cf63e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_20.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_20 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x06, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD4, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x12, 0x81, 0xB5, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCB, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_20_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_20_2m.h
new file mode 100755
index 0000000..c25c442
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_20_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_20 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x14, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x7B, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x12, 0x85, 0x1F, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCB, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_21.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_21.h
new file mode 100755
index 0000000..875d157
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_21.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_21 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x0D, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xA7, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x23, 0x86, 0xD4, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_21_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_21_2m.h
new file mode 100755
index 0000000..d49e910
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_21_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_21 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xA6, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_22.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_22.h
new file mode 100755
index 0000000..11ffd8c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_22.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_22 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x18, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x93, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8C, 0x4A, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_22_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_22_2m.h
new file mode 100755
index 0000000..3f6e51e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_22_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_22 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x49, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xBA, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCD, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_23.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_23.h
new file mode 100755
index 0000000..b6741f3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_23.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_23 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xC3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_23_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_23_2m.h
new file mode 100755
index 0000000..8e7bfa4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_23_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_23 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x7A, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xE1, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x03, 0x37, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_24.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_24.h
new file mode 100755
index 0000000..5d242a3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_24.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_24 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x44, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x44, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x7C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_24_2m.h b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_24_2m.h
new file mode 100755
index 0000000..a1c93a7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/SI4463/SI4463_config_24_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_24 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0xCC, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xCD, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x04, 0x74, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/TDMA.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/TDMA.cpp
new file mode 100755
index 0000000..2960ed0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/TDMA.cpp
@@ -0,0 +1,458 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "TDMA.h"
+#include "mbed.h"
+#include "L1L2_radio.h"
+#include "global_variables.h"
+
+static unsigned char TDMA_table_uplink_st[radio_addr_table_size];
+static int TDMA_table_uplink_usage[radio_addr_table_size];
+static int TDMA_table_is_fast[radio_addr_table_size];
+//static long int TDMA_table_TA[radio_addr_table_size];
+static unsigned int TDMA_table_RX_time[radio_addr_table_size]; 
+static unsigned char TDMA_table_up2date[radio_addr_table_size];
+static unsigned char TDMA_table_slots[radio_addr_table_size];
+static unsigned int TDMA_table_offset[radio_addr_table_size];
+static unsigned char TDMA_frame_nb; 
+static unsigned char master_allocated_slots;
+static unsigned int slave_alloc_RX_age = 2;
+static unsigned char my_multiframe_mask;
+static unsigned char my_multiframe_ID;
+//static unsigned int TDMA_slave_last_master_top = 0;
+static unsigned int TDMA_offset_multi_frame;
+
+void TDMA_init_all(void) {
+	int i;
+	for (i=0; i<radio_addr_table_size; i++) {
+		TDMA_table_uplink_st[i] = 0;
+		TDMA_table_uplink_usage [i] = 32;
+		TDMA_table_is_fast[i] = 1;
+	}
+}
+
+unsigned char TDMA_byte_elaboration(unsigned char synchro) {
+	unsigned char TDMA_byte;
+	unsigned long int uplink_buffer_size;
+	//unsigned long int uplink_buffer_size_temp;
+	if (is_TDMA_master) { // TDMA Master
+		TDMA_byte = 0x40;//uplink/downlink bit
+		TDMA_byte = TDMA_byte + (TDMA_frame_nb & 0x1F);
+		if (synchro) {
+			TDMA_frame_nb++;
+		}
+	} else { // TDMA client
+		TDMA_byte = 0x00; //uplink/downlink bit
+		// uplink buffer size
+		//uplink_buffer_size_temp = (TXPS_FIFO->last_ready - TXPS_FIFO->RD_point); 
+		//uplink_buffer_size = uplink_buffer_size_temp / 300; //number of frames
+		uplink_buffer_size = compute_TX_buff_size_global();
+		//if ( (uplink_buffer_size_temp % 300) > 0) {uplink_buffer_size++;}
+		if (uplink_buffer_size > 30) {uplink_buffer_size = 30;}
+		TDMA_byte = TDMA_byte + (uplink_buffer_size & 0x1F);
+	}
+	if (synchro) {
+		TDMA_byte = TDMA_byte + 0x20;
+	}
+	TDMA_byte = TDMA_byte + parity_bit_elab[TDMA_byte & 0x7F]; // parity bit
+	return TDMA_byte;
+}
+
+short int TDMA_TA_measure_single_frame(unsigned int frame_timer, unsigned char TDMA_byte, unsigned char client_byte, int frame_size_loc) {
+	int measured_offset = 0x7FFF;
+	int TA_answer = 0x7FFF;
+	unsigned char client_ID = 0xF0;
+	unsigned char is_downlink;
+	
+	is_downlink = TDMA_byte & 0x40; 
+	
+	if ( ((TDMA_byte & 0x20) == 0x20) && (is_downlink == 0) && (parity_bit_check[TDMA_byte]) && (parity_bit_check[client_byte]) ) { //first frame top-synchro
+		client_ID = client_byte & 0x7F;
+		if (CONF_master_FDD == 1) {
+			measured_offset = frame_timer;
+		} else {
+			measured_offset = frame_timer - ((TDMA_slave_last_master_top & 0xFFFFFF));// + 10*TDMA_table_offset[client_ID]);
+		}
+		if (frame_size_loc < 114) {
+			measured_offset = measured_offset + (114 - frame_size_loc) * 0.85; 
+		}
+		if ( (client_ID < radio_addr_table_size) && (CONF_radio_addr_table_status[client_ID]) ) {
+			TA_answer = measured_offset - (10*TDMA_table_offset[client_ID]);
+			if ( (TA_answer > -200) && (TA_answer < 2000) ) {// -1000 .. 5000
+				TDMA_table_TA[client_ID] = 0.9*TDMA_table_TA[client_ID] + 1*TA_answer;
+			}
+			//printf ("id:%i TA_single:%i TA_filt:%i\r\n", client_ID, TA_answer, TDMA_table_TA[client_ID]);
+		}
+		else if (client_ID == 0x7E) {
+			TA_answer = measured_offset - (10*TDMA_offset_multi_frame);
+			//printf ("id:%i TAth:%i\r\n", client_ID, TA_answer);
+		}
+	}
+	return (short int)TA_answer;
+}
+
+void TDMA_init_TA(unsigned char client_ID, int TA_input) {
+	if ( (TA_input > -200) && (TA_input < 2000) ) {
+		TDMA_table_TA[client_ID] = 10*TA_input;
+	}
+}
+
+void TDMA_top_measure(void) {
+	TDMA_slave_last_master_top = GLOBAL_timer.read_us();
+	TDMA_slave_last_master_top = TDMA_slave_last_master_top + 0;
+}
+
+void TDMA_FDD_up_top_measure(void) {
+	TDMA_slave_last_master_top = GLOBAL_timer.read_us();
+	TDMA_slave_last_master_top = TDMA_slave_last_master_top + 0;
+	RX_top_FDD_up_counter++;
+	//printf("t\r\n");
+}
+
+void TDMA_byte_RX_interp (unsigned char TDMA_byte, unsigned char client_ID_byte, unsigned char protocol, unsigned int RX_time) {
+	// a traiter : top client / top master / frame client / 
+	unsigned char client_ID;
+	unsigned char uplink_buffer_size;
+	unsigned char TDMA_synchro;
+	unsigned char is_downlink;
+	unsigned int loc_time;
+	TDMA_synchro = TDMA_byte & 0x20;
+	is_downlink = TDMA_byte & 0x40;
+	client_ID = client_ID_byte & 0x7F;
+	if (parity_bit_check[TDMA_byte]) { // checks parity bit
+	//if(1) {
+		if (is_TDMA_master) { // TDMA Master
+			if (is_downlink == 0) { //only uplink frames
+				uplink_buffer_size = TDMA_byte & 0x1F;
+				if ( (client_ID < radio_addr_table_size) && (parity_bit_check[client_ID_byte]) ) {
+					TDMA_table_uplink_st[client_ID] = uplink_buffer_size;
+					TDMA_table_up2date[client_ID] = 1;
+					if (uplink_buffer_size > 1) { // force to fast slots
+						TDMA_table_uplink_usage[client_ID] = 32;
+						TDMA_table_is_fast[client_ID] = 1;
+					}
+					//printf("%i upl%i mem%i fast%i\r\n", client_ID, uplink_buffer_size, TDMA_table_uplink_usage[client_ID],TDMA_table_is_fast[client_ID]);
+					if (TDMA_synchro) {
+						TDMA_table_RX_time[client_ID] = RX_time;
+					}
+				}
+			}
+		} else { // TDMA client
+			TDMA_frame_nb = TDMA_byte & 0x1F;
+			if ( (TDMA_synchro) && (is_downlink) ) { //(slave_alloc_RX_age < 2) ) {
+				TDMA_slave_last_master_top = RX_time; 
+				//debug_counter ++; 
+				if ( (slave_alloc_RX_age < 2) && (CONF_radio_state_ON_OFF) ) {
+					if ( (TDMA_frame_nb & my_multiframe_mask) == (my_multiframe_ID & my_multiframe_mask) ) {
+						loc_time = GLOBAL_timer.read_us();
+						time_next_TX_slave = ((RX_time + offset_time_TX_slave) & 0xFFFFFF );//!!!test TA june 2018 +380
+						SI4463_prepa_TX_1_call.attach_us(&SI4463_prepa_TX_1, (time_next_TX_slave - loc_time - CONF_delay_prepTX1_2_TX) &0xFFFFFF  );
+						slave_alloc_RX_age++;
+						slave_new_burst_tx_pending = 1;
+					}
+				}
+			}
+		}
+	}
+}
+
+//TDMA_slave_timeout : allow 1 more burst if no TOP received from Master
+void TDMA_slave_timeout (void) {
+	unsigned int loc_time;
+	unsigned int master_top_age;
+	loc_time = GLOBAL_timer.read_us();
+	master_top_age = loc_time - TDMA_slave_last_master_top;
+	if ( (master_top_age > (CONF_TDMA_frame_duration + 8000) ) && (master_top_age < (CONF_TDMA_frame_duration + 10000)) ) {
+		if ( (slave_alloc_RX_age < 2) && (slave_new_burst_tx_pending == 0) && (CONF_radio_state_ON_OFF) ) {
+			TDMA_frame_nb = (TDMA_frame_nb+1) & 0x1F;
+			if ( (TDMA_frame_nb & my_multiframe_mask) == (my_multiframe_ID & my_multiframe_mask) ) {
+				time_next_TX_slave = (TDMA_slave_last_master_top + CONF_TDMA_frame_duration + offset_time_TX_slave) & 0xFFFFFF;
+				SI4463_prepa_TX_1_call.attach_us(&SI4463_prepa_TX_1, (time_next_TX_slave - loc_time - CONF_delay_prepTX1_2_TX) &0xFFFFFF  );
+				slave_alloc_RX_age++;
+				slave_new_burst_tx_pending = 1;
+			}
+		}
+	}
+}
+
+void TDMA_master_allocation () {
+	int size_wo_FEC;
+	int size_w_FEC;
+	int i;
+	int allocated_slots;
+	int nb_fast_clients;
+	unsigned int loc_time_offset;
+	long int local_TA; 
+	unsigned int downlink_buffer_size;
+	//unsigned int downlink_buffer_size_temp;
+	static unsigned char TDMA_alloc_frame_raw[150];
+	unsigned char rframe_length;
+	unsigned char loc_client_needs[radio_addr_table_size];
+	unsigned char loc_master_needs;
+	unsigned char remaining_needs;
+	
+	for (i=0; i<radio_addr_table_size; i++) {
+		if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_uplink_usage[i] > 0) ) {
+			TDMA_table_is_fast[i] = 1;
+			TDMA_table_uplink_usage[i]--; 
+		}
+	}
+	//if ((TDMA_frame_nb & 0x7) == 0) { // once every 8 frames 
+	if ((TDMA_frame_nb & 0x3) == 0) { // once every 4 frames 
+		TDMA_master_allocation_slow();
+	}
+	// ** TDMA allocation algorithm for fast slots **	
+	// 1) Master computes its own downlink buffer size
+	//downlink_buffer_size_temp = (TXPS_FIFO->last_ready - TXPS_FIFO->RD_point); 
+	//downlink_buffer_size = downlink_buffer_size_temp / 300; //number of frames
+	//if ((downlink_buffer_size_temp % 300) > 0) {downlink_buffer_size++;}
+	downlink_buffer_size = compute_TX_buff_size_global();
+	if (downlink_buffer_size > 30) {downlink_buffer_size = 30;}
+	// 2) if no TDMA uplink received from client, lower its need
+	for (i=0; i<radio_addr_table_size; i++) {
+		if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_up2date[i]==0) && (TDMA_table_uplink_st[i] > 0) ) {
+			TDMA_table_uplink_st[i]--; 
+		}
+		TDMA_table_up2date[i] = 0;
+	}
+	// 3) init allocation table
+	// copy uplink state and allocate 1 slot to each active
+	// Master
+	loc_master_needs = downlink_buffer_size; // copy
+	master_allocated_slots = 1;
+	if (loc_master_needs>0) {loc_master_needs--;} // decrement
+	allocated_slots = 1; // at least 1 for master
+	// Clients
+	nb_fast_clients = 0;
+	for (i=0; i<radio_addr_table_size; i++) {
+		if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_is_fast[i]) ) {
+			nb_fast_clients++;
+			loc_client_needs[i] = TDMA_table_uplink_st[i]; // copy
+			TDMA_table_slots[i] = 1; // allocate 1 slot
+			if (loc_client_needs[i]>0) {loc_client_needs[i]--;} // decrement
+			allocated_slots++; 
+		}
+	}
+	// 4) 1st allocation pass, round robin
+	remaining_needs = 1;
+	while ( (allocated_slots < 15) && (remaining_needs > 0) ) {
+		// master
+		if ( (loc_master_needs > 0) && (allocated_slots < 15) ) {
+			master_allocated_slots++;
+			loc_master_needs--;
+			allocated_slots++;
+		}
+		if ( (loc_master_needs > 0) && (allocated_slots < 15) && (nb_fast_clients > 1) ) {// master counts 2 times if more than 1 client
+			master_allocated_slots++;
+			loc_master_needs--;
+			allocated_slots++;
+		}
+		remaining_needs = loc_master_needs;
+		for (i=0; i<radio_addr_table_size; i++) {
+			if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_is_fast[i]) && (loc_client_needs[i]>0) && (allocated_slots < 15) ) {
+				TDMA_table_slots[i]++;
+				loc_client_needs[i]--;
+				allocated_slots++;
+				remaining_needs = remaining_needs + loc_client_needs[i];
+			}
+		}
+	}
+	// 5) 2nd allocation pass, round robin of remaining, even without needs
+	while (allocated_slots < 15) {
+		master_allocated_slots++;
+		allocated_slots++;
+		for (i=0; i<radio_addr_table_size; i++) {
+			if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_is_fast[i]) && (allocated_slots < 15) ) {
+				TDMA_table_slots[i]++;
+				allocated_slots++;
+			}
+		}
+	}
+	// 6) timings construction
+	time_max_TX_burst = (CONF_reduced_TDMA_slot_duration + CONF_TDMA_slot_margin) + (master_allocated_slots * CONF_TDMA_slot_duration) + ((master_allocated_slots-1)*CONF_TDMA_slot_margin);// for Master
+	loc_time_offset = time_max_TX_burst + CONF_TDMA_slot_margin + CONF_TR_margain + CONF_TA_margain;
+	//printf("m %i", time_max_TX_burst);
+	for (i=0; i<radio_addr_table_size; i++) {
+		if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_is_fast[i]) ) {
+			local_TA = TDMA_table_TA[i];
+			if ( (local_TA > -2000) && (local_TA < 20000) ) {
+				TDMA_table_offset[i] = (loc_time_offset/10) - (local_TA/100); 
+			} else {
+				TDMA_table_offset[i] = (loc_time_offset/10); 
+			}
+			loc_time_offset = loc_time_offset + (TDMA_table_slots[i] * (CONF_TDMA_slot_duration + CONF_TDMA_slot_margin) );
+			//printf("client %i %i %i ", i, TDMA_table_offset[i], TDMA_table_slots[i]*CONF_TDMA_slot_duration);
+		}
+	}
+	//printf("\r\n");
+	//multi frame x4
+	TDMA_offset_multi_frame = loc_time_offset / 10;
+	for (i=0; i<4; i++) {
+		if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_is_fast[i]==0) ) {
+			local_TA = TDMA_table_TA[i];
+			if ( (local_TA > -2000) && (local_TA < 20000) ) {
+				TDMA_table_offset[i] = TDMA_offset_multi_frame - (local_TA/100); 
+			} else {
+				TDMA_table_offset[i] = TDMA_offset_multi_frame; 
+			}
+		}
+	}
+	loc_time_offset = loc_time_offset + CONF_TDMA_slot_duration + CONF_TDMA_slot_margin;
+	TDMA_offset_multi_frame = loc_time_offset / 10;
+	for (i=4; i<radio_addr_table_size; i++) {
+		if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_is_fast[i]==0) ) {
+			local_TA = TDMA_table_TA[i];
+			if ( (local_TA > -2000) && (local_TA < 20000) ) {
+				TDMA_table_offset[i] = TDMA_offset_multi_frame - (local_TA/100); 
+			} else {
+				TDMA_table_offset[i] = TDMA_offset_multi_frame; 
+			}
+		}
+	}
+	
+	// ** TDMA allocation frame construction **
+	TDMA_alloc_frame_raw[0] = 0xFF; // address = broadcast
+	TDMA_alloc_frame_raw[1] = 0x1F; // protocol = TDMA allocation
+	size_wo_FEC = 2;
+	for (i=0; i<radio_addr_table_size; i++) {
+		if (CONF_radio_addr_table_status[i]) { // client "i" is active
+			if (TDMA_table_is_fast[i]==1) { // inside fast slot
+			//if (1) {
+				TDMA_alloc_frame_raw[size_wo_FEC] = i; // client ID
+				size_wo_FEC++;
+				TDMA_alloc_frame_raw[size_wo_FEC] = TDMA_table_offset[i] & 0xFF; // time offset LSB
+				size_wo_FEC++;
+				TDMA_alloc_frame_raw[size_wo_FEC] = (TDMA_table_offset[i] & 0xFF00)>>8; // time offset MSB
+				size_wo_FEC++;
+				TDMA_alloc_frame_raw[size_wo_FEC] = (TDMA_table_slots[i] & 0xF); // TDMA slot length (4xLSb) and power (MSb)
+				size_wo_FEC++;
+				TDMA_alloc_frame_raw[size_wo_FEC] = 0; //  ID multi frame (4xLSb)
+				size_wo_FEC++;
+			} else { // inside slow slot
+				TDMA_alloc_frame_raw[size_wo_FEC] = i; // client ID
+				size_wo_FEC++;
+				TDMA_alloc_frame_raw[size_wo_FEC] = TDMA_table_offset[i] & 0xFF; // time offset LSB
+				size_wo_FEC++;
+				TDMA_alloc_frame_raw[size_wo_FEC] = (TDMA_table_offset[i] & 0xFF00)>>8; // time offset MSB
+				size_wo_FEC++;
+				TDMA_alloc_frame_raw[size_wo_FEC] = 1; // TDMA slot length (4xLSb) and power (MSb)
+				size_wo_FEC++;
+				//TDMA_alloc_frame_raw[size_wo_FEC] = 0x30 + (i & 0x0F); //multi frame period (4xMSb) ID multi frame (4xLSb)
+				TDMA_alloc_frame_raw[size_wo_FEC] = 0x20 + (i & 0x03); //multi frame period (4xMSb) ID multi frame (4xLSb)
+				size_wo_FEC++;
+			}
+		}
+	}
+	//Discovery slot multi frame
+	TDMA_alloc_frame_raw[size_wo_FEC] = 0x7E; // client ID
+	size_wo_FEC++;
+	TDMA_alloc_frame_raw[size_wo_FEC] = TDMA_offset_multi_frame & 0xFF; // time offset LSB
+	size_wo_FEC++;
+	TDMA_alloc_frame_raw[size_wo_FEC] = (TDMA_offset_multi_frame & 0xFF00)>>8; // time offset MSB
+	size_wo_FEC++;
+	TDMA_alloc_frame_raw[size_wo_FEC] = 1; // TDMA slot length (4xLSb) and power (MSb)
+	size_wo_FEC++;
+	//TDMA_alloc_frame_raw[size_wo_FEC] = 0x37; //multi frame period=3 (4xMSb); ID multi frame=7 (4xLSb)
+	TDMA_alloc_frame_raw[size_wo_FEC] = 0x23; //multi frame period=2 (4xMSb); ID multi frame=7 (4xLSb)
+	size_wo_FEC++;
+	//END
+	TDMA_alloc_frame_raw[size_wo_FEC] = 0xFF; // used to detect end of TDMA frame
+	size_wo_FEC++;
+	if (size_wo_FEC < 66) {
+		size_wo_FEC = 66;
+	}
+	size_w_FEC = size_w_FEC_compute (size_wo_FEC);
+	rframe_length = size_w_FEC + 1 - SI4463_offset_size;
+
+	TX_TDMA_intern_data[0] = 0;//timer coarse, useless
+	TX_TDMA_intern_data[1] = rframe_length;
+	
+	size_w_FEC = FEC_encode2(TDMA_alloc_frame_raw, TX_TDMA_intern_data+3, size_wo_FEC);
+}
+
+void TDMA_master_allocation_slow () {
+	int i;
+	for (i=0; i<radio_addr_table_size; i++) {
+		if ( (CONF_radio_addr_table_status[i]) && (TDMA_table_uplink_usage[i] == 0) ) {
+			TDMA_table_is_fast[i] = 0;
+		}
+		if (CONF_radio_addr_table_status[i] <= 0) {
+			TDMA_table_uplink_st[i] = 0;
+			TDMA_table_uplink_usage [i] = 32;
+			TDMA_table_is_fast[i] = 1;
+		}
+	}	
+}
+
+
+void TDMA_NULL_frame_init(int size) {
+	unsigned char null_frame[260];
+	int size_wo_FEC, size_w_FEC; 
+	unsigned char rframe_length;
+	null_frame[0] = my_radio_client_ID + parity_bit_elab[my_radio_client_ID]; // address = client
+	null_frame[1] = 0x00; // protocol = NULL frame
+	//size_wo_FEC = 70;
+	size_wo_FEC = size;
+	size_w_FEC = size_w_FEC_compute (size_wo_FEC);
+	rframe_length = size_w_FEC + 1 - SI4463_offset_size;
+	//TX_signaling_TDMA->data[0] = 0; // timer, date for later use
+	TX_TDMA_intern_data[0] = 0;
+	//TX_signaling_TDMA->data[1] = rframe_length; // length
+	//TX_signaling_TDMA->WR_point = 3; 
+	TX_TDMA_intern_data[1] = rframe_length;
+	//size_w_FEC = FEC_encode(null_frame, TX_signaling_TDMA, size_wo_FEC);
+	size_w_FEC = FEC_encode2(null_frame, TX_TDMA_intern_data+3, size_wo_FEC);//+3: timer, size, tdma
+	//TX_signaling_TDMA->last_ready = TX_signaling_TDMA->WR_point;
+}
+
+
+
+void TDMA_slave_alloc_exploitation(unsigned char* unFECdata, int unFECsize) {
+	static unsigned char LUT_multif_mask[8] = {0,1,3,7,15,31};
+	int i;
+	// int j;
+	unsigned char loc_client_ID;
+	unsigned char loc_TDMA_slot_length;
+	unsigned char loc_power;
+	unsigned long int loc_TDMA_offset;
+	i=2; //1st byte: client ID, 2nd byte:protocol
+	loc_client_ID = unFECdata[2];
+	while ( (loc_client_ID != 0xFF) && (i < unFECsize) ) {
+		if (loc_client_ID == my_radio_client_ID) {
+			loc_TDMA_offset = ( unFECdata[i+1] + (unFECdata[i+2]<<8) )*10;
+			offset_time_TX_slave = loc_TDMA_offset; 
+			//printf("offset:%i\r\n",loc_TDMA_offset);
+			loc_TDMA_slot_length = 0x0F & unFECdata[i+3];
+			time_max_TX_burst = (loc_TDMA_slot_length * CONF_TDMA_slot_duration) + ( (loc_TDMA_slot_length-1) *CONF_TDMA_slot_margin );
+			my_multiframe_ID = 0x0F & unFECdata[i+4];
+			my_multiframe_mask = (0xF0 & unFECdata[i+4]) >> 4;
+			my_multiframe_mask = LUT_multif_mask[my_multiframe_mask];
+			loc_power = ( 0xF0 & unFECdata[i+3] ) >> 4;
+			//printf("TDMAf:");
+			//for (j=0; j< 5; j++) {
+			//	printf(" %02X", unFECdata[i+j]);
+			//}
+			//printf ("\r\n");
+			//printf ("offs:%i length:%i multi_ID:%i multi_period:%i\r\n", offset_time_TX_slave, time_max_TX_burst, my_multiframe_ID, my_multiframe_period);
+			slave_alloc_RX_age = 0;
+		}
+		i=i+5;
+		loc_client_ID = unFECdata[i];
+	}
+	
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/TDMA.h b/NPR_FW_source_2020_06_29/NPR_14/source/TDMA.h
new file mode 100755
index 0000000..8824da0
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/TDMA.h
@@ -0,0 +1,45 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef TDMA_F4
+#define TDMA_F4
+
+void TDMA_init_all(void);
+
+unsigned char TDMA_byte_elaboration(unsigned char synchro);
+
+short int TDMA_TA_measure_single_frame(unsigned int frame_timer, unsigned char TDMA_byte, unsigned char client_ID, int frame_size_loc);
+
+void TDMA_init_TA(unsigned char client_ID, int TA_input);
+
+void TDMA_top_measure(void);
+
+void TDMA_FDD_up_top_measure(void);
+
+void TDMA_byte_RX_interp (unsigned char TDMA_byte, unsigned char client_ID_byte, unsigned char protocol, unsigned int RX_time);
+
+void TDMA_slave_timeout (void);
+
+void TDMA_master_allocation ();
+
+void TDMA_master_allocation_slow ();
+
+void TDMA_NULL_frame_init(int size);
+
+void TDMA_slave_alloc_exploitation(unsigned char* unFECdata, int unFECsize);
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/Virt_Chan.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/Virt_Chan.cpp
new file mode 100755
index 0000000..b0fab72
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/Virt_Chan.cpp
@@ -0,0 +1,26 @@
+#include "Virt_Chan.h"
+#include "mbed.h"
+
+int RTP_gateway (W5500_chip* W5500) {
+	static unsigned char RX_data[1600];
+	
+	static unsigned char IP_addr_1[6]={10,151,0,20};
+	static unsigned char eth_peer[8]={0x00,0x13,0x3b,0x73,0x12,0xae};
+	int RX_size=0;
+	int size_UDP;
+	int answer=0;
+	RX_size = W5500_read_received_size(W5500, 2); 
+	if (RX_size > 0) {
+		answer = 1; 
+		size_UDP = W5500_read_UDP_pckt(W5500, 2, RX_data);
+		
+		W5500_write_short(W5500, 0x0006, 0x09, eth_peer, 6);
+		W5500_write_short(W5500, 0x000C, 0x09, IP_addr_1, 4);
+		W5500_write_TX_buffer(W5500, 2, RX_data+8, size_UDP-8, 1);
+		
+
+	}
+	return answer;
+	
+}
+
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/Virt_Chan.h b/NPR_FW_source_2020_06_29/NPR_14/source/Virt_Chan.h
new file mode 100755
index 0000000..7893f43
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/Virt_Chan.h
@@ -0,0 +1,9 @@
+#ifndef VIRT_CHAN_F4
+#define VIRT_CHAN_F4
+
+#include "mbed.h"
+#include "W5500.h"
+
+int RTP_gateway (W5500_chip* W5500);
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/W5500.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/W5500.cpp
new file mode 100755
index 0000000..d49e500
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/W5500.cpp
@@ -0,0 +1,425 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "W5500.h"
+#include "mbed.h"
+#include "global_variables.h"
+#include "Eth_IPv4.h"
+
+void W5500_read_long(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* RX_data, int RX_size)
+{
+    unsigned char W5_command[20];
+	unsigned char trash[20];
+    W5_command[0] = W5500_addr / 256;
+    W5_command[1] = W5500_addr & 0xFF;
+    W5_command[2] = (bloc_addr * 0x08);
+    *(SPI_p_loc->cs)=0;
+	RX_data[0]=0;
+    
+	SPI_p_loc->spi_port->transfer_2 (W5_command, 3, trash, 3);
+    
+	SPI_p_loc->spi_port->transfer_2 (trash, RX_size, RX_data, RX_size);
+    wait_us(1);
+    *(SPI_p_loc->cs)=1;
+	wait_us(2);
+}
+
+void W5500_write_long(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* TX_data, int TX_size) {
+    unsigned char W5_command[4];
+	static unsigned char trash[1600];
+	
+    W5_command[0] = W5500_addr / 256;
+    W5_command[1] = W5500_addr & 0xFF;
+    W5_command[2] = (bloc_addr * 0x08) + 4;
+	SPI_p_loc->cs->write(0);
+	SPI_p_loc->spi_port->transfer_2 (W5_command, 3, trash, 3);
+	//wait_us(10);
+	
+	SPI_p_loc->spi_port->transfer_2 (TX_data, TX_size, trash, 0);
+	
+    wait_us(1);
+	SPI_p_loc->cs->write(1);
+	wait_us(2);
+}
+
+void W5500_read_short(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* RX_data_ext, int RX_size) {
+    unsigned char TX_data_loc[20];
+    unsigned char RX_data_loc[20];
+    int i;
+    TX_data_loc[0] = W5500_addr / 256;
+    TX_data_loc[1] = W5500_addr & 0xFF;
+    TX_data_loc[2] = (bloc_addr * 0x08) ;
+	SPI_p_loc->cs->write(0);
+	SPI_p_loc->spi_port->transfer_2 (TX_data_loc, RX_size+3, RX_data_loc, RX_size+3);
+    for (i=0; i < RX_size; i++) {
+        RX_data_ext[i] = RX_data_loc[i+3];
+    }
+    wait_us(1);
+	SPI_p_loc->cs->write(1);
+	wait_us(2);
+}
+
+void W5500_write_short(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* TX_data_ext, int TX_size) {
+    unsigned char TX_data_loc[10];
+	unsigned char trash[10];
+    int i;
+    TX_data_loc[0] = W5500_addr / 256;
+    TX_data_loc[1] = W5500_addr & 0xFF;
+    TX_data_loc[2] = (bloc_addr * 0x08) + 4;
+    for (i=0; i < TX_size; i++) {
+        TX_data_loc[i+3] = TX_data_ext[i];
+    }
+	SPI_p_loc->cs->write(0);
+	SPI_p_loc->spi_port->transfer_2 (TX_data_loc, TX_size+3, trash, 0);
+	wait_us(1);
+	SPI_p_loc->cs->write(1);
+	wait_us(2);
+}
+
+unsigned char W5500_read_byte(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr) {
+    unsigned char TX_data_loc[20];
+    unsigned char RX_data_loc[20];
+	unsigned char data_out;
+    TX_data_loc[0] = W5500_addr / 256;
+    TX_data_loc[1] = W5500_addr & 0xFF;
+    TX_data_loc[2] = (bloc_addr * 0x08) ;
+	SPI_p_loc->cs->write(0);
+	SPI_p_loc->spi_port->transfer_2 (TX_data_loc, 4, RX_data_loc, 4); 
+    wait_us(1);
+	SPI_p_loc->cs->write(1);
+    data_out = RX_data_loc[3]; 
+	return data_out;
+	wait_us(2);
+}
+
+void W5500_write_byte(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char data) {
+    unsigned char TX_data_loc[10];
+	unsigned char trash[10];
+    TX_data_loc[0] = W5500_addr / 256;
+    TX_data_loc[1] = W5500_addr & 0xFF;
+    TX_data_loc[2] = (bloc_addr * 0x08) + 4;
+    TX_data_loc[3] = data;
+	SPI_p_loc->cs->write(0);
+	SPI_p_loc->spi_port->transfer_2 (TX_data_loc, 4, trash, 0);
+	wait_us(1);
+	SPI_p_loc->cs->write(1);
+	wait_us(2);
+}
+
+
+void W5500_Phy_off_2sec(W5500_chip* SPI_p_loc) {
+    //unsigned char phy_config[1];
+    W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0x70);
+    wait(5);
+    W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0xF8);
+}
+
+int W5500_read_received_size(W5500_chip* SPI_p_loc, int sock_nb) {
+	int size=9999, previous_size=9999;
+	unsigned char data[10];
+	do {
+		previous_size = size;
+		W5500_read_short(SPI_p_loc, 0x0026, (sock_nb*4)+1, data, 2);
+		size = data[1] + data[0]*256;
+	} while (previous_size != size);
+		
+	//printf("size:%d\r\n", size);
+	return size;
+}
+
+int W5500_read_TX_free_size(W5500_chip* SPI_p_loc, int sock_nb) {
+	int size=9999, previous_size=9999;
+	unsigned char data[10];
+	do {
+		previous_size = size;
+		W5500_read_short(SPI_p_loc, 0x0020, (sock_nb*4)+1, data, 2);
+		size = data[1] + data[0]*256;
+	} while (previous_size != size);
+		
+	//printf("size:%d\r\n", size);
+	return size;
+}
+
+void W5500_read_RX_buffer(W5500_chip* SPI_p_loc, int sock_nb, unsigned char* data, int size) {
+	unsigned char read_pointer_raw[10];
+	unsigned short read_pointer;
+	W5500_read_short(SPI_p_loc, 0x0028, (sock_nb*4)+1, read_pointer_raw, 2);
+	read_pointer = read_pointer_raw[1] + read_pointer_raw[0] * 256;
+	W5500_read_long(SPI_p_loc, read_pointer, (sock_nb*4)+3, data, size);
+	read_pointer = read_pointer + size ;
+	read_pointer_raw[0] = read_pointer / 256;
+	read_pointer_raw[1] = read_pointer & 0xFF;
+	W5500_write_short(SPI_p_loc, 0x0028, (sock_nb*4)+1, read_pointer_raw, 2);
+	W5500_write_byte(SPI_p_loc, 0x0001, (sock_nb*4)+1, 0x40);
+}
+
+int W5500_read_UDP_pckt (W5500_chip* SPI_p_loc, int sock_nb, unsigned char* data) {
+	int size=0;
+	unsigned char read_pointer_raw[10];
+	unsigned char trash[20];
+	unsigned short read_pointer;
+	unsigned char W5_command[20];
+	W5500_read_short(SPI_p_loc, 0x0028, (sock_nb*4)+1, read_pointer_raw, 2);
+	read_pointer = read_pointer_raw[1] + read_pointer_raw[0] * 256;
+	// read first 8 bytes
+	W5_command[0] = read_pointer_raw[0];
+	W5_command[1] = read_pointer_raw[1];
+	W5_command[2] = ((sock_nb*4)+3) * 0x08;
+	SPI_p_loc->cs->write(0);
+	SPI_p_loc->spi_port->transfer_2 (W5_command, 3, trash, 3);
+	SPI_p_loc->spi_port->transfer_2 (trash, 8, data, 8);
+	size = data [7] + 256 * data[6];
+	SPI_p_loc->spi_port->transfer_2 (trash, size, data+8, size);
+	
+	size = size + 8;
+	wait_us(1);
+	SPI_p_loc->cs->write(1);
+	wait_us(2);
+	//printf ("size UDP:%d\r\n", size);
+	read_pointer = read_pointer + size ;
+		
+	read_pointer_raw[0] = read_pointer / 256;
+	read_pointer_raw[1] = read_pointer & 0xFF;
+	W5500_write_short(SPI_p_loc, 0x0028, (sock_nb*4)+1, read_pointer_raw, 2);
+	W5500_write_byte(SPI_p_loc, 0x0001, (sock_nb*4)+1, 0x40);//command receive
+	return size; 
+}
+
+int W5500_read_MAC_pckt (W5500_chip* SPI_p_loc, int sock_nb, unsigned char* data) {
+	int size=0;
+	unsigned char read_pointer_raw[10];
+	unsigned char trash[20];
+	unsigned short read_pointer;
+	unsigned char W5_command[20];
+	W5500_read_short(SPI_p_loc, 0x0028, (sock_nb*4)+1, read_pointer_raw, 2);
+	read_pointer = read_pointer_raw[1] + read_pointer_raw[0] * 256;
+	// read first 8 bytes
+	W5_command[0] = read_pointer_raw[0];
+	W5_command[1] = read_pointer_raw[1];
+	W5_command[2] = ((sock_nb*4)+3) * 0x08;
+	SPI_p_loc->cs->write(0);
+	SPI_p_loc->spi_port->transfer_2 (W5_command, 3, trash, 3);
+	SPI_p_loc->spi_port->transfer_2 (trash, 2, data, 2);
+	size = data [1] + 256 * data[0];
+	SPI_p_loc->spi_port->transfer_2 (trash, size-2, data+2, size-2);
+	
+	wait_us(1);
+	SPI_p_loc->cs->write(1);
+	wait_us(2);
+	//printf ("size UDP:%d\r\n", size);
+	read_pointer = read_pointer + size ;
+		
+	read_pointer_raw[0] = read_pointer / 256;
+	read_pointer_raw[1] = read_pointer & 0xFF;
+	W5500_write_short(SPI_p_loc, 0x0028, (sock_nb*4)+1, read_pointer_raw, 2);
+	W5500_write_byte(SPI_p_loc, 0x0001, (sock_nb*4)+1, 0x40);
+	return size; 
+}
+
+void W5500_write_TX_buffer(W5500_chip* SPI_p_loc, int sock_nb, unsigned char* data, int size, int send_mac) {
+	unsigned char write_pointer_raw[10];
+	unsigned short write_pointer;
+	W5500_read_short(SPI_p_loc, 0x0024, (sock_nb*4)+1, write_pointer_raw, 2);
+	write_pointer = write_pointer_raw[1] + write_pointer_raw[0] * 256;
+	W5500_write_long(SPI_p_loc, write_pointer, (sock_nb*4)+2, data, size);
+	write_pointer = write_pointer + size ;
+	write_pointer_raw[0] = write_pointer / 256;
+	write_pointer_raw[1] = write_pointer & 0xFF;
+	W5500_write_short(SPI_p_loc, 0x0024, (sock_nb*4)+1, write_pointer_raw, 2);
+	if (send_mac == 1) {
+		W5500_write_byte(SPI_p_loc, 0x0001, (sock_nb*4)+1, 0x21);
+	} else {
+		W5500_write_byte(SPI_p_loc, 0x0001, (sock_nb*4)+1, 0x20);
+	}
+}
+
+static int W5500_configured = 0; 	// 0 not yet configured
+									// 1 configured
+									// 2 waiting reconfigure
+									// 3 waiting reboot after reconfigure
+void W5500_re_configure (void) {
+	W5500_configured = 2; 
+	
+}
+
+void W5500_re_configure_gateway(W5500_chip* SPI_p_loc) {
+	unsigned char data[10];
+	if ( (LAN_conf_applied.LAN_def_route_activ) && (is_telnet_routed) && (is_TDMA_master) ) { 
+		IP_int2char (LAN_conf_applied.LAN_def_route, data);
+		W5500_write_long(SPI_p_loc, 0x0001, 0x00, data, 4); // gateway 
+	} else {
+		IP_int2char (0x01010101, data);
+		W5500_write_long(SPI_p_loc, 0x0001, 0x00, data, 4);
+	}	
+}
+
+void W5500_re_configure_periodic_call(W5500_chip* SPI_p_loc) {
+	unsigned char data[10];
+	if (W5500_configured == 4) { // reboot
+		//W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0xF8);//!!! 0xC8 0xF8
+		W5500_write_byte(SPI_p_loc, 0x002E, 0x00, (CONF_Eth_mode << 3) + 0xC0);//!!! 0xC8 0xF8
+		W5500_configured = 1; //configured
+	}
+	if (W5500_configured == 3) { //wait 
+		W5500_configured = 4;
+	}
+	if (W5500_configured == 2) { //reconfigure
+		IP_int2char (LAN_conf_applied.LAN_modem_IP, data);
+		W5500_write_long(SPI_p_loc, 0x000F, 0x00, data, 4); // modem IP
+		IP_int2char (LAN_conf_applied.LAN_subnet_mask, data);
+		W5500_write_long(SPI_p_loc, 0x0005, 0x00, data, 4); // net mask
+		
+		if ( (LAN_conf_applied.LAN_def_route_activ) && (is_telnet_routed) && (is_TDMA_master) ) { 
+			IP_int2char (LAN_conf_applied.LAN_def_route, data);
+			W5500_write_long(SPI_p_loc, 0x0001, 0x00, data, 4); // gateway 
+		} else {
+			IP_int2char (0x01010101, data);
+			W5500_write_long(SPI_p_loc, 0x0001, 0x00, data, 4);
+		}
+		//W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0x78); // 0x48 0x78
+		W5500_write_byte(SPI_p_loc, 0x002E, 0x00, (CONF_Eth_mode << 3) + 0x40); // 0x48 0x78
+		W5500_configured = 3; //waiting reboot
+	}
+	
+}
+
+void W5500_initial_configure(W5500_chip* SPI_p_loc) {
+    // reset
+    W5500_write_byte(SPI_p_loc, 0x0000, 0x00, 0x80);//0x90
+	wait_ms(500);
+	W5500_write_byte(SPI_p_loc, 0x0000, 0x00, 0x00);//0x10
+	//wait_ms(1600);
+	//W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0xC8);
+	//W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0x78);//48 78 for 10MB full duplex / 40 half duplex !!!
+	W5500_write_byte(SPI_p_loc, 0x002E, 0x00, (CONF_Eth_mode << 3) + 0x40);//48 78 for 10MB full duplex / 40 half duplex !!!
+	wait_ms(1600);
+	//W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0xF8);//c8 F8 for 10MB full duplex / c0 half duplexc8 !!!
+	W5500_write_byte(SPI_p_loc, 0x002E, 0x00, (CONF_Eth_mode << 3) + 0xC0);//c8 F8 for 10MB full duplex / c0 half duplexc8 !!!
+	//W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0xC8);
+	//wait_ms(1600);
+    
+	//W5500_write_byte(SPI_p_loc, 0x002E, 0x00, 0xC0);
+    
+    //IP & MAC config
+    //unsigned char data[20]={0x00,0x2E,0x00,4,5,6, 10,151,20,254};
+	//unsigned char data[20]={0x00,0x2E,0x00,4,5,6, 192,168,0,254};
+	unsigned char data[20]={0x00,0x2E,0x00,4,5,6};
+	//W5500_write_long(SPI_p_loc, 0x0009, 0x00, data, 6); // modem MAC
+	//W5500_write_long(SPI_p_loc, 0x0009, 0x00, LAN_conf_applied.modem_MAC, 6); // modem MAC
+	W5500_write_long(SPI_p_loc, 0x0009, 0x00, CONF_modem_MAC, 6); // modem MAC
+	IP_int2char (LAN_conf_applied.LAN_modem_IP, data);
+	W5500_write_long(SPI_p_loc, 0x000F, 0x00, data, 4); // modem IP
+	if ( (is_telnet_routed) && (is_TDMA_master) ) { 
+		IP_int2char (LAN_conf_applied.LAN_def_route, data);
+		W5500_write_long(SPI_p_loc, 0x0001, 0x00, data, 4); // gateway 
+	} else {
+		IP_int2char (0, data);
+		W5500_write_long(SPI_p_loc, 0x0001, 0x00, data, 4);
+	}
+	IP_int2char (LAN_conf_applied.LAN_subnet_mask, data);
+	W5500_write_long(SPI_p_loc, 0x0005, 0x00, data, 4); // net mask
+	
+    W5500_write_byte(SPI_p_loc, 0x0018, 0x00, 0x01);//sock interrupt mask 
+	
+	// Socket Read buffer size
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x01, 0x08); //0 macraw 08
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x05, 0x02); //1 telnet 02
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x09, 0x04); //2 RTP 04
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x0D, 0x02); //3 DHCP 02
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x11, 0x00); //4 
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x15, 0x00); //5 
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x19, 0x00); //6 
+	W5500_write_byte(SPI_p_loc, 0x001E, 0x1D, 0x00); //7 
+	
+	// Socket Write buffer size
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x01, 0x04); //0 macraw
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x05, 0x02); //1 telnet
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x09, 0x04); //2 RTP
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x0D, 0x02); //3 DHCP
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x11, 0x02); //4 UDP_FDD
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x15, 0x00); //5 
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x19, 0x00); //6 
+	W5500_write_byte(SPI_p_loc, 0x001F, 0x1D, 0x00); //7 
+	
+	// Socket 0 MAC RAW for packet switching
+	W5500_write_byte(SPI_p_loc, 0x0000, 0x01, 0x34); //config B4 for classic
+	W5500_write_byte(SPI_p_loc, 0x002C, 0x01, 0x04); //Interrupt mask : RECV
+	wait_ms(10);
+	W5500_write_byte(SPI_p_loc, 0x0001, 0x01, 0x01); //open
+	
+    // Socket 1 telnet 
+    W5500_write_byte(SPI_p_loc, 0x0000, 0x05, 0x01); //config
+    wait_ms(10);
+    data[0]=0x00; //port 0d23
+    data[1]=0x17;
+    W5500_write_short(SPI_p_loc, 0x0004, 0x05, data, 2); //port 23 (0x17)
+	//W5500_write_byte(SPI_p_loc, 0x002C, 0x05, 0x00); //interrupt mask
+	
+	// Socket 2 RTP port 1519
+	W5500_write_byte(SPI_p_loc, 0x0000, 0x09, 0x42); //config
+	wait_ms(10);
+	data[0]=0x05; //port 0d1519
+    data[1]=0xEF;
+	W5500_write_short(SPI_p_loc, 0x0004, 0x09, data, 2); //port rx 1519 
+	data[0]=0x05; //port 0d1516
+    data[1]=0xEC;
+	W5500_write_short(SPI_p_loc, 0x0010, 0x09, data, 2); //port tx 1516
+	W5500_write_byte(SPI_p_loc, 0x0001, 0x09, 0x01); // open
+	data[0]=10;
+	data[1]=151;
+	data[2]=0;
+	data[3]=60;
+	W5500_write_short(SPI_p_loc, 0x000C, 0x09, data, 4); //IP destination 10.151.0.21
+	
+	// Socket 3 DHCP server
+	W5500_write_byte(SPI_p_loc, 0x0000, 0x0D, 0x02); //config
+	wait_ms(10);
+	data[0]=0x00; //port 0d67
+    data[1]=0x43;
+	W5500_write_short(SPI_p_loc, 0x0004, 0x0D, data, 2); //port rx 67 
+	data[0]=0x00; //port 0d68
+    data[1]=0x44;
+	W5500_write_short(SPI_p_loc, 0x0010, 0x0D, data, 2); //port tx 68
+	W5500_write_byte(SPI_p_loc, 0x0001, 0x0D, 0x01); // open
+	data[0]=255;
+	data[1]=255;
+	data[2]=255;
+	data[3]=255;
+	data[4]=255;
+	data[5]=255;
+	W5500_write_short(SPI_p_loc, 0x000C, 0x0D, data, 4); //IP destination 255.255.255.255
+	W5500_write_short(SPI_p_loc, 0x0006, 0x0D, data, 6);
+	
+	// Socket 4 UDP_FDD
+	W5500_write_byte(SPI_p_loc, 0x0000, 0x11, 0x42); //config
+	wait_ms(10);
+	data[0]=0x1A; //port TX 0d6716 = 0x1A3E
+    data[1]=0x3E;
+	W5500_write_short(SPI_p_loc, 0x0004, 0x11, data, 2);
+	data[0]=0x1A; //port RX 0d6718 = 0x1A3C
+    data[1]=0x3C;
+	W5500_write_short(SPI_p_loc, 0x0010, 0x11, data, 2);
+	W5500_write_byte(SPI_p_loc, 0x0001, 0x11, 0x01); // open
+	IP_int2char (CONF_master_down_IP, data);
+	W5500_write_short(SPI_p_loc, 0x000C, 0x11, data, 4);
+	// Socket 5
+	
+	// Socket 6
+	
+	// Socket 7
+	W5500_configured = 1;
+}
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/W5500.h b/NPR_FW_source_2020_06_29/NPR_14/source/W5500.h
new file mode 100755
index 0000000..ef46243
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/W5500.h
@@ -0,0 +1,66 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef W5500_F4
+#define W5500_F4
+
+#include "mbed.h"
+
+struct W5500_chip{
+    SPI* spi_port;
+    DigitalOut* cs;
+	DigitalIn* interrupt;
+	unsigned char sock_interrupt;
+};
+
+void W5500_read_long(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* RX_data, int RX_size);
+
+void W5500_write_long(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* TX_data, int TX_size);
+
+void W5500_read_short(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* RX_data_ext, int RX_size);
+
+void W5500_read_char(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, char* RX_data_ext, int RX_size);
+
+void W5500_write_short(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char* TX_data_ext, int TX_size);
+
+unsigned char W5500_read_byte(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr);
+
+void W5500_write_byte(W5500_chip* SPI_p_loc, unsigned int W5500_addr, unsigned char bloc_addr, unsigned char data);
+
+void W5500_Phy_off_2sec(W5500_chip* SPI_p_loc);
+
+int W5500_read_received_size(W5500_chip* SPI_p_loc, int sock_nb);
+
+int W5500_read_TX_free_size(W5500_chip* SPI_p_loc, int sock_nb);
+
+void W5500_read_RX_buffer(W5500_chip* SPI_p_loc, int sock_nb,  unsigned char* data, int size);
+
+int W5500_read_UDP_pckt (W5500_chip* SPI_p_loc, int sock_nb, unsigned char* data);
+
+int W5500_read_MAC_pckt (W5500_chip* SPI_p_loc, int sock_nb, unsigned char* data);
+
+void W5500_write_TX_buffer(W5500_chip* SPI_p_loc, int sock_nb, unsigned char* data, int size, int send_mac);
+
+void W5500_re_configure (void);
+
+void W5500_re_configure_gateway(W5500_chip* SPI_p_loc);
+
+void W5500_re_configure_periodic_call(W5500_chip* SPI_p_loc);
+
+void W5500_initial_configure(W5500_chip* SPI_p_loc); 
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/config_flash.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/config_flash.cpp
new file mode 100755
index 0000000..7ff14f5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/config_flash.cpp
@@ -0,0 +1,274 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "config_flash.h"
+#include "mbed.h"
+#include "global_variables.h"
+#include "Eth_IPv4.h"
+#include "HMI_telnet.h"
+#include "TDMA.h"
+
+static unsigned char raw_config_data[260];
+static unsigned int config_index;
+
+unsigned int virt_EEPROM_read(unsigned char* out_data) { //reads 256 Bytes of virtual eeprom data
+	FlashIAP my_loc_flash;
+	unsigned char loc_index_char[6];
+	unsigned int loc_index_int, highest_index_seen;
+	unsigned int loc_address;
+	int i; 
+	my_loc_flash.init();
+	highest_index_seen = 0;
+	//for (i=0; i<256; i++) {
+	for (i=0; i<64; i++) {
+		my_loc_flash.read(loc_index_char, NFPR_config_addr_begin+(i*256), 4);
+		loc_index_int = (loc_index_char[0] << 24) + (loc_index_char[1] << 16) + (loc_index_char[2] << 8) + loc_index_char[3];
+		if ( (loc_index_int != 0xFFFFFFFF) && (loc_index_int > highest_index_seen) ) {
+			highest_index_seen = loc_index_int;
+		}
+	}
+	if (highest_index_seen != 0) { //valid entry found
+		//loc_address = NFPR_config_addr_begin + (highest_index_seen & 0xFF)*256;
+		loc_address = NFPR_config_addr_begin + (highest_index_seen & 0x3F)*256;
+		my_loc_flash.read(out_data, loc_address, 256);
+	}
+	my_loc_flash.deinit();
+	return highest_index_seen;
+}
+
+unsigned int virt_EEPROM_write(unsigned char* in_data, unsigned int previous_index) {
+	unsigned int new_index;
+	unsigned int loc_address;
+	FlashIAP my_loc_flash;
+	if (previous_index == 0) {
+		previous_index = 0xFF; //next index will be 0x100, errase first sector
+	}
+	new_index = previous_index + 1;
+	//loc_address = NFPR_config_addr_begin + (new_index & 0xFF)*256; //previous config 64kB
+	loc_address = NFPR_config_addr_begin + (new_index & 0x3F)*256; //previous config 
+	my_loc_flash.init();
+	if ((new_index & 7) == 0) { //new sector, errase sector
+		HMI_printf ("errase sector:%X\r\n", loc_address);
+		my_loc_flash.erase(loc_address, 2048);
+	}
+	// writes new index
+	in_data[0] = (new_index & 0xFF000000) >> 24;
+	in_data[1] = (new_index & 0xFF0000) >> 16;
+	in_data[2] = (new_index & 0xFF00) >> 8;
+	in_data[3] = new_index & 0xFF;
+	my_loc_flash.program(in_data, loc_address, 256);
+	HMI_printf("write success\r\n");
+	my_loc_flash.deinit();
+	return new_index;
+}
+
+//void virt_EEPROM_debug_read(void) {
+//	int i;
+//	unsigned int loc_address;
+//	unsigned char loc_data[260];
+//	FlashIAP my_loc_flash;
+//	my_loc_flash.init();
+//	//for (i=0; i<256; i++) {
+//	for (i=0; i<64; i++) {
+//		//loc_address = NFPR_config_addr_begin + (i & 0xFF)*256;
+//		loc_address = NFPR_config_addr_begin + (i & 0x3F)*256;
+//		my_loc_flash.read(loc_data, loc_address, 256);
+//		HMI_printf("addr:%X data:%02X %02X %02X %02X %02X %02X %02X %02X\r\n", loc_address, loc_data[0], loc_data[1], loc_data[2], loc_data[3], loc_data[4], loc_data[5], loc_data[6], loc_data[7]);
+//		wait_ms(10);
+//	}
+//	my_loc_flash.deinit();
+//}
+
+void virt_EEPROM_errase_all(void) {
+	FlashIAP my_loc_flash;
+	my_loc_flash.init();
+	//my_loc_flash.erase(NFPR_config_addr_begin, 0x10000); //previous config 64kB
+	my_loc_flash.erase(NFPR_config_addr_begin, 0x4000); //config 16kB
+	my_loc_flash.deinit();
+}
+
+// higher level functions
+
+void NFPR_config_read(AnalogIn* analog_pin) {
+	int i;
+	unsigned char default_config[260] = NFPR_default_config;
+	config_index = virt_EEPROM_read(raw_config_data);
+	if (config_index == 0) { //no previous config found
+		for (i=0; i<256; i++) {
+			raw_config_data[i] = default_config[i];
+		}
+		//MAC random 2 LSB values
+		raw_config_data[58] = NFPR_random_generator(analog_pin);
+		raw_config_data[59] = NFPR_random_generator(analog_pin);
+		raw_config_data[5] = raw_config_data[58];//callsign 1st char
+		raw_config_data[6] = raw_config_data[59];//callsign 2nd char
+		config_index = virt_EEPROM_write (raw_config_data, config_index);//save the MAC
+	}
+	apply_config_from_raw_string(raw_config_data);
+	if (is_TDMA_master == 1) {
+		my_client_radio_connexion_state = 2;
+	} else {
+		my_client_radio_connexion_state = 1;
+		my_radio_client_ID = 0x7E;
+	}
+}
+
+unsigned char NFPR_random_generator(AnalogIn* analog_pin) {
+	unsigned short interm_random;
+	unsigned char random_8;
+	//int i, j;
+	int i;
+	random_8 = 0;
+	for (i=0; i<8; i++) {
+		interm_random = analog_pin->read_u16();
+		interm_random = (interm_random & 0x10)>>4;
+		interm_random = (interm_random << i);
+		random_8 = random_8 + interm_random;
+		wait_ms(4);
+	}
+	return random_8;
+}
+
+unsigned int NFPR_config_save(void) {
+	if ( (CONF_radio_my_callsign[0] == 0) || (CONF_radio_my_callsign[2] == 0) ) {
+		HMI_printf("ERROR : not yet configured\r\n");
+		
+	} else {
+		write_config_to_raw_string(raw_config_data);
+		config_index = virt_EEPROM_write (raw_config_data, config_index);
+	}
+	return config_index;
+}
+
+void apply_config_from_raw_string(unsigned char* data_r) {
+	int i;
+	unsigned char modul_temp;
+	is_TDMA_master = data_r[4];
+	for (i=0; i<16; i++) {
+		CONF_radio_my_callsign[i] = data_r[5+i];
+	}
+	CONF_radio_my_callsign[15] = 0;
+	is_telnet_active = data_r[21];
+	modul_temp = (data_r[22] & 0x3F);
+	if ( ((modul_temp>=11)&&(modul_temp<=14)) || ((modul_temp>=20)&&(modul_temp<=24)) ) {
+		CONF_radio_modulation = modul_temp;
+	} else {
+		CONF_radio_modulation = 24;
+	}
+	CONF_frequency_band = (data_r[22] & 0xC0) >> 6;
+	//printf("freq_band:%X modul:%i\r\n", CONF_frequency_band, modul_temp);
+	CONF_radio_frequency = data_r[23];
+	CONF_radio_network_ID = data_r[24];
+	
+	//specific for clients
+	CONF_radio_static_IP_requested = data_r[25];
+	CONF_radio_IP_size_requested = IP_char2int(data_r+26);
+	LAN_conf_saved.DHCP_server_active = data_r[30];
+	LAN_conf_applied.DHCP_server_active = data_r[30];
+	
+	//specific for master
+	LAN_conf_saved.LAN_modem_IP = IP_char2int(data_r+31);
+	LAN_conf_applied.LAN_modem_IP = IP_char2int(data_r+31);
+	LAN_conf_saved.LAN_subnet_mask = IP_char2int(data_r+35);
+	LAN_conf_applied.LAN_subnet_mask = IP_char2int(data_r+35);
+	CONF_radio_IP_size = IP_char2int(data_r+39);
+	LAN_conf_saved.LAN_DNS_activ = data_r[43];
+	LAN_conf_applied.LAN_DNS_activ = data_r[43];
+	LAN_conf_saved.LAN_DNS_value = IP_char2int(data_r+44);
+	LAN_conf_applied.LAN_DNS_value = IP_char2int(data_r+44);
+	LAN_conf_saved.LAN_def_route_activ = data_r[48];
+	LAN_conf_applied.LAN_def_route_activ = data_r[48];
+	LAN_conf_saved.LAN_def_route = IP_char2int(data_r+49);
+	LAN_conf_applied.LAN_def_route = IP_char2int(data_r+49);
+	CONF_radio_IP_start = IP_char2int(data_r+53);
+	is_telnet_routed = data_r[57];
+	CONF_modem_MAC[0] = 0x4E;//N
+	CONF_modem_MAC[1] = 0x46;//F
+	CONF_modem_MAC[2] = 0x50;//P
+	CONF_modem_MAC[3] = 0x52;//R
+	CONF_modem_MAC[4] = data_r[58];
+	CONF_modem_MAC[5] = data_r[59];
+	CONF_radio_default_state_ON_OFF = data_r[60];
+	CONF_radio_PA_PWR = data_r[61];
+	
+	CONF_frequency_HD = ((data_r[64]) <<8 ) | data_r[65];
+	if ( (CONF_frequency_HD == 0x0000) || (CONF_frequency_HD > FREQ_MAX_RAW) ) {
+		CONF_frequency_HD = CONF_DEF_FREQ; // force to default frequency
+	}
+	CONF_freq_shift = ((data_r[66]) <<8) | data_r[67];
+	CONF_transmission_method = data_r[68];
+	CONF_master_FDD = data_r[69];
+	CONF_master_down_IP = IP_char2int(data_r+70);
+	if ((data_r[74] >= 0xF0) && (data_r[74] <= 0xF7)){
+		CONF_Eth_mode = data_r[74] - 0xF0;	
+	}
+	else {
+		CONF_Eth_mode = 0x07;	
+	}
+	if (LAN_conf_applied.DHCP_server_active == 1) {
+		LAN_conf_applied.DHCP_range_start = CONF_radio_IP_start;
+		LAN_conf_applied.DHCP_range_size = CONF_radio_IP_size_requested;
+		
+	}
+	if ( (is_TDMA_master == 1) && (CONF_master_FDD == 1) ) { // FDD Master down
+		G_FDD_trig_pin->output();
+	}
+	if ( (is_TDMA_master == 1) && (CONF_master_FDD == 2) ) {// FDD master up
+		G_FDD_trig_IRQ->rise(&TDMA_FDD_up_top_measure);
+	}
+}
+
+void write_config_to_raw_string (unsigned char* data_r) {
+	int i;
+	data_r[4] = is_TDMA_master;
+	for (i=0; i<16; i++) {
+		data_r[5+i] = CONF_radio_my_callsign[i];
+	}
+	data_r[21] = is_telnet_active;
+	data_r[22] = ( (CONF_frequency_band << 6) & 0xC0) + (CONF_radio_modulation & 0x3F);
+	data_r[23] = CONF_radio_frequency;
+	data_r[24] = CONF_radio_network_ID;
+	
+	//specific for clients
+	data_r[25] = CONF_radio_static_IP_requested;
+	IP_int2char(CONF_radio_IP_size_requested, data_r+26); 
+	data_r[30] = LAN_conf_saved.DHCP_server_active;
+	
+	//specific for master
+	IP_int2char(LAN_conf_saved.LAN_modem_IP, data_r+31);
+	IP_int2char(LAN_conf_saved.LAN_subnet_mask, data_r+35);
+	IP_int2char(CONF_radio_IP_size, data_r+39);
+	data_r[43] = LAN_conf_saved.LAN_DNS_activ;
+	IP_int2char(LAN_conf_saved.LAN_DNS_value, data_r+44);
+	data_r[48] = LAN_conf_saved.LAN_def_route_activ;
+	IP_int2char(LAN_conf_saved.LAN_def_route, data_r+49);
+	IP_int2char(CONF_radio_IP_start, data_r+53);
+	data_r[57] = is_telnet_routed;
+	data_r[58] = CONF_modem_MAC[4];
+	data_r[59] = CONF_modem_MAC[5];
+	data_r[60] = CONF_radio_default_state_ON_OFF;
+	data_r[61] = CONF_radio_PA_PWR;
+	
+	data_r[64] = (CONF_frequency_HD & 0xFF00)>>8;
+	data_r[65] = (CONF_frequency_HD & 0x00FF);
+	data_r[66] = (CONF_freq_shift & 0xFF00)>>8;
+	data_r[67] = (CONF_freq_shift & 0x00FF);
+	data_r[68] = CONF_transmission_method;
+	data_r[69] = CONF_master_FDD;
+	IP_int2char(CONF_master_down_IP, data_r+70);
+	data_r[74] = CONF_Eth_mode + 0xF0;
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/config_flash.h b/NPR_FW_source_2020_06_29/NPR_14/source/config_flash.h
new file mode 100755
index 0000000..46983a2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/config_flash.h
@@ -0,0 +1,84 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2018 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef CONFIG_FLASH_F4
+#define CONFIG_FLASH_F4
+
+#include "mbed.h"
+
+//#define NFPR_config_addr_begin 0x08030000
+#define NFPR_config_addr_begin 0x0803C000
+
+#define NFPR_default_config { \
+	0,0,0,0, /*		index*/\
+	0, /*			is_master*/\ 
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /*callsign*/\ 
+	1, /*			telnet_active*/\
+	24, /*			modulation*/\
+	175, /*			frequency (175 = 437MHz)*/\
+	0, /*			radio_netw_ID*/\
+	0, /*			client_static_IP*/\
+	0,0,0,1, /*		client_req_size*/\
+	1, /*			DHCP server active*/\
+	44,168,40,170, /*	modem_IP*/\
+	255,255,255,0, /*netmask*/\
+	0,0,0,32, /*	IP_size*/\
+	1, /*			DNS_active*/\
+	1,1,1,1, /*		DNS_value*/\
+	1, /*			def_route_active*/\
+	44,168,40,174, /*	def_route_val*/\
+	44,168,40,65, /*IP_begin*/\
+	1, /*			telnet_routed*/\
+	0,0, /*			MAC 2 LS bytes*/\
+	0, /*			radio_on_at_start*/\
+	127, /*			RF_power*/\
+	0,0, /*			checksum*/\
+	66, 104, /*		frequency MSB LSB 437.000*/\
+	00, 00,  /*		frequency shift MSB LSB 0*/\
+	0, /*			transmission method 0=IP 1=Ethernet*/\
+	0, /*			master_FDD 0=no 1=down 2=up*/\
+	44,168,40,252,/*master_FDD_down_IP*/\
+	7, /*			CONF_Eth*/\
+	0,0,0,0,0,0,0,0,0,0,0,0,0, /*static client 0 24 entries*/\
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 /*static client 7*/\
+}
+
+unsigned int virt_EEPROM_read(unsigned char* data);
+
+unsigned char NFPR_random_generator(AnalogIn* analog_pin);
+
+unsigned int virt_EEPROM_write(unsigned char* in_data, unsigned int previous_index);
+
+void virt_EEPROM_errase_all(void);
+
+void virt_EEPROM_debug_read(void);
+
+void apply_config_from_raw_string(unsigned char* data_r);
+
+void write_config_to_raw_string (unsigned char* data_r);
+
+void NFPR_config_read(AnalogIn* analog_pin);
+
+unsigned int NFPR_config_save(void);
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/drivers/radio/Si446x/si446x_patch.h b/NPR_FW_source_2020_06_29/NPR_14/source/drivers/radio/Si446x/si446x_patch.h
new file mode 100755
index 0000000..97734e8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/drivers/radio/Si446x/si446x_patch.h
@@ -0,0 +1,80 @@
+// COPYRIGHT=2015 Silicon Laboratories, Inc.
+// GENERATED=09:13 October 20 2015
+// ROMID=0x06
+// FUNCTION=TEST
+// MAJOR=0
+// MINOR=0
+// BUILD=0
+// PATCHID=0xCA90
+// REQUIRES=NONE
+// SIZE=512
+// CRCT=0x714b
+
+#define SI446X_PATCH_ROMID  00
+#define SI446X_PATCH_ID     00
+
+#define SI446X_PATCH_CMDS                   \
+0x08,0x04,0x21,0x71,0x4B,0x00,0x00,0xDC,0x95, \
+0x08,0x05,0xA6,0x22,0x21,0xF0,0x41,0x5B,0x26, \
+0x08,0xE2,0x2F,0x1C,0xBB,0x0A,0xA8,0x94,0x28, \
+0x08,0x05,0x87,0x67,0xE2,0x58,0x1A,0x07,0x5B, \
+0x08,0xE1,0xD0,0x72,0xD8,0x8A,0xB8,0x5B,0x7D, \
+0x08,0x05,0x11,0xEC,0x9E,0x28,0x23,0x1B,0x6D, \
+0x08,0xE2,0x4F,0x8A,0xB2,0xA9,0x29,0x14,0x13, \
+0x08,0x05,0xD1,0x2E,0x71,0x6A,0x51,0x4C,0x2C, \
+0x08,0xE5,0x80,0x27,0x42,0xA4,0x69,0xB0,0x7F, \
+0x08,0x05,0xAA,0x81,0x2A,0xBD,0x45,0xE8,0xA8, \
+0x08,0xEA,0xE4,0xF0,0x24,0xC9,0x9F,0xCC,0x3C, \
+0x08,0x05,0x08,0xF5,0x05,0x04,0x27,0x62,0x98, \
+0x08,0xEA,0x6B,0x62,0x84,0xA1,0xF9,0x4A,0xE2, \
+0x08,0x05,0xE9,0x77,0x05,0x4F,0x84,0xEE,0x35, \
+0x08,0xE2,0x43,0xC3,0x8D,0xFB,0xAD,0x54,0x25, \
+0x08,0x05,0x14,0x06,0x5E,0x39,0x36,0x2F,0x45, \
+0x08,0xEA,0x0C,0x1C,0x74,0xD0,0x11,0xFC,0x32, \
+0x08,0x05,0xDA,0x38,0xBA,0x0E,0x3C,0xE7,0x8B, \
+0x08,0xEA,0xB0,0x09,0xE6,0xFF,0x94,0xBB,0xA9, \
+0x08,0x05,0xD7,0x11,0x29,0xFE,0xDC,0x71,0xD5, \
+0x08,0xEA,0x7F,0x83,0xA7,0x60,0x90,0x62,0x18, \
+0x08,0x05,0x84,0x7F,0x6A,0xD1,0x91,0xC6,0x52, \
+0x08,0xEA,0x2A,0xD8,0x7B,0x8E,0x4A,0x9F,0x91, \
+0x08,0x05,0xBD,0xAA,0x9D,0x16,0x18,0x06,0x15, \
+0x08,0xE2,0x55,0xAD,0x2D,0x0A,0x14,0x1F,0x5D, \
+0x08,0x05,0xD3,0xE0,0x7C,0x39,0xCF,0x01,0xF0, \
+0x08,0xEF,0x3A,0x91,0x72,0x6A,0x03,0xBB,0x96, \
+0x08,0xE7,0x83,0x6D,0xA4,0x92,0xFC,0x13,0xA7, \
+0x08,0xEF,0xF8,0xFD,0xCF,0x62,0x07,0x6F,0x1E, \
+0x08,0xE7,0x4C,0xEA,0x4A,0x75,0x4F,0xD6,0xCF, \
+0x08,0xE2,0xF6,0x11,0xE4,0x26,0x0D,0x4D,0xC6, \
+0x08,0x05,0xFB,0xBF,0xE8,0x07,0x89,0xC3,0x51, \
+0x08,0xEF,0x82,0x27,0x04,0x3F,0x96,0xA8,0x58, \
+0x08,0xE7,0x41,0x29,0x3C,0x75,0x2A,0x03,0x1C, \
+0x08,0xEF,0xAF,0x59,0x98,0x36,0xAA,0x0F,0x06, \
+0x08,0xE6,0xF6,0x93,0x41,0x2D,0xEC,0x0E,0x99, \
+0x08,0x05,0x29,0x19,0x90,0xE5,0xAA,0x36,0x40, \
+0x08,0xE7,0xFB,0x68,0x10,0x7D,0x77,0x5D,0xC0, \
+0x08,0xE7,0xCB,0xB4,0xDD,0xCE,0x90,0x54,0xBE, \
+0x08,0xE7,0x72,0x8A,0xD6,0x02,0xF4,0xDD,0xCC, \
+0x08,0xE7,0x6A,0x21,0x0B,0x02,0x86,0xEC,0x15, \
+0x08,0xE7,0x7B,0x7C,0x3D,0x6B,0x81,0x03,0xD0, \
+0x08,0xEF,0x7D,0x61,0x36,0x94,0x7C,0xA0,0xDF, \
+0x08,0xEF,0xCC,0x85,0x3B,0xDA,0xE0,0x5C,0x1C, \
+0x08,0xE7,0xE3,0x75,0xBB,0x39,0x22,0x4B,0xA8, \
+0x08,0xEF,0xF9,0xCE,0xE0,0x5E,0xEB,0x1D,0xCB, \
+0x08,0xE7,0xBD,0xE2,0x70,0xD5,0xAB,0x4E,0x3F, \
+0x08,0xE7,0xB7,0x8D,0x20,0x68,0x6B,0x09,0x52, \
+0x08,0xEF,0xA1,0x1B,0x90,0xCD,0x98,0x00,0x63, \
+0x08,0xEF,0x54,0x67,0x5D,0x9C,0x11,0xFC,0x45, \
+0x08,0xE7,0xD4,0x9B,0xC8,0x97,0xBE,0x8A,0x07, \
+0x08,0xEF,0x52,0x8D,0x90,0x63,0x73,0xD5,0x2A, \
+0x08,0xEF,0x03,0xBC,0x6E,0x1C,0x76,0xBE,0x4A, \
+0x08,0xE7,0xC2,0xED,0x67,0xBA,0x5E,0x66,0x21, \
+0x08,0xEF,0xE7,0x3F,0x87,0xBE,0xE0,0x7A,0x6D, \
+0x08,0xE7,0xC9,0x70,0x93,0x1D,0x64,0xF5,0x6C, \
+0x08,0xEF,0xF5,0x28,0x08,0x34,0xB3,0xB6,0x2C, \
+0x08,0xEF,0x3A,0x0A,0xEC,0x0F,0xDB,0x56,0xCA, \
+0x08,0xEF,0x39,0xA0,0x6E,0xED,0x79,0xD0,0x24, \
+0x08,0xE7,0x6C,0x0B,0xAF,0xA9,0x4E,0x40,0xB5, \
+0x08,0xE9,0xB9,0xAF,0xBF,0x25,0x50,0xD1,0x37, \
+0x08,0x05,0x9E,0xDB,0xDE,0x3F,0x94,0xE9,0x6B, \
+0x08,0xEC,0xC5,0x05,0xAA,0x57,0xDC,0x8A,0x5E, \
+0x08,0x05,0x70,0xDA,0x84,0x84,0xDD,0xCA,0x90
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/ext_SRAM2.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/ext_SRAM2.cpp
new file mode 100755
index 0000000..7394520
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/ext_SRAM2.cpp
@@ -0,0 +1,246 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifdef EXT_SRAM_USAGE
+
+#include "mbed.h"
+#include "global_variables.h"
+#include "ext_SRAM2.h"
+
+static unsigned char trash[350];
+static unsigned short int extSRAM_FIFOs[8][94];// 8 FIFO of pointers to extSRAM
+static unsigned char extSRAM_filling[374];// 0 : empty frame slot; 1: occupied frame slot
+static int extSRAM_total_filling = 0;
+static unsigned char extSRAM_pkt_timer[374];// timer of each frame
+static unsigned short int extSRAM_pkt_size[374];// size of each frame
+static unsigned char extSRAM_FIFO_index_read[8];//Read pointers of FIFO
+static unsigned char extSRAM_FIFO_index_write[8];//write pointers of FIFO
+static unsigned char extSRAM_FIFO_filling[8];
+
+void ext_SRAM_init(void) {
+	int i;
+	int j;
+	for (i=0; i<8; i++) {
+		extSRAM_FIFO_index_read[i] = 0;
+		extSRAM_FIFO_index_write[i] = 0;
+		extSRAM_FIFO_filling[i] = 0;
+	}
+	extSRAM_total_filling = 0;
+}
+
+void ext_SRAM_set_mode(ext_SRAM_chip* loc_SPI) {
+	static unsigned char command[6] = {0x01, 0x40, 0x00, 0x00};
+	loc_SPI->cs->write(0);
+	loc_SPI->spi_port->transfer_2 (command, 2, trash, 2);
+	loc_SPI->cs->write(1);
+}
+
+/*
+void ext_SRAM_read2(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size) {
+	static unsigned char command[6] = {0x03, 0x00, 0x00, 0x00};
+	loc_SPI->cs->write(0);
+	command[3] = address & 0xFF;
+	command[2] = (address & 0xFF00) >> 8;
+	command[1] = (address & 0xFF0000) >> 16;
+	loc_SPI->spi_port->transfer_2 (command, 4, trash, 4);
+	loc_SPI->spi_port->transfer_2 (trash, size, loc_data, size);
+	loc_SPI->cs->write(1);
+}
+*/
+
+void ext_SRAM_write(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size) {
+	//static unsigned char trash[350];
+	static unsigned char command[6] = {0x02, 0x00, 0x00, 0x00};
+	loc_SPI->cs->write(0);
+	command[3] = address & 0xFF;
+	command[2] = (address & 0xFF00) >> 8;
+	command[1] = (address & 0xFF0000) >> 16;
+	loc_SPI->spi_port->transfer_2 (command, 4, trash, 4);
+	loc_SPI->spi_port->transfer_2 (loc_data, size, trash, size);
+	loc_SPI->cs->write(1);
+}
+
+int extSRAM_testfreespace(int pkt_nb, unsigned char FIFO_index) {
+	int freespace_available = 1;
+	if ( (extSRAM_FIFO_filling[FIFO_index] + pkt_nb) > 94 ) {
+		freespace_available = 0;
+	}
+	if ( (extSRAM_total_filling + pkt_nb) > 374 ) {
+		freespace_available = 0;
+	}
+	return freespace_available;
+}
+
+void extSRAM_push(unsigned char* raw_data, int size, unsigned char FIFO_nb) {
+	unsigned short int i;
+	unsigned short int free_slot = 0xFFFF;
+	for (i=0; i<350; i++) {
+		if (extSRAM_filling[i] == 0) {
+			free_slot = i;
+		}
+	}
+	if (free_slot != 0xFFFF) {
+		extSRAM_filling[free_slot] = 1;
+		extSRAM_FIFOs[FIFO_nb][extSRAM_FIFO_index_write[FIFO_nb]] = free_slot;
+		extSRAM_FIFO_index_write[FIFO_nb] ++;
+		if (extSRAM_FIFO_index_write[FIFO_nb] > 93) {
+			extSRAM_FIFO_index_write[FIFO_nb] = 0;
+		}
+		extSRAM_total_filling ++;
+		extSRAM_FIFO_filling[FIFO_nb]++;
+		extSRAM_pkt_timer[free_slot] = raw_data[0];
+		extSRAM_pkt_size[free_slot] = size;
+		ext_SRAM_write (SPI_SRAM_p, raw_data, free_slot*350, size);
+	} else {
+		printf("ERROR extSRAM push\r\n");
+	}
+}
+
+void TXPS_FIFO_fill(unsigned char* loc_data, int size) {
+	int size_to_write;
+	if ( ( (TXPS_FIFO->WR_point & TXPS_FIFO->mask) +  size) > TXPS_FIFO->mask) { // to big for 1 step
+		size_to_write = (TXPS_FIFO->mask + 1 - (TXPS_FIFO->WR_point & TXPS_FIFO->mask) );
+		//G_SI4463->spi->transfer_2 (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), size_to_write, SI_trash, size_to_write);
+		memcpy (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), loc_data, size_to_write); 
+		TXPS_FIFO->WR_point = TXPS_FIFO->WR_point + size_to_write; // should become ZERO
+		//second step
+		size_to_write = size - size_to_write; 
+		//G_SI4463->spi->transfer_2 (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), size_to_write, SI_trash, size_to_write);
+		memcpy (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), loc_data, size_to_write); 
+		TXPS_FIFO->WR_point = TXPS_FIFO->WR_point + size_to_write;
+		TXPS_FIFO->last_ready = TXPS_FIFO->WR_point;
+	} else { //1 step is enough
+		//G_SI4463->spi->transfer_2 (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), size, SI_trash, size);
+		memcpy (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), loc_data, size); 
+		TXPS_FIFO->WR_point = TXPS_FIFO->WR_point + size;
+		TXPS_FIFO->last_ready = TXPS_FIFO->WR_point;
+	}
+}
+
+/*
+void ext_SRAM_periodic_call(void) {
+	int intern_FIFO_filling;
+	int ext_FIFO_filling;
+	intern_FIFO_filling = TX_buff_intern_WR_pointer - TX_buff_intern_RD_pointer;
+	ext_FIFO_filling = TX_buff_ext_WR_pointer - TX_buff_ext_RD_pointer;
+	while ( (ext_FIFO_filling > 0) && (intern_FIFO_filling <= 9) ) {
+		ext_SRAM_read(SPI_SRAM_p, TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], TX_buff_ext_RD_pointer*128, 128);
+		TX_buff_ext_RD_pointer++;
+		TX_buff_intern_WR_pointer++;
+		TX_buff_intern_last_ready = TX_buff_intern_WR_pointer;
+	}
+}
+*/
+
+/*
+void ext_SRAM_periodic_call() {
+	static unsigned char current_buff;
+	unsigned char radio_pckt[360];
+	unsigned char nb_buffer_treated = 0;
+	unsigned char frame_datation;
+	unsigned char loc_time_char;
+	unsigned int loc_time_int;
+	unsigned short int extSRAM_pointer;
+	int one_packet_ok = 0;
+	int switch_to_next_buff = 0;
+	int fifo_full;
+	int frame_size;
+	
+	nb_buffer_treated = 0;
+	loc_time_int = GLOBAL_timer.read_us();
+	loc_time_char = (loc_time_int >> 16) & 0xFF; 
+	//condition a rajouter sur buffer interne TXPS
+	if ((TXPS_FIFO->last_ready - TXPS_FIFO->RD_point) < 3740 ) { //16380 - 350 ; 3740
+		fifo_full = 0;
+	} else {
+		fifo_full = 1;
+	}
+	//printf("FIFO full : %i\r\n", fifo_full);
+	while ( (nb_buffer_treated<8) && (one_packet_ok==0) && (fifo_full == 0) ) {//loop over all buffers
+		switch_to_next_buff = 0;
+		if (extSRAM_FIFO_filling[current_buff] > 0) {//data available in current buffer
+			extSRAM_pointer = extSRAM_FIFOs[current_buff][extSRAM_FIFO_index_read[current_buff]];
+			frame_datation = extSRAM_pkt_timer[extSRAM_pointer];
+			//frame_size = extSRAM_pkt_size[extSRAM_pointer] + 2 + SI4463_offset_size;
+			frame_size = extSRAM_pkt_size[extSRAM_pointer];
+			if ( (loc_time_char - frame_datation) < CONF_Tx_rframe_timeout) {//frame ok
+				//printf("frame OK ext SRAM\r\n");
+				ext_SRAM_read (SPI_SRAM_p, radio_pckt, extSRAM_pointer*350, frame_size);
+				radio_pckt[1] = frame_size - 2 - SI4463_offset_size;//-2
+				TXPS_FIFO_fill (radio_pckt, frame_size);
+				switch_to_next_buff = 1;
+				one_packet_ok = 1;
+			} else {//old frame
+				switch_to_next_buff = 0;
+			}
+			extSRAM_filling[extSRAM_pointer] = 0;
+			extSRAM_FIFO_index_read[current_buff]++;
+			if (extSRAM_FIFO_index_read[current_buff] > 93) {
+				extSRAM_FIFO_index_read[current_buff] = 0;
+			}
+			extSRAM_FIFO_filling[current_buff]--;
+			extSRAM_total_filling--;
+			
+		}
+		else {//no data in the current buffer
+			switch_to_next_buff = 1;
+		}
+		if (switch_to_next_buff == 1) {
+			current_buff++;
+			if (current_buff>7) {current_buff = 0;}
+			nb_buffer_treated++;
+		}
+	} 
+}
+*/
+
+
+void ext_SRAM_test(ext_SRAM_chip* loc_SPI) {
+	unsigned char test_table[400] = "bonjour!!";
+	unsigned char test_table2[400];
+	unsigned long int timer1;
+	unsigned long int timer2;
+	unsigned int loc_address;
+	int i, j;
+	printf("\r\nsram test begin\r\n");
+	//loc_SPI->cs->write(1);
+	for (i=0; i<5000; i++) {
+		loc_address = 16 * i;
+		//wait_ms(1);
+		sprintf ((char*)test_table, "jourbon %i", i);
+		ext_SRAM_write(loc_SPI, test_table, loc_address, 20);
+		printf("write %i\r\n", i);
+	}
+	for (i=0; i<5000; i++) {
+		loc_address = 16 * i;
+		for (j=0; j<30; j++) {
+			test_table2[j] = 0;
+		}
+		//wait_ms(1);
+		ext_SRAM_read2(loc_SPI, test_table2, loc_address, 20);
+		test_table2[12] = 0;
+		printf ("read addr %i content '%s' \r\n", loc_address, test_table2);
+	}
+	timer1 = GLOBAL_timer.read_us();
+	for (i=0; i<10; i++) {
+		memcpy(test_table2+i, test_table+i, 350);
+	}
+	timer2 = GLOBAL_timer.read_us();
+	printf("temps memcpy 350 %i\r\n", timer2-timer1);
+}
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/ext_SRAM2.h b/NPR_FW_source_2020_06_29/NPR_14/source/ext_SRAM2.h
new file mode 100755
index 0000000..ba4eacc
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/ext_SRAM2.h
@@ -0,0 +1,44 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef EXT_SRAM_F4
+#define EXT_SRAM_F4
+
+#include "mbed.h"
+
+struct ext_SRAM_chip{
+    SPI* spi_port;
+    DigitalOut* cs;
+};
+
+void ext_SRAM_init(void);
+
+void ext_SRAM_set_mode(ext_SRAM_chip* loc_SPI);
+
+//void ext_SRAM_read2(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size);
+
+void ext_SRAM_write(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size);
+	
+int extSRAM_testfreespace(int pkt_nb, unsigned char FIFO_index);
+
+void extSRAM_push(unsigned char* raw_data, int size, unsigned char FIFO_nb);
+
+//void ext_SRAM_periodic_call();
+
+void ext_SRAM_test(ext_SRAM_chip* loc_SPI);
+
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/global_variables.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/global_variables.cpp
new file mode 100755
index 0000000..cb508b7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/global_variables.cpp
@@ -0,0 +1,168 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "SI4463.h"
+#include "W5500.h"
+#include "global_variables.h"
+#include "ext_SRAM2.h"
+
+SI4463_Chip* G_SI4463;
+W5500_chip* W5500_p1;
+DigitalInOut* G_FDD_trig_pin;
+InterruptIn* G_FDD_trig_IRQ;
+DigitalOut* G_PTT_PA_pin;
+
+ext_SRAM_chip* SPI_SRAM_p;
+
+Serial pc(SERIAL_TX, SERIAL_RX);
+//DigitalOut* LED_connected_p;
+
+Timeout SI4463_prepa_TX_1_call;
+
+char HMI_out_str[120];
+
+unsigned int RX_FIFO_WR_point = 0;
+unsigned int RX_FIFO_RD_point = 0;
+unsigned int RX_FIFO_last_received = 0;
+unsigned char RX_FIFO_data[0x2000]; //8kB
+
+//unsigned int debug_counter = 0;
+unsigned int RX_top_FDD_up_counter = 0;
+int RX_Eth_IPv4_counter = 0;
+int TX_radio_IPv4_counter = 0;
+int RX_radio_IPv4_counter = 0;
+unsigned int RSSI_total_stat = 0;
+unsigned int RSSI_stat_pkt_nb = 0;
+
+
+int slave_new_burst_tx_pending = 0;
+
+unsigned char TX_buff_intern_FIFOdata[128][128];
+unsigned int TX_buff_intern_WR_pointer=0;
+unsigned int TX_buff_intern_RD_pointer=0;
+unsigned int TX_buff_intern_last_ready=0;
+
+unsigned char TX_buff_ext_sizes[1024];//1024
+unsigned int TX_buff_ext_WR_pointer;
+unsigned int TX_buff_ext_RD_pointer;
+unsigned int TX_buff_ext_last_ready;
+
+unsigned char TX_TDMA_intern_data[384];
+
+unsigned char is_TDMA_master = 0; //truc
+unsigned char is_telnet_active = 1;
+unsigned char is_telnet_routed = 0;
+unsigned char CONF_radio_modulation;
+unsigned char CONF_radio_frequency;
+unsigned char CONF_frequency_band;
+unsigned char CONF_radio_network_ID;
+unsigned short int CONF_frequency_HD;
+short int CONF_freq_shift=0;
+unsigned char CONF_channel_TX;
+unsigned char CONF_channel_RX;
+unsigned char CONF_SI4463_freq_conf_RX[15];
+unsigned char CONF_SI4463_freq_conf_TX[15];
+unsigned char CONF_transmission_method=0;
+unsigned char CONF_master_FDD=0;
+unsigned long int CONF_master_down_IP;
+unsigned int CONF_TDMA_frame_duration = 65000; // 
+unsigned int CONF_TDMA_slot_duration = 3360;
+unsigned int CONF_reduced_TDMA_slot_duration = 2360;
+unsigned int CONF_TDMA_slot_margin = 300;
+unsigned int CONF_TR_margain = 500;
+unsigned int CONF_TA_margain = 2000;
+unsigned int CONF_preamble_duration_for_decide = 590;
+unsigned int CONF_long_preamble_duration_for_TA = 1000;
+unsigned int CONF_byte_duration = 8;
+unsigned int CONF_additional_preamble = 700;
+unsigned long int CONF_radio_timeout = 30000000;
+unsigned long int CONF_radio_timeout_small = 10000000;
+unsigned int offset_time_TX_slave = 48000; 
+unsigned int time_next_TX_slave;
+unsigned int time_max_TX_burst = 45000;//47000
+int CONF_delay_prepTX1_2_TX = 1030;
+unsigned char my_radio_client_ID = 0xFE;
+int CONF_Tx_rframe_timeout = 30;//unit 1/65000 th of a second
+int CONF_signaling_period = 1;
+int is_SRAM_ext=1;
+int DEBUG_max_rx_size_w5500=0;
+
+unsigned int TDMA_slave_last_master_top = 0;
+
+Timer GLOBAL_timer;
+
+LAN_conf_T LAN_conf_saved;
+LAN_conf_T LAN_conf_applied; 
+
+unsigned char CONF_modem_MAC[6]; 
+unsigned char CONF_Eth_mode = 0x07;
+
+char CONF_radio_my_callsign[16];
+char CONF_radio_master_callsign[16];
+unsigned long int CONF_radio_addr_table_IP_begin[radio_addr_table_size];
+unsigned long int CONF_radio_addr_table_IP_size[radio_addr_table_size];
+char CONF_radio_addr_table_callsign[radio_addr_table_size][16];
+char CONF_radio_addr_table_status[radio_addr_table_size];
+unsigned int CONF_radio_addr_table_date[radio_addr_table_size];
+unsigned long int CONF_radio_IP_start;
+unsigned long int CONF_radio_IP_size;
+unsigned int my_client_radio_connexion_state;
+unsigned int my_client_radio_connexion_date;
+unsigned char G_connect_rejection_reason;
+int G_temperature_SI4463;
+int G_need_temperature_check = 0;
+unsigned long int CONF_radio_IP_size_requested;
+unsigned char CONF_radio_static_IP_requested;
+unsigned char CONF_radio_state_ON_OFF = 0;
+unsigned char CONF_radio_default_state_ON_OFF;
+unsigned char CONF_radio_PA_PWR = 0x7F;
+unsigned char CONF_preamble_TX_long;
+unsigned char CONF_preamble_TX_short;
+unsigned long int last_rframe_seen = 0;
+
+long int TDMA_table_TA[radio_addr_table_size];
+
+unsigned short int G_downlink_RSSI; 
+unsigned short int G_radio_addr_table_RSSI[radio_addr_table_size]; 
+unsigned short int G_downlink_BER; 
+unsigned short int G_radio_addr_table_BER[radio_addr_table_size]; 
+short int G_downlink_TA; 
+int G_downlink_bandwidth_temp;
+int G_uplink_bandwidth_temp;
+
+int super_debug = 0;
+
+unsigned char parity_bit_elab[128] = {
+	0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80,0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,
+	0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80,
+	0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80,
+	0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80,0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,
+	0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80,
+	0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80,0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,
+	0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80,0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,
+	0x80,0x00,0x00,0x80,0x00,0x80,0x80,0x00,0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x80
+};
+unsigned char parity_bit_check[256] = {
+	1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
+	0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
+	0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
+	1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
+	0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
+	1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
+	1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
+	0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1
+};
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/global_variables.h b/NPR_FW_source_2020_06_29/NPR_14/source/global_variables.h
new file mode 100755
index 0000000..a43a7b4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/global_variables.h
@@ -0,0 +1,207 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2018 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef GLOB_VARIAB_F4
+#define GLOB_VARIAB_F4
+#include "SI4463.h"
+#include "W5500.h"
+
+//#define EXT_SRAM_USAGE
+//#define FREQ_BAND_2M
+//#define NPR_L476
+
+#include "ext_SRAM2.h"
+extern ext_SRAM_chip* SPI_SRAM_p;
+
+#ifdef FREQ_BAND_2M
+	#define CONF_DEF_FREQ 1000
+	#define FREQ_RANGE_MIN 144
+	#define FREQ_RANGE_MAX 148
+	#define FREQ_MAX_RAW 4000
+	#define FREQ_BAND "2m"
+	#define SI4463_NOUTDIV 24
+#else 
+	/*420 - 450MHz*/
+	#define CONF_DEF_FREQ 17000
+	#define FREQ_RANGE_MIN 420
+	#define FREQ_RANGE_MAX 450
+	#define FREQ_MAX_RAW 30000
+	#define FREQ_BAND "70cm"
+	#define SI4463_NOUTDIV 8
+#endif
+
+#define FW_VERSION "2022_01_24"
+
+extern SI4463_Chip* G_SI4463;
+
+extern W5500_chip* W5500_p1;
+
+extern DigitalInOut* G_FDD_trig_pin;
+extern InterruptIn* G_FDD_trig_IRQ;
+extern DigitalOut* G_PTT_PA_pin;
+
+extern Serial pc;
+
+extern Timeout SI4463_prepa_TX_1_call;
+
+extern unsigned char TX_buff_intern_FIFOdata[128][128];
+extern unsigned int TX_buff_intern_WR_pointer;
+extern unsigned int TX_buff_intern_RD_pointer;
+extern unsigned int TX_buff_intern_last_ready;
+
+extern unsigned char TX_buff_ext_sizes[1024];//1024
+extern unsigned int TX_buff_ext_WR_pointer;
+extern unsigned int TX_buff_ext_RD_pointer;
+extern unsigned int TX_buff_ext_last_ready;
+
+extern unsigned char TX_TDMA_intern_data[384];
+
+extern char HMI_out_str[120];
+
+// RX FIFO (RX from radio)
+extern unsigned int RX_FIFO_WR_point;
+extern unsigned int RX_FIFO_RD_point;
+extern unsigned int RX_FIFO_last_received;
+//extern unsigned char RX_FIFO_data[0x2000]; //8kB
+extern unsigned char RX_FIFO_data[0x2000]; //8kB
+#define RX_FIFO_mask 0x1FFF 
+
+#define TXPS_FIFO_mask 0x3FFF
+#define TXPS_FIFO_threshold 14000
+#define TXPS_FIFO_threshold_sig 16380
+
+//#define CONF_Tx_rframe_timeout 30
+//CONF_Tx_rframe_timeout unit 1/65000 th of a second
+// *** TDMA ***
+extern unsigned char TX_signaling_TDMA_frame[300]; 
+
+extern unsigned char is_TDMA_master;
+extern unsigned char is_telnet_active;
+extern unsigned char is_telnet_routed;
+extern unsigned char CONF_radio_modulation;
+extern unsigned char CONF_radio_frequency;
+extern unsigned char CONF_frequency_band;
+extern unsigned char CONF_radio_network_ID;
+extern unsigned short int CONF_frequency_HD;
+extern short int CONF_freq_shift;
+extern unsigned char CONF_channel_TX;
+extern unsigned char CONF_channel_RX;
+extern unsigned char CONF_SI4463_freq_conf_RX[15];
+extern unsigned char CONF_SI4463_freq_conf_TX[15];
+extern unsigned char CONF_transmission_method;
+extern unsigned char CONF_master_FDD;
+extern unsigned long int CONF_master_down_IP;
+extern unsigned int CONF_TDMA_frame_duration;
+extern unsigned int CONF_TDMA_slot_duration;
+extern unsigned int CONF_reduced_TDMA_slot_duration;
+extern unsigned int CONF_TDMA_slot_margin;
+extern unsigned int CONF_TR_margain;
+extern unsigned int CONF_TA_margain;
+extern unsigned int CONF_preamble_duration_for_decide;
+extern unsigned int CONF_long_preamble_duration_for_TA;
+extern unsigned int CONF_byte_duration;
+extern unsigned int CONF_additional_preamble;
+extern unsigned long int CONF_radio_timeout;
+extern unsigned long int CONF_radio_timeout_small;
+extern unsigned int offset_time_TX_slave; 
+extern unsigned int time_next_TX_slave;
+extern unsigned int time_max_TX_burst;
+extern int CONF_delay_prepTX1_2_TX;
+extern unsigned char my_radio_client_ID;
+extern int CONF_Tx_rframe_timeout;
+extern int CONF_signaling_period;
+extern int is_SRAM_ext;
+
+extern int DEBUG_max_rx_size_w5500;
+
+extern unsigned int TDMA_slave_last_master_top;
+
+// *** STATISTIC and DEBUG variables ***
+//extern unsigned int debug_counter;
+extern unsigned int RX_top_FDD_up_counter;
+extern int RX_Eth_IPv4_counter;
+extern int TX_radio_IPv4_counter;
+extern int RX_radio_IPv4_counter;
+extern unsigned int RSSI_total_stat;
+extern unsigned int RSSI_stat_pkt_nb;
+
+extern int slave_new_burst_tx_pending;
+
+extern Timer GLOBAL_timer;
+
+// *** ARP and DHCP and "routing" ***
+struct LAN_conf_T { 
+	
+	//unsigned char modem_MAC[6]; 
+	unsigned long int LAN_modem_IP;
+	unsigned long int DHCP_range_start;
+	unsigned long int DHCP_range_size; //4
+	unsigned long int LAN_subnet_mask;
+	unsigned long int LAN_def_route;
+	unsigned char LAN_def_route_activ;
+	unsigned char LAN_DNS_activ;
+	unsigned long int LAN_DNS_value;
+	unsigned char DHCP_server_active;
+};
+
+extern LAN_conf_T LAN_conf_saved;
+extern LAN_conf_T LAN_conf_applied; 
+
+extern unsigned char CONF_modem_MAC[6]; 
+extern unsigned char CONF_Eth_mode;
+
+#define radio_addr_table_size 7
+extern char CONF_radio_my_callsign[16];
+extern char CONF_radio_master_callsign[16];
+extern unsigned long int CONF_radio_addr_table_IP_begin[radio_addr_table_size];
+extern unsigned long int CONF_radio_addr_table_IP_size[radio_addr_table_size];
+extern char CONF_radio_addr_table_callsign[radio_addr_table_size][16];
+extern char CONF_radio_addr_table_status[radio_addr_table_size];
+extern unsigned int CONF_radio_addr_table_date[radio_addr_table_size];
+extern unsigned long int CONF_radio_IP_start;
+extern unsigned long int CONF_radio_IP_size;
+extern unsigned int my_client_radio_connexion_state;
+extern unsigned int my_client_radio_connexion_date;
+extern unsigned char G_connect_rejection_reason;
+extern int G_temperature_SI4463;
+extern int G_need_temperature_check;
+extern unsigned long int CONF_radio_IP_size_requested;
+extern unsigned char CONF_radio_static_IP_requested;
+extern unsigned char CONF_radio_state_ON_OFF;
+extern unsigned char CONF_radio_default_state_ON_OFF;
+extern unsigned char CONF_radio_PA_PWR;
+extern unsigned char CONF_preamble_TX_long;
+extern unsigned char CONF_preamble_TX_short;
+extern unsigned long int last_rframe_seen;
+
+extern long int TDMA_table_TA[radio_addr_table_size];
+
+extern unsigned short int G_downlink_RSSI; 
+extern unsigned short int G_radio_addr_table_RSSI[radio_addr_table_size]; 
+extern unsigned short int G_downlink_BER; 
+extern unsigned short int G_radio_addr_table_BER[radio_addr_table_size]; 
+extern short int G_downlink_TA; 
+//extern short int G_radio_addr_table_TA[radio_addr_table_size]; 
+extern int G_downlink_bandwidth_temp;
+extern int G_uplink_bandwidth_temp;
+
+extern int super_debug;
+
+extern unsigned char parity_bit_elab[128];
+extern unsigned char parity_bit_check[256];
+
+#endif
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/main.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/main.cpp
new file mode 100755
index 0000000..c341f5e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/main.cpp
@@ -0,0 +1,278 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "mbed.h"
+#include "W5500.h"
+#include "SI4463.h"
+#include "HMI_telnet.h"
+//#include "Virt_Chan.h"
+#include "Eth_IPv4.h"
+#include "DHCP_ARP.h"
+#include "global_variables.h"
+#include "L1L2_radio.h"
+#include "TDMA.h"
+#include "signaling.h"
+#include "config_flash.h"
+
+#include "ext_SRAM2.h"
+
+//#define NPR_L476
+//Serial pc(SERIAL_TX, SERIAL_RX); // Nucleo
+//Serial pc(USBTX, USBRX); //NXP LPC1769
+
+DigitalInOut FDD_trig_pin(PA_10);//GPIO_11
+InterruptIn FDD_trig_IRQ(PA_10);//GPIO_11
+DigitalOut PTT_PA_pin(PA_9);//GPIO_10
+
+DigitalOut SI4463_SDN(PA_1);
+
+AnalogIn Random_pin(PA_0);
+DigitalOut LED_RX_loc(PB_1);
+DigitalOut LED_connected(PA_12);
+
+DigitalIn Int_W5500(PA_8);
+DigitalOut CS1(PA_11);//CS W5500
+SPI spi_2(PB_5, PB_4, PB_3); // mosi, miso, sclk
+DigitalOut CS3(PB_0);// CS ext SRAM PB_0 
+
+InterruptIn Int_SI4463(PA_3);
+DigitalOut CS2(PA_4);
+SPI spi_1(PA_7, PA_6, PA_5); // mosi, miso, sclk
+
+int main()
+{
+    wait_ms(200);
+	pc.baud(921600);
+    pc.printf("\r\n\r\nNPR FW %s\r\n", FW_VERSION);
+	
+	Timer slow_timer; 
+	int i = 1;
+	int temperature_timer = 0;
+	
+	static LAN_conf_T* LAN_conf_p;
+	LAN_conf_p = &LAN_conf_applied;
+	
+	static W5500_chip W5500_1;
+	W5500_p1 = &W5500_1;
+	W5500_1.spi_port = &spi_2;
+    W5500_1.cs = &CS1;
+    W5500_1.interrupt = &Int_W5500; 
+	
+//#ifdef EXT_SRAM_USAGE
+	static ext_SRAM_chip SPI_SRAM;
+	SPI_SRAM_p = &SPI_SRAM;
+	SPI_SRAM.spi_port = &spi_2;
+	SPI_SRAM.cs = &CS3;
+//#endif
+	
+	static SI4463_Chip SI4463_1;
+	SI4463_1.spi = &spi_1;//1
+	SI4463_1.cs = &CS2;//2
+	SI4463_1.interrupt = &Int_SI4463;
+	SI4463_1.RX_LED = &LED_RX_loc;
+	SI4463_1.SDN = &SI4463_SDN;
+	
+	G_SI4463 = &SI4463_1;
+	
+	G_FDD_trig_pin = &FDD_trig_pin;
+	G_FDD_trig_IRQ = &FDD_trig_IRQ;
+	G_PTT_PA_pin = &PTT_PA_pin;
+	
+	reset_DHCP_table(LAN_conf_p);
+		
+    spi_2.format(8,0);
+	spi_1.format(8,0);
+	spi_2.frequency(20000000); 
+	spi_1.frequency(10000000);
+	
+	for(i=0; i<radio_addr_table_size; i++) {
+		CONF_radio_addr_table_status[i] = 0;
+	}
+	
+	G_FDD_trig_pin->input();
+	G_PTT_PA_pin->write(0);
+	LED_RX_loc = 0;
+	LED_connected = 0;
+    CS1=1;
+	CS2=1;
+	CS3=1;
+	SI4463_SDN = 1;
+	
+	wait_ms(20);
+	is_SRAM_ext = ext_SRAM_detect();
+	
+	LED_RX_loc = 1; 
+	for (i=0; i<7; i++) {
+		wait_ms(200);
+		LED_RX_loc = !LED_RX_loc;
+		LED_connected = !LED_connected;
+		SI4463_SDN = !SI4463_SDN;
+	}
+	LED_RX_loc = 0;
+	LED_connected = 0;
+	SI4463_SDN = 1;
+	
+	printf("\r\n");
+
+	RX_FIFO_WR_point = 0;
+	RX_FIFO_RD_point = 0;
+	RX_FIFO_last_received = 0;
+
+	//TXPS_FIFO->is_single = 0;
+	//TXPS_FIFO->WR_point = 0;
+	//TXPS_FIFO->RD_point = 0;
+	//TXPS_FIFO->last_ready = 0;
+
+	GLOBAL_timer.reset();
+	GLOBAL_timer.start();
+	TDMA_init_all();
+	
+	//TXPS_FIFO->last_ready = TXPS_FIFO->WR_point;
+	for (i=0; i<0x2000; i++) {
+		RX_FIFO_data[i] = 0;
+	}
+
+	printf("      \r\n");
+	for (i=0; i<radio_addr_table_size; i++) {
+		CONF_radio_addr_table_IP_begin[i] = 0; // 0 = entry not active
+		
+	}
+	if (is_SRAM_ext) {
+		printf("config WITH ext SRAM\r\n");
+	} else {
+		printf("config WITHOUT ext SRAM\r\n");
+	}
+	
+	wait_ms(100);
+	NFPR_config_read(&Random_pin);
+
+	//SI4463_print_version(G_SI4463);//!!!!
+	SI4463_get_state(G_SI4463);
+
+	i = SI4463_configure_all();
+	if (i == 1) {
+		HMI_printf("SI4463 configured\r\n");
+	} else {
+		HMI_printf("SI4463 error while configure\r\n");
+		SI4463_print_version(G_SI4463);
+		wait_ms(5000);
+		if (serial_term_loop() == 0) {//no serial char detected
+			NVIC_SystemReset(); //reboot
+		}
+	}
+	//SI4463_print_version(G_SI4463);//!!!!
+	
+	W5500_initial_configure(W5500_p1);
+	wait_ms(2);
+#ifdef EXT_SRAM_USAGE
+	ext_SRAM_set_mode(SPI_SRAM_p);
+	wait_ms(2)
+	ext_SRAM_init();
+#endif
+	TDMA_NULL_frame_init(70);
+	
+	SI4463_periodic_temperature_check(G_SI4463);
+	Int_SI4463.fall(&SI4463_HW_interrupt);
+	if (CONF_radio_default_state_ON_OFF) {
+		//TDMA_init_all();
+		//SI4463_radio_start();
+		RADIO_on(1, 0, 1);//init state, no reconfigure, HMI output
+	}
+	HMI_printf("ready> ");
+	slow_timer.start();
+
+	unsigned int timer_snapshot;
+	int slow_action_counter = 0;
+	int signaling_counter = 0;
+	//SI4463_temp_check_init();
+	
+	int telnet_counter = 0;
+	
+	while(1) {	
+		for (i=0; i<100; i++) {
+			if ( (is_TDMA_master == 1) && (CONF_master_FDD == 2) ) {
+				FDDup_RX_FIFO_dequeue();
+			} else {
+				radio_RX_FIFO_dequeue(W5500_p1);
+			}
+			Eth_RX_dequeue(W5500_p1); 
+			TDMA_slave_timeout();
+#ifdef EXT_SRAM_USAGE
+			ext_SRAM_periodic_call();
+#endif
+			if (is_SRAM_ext == 1) {
+				ext_SRAM_periodic_call();
+			}
+			timer_snapshot = slow_timer.read_us();
+			if (timer_snapshot > 666000) {//666000
+				slow_timer.reset();
+				slow_action_counter++;
+				if (slow_action_counter > 2) {slow_action_counter = 0; }
+				
+				if (slow_action_counter == 0) {
+					HMI_periodic_call();
+				}
+				//debug_counter = 0;
+
+				
+				if (slow_action_counter == 1) {//every 2 sec
+					signaling_counter++;
+					if (signaling_counter >= CONF_signaling_period) {
+						signaling_periodic_call();
+						signaling_counter = 0;
+					}
+				}
+				
+				if (slow_action_counter == 2) {
+					DHCP_ARP_periodic_free_table();
+					W5500_re_configure_periodic_call(W5500_p1);
+				
+					temperature_timer++;
+					if(temperature_timer > 15) {// 15 every 30 sec
+						temperature_timer = 0;
+						G_need_temperature_check = 1;
+						SI4463_periodic_temperature_check_2();//SI4463_periodic_temperature_check(G_SI4463);
+					}
+				}
+			}
+		}
+		
+		if (is_TDMA_master) {
+			if (CONF_radio_state_ON_OFF==1) {LED_connected.write((timer_snapshot >> 19) & 1);}
+			else {LED_connected.write(0);}
+		} else {
+			if (my_client_radio_connexion_state == 2) {
+				LED_connected.write(1);
+			}else{
+				LED_connected.write(0);
+			}
+		}
+		if (is_telnet_active) {
+			
+			telnet_counter++;
+			if (telnet_counter>10) {
+				telnet_loop(W5500_p1);
+				telnet_counter = 0;
+			}
+		}
+		serial_term_loop();
+		
+		if ( (LAN_conf_applied.DHCP_server_active == 1) && (is_TDMA_master == 0) ) {
+			DHCP_server(LAN_conf_p, W5500_p1);
+		}
+	}
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/signaling.cpp b/NPR_FW_source_2020_06_29/NPR_14/source/signaling.cpp
new file mode 100755
index 0000000..832e6cb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/signaling.cpp
@@ -0,0 +1,580 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#include "signaling.h"
+#include "mbed.h"
+#include "Eth_IPv4.h"
+#include "global_variables.h"
+#include "L1L2_radio.h"
+#include "DHCP_ARP.h"
+#include "TDMA.h"
+#include "HMI_telnet.h"
+
+#include "ext_SRAM2.h"
+
+static unsigned char rframe_TX[380];
+static unsigned char TX_signal_frame_raw[260]; //300
+static int TX_signal_frame_point = 0;
+
+static int connect_state_machine_counter = 0;
+static int time_counter_last_ack = 0; 
+
+void signaling_frame_exploitation (unsigned char* unFECdata, int unFECsize, int TA_input) {
+	int data_pos = 2;
+	unsigned char field_type;
+	unsigned char field_length;
+	unsigned char local_ID;
+	unsigned char* local_callsign;
+	unsigned long int local_IP_start;
+	unsigned long int local_IP_size;
+	unsigned char local_static_alloc;
+	unsigned char local_reason;
+	unsigned char local_RSSI;
+	unsigned short int local_BER;
+	short int local_TA;
+	//printf("signaling rx\r\n");
+	do {
+		field_type = unFECdata[data_pos];
+		field_length = unFECdata[data_pos+1];
+		switch (field_type) {
+			case 0x01 : // WHOIS
+				local_ID = unFECdata[data_pos + 2];
+				local_callsign = unFECdata + data_pos + 3;
+				local_callsign[15] = 0;//force null termination
+				local_IP_start = IP_char2int (unFECdata + data_pos + 19);
+				local_IP_size = IP_char2int (unFECdata + data_pos + 23);
+				local_RSSI = unFECdata[data_pos + 27];
+				local_BER = unFECdata[data_pos + 28] + (unFECdata[data_pos + 29] << 8); 
+				local_TA = unFECdata[data_pos + 30] + (unFECdata[data_pos + 31] << 8); 
+				signaling_whois_interpret (local_ID, local_callsign, 
+					local_IP_start, local_IP_size,
+					local_RSSI, local_BER, local_TA); 
+				break; 
+			case 0x05 : // request new connection
+				local_callsign = unFECdata + data_pos + 2;
+				local_callsign[15] = 0;
+				local_IP_size = IP_char2int (unFECdata + data_pos + 18);
+				local_static_alloc = unFECdata[data_pos + 22];
+				if (is_TDMA_master) { 
+					signaling_connect_req_process(local_callsign, local_IP_size, local_static_alloc, TA_input); 
+				}
+				break;
+			case 0x06 : // ACK new connection
+				local_callsign = unFECdata + data_pos + 3;
+				local_callsign[15] = 0;
+				if ( (is_TDMA_master == 0) && (strcmp ((char*)local_callsign, CONF_radio_my_callsign) == 0) ) {
+					signaling_connect_ACK_process(unFECdata + data_pos + 2);
+				}
+				break;
+			case 0x07 : // NACK new connection
+				local_callsign = unFECdata + data_pos + 2;
+				local_callsign[15] = 0;
+				local_reason = unFECdata[data_pos + 18];
+				if ( (is_TDMA_master == 0) && (strcmp ((char*)local_callsign, CONF_radio_my_callsign) == 0) ) {
+					signaling_connect_NACK_process(local_reason);
+				}
+				break;
+			case 0x0B : // Request disconnection
+				local_ID = unFECdata[data_pos + 2];
+				local_callsign = unFECdata + data_pos + 3;
+				local_callsign[15] = 0;
+				if (is_TDMA_master) {
+					signaling_disconnect_req_process (local_ID, local_callsign);
+				}
+				break;
+			case 0x0C : // ACK disconnection
+				local_ID = unFECdata[data_pos + 2];
+				local_callsign = unFECdata + data_pos + 3;
+				local_callsign[15] = 0;
+				if ( (is_TDMA_master == 0) && (strcmp ((char*)local_callsign, CONF_radio_my_callsign) == 0) ) {
+					signaling_disconnect_ACK_process (local_ID, local_callsign);
+				}
+				break;
+		} 
+		data_pos = data_pos + field_length + 2;
+		
+	} while ( (field_type != 0xFF) && (data_pos < unFECsize ) );
+	
+}
+
+void signaling_whois_interpret(unsigned char loc_ID, unsigned char* loc_callsign, 
+	unsigned long int loc_IP_start, unsigned long int loc_IP_size, 
+	unsigned char RSSI_loc, unsigned short int BER_loc, short int TA_loc) {
+	unsigned char IP_start_c[5];
+	
+	IP_int2char (loc_IP_start, IP_start_c); 
+	//printf("WHOIS ID:%i CALL:%s IP_start %i.%i.%i.%i IP_size %i\r\n", loc_ID, (char*)loc_callsign, 
+	//	IP_start_c[0], IP_start_c[1], IP_start_c[2], IP_start_c[3], loc_IP_size);
+	if (is_TDMA_master == 0) { //only useful for slaves
+		if (loc_ID == 0x7F) { //who entry for master
+			strcpy (CONF_radio_master_callsign, (char*)loc_callsign);		
+		} 
+		else if (loc_ID < radio_addr_table_size) {
+			CONF_radio_addr_table_date[loc_ID] = GLOBAL_timer.read_us();
+			CONF_radio_addr_table_status[loc_ID] = 2; //
+			strcpy (CONF_radio_addr_table_callsign[loc_ID], (char*)loc_callsign);
+			CONF_radio_addr_table_IP_begin[loc_ID] = loc_IP_start;
+			CONF_radio_addr_table_IP_size[loc_ID] = loc_IP_size;
+			G_radio_addr_table_RSSI[loc_ID] = RSSI_loc;
+			G_radio_addr_table_BER[loc_ID] = BER_loc;
+			TDMA_table_TA[loc_ID] = TA_loc;
+		}
+	}
+}
+
+unsigned long int signaling_lookfor_IP_range(unsigned long int req_size) {
+	int i, j;
+	unsigned long int answer = 0xFFFFFFFF;
+	unsigned long int current_tested_pos;
+	unsigned long int next_alloc_IP;
+	
+	current_tested_pos = CONF_radio_IP_start;
+	next_alloc_IP = CONF_radio_IP_start + CONF_radio_IP_size;
+	for (j=0; j<radio_addr_table_size; j++) {//looking for next allocated IP
+		if ( (CONF_radio_addr_table_status[j]) && (CONF_radio_addr_table_IP_begin[j] >= current_tested_pos) && (CONF_radio_addr_table_IP_begin[j] < next_alloc_IP) ) {
+			next_alloc_IP = CONF_radio_addr_table_IP_begin[j];
+		}
+	}
+	if ( (next_alloc_IP - current_tested_pos) >= req_size) {
+		answer = current_tested_pos; 
+	}
+	
+	for (i=0; i<radio_addr_table_size; i++) {
+		if (CONF_radio_addr_table_status[i]) {
+			current_tested_pos = CONF_radio_addr_table_IP_begin[i] + CONF_radio_addr_table_IP_size[i];//beginning = end of previous
+			if (current_tested_pos < answer) { //only continue search if IP tested is below already found
+				next_alloc_IP = CONF_radio_IP_start + CONF_radio_IP_size;
+				for (j=0; j<radio_addr_table_size; j++) {//looking for next allocated IP
+					if ( (CONF_radio_addr_table_status[j]) && (CONF_radio_addr_table_IP_begin[j] >= current_tested_pos) && (CONF_radio_addr_table_IP_begin[j] < next_alloc_IP) ) {
+						next_alloc_IP = CONF_radio_addr_table_IP_begin[j];
+					}
+				}
+				if ( (next_alloc_IP - current_tested_pos) >= req_size) {
+					answer = current_tested_pos; 
+				}
+			}
+		}
+		
+	}
+	return answer;
+}
+
+void signaling_connect_req_process (unsigned char* client_callsign, unsigned long int req_IP_size, unsigned char req_static_alloc, int TA_input) {
+	int loc_ack = 0;
+	int i;
+	int existing_entry = -1;
+	unsigned char client_ID = 0xFF;
+	static unsigned char raw_answer[60];
+	unsigned char NACK_reason;
+	unsigned long int proposed_IP;
+	unsigned char previous_status;
+	
+	// 1) look for existing entry for this callsign
+	for (i=0; i<radio_addr_table_size; i++) {
+		if (strcmp((char*)client_callsign, CONF_radio_addr_table_callsign[i]) == 0) {
+			existing_entry = i;
+		}
+	}
+	//printf ("connect req received\r\n");
+	//printf ("found client entry %i\r\n", existing_entry);
+	if (existing_entry != -1) {
+		previous_status = CONF_radio_addr_table_status[existing_entry];
+	}
+	// 2) logic with 3 cases
+	// 2.1) existing entry matches both callsign and size
+	if ( (existing_entry != -1) && (req_IP_size == CONF_radio_addr_table_IP_size[existing_entry]) ) {
+		client_ID = existing_entry;
+		CONF_radio_addr_table_status[existing_entry] = 1;
+		CONF_radio_addr_table_date[existing_entry] = GLOBAL_timer.read_us();
+		loc_ack = 1; // Ack
+		//printf("existing entry matches\r\n");
+	}
+	// 2.2) existing entry with different size
+	if ( (existing_entry != -1) && (req_IP_size != CONF_radio_addr_table_IP_size[existing_entry]) ) {
+		CONF_radio_addr_table_status[existing_entry] = 0; //frees existing entry
+		proposed_IP = signaling_lookfor_IP_range (req_IP_size);
+		if (proposed_IP != 0xFFFFFFFF) {// IP valid found
+			client_ID = existing_entry;
+			CONF_radio_addr_table_status[client_ID] = 1;
+			CONF_radio_addr_table_IP_begin[client_ID] = proposed_IP;
+			CONF_radio_addr_table_IP_size[client_ID] = req_IP_size;
+			strcpy (CONF_radio_addr_table_callsign[client_ID], (char*)client_callsign);
+			CONF_radio_addr_table_date[client_ID] = GLOBAL_timer.read_us();
+			loc_ack = 1;
+			//printf("existing entry doesnt match, ok new\r\n");
+		} else { //no IP found
+			NACK_reason = 0x02;
+			loc_ack = 0;
+			//printf("existing entry doesnt match, no more IP\r\n");
+		}
+	}
+	if ( (existing_entry != -1) && (previous_status==0) && (loc_ack==1) ) {
+		TDMA_init_TA(client_ID, TA_input);
+	}
+	// 2.3) no previous entry
+	if (existing_entry == -1) {
+		// lookfor empty entry
+		for (i=radio_addr_table_size-1; i>=0; i--) {
+			if (CONF_radio_addr_table_status[i] <= 0) {
+				client_ID = i;
+				//printf("client ID search %i\r\n", client_ID);
+			}
+		}
+		if (client_ID == 0xFF) {
+			NACK_reason = 0x03; //max nb of clients reached
+			loc_ack = 0;
+		} else {
+			proposed_IP = signaling_lookfor_IP_range (req_IP_size);
+			if (proposed_IP != 0xFFFFFFFF) {// IP valid found
+				CONF_radio_addr_table_status[client_ID] = 1;
+				CONF_radio_addr_table_IP_begin[client_ID] = proposed_IP;
+				CONF_radio_addr_table_IP_size[client_ID] = req_IP_size;
+				strcpy (CONF_radio_addr_table_callsign[client_ID], (char*)client_callsign);
+				CONF_radio_addr_table_date[client_ID] = GLOBAL_timer.read_us();
+				TDMA_init_TA(client_ID, TA_input);
+				loc_ack = 1;
+				//printf("new, alloc OK\r\n");
+			} else { //no IP found
+				NACK_reason = 0x02;
+				loc_ack = 0;
+				//printf("new, no more IP\r\n");
+			}
+		}
+	}
+	// 3)send answer to client
+	if (loc_ack == 1) { // ACK
+		raw_answer[0] = 0x06; //signaling type = connection acknowledge
+		raw_answer[1] = 59; //size
+		raw_answer[2] = client_ID;
+		strcpy ((char*)(raw_answer + 3), (char*)client_callsign);					// Client Callsign
+		IP_int2char (CONF_radio_addr_table_IP_begin[client_ID], raw_answer + 19); 	// IP start
+		IP_int2char (CONF_radio_addr_table_IP_size[client_ID], raw_answer + 23);	// IP size
+		strcpy ((char*)(raw_answer + 27), CONF_radio_my_callsign); 					// Master callsign
+		IP_int2char (LAN_conf_applied.LAN_modem_IP, raw_answer + 43); 					// Modem IP
+		IP_int2char (LAN_conf_applied.LAN_subnet_mask, raw_answer + 47); 					// IP subnet mask
+		raw_answer[51] = LAN_conf_applied.LAN_def_route_activ;							// active default route
+		IP_int2char (LAN_conf_applied.LAN_def_route, raw_answer + 52); 					// Default Route value
+		raw_answer[56] = LAN_conf_applied.LAN_DNS_activ;									// Active DNS
+		IP_int2char (LAN_conf_applied.LAN_DNS_value, raw_answer + 57); 					// DNS value
+		signaling_TX_add_entry (raw_answer, 61);
+		signaling_frame_push();
+		//printf("\r\n ACK sent\r\n\r\n");
+	}
+	else { // NACK
+		raw_answer[0] = 0x07; //signaling type = connection NACK
+		raw_answer[1] = 33; //size
+		strcpy ((char*)(raw_answer + 2), (char*)client_callsign);
+		raw_answer[18] = NACK_reason;
+		strcpy ((char*)(raw_answer + 19), CONF_radio_my_callsign); // Master callsign;
+		signaling_TX_add_entry (raw_answer, 35);
+		signaling_frame_push();
+		//printf("\r\n NACK sent\r\n\r\n");
+	}
+}
+
+void signaling_connect_ACK_process(unsigned char* raw_data) 
+{
+	unsigned char local_client_ID;
+	unsigned long int local_IP_start;
+	unsigned long int local_IP_size;
+	unsigned long int local_modem_IP;
+	unsigned long int local_IP_subnet;
+	unsigned char local_default_route_activ;
+	unsigned long int local_default_route;
+	unsigned char local_DNS_activ;
+	unsigned long int local_DNS_value;
+	
+	int need_LAN_reset = 0;
+	//Client ID
+	local_client_ID = raw_data[0];
+	my_radio_client_ID = local_client_ID;
+	TDMA_NULL_frame_init(70);
+	// IP Start
+	local_IP_start = IP_char2int(raw_data + 17);
+	if (local_IP_start != LAN_conf_applied.DHCP_range_start) {need_LAN_reset = 1;}
+	LAN_conf_applied.DHCP_range_start = local_IP_start;
+	// IP Size
+	local_IP_size = IP_char2int(raw_data + 21);
+	if (local_IP_size != LAN_conf_applied.DHCP_range_size) {need_LAN_reset = 1;}
+	LAN_conf_applied.DHCP_range_size = local_IP_size;
+	// Master Callsign
+	strcpy(CONF_radio_master_callsign, (char*)(raw_data + 25));
+	// Modem IP
+	local_modem_IP = IP_char2int(raw_data + 41);
+	if (local_modem_IP != LAN_conf_applied.LAN_modem_IP) {need_LAN_reset = 1;}
+	LAN_conf_applied.LAN_modem_IP = local_modem_IP;
+	// IP subnet mask
+	local_IP_subnet = IP_char2int(raw_data + 45);
+	if (local_IP_subnet != LAN_conf_applied.LAN_subnet_mask) {need_LAN_reset = 1;}
+	LAN_conf_applied.LAN_subnet_mask = local_IP_subnet;
+	// Default route active
+	local_default_route_activ = raw_data[49];
+	if (local_default_route_activ != LAN_conf_applied.LAN_def_route_activ) {need_LAN_reset = 1;}
+	LAN_conf_applied.LAN_def_route_activ = local_default_route_activ;
+	// Default route value
+	local_default_route = IP_char2int(raw_data + 50);
+	if (local_default_route != LAN_conf_applied.LAN_def_route) {need_LAN_reset = 1;}
+	LAN_conf_applied.LAN_def_route = local_default_route;
+	// DNS active
+	local_DNS_activ = raw_data[54];
+	if (local_DNS_activ != LAN_conf_applied.LAN_DNS_activ) {need_LAN_reset = 1;}
+	LAN_conf_applied.LAN_DNS_activ = local_DNS_activ;
+	// DNS value
+	local_DNS_value = IP_char2int(raw_data + 55);
+	if (local_DNS_value != LAN_conf_applied.LAN_DNS_value) {need_LAN_reset = 1;}
+	LAN_conf_applied.LAN_DNS_value = local_DNS_value;
+	
+	if (need_LAN_reset) {
+		HMI_force_exit();
+		reset_DHCP_table(&LAN_conf_applied);
+		W5500_re_configure();
+		need_LAN_reset = 0;
+	}
+	my_client_radio_connexion_state = 2;
+	connect_state_machine_counter = 0;
+	time_counter_last_ack = 0; 
+	//printf("\r\n REQ ACK Received\r\n\r\n");
+}
+
+void signaling_connect_NACK_process (unsigned char reason_loc) {
+	//printf("NACK reason: %i\r\n", reason_loc);
+	G_connect_rejection_reason = reason_loc;
+	my_client_radio_connexion_state = 3;
+	connect_state_machine_counter = 0;
+}
+
+static unsigned char loc_data[40];
+
+void signaling_connect_req_TX(void) {
+	//static unsigned char loc_data[30];
+	loc_data[0] = 0x05;	// signaling type = connection request
+	loc_data[1] = 21; 	// field size
+	strcpy ((char*)(loc_data+2), CONF_radio_my_callsign); // callsign
+	IP_int2char (CONF_radio_IP_size_requested, loc_data + 18);
+	loc_data[22] = CONF_radio_static_IP_requested;
+	signaling_TX_add_entry (loc_data, 23);
+	signaling_frame_push();
+	//printf ("\r\nNEW REQUEST TX\r\n\r\n");
+}
+
+void signaling_disconnect_req_process (unsigned loc_ID, unsigned char* loc_callsign) {
+	int i;
+	int existing_entry = -1;
+	for (i=0; i<radio_addr_table_size; i++) {
+		if (strcmp((char*)loc_callsign, CONF_radio_addr_table_callsign[i]) == 0) {
+			existing_entry = i;
+		}
+	}
+	if (existing_entry != -1) {
+		CONF_radio_addr_table_status[existing_entry] = 0;
+	}
+	signaling_disconnect_ACK_TX(loc_ID, loc_callsign);
+	signaling_disconnect_ACK_TX(loc_ID, loc_callsign);//sends 2 times
+}
+
+void signaling_disconnect_ACK_process (unsigned loc_ID, unsigned char* loc_callsign) {
+	my_client_radio_connexion_state = 5;
+	my_radio_client_ID = 0x7E;
+	TDMA_NULL_frame_init(70);
+}
+
+void signaling_disconnect_req_TX (void) {
+	//static unsigned char loc_data[30]; // moved global
+	loc_data[0] = 0x0B;	// signaling type = disconnect ACK
+	loc_data[1] = 17; 	// field size
+	loc_data[2] = my_radio_client_ID;
+	strcpy ((char*)(loc_data+3), CONF_radio_my_callsign);
+	signaling_TX_add_entry (loc_data, 19);
+	signaling_frame_push();
+}
+
+void signaling_disconnect_ACK_TX (unsigned loc_ID, unsigned char* loc_callsign) {
+	//static unsigned char loc_data[30]; // moved global
+	loc_data[0] = 0x0C;	// signaling type = disconnect ACK
+	loc_data[1] = 17; 	// field size
+	loc_data[2] = loc_ID;
+	strcpy ((char*)(loc_data+3), (char*)loc_callsign);
+	signaling_TX_add_entry (loc_data, 19);
+	signaling_frame_push();
+}
+
+// TX part
+//void signaling_frame_init(unsigned char* TX_signal_frame_raw) {
+void signaling_frame_init(void) {
+	if (is_TDMA_master) {
+		TX_signal_frame_raw[0] = 0xFF; //broadcast address (plus parity bit)
+	} else {
+		TX_signal_frame_raw[0] = my_radio_client_ID + parity_bit_elab[(my_radio_client_ID & 0x7F)]; //addr slave
+	}
+	TX_signal_frame_raw[1] = 0x1E; // protocol = signaling
+	TX_signal_frame_point = 2;
+}
+
+//void signaling_single_whois_TX(unsigned char* TX_signal_frame_raw, unsigned char loc_ID, char* loc_callsign, 
+void signaling_single_whois_TX(unsigned char loc_ID, char* loc_callsign, 
+		unsigned long int loc_IP_start, unsigned long int loc_IP_size, 
+		unsigned char RSSI_loc, unsigned short int BER_loc, short int TA_loc) {
+	loc_data[0] = 0x01; //field type = who
+	loc_data[1] = 30; // field length previous 30
+	loc_data[2] = loc_ID;
+
+	strcpy ((char*)(loc_data+3), loc_callsign);
+	loc_data[18] = 0; //null termination of callsign
+	IP_int2char (loc_IP_start, loc_data + 19); // IP start
+	IP_int2char (loc_IP_size, loc_data + 23); // IP start
+	loc_data[27] = RSSI_loc; // RSSI uplink
+	loc_data[28] = BER_loc & 0xFF; // error rate uplink (lsB first)
+	loc_data[29] = (BER_loc & 0xFF00) >> 8;
+	loc_data[30] = TA_loc & 0xFF;
+	loc_data[31] = (TA_loc & 0xFF00) >> 8;
+	signaling_TX_add_entry (loc_data, 32); //previous 27
+}
+
+//void signaling_whois_TX(unsigned char* TX_signal_frame_raw) {
+void signaling_whois_TX(void) {
+	int i; 
+	unsigned int RSSI_loc;
+	if (is_TDMA_master) {
+		signaling_single_whois_TX (0x7F, CONF_radio_my_callsign, LAN_conf_applied.LAN_modem_IP, 0, 0, 0, 0); // master entry
+		for (i=0; i<radio_addr_table_size; i++) { // client entries
+			if (CONF_radio_addr_table_status[i]) {
+				RSSI_loc = (G_radio_addr_table_RSSI[i] & 0xFF00) >> 8;
+				signaling_single_whois_TX (i, CONF_radio_addr_table_callsign[i], 
+					CONF_radio_addr_table_IP_begin[i], CONF_radio_addr_table_IP_size[i], 
+					RSSI_loc, G_radio_addr_table_BER[i], (short int)(TDMA_table_TA[i] / 10) );
+			}
+		}
+		
+	} 
+	else if (my_client_radio_connexion_state == 2) { //Slave, only sends if really connected
+		signaling_single_whois_TX (my_radio_client_ID, CONF_radio_my_callsign, LAN_conf_applied.DHCP_range_start, LAN_conf_applied.DHCP_range_size, G_downlink_RSSI, G_downlink_BER, 0); // client's own entry
+		signaling_single_whois_TX (0x7F, CONF_radio_master_callsign, LAN_conf_applied.LAN_modem_IP, 0, 0, 0, 0); //MASTER entry
+	}
+}
+
+void signaling_TX_add_entry(unsigned char* raw_data, int size) {
+	if (TX_signal_frame_point == 0) {
+		signaling_frame_init();
+	}
+	if ( (TX_signal_frame_point + size) < 248) { //enough space for this entry in current frame
+		memcpy ((TX_signal_frame_raw + TX_signal_frame_point), raw_data, size);
+		TX_signal_frame_point = TX_signal_frame_point + size;
+	} else { // not enough space
+		signaling_frame_push(); // send previous entries
+		signaling_frame_init(); // initialize new frame
+		memcpy ((TX_signal_frame_raw + TX_signal_frame_point), raw_data, size);
+		TX_signal_frame_point = TX_signal_frame_point + size;
+	}
+}
+
+//void signaling_frame_push(unsigned char* TX_signal_frame_raw) {
+void signaling_frame_push(void) {
+	//int rsize_needed;
+	int size_w_FEC;
+	int size_wo_FEC;
+	unsigned char rframe_length;
+	unsigned int timer_snapshot;
+
+	TX_signal_frame_raw[TX_signal_frame_point] = 0xFF; // END flag
+	TX_signal_frame_raw[TX_signal_frame_point + 1] = 0x00; // size 0
+	TX_signal_frame_point = TX_signal_frame_point + 2;
+	size_wo_FEC = TX_signal_frame_point;
+	if (size_wo_FEC < 69) {
+		size_wo_FEC = 69;
+	}
+	//rsize_needed = 100 + (size_wo_FEC * 1.4);
+
+	//printf("sig NO ext SRAM\r\n");
+	//if ((TXPS_FIFO->last_ready - TXPS_FIFO->RD_point) < (TXPS_FIFO_threshold_sig - rsize_needed) ) { //16380  
+	if (TX_FIFO_full_global(0) == 0) {
+		timer_snapshot = GLOBAL_timer.read_us();
+		//TXPS_FIFO->data[TXPS_FIFO->WR_point & TXPS_FIFO->mask] = (timer_snapshot >> 16) & 0xFF; //timer 
+		rframe_TX[0] = (timer_snapshot >> 16) & 0xFF;
+		//TXPS_FIFO->WR_point++;
+		size_w_FEC = size_w_FEC_compute (size_wo_FEC);
+		
+		rframe_length = size_w_FEC + 1 - SI4463_offset_size;
+		//if (rframe_length < 0) {rframe_length = 0;}
+		//TXPS_FIFO->data[TXPS_FIFO->WR_point & TXPS_FIFO->mask] = rframe_length; 
+		//TXPS_FIFO->WR_point++;
+		rframe_TX[1] = rframe_length;
+		//TXPS_FIFO->data[TXPS_FIFO->WR_point & TXPS_FIFO->mask] = 0x00; //TDMA byte
+		//TXPS_FIFO->WR_point++;
+		rframe_TX[2] = 0x00; //TDMA byte
+		//size_w_FEC = FEC_encode(TX_signal_frame_raw, TXPS_FIFO, size_wo_FEC);
+		size_w_FEC = FEC_encode2(TX_signal_frame_raw, rframe_TX+3, size_wo_FEC);
+		//TX_intern_FIFO_write(rframe_TX, size_w_FEC+3);
+		TX_FIFO_write_global(rframe_TX, size_w_FEC+3);
+		//TXPS_FIFO->last_ready = TXPS_FIFO->WR_point;
+	}
+	TX_signal_frame_point = 0;
+}
+
+void signaling_periodic_call() { // called every 2 to 6 seconds
+	int i;
+	unsigned int time_since_last_ack;
+	unsigned int timer_snapshot;
+	// CLIENT STATE MACHINE
+	if (is_TDMA_master == 0) {
+		if ( (my_client_radio_connexion_state==1) && (connect_state_machine_counter>2) ) {//waiting for connexion
+			signaling_connect_req_TX();
+			connect_state_machine_counter = 0;
+			timer_snapshot = GLOBAL_timer.read_us();
+			if ( (timer_snapshot - last_rframe_seen) > CONF_radio_timeout_small) {
+				SI4463_prepa_TX_1_call.attach_us(&SI4463_prepa_TX_1, 500000);
+			}
+		}
+		if ( (my_client_radio_connexion_state==2) && (connect_state_machine_counter>5) ) {//already connected periodic update
+			signaling_connect_req_TX();
+			// no counter reset, the ack reception does it
+		}
+		if ( (my_client_radio_connexion_state==3) && (connect_state_machine_counter>15) ) {//rejected, new attempt every 15
+			signaling_connect_req_TX();
+			connect_state_machine_counter = 0;
+		}
+		if ( (my_client_radio_connexion_state==2) && (time_counter_last_ack > connexion_timeout) ) {//timeout, no ACK received for long time
+			// transition to state 1 "waiting for connection"
+			my_client_radio_connexion_state = 1;
+			radio_flush_TX_FIFO();
+			my_radio_client_ID = 0x7E;
+			TDMA_NULL_frame_init(70);
+		}
+		if ( (my_client_radio_connexion_state==4) && (connect_state_machine_counter>2) ) {//waiting for disconnection
+			signaling_disconnect_req_TX();
+			connect_state_machine_counter = 0;
+		}
+		connect_state_machine_counter++;
+		time_counter_last_ack++;
+	}
+	
+	// MASTER : timeout management for clients
+	if (is_TDMA_master) {
+		timer_snapshot = GLOBAL_timer.read_us();
+		for (i=0; i< radio_addr_table_size; i++) {
+			time_since_last_ack = timer_snapshot - CONF_radio_addr_table_date[i];
+			if ( (CONF_radio_addr_table_status[i] == 1) && (time_since_last_ack >> (2000000*connexion_timeout*CONF_signaling_period)) ) {
+				CONF_radio_addr_table_status[i] = 0; // force disconnect
+			}
+		}
+	}
+	
+	signaling_whois_TX();
+	if (TX_signal_frame_point >0) {
+		signaling_frame_push();
+		
+	}
+}
diff --git a/NPR_FW_source_2020_06_29/NPR_14/source/signaling.h b/NPR_FW_source_2020_06_29/NPR_14/source/signaling.h
new file mode 100755
index 0000000..64c163a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/NPR_14/source/signaling.h
@@ -0,0 +1,63 @@
+// This file is part of "NPR70 modem firmware" software
+// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps) 
+// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
+// 
+// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// "NPR70 modem firmware" is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with "NPR70 modem firmware".  If not, see <http://www.gnu.org/licenses/>
+
+#ifndef SIGNALING_F4
+#define SIGNALING_F4
+
+#include "mbed.h"
+#define connexion_timeout 10
+//multiple of signaling_period 10sec or 20sec or 30sec
+
+void signaling_frame_exploitation (unsigned char* unFECdata, int unFECsize, int TA_input);
+
+void signaling_whois_interpret(unsigned char loc_ID, unsigned char* loc_callsign, 
+	unsigned long int loc_IP_start, unsigned long int loc_IP_size, 
+	unsigned char RSSI_loc, unsigned short int BER_loc, short int TA_loc);
+	
+void signaling_print_who(void);
+
+unsigned long int signaling_lookfor_IP_range(unsigned long int req_size);
+
+void signaling_connect_req_process (unsigned char* client_callsign, unsigned long int req_IP_size, unsigned char req_static_alloc, int TA_input);
+
+void signaling_connect_ACK_process(unsigned char* raw_data);
+
+void signaling_connect_NACK_process (unsigned char reason_loc);
+
+void signaling_connect_req_TX(void);
+
+void signaling_disconnect_req_process (unsigned loc_ID, unsigned char* loc_callsign);
+
+void signaling_disconnect_ACK_process (unsigned loc_ID, unsigned char* loc_callsign);
+
+void signaling_disconnect_ACK_TX (unsigned loc_ID, unsigned char* loc_callsign);
+
+void signaling_frame_init();
+
+void signaling_single_whois_TX(unsigned char loc_ID, char* loc_callsign, 
+		unsigned long int loc_IP_start, unsigned long int loc_IP_size, 
+		unsigned char RSSI_loc, unsigned short int BER_loc, short int TA_loc);
+		
+void signaling_TX_add_entry(unsigned char* raw_data, int size);
+		
+void signaling_whois_TX();
+
+void signaling_frame_push();
+	
+void signaling_periodic_call();
+	
+#endif
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/how_to_compile.txt b/NPR_FW_source_2020_06_29/how_to_compile.txt
new file mode 100755
index 0000000..bed6285
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/how_to_compile.txt
@@ -0,0 +1,3 @@
+You can compile with either:
+ * ARM Mbed CLI (the offline toolchain for ARM Mbed)
+ * GCC_ARM (via makefile)
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/README.txt b/NPR_FW_source_2020_06_29/radio_config_generation_2/README.txt
new file mode 100755
index 0000000..41c0d96
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/README.txt
@@ -0,0 +1 @@
+This small windows program creates the "SI4463.h" files for each modulation, with one different constant name for each configuration, from the .h generated with "Scilicol Labs - Wireless Development Suite". 
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_10.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_10.h
new file mode 100755
index 0000000..f85583f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_10.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 56000    Fdev(Hz): 14000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 3 (BW =  92.61 kHz);  NB-filter 3 (BW = 92.61 kHz)
+// 
+// Modulation index: 0.5
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x11, 0x17, 0x00, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x03
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xD3
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x43
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xA5, 0x58, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x12, 0x81, 0xE9
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x71, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0F, 0x0F, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x9B, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x05, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_11.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_11.h
new file mode 100755
index 0000000..e31f758
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_11.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 100000    Fdev(Hz): 50000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 206.12 kHz);  NB-filter 2 (BW = 206.12 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x28
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xF6
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8A, 0x3E
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xA6, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_12.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_12.h
new file mode 100755
index 0000000..7b37ca2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_12.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 180000    Fdev(Hz): 90000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 3 (BW = 370.45 kHz);  NB-filter 3 (BW = 370.45 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x49
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xBA
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCD, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_13.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_13.h
new file mode 100755
index 0000000..513e046
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_13.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 300000    Fdev(Hz): 150000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 5 (BW = 593.60 kHz);  NB-filter 5 (BW = 593.60 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x7A
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xE1
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x02, 0xEB, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_14.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_14.h
new file mode 100755
index 0000000..4f09292
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_14.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 500000    Fdev(Hz): 250000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 824.50 kHz);  NB-filter 2 (BW = 824.50 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0xCC
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xCD
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x04, 0x61, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_20.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_20.h
new file mode 100755
index 0000000..f7ec917
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_20.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 50000    Fdev(Hz): 8333    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 103.06 kHz);  NB-filter 2 (BW = 103.06 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x14
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x7B
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x4B
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x12, 0x85, 0x1F
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCB, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_21.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_21.h
new file mode 100755
index 0000000..195bed2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_21.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 100000    Fdev(Hz): 16667    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 206.12 kHz);  NB-filter 2 (BW = 206.12 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x28
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xF6
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8A, 0x3E
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xA6, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_22.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_22.h
new file mode 100755
index 0000000..420ee5f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_22.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 180000    Fdev(Hz): 30000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 3 (BW = 370.45 kHz);  NB-filter 3 (BW = 370.45 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x49
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xBA
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCD, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_23.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_23.h
new file mode 100755
index 0000000..c219944
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_23.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 300000    Fdev(Hz): 50000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 4 (BW = 661.10 kHz);  NB-filter 4 (BW = 661.10 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x7A
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xE1
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x03, 0x37, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_24.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_24.h
new file mode 100755
index 0000000..b0457f9
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/radio_config_Si4463_24.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 500000    Fdev(Hz): 83333    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 146    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 1 (BW = 915.70 kHz);  NB-filter 1 (BW = 915.70 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xD2
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0xCC
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xCD
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x04, 0x74, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x27, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_10.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_10.xml
new file mode 100755
index 0000000..4e93fe2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_10.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>56.000</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>14.000</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_11.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_11.xml
new file mode 100755
index 0000000..2a0a36f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_11.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>100</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>50</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_12.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_12.xml
new file mode 100755
index 0000000..2324635
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_12.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>180</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>90</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_13.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_13.xml
new file mode 100755
index 0000000..cb07ecb
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_13.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>300</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_14.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_14.xml
new file mode 100755
index 0000000..15c1c93
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_14.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>500</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>250</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_20.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_20.xml
new file mode 100755
index 0000000..ef6b38b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_20.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>50</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>8.333</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_21.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_21.xml
new file mode 100755
index 0000000..c073cda
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_21.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>100</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>16.667</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_22.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_22.xml
new file mode 100755
index 0000000..9698585
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_22.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>180</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_23.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_23.xml
new file mode 100755
index 0000000..edd6b00
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_23.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>300</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>50</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_24.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_24.xml
new file mode 100755
index 0000000..8a3a57a
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_2m/si4463_revc2_empty_framework_24.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>146</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>500</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>83.333</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_10.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_10.h
new file mode 100755
index 0000000..f85583f
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_10.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 56000    Fdev(Hz): 14000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 3 (BW =  92.61 kHz);  NB-filter 3 (BW = 92.61 kHz)
+// 
+// Modulation index: 0.5
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x11, 0x17, 0x00, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x03
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xD3
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x43
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xA5, 0x58, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x12, 0x81, 0xE9
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x71, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0F, 0x0F, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x9B, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x05, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_11.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_11.h
new file mode 100755
index 0000000..7ee715c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_11.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 100000    Fdev(Hz): 50000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 206.12 kHz);  NB-filter 2 (BW = 206.12 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x0D
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xA7
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x00, 0x00, 0x00, 0x23, 0x86, 0xD4
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_12.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_12.h
new file mode 100755
index 0000000..5fca190
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_12.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 180000    Fdev(Hz): 90000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 3 (BW = 370.45 kHz);  NB-filter 3 (BW = 370.45 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x18
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x93
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8C, 0x4A
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_13.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_13.h
new file mode 100755
index 0000000..6952b35
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_13.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 300000    Fdev(Hz): 150000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 5 (BW = 593.60 kHz);  NB-filter 5 (BW = 593.60 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xF6
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8A, 0x3E
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x9A, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_14.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_14.h
new file mode 100755
index 0000000..c6e2318
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_14.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 500000    Fdev(Hz): 250000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 824.50 kHz);  NB-filter 2 (BW = 824.50 kHz)
+// 
+// Modulation index: 1
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x44
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x44
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x76, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_20.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_20.h
new file mode 100755
index 0000000..b78bb34
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_20.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 50000    Fdev(Hz): 8333    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 103.06 kHz);  NB-filter 2 (BW = 103.06 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x06
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xD4
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x4B
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x12, 0x81, 0xB5
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCB, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_21.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_21.h
new file mode 100755
index 0000000..fb2e094
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_21.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 100000    Fdev(Hz): 16667    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 2 (BW = 206.12 kHz);  NB-filter 2 (BW = 206.12 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x0D
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xA7
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x23, 0x86, 0xD4
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_22.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_22.h
new file mode 100755
index 0000000..6906bc3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_22.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 180000    Fdev(Hz): 30000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 3 (BW = 370.45 kHz);  NB-filter 3 (BW = 370.45 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x18
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x93
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8C, 0x4A
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_23.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_23.h
new file mode 100755
index 0000000..f3f7af6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_23.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 300000    Fdev(Hz): 50000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 4 (BW = 661.10 kHz);  NB-filter 4 (BW = 661.10 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xF6
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8A, 0x3E
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xC3, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_24.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_24.h
new file mode 100755
index 0000000..5a80037
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/radio_config_Si4463_24.h
@@ -0,0 +1,1069 @@
+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4463 Rev.: C2                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 5    Rsymb(sps): 500000    Fdev(Hz): 83333    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2    
+// RF Freq.(MHz): 430    API_TC: 29    fhst: 40000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// API_ARR_Det_en: 0    Fdev_error: 0    API_ETSI: 0    
+// 
+// # RX IF frequency is  -468750 Hz
+// # WB filter 1 (BW = 915.70 kHz);  NB-filter 1 (BW = 915.70 kHz)
+// 
+// Modulation index: 0.333
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+
+#include "..\drivers\radio\Si446x\si446x_patch.h"
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+*/
+#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_PREAMBLE_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x10
+// Start ID:                 0x04
+// Default values:           0x21, 
+// Descriptions:
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+*/
+#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x46
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
+
+/*
+// Set properties:           RF_MODEM_RSSI_JUMP_THRESH_4
+// Number of properties:     4
+// Group ID:                 0x20
+// Start ID:                 0x4B
+// Default values:           0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00
+
+/*
+// Set properties:           RF_PA_TC_1
+// Number of properties:     1
+// Group ID:                 0x22
+// Start ID:                 0x03
+// Default values:           0x5D, 
+// Descriptions:
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE
+
+/*
+// Command:                  RF_START_RX
+// Description:              Switches to RX state and starts reception of a packet.
+*/
+#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Command:                  RF_IRCAL
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0
+
+/*
+// Command:                  RF_IRCAL_1
+// Description:              Image rejection calibration.
+*/
+#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0
+
+/*
+// Set properties:           RF_GLOBAL_CLK_CFG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x01
+// Default values:           0x00, 
+// Descriptions:
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_3
+// Number of properties:     3
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+//   INT_CTL_MODEM_ENABLE - Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_3 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_6
+// Number of properties:     6
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+//   SYNC_CONFIG2 - Sync Word configuration bits.
+*/
+#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+//   PKT_CONFIG2 - General packet configuration bits.
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+*/
+#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30
+
+/*
+// Set properties:           RF_PKT_RX_THRESHOLD_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x0C
+// Default values:           0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+*/
+#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_3_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x18
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+*/
+#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_1_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x24
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+*/
+#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_4_CRC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x12
+// Start ID:                 0x30
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_SEED_31_24_4
+// Number of properties:     4
+// Group ID:                 0x12
+// Start ID:                 0x36
+// Default values:           0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
+//   PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
+*/
+#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x44
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x44
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
+//   MODEM_IFPKD_THRESHOLDS - 
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+*/
+#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C
+
+/*
+// Set properties:           RF_MODEM_BCR_NCO_OFFSET_2_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x24
+// Default values:           0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, 
+// Descriptions:
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+//   MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+*/
+#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF
+
+/*
+// Set properties:           RF_MODEM_AFC_LIMITER_1_3_1
+// Number of properties:     3
+// Group ID:                 0x20
+// Start ID:                 0x30
+// Default values:           0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x7C, 0xA0
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_12_1
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+//   MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x27, 0x0C, 0xA4, 0x23
+
+/*
+// Set properties:           RF_MODEM_RAW_CONTROL_10
+// Number of properties:     10
+// Group ID:                 0x20
+// Start ID:                 0x45
+// Default values:           0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, 
+// Descriptions:
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+//   MODEM_RSSI_THRESH - Configures the RSSI threshold.
+//   MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
+//   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
+//   MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40
+
+/*
+// Set properties:           RF_MODEM_RAW_SEARCH2_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x50
+// Default values:           0x00, 0x08, 
+// Descriptions:
+//   MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
+
+/*
+// Set properties:           RF_MODEM_SPIKE_DET_2_1
+// Number of properties:     2
+// Group ID:                 0x20
+// Start ID:                 0x54
+// Default values:           0x00, 0x00, 
+// Descriptions:
+//   MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
+//   MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
+*/
+#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
+
+/*
+// Set properties:           RF_MODEM_RSSI_MUTE_1_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x57
+// Default values:           0x00, 
+// Descriptions:
+//   MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
+*/
+#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00
+
+/*
+// Set properties:           RF_MODEM_DSA_CTRL1_5_1
+// Number of properties:     5
+// Group ID:                 0x20
+// Start ID:                 0x5B
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
+//   MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
+//   MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
+//   MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
+*/
+#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7_1
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8_1
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        SI446X_PATCH_CMDS, \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x05, RF_GLOBAL_XO_TUNE_1, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x05, RF_PREAMBLE_CONFIG_1, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
+        0x09, RF_MODEM_RAW_CONTROL_5, \
+        0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \
+        0x06, RF_MODEM_RAW_SEARCH2_2, \
+        0x06, RF_MODEM_SPIKE_DET_2, \
+        0x05, RF_MODEM_RSSI_MUTE_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x05, RF_PA_TC_1, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x08, RF_START_RX, \
+        0x05, RF_IRCAL, \
+        0x05, RF_IRCAL_1, \
+        0x05, RF_GLOBAL_CLK_CFG_1, \
+        0x05, RF_GLOBAL_CONFIG_1_1, \
+        0x07, RF_INT_CTL_ENABLE_3, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x0A, RF_SYNC_CONFIG_6, \
+        0x10, RF_PKT_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_THRESHOLD_12, \
+        0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
+        0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
+        0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
+        0x08, RF_PKT_CRC_SEED_31_24_4, \
+        0x10, RF_MODEM_MOD_TYPE_12_1, \
+        0x05, RF_MODEM_FREQ_DEV_0_1_1, \
+        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
+        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
+        0x05, RF_MODEM_AGC_CONTROL_1_1, \
+        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+        0x0E, RF_MODEM_RAW_CONTROL_10, \
+        0x06, RF_MODEM_RAW_SEARCH2_2_1, \
+        0x06, RF_MODEM_SPIKE_DET_2_1, \
+        0x05, RF_MODEM_RSSI_MUTE_1_1, \
+        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8_1, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_10.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_10.xml
new file mode 100755
index 0000000..4e93fe2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_10.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>56.000</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>14.000</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_11.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_11.xml
new file mode 100755
index 0000000..723fcc2
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_11.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>100</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>50</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_12.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_12.xml
new file mode 100755
index 0000000..c9f969d
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_12.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>180</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>90</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_13.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_13.xml
new file mode 100755
index 0000000..169beee
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_13.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>300</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>29</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_14.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_14.xml
new file mode 100755
index 0000000..04a6c93
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_14.xml
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>2</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>500</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>250</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_20.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_20.xml
new file mode 100755
index 0000000..54ed9b7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_20.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>50</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>8.333</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_21.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_21.xml
new file mode 100755
index 0000000..e61b529
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_21.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>100</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>16.667</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_22.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_22.xml
new file mode 100755
index 0000000..149290b
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_22.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>180</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_23.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_23.xml
new file mode 100755
index 0000000..1403152
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_23.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>300</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>50</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_24.xml b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_24.xml
new file mode 100755
index 0000000..a1cffb6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_70cm/si4463_revc2_empty_framework_24.xml
@@ -0,0 +1,531 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<RCA_ProjectData ProjectName="Empty framework" ChipType="Si4463" ChipRevision="C2" Version="3.2.11.0">
+  <DataItems>
+    <tbpFrequencyAndPower Type="System.Windows.Forms.TabPage">
+      <grbFequencyControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelNumber">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCenterFrequency">
+          <Value>430</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudChannelSpacing">
+          <Value>40</Value>
+        </DataItem>
+      </grbFequencyControl>
+      <grbCrystalControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseExternalTCXO">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceTX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalToleranceRX">
+          <Value>20</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalFrequency">
+          <Value>30</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudCrystalCapBank">
+          <Value>82</Value>
+        </DataItem>
+      </grbCrystalControl>
+      <DataItem Type="System.Windows.Forms.CheckBox" Name="chbDividedSystemClock">
+        <Checked>False</Checked>
+      </DataItem>
+      <grbClockOutput Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb32kHzClock">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbClockOutput>
+      <grbPowerAmplifierControl Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePaExternalRamp">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaRampTC">
+          <Value>29</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPaMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPaPowerLevel">
+          <Value>127</Value>
+        </DataItem>
+      </grbPowerAmplifierControl>
+    </tbpFrequencyAndPower>
+    <tbpRfParameters Type="System.Windows.Forms.TabPage">
+      <grbRfParameters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbModulationType">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDataRate">
+          <Value>500</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviation">
+          <Value>83.333</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationError">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudDeviationErrorNegative">
+          <Value>0</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbManualRxBandwidth">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.CustomContols.NumericUpDownExtended" Name="nudBandwidth">
+          <Value>150</Value>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbb4GfskMap">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbIfMode">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataRateError">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <pnlRssiControl Type="System.Windows.Forms.Panel">
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiLatch">
+            <SelectedIndex>2</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbRssiAverage">
+            <SelectedIndex>0</SelectedIndex>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.CheckBox" Name="chbCheckThresholdAtLatch">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudRssiThreshold">
+            <Value>255</Value>
+          </DataItem>
+        </pnlRssiControl>
+        <grbHighPerformance Type="System.Windows.Forms.GroupBox">
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedSelectivity">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbImprovedBlocking">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowPower">
+            <Checked>False</Checked>
+          </DataItem>
+          <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighPerformance">
+            <Checked>True</Checked>
+          </DataItem>
+        </grbHighPerformance>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableDsa">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableHighPerformanceChannelFilter">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableAntennaDiversity">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableIqCalibration">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePllAFC">
+          <Checked>False</Checked>
+        </DataItem>
+      </grbRfParameters>
+    </tbpRfParameters>
+    <tbpPacketHandler Type="System.Windows.Forms.TabPage">
+      <pccPacketHandlerConfigurator Type="NewWDS.PacketConfigControl">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPacketStructure">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+        <tabGeneralConfig Type="System.Windows.Forms.TabControl">
+          <tbpGeneralPacketConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketRxThreshold">
+              <Value>64</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketTxThreshold">
+              <Value>48</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudNumOfFields">
+              <Value>2</Value>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetDataWhiteningAtBeginingOfThePackets">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUseSyncWord">
+              <Checked>True</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbUsePreambel">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralPacketConfig>
+          <tbpVariableLengthConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableVariablePacketLength">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbVariablePacketLen Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPacketLengthAdjust">
+                <Value>90</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudVariableFieldNum">
+                <Value>2</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudLengthInField">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPacketLengthInMsb">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbAddLengthToFifo">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbVariablePacketLen>
+          </tbpVariableLengthConfig>
+          <tbpGeneralCrcConfig Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbCrcSeed">
+              <Text>00 00 00 00</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbResetCRCAtBeginingOfThePacket">
+              <Checked>True</Checked>
+            </DataItem>
+            <grbCrcPolynomial Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbCrcPolynomial">
+                <SelectedIndex>4</SelectedIndex>
+              </DataItem>
+            </grbCrcPolynomial>
+          </tbpGeneralCrcConfig>
+          <tbpGeneralDataWhiteningConfiguration Type="System.Windows.Forms.TabPage">
+            <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDataWhiteningPolynomial">
+              <SelectedIndex>1</SelectedIndex>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbDataWhiteningSeed">
+              <Text>FF FF</Text>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudOutputBitNumber">
+              <Value>0</Value>
+            </DataItem>
+            <grbPnDirection Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionForward">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPnDirectionReversed">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbPnDirection>
+          </tbpGeneralDataWhiteningConfiguration>
+          <tbpGeneralFieldConfig Type="System.Windows.Forms.TabPage">
+            <grbDataBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbDataMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbDataBitOrder>
+            <grbCrcEndian Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbHighBytesFirst">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLowBytesFirst">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbCrcEndian>
+            <grbBitOrder Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbLsbFirst">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbMsbFirst">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbBitOrder>
+            <grbManchesterPattern Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs01">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.RadioButton" Name="rdb0eqs10">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbManchesterPattern>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbInvertCrc">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbRxChainOnAfterRx">
+              <Checked>False</Checked>
+            </DataItem>
+            <DataItem Type="System.Windows.Forms.CheckBox" Name="chbModem4Gfsk">
+              <Checked>True</Checked>
+            </DataItem>
+          </tbpGeneralFieldConfig>
+        </tabGeneralConfig>
+        <tabFieldConfig Type="NewWDS.CustomTablessTabControl">
+          <tbpPreamble Type="System.Windows.Forms.TabPage">
+            <grbPreamble Type="System.Windows.Forms.GroupBox">
+              <grbPreambleType Type="System.Windows.Forms.GroupBox">
+                <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbPreamblePattern">
+                  <SelectedIndex>0</SelectedIndex>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType0101">
+                  <Checked>False</Checked>
+                </DataItem>
+                <DataItem Type="System.Windows.Forms.RadioButton" Name="rdbPreambleType1010">
+                  <Checked>True</Checked>
+                </DataItem>
+              </grbPreambleType>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleTxLength">
+                <Value>16</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.TrackBar" Name="trbPreambleTimeot">
+                <Value>30</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbPreambleManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudPreambleRXThreshold">
+                <Value>20</Value>
+              </DataItem>
+            </grbPreamble>
+          </tbpPreamble>
+          <tbpSyncWord Type="System.Windows.Forms.TabPage">
+            <grbSyncWord Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordErrorAtBeginningOnly">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLength">
+                <Value>3</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordAllowedBitError">
+                <Value>0</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudSyncWordLengthSubtract">
+                <Value>0</Value>
+              </DataItem>
+              <swcSyncWord Type="NewWDS.Applications.App_Common.PacketConfigControl.SyncWordInputControl">
+                <DataItem Type="System.Windows.Forms.MaskedTextBox" Name="mtbSyncWord">
+                  <Text>A2 4B 33</Text>
+                </DataItem>
+              </swcSyncWord>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWordManchesterEncoded">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSyncWord4GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSkipSyncWordTimeout">
+                <Checked>False</Checked>
+              </DataItem>
+            </grbSyncWord>
+          </tbpSyncWord>
+          <tbpField5 Type="System.Windows.Forms.TabPage">
+            <grbField5 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField5Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField5ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField54GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField5>
+          </tbpField5>
+          <tbpField4 Type="System.Windows.Forms.TabPage">
+            <grbField4 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField4Length">
+                <Value>7</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField4ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField44GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField4>
+          </tbpField4>
+          <tbpField3 Type="System.Windows.Forms.TabPage">
+            <grbField3 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField3Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3DataWhitening">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField3ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField34GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField3>
+          </tbpField3>
+          <tbpField2 Type="System.Windows.Forms.TabPage">
+            <grbField2 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField2Length">
+                <Value>63</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField2ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField24GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField2>
+          </tbpField2>
+          <tbpField1 Type="System.Windows.Forms.TabPage">
+            <grbField1 Type="System.Windows.Forms.GroupBox">
+              <DataItem Type="System.Windows.Forms.NumericUpDown" Name="nudField1Length">
+                <Value>1</Value>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1EnableCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1CheckCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1TransmitCRC">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1DataWhitening">
+                <Checked>True</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField1ManchesterEncoding">
+                <Checked>False</Checked>
+              </DataItem>
+              <DataItem Type="System.Windows.Forms.CheckBox" Name="chbField14GfskModulated">
+                <Checked>True</Checked>
+              </DataItem>
+            </grbField1>
+          </tbpField1>
+        </tabFieldConfig>
+      </pccPacketHandlerConfigurator>
+    </tbpPacketHandler>
+    <tbpInterrupts Type="System.Windows.Forms.TabPage">
+      <grbChipInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableChipInterrupt">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstChipInterruptStatus">
+          <Enabled>False</Enabled>
+          <Value>0</Value>
+        </DataItem>
+      </grbChipInterrupt>
+      <grbModemInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnableModemInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstModemInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>1</Value>
+        </DataItem>
+      </grbModemInterrupt>
+      <grbPacketHandlerInterrupt Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbEnablePacketHandlerInterrupt">
+          <Checked>True</Checked>
+        </DataItem>
+        <DataItem Type="NewWDS.Applications.App_Common.ByteStatusControl.ByteStatus" Name="bstPacketHandlerInterruptStatus">
+          <Enabled>True</Enabled>
+          <Value>51</Value>
+        </DataItem>
+      </grbPacketHandlerInterrupt>
+      <grbColorDescrition Type="System.Windows.Forms.GroupBox" />
+    </tbpInterrupts>
+    <tbpGPIO Type="System.Windows.Forms.TabPage">
+      <grbFastResponseRegisters Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrA">
+          <SelectedIndex>4</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrC">
+          <SelectedIndex>10</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrD">
+          <SelectedIndex>9</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbFrrB">
+          <SelectedIndex>6</SelectedIndex>
+        </DataItem>
+      </grbFastResponseRegisters>
+      <grbGPIO Type="System.Windows.Forms.GroupBox">
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio0Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio0">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio1Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio1">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio2Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio2">
+          <SelectedIndex>RX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbGpio3Pullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbGpio3">
+          <SelectedIndex>TX_STATE</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbNirqPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbNirq">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.CheckBox" Name="chbSdoPullup">
+          <Checked>False</Checked>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbSdo">
+          <SelectedIndex>DONOTHING</SelectedIndex>
+        </DataItem>
+        <DataItem Type="System.Windows.Forms.ComboBox" Name="cbbDriveStrength">
+          <SelectedIndex>0</SelectedIndex>
+        </DataItem>
+      </grbGPIO>
+    </tbpGPIO>
+  </DataItems>
+</RCA_ProjectData>
\ No newline at end of file
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_11.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_11.h
new file mode 100755
index 0000000..89e29ae
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_11.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_11 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x0D, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xA7, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x00, 0x00, 0x00, 0x23, 0x86, 0xD4, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_11_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_11_2m.h
new file mode 100755
index 0000000..8644c23
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_11_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_11 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xA6, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_12.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_12.h
new file mode 100755
index 0000000..6d1636c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_12.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_12 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x18, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x93, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8C, 0x4A, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_12_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_12_2m.h
new file mode 100755
index 0000000..61707b8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_12_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_12 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x49, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xBA, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCD, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_13.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_13.h
new file mode 100755
index 0000000..60cbad5
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_13.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_13 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x9A, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_13_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_13_2m.h
new file mode 100755
index 0000000..1d4d6a6
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_13_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_13 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xEF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x7A, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xE1, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x02, 0xEB, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_14.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_14.h
new file mode 100755
index 0000000..525c433
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_14.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_14 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x44, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x44, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x76, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_14_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_14_2m.h
new file mode 100755
index 0000000..c41f517
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_14_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_14 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x02, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x06, 0x80, 0x00, 0x3F, 0x02, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0xCC, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xCD, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x00, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x04, 0x61, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x1A, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_20.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_20.h
new file mode 100755
index 0000000..56cf63e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_20.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_20 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x06, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD4, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x12, 0x81, 0xB5, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCB, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_20_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_20_2m.h
new file mode 100755
index 0000000..c25c442
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_20_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_20 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x14, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x7B, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x12, 0x85, 0x1F, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCB, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_21.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_21.h
new file mode 100755
index 0000000..875d157
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_21.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_21 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x0D, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xA7, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x23, 0x86, 0xD4, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_21_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_21_2m.h
new file mode 100755
index 0000000..d49e910
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_21_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_21 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xA6, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x15, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x08, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_22.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_22.h
new file mode 100755
index 0000000..11ffd8c
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_22.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_22 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x18, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x93, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8C, 0x4A, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x00, 0xD3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_22_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_22_2m.h
new file mode 100755
index 0000000..3f6e51e
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_22_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_22 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x36, 0xEE, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x49, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xBA, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x20, 0x00, 0xE8, 0x00, 0x53, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xCD, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xF9, 0x01, 0x00, 0xFF, 0x06, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_23.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_23.h
new file mode 100755
index 0000000..b6741f3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_23.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_23 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xF6, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8A, 0x3E, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0xC3, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_23_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_23_2m.h
new file mode 100755
index 0000000..8e7bfa4
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_23_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_23 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x2D, 0xC6, 0xC0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x7A, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xE1, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x64, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x05, 0x1E, 0xB8, 0x05, 0x1F, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x03, 0x37, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x0B, 0x0B, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xD0, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_24.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_24.h
new file mode 100755
index 0000000..5d242a3
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_24.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_24 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x46, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x23, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x44, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0x44, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x7C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x38, 0x0A, 0xAA, 0xAA, 0x0A, 0xEC, 0x20, 0xFE, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_24_2m.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_24_2m.h
new file mode 100755
index 0000000..a1c93a7
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_config_24_2m.h
@@ -0,0 +1,125 @@
+#define RADIO_CONFIGURATION_DATA_ARRAY_24 { \
+	0x08, 0x04, 0x21, 0x71, 0x4B, 0x00, 0x00, 0xDC, 0x95, \
+	0x08, 0x05, 0xA6, 0x22, 0x21, 0xF0, 0x41, 0x5B, 0x26, \
+	0x08, 0xE2, 0x2F, 0x1C, 0xBB, 0x0A, 0xA8, 0x94, 0x28, \
+	0x08, 0x05, 0x87, 0x67, 0xE2, 0x58, 0x1A, 0x07, 0x5B, \
+	0x08, 0xE1, 0xD0, 0x72, 0xD8, 0x8A, 0xB8, 0x5B, 0x7D, \
+	0x08, 0x05, 0x11, 0xEC, 0x9E, 0x28, 0x23, 0x1B, 0x6D, \
+	0x08, 0xE2, 0x4F, 0x8A, 0xB2, 0xA9, 0x29, 0x14, 0x13, \
+	0x08, 0x05, 0xD1, 0x2E, 0x71, 0x6A, 0x51, 0x4C, 0x2C, \
+	0x08, 0xE5, 0x80, 0x27, 0x42, 0xA4, 0x69, 0xB0, 0x7F, \
+	0x08, 0x05, 0xAA, 0x81, 0x2A, 0xBD, 0x45, 0xE8, 0xA8, \
+	0x08, 0xEA, 0xE4, 0xF0, 0x24, 0xC9, 0x9F, 0xCC, 0x3C, \
+	0x08, 0x05, 0x08, 0xF5, 0x05, 0x04, 0x27, 0x62, 0x98, \
+	0x08, 0xEA, 0x6B, 0x62, 0x84, 0xA1, 0xF9, 0x4A, 0xE2, \
+	0x08, 0x05, 0xE9, 0x77, 0x05, 0x4F, 0x84, 0xEE, 0x35, \
+	0x08, 0xE2, 0x43, 0xC3, 0x8D, 0xFB, 0xAD, 0x54, 0x25, \
+	0x08, 0x05, 0x14, 0x06, 0x5E, 0x39, 0x36, 0x2F, 0x45, \
+	0x08, 0xEA, 0x0C, 0x1C, 0x74, 0xD0, 0x11, 0xFC, 0x32, \
+	0x08, 0x05, 0xDA, 0x38, 0xBA, 0x0E, 0x3C, 0xE7, 0x8B, \
+	0x08, 0xEA, 0xB0, 0x09, 0xE6, 0xFF, 0x94, 0xBB, 0xA9, \
+	0x08, 0x05, 0xD7, 0x11, 0x29, 0xFE, 0xDC, 0x71, 0xD5, \
+	0x08, 0xEA, 0x7F, 0x83, 0xA7, 0x60, 0x90, 0x62, 0x18, \
+	0x08, 0x05, 0x84, 0x7F, 0x6A, 0xD1, 0x91, 0xC6, 0x52, \
+	0x08, 0xEA, 0x2A, 0xD8, 0x7B, 0x8E, 0x4A, 0x9F, 0x91, \
+	0x08, 0x05, 0xBD, 0xAA, 0x9D, 0x16, 0x18, 0x06, 0x15, \
+	0x08, 0xE2, 0x55, 0xAD, 0x2D, 0x0A, 0x14, 0x1F, 0x5D, \
+	0x08, 0x05, 0xD3, 0xE0, 0x7C, 0x39, 0xCF, 0x01, 0xF0, \
+	0x08, 0xEF, 0x3A, 0x91, 0x72, 0x6A, 0x03, 0xBB, 0x96, \
+	0x08, 0xE7, 0x83, 0x6D, 0xA4, 0x92, 0xFC, 0x13, 0xA7, \
+	0x08, 0xEF, 0xF8, 0xFD, 0xCF, 0x62, 0x07, 0x6F, 0x1E, \
+	0x08, 0xE7, 0x4C, 0xEA, 0x4A, 0x75, 0x4F, 0xD6, 0xCF, \
+	0x08, 0xE2, 0xF6, 0x11, 0xE4, 0x26, 0x0D, 0x4D, 0xC6, \
+	0x08, 0x05, 0xFB, 0xBF, 0xE8, 0x07, 0x89, 0xC3, 0x51, \
+	0x08, 0xEF, 0x82, 0x27, 0x04, 0x3F, 0x96, 0xA8, 0x58, \
+	0x08, 0xE7, 0x41, 0x29, 0x3C, 0x75, 0x2A, 0x03, 0x1C, \
+	0x08, 0xEF, 0xAF, 0x59, 0x98, 0x36, 0xAA, 0x0F, 0x06, \
+	0x08, 0xE6, 0xF6, 0x93, 0x41, 0x2D, 0xEC, 0x0E, 0x99, \
+	0x08, 0x05, 0x29, 0x19, 0x90, 0xE5, 0xAA, 0x36, 0x40, \
+	0x08, 0xE7, 0xFB, 0x68, 0x10, 0x7D, 0x77, 0x5D, 0xC0, \
+	0x08, 0xE7, 0xCB, 0xB4, 0xDD, 0xCE, 0x90, 0x54, 0xBE, \
+	0x08, 0xE7, 0x72, 0x8A, 0xD6, 0x02, 0xF4, 0xDD, 0xCC, \
+	0x08, 0xE7, 0x6A, 0x21, 0x0B, 0x02, 0x86, 0xEC, 0x15, \
+	0x08, 0xE7, 0x7B, 0x7C, 0x3D, 0x6B, 0x81, 0x03, 0xD0, \
+	0x08, 0xEF, 0x7D, 0x61, 0x36, 0x94, 0x7C, 0xA0, 0xDF, \
+	0x08, 0xEF, 0xCC, 0x85, 0x3B, 0xDA, 0xE0, 0x5C, 0x1C, \
+	0x08, 0xE7, 0xE3, 0x75, 0xBB, 0x39, 0x22, 0x4B, 0xA8, \
+	0x08, 0xEF, 0xF9, 0xCE, 0xE0, 0x5E, 0xEB, 0x1D, 0xCB, \
+	0x08, 0xE7, 0xBD, 0xE2, 0x70, 0xD5, 0xAB, 0x4E, 0x3F, \
+	0x08, 0xE7, 0xB7, 0x8D, 0x20, 0x68, 0x6B, 0x09, 0x52, \
+	0x08, 0xEF, 0xA1, 0x1B, 0x90, 0xCD, 0x98, 0x00, 0x63, \
+	0x08, 0xEF, 0x54, 0x67, 0x5D, 0x9C, 0x11, 0xFC, 0x45, \
+	0x08, 0xE7, 0xD4, 0x9B, 0xC8, 0x97, 0xBE, 0x8A, 0x07, \
+	0x08, 0xEF, 0x52, 0x8D, 0x90, 0x63, 0x73, 0xD5, 0x2A, \
+	0x08, 0xEF, 0x03, 0xBC, 0x6E, 0x1C, 0x76, 0xBE, 0x4A, \
+	0x08, 0xE7, 0xC2, 0xED, 0x67, 0xBA, 0x5E, 0x66, 0x21, \
+	0x08, 0xEF, 0xE7, 0x3F, 0x87, 0xBE, 0xE0, 0x7A, 0x6D, \
+	0x08, 0xE7, 0xC9, 0x70, 0x93, 0x1D, 0x64, 0xF5, 0x6C, \
+	0x08, 0xEF, 0xF5, 0x28, 0x08, 0x34, 0xB3, 0xB6, 0x2C, \
+	0x08, 0xEF, 0x3A, 0x0A, 0xEC, 0x0F, 0xDB, 0x56, 0xCA, \
+	0x08, 0xEF, 0x39, 0xA0, 0x6E, 0xED, 0x79, 0xD0, 0x24, \
+	0x08, 0xE7, 0x6C, 0x0B, 0xAF, 0xA9, 0x4E, 0x40, 0xB5, \
+	0x08, 0xE9, 0xB9, 0xAF, 0xBF, 0x25, 0x50, 0xD1, 0x37, \
+	0x08, 0x05, 0x9E, 0xDB, 0xDE, 0x3F, 0x94, 0xE9, 0x6B, \
+	0x08, 0xEC, 0xC5, 0x05, 0xAA, 0x57, 0xDC, 0x8A, 0x5E, \
+	0x08, 0x05, 0x70, 0xDA, 0x84, 0x84, 0xDD, 0xCA, 0x90, \
+	0x07, 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80, \
+	0x08, 0x13, 0x00, 0x20, 0x21, 0x20, 0x00, 0x00, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x00, 0x52, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x05, 0x11, 0x10, 0x01, 0x04, 0x21, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xD2, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x02, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x69, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x01, 0x5C, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE0, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23, \
+	0x09, 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, \
+	0x08, 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x94, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x03, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, \
+	0x05, 0x11, 0x22, 0x01, 0x03, 0x1D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x3B, 0x0B, 0x00, 0x00, 0x20, 0xC5, 0x20, 0xFA, \
+	0x08, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x05, 0x17, 0x56, 0x10, 0xCA, 0xF0, \
+	0x05, 0x17, 0x13, 0x10, 0xCA, 0xF0, \
+	0x05, 0x11, 0x00, 0x01, 0x01, 0x00, \
+	0x05, 0x11, 0x00, 0x01, 0x03, 0x20, \
+	0x07, 0x11, 0x01, 0x03, 0x00, 0x03, 0x33, 0x01, \
+	0x08, 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0A, 0x09, \
+	0x0D, 0x11, 0x10, 0x09, 0x00, 0x10, 0x14, 0x00, 0xFF, 0x31, 0x00, 0x00, 0x00, 0x00, \
+	0x0A, 0x11, 0x11, 0x06, 0x00, 0x0A, 0x45, 0xD2, 0xCC, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x22, 0x00, 0x2A, 0x01, 0x5A, 0x30, \
+	0x10, 0x11, 0x12, 0x0C, 0x0C, 0x40, 0x00, 0x01, 0x16, 0x80, 0x00, 0x3F, 0x12, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x09, 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x08, 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00, \
+	0x10, 0x11, 0x20, 0x0C, 0x00, 0x05, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0xCC, \
+	0x05, 0x11, 0x20, 0x01, 0x0C, 0xCD, \
+	0x10, 0x11, 0x20, 0x0C, 0x18, 0x05, 0x00, 0x08, 0x02, 0x80, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3C, \
+	0x10, 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x02, 0x02, 0x00, 0x00, 0x23, 0x8F, 0xFF, \
+	0x07, 0x11, 0x20, 0x03, 0x30, 0x04, 0x74, 0xA0, \
+	0x05, 0x11, 0x20, 0x01, 0x35, 0xE2, \
+	0x10, 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x00, 0x1A, 0x15, 0x55, 0x00, 0x27, 0x0C, 0xA4, 0x23, \
+	0x0E, 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x5A, 0x01, 0x00, 0xFF, 0x08, 0x02, 0x18, 0x40, \
+	0x06, 0x11, 0x20, 0x02, 0x50, 0x84, 0x0D, \
+	0x06, 0x11, 0x20, 0x02, 0x54, 0x04, 0x07, \
+	0x05, 0x11, 0x20, 0x01, 0x57, 0x00, \
+	0x09, 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20, \
+	0x10, 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, \
+	0x10, 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, \
+	0x10, 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, \
+	0x08, 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x5D, \
+	0x0B, 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03, \
+	0x10, 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x0C, 0x11, 0x40, 0x08, 0x00, 0x39, 0x0B, 0x33, 0x33, 0x20, 0xC5, 0x20, 0xFA, \
+	0x00 \
+} 
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_which_config.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_which_config.h
new file mode 100755
index 0000000..0ce9eab
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/SI4463_which_config.h
@@ -0,0 +1,3 @@
+#define which_modulation 24
+#define which_band "_2m"
+#include "./SI4463_2m/radio_config_Si4463_24.h"
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/drivers/radio/Si446x/si446x_patch.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/drivers/radio/Si446x/si446x_patch.h
new file mode 100755
index 0000000..97734e8
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/drivers/radio/Si446x/si446x_patch.h
@@ -0,0 +1,80 @@
+// COPYRIGHT=2015 Silicon Laboratories, Inc.
+// GENERATED=09:13 October 20 2015
+// ROMID=0x06
+// FUNCTION=TEST
+// MAJOR=0
+// MINOR=0
+// BUILD=0
+// PATCHID=0xCA90
+// REQUIRES=NONE
+// SIZE=512
+// CRCT=0x714b
+
+#define SI446X_PATCH_ROMID  00
+#define SI446X_PATCH_ID     00
+
+#define SI446X_PATCH_CMDS                   \
+0x08,0x04,0x21,0x71,0x4B,0x00,0x00,0xDC,0x95, \
+0x08,0x05,0xA6,0x22,0x21,0xF0,0x41,0x5B,0x26, \
+0x08,0xE2,0x2F,0x1C,0xBB,0x0A,0xA8,0x94,0x28, \
+0x08,0x05,0x87,0x67,0xE2,0x58,0x1A,0x07,0x5B, \
+0x08,0xE1,0xD0,0x72,0xD8,0x8A,0xB8,0x5B,0x7D, \
+0x08,0x05,0x11,0xEC,0x9E,0x28,0x23,0x1B,0x6D, \
+0x08,0xE2,0x4F,0x8A,0xB2,0xA9,0x29,0x14,0x13, \
+0x08,0x05,0xD1,0x2E,0x71,0x6A,0x51,0x4C,0x2C, \
+0x08,0xE5,0x80,0x27,0x42,0xA4,0x69,0xB0,0x7F, \
+0x08,0x05,0xAA,0x81,0x2A,0xBD,0x45,0xE8,0xA8, \
+0x08,0xEA,0xE4,0xF0,0x24,0xC9,0x9F,0xCC,0x3C, \
+0x08,0x05,0x08,0xF5,0x05,0x04,0x27,0x62,0x98, \
+0x08,0xEA,0x6B,0x62,0x84,0xA1,0xF9,0x4A,0xE2, \
+0x08,0x05,0xE9,0x77,0x05,0x4F,0x84,0xEE,0x35, \
+0x08,0xE2,0x43,0xC3,0x8D,0xFB,0xAD,0x54,0x25, \
+0x08,0x05,0x14,0x06,0x5E,0x39,0x36,0x2F,0x45, \
+0x08,0xEA,0x0C,0x1C,0x74,0xD0,0x11,0xFC,0x32, \
+0x08,0x05,0xDA,0x38,0xBA,0x0E,0x3C,0xE7,0x8B, \
+0x08,0xEA,0xB0,0x09,0xE6,0xFF,0x94,0xBB,0xA9, \
+0x08,0x05,0xD7,0x11,0x29,0xFE,0xDC,0x71,0xD5, \
+0x08,0xEA,0x7F,0x83,0xA7,0x60,0x90,0x62,0x18, \
+0x08,0x05,0x84,0x7F,0x6A,0xD1,0x91,0xC6,0x52, \
+0x08,0xEA,0x2A,0xD8,0x7B,0x8E,0x4A,0x9F,0x91, \
+0x08,0x05,0xBD,0xAA,0x9D,0x16,0x18,0x06,0x15, \
+0x08,0xE2,0x55,0xAD,0x2D,0x0A,0x14,0x1F,0x5D, \
+0x08,0x05,0xD3,0xE0,0x7C,0x39,0xCF,0x01,0xF0, \
+0x08,0xEF,0x3A,0x91,0x72,0x6A,0x03,0xBB,0x96, \
+0x08,0xE7,0x83,0x6D,0xA4,0x92,0xFC,0x13,0xA7, \
+0x08,0xEF,0xF8,0xFD,0xCF,0x62,0x07,0x6F,0x1E, \
+0x08,0xE7,0x4C,0xEA,0x4A,0x75,0x4F,0xD6,0xCF, \
+0x08,0xE2,0xF6,0x11,0xE4,0x26,0x0D,0x4D,0xC6, \
+0x08,0x05,0xFB,0xBF,0xE8,0x07,0x89,0xC3,0x51, \
+0x08,0xEF,0x82,0x27,0x04,0x3F,0x96,0xA8,0x58, \
+0x08,0xE7,0x41,0x29,0x3C,0x75,0x2A,0x03,0x1C, \
+0x08,0xEF,0xAF,0x59,0x98,0x36,0xAA,0x0F,0x06, \
+0x08,0xE6,0xF6,0x93,0x41,0x2D,0xEC,0x0E,0x99, \
+0x08,0x05,0x29,0x19,0x90,0xE5,0xAA,0x36,0x40, \
+0x08,0xE7,0xFB,0x68,0x10,0x7D,0x77,0x5D,0xC0, \
+0x08,0xE7,0xCB,0xB4,0xDD,0xCE,0x90,0x54,0xBE, \
+0x08,0xE7,0x72,0x8A,0xD6,0x02,0xF4,0xDD,0xCC, \
+0x08,0xE7,0x6A,0x21,0x0B,0x02,0x86,0xEC,0x15, \
+0x08,0xE7,0x7B,0x7C,0x3D,0x6B,0x81,0x03,0xD0, \
+0x08,0xEF,0x7D,0x61,0x36,0x94,0x7C,0xA0,0xDF, \
+0x08,0xEF,0xCC,0x85,0x3B,0xDA,0xE0,0x5C,0x1C, \
+0x08,0xE7,0xE3,0x75,0xBB,0x39,0x22,0x4B,0xA8, \
+0x08,0xEF,0xF9,0xCE,0xE0,0x5E,0xEB,0x1D,0xCB, \
+0x08,0xE7,0xBD,0xE2,0x70,0xD5,0xAB,0x4E,0x3F, \
+0x08,0xE7,0xB7,0x8D,0x20,0x68,0x6B,0x09,0x52, \
+0x08,0xEF,0xA1,0x1B,0x90,0xCD,0x98,0x00,0x63, \
+0x08,0xEF,0x54,0x67,0x5D,0x9C,0x11,0xFC,0x45, \
+0x08,0xE7,0xD4,0x9B,0xC8,0x97,0xBE,0x8A,0x07, \
+0x08,0xEF,0x52,0x8D,0x90,0x63,0x73,0xD5,0x2A, \
+0x08,0xEF,0x03,0xBC,0x6E,0x1C,0x76,0xBE,0x4A, \
+0x08,0xE7,0xC2,0xED,0x67,0xBA,0x5E,0x66,0x21, \
+0x08,0xEF,0xE7,0x3F,0x87,0xBE,0xE0,0x7A,0x6D, \
+0x08,0xE7,0xC9,0x70,0x93,0x1D,0x64,0xF5,0x6C, \
+0x08,0xEF,0xF5,0x28,0x08,0x34,0xB3,0xB6,0x2C, \
+0x08,0xEF,0x3A,0x0A,0xEC,0x0F,0xDB,0x56,0xCA, \
+0x08,0xEF,0x39,0xA0,0x6E,0xED,0x79,0xD0,0x24, \
+0x08,0xE7,0x6C,0x0B,0xAF,0xA9,0x4E,0x40,0xB5, \
+0x08,0xE9,0xB9,0xAF,0xBF,0x25,0x50,0xD1,0x37, \
+0x08,0x05,0x9E,0xDB,0xDE,0x3F,0x94,0xE9,0x6B, \
+0x08,0xEC,0xC5,0x05,0xAA,0x57,0xDC,0x8A,0x5E, \
+0x08,0x05,0x70,0xDA,0x84,0x84,0xDD,0xCA,0x90
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.cpp b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.cpp
new file mode 100755
index 0000000..e288464
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.cpp
@@ -0,0 +1,45 @@
+
+//
+#pragma warning(disable:4996)
+#define _CRT_SECURE_NO_WARNINGS
+#define _CRT_SECURE_NO_WARNINGS
+
+
+
+#include <stdio.h>
+#include "stdafx.h"
+
+#include "SI4463_which_config.h"
+//#define which_modulation 13
+//#include "./SI4463/radio_config_Si4463_13.h"
+
+int _tmain(int argc, _TCHAR* argv[])
+{
+	unsigned char radio_config_data[1500] = RADIO_CONFIGURATION_DATA_ARRAY;
+	FILE* fid_out;
+	char filename_out[30];
+	int i = 0;
+	int j;
+	int current_command_length;
+	sprintf(filename_out, "SI4463_config_%i%s.h", which_modulation, which_band);
+	fid_out = fopen(filename_out, "w+");
+	fprintf(fid_out,"#define RADIO_CONFIGURATION_DATA_ARRAY_%i { \\\n", which_modulation);
+	current_command_length = radio_config_data[i];
+	while (current_command_length > 0) {
+		current_command_length = radio_config_data[i];
+		fprintf(fid_out,"\t");
+		for (j = 0; j <= current_command_length; j++) {
+			fprintf(fid_out,"0x%02X, ", radio_config_data[i + j]);
+		}
+		fprintf(fid_out,"\\\n");
+		i = i + current_command_length+1;
+		current_command_length = radio_config_data[i];
+		
+	}
+
+	fprintf(fid_out,"\t0x00 \\\n} \n");
+	printf("total size:%i\r\n", i);
+	return 0;
+
+}
+
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.exe b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.exe
new file mode 100755
index 0000000..d41b2d3
Binary files /dev/null and b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.exe differ
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.obj b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.obj
new file mode 100755
index 0000000..cf0395e
Binary files /dev/null and b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_generation.obj differ
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_total_2.bat b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_total_2.bat
new file mode 100755
index 0000000..b9e3562
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/radio_config_total_2.bat
@@ -0,0 +1,31 @@
+@echo off
+for %%M in (11 12 13 14 20 21 22 23 24) do (
+	echo .
+	echo *********
+	echo CONFIG %%M 70cm
+	echo *********
+	
+	
+	del SI4463_which_config.h
+	(echo #define which_modulation %%M) >> SI4463_which_config.h
+	(echo #define which_band "") >> SI4463_which_config.h
+	(echo #include "./SI4463_70cm/radio_config_Si4463_%%M.h") >> SI4463_which_config.h
+	cl /clr radio_config_generation.cpp
+	radio_config_generation.exe
+)
+
+for %%M in (11 12 13 14 20 21 22 23 24) do (
+	echo .
+	echo *********
+	echo CONFIG %%M 2m
+	echo *********
+	
+	
+	del SI4463_which_config.h
+	(echo #define which_modulation %%M) >> SI4463_which_config.h
+	(echo #define which_band "_2m") >> SI4463_which_config.h
+	(echo #include "./SI4463_2m/radio_config_Si4463_%%M.h") >> SI4463_which_config.h
+	cl /clr radio_config_generation.cpp
+	radio_config_generation.exe
+)
+
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/stdafx.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/stdafx.h
new file mode 100755
index 0000000..c36e115
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/stdafx.h
@@ -0,0 +1,15 @@
+// stdafx.h : fichier Include pour les fichiers Include système standard,
+// ou les fichiers Include spécifiques aux projets qui sont utilisés fréquemment,
+// et sont rarement modifiés
+//
+
+#pragma once
+
+#include "targetver.h"
+
+#include <stdio.h>
+#include <tchar.h>
+
+
+
+// TODO: faites référence ici aux en-têtes supplémentaires nécessaires au programme
diff --git a/NPR_FW_source_2020_06_29/radio_config_generation_2/targetver.h b/NPR_FW_source_2020_06_29/radio_config_generation_2/targetver.h
new file mode 100755
index 0000000..b9d1864
--- /dev/null
+++ b/NPR_FW_source_2020_06_29/radio_config_generation_2/targetver.h
@@ -0,0 +1,8 @@
+#pragma once
+
+// Si vous incluez SDKDDKVer.h, cela définit la dernière plateforme Windows disponible.
+
+// Si vous souhaitez générer votre application pour une plateforme Windows précédente, incluez WinSDKVer.h et
+// définissez la macro _WIN32_WINNT à la plateforme que vous souhaitez prendre en charge avant d'inclure SDKDDKVer.h.
+
+#include <SDKDDKVer.h>
diff --git a/README.md b/README.md
new file mode 100755
index 0000000..117f18f
--- /dev/null
+++ b/README.md
@@ -0,0 +1,32 @@
+# New Packet Radio
+
+   I take this source for add mod and optimisation ...<br>
+   F4IYT
+   
+   my PCB<br>
+<img src="http://xavier.debert.free.fr/NPR70/myNPR.jpg" width="20%" border="0">
+<br>
+<img src="http://xavier.debert.free.fr/NPR70/myNPR1.jpg" width="20%" border="0">
+   
+   <br>
+   PCB bottom<br>
+<img src="http://xavier.debert.free.fr/NPR70/NPR70_v05b_bot.PNG" width="20%" border="0">
+<br>
+   PCB top<br>
+<img src="http://xavier.debert.free.fr/NPR70/NPR70_v05b_top.PNG" width="20%" border="0">
+<br>
+   Schema V5<br>
+<img src="http://xavier.debert.free.fr/NPR70/sch_NPR70_v05.png" width="20%" border="0">
+<br>
+   Liste composant V5<br>
+<img src="http://xavier.debert.free.fr/NPR70/BOM_NPR70modem_v05.png" width="20%" border="0">
+
+<br><br>
+   This is the source code for the NPR-70 modem firmware by F4HDK.
+
+   This code is based on the 2020_02_23 release available at https://hackaday.io/project/164092-npr-new-packet-radio .
+
+   It adds a couple of features such as SNMP support (see the included MIB), as well as a refactor of settings (which makes it possible to update settings across firmware releases if needed) and reduced memory usage.
+
+
+